4 * Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 #include <rte_string_fns.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_ethdev_pci.h>
49 #include <rte_memzone.h>
50 #include <rte_malloc.h>
51 #include <rte_memcpy.h>
52 #include <rte_alarm.h>
54 #include <rte_eth_ctrl.h>
55 #include <rte_tailq.h>
56 #include <rte_hash_crc.h>
58 #include "i40e_logs.h"
59 #include "base/i40e_prototype.h"
60 #include "base/i40e_adminq_cmd.h"
61 #include "base/i40e_type.h"
62 #include "base/i40e_register.h"
63 #include "base/i40e_dcb.h"
64 #include "i40e_ethdev.h"
65 #include "i40e_rxtx.h"
67 #include "i40e_regs.h"
69 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
70 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
72 #define I40E_CLEAR_PXE_WAIT_MS 200
74 /* Maximun number of capability elements */
75 #define I40E_MAX_CAP_ELE_NUM 128
77 /* Wait count and inteval */
78 #define I40E_CHK_Q_ENA_COUNT 1000
79 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
81 /* Maximun number of VSI */
82 #define I40E_MAX_NUM_VSIS (384UL)
84 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
86 /* Flow control default timer */
87 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
89 /* Flow control default high water */
90 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
92 /* Flow control default low water */
93 #define I40E_DEFAULT_LOW_WATER (0x1A40/1024)
95 /* Flow control enable fwd bit */
96 #define I40E_PRTMAC_FWD_CTRL 0x00000001
98 /* Receive Packet Buffer size */
99 #define I40E_RXPBSIZE (968 * 1024)
101 /* Kilobytes shift */
102 #define I40E_KILOSHIFT 10
104 /* Receive Average Packet Size in Byte*/
105 #define I40E_PACKET_AVERAGE_SIZE 128
107 /* Mask of PF interrupt causes */
108 #define I40E_PFINT_ICR0_ENA_MASK ( \
109 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
110 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
111 I40E_PFINT_ICR0_ENA_GRST_MASK | \
112 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
113 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
114 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
115 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
116 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
117 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
119 #define I40E_FLOW_TYPES ( \
120 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
121 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
122 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
123 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
124 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
125 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
126 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
127 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
128 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
129 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
130 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
132 /* Additional timesync values. */
133 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
134 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
135 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
136 #define I40E_PRTTSYN_TSYNENA 0x80000000
137 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
138 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
140 #define I40E_MAX_PERCENT 100
141 #define I40E_DEFAULT_DCB_APP_NUM 1
142 #define I40E_DEFAULT_DCB_APP_PRIO 3
145 * Below are values for writing un-exposed registers suggested
148 /* Destination MAC address */
149 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
150 /* Source MAC address */
151 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
152 /* Outer (S-Tag) VLAN tag in the outer L2 header */
153 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
154 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
155 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
156 /* Single VLAN tag in the inner L2 header */
157 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
158 /* Source IPv4 address */
159 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
160 /* Destination IPv4 address */
161 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
162 /* Source IPv4 address for X722 */
163 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
164 /* Destination IPv4 address for X722 */
165 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
166 /* IPv4 Protocol for X722 */
167 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
168 /* IPv4 Time to Live for X722 */
169 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
170 /* IPv4 Type of Service (TOS) */
171 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
173 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
174 /* IPv4 Time to Live */
175 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
176 /* Source IPv6 address */
177 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
178 /* Destination IPv6 address */
179 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
180 /* IPv6 Traffic Class (TC) */
181 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
182 /* IPv6 Next Header */
183 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
185 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
187 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
188 /* Destination L4 port */
189 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
190 /* SCTP verification tag */
191 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
192 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
193 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
194 /* Source port of tunneling UDP */
195 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
196 /* Destination port of tunneling UDP */
197 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
198 /* UDP Tunneling ID, NVGRE/GRE key */
199 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
200 /* Last ether type */
201 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
202 /* Tunneling outer destination IPv4 address */
203 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
204 /* Tunneling outer destination IPv6 address */
205 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
206 /* 1st word of flex payload */
207 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
208 /* 2nd word of flex payload */
209 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
210 /* 3rd word of flex payload */
211 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
212 /* 4th word of flex payload */
213 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
214 /* 5th word of flex payload */
215 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
216 /* 6th word of flex payload */
217 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
218 /* 7th word of flex payload */
219 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
220 /* 8th word of flex payload */
221 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
222 /* all 8 words flex payload */
223 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
224 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
226 #define I40E_TRANSLATE_INSET 0
227 #define I40E_TRANSLATE_REG 1
229 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
230 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
231 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
232 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
233 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
234 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
236 /* PCI offset for querying capability */
237 #define PCI_DEV_CAP_REG 0xA4
238 /* PCI offset for enabling/disabling Extended Tag */
239 #define PCI_DEV_CTRL_REG 0xA8
240 /* Bit mask of Extended Tag capability */
241 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
242 /* Bit shift of Extended Tag enable/disable */
243 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
244 /* Bit mask of Extended Tag enable/disable */
245 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
247 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
248 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
249 static int i40e_dev_configure(struct rte_eth_dev *dev);
250 static int i40e_dev_start(struct rte_eth_dev *dev);
251 static void i40e_dev_stop(struct rte_eth_dev *dev);
252 static void i40e_dev_close(struct rte_eth_dev *dev);
253 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
254 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
255 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
256 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
257 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
258 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
259 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
260 struct rte_eth_stats *stats);
261 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
262 struct rte_eth_xstat *xstats, unsigned n);
263 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
264 struct rte_eth_xstat_name *xstats_names,
266 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
267 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
271 static int i40e_fw_version_get(struct rte_eth_dev *dev,
272 char *fw_version, size_t fw_size);
273 static void i40e_dev_info_get(struct rte_eth_dev *dev,
274 struct rte_eth_dev_info *dev_info);
275 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
278 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
279 enum rte_vlan_type vlan_type,
281 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
282 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
285 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
286 static int i40e_dev_led_on(struct rte_eth_dev *dev);
287 static int i40e_dev_led_off(struct rte_eth_dev *dev);
288 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
289 struct rte_eth_fc_conf *fc_conf);
290 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
291 struct rte_eth_fc_conf *fc_conf);
292 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
293 struct rte_eth_pfc_conf *pfc_conf);
294 static int i40e_macaddr_add(struct rte_eth_dev *dev,
295 struct ether_addr *mac_addr,
298 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
299 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
300 struct rte_eth_rss_reta_entry64 *reta_conf,
302 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
303 struct rte_eth_rss_reta_entry64 *reta_conf,
306 static int i40e_get_cap(struct i40e_hw *hw);
307 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
308 static int i40e_pf_setup(struct i40e_pf *pf);
309 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
310 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
311 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
312 static int i40e_dcb_setup(struct rte_eth_dev *dev);
313 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
314 bool offset_loaded, uint64_t *offset, uint64_t *stat);
315 static void i40e_stat_update_48(struct i40e_hw *hw,
321 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
322 static void i40e_dev_interrupt_handler(void *param);
323 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
324 uint32_t base, uint32_t num);
325 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
326 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
328 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
330 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
331 static int i40e_veb_release(struct i40e_veb *veb);
332 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
333 struct i40e_vsi *vsi);
334 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
335 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
336 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
337 struct i40e_macvlan_filter *mv_f,
340 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
341 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
342 struct rte_eth_rss_conf *rss_conf);
343 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
344 struct rte_eth_rss_conf *rss_conf);
345 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
346 struct rte_eth_udp_tunnel *udp_tunnel);
347 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
348 struct rte_eth_udp_tunnel *udp_tunnel);
349 static void i40e_filter_input_set_init(struct i40e_pf *pf);
350 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
351 enum rte_filter_op filter_op,
353 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
354 enum rte_filter_type filter_type,
355 enum rte_filter_op filter_op,
357 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
358 struct rte_eth_dcb_info *dcb_info);
359 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
360 static void i40e_configure_registers(struct i40e_hw *hw);
361 static void i40e_hw_init(struct rte_eth_dev *dev);
362 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
363 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
364 struct rte_eth_mirror_conf *mirror_conf,
365 uint8_t sw_id, uint8_t on);
366 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
368 static int i40e_timesync_enable(struct rte_eth_dev *dev);
369 static int i40e_timesync_disable(struct rte_eth_dev *dev);
370 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
371 struct timespec *timestamp,
373 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
374 struct timespec *timestamp);
375 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
377 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
379 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
380 struct timespec *timestamp);
381 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
382 const struct timespec *timestamp);
384 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
386 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
389 static int i40e_get_regs(struct rte_eth_dev *dev,
390 struct rte_dev_reg_info *regs);
392 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
394 static int i40e_get_eeprom(struct rte_eth_dev *dev,
395 struct rte_dev_eeprom_info *eeprom);
397 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
398 struct ether_addr *mac_addr);
400 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
402 static int i40e_ethertype_filter_convert(
403 const struct rte_eth_ethertype_filter *input,
404 struct i40e_ethertype_filter *filter);
405 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
406 struct i40e_ethertype_filter *filter);
408 static int i40e_tunnel_filter_convert(
409 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
410 struct i40e_tunnel_filter *tunnel_filter);
411 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
412 struct i40e_tunnel_filter *tunnel_filter);
413 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
415 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
416 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
417 static void i40e_filter_restore(struct i40e_pf *pf);
418 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
420 int i40e_logtype_init;
421 int i40e_logtype_driver;
423 static const struct rte_pci_id pci_id_i40e_map[] = {
424 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
425 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
426 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
427 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
428 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
429 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
430 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
431 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
432 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
435 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
436 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
437 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
438 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
439 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
440 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
441 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
442 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
443 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
444 { .vendor_id = 0, /* sentinel */ },
447 static const struct eth_dev_ops i40e_eth_dev_ops = {
448 .dev_configure = i40e_dev_configure,
449 .dev_start = i40e_dev_start,
450 .dev_stop = i40e_dev_stop,
451 .dev_close = i40e_dev_close,
452 .promiscuous_enable = i40e_dev_promiscuous_enable,
453 .promiscuous_disable = i40e_dev_promiscuous_disable,
454 .allmulticast_enable = i40e_dev_allmulticast_enable,
455 .allmulticast_disable = i40e_dev_allmulticast_disable,
456 .dev_set_link_up = i40e_dev_set_link_up,
457 .dev_set_link_down = i40e_dev_set_link_down,
458 .link_update = i40e_dev_link_update,
459 .stats_get = i40e_dev_stats_get,
460 .xstats_get = i40e_dev_xstats_get,
461 .xstats_get_names = i40e_dev_xstats_get_names,
462 .stats_reset = i40e_dev_stats_reset,
463 .xstats_reset = i40e_dev_stats_reset,
464 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
465 .fw_version_get = i40e_fw_version_get,
466 .dev_infos_get = i40e_dev_info_get,
467 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
468 .vlan_filter_set = i40e_vlan_filter_set,
469 .vlan_tpid_set = i40e_vlan_tpid_set,
470 .vlan_offload_set = i40e_vlan_offload_set,
471 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
472 .vlan_pvid_set = i40e_vlan_pvid_set,
473 .rx_queue_start = i40e_dev_rx_queue_start,
474 .rx_queue_stop = i40e_dev_rx_queue_stop,
475 .tx_queue_start = i40e_dev_tx_queue_start,
476 .tx_queue_stop = i40e_dev_tx_queue_stop,
477 .rx_queue_setup = i40e_dev_rx_queue_setup,
478 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
479 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
480 .rx_queue_release = i40e_dev_rx_queue_release,
481 .rx_queue_count = i40e_dev_rx_queue_count,
482 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
483 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
484 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
485 .tx_queue_setup = i40e_dev_tx_queue_setup,
486 .tx_queue_release = i40e_dev_tx_queue_release,
487 .dev_led_on = i40e_dev_led_on,
488 .dev_led_off = i40e_dev_led_off,
489 .flow_ctrl_get = i40e_flow_ctrl_get,
490 .flow_ctrl_set = i40e_flow_ctrl_set,
491 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
492 .mac_addr_add = i40e_macaddr_add,
493 .mac_addr_remove = i40e_macaddr_remove,
494 .reta_update = i40e_dev_rss_reta_update,
495 .reta_query = i40e_dev_rss_reta_query,
496 .rss_hash_update = i40e_dev_rss_hash_update,
497 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
498 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
499 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
500 .filter_ctrl = i40e_dev_filter_ctrl,
501 .rxq_info_get = i40e_rxq_info_get,
502 .txq_info_get = i40e_txq_info_get,
503 .mirror_rule_set = i40e_mirror_rule_set,
504 .mirror_rule_reset = i40e_mirror_rule_reset,
505 .timesync_enable = i40e_timesync_enable,
506 .timesync_disable = i40e_timesync_disable,
507 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
508 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
509 .get_dcb_info = i40e_dev_get_dcb_info,
510 .timesync_adjust_time = i40e_timesync_adjust_time,
511 .timesync_read_time = i40e_timesync_read_time,
512 .timesync_write_time = i40e_timesync_write_time,
513 .get_reg = i40e_get_regs,
514 .get_eeprom_length = i40e_get_eeprom_length,
515 .get_eeprom = i40e_get_eeprom,
516 .mac_addr_set = i40e_set_default_mac_addr,
517 .mtu_set = i40e_dev_mtu_set,
520 /* store statistics names and its offset in stats structure */
521 struct rte_i40e_xstats_name_off {
522 char name[RTE_ETH_XSTATS_NAME_SIZE];
526 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
527 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
528 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
529 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
530 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
531 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
532 rx_unknown_protocol)},
533 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
534 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
535 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
536 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
539 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
540 sizeof(rte_i40e_stats_strings[0]))
542 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
543 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
544 tx_dropped_link_down)},
545 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
546 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
548 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
549 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
551 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
553 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
555 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
556 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
557 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
558 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
559 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
560 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
562 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
564 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
566 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
568 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
570 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
572 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
574 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
576 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
577 mac_short_packet_dropped)},
578 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
580 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
581 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
582 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
584 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
586 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
588 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
590 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
592 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
594 {"rx_flow_director_atr_match_packets",
595 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
596 {"rx_flow_director_sb_match_packets",
597 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
598 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
600 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
602 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
604 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
608 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
609 sizeof(rte_i40e_hw_port_strings[0]))
611 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
612 {"xon_packets", offsetof(struct i40e_hw_port_stats,
614 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
618 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
619 sizeof(rte_i40e_rxq_prio_strings[0]))
621 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
622 {"xon_packets", offsetof(struct i40e_hw_port_stats,
624 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
626 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
627 priority_xon_2_xoff)},
630 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
631 sizeof(rte_i40e_txq_prio_strings[0]))
633 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
634 struct rte_pci_device *pci_dev)
636 return rte_eth_dev_pci_generic_probe(pci_dev,
637 sizeof(struct i40e_adapter), eth_i40e_dev_init);
640 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
642 return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
645 static struct rte_pci_driver rte_i40e_pmd = {
646 .id_table = pci_id_i40e_map,
647 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
648 .probe = eth_i40e_pci_probe,
649 .remove = eth_i40e_pci_remove,
653 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
654 struct rte_eth_link *link)
656 struct rte_eth_link *dst = link;
657 struct rte_eth_link *src = &(dev->data->dev_link);
659 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
660 *(uint64_t *)src) == 0)
667 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
668 struct rte_eth_link *link)
670 struct rte_eth_link *dst = &(dev->data->dev_link);
671 struct rte_eth_link *src = link;
673 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
674 *(uint64_t *)src) == 0)
680 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
681 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
682 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
684 #ifndef I40E_GLQF_ORT
685 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
687 #ifndef I40E_GLQF_PIT
688 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
690 #ifndef I40E_GLQF_L3_MAP
691 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
694 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
697 * Initialize registers for flexible payload, which should be set by NVM.
698 * This should be removed from code once it is fixed in NVM.
700 I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
701 I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
702 I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
703 I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
704 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
705 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
706 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
707 I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
708 I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
709 I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
710 I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
711 I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
713 /* Initialize registers for parsing packet type of QinQ */
714 I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
715 I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
718 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
721 * Add a ethertype filter to drop all flow control frames transmitted
725 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
727 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
728 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
729 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
730 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
733 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
734 I40E_FLOW_CONTROL_ETHERTYPE, flags,
735 pf->main_vsi_seid, 0,
739 "Failed to add filter to drop flow control frames from VSIs.");
743 floating_veb_list_handler(__rte_unused const char *key,
744 const char *floating_veb_value,
748 unsigned int count = 0;
751 bool *vf_floating_veb = opaque;
753 while (isblank(*floating_veb_value))
754 floating_veb_value++;
756 /* Reset floating VEB configuration for VFs */
757 for (idx = 0; idx < I40E_MAX_VF; idx++)
758 vf_floating_veb[idx] = false;
762 while (isblank(*floating_veb_value))
763 floating_veb_value++;
764 if (*floating_veb_value == '\0')
767 idx = strtoul(floating_veb_value, &end, 10);
768 if (errno || end == NULL)
770 while (isblank(*end))
774 } else if ((*end == ';') || (*end == '\0')) {
776 if (min == I40E_MAX_VF)
778 if (max >= I40E_MAX_VF)
779 max = I40E_MAX_VF - 1;
780 for (idx = min; idx <= max; idx++) {
781 vf_floating_veb[idx] = true;
788 floating_veb_value = end + 1;
789 } while (*end != '\0');
798 config_vf_floating_veb(struct rte_devargs *devargs,
799 uint16_t floating_veb,
800 bool *vf_floating_veb)
802 struct rte_kvargs *kvlist;
804 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
808 /* All the VFs attach to the floating VEB by default
809 * when the floating VEB is enabled.
811 for (i = 0; i < I40E_MAX_VF; i++)
812 vf_floating_veb[i] = true;
817 kvlist = rte_kvargs_parse(devargs->args, NULL);
821 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
822 rte_kvargs_free(kvlist);
825 /* When the floating_veb_list parameter exists, all the VFs
826 * will attach to the legacy VEB firstly, then configure VFs
827 * to the floating VEB according to the floating_veb_list.
829 if (rte_kvargs_process(kvlist, floating_veb_list,
830 floating_veb_list_handler,
831 vf_floating_veb) < 0) {
832 rte_kvargs_free(kvlist);
835 rte_kvargs_free(kvlist);
839 i40e_check_floating_handler(__rte_unused const char *key,
841 __rte_unused void *opaque)
843 if (strcmp(value, "1"))
850 is_floating_veb_supported(struct rte_devargs *devargs)
852 struct rte_kvargs *kvlist;
853 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
858 kvlist = rte_kvargs_parse(devargs->args, NULL);
862 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
863 rte_kvargs_free(kvlist);
866 /* Floating VEB is enabled when there's key-value:
867 * enable_floating_veb=1
869 if (rte_kvargs_process(kvlist, floating_veb_key,
870 i40e_check_floating_handler, NULL) < 0) {
871 rte_kvargs_free(kvlist);
874 rte_kvargs_free(kvlist);
880 config_floating_veb(struct rte_eth_dev *dev)
882 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
883 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
884 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
886 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
888 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
890 is_floating_veb_supported(pci_dev->device.devargs);
891 config_vf_floating_veb(pci_dev->device.devargs,
893 pf->floating_veb_list);
895 pf->floating_veb = false;
899 #define I40E_L2_TAGS_S_TAG_SHIFT 1
900 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
903 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
905 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
906 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
907 char ethertype_hash_name[RTE_HASH_NAMESIZE];
910 struct rte_hash_parameters ethertype_hash_params = {
911 .name = ethertype_hash_name,
912 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
913 .key_len = sizeof(struct i40e_ethertype_filter_input),
914 .hash_func = rte_hash_crc,
915 .hash_func_init_val = 0,
916 .socket_id = rte_socket_id(),
919 /* Initialize ethertype filter rule list and hash */
920 TAILQ_INIT(ðertype_rule->ethertype_list);
921 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
922 "ethertype_%s", dev->data->name);
923 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
924 if (!ethertype_rule->hash_table) {
925 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
928 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
929 sizeof(struct i40e_ethertype_filter *) *
930 I40E_MAX_ETHERTYPE_FILTER_NUM,
932 if (!ethertype_rule->hash_map) {
934 "Failed to allocate memory for ethertype hash map!");
936 goto err_ethertype_hash_map_alloc;
941 err_ethertype_hash_map_alloc:
942 rte_hash_free(ethertype_rule->hash_table);
948 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
950 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
951 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
952 char tunnel_hash_name[RTE_HASH_NAMESIZE];
955 struct rte_hash_parameters tunnel_hash_params = {
956 .name = tunnel_hash_name,
957 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
958 .key_len = sizeof(struct i40e_tunnel_filter_input),
959 .hash_func = rte_hash_crc,
960 .hash_func_init_val = 0,
961 .socket_id = rte_socket_id(),
964 /* Initialize tunnel filter rule list and hash */
965 TAILQ_INIT(&tunnel_rule->tunnel_list);
966 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
967 "tunnel_%s", dev->data->name);
968 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
969 if (!tunnel_rule->hash_table) {
970 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
973 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
974 sizeof(struct i40e_tunnel_filter *) *
975 I40E_MAX_TUNNEL_FILTER_NUM,
977 if (!tunnel_rule->hash_map) {
979 "Failed to allocate memory for tunnel hash map!");
981 goto err_tunnel_hash_map_alloc;
986 err_tunnel_hash_map_alloc:
987 rte_hash_free(tunnel_rule->hash_table);
993 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
995 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
996 struct i40e_fdir_info *fdir_info = &pf->fdir;
997 char fdir_hash_name[RTE_HASH_NAMESIZE];
1000 struct rte_hash_parameters fdir_hash_params = {
1001 .name = fdir_hash_name,
1002 .entries = I40E_MAX_FDIR_FILTER_NUM,
1003 .key_len = sizeof(struct rte_eth_fdir_input),
1004 .hash_func = rte_hash_crc,
1005 .hash_func_init_val = 0,
1006 .socket_id = rte_socket_id(),
1009 /* Initialize flow director filter rule list and hash */
1010 TAILQ_INIT(&fdir_info->fdir_list);
1011 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1012 "fdir_%s", dev->data->name);
1013 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1014 if (!fdir_info->hash_table) {
1015 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1018 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1019 sizeof(struct i40e_fdir_filter *) *
1020 I40E_MAX_FDIR_FILTER_NUM,
1022 if (!fdir_info->hash_map) {
1024 "Failed to allocate memory for fdir hash map!");
1026 goto err_fdir_hash_map_alloc;
1030 err_fdir_hash_map_alloc:
1031 rte_hash_free(fdir_info->hash_table);
1037 eth_i40e_dev_init(struct rte_eth_dev *dev)
1039 struct rte_pci_device *pci_dev;
1040 struct rte_intr_handle *intr_handle;
1041 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1042 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1043 struct i40e_vsi *vsi;
1046 uint8_t aq_fail = 0;
1048 PMD_INIT_FUNC_TRACE();
1050 dev->dev_ops = &i40e_eth_dev_ops;
1051 dev->rx_pkt_burst = i40e_recv_pkts;
1052 dev->tx_pkt_burst = i40e_xmit_pkts;
1053 dev->tx_pkt_prepare = i40e_prep_pkts;
1055 /* for secondary processes, we don't initialise any further as primary
1056 * has already done this work. Only check we don't need a different
1058 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1059 i40e_set_rx_function(dev);
1060 i40e_set_tx_function(dev);
1063 i40e_set_default_ptype_table(dev);
1064 pci_dev = I40E_DEV_TO_PCI(dev);
1065 intr_handle = &pci_dev->intr_handle;
1067 rte_eth_copy_pci_info(dev, pci_dev);
1068 dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1070 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1071 pf->adapter->eth_dev = dev;
1072 pf->dev_data = dev->data;
1074 hw->back = I40E_PF_TO_ADAPTER(pf);
1075 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1078 "Hardware is not available, as address is NULL");
1082 hw->vendor_id = pci_dev->id.vendor_id;
1083 hw->device_id = pci_dev->id.device_id;
1084 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1085 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1086 hw->bus.device = pci_dev->addr.devid;
1087 hw->bus.func = pci_dev->addr.function;
1088 hw->adapter_stopped = 0;
1090 /* Make sure all is clean before doing PF reset */
1093 /* Initialize the hardware */
1096 /* Reset here to make sure all is clean for each PF */
1097 ret = i40e_pf_reset(hw);
1099 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1103 /* Initialize the shared code (base driver) */
1104 ret = i40e_init_shared_code(hw);
1106 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1111 * To work around the NVM issue, initialize registers
1112 * for flexible payload and packet type of QinQ by
1113 * software. It should be removed once issues are fixed
1116 i40e_GLQF_reg_init(hw);
1118 /* Initialize the input set for filters (hash and fd) to default value */
1119 i40e_filter_input_set_init(pf);
1121 /* Initialize the parameters for adminq */
1122 i40e_init_adminq_parameter(hw);
1123 ret = i40e_init_adminq(hw);
1124 if (ret != I40E_SUCCESS) {
1125 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1128 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1129 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1130 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1131 ((hw->nvm.version >> 12) & 0xf),
1132 ((hw->nvm.version >> 4) & 0xff),
1133 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1135 /* initialise the L3_MAP register */
1136 ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1139 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
1141 /* Need the special FW version to support floating VEB */
1142 config_floating_veb(dev);
1143 /* Clear PXE mode */
1144 i40e_clear_pxe_mode(hw);
1145 ret = i40e_dev_sync_phy_type(hw);
1147 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1148 goto err_sync_phy_type;
1151 * On X710, performance number is far from the expectation on recent
1152 * firmware versions. The fix for this issue may not be integrated in
1153 * the following firmware version. So the workaround in software driver
1154 * is needed. It needs to modify the initial values of 3 internal only
1155 * registers. Note that the workaround can be removed when it is fixed
1156 * in firmware in the future.
1158 i40e_configure_registers(hw);
1160 /* Get hw capabilities */
1161 ret = i40e_get_cap(hw);
1162 if (ret != I40E_SUCCESS) {
1163 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1164 goto err_get_capabilities;
1167 /* Initialize parameters for PF */
1168 ret = i40e_pf_parameter_init(dev);
1170 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1171 goto err_parameter_init;
1174 /* Initialize the queue management */
1175 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1177 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1178 goto err_qp_pool_init;
1180 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1181 hw->func_caps.num_msix_vectors - 1);
1183 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1184 goto err_msix_pool_init;
1187 /* Initialize lan hmc */
1188 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1189 hw->func_caps.num_rx_qp, 0, 0);
1190 if (ret != I40E_SUCCESS) {
1191 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1192 goto err_init_lan_hmc;
1195 /* Configure lan hmc */
1196 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1197 if (ret != I40E_SUCCESS) {
1198 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1199 goto err_configure_lan_hmc;
1202 /* Get and check the mac address */
1203 i40e_get_mac_addr(hw, hw->mac.addr);
1204 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1205 PMD_INIT_LOG(ERR, "mac address is not valid");
1207 goto err_get_mac_addr;
1209 /* Copy the permanent MAC address */
1210 ether_addr_copy((struct ether_addr *) hw->mac.addr,
1211 (struct ether_addr *) hw->mac.perm_addr);
1213 /* Disable flow control */
1214 hw->fc.requested_mode = I40E_FC_NONE;
1215 i40e_set_fc(hw, &aq_fail, TRUE);
1217 /* Set the global registers with default ether type value */
1218 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1219 if (ret != I40E_SUCCESS) {
1221 "Failed to set the default outer VLAN ether type");
1222 goto err_setup_pf_switch;
1225 /* PF setup, which includes VSI setup */
1226 ret = i40e_pf_setup(pf);
1228 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1229 goto err_setup_pf_switch;
1232 /* reset all stats of the device, including pf and main vsi */
1233 i40e_dev_stats_reset(dev);
1237 /* Disable double vlan by default */
1238 i40e_vsi_config_double_vlan(vsi, FALSE);
1240 /* Disable S-TAG identification when floating_veb is disabled */
1241 if (!pf->floating_veb) {
1242 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1243 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1244 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1245 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1249 if (!vsi->max_macaddrs)
1250 len = ETHER_ADDR_LEN;
1252 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1254 /* Should be after VSI initialized */
1255 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1256 if (!dev->data->mac_addrs) {
1258 "Failed to allocated memory for storing mac address");
1261 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1262 &dev->data->mac_addrs[0]);
1264 /* Init dcb to sw mode by default */
1265 ret = i40e_dcb_init_configure(dev, TRUE);
1266 if (ret != I40E_SUCCESS) {
1267 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1268 pf->flags &= ~I40E_FLAG_DCB;
1270 /* Update HW struct after DCB configuration */
1273 /* initialize pf host driver to setup SRIOV resource if applicable */
1274 i40e_pf_host_init(dev);
1276 /* register callback func to eal lib */
1277 rte_intr_callback_register(intr_handle,
1278 i40e_dev_interrupt_handler, dev);
1280 /* configure and enable device interrupt */
1281 i40e_pf_config_irq0(hw, TRUE);
1282 i40e_pf_enable_irq0(hw);
1284 /* enable uio intr after callback register */
1285 rte_intr_enable(intr_handle);
1287 * Add an ethertype filter to drop all flow control frames transmitted
1288 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1291 i40e_add_tx_flow_control_drop_filter(pf);
1293 /* Set the max frame size to 0x2600 by default,
1294 * in case other drivers changed the default value.
1296 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1298 /* initialize mirror rule list */
1299 TAILQ_INIT(&pf->mirror_list);
1301 ret = i40e_init_ethtype_filter_list(dev);
1303 goto err_init_ethtype_filter_list;
1304 ret = i40e_init_tunnel_filter_list(dev);
1306 goto err_init_tunnel_filter_list;
1307 ret = i40e_init_fdir_filter_list(dev);
1309 goto err_init_fdir_filter_list;
1313 err_init_fdir_filter_list:
1314 rte_free(pf->tunnel.hash_table);
1315 rte_free(pf->tunnel.hash_map);
1316 err_init_tunnel_filter_list:
1317 rte_free(pf->ethertype.hash_table);
1318 rte_free(pf->ethertype.hash_map);
1319 err_init_ethtype_filter_list:
1320 rte_free(dev->data->mac_addrs);
1322 i40e_vsi_release(pf->main_vsi);
1323 err_setup_pf_switch:
1325 err_configure_lan_hmc:
1326 (void)i40e_shutdown_lan_hmc(hw);
1328 i40e_res_pool_destroy(&pf->msix_pool);
1330 i40e_res_pool_destroy(&pf->qp_pool);
1333 err_get_capabilities:
1335 (void)i40e_shutdown_adminq(hw);
1341 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1343 struct i40e_ethertype_filter *p_ethertype;
1344 struct i40e_ethertype_rule *ethertype_rule;
1346 ethertype_rule = &pf->ethertype;
1347 /* Remove all ethertype filter rules and hash */
1348 if (ethertype_rule->hash_map)
1349 rte_free(ethertype_rule->hash_map);
1350 if (ethertype_rule->hash_table)
1351 rte_hash_free(ethertype_rule->hash_table);
1353 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1354 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1355 p_ethertype, rules);
1356 rte_free(p_ethertype);
1361 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1363 struct i40e_tunnel_filter *p_tunnel;
1364 struct i40e_tunnel_rule *tunnel_rule;
1366 tunnel_rule = &pf->tunnel;
1367 /* Remove all tunnel director rules and hash */
1368 if (tunnel_rule->hash_map)
1369 rte_free(tunnel_rule->hash_map);
1370 if (tunnel_rule->hash_table)
1371 rte_hash_free(tunnel_rule->hash_table);
1373 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1374 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1380 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1382 struct i40e_fdir_filter *p_fdir;
1383 struct i40e_fdir_info *fdir_info;
1385 fdir_info = &pf->fdir;
1386 /* Remove all flow director rules and hash */
1387 if (fdir_info->hash_map)
1388 rte_free(fdir_info->hash_map);
1389 if (fdir_info->hash_table)
1390 rte_hash_free(fdir_info->hash_table);
1392 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1393 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1399 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1402 struct rte_pci_device *pci_dev;
1403 struct rte_intr_handle *intr_handle;
1405 struct i40e_filter_control_settings settings;
1406 struct rte_flow *p_flow;
1408 uint8_t aq_fail = 0;
1410 PMD_INIT_FUNC_TRACE();
1412 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1415 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1416 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1417 pci_dev = I40E_DEV_TO_PCI(dev);
1418 intr_handle = &pci_dev->intr_handle;
1420 if (hw->adapter_stopped == 0)
1421 i40e_dev_close(dev);
1423 dev->dev_ops = NULL;
1424 dev->rx_pkt_burst = NULL;
1425 dev->tx_pkt_burst = NULL;
1427 /* Clear PXE mode */
1428 i40e_clear_pxe_mode(hw);
1430 /* Unconfigure filter control */
1431 memset(&settings, 0, sizeof(settings));
1432 ret = i40e_set_filter_control(hw, &settings);
1434 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1437 /* Disable flow control */
1438 hw->fc.requested_mode = I40E_FC_NONE;
1439 i40e_set_fc(hw, &aq_fail, TRUE);
1441 /* uninitialize pf host driver */
1442 i40e_pf_host_uninit(dev);
1444 rte_free(dev->data->mac_addrs);
1445 dev->data->mac_addrs = NULL;
1447 /* disable uio intr before callback unregister */
1448 rte_intr_disable(intr_handle);
1450 /* register callback func to eal lib */
1451 rte_intr_callback_unregister(intr_handle,
1452 i40e_dev_interrupt_handler, dev);
1454 i40e_rm_ethtype_filter_list(pf);
1455 i40e_rm_tunnel_filter_list(pf);
1456 i40e_rm_fdir_filter_list(pf);
1458 /* Remove all flows */
1459 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1460 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1468 i40e_dev_configure(struct rte_eth_dev *dev)
1470 struct i40e_adapter *ad =
1471 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1472 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1473 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1476 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1477 * bulk allocation or vector Rx preconditions we will reset it.
1479 ad->rx_bulk_alloc_allowed = true;
1480 ad->rx_vec_allowed = true;
1481 ad->tx_simple_allowed = true;
1482 ad->tx_vec_allowed = true;
1484 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1485 ret = i40e_fdir_setup(pf);
1486 if (ret != I40E_SUCCESS) {
1487 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1490 ret = i40e_fdir_configure(dev);
1492 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1496 i40e_fdir_teardown(pf);
1498 ret = i40e_dev_init_vlan(dev);
1503 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1504 * RSS setting have different requirements.
1505 * General PMD driver call sequence are NIC init, configure,
1506 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1507 * will try to lookup the VSI that specific queue belongs to if VMDQ
1508 * applicable. So, VMDQ setting has to be done before
1509 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1510 * For RSS setting, it will try to calculate actual configured RX queue
1511 * number, which will be available after rx_queue_setup(). dev_start()
1512 * function is good to place RSS setup.
1514 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1515 ret = i40e_vmdq_setup(dev);
1520 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1521 ret = i40e_dcb_setup(dev);
1523 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1528 TAILQ_INIT(&pf->flow_list);
1533 /* need to release vmdq resource if exists */
1534 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1535 i40e_vsi_release(pf->vmdq[i].vsi);
1536 pf->vmdq[i].vsi = NULL;
1541 /* need to release fdir resource if exists */
1542 i40e_fdir_teardown(pf);
1547 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1549 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1550 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1551 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1552 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1553 uint16_t msix_vect = vsi->msix_intr;
1556 for (i = 0; i < vsi->nb_qps; i++) {
1557 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1558 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1562 if (vsi->type != I40E_VSI_SRIOV) {
1563 if (!rte_intr_allow_others(intr_handle)) {
1564 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1565 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1567 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1570 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1571 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1573 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1578 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1579 vsi->user_param + (msix_vect - 1);
1581 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1582 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1584 I40E_WRITE_FLUSH(hw);
1588 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1589 int base_queue, int nb_queue)
1593 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1595 /* Bind all RX queues to allocated MSIX interrupt */
1596 for (i = 0; i < nb_queue; i++) {
1597 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1598 I40E_QINT_RQCTL_ITR_INDX_MASK |
1599 ((base_queue + i + 1) <<
1600 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1601 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1602 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1604 if (i == nb_queue - 1)
1605 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1606 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1609 /* Write first RX queue to Link list register as the head element */
1610 if (vsi->type != I40E_VSI_SRIOV) {
1612 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1614 if (msix_vect == I40E_MISC_VEC_ID) {
1615 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1617 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1619 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1621 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1624 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1626 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1628 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1630 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1637 if (msix_vect == I40E_MISC_VEC_ID) {
1639 I40E_VPINT_LNKLST0(vsi->user_param),
1641 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1643 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1645 /* num_msix_vectors_vf needs to minus irq0 */
1646 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1647 vsi->user_param + (msix_vect - 1);
1649 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1651 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1653 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1657 I40E_WRITE_FLUSH(hw);
1661 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1663 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1664 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1665 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1666 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1667 uint16_t msix_vect = vsi->msix_intr;
1668 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1669 uint16_t queue_idx = 0;
1674 for (i = 0; i < vsi->nb_qps; i++) {
1675 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1676 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1679 /* INTENA flag is not auto-cleared for interrupt */
1680 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1681 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1682 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1683 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1684 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1686 /* VF bind interrupt */
1687 if (vsi->type == I40E_VSI_SRIOV) {
1688 __vsi_queues_bind_intr(vsi, msix_vect,
1689 vsi->base_queue, vsi->nb_qps);
1693 /* PF & VMDq bind interrupt */
1694 if (rte_intr_dp_is_en(intr_handle)) {
1695 if (vsi->type == I40E_VSI_MAIN) {
1698 } else if (vsi->type == I40E_VSI_VMDQ2) {
1699 struct i40e_vsi *main_vsi =
1700 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1701 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1706 for (i = 0; i < vsi->nb_used_qps; i++) {
1708 if (!rte_intr_allow_others(intr_handle))
1709 /* allow to share MISC_VEC_ID */
1710 msix_vect = I40E_MISC_VEC_ID;
1712 /* no enough msix_vect, map all to one */
1713 __vsi_queues_bind_intr(vsi, msix_vect,
1714 vsi->base_queue + i,
1715 vsi->nb_used_qps - i);
1716 for (; !!record && i < vsi->nb_used_qps; i++)
1717 intr_handle->intr_vec[queue_idx + i] =
1721 /* 1:1 queue/msix_vect mapping */
1722 __vsi_queues_bind_intr(vsi, msix_vect,
1723 vsi->base_queue + i, 1);
1725 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1733 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1735 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1736 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1737 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1738 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1739 uint16_t interval = i40e_calc_itr_interval(\
1740 RTE_LIBRTE_I40E_ITR_INTERVAL);
1741 uint16_t msix_intr, i;
1743 if (rte_intr_allow_others(intr_handle))
1744 for (i = 0; i < vsi->nb_msix; i++) {
1745 msix_intr = vsi->msix_intr + i;
1746 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1747 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1748 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1749 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1751 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1754 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1755 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1756 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1757 (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1759 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1761 I40E_WRITE_FLUSH(hw);
1765 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1767 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1768 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1769 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1770 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1771 uint16_t msix_intr, i;
1773 if (rte_intr_allow_others(intr_handle))
1774 for (i = 0; i < vsi->nb_msix; i++) {
1775 msix_intr = vsi->msix_intr + i;
1776 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1780 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1782 I40E_WRITE_FLUSH(hw);
1785 static inline uint8_t
1786 i40e_parse_link_speeds(uint16_t link_speeds)
1788 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1790 if (link_speeds & ETH_LINK_SPEED_40G)
1791 link_speed |= I40E_LINK_SPEED_40GB;
1792 if (link_speeds & ETH_LINK_SPEED_25G)
1793 link_speed |= I40E_LINK_SPEED_25GB;
1794 if (link_speeds & ETH_LINK_SPEED_20G)
1795 link_speed |= I40E_LINK_SPEED_20GB;
1796 if (link_speeds & ETH_LINK_SPEED_10G)
1797 link_speed |= I40E_LINK_SPEED_10GB;
1798 if (link_speeds & ETH_LINK_SPEED_1G)
1799 link_speed |= I40E_LINK_SPEED_1GB;
1800 if (link_speeds & ETH_LINK_SPEED_100M)
1801 link_speed |= I40E_LINK_SPEED_100MB;
1807 i40e_phy_conf_link(struct i40e_hw *hw,
1809 uint8_t force_speed)
1811 enum i40e_status_code status;
1812 struct i40e_aq_get_phy_abilities_resp phy_ab;
1813 struct i40e_aq_set_phy_config phy_conf;
1814 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1815 I40E_AQ_PHY_FLAG_PAUSE_RX |
1816 I40E_AQ_PHY_FLAG_PAUSE_RX |
1817 I40E_AQ_PHY_FLAG_LOW_POWER;
1818 const uint8_t advt = I40E_LINK_SPEED_40GB |
1819 I40E_LINK_SPEED_25GB |
1820 I40E_LINK_SPEED_10GB |
1821 I40E_LINK_SPEED_1GB |
1822 I40E_LINK_SPEED_100MB;
1826 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1831 memset(&phy_conf, 0, sizeof(phy_conf));
1833 /* bits 0-2 use the values from get_phy_abilities_resp */
1835 abilities |= phy_ab.abilities & mask;
1837 /* update ablities and speed */
1838 if (abilities & I40E_AQ_PHY_AN_ENABLED)
1839 phy_conf.link_speed = advt;
1841 phy_conf.link_speed = force_speed;
1843 phy_conf.abilities = abilities;
1845 /* use get_phy_abilities_resp value for the rest */
1846 phy_conf.phy_type = phy_ab.phy_type;
1847 phy_conf.phy_type_ext = phy_ab.phy_type_ext;
1848 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1849 phy_conf.eee_capability = phy_ab.eee_capability;
1850 phy_conf.eeer = phy_ab.eeer_val;
1851 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1853 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1854 phy_ab.abilities, phy_ab.link_speed);
1855 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
1856 phy_conf.abilities, phy_conf.link_speed);
1858 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1862 return I40E_SUCCESS;
1866 i40e_apply_link_speed(struct rte_eth_dev *dev)
1869 uint8_t abilities = 0;
1870 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1871 struct rte_eth_conf *conf = &dev->data->dev_conf;
1873 speed = i40e_parse_link_speeds(conf->link_speeds);
1874 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1875 if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1876 abilities |= I40E_AQ_PHY_AN_ENABLED;
1877 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1879 /* Skip changing speed on 40G interfaces, FW does not support */
1880 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1881 speed = I40E_LINK_SPEED_UNKNOWN;
1882 abilities |= I40E_AQ_PHY_AN_ENABLED;
1885 return i40e_phy_conf_link(hw, abilities, speed);
1889 i40e_dev_start(struct rte_eth_dev *dev)
1891 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1892 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1893 struct i40e_vsi *main_vsi = pf->main_vsi;
1895 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1896 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1897 uint32_t intr_vector = 0;
1898 struct i40e_vsi *vsi;
1900 hw->adapter_stopped = 0;
1902 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1903 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1904 dev->data->port_id);
1908 rte_intr_disable(intr_handle);
1910 if ((rte_intr_cap_multiple(intr_handle) ||
1911 !RTE_ETH_DEV_SRIOV(dev).active) &&
1912 dev->data->dev_conf.intr_conf.rxq != 0) {
1913 intr_vector = dev->data->nb_rx_queues;
1914 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1919 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1920 intr_handle->intr_vec =
1921 rte_zmalloc("intr_vec",
1922 dev->data->nb_rx_queues * sizeof(int),
1924 if (!intr_handle->intr_vec) {
1926 "Failed to allocate %d rx_queues intr_vec",
1927 dev->data->nb_rx_queues);
1932 /* Initialize VSI */
1933 ret = i40e_dev_rxtx_init(pf);
1934 if (ret != I40E_SUCCESS) {
1935 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1939 /* Map queues with MSIX interrupt */
1940 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1941 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1942 i40e_vsi_queues_bind_intr(main_vsi);
1943 i40e_vsi_enable_queues_intr(main_vsi);
1945 /* Map VMDQ VSI queues with MSIX interrupt */
1946 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1947 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1948 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1949 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1952 /* enable FDIR MSIX interrupt */
1953 if (pf->fdir.fdir_vsi) {
1954 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1955 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1958 /* Enable all queues which have been configured */
1959 ret = i40e_dev_switch_queues(pf, TRUE);
1960 if (ret != I40E_SUCCESS) {
1961 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1965 /* Enable receiving broadcast packets */
1966 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1967 if (ret != I40E_SUCCESS)
1968 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1970 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1971 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1973 if (ret != I40E_SUCCESS)
1974 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1977 /* Enable the VLAN promiscuous mode. */
1979 for (i = 0; i < pf->vf_num; i++) {
1980 vsi = pf->vfs[i].vsi;
1981 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
1986 /* Apply link configure */
1987 if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1988 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1989 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1990 ETH_LINK_SPEED_40G)) {
1991 PMD_DRV_LOG(ERR, "Invalid link setting");
1994 ret = i40e_apply_link_speed(dev);
1995 if (I40E_SUCCESS != ret) {
1996 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2000 if (!rte_intr_allow_others(intr_handle)) {
2001 rte_intr_callback_unregister(intr_handle,
2002 i40e_dev_interrupt_handler,
2004 /* configure and enable device interrupt */
2005 i40e_pf_config_irq0(hw, FALSE);
2006 i40e_pf_enable_irq0(hw);
2008 if (dev->data->dev_conf.intr_conf.lsc != 0)
2010 "lsc won't enable because of no intr multiplex");
2011 } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
2012 ret = i40e_aq_set_phy_int_mask(hw,
2013 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2014 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2015 I40E_AQ_EVENT_MEDIA_NA), NULL);
2016 if (ret != I40E_SUCCESS)
2017 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2019 /* Call get_link_info aq commond to enable LSE */
2020 i40e_dev_link_update(dev, 0);
2023 /* enable uio intr after callback register */
2024 rte_intr_enable(intr_handle);
2026 i40e_filter_restore(pf);
2028 return I40E_SUCCESS;
2031 i40e_dev_switch_queues(pf, FALSE);
2032 i40e_dev_clear_queues(dev);
2038 i40e_dev_stop(struct rte_eth_dev *dev)
2040 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2041 struct i40e_vsi *main_vsi = pf->main_vsi;
2042 struct i40e_mirror_rule *p_mirror;
2043 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2044 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2047 /* Disable all queues */
2048 i40e_dev_switch_queues(pf, FALSE);
2050 /* un-map queues with interrupt registers */
2051 i40e_vsi_disable_queues_intr(main_vsi);
2052 i40e_vsi_queues_unbind_intr(main_vsi);
2054 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2055 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2056 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2059 if (pf->fdir.fdir_vsi) {
2060 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2061 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2063 /* Clear all queues and release memory */
2064 i40e_dev_clear_queues(dev);
2067 i40e_dev_set_link_down(dev);
2069 /* Remove all mirror rules */
2070 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2071 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2074 pf->nb_mirror_rule = 0;
2076 if (!rte_intr_allow_others(intr_handle))
2077 /* resume to the default handler */
2078 rte_intr_callback_register(intr_handle,
2079 i40e_dev_interrupt_handler,
2082 /* Clean datapath event and queue/vec mapping */
2083 rte_intr_efd_disable(intr_handle);
2084 if (intr_handle->intr_vec) {
2085 rte_free(intr_handle->intr_vec);
2086 intr_handle->intr_vec = NULL;
2091 i40e_dev_close(struct rte_eth_dev *dev)
2093 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2094 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2095 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2096 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2100 PMD_INIT_FUNC_TRACE();
2103 hw->adapter_stopped = 1;
2104 i40e_dev_free_queues(dev);
2106 /* Disable interrupt */
2107 i40e_pf_disable_irq0(hw);
2108 rte_intr_disable(intr_handle);
2110 /* shutdown and destroy the HMC */
2111 i40e_shutdown_lan_hmc(hw);
2113 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2114 i40e_vsi_release(pf->vmdq[i].vsi);
2115 pf->vmdq[i].vsi = NULL;
2120 /* release all the existing VSIs and VEBs */
2121 i40e_fdir_teardown(pf);
2122 i40e_vsi_release(pf->main_vsi);
2124 /* shutdown the adminq */
2125 i40e_aq_queue_shutdown(hw, true);
2126 i40e_shutdown_adminq(hw);
2128 i40e_res_pool_destroy(&pf->qp_pool);
2129 i40e_res_pool_destroy(&pf->msix_pool);
2131 /* force a PF reset to clean anything leftover */
2132 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2133 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2134 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2135 I40E_WRITE_FLUSH(hw);
2139 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2141 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2142 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2143 struct i40e_vsi *vsi = pf->main_vsi;
2146 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2148 if (status != I40E_SUCCESS)
2149 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2151 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2153 if (status != I40E_SUCCESS)
2154 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2159 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2161 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2162 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2163 struct i40e_vsi *vsi = pf->main_vsi;
2166 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2168 if (status != I40E_SUCCESS)
2169 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2171 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2173 if (status != I40E_SUCCESS)
2174 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2178 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2180 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2181 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2182 struct i40e_vsi *vsi = pf->main_vsi;
2185 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2186 if (ret != I40E_SUCCESS)
2187 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2191 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2193 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2194 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2195 struct i40e_vsi *vsi = pf->main_vsi;
2198 if (dev->data->promiscuous == 1)
2199 return; /* must remain in all_multicast mode */
2201 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2202 vsi->seid, FALSE, NULL);
2203 if (ret != I40E_SUCCESS)
2204 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2208 * Set device link up.
2211 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2213 /* re-apply link speed setting */
2214 return i40e_apply_link_speed(dev);
2218 * Set device link down.
2221 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2223 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2224 uint8_t abilities = 0;
2225 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2227 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2228 return i40e_phy_conf_link(hw, abilities, speed);
2232 i40e_dev_link_update(struct rte_eth_dev *dev,
2233 int wait_to_complete)
2235 #define CHECK_INTERVAL 100 /* 100ms */
2236 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2237 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2238 struct i40e_link_status link_status;
2239 struct rte_eth_link link, old;
2241 unsigned rep_cnt = MAX_REPEAT_TIME;
2242 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2244 memset(&link, 0, sizeof(link));
2245 memset(&old, 0, sizeof(old));
2246 memset(&link_status, 0, sizeof(link_status));
2247 rte_i40e_dev_atomic_read_link_status(dev, &old);
2250 /* Get link status information from hardware */
2251 status = i40e_aq_get_link_info(hw, enable_lse,
2252 &link_status, NULL);
2253 if (status != I40E_SUCCESS) {
2254 link.link_speed = ETH_SPEED_NUM_100M;
2255 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2256 PMD_DRV_LOG(ERR, "Failed to get link info");
2260 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2261 if (!wait_to_complete || link.link_status)
2264 rte_delay_ms(CHECK_INTERVAL);
2265 } while (--rep_cnt);
2267 if (!link.link_status)
2270 /* i40e uses full duplex only */
2271 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2273 /* Parse the link status */
2274 switch (link_status.link_speed) {
2275 case I40E_LINK_SPEED_100MB:
2276 link.link_speed = ETH_SPEED_NUM_100M;
2278 case I40E_LINK_SPEED_1GB:
2279 link.link_speed = ETH_SPEED_NUM_1G;
2281 case I40E_LINK_SPEED_10GB:
2282 link.link_speed = ETH_SPEED_NUM_10G;
2284 case I40E_LINK_SPEED_20GB:
2285 link.link_speed = ETH_SPEED_NUM_20G;
2287 case I40E_LINK_SPEED_25GB:
2288 link.link_speed = ETH_SPEED_NUM_25G;
2290 case I40E_LINK_SPEED_40GB:
2291 link.link_speed = ETH_SPEED_NUM_40G;
2294 link.link_speed = ETH_SPEED_NUM_100M;
2298 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2299 ETH_LINK_SPEED_FIXED);
2302 rte_i40e_dev_atomic_write_link_status(dev, &link);
2303 if (link.link_status == old.link_status)
2306 i40e_notify_all_vfs_link_status(dev);
2311 /* Get all the statistics of a VSI */
2313 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2315 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2316 struct i40e_eth_stats *nes = &vsi->eth_stats;
2317 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2318 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2320 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2321 vsi->offset_loaded, &oes->rx_bytes,
2323 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2324 vsi->offset_loaded, &oes->rx_unicast,
2326 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2327 vsi->offset_loaded, &oes->rx_multicast,
2328 &nes->rx_multicast);
2329 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2330 vsi->offset_loaded, &oes->rx_broadcast,
2331 &nes->rx_broadcast);
2332 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2333 &oes->rx_discards, &nes->rx_discards);
2334 /* GLV_REPC not supported */
2335 /* GLV_RMPC not supported */
2336 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2337 &oes->rx_unknown_protocol,
2338 &nes->rx_unknown_protocol);
2339 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2340 vsi->offset_loaded, &oes->tx_bytes,
2342 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2343 vsi->offset_loaded, &oes->tx_unicast,
2345 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2346 vsi->offset_loaded, &oes->tx_multicast,
2347 &nes->tx_multicast);
2348 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2349 vsi->offset_loaded, &oes->tx_broadcast,
2350 &nes->tx_broadcast);
2351 /* GLV_TDPC not supported */
2352 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2353 &oes->tx_errors, &nes->tx_errors);
2354 vsi->offset_loaded = true;
2356 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2358 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2359 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2360 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2361 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2362 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2363 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2364 nes->rx_unknown_protocol);
2365 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2366 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2367 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2368 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2369 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2370 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2371 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2376 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2379 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2380 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2382 /* Get statistics of struct i40e_eth_stats */
2383 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2384 I40E_GLPRT_GORCL(hw->port),
2385 pf->offset_loaded, &os->eth.rx_bytes,
2387 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2388 I40E_GLPRT_UPRCL(hw->port),
2389 pf->offset_loaded, &os->eth.rx_unicast,
2390 &ns->eth.rx_unicast);
2391 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2392 I40E_GLPRT_MPRCL(hw->port),
2393 pf->offset_loaded, &os->eth.rx_multicast,
2394 &ns->eth.rx_multicast);
2395 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2396 I40E_GLPRT_BPRCL(hw->port),
2397 pf->offset_loaded, &os->eth.rx_broadcast,
2398 &ns->eth.rx_broadcast);
2399 /* Workaround: CRC size should not be included in byte statistics,
2400 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2402 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2403 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2405 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2406 pf->offset_loaded, &os->eth.rx_discards,
2407 &ns->eth.rx_discards);
2408 /* GLPRT_REPC not supported */
2409 /* GLPRT_RMPC not supported */
2410 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2412 &os->eth.rx_unknown_protocol,
2413 &ns->eth.rx_unknown_protocol);
2414 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2415 I40E_GLPRT_GOTCL(hw->port),
2416 pf->offset_loaded, &os->eth.tx_bytes,
2418 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2419 I40E_GLPRT_UPTCL(hw->port),
2420 pf->offset_loaded, &os->eth.tx_unicast,
2421 &ns->eth.tx_unicast);
2422 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2423 I40E_GLPRT_MPTCL(hw->port),
2424 pf->offset_loaded, &os->eth.tx_multicast,
2425 &ns->eth.tx_multicast);
2426 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2427 I40E_GLPRT_BPTCL(hw->port),
2428 pf->offset_loaded, &os->eth.tx_broadcast,
2429 &ns->eth.tx_broadcast);
2430 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2431 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2432 /* GLPRT_TEPC not supported */
2434 /* additional port specific stats */
2435 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2436 pf->offset_loaded, &os->tx_dropped_link_down,
2437 &ns->tx_dropped_link_down);
2438 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2439 pf->offset_loaded, &os->crc_errors,
2441 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2442 pf->offset_loaded, &os->illegal_bytes,
2443 &ns->illegal_bytes);
2444 /* GLPRT_ERRBC not supported */
2445 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2446 pf->offset_loaded, &os->mac_local_faults,
2447 &ns->mac_local_faults);
2448 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2449 pf->offset_loaded, &os->mac_remote_faults,
2450 &ns->mac_remote_faults);
2451 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2452 pf->offset_loaded, &os->rx_length_errors,
2453 &ns->rx_length_errors);
2454 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2455 pf->offset_loaded, &os->link_xon_rx,
2457 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2458 pf->offset_loaded, &os->link_xoff_rx,
2460 for (i = 0; i < 8; i++) {
2461 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2463 &os->priority_xon_rx[i],
2464 &ns->priority_xon_rx[i]);
2465 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2467 &os->priority_xoff_rx[i],
2468 &ns->priority_xoff_rx[i]);
2470 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2471 pf->offset_loaded, &os->link_xon_tx,
2473 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2474 pf->offset_loaded, &os->link_xoff_tx,
2476 for (i = 0; i < 8; i++) {
2477 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2479 &os->priority_xon_tx[i],
2480 &ns->priority_xon_tx[i]);
2481 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2483 &os->priority_xoff_tx[i],
2484 &ns->priority_xoff_tx[i]);
2485 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2487 &os->priority_xon_2_xoff[i],
2488 &ns->priority_xon_2_xoff[i]);
2490 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2491 I40E_GLPRT_PRC64L(hw->port),
2492 pf->offset_loaded, &os->rx_size_64,
2494 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2495 I40E_GLPRT_PRC127L(hw->port),
2496 pf->offset_loaded, &os->rx_size_127,
2498 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2499 I40E_GLPRT_PRC255L(hw->port),
2500 pf->offset_loaded, &os->rx_size_255,
2502 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2503 I40E_GLPRT_PRC511L(hw->port),
2504 pf->offset_loaded, &os->rx_size_511,
2506 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2507 I40E_GLPRT_PRC1023L(hw->port),
2508 pf->offset_loaded, &os->rx_size_1023,
2510 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2511 I40E_GLPRT_PRC1522L(hw->port),
2512 pf->offset_loaded, &os->rx_size_1522,
2514 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2515 I40E_GLPRT_PRC9522L(hw->port),
2516 pf->offset_loaded, &os->rx_size_big,
2518 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2519 pf->offset_loaded, &os->rx_undersize,
2521 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2522 pf->offset_loaded, &os->rx_fragments,
2524 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2525 pf->offset_loaded, &os->rx_oversize,
2527 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2528 pf->offset_loaded, &os->rx_jabber,
2530 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2531 I40E_GLPRT_PTC64L(hw->port),
2532 pf->offset_loaded, &os->tx_size_64,
2534 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2535 I40E_GLPRT_PTC127L(hw->port),
2536 pf->offset_loaded, &os->tx_size_127,
2538 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2539 I40E_GLPRT_PTC255L(hw->port),
2540 pf->offset_loaded, &os->tx_size_255,
2542 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2543 I40E_GLPRT_PTC511L(hw->port),
2544 pf->offset_loaded, &os->tx_size_511,
2546 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2547 I40E_GLPRT_PTC1023L(hw->port),
2548 pf->offset_loaded, &os->tx_size_1023,
2550 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2551 I40E_GLPRT_PTC1522L(hw->port),
2552 pf->offset_loaded, &os->tx_size_1522,
2554 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2555 I40E_GLPRT_PTC9522L(hw->port),
2556 pf->offset_loaded, &os->tx_size_big,
2558 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2560 &os->fd_sb_match, &ns->fd_sb_match);
2561 /* GLPRT_MSPDC not supported */
2562 /* GLPRT_XEC not supported */
2564 pf->offset_loaded = true;
2567 i40e_update_vsi_stats(pf->main_vsi);
2570 /* Get all statistics of a port */
2572 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2574 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2575 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2576 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2579 /* call read registers - updates values, now write them to struct */
2580 i40e_read_stats_registers(pf, hw);
2582 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2583 pf->main_vsi->eth_stats.rx_multicast +
2584 pf->main_vsi->eth_stats.rx_broadcast -
2585 pf->main_vsi->eth_stats.rx_discards;
2586 stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2587 pf->main_vsi->eth_stats.tx_multicast +
2588 pf->main_vsi->eth_stats.tx_broadcast;
2589 stats->ibytes = ns->eth.rx_bytes;
2590 stats->obytes = ns->eth.tx_bytes;
2591 stats->oerrors = ns->eth.tx_errors +
2592 pf->main_vsi->eth_stats.tx_errors;
2595 stats->imissed = ns->eth.rx_discards +
2596 pf->main_vsi->eth_stats.rx_discards;
2597 stats->ierrors = ns->crc_errors +
2598 ns->rx_length_errors + ns->rx_undersize +
2599 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2601 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2602 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
2603 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
2604 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
2605 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
2606 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
2607 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2608 ns->eth.rx_unknown_protocol);
2609 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
2610 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
2611 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
2612 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
2613 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
2614 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
2616 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
2617 ns->tx_dropped_link_down);
2618 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
2619 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
2621 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
2622 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
2623 ns->mac_local_faults);
2624 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
2625 ns->mac_remote_faults);
2626 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
2627 ns->rx_length_errors);
2628 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
2629 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
2630 for (i = 0; i < 8; i++) {
2631 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
2632 i, ns->priority_xon_rx[i]);
2633 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
2634 i, ns->priority_xoff_rx[i]);
2636 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
2637 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
2638 for (i = 0; i < 8; i++) {
2639 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
2640 i, ns->priority_xon_tx[i]);
2641 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
2642 i, ns->priority_xoff_tx[i]);
2643 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
2644 i, ns->priority_xon_2_xoff[i]);
2646 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
2647 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
2648 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
2649 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
2650 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
2651 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
2652 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
2653 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
2654 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
2655 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
2656 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
2657 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
2658 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
2659 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
2660 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
2661 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
2662 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
2663 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
2664 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2665 ns->mac_short_packet_dropped);
2666 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
2667 ns->checksum_error);
2668 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
2669 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2672 /* Reset the statistics */
2674 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2676 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2677 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2679 /* Mark PF and VSI stats to update the offset, aka "reset" */
2680 pf->offset_loaded = false;
2682 pf->main_vsi->offset_loaded = false;
2684 /* read the stats, reading current register values into offset */
2685 i40e_read_stats_registers(pf, hw);
2689 i40e_xstats_calc_num(void)
2691 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2692 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2693 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2696 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2697 struct rte_eth_xstat_name *xstats_names,
2698 __rte_unused unsigned limit)
2703 if (xstats_names == NULL)
2704 return i40e_xstats_calc_num();
2706 /* Note: limit checked in rte_eth_xstats_names() */
2708 /* Get stats from i40e_eth_stats struct */
2709 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2710 snprintf(xstats_names[count].name,
2711 sizeof(xstats_names[count].name),
2712 "%s", rte_i40e_stats_strings[i].name);
2716 /* Get individiual stats from i40e_hw_port struct */
2717 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2718 snprintf(xstats_names[count].name,
2719 sizeof(xstats_names[count].name),
2720 "%s", rte_i40e_hw_port_strings[i].name);
2724 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2725 for (prio = 0; prio < 8; prio++) {
2726 snprintf(xstats_names[count].name,
2727 sizeof(xstats_names[count].name),
2728 "rx_priority%u_%s", prio,
2729 rte_i40e_rxq_prio_strings[i].name);
2734 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2735 for (prio = 0; prio < 8; prio++) {
2736 snprintf(xstats_names[count].name,
2737 sizeof(xstats_names[count].name),
2738 "tx_priority%u_%s", prio,
2739 rte_i40e_txq_prio_strings[i].name);
2747 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2750 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2751 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2752 unsigned i, count, prio;
2753 struct i40e_hw_port_stats *hw_stats = &pf->stats;
2755 count = i40e_xstats_calc_num();
2759 i40e_read_stats_registers(pf, hw);
2766 /* Get stats from i40e_eth_stats struct */
2767 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2768 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2769 rte_i40e_stats_strings[i].offset);
2770 xstats[count].id = count;
2774 /* Get individiual stats from i40e_hw_port struct */
2775 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2776 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2777 rte_i40e_hw_port_strings[i].offset);
2778 xstats[count].id = count;
2782 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2783 for (prio = 0; prio < 8; prio++) {
2784 xstats[count].value =
2785 *(uint64_t *)(((char *)hw_stats) +
2786 rte_i40e_rxq_prio_strings[i].offset +
2787 (sizeof(uint64_t) * prio));
2788 xstats[count].id = count;
2793 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2794 for (prio = 0; prio < 8; prio++) {
2795 xstats[count].value =
2796 *(uint64_t *)(((char *)hw_stats) +
2797 rte_i40e_txq_prio_strings[i].offset +
2798 (sizeof(uint64_t) * prio));
2799 xstats[count].id = count;
2808 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2809 __rte_unused uint16_t queue_id,
2810 __rte_unused uint8_t stat_idx,
2811 __rte_unused uint8_t is_rx)
2813 PMD_INIT_FUNC_TRACE();
2819 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2821 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2827 full_ver = hw->nvm.oem_ver;
2828 ver = (u8)(full_ver >> 24);
2829 build = (u16)((full_ver >> 8) & 0xffff);
2830 patch = (u8)(full_ver & 0xff);
2832 ret = snprintf(fw_version, fw_size,
2833 "%d.%d%d 0x%08x %d.%d.%d",
2834 ((hw->nvm.version >> 12) & 0xf),
2835 ((hw->nvm.version >> 4) & 0xff),
2836 (hw->nvm.version & 0xf), hw->nvm.eetrack,
2839 ret += 1; /* add the size of '\0' */
2840 if (fw_size < (u32)ret)
2847 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2849 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2850 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2851 struct i40e_vsi *vsi = pf->main_vsi;
2852 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2854 dev_info->pci_dev = pci_dev;
2855 dev_info->max_rx_queues = vsi->nb_qps;
2856 dev_info->max_tx_queues = vsi->nb_qps;
2857 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2858 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2859 dev_info->max_mac_addrs = vsi->max_macaddrs;
2860 dev_info->max_vfs = pci_dev->max_vfs;
2861 dev_info->rx_offload_capa =
2862 DEV_RX_OFFLOAD_VLAN_STRIP |
2863 DEV_RX_OFFLOAD_QINQ_STRIP |
2864 DEV_RX_OFFLOAD_IPV4_CKSUM |
2865 DEV_RX_OFFLOAD_UDP_CKSUM |
2866 DEV_RX_OFFLOAD_TCP_CKSUM;
2867 dev_info->tx_offload_capa =
2868 DEV_TX_OFFLOAD_VLAN_INSERT |
2869 DEV_TX_OFFLOAD_QINQ_INSERT |
2870 DEV_TX_OFFLOAD_IPV4_CKSUM |
2871 DEV_TX_OFFLOAD_UDP_CKSUM |
2872 DEV_TX_OFFLOAD_TCP_CKSUM |
2873 DEV_TX_OFFLOAD_SCTP_CKSUM |
2874 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2875 DEV_TX_OFFLOAD_TCP_TSO |
2876 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2877 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2878 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2879 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2880 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2882 dev_info->reta_size = pf->hash_lut_size;
2883 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2885 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2887 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2888 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2889 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2891 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2895 dev_info->default_txconf = (struct rte_eth_txconf) {
2897 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2898 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2899 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2901 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2902 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2903 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2904 ETH_TXQ_FLAGS_NOOFFLOADS,
2907 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2908 .nb_max = I40E_MAX_RING_DESC,
2909 .nb_min = I40E_MIN_RING_DESC,
2910 .nb_align = I40E_ALIGN_RING_DESC,
2913 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2914 .nb_max = I40E_MAX_RING_DESC,
2915 .nb_min = I40E_MIN_RING_DESC,
2916 .nb_align = I40E_ALIGN_RING_DESC,
2917 .nb_seg_max = I40E_TX_MAX_SEG,
2918 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
2921 if (pf->flags & I40E_FLAG_VMDQ) {
2922 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2923 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2924 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2925 pf->max_nb_vmdq_vsi;
2926 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2927 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2928 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2931 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2933 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2934 else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2936 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2939 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2943 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2945 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2946 struct i40e_vsi *vsi = pf->main_vsi;
2947 PMD_INIT_FUNC_TRACE();
2950 return i40e_vsi_add_vlan(vsi, vlan_id);
2952 return i40e_vsi_delete_vlan(vsi, vlan_id);
2956 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2957 enum rte_vlan_type vlan_type,
2960 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2961 uint64_t reg_r = 0, reg_w = 0;
2962 uint16_t reg_id = 0;
2964 int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2966 switch (vlan_type) {
2967 case ETH_VLAN_TYPE_OUTER:
2973 case ETH_VLAN_TYPE_INNER:
2979 "Unsupported vlan type in single vlan.");
2985 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2988 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2990 if (ret != I40E_SUCCESS) {
2992 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
2998 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3001 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3002 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3003 if (reg_r == reg_w) {
3005 PMD_DRV_LOG(DEBUG, "No need to write");
3009 ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3011 if (ret != I40E_SUCCESS) {
3014 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3019 "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3026 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3028 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3029 struct i40e_vsi *vsi = pf->main_vsi;
3031 if (mask & ETH_VLAN_FILTER_MASK) {
3032 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3033 i40e_vsi_config_vlan_filter(vsi, TRUE);
3035 i40e_vsi_config_vlan_filter(vsi, FALSE);
3038 if (mask & ETH_VLAN_STRIP_MASK) {
3039 /* Enable or disable VLAN stripping */
3040 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3041 i40e_vsi_config_vlan_stripping(vsi, TRUE);
3043 i40e_vsi_config_vlan_stripping(vsi, FALSE);
3046 if (mask & ETH_VLAN_EXTEND_MASK) {
3047 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3048 i40e_vsi_config_double_vlan(vsi, TRUE);
3049 /* Set global registers with default ether type value */
3050 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3052 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3056 i40e_vsi_config_double_vlan(vsi, FALSE);
3061 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3062 __rte_unused uint16_t queue,
3063 __rte_unused int on)
3065 PMD_INIT_FUNC_TRACE();
3069 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3071 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3072 struct i40e_vsi *vsi = pf->main_vsi;
3073 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3074 struct i40e_vsi_vlan_pvid_info info;
3076 memset(&info, 0, sizeof(info));
3079 info.config.pvid = pvid;
3081 info.config.reject.tagged =
3082 data->dev_conf.txmode.hw_vlan_reject_tagged;
3083 info.config.reject.untagged =
3084 data->dev_conf.txmode.hw_vlan_reject_untagged;
3087 return i40e_vsi_vlan_pvid_set(vsi, &info);
3091 i40e_dev_led_on(struct rte_eth_dev *dev)
3093 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3094 uint32_t mode = i40e_led_get(hw);
3097 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3103 i40e_dev_led_off(struct rte_eth_dev *dev)
3105 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3106 uint32_t mode = i40e_led_get(hw);
3109 i40e_led_set(hw, 0, false);
3115 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3117 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3118 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3120 fc_conf->pause_time = pf->fc_conf.pause_time;
3121 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3122 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3124 /* Return current mode according to actual setting*/
3125 switch (hw->fc.current_mode) {
3127 fc_conf->mode = RTE_FC_FULL;
3129 case I40E_FC_TX_PAUSE:
3130 fc_conf->mode = RTE_FC_TX_PAUSE;
3132 case I40E_FC_RX_PAUSE:
3133 fc_conf->mode = RTE_FC_RX_PAUSE;
3137 fc_conf->mode = RTE_FC_NONE;
3144 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3146 uint32_t mflcn_reg, fctrl_reg, reg;
3147 uint32_t max_high_water;
3148 uint8_t i, aq_failure;
3152 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3153 [RTE_FC_NONE] = I40E_FC_NONE,
3154 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3155 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3156 [RTE_FC_FULL] = I40E_FC_FULL
3159 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3161 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3162 if ((fc_conf->high_water > max_high_water) ||
3163 (fc_conf->high_water < fc_conf->low_water)) {
3165 "Invalid high/low water setup value in KB, High_water must be <= %d.",
3170 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3171 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3172 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3174 pf->fc_conf.pause_time = fc_conf->pause_time;
3175 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3176 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3178 PMD_INIT_FUNC_TRACE();
3180 /* All the link flow control related enable/disable register
3181 * configuration is handle by the F/W
3183 err = i40e_set_fc(hw, &aq_failure, true);
3187 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3188 /* Configure flow control refresh threshold,
3189 * the value for stat_tx_pause_refresh_timer[8]
3190 * is used for global pause operation.
3194 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3195 pf->fc_conf.pause_time);
3197 /* configure the timer value included in transmitted pause
3199 * the value for stat_tx_pause_quanta[8] is used for global
3202 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3203 pf->fc_conf.pause_time);
3205 fctrl_reg = I40E_READ_REG(hw,
3206 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3208 if (fc_conf->mac_ctrl_frame_fwd != 0)
3209 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3211 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3213 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3216 /* Configure pause time (2 TCs per register) */
3217 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3218 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3219 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3221 /* Configure flow control refresh threshold value */
3222 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3223 pf->fc_conf.pause_time / 2);
3225 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3227 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3228 *depending on configuration
3230 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3231 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3232 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3234 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3235 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3238 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3241 /* config the water marker both based on the packets and bytes */
3242 I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3243 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3244 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3245 I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3246 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3247 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3248 I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3249 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3251 I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3252 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3255 I40E_WRITE_FLUSH(hw);
3261 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3262 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3264 PMD_INIT_FUNC_TRACE();
3269 /* Add a MAC address, and update filters */
3271 i40e_macaddr_add(struct rte_eth_dev *dev,
3272 struct ether_addr *mac_addr,
3273 __rte_unused uint32_t index,
3276 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3277 struct i40e_mac_filter_info mac_filter;
3278 struct i40e_vsi *vsi;
3281 /* If VMDQ not enabled or configured, return */
3282 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3283 !pf->nb_cfg_vmdq_vsi)) {
3284 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3285 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3290 if (pool > pf->nb_cfg_vmdq_vsi) {
3291 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3292 pool, pf->nb_cfg_vmdq_vsi);
3296 (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3297 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3298 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3300 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3305 vsi = pf->vmdq[pool - 1].vsi;
3307 ret = i40e_vsi_add_mac(vsi, &mac_filter);
3308 if (ret != I40E_SUCCESS) {
3309 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3315 /* Remove a MAC address, and update filters */
3317 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3319 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3320 struct i40e_vsi *vsi;
3321 struct rte_eth_dev_data *data = dev->data;
3322 struct ether_addr *macaddr;
3327 macaddr = &(data->mac_addrs[index]);
3329 pool_sel = dev->data->mac_pool_sel[index];
3331 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3332 if (pool_sel & (1ULL << i)) {
3336 /* No VMDQ pool enabled or configured */
3337 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3338 (i > pf->nb_cfg_vmdq_vsi)) {
3340 "No VMDQ pool enabled/configured");
3343 vsi = pf->vmdq[i - 1].vsi;
3345 ret = i40e_vsi_delete_mac(vsi, macaddr);
3348 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3355 /* Set perfect match or hash match of MAC and VLAN for a VF */
3357 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3358 struct rte_eth_mac_filter *filter,
3362 struct i40e_mac_filter_info mac_filter;
3363 struct ether_addr old_mac;
3364 struct ether_addr *new_mac;
3365 struct i40e_pf_vf *vf = NULL;
3370 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3373 hw = I40E_PF_TO_HW(pf);
3375 if (filter == NULL) {
3376 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3380 new_mac = &filter->mac_addr;
3382 if (is_zero_ether_addr(new_mac)) {
3383 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3387 vf_id = filter->dst_id;
3389 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3390 PMD_DRV_LOG(ERR, "Invalid argument.");
3393 vf = &pf->vfs[vf_id];
3395 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3396 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3401 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3402 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3404 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3407 mac_filter.filter_type = filter->filter_type;
3408 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3409 if (ret != I40E_SUCCESS) {
3410 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3413 ether_addr_copy(new_mac, &pf->dev_addr);
3415 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3417 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3418 if (ret != I40E_SUCCESS) {
3419 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3423 /* Clear device address as it has been removed */
3424 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3425 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3431 /* MAC filter handle */
3433 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3436 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3437 struct rte_eth_mac_filter *filter;
3438 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3439 int ret = I40E_NOT_SUPPORTED;
3441 filter = (struct rte_eth_mac_filter *)(arg);
3443 switch (filter_op) {
3444 case RTE_ETH_FILTER_NOP:
3447 case RTE_ETH_FILTER_ADD:
3448 i40e_pf_disable_irq0(hw);
3450 ret = i40e_vf_mac_filter_set(pf, filter, 1);
3451 i40e_pf_enable_irq0(hw);
3453 case RTE_ETH_FILTER_DELETE:
3454 i40e_pf_disable_irq0(hw);
3456 ret = i40e_vf_mac_filter_set(pf, filter, 0);
3457 i40e_pf_enable_irq0(hw);
3460 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3461 ret = I40E_ERR_PARAM;
3469 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3471 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3472 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3478 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3479 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3482 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3486 uint32_t *lut_dw = (uint32_t *)lut;
3487 uint16_t i, lut_size_dw = lut_size / 4;
3489 for (i = 0; i < lut_size_dw; i++)
3490 lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3497 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3506 pf = I40E_VSI_TO_PF(vsi);
3507 hw = I40E_VSI_TO_HW(vsi);
3509 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3510 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3513 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3517 uint32_t *lut_dw = (uint32_t *)lut;
3518 uint16_t i, lut_size_dw = lut_size / 4;
3520 for (i = 0; i < lut_size_dw; i++)
3521 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3522 I40E_WRITE_FLUSH(hw);
3529 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3530 struct rte_eth_rss_reta_entry64 *reta_conf,
3533 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3534 uint16_t i, lut_size = pf->hash_lut_size;
3535 uint16_t idx, shift;
3539 if (reta_size != lut_size ||
3540 reta_size > ETH_RSS_RETA_SIZE_512) {
3542 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3543 reta_size, lut_size);
3547 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3549 PMD_DRV_LOG(ERR, "No memory can be allocated");
3552 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3555 for (i = 0; i < reta_size; i++) {
3556 idx = i / RTE_RETA_GROUP_SIZE;
3557 shift = i % RTE_RETA_GROUP_SIZE;
3558 if (reta_conf[idx].mask & (1ULL << shift))
3559 lut[i] = reta_conf[idx].reta[shift];
3561 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3570 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3571 struct rte_eth_rss_reta_entry64 *reta_conf,
3574 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3575 uint16_t i, lut_size = pf->hash_lut_size;
3576 uint16_t idx, shift;
3580 if (reta_size != lut_size ||
3581 reta_size > ETH_RSS_RETA_SIZE_512) {
3583 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3584 reta_size, lut_size);
3588 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3590 PMD_DRV_LOG(ERR, "No memory can be allocated");
3594 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3597 for (i = 0; i < reta_size; i++) {
3598 idx = i / RTE_RETA_GROUP_SIZE;
3599 shift = i % RTE_RETA_GROUP_SIZE;
3600 if (reta_conf[idx].mask & (1ULL << shift))
3601 reta_conf[idx].reta[shift] = lut[i];
3611 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3612 * @hw: pointer to the HW structure
3613 * @mem: pointer to mem struct to fill out
3614 * @size: size of memory requested
3615 * @alignment: what to align the allocation to
3617 enum i40e_status_code
3618 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3619 struct i40e_dma_mem *mem,
3623 const struct rte_memzone *mz = NULL;
3624 char z_name[RTE_MEMZONE_NAMESIZE];
3627 return I40E_ERR_PARAM;
3629 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3630 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3631 alignment, RTE_PGSIZE_2M);
3633 return I40E_ERR_NO_MEMORY;
3637 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3638 mem->zone = (const void *)mz;
3640 "memzone %s allocated with physical address: %"PRIu64,
3643 return I40E_SUCCESS;
3647 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3648 * @hw: pointer to the HW structure
3649 * @mem: ptr to mem struct to free
3651 enum i40e_status_code
3652 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3653 struct i40e_dma_mem *mem)
3656 return I40E_ERR_PARAM;
3659 "memzone %s to be freed with physical address: %"PRIu64,
3660 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3661 rte_memzone_free((const struct rte_memzone *)mem->zone);
3666 return I40E_SUCCESS;
3670 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3671 * @hw: pointer to the HW structure
3672 * @mem: pointer to mem struct to fill out
3673 * @size: size of memory requested
3675 enum i40e_status_code
3676 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3677 struct i40e_virt_mem *mem,
3681 return I40E_ERR_PARAM;
3684 mem->va = rte_zmalloc("i40e", size, 0);
3687 return I40E_SUCCESS;
3689 return I40E_ERR_NO_MEMORY;
3693 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3694 * @hw: pointer to the HW structure
3695 * @mem: pointer to mem struct to free
3697 enum i40e_status_code
3698 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3699 struct i40e_virt_mem *mem)
3702 return I40E_ERR_PARAM;
3707 return I40E_SUCCESS;
3711 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3713 rte_spinlock_init(&sp->spinlock);
3717 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3719 rte_spinlock_lock(&sp->spinlock);
3723 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3725 rte_spinlock_unlock(&sp->spinlock);
3729 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3735 * Get the hardware capabilities, which will be parsed
3736 * and saved into struct i40e_hw.
3739 i40e_get_cap(struct i40e_hw *hw)
3741 struct i40e_aqc_list_capabilities_element_resp *buf;
3742 uint16_t len, size = 0;
3745 /* Calculate a huge enough buff for saving response data temporarily */
3746 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3747 I40E_MAX_CAP_ELE_NUM;
3748 buf = rte_zmalloc("i40e", len, 0);
3750 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3751 return I40E_ERR_NO_MEMORY;
3754 /* Get, parse the capabilities and save it to hw */
3755 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3756 i40e_aqc_opc_list_func_capabilities, NULL);
3757 if (ret != I40E_SUCCESS)
3758 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3760 /* Free the temporary buffer after being used */
3767 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3769 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3770 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3771 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
3772 uint16_t qp_count = 0, vsi_count = 0;
3774 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3775 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3778 /* Add the parameter init for LFC */
3779 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3780 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3781 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3783 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3784 pf->max_num_vsi = hw->func_caps.num_vsis;
3785 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3786 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3787 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3789 /* FDir queue/VSI allocation */
3790 pf->fdir_qp_offset = 0;
3791 if (hw->func_caps.fd) {
3792 pf->flags |= I40E_FLAG_FDIR;
3793 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3795 pf->fdir_nb_qps = 0;
3797 qp_count += pf->fdir_nb_qps;
3800 /* LAN queue/VSI allocation */
3801 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3802 if (!hw->func_caps.rss) {
3805 pf->flags |= I40E_FLAG_RSS;
3806 if (hw->mac.type == I40E_MAC_X722)
3807 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3808 pf->lan_nb_qps = pf->lan_nb_qp_max;
3810 qp_count += pf->lan_nb_qps;
3813 /* VF queue/VSI allocation */
3814 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3815 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3816 pf->flags |= I40E_FLAG_SRIOV;
3817 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3818 pf->vf_num = pci_dev->max_vfs;
3820 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
3821 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
3826 qp_count += pf->vf_nb_qps * pf->vf_num;
3827 vsi_count += pf->vf_num;
3829 /* VMDq queue/VSI allocation */
3830 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3831 pf->vmdq_nb_qps = 0;
3832 pf->max_nb_vmdq_vsi = 0;
3833 if (hw->func_caps.vmdq) {
3834 if (qp_count < hw->func_caps.num_tx_qp &&
3835 vsi_count < hw->func_caps.num_vsis) {
3836 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3837 qp_count) / pf->vmdq_nb_qp_max;
3839 /* Limit the maximum number of VMDq vsi to the maximum
3840 * ethdev can support
3842 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3843 hw->func_caps.num_vsis - vsi_count);
3844 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3846 if (pf->max_nb_vmdq_vsi) {
3847 pf->flags |= I40E_FLAG_VMDQ;
3848 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3850 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
3851 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
3852 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
3855 "No enough queues left for VMDq");
3858 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3861 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3862 vsi_count += pf->max_nb_vmdq_vsi;
3864 if (hw->func_caps.dcb)
3865 pf->flags |= I40E_FLAG_DCB;
3867 if (qp_count > hw->func_caps.num_tx_qp) {
3869 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
3870 qp_count, hw->func_caps.num_tx_qp);
3873 if (vsi_count > hw->func_caps.num_vsis) {
3875 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
3876 vsi_count, hw->func_caps.num_vsis);
3884 i40e_pf_get_switch_config(struct i40e_pf *pf)
3886 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3887 struct i40e_aqc_get_switch_config_resp *switch_config;
3888 struct i40e_aqc_switch_config_element_resp *element;
3889 uint16_t start_seid = 0, num_reported;
3892 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3893 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3894 if (!switch_config) {
3895 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3899 /* Get the switch configurations */
3900 ret = i40e_aq_get_switch_config(hw, switch_config,
3901 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3902 if (ret != I40E_SUCCESS) {
3903 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3906 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3907 if (num_reported != 1) { /* The number should be 1 */
3908 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3912 /* Parse the switch configuration elements */
3913 element = &(switch_config->element[0]);
3914 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3915 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3916 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3918 PMD_DRV_LOG(INFO, "Unknown element type");
3921 rte_free(switch_config);
3927 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3930 struct pool_entry *entry;
3932 if (pool == NULL || num == 0)
3935 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3936 if (entry == NULL) {
3937 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3941 /* queue heap initialize */
3942 pool->num_free = num;
3943 pool->num_alloc = 0;
3945 LIST_INIT(&pool->alloc_list);
3946 LIST_INIT(&pool->free_list);
3948 /* Initialize element */
3952 LIST_INSERT_HEAD(&pool->free_list, entry, next);
3957 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3959 struct pool_entry *entry, *next_entry;
3964 for (entry = LIST_FIRST(&pool->alloc_list);
3965 entry && (next_entry = LIST_NEXT(entry, next), 1);
3966 entry = next_entry) {
3967 LIST_REMOVE(entry, next);
3971 for (entry = LIST_FIRST(&pool->free_list);
3972 entry && (next_entry = LIST_NEXT(entry, next), 1);
3973 entry = next_entry) {
3974 LIST_REMOVE(entry, next);
3979 pool->num_alloc = 0;
3981 LIST_INIT(&pool->alloc_list);
3982 LIST_INIT(&pool->free_list);
3986 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3989 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3990 uint32_t pool_offset;
3994 PMD_DRV_LOG(ERR, "Invalid parameter");
3998 pool_offset = base - pool->base;
3999 /* Lookup in alloc list */
4000 LIST_FOREACH(entry, &pool->alloc_list, next) {
4001 if (entry->base == pool_offset) {
4002 valid_entry = entry;
4003 LIST_REMOVE(entry, next);
4008 /* Not find, return */
4009 if (valid_entry == NULL) {
4010 PMD_DRV_LOG(ERR, "Failed to find entry");
4015 * Found it, move it to free list and try to merge.
4016 * In order to make merge easier, always sort it by qbase.
4017 * Find adjacent prev and last entries.
4020 LIST_FOREACH(entry, &pool->free_list, next) {
4021 if (entry->base > valid_entry->base) {
4029 /* Try to merge with next one*/
4031 /* Merge with next one */
4032 if (valid_entry->base + valid_entry->len == next->base) {
4033 next->base = valid_entry->base;
4034 next->len += valid_entry->len;
4035 rte_free(valid_entry);
4042 /* Merge with previous one */
4043 if (prev->base + prev->len == valid_entry->base) {
4044 prev->len += valid_entry->len;
4045 /* If it merge with next one, remove next node */
4047 LIST_REMOVE(valid_entry, next);
4048 rte_free(valid_entry);
4050 rte_free(valid_entry);
4056 /* Not find any entry to merge, insert */
4059 LIST_INSERT_AFTER(prev, valid_entry, next);
4060 else if (next != NULL)
4061 LIST_INSERT_BEFORE(next, valid_entry, next);
4062 else /* It's empty list, insert to head */
4063 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4066 pool->num_free += valid_entry->len;
4067 pool->num_alloc -= valid_entry->len;
4073 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4076 struct pool_entry *entry, *valid_entry;
4078 if (pool == NULL || num == 0) {
4079 PMD_DRV_LOG(ERR, "Invalid parameter");
4083 if (pool->num_free < num) {
4084 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4085 num, pool->num_free);
4090 /* Lookup in free list and find most fit one */
4091 LIST_FOREACH(entry, &pool->free_list, next) {
4092 if (entry->len >= num) {
4094 if (entry->len == num) {
4095 valid_entry = entry;
4098 if (valid_entry == NULL || valid_entry->len > entry->len)
4099 valid_entry = entry;
4103 /* Not find one to satisfy the request, return */
4104 if (valid_entry == NULL) {
4105 PMD_DRV_LOG(ERR, "No valid entry found");
4109 * The entry have equal queue number as requested,
4110 * remove it from alloc_list.
4112 if (valid_entry->len == num) {
4113 LIST_REMOVE(valid_entry, next);
4116 * The entry have more numbers than requested,
4117 * create a new entry for alloc_list and minus its
4118 * queue base and number in free_list.
4120 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4121 if (entry == NULL) {
4123 "Failed to allocate memory for resource pool");
4126 entry->base = valid_entry->base;
4128 valid_entry->base += num;
4129 valid_entry->len -= num;
4130 valid_entry = entry;
4133 /* Insert it into alloc list, not sorted */
4134 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4136 pool->num_free -= valid_entry->len;
4137 pool->num_alloc += valid_entry->len;
4139 return valid_entry->base + pool->base;
4143 * bitmap_is_subset - Check whether src2 is subset of src1
4146 bitmap_is_subset(uint8_t src1, uint8_t src2)
4148 return !((src1 ^ src2) & src2);
4151 static enum i40e_status_code
4152 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4154 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4156 /* If DCB is not supported, only default TC is supported */
4157 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4158 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4159 return I40E_NOT_SUPPORTED;
4162 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4164 "Enabled TC map 0x%x not applicable to HW support 0x%x",
4165 hw->func_caps.enabled_tcmap, enabled_tcmap);
4166 return I40E_NOT_SUPPORTED;
4168 return I40E_SUCCESS;
4172 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4173 struct i40e_vsi_vlan_pvid_info *info)
4176 struct i40e_vsi_context ctxt;
4177 uint8_t vlan_flags = 0;
4180 if (vsi == NULL || info == NULL) {
4181 PMD_DRV_LOG(ERR, "invalid parameters");
4182 return I40E_ERR_PARAM;
4186 vsi->info.pvid = info->config.pvid;
4188 * If insert pvid is enabled, only tagged pkts are
4189 * allowed to be sent out.
4191 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4192 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4195 if (info->config.reject.tagged == 0)
4196 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4198 if (info->config.reject.untagged == 0)
4199 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4201 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4202 I40E_AQ_VSI_PVLAN_MODE_MASK);
4203 vsi->info.port_vlan_flags |= vlan_flags;
4204 vsi->info.valid_sections =
4205 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4206 memset(&ctxt, 0, sizeof(ctxt));
4207 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4208 ctxt.seid = vsi->seid;
4210 hw = I40E_VSI_TO_HW(vsi);
4211 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4212 if (ret != I40E_SUCCESS)
4213 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4219 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4221 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4223 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4225 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4226 if (ret != I40E_SUCCESS)
4230 PMD_DRV_LOG(ERR, "seid not valid");
4234 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4235 tc_bw_data.tc_valid_bits = enabled_tcmap;
4236 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4237 tc_bw_data.tc_bw_credits[i] =
4238 (enabled_tcmap & (1 << i)) ? 1 : 0;
4240 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4241 if (ret != I40E_SUCCESS) {
4242 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4246 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4247 sizeof(vsi->info.qs_handle));
4248 return I40E_SUCCESS;
4251 static enum i40e_status_code
4252 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4253 struct i40e_aqc_vsi_properties_data *info,
4254 uint8_t enabled_tcmap)
4256 enum i40e_status_code ret;
4257 int i, total_tc = 0;
4258 uint16_t qpnum_per_tc, bsf, qp_idx;
4260 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4261 if (ret != I40E_SUCCESS)
4264 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4265 if (enabled_tcmap & (1 << i))
4267 vsi->enabled_tc = enabled_tcmap;
4269 /* Number of queues per enabled TC */
4270 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4271 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4272 bsf = rte_bsf32(qpnum_per_tc);
4274 /* Adjust the queue number to actual queues that can be applied */
4275 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4276 vsi->nb_qps = qpnum_per_tc * total_tc;
4279 * Configure TC and queue mapping parameters, for enabled TC,
4280 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4281 * default queue will serve it.
4284 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4285 if (vsi->enabled_tc & (1 << i)) {
4286 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4287 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4288 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4289 qp_idx += qpnum_per_tc;
4291 info->tc_mapping[i] = 0;
4294 /* Associate queue number with VSI */
4295 if (vsi->type == I40E_VSI_SRIOV) {
4296 info->mapping_flags |=
4297 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4298 for (i = 0; i < vsi->nb_qps; i++)
4299 info->queue_mapping[i] =
4300 rte_cpu_to_le_16(vsi->base_queue + i);
4302 info->mapping_flags |=
4303 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4304 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4306 info->valid_sections |=
4307 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4309 return I40E_SUCCESS;
4313 i40e_veb_release(struct i40e_veb *veb)
4315 struct i40e_vsi *vsi;
4321 if (!TAILQ_EMPTY(&veb->head)) {
4322 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4325 /* associate_vsi field is NULL for floating VEB */
4326 if (veb->associate_vsi != NULL) {
4327 vsi = veb->associate_vsi;
4328 hw = I40E_VSI_TO_HW(vsi);
4330 vsi->uplink_seid = veb->uplink_seid;
4333 veb->associate_pf->main_vsi->floating_veb = NULL;
4334 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4337 i40e_aq_delete_element(hw, veb->seid, NULL);
4339 return I40E_SUCCESS;
4343 static struct i40e_veb *
4344 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4346 struct i40e_veb *veb;
4352 "veb setup failed, associated PF shouldn't null");
4355 hw = I40E_PF_TO_HW(pf);
4357 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4359 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4363 veb->associate_vsi = vsi;
4364 veb->associate_pf = pf;
4365 TAILQ_INIT(&veb->head);
4366 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4368 /* create floating veb if vsi is NULL */
4370 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4371 I40E_DEFAULT_TCMAP, false,
4372 &veb->seid, false, NULL);
4374 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4375 true, &veb->seid, false, NULL);
4378 if (ret != I40E_SUCCESS) {
4379 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4380 hw->aq.asq_last_status);
4383 veb->enabled_tc = I40E_DEFAULT_TCMAP;
4385 /* get statistics index */
4386 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4387 &veb->stats_idx, NULL, NULL, NULL);
4388 if (ret != I40E_SUCCESS) {
4389 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4390 hw->aq.asq_last_status);
4393 /* Get VEB bandwidth, to be implemented */
4394 /* Now associated vsi binding to the VEB, set uplink to this VEB */
4396 vsi->uplink_seid = veb->seid;
4405 i40e_vsi_release(struct i40e_vsi *vsi)
4409 struct i40e_vsi_list *vsi_list;
4412 struct i40e_mac_filter *f;
4413 uint16_t user_param;
4416 return I40E_SUCCESS;
4421 user_param = vsi->user_param;
4423 pf = I40E_VSI_TO_PF(vsi);
4424 hw = I40E_VSI_TO_HW(vsi);
4426 /* VSI has child to attach, release child first */
4428 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4429 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4432 i40e_veb_release(vsi->veb);
4435 if (vsi->floating_veb) {
4436 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4437 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4442 /* Remove all macvlan filters of the VSI */
4443 i40e_vsi_remove_all_macvlan_filter(vsi);
4444 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4447 if (vsi->type != I40E_VSI_MAIN &&
4448 ((vsi->type != I40E_VSI_SRIOV) ||
4449 !pf->floating_veb_list[user_param])) {
4450 /* Remove vsi from parent's sibling list */
4451 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4452 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4453 return I40E_ERR_PARAM;
4455 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4456 &vsi->sib_vsi_list, list);
4458 /* Remove all switch element of the VSI */
4459 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4460 if (ret != I40E_SUCCESS)
4461 PMD_DRV_LOG(ERR, "Failed to delete element");
4464 if ((vsi->type == I40E_VSI_SRIOV) &&
4465 pf->floating_veb_list[user_param]) {
4466 /* Remove vsi from parent's sibling list */
4467 if (vsi->parent_vsi == NULL ||
4468 vsi->parent_vsi->floating_veb == NULL) {
4469 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4470 return I40E_ERR_PARAM;
4472 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4473 &vsi->sib_vsi_list, list);
4475 /* Remove all switch element of the VSI */
4476 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4477 if (ret != I40E_SUCCESS)
4478 PMD_DRV_LOG(ERR, "Failed to delete element");
4481 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4483 if (vsi->type != I40E_VSI_SRIOV)
4484 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4487 return I40E_SUCCESS;
4491 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4493 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4494 struct i40e_aqc_remove_macvlan_element_data def_filter;
4495 struct i40e_mac_filter_info filter;
4498 if (vsi->type != I40E_VSI_MAIN)
4499 return I40E_ERR_CONFIG;
4500 memset(&def_filter, 0, sizeof(def_filter));
4501 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4503 def_filter.vlan_tag = 0;
4504 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4505 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4506 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4507 if (ret != I40E_SUCCESS) {
4508 struct i40e_mac_filter *f;
4509 struct ether_addr *mac;
4512 "Cannot remove the default macvlan filter");
4513 /* It needs to add the permanent mac into mac list */
4514 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4516 PMD_DRV_LOG(ERR, "failed to allocate memory");
4517 return I40E_ERR_NO_MEMORY;
4519 mac = &f->mac_info.mac_addr;
4520 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4522 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4523 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4528 (void)rte_memcpy(&filter.mac_addr,
4529 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4530 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4531 return i40e_vsi_add_mac(vsi, &filter);
4535 * i40e_vsi_get_bw_config - Query VSI BW Information
4536 * @vsi: the VSI to be queried
4538 * Returns 0 on success, negative value on failure
4540 static enum i40e_status_code
4541 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4543 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4544 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4545 struct i40e_hw *hw = &vsi->adapter->hw;
4550 memset(&bw_config, 0, sizeof(bw_config));
4551 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4552 if (ret != I40E_SUCCESS) {
4553 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4554 hw->aq.asq_last_status);
4558 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4559 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4560 &ets_sla_config, NULL);
4561 if (ret != I40E_SUCCESS) {
4563 "VSI failed to get TC bandwdith configuration %u",
4564 hw->aq.asq_last_status);
4568 /* store and print out BW info */
4569 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4570 vsi->bw_info.bw_max = bw_config.max_bw;
4571 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4572 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4573 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4574 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4576 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4577 vsi->bw_info.bw_ets_share_credits[i] =
4578 ets_sla_config.share_credits[i];
4579 vsi->bw_info.bw_ets_credits[i] =
4580 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4581 /* 4 bits per TC, 4th bit is reserved */
4582 vsi->bw_info.bw_ets_max[i] =
4583 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4584 RTE_LEN2MASK(3, uint8_t));
4585 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4586 vsi->bw_info.bw_ets_share_credits[i]);
4587 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4588 vsi->bw_info.bw_ets_credits[i]);
4589 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4590 vsi->bw_info.bw_ets_max[i]);
4593 return I40E_SUCCESS;
4596 /* i40e_enable_pf_lb
4597 * @pf: pointer to the pf structure
4599 * allow loopback on pf
4602 i40e_enable_pf_lb(struct i40e_pf *pf)
4604 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4605 struct i40e_vsi_context ctxt;
4608 /* Use the FW API if FW >= v5.0 */
4609 if (hw->aq.fw_maj_ver < 5) {
4610 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4614 memset(&ctxt, 0, sizeof(ctxt));
4615 ctxt.seid = pf->main_vsi_seid;
4616 ctxt.pf_num = hw->pf_id;
4617 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4619 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4620 ret, hw->aq.asq_last_status);
4623 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4624 ctxt.info.valid_sections =
4625 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4626 ctxt.info.switch_id |=
4627 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4629 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4631 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4632 hw->aq.asq_last_status);
4637 i40e_vsi_setup(struct i40e_pf *pf,
4638 enum i40e_vsi_type type,
4639 struct i40e_vsi *uplink_vsi,
4640 uint16_t user_param)
4642 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4643 struct i40e_vsi *vsi;
4644 struct i40e_mac_filter_info filter;
4646 struct i40e_vsi_context ctxt;
4647 struct ether_addr broadcast =
4648 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4650 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4651 uplink_vsi == NULL) {
4653 "VSI setup failed, VSI link shouldn't be NULL");
4657 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4659 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4664 * 1.type is not MAIN and uplink vsi is not NULL
4665 * If uplink vsi didn't setup VEB, create one first under veb field
4666 * 2.type is SRIOV and the uplink is NULL
4667 * If floating VEB is NULL, create one veb under floating veb field
4670 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4671 uplink_vsi->veb == NULL) {
4672 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4674 if (uplink_vsi->veb == NULL) {
4675 PMD_DRV_LOG(ERR, "VEB setup failed");
4678 /* set ALLOWLOOPBACk on pf, when veb is created */
4679 i40e_enable_pf_lb(pf);
4682 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4683 pf->main_vsi->floating_veb == NULL) {
4684 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4686 if (pf->main_vsi->floating_veb == NULL) {
4687 PMD_DRV_LOG(ERR, "VEB setup failed");
4692 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4694 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4697 TAILQ_INIT(&vsi->mac_list);
4699 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4700 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4701 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4702 vsi->user_param = user_param;
4703 vsi->vlan_anti_spoof_on = 0;
4704 vsi->vlan_filter_on = 0;
4705 /* Allocate queues */
4706 switch (vsi->type) {
4707 case I40E_VSI_MAIN :
4708 vsi->nb_qps = pf->lan_nb_qps;
4710 case I40E_VSI_SRIOV :
4711 vsi->nb_qps = pf->vf_nb_qps;
4713 case I40E_VSI_VMDQ2:
4714 vsi->nb_qps = pf->vmdq_nb_qps;
4717 vsi->nb_qps = pf->fdir_nb_qps;
4723 * The filter status descriptor is reported in rx queue 0,
4724 * while the tx queue for fdir filter programming has no
4725 * such constraints, can be non-zero queues.
4726 * To simplify it, choose FDIR vsi use queue 0 pair.
4727 * To make sure it will use queue 0 pair, queue allocation
4728 * need be done before this function is called
4730 if (type != I40E_VSI_FDIR) {
4731 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4733 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4737 vsi->base_queue = ret;
4739 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4741 /* VF has MSIX interrupt in VF range, don't allocate here */
4742 if (type == I40E_VSI_MAIN) {
4743 ret = i40e_res_pool_alloc(&pf->msix_pool,
4744 RTE_MIN(vsi->nb_qps,
4745 RTE_MAX_RXTX_INTR_VEC_ID));
4747 PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4749 goto fail_queue_alloc;
4751 vsi->msix_intr = ret;
4752 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4753 } else if (type != I40E_VSI_SRIOV) {
4754 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4756 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4757 goto fail_queue_alloc;
4759 vsi->msix_intr = ret;
4767 if (type == I40E_VSI_MAIN) {
4768 /* For main VSI, no need to add since it's default one */
4769 vsi->uplink_seid = pf->mac_seid;
4770 vsi->seid = pf->main_vsi_seid;
4771 /* Bind queues with specific MSIX interrupt */
4773 * Needs 2 interrupt at least, one for misc cause which will
4774 * enabled from OS side, Another for queues binding the
4775 * interrupt from device side only.
4778 /* Get default VSI parameters from hardware */
4779 memset(&ctxt, 0, sizeof(ctxt));
4780 ctxt.seid = vsi->seid;
4781 ctxt.pf_num = hw->pf_id;
4782 ctxt.uplink_seid = vsi->uplink_seid;
4784 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4785 if (ret != I40E_SUCCESS) {
4786 PMD_DRV_LOG(ERR, "Failed to get VSI params");
4787 goto fail_msix_alloc;
4789 (void)rte_memcpy(&vsi->info, &ctxt.info,
4790 sizeof(struct i40e_aqc_vsi_properties_data));
4791 vsi->vsi_id = ctxt.vsi_number;
4792 vsi->info.valid_sections = 0;
4794 /* Configure tc, enabled TC0 only */
4795 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4797 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4798 goto fail_msix_alloc;
4801 /* TC, queue mapping */
4802 memset(&ctxt, 0, sizeof(ctxt));
4803 vsi->info.valid_sections |=
4804 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4805 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4806 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4807 (void)rte_memcpy(&ctxt.info, &vsi->info,
4808 sizeof(struct i40e_aqc_vsi_properties_data));
4809 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4810 I40E_DEFAULT_TCMAP);
4811 if (ret != I40E_SUCCESS) {
4813 "Failed to configure TC queue mapping");
4814 goto fail_msix_alloc;
4816 ctxt.seid = vsi->seid;
4817 ctxt.pf_num = hw->pf_id;
4818 ctxt.uplink_seid = vsi->uplink_seid;
4821 /* Update VSI parameters */
4822 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4823 if (ret != I40E_SUCCESS) {
4824 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4825 goto fail_msix_alloc;
4828 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4829 sizeof(vsi->info.tc_mapping));
4830 (void)rte_memcpy(&vsi->info.queue_mapping,
4831 &ctxt.info.queue_mapping,
4832 sizeof(vsi->info.queue_mapping));
4833 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4834 vsi->info.valid_sections = 0;
4836 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4840 * Updating default filter settings are necessary to prevent
4841 * reception of tagged packets.
4842 * Some old firmware configurations load a default macvlan
4843 * filter which accepts both tagged and untagged packets.
4844 * The updating is to use a normal filter instead if needed.
4845 * For NVM 4.2.2 or after, the updating is not needed anymore.
4846 * The firmware with correct configurations load the default
4847 * macvlan filter which is expected and cannot be removed.
4849 i40e_update_default_filter_setting(vsi);
4850 i40e_config_qinq(hw, vsi);
4851 } else if (type == I40E_VSI_SRIOV) {
4852 memset(&ctxt, 0, sizeof(ctxt));
4854 * For other VSI, the uplink_seid equals to uplink VSI's
4855 * uplink_seid since they share same VEB
4857 if (uplink_vsi == NULL)
4858 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4860 vsi->uplink_seid = uplink_vsi->uplink_seid;
4861 ctxt.pf_num = hw->pf_id;
4862 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4863 ctxt.uplink_seid = vsi->uplink_seid;
4864 ctxt.connection_type = 0x1;
4865 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4867 /* Use the VEB configuration if FW >= v5.0 */
4868 if (hw->aq.fw_maj_ver >= 5) {
4869 /* Configure switch ID */
4870 ctxt.info.valid_sections |=
4871 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4872 ctxt.info.switch_id =
4873 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4876 /* Configure port/vlan */
4877 ctxt.info.valid_sections |=
4878 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4879 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4880 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4881 hw->func_caps.enabled_tcmap);
4882 if (ret != I40E_SUCCESS) {
4884 "Failed to configure TC queue mapping");
4885 goto fail_msix_alloc;
4888 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
4889 ctxt.info.valid_sections |=
4890 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4892 * Since VSI is not created yet, only configure parameter,
4893 * will add vsi below.
4896 i40e_config_qinq(hw, vsi);
4897 } else if (type == I40E_VSI_VMDQ2) {
4898 memset(&ctxt, 0, sizeof(ctxt));
4900 * For other VSI, the uplink_seid equals to uplink VSI's
4901 * uplink_seid since they share same VEB
4903 vsi->uplink_seid = uplink_vsi->uplink_seid;
4904 ctxt.pf_num = hw->pf_id;
4906 ctxt.uplink_seid = vsi->uplink_seid;
4907 ctxt.connection_type = 0x1;
4908 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4910 ctxt.info.valid_sections |=
4911 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4912 /* user_param carries flag to enable loop back */
4914 ctxt.info.switch_id =
4915 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4916 ctxt.info.switch_id |=
4917 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4920 /* Configure port/vlan */
4921 ctxt.info.valid_sections |=
4922 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4923 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4924 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4925 I40E_DEFAULT_TCMAP);
4926 if (ret != I40E_SUCCESS) {
4928 "Failed to configure TC queue mapping");
4929 goto fail_msix_alloc;
4931 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4932 ctxt.info.valid_sections |=
4933 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4934 } else if (type == I40E_VSI_FDIR) {
4935 memset(&ctxt, 0, sizeof(ctxt));
4936 vsi->uplink_seid = uplink_vsi->uplink_seid;
4937 ctxt.pf_num = hw->pf_id;
4939 ctxt.uplink_seid = vsi->uplink_seid;
4940 ctxt.connection_type = 0x1; /* regular data port */
4941 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4942 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4943 I40E_DEFAULT_TCMAP);
4944 if (ret != I40E_SUCCESS) {
4946 "Failed to configure TC queue mapping.");
4947 goto fail_msix_alloc;
4949 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4950 ctxt.info.valid_sections |=
4951 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4953 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4954 goto fail_msix_alloc;
4957 if (vsi->type != I40E_VSI_MAIN) {
4958 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4959 if (ret != I40E_SUCCESS) {
4960 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4961 hw->aq.asq_last_status);
4962 goto fail_msix_alloc;
4964 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4965 vsi->info.valid_sections = 0;
4966 vsi->seid = ctxt.seid;
4967 vsi->vsi_id = ctxt.vsi_number;
4968 vsi->sib_vsi_list.vsi = vsi;
4969 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4970 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4971 &vsi->sib_vsi_list, list);
4973 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4974 &vsi->sib_vsi_list, list);
4978 /* MAC/VLAN configuration */
4979 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4980 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4982 ret = i40e_vsi_add_mac(vsi, &filter);
4983 if (ret != I40E_SUCCESS) {
4984 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4985 goto fail_msix_alloc;
4988 /* Get VSI BW information */
4989 i40e_vsi_get_bw_config(vsi);
4992 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4994 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5000 /* Configure vlan filter on or off */
5002 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5005 struct i40e_mac_filter *f;
5007 struct i40e_mac_filter_info *mac_filter;
5008 enum rte_mac_filter_type desired_filter;
5009 int ret = I40E_SUCCESS;
5012 /* Filter to match MAC and VLAN */
5013 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5015 /* Filter to match only MAC */
5016 desired_filter = RTE_MAC_PERFECT_MATCH;
5021 mac_filter = rte_zmalloc("mac_filter_info_data",
5022 num * sizeof(*mac_filter), 0);
5023 if (mac_filter == NULL) {
5024 PMD_DRV_LOG(ERR, "failed to allocate memory");
5025 return I40E_ERR_NO_MEMORY;
5030 /* Remove all existing mac */
5031 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5032 mac_filter[i] = f->mac_info;
5033 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5035 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5036 on ? "enable" : "disable");
5042 /* Override with new filter */
5043 for (i = 0; i < num; i++) {
5044 mac_filter[i].filter_type = desired_filter;
5045 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5047 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5048 on ? "enable" : "disable");
5054 rte_free(mac_filter);
5058 /* Configure vlan stripping on or off */
5060 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5062 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5063 struct i40e_vsi_context ctxt;
5065 int ret = I40E_SUCCESS;
5067 /* Check if it has been already on or off */
5068 if (vsi->info.valid_sections &
5069 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5071 if ((vsi->info.port_vlan_flags &
5072 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5073 return 0; /* already on */
5075 if ((vsi->info.port_vlan_flags &
5076 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5077 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5078 return 0; /* already off */
5083 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5085 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5086 vsi->info.valid_sections =
5087 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5088 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5089 vsi->info.port_vlan_flags |= vlan_flags;
5090 ctxt.seid = vsi->seid;
5091 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5092 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5094 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5095 on ? "enable" : "disable");
5101 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5103 struct rte_eth_dev_data *data = dev->data;
5107 /* Apply vlan offload setting */
5108 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5109 i40e_vlan_offload_set(dev, mask);
5111 /* Apply double-vlan setting, not implemented yet */
5113 /* Apply pvid setting */
5114 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5115 data->dev_conf.txmode.hw_vlan_insert_pvid);
5117 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5123 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5125 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5127 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5131 i40e_update_flow_control(struct i40e_hw *hw)
5133 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5134 struct i40e_link_status link_status;
5135 uint32_t rxfc = 0, txfc = 0, reg;
5139 memset(&link_status, 0, sizeof(link_status));
5140 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5141 if (ret != I40E_SUCCESS) {
5142 PMD_DRV_LOG(ERR, "Failed to get link status information");
5143 goto write_reg; /* Disable flow control */
5146 an_info = hw->phy.link_info.an_info;
5147 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5148 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5149 ret = I40E_ERR_NOT_READY;
5150 goto write_reg; /* Disable flow control */
5153 * If link auto negotiation is enabled, flow control needs to
5154 * be configured according to it
5156 switch (an_info & I40E_LINK_PAUSE_RXTX) {
5157 case I40E_LINK_PAUSE_RXTX:
5160 hw->fc.current_mode = I40E_FC_FULL;
5162 case I40E_AQ_LINK_PAUSE_RX:
5164 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5166 case I40E_AQ_LINK_PAUSE_TX:
5168 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5171 hw->fc.current_mode = I40E_FC_NONE;
5176 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5177 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5178 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5179 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5180 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5181 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5188 i40e_pf_setup(struct i40e_pf *pf)
5190 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5191 struct i40e_filter_control_settings settings;
5192 struct i40e_vsi *vsi;
5195 /* Clear all stats counters */
5196 pf->offset_loaded = FALSE;
5197 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5198 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5200 ret = i40e_pf_get_switch_config(pf);
5201 if (ret != I40E_SUCCESS) {
5202 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5205 if (pf->flags & I40E_FLAG_FDIR) {
5206 /* make queue allocated first, let FDIR use queue pair 0*/
5207 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5208 if (ret != I40E_FDIR_QUEUE_ID) {
5210 "queue allocation fails for FDIR: ret =%d",
5212 pf->flags &= ~I40E_FLAG_FDIR;
5215 /* main VSI setup */
5216 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5218 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5219 return I40E_ERR_NOT_READY;
5223 /* Configure filter control */
5224 memset(&settings, 0, sizeof(settings));
5225 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5226 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5227 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5228 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5230 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5231 hw->func_caps.rss_table_size);
5232 return I40E_ERR_PARAM;
5234 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5235 hw->func_caps.rss_table_size);
5236 pf->hash_lut_size = hw->func_caps.rss_table_size;
5238 /* Enable ethtype and macvlan filters */
5239 settings.enable_ethtype = TRUE;
5240 settings.enable_macvlan = TRUE;
5241 ret = i40e_set_filter_control(hw, &settings);
5243 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5246 /* Update flow control according to the auto negotiation */
5247 i40e_update_flow_control(hw);
5249 return I40E_SUCCESS;
5253 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5259 * Set or clear TX Queue Disable flags,
5260 * which is required by hardware.
5262 i40e_pre_tx_queue_cfg(hw, q_idx, on);
5263 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5265 /* Wait until the request is finished */
5266 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5267 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5268 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5269 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5270 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5276 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5277 return I40E_SUCCESS; /* already on, skip next steps */
5279 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5280 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5282 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5283 return I40E_SUCCESS; /* already off, skip next steps */
5284 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5286 /* Write the register */
5287 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5288 /* Check the result */
5289 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5290 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5291 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5293 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5294 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5297 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5298 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5302 /* Check if it is timeout */
5303 if (j >= I40E_CHK_Q_ENA_COUNT) {
5304 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5305 (on ? "enable" : "disable"), q_idx);
5306 return I40E_ERR_TIMEOUT;
5309 return I40E_SUCCESS;
5312 /* Swith on or off the tx queues */
5314 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5316 struct rte_eth_dev_data *dev_data = pf->dev_data;
5317 struct i40e_tx_queue *txq;
5318 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5322 for (i = 0; i < dev_data->nb_tx_queues; i++) {
5323 txq = dev_data->tx_queues[i];
5324 /* Don't operate the queue if not configured or
5325 * if starting only per queue */
5326 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5329 ret = i40e_dev_tx_queue_start(dev, i);
5331 ret = i40e_dev_tx_queue_stop(dev, i);
5332 if ( ret != I40E_SUCCESS)
5336 return I40E_SUCCESS;
5340 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5345 /* Wait until the request is finished */
5346 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5347 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5348 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5349 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5350 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5355 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5356 return I40E_SUCCESS; /* Already on, skip next steps */
5357 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5359 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5360 return I40E_SUCCESS; /* Already off, skip next steps */
5361 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5364 /* Write the register */
5365 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5366 /* Check the result */
5367 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5368 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5369 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5371 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5372 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5375 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5376 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5381 /* Check if it is timeout */
5382 if (j >= I40E_CHK_Q_ENA_COUNT) {
5383 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5384 (on ? "enable" : "disable"), q_idx);
5385 return I40E_ERR_TIMEOUT;
5388 return I40E_SUCCESS;
5390 /* Switch on or off the rx queues */
5392 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5394 struct rte_eth_dev_data *dev_data = pf->dev_data;
5395 struct i40e_rx_queue *rxq;
5396 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5400 for (i = 0; i < dev_data->nb_rx_queues; i++) {
5401 rxq = dev_data->rx_queues[i];
5402 /* Don't operate the queue if not configured or
5403 * if starting only per queue */
5404 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5407 ret = i40e_dev_rx_queue_start(dev, i);
5409 ret = i40e_dev_rx_queue_stop(dev, i);
5410 if (ret != I40E_SUCCESS)
5414 return I40E_SUCCESS;
5417 /* Switch on or off all the rx/tx queues */
5419 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5424 /* enable rx queues before enabling tx queues */
5425 ret = i40e_dev_switch_rx_queues(pf, on);
5427 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5430 ret = i40e_dev_switch_tx_queues(pf, on);
5432 /* Stop tx queues before stopping rx queues */
5433 ret = i40e_dev_switch_tx_queues(pf, on);
5435 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5438 ret = i40e_dev_switch_rx_queues(pf, on);
5444 /* Initialize VSI for TX */
5446 i40e_dev_tx_init(struct i40e_pf *pf)
5448 struct rte_eth_dev_data *data = pf->dev_data;
5450 uint32_t ret = I40E_SUCCESS;
5451 struct i40e_tx_queue *txq;
5453 for (i = 0; i < data->nb_tx_queues; i++) {
5454 txq = data->tx_queues[i];
5455 if (!txq || !txq->q_set)
5457 ret = i40e_tx_queue_init(txq);
5458 if (ret != I40E_SUCCESS)
5461 if (ret == I40E_SUCCESS)
5462 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5468 /* Initialize VSI for RX */
5470 i40e_dev_rx_init(struct i40e_pf *pf)
5472 struct rte_eth_dev_data *data = pf->dev_data;
5473 int ret = I40E_SUCCESS;
5475 struct i40e_rx_queue *rxq;
5477 i40e_pf_config_mq_rx(pf);
5478 for (i = 0; i < data->nb_rx_queues; i++) {
5479 rxq = data->rx_queues[i];
5480 if (!rxq || !rxq->q_set)
5483 ret = i40e_rx_queue_init(rxq);
5484 if (ret != I40E_SUCCESS) {
5486 "Failed to do RX queue initialization");
5490 if (ret == I40E_SUCCESS)
5491 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5498 i40e_dev_rxtx_init(struct i40e_pf *pf)
5502 err = i40e_dev_tx_init(pf);
5504 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5507 err = i40e_dev_rx_init(pf);
5509 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5517 i40e_vmdq_setup(struct rte_eth_dev *dev)
5519 struct rte_eth_conf *conf = &dev->data->dev_conf;
5520 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5521 int i, err, conf_vsis, j, loop;
5522 struct i40e_vsi *vsi;
5523 struct i40e_vmdq_info *vmdq_info;
5524 struct rte_eth_vmdq_rx_conf *vmdq_conf;
5525 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5528 * Disable interrupt to avoid message from VF. Furthermore, it will
5529 * avoid race condition in VSI creation/destroy.
5531 i40e_pf_disable_irq0(hw);
5533 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5534 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5538 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5539 if (conf_vsis > pf->max_nb_vmdq_vsi) {
5540 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5541 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5542 pf->max_nb_vmdq_vsi);
5546 if (pf->vmdq != NULL) {
5547 PMD_INIT_LOG(INFO, "VMDQ already configured");
5551 pf->vmdq = rte_zmalloc("vmdq_info_struct",
5552 sizeof(*vmdq_info) * conf_vsis, 0);
5554 if (pf->vmdq == NULL) {
5555 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5559 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5561 /* Create VMDQ VSI */
5562 for (i = 0; i < conf_vsis; i++) {
5563 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5564 vmdq_conf->enable_loop_back);
5566 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5570 vmdq_info = &pf->vmdq[i];
5572 vmdq_info->vsi = vsi;
5574 pf->nb_cfg_vmdq_vsi = conf_vsis;
5576 /* Configure Vlan */
5577 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5578 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5579 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5580 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5581 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5582 vmdq_conf->pool_map[i].vlan_id, j);
5584 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5585 vmdq_conf->pool_map[i].vlan_id);
5587 PMD_INIT_LOG(ERR, "Failed to add vlan");
5595 i40e_pf_enable_irq0(hw);
5600 for (i = 0; i < conf_vsis; i++)
5601 if (pf->vmdq[i].vsi == NULL)
5604 i40e_vsi_release(pf->vmdq[i].vsi);
5608 i40e_pf_enable_irq0(hw);
5613 i40e_stat_update_32(struct i40e_hw *hw,
5621 new_data = (uint64_t)I40E_READ_REG(hw, reg);
5625 if (new_data >= *offset)
5626 *stat = (uint64_t)(new_data - *offset);
5628 *stat = (uint64_t)((new_data +
5629 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5633 i40e_stat_update_48(struct i40e_hw *hw,
5642 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5643 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5644 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5649 if (new_data >= *offset)
5650 *stat = new_data - *offset;
5652 *stat = (uint64_t)((new_data +
5653 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5655 *stat &= I40E_48_BIT_MASK;
5660 i40e_pf_disable_irq0(struct i40e_hw *hw)
5662 /* Disable all interrupt types */
5663 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5664 I40E_WRITE_FLUSH(hw);
5669 i40e_pf_enable_irq0(struct i40e_hw *hw)
5671 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5672 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5673 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5674 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5675 I40E_WRITE_FLUSH(hw);
5679 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5681 /* read pending request and disable first */
5682 i40e_pf_disable_irq0(hw);
5683 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5684 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5685 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5688 /* Link no queues with irq0 */
5689 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5690 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5694 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5696 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5697 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5700 uint32_t index, offset, val;
5705 * Try to find which VF trigger a reset, use absolute VF id to access
5706 * since the reg is global register.
5708 for (i = 0; i < pf->vf_num; i++) {
5709 abs_vf_id = hw->func_caps.vf_base_id + i;
5710 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5711 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5712 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5713 /* VFR event occured */
5714 if (val & (0x1 << offset)) {
5717 /* Clear the event first */
5718 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5720 PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5722 * Only notify a VF reset event occured,
5723 * don't trigger another SW reset
5725 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5726 if (ret != I40E_SUCCESS)
5727 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5733 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5735 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5738 for (i = 0; i < pf->vf_num; i++)
5739 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
5743 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5745 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5746 struct i40e_arq_event_info info;
5747 uint16_t pending, opcode;
5750 info.buf_len = I40E_AQ_BUF_SZ;
5751 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5752 if (!info.msg_buf) {
5753 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5759 ret = i40e_clean_arq_element(hw, &info, &pending);
5761 if (ret != I40E_SUCCESS) {
5763 "Failed to read msg from AdminQ, aq_err: %u",
5764 hw->aq.asq_last_status);
5767 opcode = rte_le_to_cpu_16(info.desc.opcode);
5770 case i40e_aqc_opc_send_msg_to_pf:
5771 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5772 i40e_pf_host_handle_vf_msg(dev,
5773 rte_le_to_cpu_16(info.desc.retval),
5774 rte_le_to_cpu_32(info.desc.cookie_high),
5775 rte_le_to_cpu_32(info.desc.cookie_low),
5779 case i40e_aqc_opc_get_link_status:
5780 ret = i40e_dev_link_update(dev, 0);
5782 _rte_eth_dev_callback_process(dev,
5783 RTE_ETH_EVENT_INTR_LSC, NULL);
5786 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
5791 rte_free(info.msg_buf);
5795 * Interrupt handler triggered by NIC for handling
5796 * specific interrupt.
5799 * Pointer to interrupt handle.
5801 * The address of parameter (struct rte_eth_dev *) regsitered before.
5807 i40e_dev_interrupt_handler(void *param)
5809 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5810 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5813 /* Disable interrupt */
5814 i40e_pf_disable_irq0(hw);
5816 /* read out interrupt causes */
5817 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5819 /* No interrupt event indicated */
5820 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5821 PMD_DRV_LOG(INFO, "No interrupt event");
5824 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5825 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5826 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5827 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5828 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5829 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5830 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5831 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5832 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5833 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5834 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5835 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5836 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5837 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5839 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5840 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5841 i40e_dev_handle_vfr_event(dev);
5843 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5844 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5845 i40e_dev_handle_aq_msg(dev);
5849 /* Enable interrupt */
5850 i40e_pf_enable_irq0(hw);
5851 rte_intr_enable(dev->intr_handle);
5855 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5856 struct i40e_macvlan_filter *filter,
5859 int ele_num, ele_buff_size;
5860 int num, actual_num, i;
5862 int ret = I40E_SUCCESS;
5863 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5864 struct i40e_aqc_add_macvlan_element_data *req_list;
5866 if (filter == NULL || total == 0)
5867 return I40E_ERR_PARAM;
5868 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5869 ele_buff_size = hw->aq.asq_buf_size;
5871 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5872 if (req_list == NULL) {
5873 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5874 return I40E_ERR_NO_MEMORY;
5879 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5880 memset(req_list, 0, ele_buff_size);
5882 for (i = 0; i < actual_num; i++) {
5883 (void)rte_memcpy(req_list[i].mac_addr,
5884 &filter[num + i].macaddr, ETH_ADDR_LEN);
5885 req_list[i].vlan_tag =
5886 rte_cpu_to_le_16(filter[num + i].vlan_id);
5888 switch (filter[num + i].filter_type) {
5889 case RTE_MAC_PERFECT_MATCH:
5890 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5891 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5893 case RTE_MACVLAN_PERFECT_MATCH:
5894 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5896 case RTE_MAC_HASH_MATCH:
5897 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5898 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5900 case RTE_MACVLAN_HASH_MATCH:
5901 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5904 PMD_DRV_LOG(ERR, "Invalid MAC match type");
5905 ret = I40E_ERR_PARAM;
5909 req_list[i].queue_number = 0;
5911 req_list[i].flags = rte_cpu_to_le_16(flags);
5914 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5916 if (ret != I40E_SUCCESS) {
5917 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5921 } while (num < total);
5929 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5930 struct i40e_macvlan_filter *filter,
5933 int ele_num, ele_buff_size;
5934 int num, actual_num, i;
5936 int ret = I40E_SUCCESS;
5937 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5938 struct i40e_aqc_remove_macvlan_element_data *req_list;
5940 if (filter == NULL || total == 0)
5941 return I40E_ERR_PARAM;
5943 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5944 ele_buff_size = hw->aq.asq_buf_size;
5946 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5947 if (req_list == NULL) {
5948 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5949 return I40E_ERR_NO_MEMORY;
5954 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5955 memset(req_list, 0, ele_buff_size);
5957 for (i = 0; i < actual_num; i++) {
5958 (void)rte_memcpy(req_list[i].mac_addr,
5959 &filter[num + i].macaddr, ETH_ADDR_LEN);
5960 req_list[i].vlan_tag =
5961 rte_cpu_to_le_16(filter[num + i].vlan_id);
5963 switch (filter[num + i].filter_type) {
5964 case RTE_MAC_PERFECT_MATCH:
5965 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5966 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5968 case RTE_MACVLAN_PERFECT_MATCH:
5969 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5971 case RTE_MAC_HASH_MATCH:
5972 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5973 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5975 case RTE_MACVLAN_HASH_MATCH:
5976 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5979 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
5980 ret = I40E_ERR_PARAM;
5983 req_list[i].flags = rte_cpu_to_le_16(flags);
5986 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5988 if (ret != I40E_SUCCESS) {
5989 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5993 } while (num < total);
6000 /* Find out specific MAC filter */
6001 static struct i40e_mac_filter *
6002 i40e_find_mac_filter(struct i40e_vsi *vsi,
6003 struct ether_addr *macaddr)
6005 struct i40e_mac_filter *f;
6007 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6008 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6016 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6019 uint32_t vid_idx, vid_bit;
6021 if (vlan_id > ETH_VLAN_ID_MAX)
6024 vid_idx = I40E_VFTA_IDX(vlan_id);
6025 vid_bit = I40E_VFTA_BIT(vlan_id);
6027 if (vsi->vfta[vid_idx] & vid_bit)
6034 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6035 uint16_t vlan_id, bool on)
6037 uint32_t vid_idx, vid_bit;
6039 vid_idx = I40E_VFTA_IDX(vlan_id);
6040 vid_bit = I40E_VFTA_BIT(vlan_id);
6043 vsi->vfta[vid_idx] |= vid_bit;
6045 vsi->vfta[vid_idx] &= ~vid_bit;
6049 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6050 uint16_t vlan_id, bool on)
6052 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6053 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6056 if (vlan_id > ETH_VLAN_ID_MAX)
6059 i40e_store_vlan_filter(vsi, vlan_id, on);
6061 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6064 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6067 ret = i40e_aq_add_vlan(hw, vsi->seid,
6068 &vlan_data, 1, NULL);
6069 if (ret != I40E_SUCCESS)
6070 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6072 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6073 &vlan_data, 1, NULL);
6074 if (ret != I40E_SUCCESS)
6076 "Failed to remove vlan filter");
6081 * Find all vlan options for specific mac addr,
6082 * return with actual vlan found.
6085 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6086 struct i40e_macvlan_filter *mv_f,
6087 int num, struct ether_addr *addr)
6093 * Not to use i40e_find_vlan_filter to decrease the loop time,
6094 * although the code looks complex.
6096 if (num < vsi->vlan_num)
6097 return I40E_ERR_PARAM;
6100 for (j = 0; j < I40E_VFTA_SIZE; j++) {
6102 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6103 if (vsi->vfta[j] & (1 << k)) {
6106 "vlan number doesn't match");
6107 return I40E_ERR_PARAM;
6109 (void)rte_memcpy(&mv_f[i].macaddr,
6110 addr, ETH_ADDR_LEN);
6112 j * I40E_UINT32_BIT_SIZE + k;
6118 return I40E_SUCCESS;
6122 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6123 struct i40e_macvlan_filter *mv_f,
6128 struct i40e_mac_filter *f;
6130 if (num < vsi->mac_num)
6131 return I40E_ERR_PARAM;
6133 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6135 PMD_DRV_LOG(ERR, "buffer number not match");
6136 return I40E_ERR_PARAM;
6138 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6140 mv_f[i].vlan_id = vlan;
6141 mv_f[i].filter_type = f->mac_info.filter_type;
6145 return I40E_SUCCESS;
6149 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6152 struct i40e_mac_filter *f;
6153 struct i40e_macvlan_filter *mv_f;
6154 int ret = I40E_SUCCESS;
6156 if (vsi == NULL || vsi->mac_num == 0)
6157 return I40E_ERR_PARAM;
6159 /* Case that no vlan is set */
6160 if (vsi->vlan_num == 0)
6163 num = vsi->mac_num * vsi->vlan_num;
6165 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6167 PMD_DRV_LOG(ERR, "failed to allocate memory");
6168 return I40E_ERR_NO_MEMORY;
6172 if (vsi->vlan_num == 0) {
6173 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6174 (void)rte_memcpy(&mv_f[i].macaddr,
6175 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6176 mv_f[i].filter_type = f->mac_info.filter_type;
6177 mv_f[i].vlan_id = 0;
6181 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6182 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6183 vsi->vlan_num, &f->mac_info.mac_addr);
6184 if (ret != I40E_SUCCESS)
6186 for (j = i; j < i + vsi->vlan_num; j++)
6187 mv_f[j].filter_type = f->mac_info.filter_type;
6192 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6200 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6202 struct i40e_macvlan_filter *mv_f;
6204 int ret = I40E_SUCCESS;
6206 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6207 return I40E_ERR_PARAM;
6209 /* If it's already set, just return */
6210 if (i40e_find_vlan_filter(vsi,vlan))
6211 return I40E_SUCCESS;
6213 mac_num = vsi->mac_num;
6216 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6217 return I40E_ERR_PARAM;
6220 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6223 PMD_DRV_LOG(ERR, "failed to allocate memory");
6224 return I40E_ERR_NO_MEMORY;
6227 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6229 if (ret != I40E_SUCCESS)
6232 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6234 if (ret != I40E_SUCCESS)
6237 i40e_set_vlan_filter(vsi, vlan, 1);
6247 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6249 struct i40e_macvlan_filter *mv_f;
6251 int ret = I40E_SUCCESS;
6254 * Vlan 0 is the generic filter for untagged packets
6255 * and can't be removed.
6257 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6258 return I40E_ERR_PARAM;
6260 /* If can't find it, just return */
6261 if (!i40e_find_vlan_filter(vsi, vlan))
6262 return I40E_ERR_PARAM;
6264 mac_num = vsi->mac_num;
6267 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6268 return I40E_ERR_PARAM;
6271 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6274 PMD_DRV_LOG(ERR, "failed to allocate memory");
6275 return I40E_ERR_NO_MEMORY;
6278 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6280 if (ret != I40E_SUCCESS)
6283 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6285 if (ret != I40E_SUCCESS)
6288 /* This is last vlan to remove, replace all mac filter with vlan 0 */
6289 if (vsi->vlan_num == 1) {
6290 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6291 if (ret != I40E_SUCCESS)
6294 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6295 if (ret != I40E_SUCCESS)
6299 i40e_set_vlan_filter(vsi, vlan, 0);
6309 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6311 struct i40e_mac_filter *f;
6312 struct i40e_macvlan_filter *mv_f;
6313 int i, vlan_num = 0;
6314 int ret = I40E_SUCCESS;
6316 /* If it's add and we've config it, return */
6317 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6319 return I40E_SUCCESS;
6320 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6321 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6324 * If vlan_num is 0, that's the first time to add mac,
6325 * set mask for vlan_id 0.
6327 if (vsi->vlan_num == 0) {
6328 i40e_set_vlan_filter(vsi, 0, 1);
6331 vlan_num = vsi->vlan_num;
6332 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6333 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6336 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6338 PMD_DRV_LOG(ERR, "failed to allocate memory");
6339 return I40E_ERR_NO_MEMORY;
6342 for (i = 0; i < vlan_num; i++) {
6343 mv_f[i].filter_type = mac_filter->filter_type;
6344 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6348 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6349 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6350 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6351 &mac_filter->mac_addr);
6352 if (ret != I40E_SUCCESS)
6356 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6357 if (ret != I40E_SUCCESS)
6360 /* Add the mac addr into mac list */
6361 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6363 PMD_DRV_LOG(ERR, "failed to allocate memory");
6364 ret = I40E_ERR_NO_MEMORY;
6367 (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6369 f->mac_info.filter_type = mac_filter->filter_type;
6370 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6381 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6383 struct i40e_mac_filter *f;
6384 struct i40e_macvlan_filter *mv_f;
6386 enum rte_mac_filter_type filter_type;
6387 int ret = I40E_SUCCESS;
6389 /* Can't find it, return an error */
6390 f = i40e_find_mac_filter(vsi, addr);
6392 return I40E_ERR_PARAM;
6394 vlan_num = vsi->vlan_num;
6395 filter_type = f->mac_info.filter_type;
6396 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6397 filter_type == RTE_MACVLAN_HASH_MATCH) {
6398 if (vlan_num == 0) {
6399 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6400 return I40E_ERR_PARAM;
6402 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6403 filter_type == RTE_MAC_HASH_MATCH)
6406 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6408 PMD_DRV_LOG(ERR, "failed to allocate memory");
6409 return I40E_ERR_NO_MEMORY;
6412 for (i = 0; i < vlan_num; i++) {
6413 mv_f[i].filter_type = filter_type;
6414 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6417 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6418 filter_type == RTE_MACVLAN_HASH_MATCH) {
6419 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6420 if (ret != I40E_SUCCESS)
6424 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6425 if (ret != I40E_SUCCESS)
6428 /* Remove the mac addr into mac list */
6429 TAILQ_REMOVE(&vsi->mac_list, f, next);
6439 /* Configure hash enable flags for RSS */
6441 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6448 if (flags & ETH_RSS_FRAG_IPV4)
6449 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6450 if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6451 if (type == I40E_MAC_X722) {
6452 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6453 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6455 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6457 if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6458 if (type == I40E_MAC_X722) {
6459 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6460 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6461 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6463 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6465 if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6466 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6467 if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6468 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6469 if (flags & ETH_RSS_FRAG_IPV6)
6470 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6471 if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6472 if (type == I40E_MAC_X722) {
6473 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6474 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6476 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6478 if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6479 if (type == I40E_MAC_X722) {
6480 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6481 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6482 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6484 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6486 if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6487 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6488 if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6489 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6490 if (flags & ETH_RSS_L2_PAYLOAD)
6491 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6496 /* Parse the hash enable flags */
6498 i40e_parse_hena(uint64_t flags)
6500 uint64_t rss_hf = 0;
6504 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6505 rss_hf |= ETH_RSS_FRAG_IPV4;
6506 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6507 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6508 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6509 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6510 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6511 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6512 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6513 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6514 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6515 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6516 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6517 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6518 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6519 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6520 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6521 rss_hf |= ETH_RSS_FRAG_IPV6;
6522 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6523 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6524 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6525 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6526 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6527 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6528 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6529 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6530 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6531 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6532 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6533 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6534 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6535 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6536 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6537 rss_hf |= ETH_RSS_L2_PAYLOAD;
6544 i40e_pf_disable_rss(struct i40e_pf *pf)
6546 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6549 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6550 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6551 if (hw->mac.type == I40E_MAC_X722)
6552 hena &= ~I40E_RSS_HENA_ALL_X722;
6554 hena &= ~I40E_RSS_HENA_ALL;
6555 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6556 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6557 I40E_WRITE_FLUSH(hw);
6561 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6563 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6564 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6567 if (!key || key_len == 0) {
6568 PMD_DRV_LOG(DEBUG, "No key to be configured");
6570 } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6572 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6576 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6577 struct i40e_aqc_get_set_rss_key_data *key_dw =
6578 (struct i40e_aqc_get_set_rss_key_data *)key;
6580 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6582 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6584 uint32_t *hash_key = (uint32_t *)key;
6587 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6588 i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6589 I40E_WRITE_FLUSH(hw);
6596 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6598 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6599 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6602 if (!key || !key_len)
6605 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6606 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6607 (struct i40e_aqc_get_set_rss_key_data *)key);
6609 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6613 uint32_t *key_dw = (uint32_t *)key;
6616 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6617 key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6619 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6625 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6627 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6632 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6633 rss_conf->rss_key_len);
6637 rss_hf = rss_conf->rss_hf;
6638 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6639 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6640 if (hw->mac.type == I40E_MAC_X722)
6641 hena &= ~I40E_RSS_HENA_ALL_X722;
6643 hena &= ~I40E_RSS_HENA_ALL;
6644 hena |= i40e_config_hena(rss_hf, hw->mac.type);
6645 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6646 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6647 I40E_WRITE_FLUSH(hw);
6653 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6654 struct rte_eth_rss_conf *rss_conf)
6656 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6657 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6658 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6661 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6662 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6663 if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6664 ? I40E_RSS_HENA_ALL_X722
6665 : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6666 if (rss_hf != 0) /* Enable RSS */
6668 return 0; /* Nothing to do */
6671 if (rss_hf == 0) /* Disable RSS */
6674 return i40e_hw_rss_hash_set(pf, rss_conf);
6678 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6679 struct rte_eth_rss_conf *rss_conf)
6681 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6682 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6685 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6686 &rss_conf->rss_key_len);
6688 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6689 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6690 rss_conf->rss_hf = i40e_parse_hena(hena);
6696 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6698 switch (filter_type) {
6699 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6700 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6702 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6703 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6705 case RTE_TUNNEL_FILTER_IMAC_TENID:
6706 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6708 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6709 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6711 case ETH_TUNNEL_FILTER_IMAC:
6712 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6714 case ETH_TUNNEL_FILTER_OIP:
6715 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6717 case ETH_TUNNEL_FILTER_IIP:
6718 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6721 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6728 /* Convert tunnel filter structure */
6730 i40e_tunnel_filter_convert(
6731 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
6732 struct i40e_tunnel_filter *tunnel_filter)
6734 ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
6735 (struct ether_addr *)&tunnel_filter->input.outer_mac);
6736 ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
6737 (struct ether_addr *)&tunnel_filter->input.inner_mac);
6738 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
6739 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
6740 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6741 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6742 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6744 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6745 tunnel_filter->input.flags = cld_filter->element.flags;
6746 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
6747 tunnel_filter->queue = cld_filter->element.queue_number;
6748 rte_memcpy(tunnel_filter->input.general_fields,
6749 cld_filter->general_fields,
6750 sizeof(cld_filter->general_fields));
6755 /* Check if there exists the tunnel filter */
6756 struct i40e_tunnel_filter *
6757 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6758 const struct i40e_tunnel_filter_input *input)
6762 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6766 return tunnel_rule->hash_map[ret];
6769 /* Add a tunnel filter into the SW list */
6771 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6772 struct i40e_tunnel_filter *tunnel_filter)
6774 struct i40e_tunnel_rule *rule = &pf->tunnel;
6777 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6780 "Failed to insert tunnel filter to hash table %d!",
6784 rule->hash_map[ret] = tunnel_filter;
6786 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6791 /* Delete a tunnel filter from the SW list */
6793 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6794 struct i40e_tunnel_filter_input *input)
6796 struct i40e_tunnel_rule *rule = &pf->tunnel;
6797 struct i40e_tunnel_filter *tunnel_filter;
6800 ret = rte_hash_del_key(rule->hash_table, input);
6803 "Failed to delete tunnel filter to hash table %d!",
6807 tunnel_filter = rule->hash_map[ret];
6808 rule->hash_map[ret] = NULL;
6810 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6811 rte_free(tunnel_filter);
6817 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6818 struct rte_eth_tunnel_filter_conf *tunnel_filter,
6823 uint8_t i, tun_type = 0;
6824 /* internal varialbe to convert ipv6 byte order */
6825 uint32_t convert_ipv6[4];
6827 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6828 struct i40e_vsi *vsi = pf->main_vsi;
6829 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
6830 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
6831 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6832 struct i40e_tunnel_filter *tunnel, *node;
6833 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6835 cld_filter = rte_zmalloc("tunnel_filter",
6836 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
6839 if (NULL == cld_filter) {
6840 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6843 pfilter = cld_filter;
6845 ether_addr_copy(&tunnel_filter->outer_mac,
6846 (struct ether_addr *)&pfilter->element.outer_mac);
6847 ether_addr_copy(&tunnel_filter->inner_mac,
6848 (struct ether_addr *)&pfilter->element.inner_mac);
6850 pfilter->element.inner_vlan =
6851 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6852 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6853 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6854 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6855 rte_memcpy(&pfilter->element.ipaddr.v4.data,
6856 &rte_cpu_to_le_32(ipv4_addr),
6857 sizeof(pfilter->element.ipaddr.v4.data));
6859 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6860 for (i = 0; i < 4; i++) {
6862 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6864 rte_memcpy(&pfilter->element.ipaddr.v6.data,
6866 sizeof(pfilter->element.ipaddr.v6.data));
6869 /* check tunneled type */
6870 switch (tunnel_filter->tunnel_type) {
6871 case RTE_TUNNEL_TYPE_VXLAN:
6872 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6874 case RTE_TUNNEL_TYPE_NVGRE:
6875 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6877 case RTE_TUNNEL_TYPE_IP_IN_GRE:
6878 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6881 /* Other tunnel types is not supported. */
6882 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6883 rte_free(cld_filter);
6887 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6888 &pfilter->element.flags);
6890 rte_free(cld_filter);
6894 pfilter->element.flags |= rte_cpu_to_le_16(
6895 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6896 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6897 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6898 pfilter->element.queue_number =
6899 rte_cpu_to_le_16(tunnel_filter->queue_id);
6901 /* Check if there is the filter in SW list */
6902 memset(&check_filter, 0, sizeof(check_filter));
6903 i40e_tunnel_filter_convert(cld_filter, &check_filter);
6904 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
6906 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
6910 if (!add && !node) {
6911 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
6916 ret = i40e_aq_add_cloud_filters(hw,
6917 vsi->seid, &cld_filter->element, 1);
6919 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
6922 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
6923 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
6924 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
6926 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6927 &cld_filter->element, 1);
6929 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
6932 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
6935 rte_free(cld_filter);
6939 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
6940 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
6941 #define I40E_TR_GENEVE_KEY_MASK 0x8
6942 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
6943 #define I40E_TR_GRE_KEY_MASK 0x400
6944 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
6945 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
6948 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
6950 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
6951 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
6952 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6953 enum i40e_status_code status = I40E_SUCCESS;
6955 memset(&filter_replace, 0,
6956 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
6957 memset(&filter_replace_buf, 0,
6958 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
6960 /* create L1 filter */
6961 filter_replace.old_filter_type =
6962 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
6963 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
6964 filter_replace.tr_bit = 0;
6966 /* Prepare the buffer, 3 entries */
6967 filter_replace_buf.data[0] =
6968 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
6969 filter_replace_buf.data[0] |=
6970 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
6971 filter_replace_buf.data[2] = 0xFF;
6972 filter_replace_buf.data[3] = 0xFF;
6973 filter_replace_buf.data[4] =
6974 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
6975 filter_replace_buf.data[4] |=
6976 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
6977 filter_replace_buf.data[7] = 0xF0;
6978 filter_replace_buf.data[8]
6979 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
6980 filter_replace_buf.data[8] |=
6981 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
6982 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
6983 I40E_TR_GENEVE_KEY_MASK |
6984 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
6985 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
6986 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
6987 I40E_TR_GRE_NO_KEY_MASK) >> 8;
6989 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
6990 &filter_replace_buf);
6995 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
6997 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
6998 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
6999 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7000 enum i40e_status_code status = I40E_SUCCESS;
7003 memset(&filter_replace, 0,
7004 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7005 memset(&filter_replace_buf, 0,
7006 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7007 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7008 I40E_AQC_MIRROR_CLOUD_FILTER;
7009 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7010 filter_replace.new_filter_type =
7011 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7012 /* Prepare the buffer, 2 entries */
7013 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7014 filter_replace_buf.data[0] |=
7015 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7016 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7017 filter_replace_buf.data[4] |=
7018 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7019 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7020 &filter_replace_buf);
7025 memset(&filter_replace, 0,
7026 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7027 memset(&filter_replace_buf, 0,
7028 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7030 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7031 I40E_AQC_MIRROR_CLOUD_FILTER;
7032 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7033 filter_replace.new_filter_type =
7034 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7035 /* Prepare the buffer, 2 entries */
7036 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7037 filter_replace_buf.data[0] |=
7038 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7039 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7040 filter_replace_buf.data[4] |=
7041 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7043 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7044 &filter_replace_buf);
7049 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7050 struct i40e_tunnel_filter_conf *tunnel_filter,
7055 uint8_t i, tun_type = 0;
7056 /* internal variable to convert ipv6 byte order */
7057 uint32_t convert_ipv6[4];
7059 struct i40e_pf_vf *vf = NULL;
7060 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7061 struct i40e_vsi *vsi;
7062 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7063 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7064 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7065 struct i40e_tunnel_filter *tunnel, *node;
7066 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7068 bool big_buffer = 0;
7070 cld_filter = rte_zmalloc("tunnel_filter",
7071 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7074 if (cld_filter == NULL) {
7075 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7078 pfilter = cld_filter;
7080 ether_addr_copy(&tunnel_filter->outer_mac,
7081 (struct ether_addr *)&pfilter->element.outer_mac);
7082 ether_addr_copy(&tunnel_filter->inner_mac,
7083 (struct ether_addr *)&pfilter->element.inner_mac);
7085 pfilter->element.inner_vlan =
7086 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7087 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7088 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7089 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7090 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7091 &rte_cpu_to_le_32(ipv4_addr),
7092 sizeof(pfilter->element.ipaddr.v4.data));
7094 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7095 for (i = 0; i < 4; i++) {
7097 rte_cpu_to_le_32(rte_be_to_cpu_32(
7098 tunnel_filter->ip_addr.ipv6_addr[i]));
7100 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7102 sizeof(pfilter->element.ipaddr.v6.data));
7105 /* check tunneled type */
7106 switch (tunnel_filter->tunnel_type) {
7107 case I40E_TUNNEL_TYPE_VXLAN:
7108 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7110 case I40E_TUNNEL_TYPE_NVGRE:
7111 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7113 case I40E_TUNNEL_TYPE_IP_IN_GRE:
7114 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7116 case I40E_TUNNEL_TYPE_MPLSoUDP:
7117 if (!pf->mpls_replace_flag) {
7118 i40e_replace_mpls_l1_filter(pf);
7119 i40e_replace_mpls_cloud_filter(pf);
7120 pf->mpls_replace_flag = 1;
7122 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7123 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7125 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7126 (teid_le & 0xF) << 12;
7127 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7130 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoUDP;
7132 case I40E_TUNNEL_TYPE_MPLSoGRE:
7133 if (!pf->mpls_replace_flag) {
7134 i40e_replace_mpls_l1_filter(pf);
7135 i40e_replace_mpls_cloud_filter(pf);
7136 pf->mpls_replace_flag = 1;
7138 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7139 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7141 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7142 (teid_le & 0xF) << 12;
7143 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7146 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoGRE;
7148 case I40E_TUNNEL_TYPE_QINQ:
7149 if (!pf->qinq_replace_flag) {
7150 ret = i40e_cloud_filter_qinq_create(pf);
7153 "QinQ tunnel filter already created.");
7154 pf->qinq_replace_flag = 1;
7156 /* Add in the General fields the values of
7157 * the Outer and Inner VLAN
7158 * Big Buffer should be set, see changes in
7159 * i40e_aq_add_cloud_filters
7161 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7162 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7166 /* Other tunnel types is not supported. */
7167 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7168 rte_free(cld_filter);
7172 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7173 pfilter->element.flags =
7174 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7175 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7176 pfilter->element.flags =
7177 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7178 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7179 pfilter->element.flags |=
7180 I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
7182 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7183 &pfilter->element.flags);
7185 rte_free(cld_filter);
7190 pfilter->element.flags |= rte_cpu_to_le_16(
7191 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7192 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7193 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7194 pfilter->element.queue_number =
7195 rte_cpu_to_le_16(tunnel_filter->queue_id);
7197 if (!tunnel_filter->is_to_vf)
7200 if (tunnel_filter->vf_id >= pf->vf_num) {
7201 PMD_DRV_LOG(ERR, "Invalid argument.");
7204 vf = &pf->vfs[tunnel_filter->vf_id];
7208 /* Check if there is the filter in SW list */
7209 memset(&check_filter, 0, sizeof(check_filter));
7210 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7211 check_filter.is_to_vf = tunnel_filter->is_to_vf;
7212 check_filter.vf_id = tunnel_filter->vf_id;
7213 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7215 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7219 if (!add && !node) {
7220 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7226 ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7227 vsi->seid, cld_filter, 1);
7229 ret = i40e_aq_add_cloud_filters(hw,
7230 vsi->seid, &cld_filter->element, 1);
7232 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7235 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7236 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7237 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7240 ret = i40e_aq_remove_cloud_filters_big_buffer(
7241 hw, vsi->seid, cld_filter, 1);
7243 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7244 &cld_filter->element, 1);
7246 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7249 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7252 rte_free(cld_filter);
7257 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7261 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7262 if (pf->vxlan_ports[i] == port)
7270 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7274 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7276 idx = i40e_get_vxlan_port_idx(pf, port);
7278 /* Check if port already exists */
7280 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7284 /* Now check if there is space to add the new port */
7285 idx = i40e_get_vxlan_port_idx(pf, 0);
7288 "Maximum number of UDP ports reached, not adding port %d",
7293 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7296 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7300 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7303 /* New port: add it and mark its index in the bitmap */
7304 pf->vxlan_ports[idx] = port;
7305 pf->vxlan_bitmap |= (1 << idx);
7307 if (!(pf->flags & I40E_FLAG_VXLAN))
7308 pf->flags |= I40E_FLAG_VXLAN;
7314 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7317 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7319 if (!(pf->flags & I40E_FLAG_VXLAN)) {
7320 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7324 idx = i40e_get_vxlan_port_idx(pf, port);
7327 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7331 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7332 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7336 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7339 pf->vxlan_ports[idx] = 0;
7340 pf->vxlan_bitmap &= ~(1 << idx);
7342 if (!pf->vxlan_bitmap)
7343 pf->flags &= ~I40E_FLAG_VXLAN;
7348 /* Add UDP tunneling port */
7350 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7351 struct rte_eth_udp_tunnel *udp_tunnel)
7354 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7356 if (udp_tunnel == NULL)
7359 switch (udp_tunnel->prot_type) {
7360 case RTE_TUNNEL_TYPE_VXLAN:
7361 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7364 case RTE_TUNNEL_TYPE_GENEVE:
7365 case RTE_TUNNEL_TYPE_TEREDO:
7366 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7371 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7379 /* Remove UDP tunneling port */
7381 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7382 struct rte_eth_udp_tunnel *udp_tunnel)
7385 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7387 if (udp_tunnel == NULL)
7390 switch (udp_tunnel->prot_type) {
7391 case RTE_TUNNEL_TYPE_VXLAN:
7392 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7394 case RTE_TUNNEL_TYPE_GENEVE:
7395 case RTE_TUNNEL_TYPE_TEREDO:
7396 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7400 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7408 /* Calculate the maximum number of contiguous PF queues that are configured */
7410 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7412 struct rte_eth_dev_data *data = pf->dev_data;
7414 struct i40e_rx_queue *rxq;
7417 for (i = 0; i < pf->lan_nb_qps; i++) {
7418 rxq = data->rx_queues[i];
7419 if (rxq && rxq->q_set)
7430 i40e_pf_config_rss(struct i40e_pf *pf)
7432 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7433 struct rte_eth_rss_conf rss_conf;
7434 uint32_t i, lut = 0;
7438 * If both VMDQ and RSS enabled, not all of PF queues are configured.
7439 * It's necessary to calulate the actual PF queues that are configured.
7441 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7442 num = i40e_pf_calc_configured_queues_num(pf);
7444 num = pf->dev_data->nb_rx_queues;
7446 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7447 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7451 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7455 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7458 lut = (lut << 8) | (j & ((0x1 <<
7459 hw->func_caps.rss_table_entry_width) - 1));
7461 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7464 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7465 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
7466 i40e_pf_disable_rss(pf);
7469 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7470 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7471 /* Random default keys */
7472 static uint32_t rss_key_default[] = {0x6b793944,
7473 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7474 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7475 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7477 rss_conf.rss_key = (uint8_t *)rss_key_default;
7478 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7482 return i40e_hw_rss_hash_set(pf, &rss_conf);
7486 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7487 struct rte_eth_tunnel_filter_conf *filter)
7489 if (pf == NULL || filter == NULL) {
7490 PMD_DRV_LOG(ERR, "Invalid parameter");
7494 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7495 PMD_DRV_LOG(ERR, "Invalid queue ID");
7499 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7500 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7504 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7505 (is_zero_ether_addr(&filter->outer_mac))) {
7506 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7510 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7511 (is_zero_ether_addr(&filter->inner_mac))) {
7512 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7519 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7520 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
7522 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7527 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7528 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7531 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7532 } else if (len == 4) {
7533 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7535 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7540 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7547 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7548 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7554 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7561 switch (cfg->cfg_type) {
7562 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7563 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7566 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7574 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7575 enum rte_filter_op filter_op,
7578 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7579 int ret = I40E_ERR_PARAM;
7581 switch (filter_op) {
7582 case RTE_ETH_FILTER_SET:
7583 ret = i40e_dev_global_config_set(hw,
7584 (struct rte_eth_global_cfg *)arg);
7587 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7595 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7596 enum rte_filter_op filter_op,
7599 struct rte_eth_tunnel_filter_conf *filter;
7600 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7601 int ret = I40E_SUCCESS;
7603 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7605 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7606 return I40E_ERR_PARAM;
7608 switch (filter_op) {
7609 case RTE_ETH_FILTER_NOP:
7610 if (!(pf->flags & I40E_FLAG_VXLAN))
7611 ret = I40E_NOT_SUPPORTED;
7613 case RTE_ETH_FILTER_ADD:
7614 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7616 case RTE_ETH_FILTER_DELETE:
7617 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7620 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7621 ret = I40E_ERR_PARAM;
7629 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7632 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7635 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7636 ret = i40e_pf_config_rss(pf);
7638 i40e_pf_disable_rss(pf);
7643 /* Get the symmetric hash enable configurations per port */
7645 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7647 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7649 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7652 /* Set the symmetric hash enable configurations per port */
7654 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7656 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7659 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7661 "Symmetric hash has already been enabled");
7664 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7666 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7668 "Symmetric hash has already been disabled");
7671 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7673 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7674 I40E_WRITE_FLUSH(hw);
7678 * Get global configurations of hash function type and symmetric hash enable
7679 * per flow type (pctype). Note that global configuration means it affects all
7680 * the ports on the same NIC.
7683 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7684 struct rte_eth_hash_global_conf *g_cfg)
7686 uint32_t reg, mask = I40E_FLOW_TYPES;
7688 enum i40e_filter_pctype pctype;
7690 memset(g_cfg, 0, sizeof(*g_cfg));
7691 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7692 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7693 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7695 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7696 PMD_DRV_LOG(DEBUG, "Hash function is %s",
7697 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7699 for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7700 if (!(mask & (1UL << i)))
7702 mask &= ~(1UL << i);
7703 /* Bit set indicats the coresponding flow type is supported */
7704 g_cfg->valid_bit_mask[0] |= (1UL << i);
7705 /* if flowtype is invalid, continue */
7706 if (!I40E_VALID_FLOW(i))
7708 pctype = i40e_flowtype_to_pctype(i);
7709 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7710 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7711 g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7718 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7721 uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7723 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7724 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7725 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7726 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7732 * As i40e supports less than 32 flow types, only first 32 bits need to
7735 mask0 = g_cfg->valid_bit_mask[0];
7736 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7738 /* Check if any unsupported flow type configured */
7739 if ((mask0 | i40e_mask) ^ i40e_mask)
7742 if (g_cfg->valid_bit_mask[i])
7750 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7756 * Set global configurations of hash function type and symmetric hash enable
7757 * per flow type (pctype). Note any modifying global configuration will affect
7758 * all the ports on the same NIC.
7761 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7762 struct rte_eth_hash_global_conf *g_cfg)
7767 uint32_t mask0 = g_cfg->valid_bit_mask[0];
7768 enum i40e_filter_pctype pctype;
7770 /* Check the input parameters */
7771 ret = i40e_hash_global_config_check(g_cfg);
7775 for (i = 0; mask0 && i < UINT32_BIT; i++) {
7776 if (!(mask0 & (1UL << i)))
7778 mask0 &= ~(1UL << i);
7779 /* if flowtype is invalid, continue */
7780 if (!I40E_VALID_FLOW(i))
7782 pctype = i40e_flowtype_to_pctype(i);
7783 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7784 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7785 if (hw->mac.type == I40E_MAC_X722) {
7786 if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_UDP) {
7787 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7788 I40E_FILTER_PCTYPE_NONF_IPV4_UDP), reg);
7789 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7790 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP),
7792 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7793 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP),
7795 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_TCP) {
7796 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7797 I40E_FILTER_PCTYPE_NONF_IPV4_TCP), reg);
7798 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7799 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK),
7801 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_UDP) {
7802 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7803 I40E_FILTER_PCTYPE_NONF_IPV6_UDP), reg);
7804 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7805 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP),
7807 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7808 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP),
7810 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_TCP) {
7811 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7812 I40E_FILTER_PCTYPE_NONF_IPV6_TCP), reg);
7813 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7814 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK),
7817 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype),
7821 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7825 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7826 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7828 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7830 "Hash function already set to Toeplitz");
7833 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7834 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7836 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7838 "Hash function already set to Simple XOR");
7841 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7843 /* Use the default, and keep it as it is */
7846 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7849 I40E_WRITE_FLUSH(hw);
7855 * Valid input sets for hash and flow director filters per PCTYPE
7858 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7859 enum rte_filter_type filter)
7863 static const uint64_t valid_hash_inset_table[] = {
7864 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7865 I40E_INSET_DMAC | I40E_INSET_SMAC |
7866 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7867 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7868 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7869 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7870 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7871 I40E_INSET_FLEX_PAYLOAD,
7872 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7873 I40E_INSET_DMAC | I40E_INSET_SMAC |
7874 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7875 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7876 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7877 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7878 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7879 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7880 I40E_INSET_FLEX_PAYLOAD,
7881 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7882 I40E_INSET_DMAC | I40E_INSET_SMAC |
7883 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7884 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7885 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7886 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7887 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7888 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7889 I40E_INSET_FLEX_PAYLOAD,
7890 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7891 I40E_INSET_DMAC | I40E_INSET_SMAC |
7892 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7893 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7894 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7895 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7896 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7897 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7898 I40E_INSET_FLEX_PAYLOAD,
7899 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7900 I40E_INSET_DMAC | I40E_INSET_SMAC |
7901 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7902 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7903 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7904 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7905 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7906 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7907 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7908 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7909 I40E_INSET_DMAC | I40E_INSET_SMAC |
7910 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7911 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7912 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7913 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7914 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7915 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7916 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7917 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7918 I40E_INSET_DMAC | I40E_INSET_SMAC |
7919 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7920 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7921 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7922 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7923 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7924 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7925 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7926 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7927 I40E_INSET_DMAC | I40E_INSET_SMAC |
7928 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7929 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7930 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7931 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7932 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7933 I40E_INSET_FLEX_PAYLOAD,
7934 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7935 I40E_INSET_DMAC | I40E_INSET_SMAC |
7936 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7937 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7938 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7939 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7940 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7941 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7942 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7943 I40E_INSET_DMAC | I40E_INSET_SMAC |
7944 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7945 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7946 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7947 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7948 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7949 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7950 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7951 I40E_INSET_DMAC | I40E_INSET_SMAC |
7952 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7953 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7954 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7955 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7956 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7957 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7958 I40E_INSET_FLEX_PAYLOAD,
7959 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7960 I40E_INSET_DMAC | I40E_INSET_SMAC |
7961 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7962 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7963 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7964 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7965 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7966 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7967 I40E_INSET_FLEX_PAYLOAD,
7968 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7969 I40E_INSET_DMAC | I40E_INSET_SMAC |
7970 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7971 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7972 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7973 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7974 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7975 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7976 I40E_INSET_FLEX_PAYLOAD,
7977 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7978 I40E_INSET_DMAC | I40E_INSET_SMAC |
7979 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7980 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7981 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7982 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7983 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7984 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7985 I40E_INSET_FLEX_PAYLOAD,
7986 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7987 I40E_INSET_DMAC | I40E_INSET_SMAC |
7988 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7989 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7990 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7991 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7992 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7993 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7994 I40E_INSET_FLEX_PAYLOAD,
7995 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7996 I40E_INSET_DMAC | I40E_INSET_SMAC |
7997 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7998 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7999 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8000 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8001 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8002 I40E_INSET_FLEX_PAYLOAD,
8003 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8004 I40E_INSET_DMAC | I40E_INSET_SMAC |
8005 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8006 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8007 I40E_INSET_FLEX_PAYLOAD,
8011 * Flow director supports only fields defined in
8012 * union rte_eth_fdir_flow.
8014 static const uint64_t valid_fdir_inset_table[] = {
8015 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8016 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8017 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8018 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8019 I40E_INSET_IPV4_TTL,
8020 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8021 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8022 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8023 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8024 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8025 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8026 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8027 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8028 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8029 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8030 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8031 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8032 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8033 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8034 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8035 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8036 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8037 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8038 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8039 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8040 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8041 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8042 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8043 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8044 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8045 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8046 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8047 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8048 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8049 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8051 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8052 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8053 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8054 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8055 I40E_INSET_IPV4_TTL,
8056 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8057 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8058 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8059 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8060 I40E_INSET_IPV6_HOP_LIMIT,
8061 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8062 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8063 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8064 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8065 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8066 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8067 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8068 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8069 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8070 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8071 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8072 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8073 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8074 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8075 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8076 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8077 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8078 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8079 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8080 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8081 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8082 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8083 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8084 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8085 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8086 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8087 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8088 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8089 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8090 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8092 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8093 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8094 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8095 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8096 I40E_INSET_IPV6_HOP_LIMIT,
8097 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8098 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8099 I40E_INSET_LAST_ETHER_TYPE,
8102 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8104 if (filter == RTE_ETH_FILTER_HASH)
8105 valid = valid_hash_inset_table[pctype];
8107 valid = valid_fdir_inset_table[pctype];
8113 * Validate if the input set is allowed for a specific PCTYPE
8116 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8117 enum rte_filter_type filter, uint64_t inset)
8121 valid = i40e_get_valid_input_set(pctype, filter);
8122 if (inset & (~valid))
8128 /* default input set fields combination per pctype */
8130 i40e_get_default_input_set(uint16_t pctype)
8132 static const uint64_t default_inset_table[] = {
8133 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8134 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8135 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8136 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8137 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8138 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8139 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8140 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8141 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8142 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8143 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8144 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8145 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8146 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8147 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8148 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8149 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8150 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8151 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8152 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8154 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8155 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8156 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8157 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8158 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8159 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8160 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8161 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8162 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8163 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8164 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8165 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8166 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8167 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8168 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8169 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8170 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8171 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8172 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8173 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8174 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8175 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8177 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8178 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8179 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8180 I40E_INSET_LAST_ETHER_TYPE,
8183 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8186 return default_inset_table[pctype];
8190 * Parse the input set from index to logical bit masks
8193 i40e_parse_input_set(uint64_t *inset,
8194 enum i40e_filter_pctype pctype,
8195 enum rte_eth_input_set_field *field,
8201 static const struct {
8202 enum rte_eth_input_set_field field;
8204 } inset_convert_table[] = {
8205 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8206 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8207 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8208 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8209 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8210 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8211 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8212 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8213 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8214 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8215 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8216 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8217 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8218 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8219 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8220 I40E_INSET_IPV6_NEXT_HDR},
8221 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8222 I40E_INSET_IPV6_HOP_LIMIT},
8223 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8224 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8225 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8226 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8227 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8228 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8229 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8230 I40E_INSET_SCTP_VT},
8231 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8232 I40E_INSET_TUNNEL_DMAC},
8233 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8234 I40E_INSET_VLAN_TUNNEL},
8235 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8236 I40E_INSET_TUNNEL_ID},
8237 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8238 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8239 I40E_INSET_FLEX_PAYLOAD_W1},
8240 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8241 I40E_INSET_FLEX_PAYLOAD_W2},
8242 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8243 I40E_INSET_FLEX_PAYLOAD_W3},
8244 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8245 I40E_INSET_FLEX_PAYLOAD_W4},
8246 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8247 I40E_INSET_FLEX_PAYLOAD_W5},
8248 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8249 I40E_INSET_FLEX_PAYLOAD_W6},
8250 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8251 I40E_INSET_FLEX_PAYLOAD_W7},
8252 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8253 I40E_INSET_FLEX_PAYLOAD_W8},
8256 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8259 /* Only one item allowed for default or all */
8261 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8262 *inset = i40e_get_default_input_set(pctype);
8264 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8265 *inset = I40E_INSET_NONE;
8270 for (i = 0, *inset = 0; i < size; i++) {
8271 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8272 if (field[i] == inset_convert_table[j].field) {
8273 *inset |= inset_convert_table[j].inset;
8278 /* It contains unsupported input set, return immediately */
8279 if (j == RTE_DIM(inset_convert_table))
8287 * Translate the input set from bit masks to register aware bit masks
8291 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8301 static const struct inset_map inset_map_common[] = {
8302 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8303 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8304 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8305 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8306 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8307 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8308 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8309 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8310 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8311 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8312 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8313 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8314 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8315 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8316 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8317 {I40E_INSET_TUNNEL_DMAC,
8318 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8319 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8320 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8321 {I40E_INSET_TUNNEL_SRC_PORT,
8322 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8323 {I40E_INSET_TUNNEL_DST_PORT,
8324 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8325 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8326 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8327 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8328 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8329 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8330 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8331 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8332 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8333 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8336 /* some different registers map in x722*/
8337 static const struct inset_map inset_map_diff_x722[] = {
8338 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8339 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8340 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8341 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8344 static const struct inset_map inset_map_diff_not_x722[] = {
8345 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8346 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8347 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8348 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8354 /* Translate input set to register aware inset */
8355 if (type == I40E_MAC_X722) {
8356 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8357 if (input & inset_map_diff_x722[i].inset)
8358 val |= inset_map_diff_x722[i].inset_reg;
8361 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8362 if (input & inset_map_diff_not_x722[i].inset)
8363 val |= inset_map_diff_not_x722[i].inset_reg;
8367 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8368 if (input & inset_map_common[i].inset)
8369 val |= inset_map_common[i].inset_reg;
8376 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8379 uint64_t inset_need_mask = inset;
8381 static const struct {
8384 } inset_mask_map[] = {
8385 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8386 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8387 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8388 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8389 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8390 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8391 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8392 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8395 if (!inset || !mask || !nb_elem)
8398 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8399 /* Clear the inset bit, if no MASK is required,
8400 * for example proto + ttl
8402 if ((inset & inset_mask_map[i].inset) ==
8403 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8404 inset_need_mask &= ~inset_mask_map[i].inset;
8405 if (!inset_need_mask)
8408 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8409 if ((inset_need_mask & inset_mask_map[i].inset) ==
8410 inset_mask_map[i].inset) {
8411 if (idx >= nb_elem) {
8412 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8415 mask[idx] = inset_mask_map[i].mask;
8424 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8426 uint32_t reg = i40e_read_rx_ctl(hw, addr);
8428 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8430 i40e_write_rx_ctl(hw, addr, val);
8431 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8432 (uint32_t)i40e_read_rx_ctl(hw, addr));
8436 i40e_filter_input_set_init(struct i40e_pf *pf)
8438 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8439 enum i40e_filter_pctype pctype;
8440 uint64_t input_set, inset_reg;
8441 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8444 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8445 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8446 if (hw->mac.type == I40E_MAC_X722) {
8447 if (!I40E_VALID_PCTYPE_X722(pctype))
8450 if (!I40E_VALID_PCTYPE(pctype))
8454 input_set = i40e_get_default_input_set(pctype);
8456 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8457 I40E_INSET_MASK_NUM_REG);
8460 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8463 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8464 (uint32_t)(inset_reg & UINT32_MAX));
8465 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8466 (uint32_t)((inset_reg >>
8467 I40E_32_BIT_WIDTH) & UINT32_MAX));
8468 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8469 (uint32_t)(inset_reg & UINT32_MAX));
8470 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8471 (uint32_t)((inset_reg >>
8472 I40E_32_BIT_WIDTH) & UINT32_MAX));
8474 for (i = 0; i < num; i++) {
8475 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8477 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8480 /*clear unused mask registers of the pctype */
8481 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8482 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8484 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8487 I40E_WRITE_FLUSH(hw);
8489 /* store the default input set */
8490 pf->hash_input_set[pctype] = input_set;
8491 pf->fdir.input_set[pctype] = input_set;
8496 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8497 struct rte_eth_input_set_conf *conf)
8499 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8500 enum i40e_filter_pctype pctype;
8501 uint64_t input_set, inset_reg = 0;
8502 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8506 PMD_DRV_LOG(ERR, "Invalid pointer");
8509 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8510 conf->op != RTE_ETH_INPUT_SET_ADD) {
8511 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8515 if (!I40E_VALID_FLOW(conf->flow_type)) {
8516 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8520 if (hw->mac.type == I40E_MAC_X722) {
8521 /* get translated pctype value in fd pctype register */
8522 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8523 I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8526 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8528 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8531 PMD_DRV_LOG(ERR, "Failed to parse input set");
8534 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8536 PMD_DRV_LOG(ERR, "Invalid input set");
8539 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8540 /* get inset value in register */
8541 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8542 inset_reg <<= I40E_32_BIT_WIDTH;
8543 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8544 input_set |= pf->hash_input_set[pctype];
8546 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8547 I40E_INSET_MASK_NUM_REG);
8551 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8553 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8554 (uint32_t)(inset_reg & UINT32_MAX));
8555 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8556 (uint32_t)((inset_reg >>
8557 I40E_32_BIT_WIDTH) & UINT32_MAX));
8559 for (i = 0; i < num; i++)
8560 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8562 /*clear unused mask registers of the pctype */
8563 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8564 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8566 I40E_WRITE_FLUSH(hw);
8568 pf->hash_input_set[pctype] = input_set;
8573 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8574 struct rte_eth_input_set_conf *conf)
8576 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8577 enum i40e_filter_pctype pctype;
8578 uint64_t input_set, inset_reg = 0;
8579 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8583 PMD_DRV_LOG(ERR, "Invalid pointer");
8586 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8587 conf->op != RTE_ETH_INPUT_SET_ADD) {
8588 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8592 if (!I40E_VALID_FLOW(conf->flow_type)) {
8593 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8597 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8599 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8602 PMD_DRV_LOG(ERR, "Failed to parse input set");
8605 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8607 PMD_DRV_LOG(ERR, "Invalid input set");
8611 /* get inset value in register */
8612 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8613 inset_reg <<= I40E_32_BIT_WIDTH;
8614 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8616 /* Can not change the inset reg for flex payload for fdir,
8617 * it is done by writing I40E_PRTQF_FD_FLXINSET
8618 * in i40e_set_flex_mask_on_pctype.
8620 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8621 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8623 input_set |= pf->fdir.input_set[pctype];
8624 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8625 I40E_INSET_MASK_NUM_REG);
8629 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8631 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8632 (uint32_t)(inset_reg & UINT32_MAX));
8633 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8634 (uint32_t)((inset_reg >>
8635 I40E_32_BIT_WIDTH) & UINT32_MAX));
8637 for (i = 0; i < num; i++)
8638 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8640 /*clear unused mask registers of the pctype */
8641 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8642 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8644 I40E_WRITE_FLUSH(hw);
8646 pf->fdir.input_set[pctype] = input_set;
8651 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8656 PMD_DRV_LOG(ERR, "Invalid pointer");
8660 switch (info->info_type) {
8661 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8662 i40e_get_symmetric_hash_enable_per_port(hw,
8663 &(info->info.enable));
8665 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8666 ret = i40e_get_hash_filter_global_config(hw,
8667 &(info->info.global_conf));
8670 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8680 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8685 PMD_DRV_LOG(ERR, "Invalid pointer");
8689 switch (info->info_type) {
8690 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8691 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8693 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8694 ret = i40e_set_hash_filter_global_config(hw,
8695 &(info->info.global_conf));
8697 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8698 ret = i40e_hash_filter_inset_select(hw,
8699 &(info->info.input_set_conf));
8703 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8712 /* Operations for hash function */
8714 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8715 enum rte_filter_op filter_op,
8718 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8721 switch (filter_op) {
8722 case RTE_ETH_FILTER_NOP:
8724 case RTE_ETH_FILTER_GET:
8725 ret = i40e_hash_filter_get(hw,
8726 (struct rte_eth_hash_filter_info *)arg);
8728 case RTE_ETH_FILTER_SET:
8729 ret = i40e_hash_filter_set(hw,
8730 (struct rte_eth_hash_filter_info *)arg);
8733 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8742 /* Convert ethertype filter structure */
8744 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8745 struct i40e_ethertype_filter *filter)
8747 rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8748 filter->input.ether_type = input->ether_type;
8749 filter->flags = input->flags;
8750 filter->queue = input->queue;
8755 /* Check if there exists the ehtertype filter */
8756 struct i40e_ethertype_filter *
8757 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8758 const struct i40e_ethertype_filter_input *input)
8762 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8766 return ethertype_rule->hash_map[ret];
8769 /* Add ethertype filter in SW list */
8771 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8772 struct i40e_ethertype_filter *filter)
8774 struct i40e_ethertype_rule *rule = &pf->ethertype;
8777 ret = rte_hash_add_key(rule->hash_table, &filter->input);
8780 "Failed to insert ethertype filter"
8781 " to hash table %d!",
8785 rule->hash_map[ret] = filter;
8787 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8792 /* Delete ethertype filter in SW list */
8794 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8795 struct i40e_ethertype_filter_input *input)
8797 struct i40e_ethertype_rule *rule = &pf->ethertype;
8798 struct i40e_ethertype_filter *filter;
8801 ret = rte_hash_del_key(rule->hash_table, input);
8804 "Failed to delete ethertype filter"
8805 " to hash table %d!",
8809 filter = rule->hash_map[ret];
8810 rule->hash_map[ret] = NULL;
8812 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8819 * Configure ethertype filter, which can director packet by filtering
8820 * with mac address and ether_type or only ether_type
8823 i40e_ethertype_filter_set(struct i40e_pf *pf,
8824 struct rte_eth_ethertype_filter *filter,
8827 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8828 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
8829 struct i40e_ethertype_filter *ethertype_filter, *node;
8830 struct i40e_ethertype_filter check_filter;
8831 struct i40e_control_filter_stats stats;
8835 if (filter->queue >= pf->dev_data->nb_rx_queues) {
8836 PMD_DRV_LOG(ERR, "Invalid queue ID");
8839 if (filter->ether_type == ETHER_TYPE_IPv4 ||
8840 filter->ether_type == ETHER_TYPE_IPv6) {
8842 "unsupported ether_type(0x%04x) in control packet filter.",
8843 filter->ether_type);
8846 if (filter->ether_type == ETHER_TYPE_VLAN)
8847 PMD_DRV_LOG(WARNING,
8848 "filter vlan ether_type in first tag is not supported.");
8850 /* Check if there is the filter in SW list */
8851 memset(&check_filter, 0, sizeof(check_filter));
8852 i40e_ethertype_filter_convert(filter, &check_filter);
8853 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
8854 &check_filter.input);
8856 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
8860 if (!add && !node) {
8861 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
8865 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8866 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8867 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8868 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8869 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8871 memset(&stats, 0, sizeof(stats));
8872 ret = i40e_aq_add_rem_control_packet_filter(hw,
8873 filter->mac_addr.addr_bytes,
8874 filter->ether_type, flags,
8876 filter->queue, add, &stats, NULL);
8879 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
8880 ret, stats.mac_etype_used, stats.etype_used,
8881 stats.mac_etype_free, stats.etype_free);
8885 /* Add or delete a filter in SW list */
8887 ethertype_filter = rte_zmalloc("ethertype_filter",
8888 sizeof(*ethertype_filter), 0);
8889 rte_memcpy(ethertype_filter, &check_filter,
8890 sizeof(check_filter));
8891 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
8893 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
8900 * Handle operations for ethertype filter.
8903 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8904 enum rte_filter_op filter_op,
8907 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8910 if (filter_op == RTE_ETH_FILTER_NOP)
8914 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8919 switch (filter_op) {
8920 case RTE_ETH_FILTER_ADD:
8921 ret = i40e_ethertype_filter_set(pf,
8922 (struct rte_eth_ethertype_filter *)arg,
8925 case RTE_ETH_FILTER_DELETE:
8926 ret = i40e_ethertype_filter_set(pf,
8927 (struct rte_eth_ethertype_filter *)arg,
8931 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
8939 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8940 enum rte_filter_type filter_type,
8941 enum rte_filter_op filter_op,
8949 switch (filter_type) {
8950 case RTE_ETH_FILTER_NONE:
8951 /* For global configuration */
8952 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8954 case RTE_ETH_FILTER_HASH:
8955 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8957 case RTE_ETH_FILTER_MACVLAN:
8958 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8960 case RTE_ETH_FILTER_ETHERTYPE:
8961 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8963 case RTE_ETH_FILTER_TUNNEL:
8964 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8966 case RTE_ETH_FILTER_FDIR:
8967 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8969 case RTE_ETH_FILTER_GENERIC:
8970 if (filter_op != RTE_ETH_FILTER_GET)
8972 *(const void **)arg = &i40e_flow_ops;
8975 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8985 * Check and enable Extended Tag.
8986 * Enabling Extended Tag is important for 40G performance.
8989 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8991 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
8995 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
8998 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9002 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9003 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9008 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9011 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9015 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9016 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9019 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9020 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9023 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9030 * As some registers wouldn't be reset unless a global hardware reset,
9031 * hardware initialization is needed to put those registers into an
9032 * expected initial state.
9035 i40e_hw_init(struct rte_eth_dev *dev)
9037 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9039 i40e_enable_extended_tag(dev);
9041 /* clear the PF Queue Filter control register */
9042 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9044 /* Disable symmetric hash per port */
9045 i40e_set_symmetric_hash_enable_per_port(hw, 0);
9048 enum i40e_filter_pctype
9049 i40e_flowtype_to_pctype(uint16_t flow_type)
9051 static const enum i40e_filter_pctype pctype_table[] = {
9052 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
9053 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
9054 I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
9055 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
9056 I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
9057 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
9058 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
9059 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
9060 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
9061 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
9062 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
9063 I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
9064 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
9065 I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
9066 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
9067 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
9068 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
9069 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
9070 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
9073 return pctype_table[flow_type];
9077 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
9079 static const uint16_t flowtype_table[] = {
9080 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
9081 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9082 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9083 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9084 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9085 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9086 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9087 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9088 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9089 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9090 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9091 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9092 RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
9093 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9094 RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
9095 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
9096 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9097 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9098 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9099 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9100 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9101 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9102 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9103 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9104 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9105 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9106 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9107 RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
9108 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9109 RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
9110 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
9113 return flowtype_table[pctype];
9117 * On X710, performance number is far from the expectation on recent firmware
9118 * versions; on XL710, performance number is also far from the expectation on
9119 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9120 * mode is enabled and port MAC address is equal to the packet destination MAC
9121 * address. The fix for this issue may not be integrated in the following
9122 * firmware version. So the workaround in software driver is needed. It needs
9123 * to modify the initial values of 3 internal only registers for both X710 and
9124 * XL710. Note that the values for X710 or XL710 could be different, and the
9125 * workaround can be removed when it is fixed in firmware in the future.
9128 /* For both X710 and XL710 */
9129 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
9130 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
9132 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9133 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
9136 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9137 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9140 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
9142 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
9143 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
9146 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9148 enum i40e_status_code status;
9149 struct i40e_aq_get_phy_abilities_resp phy_ab;
9152 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9162 i40e_configure_registers(struct i40e_hw *hw)
9168 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9169 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9170 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9176 for (i = 0; i < RTE_DIM(reg_table); i++) {
9177 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9178 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9180 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9181 else /* For X710/XL710/XXV710 */
9183 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9186 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9187 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9189 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9190 else /* For X710/XL710/XXV710 */
9192 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9195 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9196 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9197 I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9199 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9202 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9205 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9208 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9212 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9213 reg_table[i].addr, reg);
9214 if (reg == reg_table[i].val)
9217 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9218 reg_table[i].val, NULL);
9221 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9222 reg_table[i].val, reg_table[i].addr);
9225 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9226 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9230 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
9231 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
9232 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
9233 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9235 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9240 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9241 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9245 /* Configure for double VLAN RX stripping */
9246 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9247 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9248 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9249 ret = i40e_aq_debug_write_register(hw,
9250 I40E_VSI_TSR(vsi->vsi_id),
9253 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9255 return I40E_ERR_CONFIG;
9259 /* Configure for double VLAN TX insertion */
9260 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9261 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9262 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9263 ret = i40e_aq_debug_write_register(hw,
9264 I40E_VSI_L2TAGSTXVALID(
9265 vsi->vsi_id), reg, NULL);
9268 "Failed to update VSI_L2TAGSTXVALID[%d]",
9270 return I40E_ERR_CONFIG;
9278 * i40e_aq_add_mirror_rule
9279 * @hw: pointer to the hardware structure
9280 * @seid: VEB seid to add mirror rule to
9281 * @dst_id: destination vsi seid
9282 * @entries: Buffer which contains the entities to be mirrored
9283 * @count: number of entities contained in the buffer
9284 * @rule_id:the rule_id of the rule to be added
9286 * Add a mirror rule for a given veb.
9289 static enum i40e_status_code
9290 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9291 uint16_t seid, uint16_t dst_id,
9292 uint16_t rule_type, uint16_t *entries,
9293 uint16_t count, uint16_t *rule_id)
9295 struct i40e_aq_desc desc;
9296 struct i40e_aqc_add_delete_mirror_rule cmd;
9297 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9298 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9301 enum i40e_status_code status;
9303 i40e_fill_default_direct_cmd_desc(&desc,
9304 i40e_aqc_opc_add_mirror_rule);
9305 memset(&cmd, 0, sizeof(cmd));
9307 buff_len = sizeof(uint16_t) * count;
9308 desc.datalen = rte_cpu_to_le_16(buff_len);
9310 desc.flags |= rte_cpu_to_le_16(
9311 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9312 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9313 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9314 cmd.num_entries = rte_cpu_to_le_16(count);
9315 cmd.seid = rte_cpu_to_le_16(seid);
9316 cmd.destination = rte_cpu_to_le_16(dst_id);
9318 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9319 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9321 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9322 hw->aq.asq_last_status, resp->rule_id,
9323 resp->mirror_rules_used, resp->mirror_rules_free);
9324 *rule_id = rte_le_to_cpu_16(resp->rule_id);
9330 * i40e_aq_del_mirror_rule
9331 * @hw: pointer to the hardware structure
9332 * @seid: VEB seid to add mirror rule to
9333 * @entries: Buffer which contains the entities to be mirrored
9334 * @count: number of entities contained in the buffer
9335 * @rule_id:the rule_id of the rule to be delete
9337 * Delete a mirror rule for a given veb.
9340 static enum i40e_status_code
9341 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9342 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9343 uint16_t count, uint16_t rule_id)
9345 struct i40e_aq_desc desc;
9346 struct i40e_aqc_add_delete_mirror_rule cmd;
9347 uint16_t buff_len = 0;
9348 enum i40e_status_code status;
9351 i40e_fill_default_direct_cmd_desc(&desc,
9352 i40e_aqc_opc_delete_mirror_rule);
9353 memset(&cmd, 0, sizeof(cmd));
9354 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9355 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9357 cmd.num_entries = count;
9358 buff_len = sizeof(uint16_t) * count;
9359 desc.datalen = rte_cpu_to_le_16(buff_len);
9360 buff = (void *)entries;
9362 /* rule id is filled in destination field for deleting mirror rule */
9363 cmd.destination = rte_cpu_to_le_16(rule_id);
9365 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9366 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9367 cmd.seid = rte_cpu_to_le_16(seid);
9369 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9370 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9376 * i40e_mirror_rule_set
9377 * @dev: pointer to the hardware structure
9378 * @mirror_conf: mirror rule info
9379 * @sw_id: mirror rule's sw_id
9380 * @on: enable/disable
9382 * set a mirror rule.
9386 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9387 struct rte_eth_mirror_conf *mirror_conf,
9388 uint8_t sw_id, uint8_t on)
9390 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9391 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9392 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9393 struct i40e_mirror_rule *parent = NULL;
9394 uint16_t seid, dst_seid, rule_id;
9398 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9400 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9402 "mirror rule can not be configured without veb or vfs.");
9405 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9406 PMD_DRV_LOG(ERR, "mirror table is full.");
9409 if (mirror_conf->dst_pool > pf->vf_num) {
9410 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9411 mirror_conf->dst_pool);
9415 seid = pf->main_vsi->veb->seid;
9417 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9418 if (sw_id <= it->index) {
9424 if (mirr_rule && sw_id == mirr_rule->index) {
9426 PMD_DRV_LOG(ERR, "mirror rule exists.");
9429 ret = i40e_aq_del_mirror_rule(hw, seid,
9430 mirr_rule->rule_type,
9432 mirr_rule->num_entries, mirr_rule->id);
9435 "failed to remove mirror rule: ret = %d, aq_err = %d.",
9436 ret, hw->aq.asq_last_status);
9439 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9440 rte_free(mirr_rule);
9441 pf->nb_mirror_rule--;
9445 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9449 mirr_rule = rte_zmalloc("i40e_mirror_rule",
9450 sizeof(struct i40e_mirror_rule) , 0);
9452 PMD_DRV_LOG(ERR, "failed to allocate memory");
9453 return I40E_ERR_NO_MEMORY;
9455 switch (mirror_conf->rule_type) {
9456 case ETH_MIRROR_VLAN:
9457 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9458 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9459 mirr_rule->entries[j] =
9460 mirror_conf->vlan.vlan_id[i];
9465 PMD_DRV_LOG(ERR, "vlan is not specified.");
9466 rte_free(mirr_rule);
9469 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9471 case ETH_MIRROR_VIRTUAL_POOL_UP:
9472 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9473 /* check if the specified pool bit is out of range */
9474 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9475 PMD_DRV_LOG(ERR, "pool mask is out of range.");
9476 rte_free(mirr_rule);
9479 for (i = 0, j = 0; i < pf->vf_num; i++) {
9480 if (mirror_conf->pool_mask & (1ULL << i)) {
9481 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9485 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9486 /* add pf vsi to entries */
9487 mirr_rule->entries[j] = pf->main_vsi_seid;
9491 PMD_DRV_LOG(ERR, "pool is not specified.");
9492 rte_free(mirr_rule);
9495 /* egress and ingress in aq commands means from switch but not port */
9496 mirr_rule->rule_type =
9497 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9498 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9499 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9501 case ETH_MIRROR_UPLINK_PORT:
9502 /* egress and ingress in aq commands means from switch but not port*/
9503 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9505 case ETH_MIRROR_DOWNLINK_PORT:
9506 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9509 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9510 mirror_conf->rule_type);
9511 rte_free(mirr_rule);
9515 /* If the dst_pool is equal to vf_num, consider it as PF */
9516 if (mirror_conf->dst_pool == pf->vf_num)
9517 dst_seid = pf->main_vsi_seid;
9519 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9521 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9522 mirr_rule->rule_type, mirr_rule->entries,
9526 "failed to add mirror rule: ret = %d, aq_err = %d.",
9527 ret, hw->aq.asq_last_status);
9528 rte_free(mirr_rule);
9532 mirr_rule->index = sw_id;
9533 mirr_rule->num_entries = j;
9534 mirr_rule->id = rule_id;
9535 mirr_rule->dst_vsi_seid = dst_seid;
9538 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9540 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9542 pf->nb_mirror_rule++;
9547 * i40e_mirror_rule_reset
9548 * @dev: pointer to the device
9549 * @sw_id: mirror rule's sw_id
9551 * reset a mirror rule.
9555 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9557 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9558 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9559 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9563 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9565 seid = pf->main_vsi->veb->seid;
9567 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9568 if (sw_id == it->index) {
9574 ret = i40e_aq_del_mirror_rule(hw, seid,
9575 mirr_rule->rule_type,
9577 mirr_rule->num_entries, mirr_rule->id);
9580 "failed to remove mirror rule: status = %d, aq_err = %d.",
9581 ret, hw->aq.asq_last_status);
9584 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9585 rte_free(mirr_rule);
9586 pf->nb_mirror_rule--;
9588 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9595 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9597 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9598 uint64_t systim_cycles;
9600 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9601 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9604 return systim_cycles;
9608 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9610 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9613 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9614 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9621 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9623 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9626 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9627 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9634 i40e_start_timecounters(struct rte_eth_dev *dev)
9636 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9637 struct i40e_adapter *adapter =
9638 (struct i40e_adapter *)dev->data->dev_private;
9639 struct rte_eth_link link;
9640 uint32_t tsync_inc_l;
9641 uint32_t tsync_inc_h;
9643 /* Get current link speed. */
9644 memset(&link, 0, sizeof(link));
9645 i40e_dev_link_update(dev, 1);
9646 rte_i40e_dev_atomic_read_link_status(dev, &link);
9648 switch (link.link_speed) {
9649 case ETH_SPEED_NUM_40G:
9650 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9651 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9653 case ETH_SPEED_NUM_10G:
9654 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9655 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9657 case ETH_SPEED_NUM_1G:
9658 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9659 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9666 /* Set the timesync increment value. */
9667 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9668 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9670 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9671 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9672 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9674 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9675 adapter->systime_tc.cc_shift = 0;
9676 adapter->systime_tc.nsec_mask = 0;
9678 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9679 adapter->rx_tstamp_tc.cc_shift = 0;
9680 adapter->rx_tstamp_tc.nsec_mask = 0;
9682 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9683 adapter->tx_tstamp_tc.cc_shift = 0;
9684 adapter->tx_tstamp_tc.nsec_mask = 0;
9688 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9690 struct i40e_adapter *adapter =
9691 (struct i40e_adapter *)dev->data->dev_private;
9693 adapter->systime_tc.nsec += delta;
9694 adapter->rx_tstamp_tc.nsec += delta;
9695 adapter->tx_tstamp_tc.nsec += delta;
9701 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9704 struct i40e_adapter *adapter =
9705 (struct i40e_adapter *)dev->data->dev_private;
9707 ns = rte_timespec_to_ns(ts);
9709 /* Set the timecounters to a new value. */
9710 adapter->systime_tc.nsec = ns;
9711 adapter->rx_tstamp_tc.nsec = ns;
9712 adapter->tx_tstamp_tc.nsec = ns;
9718 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9720 uint64_t ns, systime_cycles;
9721 struct i40e_adapter *adapter =
9722 (struct i40e_adapter *)dev->data->dev_private;
9724 systime_cycles = i40e_read_systime_cyclecounter(dev);
9725 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9726 *ts = rte_ns_to_timespec(ns);
9732 i40e_timesync_enable(struct rte_eth_dev *dev)
9734 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9735 uint32_t tsync_ctl_l;
9736 uint32_t tsync_ctl_h;
9738 /* Stop the timesync system time. */
9739 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9740 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9741 /* Reset the timesync system time value. */
9742 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9743 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9745 i40e_start_timecounters(dev);
9747 /* Clear timesync registers. */
9748 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9749 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9750 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9751 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9752 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9753 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9755 /* Enable timestamping of PTP packets. */
9756 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9757 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9759 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9760 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9761 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9763 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9764 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9770 i40e_timesync_disable(struct rte_eth_dev *dev)
9772 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9773 uint32_t tsync_ctl_l;
9774 uint32_t tsync_ctl_h;
9776 /* Disable timestamping of transmitted PTP packets. */
9777 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9778 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9780 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9781 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9783 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9784 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9786 /* Reset the timesync increment value. */
9787 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9788 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9794 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9795 struct timespec *timestamp, uint32_t flags)
9797 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9798 struct i40e_adapter *adapter =
9799 (struct i40e_adapter *)dev->data->dev_private;
9801 uint32_t sync_status;
9802 uint32_t index = flags & 0x03;
9803 uint64_t rx_tstamp_cycles;
9806 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9807 if ((sync_status & (1 << index)) == 0)
9810 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9811 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9812 *timestamp = rte_ns_to_timespec(ns);
9818 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9819 struct timespec *timestamp)
9821 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9822 struct i40e_adapter *adapter =
9823 (struct i40e_adapter *)dev->data->dev_private;
9825 uint32_t sync_status;
9826 uint64_t tx_tstamp_cycles;
9829 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9830 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9833 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9834 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9835 *timestamp = rte_ns_to_timespec(ns);
9841 * i40e_parse_dcb_configure - parse dcb configure from user
9842 * @dev: the device being configured
9843 * @dcb_cfg: pointer of the result of parse
9844 * @*tc_map: bit map of enabled traffic classes
9846 * Returns 0 on success, negative value on failure
9849 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9850 struct i40e_dcbx_config *dcb_cfg,
9853 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9854 uint8_t i, tc_bw, bw_lf;
9856 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9858 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9859 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9860 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9864 /* assume each tc has the same bw */
9865 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9866 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9867 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9868 /* to ensure the sum of tcbw is equal to 100 */
9869 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9870 for (i = 0; i < bw_lf; i++)
9871 dcb_cfg->etscfg.tcbwtable[i]++;
9873 /* assume each tc has the same Transmission Selection Algorithm */
9874 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9875 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9877 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9878 dcb_cfg->etscfg.prioritytable[i] =
9879 dcb_rx_conf->dcb_tc[i];
9881 /* FW needs one App to configure HW */
9882 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9883 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9884 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9885 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9887 if (dcb_rx_conf->nb_tcs == 0)
9888 *tc_map = 1; /* tc0 only */
9890 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9892 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9893 dcb_cfg->pfc.willing = 0;
9894 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9895 dcb_cfg->pfc.pfcenable = *tc_map;
9901 static enum i40e_status_code
9902 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9903 struct i40e_aqc_vsi_properties_data *info,
9904 uint8_t enabled_tcmap)
9906 enum i40e_status_code ret;
9907 int i, total_tc = 0;
9908 uint16_t qpnum_per_tc, bsf, qp_idx;
9909 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9910 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9911 uint16_t used_queues;
9913 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9914 if (ret != I40E_SUCCESS)
9917 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9918 if (enabled_tcmap & (1 << i))
9923 vsi->enabled_tc = enabled_tcmap;
9925 /* different VSI has different queues assigned */
9926 if (vsi->type == I40E_VSI_MAIN)
9927 used_queues = dev_data->nb_rx_queues -
9928 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9929 else if (vsi->type == I40E_VSI_VMDQ2)
9930 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9932 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9933 return I40E_ERR_NO_AVAILABLE_VSI;
9936 qpnum_per_tc = used_queues / total_tc;
9937 /* Number of queues per enabled TC */
9938 if (qpnum_per_tc == 0) {
9939 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9940 return I40E_ERR_INVALID_QP_ID;
9942 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9944 bsf = rte_bsf32(qpnum_per_tc);
9947 * Configure TC and queue mapping parameters, for enabled TC,
9948 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9949 * default queue will serve it.
9952 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9953 if (vsi->enabled_tc & (1 << i)) {
9954 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9955 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9956 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9957 qp_idx += qpnum_per_tc;
9959 info->tc_mapping[i] = 0;
9962 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9963 if (vsi->type == I40E_VSI_SRIOV) {
9964 info->mapping_flags |=
9965 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9966 for (i = 0; i < vsi->nb_qps; i++)
9967 info->queue_mapping[i] =
9968 rte_cpu_to_le_16(vsi->base_queue + i);
9970 info->mapping_flags |=
9971 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9972 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9974 info->valid_sections |=
9975 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9977 return I40E_SUCCESS;
9981 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9982 * @veb: VEB to be configured
9983 * @tc_map: enabled TC bitmap
9985 * Returns 0 on success, negative value on failure
9987 static enum i40e_status_code
9988 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9990 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9991 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9992 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9993 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9994 enum i40e_status_code ret = I40E_SUCCESS;
9998 /* Check if enabled_tc is same as existing or new TCs */
9999 if (veb->enabled_tc == tc_map)
10002 /* configure tc bandwidth */
10003 memset(&veb_bw, 0, sizeof(veb_bw));
10004 veb_bw.tc_valid_bits = tc_map;
10005 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10006 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10007 if (tc_map & BIT_ULL(i))
10008 veb_bw.tc_bw_share_credits[i] = 1;
10010 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10014 "AQ command Config switch_comp BW allocation per TC failed = %d",
10015 hw->aq.asq_last_status);
10019 memset(&ets_query, 0, sizeof(ets_query));
10020 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10022 if (ret != I40E_SUCCESS) {
10024 "Failed to get switch_comp ETS configuration %u",
10025 hw->aq.asq_last_status);
10028 memset(&bw_query, 0, sizeof(bw_query));
10029 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10031 if (ret != I40E_SUCCESS) {
10033 "Failed to get switch_comp bandwidth configuration %u",
10034 hw->aq.asq_last_status);
10038 /* store and print out BW info */
10039 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10040 veb->bw_info.bw_max = ets_query.tc_bw_max;
10041 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10042 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10043 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10044 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10045 I40E_16_BIT_WIDTH);
10046 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10047 veb->bw_info.bw_ets_share_credits[i] =
10048 bw_query.tc_bw_share_credits[i];
10049 veb->bw_info.bw_ets_credits[i] =
10050 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10051 /* 4 bits per TC, 4th bit is reserved */
10052 veb->bw_info.bw_ets_max[i] =
10053 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10054 RTE_LEN2MASK(3, uint8_t));
10055 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10056 veb->bw_info.bw_ets_share_credits[i]);
10057 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10058 veb->bw_info.bw_ets_credits[i]);
10059 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10060 veb->bw_info.bw_ets_max[i]);
10063 veb->enabled_tc = tc_map;
10070 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10071 * @vsi: VSI to be configured
10072 * @tc_map: enabled TC bitmap
10074 * Returns 0 on success, negative value on failure
10076 static enum i40e_status_code
10077 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10079 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10080 struct i40e_vsi_context ctxt;
10081 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10082 enum i40e_status_code ret = I40E_SUCCESS;
10085 /* Check if enabled_tc is same as existing or new TCs */
10086 if (vsi->enabled_tc == tc_map)
10089 /* configure tc bandwidth */
10090 memset(&bw_data, 0, sizeof(bw_data));
10091 bw_data.tc_valid_bits = tc_map;
10092 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10093 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10094 if (tc_map & BIT_ULL(i))
10095 bw_data.tc_bw_credits[i] = 1;
10097 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10100 "AQ command Config VSI BW allocation per TC failed = %d",
10101 hw->aq.asq_last_status);
10104 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10105 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10107 /* Update Queue Pairs Mapping for currently enabled UPs */
10108 ctxt.seid = vsi->seid;
10109 ctxt.pf_num = hw->pf_id;
10111 ctxt.uplink_seid = vsi->uplink_seid;
10112 ctxt.info = vsi->info;
10114 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10118 /* Update the VSI after updating the VSI queue-mapping information */
10119 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10121 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10122 hw->aq.asq_last_status);
10125 /* update the local VSI info with updated queue map */
10126 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10127 sizeof(vsi->info.tc_mapping));
10128 (void)rte_memcpy(&vsi->info.queue_mapping,
10129 &ctxt.info.queue_mapping,
10130 sizeof(vsi->info.queue_mapping));
10131 vsi->info.mapping_flags = ctxt.info.mapping_flags;
10132 vsi->info.valid_sections = 0;
10134 /* query and update current VSI BW information */
10135 ret = i40e_vsi_get_bw_config(vsi);
10138 "Failed updating vsi bw info, err %s aq_err %s",
10139 i40e_stat_str(hw, ret),
10140 i40e_aq_str(hw, hw->aq.asq_last_status));
10144 vsi->enabled_tc = tc_map;
10151 * i40e_dcb_hw_configure - program the dcb setting to hw
10152 * @pf: pf the configuration is taken on
10153 * @new_cfg: new configuration
10154 * @tc_map: enabled TC bitmap
10156 * Returns 0 on success, negative value on failure
10158 static enum i40e_status_code
10159 i40e_dcb_hw_configure(struct i40e_pf *pf,
10160 struct i40e_dcbx_config *new_cfg,
10163 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10164 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10165 struct i40e_vsi *main_vsi = pf->main_vsi;
10166 struct i40e_vsi_list *vsi_list;
10167 enum i40e_status_code ret;
10171 /* Use the FW API if FW > v4.4*/
10172 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10173 (hw->aq.fw_maj_ver >= 5))) {
10175 "FW < v4.4, can not use FW LLDP API to configure DCB");
10176 return I40E_ERR_FIRMWARE_API_VERSION;
10179 /* Check if need reconfiguration */
10180 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10181 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10182 return I40E_SUCCESS;
10185 /* Copy the new config to the current config */
10186 *old_cfg = *new_cfg;
10187 old_cfg->etsrec = old_cfg->etscfg;
10188 ret = i40e_set_dcb_config(hw);
10190 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10191 i40e_stat_str(hw, ret),
10192 i40e_aq_str(hw, hw->aq.asq_last_status));
10195 /* set receive Arbiter to RR mode and ETS scheme by default */
10196 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10197 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10198 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
10199 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10200 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10201 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10202 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10203 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10204 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10205 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10206 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10207 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10208 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10210 /* get local mib to check whether it is configured correctly */
10212 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10213 /* Get Local DCB Config */
10214 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10215 &hw->local_dcbx_config);
10217 /* if Veb is created, need to update TC of it at first */
10218 if (main_vsi->veb) {
10219 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10221 PMD_INIT_LOG(WARNING,
10222 "Failed configuring TC for VEB seid=%d",
10223 main_vsi->veb->seid);
10225 /* Update each VSI */
10226 i40e_vsi_config_tc(main_vsi, tc_map);
10227 if (main_vsi->veb) {
10228 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10229 /* Beside main VSI and VMDQ VSIs, only enable default
10230 * TC for other VSIs
10232 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10233 ret = i40e_vsi_config_tc(vsi_list->vsi,
10236 ret = i40e_vsi_config_tc(vsi_list->vsi,
10237 I40E_DEFAULT_TCMAP);
10239 PMD_INIT_LOG(WARNING,
10240 "Failed configuring TC for VSI seid=%d",
10241 vsi_list->vsi->seid);
10245 return I40E_SUCCESS;
10249 * i40e_dcb_init_configure - initial dcb config
10250 * @dev: device being configured
10251 * @sw_dcb: indicate whether dcb is sw configured or hw offload
10253 * Returns 0 on success, negative value on failure
10256 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10258 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10259 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10262 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10263 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10267 /* DCB initialization:
10268 * Update DCB configuration from the Firmware and configure
10269 * LLDP MIB change event.
10271 if (sw_dcb == TRUE) {
10272 ret = i40e_init_dcb(hw);
10273 /* If lldp agent is stopped, the return value from
10274 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10275 * adminq status. Otherwise, it should return success.
10277 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10278 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10279 memset(&hw->local_dcbx_config, 0,
10280 sizeof(struct i40e_dcbx_config));
10281 /* set dcb default configuration */
10282 hw->local_dcbx_config.etscfg.willing = 0;
10283 hw->local_dcbx_config.etscfg.maxtcs = 0;
10284 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10285 hw->local_dcbx_config.etscfg.tsatable[0] =
10287 /* all UPs mapping to TC0 */
10288 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10289 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10290 hw->local_dcbx_config.etsrec =
10291 hw->local_dcbx_config.etscfg;
10292 hw->local_dcbx_config.pfc.willing = 0;
10293 hw->local_dcbx_config.pfc.pfccap =
10294 I40E_MAX_TRAFFIC_CLASS;
10295 /* FW needs one App to configure HW */
10296 hw->local_dcbx_config.numapps = 1;
10297 hw->local_dcbx_config.app[0].selector =
10298 I40E_APP_SEL_ETHTYPE;
10299 hw->local_dcbx_config.app[0].priority = 3;
10300 hw->local_dcbx_config.app[0].protocolid =
10301 I40E_APP_PROTOID_FCOE;
10302 ret = i40e_set_dcb_config(hw);
10305 "default dcb config fails. err = %d, aq_err = %d.",
10306 ret, hw->aq.asq_last_status);
10311 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10312 ret, hw->aq.asq_last_status);
10316 ret = i40e_aq_start_lldp(hw, NULL);
10317 if (ret != I40E_SUCCESS)
10318 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10320 ret = i40e_init_dcb(hw);
10322 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10324 "HW doesn't support DCBX offload.");
10329 "DCBX configuration failed, err = %d, aq_err = %d.",
10330 ret, hw->aq.asq_last_status);
10338 * i40e_dcb_setup - setup dcb related config
10339 * @dev: device being configured
10341 * Returns 0 on success, negative value on failure
10344 i40e_dcb_setup(struct rte_eth_dev *dev)
10346 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10347 struct i40e_dcbx_config dcb_cfg;
10348 uint8_t tc_map = 0;
10351 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10352 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10356 if (pf->vf_num != 0)
10357 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10359 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10361 PMD_INIT_LOG(ERR, "invalid dcb config");
10364 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10366 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10374 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10375 struct rte_eth_dcb_info *dcb_info)
10377 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10378 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10379 struct i40e_vsi *vsi = pf->main_vsi;
10380 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10381 uint16_t bsf, tc_mapping;
10384 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10385 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10387 dcb_info->nb_tcs = 1;
10388 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10389 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10390 for (i = 0; i < dcb_info->nb_tcs; i++)
10391 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10393 /* get queue mapping if vmdq is disabled */
10394 if (!pf->nb_cfg_vmdq_vsi) {
10395 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10396 if (!(vsi->enabled_tc & (1 << i)))
10398 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10399 dcb_info->tc_queue.tc_rxq[j][i].base =
10400 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10401 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10402 dcb_info->tc_queue.tc_txq[j][i].base =
10403 dcb_info->tc_queue.tc_rxq[j][i].base;
10404 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10405 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10406 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10407 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10408 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10413 /* get queue mapping if vmdq is enabled */
10415 vsi = pf->vmdq[j].vsi;
10416 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10417 if (!(vsi->enabled_tc & (1 << i)))
10419 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10420 dcb_info->tc_queue.tc_rxq[j][i].base =
10421 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10422 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10423 dcb_info->tc_queue.tc_txq[j][i].base =
10424 dcb_info->tc_queue.tc_rxq[j][i].base;
10425 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10426 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10427 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10428 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10429 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10432 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10437 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10439 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10440 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10441 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10442 uint16_t interval =
10443 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10444 uint16_t msix_intr;
10446 msix_intr = intr_handle->intr_vec[queue_id];
10447 if (msix_intr == I40E_MISC_VEC_ID)
10448 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10449 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10450 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10451 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10453 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10456 I40E_PFINT_DYN_CTLN(msix_intr -
10457 I40E_RX_VEC_START),
10458 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10459 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10460 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10462 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10464 I40E_WRITE_FLUSH(hw);
10465 rte_intr_enable(&pci_dev->intr_handle);
10471 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10473 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10474 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10475 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10476 uint16_t msix_intr;
10478 msix_intr = intr_handle->intr_vec[queue_id];
10479 if (msix_intr == I40E_MISC_VEC_ID)
10480 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10483 I40E_PFINT_DYN_CTLN(msix_intr -
10484 I40E_RX_VEC_START),
10486 I40E_WRITE_FLUSH(hw);
10491 static int i40e_get_regs(struct rte_eth_dev *dev,
10492 struct rte_dev_reg_info *regs)
10494 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10495 uint32_t *ptr_data = regs->data;
10496 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10497 const struct i40e_reg_info *reg_info;
10499 if (ptr_data == NULL) {
10500 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10501 regs->width = sizeof(uint32_t);
10505 /* The first few registers have to be read using AQ operations */
10507 while (i40e_regs_adminq[reg_idx].name) {
10508 reg_info = &i40e_regs_adminq[reg_idx++];
10509 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10511 arr_idx2 <= reg_info->count2;
10513 reg_offset = arr_idx * reg_info->stride1 +
10514 arr_idx2 * reg_info->stride2;
10515 reg_offset += reg_info->base_addr;
10516 ptr_data[reg_offset >> 2] =
10517 i40e_read_rx_ctl(hw, reg_offset);
10521 /* The remaining registers can be read using primitives */
10523 while (i40e_regs_others[reg_idx].name) {
10524 reg_info = &i40e_regs_others[reg_idx++];
10525 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10527 arr_idx2 <= reg_info->count2;
10529 reg_offset = arr_idx * reg_info->stride1 +
10530 arr_idx2 * reg_info->stride2;
10531 reg_offset += reg_info->base_addr;
10532 ptr_data[reg_offset >> 2] =
10533 I40E_READ_REG(hw, reg_offset);
10540 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10542 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10544 /* Convert word count to byte count */
10545 return hw->nvm.sr_size << 1;
10548 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10549 struct rte_dev_eeprom_info *eeprom)
10551 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10552 uint16_t *data = eeprom->data;
10553 uint16_t offset, length, cnt_words;
10556 offset = eeprom->offset >> 1;
10557 length = eeprom->length >> 1;
10558 cnt_words = length;
10560 if (offset > hw->nvm.sr_size ||
10561 offset + length > hw->nvm.sr_size) {
10562 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10566 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10568 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10569 if (ret_code != I40E_SUCCESS || cnt_words != length) {
10570 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10577 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10578 struct ether_addr *mac_addr)
10580 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10582 if (!is_valid_assigned_ether_addr(mac_addr)) {
10583 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10587 /* Flags: 0x3 updates port address */
10588 i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10592 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10594 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10595 struct rte_eth_dev_data *dev_data = pf->dev_data;
10596 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
10599 /* check if mtu is within the allowed range */
10600 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10603 /* mtu setting is forbidden if port is start */
10604 if (dev_data->dev_started) {
10605 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10606 dev_data->port_id);
10610 if (frame_size > ETHER_MAX_LEN)
10611 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10613 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10615 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10620 /* Restore ethertype filter */
10622 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10624 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10625 struct i40e_ethertype_filter_list
10626 *ethertype_list = &pf->ethertype.ethertype_list;
10627 struct i40e_ethertype_filter *f;
10628 struct i40e_control_filter_stats stats;
10631 TAILQ_FOREACH(f, ethertype_list, rules) {
10633 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10634 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10635 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10636 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10637 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10639 memset(&stats, 0, sizeof(stats));
10640 i40e_aq_add_rem_control_packet_filter(hw,
10641 f->input.mac_addr.addr_bytes,
10642 f->input.ether_type,
10643 flags, pf->main_vsi->seid,
10644 f->queue, 1, &stats, NULL);
10646 PMD_DRV_LOG(INFO, "Ethertype filter:"
10647 " mac_etype_used = %u, etype_used = %u,"
10648 " mac_etype_free = %u, etype_free = %u",
10649 stats.mac_etype_used, stats.etype_used,
10650 stats.mac_etype_free, stats.etype_free);
10653 /* Restore tunnel filter */
10655 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10657 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10658 struct i40e_vsi *vsi;
10659 struct i40e_pf_vf *vf;
10660 struct i40e_tunnel_filter_list
10661 *tunnel_list = &pf->tunnel.tunnel_list;
10662 struct i40e_tunnel_filter *f;
10663 struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
10664 bool big_buffer = 0;
10666 TAILQ_FOREACH(f, tunnel_list, rules) {
10668 vsi = pf->main_vsi;
10670 vf = &pf->vfs[f->vf_id];
10673 memset(&cld_filter, 0, sizeof(cld_filter));
10674 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
10675 (struct ether_addr *)&cld_filter.element.outer_mac);
10676 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
10677 (struct ether_addr *)&cld_filter.element.inner_mac);
10678 cld_filter.element.inner_vlan = f->input.inner_vlan;
10679 cld_filter.element.flags = f->input.flags;
10680 cld_filter.element.tenant_id = f->input.tenant_id;
10681 cld_filter.element.queue_number = f->queue;
10682 rte_memcpy(cld_filter.general_fields,
10683 f->input.general_fields,
10684 sizeof(f->input.general_fields));
10686 if (((f->input.flags &
10687 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ==
10688 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ||
10690 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ==
10691 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ||
10693 I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ) ==
10694 I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ))
10698 i40e_aq_add_cloud_filters_big_buffer(hw,
10699 vsi->seid, &cld_filter, 1);
10701 i40e_aq_add_cloud_filters(hw, vsi->seid,
10702 &cld_filter.element, 1);
10707 i40e_filter_restore(struct i40e_pf *pf)
10709 i40e_ethertype_filter_restore(pf);
10710 i40e_tunnel_filter_restore(pf);
10711 i40e_fdir_filter_restore(pf);
10715 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
10717 if (strcmp(dev->data->drv_name,
10725 is_i40e_supported(struct rte_eth_dev *dev)
10727 return is_device_supported(dev, &rte_i40e_pmd);
10730 /* Create a QinQ cloud filter
10732 * The Fortville NIC has limited resources for tunnel filters,
10733 * so we can only reuse existing filters.
10735 * In step 1 we define which Field Vector fields can be used for
10737 * As we do not have the inner tag defined as a field,
10738 * we have to define it first, by reusing one of L1 entries.
10740 * In step 2 we are replacing one of existing filter types with
10741 * a new one for QinQ.
10742 * As we reusing L1 and replacing L2, some of the default filter
10743 * types will disappear,which depends on L1 and L2 entries we reuse.
10745 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
10747 * 1. Create L1 filter of outer vlan (12b) which will be in use
10748 * later when we define the cloud filter.
10749 * a. Valid_flags.replace_cloud = 0
10750 * b. Old_filter = 10 (Stag_Inner_Vlan)
10751 * c. New_filter = 0x10
10752 * d. TR bit = 0xff (optional, not used here)
10753 * e. Buffer – 2 entries:
10754 * i. Byte 0 = 8 (outer vlan FV index).
10756 * Byte 2-3 = 0x0fff
10757 * ii. Byte 0 = 37 (inner vlan FV index).
10759 * Byte 2-3 = 0x0fff
10762 * 2. Create cloud filter using two L1 filters entries: stag and
10763 * new filter(outer vlan+ inner vlan)
10764 * a. Valid_flags.replace_cloud = 1
10765 * b. Old_filter = 1 (instead of outer IP)
10766 * c. New_filter = 0x10
10767 * d. Buffer – 2 entries:
10768 * i. Byte 0 = 0x80 | 7 (valid | Stag).
10769 * Byte 1-3 = 0 (rsv)
10770 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
10771 * Byte 9-11 = 0 (rsv)
10774 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
10776 int ret = -ENOTSUP;
10777 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
10778 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
10779 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10782 memset(&filter_replace, 0,
10783 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
10784 memset(&filter_replace_buf, 0,
10785 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
10787 /* create L1 filter */
10788 filter_replace.old_filter_type =
10789 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
10790 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10791 filter_replace.tr_bit = 0;
10793 /* Prepare the buffer, 2 entries */
10794 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
10795 filter_replace_buf.data[0] |=
10796 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10797 /* Field Vector 12b mask */
10798 filter_replace_buf.data[2] = 0xff;
10799 filter_replace_buf.data[3] = 0x0f;
10800 filter_replace_buf.data[4] =
10801 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
10802 filter_replace_buf.data[4] |=
10803 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10804 /* Field Vector 12b mask */
10805 filter_replace_buf.data[6] = 0xff;
10806 filter_replace_buf.data[7] = 0x0f;
10807 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
10808 &filter_replace_buf);
10809 if (ret != I40E_SUCCESS)
10812 /* Apply the second L2 cloud filter */
10813 memset(&filter_replace, 0,
10814 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
10815 memset(&filter_replace_buf, 0,
10816 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
10818 /* create L2 filter, input for L2 filter will be L1 filter */
10819 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
10820 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
10821 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10823 /* Prepare the buffer, 2 entries */
10824 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
10825 filter_replace_buf.data[0] |=
10826 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10827 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10828 filter_replace_buf.data[4] |=
10829 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10830 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
10831 &filter_replace_buf);
10835 RTE_INIT(i40e_init_log);
10837 i40e_init_log(void)
10839 i40e_logtype_init = rte_log_register("pmd.i40e.init");
10840 if (i40e_logtype_init >= 0)
10841 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
10842 i40e_logtype_driver = rte_log_register("pmd.i40e.driver");
10843 if (i40e_logtype_driver >= 0)
10844 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);