1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
14 #include <rte_common.h>
16 #include <rte_string_fns.h>
18 #include <rte_bus_pci.h>
19 #include <rte_ether.h>
20 #include <rte_ethdev_driver.h>
21 #include <rte_ethdev_pci.h>
22 #include <rte_memzone.h>
23 #include <rte_malloc.h>
24 #include <rte_memcpy.h>
25 #include <rte_alarm.h>
27 #include <rte_eth_ctrl.h>
28 #include <rte_tailq.h>
29 #include <rte_hash_crc.h>
31 #include "i40e_logs.h"
32 #include "base/i40e_prototype.h"
33 #include "base/i40e_adminq_cmd.h"
34 #include "base/i40e_type.h"
35 #include "base/i40e_register.h"
36 #include "base/i40e_dcb.h"
37 #include "i40e_ethdev.h"
38 #include "i40e_rxtx.h"
40 #include "i40e_regs.h"
41 #include "rte_pmd_i40e.h"
43 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
44 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
45 #define ETH_I40E_SUPPORT_MULTI_DRIVER "support-multi-driver"
46 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG "queue-num-per-vf"
47 #define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec"
49 #define I40E_CLEAR_PXE_WAIT_MS 200
51 /* Maximun number of capability elements */
52 #define I40E_MAX_CAP_ELE_NUM 128
54 /* Wait count and interval */
55 #define I40E_CHK_Q_ENA_COUNT 1000
56 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
58 /* Maximun number of VSI */
59 #define I40E_MAX_NUM_VSIS (384UL)
61 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
63 /* Flow control default timer */
64 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
66 /* Flow control enable fwd bit */
67 #define I40E_PRTMAC_FWD_CTRL 0x00000001
69 /* Receive Packet Buffer size */
70 #define I40E_RXPBSIZE (968 * 1024)
73 #define I40E_KILOSHIFT 10
75 /* Flow control default high water */
76 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
78 /* Flow control default low water */
79 #define I40E_DEFAULT_LOW_WATER (0xF2000 >> I40E_KILOSHIFT)
81 /* Receive Average Packet Size in Byte*/
82 #define I40E_PACKET_AVERAGE_SIZE 128
84 /* Mask of PF interrupt causes */
85 #define I40E_PFINT_ICR0_ENA_MASK ( \
86 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
87 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
88 I40E_PFINT_ICR0_ENA_GRST_MASK | \
89 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
90 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
91 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
92 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
93 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
94 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
96 #define I40E_FLOW_TYPES ( \
97 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
98 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
99 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
100 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
101 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
102 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
103 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
104 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
105 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
106 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
107 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
109 /* Additional timesync values. */
110 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
111 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
112 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
113 #define I40E_PRTTSYN_TSYNENA 0x80000000
114 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
115 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
118 * Below are values for writing un-exposed registers suggested
121 /* Destination MAC address */
122 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
123 /* Source MAC address */
124 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
125 /* Outer (S-Tag) VLAN tag in the outer L2 header */
126 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
127 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
128 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
129 /* Single VLAN tag in the inner L2 header */
130 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
131 /* Source IPv4 address */
132 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
133 /* Destination IPv4 address */
134 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
135 /* Source IPv4 address for X722 */
136 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
137 /* Destination IPv4 address for X722 */
138 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
139 /* IPv4 Protocol for X722 */
140 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
141 /* IPv4 Time to Live for X722 */
142 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
143 /* IPv4 Type of Service (TOS) */
144 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
146 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
147 /* IPv4 Time to Live */
148 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
149 /* Source IPv6 address */
150 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
151 /* Destination IPv6 address */
152 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
153 /* IPv6 Traffic Class (TC) */
154 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
155 /* IPv6 Next Header */
156 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
158 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
160 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
161 /* Destination L4 port */
162 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
163 /* SCTP verification tag */
164 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
165 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
166 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
167 /* Source port of tunneling UDP */
168 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
169 /* Destination port of tunneling UDP */
170 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
171 /* UDP Tunneling ID, NVGRE/GRE key */
172 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
173 /* Last ether type */
174 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
175 /* Tunneling outer destination IPv4 address */
176 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
177 /* Tunneling outer destination IPv6 address */
178 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
179 /* 1st word of flex payload */
180 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
181 /* 2nd word of flex payload */
182 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
183 /* 3rd word of flex payload */
184 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
185 /* 4th word of flex payload */
186 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
187 /* 5th word of flex payload */
188 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
189 /* 6th word of flex payload */
190 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
191 /* 7th word of flex payload */
192 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
193 /* 8th word of flex payload */
194 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
195 /* all 8 words flex payload */
196 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
197 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
199 #define I40E_TRANSLATE_INSET 0
200 #define I40E_TRANSLATE_REG 1
202 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
203 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
204 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
205 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
206 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
207 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
209 /* PCI offset for querying capability */
210 #define PCI_DEV_CAP_REG 0xA4
211 /* PCI offset for enabling/disabling Extended Tag */
212 #define PCI_DEV_CTRL_REG 0xA8
213 /* Bit mask of Extended Tag capability */
214 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
215 /* Bit shift of Extended Tag enable/disable */
216 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
217 /* Bit mask of Extended Tag enable/disable */
218 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
220 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
221 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
222 static int i40e_dev_configure(struct rte_eth_dev *dev);
223 static int i40e_dev_start(struct rte_eth_dev *dev);
224 static void i40e_dev_stop(struct rte_eth_dev *dev);
225 static void i40e_dev_close(struct rte_eth_dev *dev);
226 static int i40e_dev_reset(struct rte_eth_dev *dev);
227 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
228 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
229 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
230 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
231 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
232 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
233 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
234 struct rte_eth_stats *stats);
235 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
236 struct rte_eth_xstat *xstats, unsigned n);
237 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
238 struct rte_eth_xstat_name *xstats_names,
240 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
241 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
245 static int i40e_fw_version_get(struct rte_eth_dev *dev,
246 char *fw_version, size_t fw_size);
247 static void i40e_dev_info_get(struct rte_eth_dev *dev,
248 struct rte_eth_dev_info *dev_info);
249 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
252 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
253 enum rte_vlan_type vlan_type,
255 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
256 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
259 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
260 static int i40e_dev_led_on(struct rte_eth_dev *dev);
261 static int i40e_dev_led_off(struct rte_eth_dev *dev);
262 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
263 struct rte_eth_fc_conf *fc_conf);
264 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
265 struct rte_eth_fc_conf *fc_conf);
266 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
267 struct rte_eth_pfc_conf *pfc_conf);
268 static int i40e_macaddr_add(struct rte_eth_dev *dev,
269 struct ether_addr *mac_addr,
272 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
273 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
274 struct rte_eth_rss_reta_entry64 *reta_conf,
276 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
277 struct rte_eth_rss_reta_entry64 *reta_conf,
280 static int i40e_get_cap(struct i40e_hw *hw);
281 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
282 static int i40e_pf_setup(struct i40e_pf *pf);
283 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
284 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
285 static int i40e_dcb_setup(struct rte_eth_dev *dev);
286 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
287 bool offset_loaded, uint64_t *offset, uint64_t *stat);
288 static void i40e_stat_update_48(struct i40e_hw *hw,
294 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
295 static void i40e_dev_interrupt_handler(void *param);
296 static void i40e_dev_alarm_handler(void *param);
297 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
298 uint32_t base, uint32_t num);
299 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
300 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
302 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
304 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
305 static int i40e_veb_release(struct i40e_veb *veb);
306 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
307 struct i40e_vsi *vsi);
308 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
309 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
310 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
311 struct i40e_macvlan_filter *mv_f,
314 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
315 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
316 struct rte_eth_rss_conf *rss_conf);
317 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
318 struct rte_eth_rss_conf *rss_conf);
319 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
320 struct rte_eth_udp_tunnel *udp_tunnel);
321 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
322 struct rte_eth_udp_tunnel *udp_tunnel);
323 static void i40e_filter_input_set_init(struct i40e_pf *pf);
324 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
325 enum rte_filter_op filter_op,
327 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
328 enum rte_filter_type filter_type,
329 enum rte_filter_op filter_op,
331 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
332 struct rte_eth_dcb_info *dcb_info);
333 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
334 static void i40e_configure_registers(struct i40e_hw *hw);
335 static void i40e_hw_init(struct rte_eth_dev *dev);
336 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
337 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
343 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
344 struct rte_eth_mirror_conf *mirror_conf,
345 uint8_t sw_id, uint8_t on);
346 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
348 static int i40e_timesync_enable(struct rte_eth_dev *dev);
349 static int i40e_timesync_disable(struct rte_eth_dev *dev);
350 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
351 struct timespec *timestamp,
353 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
354 struct timespec *timestamp);
355 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
357 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
359 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
360 struct timespec *timestamp);
361 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
362 const struct timespec *timestamp);
364 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
366 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
369 static int i40e_get_regs(struct rte_eth_dev *dev,
370 struct rte_dev_reg_info *regs);
372 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
374 static int i40e_get_eeprom(struct rte_eth_dev *dev,
375 struct rte_dev_eeprom_info *eeprom);
377 static int i40e_get_module_info(struct rte_eth_dev *dev,
378 struct rte_eth_dev_module_info *modinfo);
379 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
380 struct rte_dev_eeprom_info *info);
382 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
383 struct ether_addr *mac_addr);
385 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
387 static int i40e_ethertype_filter_convert(
388 const struct rte_eth_ethertype_filter *input,
389 struct i40e_ethertype_filter *filter);
390 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
391 struct i40e_ethertype_filter *filter);
393 static int i40e_tunnel_filter_convert(
394 struct i40e_aqc_cloud_filters_element_bb *cld_filter,
395 struct i40e_tunnel_filter *tunnel_filter);
396 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
397 struct i40e_tunnel_filter *tunnel_filter);
398 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
400 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
401 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
402 static void i40e_filter_restore(struct i40e_pf *pf);
403 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
405 int i40e_logtype_init;
406 int i40e_logtype_driver;
408 static const char *const valid_keys[] = {
409 ETH_I40E_FLOATING_VEB_ARG,
410 ETH_I40E_FLOATING_VEB_LIST_ARG,
411 ETH_I40E_SUPPORT_MULTI_DRIVER,
412 ETH_I40E_QUEUE_NUM_PER_VF_ARG,
413 ETH_I40E_USE_LATEST_VEC,
416 static const struct rte_pci_id pci_id_i40e_map[] = {
417 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
418 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
419 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
420 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
421 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
422 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
423 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
424 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
425 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
426 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
427 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
428 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
429 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
430 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
431 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
432 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
435 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
436 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
437 { .vendor_id = 0, /* sentinel */ },
440 static const struct eth_dev_ops i40e_eth_dev_ops = {
441 .dev_configure = i40e_dev_configure,
442 .dev_start = i40e_dev_start,
443 .dev_stop = i40e_dev_stop,
444 .dev_close = i40e_dev_close,
445 .dev_reset = i40e_dev_reset,
446 .promiscuous_enable = i40e_dev_promiscuous_enable,
447 .promiscuous_disable = i40e_dev_promiscuous_disable,
448 .allmulticast_enable = i40e_dev_allmulticast_enable,
449 .allmulticast_disable = i40e_dev_allmulticast_disable,
450 .dev_set_link_up = i40e_dev_set_link_up,
451 .dev_set_link_down = i40e_dev_set_link_down,
452 .link_update = i40e_dev_link_update,
453 .stats_get = i40e_dev_stats_get,
454 .xstats_get = i40e_dev_xstats_get,
455 .xstats_get_names = i40e_dev_xstats_get_names,
456 .stats_reset = i40e_dev_stats_reset,
457 .xstats_reset = i40e_dev_stats_reset,
458 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
459 .fw_version_get = i40e_fw_version_get,
460 .dev_infos_get = i40e_dev_info_get,
461 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
462 .vlan_filter_set = i40e_vlan_filter_set,
463 .vlan_tpid_set = i40e_vlan_tpid_set,
464 .vlan_offload_set = i40e_vlan_offload_set,
465 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
466 .vlan_pvid_set = i40e_vlan_pvid_set,
467 .rx_queue_start = i40e_dev_rx_queue_start,
468 .rx_queue_stop = i40e_dev_rx_queue_stop,
469 .tx_queue_start = i40e_dev_tx_queue_start,
470 .tx_queue_stop = i40e_dev_tx_queue_stop,
471 .rx_queue_setup = i40e_dev_rx_queue_setup,
472 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
473 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
474 .rx_queue_release = i40e_dev_rx_queue_release,
475 .rx_queue_count = i40e_dev_rx_queue_count,
476 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
477 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
478 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
479 .tx_queue_setup = i40e_dev_tx_queue_setup,
480 .tx_queue_release = i40e_dev_tx_queue_release,
481 .dev_led_on = i40e_dev_led_on,
482 .dev_led_off = i40e_dev_led_off,
483 .flow_ctrl_get = i40e_flow_ctrl_get,
484 .flow_ctrl_set = i40e_flow_ctrl_set,
485 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
486 .mac_addr_add = i40e_macaddr_add,
487 .mac_addr_remove = i40e_macaddr_remove,
488 .reta_update = i40e_dev_rss_reta_update,
489 .reta_query = i40e_dev_rss_reta_query,
490 .rss_hash_update = i40e_dev_rss_hash_update,
491 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
492 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
493 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
494 .filter_ctrl = i40e_dev_filter_ctrl,
495 .rxq_info_get = i40e_rxq_info_get,
496 .txq_info_get = i40e_txq_info_get,
497 .mirror_rule_set = i40e_mirror_rule_set,
498 .mirror_rule_reset = i40e_mirror_rule_reset,
499 .timesync_enable = i40e_timesync_enable,
500 .timesync_disable = i40e_timesync_disable,
501 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
502 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
503 .get_dcb_info = i40e_dev_get_dcb_info,
504 .timesync_adjust_time = i40e_timesync_adjust_time,
505 .timesync_read_time = i40e_timesync_read_time,
506 .timesync_write_time = i40e_timesync_write_time,
507 .get_reg = i40e_get_regs,
508 .get_eeprom_length = i40e_get_eeprom_length,
509 .get_eeprom = i40e_get_eeprom,
510 .get_module_info = i40e_get_module_info,
511 .get_module_eeprom = i40e_get_module_eeprom,
512 .mac_addr_set = i40e_set_default_mac_addr,
513 .mtu_set = i40e_dev_mtu_set,
514 .tm_ops_get = i40e_tm_ops_get,
517 /* store statistics names and its offset in stats structure */
518 struct rte_i40e_xstats_name_off {
519 char name[RTE_ETH_XSTATS_NAME_SIZE];
523 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
524 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
525 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
526 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
527 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
528 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
529 rx_unknown_protocol)},
530 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
531 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
532 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
533 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
536 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
537 sizeof(rte_i40e_stats_strings[0]))
539 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
540 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
541 tx_dropped_link_down)},
542 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
543 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
545 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
546 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
548 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
550 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
552 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
553 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
554 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
555 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
556 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
557 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
559 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
561 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
563 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
565 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
567 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
569 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
571 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
573 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
574 mac_short_packet_dropped)},
575 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
577 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
578 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
579 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
581 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
583 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
585 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
587 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
589 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
591 {"rx_flow_director_atr_match_packets",
592 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
593 {"rx_flow_director_sb_match_packets",
594 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
595 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
597 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
599 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
601 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
605 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
606 sizeof(rte_i40e_hw_port_strings[0]))
608 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
609 {"xon_packets", offsetof(struct i40e_hw_port_stats,
611 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
615 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
616 sizeof(rte_i40e_rxq_prio_strings[0]))
618 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
619 {"xon_packets", offsetof(struct i40e_hw_port_stats,
621 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
623 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
624 priority_xon_2_xoff)},
627 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
628 sizeof(rte_i40e_txq_prio_strings[0]))
631 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
632 struct rte_pci_device *pci_dev)
634 char name[RTE_ETH_NAME_MAX_LEN];
635 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
638 if (pci_dev->device.devargs) {
639 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
645 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
646 sizeof(struct i40e_adapter),
647 eth_dev_pci_specific_init, pci_dev,
648 eth_i40e_dev_init, NULL);
650 if (retval || eth_da.nb_representor_ports < 1)
653 /* probe VF representor ports */
654 struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
655 pci_dev->device.name);
657 if (pf_ethdev == NULL)
660 for (i = 0; i < eth_da.nb_representor_ports; i++) {
661 struct i40e_vf_representor representor = {
662 .vf_id = eth_da.representor_ports[i],
663 .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
664 pf_ethdev->data->dev_private)->switch_domain_id,
665 .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
666 pf_ethdev->data->dev_private)
669 /* representor port net_bdf_port */
670 snprintf(name, sizeof(name), "net_%s_representor_%d",
671 pci_dev->device.name, eth_da.representor_ports[i]);
673 retval = rte_eth_dev_create(&pci_dev->device, name,
674 sizeof(struct i40e_vf_representor), NULL, NULL,
675 i40e_vf_representor_init, &representor);
678 PMD_DRV_LOG(ERR, "failed to create i40e vf "
679 "representor %s.", name);
685 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
687 struct rte_eth_dev *ethdev;
689 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
694 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
695 return rte_eth_dev_destroy(ethdev, i40e_vf_representor_uninit);
697 return rte_eth_dev_destroy(ethdev, eth_i40e_dev_uninit);
700 static struct rte_pci_driver rte_i40e_pmd = {
701 .id_table = pci_id_i40e_map,
702 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
703 RTE_PCI_DRV_IOVA_AS_VA,
704 .probe = eth_i40e_pci_probe,
705 .remove = eth_i40e_pci_remove,
709 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
712 uint32_t ori_reg_val;
713 struct rte_eth_dev *dev;
715 ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
716 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
717 i40e_write_rx_ctl(hw, reg_addr, reg_val);
718 if (ori_reg_val != reg_val)
720 "i40e device %s changed global register [0x%08x]."
721 " original: 0x%08x, new: 0x%08x",
722 dev->device->name, reg_addr, ori_reg_val, reg_val);
725 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
726 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
727 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
729 #ifndef I40E_GLQF_ORT
730 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
732 #ifndef I40E_GLQF_PIT
733 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
735 #ifndef I40E_GLQF_L3_MAP
736 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
739 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
742 * Initialize registers for parsing packet type of QinQ
743 * This should be removed from code once proper
744 * configuration API is added to avoid configuration conflicts
745 * between ports of the same device.
747 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
748 I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
751 static inline void i40e_config_automask(struct i40e_pf *pf)
753 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
756 /* INTENA flag is not auto-cleared for interrupt */
757 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
758 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
759 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
761 /* If support multi-driver, PF will use INT0. */
762 if (!pf->support_multi_driver)
763 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
765 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
768 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
771 * Add a ethertype filter to drop all flow control frames transmitted
775 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
777 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
778 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
779 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
780 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
783 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
784 I40E_FLOW_CONTROL_ETHERTYPE, flags,
785 pf->main_vsi_seid, 0,
789 "Failed to add filter to drop flow control frames from VSIs.");
793 floating_veb_list_handler(__rte_unused const char *key,
794 const char *floating_veb_value,
798 unsigned int count = 0;
801 bool *vf_floating_veb = opaque;
803 while (isblank(*floating_veb_value))
804 floating_veb_value++;
806 /* Reset floating VEB configuration for VFs */
807 for (idx = 0; idx < I40E_MAX_VF; idx++)
808 vf_floating_veb[idx] = false;
812 while (isblank(*floating_veb_value))
813 floating_veb_value++;
814 if (*floating_veb_value == '\0')
817 idx = strtoul(floating_veb_value, &end, 10);
818 if (errno || end == NULL)
820 while (isblank(*end))
824 } else if ((*end == ';') || (*end == '\0')) {
826 if (min == I40E_MAX_VF)
828 if (max >= I40E_MAX_VF)
829 max = I40E_MAX_VF - 1;
830 for (idx = min; idx <= max; idx++) {
831 vf_floating_veb[idx] = true;
838 floating_veb_value = end + 1;
839 } while (*end != '\0');
848 config_vf_floating_veb(struct rte_devargs *devargs,
849 uint16_t floating_veb,
850 bool *vf_floating_veb)
852 struct rte_kvargs *kvlist;
854 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
858 /* All the VFs attach to the floating VEB by default
859 * when the floating VEB is enabled.
861 for (i = 0; i < I40E_MAX_VF; i++)
862 vf_floating_veb[i] = true;
867 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
871 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
872 rte_kvargs_free(kvlist);
875 /* When the floating_veb_list parameter exists, all the VFs
876 * will attach to the legacy VEB firstly, then configure VFs
877 * to the floating VEB according to the floating_veb_list.
879 if (rte_kvargs_process(kvlist, floating_veb_list,
880 floating_veb_list_handler,
881 vf_floating_veb) < 0) {
882 rte_kvargs_free(kvlist);
885 rte_kvargs_free(kvlist);
889 i40e_check_floating_handler(__rte_unused const char *key,
891 __rte_unused void *opaque)
893 if (strcmp(value, "1"))
900 is_floating_veb_supported(struct rte_devargs *devargs)
902 struct rte_kvargs *kvlist;
903 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
908 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
912 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
913 rte_kvargs_free(kvlist);
916 /* Floating VEB is enabled when there's key-value:
917 * enable_floating_veb=1
919 if (rte_kvargs_process(kvlist, floating_veb_key,
920 i40e_check_floating_handler, NULL) < 0) {
921 rte_kvargs_free(kvlist);
924 rte_kvargs_free(kvlist);
930 config_floating_veb(struct rte_eth_dev *dev)
932 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
933 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
934 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
936 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
938 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
940 is_floating_veb_supported(pci_dev->device.devargs);
941 config_vf_floating_veb(pci_dev->device.devargs,
943 pf->floating_veb_list);
945 pf->floating_veb = false;
949 #define I40E_L2_TAGS_S_TAG_SHIFT 1
950 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
953 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
955 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
956 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
957 char ethertype_hash_name[RTE_HASH_NAMESIZE];
960 struct rte_hash_parameters ethertype_hash_params = {
961 .name = ethertype_hash_name,
962 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
963 .key_len = sizeof(struct i40e_ethertype_filter_input),
964 .hash_func = rte_hash_crc,
965 .hash_func_init_val = 0,
966 .socket_id = rte_socket_id(),
969 /* Initialize ethertype filter rule list and hash */
970 TAILQ_INIT(ðertype_rule->ethertype_list);
971 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
972 "ethertype_%s", dev->device->name);
973 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
974 if (!ethertype_rule->hash_table) {
975 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
978 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
979 sizeof(struct i40e_ethertype_filter *) *
980 I40E_MAX_ETHERTYPE_FILTER_NUM,
982 if (!ethertype_rule->hash_map) {
984 "Failed to allocate memory for ethertype hash map!");
986 goto err_ethertype_hash_map_alloc;
991 err_ethertype_hash_map_alloc:
992 rte_hash_free(ethertype_rule->hash_table);
998 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
1000 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1001 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
1002 char tunnel_hash_name[RTE_HASH_NAMESIZE];
1005 struct rte_hash_parameters tunnel_hash_params = {
1006 .name = tunnel_hash_name,
1007 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1008 .key_len = sizeof(struct i40e_tunnel_filter_input),
1009 .hash_func = rte_hash_crc,
1010 .hash_func_init_val = 0,
1011 .socket_id = rte_socket_id(),
1014 /* Initialize tunnel filter rule list and hash */
1015 TAILQ_INIT(&tunnel_rule->tunnel_list);
1016 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1017 "tunnel_%s", dev->device->name);
1018 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1019 if (!tunnel_rule->hash_table) {
1020 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1023 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1024 sizeof(struct i40e_tunnel_filter *) *
1025 I40E_MAX_TUNNEL_FILTER_NUM,
1027 if (!tunnel_rule->hash_map) {
1029 "Failed to allocate memory for tunnel hash map!");
1031 goto err_tunnel_hash_map_alloc;
1036 err_tunnel_hash_map_alloc:
1037 rte_hash_free(tunnel_rule->hash_table);
1043 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1045 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1046 struct i40e_fdir_info *fdir_info = &pf->fdir;
1047 char fdir_hash_name[RTE_HASH_NAMESIZE];
1050 struct rte_hash_parameters fdir_hash_params = {
1051 .name = fdir_hash_name,
1052 .entries = I40E_MAX_FDIR_FILTER_NUM,
1053 .key_len = sizeof(struct i40e_fdir_input),
1054 .hash_func = rte_hash_crc,
1055 .hash_func_init_val = 0,
1056 .socket_id = rte_socket_id(),
1059 /* Initialize flow director filter rule list and hash */
1060 TAILQ_INIT(&fdir_info->fdir_list);
1061 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1062 "fdir_%s", dev->device->name);
1063 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1064 if (!fdir_info->hash_table) {
1065 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1068 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1069 sizeof(struct i40e_fdir_filter *) *
1070 I40E_MAX_FDIR_FILTER_NUM,
1072 if (!fdir_info->hash_map) {
1074 "Failed to allocate memory for fdir hash map!");
1076 goto err_fdir_hash_map_alloc;
1080 err_fdir_hash_map_alloc:
1081 rte_hash_free(fdir_info->hash_table);
1087 i40e_init_customized_info(struct i40e_pf *pf)
1091 /* Initialize customized pctype */
1092 for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1093 pf->customized_pctype[i].index = i;
1094 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1095 pf->customized_pctype[i].valid = false;
1098 pf->gtp_support = false;
1102 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1104 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1105 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1106 struct i40e_queue_regions *info = &pf->queue_region;
1109 for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1110 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1112 memset(info, 0, sizeof(struct i40e_queue_regions));
1116 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1121 unsigned long support_multi_driver;
1124 pf = (struct i40e_pf *)opaque;
1127 support_multi_driver = strtoul(value, &end, 10);
1128 if (errno != 0 || end == value || *end != 0) {
1129 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1133 if (support_multi_driver == 1 || support_multi_driver == 0)
1134 pf->support_multi_driver = (bool)support_multi_driver;
1136 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1137 "enable global configuration by default."
1138 ETH_I40E_SUPPORT_MULTI_DRIVER);
1143 i40e_support_multi_driver(struct rte_eth_dev *dev)
1145 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1146 struct rte_kvargs *kvlist;
1149 /* Enable global configuration by default */
1150 pf->support_multi_driver = false;
1152 if (!dev->device->devargs)
1155 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1159 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1160 if (!kvargs_count) {
1161 rte_kvargs_free(kvlist);
1165 if (kvargs_count > 1)
1166 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1167 "the first invalid or last valid one is used !",
1168 ETH_I40E_SUPPORT_MULTI_DRIVER);
1170 if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1171 i40e_parse_multi_drv_handler, pf) < 0) {
1172 rte_kvargs_free(kvlist);
1176 rte_kvargs_free(kvlist);
1181 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1182 uint32_t reg_addr, uint64_t reg_val,
1183 struct i40e_asq_cmd_details *cmd_details)
1185 uint64_t ori_reg_val;
1186 struct rte_eth_dev *dev;
1189 ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1190 if (ret != I40E_SUCCESS) {
1192 "Fail to debug read from 0x%08x",
1196 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1198 if (ori_reg_val != reg_val)
1199 PMD_DRV_LOG(WARNING,
1200 "i40e device %s changed global register [0x%08x]."
1201 " original: 0x%"PRIx64", after: 0x%"PRIx64,
1202 dev->device->name, reg_addr, ori_reg_val, reg_val);
1204 return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1208 i40e_parse_latest_vec_handler(__rte_unused const char *key,
1212 struct i40e_adapter *ad;
1215 ad = (struct i40e_adapter *)opaque;
1217 use_latest_vec = atoi(value);
1219 if (use_latest_vec != 0 && use_latest_vec != 1)
1220 PMD_DRV_LOG(WARNING, "Value should be 0 or 1, set it as 1!");
1222 ad->use_latest_vec = (uint8_t)use_latest_vec;
1228 i40e_use_latest_vec(struct rte_eth_dev *dev)
1230 struct i40e_adapter *ad =
1231 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1232 struct rte_kvargs *kvlist;
1235 ad->use_latest_vec = false;
1237 if (!dev->device->devargs)
1240 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1244 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_USE_LATEST_VEC);
1245 if (!kvargs_count) {
1246 rte_kvargs_free(kvlist);
1250 if (kvargs_count > 1)
1251 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1252 "the first invalid or last valid one is used !",
1253 ETH_I40E_USE_LATEST_VEC);
1255 if (rte_kvargs_process(kvlist, ETH_I40E_USE_LATEST_VEC,
1256 i40e_parse_latest_vec_handler, ad) < 0) {
1257 rte_kvargs_free(kvlist);
1261 rte_kvargs_free(kvlist);
1265 #define I40E_ALARM_INTERVAL 50000 /* us */
1268 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1270 struct rte_pci_device *pci_dev;
1271 struct rte_intr_handle *intr_handle;
1272 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1273 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1274 struct i40e_vsi *vsi;
1277 uint8_t aq_fail = 0;
1279 PMD_INIT_FUNC_TRACE();
1281 dev->dev_ops = &i40e_eth_dev_ops;
1282 dev->rx_pkt_burst = i40e_recv_pkts;
1283 dev->tx_pkt_burst = i40e_xmit_pkts;
1284 dev->tx_pkt_prepare = i40e_prep_pkts;
1286 /* for secondary processes, we don't initialise any further as primary
1287 * has already done this work. Only check we don't need a different
1289 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1290 i40e_set_rx_function(dev);
1291 i40e_set_tx_function(dev);
1294 i40e_set_default_ptype_table(dev);
1295 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1296 intr_handle = &pci_dev->intr_handle;
1298 rte_eth_copy_pci_info(dev, pci_dev);
1300 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1301 pf->adapter->eth_dev = dev;
1302 pf->dev_data = dev->data;
1304 hw->back = I40E_PF_TO_ADAPTER(pf);
1305 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1308 "Hardware is not available, as address is NULL");
1312 hw->vendor_id = pci_dev->id.vendor_id;
1313 hw->device_id = pci_dev->id.device_id;
1314 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1315 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1316 hw->bus.device = pci_dev->addr.devid;
1317 hw->bus.func = pci_dev->addr.function;
1318 hw->adapter_stopped = 0;
1321 * Switch Tag value should not be identical to either the First Tag
1322 * or Second Tag values. So set something other than common Ethertype
1323 * for internal switching.
1325 hw->switch_tag = 0xffff;
1327 val = I40E_READ_REG(hw, I40E_GL_FWSTS);
1328 if (val & I40E_GL_FWSTS_FWS1B_MASK) {
1329 PMD_INIT_LOG(ERR, "\nERROR: "
1330 "Firmware recovery mode detected. Limiting functionality.\n"
1331 "Refer to the Intel(R) Ethernet Adapters and Devices "
1332 "User Guide for details on firmware recovery mode.");
1336 /* Check if need to support multi-driver */
1337 i40e_support_multi_driver(dev);
1338 /* Check if users want the latest supported vec path */
1339 i40e_use_latest_vec(dev);
1341 /* Make sure all is clean before doing PF reset */
1344 /* Reset here to make sure all is clean for each PF */
1345 ret = i40e_pf_reset(hw);
1347 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1351 /* Initialize the shared code (base driver) */
1352 ret = i40e_init_shared_code(hw);
1354 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1358 /* Initialize the parameters for adminq */
1359 i40e_init_adminq_parameter(hw);
1360 ret = i40e_init_adminq(hw);
1361 if (ret != I40E_SUCCESS) {
1362 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1365 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1366 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1367 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1368 ((hw->nvm.version >> 12) & 0xf),
1369 ((hw->nvm.version >> 4) & 0xff),
1370 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1372 /* Initialize the hardware */
1375 i40e_config_automask(pf);
1377 i40e_set_default_pctype_table(dev);
1380 * To work around the NVM issue, initialize registers
1381 * for packet type of QinQ by software.
1382 * It should be removed once issues are fixed in NVM.
1384 if (!pf->support_multi_driver)
1385 i40e_GLQF_reg_init(hw);
1387 /* Initialize the input set for filters (hash and fd) to default value */
1388 i40e_filter_input_set_init(pf);
1390 /* initialise the L3_MAP register */
1391 if (!pf->support_multi_driver) {
1392 ret = i40e_aq_debug_write_global_register(hw,
1393 I40E_GLQF_L3_MAP(40),
1396 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1399 "Global register 0x%08x is changed with 0x28",
1400 I40E_GLQF_L3_MAP(40));
1403 /* Need the special FW version to support floating VEB */
1404 config_floating_veb(dev);
1405 /* Clear PXE mode */
1406 i40e_clear_pxe_mode(hw);
1407 i40e_dev_sync_phy_type(hw);
1410 * On X710, performance number is far from the expectation on recent
1411 * firmware versions. The fix for this issue may not be integrated in
1412 * the following firmware version. So the workaround in software driver
1413 * is needed. It needs to modify the initial values of 3 internal only
1414 * registers. Note that the workaround can be removed when it is fixed
1415 * in firmware in the future.
1417 i40e_configure_registers(hw);
1419 /* Get hw capabilities */
1420 ret = i40e_get_cap(hw);
1421 if (ret != I40E_SUCCESS) {
1422 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1423 goto err_get_capabilities;
1426 /* Initialize parameters for PF */
1427 ret = i40e_pf_parameter_init(dev);
1429 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1430 goto err_parameter_init;
1433 /* Initialize the queue management */
1434 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1436 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1437 goto err_qp_pool_init;
1439 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1440 hw->func_caps.num_msix_vectors - 1);
1442 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1443 goto err_msix_pool_init;
1446 /* Initialize lan hmc */
1447 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1448 hw->func_caps.num_rx_qp, 0, 0);
1449 if (ret != I40E_SUCCESS) {
1450 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1451 goto err_init_lan_hmc;
1454 /* Configure lan hmc */
1455 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1456 if (ret != I40E_SUCCESS) {
1457 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1458 goto err_configure_lan_hmc;
1461 /* Get and check the mac address */
1462 i40e_get_mac_addr(hw, hw->mac.addr);
1463 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1464 PMD_INIT_LOG(ERR, "mac address is not valid");
1466 goto err_get_mac_addr;
1468 /* Copy the permanent MAC address */
1469 ether_addr_copy((struct ether_addr *) hw->mac.addr,
1470 (struct ether_addr *) hw->mac.perm_addr);
1472 /* Disable flow control */
1473 hw->fc.requested_mode = I40E_FC_NONE;
1474 i40e_set_fc(hw, &aq_fail, TRUE);
1476 /* Set the global registers with default ether type value */
1477 if (!pf->support_multi_driver) {
1478 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1480 if (ret != I40E_SUCCESS) {
1482 "Failed to set the default outer "
1484 goto err_setup_pf_switch;
1488 /* PF setup, which includes VSI setup */
1489 ret = i40e_pf_setup(pf);
1491 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1492 goto err_setup_pf_switch;
1495 /* reset all stats of the device, including pf and main vsi */
1496 i40e_dev_stats_reset(dev);
1500 /* Disable double vlan by default */
1501 i40e_vsi_config_double_vlan(vsi, FALSE);
1503 /* Disable S-TAG identification when floating_veb is disabled */
1504 if (!pf->floating_veb) {
1505 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1506 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1507 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1508 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1512 if (!vsi->max_macaddrs)
1513 len = ETHER_ADDR_LEN;
1515 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1517 /* Should be after VSI initialized */
1518 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1519 if (!dev->data->mac_addrs) {
1521 "Failed to allocated memory for storing mac address");
1524 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1525 &dev->data->mac_addrs[0]);
1527 /* Init dcb to sw mode by default */
1528 ret = i40e_dcb_init_configure(dev, TRUE);
1529 if (ret != I40E_SUCCESS) {
1530 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1531 pf->flags &= ~I40E_FLAG_DCB;
1533 /* Update HW struct after DCB configuration */
1536 /* initialize pf host driver to setup SRIOV resource if applicable */
1537 i40e_pf_host_init(dev);
1539 /* register callback func to eal lib */
1540 rte_intr_callback_register(intr_handle,
1541 i40e_dev_interrupt_handler, dev);
1543 /* configure and enable device interrupt */
1544 i40e_pf_config_irq0(hw, TRUE);
1545 i40e_pf_enable_irq0(hw);
1547 /* enable uio intr after callback register */
1548 rte_intr_enable(intr_handle);
1550 /* By default disable flexible payload in global configuration */
1551 if (!pf->support_multi_driver)
1552 i40e_flex_payload_reg_set_default(hw);
1555 * Add an ethertype filter to drop all flow control frames transmitted
1556 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1559 i40e_add_tx_flow_control_drop_filter(pf);
1561 /* Set the max frame size to 0x2600 by default,
1562 * in case other drivers changed the default value.
1564 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1566 /* initialize mirror rule list */
1567 TAILQ_INIT(&pf->mirror_list);
1569 /* initialize Traffic Manager configuration */
1570 i40e_tm_conf_init(dev);
1572 /* Initialize customized information */
1573 i40e_init_customized_info(pf);
1575 ret = i40e_init_ethtype_filter_list(dev);
1577 goto err_init_ethtype_filter_list;
1578 ret = i40e_init_tunnel_filter_list(dev);
1580 goto err_init_tunnel_filter_list;
1581 ret = i40e_init_fdir_filter_list(dev);
1583 goto err_init_fdir_filter_list;
1585 /* initialize queue region configuration */
1586 i40e_init_queue_region_conf(dev);
1588 /* initialize rss configuration from rte_flow */
1589 memset(&pf->rss_info, 0,
1590 sizeof(struct i40e_rte_flow_rss_conf));
1594 err_init_fdir_filter_list:
1595 rte_free(pf->tunnel.hash_table);
1596 rte_free(pf->tunnel.hash_map);
1597 err_init_tunnel_filter_list:
1598 rte_free(pf->ethertype.hash_table);
1599 rte_free(pf->ethertype.hash_map);
1600 err_init_ethtype_filter_list:
1601 rte_free(dev->data->mac_addrs);
1603 i40e_vsi_release(pf->main_vsi);
1604 err_setup_pf_switch:
1606 err_configure_lan_hmc:
1607 (void)i40e_shutdown_lan_hmc(hw);
1609 i40e_res_pool_destroy(&pf->msix_pool);
1611 i40e_res_pool_destroy(&pf->qp_pool);
1614 err_get_capabilities:
1615 (void)i40e_shutdown_adminq(hw);
1621 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1623 struct i40e_ethertype_filter *p_ethertype;
1624 struct i40e_ethertype_rule *ethertype_rule;
1626 ethertype_rule = &pf->ethertype;
1627 /* Remove all ethertype filter rules and hash */
1628 if (ethertype_rule->hash_map)
1629 rte_free(ethertype_rule->hash_map);
1630 if (ethertype_rule->hash_table)
1631 rte_hash_free(ethertype_rule->hash_table);
1633 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1634 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1635 p_ethertype, rules);
1636 rte_free(p_ethertype);
1641 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1643 struct i40e_tunnel_filter *p_tunnel;
1644 struct i40e_tunnel_rule *tunnel_rule;
1646 tunnel_rule = &pf->tunnel;
1647 /* Remove all tunnel director rules and hash */
1648 if (tunnel_rule->hash_map)
1649 rte_free(tunnel_rule->hash_map);
1650 if (tunnel_rule->hash_table)
1651 rte_hash_free(tunnel_rule->hash_table);
1653 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1654 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1660 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1662 struct i40e_fdir_filter *p_fdir;
1663 struct i40e_fdir_info *fdir_info;
1665 fdir_info = &pf->fdir;
1666 /* Remove all flow director rules and hash */
1667 if (fdir_info->hash_map)
1668 rte_free(fdir_info->hash_map);
1669 if (fdir_info->hash_table)
1670 rte_hash_free(fdir_info->hash_table);
1672 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1673 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1678 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1681 * Disable by default flexible payload
1682 * for corresponding L2/L3/L4 layers.
1684 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1685 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1686 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1690 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1693 struct rte_pci_device *pci_dev;
1694 struct rte_intr_handle *intr_handle;
1696 struct i40e_filter_control_settings settings;
1697 struct rte_flow *p_flow;
1699 uint8_t aq_fail = 0;
1702 PMD_INIT_FUNC_TRACE();
1704 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1707 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1708 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1709 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1710 intr_handle = &pci_dev->intr_handle;
1712 ret = rte_eth_switch_domain_free(pf->switch_domain_id);
1714 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
1716 if (hw->adapter_stopped == 0)
1717 i40e_dev_close(dev);
1719 dev->dev_ops = NULL;
1720 dev->rx_pkt_burst = NULL;
1721 dev->tx_pkt_burst = NULL;
1723 /* Clear PXE mode */
1724 i40e_clear_pxe_mode(hw);
1726 /* Unconfigure filter control */
1727 memset(&settings, 0, sizeof(settings));
1728 ret = i40e_set_filter_control(hw, &settings);
1730 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1733 /* Disable flow control */
1734 hw->fc.requested_mode = I40E_FC_NONE;
1735 i40e_set_fc(hw, &aq_fail, TRUE);
1737 /* uninitialize pf host driver */
1738 i40e_pf_host_uninit(dev);
1740 /* disable uio intr before callback unregister */
1741 rte_intr_disable(intr_handle);
1743 /* unregister callback func to eal lib */
1745 ret = rte_intr_callback_unregister(intr_handle,
1746 i40e_dev_interrupt_handler, dev);
1749 } else if (ret != -EAGAIN) {
1751 "intr callback unregister failed: %d",
1755 i40e_msec_delay(500);
1756 } while (retries++ < 5);
1758 i40e_rm_ethtype_filter_list(pf);
1759 i40e_rm_tunnel_filter_list(pf);
1760 i40e_rm_fdir_filter_list(pf);
1762 /* Remove all flows */
1763 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1764 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1768 /* Remove all Traffic Manager configuration */
1769 i40e_tm_conf_uninit(dev);
1775 i40e_dev_configure(struct rte_eth_dev *dev)
1777 struct i40e_adapter *ad =
1778 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1779 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1780 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1781 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1784 ret = i40e_dev_sync_phy_type(hw);
1788 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1789 * bulk allocation or vector Rx preconditions we will reset it.
1791 ad->rx_bulk_alloc_allowed = true;
1792 ad->rx_vec_allowed = true;
1793 ad->tx_simple_allowed = true;
1794 ad->tx_vec_allowed = true;
1796 /* Only legacy filter API needs the following fdir config. So when the
1797 * legacy filter API is deprecated, the following codes should also be
1800 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1801 ret = i40e_fdir_setup(pf);
1802 if (ret != I40E_SUCCESS) {
1803 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1806 ret = i40e_fdir_configure(dev);
1808 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1812 i40e_fdir_teardown(pf);
1814 ret = i40e_dev_init_vlan(dev);
1819 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1820 * RSS setting have different requirements.
1821 * General PMD driver call sequence are NIC init, configure,
1822 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1823 * will try to lookup the VSI that specific queue belongs to if VMDQ
1824 * applicable. So, VMDQ setting has to be done before
1825 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1826 * For RSS setting, it will try to calculate actual configured RX queue
1827 * number, which will be available after rx_queue_setup(). dev_start()
1828 * function is good to place RSS setup.
1830 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1831 ret = i40e_vmdq_setup(dev);
1836 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1837 ret = i40e_dcb_setup(dev);
1839 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1844 TAILQ_INIT(&pf->flow_list);
1849 /* need to release vmdq resource if exists */
1850 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1851 i40e_vsi_release(pf->vmdq[i].vsi);
1852 pf->vmdq[i].vsi = NULL;
1857 /* Need to release fdir resource if exists.
1858 * Only legacy filter API needs the following fdir config. So when the
1859 * legacy filter API is deprecated, the following code should also be
1862 i40e_fdir_teardown(pf);
1867 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1869 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1870 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1871 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1872 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1873 uint16_t msix_vect = vsi->msix_intr;
1876 for (i = 0; i < vsi->nb_qps; i++) {
1877 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1878 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1882 if (vsi->type != I40E_VSI_SRIOV) {
1883 if (!rte_intr_allow_others(intr_handle)) {
1884 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1885 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1887 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1890 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1891 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1893 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1898 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1899 vsi->user_param + (msix_vect - 1);
1901 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1902 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1904 I40E_WRITE_FLUSH(hw);
1908 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1909 int base_queue, int nb_queue,
1914 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1915 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1917 /* Bind all RX queues to allocated MSIX interrupt */
1918 for (i = 0; i < nb_queue; i++) {
1919 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1920 itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1921 ((base_queue + i + 1) <<
1922 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1923 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1924 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1926 if (i == nb_queue - 1)
1927 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1928 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1931 /* Write first RX queue to Link list register as the head element */
1932 if (vsi->type != I40E_VSI_SRIOV) {
1934 i40e_calc_itr_interval(1, pf->support_multi_driver);
1936 if (msix_vect == I40E_MISC_VEC_ID) {
1937 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1939 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1941 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1943 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1946 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1948 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1950 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1952 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1959 if (msix_vect == I40E_MISC_VEC_ID) {
1961 I40E_VPINT_LNKLST0(vsi->user_param),
1963 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1965 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1967 /* num_msix_vectors_vf needs to minus irq0 */
1968 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1969 vsi->user_param + (msix_vect - 1);
1971 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1973 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1975 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1979 I40E_WRITE_FLUSH(hw);
1983 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1985 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1986 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1987 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1988 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1989 uint16_t msix_vect = vsi->msix_intr;
1990 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1991 uint16_t queue_idx = 0;
1995 for (i = 0; i < vsi->nb_qps; i++) {
1996 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1997 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2000 /* VF bind interrupt */
2001 if (vsi->type == I40E_VSI_SRIOV) {
2002 __vsi_queues_bind_intr(vsi, msix_vect,
2003 vsi->base_queue, vsi->nb_qps,
2008 /* PF & VMDq bind interrupt */
2009 if (rte_intr_dp_is_en(intr_handle)) {
2010 if (vsi->type == I40E_VSI_MAIN) {
2013 } else if (vsi->type == I40E_VSI_VMDQ2) {
2014 struct i40e_vsi *main_vsi =
2015 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2016 queue_idx = vsi->base_queue - main_vsi->nb_qps;
2021 for (i = 0; i < vsi->nb_used_qps; i++) {
2023 if (!rte_intr_allow_others(intr_handle))
2024 /* allow to share MISC_VEC_ID */
2025 msix_vect = I40E_MISC_VEC_ID;
2027 /* no enough msix_vect, map all to one */
2028 __vsi_queues_bind_intr(vsi, msix_vect,
2029 vsi->base_queue + i,
2030 vsi->nb_used_qps - i,
2032 for (; !!record && i < vsi->nb_used_qps; i++)
2033 intr_handle->intr_vec[queue_idx + i] =
2037 /* 1:1 queue/msix_vect mapping */
2038 __vsi_queues_bind_intr(vsi, msix_vect,
2039 vsi->base_queue + i, 1,
2042 intr_handle->intr_vec[queue_idx + i] = msix_vect;
2050 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2052 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2053 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2054 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2055 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2056 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2057 uint16_t msix_intr, i;
2059 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2060 for (i = 0; i < vsi->nb_msix; i++) {
2061 msix_intr = vsi->msix_intr + i;
2062 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2063 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2064 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2065 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2068 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2069 I40E_PFINT_DYN_CTL0_INTENA_MASK |
2070 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2071 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2073 I40E_WRITE_FLUSH(hw);
2077 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2079 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2080 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2081 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2082 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2083 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2084 uint16_t msix_intr, i;
2086 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2087 for (i = 0; i < vsi->nb_msix; i++) {
2088 msix_intr = vsi->msix_intr + i;
2089 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2090 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2093 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2094 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2096 I40E_WRITE_FLUSH(hw);
2099 static inline uint8_t
2100 i40e_parse_link_speeds(uint16_t link_speeds)
2102 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2104 if (link_speeds & ETH_LINK_SPEED_40G)
2105 link_speed |= I40E_LINK_SPEED_40GB;
2106 if (link_speeds & ETH_LINK_SPEED_25G)
2107 link_speed |= I40E_LINK_SPEED_25GB;
2108 if (link_speeds & ETH_LINK_SPEED_20G)
2109 link_speed |= I40E_LINK_SPEED_20GB;
2110 if (link_speeds & ETH_LINK_SPEED_10G)
2111 link_speed |= I40E_LINK_SPEED_10GB;
2112 if (link_speeds & ETH_LINK_SPEED_1G)
2113 link_speed |= I40E_LINK_SPEED_1GB;
2114 if (link_speeds & ETH_LINK_SPEED_100M)
2115 link_speed |= I40E_LINK_SPEED_100MB;
2121 i40e_phy_conf_link(struct i40e_hw *hw,
2123 uint8_t force_speed,
2126 enum i40e_status_code status;
2127 struct i40e_aq_get_phy_abilities_resp phy_ab;
2128 struct i40e_aq_set_phy_config phy_conf;
2129 enum i40e_aq_phy_type cnt;
2130 uint8_t avail_speed;
2131 uint32_t phy_type_mask = 0;
2133 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2134 I40E_AQ_PHY_FLAG_PAUSE_RX |
2135 I40E_AQ_PHY_FLAG_PAUSE_RX |
2136 I40E_AQ_PHY_FLAG_LOW_POWER;
2139 /* To get phy capabilities of available speeds. */
2140 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2143 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2147 avail_speed = phy_ab.link_speed;
2149 /* To get the current phy config. */
2150 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2153 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2158 /* If link needs to go up and it is in autoneg mode the speed is OK,
2159 * no need to set up again.
2161 if (is_up && phy_ab.phy_type != 0 &&
2162 abilities & I40E_AQ_PHY_AN_ENABLED &&
2163 phy_ab.link_speed != 0)
2164 return I40E_SUCCESS;
2166 memset(&phy_conf, 0, sizeof(phy_conf));
2168 /* bits 0-2 use the values from get_phy_abilities_resp */
2170 abilities |= phy_ab.abilities & mask;
2172 phy_conf.abilities = abilities;
2174 /* If link needs to go up, but the force speed is not supported,
2175 * Warn users and config the default available speeds.
2177 if (is_up && !(force_speed & avail_speed)) {
2178 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2179 phy_conf.link_speed = avail_speed;
2181 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2184 /* PHY type mask needs to include each type except PHY type extension */
2185 for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2186 phy_type_mask |= 1 << cnt;
2188 /* use get_phy_abilities_resp value for the rest */
2189 phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2190 phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2191 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2192 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2193 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2194 phy_conf.eee_capability = phy_ab.eee_capability;
2195 phy_conf.eeer = phy_ab.eeer_val;
2196 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2198 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2199 phy_ab.abilities, phy_ab.link_speed);
2200 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
2201 phy_conf.abilities, phy_conf.link_speed);
2203 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2207 return I40E_SUCCESS;
2211 i40e_apply_link_speed(struct rte_eth_dev *dev)
2214 uint8_t abilities = 0;
2215 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2216 struct rte_eth_conf *conf = &dev->data->dev_conf;
2218 if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2219 conf->link_speeds = ETH_LINK_SPEED_40G |
2220 ETH_LINK_SPEED_25G |
2221 ETH_LINK_SPEED_20G |
2222 ETH_LINK_SPEED_10G |
2224 ETH_LINK_SPEED_100M;
2226 speed = i40e_parse_link_speeds(conf->link_speeds);
2227 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2228 I40E_AQ_PHY_AN_ENABLED |
2229 I40E_AQ_PHY_LINK_ENABLED;
2231 return i40e_phy_conf_link(hw, abilities, speed, true);
2235 i40e_dev_start(struct rte_eth_dev *dev)
2237 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2238 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2239 struct i40e_vsi *main_vsi = pf->main_vsi;
2241 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2242 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2243 uint32_t intr_vector = 0;
2244 struct i40e_vsi *vsi;
2246 hw->adapter_stopped = 0;
2248 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2250 "Invalid link_speeds for port %u, autonegotiation disabled",
2251 dev->data->port_id);
2255 rte_intr_disable(intr_handle);
2257 if ((rte_intr_cap_multiple(intr_handle) ||
2258 !RTE_ETH_DEV_SRIOV(dev).active) &&
2259 dev->data->dev_conf.intr_conf.rxq != 0) {
2260 intr_vector = dev->data->nb_rx_queues;
2261 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2266 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2267 intr_handle->intr_vec =
2268 rte_zmalloc("intr_vec",
2269 dev->data->nb_rx_queues * sizeof(int),
2271 if (!intr_handle->intr_vec) {
2273 "Failed to allocate %d rx_queues intr_vec",
2274 dev->data->nb_rx_queues);
2279 /* Initialize VSI */
2280 ret = i40e_dev_rxtx_init(pf);
2281 if (ret != I40E_SUCCESS) {
2282 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2286 /* Map queues with MSIX interrupt */
2287 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2288 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2289 i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2290 i40e_vsi_enable_queues_intr(main_vsi);
2292 /* Map VMDQ VSI queues with MSIX interrupt */
2293 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2294 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2295 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2296 I40E_ITR_INDEX_DEFAULT);
2297 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2300 /* enable FDIR MSIX interrupt */
2301 if (pf->fdir.fdir_vsi) {
2302 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2303 I40E_ITR_INDEX_NONE);
2304 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2307 /* Enable all queues which have been configured */
2308 ret = i40e_dev_switch_queues(pf, TRUE);
2309 if (ret != I40E_SUCCESS) {
2310 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2314 /* Enable receiving broadcast packets */
2315 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2316 if (ret != I40E_SUCCESS)
2317 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2319 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2320 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2322 if (ret != I40E_SUCCESS)
2323 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2326 /* Enable the VLAN promiscuous mode. */
2328 for (i = 0; i < pf->vf_num; i++) {
2329 vsi = pf->vfs[i].vsi;
2330 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2335 /* Enable mac loopback mode */
2336 if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2337 dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2338 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2339 if (ret != I40E_SUCCESS) {
2340 PMD_DRV_LOG(ERR, "fail to set loopback link");
2345 /* Apply link configure */
2346 ret = i40e_apply_link_speed(dev);
2347 if (I40E_SUCCESS != ret) {
2348 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2352 if (!rte_intr_allow_others(intr_handle)) {
2353 rte_intr_callback_unregister(intr_handle,
2354 i40e_dev_interrupt_handler,
2356 /* configure and enable device interrupt */
2357 i40e_pf_config_irq0(hw, FALSE);
2358 i40e_pf_enable_irq0(hw);
2360 if (dev->data->dev_conf.intr_conf.lsc != 0)
2362 "lsc won't enable because of no intr multiplex");
2364 ret = i40e_aq_set_phy_int_mask(hw,
2365 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2366 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2367 I40E_AQ_EVENT_MEDIA_NA), NULL);
2368 if (ret != I40E_SUCCESS)
2369 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2371 /* Call get_link_info aq commond to enable/disable LSE */
2372 i40e_dev_link_update(dev, 0);
2375 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2376 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2377 i40e_dev_alarm_handler, dev);
2379 /* enable uio intr after callback register */
2380 rte_intr_enable(intr_handle);
2383 i40e_filter_restore(pf);
2385 if (pf->tm_conf.root && !pf->tm_conf.committed)
2386 PMD_DRV_LOG(WARNING,
2387 "please call hierarchy_commit() "
2388 "before starting the port");
2390 return I40E_SUCCESS;
2393 i40e_dev_switch_queues(pf, FALSE);
2394 i40e_dev_clear_queues(dev);
2400 i40e_dev_stop(struct rte_eth_dev *dev)
2402 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2403 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2404 struct i40e_vsi *main_vsi = pf->main_vsi;
2405 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2406 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2409 if (hw->adapter_stopped == 1)
2412 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2413 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2414 rte_intr_enable(intr_handle);
2417 /* Disable all queues */
2418 i40e_dev_switch_queues(pf, FALSE);
2420 /* un-map queues with interrupt registers */
2421 i40e_vsi_disable_queues_intr(main_vsi);
2422 i40e_vsi_queues_unbind_intr(main_vsi);
2424 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2425 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2426 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2429 if (pf->fdir.fdir_vsi) {
2430 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2431 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2433 /* Clear all queues and release memory */
2434 i40e_dev_clear_queues(dev);
2437 i40e_dev_set_link_down(dev);
2439 if (!rte_intr_allow_others(intr_handle))
2440 /* resume to the default handler */
2441 rte_intr_callback_register(intr_handle,
2442 i40e_dev_interrupt_handler,
2445 /* Clean datapath event and queue/vec mapping */
2446 rte_intr_efd_disable(intr_handle);
2447 if (intr_handle->intr_vec) {
2448 rte_free(intr_handle->intr_vec);
2449 intr_handle->intr_vec = NULL;
2452 /* reset hierarchy commit */
2453 pf->tm_conf.committed = false;
2455 hw->adapter_stopped = 1;
2457 pf->adapter->rss_reta_updated = 0;
2461 i40e_dev_close(struct rte_eth_dev *dev)
2463 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2464 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2465 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2466 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2467 struct i40e_mirror_rule *p_mirror;
2472 PMD_INIT_FUNC_TRACE();
2476 /* Remove all mirror rules */
2477 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2478 ret = i40e_aq_del_mirror_rule(hw,
2479 pf->main_vsi->veb->seid,
2480 p_mirror->rule_type,
2482 p_mirror->num_entries,
2485 PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2486 "status = %d, aq_err = %d.", ret,
2487 hw->aq.asq_last_status);
2489 /* remove mirror software resource anyway */
2490 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2492 pf->nb_mirror_rule--;
2495 i40e_dev_free_queues(dev);
2497 /* Disable interrupt */
2498 i40e_pf_disable_irq0(hw);
2499 rte_intr_disable(intr_handle);
2502 * Only legacy filter API needs the following fdir config. So when the
2503 * legacy filter API is deprecated, the following code should also be
2506 i40e_fdir_teardown(pf);
2508 /* shutdown and destroy the HMC */
2509 i40e_shutdown_lan_hmc(hw);
2511 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2512 i40e_vsi_release(pf->vmdq[i].vsi);
2513 pf->vmdq[i].vsi = NULL;
2518 /* release all the existing VSIs and VEBs */
2519 i40e_vsi_release(pf->main_vsi);
2521 /* shutdown the adminq */
2522 i40e_aq_queue_shutdown(hw, true);
2523 i40e_shutdown_adminq(hw);
2525 i40e_res_pool_destroy(&pf->qp_pool);
2526 i40e_res_pool_destroy(&pf->msix_pool);
2528 /* Disable flexible payload in global configuration */
2529 if (!pf->support_multi_driver)
2530 i40e_flex_payload_reg_set_default(hw);
2532 /* force a PF reset to clean anything leftover */
2533 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2534 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2535 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2536 I40E_WRITE_FLUSH(hw);
2540 * Reset PF device only to re-initialize resources in PMD layer
2543 i40e_dev_reset(struct rte_eth_dev *dev)
2547 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2548 * its VF to make them align with it. The detailed notification
2549 * mechanism is PMD specific. As to i40e PF, it is rather complex.
2550 * To avoid unexpected behavior in VF, currently reset of PF with
2551 * SR-IOV activation is not supported. It might be supported later.
2553 if (dev->data->sriov.active)
2556 ret = eth_i40e_dev_uninit(dev);
2560 ret = eth_i40e_dev_init(dev, NULL);
2566 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2568 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2569 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2570 struct i40e_vsi *vsi = pf->main_vsi;
2573 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2575 if (status != I40E_SUCCESS)
2576 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2578 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2580 if (status != I40E_SUCCESS)
2581 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2586 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2588 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2589 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2590 struct i40e_vsi *vsi = pf->main_vsi;
2593 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2595 if (status != I40E_SUCCESS)
2596 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2598 /* must remain in all_multicast mode */
2599 if (dev->data->all_multicast == 1)
2602 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2604 if (status != I40E_SUCCESS)
2605 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2609 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2611 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2612 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2613 struct i40e_vsi *vsi = pf->main_vsi;
2616 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2617 if (ret != I40E_SUCCESS)
2618 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2622 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2624 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2625 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2626 struct i40e_vsi *vsi = pf->main_vsi;
2629 if (dev->data->promiscuous == 1)
2630 return; /* must remain in all_multicast mode */
2632 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2633 vsi->seid, FALSE, NULL);
2634 if (ret != I40E_SUCCESS)
2635 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2639 * Set device link up.
2642 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2644 /* re-apply link speed setting */
2645 return i40e_apply_link_speed(dev);
2649 * Set device link down.
2652 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2654 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2655 uint8_t abilities = 0;
2656 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2658 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2659 return i40e_phy_conf_link(hw, abilities, speed, false);
2662 static __rte_always_inline void
2663 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2665 /* Link status registers and values*/
2666 #define I40E_PRTMAC_LINKSTA 0x001E2420
2667 #define I40E_REG_LINK_UP 0x40000080
2668 #define I40E_PRTMAC_MACC 0x001E24E0
2669 #define I40E_REG_MACC_25GB 0x00020000
2670 #define I40E_REG_SPEED_MASK 0x38000000
2671 #define I40E_REG_SPEED_100MB 0x00000000
2672 #define I40E_REG_SPEED_1GB 0x08000000
2673 #define I40E_REG_SPEED_10GB 0x10000000
2674 #define I40E_REG_SPEED_20GB 0x20000000
2675 #define I40E_REG_SPEED_25_40GB 0x18000000
2676 uint32_t link_speed;
2679 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2680 link_speed = reg_val & I40E_REG_SPEED_MASK;
2681 reg_val &= I40E_REG_LINK_UP;
2682 link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2684 if (unlikely(link->link_status == 0))
2687 /* Parse the link status */
2688 switch (link_speed) {
2689 case I40E_REG_SPEED_100MB:
2690 link->link_speed = ETH_SPEED_NUM_100M;
2692 case I40E_REG_SPEED_1GB:
2693 link->link_speed = ETH_SPEED_NUM_1G;
2695 case I40E_REG_SPEED_10GB:
2696 link->link_speed = ETH_SPEED_NUM_10G;
2698 case I40E_REG_SPEED_20GB:
2699 link->link_speed = ETH_SPEED_NUM_20G;
2701 case I40E_REG_SPEED_25_40GB:
2702 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2704 if (reg_val & I40E_REG_MACC_25GB)
2705 link->link_speed = ETH_SPEED_NUM_25G;
2707 link->link_speed = ETH_SPEED_NUM_40G;
2711 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2716 static __rte_always_inline void
2717 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2718 bool enable_lse, int wait_to_complete)
2720 #define CHECK_INTERVAL 100 /* 100ms */
2721 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2722 uint32_t rep_cnt = MAX_REPEAT_TIME;
2723 struct i40e_link_status link_status;
2726 memset(&link_status, 0, sizeof(link_status));
2729 memset(&link_status, 0, sizeof(link_status));
2731 /* Get link status information from hardware */
2732 status = i40e_aq_get_link_info(hw, enable_lse,
2733 &link_status, NULL);
2734 if (unlikely(status != I40E_SUCCESS)) {
2735 link->link_speed = ETH_SPEED_NUM_100M;
2736 link->link_duplex = ETH_LINK_FULL_DUPLEX;
2737 PMD_DRV_LOG(ERR, "Failed to get link info");
2741 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2742 if (!wait_to_complete || link->link_status)
2745 rte_delay_ms(CHECK_INTERVAL);
2746 } while (--rep_cnt);
2748 /* Parse the link status */
2749 switch (link_status.link_speed) {
2750 case I40E_LINK_SPEED_100MB:
2751 link->link_speed = ETH_SPEED_NUM_100M;
2753 case I40E_LINK_SPEED_1GB:
2754 link->link_speed = ETH_SPEED_NUM_1G;
2756 case I40E_LINK_SPEED_10GB:
2757 link->link_speed = ETH_SPEED_NUM_10G;
2759 case I40E_LINK_SPEED_20GB:
2760 link->link_speed = ETH_SPEED_NUM_20G;
2762 case I40E_LINK_SPEED_25GB:
2763 link->link_speed = ETH_SPEED_NUM_25G;
2765 case I40E_LINK_SPEED_40GB:
2766 link->link_speed = ETH_SPEED_NUM_40G;
2769 link->link_speed = ETH_SPEED_NUM_100M;
2775 i40e_dev_link_update(struct rte_eth_dev *dev,
2776 int wait_to_complete)
2778 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2779 struct rte_eth_link link;
2780 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2783 memset(&link, 0, sizeof(link));
2785 /* i40e uses full duplex only */
2786 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2787 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2788 ETH_LINK_SPEED_FIXED);
2790 if (!wait_to_complete && !enable_lse)
2791 update_link_reg(hw, &link);
2793 update_link_aq(hw, &link, enable_lse, wait_to_complete);
2795 ret = rte_eth_linkstatus_set(dev, &link);
2796 i40e_notify_all_vfs_link_status(dev);
2801 /* Get all the statistics of a VSI */
2803 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2805 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2806 struct i40e_eth_stats *nes = &vsi->eth_stats;
2807 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2808 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2810 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2811 vsi->offset_loaded, &oes->rx_bytes,
2813 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2814 vsi->offset_loaded, &oes->rx_unicast,
2816 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2817 vsi->offset_loaded, &oes->rx_multicast,
2818 &nes->rx_multicast);
2819 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2820 vsi->offset_loaded, &oes->rx_broadcast,
2821 &nes->rx_broadcast);
2822 /* exclude CRC bytes */
2823 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2824 nes->rx_broadcast) * ETHER_CRC_LEN;
2826 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2827 &oes->rx_discards, &nes->rx_discards);
2828 /* GLV_REPC not supported */
2829 /* GLV_RMPC not supported */
2830 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2831 &oes->rx_unknown_protocol,
2832 &nes->rx_unknown_protocol);
2833 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2834 vsi->offset_loaded, &oes->tx_bytes,
2836 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2837 vsi->offset_loaded, &oes->tx_unicast,
2839 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2840 vsi->offset_loaded, &oes->tx_multicast,
2841 &nes->tx_multicast);
2842 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2843 vsi->offset_loaded, &oes->tx_broadcast,
2844 &nes->tx_broadcast);
2845 /* GLV_TDPC not supported */
2846 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2847 &oes->tx_errors, &nes->tx_errors);
2848 vsi->offset_loaded = true;
2850 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2852 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2853 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2854 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2855 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2856 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2857 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2858 nes->rx_unknown_protocol);
2859 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2860 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2861 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2862 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2863 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2864 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2865 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2870 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2873 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2874 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2876 /* Get rx/tx bytes of internal transfer packets */
2877 i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2878 I40E_GLV_GORCL(hw->port),
2880 &pf->internal_stats_offset.rx_bytes,
2881 &pf->internal_stats.rx_bytes);
2883 i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2884 I40E_GLV_GOTCL(hw->port),
2886 &pf->internal_stats_offset.tx_bytes,
2887 &pf->internal_stats.tx_bytes);
2888 /* Get total internal rx packet count */
2889 i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2890 I40E_GLV_UPRCL(hw->port),
2892 &pf->internal_stats_offset.rx_unicast,
2893 &pf->internal_stats.rx_unicast);
2894 i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2895 I40E_GLV_MPRCL(hw->port),
2897 &pf->internal_stats_offset.rx_multicast,
2898 &pf->internal_stats.rx_multicast);
2899 i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2900 I40E_GLV_BPRCL(hw->port),
2902 &pf->internal_stats_offset.rx_broadcast,
2903 &pf->internal_stats.rx_broadcast);
2904 /* Get total internal tx packet count */
2905 i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
2906 I40E_GLV_UPTCL(hw->port),
2908 &pf->internal_stats_offset.tx_unicast,
2909 &pf->internal_stats.tx_unicast);
2910 i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
2911 I40E_GLV_MPTCL(hw->port),
2913 &pf->internal_stats_offset.tx_multicast,
2914 &pf->internal_stats.tx_multicast);
2915 i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
2916 I40E_GLV_BPTCL(hw->port),
2918 &pf->internal_stats_offset.tx_broadcast,
2919 &pf->internal_stats.tx_broadcast);
2921 /* exclude CRC size */
2922 pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2923 pf->internal_stats.rx_multicast +
2924 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2926 /* Get statistics of struct i40e_eth_stats */
2927 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2928 I40E_GLPRT_GORCL(hw->port),
2929 pf->offset_loaded, &os->eth.rx_bytes,
2931 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2932 I40E_GLPRT_UPRCL(hw->port),
2933 pf->offset_loaded, &os->eth.rx_unicast,
2934 &ns->eth.rx_unicast);
2935 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2936 I40E_GLPRT_MPRCL(hw->port),
2937 pf->offset_loaded, &os->eth.rx_multicast,
2938 &ns->eth.rx_multicast);
2939 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2940 I40E_GLPRT_BPRCL(hw->port),
2941 pf->offset_loaded, &os->eth.rx_broadcast,
2942 &ns->eth.rx_broadcast);
2943 /* Workaround: CRC size should not be included in byte statistics,
2944 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2946 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2947 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2949 /* exclude internal rx bytes
2950 * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2951 * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
2953 * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
2955 if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2956 ns->eth.rx_bytes = 0;
2958 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2960 if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
2961 ns->eth.rx_unicast = 0;
2963 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
2965 if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
2966 ns->eth.rx_multicast = 0;
2968 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
2970 if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
2971 ns->eth.rx_broadcast = 0;
2973 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
2975 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2976 pf->offset_loaded, &os->eth.rx_discards,
2977 &ns->eth.rx_discards);
2978 /* GLPRT_REPC not supported */
2979 /* GLPRT_RMPC not supported */
2980 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2982 &os->eth.rx_unknown_protocol,
2983 &ns->eth.rx_unknown_protocol);
2984 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2985 I40E_GLPRT_GOTCL(hw->port),
2986 pf->offset_loaded, &os->eth.tx_bytes,
2988 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2989 I40E_GLPRT_UPTCL(hw->port),
2990 pf->offset_loaded, &os->eth.tx_unicast,
2991 &ns->eth.tx_unicast);
2992 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2993 I40E_GLPRT_MPTCL(hw->port),
2994 pf->offset_loaded, &os->eth.tx_multicast,
2995 &ns->eth.tx_multicast);
2996 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2997 I40E_GLPRT_BPTCL(hw->port),
2998 pf->offset_loaded, &os->eth.tx_broadcast,
2999 &ns->eth.tx_broadcast);
3000 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3001 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
3003 /* exclude internal tx bytes
3004 * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
3005 * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
3007 * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
3009 if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
3010 ns->eth.tx_bytes = 0;
3012 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3014 if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3015 ns->eth.tx_unicast = 0;
3017 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3019 if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3020 ns->eth.tx_multicast = 0;
3022 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3024 if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3025 ns->eth.tx_broadcast = 0;
3027 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3029 /* GLPRT_TEPC not supported */
3031 /* additional port specific stats */
3032 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3033 pf->offset_loaded, &os->tx_dropped_link_down,
3034 &ns->tx_dropped_link_down);
3035 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3036 pf->offset_loaded, &os->crc_errors,
3038 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3039 pf->offset_loaded, &os->illegal_bytes,
3040 &ns->illegal_bytes);
3041 /* GLPRT_ERRBC not supported */
3042 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3043 pf->offset_loaded, &os->mac_local_faults,
3044 &ns->mac_local_faults);
3045 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3046 pf->offset_loaded, &os->mac_remote_faults,
3047 &ns->mac_remote_faults);
3048 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3049 pf->offset_loaded, &os->rx_length_errors,
3050 &ns->rx_length_errors);
3051 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3052 pf->offset_loaded, &os->link_xon_rx,
3054 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3055 pf->offset_loaded, &os->link_xoff_rx,
3057 for (i = 0; i < 8; i++) {
3058 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3060 &os->priority_xon_rx[i],
3061 &ns->priority_xon_rx[i]);
3062 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3064 &os->priority_xoff_rx[i],
3065 &ns->priority_xoff_rx[i]);
3067 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3068 pf->offset_loaded, &os->link_xon_tx,
3070 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3071 pf->offset_loaded, &os->link_xoff_tx,
3073 for (i = 0; i < 8; i++) {
3074 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3076 &os->priority_xon_tx[i],
3077 &ns->priority_xon_tx[i]);
3078 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3080 &os->priority_xoff_tx[i],
3081 &ns->priority_xoff_tx[i]);
3082 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3084 &os->priority_xon_2_xoff[i],
3085 &ns->priority_xon_2_xoff[i]);
3087 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3088 I40E_GLPRT_PRC64L(hw->port),
3089 pf->offset_loaded, &os->rx_size_64,
3091 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3092 I40E_GLPRT_PRC127L(hw->port),
3093 pf->offset_loaded, &os->rx_size_127,
3095 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3096 I40E_GLPRT_PRC255L(hw->port),
3097 pf->offset_loaded, &os->rx_size_255,
3099 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3100 I40E_GLPRT_PRC511L(hw->port),
3101 pf->offset_loaded, &os->rx_size_511,
3103 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3104 I40E_GLPRT_PRC1023L(hw->port),
3105 pf->offset_loaded, &os->rx_size_1023,
3107 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3108 I40E_GLPRT_PRC1522L(hw->port),
3109 pf->offset_loaded, &os->rx_size_1522,
3111 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3112 I40E_GLPRT_PRC9522L(hw->port),
3113 pf->offset_loaded, &os->rx_size_big,
3115 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3116 pf->offset_loaded, &os->rx_undersize,
3118 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3119 pf->offset_loaded, &os->rx_fragments,
3121 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3122 pf->offset_loaded, &os->rx_oversize,
3124 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3125 pf->offset_loaded, &os->rx_jabber,
3127 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3128 I40E_GLPRT_PTC64L(hw->port),
3129 pf->offset_loaded, &os->tx_size_64,
3131 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3132 I40E_GLPRT_PTC127L(hw->port),
3133 pf->offset_loaded, &os->tx_size_127,
3135 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3136 I40E_GLPRT_PTC255L(hw->port),
3137 pf->offset_loaded, &os->tx_size_255,
3139 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3140 I40E_GLPRT_PTC511L(hw->port),
3141 pf->offset_loaded, &os->tx_size_511,
3143 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3144 I40E_GLPRT_PTC1023L(hw->port),
3145 pf->offset_loaded, &os->tx_size_1023,
3147 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3148 I40E_GLPRT_PTC1522L(hw->port),
3149 pf->offset_loaded, &os->tx_size_1522,
3151 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3152 I40E_GLPRT_PTC9522L(hw->port),
3153 pf->offset_loaded, &os->tx_size_big,
3155 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3157 &os->fd_sb_match, &ns->fd_sb_match);
3158 /* GLPRT_MSPDC not supported */
3159 /* GLPRT_XEC not supported */
3161 pf->offset_loaded = true;
3164 i40e_update_vsi_stats(pf->main_vsi);
3167 /* Get all statistics of a port */
3169 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3171 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3172 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3173 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3176 /* call read registers - updates values, now write them to struct */
3177 i40e_read_stats_registers(pf, hw);
3179 stats->ipackets = ns->eth.rx_unicast +
3180 ns->eth.rx_multicast +
3181 ns->eth.rx_broadcast -
3182 ns->eth.rx_discards -
3183 pf->main_vsi->eth_stats.rx_discards;
3184 stats->opackets = ns->eth.tx_unicast +
3185 ns->eth.tx_multicast +
3186 ns->eth.tx_broadcast;
3187 stats->ibytes = ns->eth.rx_bytes;
3188 stats->obytes = ns->eth.tx_bytes;
3189 stats->oerrors = ns->eth.tx_errors +
3190 pf->main_vsi->eth_stats.tx_errors;
3193 stats->imissed = ns->eth.rx_discards +
3194 pf->main_vsi->eth_stats.rx_discards;
3195 stats->ierrors = ns->crc_errors +
3196 ns->rx_length_errors + ns->rx_undersize +
3197 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3199 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3200 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
3201 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
3202 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
3203 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
3204 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
3205 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3206 ns->eth.rx_unknown_protocol);
3207 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
3208 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
3209 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
3210 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
3211 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
3212 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
3214 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
3215 ns->tx_dropped_link_down);
3216 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
3217 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
3219 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
3220 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
3221 ns->mac_local_faults);
3222 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
3223 ns->mac_remote_faults);
3224 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
3225 ns->rx_length_errors);
3226 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
3227 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
3228 for (i = 0; i < 8; i++) {
3229 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
3230 i, ns->priority_xon_rx[i]);
3231 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
3232 i, ns->priority_xoff_rx[i]);
3234 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
3235 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
3236 for (i = 0; i < 8; i++) {
3237 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
3238 i, ns->priority_xon_tx[i]);
3239 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
3240 i, ns->priority_xoff_tx[i]);
3241 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
3242 i, ns->priority_xon_2_xoff[i]);
3244 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
3245 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
3246 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
3247 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
3248 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
3249 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
3250 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
3251 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
3252 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
3253 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
3254 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
3255 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
3256 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
3257 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
3258 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
3259 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
3260 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
3261 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
3262 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3263 ns->mac_short_packet_dropped);
3264 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
3265 ns->checksum_error);
3266 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
3267 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3271 /* Reset the statistics */
3273 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3275 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3276 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3278 /* Mark PF and VSI stats to update the offset, aka "reset" */
3279 pf->offset_loaded = false;
3281 pf->main_vsi->offset_loaded = false;
3283 /* read the stats, reading current register values into offset */
3284 i40e_read_stats_registers(pf, hw);
3288 i40e_xstats_calc_num(void)
3290 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3291 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3292 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3295 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3296 struct rte_eth_xstat_name *xstats_names,
3297 __rte_unused unsigned limit)
3302 if (xstats_names == NULL)
3303 return i40e_xstats_calc_num();
3305 /* Note: limit checked in rte_eth_xstats_names() */
3307 /* Get stats from i40e_eth_stats struct */
3308 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3309 snprintf(xstats_names[count].name,
3310 sizeof(xstats_names[count].name),
3311 "%s", rte_i40e_stats_strings[i].name);
3315 /* Get individiual stats from i40e_hw_port struct */
3316 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3317 snprintf(xstats_names[count].name,
3318 sizeof(xstats_names[count].name),
3319 "%s", rte_i40e_hw_port_strings[i].name);
3323 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3324 for (prio = 0; prio < 8; prio++) {
3325 snprintf(xstats_names[count].name,
3326 sizeof(xstats_names[count].name),
3327 "rx_priority%u_%s", prio,
3328 rte_i40e_rxq_prio_strings[i].name);
3333 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3334 for (prio = 0; prio < 8; prio++) {
3335 snprintf(xstats_names[count].name,
3336 sizeof(xstats_names[count].name),
3337 "tx_priority%u_%s", prio,
3338 rte_i40e_txq_prio_strings[i].name);
3346 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3349 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3350 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3351 unsigned i, count, prio;
3352 struct i40e_hw_port_stats *hw_stats = &pf->stats;
3354 count = i40e_xstats_calc_num();
3358 i40e_read_stats_registers(pf, hw);
3365 /* Get stats from i40e_eth_stats struct */
3366 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3367 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3368 rte_i40e_stats_strings[i].offset);
3369 xstats[count].id = count;
3373 /* Get individiual stats from i40e_hw_port struct */
3374 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3375 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3376 rte_i40e_hw_port_strings[i].offset);
3377 xstats[count].id = count;
3381 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3382 for (prio = 0; prio < 8; prio++) {
3383 xstats[count].value =
3384 *(uint64_t *)(((char *)hw_stats) +
3385 rte_i40e_rxq_prio_strings[i].offset +
3386 (sizeof(uint64_t) * prio));
3387 xstats[count].id = count;
3392 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3393 for (prio = 0; prio < 8; prio++) {
3394 xstats[count].value =
3395 *(uint64_t *)(((char *)hw_stats) +
3396 rte_i40e_txq_prio_strings[i].offset +
3397 (sizeof(uint64_t) * prio));
3398 xstats[count].id = count;
3407 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
3408 __rte_unused uint16_t queue_id,
3409 __rte_unused uint8_t stat_idx,
3410 __rte_unused uint8_t is_rx)
3412 PMD_INIT_FUNC_TRACE();
3418 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3420 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3426 full_ver = hw->nvm.oem_ver;
3427 ver = (u8)(full_ver >> 24);
3428 build = (u16)((full_ver >> 8) & 0xffff);
3429 patch = (u8)(full_ver & 0xff);
3431 ret = snprintf(fw_version, fw_size,
3432 "%d.%d%d 0x%08x %d.%d.%d",
3433 ((hw->nvm.version >> 12) & 0xf),
3434 ((hw->nvm.version >> 4) & 0xff),
3435 (hw->nvm.version & 0xf), hw->nvm.eetrack,
3438 ret += 1; /* add the size of '\0' */
3439 if (fw_size < (u32)ret)
3446 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3448 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3449 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3450 struct i40e_vsi *vsi = pf->main_vsi;
3451 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3453 dev_info->max_rx_queues = vsi->nb_qps;
3454 dev_info->max_tx_queues = vsi->nb_qps;
3455 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3456 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3457 dev_info->max_mac_addrs = vsi->max_macaddrs;
3458 dev_info->max_vfs = pci_dev->max_vfs;
3459 dev_info->rx_queue_offload_capa = 0;
3460 dev_info->rx_offload_capa =
3461 DEV_RX_OFFLOAD_VLAN_STRIP |
3462 DEV_RX_OFFLOAD_QINQ_STRIP |
3463 DEV_RX_OFFLOAD_IPV4_CKSUM |
3464 DEV_RX_OFFLOAD_UDP_CKSUM |
3465 DEV_RX_OFFLOAD_TCP_CKSUM |
3466 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3467 DEV_RX_OFFLOAD_KEEP_CRC |
3468 DEV_RX_OFFLOAD_SCATTER |
3469 DEV_RX_OFFLOAD_VLAN_EXTEND |
3470 DEV_RX_OFFLOAD_VLAN_FILTER |
3471 DEV_RX_OFFLOAD_JUMBO_FRAME;
3473 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3474 dev_info->tx_offload_capa =
3475 DEV_TX_OFFLOAD_VLAN_INSERT |
3476 DEV_TX_OFFLOAD_QINQ_INSERT |
3477 DEV_TX_OFFLOAD_IPV4_CKSUM |
3478 DEV_TX_OFFLOAD_UDP_CKSUM |
3479 DEV_TX_OFFLOAD_TCP_CKSUM |
3480 DEV_TX_OFFLOAD_SCTP_CKSUM |
3481 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3482 DEV_TX_OFFLOAD_TCP_TSO |
3483 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3484 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3485 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3486 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3487 DEV_TX_OFFLOAD_MULTI_SEGS |
3488 dev_info->tx_queue_offload_capa;
3489 dev_info->dev_capa =
3490 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3491 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3493 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3495 dev_info->reta_size = pf->hash_lut_size;
3496 dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3498 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3500 .pthresh = I40E_DEFAULT_RX_PTHRESH,
3501 .hthresh = I40E_DEFAULT_RX_HTHRESH,
3502 .wthresh = I40E_DEFAULT_RX_WTHRESH,
3504 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3509 dev_info->default_txconf = (struct rte_eth_txconf) {
3511 .pthresh = I40E_DEFAULT_TX_PTHRESH,
3512 .hthresh = I40E_DEFAULT_TX_HTHRESH,
3513 .wthresh = I40E_DEFAULT_TX_WTHRESH,
3515 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3516 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3520 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3521 .nb_max = I40E_MAX_RING_DESC,
3522 .nb_min = I40E_MIN_RING_DESC,
3523 .nb_align = I40E_ALIGN_RING_DESC,
3526 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3527 .nb_max = I40E_MAX_RING_DESC,
3528 .nb_min = I40E_MIN_RING_DESC,
3529 .nb_align = I40E_ALIGN_RING_DESC,
3530 .nb_seg_max = I40E_TX_MAX_SEG,
3531 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3534 if (pf->flags & I40E_FLAG_VMDQ) {
3535 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3536 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3537 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3538 pf->max_nb_vmdq_vsi;
3539 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3540 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3541 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3544 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3546 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3547 dev_info->default_rxportconf.nb_queues = 2;
3548 dev_info->default_txportconf.nb_queues = 2;
3549 if (dev->data->nb_rx_queues == 1)
3550 dev_info->default_rxportconf.ring_size = 2048;
3552 dev_info->default_rxportconf.ring_size = 1024;
3553 if (dev->data->nb_tx_queues == 1)
3554 dev_info->default_txportconf.ring_size = 1024;
3556 dev_info->default_txportconf.ring_size = 512;
3558 } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3560 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3561 dev_info->default_rxportconf.nb_queues = 1;
3562 dev_info->default_txportconf.nb_queues = 1;
3563 dev_info->default_rxportconf.ring_size = 256;
3564 dev_info->default_txportconf.ring_size = 256;
3567 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3568 dev_info->default_rxportconf.nb_queues = 1;
3569 dev_info->default_txportconf.nb_queues = 1;
3570 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3571 dev_info->default_rxportconf.ring_size = 512;
3572 dev_info->default_txportconf.ring_size = 256;
3574 dev_info->default_rxportconf.ring_size = 256;
3575 dev_info->default_txportconf.ring_size = 256;
3578 dev_info->default_rxportconf.burst_size = 32;
3579 dev_info->default_txportconf.burst_size = 32;
3583 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3585 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3586 struct i40e_vsi *vsi = pf->main_vsi;
3587 PMD_INIT_FUNC_TRACE();
3590 return i40e_vsi_add_vlan(vsi, vlan_id);
3592 return i40e_vsi_delete_vlan(vsi, vlan_id);
3596 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3597 enum rte_vlan_type vlan_type,
3598 uint16_t tpid, int qinq)
3600 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3603 uint16_t reg_id = 3;
3607 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3611 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3613 if (ret != I40E_SUCCESS) {
3615 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3620 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3623 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3624 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3625 if (reg_r == reg_w) {
3626 PMD_DRV_LOG(DEBUG, "No need to write");
3630 ret = i40e_aq_debug_write_global_register(hw,
3631 I40E_GL_SWT_L2TAGCTRL(reg_id),
3633 if (ret != I40E_SUCCESS) {
3635 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3640 "Global register 0x%08x is changed with value 0x%08x",
3641 I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3647 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3648 enum rte_vlan_type vlan_type,
3651 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3652 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3653 int qinq = dev->data->dev_conf.rxmode.offloads &
3654 DEV_RX_OFFLOAD_VLAN_EXTEND;
3657 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3658 vlan_type != ETH_VLAN_TYPE_OUTER) ||
3659 (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3661 "Unsupported vlan type.");
3665 if (pf->support_multi_driver) {
3666 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3670 /* 802.1ad frames ability is added in NVM API 1.7*/
3671 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3673 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3674 hw->first_tag = rte_cpu_to_le_16(tpid);
3675 else if (vlan_type == ETH_VLAN_TYPE_INNER)
3676 hw->second_tag = rte_cpu_to_le_16(tpid);
3678 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3679 hw->second_tag = rte_cpu_to_le_16(tpid);
3681 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL);
3682 if (ret != I40E_SUCCESS) {
3684 "Set switch config failed aq_err: %d",
3685 hw->aq.asq_last_status);
3689 /* If NVM API < 1.7, keep the register setting */
3690 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3697 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3699 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3700 struct i40e_vsi *vsi = pf->main_vsi;
3701 struct rte_eth_rxmode *rxmode;
3703 rxmode = &dev->data->dev_conf.rxmode;
3704 if (mask & ETH_VLAN_FILTER_MASK) {
3705 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3706 i40e_vsi_config_vlan_filter(vsi, TRUE);
3708 i40e_vsi_config_vlan_filter(vsi, FALSE);
3711 if (mask & ETH_VLAN_STRIP_MASK) {
3712 /* Enable or disable VLAN stripping */
3713 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3714 i40e_vsi_config_vlan_stripping(vsi, TRUE);
3716 i40e_vsi_config_vlan_stripping(vsi, FALSE);
3719 if (mask & ETH_VLAN_EXTEND_MASK) {
3720 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
3721 i40e_vsi_config_double_vlan(vsi, TRUE);
3722 /* Set global registers with default ethertype. */
3723 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3725 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3729 i40e_vsi_config_double_vlan(vsi, FALSE);
3736 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3737 __rte_unused uint16_t queue,
3738 __rte_unused int on)
3740 PMD_INIT_FUNC_TRACE();
3744 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3746 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3747 struct i40e_vsi *vsi = pf->main_vsi;
3748 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3749 struct i40e_vsi_vlan_pvid_info info;
3751 memset(&info, 0, sizeof(info));
3754 info.config.pvid = pvid;
3756 info.config.reject.tagged =
3757 data->dev_conf.txmode.hw_vlan_reject_tagged;
3758 info.config.reject.untagged =
3759 data->dev_conf.txmode.hw_vlan_reject_untagged;
3762 return i40e_vsi_vlan_pvid_set(vsi, &info);
3766 i40e_dev_led_on(struct rte_eth_dev *dev)
3768 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3769 uint32_t mode = i40e_led_get(hw);
3772 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3778 i40e_dev_led_off(struct rte_eth_dev *dev)
3780 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3781 uint32_t mode = i40e_led_get(hw);
3784 i40e_led_set(hw, 0, false);
3790 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3792 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3793 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3795 fc_conf->pause_time = pf->fc_conf.pause_time;
3797 /* read out from register, in case they are modified by other port */
3798 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3799 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3800 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3801 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3803 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3804 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3806 /* Return current mode according to actual setting*/
3807 switch (hw->fc.current_mode) {
3809 fc_conf->mode = RTE_FC_FULL;
3811 case I40E_FC_TX_PAUSE:
3812 fc_conf->mode = RTE_FC_TX_PAUSE;
3814 case I40E_FC_RX_PAUSE:
3815 fc_conf->mode = RTE_FC_RX_PAUSE;
3819 fc_conf->mode = RTE_FC_NONE;
3826 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3828 uint32_t mflcn_reg, fctrl_reg, reg;
3829 uint32_t max_high_water;
3830 uint8_t i, aq_failure;
3834 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3835 [RTE_FC_NONE] = I40E_FC_NONE,
3836 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3837 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3838 [RTE_FC_FULL] = I40E_FC_FULL
3841 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3843 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3844 if ((fc_conf->high_water > max_high_water) ||
3845 (fc_conf->high_water < fc_conf->low_water)) {
3847 "Invalid high/low water setup value in KB, High_water must be <= %d.",
3852 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3853 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3854 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3856 pf->fc_conf.pause_time = fc_conf->pause_time;
3857 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3858 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3860 PMD_INIT_FUNC_TRACE();
3862 /* All the link flow control related enable/disable register
3863 * configuration is handle by the F/W
3865 err = i40e_set_fc(hw, &aq_failure, true);
3869 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3870 /* Configure flow control refresh threshold,
3871 * the value for stat_tx_pause_refresh_timer[8]
3872 * is used for global pause operation.
3876 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3877 pf->fc_conf.pause_time);
3879 /* configure the timer value included in transmitted pause
3881 * the value for stat_tx_pause_quanta[8] is used for global
3884 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3885 pf->fc_conf.pause_time);
3887 fctrl_reg = I40E_READ_REG(hw,
3888 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3890 if (fc_conf->mac_ctrl_frame_fwd != 0)
3891 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3893 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3895 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3898 /* Configure pause time (2 TCs per register) */
3899 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3900 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3901 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3903 /* Configure flow control refresh threshold value */
3904 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3905 pf->fc_conf.pause_time / 2);
3907 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3909 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3910 *depending on configuration
3912 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3913 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3914 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3916 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3917 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3920 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3923 if (!pf->support_multi_driver) {
3924 /* config water marker both based on the packets and bytes */
3925 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
3926 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3927 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3928 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
3929 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3930 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3931 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
3932 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3934 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
3935 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3939 "Water marker configuration is not supported.");
3942 I40E_WRITE_FLUSH(hw);
3948 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3949 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3951 PMD_INIT_FUNC_TRACE();
3956 /* Add a MAC address, and update filters */
3958 i40e_macaddr_add(struct rte_eth_dev *dev,
3959 struct ether_addr *mac_addr,
3960 __rte_unused uint32_t index,
3963 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3964 struct i40e_mac_filter_info mac_filter;
3965 struct i40e_vsi *vsi;
3966 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
3969 /* If VMDQ not enabled or configured, return */
3970 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3971 !pf->nb_cfg_vmdq_vsi)) {
3972 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3973 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3978 if (pool > pf->nb_cfg_vmdq_vsi) {
3979 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3980 pool, pf->nb_cfg_vmdq_vsi);
3984 rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3985 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3986 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3988 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3993 vsi = pf->vmdq[pool - 1].vsi;
3995 ret = i40e_vsi_add_mac(vsi, &mac_filter);
3996 if (ret != I40E_SUCCESS) {
3997 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4003 /* Remove a MAC address, and update filters */
4005 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4007 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4008 struct i40e_vsi *vsi;
4009 struct rte_eth_dev_data *data = dev->data;
4010 struct ether_addr *macaddr;
4015 macaddr = &(data->mac_addrs[index]);
4017 pool_sel = dev->data->mac_pool_sel[index];
4019 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4020 if (pool_sel & (1ULL << i)) {
4024 /* No VMDQ pool enabled or configured */
4025 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4026 (i > pf->nb_cfg_vmdq_vsi)) {
4028 "No VMDQ pool enabled/configured");
4031 vsi = pf->vmdq[i - 1].vsi;
4033 ret = i40e_vsi_delete_mac(vsi, macaddr);
4036 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4043 /* Set perfect match or hash match of MAC and VLAN for a VF */
4045 i40e_vf_mac_filter_set(struct i40e_pf *pf,
4046 struct rte_eth_mac_filter *filter,
4050 struct i40e_mac_filter_info mac_filter;
4051 struct ether_addr old_mac;
4052 struct ether_addr *new_mac;
4053 struct i40e_pf_vf *vf = NULL;
4058 PMD_DRV_LOG(ERR, "Invalid PF argument.");
4061 hw = I40E_PF_TO_HW(pf);
4063 if (filter == NULL) {
4064 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
4068 new_mac = &filter->mac_addr;
4070 if (is_zero_ether_addr(new_mac)) {
4071 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
4075 vf_id = filter->dst_id;
4077 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
4078 PMD_DRV_LOG(ERR, "Invalid argument.");
4081 vf = &pf->vfs[vf_id];
4083 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
4084 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
4089 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
4090 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
4092 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
4095 mac_filter.filter_type = filter->filter_type;
4096 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
4097 if (ret != I40E_SUCCESS) {
4098 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
4101 ether_addr_copy(new_mac, &pf->dev_addr);
4103 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
4105 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
4106 if (ret != I40E_SUCCESS) {
4107 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
4111 /* Clear device address as it has been removed */
4112 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
4113 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
4119 /* MAC filter handle */
4121 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4124 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4125 struct rte_eth_mac_filter *filter;
4126 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4127 int ret = I40E_NOT_SUPPORTED;
4129 filter = (struct rte_eth_mac_filter *)(arg);
4131 switch (filter_op) {
4132 case RTE_ETH_FILTER_NOP:
4135 case RTE_ETH_FILTER_ADD:
4136 i40e_pf_disable_irq0(hw);
4138 ret = i40e_vf_mac_filter_set(pf, filter, 1);
4139 i40e_pf_enable_irq0(hw);
4141 case RTE_ETH_FILTER_DELETE:
4142 i40e_pf_disable_irq0(hw);
4144 ret = i40e_vf_mac_filter_set(pf, filter, 0);
4145 i40e_pf_enable_irq0(hw);
4148 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4149 ret = I40E_ERR_PARAM;
4157 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4159 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4160 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4167 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4168 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
4171 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4175 uint32_t *lut_dw = (uint32_t *)lut;
4176 uint16_t i, lut_size_dw = lut_size / 4;
4178 if (vsi->type == I40E_VSI_SRIOV) {
4179 for (i = 0; i <= lut_size_dw; i++) {
4180 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4181 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4184 for (i = 0; i < lut_size_dw; i++)
4185 lut_dw[i] = I40E_READ_REG(hw,
4194 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4203 pf = I40E_VSI_TO_PF(vsi);
4204 hw = I40E_VSI_TO_HW(vsi);
4206 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4207 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
4210 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4214 uint32_t *lut_dw = (uint32_t *)lut;
4215 uint16_t i, lut_size_dw = lut_size / 4;
4217 if (vsi->type == I40E_VSI_SRIOV) {
4218 for (i = 0; i < lut_size_dw; i++)
4221 I40E_VFQF_HLUT1(i, vsi->user_param),
4224 for (i = 0; i < lut_size_dw; i++)
4225 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4228 I40E_WRITE_FLUSH(hw);
4235 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4236 struct rte_eth_rss_reta_entry64 *reta_conf,
4239 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4240 uint16_t i, lut_size = pf->hash_lut_size;
4241 uint16_t idx, shift;
4245 if (reta_size != lut_size ||
4246 reta_size > ETH_RSS_RETA_SIZE_512) {
4248 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4249 reta_size, lut_size);
4253 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4255 PMD_DRV_LOG(ERR, "No memory can be allocated");
4258 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4261 for (i = 0; i < reta_size; i++) {
4262 idx = i / RTE_RETA_GROUP_SIZE;
4263 shift = i % RTE_RETA_GROUP_SIZE;
4264 if (reta_conf[idx].mask & (1ULL << shift))
4265 lut[i] = reta_conf[idx].reta[shift];
4267 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4269 pf->adapter->rss_reta_updated = 1;
4278 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4279 struct rte_eth_rss_reta_entry64 *reta_conf,
4282 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4283 uint16_t i, lut_size = pf->hash_lut_size;
4284 uint16_t idx, shift;
4288 if (reta_size != lut_size ||
4289 reta_size > ETH_RSS_RETA_SIZE_512) {
4291 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4292 reta_size, lut_size);
4296 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4298 PMD_DRV_LOG(ERR, "No memory can be allocated");
4302 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4305 for (i = 0; i < reta_size; i++) {
4306 idx = i / RTE_RETA_GROUP_SIZE;
4307 shift = i % RTE_RETA_GROUP_SIZE;
4308 if (reta_conf[idx].mask & (1ULL << shift))
4309 reta_conf[idx].reta[shift] = lut[i];
4319 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4320 * @hw: pointer to the HW structure
4321 * @mem: pointer to mem struct to fill out
4322 * @size: size of memory requested
4323 * @alignment: what to align the allocation to
4325 enum i40e_status_code
4326 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4327 struct i40e_dma_mem *mem,
4331 const struct rte_memzone *mz = NULL;
4332 char z_name[RTE_MEMZONE_NAMESIZE];
4335 return I40E_ERR_PARAM;
4337 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4338 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4339 RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4341 return I40E_ERR_NO_MEMORY;
4346 mem->zone = (const void *)mz;
4348 "memzone %s allocated with physical address: %"PRIu64,
4351 return I40E_SUCCESS;
4355 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4356 * @hw: pointer to the HW structure
4357 * @mem: ptr to mem struct to free
4359 enum i40e_status_code
4360 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4361 struct i40e_dma_mem *mem)
4364 return I40E_ERR_PARAM;
4367 "memzone %s to be freed with physical address: %"PRIu64,
4368 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4369 rte_memzone_free((const struct rte_memzone *)mem->zone);
4374 return I40E_SUCCESS;
4378 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4379 * @hw: pointer to the HW structure
4380 * @mem: pointer to mem struct to fill out
4381 * @size: size of memory requested
4383 enum i40e_status_code
4384 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4385 struct i40e_virt_mem *mem,
4389 return I40E_ERR_PARAM;
4392 mem->va = rte_zmalloc("i40e", size, 0);
4395 return I40E_SUCCESS;
4397 return I40E_ERR_NO_MEMORY;
4401 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4402 * @hw: pointer to the HW structure
4403 * @mem: pointer to mem struct to free
4405 enum i40e_status_code
4406 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4407 struct i40e_virt_mem *mem)
4410 return I40E_ERR_PARAM;
4415 return I40E_SUCCESS;
4419 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4421 rte_spinlock_init(&sp->spinlock);
4425 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4427 rte_spinlock_lock(&sp->spinlock);
4431 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4433 rte_spinlock_unlock(&sp->spinlock);
4437 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4443 * Get the hardware capabilities, which will be parsed
4444 * and saved into struct i40e_hw.
4447 i40e_get_cap(struct i40e_hw *hw)
4449 struct i40e_aqc_list_capabilities_element_resp *buf;
4450 uint16_t len, size = 0;
4453 /* Calculate a huge enough buff for saving response data temporarily */
4454 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4455 I40E_MAX_CAP_ELE_NUM;
4456 buf = rte_zmalloc("i40e", len, 0);
4458 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4459 return I40E_ERR_NO_MEMORY;
4462 /* Get, parse the capabilities and save it to hw */
4463 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4464 i40e_aqc_opc_list_func_capabilities, NULL);
4465 if (ret != I40E_SUCCESS)
4466 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4468 /* Free the temporary buffer after being used */
4474 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4
4476 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4484 pf = (struct i40e_pf *)opaque;
4488 num = strtoul(value, &end, 0);
4489 if (errno != 0 || end == value || *end != 0) {
4490 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4491 "kept the value = %hu", value, pf->vf_nb_qp_max);
4495 if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4496 pf->vf_nb_qp_max = (uint16_t)num;
4498 /* here return 0 to make next valid same argument work */
4499 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4500 "power of 2 and equal or less than 16 !, Now it is "
4501 "kept the value = %hu", num, pf->vf_nb_qp_max);
4506 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4508 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4509 struct rte_kvargs *kvlist;
4512 /* set default queue number per VF as 4 */
4513 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4515 if (dev->device->devargs == NULL)
4518 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4522 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4523 if (!kvargs_count) {
4524 rte_kvargs_free(kvlist);
4528 if (kvargs_count > 1)
4529 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4530 "the first invalid or last valid one is used !",
4531 ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4533 rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4534 i40e_pf_parse_vf_queue_number_handler, pf);
4536 rte_kvargs_free(kvlist);
4542 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4544 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4545 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4546 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4547 uint16_t qp_count = 0, vsi_count = 0;
4549 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4550 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4554 i40e_pf_config_vf_rxq_number(dev);
4556 /* Add the parameter init for LFC */
4557 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4558 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4559 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4561 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4562 pf->max_num_vsi = hw->func_caps.num_vsis;
4563 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4564 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4566 /* FDir queue/VSI allocation */
4567 pf->fdir_qp_offset = 0;
4568 if (hw->func_caps.fd) {
4569 pf->flags |= I40E_FLAG_FDIR;
4570 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4572 pf->fdir_nb_qps = 0;
4574 qp_count += pf->fdir_nb_qps;
4577 /* LAN queue/VSI allocation */
4578 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4579 if (!hw->func_caps.rss) {
4582 pf->flags |= I40E_FLAG_RSS;
4583 if (hw->mac.type == I40E_MAC_X722)
4584 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4585 pf->lan_nb_qps = pf->lan_nb_qp_max;
4587 qp_count += pf->lan_nb_qps;
4590 /* VF queue/VSI allocation */
4591 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4592 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4593 pf->flags |= I40E_FLAG_SRIOV;
4594 pf->vf_nb_qps = pf->vf_nb_qp_max;
4595 pf->vf_num = pci_dev->max_vfs;
4597 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4598 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4603 qp_count += pf->vf_nb_qps * pf->vf_num;
4604 vsi_count += pf->vf_num;
4606 /* VMDq queue/VSI allocation */
4607 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4608 pf->vmdq_nb_qps = 0;
4609 pf->max_nb_vmdq_vsi = 0;
4610 if (hw->func_caps.vmdq) {
4611 if (qp_count < hw->func_caps.num_tx_qp &&
4612 vsi_count < hw->func_caps.num_vsis) {
4613 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4614 qp_count) / pf->vmdq_nb_qp_max;
4616 /* Limit the maximum number of VMDq vsi to the maximum
4617 * ethdev can support
4619 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4620 hw->func_caps.num_vsis - vsi_count);
4621 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4623 if (pf->max_nb_vmdq_vsi) {
4624 pf->flags |= I40E_FLAG_VMDQ;
4625 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4627 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4628 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4629 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4632 "No enough queues left for VMDq");
4635 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4638 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4639 vsi_count += pf->max_nb_vmdq_vsi;
4641 if (hw->func_caps.dcb)
4642 pf->flags |= I40E_FLAG_DCB;
4644 if (qp_count > hw->func_caps.num_tx_qp) {
4646 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4647 qp_count, hw->func_caps.num_tx_qp);
4650 if (vsi_count > hw->func_caps.num_vsis) {
4652 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4653 vsi_count, hw->func_caps.num_vsis);
4661 i40e_pf_get_switch_config(struct i40e_pf *pf)
4663 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4664 struct i40e_aqc_get_switch_config_resp *switch_config;
4665 struct i40e_aqc_switch_config_element_resp *element;
4666 uint16_t start_seid = 0, num_reported;
4669 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4670 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4671 if (!switch_config) {
4672 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4676 /* Get the switch configurations */
4677 ret = i40e_aq_get_switch_config(hw, switch_config,
4678 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4679 if (ret != I40E_SUCCESS) {
4680 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4683 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4684 if (num_reported != 1) { /* The number should be 1 */
4685 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4689 /* Parse the switch configuration elements */
4690 element = &(switch_config->element[0]);
4691 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4692 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4693 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4695 PMD_DRV_LOG(INFO, "Unknown element type");
4698 rte_free(switch_config);
4704 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4707 struct pool_entry *entry;
4709 if (pool == NULL || num == 0)
4712 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4713 if (entry == NULL) {
4714 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4718 /* queue heap initialize */
4719 pool->num_free = num;
4720 pool->num_alloc = 0;
4722 LIST_INIT(&pool->alloc_list);
4723 LIST_INIT(&pool->free_list);
4725 /* Initialize element */
4729 LIST_INSERT_HEAD(&pool->free_list, entry, next);
4734 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4736 struct pool_entry *entry, *next_entry;
4741 for (entry = LIST_FIRST(&pool->alloc_list);
4742 entry && (next_entry = LIST_NEXT(entry, next), 1);
4743 entry = next_entry) {
4744 LIST_REMOVE(entry, next);
4748 for (entry = LIST_FIRST(&pool->free_list);
4749 entry && (next_entry = LIST_NEXT(entry, next), 1);
4750 entry = next_entry) {
4751 LIST_REMOVE(entry, next);
4756 pool->num_alloc = 0;
4758 LIST_INIT(&pool->alloc_list);
4759 LIST_INIT(&pool->free_list);
4763 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4766 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4767 uint32_t pool_offset;
4771 PMD_DRV_LOG(ERR, "Invalid parameter");
4775 pool_offset = base - pool->base;
4776 /* Lookup in alloc list */
4777 LIST_FOREACH(entry, &pool->alloc_list, next) {
4778 if (entry->base == pool_offset) {
4779 valid_entry = entry;
4780 LIST_REMOVE(entry, next);
4785 /* Not find, return */
4786 if (valid_entry == NULL) {
4787 PMD_DRV_LOG(ERR, "Failed to find entry");
4792 * Found it, move it to free list and try to merge.
4793 * In order to make merge easier, always sort it by qbase.
4794 * Find adjacent prev and last entries.
4797 LIST_FOREACH(entry, &pool->free_list, next) {
4798 if (entry->base > valid_entry->base) {
4806 /* Try to merge with next one*/
4808 /* Merge with next one */
4809 if (valid_entry->base + valid_entry->len == next->base) {
4810 next->base = valid_entry->base;
4811 next->len += valid_entry->len;
4812 rte_free(valid_entry);
4819 /* Merge with previous one */
4820 if (prev->base + prev->len == valid_entry->base) {
4821 prev->len += valid_entry->len;
4822 /* If it merge with next one, remove next node */
4824 LIST_REMOVE(valid_entry, next);
4825 rte_free(valid_entry);
4827 rte_free(valid_entry);
4833 /* Not find any entry to merge, insert */
4836 LIST_INSERT_AFTER(prev, valid_entry, next);
4837 else if (next != NULL)
4838 LIST_INSERT_BEFORE(next, valid_entry, next);
4839 else /* It's empty list, insert to head */
4840 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4843 pool->num_free += valid_entry->len;
4844 pool->num_alloc -= valid_entry->len;
4850 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4853 struct pool_entry *entry, *valid_entry;
4855 if (pool == NULL || num == 0) {
4856 PMD_DRV_LOG(ERR, "Invalid parameter");
4860 if (pool->num_free < num) {
4861 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4862 num, pool->num_free);
4867 /* Lookup in free list and find most fit one */
4868 LIST_FOREACH(entry, &pool->free_list, next) {
4869 if (entry->len >= num) {
4871 if (entry->len == num) {
4872 valid_entry = entry;
4875 if (valid_entry == NULL || valid_entry->len > entry->len)
4876 valid_entry = entry;
4880 /* Not find one to satisfy the request, return */
4881 if (valid_entry == NULL) {
4882 PMD_DRV_LOG(ERR, "No valid entry found");
4886 * The entry have equal queue number as requested,
4887 * remove it from alloc_list.
4889 if (valid_entry->len == num) {
4890 LIST_REMOVE(valid_entry, next);
4893 * The entry have more numbers than requested,
4894 * create a new entry for alloc_list and minus its
4895 * queue base and number in free_list.
4897 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4898 if (entry == NULL) {
4900 "Failed to allocate memory for resource pool");
4903 entry->base = valid_entry->base;
4905 valid_entry->base += num;
4906 valid_entry->len -= num;
4907 valid_entry = entry;
4910 /* Insert it into alloc list, not sorted */
4911 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4913 pool->num_free -= valid_entry->len;
4914 pool->num_alloc += valid_entry->len;
4916 return valid_entry->base + pool->base;
4920 * bitmap_is_subset - Check whether src2 is subset of src1
4923 bitmap_is_subset(uint8_t src1, uint8_t src2)
4925 return !((src1 ^ src2) & src2);
4928 static enum i40e_status_code
4929 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4931 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4933 /* If DCB is not supported, only default TC is supported */
4934 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4935 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4936 return I40E_NOT_SUPPORTED;
4939 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4941 "Enabled TC map 0x%x not applicable to HW support 0x%x",
4942 hw->func_caps.enabled_tcmap, enabled_tcmap);
4943 return I40E_NOT_SUPPORTED;
4945 return I40E_SUCCESS;
4949 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4950 struct i40e_vsi_vlan_pvid_info *info)
4953 struct i40e_vsi_context ctxt;
4954 uint8_t vlan_flags = 0;
4957 if (vsi == NULL || info == NULL) {
4958 PMD_DRV_LOG(ERR, "invalid parameters");
4959 return I40E_ERR_PARAM;
4963 vsi->info.pvid = info->config.pvid;
4965 * If insert pvid is enabled, only tagged pkts are
4966 * allowed to be sent out.
4968 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4969 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4972 if (info->config.reject.tagged == 0)
4973 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4975 if (info->config.reject.untagged == 0)
4976 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4978 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4979 I40E_AQ_VSI_PVLAN_MODE_MASK);
4980 vsi->info.port_vlan_flags |= vlan_flags;
4981 vsi->info.valid_sections =
4982 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4983 memset(&ctxt, 0, sizeof(ctxt));
4984 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4985 ctxt.seid = vsi->seid;
4987 hw = I40E_VSI_TO_HW(vsi);
4988 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4989 if (ret != I40E_SUCCESS)
4990 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4996 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4998 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5000 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
5002 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5003 if (ret != I40E_SUCCESS)
5007 PMD_DRV_LOG(ERR, "seid not valid");
5011 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
5012 tc_bw_data.tc_valid_bits = enabled_tcmap;
5013 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5014 tc_bw_data.tc_bw_credits[i] =
5015 (enabled_tcmap & (1 << i)) ? 1 : 0;
5017 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5018 if (ret != I40E_SUCCESS) {
5019 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5023 rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5024 sizeof(vsi->info.qs_handle));
5025 return I40E_SUCCESS;
5028 static enum i40e_status_code
5029 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5030 struct i40e_aqc_vsi_properties_data *info,
5031 uint8_t enabled_tcmap)
5033 enum i40e_status_code ret;
5034 int i, total_tc = 0;
5035 uint16_t qpnum_per_tc, bsf, qp_idx;
5037 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5038 if (ret != I40E_SUCCESS)
5041 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5042 if (enabled_tcmap & (1 << i))
5046 vsi->enabled_tc = enabled_tcmap;
5048 /* Number of queues per enabled TC */
5049 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5050 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5051 bsf = rte_bsf32(qpnum_per_tc);
5053 /* Adjust the queue number to actual queues that can be applied */
5054 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5055 vsi->nb_qps = qpnum_per_tc * total_tc;
5058 * Configure TC and queue mapping parameters, for enabled TC,
5059 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5060 * default queue will serve it.
5063 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5064 if (vsi->enabled_tc & (1 << i)) {
5065 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5066 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5067 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5068 qp_idx += qpnum_per_tc;
5070 info->tc_mapping[i] = 0;
5073 /* Associate queue number with VSI */
5074 if (vsi->type == I40E_VSI_SRIOV) {
5075 info->mapping_flags |=
5076 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5077 for (i = 0; i < vsi->nb_qps; i++)
5078 info->queue_mapping[i] =
5079 rte_cpu_to_le_16(vsi->base_queue + i);
5081 info->mapping_flags |=
5082 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5083 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5085 info->valid_sections |=
5086 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5088 return I40E_SUCCESS;
5092 i40e_veb_release(struct i40e_veb *veb)
5094 struct i40e_vsi *vsi;
5100 if (!TAILQ_EMPTY(&veb->head)) {
5101 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5104 /* associate_vsi field is NULL for floating VEB */
5105 if (veb->associate_vsi != NULL) {
5106 vsi = veb->associate_vsi;
5107 hw = I40E_VSI_TO_HW(vsi);
5109 vsi->uplink_seid = veb->uplink_seid;
5112 veb->associate_pf->main_vsi->floating_veb = NULL;
5113 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5116 i40e_aq_delete_element(hw, veb->seid, NULL);
5118 return I40E_SUCCESS;
5122 static struct i40e_veb *
5123 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5125 struct i40e_veb *veb;
5131 "veb setup failed, associated PF shouldn't null");
5134 hw = I40E_PF_TO_HW(pf);
5136 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5138 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5142 veb->associate_vsi = vsi;
5143 veb->associate_pf = pf;
5144 TAILQ_INIT(&veb->head);
5145 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5147 /* create floating veb if vsi is NULL */
5149 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5150 I40E_DEFAULT_TCMAP, false,
5151 &veb->seid, false, NULL);
5153 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5154 true, &veb->seid, false, NULL);
5157 if (ret != I40E_SUCCESS) {
5158 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5159 hw->aq.asq_last_status);
5162 veb->enabled_tc = I40E_DEFAULT_TCMAP;
5164 /* get statistics index */
5165 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5166 &veb->stats_idx, NULL, NULL, NULL);
5167 if (ret != I40E_SUCCESS) {
5168 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5169 hw->aq.asq_last_status);
5172 /* Get VEB bandwidth, to be implemented */
5173 /* Now associated vsi binding to the VEB, set uplink to this VEB */
5175 vsi->uplink_seid = veb->seid;
5184 i40e_vsi_release(struct i40e_vsi *vsi)
5188 struct i40e_vsi_list *vsi_list;
5191 struct i40e_mac_filter *f;
5192 uint16_t user_param;
5195 return I40E_SUCCESS;
5200 user_param = vsi->user_param;
5202 pf = I40E_VSI_TO_PF(vsi);
5203 hw = I40E_VSI_TO_HW(vsi);
5205 /* VSI has child to attach, release child first */
5207 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5208 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5211 i40e_veb_release(vsi->veb);
5214 if (vsi->floating_veb) {
5215 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5216 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5221 /* Remove all macvlan filters of the VSI */
5222 i40e_vsi_remove_all_macvlan_filter(vsi);
5223 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5226 if (vsi->type != I40E_VSI_MAIN &&
5227 ((vsi->type != I40E_VSI_SRIOV) ||
5228 !pf->floating_veb_list[user_param])) {
5229 /* Remove vsi from parent's sibling list */
5230 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5231 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5232 return I40E_ERR_PARAM;
5234 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5235 &vsi->sib_vsi_list, list);
5237 /* Remove all switch element of the VSI */
5238 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5239 if (ret != I40E_SUCCESS)
5240 PMD_DRV_LOG(ERR, "Failed to delete element");
5243 if ((vsi->type == I40E_VSI_SRIOV) &&
5244 pf->floating_veb_list[user_param]) {
5245 /* Remove vsi from parent's sibling list */
5246 if (vsi->parent_vsi == NULL ||
5247 vsi->parent_vsi->floating_veb == NULL) {
5248 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5249 return I40E_ERR_PARAM;
5251 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5252 &vsi->sib_vsi_list, list);
5254 /* Remove all switch element of the VSI */
5255 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5256 if (ret != I40E_SUCCESS)
5257 PMD_DRV_LOG(ERR, "Failed to delete element");
5260 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5262 if (vsi->type != I40E_VSI_SRIOV)
5263 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5266 return I40E_SUCCESS;
5270 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5272 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5273 struct i40e_aqc_remove_macvlan_element_data def_filter;
5274 struct i40e_mac_filter_info filter;
5277 if (vsi->type != I40E_VSI_MAIN)
5278 return I40E_ERR_CONFIG;
5279 memset(&def_filter, 0, sizeof(def_filter));
5280 rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5282 def_filter.vlan_tag = 0;
5283 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5284 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5285 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5286 if (ret != I40E_SUCCESS) {
5287 struct i40e_mac_filter *f;
5288 struct ether_addr *mac;
5291 "Cannot remove the default macvlan filter");
5292 /* It needs to add the permanent mac into mac list */
5293 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5295 PMD_DRV_LOG(ERR, "failed to allocate memory");
5296 return I40E_ERR_NO_MEMORY;
5298 mac = &f->mac_info.mac_addr;
5299 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5301 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5302 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5307 rte_memcpy(&filter.mac_addr,
5308 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5309 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5310 return i40e_vsi_add_mac(vsi, &filter);
5314 * i40e_vsi_get_bw_config - Query VSI BW Information
5315 * @vsi: the VSI to be queried
5317 * Returns 0 on success, negative value on failure
5319 static enum i40e_status_code
5320 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5322 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5323 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5324 struct i40e_hw *hw = &vsi->adapter->hw;
5329 memset(&bw_config, 0, sizeof(bw_config));
5330 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5331 if (ret != I40E_SUCCESS) {
5332 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5333 hw->aq.asq_last_status);
5337 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5338 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5339 &ets_sla_config, NULL);
5340 if (ret != I40E_SUCCESS) {
5342 "VSI failed to get TC bandwdith configuration %u",
5343 hw->aq.asq_last_status);
5347 /* store and print out BW info */
5348 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5349 vsi->bw_info.bw_max = bw_config.max_bw;
5350 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5351 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5352 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5353 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5355 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5356 vsi->bw_info.bw_ets_share_credits[i] =
5357 ets_sla_config.share_credits[i];
5358 vsi->bw_info.bw_ets_credits[i] =
5359 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5360 /* 4 bits per TC, 4th bit is reserved */
5361 vsi->bw_info.bw_ets_max[i] =
5362 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5363 RTE_LEN2MASK(3, uint8_t));
5364 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5365 vsi->bw_info.bw_ets_share_credits[i]);
5366 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5367 vsi->bw_info.bw_ets_credits[i]);
5368 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5369 vsi->bw_info.bw_ets_max[i]);
5372 return I40E_SUCCESS;
5375 /* i40e_enable_pf_lb
5376 * @pf: pointer to the pf structure
5378 * allow loopback on pf
5381 i40e_enable_pf_lb(struct i40e_pf *pf)
5383 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5384 struct i40e_vsi_context ctxt;
5387 /* Use the FW API if FW >= v5.0 */
5388 if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
5389 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5393 memset(&ctxt, 0, sizeof(ctxt));
5394 ctxt.seid = pf->main_vsi_seid;
5395 ctxt.pf_num = hw->pf_id;
5396 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5398 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5399 ret, hw->aq.asq_last_status);
5402 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5403 ctxt.info.valid_sections =
5404 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5405 ctxt.info.switch_id |=
5406 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5408 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5410 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5411 hw->aq.asq_last_status);
5416 i40e_vsi_setup(struct i40e_pf *pf,
5417 enum i40e_vsi_type type,
5418 struct i40e_vsi *uplink_vsi,
5419 uint16_t user_param)
5421 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5422 struct i40e_vsi *vsi;
5423 struct i40e_mac_filter_info filter;
5425 struct i40e_vsi_context ctxt;
5426 struct ether_addr broadcast =
5427 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5429 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5430 uplink_vsi == NULL) {
5432 "VSI setup failed, VSI link shouldn't be NULL");
5436 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5438 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5443 * 1.type is not MAIN and uplink vsi is not NULL
5444 * If uplink vsi didn't setup VEB, create one first under veb field
5445 * 2.type is SRIOV and the uplink is NULL
5446 * If floating VEB is NULL, create one veb under floating veb field
5449 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5450 uplink_vsi->veb == NULL) {
5451 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5453 if (uplink_vsi->veb == NULL) {
5454 PMD_DRV_LOG(ERR, "VEB setup failed");
5457 /* set ALLOWLOOPBACk on pf, when veb is created */
5458 i40e_enable_pf_lb(pf);
5461 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5462 pf->main_vsi->floating_veb == NULL) {
5463 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5465 if (pf->main_vsi->floating_veb == NULL) {
5466 PMD_DRV_LOG(ERR, "VEB setup failed");
5471 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5473 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5476 TAILQ_INIT(&vsi->mac_list);
5478 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5479 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5480 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5481 vsi->user_param = user_param;
5482 vsi->vlan_anti_spoof_on = 0;
5483 vsi->vlan_filter_on = 0;
5484 /* Allocate queues */
5485 switch (vsi->type) {
5486 case I40E_VSI_MAIN :
5487 vsi->nb_qps = pf->lan_nb_qps;
5489 case I40E_VSI_SRIOV :
5490 vsi->nb_qps = pf->vf_nb_qps;
5492 case I40E_VSI_VMDQ2:
5493 vsi->nb_qps = pf->vmdq_nb_qps;
5496 vsi->nb_qps = pf->fdir_nb_qps;
5502 * The filter status descriptor is reported in rx queue 0,
5503 * while the tx queue for fdir filter programming has no
5504 * such constraints, can be non-zero queues.
5505 * To simplify it, choose FDIR vsi use queue 0 pair.
5506 * To make sure it will use queue 0 pair, queue allocation
5507 * need be done before this function is called
5509 if (type != I40E_VSI_FDIR) {
5510 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5512 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5516 vsi->base_queue = ret;
5518 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5520 /* VF has MSIX interrupt in VF range, don't allocate here */
5521 if (type == I40E_VSI_MAIN) {
5522 if (pf->support_multi_driver) {
5523 /* If support multi-driver, need to use INT0 instead of
5524 * allocating from msix pool. The Msix pool is init from
5525 * INT1, so it's OK just set msix_intr to 0 and nb_msix
5526 * to 1 without calling i40e_res_pool_alloc.
5531 ret = i40e_res_pool_alloc(&pf->msix_pool,
5532 RTE_MIN(vsi->nb_qps,
5533 RTE_MAX_RXTX_INTR_VEC_ID));
5536 "VSI MAIN %d get heap failed %d",
5538 goto fail_queue_alloc;
5540 vsi->msix_intr = ret;
5541 vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5542 RTE_MAX_RXTX_INTR_VEC_ID);
5544 } else if (type != I40E_VSI_SRIOV) {
5545 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5547 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5548 goto fail_queue_alloc;
5550 vsi->msix_intr = ret;
5558 if (type == I40E_VSI_MAIN) {
5559 /* For main VSI, no need to add since it's default one */
5560 vsi->uplink_seid = pf->mac_seid;
5561 vsi->seid = pf->main_vsi_seid;
5562 /* Bind queues with specific MSIX interrupt */
5564 * Needs 2 interrupt at least, one for misc cause which will
5565 * enabled from OS side, Another for queues binding the
5566 * interrupt from device side only.
5569 /* Get default VSI parameters from hardware */
5570 memset(&ctxt, 0, sizeof(ctxt));
5571 ctxt.seid = vsi->seid;
5572 ctxt.pf_num = hw->pf_id;
5573 ctxt.uplink_seid = vsi->uplink_seid;
5575 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5576 if (ret != I40E_SUCCESS) {
5577 PMD_DRV_LOG(ERR, "Failed to get VSI params");
5578 goto fail_msix_alloc;
5580 rte_memcpy(&vsi->info, &ctxt.info,
5581 sizeof(struct i40e_aqc_vsi_properties_data));
5582 vsi->vsi_id = ctxt.vsi_number;
5583 vsi->info.valid_sections = 0;
5585 /* Configure tc, enabled TC0 only */
5586 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5588 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5589 goto fail_msix_alloc;
5592 /* TC, queue mapping */
5593 memset(&ctxt, 0, sizeof(ctxt));
5594 vsi->info.valid_sections |=
5595 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5596 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5597 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5598 rte_memcpy(&ctxt.info, &vsi->info,
5599 sizeof(struct i40e_aqc_vsi_properties_data));
5600 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5601 I40E_DEFAULT_TCMAP);
5602 if (ret != I40E_SUCCESS) {
5604 "Failed to configure TC queue mapping");
5605 goto fail_msix_alloc;
5607 ctxt.seid = vsi->seid;
5608 ctxt.pf_num = hw->pf_id;
5609 ctxt.uplink_seid = vsi->uplink_seid;
5612 /* Update VSI parameters */
5613 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5614 if (ret != I40E_SUCCESS) {
5615 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5616 goto fail_msix_alloc;
5619 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5620 sizeof(vsi->info.tc_mapping));
5621 rte_memcpy(&vsi->info.queue_mapping,
5622 &ctxt.info.queue_mapping,
5623 sizeof(vsi->info.queue_mapping));
5624 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5625 vsi->info.valid_sections = 0;
5627 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5631 * Updating default filter settings are necessary to prevent
5632 * reception of tagged packets.
5633 * Some old firmware configurations load a default macvlan
5634 * filter which accepts both tagged and untagged packets.
5635 * The updating is to use a normal filter instead if needed.
5636 * For NVM 4.2.2 or after, the updating is not needed anymore.
5637 * The firmware with correct configurations load the default
5638 * macvlan filter which is expected and cannot be removed.
5640 i40e_update_default_filter_setting(vsi);
5641 i40e_config_qinq(hw, vsi);
5642 } else if (type == I40E_VSI_SRIOV) {
5643 memset(&ctxt, 0, sizeof(ctxt));
5645 * For other VSI, the uplink_seid equals to uplink VSI's
5646 * uplink_seid since they share same VEB
5648 if (uplink_vsi == NULL)
5649 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5651 vsi->uplink_seid = uplink_vsi->uplink_seid;
5652 ctxt.pf_num = hw->pf_id;
5653 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5654 ctxt.uplink_seid = vsi->uplink_seid;
5655 ctxt.connection_type = 0x1;
5656 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5658 /* Use the VEB configuration if FW >= v5.0 */
5659 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
5660 /* Configure switch ID */
5661 ctxt.info.valid_sections |=
5662 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5663 ctxt.info.switch_id =
5664 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5667 /* Configure port/vlan */
5668 ctxt.info.valid_sections |=
5669 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5670 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5671 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5672 hw->func_caps.enabled_tcmap);
5673 if (ret != I40E_SUCCESS) {
5675 "Failed to configure TC queue mapping");
5676 goto fail_msix_alloc;
5679 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5680 ctxt.info.valid_sections |=
5681 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5683 * Since VSI is not created yet, only configure parameter,
5684 * will add vsi below.
5687 i40e_config_qinq(hw, vsi);
5688 } else if (type == I40E_VSI_VMDQ2) {
5689 memset(&ctxt, 0, sizeof(ctxt));
5691 * For other VSI, the uplink_seid equals to uplink VSI's
5692 * uplink_seid since they share same VEB
5694 vsi->uplink_seid = uplink_vsi->uplink_seid;
5695 ctxt.pf_num = hw->pf_id;
5697 ctxt.uplink_seid = vsi->uplink_seid;
5698 ctxt.connection_type = 0x1;
5699 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5701 ctxt.info.valid_sections |=
5702 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5703 /* user_param carries flag to enable loop back */
5705 ctxt.info.switch_id =
5706 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5707 ctxt.info.switch_id |=
5708 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5711 /* Configure port/vlan */
5712 ctxt.info.valid_sections |=
5713 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5714 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5715 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5716 I40E_DEFAULT_TCMAP);
5717 if (ret != I40E_SUCCESS) {
5719 "Failed to configure TC queue mapping");
5720 goto fail_msix_alloc;
5722 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5723 ctxt.info.valid_sections |=
5724 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5725 } else if (type == I40E_VSI_FDIR) {
5726 memset(&ctxt, 0, sizeof(ctxt));
5727 vsi->uplink_seid = uplink_vsi->uplink_seid;
5728 ctxt.pf_num = hw->pf_id;
5730 ctxt.uplink_seid = vsi->uplink_seid;
5731 ctxt.connection_type = 0x1; /* regular data port */
5732 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5733 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5734 I40E_DEFAULT_TCMAP);
5735 if (ret != I40E_SUCCESS) {
5737 "Failed to configure TC queue mapping.");
5738 goto fail_msix_alloc;
5740 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5741 ctxt.info.valid_sections |=
5742 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5744 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5745 goto fail_msix_alloc;
5748 if (vsi->type != I40E_VSI_MAIN) {
5749 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5750 if (ret != I40E_SUCCESS) {
5751 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5752 hw->aq.asq_last_status);
5753 goto fail_msix_alloc;
5755 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5756 vsi->info.valid_sections = 0;
5757 vsi->seid = ctxt.seid;
5758 vsi->vsi_id = ctxt.vsi_number;
5759 vsi->sib_vsi_list.vsi = vsi;
5760 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5761 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5762 &vsi->sib_vsi_list, list);
5764 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5765 &vsi->sib_vsi_list, list);
5769 /* MAC/VLAN configuration */
5770 rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5771 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5773 ret = i40e_vsi_add_mac(vsi, &filter);
5774 if (ret != I40E_SUCCESS) {
5775 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5776 goto fail_msix_alloc;
5779 /* Get VSI BW information */
5780 i40e_vsi_get_bw_config(vsi);
5783 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5785 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5791 /* Configure vlan filter on or off */
5793 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5796 struct i40e_mac_filter *f;
5798 struct i40e_mac_filter_info *mac_filter;
5799 enum rte_mac_filter_type desired_filter;
5800 int ret = I40E_SUCCESS;
5803 /* Filter to match MAC and VLAN */
5804 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5806 /* Filter to match only MAC */
5807 desired_filter = RTE_MAC_PERFECT_MATCH;
5812 mac_filter = rte_zmalloc("mac_filter_info_data",
5813 num * sizeof(*mac_filter), 0);
5814 if (mac_filter == NULL) {
5815 PMD_DRV_LOG(ERR, "failed to allocate memory");
5816 return I40E_ERR_NO_MEMORY;
5821 /* Remove all existing mac */
5822 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5823 mac_filter[i] = f->mac_info;
5824 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5826 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5827 on ? "enable" : "disable");
5833 /* Override with new filter */
5834 for (i = 0; i < num; i++) {
5835 mac_filter[i].filter_type = desired_filter;
5836 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5838 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5839 on ? "enable" : "disable");
5845 rte_free(mac_filter);
5849 /* Configure vlan stripping on or off */
5851 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5853 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5854 struct i40e_vsi_context ctxt;
5856 int ret = I40E_SUCCESS;
5858 /* Check if it has been already on or off */
5859 if (vsi->info.valid_sections &
5860 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5862 if ((vsi->info.port_vlan_flags &
5863 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5864 return 0; /* already on */
5866 if ((vsi->info.port_vlan_flags &
5867 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5868 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5869 return 0; /* already off */
5874 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5876 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5877 vsi->info.valid_sections =
5878 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5879 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5880 vsi->info.port_vlan_flags |= vlan_flags;
5881 ctxt.seid = vsi->seid;
5882 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5883 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5885 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5886 on ? "enable" : "disable");
5892 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5894 struct rte_eth_dev_data *data = dev->data;
5898 /* Apply vlan offload setting */
5899 mask = ETH_VLAN_STRIP_MASK |
5900 ETH_VLAN_FILTER_MASK |
5901 ETH_VLAN_EXTEND_MASK;
5902 ret = i40e_vlan_offload_set(dev, mask);
5904 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5908 /* Apply pvid setting */
5909 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5910 data->dev_conf.txmode.hw_vlan_insert_pvid);
5912 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5918 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5920 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5922 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5926 i40e_update_flow_control(struct i40e_hw *hw)
5928 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5929 struct i40e_link_status link_status;
5930 uint32_t rxfc = 0, txfc = 0, reg;
5934 memset(&link_status, 0, sizeof(link_status));
5935 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5936 if (ret != I40E_SUCCESS) {
5937 PMD_DRV_LOG(ERR, "Failed to get link status information");
5938 goto write_reg; /* Disable flow control */
5941 an_info = hw->phy.link_info.an_info;
5942 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5943 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5944 ret = I40E_ERR_NOT_READY;
5945 goto write_reg; /* Disable flow control */
5948 * If link auto negotiation is enabled, flow control needs to
5949 * be configured according to it
5951 switch (an_info & I40E_LINK_PAUSE_RXTX) {
5952 case I40E_LINK_PAUSE_RXTX:
5955 hw->fc.current_mode = I40E_FC_FULL;
5957 case I40E_AQ_LINK_PAUSE_RX:
5959 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5961 case I40E_AQ_LINK_PAUSE_TX:
5963 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5966 hw->fc.current_mode = I40E_FC_NONE;
5971 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5972 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5973 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5974 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5975 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5976 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5983 i40e_pf_setup(struct i40e_pf *pf)
5985 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5986 struct i40e_filter_control_settings settings;
5987 struct i40e_vsi *vsi;
5990 /* Clear all stats counters */
5991 pf->offset_loaded = FALSE;
5992 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5993 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5994 memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5995 memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5997 ret = i40e_pf_get_switch_config(pf);
5998 if (ret != I40E_SUCCESS) {
5999 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
6003 ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
6005 PMD_INIT_LOG(WARNING,
6006 "failed to allocate switch domain for device %d", ret);
6008 if (pf->flags & I40E_FLAG_FDIR) {
6009 /* make queue allocated first, let FDIR use queue pair 0*/
6010 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
6011 if (ret != I40E_FDIR_QUEUE_ID) {
6013 "queue allocation fails for FDIR: ret =%d",
6015 pf->flags &= ~I40E_FLAG_FDIR;
6018 /* main VSI setup */
6019 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6021 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6022 return I40E_ERR_NOT_READY;
6026 /* Configure filter control */
6027 memset(&settings, 0, sizeof(settings));
6028 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
6029 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6030 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
6031 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6033 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6034 hw->func_caps.rss_table_size);
6035 return I40E_ERR_PARAM;
6037 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6038 hw->func_caps.rss_table_size);
6039 pf->hash_lut_size = hw->func_caps.rss_table_size;
6041 /* Enable ethtype and macvlan filters */
6042 settings.enable_ethtype = TRUE;
6043 settings.enable_macvlan = TRUE;
6044 ret = i40e_set_filter_control(hw, &settings);
6046 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6049 /* Update flow control according to the auto negotiation */
6050 i40e_update_flow_control(hw);
6052 return I40E_SUCCESS;
6056 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6062 * Set or clear TX Queue Disable flags,
6063 * which is required by hardware.
6065 i40e_pre_tx_queue_cfg(hw, q_idx, on);
6066 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6068 /* Wait until the request is finished */
6069 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6070 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6071 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6072 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6073 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6079 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6080 return I40E_SUCCESS; /* already on, skip next steps */
6082 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6083 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6085 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6086 return I40E_SUCCESS; /* already off, skip next steps */
6087 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6089 /* Write the register */
6090 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6091 /* Check the result */
6092 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6093 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6094 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6096 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6097 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6100 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6101 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6105 /* Check if it is timeout */
6106 if (j >= I40E_CHK_Q_ENA_COUNT) {
6107 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6108 (on ? "enable" : "disable"), q_idx);
6109 return I40E_ERR_TIMEOUT;
6112 return I40E_SUCCESS;
6115 /* Swith on or off the tx queues */
6117 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
6119 struct rte_eth_dev_data *dev_data = pf->dev_data;
6120 struct i40e_tx_queue *txq;
6121 struct rte_eth_dev *dev = pf->adapter->eth_dev;
6125 for (i = 0; i < dev_data->nb_tx_queues; i++) {
6126 txq = dev_data->tx_queues[i];
6127 /* Don't operate the queue if not configured or
6128 * if starting only per queue */
6129 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
6132 ret = i40e_dev_tx_queue_start(dev, i);
6134 ret = i40e_dev_tx_queue_stop(dev, i);
6135 if ( ret != I40E_SUCCESS)
6139 return I40E_SUCCESS;
6143 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6148 /* Wait until the request is finished */
6149 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6150 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6151 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6152 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6153 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6158 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6159 return I40E_SUCCESS; /* Already on, skip next steps */
6160 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6162 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6163 return I40E_SUCCESS; /* Already off, skip next steps */
6164 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6167 /* Write the register */
6168 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6169 /* Check the result */
6170 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6171 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6172 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6174 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6175 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6178 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6179 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6184 /* Check if it is timeout */
6185 if (j >= I40E_CHK_Q_ENA_COUNT) {
6186 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6187 (on ? "enable" : "disable"), q_idx);
6188 return I40E_ERR_TIMEOUT;
6191 return I40E_SUCCESS;
6193 /* Switch on or off the rx queues */
6195 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
6197 struct rte_eth_dev_data *dev_data = pf->dev_data;
6198 struct i40e_rx_queue *rxq;
6199 struct rte_eth_dev *dev = pf->adapter->eth_dev;
6203 for (i = 0; i < dev_data->nb_rx_queues; i++) {
6204 rxq = dev_data->rx_queues[i];
6205 /* Don't operate the queue if not configured or
6206 * if starting only per queue */
6207 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
6210 ret = i40e_dev_rx_queue_start(dev, i);
6212 ret = i40e_dev_rx_queue_stop(dev, i);
6213 if (ret != I40E_SUCCESS)
6217 return I40E_SUCCESS;
6220 /* Switch on or off all the rx/tx queues */
6222 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
6227 /* enable rx queues before enabling tx queues */
6228 ret = i40e_dev_switch_rx_queues(pf, on);
6230 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
6233 ret = i40e_dev_switch_tx_queues(pf, on);
6235 /* Stop tx queues before stopping rx queues */
6236 ret = i40e_dev_switch_tx_queues(pf, on);
6238 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
6241 ret = i40e_dev_switch_rx_queues(pf, on);
6247 /* Initialize VSI for TX */
6249 i40e_dev_tx_init(struct i40e_pf *pf)
6251 struct rte_eth_dev_data *data = pf->dev_data;
6253 uint32_t ret = I40E_SUCCESS;
6254 struct i40e_tx_queue *txq;
6256 for (i = 0; i < data->nb_tx_queues; i++) {
6257 txq = data->tx_queues[i];
6258 if (!txq || !txq->q_set)
6260 ret = i40e_tx_queue_init(txq);
6261 if (ret != I40E_SUCCESS)
6264 if (ret == I40E_SUCCESS)
6265 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6271 /* Initialize VSI for RX */
6273 i40e_dev_rx_init(struct i40e_pf *pf)
6275 struct rte_eth_dev_data *data = pf->dev_data;
6276 int ret = I40E_SUCCESS;
6278 struct i40e_rx_queue *rxq;
6280 i40e_pf_config_mq_rx(pf);
6281 for (i = 0; i < data->nb_rx_queues; i++) {
6282 rxq = data->rx_queues[i];
6283 if (!rxq || !rxq->q_set)
6286 ret = i40e_rx_queue_init(rxq);
6287 if (ret != I40E_SUCCESS) {
6289 "Failed to do RX queue initialization");
6293 if (ret == I40E_SUCCESS)
6294 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6301 i40e_dev_rxtx_init(struct i40e_pf *pf)
6305 err = i40e_dev_tx_init(pf);
6307 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6310 err = i40e_dev_rx_init(pf);
6312 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6320 i40e_vmdq_setup(struct rte_eth_dev *dev)
6322 struct rte_eth_conf *conf = &dev->data->dev_conf;
6323 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6324 int i, err, conf_vsis, j, loop;
6325 struct i40e_vsi *vsi;
6326 struct i40e_vmdq_info *vmdq_info;
6327 struct rte_eth_vmdq_rx_conf *vmdq_conf;
6328 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6331 * Disable interrupt to avoid message from VF. Furthermore, it will
6332 * avoid race condition in VSI creation/destroy.
6334 i40e_pf_disable_irq0(hw);
6336 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6337 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6341 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6342 if (conf_vsis > pf->max_nb_vmdq_vsi) {
6343 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6344 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6345 pf->max_nb_vmdq_vsi);
6349 if (pf->vmdq != NULL) {
6350 PMD_INIT_LOG(INFO, "VMDQ already configured");
6354 pf->vmdq = rte_zmalloc("vmdq_info_struct",
6355 sizeof(*vmdq_info) * conf_vsis, 0);
6357 if (pf->vmdq == NULL) {
6358 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6362 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6364 /* Create VMDQ VSI */
6365 for (i = 0; i < conf_vsis; i++) {
6366 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6367 vmdq_conf->enable_loop_back);
6369 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6373 vmdq_info = &pf->vmdq[i];
6375 vmdq_info->vsi = vsi;
6377 pf->nb_cfg_vmdq_vsi = conf_vsis;
6379 /* Configure Vlan */
6380 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6381 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6382 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6383 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6384 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6385 vmdq_conf->pool_map[i].vlan_id, j);
6387 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6388 vmdq_conf->pool_map[i].vlan_id);
6390 PMD_INIT_LOG(ERR, "Failed to add vlan");
6398 i40e_pf_enable_irq0(hw);
6403 for (i = 0; i < conf_vsis; i++)
6404 if (pf->vmdq[i].vsi == NULL)
6407 i40e_vsi_release(pf->vmdq[i].vsi);
6411 i40e_pf_enable_irq0(hw);
6416 i40e_stat_update_32(struct i40e_hw *hw,
6424 new_data = (uint64_t)I40E_READ_REG(hw, reg);
6428 if (new_data >= *offset)
6429 *stat = (uint64_t)(new_data - *offset);
6431 *stat = (uint64_t)((new_data +
6432 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6436 i40e_stat_update_48(struct i40e_hw *hw,
6445 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6446 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6447 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6452 if (new_data >= *offset)
6453 *stat = new_data - *offset;
6455 *stat = (uint64_t)((new_data +
6456 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6458 *stat &= I40E_48_BIT_MASK;
6463 i40e_pf_disable_irq0(struct i40e_hw *hw)
6465 /* Disable all interrupt types */
6466 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6467 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6468 I40E_WRITE_FLUSH(hw);
6473 i40e_pf_enable_irq0(struct i40e_hw *hw)
6475 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6476 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6477 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6478 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6479 I40E_WRITE_FLUSH(hw);
6483 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6485 /* read pending request and disable first */
6486 i40e_pf_disable_irq0(hw);
6487 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6488 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6489 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6492 /* Link no queues with irq0 */
6493 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6494 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6498 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6500 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6501 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6504 uint32_t index, offset, val;
6509 * Try to find which VF trigger a reset, use absolute VF id to access
6510 * since the reg is global register.
6512 for (i = 0; i < pf->vf_num; i++) {
6513 abs_vf_id = hw->func_caps.vf_base_id + i;
6514 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6515 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6516 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6517 /* VFR event occurred */
6518 if (val & (0x1 << offset)) {
6521 /* Clear the event first */
6522 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6524 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6526 * Only notify a VF reset event occurred,
6527 * don't trigger another SW reset
6529 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6530 if (ret != I40E_SUCCESS)
6531 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6537 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6539 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6542 for (i = 0; i < pf->vf_num; i++)
6543 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6547 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6549 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6550 struct i40e_arq_event_info info;
6551 uint16_t pending, opcode;
6554 info.buf_len = I40E_AQ_BUF_SZ;
6555 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6556 if (!info.msg_buf) {
6557 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6563 ret = i40e_clean_arq_element(hw, &info, &pending);
6565 if (ret != I40E_SUCCESS) {
6567 "Failed to read msg from AdminQ, aq_err: %u",
6568 hw->aq.asq_last_status);
6571 opcode = rte_le_to_cpu_16(info.desc.opcode);
6574 case i40e_aqc_opc_send_msg_to_pf:
6575 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6576 i40e_pf_host_handle_vf_msg(dev,
6577 rte_le_to_cpu_16(info.desc.retval),
6578 rte_le_to_cpu_32(info.desc.cookie_high),
6579 rte_le_to_cpu_32(info.desc.cookie_low),
6583 case i40e_aqc_opc_get_link_status:
6584 ret = i40e_dev_link_update(dev, 0);
6586 _rte_eth_dev_callback_process(dev,
6587 RTE_ETH_EVENT_INTR_LSC, NULL);
6590 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6595 rte_free(info.msg_buf);
6599 * Interrupt handler triggered by NIC for handling
6600 * specific interrupt.
6603 * Pointer to interrupt handle.
6605 * The address of parameter (struct rte_eth_dev *) regsitered before.
6611 i40e_dev_interrupt_handler(void *param)
6613 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6614 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6617 /* Disable interrupt */
6618 i40e_pf_disable_irq0(hw);
6620 /* read out interrupt causes */
6621 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6623 /* No interrupt event indicated */
6624 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6625 PMD_DRV_LOG(INFO, "No interrupt event");
6628 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6629 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6630 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6631 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6632 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6633 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6634 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6635 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6636 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6637 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6638 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6639 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6640 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6641 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6643 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6644 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6645 i40e_dev_handle_vfr_event(dev);
6647 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6648 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6649 i40e_dev_handle_aq_msg(dev);
6653 /* Enable interrupt */
6654 i40e_pf_enable_irq0(hw);
6658 i40e_dev_alarm_handler(void *param)
6660 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6661 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6664 /* Disable interrupt */
6665 i40e_pf_disable_irq0(hw);
6667 /* read out interrupt causes */
6668 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6670 /* No interrupt event indicated */
6671 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
6673 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6674 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6675 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6676 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6677 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6678 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6679 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6680 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6681 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6682 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6683 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6684 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6685 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6686 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6688 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6689 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6690 i40e_dev_handle_vfr_event(dev);
6692 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6693 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6694 i40e_dev_handle_aq_msg(dev);
6698 /* Enable interrupt */
6699 i40e_pf_enable_irq0(hw);
6700 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
6701 i40e_dev_alarm_handler, dev);
6705 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6706 struct i40e_macvlan_filter *filter,
6709 int ele_num, ele_buff_size;
6710 int num, actual_num, i;
6712 int ret = I40E_SUCCESS;
6713 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6714 struct i40e_aqc_add_macvlan_element_data *req_list;
6716 if (filter == NULL || total == 0)
6717 return I40E_ERR_PARAM;
6718 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6719 ele_buff_size = hw->aq.asq_buf_size;
6721 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6722 if (req_list == NULL) {
6723 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6724 return I40E_ERR_NO_MEMORY;
6729 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6730 memset(req_list, 0, ele_buff_size);
6732 for (i = 0; i < actual_num; i++) {
6733 rte_memcpy(req_list[i].mac_addr,
6734 &filter[num + i].macaddr, ETH_ADDR_LEN);
6735 req_list[i].vlan_tag =
6736 rte_cpu_to_le_16(filter[num + i].vlan_id);
6738 switch (filter[num + i].filter_type) {
6739 case RTE_MAC_PERFECT_MATCH:
6740 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6741 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6743 case RTE_MACVLAN_PERFECT_MATCH:
6744 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6746 case RTE_MAC_HASH_MATCH:
6747 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6748 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6750 case RTE_MACVLAN_HASH_MATCH:
6751 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6754 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6755 ret = I40E_ERR_PARAM;
6759 req_list[i].queue_number = 0;
6761 req_list[i].flags = rte_cpu_to_le_16(flags);
6764 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6766 if (ret != I40E_SUCCESS) {
6767 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6771 } while (num < total);
6779 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6780 struct i40e_macvlan_filter *filter,
6783 int ele_num, ele_buff_size;
6784 int num, actual_num, i;
6786 int ret = I40E_SUCCESS;
6787 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6788 struct i40e_aqc_remove_macvlan_element_data *req_list;
6790 if (filter == NULL || total == 0)
6791 return I40E_ERR_PARAM;
6793 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6794 ele_buff_size = hw->aq.asq_buf_size;
6796 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6797 if (req_list == NULL) {
6798 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6799 return I40E_ERR_NO_MEMORY;
6804 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6805 memset(req_list, 0, ele_buff_size);
6807 for (i = 0; i < actual_num; i++) {
6808 rte_memcpy(req_list[i].mac_addr,
6809 &filter[num + i].macaddr, ETH_ADDR_LEN);
6810 req_list[i].vlan_tag =
6811 rte_cpu_to_le_16(filter[num + i].vlan_id);
6813 switch (filter[num + i].filter_type) {
6814 case RTE_MAC_PERFECT_MATCH:
6815 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6816 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6818 case RTE_MACVLAN_PERFECT_MATCH:
6819 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6821 case RTE_MAC_HASH_MATCH:
6822 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6823 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6825 case RTE_MACVLAN_HASH_MATCH:
6826 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6829 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6830 ret = I40E_ERR_PARAM;
6833 req_list[i].flags = rte_cpu_to_le_16(flags);
6836 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6838 if (ret != I40E_SUCCESS) {
6839 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6843 } while (num < total);
6850 /* Find out specific MAC filter */
6851 static struct i40e_mac_filter *
6852 i40e_find_mac_filter(struct i40e_vsi *vsi,
6853 struct ether_addr *macaddr)
6855 struct i40e_mac_filter *f;
6857 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6858 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6866 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6869 uint32_t vid_idx, vid_bit;
6871 if (vlan_id > ETH_VLAN_ID_MAX)
6874 vid_idx = I40E_VFTA_IDX(vlan_id);
6875 vid_bit = I40E_VFTA_BIT(vlan_id);
6877 if (vsi->vfta[vid_idx] & vid_bit)
6884 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6885 uint16_t vlan_id, bool on)
6887 uint32_t vid_idx, vid_bit;
6889 vid_idx = I40E_VFTA_IDX(vlan_id);
6890 vid_bit = I40E_VFTA_BIT(vlan_id);
6893 vsi->vfta[vid_idx] |= vid_bit;
6895 vsi->vfta[vid_idx] &= ~vid_bit;
6899 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6900 uint16_t vlan_id, bool on)
6902 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6903 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6906 if (vlan_id > ETH_VLAN_ID_MAX)
6909 i40e_store_vlan_filter(vsi, vlan_id, on);
6911 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6914 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6917 ret = i40e_aq_add_vlan(hw, vsi->seid,
6918 &vlan_data, 1, NULL);
6919 if (ret != I40E_SUCCESS)
6920 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6922 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6923 &vlan_data, 1, NULL);
6924 if (ret != I40E_SUCCESS)
6926 "Failed to remove vlan filter");
6931 * Find all vlan options for specific mac addr,
6932 * return with actual vlan found.
6935 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6936 struct i40e_macvlan_filter *mv_f,
6937 int num, struct ether_addr *addr)
6943 * Not to use i40e_find_vlan_filter to decrease the loop time,
6944 * although the code looks complex.
6946 if (num < vsi->vlan_num)
6947 return I40E_ERR_PARAM;
6950 for (j = 0; j < I40E_VFTA_SIZE; j++) {
6952 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6953 if (vsi->vfta[j] & (1 << k)) {
6956 "vlan number doesn't match");
6957 return I40E_ERR_PARAM;
6959 rte_memcpy(&mv_f[i].macaddr,
6960 addr, ETH_ADDR_LEN);
6962 j * I40E_UINT32_BIT_SIZE + k;
6968 return I40E_SUCCESS;
6972 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6973 struct i40e_macvlan_filter *mv_f,
6978 struct i40e_mac_filter *f;
6980 if (num < vsi->mac_num)
6981 return I40E_ERR_PARAM;
6983 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6985 PMD_DRV_LOG(ERR, "buffer number not match");
6986 return I40E_ERR_PARAM;
6988 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6990 mv_f[i].vlan_id = vlan;
6991 mv_f[i].filter_type = f->mac_info.filter_type;
6995 return I40E_SUCCESS;
6999 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
7002 struct i40e_mac_filter *f;
7003 struct i40e_macvlan_filter *mv_f;
7004 int ret = I40E_SUCCESS;
7006 if (vsi == NULL || vsi->mac_num == 0)
7007 return I40E_ERR_PARAM;
7009 /* Case that no vlan is set */
7010 if (vsi->vlan_num == 0)
7013 num = vsi->mac_num * vsi->vlan_num;
7015 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7017 PMD_DRV_LOG(ERR, "failed to allocate memory");
7018 return I40E_ERR_NO_MEMORY;
7022 if (vsi->vlan_num == 0) {
7023 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7024 rte_memcpy(&mv_f[i].macaddr,
7025 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7026 mv_f[i].filter_type = f->mac_info.filter_type;
7027 mv_f[i].vlan_id = 0;
7031 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7032 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7033 vsi->vlan_num, &f->mac_info.mac_addr);
7034 if (ret != I40E_SUCCESS)
7036 for (j = i; j < i + vsi->vlan_num; j++)
7037 mv_f[j].filter_type = f->mac_info.filter_type;
7042 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7050 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7052 struct i40e_macvlan_filter *mv_f;
7054 int ret = I40E_SUCCESS;
7056 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
7057 return I40E_ERR_PARAM;
7059 /* If it's already set, just return */
7060 if (i40e_find_vlan_filter(vsi,vlan))
7061 return I40E_SUCCESS;
7063 mac_num = vsi->mac_num;
7066 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7067 return I40E_ERR_PARAM;
7070 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7073 PMD_DRV_LOG(ERR, "failed to allocate memory");
7074 return I40E_ERR_NO_MEMORY;
7077 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7079 if (ret != I40E_SUCCESS)
7082 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7084 if (ret != I40E_SUCCESS)
7087 i40e_set_vlan_filter(vsi, vlan, 1);
7097 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7099 struct i40e_macvlan_filter *mv_f;
7101 int ret = I40E_SUCCESS;
7104 * Vlan 0 is the generic filter for untagged packets
7105 * and can't be removed.
7107 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
7108 return I40E_ERR_PARAM;
7110 /* If can't find it, just return */
7111 if (!i40e_find_vlan_filter(vsi, vlan))
7112 return I40E_ERR_PARAM;
7114 mac_num = vsi->mac_num;
7117 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7118 return I40E_ERR_PARAM;
7121 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7124 PMD_DRV_LOG(ERR, "failed to allocate memory");
7125 return I40E_ERR_NO_MEMORY;
7128 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7130 if (ret != I40E_SUCCESS)
7133 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7135 if (ret != I40E_SUCCESS)
7138 /* This is last vlan to remove, replace all mac filter with vlan 0 */
7139 if (vsi->vlan_num == 1) {
7140 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7141 if (ret != I40E_SUCCESS)
7144 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7145 if (ret != I40E_SUCCESS)
7149 i40e_set_vlan_filter(vsi, vlan, 0);
7159 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7161 struct i40e_mac_filter *f;
7162 struct i40e_macvlan_filter *mv_f;
7163 int i, vlan_num = 0;
7164 int ret = I40E_SUCCESS;
7166 /* If it's add and we've config it, return */
7167 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7169 return I40E_SUCCESS;
7170 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
7171 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
7174 * If vlan_num is 0, that's the first time to add mac,
7175 * set mask for vlan_id 0.
7177 if (vsi->vlan_num == 0) {
7178 i40e_set_vlan_filter(vsi, 0, 1);
7181 vlan_num = vsi->vlan_num;
7182 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
7183 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
7186 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7188 PMD_DRV_LOG(ERR, "failed to allocate memory");
7189 return I40E_ERR_NO_MEMORY;
7192 for (i = 0; i < vlan_num; i++) {
7193 mv_f[i].filter_type = mac_filter->filter_type;
7194 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7198 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7199 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
7200 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7201 &mac_filter->mac_addr);
7202 if (ret != I40E_SUCCESS)
7206 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7207 if (ret != I40E_SUCCESS)
7210 /* Add the mac addr into mac list */
7211 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7213 PMD_DRV_LOG(ERR, "failed to allocate memory");
7214 ret = I40E_ERR_NO_MEMORY;
7217 rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7219 f->mac_info.filter_type = mac_filter->filter_type;
7220 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7231 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
7233 struct i40e_mac_filter *f;
7234 struct i40e_macvlan_filter *mv_f;
7236 enum rte_mac_filter_type filter_type;
7237 int ret = I40E_SUCCESS;
7239 /* Can't find it, return an error */
7240 f = i40e_find_mac_filter(vsi, addr);
7242 return I40E_ERR_PARAM;
7244 vlan_num = vsi->vlan_num;
7245 filter_type = f->mac_info.filter_type;
7246 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7247 filter_type == RTE_MACVLAN_HASH_MATCH) {
7248 if (vlan_num == 0) {
7249 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7250 return I40E_ERR_PARAM;
7252 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7253 filter_type == RTE_MAC_HASH_MATCH)
7256 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7258 PMD_DRV_LOG(ERR, "failed to allocate memory");
7259 return I40E_ERR_NO_MEMORY;
7262 for (i = 0; i < vlan_num; i++) {
7263 mv_f[i].filter_type = filter_type;
7264 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7267 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7268 filter_type == RTE_MACVLAN_HASH_MATCH) {
7269 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7270 if (ret != I40E_SUCCESS)
7274 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7275 if (ret != I40E_SUCCESS)
7278 /* Remove the mac addr into mac list */
7279 TAILQ_REMOVE(&vsi->mac_list, f, next);
7289 /* Configure hash enable flags for RSS */
7291 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7299 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7300 if (flags & (1ULL << i))
7301 hena |= adapter->pctypes_tbl[i];
7307 /* Parse the hash enable flags */
7309 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7311 uint64_t rss_hf = 0;
7317 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7318 if (flags & adapter->pctypes_tbl[i])
7319 rss_hf |= (1ULL << i);
7326 i40e_pf_disable_rss(struct i40e_pf *pf)
7328 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7330 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7331 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7332 I40E_WRITE_FLUSH(hw);
7336 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7338 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7339 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7340 uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7341 I40E_VFQF_HKEY_MAX_INDEX :
7342 I40E_PFQF_HKEY_MAX_INDEX;
7345 if (!key || key_len == 0) {
7346 PMD_DRV_LOG(DEBUG, "No key to be configured");
7348 } else if (key_len != (key_idx + 1) *
7350 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7354 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7355 struct i40e_aqc_get_set_rss_key_data *key_dw =
7356 (struct i40e_aqc_get_set_rss_key_data *)key;
7358 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7360 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7362 uint32_t *hash_key = (uint32_t *)key;
7365 if (vsi->type == I40E_VSI_SRIOV) {
7366 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7369 I40E_VFQF_HKEY1(i, vsi->user_param),
7373 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7374 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7377 I40E_WRITE_FLUSH(hw);
7384 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7386 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7387 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7391 if (!key || !key_len)
7394 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7395 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7396 (struct i40e_aqc_get_set_rss_key_data *)key);
7398 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7402 uint32_t *key_dw = (uint32_t *)key;
7405 if (vsi->type == I40E_VSI_SRIOV) {
7406 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7407 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7408 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7410 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7413 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7414 reg = I40E_PFQF_HKEY(i);
7415 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7417 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7425 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7427 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7431 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7432 rss_conf->rss_key_len);
7436 hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7437 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7438 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7439 I40E_WRITE_FLUSH(hw);
7445 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7446 struct rte_eth_rss_conf *rss_conf)
7448 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7449 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7450 uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7453 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7454 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7456 if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7457 if (rss_hf != 0) /* Enable RSS */
7459 return 0; /* Nothing to do */
7462 if (rss_hf == 0) /* Disable RSS */
7465 return i40e_hw_rss_hash_set(pf, rss_conf);
7469 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7470 struct rte_eth_rss_conf *rss_conf)
7472 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7473 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7477 ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7478 &rss_conf->rss_key_len);
7482 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7483 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7484 rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7490 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7492 switch (filter_type) {
7493 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7494 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7496 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7497 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7499 case RTE_TUNNEL_FILTER_IMAC_TENID:
7500 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7502 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7503 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7505 case ETH_TUNNEL_FILTER_IMAC:
7506 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7508 case ETH_TUNNEL_FILTER_OIP:
7509 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7511 case ETH_TUNNEL_FILTER_IIP:
7512 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7515 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7522 /* Convert tunnel filter structure */
7524 i40e_tunnel_filter_convert(
7525 struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7526 struct i40e_tunnel_filter *tunnel_filter)
7528 ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
7529 (struct ether_addr *)&tunnel_filter->input.outer_mac);
7530 ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
7531 (struct ether_addr *)&tunnel_filter->input.inner_mac);
7532 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7533 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7534 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7535 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7536 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7538 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7539 tunnel_filter->input.flags = cld_filter->element.flags;
7540 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7541 tunnel_filter->queue = cld_filter->element.queue_number;
7542 rte_memcpy(tunnel_filter->input.general_fields,
7543 cld_filter->general_fields,
7544 sizeof(cld_filter->general_fields));
7549 /* Check if there exists the tunnel filter */
7550 struct i40e_tunnel_filter *
7551 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7552 const struct i40e_tunnel_filter_input *input)
7556 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7560 return tunnel_rule->hash_map[ret];
7563 /* Add a tunnel filter into the SW list */
7565 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7566 struct i40e_tunnel_filter *tunnel_filter)
7568 struct i40e_tunnel_rule *rule = &pf->tunnel;
7571 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7574 "Failed to insert tunnel filter to hash table %d!",
7578 rule->hash_map[ret] = tunnel_filter;
7580 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7585 /* Delete a tunnel filter from the SW list */
7587 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7588 struct i40e_tunnel_filter_input *input)
7590 struct i40e_tunnel_rule *rule = &pf->tunnel;
7591 struct i40e_tunnel_filter *tunnel_filter;
7594 ret = rte_hash_del_key(rule->hash_table, input);
7597 "Failed to delete tunnel filter to hash table %d!",
7601 tunnel_filter = rule->hash_map[ret];
7602 rule->hash_map[ret] = NULL;
7604 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7605 rte_free(tunnel_filter);
7611 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7612 struct rte_eth_tunnel_filter_conf *tunnel_filter,
7616 uint32_t ipv4_addr, ipv4_addr_le;
7617 uint8_t i, tun_type = 0;
7618 /* internal varialbe to convert ipv6 byte order */
7619 uint32_t convert_ipv6[4];
7621 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7622 struct i40e_vsi *vsi = pf->main_vsi;
7623 struct i40e_aqc_cloud_filters_element_bb *cld_filter;
7624 struct i40e_aqc_cloud_filters_element_bb *pfilter;
7625 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7626 struct i40e_tunnel_filter *tunnel, *node;
7627 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7629 cld_filter = rte_zmalloc("tunnel_filter",
7630 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7633 if (NULL == cld_filter) {
7634 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7637 pfilter = cld_filter;
7639 ether_addr_copy(&tunnel_filter->outer_mac,
7640 (struct ether_addr *)&pfilter->element.outer_mac);
7641 ether_addr_copy(&tunnel_filter->inner_mac,
7642 (struct ether_addr *)&pfilter->element.inner_mac);
7644 pfilter->element.inner_vlan =
7645 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7646 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7647 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7648 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7649 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7650 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7652 sizeof(pfilter->element.ipaddr.v4.data));
7654 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7655 for (i = 0; i < 4; i++) {
7657 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7659 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7661 sizeof(pfilter->element.ipaddr.v6.data));
7664 /* check tunneled type */
7665 switch (tunnel_filter->tunnel_type) {
7666 case RTE_TUNNEL_TYPE_VXLAN:
7667 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7669 case RTE_TUNNEL_TYPE_NVGRE:
7670 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7672 case RTE_TUNNEL_TYPE_IP_IN_GRE:
7673 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7676 /* Other tunnel types is not supported. */
7677 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7678 rte_free(cld_filter);
7682 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7683 &pfilter->element.flags);
7685 rte_free(cld_filter);
7689 pfilter->element.flags |= rte_cpu_to_le_16(
7690 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7691 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7692 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7693 pfilter->element.queue_number =
7694 rte_cpu_to_le_16(tunnel_filter->queue_id);
7696 /* Check if there is the filter in SW list */
7697 memset(&check_filter, 0, sizeof(check_filter));
7698 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7699 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7701 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7702 rte_free(cld_filter);
7706 if (!add && !node) {
7707 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7708 rte_free(cld_filter);
7713 ret = i40e_aq_add_cloud_filters(hw,
7714 vsi->seid, &cld_filter->element, 1);
7716 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7717 rte_free(cld_filter);
7720 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7721 if (tunnel == NULL) {
7722 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7723 rte_free(cld_filter);
7727 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7728 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7732 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
7733 &cld_filter->element, 1);
7735 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7736 rte_free(cld_filter);
7739 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7742 rte_free(cld_filter);
7746 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7747 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
7748 #define I40E_TR_GENEVE_KEY_MASK 0x8
7749 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
7750 #define I40E_TR_GRE_KEY_MASK 0x400
7751 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
7752 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
7755 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7757 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7758 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7759 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7760 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7761 enum i40e_status_code status = I40E_SUCCESS;
7763 if (pf->support_multi_driver) {
7764 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7765 return I40E_NOT_SUPPORTED;
7768 memset(&filter_replace, 0,
7769 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7770 memset(&filter_replace_buf, 0,
7771 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7773 /* create L1 filter */
7774 filter_replace.old_filter_type =
7775 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7776 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7777 filter_replace.tr_bit = 0;
7779 /* Prepare the buffer, 3 entries */
7780 filter_replace_buf.data[0] =
7781 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7782 filter_replace_buf.data[0] |=
7783 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7784 filter_replace_buf.data[2] = 0xFF;
7785 filter_replace_buf.data[3] = 0xFF;
7786 filter_replace_buf.data[4] =
7787 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7788 filter_replace_buf.data[4] |=
7789 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7790 filter_replace_buf.data[7] = 0xF0;
7791 filter_replace_buf.data[8]
7792 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7793 filter_replace_buf.data[8] |=
7794 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7795 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7796 I40E_TR_GENEVE_KEY_MASK |
7797 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7798 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7799 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7800 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7802 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7803 &filter_replace_buf);
7804 if (!status && (filter_replace.old_filter_type !=
7805 filter_replace.new_filter_type))
7806 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7807 " original: 0x%x, new: 0x%x",
7809 filter_replace.old_filter_type,
7810 filter_replace.new_filter_type);
7816 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7818 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7819 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7820 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7821 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7822 enum i40e_status_code status = I40E_SUCCESS;
7824 if (pf->support_multi_driver) {
7825 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7826 return I40E_NOT_SUPPORTED;
7830 memset(&filter_replace, 0,
7831 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7832 memset(&filter_replace_buf, 0,
7833 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7834 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7835 I40E_AQC_MIRROR_CLOUD_FILTER;
7836 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7837 filter_replace.new_filter_type =
7838 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7839 /* Prepare the buffer, 2 entries */
7840 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7841 filter_replace_buf.data[0] |=
7842 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7843 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7844 filter_replace_buf.data[4] |=
7845 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7846 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7847 &filter_replace_buf);
7850 if (filter_replace.old_filter_type !=
7851 filter_replace.new_filter_type)
7852 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7853 " original: 0x%x, new: 0x%x",
7855 filter_replace.old_filter_type,
7856 filter_replace.new_filter_type);
7859 memset(&filter_replace, 0,
7860 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7861 memset(&filter_replace_buf, 0,
7862 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7864 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7865 I40E_AQC_MIRROR_CLOUD_FILTER;
7866 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7867 filter_replace.new_filter_type =
7868 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7869 /* Prepare the buffer, 2 entries */
7870 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7871 filter_replace_buf.data[0] |=
7872 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7873 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7874 filter_replace_buf.data[4] |=
7875 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7877 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7878 &filter_replace_buf);
7879 if (!status && (filter_replace.old_filter_type !=
7880 filter_replace.new_filter_type))
7881 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7882 " original: 0x%x, new: 0x%x",
7884 filter_replace.old_filter_type,
7885 filter_replace.new_filter_type);
7890 static enum i40e_status_code
7891 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7893 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7894 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7895 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7896 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7897 enum i40e_status_code status = I40E_SUCCESS;
7899 if (pf->support_multi_driver) {
7900 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7901 return I40E_NOT_SUPPORTED;
7905 memset(&filter_replace, 0,
7906 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7907 memset(&filter_replace_buf, 0,
7908 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7909 /* create L1 filter */
7910 filter_replace.old_filter_type =
7911 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7912 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7913 filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7914 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7915 /* Prepare the buffer, 2 entries */
7916 filter_replace_buf.data[0] =
7917 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7918 filter_replace_buf.data[0] |=
7919 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7920 filter_replace_buf.data[2] = 0xFF;
7921 filter_replace_buf.data[3] = 0xFF;
7922 filter_replace_buf.data[4] =
7923 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7924 filter_replace_buf.data[4] |=
7925 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7926 filter_replace_buf.data[6] = 0xFF;
7927 filter_replace_buf.data[7] = 0xFF;
7928 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7929 &filter_replace_buf);
7932 if (filter_replace.old_filter_type !=
7933 filter_replace.new_filter_type)
7934 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7935 " original: 0x%x, new: 0x%x",
7937 filter_replace.old_filter_type,
7938 filter_replace.new_filter_type);
7941 memset(&filter_replace, 0,
7942 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7943 memset(&filter_replace_buf, 0,
7944 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7945 /* create L1 filter */
7946 filter_replace.old_filter_type =
7947 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
7948 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
7949 filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
7950 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7951 /* Prepare the buffer, 2 entries */
7952 filter_replace_buf.data[0] =
7953 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7954 filter_replace_buf.data[0] |=
7955 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7956 filter_replace_buf.data[2] = 0xFF;
7957 filter_replace_buf.data[3] = 0xFF;
7958 filter_replace_buf.data[4] =
7959 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7960 filter_replace_buf.data[4] |=
7961 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7962 filter_replace_buf.data[6] = 0xFF;
7963 filter_replace_buf.data[7] = 0xFF;
7965 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7966 &filter_replace_buf);
7967 if (!status && (filter_replace.old_filter_type !=
7968 filter_replace.new_filter_type))
7969 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7970 " original: 0x%x, new: 0x%x",
7972 filter_replace.old_filter_type,
7973 filter_replace.new_filter_type);
7979 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
7981 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7982 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7983 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7984 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7985 enum i40e_status_code status = I40E_SUCCESS;
7987 if (pf->support_multi_driver) {
7988 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7989 return I40E_NOT_SUPPORTED;
7993 memset(&filter_replace, 0,
7994 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7995 memset(&filter_replace_buf, 0,
7996 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7997 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7998 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7999 filter_replace.new_filter_type =
8000 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8001 /* Prepare the buffer, 2 entries */
8002 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
8003 filter_replace_buf.data[0] |=
8004 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8005 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8006 filter_replace_buf.data[4] |=
8007 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8008 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8009 &filter_replace_buf);
8012 if (filter_replace.old_filter_type !=
8013 filter_replace.new_filter_type)
8014 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8015 " original: 0x%x, new: 0x%x",
8017 filter_replace.old_filter_type,
8018 filter_replace.new_filter_type);
8021 memset(&filter_replace, 0,
8022 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8023 memset(&filter_replace_buf, 0,
8024 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8025 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8026 filter_replace.old_filter_type =
8027 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8028 filter_replace.new_filter_type =
8029 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8030 /* Prepare the buffer, 2 entries */
8031 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8032 filter_replace_buf.data[0] |=
8033 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8034 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8035 filter_replace_buf.data[4] |=
8036 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8038 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8039 &filter_replace_buf);
8040 if (!status && (filter_replace.old_filter_type !=
8041 filter_replace.new_filter_type))
8042 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8043 " original: 0x%x, new: 0x%x",
8045 filter_replace.old_filter_type,
8046 filter_replace.new_filter_type);
8052 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8053 struct i40e_tunnel_filter_conf *tunnel_filter,
8057 uint32_t ipv4_addr, ipv4_addr_le;
8058 uint8_t i, tun_type = 0;
8059 /* internal variable to convert ipv6 byte order */
8060 uint32_t convert_ipv6[4];
8062 struct i40e_pf_vf *vf = NULL;
8063 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8064 struct i40e_vsi *vsi;
8065 struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8066 struct i40e_aqc_cloud_filters_element_bb *pfilter;
8067 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8068 struct i40e_tunnel_filter *tunnel, *node;
8069 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8071 bool big_buffer = 0;
8073 cld_filter = rte_zmalloc("tunnel_filter",
8074 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8077 if (cld_filter == NULL) {
8078 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8081 pfilter = cld_filter;
8083 ether_addr_copy(&tunnel_filter->outer_mac,
8084 (struct ether_addr *)&pfilter->element.outer_mac);
8085 ether_addr_copy(&tunnel_filter->inner_mac,
8086 (struct ether_addr *)&pfilter->element.inner_mac);
8088 pfilter->element.inner_vlan =
8089 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8090 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8091 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8092 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8093 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8094 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8096 sizeof(pfilter->element.ipaddr.v4.data));
8098 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8099 for (i = 0; i < 4; i++) {
8101 rte_cpu_to_le_32(rte_be_to_cpu_32(
8102 tunnel_filter->ip_addr.ipv6_addr[i]));
8104 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8106 sizeof(pfilter->element.ipaddr.v6.data));
8109 /* check tunneled type */
8110 switch (tunnel_filter->tunnel_type) {
8111 case I40E_TUNNEL_TYPE_VXLAN:
8112 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8114 case I40E_TUNNEL_TYPE_NVGRE:
8115 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8117 case I40E_TUNNEL_TYPE_IP_IN_GRE:
8118 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8120 case I40E_TUNNEL_TYPE_MPLSoUDP:
8121 if (!pf->mpls_replace_flag) {
8122 i40e_replace_mpls_l1_filter(pf);
8123 i40e_replace_mpls_cloud_filter(pf);
8124 pf->mpls_replace_flag = 1;
8126 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8127 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8129 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8130 (teid_le & 0xF) << 12;
8131 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8134 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8136 case I40E_TUNNEL_TYPE_MPLSoGRE:
8137 if (!pf->mpls_replace_flag) {
8138 i40e_replace_mpls_l1_filter(pf);
8139 i40e_replace_mpls_cloud_filter(pf);
8140 pf->mpls_replace_flag = 1;
8142 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8143 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8145 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8146 (teid_le & 0xF) << 12;
8147 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8150 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8152 case I40E_TUNNEL_TYPE_GTPC:
8153 if (!pf->gtp_replace_flag) {
8154 i40e_replace_gtp_l1_filter(pf);
8155 i40e_replace_gtp_cloud_filter(pf);
8156 pf->gtp_replace_flag = 1;
8158 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8159 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8160 (teid_le >> 16) & 0xFFFF;
8161 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8163 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8167 case I40E_TUNNEL_TYPE_GTPU:
8168 if (!pf->gtp_replace_flag) {
8169 i40e_replace_gtp_l1_filter(pf);
8170 i40e_replace_gtp_cloud_filter(pf);
8171 pf->gtp_replace_flag = 1;
8173 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8174 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8175 (teid_le >> 16) & 0xFFFF;
8176 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8178 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8182 case I40E_TUNNEL_TYPE_QINQ:
8183 if (!pf->qinq_replace_flag) {
8184 ret = i40e_cloud_filter_qinq_create(pf);
8187 "QinQ tunnel filter already created.");
8188 pf->qinq_replace_flag = 1;
8190 /* Add in the General fields the values of
8191 * the Outer and Inner VLAN
8192 * Big Buffer should be set, see changes in
8193 * i40e_aq_add_cloud_filters
8195 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8196 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8200 /* Other tunnel types is not supported. */
8201 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8202 rte_free(cld_filter);
8206 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8207 pfilter->element.flags =
8208 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8209 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8210 pfilter->element.flags =
8211 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8212 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8213 pfilter->element.flags =
8214 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8215 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8216 pfilter->element.flags =
8217 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8218 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8219 pfilter->element.flags |=
8220 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8222 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8223 &pfilter->element.flags);
8225 rte_free(cld_filter);
8230 pfilter->element.flags |= rte_cpu_to_le_16(
8231 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8232 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8233 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8234 pfilter->element.queue_number =
8235 rte_cpu_to_le_16(tunnel_filter->queue_id);
8237 if (!tunnel_filter->is_to_vf)
8240 if (tunnel_filter->vf_id >= pf->vf_num) {
8241 PMD_DRV_LOG(ERR, "Invalid argument.");
8242 rte_free(cld_filter);
8245 vf = &pf->vfs[tunnel_filter->vf_id];
8249 /* Check if there is the filter in SW list */
8250 memset(&check_filter, 0, sizeof(check_filter));
8251 i40e_tunnel_filter_convert(cld_filter, &check_filter);
8252 check_filter.is_to_vf = tunnel_filter->is_to_vf;
8253 check_filter.vf_id = tunnel_filter->vf_id;
8254 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8256 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8257 rte_free(cld_filter);
8261 if (!add && !node) {
8262 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8263 rte_free(cld_filter);
8269 ret = i40e_aq_add_cloud_filters_bb(hw,
8270 vsi->seid, cld_filter, 1);
8272 ret = i40e_aq_add_cloud_filters(hw,
8273 vsi->seid, &cld_filter->element, 1);
8275 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8276 rte_free(cld_filter);
8279 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8280 if (tunnel == NULL) {
8281 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8282 rte_free(cld_filter);
8286 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8287 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8292 ret = i40e_aq_rem_cloud_filters_bb(
8293 hw, vsi->seid, cld_filter, 1);
8295 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8296 &cld_filter->element, 1);
8298 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8299 rte_free(cld_filter);
8302 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8305 rte_free(cld_filter);
8310 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8314 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8315 if (pf->vxlan_ports[i] == port)
8323 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
8327 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8329 idx = i40e_get_vxlan_port_idx(pf, port);
8331 /* Check if port already exists */
8333 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8337 /* Now check if there is space to add the new port */
8338 idx = i40e_get_vxlan_port_idx(pf, 0);
8341 "Maximum number of UDP ports reached, not adding port %d",
8346 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
8349 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8353 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8356 /* New port: add it and mark its index in the bitmap */
8357 pf->vxlan_ports[idx] = port;
8358 pf->vxlan_bitmap |= (1 << idx);
8360 if (!(pf->flags & I40E_FLAG_VXLAN))
8361 pf->flags |= I40E_FLAG_VXLAN;
8367 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8370 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8372 if (!(pf->flags & I40E_FLAG_VXLAN)) {
8373 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8377 idx = i40e_get_vxlan_port_idx(pf, port);
8380 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8384 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8385 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8389 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8392 pf->vxlan_ports[idx] = 0;
8393 pf->vxlan_bitmap &= ~(1 << idx);
8395 if (!pf->vxlan_bitmap)
8396 pf->flags &= ~I40E_FLAG_VXLAN;
8401 /* Add UDP tunneling port */
8403 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8404 struct rte_eth_udp_tunnel *udp_tunnel)
8407 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8409 if (udp_tunnel == NULL)
8412 switch (udp_tunnel->prot_type) {
8413 case RTE_TUNNEL_TYPE_VXLAN:
8414 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
8417 case RTE_TUNNEL_TYPE_GENEVE:
8418 case RTE_TUNNEL_TYPE_TEREDO:
8419 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8424 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8432 /* Remove UDP tunneling port */
8434 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8435 struct rte_eth_udp_tunnel *udp_tunnel)
8438 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8440 if (udp_tunnel == NULL)
8443 switch (udp_tunnel->prot_type) {
8444 case RTE_TUNNEL_TYPE_VXLAN:
8445 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8447 case RTE_TUNNEL_TYPE_GENEVE:
8448 case RTE_TUNNEL_TYPE_TEREDO:
8449 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8453 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8461 /* Calculate the maximum number of contiguous PF queues that are configured */
8463 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8465 struct rte_eth_dev_data *data = pf->dev_data;
8467 struct i40e_rx_queue *rxq;
8470 for (i = 0; i < pf->lan_nb_qps; i++) {
8471 rxq = data->rx_queues[i];
8472 if (rxq && rxq->q_set)
8483 i40e_pf_config_rss(struct i40e_pf *pf)
8485 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8486 struct rte_eth_rss_conf rss_conf;
8487 uint32_t i, lut = 0;
8491 * If both VMDQ and RSS enabled, not all of PF queues are configured.
8492 * It's necessary to calculate the actual PF queues that are configured.
8494 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8495 num = i40e_pf_calc_configured_queues_num(pf);
8497 num = pf->dev_data->nb_rx_queues;
8499 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8500 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8504 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
8508 if (pf->adapter->rss_reta_updated == 0) {
8509 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8512 lut = (lut << 8) | (j & ((0x1 <<
8513 hw->func_caps.rss_table_entry_width) - 1));
8515 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2),
8520 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8521 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8522 i40e_pf_disable_rss(pf);
8525 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8526 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8527 /* Random default keys */
8528 static uint32_t rss_key_default[] = {0x6b793944,
8529 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8530 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8531 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8533 rss_conf.rss_key = (uint8_t *)rss_key_default;
8534 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8538 return i40e_hw_rss_hash_set(pf, &rss_conf);
8542 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8543 struct rte_eth_tunnel_filter_conf *filter)
8545 if (pf == NULL || filter == NULL) {
8546 PMD_DRV_LOG(ERR, "Invalid parameter");
8550 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8551 PMD_DRV_LOG(ERR, "Invalid queue ID");
8555 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
8556 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8560 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8561 (is_zero_ether_addr(&filter->outer_mac))) {
8562 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8566 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8567 (is_zero_ether_addr(&filter->inner_mac))) {
8568 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8575 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8576 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
8578 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8580 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8584 if (pf->support_multi_driver) {
8585 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8589 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8590 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8593 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8594 } else if (len == 4) {
8595 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8597 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8602 ret = i40e_aq_debug_write_global_register(hw,
8603 I40E_GL_PRS_FVBM(2),
8607 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8608 "with value 0x%08x",
8609 I40E_GL_PRS_FVBM(2), reg);
8613 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8614 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8620 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8627 switch (cfg->cfg_type) {
8628 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8629 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8632 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8640 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8641 enum rte_filter_op filter_op,
8644 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8645 int ret = I40E_ERR_PARAM;
8647 switch (filter_op) {
8648 case RTE_ETH_FILTER_SET:
8649 ret = i40e_dev_global_config_set(hw,
8650 (struct rte_eth_global_cfg *)arg);
8653 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8661 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8662 enum rte_filter_op filter_op,
8665 struct rte_eth_tunnel_filter_conf *filter;
8666 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8667 int ret = I40E_SUCCESS;
8669 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8671 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8672 return I40E_ERR_PARAM;
8674 switch (filter_op) {
8675 case RTE_ETH_FILTER_NOP:
8676 if (!(pf->flags & I40E_FLAG_VXLAN))
8677 ret = I40E_NOT_SUPPORTED;
8679 case RTE_ETH_FILTER_ADD:
8680 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8682 case RTE_ETH_FILTER_DELETE:
8683 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8686 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8687 ret = I40E_ERR_PARAM;
8695 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8698 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8701 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8702 ret = i40e_pf_config_rss(pf);
8704 i40e_pf_disable_rss(pf);
8709 /* Get the symmetric hash enable configurations per port */
8711 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8713 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8715 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8718 /* Set the symmetric hash enable configurations per port */
8720 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8722 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8725 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8727 "Symmetric hash has already been enabled");
8730 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8732 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8734 "Symmetric hash has already been disabled");
8737 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8739 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8740 I40E_WRITE_FLUSH(hw);
8744 * Get global configurations of hash function type and symmetric hash enable
8745 * per flow type (pctype). Note that global configuration means it affects all
8746 * the ports on the same NIC.
8749 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8750 struct rte_eth_hash_global_conf *g_cfg)
8752 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8756 memset(g_cfg, 0, sizeof(*g_cfg));
8757 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8758 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8759 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8761 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8762 PMD_DRV_LOG(DEBUG, "Hash function is %s",
8763 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8766 * As i40e supports less than 64 flow types, only first 64 bits need to
8769 for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8770 g_cfg->valid_bit_mask[i] = 0ULL;
8771 g_cfg->sym_hash_enable_mask[i] = 0ULL;
8774 g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
8776 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
8777 if (!adapter->pctypes_tbl[i])
8779 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8780 j < I40E_FILTER_PCTYPE_MAX; j++) {
8781 if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8782 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8783 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8784 g_cfg->sym_hash_enable_mask[0] |=
8795 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8796 const struct rte_eth_hash_global_conf *g_cfg)
8799 uint64_t mask0, i40e_mask = adapter->flow_types_mask;
8801 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8802 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8803 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8804 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8810 * As i40e supports less than 64 flow types, only first 64 bits need to
8813 mask0 = g_cfg->valid_bit_mask[0];
8814 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8816 /* Check if any unsupported flow type configured */
8817 if ((mask0 | i40e_mask) ^ i40e_mask)
8820 if (g_cfg->valid_bit_mask[i])
8828 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8834 * Set global configurations of hash function type and symmetric hash enable
8835 * per flow type (pctype). Note any modifying global configuration will affect
8836 * all the ports on the same NIC.
8839 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8840 struct rte_eth_hash_global_conf *g_cfg)
8842 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8843 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8847 uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
8849 if (pf->support_multi_driver) {
8850 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
8854 /* Check the input parameters */
8855 ret = i40e_hash_global_config_check(adapter, g_cfg);
8860 * As i40e supports less than 64 flow types, only first 64 bits need to
8863 for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
8864 if (mask0 & (1UL << i)) {
8865 reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
8866 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8868 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8869 j < I40E_FILTER_PCTYPE_MAX; j++) {
8870 if (adapter->pctypes_tbl[i] & (1ULL << j))
8871 i40e_write_global_rx_ctl(hw,
8878 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8879 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8881 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8883 "Hash function already set to Toeplitz");
8886 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8887 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8889 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8891 "Hash function already set to Simple XOR");
8894 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8896 /* Use the default, and keep it as it is */
8899 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
8902 I40E_WRITE_FLUSH(hw);
8908 * Valid input sets for hash and flow director filters per PCTYPE
8911 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8912 enum rte_filter_type filter)
8916 static const uint64_t valid_hash_inset_table[] = {
8917 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8918 I40E_INSET_DMAC | I40E_INSET_SMAC |
8919 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8920 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8921 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8922 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8923 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8924 I40E_INSET_FLEX_PAYLOAD,
8925 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8926 I40E_INSET_DMAC | I40E_INSET_SMAC |
8927 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8928 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8929 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8930 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8931 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8932 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8933 I40E_INSET_FLEX_PAYLOAD,
8934 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8935 I40E_INSET_DMAC | I40E_INSET_SMAC |
8936 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8937 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8938 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8939 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8940 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8941 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8942 I40E_INSET_FLEX_PAYLOAD,
8943 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8944 I40E_INSET_DMAC | I40E_INSET_SMAC |
8945 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8946 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8947 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8948 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8949 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8950 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8951 I40E_INSET_FLEX_PAYLOAD,
8952 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8953 I40E_INSET_DMAC | I40E_INSET_SMAC |
8954 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8955 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8956 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8957 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8958 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8959 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8960 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8961 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8962 I40E_INSET_DMAC | I40E_INSET_SMAC |
8963 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8964 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8965 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8966 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8967 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8968 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8969 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8970 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8971 I40E_INSET_DMAC | I40E_INSET_SMAC |
8972 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8973 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8974 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8975 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8976 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8977 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8978 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8979 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8980 I40E_INSET_DMAC | I40E_INSET_SMAC |
8981 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8982 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8983 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8984 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8985 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8986 I40E_INSET_FLEX_PAYLOAD,
8987 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8988 I40E_INSET_DMAC | I40E_INSET_SMAC |
8989 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8990 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8991 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8992 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8993 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8994 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8995 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8996 I40E_INSET_DMAC | I40E_INSET_SMAC |
8997 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8998 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8999 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9000 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9001 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9002 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
9003 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9004 I40E_INSET_DMAC | I40E_INSET_SMAC |
9005 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9006 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9007 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9008 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9009 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9010 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9011 I40E_INSET_FLEX_PAYLOAD,
9012 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9013 I40E_INSET_DMAC | I40E_INSET_SMAC |
9014 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9015 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9016 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9017 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9018 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9019 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9020 I40E_INSET_FLEX_PAYLOAD,
9021 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9022 I40E_INSET_DMAC | I40E_INSET_SMAC |
9023 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9024 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9025 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9026 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9027 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9028 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9029 I40E_INSET_FLEX_PAYLOAD,
9030 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9031 I40E_INSET_DMAC | I40E_INSET_SMAC |
9032 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9033 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9034 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9035 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9036 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9037 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9038 I40E_INSET_FLEX_PAYLOAD,
9039 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9040 I40E_INSET_DMAC | I40E_INSET_SMAC |
9041 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9042 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9043 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9044 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9045 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9046 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9047 I40E_INSET_FLEX_PAYLOAD,
9048 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9049 I40E_INSET_DMAC | I40E_INSET_SMAC |
9050 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9051 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9052 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9053 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9054 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9055 I40E_INSET_FLEX_PAYLOAD,
9056 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9057 I40E_INSET_DMAC | I40E_INSET_SMAC |
9058 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9059 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9060 I40E_INSET_FLEX_PAYLOAD,
9064 * Flow director supports only fields defined in
9065 * union rte_eth_fdir_flow.
9067 static const uint64_t valid_fdir_inset_table[] = {
9068 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9069 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9070 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9071 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9072 I40E_INSET_IPV4_TTL,
9073 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9074 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9075 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9076 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9077 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9078 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9079 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9080 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9081 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9082 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9083 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9084 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9085 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9086 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9087 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9088 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9089 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9090 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9091 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9092 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9093 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9094 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9095 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9096 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9097 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9098 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9099 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9100 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9101 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9102 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9104 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9105 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9106 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9107 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9108 I40E_INSET_IPV4_TTL,
9109 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9110 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9111 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9112 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9113 I40E_INSET_IPV6_HOP_LIMIT,
9114 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9115 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9116 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9117 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9118 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9119 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9120 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9121 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9122 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9123 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9124 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9125 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9126 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9127 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9128 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9129 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9130 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9131 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9132 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9133 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9134 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9135 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9136 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9137 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9138 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9139 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9140 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9141 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9142 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9143 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9145 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9146 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9147 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9148 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9149 I40E_INSET_IPV6_HOP_LIMIT,
9150 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9151 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9152 I40E_INSET_LAST_ETHER_TYPE,
9155 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9157 if (filter == RTE_ETH_FILTER_HASH)
9158 valid = valid_hash_inset_table[pctype];
9160 valid = valid_fdir_inset_table[pctype];
9166 * Validate if the input set is allowed for a specific PCTYPE
9169 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9170 enum rte_filter_type filter, uint64_t inset)
9174 valid = i40e_get_valid_input_set(pctype, filter);
9175 if (inset & (~valid))
9181 /* default input set fields combination per pctype */
9183 i40e_get_default_input_set(uint16_t pctype)
9185 static const uint64_t default_inset_table[] = {
9186 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9187 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9188 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9189 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9190 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9191 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9192 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9193 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9194 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9195 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9196 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9197 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9198 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9199 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9200 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9201 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9202 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9203 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9204 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9205 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9207 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9208 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9209 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9210 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9211 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9212 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9213 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9214 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9215 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9216 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9217 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9218 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9219 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9220 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9221 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9222 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9223 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9224 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9225 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9226 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9227 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9228 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9230 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9231 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9232 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9233 I40E_INSET_LAST_ETHER_TYPE,
9236 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9239 return default_inset_table[pctype];
9243 * Parse the input set from index to logical bit masks
9246 i40e_parse_input_set(uint64_t *inset,
9247 enum i40e_filter_pctype pctype,
9248 enum rte_eth_input_set_field *field,
9254 static const struct {
9255 enum rte_eth_input_set_field field;
9257 } inset_convert_table[] = {
9258 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9259 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9260 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9261 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9262 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9263 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9264 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9265 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9266 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9267 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9268 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9269 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9270 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9271 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9272 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9273 I40E_INSET_IPV6_NEXT_HDR},
9274 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9275 I40E_INSET_IPV6_HOP_LIMIT},
9276 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9277 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9278 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9279 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9280 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9281 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9282 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9283 I40E_INSET_SCTP_VT},
9284 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9285 I40E_INSET_TUNNEL_DMAC},
9286 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9287 I40E_INSET_VLAN_TUNNEL},
9288 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9289 I40E_INSET_TUNNEL_ID},
9290 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9291 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9292 I40E_INSET_FLEX_PAYLOAD_W1},
9293 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9294 I40E_INSET_FLEX_PAYLOAD_W2},
9295 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9296 I40E_INSET_FLEX_PAYLOAD_W3},
9297 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9298 I40E_INSET_FLEX_PAYLOAD_W4},
9299 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9300 I40E_INSET_FLEX_PAYLOAD_W5},
9301 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9302 I40E_INSET_FLEX_PAYLOAD_W6},
9303 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9304 I40E_INSET_FLEX_PAYLOAD_W7},
9305 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9306 I40E_INSET_FLEX_PAYLOAD_W8},
9309 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9312 /* Only one item allowed for default or all */
9314 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9315 *inset = i40e_get_default_input_set(pctype);
9317 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9318 *inset = I40E_INSET_NONE;
9323 for (i = 0, *inset = 0; i < size; i++) {
9324 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9325 if (field[i] == inset_convert_table[j].field) {
9326 *inset |= inset_convert_table[j].inset;
9331 /* It contains unsupported input set, return immediately */
9332 if (j == RTE_DIM(inset_convert_table))
9340 * Translate the input set from bit masks to register aware bit masks
9344 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9354 static const struct inset_map inset_map_common[] = {
9355 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9356 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9357 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9358 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9359 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9360 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9361 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9362 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9363 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9364 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9365 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9366 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9367 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9368 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9369 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9370 {I40E_INSET_TUNNEL_DMAC,
9371 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9372 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9373 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9374 {I40E_INSET_TUNNEL_SRC_PORT,
9375 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9376 {I40E_INSET_TUNNEL_DST_PORT,
9377 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9378 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9379 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9380 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9381 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9382 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9383 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9384 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9385 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9386 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9389 /* some different registers map in x722*/
9390 static const struct inset_map inset_map_diff_x722[] = {
9391 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9392 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9393 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9394 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9397 static const struct inset_map inset_map_diff_not_x722[] = {
9398 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9399 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9400 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9401 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9407 /* Translate input set to register aware inset */
9408 if (type == I40E_MAC_X722) {
9409 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9410 if (input & inset_map_diff_x722[i].inset)
9411 val |= inset_map_diff_x722[i].inset_reg;
9414 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9415 if (input & inset_map_diff_not_x722[i].inset)
9416 val |= inset_map_diff_not_x722[i].inset_reg;
9420 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9421 if (input & inset_map_common[i].inset)
9422 val |= inset_map_common[i].inset_reg;
9429 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9432 uint64_t inset_need_mask = inset;
9434 static const struct {
9437 } inset_mask_map[] = {
9438 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9439 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9440 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9441 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9442 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9443 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9444 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9445 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9448 if (!inset || !mask || !nb_elem)
9451 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9452 /* Clear the inset bit, if no MASK is required,
9453 * for example proto + ttl
9455 if ((inset & inset_mask_map[i].inset) ==
9456 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9457 inset_need_mask &= ~inset_mask_map[i].inset;
9458 if (!inset_need_mask)
9461 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9462 if ((inset_need_mask & inset_mask_map[i].inset) ==
9463 inset_mask_map[i].inset) {
9464 if (idx >= nb_elem) {
9465 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9468 mask[idx] = inset_mask_map[i].mask;
9477 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9479 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9481 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9483 i40e_write_rx_ctl(hw, addr, val);
9484 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9485 (uint32_t)i40e_read_rx_ctl(hw, addr));
9489 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9491 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9492 struct rte_eth_dev *dev;
9494 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
9496 i40e_write_rx_ctl(hw, addr, val);
9497 PMD_DRV_LOG(WARNING,
9498 "i40e device %s changed global register [0x%08x]."
9499 " original: 0x%08x, new: 0x%08x",
9500 dev->device->name, addr, reg,
9501 (uint32_t)i40e_read_rx_ctl(hw, addr));
9506 i40e_filter_input_set_init(struct i40e_pf *pf)
9508 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9509 enum i40e_filter_pctype pctype;
9510 uint64_t input_set, inset_reg;
9511 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9515 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9516 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9517 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9519 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9522 input_set = i40e_get_default_input_set(pctype);
9524 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9525 I40E_INSET_MASK_NUM_REG);
9528 if (pf->support_multi_driver && num > 0) {
9529 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9532 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9535 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9536 (uint32_t)(inset_reg & UINT32_MAX));
9537 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9538 (uint32_t)((inset_reg >>
9539 I40E_32_BIT_WIDTH) & UINT32_MAX));
9540 if (!pf->support_multi_driver) {
9541 i40e_check_write_global_reg(hw,
9542 I40E_GLQF_HASH_INSET(0, pctype),
9543 (uint32_t)(inset_reg & UINT32_MAX));
9544 i40e_check_write_global_reg(hw,
9545 I40E_GLQF_HASH_INSET(1, pctype),
9546 (uint32_t)((inset_reg >>
9547 I40E_32_BIT_WIDTH) & UINT32_MAX));
9549 for (i = 0; i < num; i++) {
9550 i40e_check_write_global_reg(hw,
9551 I40E_GLQF_FD_MSK(i, pctype),
9553 i40e_check_write_global_reg(hw,
9554 I40E_GLQF_HASH_MSK(i, pctype),
9557 /*clear unused mask registers of the pctype */
9558 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9559 i40e_check_write_global_reg(hw,
9560 I40E_GLQF_FD_MSK(i, pctype),
9562 i40e_check_write_global_reg(hw,
9563 I40E_GLQF_HASH_MSK(i, pctype),
9567 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9569 I40E_WRITE_FLUSH(hw);
9571 /* store the default input set */
9572 if (!pf->support_multi_driver)
9573 pf->hash_input_set[pctype] = input_set;
9574 pf->fdir.input_set[pctype] = input_set;
9579 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9580 struct rte_eth_input_set_conf *conf)
9582 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9583 enum i40e_filter_pctype pctype;
9584 uint64_t input_set, inset_reg = 0;
9585 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9589 PMD_DRV_LOG(ERR, "Invalid pointer");
9592 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9593 conf->op != RTE_ETH_INPUT_SET_ADD) {
9594 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9598 if (pf->support_multi_driver) {
9599 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9603 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9604 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9605 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9609 if (hw->mac.type == I40E_MAC_X722) {
9610 /* get translated pctype value in fd pctype register */
9611 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9612 I40E_GLQF_FD_PCTYPES((int)pctype));
9615 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9618 PMD_DRV_LOG(ERR, "Failed to parse input set");
9622 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9623 /* get inset value in register */
9624 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9625 inset_reg <<= I40E_32_BIT_WIDTH;
9626 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9627 input_set |= pf->hash_input_set[pctype];
9629 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9630 I40E_INSET_MASK_NUM_REG);
9634 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9636 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9637 (uint32_t)(inset_reg & UINT32_MAX));
9638 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9639 (uint32_t)((inset_reg >>
9640 I40E_32_BIT_WIDTH) & UINT32_MAX));
9642 for (i = 0; i < num; i++)
9643 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9645 /*clear unused mask registers of the pctype */
9646 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9647 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9649 I40E_WRITE_FLUSH(hw);
9651 pf->hash_input_set[pctype] = input_set;
9656 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9657 struct rte_eth_input_set_conf *conf)
9659 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9660 enum i40e_filter_pctype pctype;
9661 uint64_t input_set, inset_reg = 0;
9662 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9666 PMD_DRV_LOG(ERR, "Invalid pointer");
9669 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9670 conf->op != RTE_ETH_INPUT_SET_ADD) {
9671 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9675 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9677 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9678 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9682 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9685 PMD_DRV_LOG(ERR, "Failed to parse input set");
9689 /* get inset value in register */
9690 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9691 inset_reg <<= I40E_32_BIT_WIDTH;
9692 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9694 /* Can not change the inset reg for flex payload for fdir,
9695 * it is done by writing I40E_PRTQF_FD_FLXINSET
9696 * in i40e_set_flex_mask_on_pctype.
9698 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9699 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9701 input_set |= pf->fdir.input_set[pctype];
9702 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9703 I40E_INSET_MASK_NUM_REG);
9706 if (pf->support_multi_driver && num > 0) {
9707 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9711 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9713 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9714 (uint32_t)(inset_reg & UINT32_MAX));
9715 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9716 (uint32_t)((inset_reg >>
9717 I40E_32_BIT_WIDTH) & UINT32_MAX));
9719 if (!pf->support_multi_driver) {
9720 for (i = 0; i < num; i++)
9721 i40e_check_write_global_reg(hw,
9722 I40E_GLQF_FD_MSK(i, pctype),
9724 /*clear unused mask registers of the pctype */
9725 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9726 i40e_check_write_global_reg(hw,
9727 I40E_GLQF_FD_MSK(i, pctype),
9730 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9732 I40E_WRITE_FLUSH(hw);
9734 pf->fdir.input_set[pctype] = input_set;
9739 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9744 PMD_DRV_LOG(ERR, "Invalid pointer");
9748 switch (info->info_type) {
9749 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9750 i40e_get_symmetric_hash_enable_per_port(hw,
9751 &(info->info.enable));
9753 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9754 ret = i40e_get_hash_filter_global_config(hw,
9755 &(info->info.global_conf));
9758 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9768 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9773 PMD_DRV_LOG(ERR, "Invalid pointer");
9777 switch (info->info_type) {
9778 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9779 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9781 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9782 ret = i40e_set_hash_filter_global_config(hw,
9783 &(info->info.global_conf));
9785 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9786 ret = i40e_hash_filter_inset_select(hw,
9787 &(info->info.input_set_conf));
9791 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9800 /* Operations for hash function */
9802 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9803 enum rte_filter_op filter_op,
9806 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9809 switch (filter_op) {
9810 case RTE_ETH_FILTER_NOP:
9812 case RTE_ETH_FILTER_GET:
9813 ret = i40e_hash_filter_get(hw,
9814 (struct rte_eth_hash_filter_info *)arg);
9816 case RTE_ETH_FILTER_SET:
9817 ret = i40e_hash_filter_set(hw,
9818 (struct rte_eth_hash_filter_info *)arg);
9821 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9830 /* Convert ethertype filter structure */
9832 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9833 struct i40e_ethertype_filter *filter)
9835 rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
9836 filter->input.ether_type = input->ether_type;
9837 filter->flags = input->flags;
9838 filter->queue = input->queue;
9843 /* Check if there exists the ehtertype filter */
9844 struct i40e_ethertype_filter *
9845 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9846 const struct i40e_ethertype_filter_input *input)
9850 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9854 return ethertype_rule->hash_map[ret];
9857 /* Add ethertype filter in SW list */
9859 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9860 struct i40e_ethertype_filter *filter)
9862 struct i40e_ethertype_rule *rule = &pf->ethertype;
9865 ret = rte_hash_add_key(rule->hash_table, &filter->input);
9868 "Failed to insert ethertype filter"
9869 " to hash table %d!",
9873 rule->hash_map[ret] = filter;
9875 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9880 /* Delete ethertype filter in SW list */
9882 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9883 struct i40e_ethertype_filter_input *input)
9885 struct i40e_ethertype_rule *rule = &pf->ethertype;
9886 struct i40e_ethertype_filter *filter;
9889 ret = rte_hash_del_key(rule->hash_table, input);
9892 "Failed to delete ethertype filter"
9893 " to hash table %d!",
9897 filter = rule->hash_map[ret];
9898 rule->hash_map[ret] = NULL;
9900 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9907 * Configure ethertype filter, which can director packet by filtering
9908 * with mac address and ether_type or only ether_type
9911 i40e_ethertype_filter_set(struct i40e_pf *pf,
9912 struct rte_eth_ethertype_filter *filter,
9915 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9916 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9917 struct i40e_ethertype_filter *ethertype_filter, *node;
9918 struct i40e_ethertype_filter check_filter;
9919 struct i40e_control_filter_stats stats;
9923 if (filter->queue >= pf->dev_data->nb_rx_queues) {
9924 PMD_DRV_LOG(ERR, "Invalid queue ID");
9927 if (filter->ether_type == ETHER_TYPE_IPv4 ||
9928 filter->ether_type == ETHER_TYPE_IPv6) {
9930 "unsupported ether_type(0x%04x) in control packet filter.",
9931 filter->ether_type);
9934 if (filter->ether_type == ETHER_TYPE_VLAN)
9935 PMD_DRV_LOG(WARNING,
9936 "filter vlan ether_type in first tag is not supported.");
9938 /* Check if there is the filter in SW list */
9939 memset(&check_filter, 0, sizeof(check_filter));
9940 i40e_ethertype_filter_convert(filter, &check_filter);
9941 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9942 &check_filter.input);
9944 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9948 if (!add && !node) {
9949 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9953 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9954 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9955 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9956 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9957 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9959 memset(&stats, 0, sizeof(stats));
9960 ret = i40e_aq_add_rem_control_packet_filter(hw,
9961 filter->mac_addr.addr_bytes,
9962 filter->ether_type, flags,
9964 filter->queue, add, &stats, NULL);
9967 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9968 ret, stats.mac_etype_used, stats.etype_used,
9969 stats.mac_etype_free, stats.etype_free);
9973 /* Add or delete a filter in SW list */
9975 ethertype_filter = rte_zmalloc("ethertype_filter",
9976 sizeof(*ethertype_filter), 0);
9977 if (ethertype_filter == NULL) {
9978 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
9982 rte_memcpy(ethertype_filter, &check_filter,
9983 sizeof(check_filter));
9984 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9986 rte_free(ethertype_filter);
9988 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9995 * Handle operations for ethertype filter.
9998 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9999 enum rte_filter_op filter_op,
10002 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10005 if (filter_op == RTE_ETH_FILTER_NOP)
10009 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
10014 switch (filter_op) {
10015 case RTE_ETH_FILTER_ADD:
10016 ret = i40e_ethertype_filter_set(pf,
10017 (struct rte_eth_ethertype_filter *)arg,
10020 case RTE_ETH_FILTER_DELETE:
10021 ret = i40e_ethertype_filter_set(pf,
10022 (struct rte_eth_ethertype_filter *)arg,
10026 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
10034 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
10035 enum rte_filter_type filter_type,
10036 enum rte_filter_op filter_op,
10044 switch (filter_type) {
10045 case RTE_ETH_FILTER_NONE:
10046 /* For global configuration */
10047 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
10049 case RTE_ETH_FILTER_HASH:
10050 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
10052 case RTE_ETH_FILTER_MACVLAN:
10053 ret = i40e_mac_filter_handle(dev, filter_op, arg);
10055 case RTE_ETH_FILTER_ETHERTYPE:
10056 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
10058 case RTE_ETH_FILTER_TUNNEL:
10059 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
10061 case RTE_ETH_FILTER_FDIR:
10062 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
10064 case RTE_ETH_FILTER_GENERIC:
10065 if (filter_op != RTE_ETH_FILTER_GET)
10067 *(const void **)arg = &i40e_flow_ops;
10070 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
10080 * Check and enable Extended Tag.
10081 * Enabling Extended Tag is important for 40G performance.
10084 i40e_enable_extended_tag(struct rte_eth_dev *dev)
10086 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10090 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10093 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10097 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
10098 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
10103 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10106 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10110 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
10111 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
10114 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
10115 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
10118 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
10125 * As some registers wouldn't be reset unless a global hardware reset,
10126 * hardware initialization is needed to put those registers into an
10127 * expected initial state.
10130 i40e_hw_init(struct rte_eth_dev *dev)
10132 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10134 i40e_enable_extended_tag(dev);
10136 /* clear the PF Queue Filter control register */
10137 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
10139 /* Disable symmetric hash per port */
10140 i40e_set_symmetric_hash_enable_per_port(hw, 0);
10144 * For X722 it is possible to have multiple pctypes mapped to the same flowtype
10145 * however this function will return only one highest pctype index,
10146 * which is not quite correct. This is known problem of i40e driver
10147 * and needs to be fixed later.
10149 enum i40e_filter_pctype
10150 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
10153 uint64_t pctype_mask;
10155 if (flow_type < I40E_FLOW_TYPE_MAX) {
10156 pctype_mask = adapter->pctypes_tbl[flow_type];
10157 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
10158 if (pctype_mask & (1ULL << i))
10159 return (enum i40e_filter_pctype)i;
10162 return I40E_FILTER_PCTYPE_INVALID;
10166 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
10167 enum i40e_filter_pctype pctype)
10170 uint64_t pctype_mask = 1ULL << pctype;
10172 for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
10174 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
10178 return RTE_ETH_FLOW_UNKNOWN;
10182 * On X710, performance number is far from the expectation on recent firmware
10183 * versions; on XL710, performance number is also far from the expectation on
10184 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10185 * mode is enabled and port MAC address is equal to the packet destination MAC
10186 * address. The fix for this issue may not be integrated in the following
10187 * firmware version. So the workaround in software driver is needed. It needs
10188 * to modify the initial values of 3 internal only registers for both X710 and
10189 * XL710. Note that the values for X710 or XL710 could be different, and the
10190 * workaround can be removed when it is fixed in firmware in the future.
10193 /* For both X710 and XL710 */
10194 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1 0x10000200
10195 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x203F0200
10196 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
10198 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10199 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
10202 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10203 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10206 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
10208 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
10209 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
10212 * GL_SWR_PM_UP_THR:
10213 * The value is not impacted from the link speed, its value is set according
10214 * to the total number of ports for a better pipe-monitor configuration.
10217 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10219 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10220 .device_id = (dev), \
10221 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10223 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10224 .device_id = (dev), \
10225 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10227 static const struct {
10228 uint16_t device_id;
10230 } swr_pm_table[] = {
10231 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10232 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10233 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10234 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10236 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10237 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10238 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10239 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10240 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10241 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10242 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10246 if (value == NULL) {
10247 PMD_DRV_LOG(ERR, "value is NULL");
10251 for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10252 if (hw->device_id == swr_pm_table[i].device_id) {
10253 *value = swr_pm_table[i].val;
10255 PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10257 hw->device_id, *value);
10266 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10268 enum i40e_status_code status;
10269 struct i40e_aq_get_phy_abilities_resp phy_ab;
10270 int ret = -ENOTSUP;
10273 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10277 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10280 rte_delay_us(100000);
10282 status = i40e_aq_get_phy_capabilities(hw, false,
10283 true, &phy_ab, NULL);
10291 i40e_configure_registers(struct i40e_hw *hw)
10297 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10298 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10299 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10305 for (i = 0; i < RTE_DIM(reg_table); i++) {
10306 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10307 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10309 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10310 else /* For X710/XL710/XXV710 */
10311 if (hw->aq.fw_maj_ver < 6)
10313 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10316 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10319 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10320 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10322 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10323 else /* For X710/XL710/XXV710 */
10325 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10328 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10331 if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10332 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10333 "GL_SWR_PM_UP_THR value fixup",
10338 reg_table[i].val = cfg_val;
10341 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10344 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10345 reg_table[i].addr);
10348 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10349 reg_table[i].addr, reg);
10350 if (reg == reg_table[i].val)
10353 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10354 reg_table[i].val, NULL);
10357 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10358 reg_table[i].val, reg_table[i].addr);
10361 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10362 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10366 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
10367 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
10368 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
10369 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10371 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10376 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10377 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10381 /* Configure for double VLAN RX stripping */
10382 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10383 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10384 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10385 ret = i40e_aq_debug_write_register(hw,
10386 I40E_VSI_TSR(vsi->vsi_id),
10389 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10391 return I40E_ERR_CONFIG;
10395 /* Configure for double VLAN TX insertion */
10396 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10397 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10398 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10399 ret = i40e_aq_debug_write_register(hw,
10400 I40E_VSI_L2TAGSTXVALID(
10401 vsi->vsi_id), reg, NULL);
10404 "Failed to update VSI_L2TAGSTXVALID[%d]",
10406 return I40E_ERR_CONFIG;
10414 * i40e_aq_add_mirror_rule
10415 * @hw: pointer to the hardware structure
10416 * @seid: VEB seid to add mirror rule to
10417 * @dst_id: destination vsi seid
10418 * @entries: Buffer which contains the entities to be mirrored
10419 * @count: number of entities contained in the buffer
10420 * @rule_id:the rule_id of the rule to be added
10422 * Add a mirror rule for a given veb.
10425 static enum i40e_status_code
10426 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10427 uint16_t seid, uint16_t dst_id,
10428 uint16_t rule_type, uint16_t *entries,
10429 uint16_t count, uint16_t *rule_id)
10431 struct i40e_aq_desc desc;
10432 struct i40e_aqc_add_delete_mirror_rule cmd;
10433 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10434 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10437 enum i40e_status_code status;
10439 i40e_fill_default_direct_cmd_desc(&desc,
10440 i40e_aqc_opc_add_mirror_rule);
10441 memset(&cmd, 0, sizeof(cmd));
10443 buff_len = sizeof(uint16_t) * count;
10444 desc.datalen = rte_cpu_to_le_16(buff_len);
10446 desc.flags |= rte_cpu_to_le_16(
10447 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10448 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10449 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10450 cmd.num_entries = rte_cpu_to_le_16(count);
10451 cmd.seid = rte_cpu_to_le_16(seid);
10452 cmd.destination = rte_cpu_to_le_16(dst_id);
10454 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10455 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10457 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10458 hw->aq.asq_last_status, resp->rule_id,
10459 resp->mirror_rules_used, resp->mirror_rules_free);
10460 *rule_id = rte_le_to_cpu_16(resp->rule_id);
10466 * i40e_aq_del_mirror_rule
10467 * @hw: pointer to the hardware structure
10468 * @seid: VEB seid to add mirror rule to
10469 * @entries: Buffer which contains the entities to be mirrored
10470 * @count: number of entities contained in the buffer
10471 * @rule_id:the rule_id of the rule to be delete
10473 * Delete a mirror rule for a given veb.
10476 static enum i40e_status_code
10477 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10478 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10479 uint16_t count, uint16_t rule_id)
10481 struct i40e_aq_desc desc;
10482 struct i40e_aqc_add_delete_mirror_rule cmd;
10483 uint16_t buff_len = 0;
10484 enum i40e_status_code status;
10487 i40e_fill_default_direct_cmd_desc(&desc,
10488 i40e_aqc_opc_delete_mirror_rule);
10489 memset(&cmd, 0, sizeof(cmd));
10490 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10491 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10493 cmd.num_entries = count;
10494 buff_len = sizeof(uint16_t) * count;
10495 desc.datalen = rte_cpu_to_le_16(buff_len);
10496 buff = (void *)entries;
10498 /* rule id is filled in destination field for deleting mirror rule */
10499 cmd.destination = rte_cpu_to_le_16(rule_id);
10501 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10502 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10503 cmd.seid = rte_cpu_to_le_16(seid);
10505 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10506 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10512 * i40e_mirror_rule_set
10513 * @dev: pointer to the hardware structure
10514 * @mirror_conf: mirror rule info
10515 * @sw_id: mirror rule's sw_id
10516 * @on: enable/disable
10518 * set a mirror rule.
10522 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10523 struct rte_eth_mirror_conf *mirror_conf,
10524 uint8_t sw_id, uint8_t on)
10526 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10527 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10528 struct i40e_mirror_rule *it, *mirr_rule = NULL;
10529 struct i40e_mirror_rule *parent = NULL;
10530 uint16_t seid, dst_seid, rule_id;
10534 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10536 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10538 "mirror rule can not be configured without veb or vfs.");
10541 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10542 PMD_DRV_LOG(ERR, "mirror table is full.");
10545 if (mirror_conf->dst_pool > pf->vf_num) {
10546 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10547 mirror_conf->dst_pool);
10551 seid = pf->main_vsi->veb->seid;
10553 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10554 if (sw_id <= it->index) {
10560 if (mirr_rule && sw_id == mirr_rule->index) {
10562 PMD_DRV_LOG(ERR, "mirror rule exists.");
10565 ret = i40e_aq_del_mirror_rule(hw, seid,
10566 mirr_rule->rule_type,
10567 mirr_rule->entries,
10568 mirr_rule->num_entries, mirr_rule->id);
10571 "failed to remove mirror rule: ret = %d, aq_err = %d.",
10572 ret, hw->aq.asq_last_status);
10575 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10576 rte_free(mirr_rule);
10577 pf->nb_mirror_rule--;
10581 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10585 mirr_rule = rte_zmalloc("i40e_mirror_rule",
10586 sizeof(struct i40e_mirror_rule) , 0);
10588 PMD_DRV_LOG(ERR, "failed to allocate memory");
10589 return I40E_ERR_NO_MEMORY;
10591 switch (mirror_conf->rule_type) {
10592 case ETH_MIRROR_VLAN:
10593 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10594 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10595 mirr_rule->entries[j] =
10596 mirror_conf->vlan.vlan_id[i];
10601 PMD_DRV_LOG(ERR, "vlan is not specified.");
10602 rte_free(mirr_rule);
10605 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10607 case ETH_MIRROR_VIRTUAL_POOL_UP:
10608 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10609 /* check if the specified pool bit is out of range */
10610 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10611 PMD_DRV_LOG(ERR, "pool mask is out of range.");
10612 rte_free(mirr_rule);
10615 for (i = 0, j = 0; i < pf->vf_num; i++) {
10616 if (mirror_conf->pool_mask & (1ULL << i)) {
10617 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10621 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10622 /* add pf vsi to entries */
10623 mirr_rule->entries[j] = pf->main_vsi_seid;
10627 PMD_DRV_LOG(ERR, "pool is not specified.");
10628 rte_free(mirr_rule);
10631 /* egress and ingress in aq commands means from switch but not port */
10632 mirr_rule->rule_type =
10633 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10634 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10635 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10637 case ETH_MIRROR_UPLINK_PORT:
10638 /* egress and ingress in aq commands means from switch but not port*/
10639 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10641 case ETH_MIRROR_DOWNLINK_PORT:
10642 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10645 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10646 mirror_conf->rule_type);
10647 rte_free(mirr_rule);
10651 /* If the dst_pool is equal to vf_num, consider it as PF */
10652 if (mirror_conf->dst_pool == pf->vf_num)
10653 dst_seid = pf->main_vsi_seid;
10655 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10657 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10658 mirr_rule->rule_type, mirr_rule->entries,
10662 "failed to add mirror rule: ret = %d, aq_err = %d.",
10663 ret, hw->aq.asq_last_status);
10664 rte_free(mirr_rule);
10668 mirr_rule->index = sw_id;
10669 mirr_rule->num_entries = j;
10670 mirr_rule->id = rule_id;
10671 mirr_rule->dst_vsi_seid = dst_seid;
10674 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10676 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10678 pf->nb_mirror_rule++;
10683 * i40e_mirror_rule_reset
10684 * @dev: pointer to the device
10685 * @sw_id: mirror rule's sw_id
10687 * reset a mirror rule.
10691 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10693 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10694 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10695 struct i40e_mirror_rule *it, *mirr_rule = NULL;
10699 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10701 seid = pf->main_vsi->veb->seid;
10703 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10704 if (sw_id == it->index) {
10710 ret = i40e_aq_del_mirror_rule(hw, seid,
10711 mirr_rule->rule_type,
10712 mirr_rule->entries,
10713 mirr_rule->num_entries, mirr_rule->id);
10716 "failed to remove mirror rule: status = %d, aq_err = %d.",
10717 ret, hw->aq.asq_last_status);
10720 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10721 rte_free(mirr_rule);
10722 pf->nb_mirror_rule--;
10724 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10731 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10733 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10734 uint64_t systim_cycles;
10736 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10737 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10740 return systim_cycles;
10744 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10746 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10747 uint64_t rx_tstamp;
10749 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10750 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10757 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10759 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10760 uint64_t tx_tstamp;
10762 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10763 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10770 i40e_start_timecounters(struct rte_eth_dev *dev)
10772 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10773 struct i40e_adapter *adapter =
10774 (struct i40e_adapter *)dev->data->dev_private;
10775 struct rte_eth_link link;
10776 uint32_t tsync_inc_l;
10777 uint32_t tsync_inc_h;
10779 /* Get current link speed. */
10780 i40e_dev_link_update(dev, 1);
10781 rte_eth_linkstatus_get(dev, &link);
10783 switch (link.link_speed) {
10784 case ETH_SPEED_NUM_40G:
10785 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10786 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10788 case ETH_SPEED_NUM_10G:
10789 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10790 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10792 case ETH_SPEED_NUM_1G:
10793 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10794 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10801 /* Set the timesync increment value. */
10802 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10803 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10805 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10806 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10807 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10809 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10810 adapter->systime_tc.cc_shift = 0;
10811 adapter->systime_tc.nsec_mask = 0;
10813 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10814 adapter->rx_tstamp_tc.cc_shift = 0;
10815 adapter->rx_tstamp_tc.nsec_mask = 0;
10817 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10818 adapter->tx_tstamp_tc.cc_shift = 0;
10819 adapter->tx_tstamp_tc.nsec_mask = 0;
10823 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10825 struct i40e_adapter *adapter =
10826 (struct i40e_adapter *)dev->data->dev_private;
10828 adapter->systime_tc.nsec += delta;
10829 adapter->rx_tstamp_tc.nsec += delta;
10830 adapter->tx_tstamp_tc.nsec += delta;
10836 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10839 struct i40e_adapter *adapter =
10840 (struct i40e_adapter *)dev->data->dev_private;
10842 ns = rte_timespec_to_ns(ts);
10844 /* Set the timecounters to a new value. */
10845 adapter->systime_tc.nsec = ns;
10846 adapter->rx_tstamp_tc.nsec = ns;
10847 adapter->tx_tstamp_tc.nsec = ns;
10853 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10855 uint64_t ns, systime_cycles;
10856 struct i40e_adapter *adapter =
10857 (struct i40e_adapter *)dev->data->dev_private;
10859 systime_cycles = i40e_read_systime_cyclecounter(dev);
10860 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10861 *ts = rte_ns_to_timespec(ns);
10867 i40e_timesync_enable(struct rte_eth_dev *dev)
10869 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10870 uint32_t tsync_ctl_l;
10871 uint32_t tsync_ctl_h;
10873 /* Stop the timesync system time. */
10874 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10875 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10876 /* Reset the timesync system time value. */
10877 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10878 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10880 i40e_start_timecounters(dev);
10882 /* Clear timesync registers. */
10883 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10884 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10885 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10886 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10887 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10888 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10890 /* Enable timestamping of PTP packets. */
10891 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10892 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10894 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10895 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10896 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10898 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10899 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10905 i40e_timesync_disable(struct rte_eth_dev *dev)
10907 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10908 uint32_t tsync_ctl_l;
10909 uint32_t tsync_ctl_h;
10911 /* Disable timestamping of transmitted PTP packets. */
10912 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10913 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10915 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10916 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10918 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10919 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10921 /* Reset the timesync increment value. */
10922 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10923 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10929 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10930 struct timespec *timestamp, uint32_t flags)
10932 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10933 struct i40e_adapter *adapter =
10934 (struct i40e_adapter *)dev->data->dev_private;
10936 uint32_t sync_status;
10937 uint32_t index = flags & 0x03;
10938 uint64_t rx_tstamp_cycles;
10941 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10942 if ((sync_status & (1 << index)) == 0)
10945 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10946 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10947 *timestamp = rte_ns_to_timespec(ns);
10953 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10954 struct timespec *timestamp)
10956 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10957 struct i40e_adapter *adapter =
10958 (struct i40e_adapter *)dev->data->dev_private;
10960 uint32_t sync_status;
10961 uint64_t tx_tstamp_cycles;
10964 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10965 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10968 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10969 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10970 *timestamp = rte_ns_to_timespec(ns);
10976 * i40e_parse_dcb_configure - parse dcb configure from user
10977 * @dev: the device being configured
10978 * @dcb_cfg: pointer of the result of parse
10979 * @*tc_map: bit map of enabled traffic classes
10981 * Returns 0 on success, negative value on failure
10984 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10985 struct i40e_dcbx_config *dcb_cfg,
10988 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10989 uint8_t i, tc_bw, bw_lf;
10991 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10993 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10994 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10995 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10999 /* assume each tc has the same bw */
11000 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
11001 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11002 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
11003 /* to ensure the sum of tcbw is equal to 100 */
11004 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
11005 for (i = 0; i < bw_lf; i++)
11006 dcb_cfg->etscfg.tcbwtable[i]++;
11008 /* assume each tc has the same Transmission Selection Algorithm */
11009 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11010 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
11012 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11013 dcb_cfg->etscfg.prioritytable[i] =
11014 dcb_rx_conf->dcb_tc[i];
11016 /* FW needs one App to configure HW */
11017 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
11018 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
11019 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
11020 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
11022 if (dcb_rx_conf->nb_tcs == 0)
11023 *tc_map = 1; /* tc0 only */
11025 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
11027 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
11028 dcb_cfg->pfc.willing = 0;
11029 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
11030 dcb_cfg->pfc.pfcenable = *tc_map;
11036 static enum i40e_status_code
11037 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
11038 struct i40e_aqc_vsi_properties_data *info,
11039 uint8_t enabled_tcmap)
11041 enum i40e_status_code ret;
11042 int i, total_tc = 0;
11043 uint16_t qpnum_per_tc, bsf, qp_idx;
11044 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
11045 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
11046 uint16_t used_queues;
11048 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
11049 if (ret != I40E_SUCCESS)
11052 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11053 if (enabled_tcmap & (1 << i))
11058 vsi->enabled_tc = enabled_tcmap;
11060 /* different VSI has different queues assigned */
11061 if (vsi->type == I40E_VSI_MAIN)
11062 used_queues = dev_data->nb_rx_queues -
11063 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11064 else if (vsi->type == I40E_VSI_VMDQ2)
11065 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11067 PMD_INIT_LOG(ERR, "unsupported VSI type.");
11068 return I40E_ERR_NO_AVAILABLE_VSI;
11071 qpnum_per_tc = used_queues / total_tc;
11072 /* Number of queues per enabled TC */
11073 if (qpnum_per_tc == 0) {
11074 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
11075 return I40E_ERR_INVALID_QP_ID;
11077 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
11078 I40E_MAX_Q_PER_TC);
11079 bsf = rte_bsf32(qpnum_per_tc);
11082 * Configure TC and queue mapping parameters, for enabled TC,
11083 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
11084 * default queue will serve it.
11087 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11088 if (vsi->enabled_tc & (1 << i)) {
11089 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
11090 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
11091 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
11092 qp_idx += qpnum_per_tc;
11094 info->tc_mapping[i] = 0;
11097 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
11098 if (vsi->type == I40E_VSI_SRIOV) {
11099 info->mapping_flags |=
11100 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
11101 for (i = 0; i < vsi->nb_qps; i++)
11102 info->queue_mapping[i] =
11103 rte_cpu_to_le_16(vsi->base_queue + i);
11105 info->mapping_flags |=
11106 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
11107 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
11109 info->valid_sections |=
11110 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
11112 return I40E_SUCCESS;
11116 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
11117 * @veb: VEB to be configured
11118 * @tc_map: enabled TC bitmap
11120 * Returns 0 on success, negative value on failure
11122 static enum i40e_status_code
11123 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
11125 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
11126 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
11127 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
11128 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
11129 enum i40e_status_code ret = I40E_SUCCESS;
11133 /* Check if enabled_tc is same as existing or new TCs */
11134 if (veb->enabled_tc == tc_map)
11137 /* configure tc bandwidth */
11138 memset(&veb_bw, 0, sizeof(veb_bw));
11139 veb_bw.tc_valid_bits = tc_map;
11140 /* Enable ETS TCs with equal BW Share for now across all VSIs */
11141 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11142 if (tc_map & BIT_ULL(i))
11143 veb_bw.tc_bw_share_credits[i] = 1;
11145 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
11149 "AQ command Config switch_comp BW allocation per TC failed = %d",
11150 hw->aq.asq_last_status);
11154 memset(&ets_query, 0, sizeof(ets_query));
11155 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
11157 if (ret != I40E_SUCCESS) {
11159 "Failed to get switch_comp ETS configuration %u",
11160 hw->aq.asq_last_status);
11163 memset(&bw_query, 0, sizeof(bw_query));
11164 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
11166 if (ret != I40E_SUCCESS) {
11168 "Failed to get switch_comp bandwidth configuration %u",
11169 hw->aq.asq_last_status);
11173 /* store and print out BW info */
11174 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
11175 veb->bw_info.bw_max = ets_query.tc_bw_max;
11176 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
11177 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
11178 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
11179 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
11180 I40E_16_BIT_WIDTH);
11181 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11182 veb->bw_info.bw_ets_share_credits[i] =
11183 bw_query.tc_bw_share_credits[i];
11184 veb->bw_info.bw_ets_credits[i] =
11185 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
11186 /* 4 bits per TC, 4th bit is reserved */
11187 veb->bw_info.bw_ets_max[i] =
11188 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
11189 RTE_LEN2MASK(3, uint8_t));
11190 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
11191 veb->bw_info.bw_ets_share_credits[i]);
11192 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11193 veb->bw_info.bw_ets_credits[i]);
11194 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11195 veb->bw_info.bw_ets_max[i]);
11198 veb->enabled_tc = tc_map;
11205 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11206 * @vsi: VSI to be configured
11207 * @tc_map: enabled TC bitmap
11209 * Returns 0 on success, negative value on failure
11211 static enum i40e_status_code
11212 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11214 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11215 struct i40e_vsi_context ctxt;
11216 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11217 enum i40e_status_code ret = I40E_SUCCESS;
11220 /* Check if enabled_tc is same as existing or new TCs */
11221 if (vsi->enabled_tc == tc_map)
11224 /* configure tc bandwidth */
11225 memset(&bw_data, 0, sizeof(bw_data));
11226 bw_data.tc_valid_bits = tc_map;
11227 /* Enable ETS TCs with equal BW Share for now across all VSIs */
11228 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11229 if (tc_map & BIT_ULL(i))
11230 bw_data.tc_bw_credits[i] = 1;
11232 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11235 "AQ command Config VSI BW allocation per TC failed = %d",
11236 hw->aq.asq_last_status);
11239 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11240 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11242 /* Update Queue Pairs Mapping for currently enabled UPs */
11243 ctxt.seid = vsi->seid;
11244 ctxt.pf_num = hw->pf_id;
11246 ctxt.uplink_seid = vsi->uplink_seid;
11247 ctxt.info = vsi->info;
11249 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11253 /* Update the VSI after updating the VSI queue-mapping information */
11254 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11256 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11257 hw->aq.asq_last_status);
11260 /* update the local VSI info with updated queue map */
11261 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11262 sizeof(vsi->info.tc_mapping));
11263 rte_memcpy(&vsi->info.queue_mapping,
11264 &ctxt.info.queue_mapping,
11265 sizeof(vsi->info.queue_mapping));
11266 vsi->info.mapping_flags = ctxt.info.mapping_flags;
11267 vsi->info.valid_sections = 0;
11269 /* query and update current VSI BW information */
11270 ret = i40e_vsi_get_bw_config(vsi);
11273 "Failed updating vsi bw info, err %s aq_err %s",
11274 i40e_stat_str(hw, ret),
11275 i40e_aq_str(hw, hw->aq.asq_last_status));
11279 vsi->enabled_tc = tc_map;
11286 * i40e_dcb_hw_configure - program the dcb setting to hw
11287 * @pf: pf the configuration is taken on
11288 * @new_cfg: new configuration
11289 * @tc_map: enabled TC bitmap
11291 * Returns 0 on success, negative value on failure
11293 static enum i40e_status_code
11294 i40e_dcb_hw_configure(struct i40e_pf *pf,
11295 struct i40e_dcbx_config *new_cfg,
11298 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11299 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11300 struct i40e_vsi *main_vsi = pf->main_vsi;
11301 struct i40e_vsi_list *vsi_list;
11302 enum i40e_status_code ret;
11306 /* Use the FW API if FW > v4.4*/
11307 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11308 (hw->aq.fw_maj_ver >= 5))) {
11310 "FW < v4.4, can not use FW LLDP API to configure DCB");
11311 return I40E_ERR_FIRMWARE_API_VERSION;
11314 /* Check if need reconfiguration */
11315 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11316 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11317 return I40E_SUCCESS;
11320 /* Copy the new config to the current config */
11321 *old_cfg = *new_cfg;
11322 old_cfg->etsrec = old_cfg->etscfg;
11323 ret = i40e_set_dcb_config(hw);
11325 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11326 i40e_stat_str(hw, ret),
11327 i40e_aq_str(hw, hw->aq.asq_last_status));
11330 /* set receive Arbiter to RR mode and ETS scheme by default */
11331 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11332 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11333 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
11334 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11335 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11336 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11337 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11338 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11339 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11340 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11341 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11342 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11343 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11345 /* get local mib to check whether it is configured correctly */
11347 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11348 /* Get Local DCB Config */
11349 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11350 &hw->local_dcbx_config);
11352 /* if Veb is created, need to update TC of it at first */
11353 if (main_vsi->veb) {
11354 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11356 PMD_INIT_LOG(WARNING,
11357 "Failed configuring TC for VEB seid=%d",
11358 main_vsi->veb->seid);
11360 /* Update each VSI */
11361 i40e_vsi_config_tc(main_vsi, tc_map);
11362 if (main_vsi->veb) {
11363 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11364 /* Beside main VSI and VMDQ VSIs, only enable default
11365 * TC for other VSIs
11367 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11368 ret = i40e_vsi_config_tc(vsi_list->vsi,
11371 ret = i40e_vsi_config_tc(vsi_list->vsi,
11372 I40E_DEFAULT_TCMAP);
11374 PMD_INIT_LOG(WARNING,
11375 "Failed configuring TC for VSI seid=%d",
11376 vsi_list->vsi->seid);
11380 return I40E_SUCCESS;
11384 * i40e_dcb_init_configure - initial dcb config
11385 * @dev: device being configured
11386 * @sw_dcb: indicate whether dcb is sw configured or hw offload
11388 * Returns 0 on success, negative value on failure
11391 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11393 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11394 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11397 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11398 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11402 /* DCB initialization:
11403 * Update DCB configuration from the Firmware and configure
11404 * LLDP MIB change event.
11406 if (sw_dcb == TRUE) {
11407 /* When using NVM 6.01 or later, the RX data path does
11408 * not hang if the FW LLDP is stopped.
11410 if (((hw->nvm.version >> 12) & 0xf) >= 6 &&
11411 ((hw->nvm.version >> 4) & 0xff) >= 1) {
11412 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
11413 if (ret != I40E_SUCCESS)
11414 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
11417 ret = i40e_init_dcb(hw);
11418 /* If lldp agent is stopped, the return value from
11419 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11420 * adminq status. Otherwise, it should return success.
11422 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11423 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11424 memset(&hw->local_dcbx_config, 0,
11425 sizeof(struct i40e_dcbx_config));
11426 /* set dcb default configuration */
11427 hw->local_dcbx_config.etscfg.willing = 0;
11428 hw->local_dcbx_config.etscfg.maxtcs = 0;
11429 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11430 hw->local_dcbx_config.etscfg.tsatable[0] =
11432 /* all UPs mapping to TC0 */
11433 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11434 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11435 hw->local_dcbx_config.etsrec =
11436 hw->local_dcbx_config.etscfg;
11437 hw->local_dcbx_config.pfc.willing = 0;
11438 hw->local_dcbx_config.pfc.pfccap =
11439 I40E_MAX_TRAFFIC_CLASS;
11440 /* FW needs one App to configure HW */
11441 hw->local_dcbx_config.numapps = 1;
11442 hw->local_dcbx_config.app[0].selector =
11443 I40E_APP_SEL_ETHTYPE;
11444 hw->local_dcbx_config.app[0].priority = 3;
11445 hw->local_dcbx_config.app[0].protocolid =
11446 I40E_APP_PROTOID_FCOE;
11447 ret = i40e_set_dcb_config(hw);
11450 "default dcb config fails. err = %d, aq_err = %d.",
11451 ret, hw->aq.asq_last_status);
11456 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11457 ret, hw->aq.asq_last_status);
11461 ret = i40e_aq_start_lldp(hw, NULL);
11462 if (ret != I40E_SUCCESS)
11463 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11465 ret = i40e_init_dcb(hw);
11467 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11469 "HW doesn't support DCBX offload.");
11474 "DCBX configuration failed, err = %d, aq_err = %d.",
11475 ret, hw->aq.asq_last_status);
11483 * i40e_dcb_setup - setup dcb related config
11484 * @dev: device being configured
11486 * Returns 0 on success, negative value on failure
11489 i40e_dcb_setup(struct rte_eth_dev *dev)
11491 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11492 struct i40e_dcbx_config dcb_cfg;
11493 uint8_t tc_map = 0;
11496 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11497 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11501 if (pf->vf_num != 0)
11502 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11504 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11506 PMD_INIT_LOG(ERR, "invalid dcb config");
11509 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11511 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11519 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11520 struct rte_eth_dcb_info *dcb_info)
11522 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11523 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11524 struct i40e_vsi *vsi = pf->main_vsi;
11525 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11526 uint16_t bsf, tc_mapping;
11529 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11530 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11532 dcb_info->nb_tcs = 1;
11533 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11534 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11535 for (i = 0; i < dcb_info->nb_tcs; i++)
11536 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11538 /* get queue mapping if vmdq is disabled */
11539 if (!pf->nb_cfg_vmdq_vsi) {
11540 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11541 if (!(vsi->enabled_tc & (1 << i)))
11543 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11544 dcb_info->tc_queue.tc_rxq[j][i].base =
11545 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11546 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11547 dcb_info->tc_queue.tc_txq[j][i].base =
11548 dcb_info->tc_queue.tc_rxq[j][i].base;
11549 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11550 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11551 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11552 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11553 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11558 /* get queue mapping if vmdq is enabled */
11560 vsi = pf->vmdq[j].vsi;
11561 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11562 if (!(vsi->enabled_tc & (1 << i)))
11564 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11565 dcb_info->tc_queue.tc_rxq[j][i].base =
11566 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11567 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11568 dcb_info->tc_queue.tc_txq[j][i].base =
11569 dcb_info->tc_queue.tc_rxq[j][i].base;
11570 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11571 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11572 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11573 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11574 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11577 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11582 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11584 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11585 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11586 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11587 uint16_t msix_intr;
11589 msix_intr = intr_handle->intr_vec[queue_id];
11590 if (msix_intr == I40E_MISC_VEC_ID)
11591 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11592 I40E_PFINT_DYN_CTL0_INTENA_MASK |
11593 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11594 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11597 I40E_PFINT_DYN_CTLN(msix_intr -
11598 I40E_RX_VEC_START),
11599 I40E_PFINT_DYN_CTLN_INTENA_MASK |
11600 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11601 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11603 I40E_WRITE_FLUSH(hw);
11604 rte_intr_enable(&pci_dev->intr_handle);
11610 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11612 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11613 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11614 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11615 uint16_t msix_intr;
11617 msix_intr = intr_handle->intr_vec[queue_id];
11618 if (msix_intr == I40E_MISC_VEC_ID)
11619 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11620 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11623 I40E_PFINT_DYN_CTLN(msix_intr -
11624 I40E_RX_VEC_START),
11625 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11626 I40E_WRITE_FLUSH(hw);
11632 * This function is used to check if the register is valid.
11633 * Below is the valid registers list for X722 only:
11637 * 0x208e00--0x209000
11638 * 0x20be00--0x20c000
11639 * 0x263c00--0x264000
11640 * 0x265c00--0x266000
11642 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset)
11644 if ((type != I40E_MAC_X722) &&
11645 ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) ||
11646 (reg_offset >= 0x38700 && reg_offset <= 0x38a00) ||
11647 (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) ||
11648 (reg_offset >= 0x208e00 && reg_offset <= 0x209000) ||
11649 (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) ||
11650 (reg_offset >= 0x263c00 && reg_offset <= 0x264000) ||
11651 (reg_offset >= 0x265c00 && reg_offset <= 0x266000)))
11657 static int i40e_get_regs(struct rte_eth_dev *dev,
11658 struct rte_dev_reg_info *regs)
11660 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11661 uint32_t *ptr_data = regs->data;
11662 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11663 const struct i40e_reg_info *reg_info;
11665 if (ptr_data == NULL) {
11666 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11667 regs->width = sizeof(uint32_t);
11671 /* The first few registers have to be read using AQ operations */
11673 while (i40e_regs_adminq[reg_idx].name) {
11674 reg_info = &i40e_regs_adminq[reg_idx++];
11675 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11677 arr_idx2 <= reg_info->count2;
11679 reg_offset = arr_idx * reg_info->stride1 +
11680 arr_idx2 * reg_info->stride2;
11681 reg_offset += reg_info->base_addr;
11682 ptr_data[reg_offset >> 2] =
11683 i40e_read_rx_ctl(hw, reg_offset);
11687 /* The remaining registers can be read using primitives */
11689 while (i40e_regs_others[reg_idx].name) {
11690 reg_info = &i40e_regs_others[reg_idx++];
11691 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11693 arr_idx2 <= reg_info->count2;
11695 reg_offset = arr_idx * reg_info->stride1 +
11696 arr_idx2 * reg_info->stride2;
11697 reg_offset += reg_info->base_addr;
11698 if (!i40e_valid_regs(hw->mac.type, reg_offset))
11699 ptr_data[reg_offset >> 2] = 0;
11701 ptr_data[reg_offset >> 2] =
11702 I40E_READ_REG(hw, reg_offset);
11709 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11711 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11713 /* Convert word count to byte count */
11714 return hw->nvm.sr_size << 1;
11717 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11718 struct rte_dev_eeprom_info *eeprom)
11720 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11721 uint16_t *data = eeprom->data;
11722 uint16_t offset, length, cnt_words;
11725 offset = eeprom->offset >> 1;
11726 length = eeprom->length >> 1;
11727 cnt_words = length;
11729 if (offset > hw->nvm.sr_size ||
11730 offset + length > hw->nvm.sr_size) {
11731 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11735 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11737 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11738 if (ret_code != I40E_SUCCESS || cnt_words != length) {
11739 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11746 static int i40e_get_module_info(struct rte_eth_dev *dev,
11747 struct rte_eth_dev_module_info *modinfo)
11749 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11750 uint32_t sff8472_comp = 0;
11751 uint32_t sff8472_swap = 0;
11752 uint32_t sff8636_rev = 0;
11753 i40e_status status;
11756 /* Check if firmware supports reading module EEPROM. */
11757 if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
11759 "Module EEPROM memory read not supported. "
11760 "Please update the NVM image.\n");
11764 status = i40e_update_link_info(hw);
11768 if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
11770 "Cannot read module EEPROM memory. "
11771 "No module connected.\n");
11775 type = hw->phy.link_info.module_type[0];
11778 case I40E_MODULE_TYPE_SFP:
11779 status = i40e_aq_get_phy_register(hw,
11780 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11781 I40E_I2C_EEPROM_DEV_ADDR, 1,
11782 I40E_MODULE_SFF_8472_COMP,
11783 &sff8472_comp, NULL);
11787 status = i40e_aq_get_phy_register(hw,
11788 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11789 I40E_I2C_EEPROM_DEV_ADDR, 1,
11790 I40E_MODULE_SFF_8472_SWAP,
11791 &sff8472_swap, NULL);
11795 /* Check if the module requires address swap to access
11796 * the other EEPROM memory page.
11798 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
11799 PMD_DRV_LOG(WARNING,
11800 "Module address swap to access "
11801 "page 0xA2 is not supported.\n");
11802 modinfo->type = RTE_ETH_MODULE_SFF_8079;
11803 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11804 } else if (sff8472_comp == 0x00) {
11805 /* Module is not SFF-8472 compliant */
11806 modinfo->type = RTE_ETH_MODULE_SFF_8079;
11807 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11809 modinfo->type = RTE_ETH_MODULE_SFF_8472;
11810 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
11813 case I40E_MODULE_TYPE_QSFP_PLUS:
11814 /* Read from memory page 0. */
11815 status = i40e_aq_get_phy_register(hw,
11816 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11818 I40E_MODULE_REVISION_ADDR,
11819 &sff8636_rev, NULL);
11822 /* Determine revision compliance byte */
11823 if (sff8636_rev > 0x02) {
11824 /* Module is SFF-8636 compliant */
11825 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11826 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11828 modinfo->type = RTE_ETH_MODULE_SFF_8436;
11829 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11832 case I40E_MODULE_TYPE_QSFP28:
11833 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11834 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11837 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
11843 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
11844 struct rte_dev_eeprom_info *info)
11846 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11847 bool is_sfp = false;
11848 i40e_status status;
11849 uint8_t *data = info->data;
11850 uint32_t value = 0;
11853 if (!info || !info->length || !data)
11856 if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
11859 for (i = 0; i < info->length; i++) {
11860 u32 offset = i + info->offset;
11861 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
11863 /* Check if we need to access the other memory page */
11865 if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
11866 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
11867 addr = I40E_I2C_EEPROM_DEV_ADDR2;
11870 while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
11871 /* Compute memory page number and offset. */
11872 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
11876 status = i40e_aq_get_phy_register(hw,
11877 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11878 addr, offset, 1, &value, NULL);
11881 data[i] = (uint8_t)value;
11886 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11887 struct ether_addr *mac_addr)
11889 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11890 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11891 struct i40e_vsi *vsi = pf->main_vsi;
11892 struct i40e_mac_filter_info mac_filter;
11893 struct i40e_mac_filter *f;
11896 if (!is_valid_assigned_ether_addr(mac_addr)) {
11897 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11901 TAILQ_FOREACH(f, &vsi->mac_list, next) {
11902 if (is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
11907 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11911 mac_filter = f->mac_info;
11912 ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11913 if (ret != I40E_SUCCESS) {
11914 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11917 memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11918 ret = i40e_vsi_add_mac(vsi, &mac_filter);
11919 if (ret != I40E_SUCCESS) {
11920 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11923 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11925 ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11926 mac_addr->addr_bytes, NULL);
11927 if (ret != I40E_SUCCESS) {
11928 PMD_DRV_LOG(ERR, "Failed to change mac");
11936 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
11938 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11939 struct rte_eth_dev_data *dev_data = pf->dev_data;
11940 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
11943 /* check if mtu is within the allowed range */
11944 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
11947 /* mtu setting is forbidden if port is start */
11948 if (dev_data->dev_started) {
11949 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
11950 dev_data->port_id);
11954 if (frame_size > ETHER_MAX_LEN)
11955 dev_data->dev_conf.rxmode.offloads |=
11956 DEV_RX_OFFLOAD_JUMBO_FRAME;
11958 dev_data->dev_conf.rxmode.offloads &=
11959 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
11961 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
11966 /* Restore ethertype filter */
11968 i40e_ethertype_filter_restore(struct i40e_pf *pf)
11970 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11971 struct i40e_ethertype_filter_list
11972 *ethertype_list = &pf->ethertype.ethertype_list;
11973 struct i40e_ethertype_filter *f;
11974 struct i40e_control_filter_stats stats;
11977 TAILQ_FOREACH(f, ethertype_list, rules) {
11979 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
11980 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
11981 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
11982 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
11983 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
11985 memset(&stats, 0, sizeof(stats));
11986 i40e_aq_add_rem_control_packet_filter(hw,
11987 f->input.mac_addr.addr_bytes,
11988 f->input.ether_type,
11989 flags, pf->main_vsi->seid,
11990 f->queue, 1, &stats, NULL);
11992 PMD_DRV_LOG(INFO, "Ethertype filter:"
11993 " mac_etype_used = %u, etype_used = %u,"
11994 " mac_etype_free = %u, etype_free = %u",
11995 stats.mac_etype_used, stats.etype_used,
11996 stats.mac_etype_free, stats.etype_free);
11999 /* Restore tunnel filter */
12001 i40e_tunnel_filter_restore(struct i40e_pf *pf)
12003 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12004 struct i40e_vsi *vsi;
12005 struct i40e_pf_vf *vf;
12006 struct i40e_tunnel_filter_list
12007 *tunnel_list = &pf->tunnel.tunnel_list;
12008 struct i40e_tunnel_filter *f;
12009 struct i40e_aqc_cloud_filters_element_bb cld_filter;
12010 bool big_buffer = 0;
12012 TAILQ_FOREACH(f, tunnel_list, rules) {
12014 vsi = pf->main_vsi;
12016 vf = &pf->vfs[f->vf_id];
12019 memset(&cld_filter, 0, sizeof(cld_filter));
12020 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
12021 (struct ether_addr *)&cld_filter.element.outer_mac);
12022 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
12023 (struct ether_addr *)&cld_filter.element.inner_mac);
12024 cld_filter.element.inner_vlan = f->input.inner_vlan;
12025 cld_filter.element.flags = f->input.flags;
12026 cld_filter.element.tenant_id = f->input.tenant_id;
12027 cld_filter.element.queue_number = f->queue;
12028 rte_memcpy(cld_filter.general_fields,
12029 f->input.general_fields,
12030 sizeof(f->input.general_fields));
12032 if (((f->input.flags &
12033 I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
12034 I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
12036 I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
12037 I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
12039 I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
12040 I40E_AQC_ADD_CLOUD_FILTER_0X10))
12044 i40e_aq_add_cloud_filters_bb(hw,
12045 vsi->seid, &cld_filter, 1);
12047 i40e_aq_add_cloud_filters(hw, vsi->seid,
12048 &cld_filter.element, 1);
12052 /* Restore rss filter */
12054 i40e_rss_filter_restore(struct i40e_pf *pf)
12056 struct i40e_rte_flow_rss_conf *conf =
12058 if (conf->conf.queue_num)
12059 i40e_config_rss_filter(pf, conf, TRUE);
12063 i40e_filter_restore(struct i40e_pf *pf)
12065 i40e_ethertype_filter_restore(pf);
12066 i40e_tunnel_filter_restore(pf);
12067 i40e_fdir_filter_restore(pf);
12068 i40e_rss_filter_restore(pf);
12072 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
12074 if (strcmp(dev->device->driver->name, drv->driver.name))
12081 is_i40e_supported(struct rte_eth_dev *dev)
12083 return is_device_supported(dev, &rte_i40e_pmd);
12086 struct i40e_customized_pctype*
12087 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
12091 for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
12092 if (pf->customized_pctype[i].index == index)
12093 return &pf->customized_pctype[i];
12099 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
12100 uint32_t pkg_size, uint32_t proto_num,
12101 struct rte_pmd_i40e_proto_info *proto,
12102 enum rte_pmd_i40e_package_op op)
12104 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12105 uint32_t pctype_num;
12106 struct rte_pmd_i40e_ptype_info *pctype;
12107 uint32_t buff_size;
12108 struct i40e_customized_pctype *new_pctype = NULL;
12110 uint8_t pctype_value;
12115 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12116 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12117 PMD_DRV_LOG(ERR, "Unsupported operation.");
12121 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12122 (uint8_t *)&pctype_num, sizeof(pctype_num),
12123 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
12125 PMD_DRV_LOG(ERR, "Failed to get pctype number");
12129 PMD_DRV_LOG(INFO, "No new pctype added");
12133 buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
12134 pctype = rte_zmalloc("new_pctype", buff_size, 0);
12136 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12139 /* get information about new pctype list */
12140 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12141 (uint8_t *)pctype, buff_size,
12142 RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
12144 PMD_DRV_LOG(ERR, "Failed to get pctype list");
12149 /* Update customized pctype. */
12150 for (i = 0; i < pctype_num; i++) {
12151 pctype_value = pctype[i].ptype_id;
12152 memset(name, 0, sizeof(name));
12153 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12154 proto_id = pctype[i].protocols[j];
12155 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12157 for (n = 0; n < proto_num; n++) {
12158 if (proto[n].proto_id != proto_id)
12160 strcat(name, proto[n].name);
12165 name[strlen(name) - 1] = '\0';
12166 if (!strcmp(name, "GTPC"))
12168 i40e_find_customized_pctype(pf,
12169 I40E_CUSTOMIZED_GTPC);
12170 else if (!strcmp(name, "GTPU_IPV4"))
12172 i40e_find_customized_pctype(pf,
12173 I40E_CUSTOMIZED_GTPU_IPV4);
12174 else if (!strcmp(name, "GTPU_IPV6"))
12176 i40e_find_customized_pctype(pf,
12177 I40E_CUSTOMIZED_GTPU_IPV6);
12178 else if (!strcmp(name, "GTPU"))
12180 i40e_find_customized_pctype(pf,
12181 I40E_CUSTOMIZED_GTPU);
12183 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12184 new_pctype->pctype = pctype_value;
12185 new_pctype->valid = true;
12187 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
12188 new_pctype->valid = false;
12198 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
12199 uint32_t pkg_size, uint32_t proto_num,
12200 struct rte_pmd_i40e_proto_info *proto,
12201 enum rte_pmd_i40e_package_op op)
12203 struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
12204 uint16_t port_id = dev->data->port_id;
12205 uint32_t ptype_num;
12206 struct rte_pmd_i40e_ptype_info *ptype;
12207 uint32_t buff_size;
12209 char name[RTE_PMD_I40E_DDP_NAME_SIZE];
12214 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12215 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12216 PMD_DRV_LOG(ERR, "Unsupported operation.");
12220 if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
12221 rte_pmd_i40e_ptype_mapping_reset(port_id);
12225 /* get information about new ptype num */
12226 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12227 (uint8_t *)&ptype_num, sizeof(ptype_num),
12228 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12230 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12234 PMD_DRV_LOG(INFO, "No new ptype added");
12238 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12239 ptype = rte_zmalloc("new_ptype", buff_size, 0);
12241 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12245 /* get information about new ptype list */
12246 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12247 (uint8_t *)ptype, buff_size,
12248 RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12250 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12255 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12256 ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12257 if (!ptype_mapping) {
12258 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12263 /* Update ptype mapping table. */
12264 for (i = 0; i < ptype_num; i++) {
12265 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12266 ptype_mapping[i].sw_ptype = 0;
12268 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12269 proto_id = ptype[i].protocols[j];
12270 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12272 for (n = 0; n < proto_num; n++) {
12273 if (proto[n].proto_id != proto_id)
12275 memset(name, 0, sizeof(name));
12276 strcpy(name, proto[n].name);
12277 if (!strncasecmp(name, "PPPOE", 5))
12278 ptype_mapping[i].sw_ptype |=
12279 RTE_PTYPE_L2_ETHER_PPPOE;
12280 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12282 ptype_mapping[i].sw_ptype |=
12283 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12284 ptype_mapping[i].sw_ptype |=
12286 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12288 ptype_mapping[i].sw_ptype |=
12289 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12290 ptype_mapping[i].sw_ptype |=
12291 RTE_PTYPE_INNER_L4_FRAG;
12292 } else if (!strncasecmp(name, "OIPV4", 5)) {
12293 ptype_mapping[i].sw_ptype |=
12294 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12296 } else if (!strncasecmp(name, "IPV4", 4) &&
12298 ptype_mapping[i].sw_ptype |=
12299 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12300 else if (!strncasecmp(name, "IPV4", 4) &&
12302 ptype_mapping[i].sw_ptype |=
12303 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12304 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12306 ptype_mapping[i].sw_ptype |=
12307 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12308 ptype_mapping[i].sw_ptype |=
12310 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12312 ptype_mapping[i].sw_ptype |=
12313 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12314 ptype_mapping[i].sw_ptype |=
12315 RTE_PTYPE_INNER_L4_FRAG;
12316 } else if (!strncasecmp(name, "OIPV6", 5)) {
12317 ptype_mapping[i].sw_ptype |=
12318 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12320 } else if (!strncasecmp(name, "IPV6", 4) &&
12322 ptype_mapping[i].sw_ptype |=
12323 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12324 else if (!strncasecmp(name, "IPV6", 4) &&
12326 ptype_mapping[i].sw_ptype |=
12327 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12328 else if (!strncasecmp(name, "UDP", 3) &&
12330 ptype_mapping[i].sw_ptype |=
12332 else if (!strncasecmp(name, "UDP", 3) &&
12334 ptype_mapping[i].sw_ptype |=
12335 RTE_PTYPE_INNER_L4_UDP;
12336 else if (!strncasecmp(name, "TCP", 3) &&
12338 ptype_mapping[i].sw_ptype |=
12340 else if (!strncasecmp(name, "TCP", 3) &&
12342 ptype_mapping[i].sw_ptype |=
12343 RTE_PTYPE_INNER_L4_TCP;
12344 else if (!strncasecmp(name, "SCTP", 4) &&
12346 ptype_mapping[i].sw_ptype |=
12348 else if (!strncasecmp(name, "SCTP", 4) &&
12350 ptype_mapping[i].sw_ptype |=
12351 RTE_PTYPE_INNER_L4_SCTP;
12352 else if ((!strncasecmp(name, "ICMP", 4) ||
12353 !strncasecmp(name, "ICMPV6", 6)) &&
12355 ptype_mapping[i].sw_ptype |=
12357 else if ((!strncasecmp(name, "ICMP", 4) ||
12358 !strncasecmp(name, "ICMPV6", 6)) &&
12360 ptype_mapping[i].sw_ptype |=
12361 RTE_PTYPE_INNER_L4_ICMP;
12362 else if (!strncasecmp(name, "GTPC", 4)) {
12363 ptype_mapping[i].sw_ptype |=
12364 RTE_PTYPE_TUNNEL_GTPC;
12366 } else if (!strncasecmp(name, "GTPU", 4)) {
12367 ptype_mapping[i].sw_ptype |=
12368 RTE_PTYPE_TUNNEL_GTPU;
12370 } else if (!strncasecmp(name, "GRENAT", 6)) {
12371 ptype_mapping[i].sw_ptype |=
12372 RTE_PTYPE_TUNNEL_GRENAT;
12374 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12375 !strncasecmp(name, "L2TPV2", 6)) {
12376 ptype_mapping[i].sw_ptype |=
12377 RTE_PTYPE_TUNNEL_L2TP;
12386 ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12389 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
12391 rte_free(ptype_mapping);
12397 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12398 uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12400 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12401 uint32_t proto_num;
12402 struct rte_pmd_i40e_proto_info *proto;
12403 uint32_t buff_size;
12407 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12408 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12409 PMD_DRV_LOG(ERR, "Unsupported operation.");
12413 /* get information about protocol number */
12414 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12415 (uint8_t *)&proto_num, sizeof(proto_num),
12416 RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12418 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12422 PMD_DRV_LOG(INFO, "No new protocol added");
12426 buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12427 proto = rte_zmalloc("new_proto", buff_size, 0);
12429 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12433 /* get information about protocol list */
12434 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12435 (uint8_t *)proto, buff_size,
12436 RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12438 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12443 /* Check if GTP is supported. */
12444 for (i = 0; i < proto_num; i++) {
12445 if (!strncmp(proto[i].name, "GTP", 3)) {
12446 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12447 pf->gtp_support = true;
12449 pf->gtp_support = false;
12454 /* Update customized pctype info */
12455 ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12456 proto_num, proto, op);
12458 PMD_DRV_LOG(INFO, "No pctype is updated.");
12460 /* Update customized ptype info */
12461 ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12462 proto_num, proto, op);
12464 PMD_DRV_LOG(INFO, "No ptype is updated.");
12469 /* Create a QinQ cloud filter
12471 * The Fortville NIC has limited resources for tunnel filters,
12472 * so we can only reuse existing filters.
12474 * In step 1 we define which Field Vector fields can be used for
12476 * As we do not have the inner tag defined as a field,
12477 * we have to define it first, by reusing one of L1 entries.
12479 * In step 2 we are replacing one of existing filter types with
12480 * a new one for QinQ.
12481 * As we reusing L1 and replacing L2, some of the default filter
12482 * types will disappear,which depends on L1 and L2 entries we reuse.
12484 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12486 * 1. Create L1 filter of outer vlan (12b) which will be in use
12487 * later when we define the cloud filter.
12488 * a. Valid_flags.replace_cloud = 0
12489 * b. Old_filter = 10 (Stag_Inner_Vlan)
12490 * c. New_filter = 0x10
12491 * d. TR bit = 0xff (optional, not used here)
12492 * e. Buffer – 2 entries:
12493 * i. Byte 0 = 8 (outer vlan FV index).
12495 * Byte 2-3 = 0x0fff
12496 * ii. Byte 0 = 37 (inner vlan FV index).
12498 * Byte 2-3 = 0x0fff
12501 * 2. Create cloud filter using two L1 filters entries: stag and
12502 * new filter(outer vlan+ inner vlan)
12503 * a. Valid_flags.replace_cloud = 1
12504 * b. Old_filter = 1 (instead of outer IP)
12505 * c. New_filter = 0x10
12506 * d. Buffer – 2 entries:
12507 * i. Byte 0 = 0x80 | 7 (valid | Stag).
12508 * Byte 1-3 = 0 (rsv)
12509 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12510 * Byte 9-11 = 0 (rsv)
12513 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12515 int ret = -ENOTSUP;
12516 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
12517 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
12518 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12519 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
12521 if (pf->support_multi_driver) {
12522 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12527 memset(&filter_replace, 0,
12528 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12529 memset(&filter_replace_buf, 0,
12530 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12532 /* create L1 filter */
12533 filter_replace.old_filter_type =
12534 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12535 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12536 filter_replace.tr_bit = 0;
12538 /* Prepare the buffer, 2 entries */
12539 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12540 filter_replace_buf.data[0] |=
12541 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12542 /* Field Vector 12b mask */
12543 filter_replace_buf.data[2] = 0xff;
12544 filter_replace_buf.data[3] = 0x0f;
12545 filter_replace_buf.data[4] =
12546 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12547 filter_replace_buf.data[4] |=
12548 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12549 /* Field Vector 12b mask */
12550 filter_replace_buf.data[6] = 0xff;
12551 filter_replace_buf.data[7] = 0x0f;
12552 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12553 &filter_replace_buf);
12554 if (ret != I40E_SUCCESS)
12557 if (filter_replace.old_filter_type !=
12558 filter_replace.new_filter_type)
12559 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
12560 " original: 0x%x, new: 0x%x",
12562 filter_replace.old_filter_type,
12563 filter_replace.new_filter_type);
12565 /* Apply the second L2 cloud filter */
12566 memset(&filter_replace, 0,
12567 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12568 memset(&filter_replace_buf, 0,
12569 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12571 /* create L2 filter, input for L2 filter will be L1 filter */
12572 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12573 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12574 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12576 /* Prepare the buffer, 2 entries */
12577 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12578 filter_replace_buf.data[0] |=
12579 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12580 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12581 filter_replace_buf.data[4] |=
12582 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12583 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12584 &filter_replace_buf);
12585 if (!ret && (filter_replace.old_filter_type !=
12586 filter_replace.new_filter_type))
12587 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
12588 " original: 0x%x, new: 0x%x",
12590 filter_replace.old_filter_type,
12591 filter_replace.new_filter_type);
12597 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
12598 const struct rte_flow_action_rss *in)
12600 if (in->key_len > RTE_DIM(out->key) ||
12601 in->queue_num > RTE_DIM(out->queue))
12603 if (!in->key && in->key_len)
12605 out->conf = (struct rte_flow_action_rss){
12607 .level = in->level,
12608 .types = in->types,
12609 .key_len = in->key_len,
12610 .queue_num = in->queue_num,
12611 .queue = memcpy(out->queue, in->queue,
12612 sizeof(*in->queue) * in->queue_num),
12615 out->conf.key = memcpy(out->key, in->key, in->key_len);
12620 i40e_action_rss_same(const struct rte_flow_action_rss *comp,
12621 const struct rte_flow_action_rss *with)
12623 return (comp->func == with->func &&
12624 comp->level == with->level &&
12625 comp->types == with->types &&
12626 comp->key_len == with->key_len &&
12627 comp->queue_num == with->queue_num &&
12628 !memcmp(comp->key, with->key, with->key_len) &&
12629 !memcmp(comp->queue, with->queue,
12630 sizeof(*with->queue) * with->queue_num));
12634 i40e_config_rss_filter(struct i40e_pf *pf,
12635 struct i40e_rte_flow_rss_conf *conf, bool add)
12637 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12638 uint32_t i, lut = 0;
12640 struct rte_eth_rss_conf rss_conf = {
12641 .rss_key = conf->conf.key_len ?
12642 (void *)(uintptr_t)conf->conf.key : NULL,
12643 .rss_key_len = conf->conf.key_len,
12644 .rss_hf = conf->conf.types,
12646 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
12649 if (i40e_action_rss_same(&rss_info->conf, &conf->conf)) {
12650 i40e_pf_disable_rss(pf);
12651 memset(rss_info, 0,
12652 sizeof(struct i40e_rte_flow_rss_conf));
12658 if (rss_info->conf.queue_num)
12661 /* If both VMDQ and RSS enabled, not all of PF queues are configured.
12662 * It's necessary to calculate the actual PF queues that are configured.
12664 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
12665 num = i40e_pf_calc_configured_queues_num(pf);
12667 num = pf->dev_data->nb_rx_queues;
12669 num = RTE_MIN(num, conf->conf.queue_num);
12670 PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
12674 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS");
12678 /* Fill in redirection table */
12679 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
12682 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
12683 hw->func_caps.rss_table_entry_width) - 1));
12685 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
12688 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
12689 i40e_pf_disable_rss(pf);
12692 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
12693 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
12694 /* Random default keys */
12695 static uint32_t rss_key_default[] = {0x6b793944,
12696 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
12697 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
12698 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
12700 rss_conf.rss_key = (uint8_t *)rss_key_default;
12701 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
12705 i40e_hw_rss_hash_set(pf, &rss_conf);
12707 if (i40e_rss_conf_init(rss_info, &conf->conf))
12713 RTE_INIT(i40e_init_log)
12715 i40e_logtype_init = rte_log_register("pmd.net.i40e.init");
12716 if (i40e_logtype_init >= 0)
12717 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
12718 i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver");
12719 if (i40e_logtype_driver >= 0)
12720 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
12723 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12724 ETH_I40E_FLOATING_VEB_ARG "=1"
12725 ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
12726 ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12727 ETH_I40E_SUPPORT_MULTI_DRIVER "=1"
12728 ETH_I40E_USE_LATEST_VEC "=0|1");