4 * Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
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14 * notice, this list of conditions and the following disclaimer in
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
44 #include <rte_string_fns.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memzone.h>
49 #include <rte_malloc.h>
50 #include <rte_memcpy.h>
51 #include <rte_alarm.h>
53 #include <rte_eth_ctrl.h>
55 #include "i40e_logs.h"
56 #include "base/i40e_prototype.h"
57 #include "base/i40e_adminq_cmd.h"
58 #include "base/i40e_type.h"
59 #include "base/i40e_register.h"
60 #include "base/i40e_dcb.h"
61 #include "i40e_ethdev.h"
62 #include "i40e_rxtx.h"
64 #include "i40e_regs.h"
66 #define I40E_CLEAR_PXE_WAIT_MS 200
68 /* Maximun number of capability elements */
69 #define I40E_MAX_CAP_ELE_NUM 128
71 /* Wait count and inteval */
72 #define I40E_CHK_Q_ENA_COUNT 1000
73 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
75 /* Maximun number of VSI */
76 #define I40E_MAX_NUM_VSIS (384UL)
78 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
80 /* Flow control default timer */
81 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
83 /* Flow control default high water */
84 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
86 /* Flow control default low water */
87 #define I40E_DEFAULT_LOW_WATER (0x1A40/1024)
89 /* Flow control enable fwd bit */
90 #define I40E_PRTMAC_FWD_CTRL 0x00000001
92 /* Receive Packet Buffer size */
93 #define I40E_RXPBSIZE (968 * 1024)
96 #define I40E_KILOSHIFT 10
98 /* Receive Average Packet Size in Byte*/
99 #define I40E_PACKET_AVERAGE_SIZE 128
101 /* Mask of PF interrupt causes */
102 #define I40E_PFINT_ICR0_ENA_MASK ( \
103 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
104 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
105 I40E_PFINT_ICR0_ENA_GRST_MASK | \
106 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
107 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
108 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
109 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
110 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
111 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
112 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
114 #define I40E_FLOW_TYPES ( \
115 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
116 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
117 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
118 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
119 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
120 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
121 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
122 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
123 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
124 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
125 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
127 /* Additional timesync values. */
128 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
129 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
130 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
131 #define I40E_PRTTSYN_TSYNENA 0x80000000
132 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
133 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
135 #define I40E_MAX_PERCENT 100
136 #define I40E_DEFAULT_DCB_APP_NUM 1
137 #define I40E_DEFAULT_DCB_APP_PRIO 3
139 #define I40E_INSET_NONE 0x00000000000000000ULL
142 #define I40E_INSET_DMAC 0x0000000000000001ULL
143 #define I40E_INSET_SMAC 0x0000000000000002ULL
144 #define I40E_INSET_VLAN_OUTER 0x0000000000000004ULL
145 #define I40E_INSET_VLAN_INNER 0x0000000000000008ULL
146 #define I40E_INSET_VLAN_TUNNEL 0x0000000000000010ULL
149 #define I40E_INSET_IPV4_SRC 0x0000000000000100ULL
150 #define I40E_INSET_IPV4_DST 0x0000000000000200ULL
151 #define I40E_INSET_IPV6_SRC 0x0000000000000400ULL
152 #define I40E_INSET_IPV6_DST 0x0000000000000800ULL
153 #define I40E_INSET_SRC_PORT 0x0000000000001000ULL
154 #define I40E_INSET_DST_PORT 0x0000000000002000ULL
155 #define I40E_INSET_SCTP_VT 0x0000000000004000ULL
157 /* bit 16 ~ bit 31 */
158 #define I40E_INSET_IPV4_TOS 0x0000000000010000ULL
159 #define I40E_INSET_IPV4_PROTO 0x0000000000020000ULL
160 #define I40E_INSET_IPV4_TTL 0x0000000000040000ULL
161 #define I40E_INSET_IPV6_TC 0x0000000000080000ULL
162 #define I40E_INSET_IPV6_FLOW 0x0000000000100000ULL
163 #define I40E_INSET_IPV6_NEXT_HDR 0x0000000000200000ULL
164 #define I40E_INSET_IPV6_HOP_LIMIT 0x0000000000400000ULL
165 #define I40E_INSET_TCP_FLAGS 0x0000000000800000ULL
167 /* bit 32 ~ bit 47, tunnel fields */
168 #define I40E_INSET_TUNNEL_IPV4_DST 0x0000000100000000ULL
169 #define I40E_INSET_TUNNEL_IPV6_DST 0x0000000200000000ULL
170 #define I40E_INSET_TUNNEL_DMAC 0x0000000400000000ULL
171 #define I40E_INSET_TUNNEL_SRC_PORT 0x0000000800000000ULL
172 #define I40E_INSET_TUNNEL_DST_PORT 0x0000001000000000ULL
173 #define I40E_INSET_TUNNEL_ID 0x0000002000000000ULL
175 /* bit 48 ~ bit 55 */
176 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
178 /* bit 56 ~ bit 63, Flex Payload */
179 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
180 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
181 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
182 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
183 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
184 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
185 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
186 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
187 #define I40E_INSET_FLEX_PAYLOAD \
188 (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
189 I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
190 I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
191 I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
194 * Below are values for writing un-exposed registers suggested
197 /* Destination MAC address */
198 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
199 /* Source MAC address */
200 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
201 /* Outer (S-Tag) VLAN tag in the outer L2 header */
202 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0200000000000000ULL
203 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
204 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
205 /* Single VLAN tag in the inner L2 header */
206 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
207 /* Source IPv4 address */
208 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
209 /* Destination IPv4 address */
210 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
211 /* IPv4 Type of Service (TOS) */
212 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
214 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
215 /* IPv4 Time to Live */
216 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
217 /* Source IPv6 address */
218 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
219 /* Destination IPv6 address */
220 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
221 /* IPv6 Traffic Class (TC) */
222 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
223 /* IPv6 Next Header */
224 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
226 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
228 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
229 /* Destination L4 port */
230 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
231 /* SCTP verification tag */
232 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
233 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
234 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
235 /* Source port of tunneling UDP */
236 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
237 /* Destination port of tunneling UDP */
238 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
239 /* UDP Tunneling ID, NVGRE/GRE key */
240 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
241 /* Last ether type */
242 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
243 /* Tunneling outer destination IPv4 address */
244 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
245 /* Tunneling outer destination IPv6 address */
246 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
247 /* 1st word of flex payload */
248 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
249 /* 2nd word of flex payload */
250 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
251 /* 3rd word of flex payload */
252 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
253 /* 4th word of flex payload */
254 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
255 /* 5th word of flex payload */
256 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
257 /* 6th word of flex payload */
258 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
259 /* 7th word of flex payload */
260 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
261 /* 8th word of flex payload */
262 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
263 /* all 8 words flex payload */
264 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
265 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
267 #define I40E_TRANSLATE_INSET 0
268 #define I40E_TRANSLATE_REG 1
270 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
271 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
272 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
273 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
274 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
275 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
277 #define I40E_GL_SWT_L2TAGCTRL(_i) (0x001C0A70 + ((_i) * 4))
278 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
279 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK \
280 I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
282 /* PCI offset for querying capability */
283 #define PCI_DEV_CAP_REG 0xA4
284 /* PCI offset for enabling/disabling Extended Tag */
285 #define PCI_DEV_CTRL_REG 0xA8
286 /* Bit mask of Extended Tag capability */
287 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
288 /* Bit shift of Extended Tag enable/disable */
289 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
290 /* Bit mask of Extended Tag enable/disable */
291 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
293 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
294 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
295 static int i40e_dev_configure(struct rte_eth_dev *dev);
296 static int i40e_dev_start(struct rte_eth_dev *dev);
297 static void i40e_dev_stop(struct rte_eth_dev *dev);
298 static void i40e_dev_close(struct rte_eth_dev *dev);
299 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
300 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
301 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
302 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
303 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
304 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
305 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
306 struct rte_eth_stats *stats);
307 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
308 struct rte_eth_xstat *xstats, unsigned n);
309 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
310 struct rte_eth_xstat_name *xstats_names,
312 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
313 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
317 static void i40e_dev_info_get(struct rte_eth_dev *dev,
318 struct rte_eth_dev_info *dev_info);
319 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
322 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
323 enum rte_vlan_type vlan_type,
325 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
326 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
329 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
330 static int i40e_dev_led_on(struct rte_eth_dev *dev);
331 static int i40e_dev_led_off(struct rte_eth_dev *dev);
332 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
333 struct rte_eth_fc_conf *fc_conf);
334 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
335 struct rte_eth_fc_conf *fc_conf);
336 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
337 struct rte_eth_pfc_conf *pfc_conf);
338 static void i40e_macaddr_add(struct rte_eth_dev *dev,
339 struct ether_addr *mac_addr,
342 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
343 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
344 struct rte_eth_rss_reta_entry64 *reta_conf,
346 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
347 struct rte_eth_rss_reta_entry64 *reta_conf,
350 static int i40e_get_cap(struct i40e_hw *hw);
351 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
352 static int i40e_pf_setup(struct i40e_pf *pf);
353 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
354 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
355 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
356 static int i40e_dcb_setup(struct rte_eth_dev *dev);
357 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
358 bool offset_loaded, uint64_t *offset, uint64_t *stat);
359 static void i40e_stat_update_48(struct i40e_hw *hw,
365 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
366 static void i40e_dev_interrupt_handler(
367 __rte_unused struct rte_intr_handle *handle, void *param);
368 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
369 uint32_t base, uint32_t num);
370 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
371 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
373 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
375 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
376 static int i40e_veb_release(struct i40e_veb *veb);
377 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
378 struct i40e_vsi *vsi);
379 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
380 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
381 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
382 struct i40e_macvlan_filter *mv_f,
384 struct ether_addr *addr);
385 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
386 struct i40e_macvlan_filter *mv_f,
389 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
390 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
391 struct rte_eth_rss_conf *rss_conf);
392 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
393 struct rte_eth_rss_conf *rss_conf);
394 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
395 struct rte_eth_udp_tunnel *udp_tunnel);
396 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
397 struct rte_eth_udp_tunnel *udp_tunnel);
398 static void i40e_filter_input_set_init(struct i40e_pf *pf);
399 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
400 struct rte_eth_ethertype_filter *filter,
402 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
403 enum rte_filter_op filter_op,
405 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
406 enum rte_filter_type filter_type,
407 enum rte_filter_op filter_op,
409 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
410 struct rte_eth_dcb_info *dcb_info);
411 static void i40e_configure_registers(struct i40e_hw *hw);
412 static void i40e_hw_init(struct rte_eth_dev *dev);
413 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
414 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
415 struct rte_eth_mirror_conf *mirror_conf,
416 uint8_t sw_id, uint8_t on);
417 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
419 static int i40e_timesync_enable(struct rte_eth_dev *dev);
420 static int i40e_timesync_disable(struct rte_eth_dev *dev);
421 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
422 struct timespec *timestamp,
424 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
425 struct timespec *timestamp);
426 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
428 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
430 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
431 struct timespec *timestamp);
432 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
433 const struct timespec *timestamp);
435 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
437 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
440 static int i40e_get_reg_length(struct rte_eth_dev *dev);
442 static int i40e_get_regs(struct rte_eth_dev *dev,
443 struct rte_dev_reg_info *regs);
445 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
447 static int i40e_get_eeprom(struct rte_eth_dev *dev,
448 struct rte_dev_eeprom_info *eeprom);
450 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
451 struct ether_addr *mac_addr);
453 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
455 static const struct rte_pci_id pci_id_i40e_map[] = {
456 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
457 #include "rte_pci_dev_ids.h"
458 { .vendor_id = 0, /* sentinel */ },
461 static const struct eth_dev_ops i40e_eth_dev_ops = {
462 .dev_configure = i40e_dev_configure,
463 .dev_start = i40e_dev_start,
464 .dev_stop = i40e_dev_stop,
465 .dev_close = i40e_dev_close,
466 .promiscuous_enable = i40e_dev_promiscuous_enable,
467 .promiscuous_disable = i40e_dev_promiscuous_disable,
468 .allmulticast_enable = i40e_dev_allmulticast_enable,
469 .allmulticast_disable = i40e_dev_allmulticast_disable,
470 .dev_set_link_up = i40e_dev_set_link_up,
471 .dev_set_link_down = i40e_dev_set_link_down,
472 .link_update = i40e_dev_link_update,
473 .stats_get = i40e_dev_stats_get,
474 .xstats_get = i40e_dev_xstats_get,
475 .xstats_get_names = i40e_dev_xstats_get_names,
476 .stats_reset = i40e_dev_stats_reset,
477 .xstats_reset = i40e_dev_stats_reset,
478 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
479 .dev_infos_get = i40e_dev_info_get,
480 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
481 .vlan_filter_set = i40e_vlan_filter_set,
482 .vlan_tpid_set = i40e_vlan_tpid_set,
483 .vlan_offload_set = i40e_vlan_offload_set,
484 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
485 .vlan_pvid_set = i40e_vlan_pvid_set,
486 .rx_queue_start = i40e_dev_rx_queue_start,
487 .rx_queue_stop = i40e_dev_rx_queue_stop,
488 .tx_queue_start = i40e_dev_tx_queue_start,
489 .tx_queue_stop = i40e_dev_tx_queue_stop,
490 .rx_queue_setup = i40e_dev_rx_queue_setup,
491 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
492 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
493 .rx_queue_release = i40e_dev_rx_queue_release,
494 .rx_queue_count = i40e_dev_rx_queue_count,
495 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
496 .tx_queue_setup = i40e_dev_tx_queue_setup,
497 .tx_queue_release = i40e_dev_tx_queue_release,
498 .dev_led_on = i40e_dev_led_on,
499 .dev_led_off = i40e_dev_led_off,
500 .flow_ctrl_get = i40e_flow_ctrl_get,
501 .flow_ctrl_set = i40e_flow_ctrl_set,
502 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
503 .mac_addr_add = i40e_macaddr_add,
504 .mac_addr_remove = i40e_macaddr_remove,
505 .reta_update = i40e_dev_rss_reta_update,
506 .reta_query = i40e_dev_rss_reta_query,
507 .rss_hash_update = i40e_dev_rss_hash_update,
508 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
509 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
510 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
511 .filter_ctrl = i40e_dev_filter_ctrl,
512 .rxq_info_get = i40e_rxq_info_get,
513 .txq_info_get = i40e_txq_info_get,
514 .mirror_rule_set = i40e_mirror_rule_set,
515 .mirror_rule_reset = i40e_mirror_rule_reset,
516 .timesync_enable = i40e_timesync_enable,
517 .timesync_disable = i40e_timesync_disable,
518 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
519 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
520 .get_dcb_info = i40e_dev_get_dcb_info,
521 .timesync_adjust_time = i40e_timesync_adjust_time,
522 .timesync_read_time = i40e_timesync_read_time,
523 .timesync_write_time = i40e_timesync_write_time,
524 .get_reg_length = i40e_get_reg_length,
525 .get_reg = i40e_get_regs,
526 .get_eeprom_length = i40e_get_eeprom_length,
527 .get_eeprom = i40e_get_eeprom,
528 .mac_addr_set = i40e_set_default_mac_addr,
529 .mtu_set = i40e_dev_mtu_set,
532 /* store statistics names and its offset in stats structure */
533 struct rte_i40e_xstats_name_off {
534 char name[RTE_ETH_XSTATS_NAME_SIZE];
538 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
539 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
540 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
541 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
542 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
543 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
544 rx_unknown_protocol)},
545 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
546 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
547 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
548 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
551 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
552 sizeof(rte_i40e_stats_strings[0]))
554 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
555 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
556 tx_dropped_link_down)},
557 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
558 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
560 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
561 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
563 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
565 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
567 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
568 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
569 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
570 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
571 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
572 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
574 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
576 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
578 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
580 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
582 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
584 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
586 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
588 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
589 mac_short_packet_dropped)},
590 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
592 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
593 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
594 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
596 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
598 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
600 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
602 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
604 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
606 {"rx_flow_director_atr_match_packets",
607 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
608 {"rx_flow_director_sb_match_packets",
609 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
610 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
612 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
614 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
616 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
620 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
621 sizeof(rte_i40e_hw_port_strings[0]))
623 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
624 {"xon_packets", offsetof(struct i40e_hw_port_stats,
626 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
630 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
631 sizeof(rte_i40e_rxq_prio_strings[0]))
633 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
634 {"xon_packets", offsetof(struct i40e_hw_port_stats,
636 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
638 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
639 priority_xon_2_xoff)},
642 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
643 sizeof(rte_i40e_txq_prio_strings[0]))
645 static struct eth_driver rte_i40e_pmd = {
647 .name = "rte_i40e_pmd",
648 .id_table = pci_id_i40e_map,
649 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
650 RTE_PCI_DRV_DETACHABLE,
652 .eth_dev_init = eth_i40e_dev_init,
653 .eth_dev_uninit = eth_i40e_dev_uninit,
654 .dev_private_size = sizeof(struct i40e_adapter),
658 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
659 struct rte_eth_link *link)
661 struct rte_eth_link *dst = link;
662 struct rte_eth_link *src = &(dev->data->dev_link);
664 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
665 *(uint64_t *)src) == 0)
672 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
673 struct rte_eth_link *link)
675 struct rte_eth_link *dst = &(dev->data->dev_link);
676 struct rte_eth_link *src = link;
678 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
679 *(uint64_t *)src) == 0)
686 * Driver initialization routine.
687 * Invoked once at EAL init time.
688 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
691 rte_i40e_pmd_init(const char *name __rte_unused,
692 const char *params __rte_unused)
694 PMD_INIT_FUNC_TRACE();
695 rte_eth_driver_register(&rte_i40e_pmd);
700 static struct rte_driver rte_i40e_driver = {
702 .init = rte_i40e_pmd_init,
705 PMD_REGISTER_DRIVER(rte_i40e_driver);
708 * Initialize registers for flexible payload, which should be set by NVM.
709 * This should be removed from code once it is fixed in NVM.
711 #ifndef I40E_GLQF_ORT
712 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
714 #ifndef I40E_GLQF_PIT
715 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
718 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
720 I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
721 I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
722 I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
723 I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
724 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
725 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
726 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
727 I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
728 I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
729 I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
731 /* GLQF_PIT Registers */
732 I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
733 I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
736 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
739 * Add a ethertype filter to drop all flow control frames transmitted
743 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
745 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
746 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
747 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
748 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
751 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
752 I40E_FLOW_CONTROL_ETHERTYPE, flags,
753 pf->main_vsi_seid, 0,
756 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
757 " frames from VSIs.");
761 eth_i40e_dev_init(struct rte_eth_dev *dev)
763 struct rte_pci_device *pci_dev;
764 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
765 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
766 struct i40e_vsi *vsi;
771 PMD_INIT_FUNC_TRACE();
773 dev->dev_ops = &i40e_eth_dev_ops;
774 dev->rx_pkt_burst = i40e_recv_pkts;
775 dev->tx_pkt_burst = i40e_xmit_pkts;
777 /* for secondary processes, we don't initialise any further as primary
778 * has already done this work. Only check we don't need a different
780 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
781 i40e_set_rx_function(dev);
782 i40e_set_tx_function(dev);
785 pci_dev = dev->pci_dev;
787 rte_eth_copy_pci_info(dev, pci_dev);
789 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
790 pf->adapter->eth_dev = dev;
791 pf->dev_data = dev->data;
793 hw->back = I40E_PF_TO_ADAPTER(pf);
794 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
796 PMD_INIT_LOG(ERR, "Hardware is not available, "
797 "as address is NULL");
801 hw->vendor_id = pci_dev->id.vendor_id;
802 hw->device_id = pci_dev->id.device_id;
803 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
804 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
805 hw->bus.device = pci_dev->addr.devid;
806 hw->bus.func = pci_dev->addr.function;
807 hw->adapter_stopped = 0;
809 /* Make sure all is clean before doing PF reset */
812 /* Initialize the hardware */
815 /* Reset here to make sure all is clean for each PF */
816 ret = i40e_pf_reset(hw);
818 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
822 /* Initialize the shared code (base driver) */
823 ret = i40e_init_shared_code(hw);
825 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
830 * To work around the NVM issue,initialize registers
831 * for flexible payload by software.
832 * It should be removed once issues are fixed in NVM.
834 i40e_flex_payload_reg_init(hw);
836 /* Initialize the input set for filters (hash and fd) to default value */
837 i40e_filter_input_set_init(pf);
839 /* Initialize the parameters for adminq */
840 i40e_init_adminq_parameter(hw);
841 ret = i40e_init_adminq(hw);
842 if (ret != I40E_SUCCESS) {
843 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
846 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
847 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
848 hw->aq.api_maj_ver, hw->aq.api_min_ver,
849 ((hw->nvm.version >> 12) & 0xf),
850 ((hw->nvm.version >> 4) & 0xff),
851 (hw->nvm.version & 0xf), hw->nvm.eetrack);
854 i40e_clear_pxe_mode(hw);
857 * On X710, performance number is far from the expectation on recent
858 * firmware versions. The fix for this issue may not be integrated in
859 * the following firmware version. So the workaround in software driver
860 * is needed. It needs to modify the initial values of 3 internal only
861 * registers. Note that the workaround can be removed when it is fixed
862 * in firmware in the future.
864 i40e_configure_registers(hw);
866 /* Get hw capabilities */
867 ret = i40e_get_cap(hw);
868 if (ret != I40E_SUCCESS) {
869 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
870 goto err_get_capabilities;
873 /* Initialize parameters for PF */
874 ret = i40e_pf_parameter_init(dev);
876 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
877 goto err_parameter_init;
880 /* Initialize the queue management */
881 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
883 PMD_INIT_LOG(ERR, "Failed to init queue pool");
884 goto err_qp_pool_init;
886 ret = i40e_res_pool_init(&pf->msix_pool, 1,
887 hw->func_caps.num_msix_vectors - 1);
889 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
890 goto err_msix_pool_init;
893 /* Initialize lan hmc */
894 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
895 hw->func_caps.num_rx_qp, 0, 0);
896 if (ret != I40E_SUCCESS) {
897 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
898 goto err_init_lan_hmc;
901 /* Configure lan hmc */
902 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
903 if (ret != I40E_SUCCESS) {
904 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
905 goto err_configure_lan_hmc;
908 /* Get and check the mac address */
909 i40e_get_mac_addr(hw, hw->mac.addr);
910 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
911 PMD_INIT_LOG(ERR, "mac address is not valid");
913 goto err_get_mac_addr;
915 /* Copy the permanent MAC address */
916 ether_addr_copy((struct ether_addr *) hw->mac.addr,
917 (struct ether_addr *) hw->mac.perm_addr);
919 /* Disable flow control */
920 hw->fc.requested_mode = I40E_FC_NONE;
921 i40e_set_fc(hw, &aq_fail, TRUE);
923 /* Set the global registers with default ether type value */
924 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
925 if (ret != I40E_SUCCESS) {
926 PMD_INIT_LOG(ERR, "Failed to set the default outer "
928 goto err_setup_pf_switch;
930 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER, ETHER_TYPE_VLAN);
931 if (ret != I40E_SUCCESS) {
932 PMD_INIT_LOG(ERR, "Failed to set the default outer "
934 goto err_setup_pf_switch;
937 /* PF setup, which includes VSI setup */
938 ret = i40e_pf_setup(pf);
940 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
941 goto err_setup_pf_switch;
944 /* reset all stats of the device, including pf and main vsi */
945 i40e_dev_stats_reset(dev);
949 /* Disable double vlan by default */
950 i40e_vsi_config_double_vlan(vsi, FALSE);
952 if (!vsi->max_macaddrs)
953 len = ETHER_ADDR_LEN;
955 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
957 /* Should be after VSI initialized */
958 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
959 if (!dev->data->mac_addrs) {
960 PMD_INIT_LOG(ERR, "Failed to allocated memory "
961 "for storing mac address");
964 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
965 &dev->data->mac_addrs[0]);
967 /* initialize pf host driver to setup SRIOV resource if applicable */
968 i40e_pf_host_init(dev);
970 /* register callback func to eal lib */
971 rte_intr_callback_register(&(pci_dev->intr_handle),
972 i40e_dev_interrupt_handler, (void *)dev);
974 /* configure and enable device interrupt */
975 i40e_pf_config_irq0(hw, TRUE);
976 i40e_pf_enable_irq0(hw);
978 /* enable uio intr after callback register */
979 rte_intr_enable(&(pci_dev->intr_handle));
981 * Add an ethertype filter to drop all flow control frames transmitted
982 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
985 i40e_add_tx_flow_control_drop_filter(pf);
987 /* Set the max frame size to 0x2600 by default,
988 * in case other drivers changed the default value.
990 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
992 /* initialize mirror rule list */
993 TAILQ_INIT(&pf->mirror_list);
995 /* Init dcb to sw mode by default */
996 ret = i40e_dcb_init_configure(dev, TRUE);
997 if (ret != I40E_SUCCESS) {
998 PMD_INIT_LOG(INFO, "Failed to init dcb.");
999 pf->flags &= ~I40E_FLAG_DCB;
1005 i40e_vsi_release(pf->main_vsi);
1006 err_setup_pf_switch:
1008 err_configure_lan_hmc:
1009 (void)i40e_shutdown_lan_hmc(hw);
1011 i40e_res_pool_destroy(&pf->msix_pool);
1013 i40e_res_pool_destroy(&pf->qp_pool);
1016 err_get_capabilities:
1017 (void)i40e_shutdown_adminq(hw);
1023 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1025 struct rte_pci_device *pci_dev;
1027 struct i40e_filter_control_settings settings;
1029 uint8_t aq_fail = 0;
1031 PMD_INIT_FUNC_TRACE();
1033 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1036 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1037 pci_dev = dev->pci_dev;
1039 if (hw->adapter_stopped == 0)
1040 i40e_dev_close(dev);
1042 dev->dev_ops = NULL;
1043 dev->rx_pkt_burst = NULL;
1044 dev->tx_pkt_burst = NULL;
1047 ret = i40e_aq_stop_lldp(hw, true, NULL);
1048 if (ret != I40E_SUCCESS) /* Its failure can be ignored */
1049 PMD_INIT_LOG(INFO, "Failed to stop lldp");
1051 /* Clear PXE mode */
1052 i40e_clear_pxe_mode(hw);
1054 /* Unconfigure filter control */
1055 memset(&settings, 0, sizeof(settings));
1056 ret = i40e_set_filter_control(hw, &settings);
1058 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1061 /* Disable flow control */
1062 hw->fc.requested_mode = I40E_FC_NONE;
1063 i40e_set_fc(hw, &aq_fail, TRUE);
1065 /* uninitialize pf host driver */
1066 i40e_pf_host_uninit(dev);
1068 rte_free(dev->data->mac_addrs);
1069 dev->data->mac_addrs = NULL;
1071 /* disable uio intr before callback unregister */
1072 rte_intr_disable(&(pci_dev->intr_handle));
1074 /* register callback func to eal lib */
1075 rte_intr_callback_unregister(&(pci_dev->intr_handle),
1076 i40e_dev_interrupt_handler, (void *)dev);
1082 i40e_dev_configure(struct rte_eth_dev *dev)
1084 struct i40e_adapter *ad =
1085 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1086 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1087 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1090 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1091 * bulk allocation or vector Rx preconditions we will reset it.
1093 ad->rx_bulk_alloc_allowed = true;
1094 ad->rx_vec_allowed = true;
1095 ad->tx_simple_allowed = true;
1096 ad->tx_vec_allowed = true;
1098 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1099 ret = i40e_fdir_setup(pf);
1100 if (ret != I40E_SUCCESS) {
1101 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1104 ret = i40e_fdir_configure(dev);
1106 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1110 i40e_fdir_teardown(pf);
1112 ret = i40e_dev_init_vlan(dev);
1117 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1118 * RSS setting have different requirements.
1119 * General PMD driver call sequence are NIC init, configure,
1120 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1121 * will try to lookup the VSI that specific queue belongs to if VMDQ
1122 * applicable. So, VMDQ setting has to be done before
1123 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1124 * For RSS setting, it will try to calculate actual configured RX queue
1125 * number, which will be available after rx_queue_setup(). dev_start()
1126 * function is good to place RSS setup.
1128 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1129 ret = i40e_vmdq_setup(dev);
1134 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1135 ret = i40e_dcb_setup(dev);
1137 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1145 /* need to release vmdq resource if exists */
1146 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1147 i40e_vsi_release(pf->vmdq[i].vsi);
1148 pf->vmdq[i].vsi = NULL;
1153 /* need to release fdir resource if exists */
1154 i40e_fdir_teardown(pf);
1159 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1161 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1162 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1163 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1164 uint16_t msix_vect = vsi->msix_intr;
1167 for (i = 0; i < vsi->nb_qps; i++) {
1168 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1169 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1173 if (vsi->type != I40E_VSI_SRIOV) {
1174 if (!rte_intr_allow_others(intr_handle)) {
1175 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1176 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1178 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1181 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1182 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1184 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1189 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1190 vsi->user_param + (msix_vect - 1);
1192 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1193 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1195 I40E_WRITE_FLUSH(hw);
1199 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1200 int base_queue, int nb_queue)
1204 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1206 /* Bind all RX queues to allocated MSIX interrupt */
1207 for (i = 0; i < nb_queue; i++) {
1208 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1209 I40E_QINT_RQCTL_ITR_INDX_MASK |
1210 ((base_queue + i + 1) <<
1211 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1212 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1213 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1215 if (i == nb_queue - 1)
1216 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1217 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1220 /* Write first RX queue to Link list register as the head element */
1221 if (vsi->type != I40E_VSI_SRIOV) {
1223 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1225 if (msix_vect == I40E_MISC_VEC_ID) {
1226 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1228 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1230 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1232 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1235 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1237 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1239 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1241 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1248 if (msix_vect == I40E_MISC_VEC_ID) {
1250 I40E_VPINT_LNKLST0(vsi->user_param),
1252 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1254 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1256 /* num_msix_vectors_vf needs to minus irq0 */
1257 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1258 vsi->user_param + (msix_vect - 1);
1260 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1262 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1264 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1268 I40E_WRITE_FLUSH(hw);
1272 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1274 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1275 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1276 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1277 uint16_t msix_vect = vsi->msix_intr;
1278 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1279 uint16_t queue_idx = 0;
1284 for (i = 0; i < vsi->nb_qps; i++) {
1285 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1286 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1289 /* INTENA flag is not auto-cleared for interrupt */
1290 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1291 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1292 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1293 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1294 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1296 /* VF bind interrupt */
1297 if (vsi->type == I40E_VSI_SRIOV) {
1298 __vsi_queues_bind_intr(vsi, msix_vect,
1299 vsi->base_queue, vsi->nb_qps);
1303 /* PF & VMDq bind interrupt */
1304 if (rte_intr_dp_is_en(intr_handle)) {
1305 if (vsi->type == I40E_VSI_MAIN) {
1308 } else if (vsi->type == I40E_VSI_VMDQ2) {
1309 struct i40e_vsi *main_vsi =
1310 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1311 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1316 for (i = 0; i < vsi->nb_used_qps; i++) {
1318 if (!rte_intr_allow_others(intr_handle))
1319 /* allow to share MISC_VEC_ID */
1320 msix_vect = I40E_MISC_VEC_ID;
1322 /* no enough msix_vect, map all to one */
1323 __vsi_queues_bind_intr(vsi, msix_vect,
1324 vsi->base_queue + i,
1325 vsi->nb_used_qps - i);
1326 for (; !!record && i < vsi->nb_used_qps; i++)
1327 intr_handle->intr_vec[queue_idx + i] =
1331 /* 1:1 queue/msix_vect mapping */
1332 __vsi_queues_bind_intr(vsi, msix_vect,
1333 vsi->base_queue + i, 1);
1335 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1343 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1345 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1346 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1347 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1348 uint16_t interval = i40e_calc_itr_interval(\
1349 RTE_LIBRTE_I40E_ITR_INTERVAL);
1350 uint16_t msix_intr, i;
1352 if (rte_intr_allow_others(intr_handle))
1353 for (i = 0; i < vsi->nb_msix; i++) {
1354 msix_intr = vsi->msix_intr + i;
1355 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1356 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1357 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1358 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1360 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1363 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1364 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1365 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1366 (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1368 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1370 I40E_WRITE_FLUSH(hw);
1374 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1376 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1377 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1378 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1379 uint16_t msix_intr, i;
1381 if (rte_intr_allow_others(intr_handle))
1382 for (i = 0; i < vsi->nb_msix; i++) {
1383 msix_intr = vsi->msix_intr + i;
1384 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1388 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1390 I40E_WRITE_FLUSH(hw);
1393 static inline uint8_t
1394 i40e_parse_link_speeds(uint16_t link_speeds)
1396 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1398 if (link_speeds & ETH_LINK_SPEED_40G)
1399 link_speed |= I40E_LINK_SPEED_40GB;
1400 if (link_speeds & ETH_LINK_SPEED_20G)
1401 link_speed |= I40E_LINK_SPEED_20GB;
1402 if (link_speeds & ETH_LINK_SPEED_10G)
1403 link_speed |= I40E_LINK_SPEED_10GB;
1404 if (link_speeds & ETH_LINK_SPEED_1G)
1405 link_speed |= I40E_LINK_SPEED_1GB;
1406 if (link_speeds & ETH_LINK_SPEED_100M)
1407 link_speed |= I40E_LINK_SPEED_100MB;
1413 i40e_phy_conf_link(struct i40e_hw *hw,
1415 uint8_t force_speed)
1417 enum i40e_status_code status;
1418 struct i40e_aq_get_phy_abilities_resp phy_ab;
1419 struct i40e_aq_set_phy_config phy_conf;
1420 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1421 I40E_AQ_PHY_FLAG_PAUSE_RX |
1422 I40E_AQ_PHY_FLAG_PAUSE_RX |
1423 I40E_AQ_PHY_FLAG_LOW_POWER;
1424 const uint8_t advt = I40E_LINK_SPEED_40GB |
1425 I40E_LINK_SPEED_10GB |
1426 I40E_LINK_SPEED_1GB |
1427 I40E_LINK_SPEED_100MB;
1431 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1436 memset(&phy_conf, 0, sizeof(phy_conf));
1438 /* bits 0-2 use the values from get_phy_abilities_resp */
1440 abilities |= phy_ab.abilities & mask;
1442 /* update ablities and speed */
1443 if (abilities & I40E_AQ_PHY_AN_ENABLED)
1444 phy_conf.link_speed = advt;
1446 phy_conf.link_speed = force_speed;
1448 phy_conf.abilities = abilities;
1450 /* use get_phy_abilities_resp value for the rest */
1451 phy_conf.phy_type = phy_ab.phy_type;
1452 phy_conf.eee_capability = phy_ab.eee_capability;
1453 phy_conf.eeer = phy_ab.eeer_val;
1454 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1456 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1457 phy_ab.abilities, phy_ab.link_speed);
1458 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
1459 phy_conf.abilities, phy_conf.link_speed);
1461 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1465 return I40E_SUCCESS;
1469 i40e_apply_link_speed(struct rte_eth_dev *dev)
1472 uint8_t abilities = 0;
1473 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1474 struct rte_eth_conf *conf = &dev->data->dev_conf;
1476 speed = i40e_parse_link_speeds(conf->link_speeds);
1477 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1478 if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1479 abilities |= I40E_AQ_PHY_AN_ENABLED;
1480 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1482 /* Skip changing speed on 40G interfaces, FW does not support */
1483 if (i40e_is_40G_device(hw->device_id)) {
1484 speed = I40E_LINK_SPEED_UNKNOWN;
1485 abilities |= I40E_AQ_PHY_AN_ENABLED;
1488 return i40e_phy_conf_link(hw, abilities, speed);
1492 i40e_dev_start(struct rte_eth_dev *dev)
1494 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1495 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1496 struct i40e_vsi *main_vsi = pf->main_vsi;
1498 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1499 uint32_t intr_vector = 0;
1501 hw->adapter_stopped = 0;
1503 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1504 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1505 dev->data->port_id);
1509 rte_intr_disable(intr_handle);
1511 if ((rte_intr_cap_multiple(intr_handle) ||
1512 !RTE_ETH_DEV_SRIOV(dev).active) &&
1513 dev->data->dev_conf.intr_conf.rxq != 0) {
1514 intr_vector = dev->data->nb_rx_queues;
1515 if (rte_intr_efd_enable(intr_handle, intr_vector))
1519 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1520 intr_handle->intr_vec =
1521 rte_zmalloc("intr_vec",
1522 dev->data->nb_rx_queues * sizeof(int),
1524 if (!intr_handle->intr_vec) {
1525 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1526 " intr_vec\n", dev->data->nb_rx_queues);
1531 /* Initialize VSI */
1532 ret = i40e_dev_rxtx_init(pf);
1533 if (ret != I40E_SUCCESS) {
1534 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1538 /* Map queues with MSIX interrupt */
1539 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1540 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1541 i40e_vsi_queues_bind_intr(main_vsi);
1542 i40e_vsi_enable_queues_intr(main_vsi);
1544 /* Map VMDQ VSI queues with MSIX interrupt */
1545 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1546 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1547 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1548 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1551 /* enable FDIR MSIX interrupt */
1552 if (pf->fdir.fdir_vsi) {
1553 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1554 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1557 /* Enable all queues which have been configured */
1558 ret = i40e_dev_switch_queues(pf, TRUE);
1559 if (ret != I40E_SUCCESS) {
1560 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1564 /* Enable receiving broadcast packets */
1565 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1566 if (ret != I40E_SUCCESS)
1567 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1569 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1570 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1572 if (ret != I40E_SUCCESS)
1573 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1576 /* Apply link configure */
1577 if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1578 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1579 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_40G)) {
1580 PMD_DRV_LOG(ERR, "Invalid link setting");
1583 ret = i40e_apply_link_speed(dev);
1584 if (I40E_SUCCESS != ret) {
1585 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1589 if (!rte_intr_allow_others(intr_handle)) {
1590 rte_intr_callback_unregister(intr_handle,
1591 i40e_dev_interrupt_handler,
1593 /* configure and enable device interrupt */
1594 i40e_pf_config_irq0(hw, FALSE);
1595 i40e_pf_enable_irq0(hw);
1597 if (dev->data->dev_conf.intr_conf.lsc != 0)
1598 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1599 " no intr multiplex\n");
1602 /* enable uio intr after callback register */
1603 rte_intr_enable(intr_handle);
1605 return I40E_SUCCESS;
1608 i40e_dev_switch_queues(pf, FALSE);
1609 i40e_dev_clear_queues(dev);
1615 i40e_dev_stop(struct rte_eth_dev *dev)
1617 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1618 struct i40e_vsi *main_vsi = pf->main_vsi;
1619 struct i40e_mirror_rule *p_mirror;
1620 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1623 /* Disable all queues */
1624 i40e_dev_switch_queues(pf, FALSE);
1626 /* un-map queues with interrupt registers */
1627 i40e_vsi_disable_queues_intr(main_vsi);
1628 i40e_vsi_queues_unbind_intr(main_vsi);
1630 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1631 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1632 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1635 if (pf->fdir.fdir_vsi) {
1636 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1637 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1639 /* Clear all queues and release memory */
1640 i40e_dev_clear_queues(dev);
1643 i40e_dev_set_link_down(dev);
1645 /* Remove all mirror rules */
1646 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1647 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1650 pf->nb_mirror_rule = 0;
1652 if (!rte_intr_allow_others(intr_handle))
1653 /* resume to the default handler */
1654 rte_intr_callback_register(intr_handle,
1655 i40e_dev_interrupt_handler,
1658 /* Clean datapath event and queue/vec mapping */
1659 rte_intr_efd_disable(intr_handle);
1660 if (intr_handle->intr_vec) {
1661 rte_free(intr_handle->intr_vec);
1662 intr_handle->intr_vec = NULL;
1667 i40e_dev_close(struct rte_eth_dev *dev)
1669 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1670 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1674 PMD_INIT_FUNC_TRACE();
1677 hw->adapter_stopped = 1;
1678 i40e_dev_free_queues(dev);
1680 /* Disable interrupt */
1681 i40e_pf_disable_irq0(hw);
1682 rte_intr_disable(&(dev->pci_dev->intr_handle));
1684 /* shutdown and destroy the HMC */
1685 i40e_shutdown_lan_hmc(hw);
1687 /* release all the existing VSIs and VEBs */
1688 i40e_fdir_teardown(pf);
1689 i40e_vsi_release(pf->main_vsi);
1691 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1692 i40e_vsi_release(pf->vmdq[i].vsi);
1693 pf->vmdq[i].vsi = NULL;
1699 /* shutdown the adminq */
1700 i40e_aq_queue_shutdown(hw, true);
1701 i40e_shutdown_adminq(hw);
1703 i40e_res_pool_destroy(&pf->qp_pool);
1704 i40e_res_pool_destroy(&pf->msix_pool);
1706 /* force a PF reset to clean anything leftover */
1707 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1708 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1709 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1710 I40E_WRITE_FLUSH(hw);
1714 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1716 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1717 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1718 struct i40e_vsi *vsi = pf->main_vsi;
1721 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1723 if (status != I40E_SUCCESS)
1724 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1726 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1728 if (status != I40E_SUCCESS)
1729 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1734 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1736 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1737 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1738 struct i40e_vsi *vsi = pf->main_vsi;
1741 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1743 if (status != I40E_SUCCESS)
1744 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1746 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1748 if (status != I40E_SUCCESS)
1749 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1753 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1755 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1756 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1757 struct i40e_vsi *vsi = pf->main_vsi;
1760 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1761 if (ret != I40E_SUCCESS)
1762 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1766 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1768 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1769 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1770 struct i40e_vsi *vsi = pf->main_vsi;
1773 if (dev->data->promiscuous == 1)
1774 return; /* must remain in all_multicast mode */
1776 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1777 vsi->seid, FALSE, NULL);
1778 if (ret != I40E_SUCCESS)
1779 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1783 * Set device link up.
1786 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1788 /* re-apply link speed setting */
1789 return i40e_apply_link_speed(dev);
1793 * Set device link down.
1796 i40e_dev_set_link_down(struct rte_eth_dev *dev)
1798 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1799 uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1800 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1802 return i40e_phy_conf_link(hw, abilities, speed);
1806 i40e_dev_link_update(struct rte_eth_dev *dev,
1807 int wait_to_complete)
1809 #define CHECK_INTERVAL 100 /* 100ms */
1810 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
1811 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1812 struct i40e_link_status link_status;
1813 struct rte_eth_link link, old;
1815 unsigned rep_cnt = MAX_REPEAT_TIME;
1817 memset(&link, 0, sizeof(link));
1818 memset(&old, 0, sizeof(old));
1819 memset(&link_status, 0, sizeof(link_status));
1820 rte_i40e_dev_atomic_read_link_status(dev, &old);
1823 /* Get link status information from hardware */
1824 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1825 if (status != I40E_SUCCESS) {
1826 link.link_speed = ETH_SPEED_NUM_100M;
1827 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1828 PMD_DRV_LOG(ERR, "Failed to get link info");
1832 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1833 if (!wait_to_complete)
1836 rte_delay_ms(CHECK_INTERVAL);
1837 } while (!link.link_status && rep_cnt--);
1839 if (!link.link_status)
1842 /* i40e uses full duplex only */
1843 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1845 /* Parse the link status */
1846 switch (link_status.link_speed) {
1847 case I40E_LINK_SPEED_100MB:
1848 link.link_speed = ETH_SPEED_NUM_100M;
1850 case I40E_LINK_SPEED_1GB:
1851 link.link_speed = ETH_SPEED_NUM_1G;
1853 case I40E_LINK_SPEED_10GB:
1854 link.link_speed = ETH_SPEED_NUM_10G;
1856 case I40E_LINK_SPEED_20GB:
1857 link.link_speed = ETH_SPEED_NUM_20G;
1859 case I40E_LINK_SPEED_40GB:
1860 link.link_speed = ETH_SPEED_NUM_40G;
1863 link.link_speed = ETH_SPEED_NUM_100M;
1867 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
1868 ETH_LINK_SPEED_FIXED);
1871 rte_i40e_dev_atomic_write_link_status(dev, &link);
1872 if (link.link_status == old.link_status)
1878 /* Get all the statistics of a VSI */
1880 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1882 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1883 struct i40e_eth_stats *nes = &vsi->eth_stats;
1884 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1885 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1887 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1888 vsi->offset_loaded, &oes->rx_bytes,
1890 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1891 vsi->offset_loaded, &oes->rx_unicast,
1893 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1894 vsi->offset_loaded, &oes->rx_multicast,
1895 &nes->rx_multicast);
1896 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1897 vsi->offset_loaded, &oes->rx_broadcast,
1898 &nes->rx_broadcast);
1899 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1900 &oes->rx_discards, &nes->rx_discards);
1901 /* GLV_REPC not supported */
1902 /* GLV_RMPC not supported */
1903 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1904 &oes->rx_unknown_protocol,
1905 &nes->rx_unknown_protocol);
1906 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1907 vsi->offset_loaded, &oes->tx_bytes,
1909 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1910 vsi->offset_loaded, &oes->tx_unicast,
1912 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1913 vsi->offset_loaded, &oes->tx_multicast,
1914 &nes->tx_multicast);
1915 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1916 vsi->offset_loaded, &oes->tx_broadcast,
1917 &nes->tx_broadcast);
1918 /* GLV_TDPC not supported */
1919 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1920 &oes->tx_errors, &nes->tx_errors);
1921 vsi->offset_loaded = true;
1923 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1925 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
1926 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
1927 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
1928 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
1929 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
1930 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1931 nes->rx_unknown_protocol);
1932 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
1933 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
1934 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
1935 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
1936 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
1937 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
1938 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1943 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
1946 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1947 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1949 /* Get statistics of struct i40e_eth_stats */
1950 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1951 I40E_GLPRT_GORCL(hw->port),
1952 pf->offset_loaded, &os->eth.rx_bytes,
1954 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1955 I40E_GLPRT_UPRCL(hw->port),
1956 pf->offset_loaded, &os->eth.rx_unicast,
1957 &ns->eth.rx_unicast);
1958 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1959 I40E_GLPRT_MPRCL(hw->port),
1960 pf->offset_loaded, &os->eth.rx_multicast,
1961 &ns->eth.rx_multicast);
1962 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1963 I40E_GLPRT_BPRCL(hw->port),
1964 pf->offset_loaded, &os->eth.rx_broadcast,
1965 &ns->eth.rx_broadcast);
1966 /* Workaround: CRC size should not be included in byte statistics,
1967 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
1969 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
1970 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
1972 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1973 pf->offset_loaded, &os->eth.rx_discards,
1974 &ns->eth.rx_discards);
1975 /* GLPRT_REPC not supported */
1976 /* GLPRT_RMPC not supported */
1977 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1979 &os->eth.rx_unknown_protocol,
1980 &ns->eth.rx_unknown_protocol);
1981 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1982 I40E_GLPRT_GOTCL(hw->port),
1983 pf->offset_loaded, &os->eth.tx_bytes,
1985 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1986 I40E_GLPRT_UPTCL(hw->port),
1987 pf->offset_loaded, &os->eth.tx_unicast,
1988 &ns->eth.tx_unicast);
1989 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1990 I40E_GLPRT_MPTCL(hw->port),
1991 pf->offset_loaded, &os->eth.tx_multicast,
1992 &ns->eth.tx_multicast);
1993 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1994 I40E_GLPRT_BPTCL(hw->port),
1995 pf->offset_loaded, &os->eth.tx_broadcast,
1996 &ns->eth.tx_broadcast);
1997 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
1998 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
1999 /* GLPRT_TEPC not supported */
2001 /* additional port specific stats */
2002 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2003 pf->offset_loaded, &os->tx_dropped_link_down,
2004 &ns->tx_dropped_link_down);
2005 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2006 pf->offset_loaded, &os->crc_errors,
2008 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2009 pf->offset_loaded, &os->illegal_bytes,
2010 &ns->illegal_bytes);
2011 /* GLPRT_ERRBC not supported */
2012 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2013 pf->offset_loaded, &os->mac_local_faults,
2014 &ns->mac_local_faults);
2015 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2016 pf->offset_loaded, &os->mac_remote_faults,
2017 &ns->mac_remote_faults);
2018 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2019 pf->offset_loaded, &os->rx_length_errors,
2020 &ns->rx_length_errors);
2021 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2022 pf->offset_loaded, &os->link_xon_rx,
2024 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2025 pf->offset_loaded, &os->link_xoff_rx,
2027 for (i = 0; i < 8; i++) {
2028 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2030 &os->priority_xon_rx[i],
2031 &ns->priority_xon_rx[i]);
2032 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2034 &os->priority_xoff_rx[i],
2035 &ns->priority_xoff_rx[i]);
2037 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2038 pf->offset_loaded, &os->link_xon_tx,
2040 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2041 pf->offset_loaded, &os->link_xoff_tx,
2043 for (i = 0; i < 8; i++) {
2044 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2046 &os->priority_xon_tx[i],
2047 &ns->priority_xon_tx[i]);
2048 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2050 &os->priority_xoff_tx[i],
2051 &ns->priority_xoff_tx[i]);
2052 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2054 &os->priority_xon_2_xoff[i],
2055 &ns->priority_xon_2_xoff[i]);
2057 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2058 I40E_GLPRT_PRC64L(hw->port),
2059 pf->offset_loaded, &os->rx_size_64,
2061 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2062 I40E_GLPRT_PRC127L(hw->port),
2063 pf->offset_loaded, &os->rx_size_127,
2065 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2066 I40E_GLPRT_PRC255L(hw->port),
2067 pf->offset_loaded, &os->rx_size_255,
2069 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2070 I40E_GLPRT_PRC511L(hw->port),
2071 pf->offset_loaded, &os->rx_size_511,
2073 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2074 I40E_GLPRT_PRC1023L(hw->port),
2075 pf->offset_loaded, &os->rx_size_1023,
2077 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2078 I40E_GLPRT_PRC1522L(hw->port),
2079 pf->offset_loaded, &os->rx_size_1522,
2081 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2082 I40E_GLPRT_PRC9522L(hw->port),
2083 pf->offset_loaded, &os->rx_size_big,
2085 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2086 pf->offset_loaded, &os->rx_undersize,
2088 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2089 pf->offset_loaded, &os->rx_fragments,
2091 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2092 pf->offset_loaded, &os->rx_oversize,
2094 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2095 pf->offset_loaded, &os->rx_jabber,
2097 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2098 I40E_GLPRT_PTC64L(hw->port),
2099 pf->offset_loaded, &os->tx_size_64,
2101 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2102 I40E_GLPRT_PTC127L(hw->port),
2103 pf->offset_loaded, &os->tx_size_127,
2105 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2106 I40E_GLPRT_PTC255L(hw->port),
2107 pf->offset_loaded, &os->tx_size_255,
2109 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2110 I40E_GLPRT_PTC511L(hw->port),
2111 pf->offset_loaded, &os->tx_size_511,
2113 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2114 I40E_GLPRT_PTC1023L(hw->port),
2115 pf->offset_loaded, &os->tx_size_1023,
2117 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2118 I40E_GLPRT_PTC1522L(hw->port),
2119 pf->offset_loaded, &os->tx_size_1522,
2121 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2122 I40E_GLPRT_PTC9522L(hw->port),
2123 pf->offset_loaded, &os->tx_size_big,
2125 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2127 &os->fd_sb_match, &ns->fd_sb_match);
2128 /* GLPRT_MSPDC not supported */
2129 /* GLPRT_XEC not supported */
2131 pf->offset_loaded = true;
2134 i40e_update_vsi_stats(pf->main_vsi);
2137 /* Get all statistics of a port */
2139 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2141 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2142 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2143 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2146 /* call read registers - updates values, now write them to struct */
2147 i40e_read_stats_registers(pf, hw);
2149 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2150 pf->main_vsi->eth_stats.rx_multicast +
2151 pf->main_vsi->eth_stats.rx_broadcast -
2152 pf->main_vsi->eth_stats.rx_discards;
2153 stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2154 pf->main_vsi->eth_stats.tx_multicast +
2155 pf->main_vsi->eth_stats.tx_broadcast;
2156 stats->ibytes = ns->eth.rx_bytes;
2157 stats->obytes = ns->eth.tx_bytes;
2158 stats->oerrors = ns->eth.tx_errors +
2159 pf->main_vsi->eth_stats.tx_errors;
2162 stats->imissed = ns->eth.rx_discards +
2163 pf->main_vsi->eth_stats.rx_discards;
2164 stats->ierrors = ns->crc_errors +
2165 ns->rx_length_errors + ns->rx_undersize +
2166 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2168 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2169 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
2170 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
2171 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
2172 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
2173 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
2174 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2175 ns->eth.rx_unknown_protocol);
2176 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
2177 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
2178 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
2179 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
2180 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
2181 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
2183 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
2184 ns->tx_dropped_link_down);
2185 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
2186 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
2188 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
2189 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
2190 ns->mac_local_faults);
2191 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
2192 ns->mac_remote_faults);
2193 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
2194 ns->rx_length_errors);
2195 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
2196 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
2197 for (i = 0; i < 8; i++) {
2198 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
2199 i, ns->priority_xon_rx[i]);
2200 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
2201 i, ns->priority_xoff_rx[i]);
2203 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
2204 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
2205 for (i = 0; i < 8; i++) {
2206 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
2207 i, ns->priority_xon_tx[i]);
2208 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
2209 i, ns->priority_xoff_tx[i]);
2210 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
2211 i, ns->priority_xon_2_xoff[i]);
2213 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
2214 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
2215 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
2216 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
2217 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
2218 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
2219 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
2220 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
2221 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
2222 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
2223 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
2224 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
2225 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
2226 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
2227 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
2228 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
2229 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
2230 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
2231 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2232 ns->mac_short_packet_dropped);
2233 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
2234 ns->checksum_error);
2235 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
2236 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2239 /* Reset the statistics */
2241 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2243 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2244 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2246 /* Mark PF and VSI stats to update the offset, aka "reset" */
2247 pf->offset_loaded = false;
2249 pf->main_vsi->offset_loaded = false;
2251 /* read the stats, reading current register values into offset */
2252 i40e_read_stats_registers(pf, hw);
2256 i40e_xstats_calc_num(void)
2258 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2259 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2260 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2263 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2264 struct rte_eth_xstat_name *xstats_names,
2265 __rte_unused unsigned limit)
2270 if (xstats_names == NULL)
2271 return i40e_xstats_calc_num();
2273 /* Note: limit checked in rte_eth_xstats_names() */
2275 /* Get stats from i40e_eth_stats struct */
2276 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2277 snprintf(xstats_names[count].name,
2278 sizeof(xstats_names[count].name),
2279 "%s", rte_i40e_stats_strings[i].name);
2280 xstats_names[count].id = count;
2284 /* Get individiual stats from i40e_hw_port struct */
2285 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2286 snprintf(xstats_names[count].name,
2287 sizeof(xstats_names[count].name),
2288 "%s", rte_i40e_hw_port_strings[i].name);
2289 xstats_names[count].id = count;
2293 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2294 for (prio = 0; prio < 8; prio++) {
2295 snprintf(xstats_names[count].name,
2296 sizeof(xstats_names[count].name),
2297 "rx_priority%u_%s", prio,
2298 rte_i40e_rxq_prio_strings[i].name);
2299 xstats_names[count].id = count;
2304 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2305 for (prio = 0; prio < 8; prio++) {
2306 snprintf(xstats_names[count].name,
2307 sizeof(xstats_names[count].name),
2308 "tx_priority%u_%s", prio,
2309 rte_i40e_txq_prio_strings[i].name);
2310 xstats_names[count].id = count;
2318 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2321 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2322 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2323 unsigned i, count, prio;
2324 struct i40e_hw_port_stats *hw_stats = &pf->stats;
2326 count = i40e_xstats_calc_num();
2330 i40e_read_stats_registers(pf, hw);
2337 /* Get stats from i40e_eth_stats struct */
2338 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2339 xstats[count].id = count;
2340 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2341 rte_i40e_stats_strings[i].offset);
2345 /* Get individiual stats from i40e_hw_port struct */
2346 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2347 xstats[count].id = count;
2348 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2349 rte_i40e_hw_port_strings[i].offset);
2353 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2354 for (prio = 0; prio < 8; prio++) {
2355 xstats[count].id = count;
2356 xstats[count].value =
2357 *(uint64_t *)(((char *)hw_stats) +
2358 rte_i40e_rxq_prio_strings[i].offset +
2359 (sizeof(uint64_t) * prio));
2364 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2365 for (prio = 0; prio < 8; prio++) {
2366 xstats[count].id = count;
2367 xstats[count].value =
2368 *(uint64_t *)(((char *)hw_stats) +
2369 rte_i40e_txq_prio_strings[i].offset +
2370 (sizeof(uint64_t) * prio));
2379 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2380 __rte_unused uint16_t queue_id,
2381 __rte_unused uint8_t stat_idx,
2382 __rte_unused uint8_t is_rx)
2384 PMD_INIT_FUNC_TRACE();
2390 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2392 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2393 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2394 struct i40e_vsi *vsi = pf->main_vsi;
2396 dev_info->max_rx_queues = vsi->nb_qps;
2397 dev_info->max_tx_queues = vsi->nb_qps;
2398 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2399 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2400 dev_info->max_mac_addrs = vsi->max_macaddrs;
2401 dev_info->max_vfs = dev->pci_dev->max_vfs;
2402 dev_info->rx_offload_capa =
2403 DEV_RX_OFFLOAD_VLAN_STRIP |
2404 DEV_RX_OFFLOAD_QINQ_STRIP |
2405 DEV_RX_OFFLOAD_IPV4_CKSUM |
2406 DEV_RX_OFFLOAD_UDP_CKSUM |
2407 DEV_RX_OFFLOAD_TCP_CKSUM;
2408 dev_info->tx_offload_capa =
2409 DEV_TX_OFFLOAD_VLAN_INSERT |
2410 DEV_TX_OFFLOAD_QINQ_INSERT |
2411 DEV_TX_OFFLOAD_IPV4_CKSUM |
2412 DEV_TX_OFFLOAD_UDP_CKSUM |
2413 DEV_TX_OFFLOAD_TCP_CKSUM |
2414 DEV_TX_OFFLOAD_SCTP_CKSUM |
2415 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2416 DEV_TX_OFFLOAD_TCP_TSO;
2417 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2419 dev_info->reta_size = pf->hash_lut_size;
2420 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2422 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2424 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2425 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2426 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2428 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2432 dev_info->default_txconf = (struct rte_eth_txconf) {
2434 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2435 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2436 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2438 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2439 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2440 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2441 ETH_TXQ_FLAGS_NOOFFLOADS,
2444 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2445 .nb_max = I40E_MAX_RING_DESC,
2446 .nb_min = I40E_MIN_RING_DESC,
2447 .nb_align = I40E_ALIGN_RING_DESC,
2450 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2451 .nb_max = I40E_MAX_RING_DESC,
2452 .nb_min = I40E_MIN_RING_DESC,
2453 .nb_align = I40E_ALIGN_RING_DESC,
2456 if (pf->flags & I40E_FLAG_VMDQ) {
2457 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2458 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2459 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2460 pf->max_nb_vmdq_vsi;
2461 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2462 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2463 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2466 if (i40e_is_40G_device(hw->device_id))
2468 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2471 dev_info->speed_capa = ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G;
2475 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2477 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2478 struct i40e_vsi *vsi = pf->main_vsi;
2479 PMD_INIT_FUNC_TRACE();
2482 return i40e_vsi_add_vlan(vsi, vlan_id);
2484 return i40e_vsi_delete_vlan(vsi, vlan_id);
2488 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2489 enum rte_vlan_type vlan_type,
2492 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2493 uint64_t reg_r = 0, reg_w = 0;
2494 uint16_t reg_id = 0;
2497 switch (vlan_type) {
2498 case ETH_VLAN_TYPE_OUTER:
2501 case ETH_VLAN_TYPE_INNER:
2506 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2509 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2511 if (ret != I40E_SUCCESS) {
2512 PMD_DRV_LOG(ERR, "Fail to debug read from "
2513 "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2517 PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2518 "0x%08"PRIx64"", reg_id, reg_r);
2520 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2521 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2522 if (reg_r == reg_w) {
2524 PMD_DRV_LOG(DEBUG, "No need to write");
2528 ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2530 if (ret != I40E_SUCCESS) {
2532 PMD_DRV_LOG(ERR, "Fail to debug write to "
2533 "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2536 PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2537 "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2543 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2545 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2546 struct i40e_vsi *vsi = pf->main_vsi;
2548 if (mask & ETH_VLAN_FILTER_MASK) {
2549 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2550 i40e_vsi_config_vlan_filter(vsi, TRUE);
2552 i40e_vsi_config_vlan_filter(vsi, FALSE);
2555 if (mask & ETH_VLAN_STRIP_MASK) {
2556 /* Enable or disable VLAN stripping */
2557 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2558 i40e_vsi_config_vlan_stripping(vsi, TRUE);
2560 i40e_vsi_config_vlan_stripping(vsi, FALSE);
2563 if (mask & ETH_VLAN_EXTEND_MASK) {
2564 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2565 i40e_vsi_config_double_vlan(vsi, TRUE);
2567 i40e_vsi_config_double_vlan(vsi, FALSE);
2572 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2573 __rte_unused uint16_t queue,
2574 __rte_unused int on)
2576 PMD_INIT_FUNC_TRACE();
2580 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2582 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2583 struct i40e_vsi *vsi = pf->main_vsi;
2584 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2585 struct i40e_vsi_vlan_pvid_info info;
2587 memset(&info, 0, sizeof(info));
2590 info.config.pvid = pvid;
2592 info.config.reject.tagged =
2593 data->dev_conf.txmode.hw_vlan_reject_tagged;
2594 info.config.reject.untagged =
2595 data->dev_conf.txmode.hw_vlan_reject_untagged;
2598 return i40e_vsi_vlan_pvid_set(vsi, &info);
2602 i40e_dev_led_on(struct rte_eth_dev *dev)
2604 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2605 uint32_t mode = i40e_led_get(hw);
2608 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2614 i40e_dev_led_off(struct rte_eth_dev *dev)
2616 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2617 uint32_t mode = i40e_led_get(hw);
2620 i40e_led_set(hw, 0, false);
2626 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2628 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2629 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2631 fc_conf->pause_time = pf->fc_conf.pause_time;
2632 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2633 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2635 /* Return current mode according to actual setting*/
2636 switch (hw->fc.current_mode) {
2638 fc_conf->mode = RTE_FC_FULL;
2640 case I40E_FC_TX_PAUSE:
2641 fc_conf->mode = RTE_FC_TX_PAUSE;
2643 case I40E_FC_RX_PAUSE:
2644 fc_conf->mode = RTE_FC_RX_PAUSE;
2648 fc_conf->mode = RTE_FC_NONE;
2655 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2657 uint32_t mflcn_reg, fctrl_reg, reg;
2658 uint32_t max_high_water;
2659 uint8_t i, aq_failure;
2663 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2664 [RTE_FC_NONE] = I40E_FC_NONE,
2665 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2666 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2667 [RTE_FC_FULL] = I40E_FC_FULL
2670 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2672 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2673 if ((fc_conf->high_water > max_high_water) ||
2674 (fc_conf->high_water < fc_conf->low_water)) {
2675 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2676 "High_water must <= %d.", max_high_water);
2680 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2681 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2682 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2684 pf->fc_conf.pause_time = fc_conf->pause_time;
2685 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2686 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2688 PMD_INIT_FUNC_TRACE();
2690 /* All the link flow control related enable/disable register
2691 * configuration is handle by the F/W
2693 err = i40e_set_fc(hw, &aq_failure, true);
2697 if (i40e_is_40G_device(hw->device_id)) {
2698 /* Configure flow control refresh threshold,
2699 * the value for stat_tx_pause_refresh_timer[8]
2700 * is used for global pause operation.
2704 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2705 pf->fc_conf.pause_time);
2707 /* configure the timer value included in transmitted pause
2709 * the value for stat_tx_pause_quanta[8] is used for global
2712 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2713 pf->fc_conf.pause_time);
2715 fctrl_reg = I40E_READ_REG(hw,
2716 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2718 if (fc_conf->mac_ctrl_frame_fwd != 0)
2719 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2721 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2723 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2726 /* Configure pause time (2 TCs per register) */
2727 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2728 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2729 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2731 /* Configure flow control refresh threshold value */
2732 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2733 pf->fc_conf.pause_time / 2);
2735 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2737 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2738 *depending on configuration
2740 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2741 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2742 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2744 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2745 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2748 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2751 /* config the water marker both based on the packets and bytes */
2752 I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2753 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2754 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2755 I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2756 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2757 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2758 I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2759 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2761 I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2762 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2765 I40E_WRITE_FLUSH(hw);
2771 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2772 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2774 PMD_INIT_FUNC_TRACE();
2779 /* Add a MAC address, and update filters */
2781 i40e_macaddr_add(struct rte_eth_dev *dev,
2782 struct ether_addr *mac_addr,
2783 __rte_unused uint32_t index,
2786 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2787 struct i40e_mac_filter_info mac_filter;
2788 struct i40e_vsi *vsi;
2791 /* If VMDQ not enabled or configured, return */
2792 if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
2793 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2794 pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
2799 if (pool > pf->nb_cfg_vmdq_vsi) {
2800 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2801 pool, pf->nb_cfg_vmdq_vsi);
2805 (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2806 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2807 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2809 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
2814 vsi = pf->vmdq[pool - 1].vsi;
2816 ret = i40e_vsi_add_mac(vsi, &mac_filter);
2817 if (ret != I40E_SUCCESS) {
2818 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2823 /* Remove a MAC address, and update filters */
2825 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2827 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2828 struct i40e_vsi *vsi;
2829 struct rte_eth_dev_data *data = dev->data;
2830 struct ether_addr *macaddr;
2835 macaddr = &(data->mac_addrs[index]);
2837 pool_sel = dev->data->mac_pool_sel[index];
2839 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
2840 if (pool_sel & (1ULL << i)) {
2844 /* No VMDQ pool enabled or configured */
2845 if (!(pf->flags | I40E_FLAG_VMDQ) ||
2846 (i > pf->nb_cfg_vmdq_vsi)) {
2847 PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
2851 vsi = pf->vmdq[i - 1].vsi;
2853 ret = i40e_vsi_delete_mac(vsi, macaddr);
2856 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
2863 /* Set perfect match or hash match of MAC and VLAN for a VF */
2865 i40e_vf_mac_filter_set(struct i40e_pf *pf,
2866 struct rte_eth_mac_filter *filter,
2870 struct i40e_mac_filter_info mac_filter;
2871 struct ether_addr old_mac;
2872 struct ether_addr *new_mac;
2873 struct i40e_pf_vf *vf = NULL;
2878 PMD_DRV_LOG(ERR, "Invalid PF argument.");
2881 hw = I40E_PF_TO_HW(pf);
2883 if (filter == NULL) {
2884 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
2888 new_mac = &filter->mac_addr;
2890 if (is_zero_ether_addr(new_mac)) {
2891 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
2895 vf_id = filter->dst_id;
2897 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
2898 PMD_DRV_LOG(ERR, "Invalid argument.");
2901 vf = &pf->vfs[vf_id];
2903 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
2904 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
2909 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
2910 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
2912 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
2915 mac_filter.filter_type = filter->filter_type;
2916 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
2917 if (ret != I40E_SUCCESS) {
2918 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
2921 ether_addr_copy(new_mac, &pf->dev_addr);
2923 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
2925 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
2926 if (ret != I40E_SUCCESS) {
2927 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
2931 /* Clear device address as it has been removed */
2932 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
2933 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
2939 /* MAC filter handle */
2941 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
2944 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2945 struct rte_eth_mac_filter *filter;
2946 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2947 int ret = I40E_NOT_SUPPORTED;
2949 filter = (struct rte_eth_mac_filter *)(arg);
2951 switch (filter_op) {
2952 case RTE_ETH_FILTER_NOP:
2955 case RTE_ETH_FILTER_ADD:
2956 i40e_pf_disable_irq0(hw);
2958 ret = i40e_vf_mac_filter_set(pf, filter, 1);
2959 i40e_pf_enable_irq0(hw);
2961 case RTE_ETH_FILTER_DELETE:
2962 i40e_pf_disable_irq0(hw);
2964 ret = i40e_vf_mac_filter_set(pf, filter, 0);
2965 i40e_pf_enable_irq0(hw);
2968 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2969 ret = I40E_ERR_PARAM;
2977 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2979 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2980 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2986 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2987 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
2990 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2994 uint32_t *lut_dw = (uint32_t *)lut;
2995 uint16_t i, lut_size_dw = lut_size / 4;
2997 for (i = 0; i < lut_size_dw; i++)
2998 lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3005 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3007 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3008 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3014 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3015 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3018 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3022 uint32_t *lut_dw = (uint32_t *)lut;
3023 uint16_t i, lut_size_dw = lut_size / 4;
3025 for (i = 0; i < lut_size_dw; i++)
3026 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3027 I40E_WRITE_FLUSH(hw);
3034 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3035 struct rte_eth_rss_reta_entry64 *reta_conf,
3038 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3039 uint16_t i, lut_size = pf->hash_lut_size;
3040 uint16_t idx, shift;
3044 if (reta_size != lut_size ||
3045 reta_size > ETH_RSS_RETA_SIZE_512) {
3046 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3047 "(%d) doesn't match the number hardware can supported "
3048 "(%d)\n", reta_size, lut_size);
3052 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3054 PMD_DRV_LOG(ERR, "No memory can be allocated");
3057 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3060 for (i = 0; i < reta_size; i++) {
3061 idx = i / RTE_RETA_GROUP_SIZE;
3062 shift = i % RTE_RETA_GROUP_SIZE;
3063 if (reta_conf[idx].mask & (1ULL << shift))
3064 lut[i] = reta_conf[idx].reta[shift];
3066 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3075 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3076 struct rte_eth_rss_reta_entry64 *reta_conf,
3079 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3080 uint16_t i, lut_size = pf->hash_lut_size;
3081 uint16_t idx, shift;
3085 if (reta_size != lut_size ||
3086 reta_size > ETH_RSS_RETA_SIZE_512) {
3087 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3088 "(%d) doesn't match the number hardware can supported "
3089 "(%d)\n", reta_size, lut_size);
3093 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3095 PMD_DRV_LOG(ERR, "No memory can be allocated");
3099 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3102 for (i = 0; i < reta_size; i++) {
3103 idx = i / RTE_RETA_GROUP_SIZE;
3104 shift = i % RTE_RETA_GROUP_SIZE;
3105 if (reta_conf[idx].mask & (1ULL << shift))
3106 reta_conf[idx].reta[shift] = lut[i];
3116 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3117 * @hw: pointer to the HW structure
3118 * @mem: pointer to mem struct to fill out
3119 * @size: size of memory requested
3120 * @alignment: what to align the allocation to
3122 enum i40e_status_code
3123 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3124 struct i40e_dma_mem *mem,
3128 const struct rte_memzone *mz = NULL;
3129 char z_name[RTE_MEMZONE_NAMESIZE];
3132 return I40E_ERR_PARAM;
3134 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3135 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3136 alignment, RTE_PGSIZE_2M);
3138 return I40E_ERR_NO_MEMORY;
3142 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3143 mem->zone = (const void *)mz;
3144 PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3145 "%"PRIu64, mz->name, mem->pa);
3147 return I40E_SUCCESS;
3151 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3152 * @hw: pointer to the HW structure
3153 * @mem: ptr to mem struct to free
3155 enum i40e_status_code
3156 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3157 struct i40e_dma_mem *mem)
3160 return I40E_ERR_PARAM;
3162 PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3163 "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3165 rte_memzone_free((const struct rte_memzone *)mem->zone);
3170 return I40E_SUCCESS;
3174 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3175 * @hw: pointer to the HW structure
3176 * @mem: pointer to mem struct to fill out
3177 * @size: size of memory requested
3179 enum i40e_status_code
3180 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3181 struct i40e_virt_mem *mem,
3185 return I40E_ERR_PARAM;
3188 mem->va = rte_zmalloc("i40e", size, 0);
3191 return I40E_SUCCESS;
3193 return I40E_ERR_NO_MEMORY;
3197 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3198 * @hw: pointer to the HW structure
3199 * @mem: pointer to mem struct to free
3201 enum i40e_status_code
3202 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3203 struct i40e_virt_mem *mem)
3206 return I40E_ERR_PARAM;
3211 return I40E_SUCCESS;
3215 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3217 rte_spinlock_init(&sp->spinlock);
3221 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3223 rte_spinlock_lock(&sp->spinlock);
3227 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3229 rte_spinlock_unlock(&sp->spinlock);
3233 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3239 * Get the hardware capabilities, which will be parsed
3240 * and saved into struct i40e_hw.
3243 i40e_get_cap(struct i40e_hw *hw)
3245 struct i40e_aqc_list_capabilities_element_resp *buf;
3246 uint16_t len, size = 0;
3249 /* Calculate a huge enough buff for saving response data temporarily */
3250 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3251 I40E_MAX_CAP_ELE_NUM;
3252 buf = rte_zmalloc("i40e", len, 0);
3254 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3255 return I40E_ERR_NO_MEMORY;
3258 /* Get, parse the capabilities and save it to hw */
3259 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3260 i40e_aqc_opc_list_func_capabilities, NULL);
3261 if (ret != I40E_SUCCESS)
3262 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3264 /* Free the temporary buffer after being used */
3271 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3273 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3274 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3275 uint16_t qp_count = 0, vsi_count = 0;
3277 if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3278 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3281 /* Add the parameter init for LFC */
3282 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3283 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3284 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3286 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3287 pf->max_num_vsi = hw->func_caps.num_vsis;
3288 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3289 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3290 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3292 /* FDir queue/VSI allocation */
3293 pf->fdir_qp_offset = 0;
3294 if (hw->func_caps.fd) {
3295 pf->flags |= I40E_FLAG_FDIR;
3296 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3298 pf->fdir_nb_qps = 0;
3300 qp_count += pf->fdir_nb_qps;
3303 /* LAN queue/VSI allocation */
3304 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3305 if (!hw->func_caps.rss) {
3308 pf->flags |= I40E_FLAG_RSS;
3309 if (hw->mac.type == I40E_MAC_X722)
3310 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3311 pf->lan_nb_qps = pf->lan_nb_qp_max;
3313 qp_count += pf->lan_nb_qps;
3316 /* VF queue/VSI allocation */
3317 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3318 if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3319 pf->flags |= I40E_FLAG_SRIOV;
3320 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3321 pf->vf_num = dev->pci_dev->max_vfs;
3322 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3323 "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3324 pf->vf_nb_qps * pf->vf_num);
3329 qp_count += pf->vf_nb_qps * pf->vf_num;
3330 vsi_count += pf->vf_num;
3332 /* VMDq queue/VSI allocation */
3333 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3334 pf->vmdq_nb_qps = 0;
3335 pf->max_nb_vmdq_vsi = 0;
3336 if (hw->func_caps.vmdq) {
3337 if (qp_count < hw->func_caps.num_tx_qp &&
3338 vsi_count < hw->func_caps.num_vsis) {
3339 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3340 qp_count) / pf->vmdq_nb_qp_max;
3342 /* Limit the maximum number of VMDq vsi to the maximum
3343 * ethdev can support
3345 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3346 hw->func_caps.num_vsis - vsi_count);
3347 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3349 if (pf->max_nb_vmdq_vsi) {
3350 pf->flags |= I40E_FLAG_VMDQ;
3351 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3352 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3353 "per VMDQ VSI, in total %u queues",
3354 pf->max_nb_vmdq_vsi,
3355 pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3356 pf->max_nb_vmdq_vsi);
3358 PMD_DRV_LOG(INFO, "No enough queues left for "
3362 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3365 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3366 vsi_count += pf->max_nb_vmdq_vsi;
3368 if (hw->func_caps.dcb)
3369 pf->flags |= I40E_FLAG_DCB;
3371 if (qp_count > hw->func_caps.num_tx_qp) {
3372 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3373 "the hardware maximum %u", qp_count,
3374 hw->func_caps.num_tx_qp);
3377 if (vsi_count > hw->func_caps.num_vsis) {
3378 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3379 "the hardware maximum %u", vsi_count,
3380 hw->func_caps.num_vsis);
3388 i40e_pf_get_switch_config(struct i40e_pf *pf)
3390 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3391 struct i40e_aqc_get_switch_config_resp *switch_config;
3392 struct i40e_aqc_switch_config_element_resp *element;
3393 uint16_t start_seid = 0, num_reported;
3396 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3397 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3398 if (!switch_config) {
3399 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3403 /* Get the switch configurations */
3404 ret = i40e_aq_get_switch_config(hw, switch_config,
3405 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3406 if (ret != I40E_SUCCESS) {
3407 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3410 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3411 if (num_reported != 1) { /* The number should be 1 */
3412 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3416 /* Parse the switch configuration elements */
3417 element = &(switch_config->element[0]);
3418 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3419 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3420 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3422 PMD_DRV_LOG(INFO, "Unknown element type");
3425 rte_free(switch_config);
3431 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3434 struct pool_entry *entry;
3436 if (pool == NULL || num == 0)
3439 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3440 if (entry == NULL) {
3441 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3445 /* queue heap initialize */
3446 pool->num_free = num;
3447 pool->num_alloc = 0;
3449 LIST_INIT(&pool->alloc_list);
3450 LIST_INIT(&pool->free_list);
3452 /* Initialize element */
3456 LIST_INSERT_HEAD(&pool->free_list, entry, next);
3461 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3463 struct pool_entry *entry, *next_entry;
3468 for (entry = LIST_FIRST(&pool->alloc_list);
3469 entry && (next_entry = LIST_NEXT(entry, next), 1);
3470 entry = next_entry) {
3471 LIST_REMOVE(entry, next);
3475 for (entry = LIST_FIRST(&pool->free_list);
3476 entry && (next_entry = LIST_NEXT(entry, next), 1);
3477 entry = next_entry) {
3478 LIST_REMOVE(entry, next);
3483 pool->num_alloc = 0;
3485 LIST_INIT(&pool->alloc_list);
3486 LIST_INIT(&pool->free_list);
3490 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3493 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3494 uint32_t pool_offset;
3498 PMD_DRV_LOG(ERR, "Invalid parameter");
3502 pool_offset = base - pool->base;
3503 /* Lookup in alloc list */
3504 LIST_FOREACH(entry, &pool->alloc_list, next) {
3505 if (entry->base == pool_offset) {
3506 valid_entry = entry;
3507 LIST_REMOVE(entry, next);
3512 /* Not find, return */
3513 if (valid_entry == NULL) {
3514 PMD_DRV_LOG(ERR, "Failed to find entry");
3519 * Found it, move it to free list and try to merge.
3520 * In order to make merge easier, always sort it by qbase.
3521 * Find adjacent prev and last entries.
3524 LIST_FOREACH(entry, &pool->free_list, next) {
3525 if (entry->base > valid_entry->base) {
3533 /* Try to merge with next one*/
3535 /* Merge with next one */
3536 if (valid_entry->base + valid_entry->len == next->base) {
3537 next->base = valid_entry->base;
3538 next->len += valid_entry->len;
3539 rte_free(valid_entry);
3546 /* Merge with previous one */
3547 if (prev->base + prev->len == valid_entry->base) {
3548 prev->len += valid_entry->len;
3549 /* If it merge with next one, remove next node */
3551 LIST_REMOVE(valid_entry, next);
3552 rte_free(valid_entry);
3554 rte_free(valid_entry);
3560 /* Not find any entry to merge, insert */
3563 LIST_INSERT_AFTER(prev, valid_entry, next);
3564 else if (next != NULL)
3565 LIST_INSERT_BEFORE(next, valid_entry, next);
3566 else /* It's empty list, insert to head */
3567 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3570 pool->num_free += valid_entry->len;
3571 pool->num_alloc -= valid_entry->len;
3577 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3580 struct pool_entry *entry, *valid_entry;
3582 if (pool == NULL || num == 0) {
3583 PMD_DRV_LOG(ERR, "Invalid parameter");
3587 if (pool->num_free < num) {
3588 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3589 num, pool->num_free);
3594 /* Lookup in free list and find most fit one */
3595 LIST_FOREACH(entry, &pool->free_list, next) {
3596 if (entry->len >= num) {
3598 if (entry->len == num) {
3599 valid_entry = entry;
3602 if (valid_entry == NULL || valid_entry->len > entry->len)
3603 valid_entry = entry;
3607 /* Not find one to satisfy the request, return */
3608 if (valid_entry == NULL) {
3609 PMD_DRV_LOG(ERR, "No valid entry found");
3613 * The entry have equal queue number as requested,
3614 * remove it from alloc_list.
3616 if (valid_entry->len == num) {
3617 LIST_REMOVE(valid_entry, next);
3620 * The entry have more numbers than requested,
3621 * create a new entry for alloc_list and minus its
3622 * queue base and number in free_list.
3624 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3625 if (entry == NULL) {
3626 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3630 entry->base = valid_entry->base;
3632 valid_entry->base += num;
3633 valid_entry->len -= num;
3634 valid_entry = entry;
3637 /* Insert it into alloc list, not sorted */
3638 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3640 pool->num_free -= valid_entry->len;
3641 pool->num_alloc += valid_entry->len;
3643 return valid_entry->base + pool->base;
3647 * bitmap_is_subset - Check whether src2 is subset of src1
3650 bitmap_is_subset(uint8_t src1, uint8_t src2)
3652 return !((src1 ^ src2) & src2);
3655 static enum i40e_status_code
3656 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3658 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3660 /* If DCB is not supported, only default TC is supported */
3661 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3662 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3663 return I40E_NOT_SUPPORTED;
3666 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3667 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3668 "HW support 0x%x", hw->func_caps.enabled_tcmap,
3670 return I40E_NOT_SUPPORTED;
3672 return I40E_SUCCESS;
3676 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3677 struct i40e_vsi_vlan_pvid_info *info)
3680 struct i40e_vsi_context ctxt;
3681 uint8_t vlan_flags = 0;
3684 if (vsi == NULL || info == NULL) {
3685 PMD_DRV_LOG(ERR, "invalid parameters");
3686 return I40E_ERR_PARAM;
3690 vsi->info.pvid = info->config.pvid;
3692 * If insert pvid is enabled, only tagged pkts are
3693 * allowed to be sent out.
3695 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3696 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3699 if (info->config.reject.tagged == 0)
3700 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3702 if (info->config.reject.untagged == 0)
3703 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3705 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3706 I40E_AQ_VSI_PVLAN_MODE_MASK);
3707 vsi->info.port_vlan_flags |= vlan_flags;
3708 vsi->info.valid_sections =
3709 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3710 memset(&ctxt, 0, sizeof(ctxt));
3711 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3712 ctxt.seid = vsi->seid;
3714 hw = I40E_VSI_TO_HW(vsi);
3715 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3716 if (ret != I40E_SUCCESS)
3717 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3723 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3725 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3727 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3729 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3730 if (ret != I40E_SUCCESS)
3734 PMD_DRV_LOG(ERR, "seid not valid");
3738 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3739 tc_bw_data.tc_valid_bits = enabled_tcmap;
3740 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3741 tc_bw_data.tc_bw_credits[i] =
3742 (enabled_tcmap & (1 << i)) ? 1 : 0;
3744 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3745 if (ret != I40E_SUCCESS) {
3746 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3750 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3751 sizeof(vsi->info.qs_handle));
3752 return I40E_SUCCESS;
3755 static enum i40e_status_code
3756 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3757 struct i40e_aqc_vsi_properties_data *info,
3758 uint8_t enabled_tcmap)
3760 enum i40e_status_code ret;
3761 int i, total_tc = 0;
3762 uint16_t qpnum_per_tc, bsf, qp_idx;
3764 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3765 if (ret != I40E_SUCCESS)
3768 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3769 if (enabled_tcmap & (1 << i))
3771 vsi->enabled_tc = enabled_tcmap;
3773 /* Number of queues per enabled TC */
3774 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3775 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3776 bsf = rte_bsf32(qpnum_per_tc);
3778 /* Adjust the queue number to actual queues that can be applied */
3779 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3780 vsi->nb_qps = qpnum_per_tc * total_tc;
3783 * Configure TC and queue mapping parameters, for enabled TC,
3784 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3785 * default queue will serve it.
3788 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3789 if (vsi->enabled_tc & (1 << i)) {
3790 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3791 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3792 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
3793 qp_idx += qpnum_per_tc;
3795 info->tc_mapping[i] = 0;
3798 /* Associate queue number with VSI */
3799 if (vsi->type == I40E_VSI_SRIOV) {
3800 info->mapping_flags |=
3801 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
3802 for (i = 0; i < vsi->nb_qps; i++)
3803 info->queue_mapping[i] =
3804 rte_cpu_to_le_16(vsi->base_queue + i);
3806 info->mapping_flags |=
3807 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3808 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3810 info->valid_sections |=
3811 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
3813 return I40E_SUCCESS;
3817 i40e_veb_release(struct i40e_veb *veb)
3819 struct i40e_vsi *vsi;
3822 if (veb == NULL || veb->associate_vsi == NULL)
3825 if (!TAILQ_EMPTY(&veb->head)) {
3826 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
3830 vsi = veb->associate_vsi;
3831 hw = I40E_VSI_TO_HW(vsi);
3833 vsi->uplink_seid = veb->uplink_seid;
3834 i40e_aq_delete_element(hw, veb->seid, NULL);
3837 return I40E_SUCCESS;
3841 static struct i40e_veb *
3842 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
3844 struct i40e_veb *veb;
3848 if (NULL == pf || vsi == NULL) {
3849 PMD_DRV_LOG(ERR, "veb setup failed, "
3850 "associated VSI shouldn't null");
3853 hw = I40E_PF_TO_HW(pf);
3855 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
3857 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
3861 veb->associate_vsi = vsi;
3862 TAILQ_INIT(&veb->head);
3863 veb->uplink_seid = vsi->uplink_seid;
3865 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
3866 I40E_DEFAULT_TCMAP, false, &veb->seid, false, NULL);
3868 if (ret != I40E_SUCCESS) {
3869 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
3870 hw->aq.asq_last_status);
3874 /* get statistics index */
3875 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
3876 &veb->stats_idx, NULL, NULL, NULL);
3877 if (ret != I40E_SUCCESS) {
3878 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
3879 hw->aq.asq_last_status);
3883 /* Get VEB bandwidth, to be implemented */
3884 /* Now associated vsi binding to the VEB, set uplink to this VEB */
3885 vsi->uplink_seid = veb->seid;
3894 i40e_vsi_release(struct i40e_vsi *vsi)
3898 struct i40e_vsi_list *vsi_list;
3900 struct i40e_mac_filter *f;
3903 return I40E_SUCCESS;
3905 pf = I40E_VSI_TO_PF(vsi);
3906 hw = I40E_VSI_TO_HW(vsi);
3908 /* VSI has child to attach, release child first */
3910 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
3911 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
3913 TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
3915 i40e_veb_release(vsi->veb);
3918 /* Remove all macvlan filters of the VSI */
3919 i40e_vsi_remove_all_macvlan_filter(vsi);
3920 TAILQ_FOREACH(f, &vsi->mac_list, next)
3923 if (vsi->type != I40E_VSI_MAIN) {
3924 /* Remove vsi from parent's sibling list */
3925 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
3926 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
3927 return I40E_ERR_PARAM;
3929 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
3930 &vsi->sib_vsi_list, list);
3932 /* Remove all switch element of the VSI */
3933 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
3934 if (ret != I40E_SUCCESS)
3935 PMD_DRV_LOG(ERR, "Failed to delete element");
3937 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
3939 if (vsi->type != I40E_VSI_SRIOV)
3940 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
3943 return I40E_SUCCESS;
3947 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
3949 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3950 struct i40e_aqc_remove_macvlan_element_data def_filter;
3951 struct i40e_mac_filter_info filter;
3954 if (vsi->type != I40E_VSI_MAIN)
3955 return I40E_ERR_CONFIG;
3956 memset(&def_filter, 0, sizeof(def_filter));
3957 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
3959 def_filter.vlan_tag = 0;
3960 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
3961 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
3962 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
3963 if (ret != I40E_SUCCESS) {
3964 struct i40e_mac_filter *f;
3965 struct ether_addr *mac;
3967 PMD_DRV_LOG(WARNING, "Cannot remove the default "
3969 /* It needs to add the permanent mac into mac list */
3970 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3972 PMD_DRV_LOG(ERR, "failed to allocate memory");
3973 return I40E_ERR_NO_MEMORY;
3975 mac = &f->mac_info.mac_addr;
3976 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
3978 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3979 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3984 (void)rte_memcpy(&filter.mac_addr,
3985 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
3986 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3987 return i40e_vsi_add_mac(vsi, &filter);
3991 * i40e_vsi_get_bw_config - Query VSI BW Information
3992 * @vsi: the VSI to be queried
3994 * Returns 0 on success, negative value on failure
3996 static enum i40e_status_code
3997 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
3999 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4000 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4001 struct i40e_hw *hw = &vsi->adapter->hw;
4006 memset(&bw_config, 0, sizeof(bw_config));
4007 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4008 if (ret != I40E_SUCCESS) {
4009 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4010 hw->aq.asq_last_status);
4014 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4015 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4016 &ets_sla_config, NULL);
4017 if (ret != I40E_SUCCESS) {
4018 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
4019 "configuration %u", hw->aq.asq_last_status);
4023 /* store and print out BW info */
4024 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4025 vsi->bw_info.bw_max = bw_config.max_bw;
4026 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4027 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4028 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4029 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4031 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4032 vsi->bw_info.bw_ets_share_credits[i] =
4033 ets_sla_config.share_credits[i];
4034 vsi->bw_info.bw_ets_credits[i] =
4035 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4036 /* 4 bits per TC, 4th bit is reserved */
4037 vsi->bw_info.bw_ets_max[i] =
4038 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4039 RTE_LEN2MASK(3, uint8_t));
4040 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4041 vsi->bw_info.bw_ets_share_credits[i]);
4042 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4043 vsi->bw_info.bw_ets_credits[i]);
4044 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4045 vsi->bw_info.bw_ets_max[i]);
4048 return I40E_SUCCESS;
4051 /* i40e_enable_pf_lb
4052 * @pf: pointer to the pf structure
4054 * allow loopback on pf
4057 i40e_enable_pf_lb(struct i40e_pf *pf)
4059 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4060 struct i40e_vsi_context ctxt;
4063 /* Use the FW API if FW >= v5.0 */
4064 if (hw->aq.fw_maj_ver < 5) {
4065 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4069 memset(&ctxt, 0, sizeof(ctxt));
4070 ctxt.seid = pf->main_vsi_seid;
4071 ctxt.pf_num = hw->pf_id;
4072 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4074 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4075 ret, hw->aq.asq_last_status);
4078 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4079 ctxt.info.valid_sections =
4080 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4081 ctxt.info.switch_id |=
4082 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4084 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4086 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
4087 hw->aq.asq_last_status);
4092 i40e_vsi_setup(struct i40e_pf *pf,
4093 enum i40e_vsi_type type,
4094 struct i40e_vsi *uplink_vsi,
4095 uint16_t user_param)
4097 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4098 struct i40e_vsi *vsi;
4099 struct i40e_mac_filter_info filter;
4101 struct i40e_vsi_context ctxt;
4102 struct ether_addr broadcast =
4103 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4105 if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
4106 PMD_DRV_LOG(ERR, "VSI setup failed, "
4107 "VSI link shouldn't be NULL");
4111 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4112 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
4113 "uplink VSI should be NULL");
4117 /* If uplink vsi didn't setup VEB, create one first */
4118 if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
4119 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4121 if (NULL == uplink_vsi->veb) {
4122 PMD_DRV_LOG(ERR, "VEB setup failed");
4125 /* set ALLOWLOOPBACk on pf, when veb is created */
4126 i40e_enable_pf_lb(pf);
4129 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4131 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4134 TAILQ_INIT(&vsi->mac_list);
4136 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4137 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4138 vsi->parent_vsi = uplink_vsi;
4139 vsi->user_param = user_param;
4140 /* Allocate queues */
4141 switch (vsi->type) {
4142 case I40E_VSI_MAIN :
4143 vsi->nb_qps = pf->lan_nb_qps;
4145 case I40E_VSI_SRIOV :
4146 vsi->nb_qps = pf->vf_nb_qps;
4148 case I40E_VSI_VMDQ2:
4149 vsi->nb_qps = pf->vmdq_nb_qps;
4152 vsi->nb_qps = pf->fdir_nb_qps;
4158 * The filter status descriptor is reported in rx queue 0,
4159 * while the tx queue for fdir filter programming has no
4160 * such constraints, can be non-zero queues.
4161 * To simplify it, choose FDIR vsi use queue 0 pair.
4162 * To make sure it will use queue 0 pair, queue allocation
4163 * need be done before this function is called
4165 if (type != I40E_VSI_FDIR) {
4166 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4168 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4172 vsi->base_queue = ret;
4174 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4176 /* VF has MSIX interrupt in VF range, don't allocate here */
4177 if (type == I40E_VSI_MAIN) {
4178 ret = i40e_res_pool_alloc(&pf->msix_pool,
4179 RTE_MIN(vsi->nb_qps,
4180 RTE_MAX_RXTX_INTR_VEC_ID));
4182 PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4184 goto fail_queue_alloc;
4186 vsi->msix_intr = ret;
4187 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4188 } else if (type != I40E_VSI_SRIOV) {
4189 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4191 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4192 goto fail_queue_alloc;
4194 vsi->msix_intr = ret;
4202 if (type == I40E_VSI_MAIN) {
4203 /* For main VSI, no need to add since it's default one */
4204 vsi->uplink_seid = pf->mac_seid;
4205 vsi->seid = pf->main_vsi_seid;
4206 /* Bind queues with specific MSIX interrupt */
4208 * Needs 2 interrupt at least, one for misc cause which will
4209 * enabled from OS side, Another for queues binding the
4210 * interrupt from device side only.
4213 /* Get default VSI parameters from hardware */
4214 memset(&ctxt, 0, sizeof(ctxt));
4215 ctxt.seid = vsi->seid;
4216 ctxt.pf_num = hw->pf_id;
4217 ctxt.uplink_seid = vsi->uplink_seid;
4219 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4220 if (ret != I40E_SUCCESS) {
4221 PMD_DRV_LOG(ERR, "Failed to get VSI params");
4222 goto fail_msix_alloc;
4224 (void)rte_memcpy(&vsi->info, &ctxt.info,
4225 sizeof(struct i40e_aqc_vsi_properties_data));
4226 vsi->vsi_id = ctxt.vsi_number;
4227 vsi->info.valid_sections = 0;
4229 /* Configure tc, enabled TC0 only */
4230 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4232 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4233 goto fail_msix_alloc;
4236 /* TC, queue mapping */
4237 memset(&ctxt, 0, sizeof(ctxt));
4238 vsi->info.valid_sections |=
4239 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4240 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4241 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4242 (void)rte_memcpy(&ctxt.info, &vsi->info,
4243 sizeof(struct i40e_aqc_vsi_properties_data));
4244 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4245 I40E_DEFAULT_TCMAP);
4246 if (ret != I40E_SUCCESS) {
4247 PMD_DRV_LOG(ERR, "Failed to configure "
4248 "TC queue mapping");
4249 goto fail_msix_alloc;
4251 ctxt.seid = vsi->seid;
4252 ctxt.pf_num = hw->pf_id;
4253 ctxt.uplink_seid = vsi->uplink_seid;
4256 /* Update VSI parameters */
4257 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4258 if (ret != I40E_SUCCESS) {
4259 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4260 goto fail_msix_alloc;
4263 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4264 sizeof(vsi->info.tc_mapping));
4265 (void)rte_memcpy(&vsi->info.queue_mapping,
4266 &ctxt.info.queue_mapping,
4267 sizeof(vsi->info.queue_mapping));
4268 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4269 vsi->info.valid_sections = 0;
4271 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4275 * Updating default filter settings are necessary to prevent
4276 * reception of tagged packets.
4277 * Some old firmware configurations load a default macvlan
4278 * filter which accepts both tagged and untagged packets.
4279 * The updating is to use a normal filter instead if needed.
4280 * For NVM 4.2.2 or after, the updating is not needed anymore.
4281 * The firmware with correct configurations load the default
4282 * macvlan filter which is expected and cannot be removed.
4284 i40e_update_default_filter_setting(vsi);
4285 i40e_config_qinq(hw, vsi);
4286 } else if (type == I40E_VSI_SRIOV) {
4287 memset(&ctxt, 0, sizeof(ctxt));
4289 * For other VSI, the uplink_seid equals to uplink VSI's
4290 * uplink_seid since they share same VEB
4292 vsi->uplink_seid = uplink_vsi->uplink_seid;
4293 ctxt.pf_num = hw->pf_id;
4294 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4295 ctxt.uplink_seid = vsi->uplink_seid;
4296 ctxt.connection_type = 0x1;
4297 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4299 /* Use the VEB configuration if FW >= v5.0 */
4300 if (hw->aq.fw_maj_ver >= 5) {
4301 /* Configure switch ID */
4302 ctxt.info.valid_sections |=
4303 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4304 ctxt.info.switch_id =
4305 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4308 /* Configure port/vlan */
4309 ctxt.info.valid_sections |=
4310 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4311 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4312 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4313 I40E_DEFAULT_TCMAP);
4314 if (ret != I40E_SUCCESS) {
4315 PMD_DRV_LOG(ERR, "Failed to configure "
4316 "TC queue mapping");
4317 goto fail_msix_alloc;
4319 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4320 ctxt.info.valid_sections |=
4321 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4323 * Since VSI is not created yet, only configure parameter,
4324 * will add vsi below.
4327 i40e_config_qinq(hw, vsi);
4328 } else if (type == I40E_VSI_VMDQ2) {
4329 memset(&ctxt, 0, sizeof(ctxt));
4331 * For other VSI, the uplink_seid equals to uplink VSI's
4332 * uplink_seid since they share same VEB
4334 vsi->uplink_seid = uplink_vsi->uplink_seid;
4335 ctxt.pf_num = hw->pf_id;
4337 ctxt.uplink_seid = vsi->uplink_seid;
4338 ctxt.connection_type = 0x1;
4339 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4341 ctxt.info.valid_sections |=
4342 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4343 /* user_param carries flag to enable loop back */
4345 ctxt.info.switch_id =
4346 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4347 ctxt.info.switch_id |=
4348 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4351 /* Configure port/vlan */
4352 ctxt.info.valid_sections |=
4353 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4354 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4355 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4356 I40E_DEFAULT_TCMAP);
4357 if (ret != I40E_SUCCESS) {
4358 PMD_DRV_LOG(ERR, "Failed to configure "
4359 "TC queue mapping");
4360 goto fail_msix_alloc;
4362 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4363 ctxt.info.valid_sections |=
4364 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4365 } else if (type == I40E_VSI_FDIR) {
4366 memset(&ctxt, 0, sizeof(ctxt));
4367 vsi->uplink_seid = uplink_vsi->uplink_seid;
4368 ctxt.pf_num = hw->pf_id;
4370 ctxt.uplink_seid = vsi->uplink_seid;
4371 ctxt.connection_type = 0x1; /* regular data port */
4372 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4373 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4374 I40E_DEFAULT_TCMAP);
4375 if (ret != I40E_SUCCESS) {
4376 PMD_DRV_LOG(ERR, "Failed to configure "
4377 "TC queue mapping.");
4378 goto fail_msix_alloc;
4380 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4381 ctxt.info.valid_sections |=
4382 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4384 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4385 goto fail_msix_alloc;
4388 if (vsi->type != I40E_VSI_MAIN) {
4389 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4390 if (ret != I40E_SUCCESS) {
4391 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4392 hw->aq.asq_last_status);
4393 goto fail_msix_alloc;
4395 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4396 vsi->info.valid_sections = 0;
4397 vsi->seid = ctxt.seid;
4398 vsi->vsi_id = ctxt.vsi_number;
4399 vsi->sib_vsi_list.vsi = vsi;
4400 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4401 &vsi->sib_vsi_list, list);
4404 /* MAC/VLAN configuration */
4405 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4406 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4408 ret = i40e_vsi_add_mac(vsi, &filter);
4409 if (ret != I40E_SUCCESS) {
4410 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4411 goto fail_msix_alloc;
4414 /* Get VSI BW information */
4415 i40e_vsi_get_bw_config(vsi);
4418 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4420 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4426 /* Configure vlan filter on or off */
4428 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4431 struct i40e_mac_filter *f;
4432 struct i40e_mac_filter_info *mac_filter;
4433 enum rte_mac_filter_type desired_filter;
4434 int ret = I40E_SUCCESS;
4437 /* Filter to match MAC and VLAN */
4438 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4440 /* Filter to match only MAC */
4441 desired_filter = RTE_MAC_PERFECT_MATCH;
4446 mac_filter = rte_zmalloc("mac_filter_info_data",
4447 num * sizeof(*mac_filter), 0);
4448 if (mac_filter == NULL) {
4449 PMD_DRV_LOG(ERR, "failed to allocate memory");
4450 return I40E_ERR_NO_MEMORY;
4455 /* Remove all existing mac */
4456 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4457 mac_filter[i] = f->mac_info;
4458 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4460 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4461 on ? "enable" : "disable");
4467 /* Override with new filter */
4468 for (i = 0; i < num; i++) {
4469 mac_filter[i].filter_type = desired_filter;
4470 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4472 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4473 on ? "enable" : "disable");
4479 rte_free(mac_filter);
4483 /* Configure vlan stripping on or off */
4485 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4487 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4488 struct i40e_vsi_context ctxt;
4490 int ret = I40E_SUCCESS;
4492 /* Check if it has been already on or off */
4493 if (vsi->info.valid_sections &
4494 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4496 if ((vsi->info.port_vlan_flags &
4497 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4498 return 0; /* already on */
4500 if ((vsi->info.port_vlan_flags &
4501 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4502 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4503 return 0; /* already off */
4508 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4510 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4511 vsi->info.valid_sections =
4512 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4513 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4514 vsi->info.port_vlan_flags |= vlan_flags;
4515 ctxt.seid = vsi->seid;
4516 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4517 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4519 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4520 on ? "enable" : "disable");
4526 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4528 struct rte_eth_dev_data *data = dev->data;
4532 /* Apply vlan offload setting */
4533 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
4534 i40e_vlan_offload_set(dev, mask);
4536 /* Apply double-vlan setting, not implemented yet */
4538 /* Apply pvid setting */
4539 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4540 data->dev_conf.txmode.hw_vlan_insert_pvid);
4542 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4548 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4550 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4552 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4556 i40e_update_flow_control(struct i40e_hw *hw)
4558 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4559 struct i40e_link_status link_status;
4560 uint32_t rxfc = 0, txfc = 0, reg;
4564 memset(&link_status, 0, sizeof(link_status));
4565 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4566 if (ret != I40E_SUCCESS) {
4567 PMD_DRV_LOG(ERR, "Failed to get link status information");
4568 goto write_reg; /* Disable flow control */
4571 an_info = hw->phy.link_info.an_info;
4572 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4573 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4574 ret = I40E_ERR_NOT_READY;
4575 goto write_reg; /* Disable flow control */
4578 * If link auto negotiation is enabled, flow control needs to
4579 * be configured according to it
4581 switch (an_info & I40E_LINK_PAUSE_RXTX) {
4582 case I40E_LINK_PAUSE_RXTX:
4585 hw->fc.current_mode = I40E_FC_FULL;
4587 case I40E_AQ_LINK_PAUSE_RX:
4589 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4591 case I40E_AQ_LINK_PAUSE_TX:
4593 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4596 hw->fc.current_mode = I40E_FC_NONE;
4601 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4602 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4603 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4604 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4605 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4606 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4613 i40e_pf_setup(struct i40e_pf *pf)
4615 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4616 struct i40e_filter_control_settings settings;
4617 struct i40e_vsi *vsi;
4620 /* Clear all stats counters */
4621 pf->offset_loaded = FALSE;
4622 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4623 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4625 ret = i40e_pf_get_switch_config(pf);
4626 if (ret != I40E_SUCCESS) {
4627 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4630 if (pf->flags & I40E_FLAG_FDIR) {
4631 /* make queue allocated first, let FDIR use queue pair 0*/
4632 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4633 if (ret != I40E_FDIR_QUEUE_ID) {
4634 PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4636 pf->flags &= ~I40E_FLAG_FDIR;
4639 /* main VSI setup */
4640 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4642 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4643 return I40E_ERR_NOT_READY;
4647 /* Configure filter control */
4648 memset(&settings, 0, sizeof(settings));
4649 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4650 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4651 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4652 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4654 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4655 hw->func_caps.rss_table_size);
4656 return I40E_ERR_PARAM;
4658 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4659 "size: %u\n", hw->func_caps.rss_table_size);
4660 pf->hash_lut_size = hw->func_caps.rss_table_size;
4662 /* Enable ethtype and macvlan filters */
4663 settings.enable_ethtype = TRUE;
4664 settings.enable_macvlan = TRUE;
4665 ret = i40e_set_filter_control(hw, &settings);
4667 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4670 /* Update flow control according to the auto negotiation */
4671 i40e_update_flow_control(hw);
4673 return I40E_SUCCESS;
4677 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4683 * Set or clear TX Queue Disable flags,
4684 * which is required by hardware.
4686 i40e_pre_tx_queue_cfg(hw, q_idx, on);
4687 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4689 /* Wait until the request is finished */
4690 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4691 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4692 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4693 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4694 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4700 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4701 return I40E_SUCCESS; /* already on, skip next steps */
4703 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4704 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4706 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4707 return I40E_SUCCESS; /* already off, skip next steps */
4708 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4710 /* Write the register */
4711 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4712 /* Check the result */
4713 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4714 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4715 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4717 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4718 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
4721 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4722 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4726 /* Check if it is timeout */
4727 if (j >= I40E_CHK_Q_ENA_COUNT) {
4728 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
4729 (on ? "enable" : "disable"), q_idx);
4730 return I40E_ERR_TIMEOUT;
4733 return I40E_SUCCESS;
4736 /* Swith on or off the tx queues */
4738 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
4740 struct rte_eth_dev_data *dev_data = pf->dev_data;
4741 struct i40e_tx_queue *txq;
4742 struct rte_eth_dev *dev = pf->adapter->eth_dev;
4746 for (i = 0; i < dev_data->nb_tx_queues; i++) {
4747 txq = dev_data->tx_queues[i];
4748 /* Don't operate the queue if not configured or
4749 * if starting only per queue */
4750 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
4753 ret = i40e_dev_tx_queue_start(dev, i);
4755 ret = i40e_dev_tx_queue_stop(dev, i);
4756 if ( ret != I40E_SUCCESS)
4760 return I40E_SUCCESS;
4764 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4769 /* Wait until the request is finished */
4770 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4771 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4772 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4773 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4774 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
4779 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
4780 return I40E_SUCCESS; /* Already on, skip next steps */
4781 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
4783 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4784 return I40E_SUCCESS; /* Already off, skip next steps */
4785 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
4788 /* Write the register */
4789 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
4790 /* Check the result */
4791 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4792 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4793 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4795 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4796 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
4799 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4800 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4805 /* Check if it is timeout */
4806 if (j >= I40E_CHK_Q_ENA_COUNT) {
4807 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
4808 (on ? "enable" : "disable"), q_idx);
4809 return I40E_ERR_TIMEOUT;
4812 return I40E_SUCCESS;
4814 /* Switch on or off the rx queues */
4816 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
4818 struct rte_eth_dev_data *dev_data = pf->dev_data;
4819 struct i40e_rx_queue *rxq;
4820 struct rte_eth_dev *dev = pf->adapter->eth_dev;
4824 for (i = 0; i < dev_data->nb_rx_queues; i++) {
4825 rxq = dev_data->rx_queues[i];
4826 /* Don't operate the queue if not configured or
4827 * if starting only per queue */
4828 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
4831 ret = i40e_dev_rx_queue_start(dev, i);
4833 ret = i40e_dev_rx_queue_stop(dev, i);
4834 if (ret != I40E_SUCCESS)
4838 return I40E_SUCCESS;
4841 /* Switch on or off all the rx/tx queues */
4843 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
4848 /* enable rx queues before enabling tx queues */
4849 ret = i40e_dev_switch_rx_queues(pf, on);
4851 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
4854 ret = i40e_dev_switch_tx_queues(pf, on);
4856 /* Stop tx queues before stopping rx queues */
4857 ret = i40e_dev_switch_tx_queues(pf, on);
4859 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
4862 ret = i40e_dev_switch_rx_queues(pf, on);
4868 /* Initialize VSI for TX */
4870 i40e_dev_tx_init(struct i40e_pf *pf)
4872 struct rte_eth_dev_data *data = pf->dev_data;
4874 uint32_t ret = I40E_SUCCESS;
4875 struct i40e_tx_queue *txq;
4877 for (i = 0; i < data->nb_tx_queues; i++) {
4878 txq = data->tx_queues[i];
4879 if (!txq || !txq->q_set)
4881 ret = i40e_tx_queue_init(txq);
4882 if (ret != I40E_SUCCESS)
4885 if (ret == I40E_SUCCESS)
4886 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
4892 /* Initialize VSI for RX */
4894 i40e_dev_rx_init(struct i40e_pf *pf)
4896 struct rte_eth_dev_data *data = pf->dev_data;
4897 int ret = I40E_SUCCESS;
4899 struct i40e_rx_queue *rxq;
4901 i40e_pf_config_mq_rx(pf);
4902 for (i = 0; i < data->nb_rx_queues; i++) {
4903 rxq = data->rx_queues[i];
4904 if (!rxq || !rxq->q_set)
4907 ret = i40e_rx_queue_init(rxq);
4908 if (ret != I40E_SUCCESS) {
4909 PMD_DRV_LOG(ERR, "Failed to do RX queue "
4914 if (ret == I40E_SUCCESS)
4915 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
4922 i40e_dev_rxtx_init(struct i40e_pf *pf)
4926 err = i40e_dev_tx_init(pf);
4928 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
4931 err = i40e_dev_rx_init(pf);
4933 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
4941 i40e_vmdq_setup(struct rte_eth_dev *dev)
4943 struct rte_eth_conf *conf = &dev->data->dev_conf;
4944 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4945 int i, err, conf_vsis, j, loop;
4946 struct i40e_vsi *vsi;
4947 struct i40e_vmdq_info *vmdq_info;
4948 struct rte_eth_vmdq_rx_conf *vmdq_conf;
4949 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4952 * Disable interrupt to avoid message from VF. Furthermore, it will
4953 * avoid race condition in VSI creation/destroy.
4955 i40e_pf_disable_irq0(hw);
4957 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
4958 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
4962 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
4963 if (conf_vsis > pf->max_nb_vmdq_vsi) {
4964 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
4965 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
4966 pf->max_nb_vmdq_vsi);
4970 if (pf->vmdq != NULL) {
4971 PMD_INIT_LOG(INFO, "VMDQ already configured");
4975 pf->vmdq = rte_zmalloc("vmdq_info_struct",
4976 sizeof(*vmdq_info) * conf_vsis, 0);
4978 if (pf->vmdq == NULL) {
4979 PMD_INIT_LOG(ERR, "Failed to allocate memory");
4983 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
4985 /* Create VMDQ VSI */
4986 for (i = 0; i < conf_vsis; i++) {
4987 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
4988 vmdq_conf->enable_loop_back);
4990 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
4994 vmdq_info = &pf->vmdq[i];
4996 vmdq_info->vsi = vsi;
4998 pf->nb_cfg_vmdq_vsi = conf_vsis;
5000 /* Configure Vlan */
5001 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5002 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5003 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5004 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5005 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5006 vmdq_conf->pool_map[i].vlan_id, j);
5008 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5009 vmdq_conf->pool_map[i].vlan_id);
5011 PMD_INIT_LOG(ERR, "Failed to add vlan");
5019 i40e_pf_enable_irq0(hw);
5024 for (i = 0; i < conf_vsis; i++)
5025 if (pf->vmdq[i].vsi == NULL)
5028 i40e_vsi_release(pf->vmdq[i].vsi);
5032 i40e_pf_enable_irq0(hw);
5037 i40e_stat_update_32(struct i40e_hw *hw,
5045 new_data = (uint64_t)I40E_READ_REG(hw, reg);
5049 if (new_data >= *offset)
5050 *stat = (uint64_t)(new_data - *offset);
5052 *stat = (uint64_t)((new_data +
5053 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5057 i40e_stat_update_48(struct i40e_hw *hw,
5066 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5067 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5068 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5073 if (new_data >= *offset)
5074 *stat = new_data - *offset;
5076 *stat = (uint64_t)((new_data +
5077 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5079 *stat &= I40E_48_BIT_MASK;
5084 i40e_pf_disable_irq0(struct i40e_hw *hw)
5086 /* Disable all interrupt types */
5087 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5088 I40E_WRITE_FLUSH(hw);
5093 i40e_pf_enable_irq0(struct i40e_hw *hw)
5095 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5096 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5097 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5098 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5099 I40E_WRITE_FLUSH(hw);
5103 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5105 /* read pending request and disable first */
5106 i40e_pf_disable_irq0(hw);
5107 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5108 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5109 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5112 /* Link no queues with irq0 */
5113 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5114 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5118 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5120 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5121 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5124 uint32_t index, offset, val;
5129 * Try to find which VF trigger a reset, use absolute VF id to access
5130 * since the reg is global register.
5132 for (i = 0; i < pf->vf_num; i++) {
5133 abs_vf_id = hw->func_caps.vf_base_id + i;
5134 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5135 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5136 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5137 /* VFR event occured */
5138 if (val & (0x1 << offset)) {
5141 /* Clear the event first */
5142 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5144 PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5146 * Only notify a VF reset event occured,
5147 * don't trigger another SW reset
5149 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5150 if (ret != I40E_SUCCESS)
5151 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5157 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5159 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5160 struct i40e_arq_event_info info;
5161 uint16_t pending, opcode;
5164 info.buf_len = I40E_AQ_BUF_SZ;
5165 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5166 if (!info.msg_buf) {
5167 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5173 ret = i40e_clean_arq_element(hw, &info, &pending);
5175 if (ret != I40E_SUCCESS) {
5176 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5177 "aq_err: %u", hw->aq.asq_last_status);
5180 opcode = rte_le_to_cpu_16(info.desc.opcode);
5183 case i40e_aqc_opc_send_msg_to_pf:
5184 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5185 i40e_pf_host_handle_vf_msg(dev,
5186 rte_le_to_cpu_16(info.desc.retval),
5187 rte_le_to_cpu_32(info.desc.cookie_high),
5188 rte_le_to_cpu_32(info.desc.cookie_low),
5193 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5198 rte_free(info.msg_buf);
5202 * Interrupt handler is registered as the alarm callback for handling LSC
5203 * interrupt in a definite of time, in order to wait the NIC into a stable
5204 * state. Currently it waits 1 sec in i40e for the link up interrupt, and
5205 * no need for link down interrupt.
5208 i40e_dev_interrupt_delayed_handler(void *param)
5210 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5211 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5214 /* read interrupt causes again */
5215 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5217 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5218 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5219 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
5220 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5221 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
5222 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5223 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
5224 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5225 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
5226 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5227 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
5229 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5230 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
5231 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5232 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
5233 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5235 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5236 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
5237 i40e_dev_handle_vfr_event(dev);
5239 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5240 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
5241 i40e_dev_handle_aq_msg(dev);
5244 /* handle the link up interrupt in an alarm callback */
5245 i40e_dev_link_update(dev, 0);
5246 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
5248 i40e_pf_enable_irq0(hw);
5249 rte_intr_enable(&(dev->pci_dev->intr_handle));
5253 * Interrupt handler triggered by NIC for handling
5254 * specific interrupt.
5257 * Pointer to interrupt handle.
5259 * The address of parameter (struct rte_eth_dev *) regsitered before.
5265 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
5268 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5269 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5272 /* Disable interrupt */
5273 i40e_pf_disable_irq0(hw);
5275 /* read out interrupt causes */
5276 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5278 /* No interrupt event indicated */
5279 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5280 PMD_DRV_LOG(INFO, "No interrupt event");
5283 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5284 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5285 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5286 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5287 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5288 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5289 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5290 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5291 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5292 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5293 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5294 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5295 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5296 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5297 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5298 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5300 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5301 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5302 i40e_dev_handle_vfr_event(dev);
5304 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5305 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5306 i40e_dev_handle_aq_msg(dev);
5309 /* Link Status Change interrupt */
5310 if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
5311 #define I40E_US_PER_SECOND 1000000
5312 struct rte_eth_link link;
5314 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
5315 memset(&link, 0, sizeof(link));
5316 rte_i40e_dev_atomic_read_link_status(dev, &link);
5317 i40e_dev_link_update(dev, 0);
5320 * For link up interrupt, it needs to wait 1 second to let the
5321 * hardware be a stable state. Otherwise several consecutive
5322 * interrupts can be observed.
5323 * For link down interrupt, no need to wait.
5325 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
5326 i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
5329 _rte_eth_dev_callback_process(dev,
5330 RTE_ETH_EVENT_INTR_LSC);
5334 /* Enable interrupt */
5335 i40e_pf_enable_irq0(hw);
5336 rte_intr_enable(&(dev->pci_dev->intr_handle));
5340 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5341 struct i40e_macvlan_filter *filter,
5344 int ele_num, ele_buff_size;
5345 int num, actual_num, i;
5347 int ret = I40E_SUCCESS;
5348 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5349 struct i40e_aqc_add_macvlan_element_data *req_list;
5351 if (filter == NULL || total == 0)
5352 return I40E_ERR_PARAM;
5353 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5354 ele_buff_size = hw->aq.asq_buf_size;
5356 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5357 if (req_list == NULL) {
5358 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5359 return I40E_ERR_NO_MEMORY;
5364 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5365 memset(req_list, 0, ele_buff_size);
5367 for (i = 0; i < actual_num; i++) {
5368 (void)rte_memcpy(req_list[i].mac_addr,
5369 &filter[num + i].macaddr, ETH_ADDR_LEN);
5370 req_list[i].vlan_tag =
5371 rte_cpu_to_le_16(filter[num + i].vlan_id);
5373 switch (filter[num + i].filter_type) {
5374 case RTE_MAC_PERFECT_MATCH:
5375 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5376 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5378 case RTE_MACVLAN_PERFECT_MATCH:
5379 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5381 case RTE_MAC_HASH_MATCH:
5382 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5383 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5385 case RTE_MACVLAN_HASH_MATCH:
5386 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5389 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5390 ret = I40E_ERR_PARAM;
5394 req_list[i].queue_number = 0;
5396 req_list[i].flags = rte_cpu_to_le_16(flags);
5399 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5401 if (ret != I40E_SUCCESS) {
5402 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5406 } while (num < total);
5414 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5415 struct i40e_macvlan_filter *filter,
5418 int ele_num, ele_buff_size;
5419 int num, actual_num, i;
5421 int ret = I40E_SUCCESS;
5422 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5423 struct i40e_aqc_remove_macvlan_element_data *req_list;
5425 if (filter == NULL || total == 0)
5426 return I40E_ERR_PARAM;
5428 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5429 ele_buff_size = hw->aq.asq_buf_size;
5431 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5432 if (req_list == NULL) {
5433 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5434 return I40E_ERR_NO_MEMORY;
5439 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5440 memset(req_list, 0, ele_buff_size);
5442 for (i = 0; i < actual_num; i++) {
5443 (void)rte_memcpy(req_list[i].mac_addr,
5444 &filter[num + i].macaddr, ETH_ADDR_LEN);
5445 req_list[i].vlan_tag =
5446 rte_cpu_to_le_16(filter[num + i].vlan_id);
5448 switch (filter[num + i].filter_type) {
5449 case RTE_MAC_PERFECT_MATCH:
5450 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5451 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5453 case RTE_MACVLAN_PERFECT_MATCH:
5454 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5456 case RTE_MAC_HASH_MATCH:
5457 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5458 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5460 case RTE_MACVLAN_HASH_MATCH:
5461 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5464 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5465 ret = I40E_ERR_PARAM;
5468 req_list[i].flags = rte_cpu_to_le_16(flags);
5471 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5473 if (ret != I40E_SUCCESS) {
5474 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5478 } while (num < total);
5485 /* Find out specific MAC filter */
5486 static struct i40e_mac_filter *
5487 i40e_find_mac_filter(struct i40e_vsi *vsi,
5488 struct ether_addr *macaddr)
5490 struct i40e_mac_filter *f;
5492 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5493 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5501 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5504 uint32_t vid_idx, vid_bit;
5506 if (vlan_id > ETH_VLAN_ID_MAX)
5509 vid_idx = I40E_VFTA_IDX(vlan_id);
5510 vid_bit = I40E_VFTA_BIT(vlan_id);
5512 if (vsi->vfta[vid_idx] & vid_bit)
5519 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5520 uint16_t vlan_id, bool on)
5522 uint32_t vid_idx, vid_bit;
5524 if (vlan_id > ETH_VLAN_ID_MAX)
5527 vid_idx = I40E_VFTA_IDX(vlan_id);
5528 vid_bit = I40E_VFTA_BIT(vlan_id);
5531 vsi->vfta[vid_idx] |= vid_bit;
5533 vsi->vfta[vid_idx] &= ~vid_bit;
5537 * Find all vlan options for specific mac addr,
5538 * return with actual vlan found.
5541 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5542 struct i40e_macvlan_filter *mv_f,
5543 int num, struct ether_addr *addr)
5549 * Not to use i40e_find_vlan_filter to decrease the loop time,
5550 * although the code looks complex.
5552 if (num < vsi->vlan_num)
5553 return I40E_ERR_PARAM;
5556 for (j = 0; j < I40E_VFTA_SIZE; j++) {
5558 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5559 if (vsi->vfta[j] & (1 << k)) {
5561 PMD_DRV_LOG(ERR, "vlan number "
5563 return I40E_ERR_PARAM;
5565 (void)rte_memcpy(&mv_f[i].macaddr,
5566 addr, ETH_ADDR_LEN);
5568 j * I40E_UINT32_BIT_SIZE + k;
5574 return I40E_SUCCESS;
5578 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5579 struct i40e_macvlan_filter *mv_f,
5584 struct i40e_mac_filter *f;
5586 if (num < vsi->mac_num)
5587 return I40E_ERR_PARAM;
5589 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5591 PMD_DRV_LOG(ERR, "buffer number not match");
5592 return I40E_ERR_PARAM;
5594 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5596 mv_f[i].vlan_id = vlan;
5597 mv_f[i].filter_type = f->mac_info.filter_type;
5601 return I40E_SUCCESS;
5605 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5608 struct i40e_mac_filter *f;
5609 struct i40e_macvlan_filter *mv_f;
5610 int ret = I40E_SUCCESS;
5612 if (vsi == NULL || vsi->mac_num == 0)
5613 return I40E_ERR_PARAM;
5615 /* Case that no vlan is set */
5616 if (vsi->vlan_num == 0)
5619 num = vsi->mac_num * vsi->vlan_num;
5621 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5623 PMD_DRV_LOG(ERR, "failed to allocate memory");
5624 return I40E_ERR_NO_MEMORY;
5628 if (vsi->vlan_num == 0) {
5629 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5630 (void)rte_memcpy(&mv_f[i].macaddr,
5631 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5632 mv_f[i].vlan_id = 0;
5636 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5637 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5638 vsi->vlan_num, &f->mac_info.mac_addr);
5639 if (ret != I40E_SUCCESS)
5645 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5653 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5655 struct i40e_macvlan_filter *mv_f;
5657 int ret = I40E_SUCCESS;
5659 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5660 return I40E_ERR_PARAM;
5662 /* If it's already set, just return */
5663 if (i40e_find_vlan_filter(vsi,vlan))
5664 return I40E_SUCCESS;
5666 mac_num = vsi->mac_num;
5669 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5670 return I40E_ERR_PARAM;
5673 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5676 PMD_DRV_LOG(ERR, "failed to allocate memory");
5677 return I40E_ERR_NO_MEMORY;
5680 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5682 if (ret != I40E_SUCCESS)
5685 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5687 if (ret != I40E_SUCCESS)
5690 i40e_set_vlan_filter(vsi, vlan, 1);
5700 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5702 struct i40e_macvlan_filter *mv_f;
5704 int ret = I40E_SUCCESS;
5707 * Vlan 0 is the generic filter for untagged packets
5708 * and can't be removed.
5710 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5711 return I40E_ERR_PARAM;
5713 /* If can't find it, just return */
5714 if (!i40e_find_vlan_filter(vsi, vlan))
5715 return I40E_ERR_PARAM;
5717 mac_num = vsi->mac_num;
5720 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5721 return I40E_ERR_PARAM;
5724 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5727 PMD_DRV_LOG(ERR, "failed to allocate memory");
5728 return I40E_ERR_NO_MEMORY;
5731 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5733 if (ret != I40E_SUCCESS)
5736 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5738 if (ret != I40E_SUCCESS)
5741 /* This is last vlan to remove, replace all mac filter with vlan 0 */
5742 if (vsi->vlan_num == 1) {
5743 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5744 if (ret != I40E_SUCCESS)
5747 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5748 if (ret != I40E_SUCCESS)
5752 i40e_set_vlan_filter(vsi, vlan, 0);
5762 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
5764 struct i40e_mac_filter *f;
5765 struct i40e_macvlan_filter *mv_f;
5766 int i, vlan_num = 0;
5767 int ret = I40E_SUCCESS;
5769 /* If it's add and we've config it, return */
5770 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
5772 return I40E_SUCCESS;
5773 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
5774 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
5777 * If vlan_num is 0, that's the first time to add mac,
5778 * set mask for vlan_id 0.
5780 if (vsi->vlan_num == 0) {
5781 i40e_set_vlan_filter(vsi, 0, 1);
5784 vlan_num = vsi->vlan_num;
5785 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
5786 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
5789 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5791 PMD_DRV_LOG(ERR, "failed to allocate memory");
5792 return I40E_ERR_NO_MEMORY;
5795 for (i = 0; i < vlan_num; i++) {
5796 mv_f[i].filter_type = mac_filter->filter_type;
5797 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
5801 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5802 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
5803 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
5804 &mac_filter->mac_addr);
5805 if (ret != I40E_SUCCESS)
5809 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
5810 if (ret != I40E_SUCCESS)
5813 /* Add the mac addr into mac list */
5814 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5816 PMD_DRV_LOG(ERR, "failed to allocate memory");
5817 ret = I40E_ERR_NO_MEMORY;
5820 (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
5822 f->mac_info.filter_type = mac_filter->filter_type;
5823 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5834 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
5836 struct i40e_mac_filter *f;
5837 struct i40e_macvlan_filter *mv_f;
5839 enum rte_mac_filter_type filter_type;
5840 int ret = I40E_SUCCESS;
5842 /* Can't find it, return an error */
5843 f = i40e_find_mac_filter(vsi, addr);
5845 return I40E_ERR_PARAM;
5847 vlan_num = vsi->vlan_num;
5848 filter_type = f->mac_info.filter_type;
5849 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5850 filter_type == RTE_MACVLAN_HASH_MATCH) {
5851 if (vlan_num == 0) {
5852 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
5853 return I40E_ERR_PARAM;
5855 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
5856 filter_type == RTE_MAC_HASH_MATCH)
5859 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5861 PMD_DRV_LOG(ERR, "failed to allocate memory");
5862 return I40E_ERR_NO_MEMORY;
5865 for (i = 0; i < vlan_num; i++) {
5866 mv_f[i].filter_type = filter_type;
5867 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5870 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5871 filter_type == RTE_MACVLAN_HASH_MATCH) {
5872 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
5873 if (ret != I40E_SUCCESS)
5877 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
5878 if (ret != I40E_SUCCESS)
5881 /* Remove the mac addr into mac list */
5882 TAILQ_REMOVE(&vsi->mac_list, f, next);
5892 /* Configure hash enable flags for RSS */
5894 i40e_config_hena(uint64_t flags)
5901 if (flags & ETH_RSS_FRAG_IPV4)
5902 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
5903 if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
5904 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
5905 if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
5906 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
5907 if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
5908 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
5909 if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
5910 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
5911 if (flags & ETH_RSS_FRAG_IPV6)
5912 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
5913 if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
5914 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
5915 if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
5916 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
5917 if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
5918 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
5919 if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
5920 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
5921 if (flags & ETH_RSS_L2_PAYLOAD)
5922 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
5927 /* Parse the hash enable flags */
5929 i40e_parse_hena(uint64_t flags)
5931 uint64_t rss_hf = 0;
5935 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
5936 rss_hf |= ETH_RSS_FRAG_IPV4;
5937 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
5938 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
5939 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
5940 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
5941 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
5942 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
5943 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
5944 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
5945 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
5946 rss_hf |= ETH_RSS_FRAG_IPV6;
5947 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
5948 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
5949 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
5950 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
5951 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
5952 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
5953 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
5954 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
5955 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
5956 rss_hf |= ETH_RSS_L2_PAYLOAD;
5963 i40e_pf_disable_rss(struct i40e_pf *pf)
5965 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5968 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
5969 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
5970 hena &= ~I40E_RSS_HENA_ALL;
5971 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5972 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5973 I40E_WRITE_FLUSH(hw);
5977 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
5979 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5980 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5983 if (!key || key_len == 0) {
5984 PMD_DRV_LOG(DEBUG, "No key to be configured");
5986 } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5988 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
5992 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5993 struct i40e_aqc_get_set_rss_key_data *key_dw =
5994 (struct i40e_aqc_get_set_rss_key_data *)key;
5996 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
5998 PMD_INIT_LOG(ERR, "Failed to configure RSS key "
6001 uint32_t *hash_key = (uint32_t *)key;
6004 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6005 i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6006 I40E_WRITE_FLUSH(hw);
6013 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6015 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6016 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6019 if (!key || !key_len)
6022 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6023 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6024 (struct i40e_aqc_get_set_rss_key_data *)key);
6026 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6030 uint32_t *key_dw = (uint32_t *)key;
6033 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6034 key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6036 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6042 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6044 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6049 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6050 rss_conf->rss_key_len);
6054 rss_hf = rss_conf->rss_hf;
6055 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6056 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6057 hena &= ~I40E_RSS_HENA_ALL;
6058 hena |= i40e_config_hena(rss_hf);
6059 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6060 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6061 I40E_WRITE_FLUSH(hw);
6067 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6068 struct rte_eth_rss_conf *rss_conf)
6070 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6071 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6072 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6075 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6076 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6077 if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
6078 if (rss_hf != 0) /* Enable RSS */
6080 return 0; /* Nothing to do */
6083 if (rss_hf == 0) /* Disable RSS */
6086 return i40e_hw_rss_hash_set(pf, rss_conf);
6090 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6091 struct rte_eth_rss_conf *rss_conf)
6093 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6094 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6097 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6098 &rss_conf->rss_key_len);
6100 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6101 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6102 rss_conf->rss_hf = i40e_parse_hena(hena);
6108 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6110 switch (filter_type) {
6111 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6112 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6114 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6115 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6117 case RTE_TUNNEL_FILTER_IMAC_TENID:
6118 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6120 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6121 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6123 case ETH_TUNNEL_FILTER_IMAC:
6124 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6126 case ETH_TUNNEL_FILTER_OIP:
6127 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6129 case ETH_TUNNEL_FILTER_IIP:
6130 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6133 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6141 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6142 struct rte_eth_tunnel_filter_conf *tunnel_filter,
6147 uint8_t i, tun_type = 0;
6148 /* internal varialbe to convert ipv6 byte order */
6149 uint32_t convert_ipv6[4];
6151 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6152 struct i40e_vsi *vsi = pf->main_vsi;
6153 struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter;
6154 struct i40e_aqc_add_remove_cloud_filters_element_data *pfilter;
6156 cld_filter = rte_zmalloc("tunnel_filter",
6157 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6160 if (NULL == cld_filter) {
6161 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6164 pfilter = cld_filter;
6166 ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6167 ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6169 pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6170 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6171 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6172 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6173 rte_memcpy(&pfilter->ipaddr.v4.data,
6174 &rte_cpu_to_le_32(ipv4_addr),
6175 sizeof(pfilter->ipaddr.v4.data));
6177 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6178 for (i = 0; i < 4; i++) {
6180 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6182 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6183 sizeof(pfilter->ipaddr.v6.data));
6186 /* check tunneled type */
6187 switch (tunnel_filter->tunnel_type) {
6188 case RTE_TUNNEL_TYPE_VXLAN:
6189 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6191 case RTE_TUNNEL_TYPE_NVGRE:
6192 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6194 case RTE_TUNNEL_TYPE_IP_IN_GRE:
6195 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6198 /* Other tunnel types is not supported. */
6199 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6200 rte_free(cld_filter);
6204 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6207 rte_free(cld_filter);
6211 pfilter->flags |= rte_cpu_to_le_16(
6212 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6213 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6214 pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6215 pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6218 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6220 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6223 rte_free(cld_filter);
6228 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6232 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6233 if (pf->vxlan_ports[i] == port)
6241 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6245 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6247 idx = i40e_get_vxlan_port_idx(pf, port);
6249 /* Check if port already exists */
6251 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6255 /* Now check if there is space to add the new port */
6256 idx = i40e_get_vxlan_port_idx(pf, 0);
6258 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6259 "not adding port %d", port);
6263 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6266 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6270 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6273 /* New port: add it and mark its index in the bitmap */
6274 pf->vxlan_ports[idx] = port;
6275 pf->vxlan_bitmap |= (1 << idx);
6277 if (!(pf->flags & I40E_FLAG_VXLAN))
6278 pf->flags |= I40E_FLAG_VXLAN;
6284 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6287 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6289 if (!(pf->flags & I40E_FLAG_VXLAN)) {
6290 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6294 idx = i40e_get_vxlan_port_idx(pf, port);
6297 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6301 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6302 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6306 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6309 pf->vxlan_ports[idx] = 0;
6310 pf->vxlan_bitmap &= ~(1 << idx);
6312 if (!pf->vxlan_bitmap)
6313 pf->flags &= ~I40E_FLAG_VXLAN;
6318 /* Add UDP tunneling port */
6320 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6321 struct rte_eth_udp_tunnel *udp_tunnel)
6324 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6326 if (udp_tunnel == NULL)
6329 switch (udp_tunnel->prot_type) {
6330 case RTE_TUNNEL_TYPE_VXLAN:
6331 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6334 case RTE_TUNNEL_TYPE_GENEVE:
6335 case RTE_TUNNEL_TYPE_TEREDO:
6336 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6341 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6349 /* Remove UDP tunneling port */
6351 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6352 struct rte_eth_udp_tunnel *udp_tunnel)
6355 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6357 if (udp_tunnel == NULL)
6360 switch (udp_tunnel->prot_type) {
6361 case RTE_TUNNEL_TYPE_VXLAN:
6362 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6364 case RTE_TUNNEL_TYPE_GENEVE:
6365 case RTE_TUNNEL_TYPE_TEREDO:
6366 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6370 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6378 /* Calculate the maximum number of contiguous PF queues that are configured */
6380 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6382 struct rte_eth_dev_data *data = pf->dev_data;
6384 struct i40e_rx_queue *rxq;
6387 for (i = 0; i < pf->lan_nb_qps; i++) {
6388 rxq = data->rx_queues[i];
6389 if (rxq && rxq->q_set)
6400 i40e_pf_config_rss(struct i40e_pf *pf)
6402 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6403 struct rte_eth_rss_conf rss_conf;
6404 uint32_t i, lut = 0;
6408 * If both VMDQ and RSS enabled, not all of PF queues are configured.
6409 * It's necessary to calulate the actual PF queues that are configured.
6411 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6412 num = i40e_pf_calc_configured_queues_num(pf);
6414 num = pf->dev_data->nb_rx_queues;
6416 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6417 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6421 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6425 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6428 lut = (lut << 8) | (j & ((0x1 <<
6429 hw->func_caps.rss_table_entry_width) - 1));
6431 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6434 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6435 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6436 i40e_pf_disable_rss(pf);
6439 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6440 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6441 /* Random default keys */
6442 static uint32_t rss_key_default[] = {0x6b793944,
6443 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6444 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6445 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6447 rss_conf.rss_key = (uint8_t *)rss_key_default;
6448 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6452 return i40e_hw_rss_hash_set(pf, &rss_conf);
6456 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6457 struct rte_eth_tunnel_filter_conf *filter)
6459 if (pf == NULL || filter == NULL) {
6460 PMD_DRV_LOG(ERR, "Invalid parameter");
6464 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6465 PMD_DRV_LOG(ERR, "Invalid queue ID");
6469 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6470 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6474 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6475 (is_zero_ether_addr(&filter->outer_mac))) {
6476 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6480 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6481 (is_zero_ether_addr(&filter->inner_mac))) {
6482 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6489 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6490 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
6492 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6497 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6498 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6501 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6502 } else if (len == 4) {
6503 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6505 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6510 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6517 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6518 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6524 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6531 switch (cfg->cfg_type) {
6532 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6533 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6536 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6544 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6545 enum rte_filter_op filter_op,
6548 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6549 int ret = I40E_ERR_PARAM;
6551 switch (filter_op) {
6552 case RTE_ETH_FILTER_SET:
6553 ret = i40e_dev_global_config_set(hw,
6554 (struct rte_eth_global_cfg *)arg);
6557 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6565 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6566 enum rte_filter_op filter_op,
6569 struct rte_eth_tunnel_filter_conf *filter;
6570 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6571 int ret = I40E_SUCCESS;
6573 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6575 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6576 return I40E_ERR_PARAM;
6578 switch (filter_op) {
6579 case RTE_ETH_FILTER_NOP:
6580 if (!(pf->flags & I40E_FLAG_VXLAN))
6581 ret = I40E_NOT_SUPPORTED;
6583 case RTE_ETH_FILTER_ADD:
6584 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6586 case RTE_ETH_FILTER_DELETE:
6587 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6590 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6591 ret = I40E_ERR_PARAM;
6599 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6602 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6605 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6606 ret = i40e_pf_config_rss(pf);
6608 i40e_pf_disable_rss(pf);
6613 /* Get the symmetric hash enable configurations per port */
6615 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6617 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6619 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6622 /* Set the symmetric hash enable configurations per port */
6624 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6626 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6629 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6630 PMD_DRV_LOG(INFO, "Symmetric hash has already "
6634 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6636 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6637 PMD_DRV_LOG(INFO, "Symmetric hash has already "
6641 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6643 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
6644 I40E_WRITE_FLUSH(hw);
6648 * Get global configurations of hash function type and symmetric hash enable
6649 * per flow type (pctype). Note that global configuration means it affects all
6650 * the ports on the same NIC.
6653 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6654 struct rte_eth_hash_global_conf *g_cfg)
6656 uint32_t reg, mask = I40E_FLOW_TYPES;
6658 enum i40e_filter_pctype pctype;
6660 memset(g_cfg, 0, sizeof(*g_cfg));
6661 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6662 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6663 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6665 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6666 PMD_DRV_LOG(DEBUG, "Hash function is %s",
6667 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6669 for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6670 if (!(mask & (1UL << i)))
6672 mask &= ~(1UL << i);
6673 /* Bit set indicats the coresponding flow type is supported */
6674 g_cfg->valid_bit_mask[0] |= (1UL << i);
6675 pctype = i40e_flowtype_to_pctype(i);
6676 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
6677 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6678 g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6685 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6688 uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6690 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
6691 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
6692 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
6693 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
6699 * As i40e supports less than 32 flow types, only first 32 bits need to
6702 mask0 = g_cfg->valid_bit_mask[0];
6703 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
6705 /* Check if any unsupported flow type configured */
6706 if ((mask0 | i40e_mask) ^ i40e_mask)
6709 if (g_cfg->valid_bit_mask[i])
6717 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
6723 * Set global configurations of hash function type and symmetric hash enable
6724 * per flow type (pctype). Note any modifying global configuration will affect
6725 * all the ports on the same NIC.
6728 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
6729 struct rte_eth_hash_global_conf *g_cfg)
6734 uint32_t mask0 = g_cfg->valid_bit_mask[0];
6735 enum i40e_filter_pctype pctype;
6737 /* Check the input parameters */
6738 ret = i40e_hash_global_config_check(g_cfg);
6742 for (i = 0; mask0 && i < UINT32_BIT; i++) {
6743 if (!(mask0 & (1UL << i)))
6745 mask0 &= ~(1UL << i);
6746 pctype = i40e_flowtype_to_pctype(i);
6747 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
6748 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
6749 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
6752 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6753 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
6755 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
6756 PMD_DRV_LOG(DEBUG, "Hash function already set to "
6760 reg |= I40E_GLQF_CTL_HTOEP_MASK;
6761 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
6763 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
6764 PMD_DRV_LOG(DEBUG, "Hash function already set to "
6768 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
6770 /* Use the default, and keep it as it is */
6773 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
6776 I40E_WRITE_FLUSH(hw);
6782 * Valid input sets for hash and flow director filters per PCTYPE
6785 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
6786 enum rte_filter_type filter)
6790 static const uint64_t valid_hash_inset_table[] = {
6791 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6792 I40E_INSET_DMAC | I40E_INSET_SMAC |
6793 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6794 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
6795 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
6796 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6797 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6798 I40E_INSET_FLEX_PAYLOAD,
6799 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6800 I40E_INSET_DMAC | I40E_INSET_SMAC |
6801 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6802 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6803 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6804 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6805 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6806 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6807 I40E_INSET_FLEX_PAYLOAD,
6808 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6809 I40E_INSET_DMAC | I40E_INSET_SMAC |
6810 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6811 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6812 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6813 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6814 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6815 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6816 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
6817 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6818 I40E_INSET_DMAC | I40E_INSET_SMAC |
6819 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6820 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6821 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6822 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6823 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6824 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6825 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6826 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6827 I40E_INSET_DMAC | I40E_INSET_SMAC |
6828 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6829 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6830 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6831 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6832 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6833 I40E_INSET_FLEX_PAYLOAD,
6834 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6835 I40E_INSET_DMAC | I40E_INSET_SMAC |
6836 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6837 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6838 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6839 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
6840 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
6841 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
6842 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6843 I40E_INSET_DMAC | I40E_INSET_SMAC |
6844 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6845 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6846 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6847 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6848 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6849 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
6850 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6851 I40E_INSET_DMAC | I40E_INSET_SMAC |
6852 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6853 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6854 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6855 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6856 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6857 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
6858 I40E_INSET_FLEX_PAYLOAD,
6859 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6860 I40E_INSET_DMAC | I40E_INSET_SMAC |
6861 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6862 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6863 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6864 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6865 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6866 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
6867 I40E_INSET_FLEX_PAYLOAD,
6868 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6869 I40E_INSET_DMAC | I40E_INSET_SMAC |
6870 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6871 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6872 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6873 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6874 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
6875 I40E_INSET_FLEX_PAYLOAD,
6876 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6877 I40E_INSET_DMAC | I40E_INSET_SMAC |
6878 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6879 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
6880 I40E_INSET_FLEX_PAYLOAD,
6884 * Flow director supports only fields defined in
6885 * union rte_eth_fdir_flow.
6887 static const uint64_t valid_fdir_inset_table[] = {
6888 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6889 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6890 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6891 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
6892 I40E_INSET_IPV4_TTL,
6893 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6894 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6895 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6896 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
6897 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6898 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6899 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6900 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6901 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
6902 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6903 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6904 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6905 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6906 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
6907 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6909 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6910 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6911 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6912 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
6913 I40E_INSET_IPV4_TTL,
6914 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6915 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6916 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6917 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
6918 I40E_INSET_IPV6_HOP_LIMIT,
6919 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6920 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6921 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6922 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
6923 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6924 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6925 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6926 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6927 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
6928 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6929 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6930 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6931 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6932 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
6933 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6935 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6936 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6937 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6938 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
6939 I40E_INSET_IPV6_HOP_LIMIT,
6940 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6941 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6942 I40E_INSET_LAST_ETHER_TYPE,
6945 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6947 if (filter == RTE_ETH_FILTER_HASH)
6948 valid = valid_hash_inset_table[pctype];
6950 valid = valid_fdir_inset_table[pctype];
6956 * Validate if the input set is allowed for a specific PCTYPE
6959 i40e_validate_input_set(enum i40e_filter_pctype pctype,
6960 enum rte_filter_type filter, uint64_t inset)
6964 valid = i40e_get_valid_input_set(pctype, filter);
6965 if (inset & (~valid))
6971 /* default input set fields combination per pctype */
6973 i40e_get_default_input_set(uint16_t pctype)
6975 static const uint64_t default_inset_table[] = {
6976 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6977 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6978 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6979 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6980 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6981 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6982 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6983 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6984 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6985 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6986 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6988 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6989 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6990 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6991 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6992 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6993 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6994 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6995 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6996 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6997 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6998 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6999 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7000 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7002 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7003 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7004 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7005 I40E_INSET_LAST_ETHER_TYPE,
7008 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7011 return default_inset_table[pctype];
7015 * Parse the input set from index to logical bit masks
7018 i40e_parse_input_set(uint64_t *inset,
7019 enum i40e_filter_pctype pctype,
7020 enum rte_eth_input_set_field *field,
7026 static const struct {
7027 enum rte_eth_input_set_field field;
7029 } inset_convert_table[] = {
7030 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7031 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7032 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7033 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7034 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7035 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7036 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7037 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7038 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7039 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7040 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7041 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7042 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7043 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7044 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7045 I40E_INSET_IPV6_NEXT_HDR},
7046 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7047 I40E_INSET_IPV6_HOP_LIMIT},
7048 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7049 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7050 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7051 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7052 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7053 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7054 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7055 I40E_INSET_SCTP_VT},
7056 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7057 I40E_INSET_TUNNEL_DMAC},
7058 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7059 I40E_INSET_VLAN_TUNNEL},
7060 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7061 I40E_INSET_TUNNEL_ID},
7062 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7063 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7064 I40E_INSET_FLEX_PAYLOAD_W1},
7065 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7066 I40E_INSET_FLEX_PAYLOAD_W2},
7067 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7068 I40E_INSET_FLEX_PAYLOAD_W3},
7069 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7070 I40E_INSET_FLEX_PAYLOAD_W4},
7071 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7072 I40E_INSET_FLEX_PAYLOAD_W5},
7073 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7074 I40E_INSET_FLEX_PAYLOAD_W6},
7075 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7076 I40E_INSET_FLEX_PAYLOAD_W7},
7077 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7078 I40E_INSET_FLEX_PAYLOAD_W8},
7081 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7084 /* Only one item allowed for default or all */
7086 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7087 *inset = i40e_get_default_input_set(pctype);
7089 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7090 *inset = I40E_INSET_NONE;
7095 for (i = 0, *inset = 0; i < size; i++) {
7096 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7097 if (field[i] == inset_convert_table[j].field) {
7098 *inset |= inset_convert_table[j].inset;
7103 /* It contains unsupported input set, return immediately */
7104 if (j == RTE_DIM(inset_convert_table))
7112 * Translate the input set from bit masks to register aware bit masks
7116 i40e_translate_input_set_reg(uint64_t input)
7121 static const struct {
7125 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7126 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7127 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7128 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7129 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7130 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7131 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7132 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7133 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7134 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7135 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7136 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7137 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7138 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7139 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7140 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7141 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7142 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7143 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7144 {I40E_INSET_TUNNEL_DMAC,
7145 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7146 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7147 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7148 {I40E_INSET_TUNNEL_SRC_PORT,
7149 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7150 {I40E_INSET_TUNNEL_DST_PORT,
7151 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7152 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7153 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7154 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7155 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7156 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7157 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7158 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7159 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7160 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7166 /* Translate input set to register aware inset */
7167 for (i = 0; i < RTE_DIM(inset_map); i++) {
7168 if (input & inset_map[i].inset)
7169 val |= inset_map[i].inset_reg;
7176 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7179 uint64_t inset_need_mask = inset;
7181 static const struct {
7184 } inset_mask_map[] = {
7185 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7186 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7187 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7188 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7189 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7190 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7191 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7192 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7195 if (!inset || !mask || !nb_elem)
7198 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7199 /* Clear the inset bit, if no MASK is required,
7200 * for example proto + ttl
7202 if ((inset & inset_mask_map[i].inset) ==
7203 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
7204 inset_need_mask &= ~inset_mask_map[i].inset;
7205 if (!inset_need_mask)
7208 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7209 if ((inset_need_mask & inset_mask_map[i].inset) ==
7210 inset_mask_map[i].inset) {
7211 if (idx >= nb_elem) {
7212 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
7215 mask[idx] = inset_mask_map[i].mask;
7224 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7226 uint32_t reg = i40e_read_rx_ctl(hw, addr);
7228 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7230 i40e_write_rx_ctl(hw, addr, val);
7231 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7232 (uint32_t)i40e_read_rx_ctl(hw, addr));
7236 i40e_filter_input_set_init(struct i40e_pf *pf)
7238 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7239 enum i40e_filter_pctype pctype;
7240 uint64_t input_set, inset_reg;
7241 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7244 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
7245 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
7246 if (!I40E_VALID_PCTYPE(pctype))
7248 input_set = i40e_get_default_input_set(pctype);
7250 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7251 I40E_INSET_MASK_NUM_REG);
7254 inset_reg = i40e_translate_input_set_reg(input_set);
7256 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7257 (uint32_t)(inset_reg & UINT32_MAX));
7258 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7259 (uint32_t)((inset_reg >>
7260 I40E_32_BIT_WIDTH) & UINT32_MAX));
7261 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7262 (uint32_t)(inset_reg & UINT32_MAX));
7263 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7264 (uint32_t)((inset_reg >>
7265 I40E_32_BIT_WIDTH) & UINT32_MAX));
7267 for (i = 0; i < num; i++) {
7268 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7270 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7273 /*clear unused mask registers of the pctype */
7274 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
7275 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7277 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7280 I40E_WRITE_FLUSH(hw);
7282 /* store the default input set */
7283 pf->hash_input_set[pctype] = input_set;
7284 pf->fdir.input_set[pctype] = input_set;
7289 i40e_hash_filter_inset_select(struct i40e_hw *hw,
7290 struct rte_eth_input_set_conf *conf)
7292 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
7293 enum i40e_filter_pctype pctype;
7294 uint64_t input_set, inset_reg = 0;
7295 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7299 PMD_DRV_LOG(ERR, "Invalid pointer");
7302 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7303 conf->op != RTE_ETH_INPUT_SET_ADD) {
7304 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7308 pctype = i40e_flowtype_to_pctype(conf->flow_type);
7309 if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
7310 PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
7315 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7318 PMD_DRV_LOG(ERR, "Failed to parse input set");
7321 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
7323 PMD_DRV_LOG(ERR, "Invalid input set");
7326 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
7327 /* get inset value in register */
7328 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
7329 inset_reg <<= I40E_32_BIT_WIDTH;
7330 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
7331 input_set |= pf->hash_input_set[pctype];
7333 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7334 I40E_INSET_MASK_NUM_REG);
7338 inset_reg |= i40e_translate_input_set_reg(input_set);
7340 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7341 (uint32_t)(inset_reg & UINT32_MAX));
7342 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7343 (uint32_t)((inset_reg >>
7344 I40E_32_BIT_WIDTH) & UINT32_MAX));
7346 for (i = 0; i < num; i++)
7347 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7349 /*clear unused mask registers of the pctype */
7350 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7351 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7353 I40E_WRITE_FLUSH(hw);
7355 pf->hash_input_set[pctype] = input_set;
7360 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
7361 struct rte_eth_input_set_conf *conf)
7363 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7364 enum i40e_filter_pctype pctype;
7365 uint64_t input_set, inset_reg = 0;
7366 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7370 PMD_DRV_LOG(ERR, "Invalid pointer");
7373 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7374 conf->op != RTE_ETH_INPUT_SET_ADD) {
7375 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7379 pctype = i40e_flowtype_to_pctype(conf->flow_type);
7380 if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
7381 PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
7385 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7388 PMD_DRV_LOG(ERR, "Failed to parse input set");
7391 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
7393 PMD_DRV_LOG(ERR, "Invalid input set");
7397 /* get inset value in register */
7398 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
7399 inset_reg <<= I40E_32_BIT_WIDTH;
7400 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
7402 /* Can not change the inset reg for flex payload for fdir,
7403 * it is done by writing I40E_PRTQF_FD_FLXINSET
7404 * in i40e_set_flex_mask_on_pctype.
7406 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
7407 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
7409 input_set |= pf->fdir.input_set[pctype];
7410 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7411 I40E_INSET_MASK_NUM_REG);
7415 inset_reg |= i40e_translate_input_set_reg(input_set);
7417 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7418 (uint32_t)(inset_reg & UINT32_MAX));
7419 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7420 (uint32_t)((inset_reg >>
7421 I40E_32_BIT_WIDTH) & UINT32_MAX));
7423 for (i = 0; i < num; i++)
7424 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7426 /*clear unused mask registers of the pctype */
7427 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7428 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7430 I40E_WRITE_FLUSH(hw);
7432 pf->fdir.input_set[pctype] = input_set;
7437 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7442 PMD_DRV_LOG(ERR, "Invalid pointer");
7446 switch (info->info_type) {
7447 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7448 i40e_get_symmetric_hash_enable_per_port(hw,
7449 &(info->info.enable));
7451 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7452 ret = i40e_get_hash_filter_global_config(hw,
7453 &(info->info.global_conf));
7456 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7466 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7471 PMD_DRV_LOG(ERR, "Invalid pointer");
7475 switch (info->info_type) {
7476 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7477 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7479 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7480 ret = i40e_set_hash_filter_global_config(hw,
7481 &(info->info.global_conf));
7483 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7484 ret = i40e_hash_filter_inset_select(hw,
7485 &(info->info.input_set_conf));
7489 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7498 /* Operations for hash function */
7500 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7501 enum rte_filter_op filter_op,
7504 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7507 switch (filter_op) {
7508 case RTE_ETH_FILTER_NOP:
7510 case RTE_ETH_FILTER_GET:
7511 ret = i40e_hash_filter_get(hw,
7512 (struct rte_eth_hash_filter_info *)arg);
7514 case RTE_ETH_FILTER_SET:
7515 ret = i40e_hash_filter_set(hw,
7516 (struct rte_eth_hash_filter_info *)arg);
7519 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
7529 * Configure ethertype filter, which can director packet by filtering
7530 * with mac address and ether_type or only ether_type
7533 i40e_ethertype_filter_set(struct i40e_pf *pf,
7534 struct rte_eth_ethertype_filter *filter,
7537 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7538 struct i40e_control_filter_stats stats;
7542 if (filter->queue >= pf->dev_data->nb_rx_queues) {
7543 PMD_DRV_LOG(ERR, "Invalid queue ID");
7546 if (filter->ether_type == ETHER_TYPE_IPv4 ||
7547 filter->ether_type == ETHER_TYPE_IPv6) {
7548 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
7549 " control packet filter.", filter->ether_type);
7552 if (filter->ether_type == ETHER_TYPE_VLAN)
7553 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
7556 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
7557 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
7558 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
7559 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
7560 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
7562 memset(&stats, 0, sizeof(stats));
7563 ret = i40e_aq_add_rem_control_packet_filter(hw,
7564 filter->mac_addr.addr_bytes,
7565 filter->ether_type, flags,
7567 filter->queue, add, &stats, NULL);
7569 PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
7570 " mac_etype_used = %u, etype_used = %u,"
7571 " mac_etype_free = %u, etype_free = %u\n",
7572 ret, stats.mac_etype_used, stats.etype_used,
7573 stats.mac_etype_free, stats.etype_free);
7580 * Handle operations for ethertype filter.
7583 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
7584 enum rte_filter_op filter_op,
7587 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7590 if (filter_op == RTE_ETH_FILTER_NOP)
7594 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
7599 switch (filter_op) {
7600 case RTE_ETH_FILTER_ADD:
7601 ret = i40e_ethertype_filter_set(pf,
7602 (struct rte_eth_ethertype_filter *)arg,
7605 case RTE_ETH_FILTER_DELETE:
7606 ret = i40e_ethertype_filter_set(pf,
7607 (struct rte_eth_ethertype_filter *)arg,
7611 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
7619 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
7620 enum rte_filter_type filter_type,
7621 enum rte_filter_op filter_op,
7629 switch (filter_type) {
7630 case RTE_ETH_FILTER_NONE:
7631 /* For global configuration */
7632 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
7634 case RTE_ETH_FILTER_HASH:
7635 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
7637 case RTE_ETH_FILTER_MACVLAN:
7638 ret = i40e_mac_filter_handle(dev, filter_op, arg);
7640 case RTE_ETH_FILTER_ETHERTYPE:
7641 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
7643 case RTE_ETH_FILTER_TUNNEL:
7644 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
7646 case RTE_ETH_FILTER_FDIR:
7647 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
7650 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7660 * Check and enable Extended Tag.
7661 * Enabling Extended Tag is important for 40G performance.
7664 i40e_enable_extended_tag(struct rte_eth_dev *dev)
7669 ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7672 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7676 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
7677 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
7682 ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7685 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7689 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
7690 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
7693 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
7694 ret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf),
7697 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
7704 * As some registers wouldn't be reset unless a global hardware reset,
7705 * hardware initialization is needed to put those registers into an
7706 * expected initial state.
7709 i40e_hw_init(struct rte_eth_dev *dev)
7711 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7713 i40e_enable_extended_tag(dev);
7715 /* clear the PF Queue Filter control register */
7716 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
7718 /* Disable symmetric hash per port */
7719 i40e_set_symmetric_hash_enable_per_port(hw, 0);
7722 enum i40e_filter_pctype
7723 i40e_flowtype_to_pctype(uint16_t flow_type)
7725 static const enum i40e_filter_pctype pctype_table[] = {
7726 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
7727 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
7728 I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
7729 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
7730 I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
7731 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
7732 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
7733 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
7734 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
7735 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
7736 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
7737 I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
7738 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
7739 I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
7740 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
7741 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
7742 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
7743 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
7744 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
7747 return pctype_table[flow_type];
7751 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
7753 static const uint16_t flowtype_table[] = {
7754 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
7755 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7756 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
7757 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7758 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
7759 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7760 RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
7761 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7762 RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
7763 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
7764 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7765 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
7766 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7767 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
7768 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7769 RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
7770 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7771 RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
7772 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
7775 return flowtype_table[pctype];
7779 * On X710, performance number is far from the expectation on recent firmware
7780 * versions; on XL710, performance number is also far from the expectation on
7781 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
7782 * mode is enabled and port MAC address is equal to the packet destination MAC
7783 * address. The fix for this issue may not be integrated in the following
7784 * firmware version. So the workaround in software driver is needed. It needs
7785 * to modify the initial values of 3 internal only registers for both X710 and
7786 * XL710. Note that the values for X710 or XL710 could be different, and the
7787 * workaround can be removed when it is fixed in firmware in the future.
7790 /* For both X710 and XL710 */
7791 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
7792 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
7794 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
7795 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
7798 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
7800 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
7801 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
7804 i40e_configure_registers(struct i40e_hw *hw)
7810 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
7811 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
7812 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
7818 for (i = 0; i < RTE_DIM(reg_table); i++) {
7819 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
7820 if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
7822 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
7825 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
7828 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
7831 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
7835 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
7836 reg_table[i].addr, reg);
7837 if (reg == reg_table[i].val)
7840 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
7841 reg_table[i].val, NULL);
7843 PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
7844 "address of 0x%"PRIx32, reg_table[i].val,
7848 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
7849 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
7853 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
7854 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
7855 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
7856 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
7858 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
7863 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
7864 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
7868 /* Configure for double VLAN RX stripping */
7869 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
7870 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
7871 reg |= I40E_VSI_TSR_QINQ_CONFIG;
7872 ret = i40e_aq_debug_write_register(hw,
7873 I40E_VSI_TSR(vsi->vsi_id),
7876 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
7878 return I40E_ERR_CONFIG;
7882 /* Configure for double VLAN TX insertion */
7883 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
7884 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
7885 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
7886 ret = i40e_aq_debug_write_register(hw,
7887 I40E_VSI_L2TAGSTXVALID(
7888 vsi->vsi_id), reg, NULL);
7890 PMD_DRV_LOG(ERR, "Failed to update "
7891 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
7892 return I40E_ERR_CONFIG;
7900 * i40e_aq_add_mirror_rule
7901 * @hw: pointer to the hardware structure
7902 * @seid: VEB seid to add mirror rule to
7903 * @dst_id: destination vsi seid
7904 * @entries: Buffer which contains the entities to be mirrored
7905 * @count: number of entities contained in the buffer
7906 * @rule_id:the rule_id of the rule to be added
7908 * Add a mirror rule for a given veb.
7911 static enum i40e_status_code
7912 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
7913 uint16_t seid, uint16_t dst_id,
7914 uint16_t rule_type, uint16_t *entries,
7915 uint16_t count, uint16_t *rule_id)
7917 struct i40e_aq_desc desc;
7918 struct i40e_aqc_add_delete_mirror_rule cmd;
7919 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
7920 (struct i40e_aqc_add_delete_mirror_rule_completion *)
7923 enum i40e_status_code status;
7925 i40e_fill_default_direct_cmd_desc(&desc,
7926 i40e_aqc_opc_add_mirror_rule);
7927 memset(&cmd, 0, sizeof(cmd));
7929 buff_len = sizeof(uint16_t) * count;
7930 desc.datalen = rte_cpu_to_le_16(buff_len);
7932 desc.flags |= rte_cpu_to_le_16(
7933 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
7934 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7935 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7936 cmd.num_entries = rte_cpu_to_le_16(count);
7937 cmd.seid = rte_cpu_to_le_16(seid);
7938 cmd.destination = rte_cpu_to_le_16(dst_id);
7940 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7941 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
7942 PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
7944 " mirror_rules_used = %u, mirror_rules_free = %u,",
7945 hw->aq.asq_last_status, resp->rule_id,
7946 resp->mirror_rules_used, resp->mirror_rules_free);
7947 *rule_id = rte_le_to_cpu_16(resp->rule_id);
7953 * i40e_aq_del_mirror_rule
7954 * @hw: pointer to the hardware structure
7955 * @seid: VEB seid to add mirror rule to
7956 * @entries: Buffer which contains the entities to be mirrored
7957 * @count: number of entities contained in the buffer
7958 * @rule_id:the rule_id of the rule to be delete
7960 * Delete a mirror rule for a given veb.
7963 static enum i40e_status_code
7964 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
7965 uint16_t seid, uint16_t rule_type, uint16_t *entries,
7966 uint16_t count, uint16_t rule_id)
7968 struct i40e_aq_desc desc;
7969 struct i40e_aqc_add_delete_mirror_rule cmd;
7970 uint16_t buff_len = 0;
7971 enum i40e_status_code status;
7974 i40e_fill_default_direct_cmd_desc(&desc,
7975 i40e_aqc_opc_delete_mirror_rule);
7976 memset(&cmd, 0, sizeof(cmd));
7977 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
7978 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
7980 cmd.num_entries = count;
7981 buff_len = sizeof(uint16_t) * count;
7982 desc.datalen = rte_cpu_to_le_16(buff_len);
7983 buff = (void *)entries;
7985 /* rule id is filled in destination field for deleting mirror rule */
7986 cmd.destination = rte_cpu_to_le_16(rule_id);
7988 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7989 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7990 cmd.seid = rte_cpu_to_le_16(seid);
7992 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7993 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
7999 * i40e_mirror_rule_set
8000 * @dev: pointer to the hardware structure
8001 * @mirror_conf: mirror rule info
8002 * @sw_id: mirror rule's sw_id
8003 * @on: enable/disable
8005 * set a mirror rule.
8009 i40e_mirror_rule_set(struct rte_eth_dev *dev,
8010 struct rte_eth_mirror_conf *mirror_conf,
8011 uint8_t sw_id, uint8_t on)
8013 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8014 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8015 struct i40e_mirror_rule *it, *mirr_rule = NULL;
8016 struct i40e_mirror_rule *parent = NULL;
8017 uint16_t seid, dst_seid, rule_id;
8021 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
8023 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
8024 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
8025 " without veb or vfs.");
8028 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
8029 PMD_DRV_LOG(ERR, "mirror table is full.");
8032 if (mirror_conf->dst_pool > pf->vf_num) {
8033 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
8034 mirror_conf->dst_pool);
8038 seid = pf->main_vsi->veb->seid;
8040 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8041 if (sw_id <= it->index) {
8047 if (mirr_rule && sw_id == mirr_rule->index) {
8049 PMD_DRV_LOG(ERR, "mirror rule exists.");
8052 ret = i40e_aq_del_mirror_rule(hw, seid,
8053 mirr_rule->rule_type,
8055 mirr_rule->num_entries, mirr_rule->id);
8057 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8058 " ret = %d, aq_err = %d.",
8059 ret, hw->aq.asq_last_status);
8062 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8063 rte_free(mirr_rule);
8064 pf->nb_mirror_rule--;
8068 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8072 mirr_rule = rte_zmalloc("i40e_mirror_rule",
8073 sizeof(struct i40e_mirror_rule) , 0);
8075 PMD_DRV_LOG(ERR, "failed to allocate memory");
8076 return I40E_ERR_NO_MEMORY;
8078 switch (mirror_conf->rule_type) {
8079 case ETH_MIRROR_VLAN:
8080 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
8081 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
8082 mirr_rule->entries[j] =
8083 mirror_conf->vlan.vlan_id[i];
8088 PMD_DRV_LOG(ERR, "vlan is not specified.");
8089 rte_free(mirr_rule);
8092 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
8094 case ETH_MIRROR_VIRTUAL_POOL_UP:
8095 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
8096 /* check if the specified pool bit is out of range */
8097 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
8098 PMD_DRV_LOG(ERR, "pool mask is out of range.");
8099 rte_free(mirr_rule);
8102 for (i = 0, j = 0; i < pf->vf_num; i++) {
8103 if (mirror_conf->pool_mask & (1ULL << i)) {
8104 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
8108 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
8109 /* add pf vsi to entries */
8110 mirr_rule->entries[j] = pf->main_vsi_seid;
8114 PMD_DRV_LOG(ERR, "pool is not specified.");
8115 rte_free(mirr_rule);
8118 /* egress and ingress in aq commands means from switch but not port */
8119 mirr_rule->rule_type =
8120 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
8121 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
8122 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
8124 case ETH_MIRROR_UPLINK_PORT:
8125 /* egress and ingress in aq commands means from switch but not port*/
8126 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
8128 case ETH_MIRROR_DOWNLINK_PORT:
8129 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
8132 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
8133 mirror_conf->rule_type);
8134 rte_free(mirr_rule);
8138 /* If the dst_pool is equal to vf_num, consider it as PF */
8139 if (mirror_conf->dst_pool == pf->vf_num)
8140 dst_seid = pf->main_vsi_seid;
8142 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
8144 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
8145 mirr_rule->rule_type, mirr_rule->entries,
8148 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
8149 " ret = %d, aq_err = %d.",
8150 ret, hw->aq.asq_last_status);
8151 rte_free(mirr_rule);
8155 mirr_rule->index = sw_id;
8156 mirr_rule->num_entries = j;
8157 mirr_rule->id = rule_id;
8158 mirr_rule->dst_vsi_seid = dst_seid;
8161 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
8163 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
8165 pf->nb_mirror_rule++;
8170 * i40e_mirror_rule_reset
8171 * @dev: pointer to the device
8172 * @sw_id: mirror rule's sw_id
8174 * reset a mirror rule.
8178 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
8180 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8181 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8182 struct i40e_mirror_rule *it, *mirr_rule = NULL;
8186 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
8188 seid = pf->main_vsi->veb->seid;
8190 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8191 if (sw_id == it->index) {
8197 ret = i40e_aq_del_mirror_rule(hw, seid,
8198 mirr_rule->rule_type,
8200 mirr_rule->num_entries, mirr_rule->id);
8202 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8203 " status = %d, aq_err = %d.",
8204 ret, hw->aq.asq_last_status);
8207 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8208 rte_free(mirr_rule);
8209 pf->nb_mirror_rule--;
8211 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8218 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
8220 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8221 uint64_t systim_cycles;
8223 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
8224 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
8227 return systim_cycles;
8231 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
8233 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8236 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
8237 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
8244 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
8246 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8249 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
8250 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
8257 i40e_start_timecounters(struct rte_eth_dev *dev)
8259 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8260 struct i40e_adapter *adapter =
8261 (struct i40e_adapter *)dev->data->dev_private;
8262 struct rte_eth_link link;
8263 uint32_t tsync_inc_l;
8264 uint32_t tsync_inc_h;
8266 /* Get current link speed. */
8267 memset(&link, 0, sizeof(link));
8268 i40e_dev_link_update(dev, 1);
8269 rte_i40e_dev_atomic_read_link_status(dev, &link);
8271 switch (link.link_speed) {
8272 case ETH_SPEED_NUM_40G:
8273 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
8274 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
8276 case ETH_SPEED_NUM_10G:
8277 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
8278 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
8280 case ETH_SPEED_NUM_1G:
8281 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
8282 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
8289 /* Set the timesync increment value. */
8290 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
8291 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
8293 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
8294 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8295 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8297 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8298 adapter->systime_tc.cc_shift = 0;
8299 adapter->systime_tc.nsec_mask = 0;
8301 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8302 adapter->rx_tstamp_tc.cc_shift = 0;
8303 adapter->rx_tstamp_tc.nsec_mask = 0;
8305 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8306 adapter->tx_tstamp_tc.cc_shift = 0;
8307 adapter->tx_tstamp_tc.nsec_mask = 0;
8311 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
8313 struct i40e_adapter *adapter =
8314 (struct i40e_adapter *)dev->data->dev_private;
8316 adapter->systime_tc.nsec += delta;
8317 adapter->rx_tstamp_tc.nsec += delta;
8318 adapter->tx_tstamp_tc.nsec += delta;
8324 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
8327 struct i40e_adapter *adapter =
8328 (struct i40e_adapter *)dev->data->dev_private;
8330 ns = rte_timespec_to_ns(ts);
8332 /* Set the timecounters to a new value. */
8333 adapter->systime_tc.nsec = ns;
8334 adapter->rx_tstamp_tc.nsec = ns;
8335 adapter->tx_tstamp_tc.nsec = ns;
8341 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
8343 uint64_t ns, systime_cycles;
8344 struct i40e_adapter *adapter =
8345 (struct i40e_adapter *)dev->data->dev_private;
8347 systime_cycles = i40e_read_systime_cyclecounter(dev);
8348 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
8349 *ts = rte_ns_to_timespec(ns);
8355 i40e_timesync_enable(struct rte_eth_dev *dev)
8357 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8358 uint32_t tsync_ctl_l;
8359 uint32_t tsync_ctl_h;
8361 /* Stop the timesync system time. */
8362 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8363 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8364 /* Reset the timesync system time value. */
8365 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
8366 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
8368 i40e_start_timecounters(dev);
8370 /* Clear timesync registers. */
8371 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8372 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
8373 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
8374 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
8375 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
8376 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
8378 /* Enable timestamping of PTP packets. */
8379 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8380 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
8382 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8383 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
8384 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
8386 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8387 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8393 i40e_timesync_disable(struct rte_eth_dev *dev)
8395 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8396 uint32_t tsync_ctl_l;
8397 uint32_t tsync_ctl_h;
8399 /* Disable timestamping of transmitted PTP packets. */
8400 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8401 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
8403 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8404 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
8406 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8407 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8409 /* Reset the timesync increment value. */
8410 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8411 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8417 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
8418 struct timespec *timestamp, uint32_t flags)
8420 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8421 struct i40e_adapter *adapter =
8422 (struct i40e_adapter *)dev->data->dev_private;
8424 uint32_t sync_status;
8425 uint32_t index = flags & 0x03;
8426 uint64_t rx_tstamp_cycles;
8429 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
8430 if ((sync_status & (1 << index)) == 0)
8433 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
8434 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
8435 *timestamp = rte_ns_to_timespec(ns);
8441 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
8442 struct timespec *timestamp)
8444 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8445 struct i40e_adapter *adapter =
8446 (struct i40e_adapter *)dev->data->dev_private;
8448 uint32_t sync_status;
8449 uint64_t tx_tstamp_cycles;
8452 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8453 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
8456 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
8457 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
8458 *timestamp = rte_ns_to_timespec(ns);
8464 * i40e_parse_dcb_configure - parse dcb configure from user
8465 * @dev: the device being configured
8466 * @dcb_cfg: pointer of the result of parse
8467 * @*tc_map: bit map of enabled traffic classes
8469 * Returns 0 on success, negative value on failure
8472 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
8473 struct i40e_dcbx_config *dcb_cfg,
8476 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
8477 uint8_t i, tc_bw, bw_lf;
8479 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
8481 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
8482 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
8483 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
8487 /* assume each tc has the same bw */
8488 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
8489 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8490 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
8491 /* to ensure the sum of tcbw is equal to 100 */
8492 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
8493 for (i = 0; i < bw_lf; i++)
8494 dcb_cfg->etscfg.tcbwtable[i]++;
8496 /* assume each tc has the same Transmission Selection Algorithm */
8497 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8498 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
8500 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8501 dcb_cfg->etscfg.prioritytable[i] =
8502 dcb_rx_conf->dcb_tc[i];
8504 /* FW needs one App to configure HW */
8505 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
8506 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
8507 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
8508 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
8510 if (dcb_rx_conf->nb_tcs == 0)
8511 *tc_map = 1; /* tc0 only */
8513 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
8515 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
8516 dcb_cfg->pfc.willing = 0;
8517 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
8518 dcb_cfg->pfc.pfcenable = *tc_map;
8524 static enum i40e_status_code
8525 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
8526 struct i40e_aqc_vsi_properties_data *info,
8527 uint8_t enabled_tcmap)
8529 enum i40e_status_code ret;
8530 int i, total_tc = 0;
8531 uint16_t qpnum_per_tc, bsf, qp_idx;
8532 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
8533 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
8534 uint16_t used_queues;
8536 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
8537 if (ret != I40E_SUCCESS)
8540 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8541 if (enabled_tcmap & (1 << i))
8546 vsi->enabled_tc = enabled_tcmap;
8548 /* different VSI has different queues assigned */
8549 if (vsi->type == I40E_VSI_MAIN)
8550 used_queues = dev_data->nb_rx_queues -
8551 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8552 else if (vsi->type == I40E_VSI_VMDQ2)
8553 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8555 PMD_INIT_LOG(ERR, "unsupported VSI type.");
8556 return I40E_ERR_NO_AVAILABLE_VSI;
8559 qpnum_per_tc = used_queues / total_tc;
8560 /* Number of queues per enabled TC */
8561 if (qpnum_per_tc == 0) {
8562 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
8563 return I40E_ERR_INVALID_QP_ID;
8565 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
8567 bsf = rte_bsf32(qpnum_per_tc);
8570 * Configure TC and queue mapping parameters, for enabled TC,
8571 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
8572 * default queue will serve it.
8575 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8576 if (vsi->enabled_tc & (1 << i)) {
8577 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
8578 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
8579 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
8580 qp_idx += qpnum_per_tc;
8582 info->tc_mapping[i] = 0;
8585 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
8586 if (vsi->type == I40E_VSI_SRIOV) {
8587 info->mapping_flags |=
8588 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
8589 for (i = 0; i < vsi->nb_qps; i++)
8590 info->queue_mapping[i] =
8591 rte_cpu_to_le_16(vsi->base_queue + i);
8593 info->mapping_flags |=
8594 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
8595 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
8597 info->valid_sections |=
8598 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
8600 return I40E_SUCCESS;
8604 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
8605 * @veb: VEB to be configured
8606 * @tc_map: enabled TC bitmap
8608 * Returns 0 on success, negative value on failure
8610 static enum i40e_status_code
8611 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
8613 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
8614 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
8615 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
8616 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
8617 enum i40e_status_code ret = I40E_SUCCESS;
8621 /* Check if enabled_tc is same as existing or new TCs */
8622 if (veb->enabled_tc == tc_map)
8625 /* configure tc bandwidth */
8626 memset(&veb_bw, 0, sizeof(veb_bw));
8627 veb_bw.tc_valid_bits = tc_map;
8628 /* Enable ETS TCs with equal BW Share for now across all VSIs */
8629 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8630 if (tc_map & BIT_ULL(i))
8631 veb_bw.tc_bw_share_credits[i] = 1;
8633 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
8636 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
8637 " per TC failed = %d",
8638 hw->aq.asq_last_status);
8642 memset(&ets_query, 0, sizeof(ets_query));
8643 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
8645 if (ret != I40E_SUCCESS) {
8646 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
8647 " configuration %u", hw->aq.asq_last_status);
8650 memset(&bw_query, 0, sizeof(bw_query));
8651 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
8653 if (ret != I40E_SUCCESS) {
8654 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
8655 " configuration %u", hw->aq.asq_last_status);
8659 /* store and print out BW info */
8660 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
8661 veb->bw_info.bw_max = ets_query.tc_bw_max;
8662 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
8663 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
8664 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
8665 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
8667 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8668 veb->bw_info.bw_ets_share_credits[i] =
8669 bw_query.tc_bw_share_credits[i];
8670 veb->bw_info.bw_ets_credits[i] =
8671 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
8672 /* 4 bits per TC, 4th bit is reserved */
8673 veb->bw_info.bw_ets_max[i] =
8674 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
8675 RTE_LEN2MASK(3, uint8_t));
8676 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
8677 veb->bw_info.bw_ets_share_credits[i]);
8678 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
8679 veb->bw_info.bw_ets_credits[i]);
8680 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
8681 veb->bw_info.bw_ets_max[i]);
8684 veb->enabled_tc = tc_map;
8691 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
8692 * @vsi: VSI to be configured
8693 * @tc_map: enabled TC bitmap
8695 * Returns 0 on success, negative value on failure
8697 static enum i40e_status_code
8698 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
8700 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
8701 struct i40e_vsi_context ctxt;
8702 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
8703 enum i40e_status_code ret = I40E_SUCCESS;
8706 /* Check if enabled_tc is same as existing or new TCs */
8707 if (vsi->enabled_tc == tc_map)
8710 /* configure tc bandwidth */
8711 memset(&bw_data, 0, sizeof(bw_data));
8712 bw_data.tc_valid_bits = tc_map;
8713 /* Enable ETS TCs with equal BW Share for now across all VSIs */
8714 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8715 if (tc_map & BIT_ULL(i))
8716 bw_data.tc_bw_credits[i] = 1;
8718 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
8720 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
8721 " per TC failed = %d",
8722 hw->aq.asq_last_status);
8725 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
8726 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
8728 /* Update Queue Pairs Mapping for currently enabled UPs */
8729 ctxt.seid = vsi->seid;
8730 ctxt.pf_num = hw->pf_id;
8732 ctxt.uplink_seid = vsi->uplink_seid;
8733 ctxt.info = vsi->info;
8735 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
8739 /* Update the VSI after updating the VSI queue-mapping information */
8740 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8742 PMD_INIT_LOG(ERR, "Failed to configure "
8743 "TC queue mapping = %d",
8744 hw->aq.asq_last_status);
8747 /* update the local VSI info with updated queue map */
8748 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
8749 sizeof(vsi->info.tc_mapping));
8750 (void)rte_memcpy(&vsi->info.queue_mapping,
8751 &ctxt.info.queue_mapping,
8752 sizeof(vsi->info.queue_mapping));
8753 vsi->info.mapping_flags = ctxt.info.mapping_flags;
8754 vsi->info.valid_sections = 0;
8756 /* query and update current VSI BW information */
8757 ret = i40e_vsi_get_bw_config(vsi);
8760 "Failed updating vsi bw info, err %s aq_err %s",
8761 i40e_stat_str(hw, ret),
8762 i40e_aq_str(hw, hw->aq.asq_last_status));
8766 vsi->enabled_tc = tc_map;
8773 * i40e_dcb_hw_configure - program the dcb setting to hw
8774 * @pf: pf the configuration is taken on
8775 * @new_cfg: new configuration
8776 * @tc_map: enabled TC bitmap
8778 * Returns 0 on success, negative value on failure
8780 static enum i40e_status_code
8781 i40e_dcb_hw_configure(struct i40e_pf *pf,
8782 struct i40e_dcbx_config *new_cfg,
8785 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8786 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
8787 struct i40e_vsi *main_vsi = pf->main_vsi;
8788 struct i40e_vsi_list *vsi_list;
8789 enum i40e_status_code ret;
8793 /* Use the FW API if FW > v4.4*/
8794 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
8795 (hw->aq.fw_maj_ver >= 5))) {
8796 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
8797 " to configure DCB");
8798 return I40E_ERR_FIRMWARE_API_VERSION;
8801 /* Check if need reconfiguration */
8802 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
8803 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
8804 return I40E_SUCCESS;
8807 /* Copy the new config to the current config */
8808 *old_cfg = *new_cfg;
8809 old_cfg->etsrec = old_cfg->etscfg;
8810 ret = i40e_set_dcb_config(hw);
8813 "Set DCB Config failed, err %s aq_err %s\n",
8814 i40e_stat_str(hw, ret),
8815 i40e_aq_str(hw, hw->aq.asq_last_status));
8818 /* set receive Arbiter to RR mode and ETS scheme by default */
8819 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
8820 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
8821 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
8822 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
8823 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
8824 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
8825 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
8826 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
8827 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
8828 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
8829 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
8830 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
8831 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
8833 /* get local mib to check whether it is configured correctly */
8835 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
8836 /* Get Local DCB Config */
8837 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
8838 &hw->local_dcbx_config);
8840 /* if Veb is created, need to update TC of it at first */
8841 if (main_vsi->veb) {
8842 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
8844 PMD_INIT_LOG(WARNING,
8845 "Failed configuring TC for VEB seid=%d\n",
8846 main_vsi->veb->seid);
8848 /* Update each VSI */
8849 i40e_vsi_config_tc(main_vsi, tc_map);
8850 if (main_vsi->veb) {
8851 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
8852 /* Beside main VSI and VMDQ VSIs, only enable default
8855 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
8856 ret = i40e_vsi_config_tc(vsi_list->vsi,
8859 ret = i40e_vsi_config_tc(vsi_list->vsi,
8860 I40E_DEFAULT_TCMAP);
8862 PMD_INIT_LOG(WARNING,
8863 "Failed configuring TC for VSI seid=%d\n",
8864 vsi_list->vsi->seid);
8868 return I40E_SUCCESS;
8872 * i40e_dcb_init_configure - initial dcb config
8873 * @dev: device being configured
8874 * @sw_dcb: indicate whether dcb is sw configured or hw offload
8876 * Returns 0 on success, negative value on failure
8879 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
8881 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8882 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8885 if ((pf->flags & I40E_FLAG_DCB) == 0) {
8886 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8890 /* DCB initialization:
8891 * Update DCB configuration from the Firmware and configure
8892 * LLDP MIB change event.
8894 if (sw_dcb == TRUE) {
8895 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
8896 if (ret != I40E_SUCCESS)
8897 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
8899 ret = i40e_init_dcb(hw);
8900 /* if sw_dcb, lldp agent is stopped, the return from
8901 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
8904 if (ret != I40E_SUCCESS &&
8905 hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
8906 memset(&hw->local_dcbx_config, 0,
8907 sizeof(struct i40e_dcbx_config));
8908 /* set dcb default configuration */
8909 hw->local_dcbx_config.etscfg.willing = 0;
8910 hw->local_dcbx_config.etscfg.maxtcs = 0;
8911 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
8912 hw->local_dcbx_config.etscfg.tsatable[0] =
8914 hw->local_dcbx_config.etsrec =
8915 hw->local_dcbx_config.etscfg;
8916 hw->local_dcbx_config.pfc.willing = 0;
8917 hw->local_dcbx_config.pfc.pfccap =
8918 I40E_MAX_TRAFFIC_CLASS;
8919 /* FW needs one App to configure HW */
8920 hw->local_dcbx_config.numapps = 1;
8921 hw->local_dcbx_config.app[0].selector =
8922 I40E_APP_SEL_ETHTYPE;
8923 hw->local_dcbx_config.app[0].priority = 3;
8924 hw->local_dcbx_config.app[0].protocolid =
8925 I40E_APP_PROTOID_FCOE;
8926 ret = i40e_set_dcb_config(hw);
8928 PMD_INIT_LOG(ERR, "default dcb config fails."
8929 " err = %d, aq_err = %d.", ret,
8930 hw->aq.asq_last_status);
8934 PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8935 " aq_err = %d.", ret,
8936 hw->aq.asq_last_status);
8940 ret = i40e_aq_start_lldp(hw, NULL);
8941 if (ret != I40E_SUCCESS)
8942 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
8944 ret = i40e_init_dcb(hw);
8946 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
8947 PMD_INIT_LOG(ERR, "HW doesn't support"
8952 PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8953 " aq_err = %d.", ret,
8954 hw->aq.asq_last_status);
8962 * i40e_dcb_setup - setup dcb related config
8963 * @dev: device being configured
8965 * Returns 0 on success, negative value on failure
8968 i40e_dcb_setup(struct rte_eth_dev *dev)
8970 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8971 struct i40e_dcbx_config dcb_cfg;
8975 if ((pf->flags & I40E_FLAG_DCB) == 0) {
8976 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8980 if (pf->vf_num != 0)
8981 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
8983 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
8985 PMD_INIT_LOG(ERR, "invalid dcb config");
8988 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
8990 PMD_INIT_LOG(ERR, "dcb sw configure fails");
8998 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
8999 struct rte_eth_dcb_info *dcb_info)
9001 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9002 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9003 struct i40e_vsi *vsi = pf->main_vsi;
9004 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
9005 uint16_t bsf, tc_mapping;
9008 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
9009 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
9011 dcb_info->nb_tcs = 1;
9012 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9013 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
9014 for (i = 0; i < dcb_info->nb_tcs; i++)
9015 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
9017 /* get queue mapping if vmdq is disabled */
9018 if (!pf->nb_cfg_vmdq_vsi) {
9019 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9020 if (!(vsi->enabled_tc & (1 << i)))
9022 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9023 dcb_info->tc_queue.tc_rxq[j][i].base =
9024 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9025 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9026 dcb_info->tc_queue.tc_txq[j][i].base =
9027 dcb_info->tc_queue.tc_rxq[j][i].base;
9028 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9029 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9030 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9031 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9032 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9037 /* get queue mapping if vmdq is enabled */
9039 vsi = pf->vmdq[j].vsi;
9040 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9041 if (!(vsi->enabled_tc & (1 << i)))
9043 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9044 dcb_info->tc_queue.tc_rxq[j][i].base =
9045 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9046 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9047 dcb_info->tc_queue.tc_txq[j][i].base =
9048 dcb_info->tc_queue.tc_rxq[j][i].base;
9049 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9050 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9051 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9052 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9053 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9056 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
9061 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
9063 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9064 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9066 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
9069 msix_intr = intr_handle->intr_vec[queue_id];
9070 if (msix_intr == I40E_MISC_VEC_ID)
9071 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
9072 I40E_PFINT_DYN_CTLN_INTENA_MASK |
9073 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9074 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9076 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9079 I40E_PFINT_DYN_CTLN(msix_intr -
9081 I40E_PFINT_DYN_CTLN_INTENA_MASK |
9082 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9083 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9085 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9087 I40E_WRITE_FLUSH(hw);
9088 rte_intr_enable(&dev->pci_dev->intr_handle);
9094 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
9096 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9097 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9100 msix_intr = intr_handle->intr_vec[queue_id];
9101 if (msix_intr == I40E_MISC_VEC_ID)
9102 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
9105 I40E_PFINT_DYN_CTLN(msix_intr -
9108 I40E_WRITE_FLUSH(hw);
9113 static int i40e_get_reg_length(__rte_unused struct rte_eth_dev *dev)
9115 /* Highest base addr + 32-bit word */
9116 return I40E_GLGEN_STAT_CLEAR + 4;
9119 static int i40e_get_regs(struct rte_eth_dev *dev,
9120 struct rte_dev_reg_info *regs)
9122 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9123 uint32_t *ptr_data = regs->data;
9124 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
9125 const struct i40e_reg_info *reg_info;
9127 /* The first few registers have to be read using AQ operations */
9129 while (i40e_regs_adminq[reg_idx].name) {
9130 reg_info = &i40e_regs_adminq[reg_idx++];
9131 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9133 arr_idx2 <= reg_info->count2;
9135 reg_offset = arr_idx * reg_info->stride1 +
9136 arr_idx2 * reg_info->stride2;
9137 reg_offset += reg_info->base_addr;
9138 ptr_data[reg_offset >> 2] =
9139 i40e_read_rx_ctl(hw, reg_offset);
9143 /* The remaining registers can be read using primitives */
9145 while (i40e_regs_others[reg_idx].name) {
9146 reg_info = &i40e_regs_others[reg_idx++];
9147 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9149 arr_idx2 <= reg_info->count2;
9151 reg_offset = arr_idx * reg_info->stride1 +
9152 arr_idx2 * reg_info->stride2;
9153 reg_offset += reg_info->base_addr;
9154 ptr_data[reg_offset >> 2] =
9155 I40E_READ_REG(hw, reg_offset);
9162 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
9164 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9166 /* Convert word count to byte count */
9167 return hw->nvm.sr_size << 1;
9170 static int i40e_get_eeprom(struct rte_eth_dev *dev,
9171 struct rte_dev_eeprom_info *eeprom)
9173 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9174 uint16_t *data = eeprom->data;
9175 uint16_t offset, length, cnt_words;
9178 offset = eeprom->offset >> 1;
9179 length = eeprom->length >> 1;
9182 if (offset > hw->nvm.sr_size ||
9183 offset + length > hw->nvm.sr_size) {
9184 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
9188 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
9190 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
9191 if (ret_code != I40E_SUCCESS || cnt_words != length) {
9192 PMD_DRV_LOG(ERR, "EEPROM read failed.");
9199 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
9200 struct ether_addr *mac_addr)
9202 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9204 if (!is_valid_assigned_ether_addr(mac_addr)) {
9205 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
9209 /* Flags: 0x3 updates port address */
9210 i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
9214 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
9216 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9217 struct rte_eth_dev_data *dev_data = pf->dev_data;
9218 uint32_t frame_size = mtu + ETHER_HDR_LEN
9219 + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
9222 /* check if mtu is within the allowed range */
9223 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
9226 /* mtu setting is forbidden if port is start */
9227 if (dev_data->dev_started) {
9229 "port %d must be stopped before configuration\n",
9234 if (frame_size > ETHER_MAX_LEN)
9235 dev_data->dev_conf.rxmode.jumbo_frame = 1;
9237 dev_data->dev_conf.rxmode.jumbo_frame = 0;
9239 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;