4 * Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 #include <rte_string_fns.h>
46 #include <rte_bus_pci.h>
47 #include <rte_ether.h>
48 #include <rte_ethdev.h>
49 #include <rte_ethdev_pci.h>
50 #include <rte_memzone.h>
51 #include <rte_malloc.h>
52 #include <rte_memcpy.h>
53 #include <rte_alarm.h>
55 #include <rte_eth_ctrl.h>
56 #include <rte_tailq.h>
57 #include <rte_hash_crc.h>
59 #include "i40e_logs.h"
60 #include "base/i40e_prototype.h"
61 #include "base/i40e_adminq_cmd.h"
62 #include "base/i40e_type.h"
63 #include "base/i40e_register.h"
64 #include "base/i40e_dcb.h"
65 #include "i40e_ethdev.h"
66 #include "i40e_rxtx.h"
68 #include "i40e_regs.h"
69 #include "rte_pmd_i40e.h"
71 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
72 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
74 #define I40E_CLEAR_PXE_WAIT_MS 200
76 /* Maximun number of capability elements */
77 #define I40E_MAX_CAP_ELE_NUM 128
79 /* Wait count and interval */
80 #define I40E_CHK_Q_ENA_COUNT 1000
81 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
83 /* Maximun number of VSI */
84 #define I40E_MAX_NUM_VSIS (384UL)
86 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
88 /* Flow control default timer */
89 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
91 /* Flow control enable fwd bit */
92 #define I40E_PRTMAC_FWD_CTRL 0x00000001
94 /* Receive Packet Buffer size */
95 #define I40E_RXPBSIZE (968 * 1024)
98 #define I40E_KILOSHIFT 10
100 /* Flow control default high water */
101 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
103 /* Flow control default low water */
104 #define I40E_DEFAULT_LOW_WATER (0xF2000 >> I40E_KILOSHIFT)
106 /* Receive Average Packet Size in Byte*/
107 #define I40E_PACKET_AVERAGE_SIZE 128
109 /* Mask of PF interrupt causes */
110 #define I40E_PFINT_ICR0_ENA_MASK ( \
111 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
112 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
113 I40E_PFINT_ICR0_ENA_GRST_MASK | \
114 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
115 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
116 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
117 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
118 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
119 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
121 #define I40E_FLOW_TYPES ( \
122 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
123 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
124 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
125 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
126 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
127 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
128 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
129 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
130 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
131 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
132 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
134 /* Additional timesync values. */
135 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
136 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
137 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
138 #define I40E_PRTTSYN_TSYNENA 0x80000000
139 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
140 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
143 * Below are values for writing un-exposed registers suggested
146 /* Destination MAC address */
147 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
148 /* Source MAC address */
149 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
150 /* Outer (S-Tag) VLAN tag in the outer L2 header */
151 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
152 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
153 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
154 /* Single VLAN tag in the inner L2 header */
155 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
156 /* Source IPv4 address */
157 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
158 /* Destination IPv4 address */
159 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
160 /* Source IPv4 address for X722 */
161 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
162 /* Destination IPv4 address for X722 */
163 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
164 /* IPv4 Protocol for X722 */
165 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
166 /* IPv4 Time to Live for X722 */
167 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
168 /* IPv4 Type of Service (TOS) */
169 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
171 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
172 /* IPv4 Time to Live */
173 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
174 /* Source IPv6 address */
175 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
176 /* Destination IPv6 address */
177 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
178 /* IPv6 Traffic Class (TC) */
179 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
180 /* IPv6 Next Header */
181 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
183 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
185 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
186 /* Destination L4 port */
187 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
188 /* SCTP verification tag */
189 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
190 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
191 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
192 /* Source port of tunneling UDP */
193 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
194 /* Destination port of tunneling UDP */
195 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
196 /* UDP Tunneling ID, NVGRE/GRE key */
197 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
198 /* Last ether type */
199 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
200 /* Tunneling outer destination IPv4 address */
201 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
202 /* Tunneling outer destination IPv6 address */
203 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
204 /* 1st word of flex payload */
205 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
206 /* 2nd word of flex payload */
207 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
208 /* 3rd word of flex payload */
209 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
210 /* 4th word of flex payload */
211 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
212 /* 5th word of flex payload */
213 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
214 /* 6th word of flex payload */
215 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
216 /* 7th word of flex payload */
217 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
218 /* 8th word of flex payload */
219 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
220 /* all 8 words flex payload */
221 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
222 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
224 #define I40E_TRANSLATE_INSET 0
225 #define I40E_TRANSLATE_REG 1
227 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
228 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
229 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
230 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
231 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
232 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
234 /* PCI offset for querying capability */
235 #define PCI_DEV_CAP_REG 0xA4
236 /* PCI offset for enabling/disabling Extended Tag */
237 #define PCI_DEV_CTRL_REG 0xA8
238 /* Bit mask of Extended Tag capability */
239 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
240 /* Bit shift of Extended Tag enable/disable */
241 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
242 /* Bit mask of Extended Tag enable/disable */
243 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
245 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
246 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
247 static int i40e_dev_configure(struct rte_eth_dev *dev);
248 static int i40e_dev_start(struct rte_eth_dev *dev);
249 static void i40e_dev_stop(struct rte_eth_dev *dev);
250 static void i40e_dev_close(struct rte_eth_dev *dev);
251 static int i40e_dev_reset(struct rte_eth_dev *dev);
252 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
253 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
254 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
255 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
256 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
257 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
258 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
259 struct rte_eth_stats *stats);
260 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
261 struct rte_eth_xstat *xstats, unsigned n);
262 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
263 struct rte_eth_xstat_name *xstats_names,
265 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
266 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
270 static int i40e_fw_version_get(struct rte_eth_dev *dev,
271 char *fw_version, size_t fw_size);
272 static void i40e_dev_info_get(struct rte_eth_dev *dev,
273 struct rte_eth_dev_info *dev_info);
274 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
277 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
278 enum rte_vlan_type vlan_type,
280 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
281 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
284 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
285 static int i40e_dev_led_on(struct rte_eth_dev *dev);
286 static int i40e_dev_led_off(struct rte_eth_dev *dev);
287 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
288 struct rte_eth_fc_conf *fc_conf);
289 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
290 struct rte_eth_fc_conf *fc_conf);
291 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
292 struct rte_eth_pfc_conf *pfc_conf);
293 static int i40e_macaddr_add(struct rte_eth_dev *dev,
294 struct ether_addr *mac_addr,
297 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
298 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
299 struct rte_eth_rss_reta_entry64 *reta_conf,
301 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
302 struct rte_eth_rss_reta_entry64 *reta_conf,
305 static int i40e_get_cap(struct i40e_hw *hw);
306 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
307 static int i40e_pf_setup(struct i40e_pf *pf);
308 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
309 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
310 static int i40e_dcb_setup(struct rte_eth_dev *dev);
311 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
312 bool offset_loaded, uint64_t *offset, uint64_t *stat);
313 static void i40e_stat_update_48(struct i40e_hw *hw,
319 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
320 static void i40e_dev_interrupt_handler(void *param);
321 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
322 uint32_t base, uint32_t num);
323 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
324 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
326 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
328 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
329 static int i40e_veb_release(struct i40e_veb *veb);
330 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
331 struct i40e_vsi *vsi);
332 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
333 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
334 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
335 struct i40e_macvlan_filter *mv_f,
338 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
339 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
340 struct rte_eth_rss_conf *rss_conf);
341 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
342 struct rte_eth_rss_conf *rss_conf);
343 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
344 struct rte_eth_udp_tunnel *udp_tunnel);
345 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
346 struct rte_eth_udp_tunnel *udp_tunnel);
347 static void i40e_filter_input_set_init(struct i40e_pf *pf);
348 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
349 enum rte_filter_op filter_op,
351 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
352 enum rte_filter_type filter_type,
353 enum rte_filter_op filter_op,
355 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
356 struct rte_eth_dcb_info *dcb_info);
357 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
358 static void i40e_configure_registers(struct i40e_hw *hw);
359 static void i40e_hw_init(struct rte_eth_dev *dev);
360 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
361 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
367 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
368 struct rte_eth_mirror_conf *mirror_conf,
369 uint8_t sw_id, uint8_t on);
370 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
372 static int i40e_timesync_enable(struct rte_eth_dev *dev);
373 static int i40e_timesync_disable(struct rte_eth_dev *dev);
374 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
375 struct timespec *timestamp,
377 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
378 struct timespec *timestamp);
379 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
381 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
383 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
384 struct timespec *timestamp);
385 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
386 const struct timespec *timestamp);
388 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
390 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
393 static int i40e_get_regs(struct rte_eth_dev *dev,
394 struct rte_dev_reg_info *regs);
396 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
398 static int i40e_get_eeprom(struct rte_eth_dev *dev,
399 struct rte_dev_eeprom_info *eeprom);
401 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
402 struct ether_addr *mac_addr);
404 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
406 static int i40e_ethertype_filter_convert(
407 const struct rte_eth_ethertype_filter *input,
408 struct i40e_ethertype_filter *filter);
409 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
410 struct i40e_ethertype_filter *filter);
412 static int i40e_tunnel_filter_convert(
413 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
414 struct i40e_tunnel_filter *tunnel_filter);
415 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
416 struct i40e_tunnel_filter *tunnel_filter);
417 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
419 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
420 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
421 static void i40e_filter_restore(struct i40e_pf *pf);
422 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
424 int i40e_logtype_init;
425 int i40e_logtype_driver;
427 static const struct rte_pci_id pci_id_i40e_map[] = {
428 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
429 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
430 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
431 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
432 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
435 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
436 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
437 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
438 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
439 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
440 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
441 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
442 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
443 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
444 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
445 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
446 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
447 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
448 { .vendor_id = 0, /* sentinel */ },
451 static const struct eth_dev_ops i40e_eth_dev_ops = {
452 .dev_configure = i40e_dev_configure,
453 .dev_start = i40e_dev_start,
454 .dev_stop = i40e_dev_stop,
455 .dev_close = i40e_dev_close,
456 .dev_reset = i40e_dev_reset,
457 .promiscuous_enable = i40e_dev_promiscuous_enable,
458 .promiscuous_disable = i40e_dev_promiscuous_disable,
459 .allmulticast_enable = i40e_dev_allmulticast_enable,
460 .allmulticast_disable = i40e_dev_allmulticast_disable,
461 .dev_set_link_up = i40e_dev_set_link_up,
462 .dev_set_link_down = i40e_dev_set_link_down,
463 .link_update = i40e_dev_link_update,
464 .stats_get = i40e_dev_stats_get,
465 .xstats_get = i40e_dev_xstats_get,
466 .xstats_get_names = i40e_dev_xstats_get_names,
467 .stats_reset = i40e_dev_stats_reset,
468 .xstats_reset = i40e_dev_stats_reset,
469 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
470 .fw_version_get = i40e_fw_version_get,
471 .dev_infos_get = i40e_dev_info_get,
472 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
473 .vlan_filter_set = i40e_vlan_filter_set,
474 .vlan_tpid_set = i40e_vlan_tpid_set,
475 .vlan_offload_set = i40e_vlan_offload_set,
476 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
477 .vlan_pvid_set = i40e_vlan_pvid_set,
478 .rx_queue_start = i40e_dev_rx_queue_start,
479 .rx_queue_stop = i40e_dev_rx_queue_stop,
480 .tx_queue_start = i40e_dev_tx_queue_start,
481 .tx_queue_stop = i40e_dev_tx_queue_stop,
482 .rx_queue_setup = i40e_dev_rx_queue_setup,
483 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
484 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
485 .rx_queue_release = i40e_dev_rx_queue_release,
486 .rx_queue_count = i40e_dev_rx_queue_count,
487 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
488 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
489 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
490 .tx_queue_setup = i40e_dev_tx_queue_setup,
491 .tx_queue_release = i40e_dev_tx_queue_release,
492 .dev_led_on = i40e_dev_led_on,
493 .dev_led_off = i40e_dev_led_off,
494 .flow_ctrl_get = i40e_flow_ctrl_get,
495 .flow_ctrl_set = i40e_flow_ctrl_set,
496 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
497 .mac_addr_add = i40e_macaddr_add,
498 .mac_addr_remove = i40e_macaddr_remove,
499 .reta_update = i40e_dev_rss_reta_update,
500 .reta_query = i40e_dev_rss_reta_query,
501 .rss_hash_update = i40e_dev_rss_hash_update,
502 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
503 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
504 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
505 .filter_ctrl = i40e_dev_filter_ctrl,
506 .rxq_info_get = i40e_rxq_info_get,
507 .txq_info_get = i40e_txq_info_get,
508 .mirror_rule_set = i40e_mirror_rule_set,
509 .mirror_rule_reset = i40e_mirror_rule_reset,
510 .timesync_enable = i40e_timesync_enable,
511 .timesync_disable = i40e_timesync_disable,
512 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
513 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
514 .get_dcb_info = i40e_dev_get_dcb_info,
515 .timesync_adjust_time = i40e_timesync_adjust_time,
516 .timesync_read_time = i40e_timesync_read_time,
517 .timesync_write_time = i40e_timesync_write_time,
518 .get_reg = i40e_get_regs,
519 .get_eeprom_length = i40e_get_eeprom_length,
520 .get_eeprom = i40e_get_eeprom,
521 .mac_addr_set = i40e_set_default_mac_addr,
522 .mtu_set = i40e_dev_mtu_set,
523 .tm_ops_get = i40e_tm_ops_get,
526 /* store statistics names and its offset in stats structure */
527 struct rte_i40e_xstats_name_off {
528 char name[RTE_ETH_XSTATS_NAME_SIZE];
532 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
533 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
534 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
535 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
536 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
537 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
538 rx_unknown_protocol)},
539 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
540 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
541 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
542 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
545 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
546 sizeof(rte_i40e_stats_strings[0]))
548 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
549 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
550 tx_dropped_link_down)},
551 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
552 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
554 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
555 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
557 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
559 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
561 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
562 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
563 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
564 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
565 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
566 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
568 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
570 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
572 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
574 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
576 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
578 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
580 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
582 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
583 mac_short_packet_dropped)},
584 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
586 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
587 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
588 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
590 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
592 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
594 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
596 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
598 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
600 {"rx_flow_director_atr_match_packets",
601 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
602 {"rx_flow_director_sb_match_packets",
603 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
604 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
606 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
608 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
610 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
614 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
615 sizeof(rte_i40e_hw_port_strings[0]))
617 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
618 {"xon_packets", offsetof(struct i40e_hw_port_stats,
620 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
624 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
625 sizeof(rte_i40e_rxq_prio_strings[0]))
627 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
628 {"xon_packets", offsetof(struct i40e_hw_port_stats,
630 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
632 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
633 priority_xon_2_xoff)},
636 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
637 sizeof(rte_i40e_txq_prio_strings[0]))
639 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
640 struct rte_pci_device *pci_dev)
642 return rte_eth_dev_pci_generic_probe(pci_dev,
643 sizeof(struct i40e_adapter), eth_i40e_dev_init);
646 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
648 return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
651 static struct rte_pci_driver rte_i40e_pmd = {
652 .id_table = pci_id_i40e_map,
653 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
654 RTE_PCI_DRV_IOVA_AS_VA,
655 .probe = eth_i40e_pci_probe,
656 .remove = eth_i40e_pci_remove,
660 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
661 struct rte_eth_link *link)
663 struct rte_eth_link *dst = link;
664 struct rte_eth_link *src = &(dev->data->dev_link);
666 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
667 *(uint64_t *)src) == 0)
674 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
675 struct rte_eth_link *link)
677 struct rte_eth_link *dst = &(dev->data->dev_link);
678 struct rte_eth_link *src = link;
680 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
681 *(uint64_t *)src) == 0)
687 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
688 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
689 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
691 #ifndef I40E_GLQF_ORT
692 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
694 #ifndef I40E_GLQF_PIT
695 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
697 #ifndef I40E_GLQF_L3_MAP
698 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
701 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
704 * Force global configuration for flexible payload
705 * to the first 16 bytes of the corresponding L2/L3/L4 paylod.
706 * This should be removed from code once proper
707 * configuration API is added to avoid configuration conflicts
708 * between ports of the same device.
710 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
711 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
712 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
715 * Initialize registers for parsing packet type of QinQ
716 * This should be removed from code once proper
717 * configuration API is added to avoid configuration conflicts
718 * between ports of the same device.
720 I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
721 I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
724 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
727 * Add a ethertype filter to drop all flow control frames transmitted
731 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
733 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
734 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
735 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
736 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
739 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
740 I40E_FLOW_CONTROL_ETHERTYPE, flags,
741 pf->main_vsi_seid, 0,
745 "Failed to add filter to drop flow control frames from VSIs.");
749 floating_veb_list_handler(__rte_unused const char *key,
750 const char *floating_veb_value,
754 unsigned int count = 0;
757 bool *vf_floating_veb = opaque;
759 while (isblank(*floating_veb_value))
760 floating_veb_value++;
762 /* Reset floating VEB configuration for VFs */
763 for (idx = 0; idx < I40E_MAX_VF; idx++)
764 vf_floating_veb[idx] = false;
768 while (isblank(*floating_veb_value))
769 floating_veb_value++;
770 if (*floating_veb_value == '\0')
773 idx = strtoul(floating_veb_value, &end, 10);
774 if (errno || end == NULL)
776 while (isblank(*end))
780 } else if ((*end == ';') || (*end == '\0')) {
782 if (min == I40E_MAX_VF)
784 if (max >= I40E_MAX_VF)
785 max = I40E_MAX_VF - 1;
786 for (idx = min; idx <= max; idx++) {
787 vf_floating_veb[idx] = true;
794 floating_veb_value = end + 1;
795 } while (*end != '\0');
804 config_vf_floating_veb(struct rte_devargs *devargs,
805 uint16_t floating_veb,
806 bool *vf_floating_veb)
808 struct rte_kvargs *kvlist;
810 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
814 /* All the VFs attach to the floating VEB by default
815 * when the floating VEB is enabled.
817 for (i = 0; i < I40E_MAX_VF; i++)
818 vf_floating_veb[i] = true;
823 kvlist = rte_kvargs_parse(devargs->args, NULL);
827 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
828 rte_kvargs_free(kvlist);
831 /* When the floating_veb_list parameter exists, all the VFs
832 * will attach to the legacy VEB firstly, then configure VFs
833 * to the floating VEB according to the floating_veb_list.
835 if (rte_kvargs_process(kvlist, floating_veb_list,
836 floating_veb_list_handler,
837 vf_floating_veb) < 0) {
838 rte_kvargs_free(kvlist);
841 rte_kvargs_free(kvlist);
845 i40e_check_floating_handler(__rte_unused const char *key,
847 __rte_unused void *opaque)
849 if (strcmp(value, "1"))
856 is_floating_veb_supported(struct rte_devargs *devargs)
858 struct rte_kvargs *kvlist;
859 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
864 kvlist = rte_kvargs_parse(devargs->args, NULL);
868 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
869 rte_kvargs_free(kvlist);
872 /* Floating VEB is enabled when there's key-value:
873 * enable_floating_veb=1
875 if (rte_kvargs_process(kvlist, floating_veb_key,
876 i40e_check_floating_handler, NULL) < 0) {
877 rte_kvargs_free(kvlist);
880 rte_kvargs_free(kvlist);
886 config_floating_veb(struct rte_eth_dev *dev)
888 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
889 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
890 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
892 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
894 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
896 is_floating_veb_supported(pci_dev->device.devargs);
897 config_vf_floating_veb(pci_dev->device.devargs,
899 pf->floating_veb_list);
901 pf->floating_veb = false;
905 #define I40E_L2_TAGS_S_TAG_SHIFT 1
906 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
909 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
911 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
912 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
913 char ethertype_hash_name[RTE_HASH_NAMESIZE];
916 struct rte_hash_parameters ethertype_hash_params = {
917 .name = ethertype_hash_name,
918 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
919 .key_len = sizeof(struct i40e_ethertype_filter_input),
920 .hash_func = rte_hash_crc,
921 .hash_func_init_val = 0,
922 .socket_id = rte_socket_id(),
925 /* Initialize ethertype filter rule list and hash */
926 TAILQ_INIT(ðertype_rule->ethertype_list);
927 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
928 "ethertype_%s", dev->device->name);
929 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
930 if (!ethertype_rule->hash_table) {
931 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
934 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
935 sizeof(struct i40e_ethertype_filter *) *
936 I40E_MAX_ETHERTYPE_FILTER_NUM,
938 if (!ethertype_rule->hash_map) {
940 "Failed to allocate memory for ethertype hash map!");
942 goto err_ethertype_hash_map_alloc;
947 err_ethertype_hash_map_alloc:
948 rte_hash_free(ethertype_rule->hash_table);
954 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
956 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
957 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
958 char tunnel_hash_name[RTE_HASH_NAMESIZE];
961 struct rte_hash_parameters tunnel_hash_params = {
962 .name = tunnel_hash_name,
963 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
964 .key_len = sizeof(struct i40e_tunnel_filter_input),
965 .hash_func = rte_hash_crc,
966 .hash_func_init_val = 0,
967 .socket_id = rte_socket_id(),
970 /* Initialize tunnel filter rule list and hash */
971 TAILQ_INIT(&tunnel_rule->tunnel_list);
972 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
973 "tunnel_%s", dev->device->name);
974 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
975 if (!tunnel_rule->hash_table) {
976 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
979 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
980 sizeof(struct i40e_tunnel_filter *) *
981 I40E_MAX_TUNNEL_FILTER_NUM,
983 if (!tunnel_rule->hash_map) {
985 "Failed to allocate memory for tunnel hash map!");
987 goto err_tunnel_hash_map_alloc;
992 err_tunnel_hash_map_alloc:
993 rte_hash_free(tunnel_rule->hash_table);
999 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1001 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1002 struct i40e_fdir_info *fdir_info = &pf->fdir;
1003 char fdir_hash_name[RTE_HASH_NAMESIZE];
1006 struct rte_hash_parameters fdir_hash_params = {
1007 .name = fdir_hash_name,
1008 .entries = I40E_MAX_FDIR_FILTER_NUM,
1009 .key_len = sizeof(struct rte_eth_fdir_input),
1010 .hash_func = rte_hash_crc,
1011 .hash_func_init_val = 0,
1012 .socket_id = rte_socket_id(),
1015 /* Initialize flow director filter rule list and hash */
1016 TAILQ_INIT(&fdir_info->fdir_list);
1017 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1018 "fdir_%s", dev->device->name);
1019 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1020 if (!fdir_info->hash_table) {
1021 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1024 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1025 sizeof(struct i40e_fdir_filter *) *
1026 I40E_MAX_FDIR_FILTER_NUM,
1028 if (!fdir_info->hash_map) {
1030 "Failed to allocate memory for fdir hash map!");
1032 goto err_fdir_hash_map_alloc;
1036 err_fdir_hash_map_alloc:
1037 rte_hash_free(fdir_info->hash_table);
1043 i40e_init_customized_info(struct i40e_pf *pf)
1047 /* Initialize customized pctype */
1048 for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1049 pf->customized_pctype[i].index = i;
1050 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1051 pf->customized_pctype[i].valid = false;
1054 pf->gtp_support = false;
1058 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1060 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1061 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1062 struct i40e_queue_regions *info = &pf->queue_region;
1065 for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1066 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1068 memset(info, 0, sizeof(struct i40e_queue_regions));
1072 eth_i40e_dev_init(struct rte_eth_dev *dev)
1074 struct rte_pci_device *pci_dev;
1075 struct rte_intr_handle *intr_handle;
1076 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1077 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1078 struct i40e_vsi *vsi;
1081 uint8_t aq_fail = 0;
1083 PMD_INIT_FUNC_TRACE();
1085 dev->dev_ops = &i40e_eth_dev_ops;
1086 dev->rx_pkt_burst = i40e_recv_pkts;
1087 dev->tx_pkt_burst = i40e_xmit_pkts;
1088 dev->tx_pkt_prepare = i40e_prep_pkts;
1090 /* for secondary processes, we don't initialise any further as primary
1091 * has already done this work. Only check we don't need a different
1093 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1094 i40e_set_rx_function(dev);
1095 i40e_set_tx_function(dev);
1098 i40e_set_default_ptype_table(dev);
1099 i40e_set_default_pctype_table(dev);
1100 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1101 intr_handle = &pci_dev->intr_handle;
1103 rte_eth_copy_pci_info(dev, pci_dev);
1105 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1106 pf->adapter->eth_dev = dev;
1107 pf->dev_data = dev->data;
1109 hw->back = I40E_PF_TO_ADAPTER(pf);
1110 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1113 "Hardware is not available, as address is NULL");
1117 hw->vendor_id = pci_dev->id.vendor_id;
1118 hw->device_id = pci_dev->id.device_id;
1119 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1120 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1121 hw->bus.device = pci_dev->addr.devid;
1122 hw->bus.func = pci_dev->addr.function;
1123 hw->adapter_stopped = 0;
1125 /* Make sure all is clean before doing PF reset */
1128 /* Initialize the hardware */
1131 /* Reset here to make sure all is clean for each PF */
1132 ret = i40e_pf_reset(hw);
1134 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1138 /* Initialize the shared code (base driver) */
1139 ret = i40e_init_shared_code(hw);
1141 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1146 * To work around the NVM issue, initialize registers
1147 * for flexible payload and packet type of QinQ by
1148 * software. It should be removed once issues are fixed
1151 i40e_GLQF_reg_init(hw);
1153 /* Initialize the input set for filters (hash and fd) to default value */
1154 i40e_filter_input_set_init(pf);
1156 /* Initialize the parameters for adminq */
1157 i40e_init_adminq_parameter(hw);
1158 ret = i40e_init_adminq(hw);
1159 if (ret != I40E_SUCCESS) {
1160 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1163 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1164 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1165 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1166 ((hw->nvm.version >> 12) & 0xf),
1167 ((hw->nvm.version >> 4) & 0xff),
1168 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1170 /* initialise the L3_MAP register */
1171 ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1174 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
1176 /* Need the special FW version to support floating VEB */
1177 config_floating_veb(dev);
1178 /* Clear PXE mode */
1179 i40e_clear_pxe_mode(hw);
1180 i40e_dev_sync_phy_type(hw);
1183 * On X710, performance number is far from the expectation on recent
1184 * firmware versions. The fix for this issue may not be integrated in
1185 * the following firmware version. So the workaround in software driver
1186 * is needed. It needs to modify the initial values of 3 internal only
1187 * registers. Note that the workaround can be removed when it is fixed
1188 * in firmware in the future.
1190 i40e_configure_registers(hw);
1192 /* Get hw capabilities */
1193 ret = i40e_get_cap(hw);
1194 if (ret != I40E_SUCCESS) {
1195 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1196 goto err_get_capabilities;
1199 /* Initialize parameters for PF */
1200 ret = i40e_pf_parameter_init(dev);
1202 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1203 goto err_parameter_init;
1206 /* Initialize the queue management */
1207 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1209 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1210 goto err_qp_pool_init;
1212 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1213 hw->func_caps.num_msix_vectors - 1);
1215 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1216 goto err_msix_pool_init;
1219 /* Initialize lan hmc */
1220 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1221 hw->func_caps.num_rx_qp, 0, 0);
1222 if (ret != I40E_SUCCESS) {
1223 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1224 goto err_init_lan_hmc;
1227 /* Configure lan hmc */
1228 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1229 if (ret != I40E_SUCCESS) {
1230 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1231 goto err_configure_lan_hmc;
1234 /* Get and check the mac address */
1235 i40e_get_mac_addr(hw, hw->mac.addr);
1236 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1237 PMD_INIT_LOG(ERR, "mac address is not valid");
1239 goto err_get_mac_addr;
1241 /* Copy the permanent MAC address */
1242 ether_addr_copy((struct ether_addr *) hw->mac.addr,
1243 (struct ether_addr *) hw->mac.perm_addr);
1245 /* Disable flow control */
1246 hw->fc.requested_mode = I40E_FC_NONE;
1247 i40e_set_fc(hw, &aq_fail, TRUE);
1249 /* Set the global registers with default ether type value */
1250 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1251 if (ret != I40E_SUCCESS) {
1253 "Failed to set the default outer VLAN ether type");
1254 goto err_setup_pf_switch;
1257 /* PF setup, which includes VSI setup */
1258 ret = i40e_pf_setup(pf);
1260 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1261 goto err_setup_pf_switch;
1264 /* reset all stats of the device, including pf and main vsi */
1265 i40e_dev_stats_reset(dev);
1269 /* Disable double vlan by default */
1270 i40e_vsi_config_double_vlan(vsi, FALSE);
1272 /* Disable S-TAG identification when floating_veb is disabled */
1273 if (!pf->floating_veb) {
1274 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1275 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1276 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1277 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1281 if (!vsi->max_macaddrs)
1282 len = ETHER_ADDR_LEN;
1284 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1286 /* Should be after VSI initialized */
1287 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1288 if (!dev->data->mac_addrs) {
1290 "Failed to allocated memory for storing mac address");
1293 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1294 &dev->data->mac_addrs[0]);
1296 /* Init dcb to sw mode by default */
1297 ret = i40e_dcb_init_configure(dev, TRUE);
1298 if (ret != I40E_SUCCESS) {
1299 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1300 pf->flags &= ~I40E_FLAG_DCB;
1302 /* Update HW struct after DCB configuration */
1305 /* initialize pf host driver to setup SRIOV resource if applicable */
1306 i40e_pf_host_init(dev);
1308 /* register callback func to eal lib */
1309 rte_intr_callback_register(intr_handle,
1310 i40e_dev_interrupt_handler, dev);
1312 /* configure and enable device interrupt */
1313 i40e_pf_config_irq0(hw, TRUE);
1314 i40e_pf_enable_irq0(hw);
1316 /* enable uio intr after callback register */
1317 rte_intr_enable(intr_handle);
1319 * Add an ethertype filter to drop all flow control frames transmitted
1320 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1323 i40e_add_tx_flow_control_drop_filter(pf);
1325 /* Set the max frame size to 0x2600 by default,
1326 * in case other drivers changed the default value.
1328 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1330 /* initialize mirror rule list */
1331 TAILQ_INIT(&pf->mirror_list);
1333 /* initialize Traffic Manager configuration */
1334 i40e_tm_conf_init(dev);
1336 /* Initialize customized information */
1337 i40e_init_customized_info(pf);
1339 ret = i40e_init_ethtype_filter_list(dev);
1341 goto err_init_ethtype_filter_list;
1342 ret = i40e_init_tunnel_filter_list(dev);
1344 goto err_init_tunnel_filter_list;
1345 ret = i40e_init_fdir_filter_list(dev);
1347 goto err_init_fdir_filter_list;
1349 /* initialize queue region configuration */
1350 i40e_init_queue_region_conf(dev);
1354 err_init_fdir_filter_list:
1355 rte_free(pf->tunnel.hash_table);
1356 rte_free(pf->tunnel.hash_map);
1357 err_init_tunnel_filter_list:
1358 rte_free(pf->ethertype.hash_table);
1359 rte_free(pf->ethertype.hash_map);
1360 err_init_ethtype_filter_list:
1361 rte_free(dev->data->mac_addrs);
1363 i40e_vsi_release(pf->main_vsi);
1364 err_setup_pf_switch:
1366 err_configure_lan_hmc:
1367 (void)i40e_shutdown_lan_hmc(hw);
1369 i40e_res_pool_destroy(&pf->msix_pool);
1371 i40e_res_pool_destroy(&pf->qp_pool);
1374 err_get_capabilities:
1375 (void)i40e_shutdown_adminq(hw);
1381 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1383 struct i40e_ethertype_filter *p_ethertype;
1384 struct i40e_ethertype_rule *ethertype_rule;
1386 ethertype_rule = &pf->ethertype;
1387 /* Remove all ethertype filter rules and hash */
1388 if (ethertype_rule->hash_map)
1389 rte_free(ethertype_rule->hash_map);
1390 if (ethertype_rule->hash_table)
1391 rte_hash_free(ethertype_rule->hash_table);
1393 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1394 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1395 p_ethertype, rules);
1396 rte_free(p_ethertype);
1401 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1403 struct i40e_tunnel_filter *p_tunnel;
1404 struct i40e_tunnel_rule *tunnel_rule;
1406 tunnel_rule = &pf->tunnel;
1407 /* Remove all tunnel director rules and hash */
1408 if (tunnel_rule->hash_map)
1409 rte_free(tunnel_rule->hash_map);
1410 if (tunnel_rule->hash_table)
1411 rte_hash_free(tunnel_rule->hash_table);
1413 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1414 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1420 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1422 struct i40e_fdir_filter *p_fdir;
1423 struct i40e_fdir_info *fdir_info;
1425 fdir_info = &pf->fdir;
1426 /* Remove all flow director rules and hash */
1427 if (fdir_info->hash_map)
1428 rte_free(fdir_info->hash_map);
1429 if (fdir_info->hash_table)
1430 rte_hash_free(fdir_info->hash_table);
1432 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1433 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1439 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1442 struct rte_pci_device *pci_dev;
1443 struct rte_intr_handle *intr_handle;
1445 struct i40e_filter_control_settings settings;
1446 struct rte_flow *p_flow;
1448 uint8_t aq_fail = 0;
1450 PMD_INIT_FUNC_TRACE();
1452 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1455 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1456 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1457 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1458 intr_handle = &pci_dev->intr_handle;
1460 if (hw->adapter_stopped == 0)
1461 i40e_dev_close(dev);
1463 dev->dev_ops = NULL;
1464 dev->rx_pkt_burst = NULL;
1465 dev->tx_pkt_burst = NULL;
1467 /* Clear PXE mode */
1468 i40e_clear_pxe_mode(hw);
1470 /* Unconfigure filter control */
1471 memset(&settings, 0, sizeof(settings));
1472 ret = i40e_set_filter_control(hw, &settings);
1474 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1477 /* Disable flow control */
1478 hw->fc.requested_mode = I40E_FC_NONE;
1479 i40e_set_fc(hw, &aq_fail, TRUE);
1481 /* uninitialize pf host driver */
1482 i40e_pf_host_uninit(dev);
1484 rte_free(dev->data->mac_addrs);
1485 dev->data->mac_addrs = NULL;
1487 /* disable uio intr before callback unregister */
1488 rte_intr_disable(intr_handle);
1490 /* register callback func to eal lib */
1491 rte_intr_callback_unregister(intr_handle,
1492 i40e_dev_interrupt_handler, dev);
1494 i40e_rm_ethtype_filter_list(pf);
1495 i40e_rm_tunnel_filter_list(pf);
1496 i40e_rm_fdir_filter_list(pf);
1498 /* Remove all flows */
1499 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1500 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1504 /* Remove all Traffic Manager configuration */
1505 i40e_tm_conf_uninit(dev);
1511 i40e_dev_configure(struct rte_eth_dev *dev)
1513 struct i40e_adapter *ad =
1514 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1515 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1516 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1517 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1520 ret = i40e_dev_sync_phy_type(hw);
1524 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1525 * bulk allocation or vector Rx preconditions we will reset it.
1527 ad->rx_bulk_alloc_allowed = true;
1528 ad->rx_vec_allowed = true;
1529 ad->tx_simple_allowed = true;
1530 ad->tx_vec_allowed = true;
1532 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1533 ret = i40e_fdir_setup(pf);
1534 if (ret != I40E_SUCCESS) {
1535 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1538 ret = i40e_fdir_configure(dev);
1540 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1544 i40e_fdir_teardown(pf);
1546 ret = i40e_dev_init_vlan(dev);
1551 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1552 * RSS setting have different requirements.
1553 * General PMD driver call sequence are NIC init, configure,
1554 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1555 * will try to lookup the VSI that specific queue belongs to if VMDQ
1556 * applicable. So, VMDQ setting has to be done before
1557 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1558 * For RSS setting, it will try to calculate actual configured RX queue
1559 * number, which will be available after rx_queue_setup(). dev_start()
1560 * function is good to place RSS setup.
1562 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1563 ret = i40e_vmdq_setup(dev);
1568 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1569 ret = i40e_dcb_setup(dev);
1571 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1576 TAILQ_INIT(&pf->flow_list);
1581 /* need to release vmdq resource if exists */
1582 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1583 i40e_vsi_release(pf->vmdq[i].vsi);
1584 pf->vmdq[i].vsi = NULL;
1589 /* need to release fdir resource if exists */
1590 i40e_fdir_teardown(pf);
1595 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1597 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1598 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1599 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1600 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1601 uint16_t msix_vect = vsi->msix_intr;
1604 for (i = 0; i < vsi->nb_qps; i++) {
1605 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1606 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1610 if (vsi->type != I40E_VSI_SRIOV) {
1611 if (!rte_intr_allow_others(intr_handle)) {
1612 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1613 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1615 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1618 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1619 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1621 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1626 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1627 vsi->user_param + (msix_vect - 1);
1629 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1630 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1632 I40E_WRITE_FLUSH(hw);
1636 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1637 int base_queue, int nb_queue,
1642 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1644 /* Bind all RX queues to allocated MSIX interrupt */
1645 for (i = 0; i < nb_queue; i++) {
1646 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1647 itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1648 ((base_queue + i + 1) <<
1649 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1650 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1651 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1653 if (i == nb_queue - 1)
1654 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1655 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1658 /* Write first RX queue to Link list register as the head element */
1659 if (vsi->type != I40E_VSI_SRIOV) {
1661 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1663 if (msix_vect == I40E_MISC_VEC_ID) {
1664 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1666 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1668 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1670 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1673 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1675 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1677 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1679 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1686 if (msix_vect == I40E_MISC_VEC_ID) {
1688 I40E_VPINT_LNKLST0(vsi->user_param),
1690 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1692 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1694 /* num_msix_vectors_vf needs to minus irq0 */
1695 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1696 vsi->user_param + (msix_vect - 1);
1698 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1700 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1702 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1706 I40E_WRITE_FLUSH(hw);
1710 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1712 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1713 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1714 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1715 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1716 uint16_t msix_vect = vsi->msix_intr;
1717 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1718 uint16_t queue_idx = 0;
1723 for (i = 0; i < vsi->nb_qps; i++) {
1724 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1725 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1728 /* INTENA flag is not auto-cleared for interrupt */
1729 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1730 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1731 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1732 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1733 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1735 /* VF bind interrupt */
1736 if (vsi->type == I40E_VSI_SRIOV) {
1737 __vsi_queues_bind_intr(vsi, msix_vect,
1738 vsi->base_queue, vsi->nb_qps,
1743 /* PF & VMDq bind interrupt */
1744 if (rte_intr_dp_is_en(intr_handle)) {
1745 if (vsi->type == I40E_VSI_MAIN) {
1748 } else if (vsi->type == I40E_VSI_VMDQ2) {
1749 struct i40e_vsi *main_vsi =
1750 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1751 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1756 for (i = 0; i < vsi->nb_used_qps; i++) {
1758 if (!rte_intr_allow_others(intr_handle))
1759 /* allow to share MISC_VEC_ID */
1760 msix_vect = I40E_MISC_VEC_ID;
1762 /* no enough msix_vect, map all to one */
1763 __vsi_queues_bind_intr(vsi, msix_vect,
1764 vsi->base_queue + i,
1765 vsi->nb_used_qps - i,
1767 for (; !!record && i < vsi->nb_used_qps; i++)
1768 intr_handle->intr_vec[queue_idx + i] =
1772 /* 1:1 queue/msix_vect mapping */
1773 __vsi_queues_bind_intr(vsi, msix_vect,
1774 vsi->base_queue + i, 1,
1777 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1785 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1787 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1788 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1789 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1790 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1791 uint16_t interval = i40e_calc_itr_interval(\
1792 RTE_LIBRTE_I40E_ITR_INTERVAL);
1793 uint16_t msix_intr, i;
1795 if (rte_intr_allow_others(intr_handle))
1796 for (i = 0; i < vsi->nb_msix; i++) {
1797 msix_intr = vsi->msix_intr + i;
1798 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1799 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1800 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1801 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1803 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1806 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1807 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1808 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1809 (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1811 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1813 I40E_WRITE_FLUSH(hw);
1817 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1819 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1820 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1821 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1822 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1823 uint16_t msix_intr, i;
1825 if (rte_intr_allow_others(intr_handle))
1826 for (i = 0; i < vsi->nb_msix; i++) {
1827 msix_intr = vsi->msix_intr + i;
1828 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1832 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1834 I40E_WRITE_FLUSH(hw);
1837 static inline uint8_t
1838 i40e_parse_link_speeds(uint16_t link_speeds)
1840 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1842 if (link_speeds & ETH_LINK_SPEED_40G)
1843 link_speed |= I40E_LINK_SPEED_40GB;
1844 if (link_speeds & ETH_LINK_SPEED_25G)
1845 link_speed |= I40E_LINK_SPEED_25GB;
1846 if (link_speeds & ETH_LINK_SPEED_20G)
1847 link_speed |= I40E_LINK_SPEED_20GB;
1848 if (link_speeds & ETH_LINK_SPEED_10G)
1849 link_speed |= I40E_LINK_SPEED_10GB;
1850 if (link_speeds & ETH_LINK_SPEED_1G)
1851 link_speed |= I40E_LINK_SPEED_1GB;
1852 if (link_speeds & ETH_LINK_SPEED_100M)
1853 link_speed |= I40E_LINK_SPEED_100MB;
1859 i40e_phy_conf_link(struct i40e_hw *hw,
1861 uint8_t force_speed,
1864 enum i40e_status_code status;
1865 struct i40e_aq_get_phy_abilities_resp phy_ab;
1866 struct i40e_aq_set_phy_config phy_conf;
1867 enum i40e_aq_phy_type cnt;
1868 uint32_t phy_type_mask = 0;
1870 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1871 I40E_AQ_PHY_FLAG_PAUSE_RX |
1872 I40E_AQ_PHY_FLAG_PAUSE_RX |
1873 I40E_AQ_PHY_FLAG_LOW_POWER;
1874 const uint8_t advt = I40E_LINK_SPEED_40GB |
1875 I40E_LINK_SPEED_25GB |
1876 I40E_LINK_SPEED_10GB |
1877 I40E_LINK_SPEED_1GB |
1878 I40E_LINK_SPEED_100MB;
1882 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1887 /* If link already up, no need to set up again */
1888 if (is_up && phy_ab.phy_type != 0)
1889 return I40E_SUCCESS;
1891 memset(&phy_conf, 0, sizeof(phy_conf));
1893 /* bits 0-2 use the values from get_phy_abilities_resp */
1895 abilities |= phy_ab.abilities & mask;
1897 /* update ablities and speed */
1898 if (abilities & I40E_AQ_PHY_AN_ENABLED)
1899 phy_conf.link_speed = advt;
1901 phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed;
1903 phy_conf.abilities = abilities;
1907 /* To enable link, phy_type mask needs to include each type */
1908 for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_MAX; cnt++)
1909 phy_type_mask |= 1 << cnt;
1911 /* use get_phy_abilities_resp value for the rest */
1912 phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
1913 phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
1914 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
1915 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
1916 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1917 phy_conf.eee_capability = phy_ab.eee_capability;
1918 phy_conf.eeer = phy_ab.eeer_val;
1919 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1921 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1922 phy_ab.abilities, phy_ab.link_speed);
1923 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
1924 phy_conf.abilities, phy_conf.link_speed);
1926 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1930 return I40E_SUCCESS;
1934 i40e_apply_link_speed(struct rte_eth_dev *dev)
1937 uint8_t abilities = 0;
1938 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1939 struct rte_eth_conf *conf = &dev->data->dev_conf;
1941 speed = i40e_parse_link_speeds(conf->link_speeds);
1942 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1943 if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1944 abilities |= I40E_AQ_PHY_AN_ENABLED;
1945 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1947 return i40e_phy_conf_link(hw, abilities, speed, true);
1951 i40e_dev_start(struct rte_eth_dev *dev)
1953 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1954 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1955 struct i40e_vsi *main_vsi = pf->main_vsi;
1957 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1958 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1959 uint32_t intr_vector = 0;
1960 struct i40e_vsi *vsi;
1962 hw->adapter_stopped = 0;
1964 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1966 "Invalid link_speeds for port %u, autonegotiation disabled",
1967 dev->data->port_id);
1971 rte_intr_disable(intr_handle);
1973 if ((rte_intr_cap_multiple(intr_handle) ||
1974 !RTE_ETH_DEV_SRIOV(dev).active) &&
1975 dev->data->dev_conf.intr_conf.rxq != 0) {
1976 intr_vector = dev->data->nb_rx_queues;
1977 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1982 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1983 intr_handle->intr_vec =
1984 rte_zmalloc("intr_vec",
1985 dev->data->nb_rx_queues * sizeof(int),
1987 if (!intr_handle->intr_vec) {
1989 "Failed to allocate %d rx_queues intr_vec",
1990 dev->data->nb_rx_queues);
1995 /* Initialize VSI */
1996 ret = i40e_dev_rxtx_init(pf);
1997 if (ret != I40E_SUCCESS) {
1998 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2002 /* Map queues with MSIX interrupt */
2003 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2004 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2005 i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2006 i40e_vsi_enable_queues_intr(main_vsi);
2008 /* Map VMDQ VSI queues with MSIX interrupt */
2009 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2010 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2011 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2012 I40E_ITR_INDEX_DEFAULT);
2013 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2016 /* enable FDIR MSIX interrupt */
2017 if (pf->fdir.fdir_vsi) {
2018 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2019 I40E_ITR_INDEX_NONE);
2020 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2023 /* Enable all queues which have been configured */
2024 ret = i40e_dev_switch_queues(pf, TRUE);
2025 if (ret != I40E_SUCCESS) {
2026 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2030 /* Enable receiving broadcast packets */
2031 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2032 if (ret != I40E_SUCCESS)
2033 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2035 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2036 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2038 if (ret != I40E_SUCCESS)
2039 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2042 /* Enable the VLAN promiscuous mode. */
2044 for (i = 0; i < pf->vf_num; i++) {
2045 vsi = pf->vfs[i].vsi;
2046 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2051 /* Apply link configure */
2052 if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
2053 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
2054 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
2055 ETH_LINK_SPEED_40G)) {
2056 PMD_DRV_LOG(ERR, "Invalid link setting");
2059 ret = i40e_apply_link_speed(dev);
2060 if (I40E_SUCCESS != ret) {
2061 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2065 if (!rte_intr_allow_others(intr_handle)) {
2066 rte_intr_callback_unregister(intr_handle,
2067 i40e_dev_interrupt_handler,
2069 /* configure and enable device interrupt */
2070 i40e_pf_config_irq0(hw, FALSE);
2071 i40e_pf_enable_irq0(hw);
2073 if (dev->data->dev_conf.intr_conf.lsc != 0)
2075 "lsc won't enable because of no intr multiplex");
2077 ret = i40e_aq_set_phy_int_mask(hw,
2078 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2079 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2080 I40E_AQ_EVENT_MEDIA_NA), NULL);
2081 if (ret != I40E_SUCCESS)
2082 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2084 /* Call get_link_info aq commond to enable/disable LSE */
2085 i40e_dev_link_update(dev, 0);
2088 /* enable uio intr after callback register */
2089 rte_intr_enable(intr_handle);
2091 i40e_filter_restore(pf);
2093 if (pf->tm_conf.root && !pf->tm_conf.committed)
2094 PMD_DRV_LOG(WARNING,
2095 "please call hierarchy_commit() "
2096 "before starting the port");
2098 return I40E_SUCCESS;
2101 i40e_dev_switch_queues(pf, FALSE);
2102 i40e_dev_clear_queues(dev);
2108 i40e_dev_stop(struct rte_eth_dev *dev)
2110 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2111 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2112 struct i40e_vsi *main_vsi = pf->main_vsi;
2113 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2114 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2117 if (hw->adapter_stopped == 1)
2119 /* Disable all queues */
2120 i40e_dev_switch_queues(pf, FALSE);
2122 /* un-map queues with interrupt registers */
2123 i40e_vsi_disable_queues_intr(main_vsi);
2124 i40e_vsi_queues_unbind_intr(main_vsi);
2126 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2127 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2128 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2131 if (pf->fdir.fdir_vsi) {
2132 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2133 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2135 /* Clear all queues and release memory */
2136 i40e_dev_clear_queues(dev);
2139 i40e_dev_set_link_down(dev);
2141 if (!rte_intr_allow_others(intr_handle))
2142 /* resume to the default handler */
2143 rte_intr_callback_register(intr_handle,
2144 i40e_dev_interrupt_handler,
2147 /* Clean datapath event and queue/vec mapping */
2148 rte_intr_efd_disable(intr_handle);
2149 if (intr_handle->intr_vec) {
2150 rte_free(intr_handle->intr_vec);
2151 intr_handle->intr_vec = NULL;
2154 /* reset hierarchy commit */
2155 pf->tm_conf.committed = false;
2157 /* Remove all the queue region configuration */
2158 i40e_flush_queue_region_all_conf(dev, hw, pf, 0);
2160 hw->adapter_stopped = 1;
2164 i40e_dev_close(struct rte_eth_dev *dev)
2166 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2167 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2168 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2169 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2170 struct i40e_mirror_rule *p_mirror;
2175 PMD_INIT_FUNC_TRACE();
2179 /* Remove all mirror rules */
2180 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2181 ret = i40e_aq_del_mirror_rule(hw,
2182 pf->main_vsi->veb->seid,
2183 p_mirror->rule_type,
2185 p_mirror->num_entries,
2188 PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2189 "status = %d, aq_err = %d.", ret,
2190 hw->aq.asq_last_status);
2192 /* remove mirror software resource anyway */
2193 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2195 pf->nb_mirror_rule--;
2198 i40e_dev_free_queues(dev);
2200 /* Disable interrupt */
2201 i40e_pf_disable_irq0(hw);
2202 rte_intr_disable(intr_handle);
2204 /* shutdown and destroy the HMC */
2205 i40e_shutdown_lan_hmc(hw);
2207 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2208 i40e_vsi_release(pf->vmdq[i].vsi);
2209 pf->vmdq[i].vsi = NULL;
2214 /* release all the existing VSIs and VEBs */
2215 i40e_fdir_teardown(pf);
2216 i40e_vsi_release(pf->main_vsi);
2218 /* shutdown the adminq */
2219 i40e_aq_queue_shutdown(hw, true);
2220 i40e_shutdown_adminq(hw);
2222 i40e_res_pool_destroy(&pf->qp_pool);
2223 i40e_res_pool_destroy(&pf->msix_pool);
2225 /* force a PF reset to clean anything leftover */
2226 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2227 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2228 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2229 I40E_WRITE_FLUSH(hw);
2233 * Reset PF device only to re-initialize resources in PMD layer
2236 i40e_dev_reset(struct rte_eth_dev *dev)
2240 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2241 * its VF to make them align with it. The detailed notification
2242 * mechanism is PMD specific. As to i40e PF, it is rather complex.
2243 * To avoid unexpected behavior in VF, currently reset of PF with
2244 * SR-IOV activation is not supported. It might be supported later.
2246 if (dev->data->sriov.active)
2249 ret = eth_i40e_dev_uninit(dev);
2253 ret = eth_i40e_dev_init(dev);
2259 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2261 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2262 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2263 struct i40e_vsi *vsi = pf->main_vsi;
2266 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2268 if (status != I40E_SUCCESS)
2269 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2271 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2273 if (status != I40E_SUCCESS)
2274 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2279 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2281 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2282 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2283 struct i40e_vsi *vsi = pf->main_vsi;
2286 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2288 if (status != I40E_SUCCESS)
2289 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2291 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2293 if (status != I40E_SUCCESS)
2294 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2298 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2300 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2301 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2302 struct i40e_vsi *vsi = pf->main_vsi;
2305 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2306 if (ret != I40E_SUCCESS)
2307 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2311 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2313 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2314 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2315 struct i40e_vsi *vsi = pf->main_vsi;
2318 if (dev->data->promiscuous == 1)
2319 return; /* must remain in all_multicast mode */
2321 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2322 vsi->seid, FALSE, NULL);
2323 if (ret != I40E_SUCCESS)
2324 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2328 * Set device link up.
2331 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2333 /* re-apply link speed setting */
2334 return i40e_apply_link_speed(dev);
2338 * Set device link down.
2341 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2343 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2344 uint8_t abilities = 0;
2345 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2347 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2348 return i40e_phy_conf_link(hw, abilities, speed, false);
2352 i40e_dev_link_update(struct rte_eth_dev *dev,
2353 int wait_to_complete)
2355 #define CHECK_INTERVAL 100 /* 100ms */
2356 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2357 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2358 struct i40e_link_status link_status;
2359 struct rte_eth_link link, old;
2361 unsigned rep_cnt = MAX_REPEAT_TIME;
2362 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2364 memset(&link, 0, sizeof(link));
2365 memset(&old, 0, sizeof(old));
2366 memset(&link_status, 0, sizeof(link_status));
2367 rte_i40e_dev_atomic_read_link_status(dev, &old);
2370 /* Get link status information from hardware */
2371 status = i40e_aq_get_link_info(hw, enable_lse,
2372 &link_status, NULL);
2373 if (status != I40E_SUCCESS) {
2374 link.link_speed = ETH_SPEED_NUM_100M;
2375 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2376 PMD_DRV_LOG(ERR, "Failed to get link info");
2380 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2381 if (!wait_to_complete || link.link_status)
2384 rte_delay_ms(CHECK_INTERVAL);
2385 } while (--rep_cnt);
2387 if (!link.link_status)
2390 /* i40e uses full duplex only */
2391 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2393 /* Parse the link status */
2394 switch (link_status.link_speed) {
2395 case I40E_LINK_SPEED_100MB:
2396 link.link_speed = ETH_SPEED_NUM_100M;
2398 case I40E_LINK_SPEED_1GB:
2399 link.link_speed = ETH_SPEED_NUM_1G;
2401 case I40E_LINK_SPEED_10GB:
2402 link.link_speed = ETH_SPEED_NUM_10G;
2404 case I40E_LINK_SPEED_20GB:
2405 link.link_speed = ETH_SPEED_NUM_20G;
2407 case I40E_LINK_SPEED_25GB:
2408 link.link_speed = ETH_SPEED_NUM_25G;
2410 case I40E_LINK_SPEED_40GB:
2411 link.link_speed = ETH_SPEED_NUM_40G;
2414 link.link_speed = ETH_SPEED_NUM_100M;
2418 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2419 ETH_LINK_SPEED_FIXED);
2422 rte_i40e_dev_atomic_write_link_status(dev, &link);
2423 if (link.link_status == old.link_status)
2426 i40e_notify_all_vfs_link_status(dev);
2431 /* Get all the statistics of a VSI */
2433 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2435 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2436 struct i40e_eth_stats *nes = &vsi->eth_stats;
2437 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2438 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2440 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2441 vsi->offset_loaded, &oes->rx_bytes,
2443 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2444 vsi->offset_loaded, &oes->rx_unicast,
2446 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2447 vsi->offset_loaded, &oes->rx_multicast,
2448 &nes->rx_multicast);
2449 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2450 vsi->offset_loaded, &oes->rx_broadcast,
2451 &nes->rx_broadcast);
2452 /* exclude CRC bytes */
2453 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2454 nes->rx_broadcast) * ETHER_CRC_LEN;
2456 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2457 &oes->rx_discards, &nes->rx_discards);
2458 /* GLV_REPC not supported */
2459 /* GLV_RMPC not supported */
2460 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2461 &oes->rx_unknown_protocol,
2462 &nes->rx_unknown_protocol);
2463 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2464 vsi->offset_loaded, &oes->tx_bytes,
2466 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2467 vsi->offset_loaded, &oes->tx_unicast,
2469 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2470 vsi->offset_loaded, &oes->tx_multicast,
2471 &nes->tx_multicast);
2472 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2473 vsi->offset_loaded, &oes->tx_broadcast,
2474 &nes->tx_broadcast);
2475 /* GLV_TDPC not supported */
2476 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2477 &oes->tx_errors, &nes->tx_errors);
2478 vsi->offset_loaded = true;
2480 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2482 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2483 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2484 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2485 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2486 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2487 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2488 nes->rx_unknown_protocol);
2489 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2490 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2491 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2492 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2493 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2494 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2495 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2500 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2503 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2504 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2506 /* Get rx/tx bytes of internal transfer packets */
2507 i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2508 I40E_GLV_GORCL(hw->port),
2510 &pf->internal_stats_offset.rx_bytes,
2511 &pf->internal_stats.rx_bytes);
2513 i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2514 I40E_GLV_GOTCL(hw->port),
2516 &pf->internal_stats_offset.tx_bytes,
2517 &pf->internal_stats.tx_bytes);
2518 /* Get total internal rx packet count */
2519 i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2520 I40E_GLV_UPRCL(hw->port),
2522 &pf->internal_stats_offset.rx_unicast,
2523 &pf->internal_stats.rx_unicast);
2524 i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2525 I40E_GLV_MPRCL(hw->port),
2527 &pf->internal_stats_offset.rx_multicast,
2528 &pf->internal_stats.rx_multicast);
2529 i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2530 I40E_GLV_BPRCL(hw->port),
2532 &pf->internal_stats_offset.rx_broadcast,
2533 &pf->internal_stats.rx_broadcast);
2535 /* exclude CRC size */
2536 pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2537 pf->internal_stats.rx_multicast +
2538 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2540 /* Get statistics of struct i40e_eth_stats */
2541 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2542 I40E_GLPRT_GORCL(hw->port),
2543 pf->offset_loaded, &os->eth.rx_bytes,
2545 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2546 I40E_GLPRT_UPRCL(hw->port),
2547 pf->offset_loaded, &os->eth.rx_unicast,
2548 &ns->eth.rx_unicast);
2549 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2550 I40E_GLPRT_MPRCL(hw->port),
2551 pf->offset_loaded, &os->eth.rx_multicast,
2552 &ns->eth.rx_multicast);
2553 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2554 I40E_GLPRT_BPRCL(hw->port),
2555 pf->offset_loaded, &os->eth.rx_broadcast,
2556 &ns->eth.rx_broadcast);
2557 /* Workaround: CRC size should not be included in byte statistics,
2558 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2560 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2561 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2563 /* Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2564 * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negtive
2567 if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2568 ns->eth.rx_bytes = 0;
2569 /* exlude internal rx bytes */
2571 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2573 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2574 pf->offset_loaded, &os->eth.rx_discards,
2575 &ns->eth.rx_discards);
2576 /* GLPRT_REPC not supported */
2577 /* GLPRT_RMPC not supported */
2578 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2580 &os->eth.rx_unknown_protocol,
2581 &ns->eth.rx_unknown_protocol);
2582 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2583 I40E_GLPRT_GOTCL(hw->port),
2584 pf->offset_loaded, &os->eth.tx_bytes,
2586 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2587 I40E_GLPRT_UPTCL(hw->port),
2588 pf->offset_loaded, &os->eth.tx_unicast,
2589 &ns->eth.tx_unicast);
2590 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2591 I40E_GLPRT_MPTCL(hw->port),
2592 pf->offset_loaded, &os->eth.tx_multicast,
2593 &ns->eth.tx_multicast);
2594 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2595 I40E_GLPRT_BPTCL(hw->port),
2596 pf->offset_loaded, &os->eth.tx_broadcast,
2597 &ns->eth.tx_broadcast);
2598 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2599 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2601 /* exclude internal tx bytes */
2602 if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2603 ns->eth.tx_bytes = 0;
2605 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2607 /* GLPRT_TEPC not supported */
2609 /* additional port specific stats */
2610 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2611 pf->offset_loaded, &os->tx_dropped_link_down,
2612 &ns->tx_dropped_link_down);
2613 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2614 pf->offset_loaded, &os->crc_errors,
2616 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2617 pf->offset_loaded, &os->illegal_bytes,
2618 &ns->illegal_bytes);
2619 /* GLPRT_ERRBC not supported */
2620 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2621 pf->offset_loaded, &os->mac_local_faults,
2622 &ns->mac_local_faults);
2623 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2624 pf->offset_loaded, &os->mac_remote_faults,
2625 &ns->mac_remote_faults);
2626 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2627 pf->offset_loaded, &os->rx_length_errors,
2628 &ns->rx_length_errors);
2629 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2630 pf->offset_loaded, &os->link_xon_rx,
2632 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2633 pf->offset_loaded, &os->link_xoff_rx,
2635 for (i = 0; i < 8; i++) {
2636 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2638 &os->priority_xon_rx[i],
2639 &ns->priority_xon_rx[i]);
2640 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2642 &os->priority_xoff_rx[i],
2643 &ns->priority_xoff_rx[i]);
2645 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2646 pf->offset_loaded, &os->link_xon_tx,
2648 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2649 pf->offset_loaded, &os->link_xoff_tx,
2651 for (i = 0; i < 8; i++) {
2652 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2654 &os->priority_xon_tx[i],
2655 &ns->priority_xon_tx[i]);
2656 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2658 &os->priority_xoff_tx[i],
2659 &ns->priority_xoff_tx[i]);
2660 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2662 &os->priority_xon_2_xoff[i],
2663 &ns->priority_xon_2_xoff[i]);
2665 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2666 I40E_GLPRT_PRC64L(hw->port),
2667 pf->offset_loaded, &os->rx_size_64,
2669 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2670 I40E_GLPRT_PRC127L(hw->port),
2671 pf->offset_loaded, &os->rx_size_127,
2673 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2674 I40E_GLPRT_PRC255L(hw->port),
2675 pf->offset_loaded, &os->rx_size_255,
2677 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2678 I40E_GLPRT_PRC511L(hw->port),
2679 pf->offset_loaded, &os->rx_size_511,
2681 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2682 I40E_GLPRT_PRC1023L(hw->port),
2683 pf->offset_loaded, &os->rx_size_1023,
2685 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2686 I40E_GLPRT_PRC1522L(hw->port),
2687 pf->offset_loaded, &os->rx_size_1522,
2689 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2690 I40E_GLPRT_PRC9522L(hw->port),
2691 pf->offset_loaded, &os->rx_size_big,
2693 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2694 pf->offset_loaded, &os->rx_undersize,
2696 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2697 pf->offset_loaded, &os->rx_fragments,
2699 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2700 pf->offset_loaded, &os->rx_oversize,
2702 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2703 pf->offset_loaded, &os->rx_jabber,
2705 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2706 I40E_GLPRT_PTC64L(hw->port),
2707 pf->offset_loaded, &os->tx_size_64,
2709 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2710 I40E_GLPRT_PTC127L(hw->port),
2711 pf->offset_loaded, &os->tx_size_127,
2713 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2714 I40E_GLPRT_PTC255L(hw->port),
2715 pf->offset_loaded, &os->tx_size_255,
2717 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2718 I40E_GLPRT_PTC511L(hw->port),
2719 pf->offset_loaded, &os->tx_size_511,
2721 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2722 I40E_GLPRT_PTC1023L(hw->port),
2723 pf->offset_loaded, &os->tx_size_1023,
2725 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2726 I40E_GLPRT_PTC1522L(hw->port),
2727 pf->offset_loaded, &os->tx_size_1522,
2729 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2730 I40E_GLPRT_PTC9522L(hw->port),
2731 pf->offset_loaded, &os->tx_size_big,
2733 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2735 &os->fd_sb_match, &ns->fd_sb_match);
2736 /* GLPRT_MSPDC not supported */
2737 /* GLPRT_XEC not supported */
2739 pf->offset_loaded = true;
2742 i40e_update_vsi_stats(pf->main_vsi);
2745 /* Get all statistics of a port */
2747 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2749 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2750 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2751 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2754 /* call read registers - updates values, now write them to struct */
2755 i40e_read_stats_registers(pf, hw);
2757 stats->ipackets = ns->eth.rx_unicast +
2758 ns->eth.rx_multicast +
2759 ns->eth.rx_broadcast -
2760 ns->eth.rx_discards -
2761 pf->main_vsi->eth_stats.rx_discards;
2762 stats->opackets = ns->eth.tx_unicast +
2763 ns->eth.tx_multicast +
2764 ns->eth.tx_broadcast;
2765 stats->ibytes = ns->eth.rx_bytes;
2766 stats->obytes = ns->eth.tx_bytes;
2767 stats->oerrors = ns->eth.tx_errors +
2768 pf->main_vsi->eth_stats.tx_errors;
2771 stats->imissed = ns->eth.rx_discards +
2772 pf->main_vsi->eth_stats.rx_discards;
2773 stats->ierrors = ns->crc_errors +
2774 ns->rx_length_errors + ns->rx_undersize +
2775 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2777 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2778 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
2779 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
2780 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
2781 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
2782 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
2783 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2784 ns->eth.rx_unknown_protocol);
2785 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
2786 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
2787 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
2788 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
2789 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
2790 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
2792 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
2793 ns->tx_dropped_link_down);
2794 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
2795 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
2797 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
2798 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
2799 ns->mac_local_faults);
2800 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
2801 ns->mac_remote_faults);
2802 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
2803 ns->rx_length_errors);
2804 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
2805 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
2806 for (i = 0; i < 8; i++) {
2807 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
2808 i, ns->priority_xon_rx[i]);
2809 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
2810 i, ns->priority_xoff_rx[i]);
2812 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
2813 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
2814 for (i = 0; i < 8; i++) {
2815 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
2816 i, ns->priority_xon_tx[i]);
2817 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
2818 i, ns->priority_xoff_tx[i]);
2819 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
2820 i, ns->priority_xon_2_xoff[i]);
2822 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
2823 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
2824 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
2825 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
2826 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
2827 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
2828 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
2829 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
2830 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
2831 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
2832 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
2833 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
2834 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
2835 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
2836 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
2837 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
2838 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
2839 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
2840 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2841 ns->mac_short_packet_dropped);
2842 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
2843 ns->checksum_error);
2844 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
2845 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2849 /* Reset the statistics */
2851 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2853 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2854 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2856 /* Mark PF and VSI stats to update the offset, aka "reset" */
2857 pf->offset_loaded = false;
2859 pf->main_vsi->offset_loaded = false;
2861 /* read the stats, reading current register values into offset */
2862 i40e_read_stats_registers(pf, hw);
2866 i40e_xstats_calc_num(void)
2868 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2869 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2870 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2873 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2874 struct rte_eth_xstat_name *xstats_names,
2875 __rte_unused unsigned limit)
2880 if (xstats_names == NULL)
2881 return i40e_xstats_calc_num();
2883 /* Note: limit checked in rte_eth_xstats_names() */
2885 /* Get stats from i40e_eth_stats struct */
2886 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2887 snprintf(xstats_names[count].name,
2888 sizeof(xstats_names[count].name),
2889 "%s", rte_i40e_stats_strings[i].name);
2893 /* Get individiual stats from i40e_hw_port struct */
2894 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2895 snprintf(xstats_names[count].name,
2896 sizeof(xstats_names[count].name),
2897 "%s", rte_i40e_hw_port_strings[i].name);
2901 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2902 for (prio = 0; prio < 8; prio++) {
2903 snprintf(xstats_names[count].name,
2904 sizeof(xstats_names[count].name),
2905 "rx_priority%u_%s", prio,
2906 rte_i40e_rxq_prio_strings[i].name);
2911 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2912 for (prio = 0; prio < 8; prio++) {
2913 snprintf(xstats_names[count].name,
2914 sizeof(xstats_names[count].name),
2915 "tx_priority%u_%s", prio,
2916 rte_i40e_txq_prio_strings[i].name);
2924 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2927 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2928 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2929 unsigned i, count, prio;
2930 struct i40e_hw_port_stats *hw_stats = &pf->stats;
2932 count = i40e_xstats_calc_num();
2936 i40e_read_stats_registers(pf, hw);
2943 /* Get stats from i40e_eth_stats struct */
2944 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2945 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2946 rte_i40e_stats_strings[i].offset);
2947 xstats[count].id = count;
2951 /* Get individiual stats from i40e_hw_port struct */
2952 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2953 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2954 rte_i40e_hw_port_strings[i].offset);
2955 xstats[count].id = count;
2959 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2960 for (prio = 0; prio < 8; prio++) {
2961 xstats[count].value =
2962 *(uint64_t *)(((char *)hw_stats) +
2963 rte_i40e_rxq_prio_strings[i].offset +
2964 (sizeof(uint64_t) * prio));
2965 xstats[count].id = count;
2970 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2971 for (prio = 0; prio < 8; prio++) {
2972 xstats[count].value =
2973 *(uint64_t *)(((char *)hw_stats) +
2974 rte_i40e_txq_prio_strings[i].offset +
2975 (sizeof(uint64_t) * prio));
2976 xstats[count].id = count;
2985 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2986 __rte_unused uint16_t queue_id,
2987 __rte_unused uint8_t stat_idx,
2988 __rte_unused uint8_t is_rx)
2990 PMD_INIT_FUNC_TRACE();
2996 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2998 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3004 full_ver = hw->nvm.oem_ver;
3005 ver = (u8)(full_ver >> 24);
3006 build = (u16)((full_ver >> 8) & 0xffff);
3007 patch = (u8)(full_ver & 0xff);
3009 ret = snprintf(fw_version, fw_size,
3010 "%d.%d%d 0x%08x %d.%d.%d",
3011 ((hw->nvm.version >> 12) & 0xf),
3012 ((hw->nvm.version >> 4) & 0xff),
3013 (hw->nvm.version & 0xf), hw->nvm.eetrack,
3016 ret += 1; /* add the size of '\0' */
3017 if (fw_size < (u32)ret)
3024 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3026 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3027 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3028 struct i40e_vsi *vsi = pf->main_vsi;
3029 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3031 dev_info->pci_dev = pci_dev;
3032 dev_info->max_rx_queues = vsi->nb_qps;
3033 dev_info->max_tx_queues = vsi->nb_qps;
3034 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3035 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3036 dev_info->max_mac_addrs = vsi->max_macaddrs;
3037 dev_info->max_vfs = pci_dev->max_vfs;
3038 dev_info->rx_offload_capa =
3039 DEV_RX_OFFLOAD_VLAN_STRIP |
3040 DEV_RX_OFFLOAD_QINQ_STRIP |
3041 DEV_RX_OFFLOAD_IPV4_CKSUM |
3042 DEV_RX_OFFLOAD_UDP_CKSUM |
3043 DEV_RX_OFFLOAD_TCP_CKSUM;
3044 dev_info->tx_offload_capa =
3045 DEV_TX_OFFLOAD_VLAN_INSERT |
3046 DEV_TX_OFFLOAD_QINQ_INSERT |
3047 DEV_TX_OFFLOAD_IPV4_CKSUM |
3048 DEV_TX_OFFLOAD_UDP_CKSUM |
3049 DEV_TX_OFFLOAD_TCP_CKSUM |
3050 DEV_TX_OFFLOAD_SCTP_CKSUM |
3051 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3052 DEV_TX_OFFLOAD_TCP_TSO |
3053 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3054 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3055 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3056 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
3057 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3059 dev_info->reta_size = pf->hash_lut_size;
3060 dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3062 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3064 .pthresh = I40E_DEFAULT_RX_PTHRESH,
3065 .hthresh = I40E_DEFAULT_RX_HTHRESH,
3066 .wthresh = I40E_DEFAULT_RX_WTHRESH,
3068 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3072 dev_info->default_txconf = (struct rte_eth_txconf) {
3074 .pthresh = I40E_DEFAULT_TX_PTHRESH,
3075 .hthresh = I40E_DEFAULT_TX_HTHRESH,
3076 .wthresh = I40E_DEFAULT_TX_WTHRESH,
3078 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3079 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3080 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3081 ETH_TXQ_FLAGS_NOOFFLOADS,
3084 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3085 .nb_max = I40E_MAX_RING_DESC,
3086 .nb_min = I40E_MIN_RING_DESC,
3087 .nb_align = I40E_ALIGN_RING_DESC,
3090 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3091 .nb_max = I40E_MAX_RING_DESC,
3092 .nb_min = I40E_MIN_RING_DESC,
3093 .nb_align = I40E_ALIGN_RING_DESC,
3094 .nb_seg_max = I40E_TX_MAX_SEG,
3095 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3098 if (pf->flags & I40E_FLAG_VMDQ) {
3099 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3100 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3101 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3102 pf->max_nb_vmdq_vsi;
3103 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3104 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3105 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3108 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
3110 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3111 else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
3113 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3116 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3120 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3122 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3123 struct i40e_vsi *vsi = pf->main_vsi;
3124 PMD_INIT_FUNC_TRACE();
3127 return i40e_vsi_add_vlan(vsi, vlan_id);
3129 return i40e_vsi_delete_vlan(vsi, vlan_id);
3133 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3134 enum rte_vlan_type vlan_type,
3135 uint16_t tpid, int qinq)
3137 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3140 uint16_t reg_id = 3;
3144 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3148 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3150 if (ret != I40E_SUCCESS) {
3152 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3157 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3160 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3161 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3162 if (reg_r == reg_w) {
3163 PMD_DRV_LOG(DEBUG, "No need to write");
3167 ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3169 if (ret != I40E_SUCCESS) {
3171 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3176 "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3183 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3184 enum rte_vlan_type vlan_type,
3187 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3188 int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
3191 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3192 vlan_type != ETH_VLAN_TYPE_OUTER) ||
3193 (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3195 "Unsupported vlan type.");
3198 /* 802.1ad frames ability is added in NVM API 1.7*/
3199 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3201 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3202 hw->first_tag = rte_cpu_to_le_16(tpid);
3203 else if (vlan_type == ETH_VLAN_TYPE_INNER)
3204 hw->second_tag = rte_cpu_to_le_16(tpid);
3206 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3207 hw->second_tag = rte_cpu_to_le_16(tpid);
3209 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3210 if (ret != I40E_SUCCESS) {
3212 "Set switch config failed aq_err: %d",
3213 hw->aq.asq_last_status);
3217 /* If NVM API < 1.7, keep the register setting */
3218 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3225 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3227 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3228 struct i40e_vsi *vsi = pf->main_vsi;
3230 if (mask & ETH_VLAN_FILTER_MASK) {
3231 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3232 i40e_vsi_config_vlan_filter(vsi, TRUE);
3234 i40e_vsi_config_vlan_filter(vsi, FALSE);
3237 if (mask & ETH_VLAN_STRIP_MASK) {
3238 /* Enable or disable VLAN stripping */
3239 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3240 i40e_vsi_config_vlan_stripping(vsi, TRUE);
3242 i40e_vsi_config_vlan_stripping(vsi, FALSE);
3245 if (mask & ETH_VLAN_EXTEND_MASK) {
3246 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3247 i40e_vsi_config_double_vlan(vsi, TRUE);
3248 /* Set global registers with default ethertype. */
3249 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3251 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3255 i40e_vsi_config_double_vlan(vsi, FALSE);
3262 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3263 __rte_unused uint16_t queue,
3264 __rte_unused int on)
3266 PMD_INIT_FUNC_TRACE();
3270 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3272 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3273 struct i40e_vsi *vsi = pf->main_vsi;
3274 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3275 struct i40e_vsi_vlan_pvid_info info;
3277 memset(&info, 0, sizeof(info));
3280 info.config.pvid = pvid;
3282 info.config.reject.tagged =
3283 data->dev_conf.txmode.hw_vlan_reject_tagged;
3284 info.config.reject.untagged =
3285 data->dev_conf.txmode.hw_vlan_reject_untagged;
3288 return i40e_vsi_vlan_pvid_set(vsi, &info);
3292 i40e_dev_led_on(struct rte_eth_dev *dev)
3294 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3295 uint32_t mode = i40e_led_get(hw);
3298 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3304 i40e_dev_led_off(struct rte_eth_dev *dev)
3306 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3307 uint32_t mode = i40e_led_get(hw);
3310 i40e_led_set(hw, 0, false);
3316 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3318 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3319 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3321 fc_conf->pause_time = pf->fc_conf.pause_time;
3323 /* read out from register, in case they are modified by other port */
3324 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3325 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3326 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3327 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3329 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3330 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3332 /* Return current mode according to actual setting*/
3333 switch (hw->fc.current_mode) {
3335 fc_conf->mode = RTE_FC_FULL;
3337 case I40E_FC_TX_PAUSE:
3338 fc_conf->mode = RTE_FC_TX_PAUSE;
3340 case I40E_FC_RX_PAUSE:
3341 fc_conf->mode = RTE_FC_RX_PAUSE;
3345 fc_conf->mode = RTE_FC_NONE;
3352 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3354 uint32_t mflcn_reg, fctrl_reg, reg;
3355 uint32_t max_high_water;
3356 uint8_t i, aq_failure;
3360 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3361 [RTE_FC_NONE] = I40E_FC_NONE,
3362 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3363 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3364 [RTE_FC_FULL] = I40E_FC_FULL
3367 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3369 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3370 if ((fc_conf->high_water > max_high_water) ||
3371 (fc_conf->high_water < fc_conf->low_water)) {
3373 "Invalid high/low water setup value in KB, High_water must be <= %d.",
3378 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3379 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3380 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3382 pf->fc_conf.pause_time = fc_conf->pause_time;
3383 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3384 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3386 PMD_INIT_FUNC_TRACE();
3388 /* All the link flow control related enable/disable register
3389 * configuration is handle by the F/W
3391 err = i40e_set_fc(hw, &aq_failure, true);
3395 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3396 /* Configure flow control refresh threshold,
3397 * the value for stat_tx_pause_refresh_timer[8]
3398 * is used for global pause operation.
3402 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3403 pf->fc_conf.pause_time);
3405 /* configure the timer value included in transmitted pause
3407 * the value for stat_tx_pause_quanta[8] is used for global
3410 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3411 pf->fc_conf.pause_time);
3413 fctrl_reg = I40E_READ_REG(hw,
3414 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3416 if (fc_conf->mac_ctrl_frame_fwd != 0)
3417 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3419 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3421 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3424 /* Configure pause time (2 TCs per register) */
3425 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3426 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3427 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3429 /* Configure flow control refresh threshold value */
3430 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3431 pf->fc_conf.pause_time / 2);
3433 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3435 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3436 *depending on configuration
3438 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3439 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3440 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3442 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3443 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3446 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3449 /* config the water marker both based on the packets and bytes */
3450 I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3451 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3452 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3453 I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3454 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3455 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3456 I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3457 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3459 I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3460 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3463 I40E_WRITE_FLUSH(hw);
3469 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3470 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3472 PMD_INIT_FUNC_TRACE();
3477 /* Add a MAC address, and update filters */
3479 i40e_macaddr_add(struct rte_eth_dev *dev,
3480 struct ether_addr *mac_addr,
3481 __rte_unused uint32_t index,
3484 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3485 struct i40e_mac_filter_info mac_filter;
3486 struct i40e_vsi *vsi;
3489 /* If VMDQ not enabled or configured, return */
3490 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3491 !pf->nb_cfg_vmdq_vsi)) {
3492 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3493 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3498 if (pool > pf->nb_cfg_vmdq_vsi) {
3499 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3500 pool, pf->nb_cfg_vmdq_vsi);
3504 rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3505 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3506 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3508 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3513 vsi = pf->vmdq[pool - 1].vsi;
3515 ret = i40e_vsi_add_mac(vsi, &mac_filter);
3516 if (ret != I40E_SUCCESS) {
3517 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3523 /* Remove a MAC address, and update filters */
3525 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3527 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3528 struct i40e_vsi *vsi;
3529 struct rte_eth_dev_data *data = dev->data;
3530 struct ether_addr *macaddr;
3535 macaddr = &(data->mac_addrs[index]);
3537 pool_sel = dev->data->mac_pool_sel[index];
3539 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3540 if (pool_sel & (1ULL << i)) {
3544 /* No VMDQ pool enabled or configured */
3545 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3546 (i > pf->nb_cfg_vmdq_vsi)) {
3548 "No VMDQ pool enabled/configured");
3551 vsi = pf->vmdq[i - 1].vsi;
3553 ret = i40e_vsi_delete_mac(vsi, macaddr);
3556 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3563 /* Set perfect match or hash match of MAC and VLAN for a VF */
3565 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3566 struct rte_eth_mac_filter *filter,
3570 struct i40e_mac_filter_info mac_filter;
3571 struct ether_addr old_mac;
3572 struct ether_addr *new_mac;
3573 struct i40e_pf_vf *vf = NULL;
3578 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3581 hw = I40E_PF_TO_HW(pf);
3583 if (filter == NULL) {
3584 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3588 new_mac = &filter->mac_addr;
3590 if (is_zero_ether_addr(new_mac)) {
3591 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3595 vf_id = filter->dst_id;
3597 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3598 PMD_DRV_LOG(ERR, "Invalid argument.");
3601 vf = &pf->vfs[vf_id];
3603 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3604 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3609 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3610 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3612 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3615 mac_filter.filter_type = filter->filter_type;
3616 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3617 if (ret != I40E_SUCCESS) {
3618 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3621 ether_addr_copy(new_mac, &pf->dev_addr);
3623 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3625 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3626 if (ret != I40E_SUCCESS) {
3627 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3631 /* Clear device address as it has been removed */
3632 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3633 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3639 /* MAC filter handle */
3641 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3644 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3645 struct rte_eth_mac_filter *filter;
3646 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3647 int ret = I40E_NOT_SUPPORTED;
3649 filter = (struct rte_eth_mac_filter *)(arg);
3651 switch (filter_op) {
3652 case RTE_ETH_FILTER_NOP:
3655 case RTE_ETH_FILTER_ADD:
3656 i40e_pf_disable_irq0(hw);
3658 ret = i40e_vf_mac_filter_set(pf, filter, 1);
3659 i40e_pf_enable_irq0(hw);
3661 case RTE_ETH_FILTER_DELETE:
3662 i40e_pf_disable_irq0(hw);
3664 ret = i40e_vf_mac_filter_set(pf, filter, 0);
3665 i40e_pf_enable_irq0(hw);
3668 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3669 ret = I40E_ERR_PARAM;
3677 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3679 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3680 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3686 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3687 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3690 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3694 uint32_t *lut_dw = (uint32_t *)lut;
3695 uint16_t i, lut_size_dw = lut_size / 4;
3697 for (i = 0; i < lut_size_dw; i++)
3698 lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3705 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3714 pf = I40E_VSI_TO_PF(vsi);
3715 hw = I40E_VSI_TO_HW(vsi);
3717 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3718 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3721 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3725 uint32_t *lut_dw = (uint32_t *)lut;
3726 uint16_t i, lut_size_dw = lut_size / 4;
3728 for (i = 0; i < lut_size_dw; i++)
3729 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3730 I40E_WRITE_FLUSH(hw);
3737 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3738 struct rte_eth_rss_reta_entry64 *reta_conf,
3741 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3742 uint16_t i, lut_size = pf->hash_lut_size;
3743 uint16_t idx, shift;
3747 if (reta_size != lut_size ||
3748 reta_size > ETH_RSS_RETA_SIZE_512) {
3750 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3751 reta_size, lut_size);
3755 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3757 PMD_DRV_LOG(ERR, "No memory can be allocated");
3760 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3763 for (i = 0; i < reta_size; i++) {
3764 idx = i / RTE_RETA_GROUP_SIZE;
3765 shift = i % RTE_RETA_GROUP_SIZE;
3766 if (reta_conf[idx].mask & (1ULL << shift))
3767 lut[i] = reta_conf[idx].reta[shift];
3769 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3778 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3779 struct rte_eth_rss_reta_entry64 *reta_conf,
3782 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3783 uint16_t i, lut_size = pf->hash_lut_size;
3784 uint16_t idx, shift;
3788 if (reta_size != lut_size ||
3789 reta_size > ETH_RSS_RETA_SIZE_512) {
3791 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3792 reta_size, lut_size);
3796 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3798 PMD_DRV_LOG(ERR, "No memory can be allocated");
3802 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3805 for (i = 0; i < reta_size; i++) {
3806 idx = i / RTE_RETA_GROUP_SIZE;
3807 shift = i % RTE_RETA_GROUP_SIZE;
3808 if (reta_conf[idx].mask & (1ULL << shift))
3809 reta_conf[idx].reta[shift] = lut[i];
3819 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3820 * @hw: pointer to the HW structure
3821 * @mem: pointer to mem struct to fill out
3822 * @size: size of memory requested
3823 * @alignment: what to align the allocation to
3825 enum i40e_status_code
3826 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3827 struct i40e_dma_mem *mem,
3831 const struct rte_memzone *mz = NULL;
3832 char z_name[RTE_MEMZONE_NAMESIZE];
3835 return I40E_ERR_PARAM;
3837 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3838 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3839 alignment, RTE_PGSIZE_2M);
3841 return I40E_ERR_NO_MEMORY;
3846 mem->zone = (const void *)mz;
3848 "memzone %s allocated with physical address: %"PRIu64,
3851 return I40E_SUCCESS;
3855 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3856 * @hw: pointer to the HW structure
3857 * @mem: ptr to mem struct to free
3859 enum i40e_status_code
3860 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3861 struct i40e_dma_mem *mem)
3864 return I40E_ERR_PARAM;
3867 "memzone %s to be freed with physical address: %"PRIu64,
3868 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3869 rte_memzone_free((const struct rte_memzone *)mem->zone);
3874 return I40E_SUCCESS;
3878 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3879 * @hw: pointer to the HW structure
3880 * @mem: pointer to mem struct to fill out
3881 * @size: size of memory requested
3883 enum i40e_status_code
3884 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3885 struct i40e_virt_mem *mem,
3889 return I40E_ERR_PARAM;
3892 mem->va = rte_zmalloc("i40e", size, 0);
3895 return I40E_SUCCESS;
3897 return I40E_ERR_NO_MEMORY;
3901 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3902 * @hw: pointer to the HW structure
3903 * @mem: pointer to mem struct to free
3905 enum i40e_status_code
3906 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3907 struct i40e_virt_mem *mem)
3910 return I40E_ERR_PARAM;
3915 return I40E_SUCCESS;
3919 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3921 rte_spinlock_init(&sp->spinlock);
3925 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3927 rte_spinlock_lock(&sp->spinlock);
3931 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3933 rte_spinlock_unlock(&sp->spinlock);
3937 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3943 * Get the hardware capabilities, which will be parsed
3944 * and saved into struct i40e_hw.
3947 i40e_get_cap(struct i40e_hw *hw)
3949 struct i40e_aqc_list_capabilities_element_resp *buf;
3950 uint16_t len, size = 0;
3953 /* Calculate a huge enough buff for saving response data temporarily */
3954 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3955 I40E_MAX_CAP_ELE_NUM;
3956 buf = rte_zmalloc("i40e", len, 0);
3958 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3959 return I40E_ERR_NO_MEMORY;
3962 /* Get, parse the capabilities and save it to hw */
3963 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3964 i40e_aqc_opc_list_func_capabilities, NULL);
3965 if (ret != I40E_SUCCESS)
3966 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3968 /* Free the temporary buffer after being used */
3975 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3977 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3978 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3979 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3980 uint16_t qp_count = 0, vsi_count = 0;
3982 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3983 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3986 /* Add the parameter init for LFC */
3987 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3988 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3989 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3991 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3992 pf->max_num_vsi = hw->func_caps.num_vsis;
3993 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3994 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3995 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3997 /* FDir queue/VSI allocation */
3998 pf->fdir_qp_offset = 0;
3999 if (hw->func_caps.fd) {
4000 pf->flags |= I40E_FLAG_FDIR;
4001 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4003 pf->fdir_nb_qps = 0;
4005 qp_count += pf->fdir_nb_qps;
4008 /* LAN queue/VSI allocation */
4009 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4010 if (!hw->func_caps.rss) {
4013 pf->flags |= I40E_FLAG_RSS;
4014 if (hw->mac.type == I40E_MAC_X722)
4015 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4016 pf->lan_nb_qps = pf->lan_nb_qp_max;
4018 qp_count += pf->lan_nb_qps;
4021 /* VF queue/VSI allocation */
4022 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4023 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4024 pf->flags |= I40E_FLAG_SRIOV;
4025 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4026 pf->vf_num = pci_dev->max_vfs;
4028 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4029 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4034 qp_count += pf->vf_nb_qps * pf->vf_num;
4035 vsi_count += pf->vf_num;
4037 /* VMDq queue/VSI allocation */
4038 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4039 pf->vmdq_nb_qps = 0;
4040 pf->max_nb_vmdq_vsi = 0;
4041 if (hw->func_caps.vmdq) {
4042 if (qp_count < hw->func_caps.num_tx_qp &&
4043 vsi_count < hw->func_caps.num_vsis) {
4044 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4045 qp_count) / pf->vmdq_nb_qp_max;
4047 /* Limit the maximum number of VMDq vsi to the maximum
4048 * ethdev can support
4050 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4051 hw->func_caps.num_vsis - vsi_count);
4052 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4054 if (pf->max_nb_vmdq_vsi) {
4055 pf->flags |= I40E_FLAG_VMDQ;
4056 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4058 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4059 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4060 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4063 "No enough queues left for VMDq");
4066 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4069 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4070 vsi_count += pf->max_nb_vmdq_vsi;
4072 if (hw->func_caps.dcb)
4073 pf->flags |= I40E_FLAG_DCB;
4075 if (qp_count > hw->func_caps.num_tx_qp) {
4077 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4078 qp_count, hw->func_caps.num_tx_qp);
4081 if (vsi_count > hw->func_caps.num_vsis) {
4083 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4084 vsi_count, hw->func_caps.num_vsis);
4092 i40e_pf_get_switch_config(struct i40e_pf *pf)
4094 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4095 struct i40e_aqc_get_switch_config_resp *switch_config;
4096 struct i40e_aqc_switch_config_element_resp *element;
4097 uint16_t start_seid = 0, num_reported;
4100 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4101 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4102 if (!switch_config) {
4103 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4107 /* Get the switch configurations */
4108 ret = i40e_aq_get_switch_config(hw, switch_config,
4109 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4110 if (ret != I40E_SUCCESS) {
4111 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4114 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4115 if (num_reported != 1) { /* The number should be 1 */
4116 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4120 /* Parse the switch configuration elements */
4121 element = &(switch_config->element[0]);
4122 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4123 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4124 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4126 PMD_DRV_LOG(INFO, "Unknown element type");
4129 rte_free(switch_config);
4135 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4138 struct pool_entry *entry;
4140 if (pool == NULL || num == 0)
4143 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4144 if (entry == NULL) {
4145 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4149 /* queue heap initialize */
4150 pool->num_free = num;
4151 pool->num_alloc = 0;
4153 LIST_INIT(&pool->alloc_list);
4154 LIST_INIT(&pool->free_list);
4156 /* Initialize element */
4160 LIST_INSERT_HEAD(&pool->free_list, entry, next);
4165 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4167 struct pool_entry *entry, *next_entry;
4172 for (entry = LIST_FIRST(&pool->alloc_list);
4173 entry && (next_entry = LIST_NEXT(entry, next), 1);
4174 entry = next_entry) {
4175 LIST_REMOVE(entry, next);
4179 for (entry = LIST_FIRST(&pool->free_list);
4180 entry && (next_entry = LIST_NEXT(entry, next), 1);
4181 entry = next_entry) {
4182 LIST_REMOVE(entry, next);
4187 pool->num_alloc = 0;
4189 LIST_INIT(&pool->alloc_list);
4190 LIST_INIT(&pool->free_list);
4194 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4197 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4198 uint32_t pool_offset;
4202 PMD_DRV_LOG(ERR, "Invalid parameter");
4206 pool_offset = base - pool->base;
4207 /* Lookup in alloc list */
4208 LIST_FOREACH(entry, &pool->alloc_list, next) {
4209 if (entry->base == pool_offset) {
4210 valid_entry = entry;
4211 LIST_REMOVE(entry, next);
4216 /* Not find, return */
4217 if (valid_entry == NULL) {
4218 PMD_DRV_LOG(ERR, "Failed to find entry");
4223 * Found it, move it to free list and try to merge.
4224 * In order to make merge easier, always sort it by qbase.
4225 * Find adjacent prev and last entries.
4228 LIST_FOREACH(entry, &pool->free_list, next) {
4229 if (entry->base > valid_entry->base) {
4237 /* Try to merge with next one*/
4239 /* Merge with next one */
4240 if (valid_entry->base + valid_entry->len == next->base) {
4241 next->base = valid_entry->base;
4242 next->len += valid_entry->len;
4243 rte_free(valid_entry);
4250 /* Merge with previous one */
4251 if (prev->base + prev->len == valid_entry->base) {
4252 prev->len += valid_entry->len;
4253 /* If it merge with next one, remove next node */
4255 LIST_REMOVE(valid_entry, next);
4256 rte_free(valid_entry);
4258 rte_free(valid_entry);
4264 /* Not find any entry to merge, insert */
4267 LIST_INSERT_AFTER(prev, valid_entry, next);
4268 else if (next != NULL)
4269 LIST_INSERT_BEFORE(next, valid_entry, next);
4270 else /* It's empty list, insert to head */
4271 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4274 pool->num_free += valid_entry->len;
4275 pool->num_alloc -= valid_entry->len;
4281 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4284 struct pool_entry *entry, *valid_entry;
4286 if (pool == NULL || num == 0) {
4287 PMD_DRV_LOG(ERR, "Invalid parameter");
4291 if (pool->num_free < num) {
4292 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4293 num, pool->num_free);
4298 /* Lookup in free list and find most fit one */
4299 LIST_FOREACH(entry, &pool->free_list, next) {
4300 if (entry->len >= num) {
4302 if (entry->len == num) {
4303 valid_entry = entry;
4306 if (valid_entry == NULL || valid_entry->len > entry->len)
4307 valid_entry = entry;
4311 /* Not find one to satisfy the request, return */
4312 if (valid_entry == NULL) {
4313 PMD_DRV_LOG(ERR, "No valid entry found");
4317 * The entry have equal queue number as requested,
4318 * remove it from alloc_list.
4320 if (valid_entry->len == num) {
4321 LIST_REMOVE(valid_entry, next);
4324 * The entry have more numbers than requested,
4325 * create a new entry for alloc_list and minus its
4326 * queue base and number in free_list.
4328 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4329 if (entry == NULL) {
4331 "Failed to allocate memory for resource pool");
4334 entry->base = valid_entry->base;
4336 valid_entry->base += num;
4337 valid_entry->len -= num;
4338 valid_entry = entry;
4341 /* Insert it into alloc list, not sorted */
4342 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4344 pool->num_free -= valid_entry->len;
4345 pool->num_alloc += valid_entry->len;
4347 return valid_entry->base + pool->base;
4351 * bitmap_is_subset - Check whether src2 is subset of src1
4354 bitmap_is_subset(uint8_t src1, uint8_t src2)
4356 return !((src1 ^ src2) & src2);
4359 static enum i40e_status_code
4360 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4362 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4364 /* If DCB is not supported, only default TC is supported */
4365 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4366 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4367 return I40E_NOT_SUPPORTED;
4370 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4372 "Enabled TC map 0x%x not applicable to HW support 0x%x",
4373 hw->func_caps.enabled_tcmap, enabled_tcmap);
4374 return I40E_NOT_SUPPORTED;
4376 return I40E_SUCCESS;
4380 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4381 struct i40e_vsi_vlan_pvid_info *info)
4384 struct i40e_vsi_context ctxt;
4385 uint8_t vlan_flags = 0;
4388 if (vsi == NULL || info == NULL) {
4389 PMD_DRV_LOG(ERR, "invalid parameters");
4390 return I40E_ERR_PARAM;
4394 vsi->info.pvid = info->config.pvid;
4396 * If insert pvid is enabled, only tagged pkts are
4397 * allowed to be sent out.
4399 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4400 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4403 if (info->config.reject.tagged == 0)
4404 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4406 if (info->config.reject.untagged == 0)
4407 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4409 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4410 I40E_AQ_VSI_PVLAN_MODE_MASK);
4411 vsi->info.port_vlan_flags |= vlan_flags;
4412 vsi->info.valid_sections =
4413 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4414 memset(&ctxt, 0, sizeof(ctxt));
4415 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4416 ctxt.seid = vsi->seid;
4418 hw = I40E_VSI_TO_HW(vsi);
4419 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4420 if (ret != I40E_SUCCESS)
4421 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4427 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4429 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4431 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4433 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4434 if (ret != I40E_SUCCESS)
4438 PMD_DRV_LOG(ERR, "seid not valid");
4442 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4443 tc_bw_data.tc_valid_bits = enabled_tcmap;
4444 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4445 tc_bw_data.tc_bw_credits[i] =
4446 (enabled_tcmap & (1 << i)) ? 1 : 0;
4448 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4449 if (ret != I40E_SUCCESS) {
4450 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4454 rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4455 sizeof(vsi->info.qs_handle));
4456 return I40E_SUCCESS;
4459 static enum i40e_status_code
4460 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4461 struct i40e_aqc_vsi_properties_data *info,
4462 uint8_t enabled_tcmap)
4464 enum i40e_status_code ret;
4465 int i, total_tc = 0;
4466 uint16_t qpnum_per_tc, bsf, qp_idx;
4468 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4469 if (ret != I40E_SUCCESS)
4472 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4473 if (enabled_tcmap & (1 << i))
4477 vsi->enabled_tc = enabled_tcmap;
4479 /* Number of queues per enabled TC */
4480 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4481 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4482 bsf = rte_bsf32(qpnum_per_tc);
4484 /* Adjust the queue number to actual queues that can be applied */
4485 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4486 vsi->nb_qps = qpnum_per_tc * total_tc;
4489 * Configure TC and queue mapping parameters, for enabled TC,
4490 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4491 * default queue will serve it.
4494 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4495 if (vsi->enabled_tc & (1 << i)) {
4496 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4497 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4498 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4499 qp_idx += qpnum_per_tc;
4501 info->tc_mapping[i] = 0;
4504 /* Associate queue number with VSI */
4505 if (vsi->type == I40E_VSI_SRIOV) {
4506 info->mapping_flags |=
4507 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4508 for (i = 0; i < vsi->nb_qps; i++)
4509 info->queue_mapping[i] =
4510 rte_cpu_to_le_16(vsi->base_queue + i);
4512 info->mapping_flags |=
4513 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4514 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4516 info->valid_sections |=
4517 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4519 return I40E_SUCCESS;
4523 i40e_veb_release(struct i40e_veb *veb)
4525 struct i40e_vsi *vsi;
4531 if (!TAILQ_EMPTY(&veb->head)) {
4532 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4535 /* associate_vsi field is NULL for floating VEB */
4536 if (veb->associate_vsi != NULL) {
4537 vsi = veb->associate_vsi;
4538 hw = I40E_VSI_TO_HW(vsi);
4540 vsi->uplink_seid = veb->uplink_seid;
4543 veb->associate_pf->main_vsi->floating_veb = NULL;
4544 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4547 i40e_aq_delete_element(hw, veb->seid, NULL);
4549 return I40E_SUCCESS;
4553 static struct i40e_veb *
4554 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4556 struct i40e_veb *veb;
4562 "veb setup failed, associated PF shouldn't null");
4565 hw = I40E_PF_TO_HW(pf);
4567 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4569 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4573 veb->associate_vsi = vsi;
4574 veb->associate_pf = pf;
4575 TAILQ_INIT(&veb->head);
4576 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4578 /* create floating veb if vsi is NULL */
4580 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4581 I40E_DEFAULT_TCMAP, false,
4582 &veb->seid, false, NULL);
4584 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4585 true, &veb->seid, false, NULL);
4588 if (ret != I40E_SUCCESS) {
4589 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4590 hw->aq.asq_last_status);
4593 veb->enabled_tc = I40E_DEFAULT_TCMAP;
4595 /* get statistics index */
4596 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4597 &veb->stats_idx, NULL, NULL, NULL);
4598 if (ret != I40E_SUCCESS) {
4599 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4600 hw->aq.asq_last_status);
4603 /* Get VEB bandwidth, to be implemented */
4604 /* Now associated vsi binding to the VEB, set uplink to this VEB */
4606 vsi->uplink_seid = veb->seid;
4615 i40e_vsi_release(struct i40e_vsi *vsi)
4619 struct i40e_vsi_list *vsi_list;
4622 struct i40e_mac_filter *f;
4623 uint16_t user_param;
4626 return I40E_SUCCESS;
4631 user_param = vsi->user_param;
4633 pf = I40E_VSI_TO_PF(vsi);
4634 hw = I40E_VSI_TO_HW(vsi);
4636 /* VSI has child to attach, release child first */
4638 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4639 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4642 i40e_veb_release(vsi->veb);
4645 if (vsi->floating_veb) {
4646 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4647 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4652 /* Remove all macvlan filters of the VSI */
4653 i40e_vsi_remove_all_macvlan_filter(vsi);
4654 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4657 if (vsi->type != I40E_VSI_MAIN &&
4658 ((vsi->type != I40E_VSI_SRIOV) ||
4659 !pf->floating_veb_list[user_param])) {
4660 /* Remove vsi from parent's sibling list */
4661 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4662 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4663 return I40E_ERR_PARAM;
4665 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4666 &vsi->sib_vsi_list, list);
4668 /* Remove all switch element of the VSI */
4669 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4670 if (ret != I40E_SUCCESS)
4671 PMD_DRV_LOG(ERR, "Failed to delete element");
4674 if ((vsi->type == I40E_VSI_SRIOV) &&
4675 pf->floating_veb_list[user_param]) {
4676 /* Remove vsi from parent's sibling list */
4677 if (vsi->parent_vsi == NULL ||
4678 vsi->parent_vsi->floating_veb == NULL) {
4679 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4680 return I40E_ERR_PARAM;
4682 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4683 &vsi->sib_vsi_list, list);
4685 /* Remove all switch element of the VSI */
4686 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4687 if (ret != I40E_SUCCESS)
4688 PMD_DRV_LOG(ERR, "Failed to delete element");
4691 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4693 if (vsi->type != I40E_VSI_SRIOV)
4694 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4697 return I40E_SUCCESS;
4701 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4703 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4704 struct i40e_aqc_remove_macvlan_element_data def_filter;
4705 struct i40e_mac_filter_info filter;
4708 if (vsi->type != I40E_VSI_MAIN)
4709 return I40E_ERR_CONFIG;
4710 memset(&def_filter, 0, sizeof(def_filter));
4711 rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4713 def_filter.vlan_tag = 0;
4714 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4715 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4716 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4717 if (ret != I40E_SUCCESS) {
4718 struct i40e_mac_filter *f;
4719 struct ether_addr *mac;
4722 "Cannot remove the default macvlan filter");
4723 /* It needs to add the permanent mac into mac list */
4724 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4726 PMD_DRV_LOG(ERR, "failed to allocate memory");
4727 return I40E_ERR_NO_MEMORY;
4729 mac = &f->mac_info.mac_addr;
4730 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4732 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4733 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4738 rte_memcpy(&filter.mac_addr,
4739 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4740 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4741 return i40e_vsi_add_mac(vsi, &filter);
4745 * i40e_vsi_get_bw_config - Query VSI BW Information
4746 * @vsi: the VSI to be queried
4748 * Returns 0 on success, negative value on failure
4750 static enum i40e_status_code
4751 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4753 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4754 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4755 struct i40e_hw *hw = &vsi->adapter->hw;
4760 memset(&bw_config, 0, sizeof(bw_config));
4761 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4762 if (ret != I40E_SUCCESS) {
4763 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4764 hw->aq.asq_last_status);
4768 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4769 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4770 &ets_sla_config, NULL);
4771 if (ret != I40E_SUCCESS) {
4773 "VSI failed to get TC bandwdith configuration %u",
4774 hw->aq.asq_last_status);
4778 /* store and print out BW info */
4779 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4780 vsi->bw_info.bw_max = bw_config.max_bw;
4781 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4782 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4783 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4784 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4786 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4787 vsi->bw_info.bw_ets_share_credits[i] =
4788 ets_sla_config.share_credits[i];
4789 vsi->bw_info.bw_ets_credits[i] =
4790 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4791 /* 4 bits per TC, 4th bit is reserved */
4792 vsi->bw_info.bw_ets_max[i] =
4793 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4794 RTE_LEN2MASK(3, uint8_t));
4795 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4796 vsi->bw_info.bw_ets_share_credits[i]);
4797 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4798 vsi->bw_info.bw_ets_credits[i]);
4799 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4800 vsi->bw_info.bw_ets_max[i]);
4803 return I40E_SUCCESS;
4806 /* i40e_enable_pf_lb
4807 * @pf: pointer to the pf structure
4809 * allow loopback on pf
4812 i40e_enable_pf_lb(struct i40e_pf *pf)
4814 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4815 struct i40e_vsi_context ctxt;
4818 /* Use the FW API if FW >= v5.0 */
4819 if (hw->aq.fw_maj_ver < 5) {
4820 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4824 memset(&ctxt, 0, sizeof(ctxt));
4825 ctxt.seid = pf->main_vsi_seid;
4826 ctxt.pf_num = hw->pf_id;
4827 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4829 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4830 ret, hw->aq.asq_last_status);
4833 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4834 ctxt.info.valid_sections =
4835 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4836 ctxt.info.switch_id |=
4837 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4839 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4841 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4842 hw->aq.asq_last_status);
4847 i40e_vsi_setup(struct i40e_pf *pf,
4848 enum i40e_vsi_type type,
4849 struct i40e_vsi *uplink_vsi,
4850 uint16_t user_param)
4852 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4853 struct i40e_vsi *vsi;
4854 struct i40e_mac_filter_info filter;
4856 struct i40e_vsi_context ctxt;
4857 struct ether_addr broadcast =
4858 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4860 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4861 uplink_vsi == NULL) {
4863 "VSI setup failed, VSI link shouldn't be NULL");
4867 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4869 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4874 * 1.type is not MAIN and uplink vsi is not NULL
4875 * If uplink vsi didn't setup VEB, create one first under veb field
4876 * 2.type is SRIOV and the uplink is NULL
4877 * If floating VEB is NULL, create one veb under floating veb field
4880 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4881 uplink_vsi->veb == NULL) {
4882 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4884 if (uplink_vsi->veb == NULL) {
4885 PMD_DRV_LOG(ERR, "VEB setup failed");
4888 /* set ALLOWLOOPBACk on pf, when veb is created */
4889 i40e_enable_pf_lb(pf);
4892 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4893 pf->main_vsi->floating_veb == NULL) {
4894 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4896 if (pf->main_vsi->floating_veb == NULL) {
4897 PMD_DRV_LOG(ERR, "VEB setup failed");
4902 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4904 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4907 TAILQ_INIT(&vsi->mac_list);
4909 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4910 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4911 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4912 vsi->user_param = user_param;
4913 vsi->vlan_anti_spoof_on = 0;
4914 vsi->vlan_filter_on = 0;
4915 /* Allocate queues */
4916 switch (vsi->type) {
4917 case I40E_VSI_MAIN :
4918 vsi->nb_qps = pf->lan_nb_qps;
4920 case I40E_VSI_SRIOV :
4921 vsi->nb_qps = pf->vf_nb_qps;
4923 case I40E_VSI_VMDQ2:
4924 vsi->nb_qps = pf->vmdq_nb_qps;
4927 vsi->nb_qps = pf->fdir_nb_qps;
4933 * The filter status descriptor is reported in rx queue 0,
4934 * while the tx queue for fdir filter programming has no
4935 * such constraints, can be non-zero queues.
4936 * To simplify it, choose FDIR vsi use queue 0 pair.
4937 * To make sure it will use queue 0 pair, queue allocation
4938 * need be done before this function is called
4940 if (type != I40E_VSI_FDIR) {
4941 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4943 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4947 vsi->base_queue = ret;
4949 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4951 /* VF has MSIX interrupt in VF range, don't allocate here */
4952 if (type == I40E_VSI_MAIN) {
4953 ret = i40e_res_pool_alloc(&pf->msix_pool,
4954 RTE_MIN(vsi->nb_qps,
4955 RTE_MAX_RXTX_INTR_VEC_ID));
4957 PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4959 goto fail_queue_alloc;
4961 vsi->msix_intr = ret;
4962 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4963 } else if (type != I40E_VSI_SRIOV) {
4964 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4966 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4967 goto fail_queue_alloc;
4969 vsi->msix_intr = ret;
4977 if (type == I40E_VSI_MAIN) {
4978 /* For main VSI, no need to add since it's default one */
4979 vsi->uplink_seid = pf->mac_seid;
4980 vsi->seid = pf->main_vsi_seid;
4981 /* Bind queues with specific MSIX interrupt */
4983 * Needs 2 interrupt at least, one for misc cause which will
4984 * enabled from OS side, Another for queues binding the
4985 * interrupt from device side only.
4988 /* Get default VSI parameters from hardware */
4989 memset(&ctxt, 0, sizeof(ctxt));
4990 ctxt.seid = vsi->seid;
4991 ctxt.pf_num = hw->pf_id;
4992 ctxt.uplink_seid = vsi->uplink_seid;
4994 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4995 if (ret != I40E_SUCCESS) {
4996 PMD_DRV_LOG(ERR, "Failed to get VSI params");
4997 goto fail_msix_alloc;
4999 rte_memcpy(&vsi->info, &ctxt.info,
5000 sizeof(struct i40e_aqc_vsi_properties_data));
5001 vsi->vsi_id = ctxt.vsi_number;
5002 vsi->info.valid_sections = 0;
5004 /* Configure tc, enabled TC0 only */
5005 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5007 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5008 goto fail_msix_alloc;
5011 /* TC, queue mapping */
5012 memset(&ctxt, 0, sizeof(ctxt));
5013 vsi->info.valid_sections |=
5014 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5015 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5016 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5017 rte_memcpy(&ctxt.info, &vsi->info,
5018 sizeof(struct i40e_aqc_vsi_properties_data));
5019 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5020 I40E_DEFAULT_TCMAP);
5021 if (ret != I40E_SUCCESS) {
5023 "Failed to configure TC queue mapping");
5024 goto fail_msix_alloc;
5026 ctxt.seid = vsi->seid;
5027 ctxt.pf_num = hw->pf_id;
5028 ctxt.uplink_seid = vsi->uplink_seid;
5031 /* Update VSI parameters */
5032 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5033 if (ret != I40E_SUCCESS) {
5034 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5035 goto fail_msix_alloc;
5038 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5039 sizeof(vsi->info.tc_mapping));
5040 rte_memcpy(&vsi->info.queue_mapping,
5041 &ctxt.info.queue_mapping,
5042 sizeof(vsi->info.queue_mapping));
5043 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5044 vsi->info.valid_sections = 0;
5046 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5050 * Updating default filter settings are necessary to prevent
5051 * reception of tagged packets.
5052 * Some old firmware configurations load a default macvlan
5053 * filter which accepts both tagged and untagged packets.
5054 * The updating is to use a normal filter instead if needed.
5055 * For NVM 4.2.2 or after, the updating is not needed anymore.
5056 * The firmware with correct configurations load the default
5057 * macvlan filter which is expected and cannot be removed.
5059 i40e_update_default_filter_setting(vsi);
5060 i40e_config_qinq(hw, vsi);
5061 } else if (type == I40E_VSI_SRIOV) {
5062 memset(&ctxt, 0, sizeof(ctxt));
5064 * For other VSI, the uplink_seid equals to uplink VSI's
5065 * uplink_seid since they share same VEB
5067 if (uplink_vsi == NULL)
5068 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5070 vsi->uplink_seid = uplink_vsi->uplink_seid;
5071 ctxt.pf_num = hw->pf_id;
5072 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5073 ctxt.uplink_seid = vsi->uplink_seid;
5074 ctxt.connection_type = 0x1;
5075 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5077 /* Use the VEB configuration if FW >= v5.0 */
5078 if (hw->aq.fw_maj_ver >= 5) {
5079 /* Configure switch ID */
5080 ctxt.info.valid_sections |=
5081 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5082 ctxt.info.switch_id =
5083 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5086 /* Configure port/vlan */
5087 ctxt.info.valid_sections |=
5088 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5089 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5090 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5091 hw->func_caps.enabled_tcmap);
5092 if (ret != I40E_SUCCESS) {
5094 "Failed to configure TC queue mapping");
5095 goto fail_msix_alloc;
5098 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5099 ctxt.info.valid_sections |=
5100 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5102 * Since VSI is not created yet, only configure parameter,
5103 * will add vsi below.
5106 i40e_config_qinq(hw, vsi);
5107 } else if (type == I40E_VSI_VMDQ2) {
5108 memset(&ctxt, 0, sizeof(ctxt));
5110 * For other VSI, the uplink_seid equals to uplink VSI's
5111 * uplink_seid since they share same VEB
5113 vsi->uplink_seid = uplink_vsi->uplink_seid;
5114 ctxt.pf_num = hw->pf_id;
5116 ctxt.uplink_seid = vsi->uplink_seid;
5117 ctxt.connection_type = 0x1;
5118 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5120 ctxt.info.valid_sections |=
5121 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5122 /* user_param carries flag to enable loop back */
5124 ctxt.info.switch_id =
5125 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5126 ctxt.info.switch_id |=
5127 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5130 /* Configure port/vlan */
5131 ctxt.info.valid_sections |=
5132 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5133 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5134 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5135 I40E_DEFAULT_TCMAP);
5136 if (ret != I40E_SUCCESS) {
5138 "Failed to configure TC queue mapping");
5139 goto fail_msix_alloc;
5141 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5142 ctxt.info.valid_sections |=
5143 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5144 } else if (type == I40E_VSI_FDIR) {
5145 memset(&ctxt, 0, sizeof(ctxt));
5146 vsi->uplink_seid = uplink_vsi->uplink_seid;
5147 ctxt.pf_num = hw->pf_id;
5149 ctxt.uplink_seid = vsi->uplink_seid;
5150 ctxt.connection_type = 0x1; /* regular data port */
5151 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5152 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5153 I40E_DEFAULT_TCMAP);
5154 if (ret != I40E_SUCCESS) {
5156 "Failed to configure TC queue mapping.");
5157 goto fail_msix_alloc;
5159 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5160 ctxt.info.valid_sections |=
5161 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5163 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5164 goto fail_msix_alloc;
5167 if (vsi->type != I40E_VSI_MAIN) {
5168 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5169 if (ret != I40E_SUCCESS) {
5170 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5171 hw->aq.asq_last_status);
5172 goto fail_msix_alloc;
5174 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5175 vsi->info.valid_sections = 0;
5176 vsi->seid = ctxt.seid;
5177 vsi->vsi_id = ctxt.vsi_number;
5178 vsi->sib_vsi_list.vsi = vsi;
5179 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5180 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5181 &vsi->sib_vsi_list, list);
5183 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5184 &vsi->sib_vsi_list, list);
5188 /* MAC/VLAN configuration */
5189 rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5190 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5192 ret = i40e_vsi_add_mac(vsi, &filter);
5193 if (ret != I40E_SUCCESS) {
5194 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5195 goto fail_msix_alloc;
5198 /* Get VSI BW information */
5199 i40e_vsi_get_bw_config(vsi);
5202 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5204 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5210 /* Configure vlan filter on or off */
5212 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5215 struct i40e_mac_filter *f;
5217 struct i40e_mac_filter_info *mac_filter;
5218 enum rte_mac_filter_type desired_filter;
5219 int ret = I40E_SUCCESS;
5222 /* Filter to match MAC and VLAN */
5223 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5225 /* Filter to match only MAC */
5226 desired_filter = RTE_MAC_PERFECT_MATCH;
5231 mac_filter = rte_zmalloc("mac_filter_info_data",
5232 num * sizeof(*mac_filter), 0);
5233 if (mac_filter == NULL) {
5234 PMD_DRV_LOG(ERR, "failed to allocate memory");
5235 return I40E_ERR_NO_MEMORY;
5240 /* Remove all existing mac */
5241 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5242 mac_filter[i] = f->mac_info;
5243 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5245 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5246 on ? "enable" : "disable");
5252 /* Override with new filter */
5253 for (i = 0; i < num; i++) {
5254 mac_filter[i].filter_type = desired_filter;
5255 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5257 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5258 on ? "enable" : "disable");
5264 rte_free(mac_filter);
5268 /* Configure vlan stripping on or off */
5270 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5272 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5273 struct i40e_vsi_context ctxt;
5275 int ret = I40E_SUCCESS;
5277 /* Check if it has been already on or off */
5278 if (vsi->info.valid_sections &
5279 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5281 if ((vsi->info.port_vlan_flags &
5282 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5283 return 0; /* already on */
5285 if ((vsi->info.port_vlan_flags &
5286 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5287 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5288 return 0; /* already off */
5293 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5295 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5296 vsi->info.valid_sections =
5297 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5298 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5299 vsi->info.port_vlan_flags |= vlan_flags;
5300 ctxt.seid = vsi->seid;
5301 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5302 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5304 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5305 on ? "enable" : "disable");
5311 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5313 struct rte_eth_dev_data *data = dev->data;
5317 /* Apply vlan offload setting */
5318 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5319 ret = i40e_vlan_offload_set(dev, mask);
5321 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5325 /* Apply double-vlan setting, not implemented yet */
5327 /* Apply pvid setting */
5328 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5329 data->dev_conf.txmode.hw_vlan_insert_pvid);
5331 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5337 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5339 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5341 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5345 i40e_update_flow_control(struct i40e_hw *hw)
5347 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5348 struct i40e_link_status link_status;
5349 uint32_t rxfc = 0, txfc = 0, reg;
5353 memset(&link_status, 0, sizeof(link_status));
5354 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5355 if (ret != I40E_SUCCESS) {
5356 PMD_DRV_LOG(ERR, "Failed to get link status information");
5357 goto write_reg; /* Disable flow control */
5360 an_info = hw->phy.link_info.an_info;
5361 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5362 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5363 ret = I40E_ERR_NOT_READY;
5364 goto write_reg; /* Disable flow control */
5367 * If link auto negotiation is enabled, flow control needs to
5368 * be configured according to it
5370 switch (an_info & I40E_LINK_PAUSE_RXTX) {
5371 case I40E_LINK_PAUSE_RXTX:
5374 hw->fc.current_mode = I40E_FC_FULL;
5376 case I40E_AQ_LINK_PAUSE_RX:
5378 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5380 case I40E_AQ_LINK_PAUSE_TX:
5382 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5385 hw->fc.current_mode = I40E_FC_NONE;
5390 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5391 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5392 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5393 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5394 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5395 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5402 i40e_pf_setup(struct i40e_pf *pf)
5404 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5405 struct i40e_filter_control_settings settings;
5406 struct i40e_vsi *vsi;
5409 /* Clear all stats counters */
5410 pf->offset_loaded = FALSE;
5411 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5412 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5413 memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5414 memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5416 ret = i40e_pf_get_switch_config(pf);
5417 if (ret != I40E_SUCCESS) {
5418 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5421 if (pf->flags & I40E_FLAG_FDIR) {
5422 /* make queue allocated first, let FDIR use queue pair 0*/
5423 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5424 if (ret != I40E_FDIR_QUEUE_ID) {
5426 "queue allocation fails for FDIR: ret =%d",
5428 pf->flags &= ~I40E_FLAG_FDIR;
5431 /* main VSI setup */
5432 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5434 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5435 return I40E_ERR_NOT_READY;
5439 /* Configure filter control */
5440 memset(&settings, 0, sizeof(settings));
5441 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5442 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5443 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5444 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5446 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5447 hw->func_caps.rss_table_size);
5448 return I40E_ERR_PARAM;
5450 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5451 hw->func_caps.rss_table_size);
5452 pf->hash_lut_size = hw->func_caps.rss_table_size;
5454 /* Enable ethtype and macvlan filters */
5455 settings.enable_ethtype = TRUE;
5456 settings.enable_macvlan = TRUE;
5457 ret = i40e_set_filter_control(hw, &settings);
5459 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5462 /* Update flow control according to the auto negotiation */
5463 i40e_update_flow_control(hw);
5465 return I40E_SUCCESS;
5469 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5475 * Set or clear TX Queue Disable flags,
5476 * which is required by hardware.
5478 i40e_pre_tx_queue_cfg(hw, q_idx, on);
5479 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5481 /* Wait until the request is finished */
5482 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5483 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5484 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5485 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5486 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5492 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5493 return I40E_SUCCESS; /* already on, skip next steps */
5495 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5496 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5498 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5499 return I40E_SUCCESS; /* already off, skip next steps */
5500 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5502 /* Write the register */
5503 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5504 /* Check the result */
5505 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5506 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5507 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5509 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5510 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5513 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5514 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5518 /* Check if it is timeout */
5519 if (j >= I40E_CHK_Q_ENA_COUNT) {
5520 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5521 (on ? "enable" : "disable"), q_idx);
5522 return I40E_ERR_TIMEOUT;
5525 return I40E_SUCCESS;
5528 /* Swith on or off the tx queues */
5530 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5532 struct rte_eth_dev_data *dev_data = pf->dev_data;
5533 struct i40e_tx_queue *txq;
5534 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5538 for (i = 0; i < dev_data->nb_tx_queues; i++) {
5539 txq = dev_data->tx_queues[i];
5540 /* Don't operate the queue if not configured or
5541 * if starting only per queue */
5542 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5545 ret = i40e_dev_tx_queue_start(dev, i);
5547 ret = i40e_dev_tx_queue_stop(dev, i);
5548 if ( ret != I40E_SUCCESS)
5552 return I40E_SUCCESS;
5556 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5561 /* Wait until the request is finished */
5562 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5563 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5564 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5565 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5566 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5571 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5572 return I40E_SUCCESS; /* Already on, skip next steps */
5573 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5575 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5576 return I40E_SUCCESS; /* Already off, skip next steps */
5577 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5580 /* Write the register */
5581 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5582 /* Check the result */
5583 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5584 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5585 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5587 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5588 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5591 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5592 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5597 /* Check if it is timeout */
5598 if (j >= I40E_CHK_Q_ENA_COUNT) {
5599 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5600 (on ? "enable" : "disable"), q_idx);
5601 return I40E_ERR_TIMEOUT;
5604 return I40E_SUCCESS;
5606 /* Switch on or off the rx queues */
5608 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5610 struct rte_eth_dev_data *dev_data = pf->dev_data;
5611 struct i40e_rx_queue *rxq;
5612 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5616 for (i = 0; i < dev_data->nb_rx_queues; i++) {
5617 rxq = dev_data->rx_queues[i];
5618 /* Don't operate the queue if not configured or
5619 * if starting only per queue */
5620 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5623 ret = i40e_dev_rx_queue_start(dev, i);
5625 ret = i40e_dev_rx_queue_stop(dev, i);
5626 if (ret != I40E_SUCCESS)
5630 return I40E_SUCCESS;
5633 /* Switch on or off all the rx/tx queues */
5635 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5640 /* enable rx queues before enabling tx queues */
5641 ret = i40e_dev_switch_rx_queues(pf, on);
5643 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5646 ret = i40e_dev_switch_tx_queues(pf, on);
5648 /* Stop tx queues before stopping rx queues */
5649 ret = i40e_dev_switch_tx_queues(pf, on);
5651 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5654 ret = i40e_dev_switch_rx_queues(pf, on);
5660 /* Initialize VSI for TX */
5662 i40e_dev_tx_init(struct i40e_pf *pf)
5664 struct rte_eth_dev_data *data = pf->dev_data;
5666 uint32_t ret = I40E_SUCCESS;
5667 struct i40e_tx_queue *txq;
5669 for (i = 0; i < data->nb_tx_queues; i++) {
5670 txq = data->tx_queues[i];
5671 if (!txq || !txq->q_set)
5673 ret = i40e_tx_queue_init(txq);
5674 if (ret != I40E_SUCCESS)
5677 if (ret == I40E_SUCCESS)
5678 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5684 /* Initialize VSI for RX */
5686 i40e_dev_rx_init(struct i40e_pf *pf)
5688 struct rte_eth_dev_data *data = pf->dev_data;
5689 int ret = I40E_SUCCESS;
5691 struct i40e_rx_queue *rxq;
5693 i40e_pf_config_mq_rx(pf);
5694 for (i = 0; i < data->nb_rx_queues; i++) {
5695 rxq = data->rx_queues[i];
5696 if (!rxq || !rxq->q_set)
5699 ret = i40e_rx_queue_init(rxq);
5700 if (ret != I40E_SUCCESS) {
5702 "Failed to do RX queue initialization");
5706 if (ret == I40E_SUCCESS)
5707 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5714 i40e_dev_rxtx_init(struct i40e_pf *pf)
5718 err = i40e_dev_tx_init(pf);
5720 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5723 err = i40e_dev_rx_init(pf);
5725 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5733 i40e_vmdq_setup(struct rte_eth_dev *dev)
5735 struct rte_eth_conf *conf = &dev->data->dev_conf;
5736 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5737 int i, err, conf_vsis, j, loop;
5738 struct i40e_vsi *vsi;
5739 struct i40e_vmdq_info *vmdq_info;
5740 struct rte_eth_vmdq_rx_conf *vmdq_conf;
5741 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5744 * Disable interrupt to avoid message from VF. Furthermore, it will
5745 * avoid race condition in VSI creation/destroy.
5747 i40e_pf_disable_irq0(hw);
5749 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5750 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5754 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5755 if (conf_vsis > pf->max_nb_vmdq_vsi) {
5756 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5757 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5758 pf->max_nb_vmdq_vsi);
5762 if (pf->vmdq != NULL) {
5763 PMD_INIT_LOG(INFO, "VMDQ already configured");
5767 pf->vmdq = rte_zmalloc("vmdq_info_struct",
5768 sizeof(*vmdq_info) * conf_vsis, 0);
5770 if (pf->vmdq == NULL) {
5771 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5775 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5777 /* Create VMDQ VSI */
5778 for (i = 0; i < conf_vsis; i++) {
5779 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5780 vmdq_conf->enable_loop_back);
5782 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5786 vmdq_info = &pf->vmdq[i];
5788 vmdq_info->vsi = vsi;
5790 pf->nb_cfg_vmdq_vsi = conf_vsis;
5792 /* Configure Vlan */
5793 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5794 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5795 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5796 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5797 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5798 vmdq_conf->pool_map[i].vlan_id, j);
5800 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5801 vmdq_conf->pool_map[i].vlan_id);
5803 PMD_INIT_LOG(ERR, "Failed to add vlan");
5811 i40e_pf_enable_irq0(hw);
5816 for (i = 0; i < conf_vsis; i++)
5817 if (pf->vmdq[i].vsi == NULL)
5820 i40e_vsi_release(pf->vmdq[i].vsi);
5824 i40e_pf_enable_irq0(hw);
5829 i40e_stat_update_32(struct i40e_hw *hw,
5837 new_data = (uint64_t)I40E_READ_REG(hw, reg);
5841 if (new_data >= *offset)
5842 *stat = (uint64_t)(new_data - *offset);
5844 *stat = (uint64_t)((new_data +
5845 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5849 i40e_stat_update_48(struct i40e_hw *hw,
5858 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5859 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5860 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5865 if (new_data >= *offset)
5866 *stat = new_data - *offset;
5868 *stat = (uint64_t)((new_data +
5869 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5871 *stat &= I40E_48_BIT_MASK;
5876 i40e_pf_disable_irq0(struct i40e_hw *hw)
5878 /* Disable all interrupt types */
5879 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5880 I40E_WRITE_FLUSH(hw);
5885 i40e_pf_enable_irq0(struct i40e_hw *hw)
5887 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5888 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5889 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5890 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5891 I40E_WRITE_FLUSH(hw);
5895 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5897 /* read pending request and disable first */
5898 i40e_pf_disable_irq0(hw);
5899 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5900 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5901 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5904 /* Link no queues with irq0 */
5905 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5906 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5910 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5912 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5913 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5916 uint32_t index, offset, val;
5921 * Try to find which VF trigger a reset, use absolute VF id to access
5922 * since the reg is global register.
5924 for (i = 0; i < pf->vf_num; i++) {
5925 abs_vf_id = hw->func_caps.vf_base_id + i;
5926 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5927 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5928 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5929 /* VFR event occurred */
5930 if (val & (0x1 << offset)) {
5933 /* Clear the event first */
5934 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5936 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
5938 * Only notify a VF reset event occurred,
5939 * don't trigger another SW reset
5941 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5942 if (ret != I40E_SUCCESS)
5943 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5949 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5951 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5954 for (i = 0; i < pf->vf_num; i++)
5955 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
5959 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5961 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5962 struct i40e_arq_event_info info;
5963 uint16_t pending, opcode;
5966 info.buf_len = I40E_AQ_BUF_SZ;
5967 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5968 if (!info.msg_buf) {
5969 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5975 ret = i40e_clean_arq_element(hw, &info, &pending);
5977 if (ret != I40E_SUCCESS) {
5979 "Failed to read msg from AdminQ, aq_err: %u",
5980 hw->aq.asq_last_status);
5983 opcode = rte_le_to_cpu_16(info.desc.opcode);
5986 case i40e_aqc_opc_send_msg_to_pf:
5987 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5988 i40e_pf_host_handle_vf_msg(dev,
5989 rte_le_to_cpu_16(info.desc.retval),
5990 rte_le_to_cpu_32(info.desc.cookie_high),
5991 rte_le_to_cpu_32(info.desc.cookie_low),
5995 case i40e_aqc_opc_get_link_status:
5996 ret = i40e_dev_link_update(dev, 0);
5998 _rte_eth_dev_callback_process(dev,
5999 RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
6002 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6007 rte_free(info.msg_buf);
6011 * Interrupt handler triggered by NIC for handling
6012 * specific interrupt.
6015 * Pointer to interrupt handle.
6017 * The address of parameter (struct rte_eth_dev *) regsitered before.
6023 i40e_dev_interrupt_handler(void *param)
6025 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6026 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6029 /* Disable interrupt */
6030 i40e_pf_disable_irq0(hw);
6032 /* read out interrupt causes */
6033 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6035 /* No interrupt event indicated */
6036 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6037 PMD_DRV_LOG(INFO, "No interrupt event");
6040 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6041 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6042 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6043 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6044 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6045 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6046 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6047 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6048 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6049 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6050 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6051 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6052 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6053 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6055 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6056 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6057 i40e_dev_handle_vfr_event(dev);
6059 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6060 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6061 i40e_dev_handle_aq_msg(dev);
6065 /* Enable interrupt */
6066 i40e_pf_enable_irq0(hw);
6067 rte_intr_enable(dev->intr_handle);
6071 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6072 struct i40e_macvlan_filter *filter,
6075 int ele_num, ele_buff_size;
6076 int num, actual_num, i;
6078 int ret = I40E_SUCCESS;
6079 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6080 struct i40e_aqc_add_macvlan_element_data *req_list;
6082 if (filter == NULL || total == 0)
6083 return I40E_ERR_PARAM;
6084 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6085 ele_buff_size = hw->aq.asq_buf_size;
6087 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6088 if (req_list == NULL) {
6089 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6090 return I40E_ERR_NO_MEMORY;
6095 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6096 memset(req_list, 0, ele_buff_size);
6098 for (i = 0; i < actual_num; i++) {
6099 rte_memcpy(req_list[i].mac_addr,
6100 &filter[num + i].macaddr, ETH_ADDR_LEN);
6101 req_list[i].vlan_tag =
6102 rte_cpu_to_le_16(filter[num + i].vlan_id);
6104 switch (filter[num + i].filter_type) {
6105 case RTE_MAC_PERFECT_MATCH:
6106 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6107 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6109 case RTE_MACVLAN_PERFECT_MATCH:
6110 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6112 case RTE_MAC_HASH_MATCH:
6113 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6114 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6116 case RTE_MACVLAN_HASH_MATCH:
6117 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6120 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6121 ret = I40E_ERR_PARAM;
6125 req_list[i].queue_number = 0;
6127 req_list[i].flags = rte_cpu_to_le_16(flags);
6130 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6132 if (ret != I40E_SUCCESS) {
6133 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6137 } while (num < total);
6145 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6146 struct i40e_macvlan_filter *filter,
6149 int ele_num, ele_buff_size;
6150 int num, actual_num, i;
6152 int ret = I40E_SUCCESS;
6153 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6154 struct i40e_aqc_remove_macvlan_element_data *req_list;
6156 if (filter == NULL || total == 0)
6157 return I40E_ERR_PARAM;
6159 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6160 ele_buff_size = hw->aq.asq_buf_size;
6162 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6163 if (req_list == NULL) {
6164 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6165 return I40E_ERR_NO_MEMORY;
6170 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6171 memset(req_list, 0, ele_buff_size);
6173 for (i = 0; i < actual_num; i++) {
6174 rte_memcpy(req_list[i].mac_addr,
6175 &filter[num + i].macaddr, ETH_ADDR_LEN);
6176 req_list[i].vlan_tag =
6177 rte_cpu_to_le_16(filter[num + i].vlan_id);
6179 switch (filter[num + i].filter_type) {
6180 case RTE_MAC_PERFECT_MATCH:
6181 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6182 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6184 case RTE_MACVLAN_PERFECT_MATCH:
6185 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6187 case RTE_MAC_HASH_MATCH:
6188 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6189 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6191 case RTE_MACVLAN_HASH_MATCH:
6192 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6195 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6196 ret = I40E_ERR_PARAM;
6199 req_list[i].flags = rte_cpu_to_le_16(flags);
6202 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6204 if (ret != I40E_SUCCESS) {
6205 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6209 } while (num < total);
6216 /* Find out specific MAC filter */
6217 static struct i40e_mac_filter *
6218 i40e_find_mac_filter(struct i40e_vsi *vsi,
6219 struct ether_addr *macaddr)
6221 struct i40e_mac_filter *f;
6223 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6224 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6232 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6235 uint32_t vid_idx, vid_bit;
6237 if (vlan_id > ETH_VLAN_ID_MAX)
6240 vid_idx = I40E_VFTA_IDX(vlan_id);
6241 vid_bit = I40E_VFTA_BIT(vlan_id);
6243 if (vsi->vfta[vid_idx] & vid_bit)
6250 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6251 uint16_t vlan_id, bool on)
6253 uint32_t vid_idx, vid_bit;
6255 vid_idx = I40E_VFTA_IDX(vlan_id);
6256 vid_bit = I40E_VFTA_BIT(vlan_id);
6259 vsi->vfta[vid_idx] |= vid_bit;
6261 vsi->vfta[vid_idx] &= ~vid_bit;
6265 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6266 uint16_t vlan_id, bool on)
6268 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6269 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6272 if (vlan_id > ETH_VLAN_ID_MAX)
6275 i40e_store_vlan_filter(vsi, vlan_id, on);
6277 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6280 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6283 ret = i40e_aq_add_vlan(hw, vsi->seid,
6284 &vlan_data, 1, NULL);
6285 if (ret != I40E_SUCCESS)
6286 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6288 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6289 &vlan_data, 1, NULL);
6290 if (ret != I40E_SUCCESS)
6292 "Failed to remove vlan filter");
6297 * Find all vlan options for specific mac addr,
6298 * return with actual vlan found.
6301 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6302 struct i40e_macvlan_filter *mv_f,
6303 int num, struct ether_addr *addr)
6309 * Not to use i40e_find_vlan_filter to decrease the loop time,
6310 * although the code looks complex.
6312 if (num < vsi->vlan_num)
6313 return I40E_ERR_PARAM;
6316 for (j = 0; j < I40E_VFTA_SIZE; j++) {
6318 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6319 if (vsi->vfta[j] & (1 << k)) {
6322 "vlan number doesn't match");
6323 return I40E_ERR_PARAM;
6325 rte_memcpy(&mv_f[i].macaddr,
6326 addr, ETH_ADDR_LEN);
6328 j * I40E_UINT32_BIT_SIZE + k;
6334 return I40E_SUCCESS;
6338 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6339 struct i40e_macvlan_filter *mv_f,
6344 struct i40e_mac_filter *f;
6346 if (num < vsi->mac_num)
6347 return I40E_ERR_PARAM;
6349 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6351 PMD_DRV_LOG(ERR, "buffer number not match");
6352 return I40E_ERR_PARAM;
6354 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6356 mv_f[i].vlan_id = vlan;
6357 mv_f[i].filter_type = f->mac_info.filter_type;
6361 return I40E_SUCCESS;
6365 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6368 struct i40e_mac_filter *f;
6369 struct i40e_macvlan_filter *mv_f;
6370 int ret = I40E_SUCCESS;
6372 if (vsi == NULL || vsi->mac_num == 0)
6373 return I40E_ERR_PARAM;
6375 /* Case that no vlan is set */
6376 if (vsi->vlan_num == 0)
6379 num = vsi->mac_num * vsi->vlan_num;
6381 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6383 PMD_DRV_LOG(ERR, "failed to allocate memory");
6384 return I40E_ERR_NO_MEMORY;
6388 if (vsi->vlan_num == 0) {
6389 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6390 rte_memcpy(&mv_f[i].macaddr,
6391 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6392 mv_f[i].filter_type = f->mac_info.filter_type;
6393 mv_f[i].vlan_id = 0;
6397 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6398 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6399 vsi->vlan_num, &f->mac_info.mac_addr);
6400 if (ret != I40E_SUCCESS)
6402 for (j = i; j < i + vsi->vlan_num; j++)
6403 mv_f[j].filter_type = f->mac_info.filter_type;
6408 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6416 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6418 struct i40e_macvlan_filter *mv_f;
6420 int ret = I40E_SUCCESS;
6422 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6423 return I40E_ERR_PARAM;
6425 /* If it's already set, just return */
6426 if (i40e_find_vlan_filter(vsi,vlan))
6427 return I40E_SUCCESS;
6429 mac_num = vsi->mac_num;
6432 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6433 return I40E_ERR_PARAM;
6436 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6439 PMD_DRV_LOG(ERR, "failed to allocate memory");
6440 return I40E_ERR_NO_MEMORY;
6443 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6445 if (ret != I40E_SUCCESS)
6448 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6450 if (ret != I40E_SUCCESS)
6453 i40e_set_vlan_filter(vsi, vlan, 1);
6463 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6465 struct i40e_macvlan_filter *mv_f;
6467 int ret = I40E_SUCCESS;
6470 * Vlan 0 is the generic filter for untagged packets
6471 * and can't be removed.
6473 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6474 return I40E_ERR_PARAM;
6476 /* If can't find it, just return */
6477 if (!i40e_find_vlan_filter(vsi, vlan))
6478 return I40E_ERR_PARAM;
6480 mac_num = vsi->mac_num;
6483 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6484 return I40E_ERR_PARAM;
6487 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6490 PMD_DRV_LOG(ERR, "failed to allocate memory");
6491 return I40E_ERR_NO_MEMORY;
6494 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6496 if (ret != I40E_SUCCESS)
6499 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6501 if (ret != I40E_SUCCESS)
6504 /* This is last vlan to remove, replace all mac filter with vlan 0 */
6505 if (vsi->vlan_num == 1) {
6506 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6507 if (ret != I40E_SUCCESS)
6510 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6511 if (ret != I40E_SUCCESS)
6515 i40e_set_vlan_filter(vsi, vlan, 0);
6525 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6527 struct i40e_mac_filter *f;
6528 struct i40e_macvlan_filter *mv_f;
6529 int i, vlan_num = 0;
6530 int ret = I40E_SUCCESS;
6532 /* If it's add and we've config it, return */
6533 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6535 return I40E_SUCCESS;
6536 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6537 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6540 * If vlan_num is 0, that's the first time to add mac,
6541 * set mask for vlan_id 0.
6543 if (vsi->vlan_num == 0) {
6544 i40e_set_vlan_filter(vsi, 0, 1);
6547 vlan_num = vsi->vlan_num;
6548 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6549 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6552 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6554 PMD_DRV_LOG(ERR, "failed to allocate memory");
6555 return I40E_ERR_NO_MEMORY;
6558 for (i = 0; i < vlan_num; i++) {
6559 mv_f[i].filter_type = mac_filter->filter_type;
6560 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6564 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6565 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6566 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6567 &mac_filter->mac_addr);
6568 if (ret != I40E_SUCCESS)
6572 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6573 if (ret != I40E_SUCCESS)
6576 /* Add the mac addr into mac list */
6577 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6579 PMD_DRV_LOG(ERR, "failed to allocate memory");
6580 ret = I40E_ERR_NO_MEMORY;
6583 rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6585 f->mac_info.filter_type = mac_filter->filter_type;
6586 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6597 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6599 struct i40e_mac_filter *f;
6600 struct i40e_macvlan_filter *mv_f;
6602 enum rte_mac_filter_type filter_type;
6603 int ret = I40E_SUCCESS;
6605 /* Can't find it, return an error */
6606 f = i40e_find_mac_filter(vsi, addr);
6608 return I40E_ERR_PARAM;
6610 vlan_num = vsi->vlan_num;
6611 filter_type = f->mac_info.filter_type;
6612 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6613 filter_type == RTE_MACVLAN_HASH_MATCH) {
6614 if (vlan_num == 0) {
6615 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6616 return I40E_ERR_PARAM;
6618 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6619 filter_type == RTE_MAC_HASH_MATCH)
6622 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6624 PMD_DRV_LOG(ERR, "failed to allocate memory");
6625 return I40E_ERR_NO_MEMORY;
6628 for (i = 0; i < vlan_num; i++) {
6629 mv_f[i].filter_type = filter_type;
6630 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6633 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6634 filter_type == RTE_MACVLAN_HASH_MATCH) {
6635 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6636 if (ret != I40E_SUCCESS)
6640 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6641 if (ret != I40E_SUCCESS)
6644 /* Remove the mac addr into mac list */
6645 TAILQ_REMOVE(&vsi->mac_list, f, next);
6655 /* Configure hash enable flags for RSS */
6657 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
6665 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6666 if (flags & (1ULL << i))
6667 hena |= adapter->pctypes_tbl[i];
6673 /* Parse the hash enable flags */
6675 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
6677 uint64_t rss_hf = 0;
6683 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6684 if (flags & adapter->pctypes_tbl[i])
6685 rss_hf |= (1ULL << i);
6692 i40e_pf_disable_rss(struct i40e_pf *pf)
6694 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6696 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
6697 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
6698 I40E_WRITE_FLUSH(hw);
6702 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6704 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6705 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6708 if (!key || key_len == 0) {
6709 PMD_DRV_LOG(DEBUG, "No key to be configured");
6711 } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6713 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6717 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6718 struct i40e_aqc_get_set_rss_key_data *key_dw =
6719 (struct i40e_aqc_get_set_rss_key_data *)key;
6721 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6723 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6725 uint32_t *hash_key = (uint32_t *)key;
6728 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6729 i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6730 I40E_WRITE_FLUSH(hw);
6737 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6739 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6740 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6743 if (!key || !key_len)
6746 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6747 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6748 (struct i40e_aqc_get_set_rss_key_data *)key);
6750 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6754 uint32_t *key_dw = (uint32_t *)key;
6757 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6758 key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6760 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6766 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6768 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6772 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6773 rss_conf->rss_key_len);
6777 hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
6778 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6779 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6780 I40E_WRITE_FLUSH(hw);
6786 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6787 struct rte_eth_rss_conf *rss_conf)
6789 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6790 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6791 uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
6794 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6795 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6797 if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
6798 if (rss_hf != 0) /* Enable RSS */
6800 return 0; /* Nothing to do */
6803 if (rss_hf == 0) /* Disable RSS */
6806 return i40e_hw_rss_hash_set(pf, rss_conf);
6810 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6811 struct rte_eth_rss_conf *rss_conf)
6813 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6814 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6817 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6818 &rss_conf->rss_key_len);
6820 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6821 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6822 rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
6828 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6830 switch (filter_type) {
6831 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6832 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6834 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6835 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6837 case RTE_TUNNEL_FILTER_IMAC_TENID:
6838 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6840 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6841 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6843 case ETH_TUNNEL_FILTER_IMAC:
6844 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6846 case ETH_TUNNEL_FILTER_OIP:
6847 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6849 case ETH_TUNNEL_FILTER_IIP:
6850 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6853 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6860 /* Convert tunnel filter structure */
6862 i40e_tunnel_filter_convert(
6863 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
6864 struct i40e_tunnel_filter *tunnel_filter)
6866 ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
6867 (struct ether_addr *)&tunnel_filter->input.outer_mac);
6868 ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
6869 (struct ether_addr *)&tunnel_filter->input.inner_mac);
6870 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
6871 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
6872 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6873 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6874 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6876 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6877 tunnel_filter->input.flags = cld_filter->element.flags;
6878 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
6879 tunnel_filter->queue = cld_filter->element.queue_number;
6880 rte_memcpy(tunnel_filter->input.general_fields,
6881 cld_filter->general_fields,
6882 sizeof(cld_filter->general_fields));
6887 /* Check if there exists the tunnel filter */
6888 struct i40e_tunnel_filter *
6889 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6890 const struct i40e_tunnel_filter_input *input)
6894 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6898 return tunnel_rule->hash_map[ret];
6901 /* Add a tunnel filter into the SW list */
6903 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6904 struct i40e_tunnel_filter *tunnel_filter)
6906 struct i40e_tunnel_rule *rule = &pf->tunnel;
6909 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6912 "Failed to insert tunnel filter to hash table %d!",
6916 rule->hash_map[ret] = tunnel_filter;
6918 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6923 /* Delete a tunnel filter from the SW list */
6925 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6926 struct i40e_tunnel_filter_input *input)
6928 struct i40e_tunnel_rule *rule = &pf->tunnel;
6929 struct i40e_tunnel_filter *tunnel_filter;
6932 ret = rte_hash_del_key(rule->hash_table, input);
6935 "Failed to delete tunnel filter to hash table %d!",
6939 tunnel_filter = rule->hash_map[ret];
6940 rule->hash_map[ret] = NULL;
6942 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6943 rte_free(tunnel_filter);
6949 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6950 struct rte_eth_tunnel_filter_conf *tunnel_filter,
6955 uint8_t i, tun_type = 0;
6956 /* internal varialbe to convert ipv6 byte order */
6957 uint32_t convert_ipv6[4];
6959 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6960 struct i40e_vsi *vsi = pf->main_vsi;
6961 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
6962 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
6963 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6964 struct i40e_tunnel_filter *tunnel, *node;
6965 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6967 cld_filter = rte_zmalloc("tunnel_filter",
6968 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
6971 if (NULL == cld_filter) {
6972 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6975 pfilter = cld_filter;
6977 ether_addr_copy(&tunnel_filter->outer_mac,
6978 (struct ether_addr *)&pfilter->element.outer_mac);
6979 ether_addr_copy(&tunnel_filter->inner_mac,
6980 (struct ether_addr *)&pfilter->element.inner_mac);
6982 pfilter->element.inner_vlan =
6983 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6984 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6985 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6986 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6987 rte_memcpy(&pfilter->element.ipaddr.v4.data,
6988 &rte_cpu_to_le_32(ipv4_addr),
6989 sizeof(pfilter->element.ipaddr.v4.data));
6991 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6992 for (i = 0; i < 4; i++) {
6994 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6996 rte_memcpy(&pfilter->element.ipaddr.v6.data,
6998 sizeof(pfilter->element.ipaddr.v6.data));
7001 /* check tunneled type */
7002 switch (tunnel_filter->tunnel_type) {
7003 case RTE_TUNNEL_TYPE_VXLAN:
7004 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7006 case RTE_TUNNEL_TYPE_NVGRE:
7007 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7009 case RTE_TUNNEL_TYPE_IP_IN_GRE:
7010 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7013 /* Other tunnel types is not supported. */
7014 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7015 rte_free(cld_filter);
7019 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7020 &pfilter->element.flags);
7022 rte_free(cld_filter);
7026 pfilter->element.flags |= rte_cpu_to_le_16(
7027 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7028 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7029 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7030 pfilter->element.queue_number =
7031 rte_cpu_to_le_16(tunnel_filter->queue_id);
7033 /* Check if there is the filter in SW list */
7034 memset(&check_filter, 0, sizeof(check_filter));
7035 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7036 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7038 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7042 if (!add && !node) {
7043 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7048 ret = i40e_aq_add_cloud_filters(hw,
7049 vsi->seid, &cld_filter->element, 1);
7051 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7054 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7055 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7056 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7058 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7059 &cld_filter->element, 1);
7061 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7064 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7067 rte_free(cld_filter);
7071 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7072 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
7073 #define I40E_TR_GENEVE_KEY_MASK 0x8
7074 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
7075 #define I40E_TR_GRE_KEY_MASK 0x400
7076 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
7077 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
7080 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7082 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7083 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7084 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7085 enum i40e_status_code status = I40E_SUCCESS;
7087 memset(&filter_replace, 0,
7088 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7089 memset(&filter_replace_buf, 0,
7090 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7092 /* create L1 filter */
7093 filter_replace.old_filter_type =
7094 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7095 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7096 filter_replace.tr_bit = 0;
7098 /* Prepare the buffer, 3 entries */
7099 filter_replace_buf.data[0] =
7100 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7101 filter_replace_buf.data[0] |=
7102 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7103 filter_replace_buf.data[2] = 0xFF;
7104 filter_replace_buf.data[3] = 0xFF;
7105 filter_replace_buf.data[4] =
7106 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7107 filter_replace_buf.data[4] |=
7108 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7109 filter_replace_buf.data[7] = 0xF0;
7110 filter_replace_buf.data[8]
7111 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7112 filter_replace_buf.data[8] |=
7113 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7114 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7115 I40E_TR_GENEVE_KEY_MASK |
7116 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7117 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7118 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7119 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7121 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7122 &filter_replace_buf);
7127 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7129 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7130 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7131 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7132 enum i40e_status_code status = I40E_SUCCESS;
7135 memset(&filter_replace, 0,
7136 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7137 memset(&filter_replace_buf, 0,
7138 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7139 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7140 I40E_AQC_MIRROR_CLOUD_FILTER;
7141 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7142 filter_replace.new_filter_type =
7143 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7144 /* Prepare the buffer, 2 entries */
7145 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7146 filter_replace_buf.data[0] |=
7147 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7148 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7149 filter_replace_buf.data[4] |=
7150 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7151 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7152 &filter_replace_buf);
7157 memset(&filter_replace, 0,
7158 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7159 memset(&filter_replace_buf, 0,
7160 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7162 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7163 I40E_AQC_MIRROR_CLOUD_FILTER;
7164 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7165 filter_replace.new_filter_type =
7166 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7167 /* Prepare the buffer, 2 entries */
7168 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7169 filter_replace_buf.data[0] |=
7170 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7171 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7172 filter_replace_buf.data[4] |=
7173 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7175 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7176 &filter_replace_buf);
7180 static enum i40e_status_code
7181 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7183 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7184 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7185 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7186 enum i40e_status_code status = I40E_SUCCESS;
7189 memset(&filter_replace, 0,
7190 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7191 memset(&filter_replace_buf, 0,
7192 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7193 /* create L1 filter */
7194 filter_replace.old_filter_type =
7195 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7196 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7197 filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7198 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7199 /* Prepare the buffer, 2 entries */
7200 filter_replace_buf.data[0] =
7201 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7202 filter_replace_buf.data[0] |=
7203 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7204 filter_replace_buf.data[2] = 0xFF;
7205 filter_replace_buf.data[3] = 0xFF;
7206 filter_replace_buf.data[4] =
7207 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7208 filter_replace_buf.data[4] |=
7209 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7210 filter_replace_buf.data[6] = 0xFF;
7211 filter_replace_buf.data[7] = 0xFF;
7212 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7213 &filter_replace_buf);
7218 memset(&filter_replace, 0,
7219 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7220 memset(&filter_replace_buf, 0,
7221 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7222 /* create L1 filter */
7223 filter_replace.old_filter_type =
7224 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
7225 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
7226 filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
7227 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7228 /* Prepare the buffer, 2 entries */
7229 filter_replace_buf.data[0] =
7230 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7231 filter_replace_buf.data[0] |=
7232 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7233 filter_replace_buf.data[2] = 0xFF;
7234 filter_replace_buf.data[3] = 0xFF;
7235 filter_replace_buf.data[4] =
7236 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7237 filter_replace_buf.data[4] |=
7238 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7239 filter_replace_buf.data[6] = 0xFF;
7240 filter_replace_buf.data[7] = 0xFF;
7242 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7243 &filter_replace_buf);
7248 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
7250 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7251 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7252 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7253 enum i40e_status_code status = I40E_SUCCESS;
7256 memset(&filter_replace, 0,
7257 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7258 memset(&filter_replace_buf, 0,
7259 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7260 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7261 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7262 filter_replace.new_filter_type =
7263 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7264 /* Prepare the buffer, 2 entries */
7265 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
7266 filter_replace_buf.data[0] |=
7267 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7268 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7269 filter_replace_buf.data[4] |=
7270 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7271 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7272 &filter_replace_buf);
7277 memset(&filter_replace, 0,
7278 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7279 memset(&filter_replace_buf, 0,
7280 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7281 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7282 filter_replace.old_filter_type =
7283 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7284 filter_replace.new_filter_type =
7285 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7286 /* Prepare the buffer, 2 entries */
7287 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
7288 filter_replace_buf.data[0] |=
7289 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7290 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7291 filter_replace_buf.data[4] |=
7292 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7294 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7295 &filter_replace_buf);
7300 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7301 struct i40e_tunnel_filter_conf *tunnel_filter,
7306 uint8_t i, tun_type = 0;
7307 /* internal variable to convert ipv6 byte order */
7308 uint32_t convert_ipv6[4];
7310 struct i40e_pf_vf *vf = NULL;
7311 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7312 struct i40e_vsi *vsi;
7313 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7314 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7315 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7316 struct i40e_tunnel_filter *tunnel, *node;
7317 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7319 bool big_buffer = 0;
7321 cld_filter = rte_zmalloc("tunnel_filter",
7322 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7325 if (cld_filter == NULL) {
7326 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7329 pfilter = cld_filter;
7331 ether_addr_copy(&tunnel_filter->outer_mac,
7332 (struct ether_addr *)&pfilter->element.outer_mac);
7333 ether_addr_copy(&tunnel_filter->inner_mac,
7334 (struct ether_addr *)&pfilter->element.inner_mac);
7336 pfilter->element.inner_vlan =
7337 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7338 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7339 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7340 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7341 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7342 &rte_cpu_to_le_32(ipv4_addr),
7343 sizeof(pfilter->element.ipaddr.v4.data));
7345 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7346 for (i = 0; i < 4; i++) {
7348 rte_cpu_to_le_32(rte_be_to_cpu_32(
7349 tunnel_filter->ip_addr.ipv6_addr[i]));
7351 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7353 sizeof(pfilter->element.ipaddr.v6.data));
7356 /* check tunneled type */
7357 switch (tunnel_filter->tunnel_type) {
7358 case I40E_TUNNEL_TYPE_VXLAN:
7359 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7361 case I40E_TUNNEL_TYPE_NVGRE:
7362 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7364 case I40E_TUNNEL_TYPE_IP_IN_GRE:
7365 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7367 case I40E_TUNNEL_TYPE_MPLSoUDP:
7368 if (!pf->mpls_replace_flag) {
7369 i40e_replace_mpls_l1_filter(pf);
7370 i40e_replace_mpls_cloud_filter(pf);
7371 pf->mpls_replace_flag = 1;
7373 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7374 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7376 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7377 (teid_le & 0xF) << 12;
7378 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7381 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
7383 case I40E_TUNNEL_TYPE_MPLSoGRE:
7384 if (!pf->mpls_replace_flag) {
7385 i40e_replace_mpls_l1_filter(pf);
7386 i40e_replace_mpls_cloud_filter(pf);
7387 pf->mpls_replace_flag = 1;
7389 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7390 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7392 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7393 (teid_le & 0xF) << 12;
7394 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7397 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
7399 case I40E_TUNNEL_TYPE_GTPC:
7400 if (!pf->gtp_replace_flag) {
7401 i40e_replace_gtp_l1_filter(pf);
7402 i40e_replace_gtp_cloud_filter(pf);
7403 pf->gtp_replace_flag = 1;
7405 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7406 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
7407 (teid_le >> 16) & 0xFFFF;
7408 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
7410 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
7414 case I40E_TUNNEL_TYPE_GTPU:
7415 if (!pf->gtp_replace_flag) {
7416 i40e_replace_gtp_l1_filter(pf);
7417 i40e_replace_gtp_cloud_filter(pf);
7418 pf->gtp_replace_flag = 1;
7420 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7421 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
7422 (teid_le >> 16) & 0xFFFF;
7423 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
7425 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
7429 case I40E_TUNNEL_TYPE_QINQ:
7430 if (!pf->qinq_replace_flag) {
7431 ret = i40e_cloud_filter_qinq_create(pf);
7434 "QinQ tunnel filter already created.");
7435 pf->qinq_replace_flag = 1;
7437 /* Add in the General fields the values of
7438 * the Outer and Inner VLAN
7439 * Big Buffer should be set, see changes in
7440 * i40e_aq_add_cloud_filters
7442 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7443 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7447 /* Other tunnel types is not supported. */
7448 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7449 rte_free(cld_filter);
7453 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7454 pfilter->element.flags =
7455 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7456 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7457 pfilter->element.flags =
7458 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7459 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
7460 pfilter->element.flags =
7461 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7462 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
7463 pfilter->element.flags =
7464 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7465 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7466 pfilter->element.flags |=
7467 I40E_AQC_ADD_CLOUD_FILTER_0X10;
7469 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7470 &pfilter->element.flags);
7472 rte_free(cld_filter);
7477 pfilter->element.flags |= rte_cpu_to_le_16(
7478 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7479 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7480 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7481 pfilter->element.queue_number =
7482 rte_cpu_to_le_16(tunnel_filter->queue_id);
7484 if (!tunnel_filter->is_to_vf)
7487 if (tunnel_filter->vf_id >= pf->vf_num) {
7488 PMD_DRV_LOG(ERR, "Invalid argument.");
7491 vf = &pf->vfs[tunnel_filter->vf_id];
7495 /* Check if there is the filter in SW list */
7496 memset(&check_filter, 0, sizeof(check_filter));
7497 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7498 check_filter.is_to_vf = tunnel_filter->is_to_vf;
7499 check_filter.vf_id = tunnel_filter->vf_id;
7500 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7502 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7506 if (!add && !node) {
7507 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7513 ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7514 vsi->seid, cld_filter, 1);
7516 ret = i40e_aq_add_cloud_filters(hw,
7517 vsi->seid, &cld_filter->element, 1);
7519 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7522 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7523 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7524 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7527 ret = i40e_aq_remove_cloud_filters_big_buffer(
7528 hw, vsi->seid, cld_filter, 1);
7530 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7531 &cld_filter->element, 1);
7533 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7536 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7539 rte_free(cld_filter);
7544 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7548 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7549 if (pf->vxlan_ports[i] == port)
7557 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7561 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7563 idx = i40e_get_vxlan_port_idx(pf, port);
7565 /* Check if port already exists */
7567 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7571 /* Now check if there is space to add the new port */
7572 idx = i40e_get_vxlan_port_idx(pf, 0);
7575 "Maximum number of UDP ports reached, not adding port %d",
7580 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7583 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7587 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7590 /* New port: add it and mark its index in the bitmap */
7591 pf->vxlan_ports[idx] = port;
7592 pf->vxlan_bitmap |= (1 << idx);
7594 if (!(pf->flags & I40E_FLAG_VXLAN))
7595 pf->flags |= I40E_FLAG_VXLAN;
7601 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7604 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7606 if (!(pf->flags & I40E_FLAG_VXLAN)) {
7607 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7611 idx = i40e_get_vxlan_port_idx(pf, port);
7614 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7618 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7619 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7623 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7626 pf->vxlan_ports[idx] = 0;
7627 pf->vxlan_bitmap &= ~(1 << idx);
7629 if (!pf->vxlan_bitmap)
7630 pf->flags &= ~I40E_FLAG_VXLAN;
7635 /* Add UDP tunneling port */
7637 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7638 struct rte_eth_udp_tunnel *udp_tunnel)
7641 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7643 if (udp_tunnel == NULL)
7646 switch (udp_tunnel->prot_type) {
7647 case RTE_TUNNEL_TYPE_VXLAN:
7648 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7651 case RTE_TUNNEL_TYPE_GENEVE:
7652 case RTE_TUNNEL_TYPE_TEREDO:
7653 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7658 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7666 /* Remove UDP tunneling port */
7668 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7669 struct rte_eth_udp_tunnel *udp_tunnel)
7672 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7674 if (udp_tunnel == NULL)
7677 switch (udp_tunnel->prot_type) {
7678 case RTE_TUNNEL_TYPE_VXLAN:
7679 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7681 case RTE_TUNNEL_TYPE_GENEVE:
7682 case RTE_TUNNEL_TYPE_TEREDO:
7683 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7687 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7695 /* Calculate the maximum number of contiguous PF queues that are configured */
7697 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7699 struct rte_eth_dev_data *data = pf->dev_data;
7701 struct i40e_rx_queue *rxq;
7704 for (i = 0; i < pf->lan_nb_qps; i++) {
7705 rxq = data->rx_queues[i];
7706 if (rxq && rxq->q_set)
7717 i40e_pf_config_rss(struct i40e_pf *pf)
7719 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7720 struct rte_eth_rss_conf rss_conf;
7721 uint32_t i, lut = 0;
7725 * If both VMDQ and RSS enabled, not all of PF queues are configured.
7726 * It's necessary to calculate the actual PF queues that are configured.
7728 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7729 num = i40e_pf_calc_configured_queues_num(pf);
7731 num = pf->dev_data->nb_rx_queues;
7733 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7734 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7738 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7742 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7745 lut = (lut << 8) | (j & ((0x1 <<
7746 hw->func_caps.rss_table_entry_width) - 1));
7748 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7751 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7752 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
7753 i40e_pf_disable_rss(pf);
7756 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7757 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7758 /* Random default keys */
7759 static uint32_t rss_key_default[] = {0x6b793944,
7760 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7761 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7762 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7764 rss_conf.rss_key = (uint8_t *)rss_key_default;
7765 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7769 return i40e_hw_rss_hash_set(pf, &rss_conf);
7773 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7774 struct rte_eth_tunnel_filter_conf *filter)
7776 if (pf == NULL || filter == NULL) {
7777 PMD_DRV_LOG(ERR, "Invalid parameter");
7781 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7782 PMD_DRV_LOG(ERR, "Invalid queue ID");
7786 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7787 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7791 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7792 (is_zero_ether_addr(&filter->outer_mac))) {
7793 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7797 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7798 (is_zero_ether_addr(&filter->inner_mac))) {
7799 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7806 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7807 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
7809 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7814 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7815 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7818 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7819 } else if (len == 4) {
7820 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7822 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7827 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7834 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7835 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7841 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7848 switch (cfg->cfg_type) {
7849 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7850 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7853 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7861 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7862 enum rte_filter_op filter_op,
7865 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7866 int ret = I40E_ERR_PARAM;
7868 switch (filter_op) {
7869 case RTE_ETH_FILTER_SET:
7870 ret = i40e_dev_global_config_set(hw,
7871 (struct rte_eth_global_cfg *)arg);
7874 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7882 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7883 enum rte_filter_op filter_op,
7886 struct rte_eth_tunnel_filter_conf *filter;
7887 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7888 int ret = I40E_SUCCESS;
7890 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7892 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7893 return I40E_ERR_PARAM;
7895 switch (filter_op) {
7896 case RTE_ETH_FILTER_NOP:
7897 if (!(pf->flags & I40E_FLAG_VXLAN))
7898 ret = I40E_NOT_SUPPORTED;
7900 case RTE_ETH_FILTER_ADD:
7901 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7903 case RTE_ETH_FILTER_DELETE:
7904 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7907 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7908 ret = I40E_ERR_PARAM;
7916 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7919 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7922 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7923 ret = i40e_pf_config_rss(pf);
7925 i40e_pf_disable_rss(pf);
7930 /* Get the symmetric hash enable configurations per port */
7932 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7934 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7936 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7939 /* Set the symmetric hash enable configurations per port */
7941 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7943 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7946 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7948 "Symmetric hash has already been enabled");
7951 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7953 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7955 "Symmetric hash has already been disabled");
7958 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7960 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7961 I40E_WRITE_FLUSH(hw);
7965 * Get global configurations of hash function type and symmetric hash enable
7966 * per flow type (pctype). Note that global configuration means it affects all
7967 * the ports on the same NIC.
7970 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7971 struct rte_eth_hash_global_conf *g_cfg)
7973 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
7977 memset(g_cfg, 0, sizeof(*g_cfg));
7978 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7979 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7980 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7982 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7983 PMD_DRV_LOG(DEBUG, "Hash function is %s",
7984 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7987 * We work only with lowest 32 bits which is not correct, but to work
7988 * properly the valid_bit_mask size should be increased up to 64 bits
7989 * and this will brake ABI. This modification will be done in next
7992 g_cfg->valid_bit_mask[0] = (uint32_t)adapter->flow_types_mask;
7994 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT32_BIT; i++) {
7995 if (!adapter->pctypes_tbl[i])
7997 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
7998 j < I40E_FILTER_PCTYPE_MAX; j++) {
7999 if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8000 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8001 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8002 g_cfg->sym_hash_enable_mask[0] |=
8013 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8014 const struct rte_eth_hash_global_conf *g_cfg)
8017 uint32_t mask0, i40e_mask = adapter->flow_types_mask;
8019 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8020 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8021 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8022 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8028 * As i40e supports less than 32 flow types, only first 32 bits need to
8031 mask0 = g_cfg->valid_bit_mask[0];
8032 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8034 /* Check if any unsupported flow type configured */
8035 if ((mask0 | i40e_mask) ^ i40e_mask)
8038 if (g_cfg->valid_bit_mask[i])
8046 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8052 * Set global configurations of hash function type and symmetric hash enable
8053 * per flow type (pctype). Note any modifying global configuration will affect
8054 * all the ports on the same NIC.
8057 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8058 struct rte_eth_hash_global_conf *g_cfg)
8060 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8065 * We work only with lowest 32 bits which is not correct, but to work
8066 * properly the valid_bit_mask size should be increased up to 64 bits
8067 * and this will brake ABI. This modification will be done in next
8070 uint32_t mask0 = g_cfg->valid_bit_mask[0] &
8071 (uint32_t)adapter->flow_types_mask;
8073 /* Check the input parameters */
8074 ret = i40e_hash_global_config_check(adapter, g_cfg);
8078 for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT32_BIT; i++) {
8079 if (mask0 & (1UL << i)) {
8080 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
8081 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8083 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8084 j < I40E_FILTER_PCTYPE_MAX; j++) {
8085 if (adapter->pctypes_tbl[i] & (1ULL << j))
8086 i40e_write_rx_ctl(hw,
8093 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8094 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8096 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8098 "Hash function already set to Toeplitz");
8101 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8102 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8104 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8106 "Hash function already set to Simple XOR");
8109 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8111 /* Use the default, and keep it as it is */
8114 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
8117 I40E_WRITE_FLUSH(hw);
8123 * Valid input sets for hash and flow director filters per PCTYPE
8126 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8127 enum rte_filter_type filter)
8131 static const uint64_t valid_hash_inset_table[] = {
8132 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8133 I40E_INSET_DMAC | I40E_INSET_SMAC |
8134 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8135 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8136 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8137 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8138 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8139 I40E_INSET_FLEX_PAYLOAD,
8140 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8141 I40E_INSET_DMAC | I40E_INSET_SMAC |
8142 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8143 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8144 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8145 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8146 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8147 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8148 I40E_INSET_FLEX_PAYLOAD,
8149 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8150 I40E_INSET_DMAC | I40E_INSET_SMAC |
8151 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8152 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8153 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8154 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8155 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8156 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8157 I40E_INSET_FLEX_PAYLOAD,
8158 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8159 I40E_INSET_DMAC | I40E_INSET_SMAC |
8160 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8161 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8162 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8163 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8164 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8165 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8166 I40E_INSET_FLEX_PAYLOAD,
8167 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8168 I40E_INSET_DMAC | I40E_INSET_SMAC |
8169 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8170 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8171 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8172 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8173 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8174 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8175 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8176 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8177 I40E_INSET_DMAC | I40E_INSET_SMAC |
8178 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8179 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8180 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8181 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8182 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8183 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8184 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8185 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8186 I40E_INSET_DMAC | I40E_INSET_SMAC |
8187 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8188 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8189 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8190 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8191 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8192 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8193 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8194 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8195 I40E_INSET_DMAC | I40E_INSET_SMAC |
8196 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8197 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8198 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8199 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8200 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8201 I40E_INSET_FLEX_PAYLOAD,
8202 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8203 I40E_INSET_DMAC | I40E_INSET_SMAC |
8204 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8205 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8206 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8207 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8208 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8209 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8210 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8211 I40E_INSET_DMAC | I40E_INSET_SMAC |
8212 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8213 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8214 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8215 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8216 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8217 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8218 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8219 I40E_INSET_DMAC | I40E_INSET_SMAC |
8220 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8221 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8222 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8223 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8224 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8225 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8226 I40E_INSET_FLEX_PAYLOAD,
8227 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8228 I40E_INSET_DMAC | I40E_INSET_SMAC |
8229 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8230 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8231 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8232 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8233 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8234 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8235 I40E_INSET_FLEX_PAYLOAD,
8236 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8237 I40E_INSET_DMAC | I40E_INSET_SMAC |
8238 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8239 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8240 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8241 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8242 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8243 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8244 I40E_INSET_FLEX_PAYLOAD,
8245 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8246 I40E_INSET_DMAC | I40E_INSET_SMAC |
8247 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8248 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8249 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8250 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8251 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8252 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8253 I40E_INSET_FLEX_PAYLOAD,
8254 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8255 I40E_INSET_DMAC | I40E_INSET_SMAC |
8256 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8257 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8258 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8259 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8260 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8261 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8262 I40E_INSET_FLEX_PAYLOAD,
8263 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8264 I40E_INSET_DMAC | I40E_INSET_SMAC |
8265 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8266 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8267 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8268 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8269 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8270 I40E_INSET_FLEX_PAYLOAD,
8271 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8272 I40E_INSET_DMAC | I40E_INSET_SMAC |
8273 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8274 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8275 I40E_INSET_FLEX_PAYLOAD,
8279 * Flow director supports only fields defined in
8280 * union rte_eth_fdir_flow.
8282 static const uint64_t valid_fdir_inset_table[] = {
8283 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8284 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8285 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8286 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8287 I40E_INSET_IPV4_TTL,
8288 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8289 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8290 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8291 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8292 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8293 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8294 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8295 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8296 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8297 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8298 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8299 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8300 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8301 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8302 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8303 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8304 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8305 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8306 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8307 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8308 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8309 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8310 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8311 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8312 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8313 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8314 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8315 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8316 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8317 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8319 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8320 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8321 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8322 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8323 I40E_INSET_IPV4_TTL,
8324 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8325 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8326 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8327 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8328 I40E_INSET_IPV6_HOP_LIMIT,
8329 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8330 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8331 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8332 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8333 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8334 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8335 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8336 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8337 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8338 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8339 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8340 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8341 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8342 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8343 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8344 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8345 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8346 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8347 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8348 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8349 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8350 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8351 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8352 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8353 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8354 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8355 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8356 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8357 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8358 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8360 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8361 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8362 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8363 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8364 I40E_INSET_IPV6_HOP_LIMIT,
8365 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8366 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8367 I40E_INSET_LAST_ETHER_TYPE,
8370 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8372 if (filter == RTE_ETH_FILTER_HASH)
8373 valid = valid_hash_inset_table[pctype];
8375 valid = valid_fdir_inset_table[pctype];
8381 * Validate if the input set is allowed for a specific PCTYPE
8384 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8385 enum rte_filter_type filter, uint64_t inset)
8389 valid = i40e_get_valid_input_set(pctype, filter);
8390 if (inset & (~valid))
8396 /* default input set fields combination per pctype */
8398 i40e_get_default_input_set(uint16_t pctype)
8400 static const uint64_t default_inset_table[] = {
8401 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8402 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8403 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8404 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8405 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8406 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8407 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8408 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8409 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8410 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8411 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8412 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8413 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8414 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8415 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8416 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8417 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8418 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8419 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8420 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8422 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8423 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8424 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8425 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8426 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8427 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8428 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8429 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8430 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8431 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8432 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8433 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8434 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8435 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8436 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8437 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8438 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8439 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8440 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8441 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8442 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8443 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8445 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8446 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8447 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8448 I40E_INSET_LAST_ETHER_TYPE,
8451 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8454 return default_inset_table[pctype];
8458 * Parse the input set from index to logical bit masks
8461 i40e_parse_input_set(uint64_t *inset,
8462 enum i40e_filter_pctype pctype,
8463 enum rte_eth_input_set_field *field,
8469 static const struct {
8470 enum rte_eth_input_set_field field;
8472 } inset_convert_table[] = {
8473 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8474 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8475 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8476 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8477 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8478 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8479 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8480 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8481 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8482 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8483 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8484 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8485 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8486 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8487 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8488 I40E_INSET_IPV6_NEXT_HDR},
8489 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8490 I40E_INSET_IPV6_HOP_LIMIT},
8491 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8492 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8493 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8494 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8495 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8496 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8497 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8498 I40E_INSET_SCTP_VT},
8499 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8500 I40E_INSET_TUNNEL_DMAC},
8501 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8502 I40E_INSET_VLAN_TUNNEL},
8503 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8504 I40E_INSET_TUNNEL_ID},
8505 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8506 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8507 I40E_INSET_FLEX_PAYLOAD_W1},
8508 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8509 I40E_INSET_FLEX_PAYLOAD_W2},
8510 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8511 I40E_INSET_FLEX_PAYLOAD_W3},
8512 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8513 I40E_INSET_FLEX_PAYLOAD_W4},
8514 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8515 I40E_INSET_FLEX_PAYLOAD_W5},
8516 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8517 I40E_INSET_FLEX_PAYLOAD_W6},
8518 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8519 I40E_INSET_FLEX_PAYLOAD_W7},
8520 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8521 I40E_INSET_FLEX_PAYLOAD_W8},
8524 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8527 /* Only one item allowed for default or all */
8529 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8530 *inset = i40e_get_default_input_set(pctype);
8532 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8533 *inset = I40E_INSET_NONE;
8538 for (i = 0, *inset = 0; i < size; i++) {
8539 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8540 if (field[i] == inset_convert_table[j].field) {
8541 *inset |= inset_convert_table[j].inset;
8546 /* It contains unsupported input set, return immediately */
8547 if (j == RTE_DIM(inset_convert_table))
8555 * Translate the input set from bit masks to register aware bit masks
8559 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8569 static const struct inset_map inset_map_common[] = {
8570 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8571 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8572 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8573 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8574 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8575 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8576 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8577 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8578 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8579 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8580 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8581 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8582 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8583 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8584 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8585 {I40E_INSET_TUNNEL_DMAC,
8586 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8587 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8588 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8589 {I40E_INSET_TUNNEL_SRC_PORT,
8590 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8591 {I40E_INSET_TUNNEL_DST_PORT,
8592 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8593 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8594 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8595 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8596 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8597 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8598 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8599 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8600 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8601 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8604 /* some different registers map in x722*/
8605 static const struct inset_map inset_map_diff_x722[] = {
8606 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8607 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8608 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8609 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8612 static const struct inset_map inset_map_diff_not_x722[] = {
8613 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8614 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8615 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8616 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8622 /* Translate input set to register aware inset */
8623 if (type == I40E_MAC_X722) {
8624 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8625 if (input & inset_map_diff_x722[i].inset)
8626 val |= inset_map_diff_x722[i].inset_reg;
8629 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8630 if (input & inset_map_diff_not_x722[i].inset)
8631 val |= inset_map_diff_not_x722[i].inset_reg;
8635 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8636 if (input & inset_map_common[i].inset)
8637 val |= inset_map_common[i].inset_reg;
8644 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8647 uint64_t inset_need_mask = inset;
8649 static const struct {
8652 } inset_mask_map[] = {
8653 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8654 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8655 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8656 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8657 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8658 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8659 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8660 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8663 if (!inset || !mask || !nb_elem)
8666 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8667 /* Clear the inset bit, if no MASK is required,
8668 * for example proto + ttl
8670 if ((inset & inset_mask_map[i].inset) ==
8671 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8672 inset_need_mask &= ~inset_mask_map[i].inset;
8673 if (!inset_need_mask)
8676 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8677 if ((inset_need_mask & inset_mask_map[i].inset) ==
8678 inset_mask_map[i].inset) {
8679 if (idx >= nb_elem) {
8680 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8683 mask[idx] = inset_mask_map[i].mask;
8692 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8694 uint32_t reg = i40e_read_rx_ctl(hw, addr);
8696 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8698 i40e_write_rx_ctl(hw, addr, val);
8699 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8700 (uint32_t)i40e_read_rx_ctl(hw, addr));
8704 i40e_filter_input_set_init(struct i40e_pf *pf)
8706 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8707 enum i40e_filter_pctype pctype;
8708 uint64_t input_set, inset_reg;
8709 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8713 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8714 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8715 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
8717 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
8720 input_set = i40e_get_default_input_set(pctype);
8722 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8723 I40E_INSET_MASK_NUM_REG);
8726 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8729 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8730 (uint32_t)(inset_reg & UINT32_MAX));
8731 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8732 (uint32_t)((inset_reg >>
8733 I40E_32_BIT_WIDTH) & UINT32_MAX));
8734 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8735 (uint32_t)(inset_reg & UINT32_MAX));
8736 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8737 (uint32_t)((inset_reg >>
8738 I40E_32_BIT_WIDTH) & UINT32_MAX));
8740 for (i = 0; i < num; i++) {
8741 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8743 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8746 /*clear unused mask registers of the pctype */
8747 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8748 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8750 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8753 I40E_WRITE_FLUSH(hw);
8755 /* store the default input set */
8756 pf->hash_input_set[pctype] = input_set;
8757 pf->fdir.input_set[pctype] = input_set;
8762 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8763 struct rte_eth_input_set_conf *conf)
8765 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8766 enum i40e_filter_pctype pctype;
8767 uint64_t input_set, inset_reg = 0;
8768 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8772 PMD_DRV_LOG(ERR, "Invalid pointer");
8775 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8776 conf->op != RTE_ETH_INPUT_SET_ADD) {
8777 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8781 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
8782 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
8783 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8787 if (hw->mac.type == I40E_MAC_X722) {
8788 /* get translated pctype value in fd pctype register */
8789 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8790 I40E_GLQF_FD_PCTYPES((int)pctype));
8793 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8796 PMD_DRV_LOG(ERR, "Failed to parse input set");
8800 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8801 /* get inset value in register */
8802 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8803 inset_reg <<= I40E_32_BIT_WIDTH;
8804 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8805 input_set |= pf->hash_input_set[pctype];
8807 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8808 I40E_INSET_MASK_NUM_REG);
8812 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8814 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8815 (uint32_t)(inset_reg & UINT32_MAX));
8816 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8817 (uint32_t)((inset_reg >>
8818 I40E_32_BIT_WIDTH) & UINT32_MAX));
8820 for (i = 0; i < num; i++)
8821 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8823 /*clear unused mask registers of the pctype */
8824 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8825 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8827 I40E_WRITE_FLUSH(hw);
8829 pf->hash_input_set[pctype] = input_set;
8834 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8835 struct rte_eth_input_set_conf *conf)
8837 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8838 enum i40e_filter_pctype pctype;
8839 uint64_t input_set, inset_reg = 0;
8840 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8844 PMD_DRV_LOG(ERR, "Invalid pointer");
8847 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8848 conf->op != RTE_ETH_INPUT_SET_ADD) {
8849 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8853 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
8855 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
8856 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8860 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8863 PMD_DRV_LOG(ERR, "Failed to parse input set");
8867 /* get inset value in register */
8868 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8869 inset_reg <<= I40E_32_BIT_WIDTH;
8870 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8872 /* Can not change the inset reg for flex payload for fdir,
8873 * it is done by writing I40E_PRTQF_FD_FLXINSET
8874 * in i40e_set_flex_mask_on_pctype.
8876 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8877 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8879 input_set |= pf->fdir.input_set[pctype];
8880 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8881 I40E_INSET_MASK_NUM_REG);
8885 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8887 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8888 (uint32_t)(inset_reg & UINT32_MAX));
8889 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8890 (uint32_t)((inset_reg >>
8891 I40E_32_BIT_WIDTH) & UINT32_MAX));
8893 for (i = 0; i < num; i++)
8894 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8896 /*clear unused mask registers of the pctype */
8897 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8898 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8900 I40E_WRITE_FLUSH(hw);
8902 pf->fdir.input_set[pctype] = input_set;
8907 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8912 PMD_DRV_LOG(ERR, "Invalid pointer");
8916 switch (info->info_type) {
8917 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8918 i40e_get_symmetric_hash_enable_per_port(hw,
8919 &(info->info.enable));
8921 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8922 ret = i40e_get_hash_filter_global_config(hw,
8923 &(info->info.global_conf));
8926 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8936 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8941 PMD_DRV_LOG(ERR, "Invalid pointer");
8945 switch (info->info_type) {
8946 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8947 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8949 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8950 ret = i40e_set_hash_filter_global_config(hw,
8951 &(info->info.global_conf));
8953 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8954 ret = i40e_hash_filter_inset_select(hw,
8955 &(info->info.input_set_conf));
8959 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8968 /* Operations for hash function */
8970 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8971 enum rte_filter_op filter_op,
8974 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8977 switch (filter_op) {
8978 case RTE_ETH_FILTER_NOP:
8980 case RTE_ETH_FILTER_GET:
8981 ret = i40e_hash_filter_get(hw,
8982 (struct rte_eth_hash_filter_info *)arg);
8984 case RTE_ETH_FILTER_SET:
8985 ret = i40e_hash_filter_set(hw,
8986 (struct rte_eth_hash_filter_info *)arg);
8989 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8998 /* Convert ethertype filter structure */
9000 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9001 struct i40e_ethertype_filter *filter)
9003 rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
9004 filter->input.ether_type = input->ether_type;
9005 filter->flags = input->flags;
9006 filter->queue = input->queue;
9011 /* Check if there exists the ehtertype filter */
9012 struct i40e_ethertype_filter *
9013 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9014 const struct i40e_ethertype_filter_input *input)
9018 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9022 return ethertype_rule->hash_map[ret];
9025 /* Add ethertype filter in SW list */
9027 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9028 struct i40e_ethertype_filter *filter)
9030 struct i40e_ethertype_rule *rule = &pf->ethertype;
9033 ret = rte_hash_add_key(rule->hash_table, &filter->input);
9036 "Failed to insert ethertype filter"
9037 " to hash table %d!",
9041 rule->hash_map[ret] = filter;
9043 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9048 /* Delete ethertype filter in SW list */
9050 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9051 struct i40e_ethertype_filter_input *input)
9053 struct i40e_ethertype_rule *rule = &pf->ethertype;
9054 struct i40e_ethertype_filter *filter;
9057 ret = rte_hash_del_key(rule->hash_table, input);
9060 "Failed to delete ethertype filter"
9061 " to hash table %d!",
9065 filter = rule->hash_map[ret];
9066 rule->hash_map[ret] = NULL;
9068 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9075 * Configure ethertype filter, which can director packet by filtering
9076 * with mac address and ether_type or only ether_type
9079 i40e_ethertype_filter_set(struct i40e_pf *pf,
9080 struct rte_eth_ethertype_filter *filter,
9083 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9084 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9085 struct i40e_ethertype_filter *ethertype_filter, *node;
9086 struct i40e_ethertype_filter check_filter;
9087 struct i40e_control_filter_stats stats;
9091 if (filter->queue >= pf->dev_data->nb_rx_queues) {
9092 PMD_DRV_LOG(ERR, "Invalid queue ID");
9095 if (filter->ether_type == ETHER_TYPE_IPv4 ||
9096 filter->ether_type == ETHER_TYPE_IPv6) {
9098 "unsupported ether_type(0x%04x) in control packet filter.",
9099 filter->ether_type);
9102 if (filter->ether_type == ETHER_TYPE_VLAN)
9103 PMD_DRV_LOG(WARNING,
9104 "filter vlan ether_type in first tag is not supported.");
9106 /* Check if there is the filter in SW list */
9107 memset(&check_filter, 0, sizeof(check_filter));
9108 i40e_ethertype_filter_convert(filter, &check_filter);
9109 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9110 &check_filter.input);
9112 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9116 if (!add && !node) {
9117 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9121 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9122 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9123 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9124 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9125 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9127 memset(&stats, 0, sizeof(stats));
9128 ret = i40e_aq_add_rem_control_packet_filter(hw,
9129 filter->mac_addr.addr_bytes,
9130 filter->ether_type, flags,
9132 filter->queue, add, &stats, NULL);
9135 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9136 ret, stats.mac_etype_used, stats.etype_used,
9137 stats.mac_etype_free, stats.etype_free);
9141 /* Add or delete a filter in SW list */
9143 ethertype_filter = rte_zmalloc("ethertype_filter",
9144 sizeof(*ethertype_filter), 0);
9145 rte_memcpy(ethertype_filter, &check_filter,
9146 sizeof(check_filter));
9147 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9149 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9156 * Handle operations for ethertype filter.
9159 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9160 enum rte_filter_op filter_op,
9163 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9166 if (filter_op == RTE_ETH_FILTER_NOP)
9170 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9175 switch (filter_op) {
9176 case RTE_ETH_FILTER_ADD:
9177 ret = i40e_ethertype_filter_set(pf,
9178 (struct rte_eth_ethertype_filter *)arg,
9181 case RTE_ETH_FILTER_DELETE:
9182 ret = i40e_ethertype_filter_set(pf,
9183 (struct rte_eth_ethertype_filter *)arg,
9187 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9195 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9196 enum rte_filter_type filter_type,
9197 enum rte_filter_op filter_op,
9205 switch (filter_type) {
9206 case RTE_ETH_FILTER_NONE:
9207 /* For global configuration */
9208 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9210 case RTE_ETH_FILTER_HASH:
9211 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9213 case RTE_ETH_FILTER_MACVLAN:
9214 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9216 case RTE_ETH_FILTER_ETHERTYPE:
9217 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9219 case RTE_ETH_FILTER_TUNNEL:
9220 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9222 case RTE_ETH_FILTER_FDIR:
9223 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9225 case RTE_ETH_FILTER_GENERIC:
9226 if (filter_op != RTE_ETH_FILTER_GET)
9228 *(const void **)arg = &i40e_flow_ops;
9231 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9241 * Check and enable Extended Tag.
9242 * Enabling Extended Tag is important for 40G performance.
9245 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9247 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9251 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9254 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9258 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9259 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9264 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9267 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9271 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9272 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9275 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9276 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9279 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9286 * As some registers wouldn't be reset unless a global hardware reset,
9287 * hardware initialization is needed to put those registers into an
9288 * expected initial state.
9291 i40e_hw_init(struct rte_eth_dev *dev)
9293 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9295 i40e_enable_extended_tag(dev);
9297 /* clear the PF Queue Filter control register */
9298 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9300 /* Disable symmetric hash per port */
9301 i40e_set_symmetric_hash_enable_per_port(hw, 0);
9305 * For X722 it is possible to have multiple pctypes mapped to the same flowtype
9306 * however this function will return only one highest pctype index,
9307 * which is not quite correct. This is known problem of i40e driver
9308 * and needs to be fixed later.
9310 enum i40e_filter_pctype
9311 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
9314 uint64_t pctype_mask;
9316 if (flow_type < I40E_FLOW_TYPE_MAX) {
9317 pctype_mask = adapter->pctypes_tbl[flow_type];
9318 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
9319 if (pctype_mask & (1ULL << i))
9320 return (enum i40e_filter_pctype)i;
9323 return I40E_FILTER_PCTYPE_INVALID;
9327 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
9328 enum i40e_filter_pctype pctype)
9331 uint64_t pctype_mask = 1ULL << pctype;
9333 for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
9335 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
9339 return RTE_ETH_FLOW_UNKNOWN;
9343 * On X710, performance number is far from the expectation on recent firmware
9344 * versions; on XL710, performance number is also far from the expectation on
9345 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9346 * mode is enabled and port MAC address is equal to the packet destination MAC
9347 * address. The fix for this issue may not be integrated in the following
9348 * firmware version. So the workaround in software driver is needed. It needs
9349 * to modify the initial values of 3 internal only registers for both X710 and
9350 * XL710. Note that the values for X710 or XL710 could be different, and the
9351 * workaround can be removed when it is fixed in firmware in the future.
9354 /* For both X710 and XL710 */
9355 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1 0x10000200
9356 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x20000200
9357 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
9359 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9360 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
9363 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9364 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9367 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
9369 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
9370 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
9373 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9375 enum i40e_status_code status;
9376 struct i40e_aq_get_phy_abilities_resp phy_ab;
9380 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9384 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
9387 rte_delay_us(100000);
9389 status = i40e_aq_get_phy_capabilities(hw, false,
9390 true, &phy_ab, NULL);
9398 i40e_configure_registers(struct i40e_hw *hw)
9404 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9405 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9406 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9412 for (i = 0; i < RTE_DIM(reg_table); i++) {
9413 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9414 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9416 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9417 else /* For X710/XL710/XXV710 */
9418 if (hw->aq.fw_maj_ver < 6)
9420 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
9423 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
9426 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9427 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9429 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9430 else /* For X710/XL710/XXV710 */
9432 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9435 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9436 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9437 I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9439 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9442 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9445 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9448 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9452 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9453 reg_table[i].addr, reg);
9454 if (reg == reg_table[i].val)
9457 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9458 reg_table[i].val, NULL);
9461 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9462 reg_table[i].val, reg_table[i].addr);
9465 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9466 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9470 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
9471 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
9472 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
9473 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9475 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9480 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9481 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9485 /* Configure for double VLAN RX stripping */
9486 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9487 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9488 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9489 ret = i40e_aq_debug_write_register(hw,
9490 I40E_VSI_TSR(vsi->vsi_id),
9493 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9495 return I40E_ERR_CONFIG;
9499 /* Configure for double VLAN TX insertion */
9500 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9501 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9502 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9503 ret = i40e_aq_debug_write_register(hw,
9504 I40E_VSI_L2TAGSTXVALID(
9505 vsi->vsi_id), reg, NULL);
9508 "Failed to update VSI_L2TAGSTXVALID[%d]",
9510 return I40E_ERR_CONFIG;
9518 * i40e_aq_add_mirror_rule
9519 * @hw: pointer to the hardware structure
9520 * @seid: VEB seid to add mirror rule to
9521 * @dst_id: destination vsi seid
9522 * @entries: Buffer which contains the entities to be mirrored
9523 * @count: number of entities contained in the buffer
9524 * @rule_id:the rule_id of the rule to be added
9526 * Add a mirror rule for a given veb.
9529 static enum i40e_status_code
9530 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9531 uint16_t seid, uint16_t dst_id,
9532 uint16_t rule_type, uint16_t *entries,
9533 uint16_t count, uint16_t *rule_id)
9535 struct i40e_aq_desc desc;
9536 struct i40e_aqc_add_delete_mirror_rule cmd;
9537 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9538 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9541 enum i40e_status_code status;
9543 i40e_fill_default_direct_cmd_desc(&desc,
9544 i40e_aqc_opc_add_mirror_rule);
9545 memset(&cmd, 0, sizeof(cmd));
9547 buff_len = sizeof(uint16_t) * count;
9548 desc.datalen = rte_cpu_to_le_16(buff_len);
9550 desc.flags |= rte_cpu_to_le_16(
9551 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9552 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9553 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9554 cmd.num_entries = rte_cpu_to_le_16(count);
9555 cmd.seid = rte_cpu_to_le_16(seid);
9556 cmd.destination = rte_cpu_to_le_16(dst_id);
9558 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9559 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9561 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9562 hw->aq.asq_last_status, resp->rule_id,
9563 resp->mirror_rules_used, resp->mirror_rules_free);
9564 *rule_id = rte_le_to_cpu_16(resp->rule_id);
9570 * i40e_aq_del_mirror_rule
9571 * @hw: pointer to the hardware structure
9572 * @seid: VEB seid to add mirror rule to
9573 * @entries: Buffer which contains the entities to be mirrored
9574 * @count: number of entities contained in the buffer
9575 * @rule_id:the rule_id of the rule to be delete
9577 * Delete a mirror rule for a given veb.
9580 static enum i40e_status_code
9581 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9582 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9583 uint16_t count, uint16_t rule_id)
9585 struct i40e_aq_desc desc;
9586 struct i40e_aqc_add_delete_mirror_rule cmd;
9587 uint16_t buff_len = 0;
9588 enum i40e_status_code status;
9591 i40e_fill_default_direct_cmd_desc(&desc,
9592 i40e_aqc_opc_delete_mirror_rule);
9593 memset(&cmd, 0, sizeof(cmd));
9594 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9595 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9597 cmd.num_entries = count;
9598 buff_len = sizeof(uint16_t) * count;
9599 desc.datalen = rte_cpu_to_le_16(buff_len);
9600 buff = (void *)entries;
9602 /* rule id is filled in destination field for deleting mirror rule */
9603 cmd.destination = rte_cpu_to_le_16(rule_id);
9605 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9606 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9607 cmd.seid = rte_cpu_to_le_16(seid);
9609 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9610 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9616 * i40e_mirror_rule_set
9617 * @dev: pointer to the hardware structure
9618 * @mirror_conf: mirror rule info
9619 * @sw_id: mirror rule's sw_id
9620 * @on: enable/disable
9622 * set a mirror rule.
9626 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9627 struct rte_eth_mirror_conf *mirror_conf,
9628 uint8_t sw_id, uint8_t on)
9630 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9631 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9632 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9633 struct i40e_mirror_rule *parent = NULL;
9634 uint16_t seid, dst_seid, rule_id;
9638 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9640 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9642 "mirror rule can not be configured without veb or vfs.");
9645 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9646 PMD_DRV_LOG(ERR, "mirror table is full.");
9649 if (mirror_conf->dst_pool > pf->vf_num) {
9650 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9651 mirror_conf->dst_pool);
9655 seid = pf->main_vsi->veb->seid;
9657 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9658 if (sw_id <= it->index) {
9664 if (mirr_rule && sw_id == mirr_rule->index) {
9666 PMD_DRV_LOG(ERR, "mirror rule exists.");
9669 ret = i40e_aq_del_mirror_rule(hw, seid,
9670 mirr_rule->rule_type,
9672 mirr_rule->num_entries, mirr_rule->id);
9675 "failed to remove mirror rule: ret = %d, aq_err = %d.",
9676 ret, hw->aq.asq_last_status);
9679 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9680 rte_free(mirr_rule);
9681 pf->nb_mirror_rule--;
9685 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9689 mirr_rule = rte_zmalloc("i40e_mirror_rule",
9690 sizeof(struct i40e_mirror_rule) , 0);
9692 PMD_DRV_LOG(ERR, "failed to allocate memory");
9693 return I40E_ERR_NO_MEMORY;
9695 switch (mirror_conf->rule_type) {
9696 case ETH_MIRROR_VLAN:
9697 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9698 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9699 mirr_rule->entries[j] =
9700 mirror_conf->vlan.vlan_id[i];
9705 PMD_DRV_LOG(ERR, "vlan is not specified.");
9706 rte_free(mirr_rule);
9709 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9711 case ETH_MIRROR_VIRTUAL_POOL_UP:
9712 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9713 /* check if the specified pool bit is out of range */
9714 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9715 PMD_DRV_LOG(ERR, "pool mask is out of range.");
9716 rte_free(mirr_rule);
9719 for (i = 0, j = 0; i < pf->vf_num; i++) {
9720 if (mirror_conf->pool_mask & (1ULL << i)) {
9721 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9725 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9726 /* add pf vsi to entries */
9727 mirr_rule->entries[j] = pf->main_vsi_seid;
9731 PMD_DRV_LOG(ERR, "pool is not specified.");
9732 rte_free(mirr_rule);
9735 /* egress and ingress in aq commands means from switch but not port */
9736 mirr_rule->rule_type =
9737 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9738 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9739 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9741 case ETH_MIRROR_UPLINK_PORT:
9742 /* egress and ingress in aq commands means from switch but not port*/
9743 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9745 case ETH_MIRROR_DOWNLINK_PORT:
9746 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9749 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9750 mirror_conf->rule_type);
9751 rte_free(mirr_rule);
9755 /* If the dst_pool is equal to vf_num, consider it as PF */
9756 if (mirror_conf->dst_pool == pf->vf_num)
9757 dst_seid = pf->main_vsi_seid;
9759 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9761 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9762 mirr_rule->rule_type, mirr_rule->entries,
9766 "failed to add mirror rule: ret = %d, aq_err = %d.",
9767 ret, hw->aq.asq_last_status);
9768 rte_free(mirr_rule);
9772 mirr_rule->index = sw_id;
9773 mirr_rule->num_entries = j;
9774 mirr_rule->id = rule_id;
9775 mirr_rule->dst_vsi_seid = dst_seid;
9778 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9780 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9782 pf->nb_mirror_rule++;
9787 * i40e_mirror_rule_reset
9788 * @dev: pointer to the device
9789 * @sw_id: mirror rule's sw_id
9791 * reset a mirror rule.
9795 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9797 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9798 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9799 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9803 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9805 seid = pf->main_vsi->veb->seid;
9807 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9808 if (sw_id == it->index) {
9814 ret = i40e_aq_del_mirror_rule(hw, seid,
9815 mirr_rule->rule_type,
9817 mirr_rule->num_entries, mirr_rule->id);
9820 "failed to remove mirror rule: status = %d, aq_err = %d.",
9821 ret, hw->aq.asq_last_status);
9824 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9825 rte_free(mirr_rule);
9826 pf->nb_mirror_rule--;
9828 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9835 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9837 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9838 uint64_t systim_cycles;
9840 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9841 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9844 return systim_cycles;
9848 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9850 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9853 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9854 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9861 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9863 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9866 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9867 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9874 i40e_start_timecounters(struct rte_eth_dev *dev)
9876 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9877 struct i40e_adapter *adapter =
9878 (struct i40e_adapter *)dev->data->dev_private;
9879 struct rte_eth_link link;
9880 uint32_t tsync_inc_l;
9881 uint32_t tsync_inc_h;
9883 /* Get current link speed. */
9884 memset(&link, 0, sizeof(link));
9885 i40e_dev_link_update(dev, 1);
9886 rte_i40e_dev_atomic_read_link_status(dev, &link);
9888 switch (link.link_speed) {
9889 case ETH_SPEED_NUM_40G:
9890 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9891 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9893 case ETH_SPEED_NUM_10G:
9894 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9895 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9897 case ETH_SPEED_NUM_1G:
9898 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9899 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9906 /* Set the timesync increment value. */
9907 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9908 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9910 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9911 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9912 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9914 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9915 adapter->systime_tc.cc_shift = 0;
9916 adapter->systime_tc.nsec_mask = 0;
9918 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9919 adapter->rx_tstamp_tc.cc_shift = 0;
9920 adapter->rx_tstamp_tc.nsec_mask = 0;
9922 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9923 adapter->tx_tstamp_tc.cc_shift = 0;
9924 adapter->tx_tstamp_tc.nsec_mask = 0;
9928 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9930 struct i40e_adapter *adapter =
9931 (struct i40e_adapter *)dev->data->dev_private;
9933 adapter->systime_tc.nsec += delta;
9934 adapter->rx_tstamp_tc.nsec += delta;
9935 adapter->tx_tstamp_tc.nsec += delta;
9941 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9944 struct i40e_adapter *adapter =
9945 (struct i40e_adapter *)dev->data->dev_private;
9947 ns = rte_timespec_to_ns(ts);
9949 /* Set the timecounters to a new value. */
9950 adapter->systime_tc.nsec = ns;
9951 adapter->rx_tstamp_tc.nsec = ns;
9952 adapter->tx_tstamp_tc.nsec = ns;
9958 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9960 uint64_t ns, systime_cycles;
9961 struct i40e_adapter *adapter =
9962 (struct i40e_adapter *)dev->data->dev_private;
9964 systime_cycles = i40e_read_systime_cyclecounter(dev);
9965 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9966 *ts = rte_ns_to_timespec(ns);
9972 i40e_timesync_enable(struct rte_eth_dev *dev)
9974 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9975 uint32_t tsync_ctl_l;
9976 uint32_t tsync_ctl_h;
9978 /* Stop the timesync system time. */
9979 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9980 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9981 /* Reset the timesync system time value. */
9982 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9983 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9985 i40e_start_timecounters(dev);
9987 /* Clear timesync registers. */
9988 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9989 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9990 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9991 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9992 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9993 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9995 /* Enable timestamping of PTP packets. */
9996 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9997 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9999 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10000 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10001 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10003 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10004 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10010 i40e_timesync_disable(struct rte_eth_dev *dev)
10012 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10013 uint32_t tsync_ctl_l;
10014 uint32_t tsync_ctl_h;
10016 /* Disable timestamping of transmitted PTP packets. */
10017 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10018 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10020 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10021 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10023 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10024 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10026 /* Reset the timesync increment value. */
10027 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10028 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10034 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10035 struct timespec *timestamp, uint32_t flags)
10037 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10038 struct i40e_adapter *adapter =
10039 (struct i40e_adapter *)dev->data->dev_private;
10041 uint32_t sync_status;
10042 uint32_t index = flags & 0x03;
10043 uint64_t rx_tstamp_cycles;
10046 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10047 if ((sync_status & (1 << index)) == 0)
10050 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10051 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10052 *timestamp = rte_ns_to_timespec(ns);
10058 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10059 struct timespec *timestamp)
10061 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10062 struct i40e_adapter *adapter =
10063 (struct i40e_adapter *)dev->data->dev_private;
10065 uint32_t sync_status;
10066 uint64_t tx_tstamp_cycles;
10069 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10070 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10073 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10074 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10075 *timestamp = rte_ns_to_timespec(ns);
10081 * i40e_parse_dcb_configure - parse dcb configure from user
10082 * @dev: the device being configured
10083 * @dcb_cfg: pointer of the result of parse
10084 * @*tc_map: bit map of enabled traffic classes
10086 * Returns 0 on success, negative value on failure
10089 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10090 struct i40e_dcbx_config *dcb_cfg,
10093 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10094 uint8_t i, tc_bw, bw_lf;
10096 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10098 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10099 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10100 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10104 /* assume each tc has the same bw */
10105 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10106 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10107 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10108 /* to ensure the sum of tcbw is equal to 100 */
10109 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10110 for (i = 0; i < bw_lf; i++)
10111 dcb_cfg->etscfg.tcbwtable[i]++;
10113 /* assume each tc has the same Transmission Selection Algorithm */
10114 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10115 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10117 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10118 dcb_cfg->etscfg.prioritytable[i] =
10119 dcb_rx_conf->dcb_tc[i];
10121 /* FW needs one App to configure HW */
10122 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10123 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10124 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10125 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10127 if (dcb_rx_conf->nb_tcs == 0)
10128 *tc_map = 1; /* tc0 only */
10130 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10132 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10133 dcb_cfg->pfc.willing = 0;
10134 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10135 dcb_cfg->pfc.pfcenable = *tc_map;
10141 static enum i40e_status_code
10142 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10143 struct i40e_aqc_vsi_properties_data *info,
10144 uint8_t enabled_tcmap)
10146 enum i40e_status_code ret;
10147 int i, total_tc = 0;
10148 uint16_t qpnum_per_tc, bsf, qp_idx;
10149 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10150 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10151 uint16_t used_queues;
10153 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10154 if (ret != I40E_SUCCESS)
10157 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10158 if (enabled_tcmap & (1 << i))
10163 vsi->enabled_tc = enabled_tcmap;
10165 /* different VSI has different queues assigned */
10166 if (vsi->type == I40E_VSI_MAIN)
10167 used_queues = dev_data->nb_rx_queues -
10168 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10169 else if (vsi->type == I40E_VSI_VMDQ2)
10170 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10172 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10173 return I40E_ERR_NO_AVAILABLE_VSI;
10176 qpnum_per_tc = used_queues / total_tc;
10177 /* Number of queues per enabled TC */
10178 if (qpnum_per_tc == 0) {
10179 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10180 return I40E_ERR_INVALID_QP_ID;
10182 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10183 I40E_MAX_Q_PER_TC);
10184 bsf = rte_bsf32(qpnum_per_tc);
10187 * Configure TC and queue mapping parameters, for enabled TC,
10188 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10189 * default queue will serve it.
10192 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10193 if (vsi->enabled_tc & (1 << i)) {
10194 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10195 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10196 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10197 qp_idx += qpnum_per_tc;
10199 info->tc_mapping[i] = 0;
10202 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10203 if (vsi->type == I40E_VSI_SRIOV) {
10204 info->mapping_flags |=
10205 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10206 for (i = 0; i < vsi->nb_qps; i++)
10207 info->queue_mapping[i] =
10208 rte_cpu_to_le_16(vsi->base_queue + i);
10210 info->mapping_flags |=
10211 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10212 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10214 info->valid_sections |=
10215 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10217 return I40E_SUCCESS;
10221 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10222 * @veb: VEB to be configured
10223 * @tc_map: enabled TC bitmap
10225 * Returns 0 on success, negative value on failure
10227 static enum i40e_status_code
10228 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10230 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10231 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10232 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10233 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10234 enum i40e_status_code ret = I40E_SUCCESS;
10238 /* Check if enabled_tc is same as existing or new TCs */
10239 if (veb->enabled_tc == tc_map)
10242 /* configure tc bandwidth */
10243 memset(&veb_bw, 0, sizeof(veb_bw));
10244 veb_bw.tc_valid_bits = tc_map;
10245 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10246 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10247 if (tc_map & BIT_ULL(i))
10248 veb_bw.tc_bw_share_credits[i] = 1;
10250 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10254 "AQ command Config switch_comp BW allocation per TC failed = %d",
10255 hw->aq.asq_last_status);
10259 memset(&ets_query, 0, sizeof(ets_query));
10260 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10262 if (ret != I40E_SUCCESS) {
10264 "Failed to get switch_comp ETS configuration %u",
10265 hw->aq.asq_last_status);
10268 memset(&bw_query, 0, sizeof(bw_query));
10269 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10271 if (ret != I40E_SUCCESS) {
10273 "Failed to get switch_comp bandwidth configuration %u",
10274 hw->aq.asq_last_status);
10278 /* store and print out BW info */
10279 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10280 veb->bw_info.bw_max = ets_query.tc_bw_max;
10281 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10282 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10283 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10284 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10285 I40E_16_BIT_WIDTH);
10286 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10287 veb->bw_info.bw_ets_share_credits[i] =
10288 bw_query.tc_bw_share_credits[i];
10289 veb->bw_info.bw_ets_credits[i] =
10290 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10291 /* 4 bits per TC, 4th bit is reserved */
10292 veb->bw_info.bw_ets_max[i] =
10293 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10294 RTE_LEN2MASK(3, uint8_t));
10295 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10296 veb->bw_info.bw_ets_share_credits[i]);
10297 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10298 veb->bw_info.bw_ets_credits[i]);
10299 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10300 veb->bw_info.bw_ets_max[i]);
10303 veb->enabled_tc = tc_map;
10310 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10311 * @vsi: VSI to be configured
10312 * @tc_map: enabled TC bitmap
10314 * Returns 0 on success, negative value on failure
10316 static enum i40e_status_code
10317 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10319 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10320 struct i40e_vsi_context ctxt;
10321 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10322 enum i40e_status_code ret = I40E_SUCCESS;
10325 /* Check if enabled_tc is same as existing or new TCs */
10326 if (vsi->enabled_tc == tc_map)
10329 /* configure tc bandwidth */
10330 memset(&bw_data, 0, sizeof(bw_data));
10331 bw_data.tc_valid_bits = tc_map;
10332 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10333 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10334 if (tc_map & BIT_ULL(i))
10335 bw_data.tc_bw_credits[i] = 1;
10337 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10340 "AQ command Config VSI BW allocation per TC failed = %d",
10341 hw->aq.asq_last_status);
10344 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10345 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10347 /* Update Queue Pairs Mapping for currently enabled UPs */
10348 ctxt.seid = vsi->seid;
10349 ctxt.pf_num = hw->pf_id;
10351 ctxt.uplink_seid = vsi->uplink_seid;
10352 ctxt.info = vsi->info;
10354 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10358 /* Update the VSI after updating the VSI queue-mapping information */
10359 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10361 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10362 hw->aq.asq_last_status);
10365 /* update the local VSI info with updated queue map */
10366 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10367 sizeof(vsi->info.tc_mapping));
10368 rte_memcpy(&vsi->info.queue_mapping,
10369 &ctxt.info.queue_mapping,
10370 sizeof(vsi->info.queue_mapping));
10371 vsi->info.mapping_flags = ctxt.info.mapping_flags;
10372 vsi->info.valid_sections = 0;
10374 /* query and update current VSI BW information */
10375 ret = i40e_vsi_get_bw_config(vsi);
10378 "Failed updating vsi bw info, err %s aq_err %s",
10379 i40e_stat_str(hw, ret),
10380 i40e_aq_str(hw, hw->aq.asq_last_status));
10384 vsi->enabled_tc = tc_map;
10391 * i40e_dcb_hw_configure - program the dcb setting to hw
10392 * @pf: pf the configuration is taken on
10393 * @new_cfg: new configuration
10394 * @tc_map: enabled TC bitmap
10396 * Returns 0 on success, negative value on failure
10398 static enum i40e_status_code
10399 i40e_dcb_hw_configure(struct i40e_pf *pf,
10400 struct i40e_dcbx_config *new_cfg,
10403 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10404 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10405 struct i40e_vsi *main_vsi = pf->main_vsi;
10406 struct i40e_vsi_list *vsi_list;
10407 enum i40e_status_code ret;
10411 /* Use the FW API if FW > v4.4*/
10412 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10413 (hw->aq.fw_maj_ver >= 5))) {
10415 "FW < v4.4, can not use FW LLDP API to configure DCB");
10416 return I40E_ERR_FIRMWARE_API_VERSION;
10419 /* Check if need reconfiguration */
10420 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10421 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10422 return I40E_SUCCESS;
10425 /* Copy the new config to the current config */
10426 *old_cfg = *new_cfg;
10427 old_cfg->etsrec = old_cfg->etscfg;
10428 ret = i40e_set_dcb_config(hw);
10430 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10431 i40e_stat_str(hw, ret),
10432 i40e_aq_str(hw, hw->aq.asq_last_status));
10435 /* set receive Arbiter to RR mode and ETS scheme by default */
10436 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10437 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10438 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
10439 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10440 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10441 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10442 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10443 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10444 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10445 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10446 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10447 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10448 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10450 /* get local mib to check whether it is configured correctly */
10452 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10453 /* Get Local DCB Config */
10454 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10455 &hw->local_dcbx_config);
10457 /* if Veb is created, need to update TC of it at first */
10458 if (main_vsi->veb) {
10459 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10461 PMD_INIT_LOG(WARNING,
10462 "Failed configuring TC for VEB seid=%d",
10463 main_vsi->veb->seid);
10465 /* Update each VSI */
10466 i40e_vsi_config_tc(main_vsi, tc_map);
10467 if (main_vsi->veb) {
10468 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10469 /* Beside main VSI and VMDQ VSIs, only enable default
10470 * TC for other VSIs
10472 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10473 ret = i40e_vsi_config_tc(vsi_list->vsi,
10476 ret = i40e_vsi_config_tc(vsi_list->vsi,
10477 I40E_DEFAULT_TCMAP);
10479 PMD_INIT_LOG(WARNING,
10480 "Failed configuring TC for VSI seid=%d",
10481 vsi_list->vsi->seid);
10485 return I40E_SUCCESS;
10489 * i40e_dcb_init_configure - initial dcb config
10490 * @dev: device being configured
10491 * @sw_dcb: indicate whether dcb is sw configured or hw offload
10493 * Returns 0 on success, negative value on failure
10496 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10498 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10499 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10502 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10503 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10507 /* DCB initialization:
10508 * Update DCB configuration from the Firmware and configure
10509 * LLDP MIB change event.
10511 if (sw_dcb == TRUE) {
10512 ret = i40e_init_dcb(hw);
10513 /* If lldp agent is stopped, the return value from
10514 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10515 * adminq status. Otherwise, it should return success.
10517 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10518 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10519 memset(&hw->local_dcbx_config, 0,
10520 sizeof(struct i40e_dcbx_config));
10521 /* set dcb default configuration */
10522 hw->local_dcbx_config.etscfg.willing = 0;
10523 hw->local_dcbx_config.etscfg.maxtcs = 0;
10524 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10525 hw->local_dcbx_config.etscfg.tsatable[0] =
10527 /* all UPs mapping to TC0 */
10528 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10529 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10530 hw->local_dcbx_config.etsrec =
10531 hw->local_dcbx_config.etscfg;
10532 hw->local_dcbx_config.pfc.willing = 0;
10533 hw->local_dcbx_config.pfc.pfccap =
10534 I40E_MAX_TRAFFIC_CLASS;
10535 /* FW needs one App to configure HW */
10536 hw->local_dcbx_config.numapps = 1;
10537 hw->local_dcbx_config.app[0].selector =
10538 I40E_APP_SEL_ETHTYPE;
10539 hw->local_dcbx_config.app[0].priority = 3;
10540 hw->local_dcbx_config.app[0].protocolid =
10541 I40E_APP_PROTOID_FCOE;
10542 ret = i40e_set_dcb_config(hw);
10545 "default dcb config fails. err = %d, aq_err = %d.",
10546 ret, hw->aq.asq_last_status);
10551 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10552 ret, hw->aq.asq_last_status);
10556 ret = i40e_aq_start_lldp(hw, NULL);
10557 if (ret != I40E_SUCCESS)
10558 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10560 ret = i40e_init_dcb(hw);
10562 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10564 "HW doesn't support DCBX offload.");
10569 "DCBX configuration failed, err = %d, aq_err = %d.",
10570 ret, hw->aq.asq_last_status);
10578 * i40e_dcb_setup - setup dcb related config
10579 * @dev: device being configured
10581 * Returns 0 on success, negative value on failure
10584 i40e_dcb_setup(struct rte_eth_dev *dev)
10586 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10587 struct i40e_dcbx_config dcb_cfg;
10588 uint8_t tc_map = 0;
10591 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10592 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10596 if (pf->vf_num != 0)
10597 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10599 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10601 PMD_INIT_LOG(ERR, "invalid dcb config");
10604 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10606 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10614 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10615 struct rte_eth_dcb_info *dcb_info)
10617 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10618 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10619 struct i40e_vsi *vsi = pf->main_vsi;
10620 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10621 uint16_t bsf, tc_mapping;
10624 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10625 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10627 dcb_info->nb_tcs = 1;
10628 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10629 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10630 for (i = 0; i < dcb_info->nb_tcs; i++)
10631 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10633 /* get queue mapping if vmdq is disabled */
10634 if (!pf->nb_cfg_vmdq_vsi) {
10635 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10636 if (!(vsi->enabled_tc & (1 << i)))
10638 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10639 dcb_info->tc_queue.tc_rxq[j][i].base =
10640 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10641 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10642 dcb_info->tc_queue.tc_txq[j][i].base =
10643 dcb_info->tc_queue.tc_rxq[j][i].base;
10644 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10645 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10646 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10647 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10648 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10653 /* get queue mapping if vmdq is enabled */
10655 vsi = pf->vmdq[j].vsi;
10656 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10657 if (!(vsi->enabled_tc & (1 << i)))
10659 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10660 dcb_info->tc_queue.tc_rxq[j][i].base =
10661 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10662 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10663 dcb_info->tc_queue.tc_txq[j][i].base =
10664 dcb_info->tc_queue.tc_rxq[j][i].base;
10665 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10666 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10667 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10668 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10669 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10672 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10677 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10679 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10680 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10681 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10682 uint16_t interval =
10683 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10684 uint16_t msix_intr;
10686 msix_intr = intr_handle->intr_vec[queue_id];
10687 if (msix_intr == I40E_MISC_VEC_ID)
10688 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10689 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10690 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10691 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10693 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10696 I40E_PFINT_DYN_CTLN(msix_intr -
10697 I40E_RX_VEC_START),
10698 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10699 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10700 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10702 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10704 I40E_WRITE_FLUSH(hw);
10705 rte_intr_enable(&pci_dev->intr_handle);
10711 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10713 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10714 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10715 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10716 uint16_t msix_intr;
10718 msix_intr = intr_handle->intr_vec[queue_id];
10719 if (msix_intr == I40E_MISC_VEC_ID)
10720 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10723 I40E_PFINT_DYN_CTLN(msix_intr -
10724 I40E_RX_VEC_START),
10726 I40E_WRITE_FLUSH(hw);
10731 static int i40e_get_regs(struct rte_eth_dev *dev,
10732 struct rte_dev_reg_info *regs)
10734 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10735 uint32_t *ptr_data = regs->data;
10736 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10737 const struct i40e_reg_info *reg_info;
10739 if (ptr_data == NULL) {
10740 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10741 regs->width = sizeof(uint32_t);
10745 /* The first few registers have to be read using AQ operations */
10747 while (i40e_regs_adminq[reg_idx].name) {
10748 reg_info = &i40e_regs_adminq[reg_idx++];
10749 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10751 arr_idx2 <= reg_info->count2;
10753 reg_offset = arr_idx * reg_info->stride1 +
10754 arr_idx2 * reg_info->stride2;
10755 reg_offset += reg_info->base_addr;
10756 ptr_data[reg_offset >> 2] =
10757 i40e_read_rx_ctl(hw, reg_offset);
10761 /* The remaining registers can be read using primitives */
10763 while (i40e_regs_others[reg_idx].name) {
10764 reg_info = &i40e_regs_others[reg_idx++];
10765 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10767 arr_idx2 <= reg_info->count2;
10769 reg_offset = arr_idx * reg_info->stride1 +
10770 arr_idx2 * reg_info->stride2;
10771 reg_offset += reg_info->base_addr;
10772 ptr_data[reg_offset >> 2] =
10773 I40E_READ_REG(hw, reg_offset);
10780 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10782 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10784 /* Convert word count to byte count */
10785 return hw->nvm.sr_size << 1;
10788 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10789 struct rte_dev_eeprom_info *eeprom)
10791 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10792 uint16_t *data = eeprom->data;
10793 uint16_t offset, length, cnt_words;
10796 offset = eeprom->offset >> 1;
10797 length = eeprom->length >> 1;
10798 cnt_words = length;
10800 if (offset > hw->nvm.sr_size ||
10801 offset + length > hw->nvm.sr_size) {
10802 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10806 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10808 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10809 if (ret_code != I40E_SUCCESS || cnt_words != length) {
10810 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10817 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10818 struct ether_addr *mac_addr)
10820 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10822 if (!is_valid_assigned_ether_addr(mac_addr)) {
10823 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10827 /* Flags: 0x3 updates port address */
10828 i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10832 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10834 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10835 struct rte_eth_dev_data *dev_data = pf->dev_data;
10836 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
10839 /* check if mtu is within the allowed range */
10840 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10843 /* mtu setting is forbidden if port is start */
10844 if (dev_data->dev_started) {
10845 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10846 dev_data->port_id);
10850 if (frame_size > ETHER_MAX_LEN)
10851 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10853 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10855 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10860 /* Restore ethertype filter */
10862 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10864 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10865 struct i40e_ethertype_filter_list
10866 *ethertype_list = &pf->ethertype.ethertype_list;
10867 struct i40e_ethertype_filter *f;
10868 struct i40e_control_filter_stats stats;
10871 TAILQ_FOREACH(f, ethertype_list, rules) {
10873 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10874 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10875 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10876 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10877 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10879 memset(&stats, 0, sizeof(stats));
10880 i40e_aq_add_rem_control_packet_filter(hw,
10881 f->input.mac_addr.addr_bytes,
10882 f->input.ether_type,
10883 flags, pf->main_vsi->seid,
10884 f->queue, 1, &stats, NULL);
10886 PMD_DRV_LOG(INFO, "Ethertype filter:"
10887 " mac_etype_used = %u, etype_used = %u,"
10888 " mac_etype_free = %u, etype_free = %u",
10889 stats.mac_etype_used, stats.etype_used,
10890 stats.mac_etype_free, stats.etype_free);
10893 /* Restore tunnel filter */
10895 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10897 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10898 struct i40e_vsi *vsi;
10899 struct i40e_pf_vf *vf;
10900 struct i40e_tunnel_filter_list
10901 *tunnel_list = &pf->tunnel.tunnel_list;
10902 struct i40e_tunnel_filter *f;
10903 struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
10904 bool big_buffer = 0;
10906 TAILQ_FOREACH(f, tunnel_list, rules) {
10908 vsi = pf->main_vsi;
10910 vf = &pf->vfs[f->vf_id];
10913 memset(&cld_filter, 0, sizeof(cld_filter));
10914 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
10915 (struct ether_addr *)&cld_filter.element.outer_mac);
10916 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
10917 (struct ether_addr *)&cld_filter.element.inner_mac);
10918 cld_filter.element.inner_vlan = f->input.inner_vlan;
10919 cld_filter.element.flags = f->input.flags;
10920 cld_filter.element.tenant_id = f->input.tenant_id;
10921 cld_filter.element.queue_number = f->queue;
10922 rte_memcpy(cld_filter.general_fields,
10923 f->input.general_fields,
10924 sizeof(f->input.general_fields));
10926 if (((f->input.flags &
10927 I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
10928 I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
10930 I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
10931 I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
10933 I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
10934 I40E_AQC_ADD_CLOUD_FILTER_0X10))
10938 i40e_aq_add_cloud_filters_big_buffer(hw,
10939 vsi->seid, &cld_filter, 1);
10941 i40e_aq_add_cloud_filters(hw, vsi->seid,
10942 &cld_filter.element, 1);
10947 i40e_filter_restore(struct i40e_pf *pf)
10949 i40e_ethertype_filter_restore(pf);
10950 i40e_tunnel_filter_restore(pf);
10951 i40e_fdir_filter_restore(pf);
10955 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
10957 if (strcmp(dev->device->driver->name, drv->driver.name))
10964 is_i40e_supported(struct rte_eth_dev *dev)
10966 return is_device_supported(dev, &rte_i40e_pmd);
10969 struct i40e_customized_pctype*
10970 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
10974 for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
10975 if (pf->customized_pctype[i].index == index)
10976 return &pf->customized_pctype[i];
10982 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
10983 uint32_t pkg_size, uint32_t proto_num,
10984 struct rte_pmd_i40e_proto_info *proto)
10986 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10987 uint32_t pctype_num;
10988 struct rte_pmd_i40e_ptype_info *pctype;
10989 uint32_t buff_size;
10990 struct i40e_customized_pctype *new_pctype = NULL;
10992 uint8_t pctype_value;
10997 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
10998 (uint8_t *)&pctype_num, sizeof(pctype_num),
10999 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
11001 PMD_DRV_LOG(ERR, "Failed to get pctype number");
11005 PMD_DRV_LOG(INFO, "No new pctype added");
11009 buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
11010 pctype = rte_zmalloc("new_pctype", buff_size, 0);
11012 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11015 /* get information about new pctype list */
11016 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11017 (uint8_t *)pctype, buff_size,
11018 RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
11020 PMD_DRV_LOG(ERR, "Failed to get pctype list");
11025 /* Update customized pctype. */
11026 for (i = 0; i < pctype_num; i++) {
11027 pctype_value = pctype[i].ptype_id;
11028 memset(name, 0, sizeof(name));
11029 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11030 proto_id = pctype[i].protocols[j];
11031 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11033 for (n = 0; n < proto_num; n++) {
11034 if (proto[n].proto_id != proto_id)
11036 strcat(name, proto[n].name);
11041 name[strlen(name) - 1] = '\0';
11042 if (!strcmp(name, "GTPC"))
11044 i40e_find_customized_pctype(pf,
11045 I40E_CUSTOMIZED_GTPC);
11046 else if (!strcmp(name, "GTPU_IPV4"))
11048 i40e_find_customized_pctype(pf,
11049 I40E_CUSTOMIZED_GTPU_IPV4);
11050 else if (!strcmp(name, "GTPU_IPV6"))
11052 i40e_find_customized_pctype(pf,
11053 I40E_CUSTOMIZED_GTPU_IPV6);
11054 else if (!strcmp(name, "GTPU"))
11056 i40e_find_customized_pctype(pf,
11057 I40E_CUSTOMIZED_GTPU);
11059 new_pctype->pctype = pctype_value;
11060 new_pctype->valid = true;
11069 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
11070 uint32_t pkg_size, uint32_t proto_num,
11071 struct rte_pmd_i40e_proto_info *proto)
11073 struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
11074 uint16_t port_id = dev->data->port_id;
11075 uint32_t ptype_num;
11076 struct rte_pmd_i40e_ptype_info *ptype;
11077 uint32_t buff_size;
11079 char name[RTE_PMD_I40E_DDP_NAME_SIZE];
11084 /* get information about new ptype num */
11085 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11086 (uint8_t *)&ptype_num, sizeof(ptype_num),
11087 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
11089 PMD_DRV_LOG(ERR, "Failed to get ptype number");
11093 PMD_DRV_LOG(INFO, "No new ptype added");
11097 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
11098 ptype = rte_zmalloc("new_ptype", buff_size, 0);
11100 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11104 /* get information about new ptype list */
11105 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11106 (uint8_t *)ptype, buff_size,
11107 RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
11109 PMD_DRV_LOG(ERR, "Failed to get ptype list");
11114 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
11115 ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
11116 if (!ptype_mapping) {
11117 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11122 /* Update ptype mapping table. */
11123 for (i = 0; i < ptype_num; i++) {
11124 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
11125 ptype_mapping[i].sw_ptype = 0;
11127 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11128 proto_id = ptype[i].protocols[j];
11129 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11131 for (n = 0; n < proto_num; n++) {
11132 if (proto[n].proto_id != proto_id)
11134 memset(name, 0, sizeof(name));
11135 strcpy(name, proto[n].name);
11136 if (!strncmp(name, "IPV4", 4) && !inner_ip) {
11137 ptype_mapping[i].sw_ptype |=
11138 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11140 } else if (!strncmp(name, "IPV4FRAG", 8) &&
11142 ptype_mapping[i].sw_ptype |=
11143 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11144 ptype_mapping[i].sw_ptype |=
11145 RTE_PTYPE_INNER_L4_FRAG;
11146 } else if (!strncmp(name, "IPV4", 4) &&
11148 ptype_mapping[i].sw_ptype |=
11149 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11150 else if (!strncmp(name, "IPV6", 4) &&
11152 ptype_mapping[i].sw_ptype |=
11153 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11155 } else if (!strncmp(name, "IPV6FRAG", 8) &&
11157 ptype_mapping[i].sw_ptype |=
11158 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11159 ptype_mapping[i].sw_ptype |=
11160 RTE_PTYPE_INNER_L4_FRAG;
11161 } else if (!strncmp(name, "IPV6", 4) &&
11163 ptype_mapping[i].sw_ptype |=
11164 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11165 else if (!strncmp(name, "GTPC", 4))
11166 ptype_mapping[i].sw_ptype |=
11167 RTE_PTYPE_TUNNEL_GTPC;
11168 else if (!strncmp(name, "GTPU", 4))
11169 ptype_mapping[i].sw_ptype |=
11170 RTE_PTYPE_TUNNEL_GTPU;
11171 else if (!strncmp(name, "UDP", 3))
11172 ptype_mapping[i].sw_ptype |=
11173 RTE_PTYPE_INNER_L4_UDP;
11174 else if (!strncmp(name, "TCP", 3))
11175 ptype_mapping[i].sw_ptype |=
11176 RTE_PTYPE_INNER_L4_TCP;
11177 else if (!strncmp(name, "SCTP", 4))
11178 ptype_mapping[i].sw_ptype |=
11179 RTE_PTYPE_INNER_L4_SCTP;
11180 else if (!strncmp(name, "ICMP", 4) ||
11181 !strncmp(name, "ICMPV6", 6))
11182 ptype_mapping[i].sw_ptype |=
11183 RTE_PTYPE_INNER_L4_ICMP;
11190 ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
11193 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
11195 rte_free(ptype_mapping);
11201 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
11204 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11205 uint32_t proto_num;
11206 struct rte_pmd_i40e_proto_info *proto;
11207 uint32_t buff_size;
11211 /* get information about protocol number */
11212 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11213 (uint8_t *)&proto_num, sizeof(proto_num),
11214 RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
11216 PMD_DRV_LOG(ERR, "Failed to get protocol number");
11220 PMD_DRV_LOG(INFO, "No new protocol added");
11224 buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
11225 proto = rte_zmalloc("new_proto", buff_size, 0);
11227 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11231 /* get information about protocol list */
11232 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11233 (uint8_t *)proto, buff_size,
11234 RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
11236 PMD_DRV_LOG(ERR, "Failed to get protocol list");
11241 /* Check if GTP is supported. */
11242 for (i = 0; i < proto_num; i++) {
11243 if (!strncmp(proto[i].name, "GTP", 3)) {
11244 pf->gtp_support = true;
11249 /* Update customized pctype info */
11250 ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
11253 PMD_DRV_LOG(INFO, "No pctype is updated.");
11255 /* Update customized ptype info */
11256 ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
11259 PMD_DRV_LOG(INFO, "No ptype is updated.");
11264 /* Create a QinQ cloud filter
11266 * The Fortville NIC has limited resources for tunnel filters,
11267 * so we can only reuse existing filters.
11269 * In step 1 we define which Field Vector fields can be used for
11271 * As we do not have the inner tag defined as a field,
11272 * we have to define it first, by reusing one of L1 entries.
11274 * In step 2 we are replacing one of existing filter types with
11275 * a new one for QinQ.
11276 * As we reusing L1 and replacing L2, some of the default filter
11277 * types will disappear,which depends on L1 and L2 entries we reuse.
11279 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
11281 * 1. Create L1 filter of outer vlan (12b) which will be in use
11282 * later when we define the cloud filter.
11283 * a. Valid_flags.replace_cloud = 0
11284 * b. Old_filter = 10 (Stag_Inner_Vlan)
11285 * c. New_filter = 0x10
11286 * d. TR bit = 0xff (optional, not used here)
11287 * e. Buffer – 2 entries:
11288 * i. Byte 0 = 8 (outer vlan FV index).
11290 * Byte 2-3 = 0x0fff
11291 * ii. Byte 0 = 37 (inner vlan FV index).
11293 * Byte 2-3 = 0x0fff
11296 * 2. Create cloud filter using two L1 filters entries: stag and
11297 * new filter(outer vlan+ inner vlan)
11298 * a. Valid_flags.replace_cloud = 1
11299 * b. Old_filter = 1 (instead of outer IP)
11300 * c. New_filter = 0x10
11301 * d. Buffer – 2 entries:
11302 * i. Byte 0 = 0x80 | 7 (valid | Stag).
11303 * Byte 1-3 = 0 (rsv)
11304 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
11305 * Byte 9-11 = 0 (rsv)
11308 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
11310 int ret = -ENOTSUP;
11311 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
11312 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
11313 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11316 memset(&filter_replace, 0,
11317 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11318 memset(&filter_replace_buf, 0,
11319 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11321 /* create L1 filter */
11322 filter_replace.old_filter_type =
11323 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
11324 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11325 filter_replace.tr_bit = 0;
11327 /* Prepare the buffer, 2 entries */
11328 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
11329 filter_replace_buf.data[0] |=
11330 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11331 /* Field Vector 12b mask */
11332 filter_replace_buf.data[2] = 0xff;
11333 filter_replace_buf.data[3] = 0x0f;
11334 filter_replace_buf.data[4] =
11335 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
11336 filter_replace_buf.data[4] |=
11337 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11338 /* Field Vector 12b mask */
11339 filter_replace_buf.data[6] = 0xff;
11340 filter_replace_buf.data[7] = 0x0f;
11341 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11342 &filter_replace_buf);
11343 if (ret != I40E_SUCCESS)
11346 /* Apply the second L2 cloud filter */
11347 memset(&filter_replace, 0,
11348 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11349 memset(&filter_replace_buf, 0,
11350 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11352 /* create L2 filter, input for L2 filter will be L1 filter */
11353 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
11354 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
11355 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11357 /* Prepare the buffer, 2 entries */
11358 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
11359 filter_replace_buf.data[0] |=
11360 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11361 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11362 filter_replace_buf.data[4] |=
11363 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11364 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11365 &filter_replace_buf);
11369 RTE_INIT(i40e_init_log);
11371 i40e_init_log(void)
11373 i40e_logtype_init = rte_log_register("pmd.i40e.init");
11374 if (i40e_logtype_init >= 0)
11375 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
11376 i40e_logtype_driver = rte_log_register("pmd.i40e.driver");
11377 if (i40e_logtype_driver >= 0)
11378 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);