4 * Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 #include <rte_string_fns.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_ethdev_pci.h>
49 #include <rte_memzone.h>
50 #include <rte_malloc.h>
51 #include <rte_memcpy.h>
52 #include <rte_alarm.h>
54 #include <rte_eth_ctrl.h>
55 #include <rte_tailq.h>
56 #include <rte_hash_crc.h>
58 #include "i40e_logs.h"
59 #include "base/i40e_prototype.h"
60 #include "base/i40e_adminq_cmd.h"
61 #include "base/i40e_type.h"
62 #include "base/i40e_register.h"
63 #include "base/i40e_dcb.h"
64 #include "i40e_ethdev.h"
65 #include "i40e_rxtx.h"
67 #include "i40e_regs.h"
69 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
70 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
72 #define I40E_CLEAR_PXE_WAIT_MS 200
74 /* Maximun number of capability elements */
75 #define I40E_MAX_CAP_ELE_NUM 128
77 /* Wait count and inteval */
78 #define I40E_CHK_Q_ENA_COUNT 1000
79 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
81 /* Maximun number of VSI */
82 #define I40E_MAX_NUM_VSIS (384UL)
84 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
86 /* Flow control default timer */
87 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
89 /* Flow control default high water */
90 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
92 /* Flow control default low water */
93 #define I40E_DEFAULT_LOW_WATER (0x1A40/1024)
95 /* Flow control enable fwd bit */
96 #define I40E_PRTMAC_FWD_CTRL 0x00000001
98 /* Receive Packet Buffer size */
99 #define I40E_RXPBSIZE (968 * 1024)
101 /* Kilobytes shift */
102 #define I40E_KILOSHIFT 10
104 /* Receive Average Packet Size in Byte*/
105 #define I40E_PACKET_AVERAGE_SIZE 128
107 /* Mask of PF interrupt causes */
108 #define I40E_PFINT_ICR0_ENA_MASK ( \
109 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
110 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
111 I40E_PFINT_ICR0_ENA_GRST_MASK | \
112 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
113 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
114 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
115 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
116 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
117 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
119 #define I40E_FLOW_TYPES ( \
120 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
121 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
122 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
123 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
124 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
125 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
126 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
127 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
128 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
129 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
130 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
132 /* Additional timesync values. */
133 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
134 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
135 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
136 #define I40E_PRTTSYN_TSYNENA 0x80000000
137 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
138 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
140 #define I40E_MAX_PERCENT 100
141 #define I40E_DEFAULT_DCB_APP_NUM 1
142 #define I40E_DEFAULT_DCB_APP_PRIO 3
145 * Below are values for writing un-exposed registers suggested
148 /* Destination MAC address */
149 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
150 /* Source MAC address */
151 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
152 /* Outer (S-Tag) VLAN tag in the outer L2 header */
153 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
154 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
155 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
156 /* Single VLAN tag in the inner L2 header */
157 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
158 /* Source IPv4 address */
159 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
160 /* Destination IPv4 address */
161 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
162 /* Source IPv4 address for X722 */
163 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
164 /* Destination IPv4 address for X722 */
165 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
166 /* IPv4 Protocol for X722 */
167 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
168 /* IPv4 Time to Live for X722 */
169 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
170 /* IPv4 Type of Service (TOS) */
171 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
173 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
174 /* IPv4 Time to Live */
175 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
176 /* Source IPv6 address */
177 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
178 /* Destination IPv6 address */
179 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
180 /* IPv6 Traffic Class (TC) */
181 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
182 /* IPv6 Next Header */
183 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
185 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
187 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
188 /* Destination L4 port */
189 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
190 /* SCTP verification tag */
191 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
192 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
193 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
194 /* Source port of tunneling UDP */
195 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
196 /* Destination port of tunneling UDP */
197 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
198 /* UDP Tunneling ID, NVGRE/GRE key */
199 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
200 /* Last ether type */
201 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
202 /* Tunneling outer destination IPv4 address */
203 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
204 /* Tunneling outer destination IPv6 address */
205 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
206 /* 1st word of flex payload */
207 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
208 /* 2nd word of flex payload */
209 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
210 /* 3rd word of flex payload */
211 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
212 /* 4th word of flex payload */
213 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
214 /* 5th word of flex payload */
215 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
216 /* 6th word of flex payload */
217 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
218 /* 7th word of flex payload */
219 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
220 /* 8th word of flex payload */
221 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
222 /* all 8 words flex payload */
223 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
224 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
226 #define I40E_TRANSLATE_INSET 0
227 #define I40E_TRANSLATE_REG 1
229 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
230 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
231 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
232 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
233 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
234 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
236 /* PCI offset for querying capability */
237 #define PCI_DEV_CAP_REG 0xA4
238 /* PCI offset for enabling/disabling Extended Tag */
239 #define PCI_DEV_CTRL_REG 0xA8
240 /* Bit mask of Extended Tag capability */
241 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
242 /* Bit shift of Extended Tag enable/disable */
243 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
244 /* Bit mask of Extended Tag enable/disable */
245 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
247 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
248 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
249 static int i40e_dev_configure(struct rte_eth_dev *dev);
250 static int i40e_dev_start(struct rte_eth_dev *dev);
251 static void i40e_dev_stop(struct rte_eth_dev *dev);
252 static void i40e_dev_close(struct rte_eth_dev *dev);
253 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
254 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
255 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
256 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
257 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
258 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
259 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
260 struct rte_eth_stats *stats);
261 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
262 struct rte_eth_xstat *xstats, unsigned n);
263 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
264 struct rte_eth_xstat_name *xstats_names,
266 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
267 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
271 static int i40e_fw_version_get(struct rte_eth_dev *dev,
272 char *fw_version, size_t fw_size);
273 static void i40e_dev_info_get(struct rte_eth_dev *dev,
274 struct rte_eth_dev_info *dev_info);
275 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
278 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
279 enum rte_vlan_type vlan_type,
281 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
282 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
285 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
286 static int i40e_dev_led_on(struct rte_eth_dev *dev);
287 static int i40e_dev_led_off(struct rte_eth_dev *dev);
288 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
289 struct rte_eth_fc_conf *fc_conf);
290 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
291 struct rte_eth_fc_conf *fc_conf);
292 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
293 struct rte_eth_pfc_conf *pfc_conf);
294 static void i40e_macaddr_add(struct rte_eth_dev *dev,
295 struct ether_addr *mac_addr,
298 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
299 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
300 struct rte_eth_rss_reta_entry64 *reta_conf,
302 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
303 struct rte_eth_rss_reta_entry64 *reta_conf,
306 static int i40e_get_cap(struct i40e_hw *hw);
307 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
308 static int i40e_pf_setup(struct i40e_pf *pf);
309 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
310 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
311 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
312 static int i40e_dcb_setup(struct rte_eth_dev *dev);
313 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
314 bool offset_loaded, uint64_t *offset, uint64_t *stat);
315 static void i40e_stat_update_48(struct i40e_hw *hw,
321 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
322 static void i40e_dev_interrupt_handler(void *param);
323 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
324 uint32_t base, uint32_t num);
325 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
326 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
328 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
330 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
331 static int i40e_veb_release(struct i40e_veb *veb);
332 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
333 struct i40e_vsi *vsi);
334 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
335 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
336 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
337 struct i40e_macvlan_filter *mv_f,
340 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
341 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
342 struct rte_eth_rss_conf *rss_conf);
343 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
344 struct rte_eth_rss_conf *rss_conf);
345 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
346 struct rte_eth_udp_tunnel *udp_tunnel);
347 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
348 struct rte_eth_udp_tunnel *udp_tunnel);
349 static void i40e_filter_input_set_init(struct i40e_pf *pf);
350 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
351 enum rte_filter_op filter_op,
353 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
354 enum rte_filter_type filter_type,
355 enum rte_filter_op filter_op,
357 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
358 struct rte_eth_dcb_info *dcb_info);
359 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
360 static void i40e_configure_registers(struct i40e_hw *hw);
361 static void i40e_hw_init(struct rte_eth_dev *dev);
362 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
363 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
364 struct rte_eth_mirror_conf *mirror_conf,
365 uint8_t sw_id, uint8_t on);
366 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
368 static int i40e_timesync_enable(struct rte_eth_dev *dev);
369 static int i40e_timesync_disable(struct rte_eth_dev *dev);
370 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
371 struct timespec *timestamp,
373 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
374 struct timespec *timestamp);
375 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
377 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
379 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
380 struct timespec *timestamp);
381 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
382 const struct timespec *timestamp);
384 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
386 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
389 static int i40e_get_regs(struct rte_eth_dev *dev,
390 struct rte_dev_reg_info *regs);
392 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
394 static int i40e_get_eeprom(struct rte_eth_dev *dev,
395 struct rte_dev_eeprom_info *eeprom);
397 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
398 struct ether_addr *mac_addr);
400 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
402 static int i40e_ethertype_filter_convert(
403 const struct rte_eth_ethertype_filter *input,
404 struct i40e_ethertype_filter *filter);
405 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
406 struct i40e_ethertype_filter *filter);
408 static int i40e_tunnel_filter_convert(
409 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
410 struct i40e_tunnel_filter *tunnel_filter);
411 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
412 struct i40e_tunnel_filter *tunnel_filter);
413 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
415 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
416 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
417 static void i40e_filter_restore(struct i40e_pf *pf);
418 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
420 int i40e_logtype_init;
421 int i40e_logtype_driver;
423 static const struct rte_pci_id pci_id_i40e_map[] = {
424 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
425 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
426 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
427 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
428 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
429 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
430 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
431 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
432 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
435 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
436 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
437 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
438 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
439 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
440 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
441 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
442 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
443 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
444 { .vendor_id = 0, /* sentinel */ },
447 static const struct eth_dev_ops i40e_eth_dev_ops = {
448 .dev_configure = i40e_dev_configure,
449 .dev_start = i40e_dev_start,
450 .dev_stop = i40e_dev_stop,
451 .dev_close = i40e_dev_close,
452 .promiscuous_enable = i40e_dev_promiscuous_enable,
453 .promiscuous_disable = i40e_dev_promiscuous_disable,
454 .allmulticast_enable = i40e_dev_allmulticast_enable,
455 .allmulticast_disable = i40e_dev_allmulticast_disable,
456 .dev_set_link_up = i40e_dev_set_link_up,
457 .dev_set_link_down = i40e_dev_set_link_down,
458 .link_update = i40e_dev_link_update,
459 .stats_get = i40e_dev_stats_get,
460 .xstats_get = i40e_dev_xstats_get,
461 .xstats_get_names = i40e_dev_xstats_get_names,
462 .stats_reset = i40e_dev_stats_reset,
463 .xstats_reset = i40e_dev_stats_reset,
464 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
465 .fw_version_get = i40e_fw_version_get,
466 .dev_infos_get = i40e_dev_info_get,
467 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
468 .vlan_filter_set = i40e_vlan_filter_set,
469 .vlan_tpid_set = i40e_vlan_tpid_set,
470 .vlan_offload_set = i40e_vlan_offload_set,
471 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
472 .vlan_pvid_set = i40e_vlan_pvid_set,
473 .rx_queue_start = i40e_dev_rx_queue_start,
474 .rx_queue_stop = i40e_dev_rx_queue_stop,
475 .tx_queue_start = i40e_dev_tx_queue_start,
476 .tx_queue_stop = i40e_dev_tx_queue_stop,
477 .rx_queue_setup = i40e_dev_rx_queue_setup,
478 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
479 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
480 .rx_queue_release = i40e_dev_rx_queue_release,
481 .rx_queue_count = i40e_dev_rx_queue_count,
482 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
483 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
484 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
485 .tx_queue_setup = i40e_dev_tx_queue_setup,
486 .tx_queue_release = i40e_dev_tx_queue_release,
487 .dev_led_on = i40e_dev_led_on,
488 .dev_led_off = i40e_dev_led_off,
489 .flow_ctrl_get = i40e_flow_ctrl_get,
490 .flow_ctrl_set = i40e_flow_ctrl_set,
491 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
492 .mac_addr_add = i40e_macaddr_add,
493 .mac_addr_remove = i40e_macaddr_remove,
494 .reta_update = i40e_dev_rss_reta_update,
495 .reta_query = i40e_dev_rss_reta_query,
496 .rss_hash_update = i40e_dev_rss_hash_update,
497 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
498 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
499 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
500 .filter_ctrl = i40e_dev_filter_ctrl,
501 .rxq_info_get = i40e_rxq_info_get,
502 .txq_info_get = i40e_txq_info_get,
503 .mirror_rule_set = i40e_mirror_rule_set,
504 .mirror_rule_reset = i40e_mirror_rule_reset,
505 .timesync_enable = i40e_timesync_enable,
506 .timesync_disable = i40e_timesync_disable,
507 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
508 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
509 .get_dcb_info = i40e_dev_get_dcb_info,
510 .timesync_adjust_time = i40e_timesync_adjust_time,
511 .timesync_read_time = i40e_timesync_read_time,
512 .timesync_write_time = i40e_timesync_write_time,
513 .get_reg = i40e_get_regs,
514 .get_eeprom_length = i40e_get_eeprom_length,
515 .get_eeprom = i40e_get_eeprom,
516 .mac_addr_set = i40e_set_default_mac_addr,
517 .mtu_set = i40e_dev_mtu_set,
520 /* store statistics names and its offset in stats structure */
521 struct rte_i40e_xstats_name_off {
522 char name[RTE_ETH_XSTATS_NAME_SIZE];
526 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
527 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
528 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
529 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
530 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
531 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
532 rx_unknown_protocol)},
533 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
534 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
535 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
536 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
539 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
540 sizeof(rte_i40e_stats_strings[0]))
542 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
543 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
544 tx_dropped_link_down)},
545 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
546 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
548 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
549 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
551 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
553 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
555 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
556 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
557 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
558 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
559 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
560 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
562 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
564 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
566 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
568 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
570 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
572 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
574 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
576 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
577 mac_short_packet_dropped)},
578 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
580 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
581 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
582 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
584 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
586 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
588 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
590 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
592 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
594 {"rx_flow_director_atr_match_packets",
595 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
596 {"rx_flow_director_sb_match_packets",
597 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
598 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
600 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
602 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
604 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
608 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
609 sizeof(rte_i40e_hw_port_strings[0]))
611 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
612 {"xon_packets", offsetof(struct i40e_hw_port_stats,
614 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
618 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
619 sizeof(rte_i40e_rxq_prio_strings[0]))
621 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
622 {"xon_packets", offsetof(struct i40e_hw_port_stats,
624 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
626 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
627 priority_xon_2_xoff)},
630 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
631 sizeof(rte_i40e_txq_prio_strings[0]))
633 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
634 struct rte_pci_device *pci_dev)
636 return rte_eth_dev_pci_generic_probe(pci_dev,
637 sizeof(struct i40e_adapter), eth_i40e_dev_init);
640 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
642 return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
645 static struct rte_pci_driver rte_i40e_pmd = {
646 .id_table = pci_id_i40e_map,
647 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
648 .probe = eth_i40e_pci_probe,
649 .remove = eth_i40e_pci_remove,
653 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
654 struct rte_eth_link *link)
656 struct rte_eth_link *dst = link;
657 struct rte_eth_link *src = &(dev->data->dev_link);
659 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
660 *(uint64_t *)src) == 0)
667 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
668 struct rte_eth_link *link)
670 struct rte_eth_link *dst = &(dev->data->dev_link);
671 struct rte_eth_link *src = link;
673 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
674 *(uint64_t *)src) == 0)
680 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
681 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
682 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio");
684 #ifndef I40E_GLQF_ORT
685 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
687 #ifndef I40E_GLQF_PIT
688 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
690 #ifndef I40E_GLQF_L3_MAP
691 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
694 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
697 * Initialize registers for flexible payload, which should be set by NVM.
698 * This should be removed from code once it is fixed in NVM.
700 I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
701 I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
702 I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
703 I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
704 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
705 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
706 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
707 I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
708 I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
709 I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
710 I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
711 I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
713 /* Initialize registers for parsing packet type of QinQ */
714 I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
715 I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
718 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
721 * Add a ethertype filter to drop all flow control frames transmitted
725 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
727 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
728 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
729 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
730 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
733 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
734 I40E_FLOW_CONTROL_ETHERTYPE, flags,
735 pf->main_vsi_seid, 0,
739 "Failed to add filter to drop flow control frames from VSIs.");
743 floating_veb_list_handler(__rte_unused const char *key,
744 const char *floating_veb_value,
748 unsigned int count = 0;
751 bool *vf_floating_veb = opaque;
753 while (isblank(*floating_veb_value))
754 floating_veb_value++;
756 /* Reset floating VEB configuration for VFs */
757 for (idx = 0; idx < I40E_MAX_VF; idx++)
758 vf_floating_veb[idx] = false;
762 while (isblank(*floating_veb_value))
763 floating_veb_value++;
764 if (*floating_veb_value == '\0')
767 idx = strtoul(floating_veb_value, &end, 10);
768 if (errno || end == NULL)
770 while (isblank(*end))
774 } else if ((*end == ';') || (*end == '\0')) {
776 if (min == I40E_MAX_VF)
778 if (max >= I40E_MAX_VF)
779 max = I40E_MAX_VF - 1;
780 for (idx = min; idx <= max; idx++) {
781 vf_floating_veb[idx] = true;
788 floating_veb_value = end + 1;
789 } while (*end != '\0');
798 config_vf_floating_veb(struct rte_devargs *devargs,
799 uint16_t floating_veb,
800 bool *vf_floating_veb)
802 struct rte_kvargs *kvlist;
804 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
808 /* All the VFs attach to the floating VEB by default
809 * when the floating VEB is enabled.
811 for (i = 0; i < I40E_MAX_VF; i++)
812 vf_floating_veb[i] = true;
817 kvlist = rte_kvargs_parse(devargs->args, NULL);
821 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
822 rte_kvargs_free(kvlist);
825 /* When the floating_veb_list parameter exists, all the VFs
826 * will attach to the legacy VEB firstly, then configure VFs
827 * to the floating VEB according to the floating_veb_list.
829 if (rte_kvargs_process(kvlist, floating_veb_list,
830 floating_veb_list_handler,
831 vf_floating_veb) < 0) {
832 rte_kvargs_free(kvlist);
835 rte_kvargs_free(kvlist);
839 i40e_check_floating_handler(__rte_unused const char *key,
841 __rte_unused void *opaque)
843 if (strcmp(value, "1"))
850 is_floating_veb_supported(struct rte_devargs *devargs)
852 struct rte_kvargs *kvlist;
853 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
858 kvlist = rte_kvargs_parse(devargs->args, NULL);
862 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
863 rte_kvargs_free(kvlist);
866 /* Floating VEB is enabled when there's key-value:
867 * enable_floating_veb=1
869 if (rte_kvargs_process(kvlist, floating_veb_key,
870 i40e_check_floating_handler, NULL) < 0) {
871 rte_kvargs_free(kvlist);
874 rte_kvargs_free(kvlist);
880 config_floating_veb(struct rte_eth_dev *dev)
882 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
883 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
884 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
886 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
888 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
890 is_floating_veb_supported(pci_dev->device.devargs);
891 config_vf_floating_veb(pci_dev->device.devargs,
893 pf->floating_veb_list);
895 pf->floating_veb = false;
899 #define I40E_L2_TAGS_S_TAG_SHIFT 1
900 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
903 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
905 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
906 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
907 char ethertype_hash_name[RTE_HASH_NAMESIZE];
910 struct rte_hash_parameters ethertype_hash_params = {
911 .name = ethertype_hash_name,
912 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
913 .key_len = sizeof(struct i40e_ethertype_filter_input),
914 .hash_func = rte_hash_crc,
915 .hash_func_init_val = 0,
916 .socket_id = rte_socket_id(),
919 /* Initialize ethertype filter rule list and hash */
920 TAILQ_INIT(ðertype_rule->ethertype_list);
921 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
922 "ethertype_%s", dev->data->name);
923 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
924 if (!ethertype_rule->hash_table) {
925 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
928 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
929 sizeof(struct i40e_ethertype_filter *) *
930 I40E_MAX_ETHERTYPE_FILTER_NUM,
932 if (!ethertype_rule->hash_map) {
934 "Failed to allocate memory for ethertype hash map!");
936 goto err_ethertype_hash_map_alloc;
941 err_ethertype_hash_map_alloc:
942 rte_hash_free(ethertype_rule->hash_table);
948 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
950 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
951 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
952 char tunnel_hash_name[RTE_HASH_NAMESIZE];
955 struct rte_hash_parameters tunnel_hash_params = {
956 .name = tunnel_hash_name,
957 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
958 .key_len = sizeof(struct i40e_tunnel_filter_input),
959 .hash_func = rte_hash_crc,
960 .hash_func_init_val = 0,
961 .socket_id = rte_socket_id(),
964 /* Initialize tunnel filter rule list and hash */
965 TAILQ_INIT(&tunnel_rule->tunnel_list);
966 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
967 "tunnel_%s", dev->data->name);
968 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
969 if (!tunnel_rule->hash_table) {
970 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
973 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
974 sizeof(struct i40e_tunnel_filter *) *
975 I40E_MAX_TUNNEL_FILTER_NUM,
977 if (!tunnel_rule->hash_map) {
979 "Failed to allocate memory for tunnel hash map!");
981 goto err_tunnel_hash_map_alloc;
986 err_tunnel_hash_map_alloc:
987 rte_hash_free(tunnel_rule->hash_table);
993 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
995 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
996 struct i40e_fdir_info *fdir_info = &pf->fdir;
997 char fdir_hash_name[RTE_HASH_NAMESIZE];
1000 struct rte_hash_parameters fdir_hash_params = {
1001 .name = fdir_hash_name,
1002 .entries = I40E_MAX_FDIR_FILTER_NUM,
1003 .key_len = sizeof(struct rte_eth_fdir_input),
1004 .hash_func = rte_hash_crc,
1005 .hash_func_init_val = 0,
1006 .socket_id = rte_socket_id(),
1009 /* Initialize flow director filter rule list and hash */
1010 TAILQ_INIT(&fdir_info->fdir_list);
1011 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1012 "fdir_%s", dev->data->name);
1013 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1014 if (!fdir_info->hash_table) {
1015 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1018 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1019 sizeof(struct i40e_fdir_filter *) *
1020 I40E_MAX_FDIR_FILTER_NUM,
1022 if (!fdir_info->hash_map) {
1024 "Failed to allocate memory for fdir hash map!");
1026 goto err_fdir_hash_map_alloc;
1030 err_fdir_hash_map_alloc:
1031 rte_hash_free(fdir_info->hash_table);
1037 eth_i40e_dev_init(struct rte_eth_dev *dev)
1039 struct rte_pci_device *pci_dev;
1040 struct rte_intr_handle *intr_handle;
1041 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1042 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1043 struct i40e_vsi *vsi;
1046 uint8_t aq_fail = 0;
1048 PMD_INIT_FUNC_TRACE();
1050 dev->dev_ops = &i40e_eth_dev_ops;
1051 dev->rx_pkt_burst = i40e_recv_pkts;
1052 dev->tx_pkt_burst = i40e_xmit_pkts;
1053 dev->tx_pkt_prepare = i40e_prep_pkts;
1055 /* for secondary processes, we don't initialise any further as primary
1056 * has already done this work. Only check we don't need a different
1058 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1059 i40e_set_rx_function(dev);
1060 i40e_set_tx_function(dev);
1063 i40e_set_default_ptype_table(dev);
1064 pci_dev = I40E_DEV_TO_PCI(dev);
1065 intr_handle = &pci_dev->intr_handle;
1067 rte_eth_copy_pci_info(dev, pci_dev);
1068 dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1070 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1071 pf->adapter->eth_dev = dev;
1072 pf->dev_data = dev->data;
1074 hw->back = I40E_PF_TO_ADAPTER(pf);
1075 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1078 "Hardware is not available, as address is NULL");
1082 hw->vendor_id = pci_dev->id.vendor_id;
1083 hw->device_id = pci_dev->id.device_id;
1084 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1085 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1086 hw->bus.device = pci_dev->addr.devid;
1087 hw->bus.func = pci_dev->addr.function;
1088 hw->adapter_stopped = 0;
1090 /* Make sure all is clean before doing PF reset */
1093 /* Initialize the hardware */
1096 /* Reset here to make sure all is clean for each PF */
1097 ret = i40e_pf_reset(hw);
1099 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1103 /* Initialize the shared code (base driver) */
1104 ret = i40e_init_shared_code(hw);
1106 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1111 * To work around the NVM issue, initialize registers
1112 * for flexible payload and packet type of QinQ by
1113 * software. It should be removed once issues are fixed
1116 i40e_GLQF_reg_init(hw);
1118 /* Initialize the input set for filters (hash and fd) to default value */
1119 i40e_filter_input_set_init(pf);
1121 /* Initialize the parameters for adminq */
1122 i40e_init_adminq_parameter(hw);
1123 ret = i40e_init_adminq(hw);
1124 if (ret != I40E_SUCCESS) {
1125 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1128 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1129 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1130 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1131 ((hw->nvm.version >> 12) & 0xf),
1132 ((hw->nvm.version >> 4) & 0xff),
1133 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1135 /* initialise the L3_MAP register */
1136 ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1139 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
1141 /* Need the special FW version to support floating VEB */
1142 config_floating_veb(dev);
1143 /* Clear PXE mode */
1144 i40e_clear_pxe_mode(hw);
1145 ret = i40e_dev_sync_phy_type(hw);
1147 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1148 goto err_sync_phy_type;
1151 * On X710, performance number is far from the expectation on recent
1152 * firmware versions. The fix for this issue may not be integrated in
1153 * the following firmware version. So the workaround in software driver
1154 * is needed. It needs to modify the initial values of 3 internal only
1155 * registers. Note that the workaround can be removed when it is fixed
1156 * in firmware in the future.
1158 i40e_configure_registers(hw);
1160 /* Get hw capabilities */
1161 ret = i40e_get_cap(hw);
1162 if (ret != I40E_SUCCESS) {
1163 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1164 goto err_get_capabilities;
1167 /* Initialize parameters for PF */
1168 ret = i40e_pf_parameter_init(dev);
1170 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1171 goto err_parameter_init;
1174 /* Initialize the queue management */
1175 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1177 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1178 goto err_qp_pool_init;
1180 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1181 hw->func_caps.num_msix_vectors - 1);
1183 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1184 goto err_msix_pool_init;
1187 /* Initialize lan hmc */
1188 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1189 hw->func_caps.num_rx_qp, 0, 0);
1190 if (ret != I40E_SUCCESS) {
1191 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1192 goto err_init_lan_hmc;
1195 /* Configure lan hmc */
1196 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1197 if (ret != I40E_SUCCESS) {
1198 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1199 goto err_configure_lan_hmc;
1202 /* Get and check the mac address */
1203 i40e_get_mac_addr(hw, hw->mac.addr);
1204 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1205 PMD_INIT_LOG(ERR, "mac address is not valid");
1207 goto err_get_mac_addr;
1209 /* Copy the permanent MAC address */
1210 ether_addr_copy((struct ether_addr *) hw->mac.addr,
1211 (struct ether_addr *) hw->mac.perm_addr);
1213 /* Disable flow control */
1214 hw->fc.requested_mode = I40E_FC_NONE;
1215 i40e_set_fc(hw, &aq_fail, TRUE);
1217 /* Set the global registers with default ether type value */
1218 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1219 if (ret != I40E_SUCCESS) {
1221 "Failed to set the default outer VLAN ether type");
1222 goto err_setup_pf_switch;
1225 /* PF setup, which includes VSI setup */
1226 ret = i40e_pf_setup(pf);
1228 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1229 goto err_setup_pf_switch;
1232 /* reset all stats of the device, including pf and main vsi */
1233 i40e_dev_stats_reset(dev);
1237 /* Disable double vlan by default */
1238 i40e_vsi_config_double_vlan(vsi, FALSE);
1240 /* Disable S-TAG identification when floating_veb is disabled */
1241 if (!pf->floating_veb) {
1242 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1243 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1244 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1245 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1249 if (!vsi->max_macaddrs)
1250 len = ETHER_ADDR_LEN;
1252 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1254 /* Should be after VSI initialized */
1255 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1256 if (!dev->data->mac_addrs) {
1258 "Failed to allocated memory for storing mac address");
1261 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1262 &dev->data->mac_addrs[0]);
1264 /* Init dcb to sw mode by default */
1265 ret = i40e_dcb_init_configure(dev, TRUE);
1266 if (ret != I40E_SUCCESS) {
1267 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1268 pf->flags &= ~I40E_FLAG_DCB;
1270 /* Update HW struct after DCB configuration */
1273 /* initialize pf host driver to setup SRIOV resource if applicable */
1274 i40e_pf_host_init(dev);
1276 /* register callback func to eal lib */
1277 rte_intr_callback_register(intr_handle,
1278 i40e_dev_interrupt_handler, dev);
1280 /* configure and enable device interrupt */
1281 i40e_pf_config_irq0(hw, TRUE);
1282 i40e_pf_enable_irq0(hw);
1284 /* enable uio intr after callback register */
1285 rte_intr_enable(intr_handle);
1287 * Add an ethertype filter to drop all flow control frames transmitted
1288 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1291 i40e_add_tx_flow_control_drop_filter(pf);
1293 /* Set the max frame size to 0x2600 by default,
1294 * in case other drivers changed the default value.
1296 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1298 /* initialize mirror rule list */
1299 TAILQ_INIT(&pf->mirror_list);
1301 ret = i40e_init_ethtype_filter_list(dev);
1303 goto err_init_ethtype_filter_list;
1304 ret = i40e_init_tunnel_filter_list(dev);
1306 goto err_init_tunnel_filter_list;
1307 ret = i40e_init_fdir_filter_list(dev);
1309 goto err_init_fdir_filter_list;
1313 err_init_fdir_filter_list:
1314 rte_free(pf->tunnel.hash_table);
1315 rte_free(pf->tunnel.hash_map);
1316 err_init_tunnel_filter_list:
1317 rte_free(pf->ethertype.hash_table);
1318 rte_free(pf->ethertype.hash_map);
1319 err_init_ethtype_filter_list:
1320 rte_free(dev->data->mac_addrs);
1322 i40e_vsi_release(pf->main_vsi);
1323 err_setup_pf_switch:
1325 err_configure_lan_hmc:
1326 (void)i40e_shutdown_lan_hmc(hw);
1328 i40e_res_pool_destroy(&pf->msix_pool);
1330 i40e_res_pool_destroy(&pf->qp_pool);
1333 err_get_capabilities:
1335 (void)i40e_shutdown_adminq(hw);
1341 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1343 struct i40e_ethertype_filter *p_ethertype;
1344 struct i40e_ethertype_rule *ethertype_rule;
1346 ethertype_rule = &pf->ethertype;
1347 /* Remove all ethertype filter rules and hash */
1348 if (ethertype_rule->hash_map)
1349 rte_free(ethertype_rule->hash_map);
1350 if (ethertype_rule->hash_table)
1351 rte_hash_free(ethertype_rule->hash_table);
1353 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1354 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1355 p_ethertype, rules);
1356 rte_free(p_ethertype);
1361 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1363 struct i40e_tunnel_filter *p_tunnel;
1364 struct i40e_tunnel_rule *tunnel_rule;
1366 tunnel_rule = &pf->tunnel;
1367 /* Remove all tunnel director rules and hash */
1368 if (tunnel_rule->hash_map)
1369 rte_free(tunnel_rule->hash_map);
1370 if (tunnel_rule->hash_table)
1371 rte_hash_free(tunnel_rule->hash_table);
1373 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1374 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1380 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1382 struct i40e_fdir_filter *p_fdir;
1383 struct i40e_fdir_info *fdir_info;
1385 fdir_info = &pf->fdir;
1386 /* Remove all flow director rules and hash */
1387 if (fdir_info->hash_map)
1388 rte_free(fdir_info->hash_map);
1389 if (fdir_info->hash_table)
1390 rte_hash_free(fdir_info->hash_table);
1392 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1393 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1399 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1402 struct rte_pci_device *pci_dev;
1403 struct rte_intr_handle *intr_handle;
1405 struct i40e_filter_control_settings settings;
1406 struct rte_flow *p_flow;
1408 uint8_t aq_fail = 0;
1410 PMD_INIT_FUNC_TRACE();
1412 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1415 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1416 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1417 pci_dev = I40E_DEV_TO_PCI(dev);
1418 intr_handle = &pci_dev->intr_handle;
1420 if (hw->adapter_stopped == 0)
1421 i40e_dev_close(dev);
1423 dev->dev_ops = NULL;
1424 dev->rx_pkt_burst = NULL;
1425 dev->tx_pkt_burst = NULL;
1427 /* Clear PXE mode */
1428 i40e_clear_pxe_mode(hw);
1430 /* Unconfigure filter control */
1431 memset(&settings, 0, sizeof(settings));
1432 ret = i40e_set_filter_control(hw, &settings);
1434 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1437 /* Disable flow control */
1438 hw->fc.requested_mode = I40E_FC_NONE;
1439 i40e_set_fc(hw, &aq_fail, TRUE);
1441 /* uninitialize pf host driver */
1442 i40e_pf_host_uninit(dev);
1444 rte_free(dev->data->mac_addrs);
1445 dev->data->mac_addrs = NULL;
1447 /* disable uio intr before callback unregister */
1448 rte_intr_disable(intr_handle);
1450 /* register callback func to eal lib */
1451 rte_intr_callback_unregister(intr_handle,
1452 i40e_dev_interrupt_handler, dev);
1454 i40e_rm_ethtype_filter_list(pf);
1455 i40e_rm_tunnel_filter_list(pf);
1456 i40e_rm_fdir_filter_list(pf);
1458 /* Remove all flows */
1459 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1460 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1468 i40e_dev_configure(struct rte_eth_dev *dev)
1470 struct i40e_adapter *ad =
1471 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1472 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1473 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1476 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1477 * bulk allocation or vector Rx preconditions we will reset it.
1479 ad->rx_bulk_alloc_allowed = true;
1480 ad->rx_vec_allowed = true;
1481 ad->tx_simple_allowed = true;
1482 ad->tx_vec_allowed = true;
1484 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1485 ret = i40e_fdir_setup(pf);
1486 if (ret != I40E_SUCCESS) {
1487 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1490 ret = i40e_fdir_configure(dev);
1492 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1496 i40e_fdir_teardown(pf);
1498 ret = i40e_dev_init_vlan(dev);
1503 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1504 * RSS setting have different requirements.
1505 * General PMD driver call sequence are NIC init, configure,
1506 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1507 * will try to lookup the VSI that specific queue belongs to if VMDQ
1508 * applicable. So, VMDQ setting has to be done before
1509 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1510 * For RSS setting, it will try to calculate actual configured RX queue
1511 * number, which will be available after rx_queue_setup(). dev_start()
1512 * function is good to place RSS setup.
1514 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1515 ret = i40e_vmdq_setup(dev);
1520 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1521 ret = i40e_dcb_setup(dev);
1523 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1528 TAILQ_INIT(&pf->flow_list);
1533 /* need to release vmdq resource if exists */
1534 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1535 i40e_vsi_release(pf->vmdq[i].vsi);
1536 pf->vmdq[i].vsi = NULL;
1541 /* need to release fdir resource if exists */
1542 i40e_fdir_teardown(pf);
1547 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1549 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1550 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1551 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1552 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1553 uint16_t msix_vect = vsi->msix_intr;
1556 for (i = 0; i < vsi->nb_qps; i++) {
1557 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1558 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1562 if (vsi->type != I40E_VSI_SRIOV) {
1563 if (!rte_intr_allow_others(intr_handle)) {
1564 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1565 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1567 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1570 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1571 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1573 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1578 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1579 vsi->user_param + (msix_vect - 1);
1581 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1582 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1584 I40E_WRITE_FLUSH(hw);
1588 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1589 int base_queue, int nb_queue)
1593 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1595 /* Bind all RX queues to allocated MSIX interrupt */
1596 for (i = 0; i < nb_queue; i++) {
1597 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1598 I40E_QINT_RQCTL_ITR_INDX_MASK |
1599 ((base_queue + i + 1) <<
1600 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1601 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1602 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1604 if (i == nb_queue - 1)
1605 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1606 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1609 /* Write first RX queue to Link list register as the head element */
1610 if (vsi->type != I40E_VSI_SRIOV) {
1612 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1614 if (msix_vect == I40E_MISC_VEC_ID) {
1615 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1617 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1619 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1621 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1624 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1626 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1628 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1630 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1637 if (msix_vect == I40E_MISC_VEC_ID) {
1639 I40E_VPINT_LNKLST0(vsi->user_param),
1641 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1643 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1645 /* num_msix_vectors_vf needs to minus irq0 */
1646 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1647 vsi->user_param + (msix_vect - 1);
1649 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1651 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1653 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1657 I40E_WRITE_FLUSH(hw);
1661 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1663 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1664 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1665 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1666 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1667 uint16_t msix_vect = vsi->msix_intr;
1668 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1669 uint16_t queue_idx = 0;
1674 for (i = 0; i < vsi->nb_qps; i++) {
1675 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1676 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1679 /* INTENA flag is not auto-cleared for interrupt */
1680 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1681 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1682 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1683 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1684 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1686 /* VF bind interrupt */
1687 if (vsi->type == I40E_VSI_SRIOV) {
1688 __vsi_queues_bind_intr(vsi, msix_vect,
1689 vsi->base_queue, vsi->nb_qps);
1693 /* PF & VMDq bind interrupt */
1694 if (rte_intr_dp_is_en(intr_handle)) {
1695 if (vsi->type == I40E_VSI_MAIN) {
1698 } else if (vsi->type == I40E_VSI_VMDQ2) {
1699 struct i40e_vsi *main_vsi =
1700 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1701 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1706 for (i = 0; i < vsi->nb_used_qps; i++) {
1708 if (!rte_intr_allow_others(intr_handle))
1709 /* allow to share MISC_VEC_ID */
1710 msix_vect = I40E_MISC_VEC_ID;
1712 /* no enough msix_vect, map all to one */
1713 __vsi_queues_bind_intr(vsi, msix_vect,
1714 vsi->base_queue + i,
1715 vsi->nb_used_qps - i);
1716 for (; !!record && i < vsi->nb_used_qps; i++)
1717 intr_handle->intr_vec[queue_idx + i] =
1721 /* 1:1 queue/msix_vect mapping */
1722 __vsi_queues_bind_intr(vsi, msix_vect,
1723 vsi->base_queue + i, 1);
1725 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1733 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1735 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1736 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1737 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1738 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1739 uint16_t interval = i40e_calc_itr_interval(\
1740 RTE_LIBRTE_I40E_ITR_INTERVAL);
1741 uint16_t msix_intr, i;
1743 if (rte_intr_allow_others(intr_handle))
1744 for (i = 0; i < vsi->nb_msix; i++) {
1745 msix_intr = vsi->msix_intr + i;
1746 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1747 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1748 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1749 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1751 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1754 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1755 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1756 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1757 (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1759 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1761 I40E_WRITE_FLUSH(hw);
1765 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1767 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1768 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1769 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1770 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1771 uint16_t msix_intr, i;
1773 if (rte_intr_allow_others(intr_handle))
1774 for (i = 0; i < vsi->nb_msix; i++) {
1775 msix_intr = vsi->msix_intr + i;
1776 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1780 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1782 I40E_WRITE_FLUSH(hw);
1785 static inline uint8_t
1786 i40e_parse_link_speeds(uint16_t link_speeds)
1788 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1790 if (link_speeds & ETH_LINK_SPEED_40G)
1791 link_speed |= I40E_LINK_SPEED_40GB;
1792 if (link_speeds & ETH_LINK_SPEED_25G)
1793 link_speed |= I40E_LINK_SPEED_25GB;
1794 if (link_speeds & ETH_LINK_SPEED_20G)
1795 link_speed |= I40E_LINK_SPEED_20GB;
1796 if (link_speeds & ETH_LINK_SPEED_10G)
1797 link_speed |= I40E_LINK_SPEED_10GB;
1798 if (link_speeds & ETH_LINK_SPEED_1G)
1799 link_speed |= I40E_LINK_SPEED_1GB;
1800 if (link_speeds & ETH_LINK_SPEED_100M)
1801 link_speed |= I40E_LINK_SPEED_100MB;
1807 i40e_phy_conf_link(struct i40e_hw *hw,
1809 uint8_t force_speed)
1811 enum i40e_status_code status;
1812 struct i40e_aq_get_phy_abilities_resp phy_ab;
1813 struct i40e_aq_set_phy_config phy_conf;
1814 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1815 I40E_AQ_PHY_FLAG_PAUSE_RX |
1816 I40E_AQ_PHY_FLAG_PAUSE_RX |
1817 I40E_AQ_PHY_FLAG_LOW_POWER;
1818 const uint8_t advt = I40E_LINK_SPEED_40GB |
1819 I40E_LINK_SPEED_25GB |
1820 I40E_LINK_SPEED_10GB |
1821 I40E_LINK_SPEED_1GB |
1822 I40E_LINK_SPEED_100MB;
1826 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1831 memset(&phy_conf, 0, sizeof(phy_conf));
1833 /* bits 0-2 use the values from get_phy_abilities_resp */
1835 abilities |= phy_ab.abilities & mask;
1837 /* update ablities and speed */
1838 if (abilities & I40E_AQ_PHY_AN_ENABLED)
1839 phy_conf.link_speed = advt;
1841 phy_conf.link_speed = force_speed;
1843 phy_conf.abilities = abilities;
1845 /* use get_phy_abilities_resp value for the rest */
1846 phy_conf.phy_type = phy_ab.phy_type;
1847 phy_conf.phy_type_ext = phy_ab.phy_type_ext;
1848 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1849 phy_conf.eee_capability = phy_ab.eee_capability;
1850 phy_conf.eeer = phy_ab.eeer_val;
1851 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1853 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1854 phy_ab.abilities, phy_ab.link_speed);
1855 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
1856 phy_conf.abilities, phy_conf.link_speed);
1858 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1862 return I40E_SUCCESS;
1866 i40e_apply_link_speed(struct rte_eth_dev *dev)
1869 uint8_t abilities = 0;
1870 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1871 struct rte_eth_conf *conf = &dev->data->dev_conf;
1873 speed = i40e_parse_link_speeds(conf->link_speeds);
1874 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1875 if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1876 abilities |= I40E_AQ_PHY_AN_ENABLED;
1877 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1879 /* Skip changing speed on 40G interfaces, FW does not support */
1880 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1881 speed = I40E_LINK_SPEED_UNKNOWN;
1882 abilities |= I40E_AQ_PHY_AN_ENABLED;
1885 return i40e_phy_conf_link(hw, abilities, speed);
1889 i40e_dev_start(struct rte_eth_dev *dev)
1891 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1892 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1893 struct i40e_vsi *main_vsi = pf->main_vsi;
1895 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1896 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1897 uint32_t intr_vector = 0;
1898 struct i40e_vsi *vsi;
1900 hw->adapter_stopped = 0;
1902 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1903 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1904 dev->data->port_id);
1908 rte_intr_disable(intr_handle);
1910 if ((rte_intr_cap_multiple(intr_handle) ||
1911 !RTE_ETH_DEV_SRIOV(dev).active) &&
1912 dev->data->dev_conf.intr_conf.rxq != 0) {
1913 intr_vector = dev->data->nb_rx_queues;
1914 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1919 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1920 intr_handle->intr_vec =
1921 rte_zmalloc("intr_vec",
1922 dev->data->nb_rx_queues * sizeof(int),
1924 if (!intr_handle->intr_vec) {
1926 "Failed to allocate %d rx_queues intr_vec",
1927 dev->data->nb_rx_queues);
1932 /* Initialize VSI */
1933 ret = i40e_dev_rxtx_init(pf);
1934 if (ret != I40E_SUCCESS) {
1935 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1939 /* Map queues with MSIX interrupt */
1940 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1941 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1942 i40e_vsi_queues_bind_intr(main_vsi);
1943 i40e_vsi_enable_queues_intr(main_vsi);
1945 /* Map VMDQ VSI queues with MSIX interrupt */
1946 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1947 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1948 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1949 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1952 /* enable FDIR MSIX interrupt */
1953 if (pf->fdir.fdir_vsi) {
1954 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1955 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1958 /* Enable all queues which have been configured */
1959 ret = i40e_dev_switch_queues(pf, TRUE);
1960 if (ret != I40E_SUCCESS) {
1961 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1965 /* Enable receiving broadcast packets */
1966 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1967 if (ret != I40E_SUCCESS)
1968 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1970 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1971 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1973 if (ret != I40E_SUCCESS)
1974 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1977 /* Enable the VLAN promiscuous mode. */
1979 for (i = 0; i < pf->vf_num; i++) {
1980 vsi = pf->vfs[i].vsi;
1981 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
1986 /* Apply link configure */
1987 if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1988 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1989 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1990 ETH_LINK_SPEED_40G)) {
1991 PMD_DRV_LOG(ERR, "Invalid link setting");
1994 ret = i40e_apply_link_speed(dev);
1995 if (I40E_SUCCESS != ret) {
1996 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2000 if (!rte_intr_allow_others(intr_handle)) {
2001 rte_intr_callback_unregister(intr_handle,
2002 i40e_dev_interrupt_handler,
2004 /* configure and enable device interrupt */
2005 i40e_pf_config_irq0(hw, FALSE);
2006 i40e_pf_enable_irq0(hw);
2008 if (dev->data->dev_conf.intr_conf.lsc != 0)
2010 "lsc won't enable because of no intr multiplex");
2011 } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
2012 ret = i40e_aq_set_phy_int_mask(hw,
2013 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2014 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2015 I40E_AQ_EVENT_MEDIA_NA), NULL);
2016 if (ret != I40E_SUCCESS)
2017 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2019 /* Call get_link_info aq commond to enable LSE */
2020 i40e_dev_link_update(dev, 0);
2023 /* enable uio intr after callback register */
2024 rte_intr_enable(intr_handle);
2026 i40e_filter_restore(pf);
2028 return I40E_SUCCESS;
2031 i40e_dev_switch_queues(pf, FALSE);
2032 i40e_dev_clear_queues(dev);
2038 i40e_dev_stop(struct rte_eth_dev *dev)
2040 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2041 struct i40e_vsi *main_vsi = pf->main_vsi;
2042 struct i40e_mirror_rule *p_mirror;
2043 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2044 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2047 /* Disable all queues */
2048 i40e_dev_switch_queues(pf, FALSE);
2050 /* un-map queues with interrupt registers */
2051 i40e_vsi_disable_queues_intr(main_vsi);
2052 i40e_vsi_queues_unbind_intr(main_vsi);
2054 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2055 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2056 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2059 if (pf->fdir.fdir_vsi) {
2060 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2061 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2063 /* Clear all queues and release memory */
2064 i40e_dev_clear_queues(dev);
2067 i40e_dev_set_link_down(dev);
2069 /* Remove all mirror rules */
2070 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2071 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2074 pf->nb_mirror_rule = 0;
2076 if (!rte_intr_allow_others(intr_handle))
2077 /* resume to the default handler */
2078 rte_intr_callback_register(intr_handle,
2079 i40e_dev_interrupt_handler,
2082 /* Clean datapath event and queue/vec mapping */
2083 rte_intr_efd_disable(intr_handle);
2084 if (intr_handle->intr_vec) {
2085 rte_free(intr_handle->intr_vec);
2086 intr_handle->intr_vec = NULL;
2091 i40e_dev_close(struct rte_eth_dev *dev)
2093 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2094 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2095 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2096 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2100 PMD_INIT_FUNC_TRACE();
2103 hw->adapter_stopped = 1;
2104 i40e_dev_free_queues(dev);
2106 /* Disable interrupt */
2107 i40e_pf_disable_irq0(hw);
2108 rte_intr_disable(intr_handle);
2110 /* shutdown and destroy the HMC */
2111 i40e_shutdown_lan_hmc(hw);
2113 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2114 i40e_vsi_release(pf->vmdq[i].vsi);
2115 pf->vmdq[i].vsi = NULL;
2120 /* release all the existing VSIs and VEBs */
2121 i40e_fdir_teardown(pf);
2122 i40e_vsi_release(pf->main_vsi);
2124 /* shutdown the adminq */
2125 i40e_aq_queue_shutdown(hw, true);
2126 i40e_shutdown_adminq(hw);
2128 i40e_res_pool_destroy(&pf->qp_pool);
2129 i40e_res_pool_destroy(&pf->msix_pool);
2131 /* force a PF reset to clean anything leftover */
2132 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2133 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2134 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2135 I40E_WRITE_FLUSH(hw);
2139 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2141 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2142 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2143 struct i40e_vsi *vsi = pf->main_vsi;
2146 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2148 if (status != I40E_SUCCESS)
2149 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2151 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2153 if (status != I40E_SUCCESS)
2154 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2159 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2161 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2162 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2163 struct i40e_vsi *vsi = pf->main_vsi;
2166 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2168 if (status != I40E_SUCCESS)
2169 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2171 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2173 if (status != I40E_SUCCESS)
2174 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2178 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2180 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2181 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2182 struct i40e_vsi *vsi = pf->main_vsi;
2185 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2186 if (ret != I40E_SUCCESS)
2187 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2191 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2193 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2194 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2195 struct i40e_vsi *vsi = pf->main_vsi;
2198 if (dev->data->promiscuous == 1)
2199 return; /* must remain in all_multicast mode */
2201 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2202 vsi->seid, FALSE, NULL);
2203 if (ret != I40E_SUCCESS)
2204 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2208 * Set device link up.
2211 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2213 /* re-apply link speed setting */
2214 return i40e_apply_link_speed(dev);
2218 * Set device link down.
2221 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2223 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2224 uint8_t abilities = 0;
2225 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2227 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2228 return i40e_phy_conf_link(hw, abilities, speed);
2232 i40e_dev_link_update(struct rte_eth_dev *dev,
2233 int wait_to_complete)
2235 #define CHECK_INTERVAL 100 /* 100ms */
2236 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2237 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2238 struct i40e_link_status link_status;
2239 struct rte_eth_link link, old;
2241 unsigned rep_cnt = MAX_REPEAT_TIME;
2242 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2244 memset(&link, 0, sizeof(link));
2245 memset(&old, 0, sizeof(old));
2246 memset(&link_status, 0, sizeof(link_status));
2247 rte_i40e_dev_atomic_read_link_status(dev, &old);
2250 /* Get link status information from hardware */
2251 status = i40e_aq_get_link_info(hw, enable_lse,
2252 &link_status, NULL);
2253 if (status != I40E_SUCCESS) {
2254 link.link_speed = ETH_SPEED_NUM_100M;
2255 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2256 PMD_DRV_LOG(ERR, "Failed to get link info");
2260 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2261 if (!wait_to_complete || link.link_status)
2264 rte_delay_ms(CHECK_INTERVAL);
2265 } while (--rep_cnt);
2267 if (!link.link_status)
2270 /* i40e uses full duplex only */
2271 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2273 /* Parse the link status */
2274 switch (link_status.link_speed) {
2275 case I40E_LINK_SPEED_100MB:
2276 link.link_speed = ETH_SPEED_NUM_100M;
2278 case I40E_LINK_SPEED_1GB:
2279 link.link_speed = ETH_SPEED_NUM_1G;
2281 case I40E_LINK_SPEED_10GB:
2282 link.link_speed = ETH_SPEED_NUM_10G;
2284 case I40E_LINK_SPEED_20GB:
2285 link.link_speed = ETH_SPEED_NUM_20G;
2287 case I40E_LINK_SPEED_25GB:
2288 link.link_speed = ETH_SPEED_NUM_25G;
2290 case I40E_LINK_SPEED_40GB:
2291 link.link_speed = ETH_SPEED_NUM_40G;
2294 link.link_speed = ETH_SPEED_NUM_100M;
2298 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2299 ETH_LINK_SPEED_FIXED);
2302 rte_i40e_dev_atomic_write_link_status(dev, &link);
2303 if (link.link_status == old.link_status)
2306 i40e_notify_all_vfs_link_status(dev);
2311 /* Get all the statistics of a VSI */
2313 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2315 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2316 struct i40e_eth_stats *nes = &vsi->eth_stats;
2317 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2318 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2320 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2321 vsi->offset_loaded, &oes->rx_bytes,
2323 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2324 vsi->offset_loaded, &oes->rx_unicast,
2326 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2327 vsi->offset_loaded, &oes->rx_multicast,
2328 &nes->rx_multicast);
2329 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2330 vsi->offset_loaded, &oes->rx_broadcast,
2331 &nes->rx_broadcast);
2332 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2333 &oes->rx_discards, &nes->rx_discards);
2334 /* GLV_REPC not supported */
2335 /* GLV_RMPC not supported */
2336 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2337 &oes->rx_unknown_protocol,
2338 &nes->rx_unknown_protocol);
2339 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2340 vsi->offset_loaded, &oes->tx_bytes,
2342 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2343 vsi->offset_loaded, &oes->tx_unicast,
2345 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2346 vsi->offset_loaded, &oes->tx_multicast,
2347 &nes->tx_multicast);
2348 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2349 vsi->offset_loaded, &oes->tx_broadcast,
2350 &nes->tx_broadcast);
2351 /* GLV_TDPC not supported */
2352 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2353 &oes->tx_errors, &nes->tx_errors);
2354 vsi->offset_loaded = true;
2356 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2358 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2359 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2360 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2361 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2362 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2363 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2364 nes->rx_unknown_protocol);
2365 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2366 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2367 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2368 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2369 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2370 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2371 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2376 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2379 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2380 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2382 /* Get statistics of struct i40e_eth_stats */
2383 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2384 I40E_GLPRT_GORCL(hw->port),
2385 pf->offset_loaded, &os->eth.rx_bytes,
2387 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2388 I40E_GLPRT_UPRCL(hw->port),
2389 pf->offset_loaded, &os->eth.rx_unicast,
2390 &ns->eth.rx_unicast);
2391 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2392 I40E_GLPRT_MPRCL(hw->port),
2393 pf->offset_loaded, &os->eth.rx_multicast,
2394 &ns->eth.rx_multicast);
2395 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2396 I40E_GLPRT_BPRCL(hw->port),
2397 pf->offset_loaded, &os->eth.rx_broadcast,
2398 &ns->eth.rx_broadcast);
2399 /* Workaround: CRC size should not be included in byte statistics,
2400 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2402 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2403 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2405 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2406 pf->offset_loaded, &os->eth.rx_discards,
2407 &ns->eth.rx_discards);
2408 /* GLPRT_REPC not supported */
2409 /* GLPRT_RMPC not supported */
2410 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2412 &os->eth.rx_unknown_protocol,
2413 &ns->eth.rx_unknown_protocol);
2414 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2415 I40E_GLPRT_GOTCL(hw->port),
2416 pf->offset_loaded, &os->eth.tx_bytes,
2418 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2419 I40E_GLPRT_UPTCL(hw->port),
2420 pf->offset_loaded, &os->eth.tx_unicast,
2421 &ns->eth.tx_unicast);
2422 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2423 I40E_GLPRT_MPTCL(hw->port),
2424 pf->offset_loaded, &os->eth.tx_multicast,
2425 &ns->eth.tx_multicast);
2426 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2427 I40E_GLPRT_BPTCL(hw->port),
2428 pf->offset_loaded, &os->eth.tx_broadcast,
2429 &ns->eth.tx_broadcast);
2430 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2431 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2432 /* GLPRT_TEPC not supported */
2434 /* additional port specific stats */
2435 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2436 pf->offset_loaded, &os->tx_dropped_link_down,
2437 &ns->tx_dropped_link_down);
2438 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2439 pf->offset_loaded, &os->crc_errors,
2441 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2442 pf->offset_loaded, &os->illegal_bytes,
2443 &ns->illegal_bytes);
2444 /* GLPRT_ERRBC not supported */
2445 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2446 pf->offset_loaded, &os->mac_local_faults,
2447 &ns->mac_local_faults);
2448 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2449 pf->offset_loaded, &os->mac_remote_faults,
2450 &ns->mac_remote_faults);
2451 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2452 pf->offset_loaded, &os->rx_length_errors,
2453 &ns->rx_length_errors);
2454 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2455 pf->offset_loaded, &os->link_xon_rx,
2457 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2458 pf->offset_loaded, &os->link_xoff_rx,
2460 for (i = 0; i < 8; i++) {
2461 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2463 &os->priority_xon_rx[i],
2464 &ns->priority_xon_rx[i]);
2465 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2467 &os->priority_xoff_rx[i],
2468 &ns->priority_xoff_rx[i]);
2470 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2471 pf->offset_loaded, &os->link_xon_tx,
2473 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2474 pf->offset_loaded, &os->link_xoff_tx,
2476 for (i = 0; i < 8; i++) {
2477 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2479 &os->priority_xon_tx[i],
2480 &ns->priority_xon_tx[i]);
2481 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2483 &os->priority_xoff_tx[i],
2484 &ns->priority_xoff_tx[i]);
2485 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2487 &os->priority_xon_2_xoff[i],
2488 &ns->priority_xon_2_xoff[i]);
2490 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2491 I40E_GLPRT_PRC64L(hw->port),
2492 pf->offset_loaded, &os->rx_size_64,
2494 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2495 I40E_GLPRT_PRC127L(hw->port),
2496 pf->offset_loaded, &os->rx_size_127,
2498 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2499 I40E_GLPRT_PRC255L(hw->port),
2500 pf->offset_loaded, &os->rx_size_255,
2502 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2503 I40E_GLPRT_PRC511L(hw->port),
2504 pf->offset_loaded, &os->rx_size_511,
2506 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2507 I40E_GLPRT_PRC1023L(hw->port),
2508 pf->offset_loaded, &os->rx_size_1023,
2510 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2511 I40E_GLPRT_PRC1522L(hw->port),
2512 pf->offset_loaded, &os->rx_size_1522,
2514 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2515 I40E_GLPRT_PRC9522L(hw->port),
2516 pf->offset_loaded, &os->rx_size_big,
2518 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2519 pf->offset_loaded, &os->rx_undersize,
2521 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2522 pf->offset_loaded, &os->rx_fragments,
2524 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2525 pf->offset_loaded, &os->rx_oversize,
2527 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2528 pf->offset_loaded, &os->rx_jabber,
2530 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2531 I40E_GLPRT_PTC64L(hw->port),
2532 pf->offset_loaded, &os->tx_size_64,
2534 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2535 I40E_GLPRT_PTC127L(hw->port),
2536 pf->offset_loaded, &os->tx_size_127,
2538 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2539 I40E_GLPRT_PTC255L(hw->port),
2540 pf->offset_loaded, &os->tx_size_255,
2542 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2543 I40E_GLPRT_PTC511L(hw->port),
2544 pf->offset_loaded, &os->tx_size_511,
2546 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2547 I40E_GLPRT_PTC1023L(hw->port),
2548 pf->offset_loaded, &os->tx_size_1023,
2550 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2551 I40E_GLPRT_PTC1522L(hw->port),
2552 pf->offset_loaded, &os->tx_size_1522,
2554 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2555 I40E_GLPRT_PTC9522L(hw->port),
2556 pf->offset_loaded, &os->tx_size_big,
2558 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2560 &os->fd_sb_match, &ns->fd_sb_match);
2561 /* GLPRT_MSPDC not supported */
2562 /* GLPRT_XEC not supported */
2564 pf->offset_loaded = true;
2567 i40e_update_vsi_stats(pf->main_vsi);
2570 /* Get all statistics of a port */
2572 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2574 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2575 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2576 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2579 /* call read registers - updates values, now write them to struct */
2580 i40e_read_stats_registers(pf, hw);
2582 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2583 pf->main_vsi->eth_stats.rx_multicast +
2584 pf->main_vsi->eth_stats.rx_broadcast -
2585 pf->main_vsi->eth_stats.rx_discards;
2586 stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2587 pf->main_vsi->eth_stats.tx_multicast +
2588 pf->main_vsi->eth_stats.tx_broadcast;
2589 stats->ibytes = ns->eth.rx_bytes;
2590 stats->obytes = ns->eth.tx_bytes;
2591 stats->oerrors = ns->eth.tx_errors +
2592 pf->main_vsi->eth_stats.tx_errors;
2595 stats->imissed = ns->eth.rx_discards +
2596 pf->main_vsi->eth_stats.rx_discards;
2597 stats->ierrors = ns->crc_errors +
2598 ns->rx_length_errors + ns->rx_undersize +
2599 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2601 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2602 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
2603 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
2604 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
2605 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
2606 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
2607 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2608 ns->eth.rx_unknown_protocol);
2609 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
2610 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
2611 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
2612 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
2613 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
2614 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
2616 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
2617 ns->tx_dropped_link_down);
2618 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
2619 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
2621 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
2622 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
2623 ns->mac_local_faults);
2624 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
2625 ns->mac_remote_faults);
2626 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
2627 ns->rx_length_errors);
2628 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
2629 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
2630 for (i = 0; i < 8; i++) {
2631 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
2632 i, ns->priority_xon_rx[i]);
2633 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
2634 i, ns->priority_xoff_rx[i]);
2636 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
2637 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
2638 for (i = 0; i < 8; i++) {
2639 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
2640 i, ns->priority_xon_tx[i]);
2641 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
2642 i, ns->priority_xoff_tx[i]);
2643 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
2644 i, ns->priority_xon_2_xoff[i]);
2646 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
2647 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
2648 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
2649 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
2650 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
2651 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
2652 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
2653 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
2654 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
2655 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
2656 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
2657 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
2658 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
2659 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
2660 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
2661 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
2662 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
2663 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
2664 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2665 ns->mac_short_packet_dropped);
2666 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
2667 ns->checksum_error);
2668 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
2669 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2672 /* Reset the statistics */
2674 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2676 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2677 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2679 /* Mark PF and VSI stats to update the offset, aka "reset" */
2680 pf->offset_loaded = false;
2682 pf->main_vsi->offset_loaded = false;
2684 /* read the stats, reading current register values into offset */
2685 i40e_read_stats_registers(pf, hw);
2689 i40e_xstats_calc_num(void)
2691 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2692 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2693 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2696 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2697 struct rte_eth_xstat_name *xstats_names,
2698 __rte_unused unsigned limit)
2703 if (xstats_names == NULL)
2704 return i40e_xstats_calc_num();
2706 /* Note: limit checked in rte_eth_xstats_names() */
2708 /* Get stats from i40e_eth_stats struct */
2709 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2710 snprintf(xstats_names[count].name,
2711 sizeof(xstats_names[count].name),
2712 "%s", rte_i40e_stats_strings[i].name);
2716 /* Get individiual stats from i40e_hw_port struct */
2717 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2718 snprintf(xstats_names[count].name,
2719 sizeof(xstats_names[count].name),
2720 "%s", rte_i40e_hw_port_strings[i].name);
2724 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2725 for (prio = 0; prio < 8; prio++) {
2726 snprintf(xstats_names[count].name,
2727 sizeof(xstats_names[count].name),
2728 "rx_priority%u_%s", prio,
2729 rte_i40e_rxq_prio_strings[i].name);
2734 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2735 for (prio = 0; prio < 8; prio++) {
2736 snprintf(xstats_names[count].name,
2737 sizeof(xstats_names[count].name),
2738 "tx_priority%u_%s", prio,
2739 rte_i40e_txq_prio_strings[i].name);
2747 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2750 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2751 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2752 unsigned i, count, prio;
2753 struct i40e_hw_port_stats *hw_stats = &pf->stats;
2755 count = i40e_xstats_calc_num();
2759 i40e_read_stats_registers(pf, hw);
2766 /* Get stats from i40e_eth_stats struct */
2767 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2768 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2769 rte_i40e_stats_strings[i].offset);
2770 xstats[count].id = count;
2774 /* Get individiual stats from i40e_hw_port struct */
2775 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2776 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2777 rte_i40e_hw_port_strings[i].offset);
2778 xstats[count].id = count;
2782 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2783 for (prio = 0; prio < 8; prio++) {
2784 xstats[count].value =
2785 *(uint64_t *)(((char *)hw_stats) +
2786 rte_i40e_rxq_prio_strings[i].offset +
2787 (sizeof(uint64_t) * prio));
2788 xstats[count].id = count;
2793 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2794 for (prio = 0; prio < 8; prio++) {
2795 xstats[count].value =
2796 *(uint64_t *)(((char *)hw_stats) +
2797 rte_i40e_txq_prio_strings[i].offset +
2798 (sizeof(uint64_t) * prio));
2799 xstats[count].id = count;
2808 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2809 __rte_unused uint16_t queue_id,
2810 __rte_unused uint8_t stat_idx,
2811 __rte_unused uint8_t is_rx)
2813 PMD_INIT_FUNC_TRACE();
2819 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2821 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2827 full_ver = hw->nvm.oem_ver;
2828 ver = (u8)(full_ver >> 24);
2829 build = (u16)((full_ver >> 8) & 0xffff);
2830 patch = (u8)(full_ver & 0xff);
2832 ret = snprintf(fw_version, fw_size,
2833 "%d.%d%d 0x%08x %d.%d.%d",
2834 ((hw->nvm.version >> 12) & 0xf),
2835 ((hw->nvm.version >> 4) & 0xff),
2836 (hw->nvm.version & 0xf), hw->nvm.eetrack,
2839 ret += 1; /* add the size of '\0' */
2840 if (fw_size < (u32)ret)
2847 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2849 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2850 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2851 struct i40e_vsi *vsi = pf->main_vsi;
2852 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2854 dev_info->pci_dev = pci_dev;
2855 dev_info->max_rx_queues = vsi->nb_qps;
2856 dev_info->max_tx_queues = vsi->nb_qps;
2857 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2858 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2859 dev_info->max_mac_addrs = vsi->max_macaddrs;
2860 dev_info->max_vfs = pci_dev->max_vfs;
2861 dev_info->rx_offload_capa =
2862 DEV_RX_OFFLOAD_VLAN_STRIP |
2863 DEV_RX_OFFLOAD_QINQ_STRIP |
2864 DEV_RX_OFFLOAD_IPV4_CKSUM |
2865 DEV_RX_OFFLOAD_UDP_CKSUM |
2866 DEV_RX_OFFLOAD_TCP_CKSUM;
2867 dev_info->tx_offload_capa =
2868 DEV_TX_OFFLOAD_VLAN_INSERT |
2869 DEV_TX_OFFLOAD_QINQ_INSERT |
2870 DEV_TX_OFFLOAD_IPV4_CKSUM |
2871 DEV_TX_OFFLOAD_UDP_CKSUM |
2872 DEV_TX_OFFLOAD_TCP_CKSUM |
2873 DEV_TX_OFFLOAD_SCTP_CKSUM |
2874 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2875 DEV_TX_OFFLOAD_TCP_TSO |
2876 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2877 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2878 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2879 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2880 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2882 dev_info->reta_size = pf->hash_lut_size;
2883 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2885 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2887 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2888 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2889 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2891 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2895 dev_info->default_txconf = (struct rte_eth_txconf) {
2897 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2898 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2899 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2901 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2902 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2903 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2904 ETH_TXQ_FLAGS_NOOFFLOADS,
2907 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2908 .nb_max = I40E_MAX_RING_DESC,
2909 .nb_min = I40E_MIN_RING_DESC,
2910 .nb_align = I40E_ALIGN_RING_DESC,
2913 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2914 .nb_max = I40E_MAX_RING_DESC,
2915 .nb_min = I40E_MIN_RING_DESC,
2916 .nb_align = I40E_ALIGN_RING_DESC,
2917 .nb_seg_max = I40E_TX_MAX_SEG,
2918 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
2921 if (pf->flags & I40E_FLAG_VMDQ) {
2922 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2923 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2924 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2925 pf->max_nb_vmdq_vsi;
2926 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2927 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2928 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2931 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2933 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2934 else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2936 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2939 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2943 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2945 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2946 struct i40e_vsi *vsi = pf->main_vsi;
2947 PMD_INIT_FUNC_TRACE();
2950 return i40e_vsi_add_vlan(vsi, vlan_id);
2952 return i40e_vsi_delete_vlan(vsi, vlan_id);
2956 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2957 enum rte_vlan_type vlan_type,
2960 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2961 uint64_t reg_r = 0, reg_w = 0;
2962 uint16_t reg_id = 0;
2964 int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2966 switch (vlan_type) {
2967 case ETH_VLAN_TYPE_OUTER:
2973 case ETH_VLAN_TYPE_INNER:
2979 "Unsupported vlan type in single vlan.");
2985 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2988 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2990 if (ret != I40E_SUCCESS) {
2992 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
2998 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3001 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3002 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3003 if (reg_r == reg_w) {
3005 PMD_DRV_LOG(DEBUG, "No need to write");
3009 ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3011 if (ret != I40E_SUCCESS) {
3014 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3019 "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3026 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3028 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3029 struct i40e_vsi *vsi = pf->main_vsi;
3031 if (mask & ETH_VLAN_FILTER_MASK) {
3032 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3033 i40e_vsi_config_vlan_filter(vsi, TRUE);
3035 i40e_vsi_config_vlan_filter(vsi, FALSE);
3038 if (mask & ETH_VLAN_STRIP_MASK) {
3039 /* Enable or disable VLAN stripping */
3040 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3041 i40e_vsi_config_vlan_stripping(vsi, TRUE);
3043 i40e_vsi_config_vlan_stripping(vsi, FALSE);
3046 if (mask & ETH_VLAN_EXTEND_MASK) {
3047 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3048 i40e_vsi_config_double_vlan(vsi, TRUE);
3049 /* Set global registers with default ether type value */
3050 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3052 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3056 i40e_vsi_config_double_vlan(vsi, FALSE);
3061 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3062 __rte_unused uint16_t queue,
3063 __rte_unused int on)
3065 PMD_INIT_FUNC_TRACE();
3069 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3071 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3072 struct i40e_vsi *vsi = pf->main_vsi;
3073 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3074 struct i40e_vsi_vlan_pvid_info info;
3076 memset(&info, 0, sizeof(info));
3079 info.config.pvid = pvid;
3081 info.config.reject.tagged =
3082 data->dev_conf.txmode.hw_vlan_reject_tagged;
3083 info.config.reject.untagged =
3084 data->dev_conf.txmode.hw_vlan_reject_untagged;
3087 return i40e_vsi_vlan_pvid_set(vsi, &info);
3091 i40e_dev_led_on(struct rte_eth_dev *dev)
3093 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3094 uint32_t mode = i40e_led_get(hw);
3097 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3103 i40e_dev_led_off(struct rte_eth_dev *dev)
3105 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3106 uint32_t mode = i40e_led_get(hw);
3109 i40e_led_set(hw, 0, false);
3115 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3117 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3118 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3120 fc_conf->pause_time = pf->fc_conf.pause_time;
3121 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3122 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3124 /* Return current mode according to actual setting*/
3125 switch (hw->fc.current_mode) {
3127 fc_conf->mode = RTE_FC_FULL;
3129 case I40E_FC_TX_PAUSE:
3130 fc_conf->mode = RTE_FC_TX_PAUSE;
3132 case I40E_FC_RX_PAUSE:
3133 fc_conf->mode = RTE_FC_RX_PAUSE;
3137 fc_conf->mode = RTE_FC_NONE;
3144 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3146 uint32_t mflcn_reg, fctrl_reg, reg;
3147 uint32_t max_high_water;
3148 uint8_t i, aq_failure;
3152 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3153 [RTE_FC_NONE] = I40E_FC_NONE,
3154 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3155 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3156 [RTE_FC_FULL] = I40E_FC_FULL
3159 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3161 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3162 if ((fc_conf->high_water > max_high_water) ||
3163 (fc_conf->high_water < fc_conf->low_water)) {
3165 "Invalid high/low water setup value in KB, High_water must be <= %d.",
3170 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3171 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3172 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3174 pf->fc_conf.pause_time = fc_conf->pause_time;
3175 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3176 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3178 PMD_INIT_FUNC_TRACE();
3180 /* All the link flow control related enable/disable register
3181 * configuration is handle by the F/W
3183 err = i40e_set_fc(hw, &aq_failure, true);
3187 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3188 /* Configure flow control refresh threshold,
3189 * the value for stat_tx_pause_refresh_timer[8]
3190 * is used for global pause operation.
3194 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3195 pf->fc_conf.pause_time);
3197 /* configure the timer value included in transmitted pause
3199 * the value for stat_tx_pause_quanta[8] is used for global
3202 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3203 pf->fc_conf.pause_time);
3205 fctrl_reg = I40E_READ_REG(hw,
3206 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3208 if (fc_conf->mac_ctrl_frame_fwd != 0)
3209 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3211 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3213 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3216 /* Configure pause time (2 TCs per register) */
3217 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3218 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3219 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3221 /* Configure flow control refresh threshold value */
3222 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3223 pf->fc_conf.pause_time / 2);
3225 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3227 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3228 *depending on configuration
3230 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3231 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3232 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3234 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3235 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3238 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3241 /* config the water marker both based on the packets and bytes */
3242 I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3243 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3244 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3245 I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3246 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3247 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3248 I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3249 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3251 I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3252 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3255 I40E_WRITE_FLUSH(hw);
3261 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3262 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3264 PMD_INIT_FUNC_TRACE();
3269 /* Add a MAC address, and update filters */
3271 i40e_macaddr_add(struct rte_eth_dev *dev,
3272 struct ether_addr *mac_addr,
3273 __rte_unused uint32_t index,
3276 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3277 struct i40e_mac_filter_info mac_filter;
3278 struct i40e_vsi *vsi;
3281 /* If VMDQ not enabled or configured, return */
3282 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3283 !pf->nb_cfg_vmdq_vsi)) {
3284 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3285 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3290 if (pool > pf->nb_cfg_vmdq_vsi) {
3291 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3292 pool, pf->nb_cfg_vmdq_vsi);
3296 (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3297 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3298 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3300 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3305 vsi = pf->vmdq[pool - 1].vsi;
3307 ret = i40e_vsi_add_mac(vsi, &mac_filter);
3308 if (ret != I40E_SUCCESS) {
3309 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3314 /* Remove a MAC address, and update filters */
3316 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3318 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3319 struct i40e_vsi *vsi;
3320 struct rte_eth_dev_data *data = dev->data;
3321 struct ether_addr *macaddr;
3326 macaddr = &(data->mac_addrs[index]);
3328 pool_sel = dev->data->mac_pool_sel[index];
3330 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3331 if (pool_sel & (1ULL << i)) {
3335 /* No VMDQ pool enabled or configured */
3336 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3337 (i > pf->nb_cfg_vmdq_vsi)) {
3339 "No VMDQ pool enabled/configured");
3342 vsi = pf->vmdq[i - 1].vsi;
3344 ret = i40e_vsi_delete_mac(vsi, macaddr);
3347 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3354 /* Set perfect match or hash match of MAC and VLAN for a VF */
3356 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3357 struct rte_eth_mac_filter *filter,
3361 struct i40e_mac_filter_info mac_filter;
3362 struct ether_addr old_mac;
3363 struct ether_addr *new_mac;
3364 struct i40e_pf_vf *vf = NULL;
3369 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3372 hw = I40E_PF_TO_HW(pf);
3374 if (filter == NULL) {
3375 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3379 new_mac = &filter->mac_addr;
3381 if (is_zero_ether_addr(new_mac)) {
3382 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3386 vf_id = filter->dst_id;
3388 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3389 PMD_DRV_LOG(ERR, "Invalid argument.");
3392 vf = &pf->vfs[vf_id];
3394 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3395 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3400 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3401 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3403 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3406 mac_filter.filter_type = filter->filter_type;
3407 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3408 if (ret != I40E_SUCCESS) {
3409 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3412 ether_addr_copy(new_mac, &pf->dev_addr);
3414 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3416 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3417 if (ret != I40E_SUCCESS) {
3418 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3422 /* Clear device address as it has been removed */
3423 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3424 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3430 /* MAC filter handle */
3432 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3435 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3436 struct rte_eth_mac_filter *filter;
3437 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3438 int ret = I40E_NOT_SUPPORTED;
3440 filter = (struct rte_eth_mac_filter *)(arg);
3442 switch (filter_op) {
3443 case RTE_ETH_FILTER_NOP:
3446 case RTE_ETH_FILTER_ADD:
3447 i40e_pf_disable_irq0(hw);
3449 ret = i40e_vf_mac_filter_set(pf, filter, 1);
3450 i40e_pf_enable_irq0(hw);
3452 case RTE_ETH_FILTER_DELETE:
3453 i40e_pf_disable_irq0(hw);
3455 ret = i40e_vf_mac_filter_set(pf, filter, 0);
3456 i40e_pf_enable_irq0(hw);
3459 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3460 ret = I40E_ERR_PARAM;
3468 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3470 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3471 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3477 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3478 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3481 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3485 uint32_t *lut_dw = (uint32_t *)lut;
3486 uint16_t i, lut_size_dw = lut_size / 4;
3488 for (i = 0; i < lut_size_dw; i++)
3489 lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3496 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3505 pf = I40E_VSI_TO_PF(vsi);
3506 hw = I40E_VSI_TO_HW(vsi);
3508 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3509 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3512 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3516 uint32_t *lut_dw = (uint32_t *)lut;
3517 uint16_t i, lut_size_dw = lut_size / 4;
3519 for (i = 0; i < lut_size_dw; i++)
3520 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3521 I40E_WRITE_FLUSH(hw);
3528 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3529 struct rte_eth_rss_reta_entry64 *reta_conf,
3532 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3533 uint16_t i, lut_size = pf->hash_lut_size;
3534 uint16_t idx, shift;
3538 if (reta_size != lut_size ||
3539 reta_size > ETH_RSS_RETA_SIZE_512) {
3541 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3542 reta_size, lut_size);
3546 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3548 PMD_DRV_LOG(ERR, "No memory can be allocated");
3551 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3554 for (i = 0; i < reta_size; i++) {
3555 idx = i / RTE_RETA_GROUP_SIZE;
3556 shift = i % RTE_RETA_GROUP_SIZE;
3557 if (reta_conf[idx].mask & (1ULL << shift))
3558 lut[i] = reta_conf[idx].reta[shift];
3560 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3569 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3570 struct rte_eth_rss_reta_entry64 *reta_conf,
3573 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3574 uint16_t i, lut_size = pf->hash_lut_size;
3575 uint16_t idx, shift;
3579 if (reta_size != lut_size ||
3580 reta_size > ETH_RSS_RETA_SIZE_512) {
3582 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3583 reta_size, lut_size);
3587 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3589 PMD_DRV_LOG(ERR, "No memory can be allocated");
3593 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3596 for (i = 0; i < reta_size; i++) {
3597 idx = i / RTE_RETA_GROUP_SIZE;
3598 shift = i % RTE_RETA_GROUP_SIZE;
3599 if (reta_conf[idx].mask & (1ULL << shift))
3600 reta_conf[idx].reta[shift] = lut[i];
3610 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3611 * @hw: pointer to the HW structure
3612 * @mem: pointer to mem struct to fill out
3613 * @size: size of memory requested
3614 * @alignment: what to align the allocation to
3616 enum i40e_status_code
3617 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3618 struct i40e_dma_mem *mem,
3622 const struct rte_memzone *mz = NULL;
3623 char z_name[RTE_MEMZONE_NAMESIZE];
3626 return I40E_ERR_PARAM;
3628 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3629 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3630 alignment, RTE_PGSIZE_2M);
3632 return I40E_ERR_NO_MEMORY;
3636 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3637 mem->zone = (const void *)mz;
3639 "memzone %s allocated with physical address: %"PRIu64,
3642 return I40E_SUCCESS;
3646 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3647 * @hw: pointer to the HW structure
3648 * @mem: ptr to mem struct to free
3650 enum i40e_status_code
3651 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3652 struct i40e_dma_mem *mem)
3655 return I40E_ERR_PARAM;
3658 "memzone %s to be freed with physical address: %"PRIu64,
3659 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3660 rte_memzone_free((const struct rte_memzone *)mem->zone);
3665 return I40E_SUCCESS;
3669 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3670 * @hw: pointer to the HW structure
3671 * @mem: pointer to mem struct to fill out
3672 * @size: size of memory requested
3674 enum i40e_status_code
3675 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3676 struct i40e_virt_mem *mem,
3680 return I40E_ERR_PARAM;
3683 mem->va = rte_zmalloc("i40e", size, 0);
3686 return I40E_SUCCESS;
3688 return I40E_ERR_NO_MEMORY;
3692 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3693 * @hw: pointer to the HW structure
3694 * @mem: pointer to mem struct to free
3696 enum i40e_status_code
3697 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3698 struct i40e_virt_mem *mem)
3701 return I40E_ERR_PARAM;
3706 return I40E_SUCCESS;
3710 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3712 rte_spinlock_init(&sp->spinlock);
3716 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3718 rte_spinlock_lock(&sp->spinlock);
3722 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3724 rte_spinlock_unlock(&sp->spinlock);
3728 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3734 * Get the hardware capabilities, which will be parsed
3735 * and saved into struct i40e_hw.
3738 i40e_get_cap(struct i40e_hw *hw)
3740 struct i40e_aqc_list_capabilities_element_resp *buf;
3741 uint16_t len, size = 0;
3744 /* Calculate a huge enough buff for saving response data temporarily */
3745 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3746 I40E_MAX_CAP_ELE_NUM;
3747 buf = rte_zmalloc("i40e", len, 0);
3749 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3750 return I40E_ERR_NO_MEMORY;
3753 /* Get, parse the capabilities and save it to hw */
3754 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3755 i40e_aqc_opc_list_func_capabilities, NULL);
3756 if (ret != I40E_SUCCESS)
3757 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3759 /* Free the temporary buffer after being used */
3766 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3768 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3769 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3770 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
3771 uint16_t qp_count = 0, vsi_count = 0;
3773 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3774 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3777 /* Add the parameter init for LFC */
3778 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3779 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3780 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3782 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3783 pf->max_num_vsi = hw->func_caps.num_vsis;
3784 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3785 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3786 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3788 /* FDir queue/VSI allocation */
3789 pf->fdir_qp_offset = 0;
3790 if (hw->func_caps.fd) {
3791 pf->flags |= I40E_FLAG_FDIR;
3792 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3794 pf->fdir_nb_qps = 0;
3796 qp_count += pf->fdir_nb_qps;
3799 /* LAN queue/VSI allocation */
3800 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3801 if (!hw->func_caps.rss) {
3804 pf->flags |= I40E_FLAG_RSS;
3805 if (hw->mac.type == I40E_MAC_X722)
3806 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3807 pf->lan_nb_qps = pf->lan_nb_qp_max;
3809 qp_count += pf->lan_nb_qps;
3812 /* VF queue/VSI allocation */
3813 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3814 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3815 pf->flags |= I40E_FLAG_SRIOV;
3816 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3817 pf->vf_num = pci_dev->max_vfs;
3819 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
3820 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
3825 qp_count += pf->vf_nb_qps * pf->vf_num;
3826 vsi_count += pf->vf_num;
3828 /* VMDq queue/VSI allocation */
3829 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3830 pf->vmdq_nb_qps = 0;
3831 pf->max_nb_vmdq_vsi = 0;
3832 if (hw->func_caps.vmdq) {
3833 if (qp_count < hw->func_caps.num_tx_qp &&
3834 vsi_count < hw->func_caps.num_vsis) {
3835 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3836 qp_count) / pf->vmdq_nb_qp_max;
3838 /* Limit the maximum number of VMDq vsi to the maximum
3839 * ethdev can support
3841 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3842 hw->func_caps.num_vsis - vsi_count);
3843 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3845 if (pf->max_nb_vmdq_vsi) {
3846 pf->flags |= I40E_FLAG_VMDQ;
3847 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3849 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
3850 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
3851 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
3854 "No enough queues left for VMDq");
3857 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3860 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3861 vsi_count += pf->max_nb_vmdq_vsi;
3863 if (hw->func_caps.dcb)
3864 pf->flags |= I40E_FLAG_DCB;
3866 if (qp_count > hw->func_caps.num_tx_qp) {
3868 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
3869 qp_count, hw->func_caps.num_tx_qp);
3872 if (vsi_count > hw->func_caps.num_vsis) {
3874 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
3875 vsi_count, hw->func_caps.num_vsis);
3883 i40e_pf_get_switch_config(struct i40e_pf *pf)
3885 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3886 struct i40e_aqc_get_switch_config_resp *switch_config;
3887 struct i40e_aqc_switch_config_element_resp *element;
3888 uint16_t start_seid = 0, num_reported;
3891 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3892 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3893 if (!switch_config) {
3894 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3898 /* Get the switch configurations */
3899 ret = i40e_aq_get_switch_config(hw, switch_config,
3900 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3901 if (ret != I40E_SUCCESS) {
3902 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3905 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3906 if (num_reported != 1) { /* The number should be 1 */
3907 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3911 /* Parse the switch configuration elements */
3912 element = &(switch_config->element[0]);
3913 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3914 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3915 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3917 PMD_DRV_LOG(INFO, "Unknown element type");
3920 rte_free(switch_config);
3926 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3929 struct pool_entry *entry;
3931 if (pool == NULL || num == 0)
3934 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3935 if (entry == NULL) {
3936 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3940 /* queue heap initialize */
3941 pool->num_free = num;
3942 pool->num_alloc = 0;
3944 LIST_INIT(&pool->alloc_list);
3945 LIST_INIT(&pool->free_list);
3947 /* Initialize element */
3951 LIST_INSERT_HEAD(&pool->free_list, entry, next);
3956 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3958 struct pool_entry *entry, *next_entry;
3963 for (entry = LIST_FIRST(&pool->alloc_list);
3964 entry && (next_entry = LIST_NEXT(entry, next), 1);
3965 entry = next_entry) {
3966 LIST_REMOVE(entry, next);
3970 for (entry = LIST_FIRST(&pool->free_list);
3971 entry && (next_entry = LIST_NEXT(entry, next), 1);
3972 entry = next_entry) {
3973 LIST_REMOVE(entry, next);
3978 pool->num_alloc = 0;
3980 LIST_INIT(&pool->alloc_list);
3981 LIST_INIT(&pool->free_list);
3985 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3988 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3989 uint32_t pool_offset;
3993 PMD_DRV_LOG(ERR, "Invalid parameter");
3997 pool_offset = base - pool->base;
3998 /* Lookup in alloc list */
3999 LIST_FOREACH(entry, &pool->alloc_list, next) {
4000 if (entry->base == pool_offset) {
4001 valid_entry = entry;
4002 LIST_REMOVE(entry, next);
4007 /* Not find, return */
4008 if (valid_entry == NULL) {
4009 PMD_DRV_LOG(ERR, "Failed to find entry");
4014 * Found it, move it to free list and try to merge.
4015 * In order to make merge easier, always sort it by qbase.
4016 * Find adjacent prev and last entries.
4019 LIST_FOREACH(entry, &pool->free_list, next) {
4020 if (entry->base > valid_entry->base) {
4028 /* Try to merge with next one*/
4030 /* Merge with next one */
4031 if (valid_entry->base + valid_entry->len == next->base) {
4032 next->base = valid_entry->base;
4033 next->len += valid_entry->len;
4034 rte_free(valid_entry);
4041 /* Merge with previous one */
4042 if (prev->base + prev->len == valid_entry->base) {
4043 prev->len += valid_entry->len;
4044 /* If it merge with next one, remove next node */
4046 LIST_REMOVE(valid_entry, next);
4047 rte_free(valid_entry);
4049 rte_free(valid_entry);
4055 /* Not find any entry to merge, insert */
4058 LIST_INSERT_AFTER(prev, valid_entry, next);
4059 else if (next != NULL)
4060 LIST_INSERT_BEFORE(next, valid_entry, next);
4061 else /* It's empty list, insert to head */
4062 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4065 pool->num_free += valid_entry->len;
4066 pool->num_alloc -= valid_entry->len;
4072 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4075 struct pool_entry *entry, *valid_entry;
4077 if (pool == NULL || num == 0) {
4078 PMD_DRV_LOG(ERR, "Invalid parameter");
4082 if (pool->num_free < num) {
4083 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4084 num, pool->num_free);
4089 /* Lookup in free list and find most fit one */
4090 LIST_FOREACH(entry, &pool->free_list, next) {
4091 if (entry->len >= num) {
4093 if (entry->len == num) {
4094 valid_entry = entry;
4097 if (valid_entry == NULL || valid_entry->len > entry->len)
4098 valid_entry = entry;
4102 /* Not find one to satisfy the request, return */
4103 if (valid_entry == NULL) {
4104 PMD_DRV_LOG(ERR, "No valid entry found");
4108 * The entry have equal queue number as requested,
4109 * remove it from alloc_list.
4111 if (valid_entry->len == num) {
4112 LIST_REMOVE(valid_entry, next);
4115 * The entry have more numbers than requested,
4116 * create a new entry for alloc_list and minus its
4117 * queue base and number in free_list.
4119 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4120 if (entry == NULL) {
4122 "Failed to allocate memory for resource pool");
4125 entry->base = valid_entry->base;
4127 valid_entry->base += num;
4128 valid_entry->len -= num;
4129 valid_entry = entry;
4132 /* Insert it into alloc list, not sorted */
4133 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4135 pool->num_free -= valid_entry->len;
4136 pool->num_alloc += valid_entry->len;
4138 return valid_entry->base + pool->base;
4142 * bitmap_is_subset - Check whether src2 is subset of src1
4145 bitmap_is_subset(uint8_t src1, uint8_t src2)
4147 return !((src1 ^ src2) & src2);
4150 static enum i40e_status_code
4151 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4153 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4155 /* If DCB is not supported, only default TC is supported */
4156 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4157 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4158 return I40E_NOT_SUPPORTED;
4161 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4163 "Enabled TC map 0x%x not applicable to HW support 0x%x",
4164 hw->func_caps.enabled_tcmap, enabled_tcmap);
4165 return I40E_NOT_SUPPORTED;
4167 return I40E_SUCCESS;
4171 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4172 struct i40e_vsi_vlan_pvid_info *info)
4175 struct i40e_vsi_context ctxt;
4176 uint8_t vlan_flags = 0;
4179 if (vsi == NULL || info == NULL) {
4180 PMD_DRV_LOG(ERR, "invalid parameters");
4181 return I40E_ERR_PARAM;
4185 vsi->info.pvid = info->config.pvid;
4187 * If insert pvid is enabled, only tagged pkts are
4188 * allowed to be sent out.
4190 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4191 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4194 if (info->config.reject.tagged == 0)
4195 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4197 if (info->config.reject.untagged == 0)
4198 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4200 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4201 I40E_AQ_VSI_PVLAN_MODE_MASK);
4202 vsi->info.port_vlan_flags |= vlan_flags;
4203 vsi->info.valid_sections =
4204 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4205 memset(&ctxt, 0, sizeof(ctxt));
4206 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4207 ctxt.seid = vsi->seid;
4209 hw = I40E_VSI_TO_HW(vsi);
4210 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4211 if (ret != I40E_SUCCESS)
4212 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4218 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4220 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4222 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4224 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4225 if (ret != I40E_SUCCESS)
4229 PMD_DRV_LOG(ERR, "seid not valid");
4233 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4234 tc_bw_data.tc_valid_bits = enabled_tcmap;
4235 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4236 tc_bw_data.tc_bw_credits[i] =
4237 (enabled_tcmap & (1 << i)) ? 1 : 0;
4239 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4240 if (ret != I40E_SUCCESS) {
4241 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4245 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4246 sizeof(vsi->info.qs_handle));
4247 return I40E_SUCCESS;
4250 static enum i40e_status_code
4251 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4252 struct i40e_aqc_vsi_properties_data *info,
4253 uint8_t enabled_tcmap)
4255 enum i40e_status_code ret;
4256 int i, total_tc = 0;
4257 uint16_t qpnum_per_tc, bsf, qp_idx;
4259 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4260 if (ret != I40E_SUCCESS)
4263 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4264 if (enabled_tcmap & (1 << i))
4266 vsi->enabled_tc = enabled_tcmap;
4268 /* Number of queues per enabled TC */
4269 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4270 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4271 bsf = rte_bsf32(qpnum_per_tc);
4273 /* Adjust the queue number to actual queues that can be applied */
4274 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4275 vsi->nb_qps = qpnum_per_tc * total_tc;
4278 * Configure TC and queue mapping parameters, for enabled TC,
4279 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4280 * default queue will serve it.
4283 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4284 if (vsi->enabled_tc & (1 << i)) {
4285 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4286 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4287 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4288 qp_idx += qpnum_per_tc;
4290 info->tc_mapping[i] = 0;
4293 /* Associate queue number with VSI */
4294 if (vsi->type == I40E_VSI_SRIOV) {
4295 info->mapping_flags |=
4296 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4297 for (i = 0; i < vsi->nb_qps; i++)
4298 info->queue_mapping[i] =
4299 rte_cpu_to_le_16(vsi->base_queue + i);
4301 info->mapping_flags |=
4302 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4303 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4305 info->valid_sections |=
4306 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4308 return I40E_SUCCESS;
4312 i40e_veb_release(struct i40e_veb *veb)
4314 struct i40e_vsi *vsi;
4320 if (!TAILQ_EMPTY(&veb->head)) {
4321 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4324 /* associate_vsi field is NULL for floating VEB */
4325 if (veb->associate_vsi != NULL) {
4326 vsi = veb->associate_vsi;
4327 hw = I40E_VSI_TO_HW(vsi);
4329 vsi->uplink_seid = veb->uplink_seid;
4332 veb->associate_pf->main_vsi->floating_veb = NULL;
4333 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4336 i40e_aq_delete_element(hw, veb->seid, NULL);
4338 return I40E_SUCCESS;
4342 static struct i40e_veb *
4343 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4345 struct i40e_veb *veb;
4351 "veb setup failed, associated PF shouldn't null");
4354 hw = I40E_PF_TO_HW(pf);
4356 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4358 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4362 veb->associate_vsi = vsi;
4363 veb->associate_pf = pf;
4364 TAILQ_INIT(&veb->head);
4365 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4367 /* create floating veb if vsi is NULL */
4369 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4370 I40E_DEFAULT_TCMAP, false,
4371 &veb->seid, false, NULL);
4373 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4374 true, &veb->seid, false, NULL);
4377 if (ret != I40E_SUCCESS) {
4378 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4379 hw->aq.asq_last_status);
4382 veb->enabled_tc = I40E_DEFAULT_TCMAP;
4384 /* get statistics index */
4385 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4386 &veb->stats_idx, NULL, NULL, NULL);
4387 if (ret != I40E_SUCCESS) {
4388 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4389 hw->aq.asq_last_status);
4392 /* Get VEB bandwidth, to be implemented */
4393 /* Now associated vsi binding to the VEB, set uplink to this VEB */
4395 vsi->uplink_seid = veb->seid;
4404 i40e_vsi_release(struct i40e_vsi *vsi)
4408 struct i40e_vsi_list *vsi_list;
4411 struct i40e_mac_filter *f;
4412 uint16_t user_param;
4415 return I40E_SUCCESS;
4420 user_param = vsi->user_param;
4422 pf = I40E_VSI_TO_PF(vsi);
4423 hw = I40E_VSI_TO_HW(vsi);
4425 /* VSI has child to attach, release child first */
4427 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4428 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4431 i40e_veb_release(vsi->veb);
4434 if (vsi->floating_veb) {
4435 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4436 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4441 /* Remove all macvlan filters of the VSI */
4442 i40e_vsi_remove_all_macvlan_filter(vsi);
4443 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4446 if (vsi->type != I40E_VSI_MAIN &&
4447 ((vsi->type != I40E_VSI_SRIOV) ||
4448 !pf->floating_veb_list[user_param])) {
4449 /* Remove vsi from parent's sibling list */
4450 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4451 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4452 return I40E_ERR_PARAM;
4454 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4455 &vsi->sib_vsi_list, list);
4457 /* Remove all switch element of the VSI */
4458 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4459 if (ret != I40E_SUCCESS)
4460 PMD_DRV_LOG(ERR, "Failed to delete element");
4463 if ((vsi->type == I40E_VSI_SRIOV) &&
4464 pf->floating_veb_list[user_param]) {
4465 /* Remove vsi from parent's sibling list */
4466 if (vsi->parent_vsi == NULL ||
4467 vsi->parent_vsi->floating_veb == NULL) {
4468 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4469 return I40E_ERR_PARAM;
4471 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4472 &vsi->sib_vsi_list, list);
4474 /* Remove all switch element of the VSI */
4475 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4476 if (ret != I40E_SUCCESS)
4477 PMD_DRV_LOG(ERR, "Failed to delete element");
4480 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4482 if (vsi->type != I40E_VSI_SRIOV)
4483 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4486 return I40E_SUCCESS;
4490 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4492 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4493 struct i40e_aqc_remove_macvlan_element_data def_filter;
4494 struct i40e_mac_filter_info filter;
4497 if (vsi->type != I40E_VSI_MAIN)
4498 return I40E_ERR_CONFIG;
4499 memset(&def_filter, 0, sizeof(def_filter));
4500 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4502 def_filter.vlan_tag = 0;
4503 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4504 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4505 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4506 if (ret != I40E_SUCCESS) {
4507 struct i40e_mac_filter *f;
4508 struct ether_addr *mac;
4510 PMD_DRV_LOG(WARNING,
4511 "Cannot remove the default macvlan filter");
4512 /* It needs to add the permanent mac into mac list */
4513 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4515 PMD_DRV_LOG(ERR, "failed to allocate memory");
4516 return I40E_ERR_NO_MEMORY;
4518 mac = &f->mac_info.mac_addr;
4519 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4521 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4522 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4527 (void)rte_memcpy(&filter.mac_addr,
4528 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4529 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4530 return i40e_vsi_add_mac(vsi, &filter);
4534 * i40e_vsi_get_bw_config - Query VSI BW Information
4535 * @vsi: the VSI to be queried
4537 * Returns 0 on success, negative value on failure
4539 static enum i40e_status_code
4540 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4542 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4543 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4544 struct i40e_hw *hw = &vsi->adapter->hw;
4549 memset(&bw_config, 0, sizeof(bw_config));
4550 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4551 if (ret != I40E_SUCCESS) {
4552 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4553 hw->aq.asq_last_status);
4557 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4558 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4559 &ets_sla_config, NULL);
4560 if (ret != I40E_SUCCESS) {
4562 "VSI failed to get TC bandwdith configuration %u",
4563 hw->aq.asq_last_status);
4567 /* store and print out BW info */
4568 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4569 vsi->bw_info.bw_max = bw_config.max_bw;
4570 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4571 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4572 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4573 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4575 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4576 vsi->bw_info.bw_ets_share_credits[i] =
4577 ets_sla_config.share_credits[i];
4578 vsi->bw_info.bw_ets_credits[i] =
4579 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4580 /* 4 bits per TC, 4th bit is reserved */
4581 vsi->bw_info.bw_ets_max[i] =
4582 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4583 RTE_LEN2MASK(3, uint8_t));
4584 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4585 vsi->bw_info.bw_ets_share_credits[i]);
4586 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4587 vsi->bw_info.bw_ets_credits[i]);
4588 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4589 vsi->bw_info.bw_ets_max[i]);
4592 return I40E_SUCCESS;
4595 /* i40e_enable_pf_lb
4596 * @pf: pointer to the pf structure
4598 * allow loopback on pf
4601 i40e_enable_pf_lb(struct i40e_pf *pf)
4603 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4604 struct i40e_vsi_context ctxt;
4607 /* Use the FW API if FW >= v5.0 */
4608 if (hw->aq.fw_maj_ver < 5) {
4609 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4613 memset(&ctxt, 0, sizeof(ctxt));
4614 ctxt.seid = pf->main_vsi_seid;
4615 ctxt.pf_num = hw->pf_id;
4616 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4618 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4619 ret, hw->aq.asq_last_status);
4622 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4623 ctxt.info.valid_sections =
4624 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4625 ctxt.info.switch_id |=
4626 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4628 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4630 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4631 hw->aq.asq_last_status);
4636 i40e_vsi_setup(struct i40e_pf *pf,
4637 enum i40e_vsi_type type,
4638 struct i40e_vsi *uplink_vsi,
4639 uint16_t user_param)
4641 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4642 struct i40e_vsi *vsi;
4643 struct i40e_mac_filter_info filter;
4645 struct i40e_vsi_context ctxt;
4646 struct ether_addr broadcast =
4647 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4649 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4650 uplink_vsi == NULL) {
4652 "VSI setup failed, VSI link shouldn't be NULL");
4656 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4658 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4663 * 1.type is not MAIN and uplink vsi is not NULL
4664 * If uplink vsi didn't setup VEB, create one first under veb field
4665 * 2.type is SRIOV and the uplink is NULL
4666 * If floating VEB is NULL, create one veb under floating veb field
4669 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4670 uplink_vsi->veb == NULL) {
4671 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4673 if (uplink_vsi->veb == NULL) {
4674 PMD_DRV_LOG(ERR, "VEB setup failed");
4677 /* set ALLOWLOOPBACk on pf, when veb is created */
4678 i40e_enable_pf_lb(pf);
4681 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4682 pf->main_vsi->floating_veb == NULL) {
4683 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4685 if (pf->main_vsi->floating_veb == NULL) {
4686 PMD_DRV_LOG(ERR, "VEB setup failed");
4691 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4693 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4696 TAILQ_INIT(&vsi->mac_list);
4698 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4699 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4700 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4701 vsi->user_param = user_param;
4702 vsi->vlan_anti_spoof_on = 0;
4703 vsi->vlan_filter_on = 0;
4704 /* Allocate queues */
4705 switch (vsi->type) {
4706 case I40E_VSI_MAIN :
4707 vsi->nb_qps = pf->lan_nb_qps;
4709 case I40E_VSI_SRIOV :
4710 vsi->nb_qps = pf->vf_nb_qps;
4712 case I40E_VSI_VMDQ2:
4713 vsi->nb_qps = pf->vmdq_nb_qps;
4716 vsi->nb_qps = pf->fdir_nb_qps;
4722 * The filter status descriptor is reported in rx queue 0,
4723 * while the tx queue for fdir filter programming has no
4724 * such constraints, can be non-zero queues.
4725 * To simplify it, choose FDIR vsi use queue 0 pair.
4726 * To make sure it will use queue 0 pair, queue allocation
4727 * need be done before this function is called
4729 if (type != I40E_VSI_FDIR) {
4730 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4732 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4736 vsi->base_queue = ret;
4738 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4740 /* VF has MSIX interrupt in VF range, don't allocate here */
4741 if (type == I40E_VSI_MAIN) {
4742 ret = i40e_res_pool_alloc(&pf->msix_pool,
4743 RTE_MIN(vsi->nb_qps,
4744 RTE_MAX_RXTX_INTR_VEC_ID));
4746 PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4748 goto fail_queue_alloc;
4750 vsi->msix_intr = ret;
4751 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4752 } else if (type != I40E_VSI_SRIOV) {
4753 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4755 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4756 goto fail_queue_alloc;
4758 vsi->msix_intr = ret;
4766 if (type == I40E_VSI_MAIN) {
4767 /* For main VSI, no need to add since it's default one */
4768 vsi->uplink_seid = pf->mac_seid;
4769 vsi->seid = pf->main_vsi_seid;
4770 /* Bind queues with specific MSIX interrupt */
4772 * Needs 2 interrupt at least, one for misc cause which will
4773 * enabled from OS side, Another for queues binding the
4774 * interrupt from device side only.
4777 /* Get default VSI parameters from hardware */
4778 memset(&ctxt, 0, sizeof(ctxt));
4779 ctxt.seid = vsi->seid;
4780 ctxt.pf_num = hw->pf_id;
4781 ctxt.uplink_seid = vsi->uplink_seid;
4783 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4784 if (ret != I40E_SUCCESS) {
4785 PMD_DRV_LOG(ERR, "Failed to get VSI params");
4786 goto fail_msix_alloc;
4788 (void)rte_memcpy(&vsi->info, &ctxt.info,
4789 sizeof(struct i40e_aqc_vsi_properties_data));
4790 vsi->vsi_id = ctxt.vsi_number;
4791 vsi->info.valid_sections = 0;
4793 /* Configure tc, enabled TC0 only */
4794 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4796 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4797 goto fail_msix_alloc;
4800 /* TC, queue mapping */
4801 memset(&ctxt, 0, sizeof(ctxt));
4802 vsi->info.valid_sections |=
4803 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4804 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4805 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4806 (void)rte_memcpy(&ctxt.info, &vsi->info,
4807 sizeof(struct i40e_aqc_vsi_properties_data));
4808 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4809 I40E_DEFAULT_TCMAP);
4810 if (ret != I40E_SUCCESS) {
4812 "Failed to configure TC queue mapping");
4813 goto fail_msix_alloc;
4815 ctxt.seid = vsi->seid;
4816 ctxt.pf_num = hw->pf_id;
4817 ctxt.uplink_seid = vsi->uplink_seid;
4820 /* Update VSI parameters */
4821 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4822 if (ret != I40E_SUCCESS) {
4823 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4824 goto fail_msix_alloc;
4827 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4828 sizeof(vsi->info.tc_mapping));
4829 (void)rte_memcpy(&vsi->info.queue_mapping,
4830 &ctxt.info.queue_mapping,
4831 sizeof(vsi->info.queue_mapping));
4832 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4833 vsi->info.valid_sections = 0;
4835 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4839 * Updating default filter settings are necessary to prevent
4840 * reception of tagged packets.
4841 * Some old firmware configurations load a default macvlan
4842 * filter which accepts both tagged and untagged packets.
4843 * The updating is to use a normal filter instead if needed.
4844 * For NVM 4.2.2 or after, the updating is not needed anymore.
4845 * The firmware with correct configurations load the default
4846 * macvlan filter which is expected and cannot be removed.
4848 i40e_update_default_filter_setting(vsi);
4849 i40e_config_qinq(hw, vsi);
4850 } else if (type == I40E_VSI_SRIOV) {
4851 memset(&ctxt, 0, sizeof(ctxt));
4853 * For other VSI, the uplink_seid equals to uplink VSI's
4854 * uplink_seid since they share same VEB
4856 if (uplink_vsi == NULL)
4857 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4859 vsi->uplink_seid = uplink_vsi->uplink_seid;
4860 ctxt.pf_num = hw->pf_id;
4861 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4862 ctxt.uplink_seid = vsi->uplink_seid;
4863 ctxt.connection_type = 0x1;
4864 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4866 /* Use the VEB configuration if FW >= v5.0 */
4867 if (hw->aq.fw_maj_ver >= 5) {
4868 /* Configure switch ID */
4869 ctxt.info.valid_sections |=
4870 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4871 ctxt.info.switch_id =
4872 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4875 /* Configure port/vlan */
4876 ctxt.info.valid_sections |=
4877 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4878 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4879 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4880 hw->func_caps.enabled_tcmap);
4881 if (ret != I40E_SUCCESS) {
4883 "Failed to configure TC queue mapping");
4884 goto fail_msix_alloc;
4887 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
4888 ctxt.info.valid_sections |=
4889 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4891 * Since VSI is not created yet, only configure parameter,
4892 * will add vsi below.
4895 i40e_config_qinq(hw, vsi);
4896 } else if (type == I40E_VSI_VMDQ2) {
4897 memset(&ctxt, 0, sizeof(ctxt));
4899 * For other VSI, the uplink_seid equals to uplink VSI's
4900 * uplink_seid since they share same VEB
4902 vsi->uplink_seid = uplink_vsi->uplink_seid;
4903 ctxt.pf_num = hw->pf_id;
4905 ctxt.uplink_seid = vsi->uplink_seid;
4906 ctxt.connection_type = 0x1;
4907 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4909 ctxt.info.valid_sections |=
4910 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4911 /* user_param carries flag to enable loop back */
4913 ctxt.info.switch_id =
4914 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4915 ctxt.info.switch_id |=
4916 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4919 /* Configure port/vlan */
4920 ctxt.info.valid_sections |=
4921 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4922 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4923 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4924 I40E_DEFAULT_TCMAP);
4925 if (ret != I40E_SUCCESS) {
4927 "Failed to configure TC queue mapping");
4928 goto fail_msix_alloc;
4930 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4931 ctxt.info.valid_sections |=
4932 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4933 } else if (type == I40E_VSI_FDIR) {
4934 memset(&ctxt, 0, sizeof(ctxt));
4935 vsi->uplink_seid = uplink_vsi->uplink_seid;
4936 ctxt.pf_num = hw->pf_id;
4938 ctxt.uplink_seid = vsi->uplink_seid;
4939 ctxt.connection_type = 0x1; /* regular data port */
4940 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4941 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4942 I40E_DEFAULT_TCMAP);
4943 if (ret != I40E_SUCCESS) {
4945 "Failed to configure TC queue mapping.");
4946 goto fail_msix_alloc;
4948 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4949 ctxt.info.valid_sections |=
4950 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4952 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4953 goto fail_msix_alloc;
4956 if (vsi->type != I40E_VSI_MAIN) {
4957 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4958 if (ret != I40E_SUCCESS) {
4959 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4960 hw->aq.asq_last_status);
4961 goto fail_msix_alloc;
4963 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4964 vsi->info.valid_sections = 0;
4965 vsi->seid = ctxt.seid;
4966 vsi->vsi_id = ctxt.vsi_number;
4967 vsi->sib_vsi_list.vsi = vsi;
4968 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4969 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4970 &vsi->sib_vsi_list, list);
4972 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4973 &vsi->sib_vsi_list, list);
4977 /* MAC/VLAN configuration */
4978 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4979 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4981 ret = i40e_vsi_add_mac(vsi, &filter);
4982 if (ret != I40E_SUCCESS) {
4983 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4984 goto fail_msix_alloc;
4987 /* Get VSI BW information */
4988 i40e_vsi_get_bw_config(vsi);
4991 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4993 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4999 /* Configure vlan filter on or off */
5001 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5004 struct i40e_mac_filter *f;
5006 struct i40e_mac_filter_info *mac_filter;
5007 enum rte_mac_filter_type desired_filter;
5008 int ret = I40E_SUCCESS;
5011 /* Filter to match MAC and VLAN */
5012 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5014 /* Filter to match only MAC */
5015 desired_filter = RTE_MAC_PERFECT_MATCH;
5020 mac_filter = rte_zmalloc("mac_filter_info_data",
5021 num * sizeof(*mac_filter), 0);
5022 if (mac_filter == NULL) {
5023 PMD_DRV_LOG(ERR, "failed to allocate memory");
5024 return I40E_ERR_NO_MEMORY;
5029 /* Remove all existing mac */
5030 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5031 mac_filter[i] = f->mac_info;
5032 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5034 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5035 on ? "enable" : "disable");
5041 /* Override with new filter */
5042 for (i = 0; i < num; i++) {
5043 mac_filter[i].filter_type = desired_filter;
5044 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5046 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5047 on ? "enable" : "disable");
5053 rte_free(mac_filter);
5057 /* Configure vlan stripping on or off */
5059 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5061 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5062 struct i40e_vsi_context ctxt;
5064 int ret = I40E_SUCCESS;
5066 /* Check if it has been already on or off */
5067 if (vsi->info.valid_sections &
5068 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5070 if ((vsi->info.port_vlan_flags &
5071 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5072 return 0; /* already on */
5074 if ((vsi->info.port_vlan_flags &
5075 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5076 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5077 return 0; /* already off */
5082 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5084 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5085 vsi->info.valid_sections =
5086 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5087 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5088 vsi->info.port_vlan_flags |= vlan_flags;
5089 ctxt.seid = vsi->seid;
5090 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5091 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5093 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5094 on ? "enable" : "disable");
5100 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5102 struct rte_eth_dev_data *data = dev->data;
5106 /* Apply vlan offload setting */
5107 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5108 i40e_vlan_offload_set(dev, mask);
5110 /* Apply double-vlan setting, not implemented yet */
5112 /* Apply pvid setting */
5113 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5114 data->dev_conf.txmode.hw_vlan_insert_pvid);
5116 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5122 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5124 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5126 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5130 i40e_update_flow_control(struct i40e_hw *hw)
5132 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5133 struct i40e_link_status link_status;
5134 uint32_t rxfc = 0, txfc = 0, reg;
5138 memset(&link_status, 0, sizeof(link_status));
5139 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5140 if (ret != I40E_SUCCESS) {
5141 PMD_DRV_LOG(ERR, "Failed to get link status information");
5142 goto write_reg; /* Disable flow control */
5145 an_info = hw->phy.link_info.an_info;
5146 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5147 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5148 ret = I40E_ERR_NOT_READY;
5149 goto write_reg; /* Disable flow control */
5152 * If link auto negotiation is enabled, flow control needs to
5153 * be configured according to it
5155 switch (an_info & I40E_LINK_PAUSE_RXTX) {
5156 case I40E_LINK_PAUSE_RXTX:
5159 hw->fc.current_mode = I40E_FC_FULL;
5161 case I40E_AQ_LINK_PAUSE_RX:
5163 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5165 case I40E_AQ_LINK_PAUSE_TX:
5167 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5170 hw->fc.current_mode = I40E_FC_NONE;
5175 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5176 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5177 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5178 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5179 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5180 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5187 i40e_pf_setup(struct i40e_pf *pf)
5189 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5190 struct i40e_filter_control_settings settings;
5191 struct i40e_vsi *vsi;
5194 /* Clear all stats counters */
5195 pf->offset_loaded = FALSE;
5196 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5197 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5199 ret = i40e_pf_get_switch_config(pf);
5200 if (ret != I40E_SUCCESS) {
5201 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5204 if (pf->flags & I40E_FLAG_FDIR) {
5205 /* make queue allocated first, let FDIR use queue pair 0*/
5206 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5207 if (ret != I40E_FDIR_QUEUE_ID) {
5209 "queue allocation fails for FDIR: ret =%d",
5211 pf->flags &= ~I40E_FLAG_FDIR;
5214 /* main VSI setup */
5215 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5217 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5218 return I40E_ERR_NOT_READY;
5222 /* Configure filter control */
5223 memset(&settings, 0, sizeof(settings));
5224 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5225 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5226 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5227 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5229 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5230 hw->func_caps.rss_table_size);
5231 return I40E_ERR_PARAM;
5233 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5234 hw->func_caps.rss_table_size);
5235 pf->hash_lut_size = hw->func_caps.rss_table_size;
5237 /* Enable ethtype and macvlan filters */
5238 settings.enable_ethtype = TRUE;
5239 settings.enable_macvlan = TRUE;
5240 ret = i40e_set_filter_control(hw, &settings);
5242 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5245 /* Update flow control according to the auto negotiation */
5246 i40e_update_flow_control(hw);
5248 return I40E_SUCCESS;
5252 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5258 * Set or clear TX Queue Disable flags,
5259 * which is required by hardware.
5261 i40e_pre_tx_queue_cfg(hw, q_idx, on);
5262 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5264 /* Wait until the request is finished */
5265 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5266 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5267 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5268 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5269 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5275 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5276 return I40E_SUCCESS; /* already on, skip next steps */
5278 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5279 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5281 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5282 return I40E_SUCCESS; /* already off, skip next steps */
5283 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5285 /* Write the register */
5286 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5287 /* Check the result */
5288 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5289 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5290 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5292 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5293 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5296 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5297 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5301 /* Check if it is timeout */
5302 if (j >= I40E_CHK_Q_ENA_COUNT) {
5303 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5304 (on ? "enable" : "disable"), q_idx);
5305 return I40E_ERR_TIMEOUT;
5308 return I40E_SUCCESS;
5311 /* Swith on or off the tx queues */
5313 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5315 struct rte_eth_dev_data *dev_data = pf->dev_data;
5316 struct i40e_tx_queue *txq;
5317 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5321 for (i = 0; i < dev_data->nb_tx_queues; i++) {
5322 txq = dev_data->tx_queues[i];
5323 /* Don't operate the queue if not configured or
5324 * if starting only per queue */
5325 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5328 ret = i40e_dev_tx_queue_start(dev, i);
5330 ret = i40e_dev_tx_queue_stop(dev, i);
5331 if ( ret != I40E_SUCCESS)
5335 return I40E_SUCCESS;
5339 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5344 /* Wait until the request is finished */
5345 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5346 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5347 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5348 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5349 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5354 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5355 return I40E_SUCCESS; /* Already on, skip next steps */
5356 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5358 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5359 return I40E_SUCCESS; /* Already off, skip next steps */
5360 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5363 /* Write the register */
5364 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5365 /* Check the result */
5366 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5367 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5368 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5370 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5371 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5374 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5375 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5380 /* Check if it is timeout */
5381 if (j >= I40E_CHK_Q_ENA_COUNT) {
5382 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5383 (on ? "enable" : "disable"), q_idx);
5384 return I40E_ERR_TIMEOUT;
5387 return I40E_SUCCESS;
5389 /* Switch on or off the rx queues */
5391 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5393 struct rte_eth_dev_data *dev_data = pf->dev_data;
5394 struct i40e_rx_queue *rxq;
5395 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5399 for (i = 0; i < dev_data->nb_rx_queues; i++) {
5400 rxq = dev_data->rx_queues[i];
5401 /* Don't operate the queue if not configured or
5402 * if starting only per queue */
5403 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5406 ret = i40e_dev_rx_queue_start(dev, i);
5408 ret = i40e_dev_rx_queue_stop(dev, i);
5409 if (ret != I40E_SUCCESS)
5413 return I40E_SUCCESS;
5416 /* Switch on or off all the rx/tx queues */
5418 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5423 /* enable rx queues before enabling tx queues */
5424 ret = i40e_dev_switch_rx_queues(pf, on);
5426 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5429 ret = i40e_dev_switch_tx_queues(pf, on);
5431 /* Stop tx queues before stopping rx queues */
5432 ret = i40e_dev_switch_tx_queues(pf, on);
5434 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5437 ret = i40e_dev_switch_rx_queues(pf, on);
5443 /* Initialize VSI for TX */
5445 i40e_dev_tx_init(struct i40e_pf *pf)
5447 struct rte_eth_dev_data *data = pf->dev_data;
5449 uint32_t ret = I40E_SUCCESS;
5450 struct i40e_tx_queue *txq;
5452 for (i = 0; i < data->nb_tx_queues; i++) {
5453 txq = data->tx_queues[i];
5454 if (!txq || !txq->q_set)
5456 ret = i40e_tx_queue_init(txq);
5457 if (ret != I40E_SUCCESS)
5460 if (ret == I40E_SUCCESS)
5461 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5467 /* Initialize VSI for RX */
5469 i40e_dev_rx_init(struct i40e_pf *pf)
5471 struct rte_eth_dev_data *data = pf->dev_data;
5472 int ret = I40E_SUCCESS;
5474 struct i40e_rx_queue *rxq;
5476 i40e_pf_config_mq_rx(pf);
5477 for (i = 0; i < data->nb_rx_queues; i++) {
5478 rxq = data->rx_queues[i];
5479 if (!rxq || !rxq->q_set)
5482 ret = i40e_rx_queue_init(rxq);
5483 if (ret != I40E_SUCCESS) {
5485 "Failed to do RX queue initialization");
5489 if (ret == I40E_SUCCESS)
5490 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5497 i40e_dev_rxtx_init(struct i40e_pf *pf)
5501 err = i40e_dev_tx_init(pf);
5503 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5506 err = i40e_dev_rx_init(pf);
5508 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5516 i40e_vmdq_setup(struct rte_eth_dev *dev)
5518 struct rte_eth_conf *conf = &dev->data->dev_conf;
5519 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5520 int i, err, conf_vsis, j, loop;
5521 struct i40e_vsi *vsi;
5522 struct i40e_vmdq_info *vmdq_info;
5523 struct rte_eth_vmdq_rx_conf *vmdq_conf;
5524 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5527 * Disable interrupt to avoid message from VF. Furthermore, it will
5528 * avoid race condition in VSI creation/destroy.
5530 i40e_pf_disable_irq0(hw);
5532 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5533 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5537 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5538 if (conf_vsis > pf->max_nb_vmdq_vsi) {
5539 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5540 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5541 pf->max_nb_vmdq_vsi);
5545 if (pf->vmdq != NULL) {
5546 PMD_INIT_LOG(INFO, "VMDQ already configured");
5550 pf->vmdq = rte_zmalloc("vmdq_info_struct",
5551 sizeof(*vmdq_info) * conf_vsis, 0);
5553 if (pf->vmdq == NULL) {
5554 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5558 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5560 /* Create VMDQ VSI */
5561 for (i = 0; i < conf_vsis; i++) {
5562 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5563 vmdq_conf->enable_loop_back);
5565 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5569 vmdq_info = &pf->vmdq[i];
5571 vmdq_info->vsi = vsi;
5573 pf->nb_cfg_vmdq_vsi = conf_vsis;
5575 /* Configure Vlan */
5576 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5577 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5578 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5579 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5580 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5581 vmdq_conf->pool_map[i].vlan_id, j);
5583 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5584 vmdq_conf->pool_map[i].vlan_id);
5586 PMD_INIT_LOG(ERR, "Failed to add vlan");
5594 i40e_pf_enable_irq0(hw);
5599 for (i = 0; i < conf_vsis; i++)
5600 if (pf->vmdq[i].vsi == NULL)
5603 i40e_vsi_release(pf->vmdq[i].vsi);
5607 i40e_pf_enable_irq0(hw);
5612 i40e_stat_update_32(struct i40e_hw *hw,
5620 new_data = (uint64_t)I40E_READ_REG(hw, reg);
5624 if (new_data >= *offset)
5625 *stat = (uint64_t)(new_data - *offset);
5627 *stat = (uint64_t)((new_data +
5628 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5632 i40e_stat_update_48(struct i40e_hw *hw,
5641 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5642 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5643 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5648 if (new_data >= *offset)
5649 *stat = new_data - *offset;
5651 *stat = (uint64_t)((new_data +
5652 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5654 *stat &= I40E_48_BIT_MASK;
5659 i40e_pf_disable_irq0(struct i40e_hw *hw)
5661 /* Disable all interrupt types */
5662 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5663 I40E_WRITE_FLUSH(hw);
5668 i40e_pf_enable_irq0(struct i40e_hw *hw)
5670 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5671 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5672 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5673 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5674 I40E_WRITE_FLUSH(hw);
5678 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5680 /* read pending request and disable first */
5681 i40e_pf_disable_irq0(hw);
5682 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5683 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5684 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5687 /* Link no queues with irq0 */
5688 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5689 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5693 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5695 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5696 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5699 uint32_t index, offset, val;
5704 * Try to find which VF trigger a reset, use absolute VF id to access
5705 * since the reg is global register.
5707 for (i = 0; i < pf->vf_num; i++) {
5708 abs_vf_id = hw->func_caps.vf_base_id + i;
5709 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5710 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5711 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5712 /* VFR event occured */
5713 if (val & (0x1 << offset)) {
5716 /* Clear the event first */
5717 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5719 PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5721 * Only notify a VF reset event occured,
5722 * don't trigger another SW reset
5724 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5725 if (ret != I40E_SUCCESS)
5726 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5732 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5734 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5737 for (i = 0; i < pf->vf_num; i++)
5738 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
5742 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5744 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5745 struct i40e_arq_event_info info;
5746 uint16_t pending, opcode;
5749 info.buf_len = I40E_AQ_BUF_SZ;
5750 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5751 if (!info.msg_buf) {
5752 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5758 ret = i40e_clean_arq_element(hw, &info, &pending);
5760 if (ret != I40E_SUCCESS) {
5762 "Failed to read msg from AdminQ, aq_err: %u",
5763 hw->aq.asq_last_status);
5766 opcode = rte_le_to_cpu_16(info.desc.opcode);
5769 case i40e_aqc_opc_send_msg_to_pf:
5770 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5771 i40e_pf_host_handle_vf_msg(dev,
5772 rte_le_to_cpu_16(info.desc.retval),
5773 rte_le_to_cpu_32(info.desc.cookie_high),
5774 rte_le_to_cpu_32(info.desc.cookie_low),
5778 case i40e_aqc_opc_get_link_status:
5779 ret = i40e_dev_link_update(dev, 0);
5781 _rte_eth_dev_callback_process(dev,
5782 RTE_ETH_EVENT_INTR_LSC, NULL);
5785 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5790 rte_free(info.msg_buf);
5794 * Interrupt handler triggered by NIC for handling
5795 * specific interrupt.
5798 * Pointer to interrupt handle.
5800 * The address of parameter (struct rte_eth_dev *) regsitered before.
5806 i40e_dev_interrupt_handler(void *param)
5808 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5809 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5812 /* Disable interrupt */
5813 i40e_pf_disable_irq0(hw);
5815 /* read out interrupt causes */
5816 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5818 /* No interrupt event indicated */
5819 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5820 PMD_DRV_LOG(INFO, "No interrupt event");
5823 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5824 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5825 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5826 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5827 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5828 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5829 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5830 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5831 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5832 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5833 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5834 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5835 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5836 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5838 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5839 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5840 i40e_dev_handle_vfr_event(dev);
5842 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5843 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5844 i40e_dev_handle_aq_msg(dev);
5848 /* Enable interrupt */
5849 i40e_pf_enable_irq0(hw);
5850 rte_intr_enable(dev->intr_handle);
5854 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5855 struct i40e_macvlan_filter *filter,
5858 int ele_num, ele_buff_size;
5859 int num, actual_num, i;
5861 int ret = I40E_SUCCESS;
5862 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5863 struct i40e_aqc_add_macvlan_element_data *req_list;
5865 if (filter == NULL || total == 0)
5866 return I40E_ERR_PARAM;
5867 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5868 ele_buff_size = hw->aq.asq_buf_size;
5870 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5871 if (req_list == NULL) {
5872 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5873 return I40E_ERR_NO_MEMORY;
5878 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5879 memset(req_list, 0, ele_buff_size);
5881 for (i = 0; i < actual_num; i++) {
5882 (void)rte_memcpy(req_list[i].mac_addr,
5883 &filter[num + i].macaddr, ETH_ADDR_LEN);
5884 req_list[i].vlan_tag =
5885 rte_cpu_to_le_16(filter[num + i].vlan_id);
5887 switch (filter[num + i].filter_type) {
5888 case RTE_MAC_PERFECT_MATCH:
5889 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5890 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5892 case RTE_MACVLAN_PERFECT_MATCH:
5893 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5895 case RTE_MAC_HASH_MATCH:
5896 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5897 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5899 case RTE_MACVLAN_HASH_MATCH:
5900 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5903 PMD_DRV_LOG(ERR, "Invalid MAC match type");
5904 ret = I40E_ERR_PARAM;
5908 req_list[i].queue_number = 0;
5910 req_list[i].flags = rte_cpu_to_le_16(flags);
5913 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5915 if (ret != I40E_SUCCESS) {
5916 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5920 } while (num < total);
5928 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5929 struct i40e_macvlan_filter *filter,
5932 int ele_num, ele_buff_size;
5933 int num, actual_num, i;
5935 int ret = I40E_SUCCESS;
5936 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5937 struct i40e_aqc_remove_macvlan_element_data *req_list;
5939 if (filter == NULL || total == 0)
5940 return I40E_ERR_PARAM;
5942 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5943 ele_buff_size = hw->aq.asq_buf_size;
5945 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5946 if (req_list == NULL) {
5947 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5948 return I40E_ERR_NO_MEMORY;
5953 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5954 memset(req_list, 0, ele_buff_size);
5956 for (i = 0; i < actual_num; i++) {
5957 (void)rte_memcpy(req_list[i].mac_addr,
5958 &filter[num + i].macaddr, ETH_ADDR_LEN);
5959 req_list[i].vlan_tag =
5960 rte_cpu_to_le_16(filter[num + i].vlan_id);
5962 switch (filter[num + i].filter_type) {
5963 case RTE_MAC_PERFECT_MATCH:
5964 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5965 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5967 case RTE_MACVLAN_PERFECT_MATCH:
5968 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5970 case RTE_MAC_HASH_MATCH:
5971 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5972 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5974 case RTE_MACVLAN_HASH_MATCH:
5975 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5978 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
5979 ret = I40E_ERR_PARAM;
5982 req_list[i].flags = rte_cpu_to_le_16(flags);
5985 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5987 if (ret != I40E_SUCCESS) {
5988 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5992 } while (num < total);
5999 /* Find out specific MAC filter */
6000 static struct i40e_mac_filter *
6001 i40e_find_mac_filter(struct i40e_vsi *vsi,
6002 struct ether_addr *macaddr)
6004 struct i40e_mac_filter *f;
6006 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6007 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6015 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6018 uint32_t vid_idx, vid_bit;
6020 if (vlan_id > ETH_VLAN_ID_MAX)
6023 vid_idx = I40E_VFTA_IDX(vlan_id);
6024 vid_bit = I40E_VFTA_BIT(vlan_id);
6026 if (vsi->vfta[vid_idx] & vid_bit)
6033 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6034 uint16_t vlan_id, bool on)
6036 uint32_t vid_idx, vid_bit;
6038 vid_idx = I40E_VFTA_IDX(vlan_id);
6039 vid_bit = I40E_VFTA_BIT(vlan_id);
6042 vsi->vfta[vid_idx] |= vid_bit;
6044 vsi->vfta[vid_idx] &= ~vid_bit;
6048 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6049 uint16_t vlan_id, bool on)
6051 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6052 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6055 if (vlan_id > ETH_VLAN_ID_MAX)
6058 i40e_store_vlan_filter(vsi, vlan_id, on);
6060 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6063 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6066 ret = i40e_aq_add_vlan(hw, vsi->seid,
6067 &vlan_data, 1, NULL);
6068 if (ret != I40E_SUCCESS)
6069 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6071 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6072 &vlan_data, 1, NULL);
6073 if (ret != I40E_SUCCESS)
6075 "Failed to remove vlan filter");
6080 * Find all vlan options for specific mac addr,
6081 * return with actual vlan found.
6084 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6085 struct i40e_macvlan_filter *mv_f,
6086 int num, struct ether_addr *addr)
6092 * Not to use i40e_find_vlan_filter to decrease the loop time,
6093 * although the code looks complex.
6095 if (num < vsi->vlan_num)
6096 return I40E_ERR_PARAM;
6099 for (j = 0; j < I40E_VFTA_SIZE; j++) {
6101 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6102 if (vsi->vfta[j] & (1 << k)) {
6105 "vlan number doesn't match");
6106 return I40E_ERR_PARAM;
6108 (void)rte_memcpy(&mv_f[i].macaddr,
6109 addr, ETH_ADDR_LEN);
6111 j * I40E_UINT32_BIT_SIZE + k;
6117 return I40E_SUCCESS;
6121 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6122 struct i40e_macvlan_filter *mv_f,
6127 struct i40e_mac_filter *f;
6129 if (num < vsi->mac_num)
6130 return I40E_ERR_PARAM;
6132 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6134 PMD_DRV_LOG(ERR, "buffer number not match");
6135 return I40E_ERR_PARAM;
6137 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6139 mv_f[i].vlan_id = vlan;
6140 mv_f[i].filter_type = f->mac_info.filter_type;
6144 return I40E_SUCCESS;
6148 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6151 struct i40e_mac_filter *f;
6152 struct i40e_macvlan_filter *mv_f;
6153 int ret = I40E_SUCCESS;
6155 if (vsi == NULL || vsi->mac_num == 0)
6156 return I40E_ERR_PARAM;
6158 /* Case that no vlan is set */
6159 if (vsi->vlan_num == 0)
6162 num = vsi->mac_num * vsi->vlan_num;
6164 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6166 PMD_DRV_LOG(ERR, "failed to allocate memory");
6167 return I40E_ERR_NO_MEMORY;
6171 if (vsi->vlan_num == 0) {
6172 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6173 (void)rte_memcpy(&mv_f[i].macaddr,
6174 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6175 mv_f[i].filter_type = f->mac_info.filter_type;
6176 mv_f[i].vlan_id = 0;
6180 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6181 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6182 vsi->vlan_num, &f->mac_info.mac_addr);
6183 if (ret != I40E_SUCCESS)
6185 for (j = i; j < i + vsi->vlan_num; j++)
6186 mv_f[j].filter_type = f->mac_info.filter_type;
6191 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6199 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6201 struct i40e_macvlan_filter *mv_f;
6203 int ret = I40E_SUCCESS;
6205 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6206 return I40E_ERR_PARAM;
6208 /* If it's already set, just return */
6209 if (i40e_find_vlan_filter(vsi,vlan))
6210 return I40E_SUCCESS;
6212 mac_num = vsi->mac_num;
6215 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6216 return I40E_ERR_PARAM;
6219 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6222 PMD_DRV_LOG(ERR, "failed to allocate memory");
6223 return I40E_ERR_NO_MEMORY;
6226 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6228 if (ret != I40E_SUCCESS)
6231 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6233 if (ret != I40E_SUCCESS)
6236 i40e_set_vlan_filter(vsi, vlan, 1);
6246 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6248 struct i40e_macvlan_filter *mv_f;
6250 int ret = I40E_SUCCESS;
6253 * Vlan 0 is the generic filter for untagged packets
6254 * and can't be removed.
6256 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6257 return I40E_ERR_PARAM;
6259 /* If can't find it, just return */
6260 if (!i40e_find_vlan_filter(vsi, vlan))
6261 return I40E_ERR_PARAM;
6263 mac_num = vsi->mac_num;
6266 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6267 return I40E_ERR_PARAM;
6270 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6273 PMD_DRV_LOG(ERR, "failed to allocate memory");
6274 return I40E_ERR_NO_MEMORY;
6277 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6279 if (ret != I40E_SUCCESS)
6282 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6284 if (ret != I40E_SUCCESS)
6287 /* This is last vlan to remove, replace all mac filter with vlan 0 */
6288 if (vsi->vlan_num == 1) {
6289 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6290 if (ret != I40E_SUCCESS)
6293 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6294 if (ret != I40E_SUCCESS)
6298 i40e_set_vlan_filter(vsi, vlan, 0);
6308 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6310 struct i40e_mac_filter *f;
6311 struct i40e_macvlan_filter *mv_f;
6312 int i, vlan_num = 0;
6313 int ret = I40E_SUCCESS;
6315 /* If it's add and we've config it, return */
6316 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6318 return I40E_SUCCESS;
6319 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6320 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6323 * If vlan_num is 0, that's the first time to add mac,
6324 * set mask for vlan_id 0.
6326 if (vsi->vlan_num == 0) {
6327 i40e_set_vlan_filter(vsi, 0, 1);
6330 vlan_num = vsi->vlan_num;
6331 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6332 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6335 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6337 PMD_DRV_LOG(ERR, "failed to allocate memory");
6338 return I40E_ERR_NO_MEMORY;
6341 for (i = 0; i < vlan_num; i++) {
6342 mv_f[i].filter_type = mac_filter->filter_type;
6343 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6347 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6348 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6349 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6350 &mac_filter->mac_addr);
6351 if (ret != I40E_SUCCESS)
6355 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6356 if (ret != I40E_SUCCESS)
6359 /* Add the mac addr into mac list */
6360 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6362 PMD_DRV_LOG(ERR, "failed to allocate memory");
6363 ret = I40E_ERR_NO_MEMORY;
6366 (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6368 f->mac_info.filter_type = mac_filter->filter_type;
6369 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6380 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6382 struct i40e_mac_filter *f;
6383 struct i40e_macvlan_filter *mv_f;
6385 enum rte_mac_filter_type filter_type;
6386 int ret = I40E_SUCCESS;
6388 /* Can't find it, return an error */
6389 f = i40e_find_mac_filter(vsi, addr);
6391 return I40E_ERR_PARAM;
6393 vlan_num = vsi->vlan_num;
6394 filter_type = f->mac_info.filter_type;
6395 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6396 filter_type == RTE_MACVLAN_HASH_MATCH) {
6397 if (vlan_num == 0) {
6398 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6399 return I40E_ERR_PARAM;
6401 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6402 filter_type == RTE_MAC_HASH_MATCH)
6405 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6407 PMD_DRV_LOG(ERR, "failed to allocate memory");
6408 return I40E_ERR_NO_MEMORY;
6411 for (i = 0; i < vlan_num; i++) {
6412 mv_f[i].filter_type = filter_type;
6413 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6416 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6417 filter_type == RTE_MACVLAN_HASH_MATCH) {
6418 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6419 if (ret != I40E_SUCCESS)
6423 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6424 if (ret != I40E_SUCCESS)
6427 /* Remove the mac addr into mac list */
6428 TAILQ_REMOVE(&vsi->mac_list, f, next);
6438 /* Configure hash enable flags for RSS */
6440 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6447 if (flags & ETH_RSS_FRAG_IPV4)
6448 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6449 if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6450 if (type == I40E_MAC_X722) {
6451 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6452 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6454 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6456 if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6457 if (type == I40E_MAC_X722) {
6458 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6459 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6460 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6462 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6464 if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6465 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6466 if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6467 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6468 if (flags & ETH_RSS_FRAG_IPV6)
6469 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6470 if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6471 if (type == I40E_MAC_X722) {
6472 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6473 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6475 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6477 if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6478 if (type == I40E_MAC_X722) {
6479 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6480 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6481 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6483 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6485 if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6486 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6487 if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6488 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6489 if (flags & ETH_RSS_L2_PAYLOAD)
6490 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6495 /* Parse the hash enable flags */
6497 i40e_parse_hena(uint64_t flags)
6499 uint64_t rss_hf = 0;
6503 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6504 rss_hf |= ETH_RSS_FRAG_IPV4;
6505 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6506 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6507 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6508 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6509 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6510 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6511 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6512 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6513 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6514 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6515 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6516 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6517 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6518 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6519 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6520 rss_hf |= ETH_RSS_FRAG_IPV6;
6521 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6522 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6523 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6524 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6525 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6526 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6527 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6528 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6529 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6530 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6531 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6532 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6533 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6534 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6535 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6536 rss_hf |= ETH_RSS_L2_PAYLOAD;
6543 i40e_pf_disable_rss(struct i40e_pf *pf)
6545 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6548 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6549 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6550 if (hw->mac.type == I40E_MAC_X722)
6551 hena &= ~I40E_RSS_HENA_ALL_X722;
6553 hena &= ~I40E_RSS_HENA_ALL;
6554 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6555 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6556 I40E_WRITE_FLUSH(hw);
6560 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6562 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6563 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6566 if (!key || key_len == 0) {
6567 PMD_DRV_LOG(DEBUG, "No key to be configured");
6569 } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6571 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6575 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6576 struct i40e_aqc_get_set_rss_key_data *key_dw =
6577 (struct i40e_aqc_get_set_rss_key_data *)key;
6579 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6581 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6583 uint32_t *hash_key = (uint32_t *)key;
6586 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6587 i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6588 I40E_WRITE_FLUSH(hw);
6595 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6597 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6598 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6601 if (!key || !key_len)
6604 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6605 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6606 (struct i40e_aqc_get_set_rss_key_data *)key);
6608 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6612 uint32_t *key_dw = (uint32_t *)key;
6615 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6616 key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6618 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6624 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6626 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6631 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6632 rss_conf->rss_key_len);
6636 rss_hf = rss_conf->rss_hf;
6637 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6638 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6639 if (hw->mac.type == I40E_MAC_X722)
6640 hena &= ~I40E_RSS_HENA_ALL_X722;
6642 hena &= ~I40E_RSS_HENA_ALL;
6643 hena |= i40e_config_hena(rss_hf, hw->mac.type);
6644 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6645 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6646 I40E_WRITE_FLUSH(hw);
6652 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6653 struct rte_eth_rss_conf *rss_conf)
6655 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6656 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6657 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6660 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6661 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6662 if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6663 ? I40E_RSS_HENA_ALL_X722
6664 : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6665 if (rss_hf != 0) /* Enable RSS */
6667 return 0; /* Nothing to do */
6670 if (rss_hf == 0) /* Disable RSS */
6673 return i40e_hw_rss_hash_set(pf, rss_conf);
6677 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6678 struct rte_eth_rss_conf *rss_conf)
6680 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6681 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6684 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6685 &rss_conf->rss_key_len);
6687 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6688 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6689 rss_conf->rss_hf = i40e_parse_hena(hena);
6695 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6697 switch (filter_type) {
6698 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6699 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6701 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6702 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6704 case RTE_TUNNEL_FILTER_IMAC_TENID:
6705 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6707 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6708 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6710 case ETH_TUNNEL_FILTER_IMAC:
6711 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6713 case ETH_TUNNEL_FILTER_OIP:
6714 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6716 case ETH_TUNNEL_FILTER_IIP:
6717 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6720 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6727 /* Convert tunnel filter structure */
6729 i40e_tunnel_filter_convert(
6730 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
6731 struct i40e_tunnel_filter *tunnel_filter)
6733 ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
6734 (struct ether_addr *)&tunnel_filter->input.outer_mac);
6735 ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
6736 (struct ether_addr *)&tunnel_filter->input.inner_mac);
6737 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
6738 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
6739 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6740 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6741 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6743 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6744 tunnel_filter->input.flags = cld_filter->element.flags;
6745 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
6746 tunnel_filter->queue = cld_filter->element.queue_number;
6747 rte_memcpy(tunnel_filter->input.general_fields,
6748 cld_filter->general_fields,
6749 sizeof(cld_filter->general_fields));
6754 /* Check if there exists the tunnel filter */
6755 struct i40e_tunnel_filter *
6756 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6757 const struct i40e_tunnel_filter_input *input)
6761 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6765 return tunnel_rule->hash_map[ret];
6768 /* Add a tunnel filter into the SW list */
6770 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6771 struct i40e_tunnel_filter *tunnel_filter)
6773 struct i40e_tunnel_rule *rule = &pf->tunnel;
6776 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6779 "Failed to insert tunnel filter to hash table %d!",
6783 rule->hash_map[ret] = tunnel_filter;
6785 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6790 /* Delete a tunnel filter from the SW list */
6792 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6793 struct i40e_tunnel_filter_input *input)
6795 struct i40e_tunnel_rule *rule = &pf->tunnel;
6796 struct i40e_tunnel_filter *tunnel_filter;
6799 ret = rte_hash_del_key(rule->hash_table, input);
6802 "Failed to delete tunnel filter to hash table %d!",
6806 tunnel_filter = rule->hash_map[ret];
6807 rule->hash_map[ret] = NULL;
6809 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6810 rte_free(tunnel_filter);
6816 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6817 struct rte_eth_tunnel_filter_conf *tunnel_filter,
6822 uint8_t i, tun_type = 0;
6823 /* internal varialbe to convert ipv6 byte order */
6824 uint32_t convert_ipv6[4];
6826 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6827 struct i40e_vsi *vsi = pf->main_vsi;
6828 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
6829 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
6830 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6831 struct i40e_tunnel_filter *tunnel, *node;
6832 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6834 cld_filter = rte_zmalloc("tunnel_filter",
6835 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
6838 if (NULL == cld_filter) {
6839 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6842 pfilter = cld_filter;
6844 ether_addr_copy(&tunnel_filter->outer_mac,
6845 (struct ether_addr *)&pfilter->element.outer_mac);
6846 ether_addr_copy(&tunnel_filter->inner_mac,
6847 (struct ether_addr *)&pfilter->element.inner_mac);
6849 pfilter->element.inner_vlan =
6850 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6851 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6852 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6853 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6854 rte_memcpy(&pfilter->element.ipaddr.v4.data,
6855 &rte_cpu_to_le_32(ipv4_addr),
6856 sizeof(pfilter->element.ipaddr.v4.data));
6858 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6859 for (i = 0; i < 4; i++) {
6861 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6863 rte_memcpy(&pfilter->element.ipaddr.v6.data,
6865 sizeof(pfilter->element.ipaddr.v6.data));
6868 /* check tunneled type */
6869 switch (tunnel_filter->tunnel_type) {
6870 case RTE_TUNNEL_TYPE_VXLAN:
6871 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6873 case RTE_TUNNEL_TYPE_NVGRE:
6874 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6876 case RTE_TUNNEL_TYPE_IP_IN_GRE:
6877 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6880 /* Other tunnel types is not supported. */
6881 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6882 rte_free(cld_filter);
6886 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6887 &pfilter->element.flags);
6889 rte_free(cld_filter);
6893 pfilter->element.flags |= rte_cpu_to_le_16(
6894 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6895 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6896 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6897 pfilter->element.queue_number =
6898 rte_cpu_to_le_16(tunnel_filter->queue_id);
6900 /* Check if there is the filter in SW list */
6901 memset(&check_filter, 0, sizeof(check_filter));
6902 i40e_tunnel_filter_convert(cld_filter, &check_filter);
6903 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
6905 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
6909 if (!add && !node) {
6910 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
6915 ret = i40e_aq_add_cloud_filters(hw,
6916 vsi->seid, &cld_filter->element, 1);
6918 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
6921 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
6922 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
6923 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
6925 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6926 &cld_filter->element, 1);
6928 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
6931 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
6934 rte_free(cld_filter);
6938 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
6939 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
6940 #define I40E_TR_GENEVE_KEY_MASK 0x8
6941 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
6942 #define I40E_TR_GRE_KEY_MASK 0x400
6943 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
6944 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
6947 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
6949 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
6950 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
6951 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6952 enum i40e_status_code status = I40E_SUCCESS;
6954 memset(&filter_replace, 0,
6955 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
6956 memset(&filter_replace_buf, 0,
6957 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
6959 /* create L1 filter */
6960 filter_replace.old_filter_type =
6961 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
6962 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
6963 filter_replace.tr_bit = 0;
6965 /* Prepare the buffer, 3 entries */
6966 filter_replace_buf.data[0] =
6967 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
6968 filter_replace_buf.data[0] |=
6969 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
6970 filter_replace_buf.data[2] = 0xFF;
6971 filter_replace_buf.data[3] = 0xFF;
6972 filter_replace_buf.data[4] =
6973 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
6974 filter_replace_buf.data[4] |=
6975 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
6976 filter_replace_buf.data[7] = 0xF0;
6977 filter_replace_buf.data[8]
6978 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
6979 filter_replace_buf.data[8] |=
6980 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
6981 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
6982 I40E_TR_GENEVE_KEY_MASK |
6983 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
6984 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
6985 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
6986 I40E_TR_GRE_NO_KEY_MASK) >> 8;
6988 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
6989 &filter_replace_buf);
6994 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
6996 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
6997 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
6998 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6999 enum i40e_status_code status = I40E_SUCCESS;
7002 memset(&filter_replace, 0,
7003 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7004 memset(&filter_replace_buf, 0,
7005 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7006 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7007 I40E_AQC_MIRROR_CLOUD_FILTER;
7008 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7009 filter_replace.new_filter_type =
7010 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7011 /* Prepare the buffer, 2 entries */
7012 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7013 filter_replace_buf.data[0] |=
7014 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7015 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7016 filter_replace_buf.data[4] |=
7017 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7018 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7019 &filter_replace_buf);
7024 memset(&filter_replace, 0,
7025 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7026 memset(&filter_replace_buf, 0,
7027 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7029 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7030 I40E_AQC_MIRROR_CLOUD_FILTER;
7031 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7032 filter_replace.new_filter_type =
7033 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7034 /* Prepare the buffer, 2 entries */
7035 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7036 filter_replace_buf.data[0] |=
7037 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7038 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7039 filter_replace_buf.data[4] |=
7040 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7042 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7043 &filter_replace_buf);
7048 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7049 struct i40e_tunnel_filter_conf *tunnel_filter,
7054 uint8_t i, tun_type = 0;
7055 /* internal variable to convert ipv6 byte order */
7056 uint32_t convert_ipv6[4];
7058 struct i40e_pf_vf *vf = NULL;
7059 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7060 struct i40e_vsi *vsi;
7061 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7062 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7063 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7064 struct i40e_tunnel_filter *tunnel, *node;
7065 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7067 bool big_buffer = 0;
7069 cld_filter = rte_zmalloc("tunnel_filter",
7070 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7073 if (cld_filter == NULL) {
7074 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7077 pfilter = cld_filter;
7079 ether_addr_copy(&tunnel_filter->outer_mac,
7080 (struct ether_addr *)&pfilter->element.outer_mac);
7081 ether_addr_copy(&tunnel_filter->inner_mac,
7082 (struct ether_addr *)&pfilter->element.inner_mac);
7084 pfilter->element.inner_vlan =
7085 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7086 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7087 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7088 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7089 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7090 &rte_cpu_to_le_32(ipv4_addr),
7091 sizeof(pfilter->element.ipaddr.v4.data));
7093 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7094 for (i = 0; i < 4; i++) {
7096 rte_cpu_to_le_32(rte_be_to_cpu_32(
7097 tunnel_filter->ip_addr.ipv6_addr[i]));
7099 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7101 sizeof(pfilter->element.ipaddr.v6.data));
7104 /* check tunneled type */
7105 switch (tunnel_filter->tunnel_type) {
7106 case I40E_TUNNEL_TYPE_VXLAN:
7107 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7109 case I40E_TUNNEL_TYPE_NVGRE:
7110 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7112 case I40E_TUNNEL_TYPE_IP_IN_GRE:
7113 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7115 case I40E_TUNNEL_TYPE_MPLSoUDP:
7116 if (!pf->mpls_replace_flag) {
7117 i40e_replace_mpls_l1_filter(pf);
7118 i40e_replace_mpls_cloud_filter(pf);
7119 pf->mpls_replace_flag = 1;
7121 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7122 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7124 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7125 (teid_le & 0xF) << 12;
7126 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7129 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoUDP;
7131 case I40E_TUNNEL_TYPE_MPLSoGRE:
7132 if (!pf->mpls_replace_flag) {
7133 i40e_replace_mpls_l1_filter(pf);
7134 i40e_replace_mpls_cloud_filter(pf);
7135 pf->mpls_replace_flag = 1;
7137 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7138 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7140 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7141 (teid_le & 0xF) << 12;
7142 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7145 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoGRE;
7147 case I40E_TUNNEL_TYPE_QINQ:
7148 if (!pf->qinq_replace_flag) {
7149 ret = i40e_cloud_filter_qinq_create(pf);
7152 "Failed to create a qinq tunnel filter.");
7153 pf->qinq_replace_flag = 1;
7155 /* Add in the General fields the values of
7156 * the Outer and Inner VLAN
7157 * Big Buffer should be set, see changes in
7158 * i40e_aq_add_cloud_filters
7160 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7161 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7165 /* Other tunnel types is not supported. */
7166 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7167 rte_free(cld_filter);
7171 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7172 pfilter->element.flags =
7173 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7174 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7175 pfilter->element.flags =
7176 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7177 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7178 pfilter->element.flags |=
7179 I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
7181 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7182 &pfilter->element.flags);
7184 rte_free(cld_filter);
7189 pfilter->element.flags |= rte_cpu_to_le_16(
7190 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7191 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7192 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7193 pfilter->element.queue_number =
7194 rte_cpu_to_le_16(tunnel_filter->queue_id);
7196 if (!tunnel_filter->is_to_vf)
7199 if (tunnel_filter->vf_id >= pf->vf_num) {
7200 PMD_DRV_LOG(ERR, "Invalid argument.");
7203 vf = &pf->vfs[tunnel_filter->vf_id];
7207 /* Check if there is the filter in SW list */
7208 memset(&check_filter, 0, sizeof(check_filter));
7209 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7210 check_filter.is_to_vf = tunnel_filter->is_to_vf;
7211 check_filter.vf_id = tunnel_filter->vf_id;
7212 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7214 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7218 if (!add && !node) {
7219 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7225 ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7226 vsi->seid, cld_filter, 1);
7228 ret = i40e_aq_add_cloud_filters(hw,
7229 vsi->seid, &cld_filter->element, 1);
7231 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7234 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7235 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7236 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7239 ret = i40e_aq_remove_cloud_filters_big_buffer(
7240 hw, vsi->seid, cld_filter, 1);
7242 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7243 &cld_filter->element, 1);
7245 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7248 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7251 rte_free(cld_filter);
7256 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7260 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7261 if (pf->vxlan_ports[i] == port)
7269 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7273 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7275 idx = i40e_get_vxlan_port_idx(pf, port);
7277 /* Check if port already exists */
7279 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7283 /* Now check if there is space to add the new port */
7284 idx = i40e_get_vxlan_port_idx(pf, 0);
7287 "Maximum number of UDP ports reached, not adding port %d",
7292 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7295 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7299 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7302 /* New port: add it and mark its index in the bitmap */
7303 pf->vxlan_ports[idx] = port;
7304 pf->vxlan_bitmap |= (1 << idx);
7306 if (!(pf->flags & I40E_FLAG_VXLAN))
7307 pf->flags |= I40E_FLAG_VXLAN;
7313 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7316 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7318 if (!(pf->flags & I40E_FLAG_VXLAN)) {
7319 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7323 idx = i40e_get_vxlan_port_idx(pf, port);
7326 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7330 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7331 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7335 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7338 pf->vxlan_ports[idx] = 0;
7339 pf->vxlan_bitmap &= ~(1 << idx);
7341 if (!pf->vxlan_bitmap)
7342 pf->flags &= ~I40E_FLAG_VXLAN;
7347 /* Add UDP tunneling port */
7349 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7350 struct rte_eth_udp_tunnel *udp_tunnel)
7353 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7355 if (udp_tunnel == NULL)
7358 switch (udp_tunnel->prot_type) {
7359 case RTE_TUNNEL_TYPE_VXLAN:
7360 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7363 case RTE_TUNNEL_TYPE_GENEVE:
7364 case RTE_TUNNEL_TYPE_TEREDO:
7365 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7370 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7378 /* Remove UDP tunneling port */
7380 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7381 struct rte_eth_udp_tunnel *udp_tunnel)
7384 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7386 if (udp_tunnel == NULL)
7389 switch (udp_tunnel->prot_type) {
7390 case RTE_TUNNEL_TYPE_VXLAN:
7391 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7393 case RTE_TUNNEL_TYPE_GENEVE:
7394 case RTE_TUNNEL_TYPE_TEREDO:
7395 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7399 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7407 /* Calculate the maximum number of contiguous PF queues that are configured */
7409 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7411 struct rte_eth_dev_data *data = pf->dev_data;
7413 struct i40e_rx_queue *rxq;
7416 for (i = 0; i < pf->lan_nb_qps; i++) {
7417 rxq = data->rx_queues[i];
7418 if (rxq && rxq->q_set)
7429 i40e_pf_config_rss(struct i40e_pf *pf)
7431 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7432 struct rte_eth_rss_conf rss_conf;
7433 uint32_t i, lut = 0;
7437 * If both VMDQ and RSS enabled, not all of PF queues are configured.
7438 * It's necessary to calulate the actual PF queues that are configured.
7440 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7441 num = i40e_pf_calc_configured_queues_num(pf);
7443 num = pf->dev_data->nb_rx_queues;
7445 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7446 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7450 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7454 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7457 lut = (lut << 8) | (j & ((0x1 <<
7458 hw->func_caps.rss_table_entry_width) - 1));
7460 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7463 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7464 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
7465 i40e_pf_disable_rss(pf);
7468 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7469 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7470 /* Random default keys */
7471 static uint32_t rss_key_default[] = {0x6b793944,
7472 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7473 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7474 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7476 rss_conf.rss_key = (uint8_t *)rss_key_default;
7477 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7481 return i40e_hw_rss_hash_set(pf, &rss_conf);
7485 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7486 struct rte_eth_tunnel_filter_conf *filter)
7488 if (pf == NULL || filter == NULL) {
7489 PMD_DRV_LOG(ERR, "Invalid parameter");
7493 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7494 PMD_DRV_LOG(ERR, "Invalid queue ID");
7498 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7499 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7503 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7504 (is_zero_ether_addr(&filter->outer_mac))) {
7505 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7509 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7510 (is_zero_ether_addr(&filter->inner_mac))) {
7511 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7518 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7519 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
7521 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7526 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7527 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7530 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7531 } else if (len == 4) {
7532 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7534 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7539 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7546 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7547 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7553 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7560 switch (cfg->cfg_type) {
7561 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7562 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7565 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7573 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7574 enum rte_filter_op filter_op,
7577 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7578 int ret = I40E_ERR_PARAM;
7580 switch (filter_op) {
7581 case RTE_ETH_FILTER_SET:
7582 ret = i40e_dev_global_config_set(hw,
7583 (struct rte_eth_global_cfg *)arg);
7586 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7594 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7595 enum rte_filter_op filter_op,
7598 struct rte_eth_tunnel_filter_conf *filter;
7599 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7600 int ret = I40E_SUCCESS;
7602 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7604 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7605 return I40E_ERR_PARAM;
7607 switch (filter_op) {
7608 case RTE_ETH_FILTER_NOP:
7609 if (!(pf->flags & I40E_FLAG_VXLAN))
7610 ret = I40E_NOT_SUPPORTED;
7612 case RTE_ETH_FILTER_ADD:
7613 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7615 case RTE_ETH_FILTER_DELETE:
7616 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7619 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7620 ret = I40E_ERR_PARAM;
7628 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7631 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7634 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7635 ret = i40e_pf_config_rss(pf);
7637 i40e_pf_disable_rss(pf);
7642 /* Get the symmetric hash enable configurations per port */
7644 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7646 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7648 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7651 /* Set the symmetric hash enable configurations per port */
7653 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7655 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7658 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7660 "Symmetric hash has already been enabled");
7663 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7665 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7667 "Symmetric hash has already been disabled");
7670 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7672 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7673 I40E_WRITE_FLUSH(hw);
7677 * Get global configurations of hash function type and symmetric hash enable
7678 * per flow type (pctype). Note that global configuration means it affects all
7679 * the ports on the same NIC.
7682 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7683 struct rte_eth_hash_global_conf *g_cfg)
7685 uint32_t reg, mask = I40E_FLOW_TYPES;
7687 enum i40e_filter_pctype pctype;
7689 memset(g_cfg, 0, sizeof(*g_cfg));
7690 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7691 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7692 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7694 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7695 PMD_DRV_LOG(DEBUG, "Hash function is %s",
7696 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7698 for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7699 if (!(mask & (1UL << i)))
7701 mask &= ~(1UL << i);
7702 /* Bit set indicats the coresponding flow type is supported */
7703 g_cfg->valid_bit_mask[0] |= (1UL << i);
7704 /* if flowtype is invalid, continue */
7705 if (!I40E_VALID_FLOW(i))
7707 pctype = i40e_flowtype_to_pctype(i);
7708 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7709 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7710 g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7717 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7720 uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7722 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7723 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7724 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7725 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7731 * As i40e supports less than 32 flow types, only first 32 bits need to
7734 mask0 = g_cfg->valid_bit_mask[0];
7735 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7737 /* Check if any unsupported flow type configured */
7738 if ((mask0 | i40e_mask) ^ i40e_mask)
7741 if (g_cfg->valid_bit_mask[i])
7749 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7755 * Set global configurations of hash function type and symmetric hash enable
7756 * per flow type (pctype). Note any modifying global configuration will affect
7757 * all the ports on the same NIC.
7760 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7761 struct rte_eth_hash_global_conf *g_cfg)
7766 uint32_t mask0 = g_cfg->valid_bit_mask[0];
7767 enum i40e_filter_pctype pctype;
7769 /* Check the input parameters */
7770 ret = i40e_hash_global_config_check(g_cfg);
7774 for (i = 0; mask0 && i < UINT32_BIT; i++) {
7775 if (!(mask0 & (1UL << i)))
7777 mask0 &= ~(1UL << i);
7778 /* if flowtype is invalid, continue */
7779 if (!I40E_VALID_FLOW(i))
7781 pctype = i40e_flowtype_to_pctype(i);
7782 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7783 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7784 if (hw->mac.type == I40E_MAC_X722) {
7785 if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_UDP) {
7786 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7787 I40E_FILTER_PCTYPE_NONF_IPV4_UDP), reg);
7788 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7789 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP),
7791 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7792 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP),
7794 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_TCP) {
7795 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7796 I40E_FILTER_PCTYPE_NONF_IPV4_TCP), reg);
7797 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7798 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK),
7800 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_UDP) {
7801 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7802 I40E_FILTER_PCTYPE_NONF_IPV6_UDP), reg);
7803 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7804 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP),
7806 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7807 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP),
7809 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_TCP) {
7810 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7811 I40E_FILTER_PCTYPE_NONF_IPV6_TCP), reg);
7812 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7813 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK),
7816 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype),
7820 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7824 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7825 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7827 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7829 "Hash function already set to Toeplitz");
7832 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7833 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7835 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7837 "Hash function already set to Simple XOR");
7840 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7842 /* Use the default, and keep it as it is */
7845 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7848 I40E_WRITE_FLUSH(hw);
7854 * Valid input sets for hash and flow director filters per PCTYPE
7857 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7858 enum rte_filter_type filter)
7862 static const uint64_t valid_hash_inset_table[] = {
7863 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7864 I40E_INSET_DMAC | I40E_INSET_SMAC |
7865 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7866 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7867 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7868 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7869 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7870 I40E_INSET_FLEX_PAYLOAD,
7871 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7872 I40E_INSET_DMAC | I40E_INSET_SMAC |
7873 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7874 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7875 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7876 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7877 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7878 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7879 I40E_INSET_FLEX_PAYLOAD,
7880 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7881 I40E_INSET_DMAC | I40E_INSET_SMAC |
7882 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7883 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7884 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7885 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7886 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7887 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7888 I40E_INSET_FLEX_PAYLOAD,
7889 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7890 I40E_INSET_DMAC | I40E_INSET_SMAC |
7891 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7892 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7893 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7894 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7895 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7896 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7897 I40E_INSET_FLEX_PAYLOAD,
7898 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7899 I40E_INSET_DMAC | I40E_INSET_SMAC |
7900 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7901 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7902 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7903 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7904 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7905 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7906 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7907 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7908 I40E_INSET_DMAC | I40E_INSET_SMAC |
7909 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7910 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7911 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7912 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7913 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7914 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7915 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7916 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7917 I40E_INSET_DMAC | I40E_INSET_SMAC |
7918 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7919 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7920 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7921 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7922 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7923 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7924 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7925 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7926 I40E_INSET_DMAC | I40E_INSET_SMAC |
7927 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7928 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7929 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7930 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7931 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7932 I40E_INSET_FLEX_PAYLOAD,
7933 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7934 I40E_INSET_DMAC | I40E_INSET_SMAC |
7935 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7936 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7937 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7938 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7939 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7940 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7941 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7942 I40E_INSET_DMAC | I40E_INSET_SMAC |
7943 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7944 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7945 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7946 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7947 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7948 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7949 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7950 I40E_INSET_DMAC | I40E_INSET_SMAC |
7951 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7952 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7953 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7954 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7955 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7956 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7957 I40E_INSET_FLEX_PAYLOAD,
7958 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7959 I40E_INSET_DMAC | I40E_INSET_SMAC |
7960 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7961 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7962 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7963 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7964 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7965 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7966 I40E_INSET_FLEX_PAYLOAD,
7967 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7968 I40E_INSET_DMAC | I40E_INSET_SMAC |
7969 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7970 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7971 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7972 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7973 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7974 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7975 I40E_INSET_FLEX_PAYLOAD,
7976 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7977 I40E_INSET_DMAC | I40E_INSET_SMAC |
7978 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7979 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7980 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7981 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7982 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7983 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7984 I40E_INSET_FLEX_PAYLOAD,
7985 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7986 I40E_INSET_DMAC | I40E_INSET_SMAC |
7987 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7988 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7989 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7990 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7991 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7992 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7993 I40E_INSET_FLEX_PAYLOAD,
7994 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7995 I40E_INSET_DMAC | I40E_INSET_SMAC |
7996 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7997 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7998 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7999 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8000 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8001 I40E_INSET_FLEX_PAYLOAD,
8002 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8003 I40E_INSET_DMAC | I40E_INSET_SMAC |
8004 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8005 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8006 I40E_INSET_FLEX_PAYLOAD,
8010 * Flow director supports only fields defined in
8011 * union rte_eth_fdir_flow.
8013 static const uint64_t valid_fdir_inset_table[] = {
8014 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8015 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8016 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8017 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8018 I40E_INSET_IPV4_TTL,
8019 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8020 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8021 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8022 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8023 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8024 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8025 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8026 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8027 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8028 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8029 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8030 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8031 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8032 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8033 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8034 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8035 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8036 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8037 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8038 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8039 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8040 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8041 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8042 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8043 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8044 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8045 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8046 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8047 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8048 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8050 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8051 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8052 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8053 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8054 I40E_INSET_IPV4_TTL,
8055 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8056 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8057 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8058 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8059 I40E_INSET_IPV6_HOP_LIMIT,
8060 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8061 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8062 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8063 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8064 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8065 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8066 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8067 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8068 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8069 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8070 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8071 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8072 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8073 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8074 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8075 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8076 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8077 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8078 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8079 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8080 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8081 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8082 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8083 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8084 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8085 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8086 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8087 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8088 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8089 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8091 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8092 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8093 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8094 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8095 I40E_INSET_IPV6_HOP_LIMIT,
8096 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8097 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8098 I40E_INSET_LAST_ETHER_TYPE,
8101 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8103 if (filter == RTE_ETH_FILTER_HASH)
8104 valid = valid_hash_inset_table[pctype];
8106 valid = valid_fdir_inset_table[pctype];
8112 * Validate if the input set is allowed for a specific PCTYPE
8115 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8116 enum rte_filter_type filter, uint64_t inset)
8120 valid = i40e_get_valid_input_set(pctype, filter);
8121 if (inset & (~valid))
8127 /* default input set fields combination per pctype */
8129 i40e_get_default_input_set(uint16_t pctype)
8131 static const uint64_t default_inset_table[] = {
8132 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8133 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8134 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8135 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8136 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8137 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8138 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8139 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8140 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8141 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8142 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8143 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8144 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8145 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8146 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8147 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8148 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8149 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8150 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8151 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8153 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8154 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8155 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8156 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8157 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8158 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8159 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8160 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8161 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8162 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8163 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8164 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8165 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8166 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8167 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8168 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8169 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8170 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8171 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8172 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8173 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8174 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8176 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8177 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8178 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8179 I40E_INSET_LAST_ETHER_TYPE,
8182 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8185 return default_inset_table[pctype];
8189 * Parse the input set from index to logical bit masks
8192 i40e_parse_input_set(uint64_t *inset,
8193 enum i40e_filter_pctype pctype,
8194 enum rte_eth_input_set_field *field,
8200 static const struct {
8201 enum rte_eth_input_set_field field;
8203 } inset_convert_table[] = {
8204 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8205 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8206 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8207 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8208 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8209 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8210 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8211 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8212 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8213 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8214 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8215 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8216 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8217 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8218 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8219 I40E_INSET_IPV6_NEXT_HDR},
8220 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8221 I40E_INSET_IPV6_HOP_LIMIT},
8222 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8223 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8224 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8225 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8226 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8227 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8228 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8229 I40E_INSET_SCTP_VT},
8230 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8231 I40E_INSET_TUNNEL_DMAC},
8232 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8233 I40E_INSET_VLAN_TUNNEL},
8234 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8235 I40E_INSET_TUNNEL_ID},
8236 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8237 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8238 I40E_INSET_FLEX_PAYLOAD_W1},
8239 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8240 I40E_INSET_FLEX_PAYLOAD_W2},
8241 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8242 I40E_INSET_FLEX_PAYLOAD_W3},
8243 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8244 I40E_INSET_FLEX_PAYLOAD_W4},
8245 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8246 I40E_INSET_FLEX_PAYLOAD_W5},
8247 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8248 I40E_INSET_FLEX_PAYLOAD_W6},
8249 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8250 I40E_INSET_FLEX_PAYLOAD_W7},
8251 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8252 I40E_INSET_FLEX_PAYLOAD_W8},
8255 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8258 /* Only one item allowed for default or all */
8260 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8261 *inset = i40e_get_default_input_set(pctype);
8263 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8264 *inset = I40E_INSET_NONE;
8269 for (i = 0, *inset = 0; i < size; i++) {
8270 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8271 if (field[i] == inset_convert_table[j].field) {
8272 *inset |= inset_convert_table[j].inset;
8277 /* It contains unsupported input set, return immediately */
8278 if (j == RTE_DIM(inset_convert_table))
8286 * Translate the input set from bit masks to register aware bit masks
8290 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8300 static const struct inset_map inset_map_common[] = {
8301 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8302 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8303 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8304 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8305 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8306 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8307 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8308 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8309 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8310 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8311 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8312 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8313 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8314 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8315 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8316 {I40E_INSET_TUNNEL_DMAC,
8317 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8318 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8319 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8320 {I40E_INSET_TUNNEL_SRC_PORT,
8321 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8322 {I40E_INSET_TUNNEL_DST_PORT,
8323 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8324 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8325 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8326 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8327 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8328 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8329 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8330 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8331 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8332 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8335 /* some different registers map in x722*/
8336 static const struct inset_map inset_map_diff_x722[] = {
8337 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8338 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8339 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8340 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8343 static const struct inset_map inset_map_diff_not_x722[] = {
8344 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8345 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8346 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8347 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8353 /* Translate input set to register aware inset */
8354 if (type == I40E_MAC_X722) {
8355 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8356 if (input & inset_map_diff_x722[i].inset)
8357 val |= inset_map_diff_x722[i].inset_reg;
8360 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8361 if (input & inset_map_diff_not_x722[i].inset)
8362 val |= inset_map_diff_not_x722[i].inset_reg;
8366 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8367 if (input & inset_map_common[i].inset)
8368 val |= inset_map_common[i].inset_reg;
8375 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8378 uint64_t inset_need_mask = inset;
8380 static const struct {
8383 } inset_mask_map[] = {
8384 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8385 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8386 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8387 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8388 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8389 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8390 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8391 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8394 if (!inset || !mask || !nb_elem)
8397 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8398 /* Clear the inset bit, if no MASK is required,
8399 * for example proto + ttl
8401 if ((inset & inset_mask_map[i].inset) ==
8402 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8403 inset_need_mask &= ~inset_mask_map[i].inset;
8404 if (!inset_need_mask)
8407 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8408 if ((inset_need_mask & inset_mask_map[i].inset) ==
8409 inset_mask_map[i].inset) {
8410 if (idx >= nb_elem) {
8411 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8414 mask[idx] = inset_mask_map[i].mask;
8423 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8425 uint32_t reg = i40e_read_rx_ctl(hw, addr);
8427 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8429 i40e_write_rx_ctl(hw, addr, val);
8430 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8431 (uint32_t)i40e_read_rx_ctl(hw, addr));
8435 i40e_filter_input_set_init(struct i40e_pf *pf)
8437 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8438 enum i40e_filter_pctype pctype;
8439 uint64_t input_set, inset_reg;
8440 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8443 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8444 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8445 if (hw->mac.type == I40E_MAC_X722) {
8446 if (!I40E_VALID_PCTYPE_X722(pctype))
8449 if (!I40E_VALID_PCTYPE(pctype))
8453 input_set = i40e_get_default_input_set(pctype);
8455 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8456 I40E_INSET_MASK_NUM_REG);
8459 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8462 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8463 (uint32_t)(inset_reg & UINT32_MAX));
8464 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8465 (uint32_t)((inset_reg >>
8466 I40E_32_BIT_WIDTH) & UINT32_MAX));
8467 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8468 (uint32_t)(inset_reg & UINT32_MAX));
8469 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8470 (uint32_t)((inset_reg >>
8471 I40E_32_BIT_WIDTH) & UINT32_MAX));
8473 for (i = 0; i < num; i++) {
8474 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8476 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8479 /*clear unused mask registers of the pctype */
8480 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8481 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8483 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8486 I40E_WRITE_FLUSH(hw);
8488 /* store the default input set */
8489 pf->hash_input_set[pctype] = input_set;
8490 pf->fdir.input_set[pctype] = input_set;
8495 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8496 struct rte_eth_input_set_conf *conf)
8498 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8499 enum i40e_filter_pctype pctype;
8500 uint64_t input_set, inset_reg = 0;
8501 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8505 PMD_DRV_LOG(ERR, "Invalid pointer");
8508 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8509 conf->op != RTE_ETH_INPUT_SET_ADD) {
8510 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8514 if (!I40E_VALID_FLOW(conf->flow_type)) {
8515 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8519 if (hw->mac.type == I40E_MAC_X722) {
8520 /* get translated pctype value in fd pctype register */
8521 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8522 I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8525 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8527 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8530 PMD_DRV_LOG(ERR, "Failed to parse input set");
8533 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8535 PMD_DRV_LOG(ERR, "Invalid input set");
8538 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8539 /* get inset value in register */
8540 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8541 inset_reg <<= I40E_32_BIT_WIDTH;
8542 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8543 input_set |= pf->hash_input_set[pctype];
8545 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8546 I40E_INSET_MASK_NUM_REG);
8550 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8552 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8553 (uint32_t)(inset_reg & UINT32_MAX));
8554 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8555 (uint32_t)((inset_reg >>
8556 I40E_32_BIT_WIDTH) & UINT32_MAX));
8558 for (i = 0; i < num; i++)
8559 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8561 /*clear unused mask registers of the pctype */
8562 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8563 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8565 I40E_WRITE_FLUSH(hw);
8567 pf->hash_input_set[pctype] = input_set;
8572 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8573 struct rte_eth_input_set_conf *conf)
8575 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8576 enum i40e_filter_pctype pctype;
8577 uint64_t input_set, inset_reg = 0;
8578 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8582 PMD_DRV_LOG(ERR, "Invalid pointer");
8585 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8586 conf->op != RTE_ETH_INPUT_SET_ADD) {
8587 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8591 if (!I40E_VALID_FLOW(conf->flow_type)) {
8592 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8596 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8598 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8601 PMD_DRV_LOG(ERR, "Failed to parse input set");
8604 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8606 PMD_DRV_LOG(ERR, "Invalid input set");
8610 /* get inset value in register */
8611 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8612 inset_reg <<= I40E_32_BIT_WIDTH;
8613 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8615 /* Can not change the inset reg for flex payload for fdir,
8616 * it is done by writing I40E_PRTQF_FD_FLXINSET
8617 * in i40e_set_flex_mask_on_pctype.
8619 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8620 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8622 input_set |= pf->fdir.input_set[pctype];
8623 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8624 I40E_INSET_MASK_NUM_REG);
8628 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8630 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8631 (uint32_t)(inset_reg & UINT32_MAX));
8632 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8633 (uint32_t)((inset_reg >>
8634 I40E_32_BIT_WIDTH) & UINT32_MAX));
8636 for (i = 0; i < num; i++)
8637 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8639 /*clear unused mask registers of the pctype */
8640 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8641 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8643 I40E_WRITE_FLUSH(hw);
8645 pf->fdir.input_set[pctype] = input_set;
8650 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8655 PMD_DRV_LOG(ERR, "Invalid pointer");
8659 switch (info->info_type) {
8660 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8661 i40e_get_symmetric_hash_enable_per_port(hw,
8662 &(info->info.enable));
8664 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8665 ret = i40e_get_hash_filter_global_config(hw,
8666 &(info->info.global_conf));
8669 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8679 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8684 PMD_DRV_LOG(ERR, "Invalid pointer");
8688 switch (info->info_type) {
8689 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8690 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8692 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8693 ret = i40e_set_hash_filter_global_config(hw,
8694 &(info->info.global_conf));
8696 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8697 ret = i40e_hash_filter_inset_select(hw,
8698 &(info->info.input_set_conf));
8702 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8711 /* Operations for hash function */
8713 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8714 enum rte_filter_op filter_op,
8717 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8720 switch (filter_op) {
8721 case RTE_ETH_FILTER_NOP:
8723 case RTE_ETH_FILTER_GET:
8724 ret = i40e_hash_filter_get(hw,
8725 (struct rte_eth_hash_filter_info *)arg);
8727 case RTE_ETH_FILTER_SET:
8728 ret = i40e_hash_filter_set(hw,
8729 (struct rte_eth_hash_filter_info *)arg);
8732 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8741 /* Convert ethertype filter structure */
8743 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8744 struct i40e_ethertype_filter *filter)
8746 rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8747 filter->input.ether_type = input->ether_type;
8748 filter->flags = input->flags;
8749 filter->queue = input->queue;
8754 /* Check if there exists the ehtertype filter */
8755 struct i40e_ethertype_filter *
8756 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8757 const struct i40e_ethertype_filter_input *input)
8761 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8765 return ethertype_rule->hash_map[ret];
8768 /* Add ethertype filter in SW list */
8770 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8771 struct i40e_ethertype_filter *filter)
8773 struct i40e_ethertype_rule *rule = &pf->ethertype;
8776 ret = rte_hash_add_key(rule->hash_table, &filter->input);
8779 "Failed to insert ethertype filter"
8780 " to hash table %d!",
8784 rule->hash_map[ret] = filter;
8786 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8791 /* Delete ethertype filter in SW list */
8793 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8794 struct i40e_ethertype_filter_input *input)
8796 struct i40e_ethertype_rule *rule = &pf->ethertype;
8797 struct i40e_ethertype_filter *filter;
8800 ret = rte_hash_del_key(rule->hash_table, input);
8803 "Failed to delete ethertype filter"
8804 " to hash table %d!",
8808 filter = rule->hash_map[ret];
8809 rule->hash_map[ret] = NULL;
8811 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8818 * Configure ethertype filter, which can director packet by filtering
8819 * with mac address and ether_type or only ether_type
8822 i40e_ethertype_filter_set(struct i40e_pf *pf,
8823 struct rte_eth_ethertype_filter *filter,
8826 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8827 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
8828 struct i40e_ethertype_filter *ethertype_filter, *node;
8829 struct i40e_ethertype_filter check_filter;
8830 struct i40e_control_filter_stats stats;
8834 if (filter->queue >= pf->dev_data->nb_rx_queues) {
8835 PMD_DRV_LOG(ERR, "Invalid queue ID");
8838 if (filter->ether_type == ETHER_TYPE_IPv4 ||
8839 filter->ether_type == ETHER_TYPE_IPv6) {
8841 "unsupported ether_type(0x%04x) in control packet filter.",
8842 filter->ether_type);
8845 if (filter->ether_type == ETHER_TYPE_VLAN)
8846 PMD_DRV_LOG(WARNING,
8847 "filter vlan ether_type in first tag is not supported.");
8849 /* Check if there is the filter in SW list */
8850 memset(&check_filter, 0, sizeof(check_filter));
8851 i40e_ethertype_filter_convert(filter, &check_filter);
8852 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
8853 &check_filter.input);
8855 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
8859 if (!add && !node) {
8860 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
8864 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8865 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8866 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8867 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8868 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8870 memset(&stats, 0, sizeof(stats));
8871 ret = i40e_aq_add_rem_control_packet_filter(hw,
8872 filter->mac_addr.addr_bytes,
8873 filter->ether_type, flags,
8875 filter->queue, add, &stats, NULL);
8878 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
8879 ret, stats.mac_etype_used, stats.etype_used,
8880 stats.mac_etype_free, stats.etype_free);
8884 /* Add or delete a filter in SW list */
8886 ethertype_filter = rte_zmalloc("ethertype_filter",
8887 sizeof(*ethertype_filter), 0);
8888 rte_memcpy(ethertype_filter, &check_filter,
8889 sizeof(check_filter));
8890 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
8892 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
8899 * Handle operations for ethertype filter.
8902 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8903 enum rte_filter_op filter_op,
8906 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8909 if (filter_op == RTE_ETH_FILTER_NOP)
8913 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8918 switch (filter_op) {
8919 case RTE_ETH_FILTER_ADD:
8920 ret = i40e_ethertype_filter_set(pf,
8921 (struct rte_eth_ethertype_filter *)arg,
8924 case RTE_ETH_FILTER_DELETE:
8925 ret = i40e_ethertype_filter_set(pf,
8926 (struct rte_eth_ethertype_filter *)arg,
8930 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
8938 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8939 enum rte_filter_type filter_type,
8940 enum rte_filter_op filter_op,
8948 switch (filter_type) {
8949 case RTE_ETH_FILTER_NONE:
8950 /* For global configuration */
8951 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8953 case RTE_ETH_FILTER_HASH:
8954 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8956 case RTE_ETH_FILTER_MACVLAN:
8957 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8959 case RTE_ETH_FILTER_ETHERTYPE:
8960 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8962 case RTE_ETH_FILTER_TUNNEL:
8963 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8965 case RTE_ETH_FILTER_FDIR:
8966 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8968 case RTE_ETH_FILTER_GENERIC:
8969 if (filter_op != RTE_ETH_FILTER_GET)
8971 *(const void **)arg = &i40e_flow_ops;
8974 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8984 * Check and enable Extended Tag.
8985 * Enabling Extended Tag is important for 40G performance.
8988 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8990 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
8994 ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8997 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9001 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9002 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9007 ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
9010 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9014 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9015 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9018 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9019 ret = rte_eal_pci_write_config(pci_dev, &buf, sizeof(buf),
9022 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9029 * As some registers wouldn't be reset unless a global hardware reset,
9030 * hardware initialization is needed to put those registers into an
9031 * expected initial state.
9034 i40e_hw_init(struct rte_eth_dev *dev)
9036 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9038 i40e_enable_extended_tag(dev);
9040 /* clear the PF Queue Filter control register */
9041 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9043 /* Disable symmetric hash per port */
9044 i40e_set_symmetric_hash_enable_per_port(hw, 0);
9047 enum i40e_filter_pctype
9048 i40e_flowtype_to_pctype(uint16_t flow_type)
9050 static const enum i40e_filter_pctype pctype_table[] = {
9051 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
9052 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
9053 I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
9054 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
9055 I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
9056 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
9057 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
9058 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
9059 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
9060 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
9061 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
9062 I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
9063 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
9064 I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
9065 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
9066 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
9067 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
9068 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
9069 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
9072 return pctype_table[flow_type];
9076 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
9078 static const uint16_t flowtype_table[] = {
9079 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
9080 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9081 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9082 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9083 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9084 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9085 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9086 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9087 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9088 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9089 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9090 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9091 RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
9092 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9093 RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
9094 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
9095 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9096 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9097 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9098 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9099 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9100 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9101 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9102 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9103 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9104 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9105 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9106 RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
9107 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9108 RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
9109 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
9112 return flowtype_table[pctype];
9116 * On X710, performance number is far from the expectation on recent firmware
9117 * versions; on XL710, performance number is also far from the expectation on
9118 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9119 * mode is enabled and port MAC address is equal to the packet destination MAC
9120 * address. The fix for this issue may not be integrated in the following
9121 * firmware version. So the workaround in software driver is needed. It needs
9122 * to modify the initial values of 3 internal only registers for both X710 and
9123 * XL710. Note that the values for X710 or XL710 could be different, and the
9124 * workaround can be removed when it is fixed in firmware in the future.
9127 /* For both X710 and XL710 */
9128 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
9129 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
9131 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9132 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
9135 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9136 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9139 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
9141 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
9142 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
9145 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9147 enum i40e_status_code status;
9148 struct i40e_aq_get_phy_abilities_resp phy_ab;
9151 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9161 i40e_configure_registers(struct i40e_hw *hw)
9167 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9168 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9169 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9175 for (i = 0; i < RTE_DIM(reg_table); i++) {
9176 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9177 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9179 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9180 else /* For X710/XL710/XXV710 */
9182 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9185 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9186 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9188 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9189 else /* For X710/XL710/XXV710 */
9191 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9194 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9195 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9196 I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9198 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9201 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9204 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9207 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9211 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9212 reg_table[i].addr, reg);
9213 if (reg == reg_table[i].val)
9216 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9217 reg_table[i].val, NULL);
9220 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9221 reg_table[i].val, reg_table[i].addr);
9224 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9225 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9229 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
9230 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
9231 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
9232 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9234 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9239 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9240 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9244 /* Configure for double VLAN RX stripping */
9245 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9246 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9247 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9248 ret = i40e_aq_debug_write_register(hw,
9249 I40E_VSI_TSR(vsi->vsi_id),
9252 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9254 return I40E_ERR_CONFIG;
9258 /* Configure for double VLAN TX insertion */
9259 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9260 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9261 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9262 ret = i40e_aq_debug_write_register(hw,
9263 I40E_VSI_L2TAGSTXVALID(
9264 vsi->vsi_id), reg, NULL);
9267 "Failed to update VSI_L2TAGSTXVALID[%d]",
9269 return I40E_ERR_CONFIG;
9277 * i40e_aq_add_mirror_rule
9278 * @hw: pointer to the hardware structure
9279 * @seid: VEB seid to add mirror rule to
9280 * @dst_id: destination vsi seid
9281 * @entries: Buffer which contains the entities to be mirrored
9282 * @count: number of entities contained in the buffer
9283 * @rule_id:the rule_id of the rule to be added
9285 * Add a mirror rule for a given veb.
9288 static enum i40e_status_code
9289 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9290 uint16_t seid, uint16_t dst_id,
9291 uint16_t rule_type, uint16_t *entries,
9292 uint16_t count, uint16_t *rule_id)
9294 struct i40e_aq_desc desc;
9295 struct i40e_aqc_add_delete_mirror_rule cmd;
9296 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9297 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9300 enum i40e_status_code status;
9302 i40e_fill_default_direct_cmd_desc(&desc,
9303 i40e_aqc_opc_add_mirror_rule);
9304 memset(&cmd, 0, sizeof(cmd));
9306 buff_len = sizeof(uint16_t) * count;
9307 desc.datalen = rte_cpu_to_le_16(buff_len);
9309 desc.flags |= rte_cpu_to_le_16(
9310 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9311 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9312 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9313 cmd.num_entries = rte_cpu_to_le_16(count);
9314 cmd.seid = rte_cpu_to_le_16(seid);
9315 cmd.destination = rte_cpu_to_le_16(dst_id);
9317 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9318 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9320 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9321 hw->aq.asq_last_status, resp->rule_id,
9322 resp->mirror_rules_used, resp->mirror_rules_free);
9323 *rule_id = rte_le_to_cpu_16(resp->rule_id);
9329 * i40e_aq_del_mirror_rule
9330 * @hw: pointer to the hardware structure
9331 * @seid: VEB seid to add mirror rule to
9332 * @entries: Buffer which contains the entities to be mirrored
9333 * @count: number of entities contained in the buffer
9334 * @rule_id:the rule_id of the rule to be delete
9336 * Delete a mirror rule for a given veb.
9339 static enum i40e_status_code
9340 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9341 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9342 uint16_t count, uint16_t rule_id)
9344 struct i40e_aq_desc desc;
9345 struct i40e_aqc_add_delete_mirror_rule cmd;
9346 uint16_t buff_len = 0;
9347 enum i40e_status_code status;
9350 i40e_fill_default_direct_cmd_desc(&desc,
9351 i40e_aqc_opc_delete_mirror_rule);
9352 memset(&cmd, 0, sizeof(cmd));
9353 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9354 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9356 cmd.num_entries = count;
9357 buff_len = sizeof(uint16_t) * count;
9358 desc.datalen = rte_cpu_to_le_16(buff_len);
9359 buff = (void *)entries;
9361 /* rule id is filled in destination field for deleting mirror rule */
9362 cmd.destination = rte_cpu_to_le_16(rule_id);
9364 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9365 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9366 cmd.seid = rte_cpu_to_le_16(seid);
9368 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9369 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9375 * i40e_mirror_rule_set
9376 * @dev: pointer to the hardware structure
9377 * @mirror_conf: mirror rule info
9378 * @sw_id: mirror rule's sw_id
9379 * @on: enable/disable
9381 * set a mirror rule.
9385 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9386 struct rte_eth_mirror_conf *mirror_conf,
9387 uint8_t sw_id, uint8_t on)
9389 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9390 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9391 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9392 struct i40e_mirror_rule *parent = NULL;
9393 uint16_t seid, dst_seid, rule_id;
9397 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9399 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9401 "mirror rule can not be configured without veb or vfs.");
9404 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9405 PMD_DRV_LOG(ERR, "mirror table is full.");
9408 if (mirror_conf->dst_pool > pf->vf_num) {
9409 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9410 mirror_conf->dst_pool);
9414 seid = pf->main_vsi->veb->seid;
9416 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9417 if (sw_id <= it->index) {
9423 if (mirr_rule && sw_id == mirr_rule->index) {
9425 PMD_DRV_LOG(ERR, "mirror rule exists.");
9428 ret = i40e_aq_del_mirror_rule(hw, seid,
9429 mirr_rule->rule_type,
9431 mirr_rule->num_entries, mirr_rule->id);
9434 "failed to remove mirror rule: ret = %d, aq_err = %d.",
9435 ret, hw->aq.asq_last_status);
9438 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9439 rte_free(mirr_rule);
9440 pf->nb_mirror_rule--;
9444 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9448 mirr_rule = rte_zmalloc("i40e_mirror_rule",
9449 sizeof(struct i40e_mirror_rule) , 0);
9451 PMD_DRV_LOG(ERR, "failed to allocate memory");
9452 return I40E_ERR_NO_MEMORY;
9454 switch (mirror_conf->rule_type) {
9455 case ETH_MIRROR_VLAN:
9456 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9457 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9458 mirr_rule->entries[j] =
9459 mirror_conf->vlan.vlan_id[i];
9464 PMD_DRV_LOG(ERR, "vlan is not specified.");
9465 rte_free(mirr_rule);
9468 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9470 case ETH_MIRROR_VIRTUAL_POOL_UP:
9471 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9472 /* check if the specified pool bit is out of range */
9473 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9474 PMD_DRV_LOG(ERR, "pool mask is out of range.");
9475 rte_free(mirr_rule);
9478 for (i = 0, j = 0; i < pf->vf_num; i++) {
9479 if (mirror_conf->pool_mask & (1ULL << i)) {
9480 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9484 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9485 /* add pf vsi to entries */
9486 mirr_rule->entries[j] = pf->main_vsi_seid;
9490 PMD_DRV_LOG(ERR, "pool is not specified.");
9491 rte_free(mirr_rule);
9494 /* egress and ingress in aq commands means from switch but not port */
9495 mirr_rule->rule_type =
9496 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9497 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9498 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9500 case ETH_MIRROR_UPLINK_PORT:
9501 /* egress and ingress in aq commands means from switch but not port*/
9502 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9504 case ETH_MIRROR_DOWNLINK_PORT:
9505 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9508 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9509 mirror_conf->rule_type);
9510 rte_free(mirr_rule);
9514 /* If the dst_pool is equal to vf_num, consider it as PF */
9515 if (mirror_conf->dst_pool == pf->vf_num)
9516 dst_seid = pf->main_vsi_seid;
9518 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9520 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9521 mirr_rule->rule_type, mirr_rule->entries,
9525 "failed to add mirror rule: ret = %d, aq_err = %d.",
9526 ret, hw->aq.asq_last_status);
9527 rte_free(mirr_rule);
9531 mirr_rule->index = sw_id;
9532 mirr_rule->num_entries = j;
9533 mirr_rule->id = rule_id;
9534 mirr_rule->dst_vsi_seid = dst_seid;
9537 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9539 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9541 pf->nb_mirror_rule++;
9546 * i40e_mirror_rule_reset
9547 * @dev: pointer to the device
9548 * @sw_id: mirror rule's sw_id
9550 * reset a mirror rule.
9554 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9556 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9557 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9558 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9562 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9564 seid = pf->main_vsi->veb->seid;
9566 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9567 if (sw_id == it->index) {
9573 ret = i40e_aq_del_mirror_rule(hw, seid,
9574 mirr_rule->rule_type,
9576 mirr_rule->num_entries, mirr_rule->id);
9579 "failed to remove mirror rule: status = %d, aq_err = %d.",
9580 ret, hw->aq.asq_last_status);
9583 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9584 rte_free(mirr_rule);
9585 pf->nb_mirror_rule--;
9587 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9594 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9596 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9597 uint64_t systim_cycles;
9599 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9600 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9603 return systim_cycles;
9607 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9609 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9612 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9613 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9620 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9622 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9625 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9626 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9633 i40e_start_timecounters(struct rte_eth_dev *dev)
9635 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9636 struct i40e_adapter *adapter =
9637 (struct i40e_adapter *)dev->data->dev_private;
9638 struct rte_eth_link link;
9639 uint32_t tsync_inc_l;
9640 uint32_t tsync_inc_h;
9642 /* Get current link speed. */
9643 memset(&link, 0, sizeof(link));
9644 i40e_dev_link_update(dev, 1);
9645 rte_i40e_dev_atomic_read_link_status(dev, &link);
9647 switch (link.link_speed) {
9648 case ETH_SPEED_NUM_40G:
9649 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9650 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9652 case ETH_SPEED_NUM_10G:
9653 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9654 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9656 case ETH_SPEED_NUM_1G:
9657 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9658 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9665 /* Set the timesync increment value. */
9666 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9667 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9669 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9670 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9671 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9673 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9674 adapter->systime_tc.cc_shift = 0;
9675 adapter->systime_tc.nsec_mask = 0;
9677 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9678 adapter->rx_tstamp_tc.cc_shift = 0;
9679 adapter->rx_tstamp_tc.nsec_mask = 0;
9681 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9682 adapter->tx_tstamp_tc.cc_shift = 0;
9683 adapter->tx_tstamp_tc.nsec_mask = 0;
9687 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9689 struct i40e_adapter *adapter =
9690 (struct i40e_adapter *)dev->data->dev_private;
9692 adapter->systime_tc.nsec += delta;
9693 adapter->rx_tstamp_tc.nsec += delta;
9694 adapter->tx_tstamp_tc.nsec += delta;
9700 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9703 struct i40e_adapter *adapter =
9704 (struct i40e_adapter *)dev->data->dev_private;
9706 ns = rte_timespec_to_ns(ts);
9708 /* Set the timecounters to a new value. */
9709 adapter->systime_tc.nsec = ns;
9710 adapter->rx_tstamp_tc.nsec = ns;
9711 adapter->tx_tstamp_tc.nsec = ns;
9717 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9719 uint64_t ns, systime_cycles;
9720 struct i40e_adapter *adapter =
9721 (struct i40e_adapter *)dev->data->dev_private;
9723 systime_cycles = i40e_read_systime_cyclecounter(dev);
9724 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9725 *ts = rte_ns_to_timespec(ns);
9731 i40e_timesync_enable(struct rte_eth_dev *dev)
9733 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9734 uint32_t tsync_ctl_l;
9735 uint32_t tsync_ctl_h;
9737 /* Stop the timesync system time. */
9738 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9739 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9740 /* Reset the timesync system time value. */
9741 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9742 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9744 i40e_start_timecounters(dev);
9746 /* Clear timesync registers. */
9747 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9748 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9749 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9750 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9751 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9752 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9754 /* Enable timestamping of PTP packets. */
9755 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9756 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9758 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9759 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9760 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9762 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9763 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9769 i40e_timesync_disable(struct rte_eth_dev *dev)
9771 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9772 uint32_t tsync_ctl_l;
9773 uint32_t tsync_ctl_h;
9775 /* Disable timestamping of transmitted PTP packets. */
9776 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9777 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9779 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9780 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9782 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9783 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9785 /* Reset the timesync increment value. */
9786 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9787 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9793 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9794 struct timespec *timestamp, uint32_t flags)
9796 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9797 struct i40e_adapter *adapter =
9798 (struct i40e_adapter *)dev->data->dev_private;
9800 uint32_t sync_status;
9801 uint32_t index = flags & 0x03;
9802 uint64_t rx_tstamp_cycles;
9805 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9806 if ((sync_status & (1 << index)) == 0)
9809 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9810 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9811 *timestamp = rte_ns_to_timespec(ns);
9817 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9818 struct timespec *timestamp)
9820 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9821 struct i40e_adapter *adapter =
9822 (struct i40e_adapter *)dev->data->dev_private;
9824 uint32_t sync_status;
9825 uint64_t tx_tstamp_cycles;
9828 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9829 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9832 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9833 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9834 *timestamp = rte_ns_to_timespec(ns);
9840 * i40e_parse_dcb_configure - parse dcb configure from user
9841 * @dev: the device being configured
9842 * @dcb_cfg: pointer of the result of parse
9843 * @*tc_map: bit map of enabled traffic classes
9845 * Returns 0 on success, negative value on failure
9848 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9849 struct i40e_dcbx_config *dcb_cfg,
9852 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9853 uint8_t i, tc_bw, bw_lf;
9855 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9857 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9858 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9859 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9863 /* assume each tc has the same bw */
9864 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9865 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9866 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9867 /* to ensure the sum of tcbw is equal to 100 */
9868 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9869 for (i = 0; i < bw_lf; i++)
9870 dcb_cfg->etscfg.tcbwtable[i]++;
9872 /* assume each tc has the same Transmission Selection Algorithm */
9873 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9874 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9876 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9877 dcb_cfg->etscfg.prioritytable[i] =
9878 dcb_rx_conf->dcb_tc[i];
9880 /* FW needs one App to configure HW */
9881 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9882 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9883 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9884 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9886 if (dcb_rx_conf->nb_tcs == 0)
9887 *tc_map = 1; /* tc0 only */
9889 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9891 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9892 dcb_cfg->pfc.willing = 0;
9893 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9894 dcb_cfg->pfc.pfcenable = *tc_map;
9900 static enum i40e_status_code
9901 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9902 struct i40e_aqc_vsi_properties_data *info,
9903 uint8_t enabled_tcmap)
9905 enum i40e_status_code ret;
9906 int i, total_tc = 0;
9907 uint16_t qpnum_per_tc, bsf, qp_idx;
9908 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9909 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9910 uint16_t used_queues;
9912 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9913 if (ret != I40E_SUCCESS)
9916 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9917 if (enabled_tcmap & (1 << i))
9922 vsi->enabled_tc = enabled_tcmap;
9924 /* different VSI has different queues assigned */
9925 if (vsi->type == I40E_VSI_MAIN)
9926 used_queues = dev_data->nb_rx_queues -
9927 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9928 else if (vsi->type == I40E_VSI_VMDQ2)
9929 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9931 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9932 return I40E_ERR_NO_AVAILABLE_VSI;
9935 qpnum_per_tc = used_queues / total_tc;
9936 /* Number of queues per enabled TC */
9937 if (qpnum_per_tc == 0) {
9938 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9939 return I40E_ERR_INVALID_QP_ID;
9941 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9943 bsf = rte_bsf32(qpnum_per_tc);
9946 * Configure TC and queue mapping parameters, for enabled TC,
9947 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9948 * default queue will serve it.
9951 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9952 if (vsi->enabled_tc & (1 << i)) {
9953 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9954 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9955 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9956 qp_idx += qpnum_per_tc;
9958 info->tc_mapping[i] = 0;
9961 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9962 if (vsi->type == I40E_VSI_SRIOV) {
9963 info->mapping_flags |=
9964 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9965 for (i = 0; i < vsi->nb_qps; i++)
9966 info->queue_mapping[i] =
9967 rte_cpu_to_le_16(vsi->base_queue + i);
9969 info->mapping_flags |=
9970 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9971 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9973 info->valid_sections |=
9974 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9976 return I40E_SUCCESS;
9980 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9981 * @veb: VEB to be configured
9982 * @tc_map: enabled TC bitmap
9984 * Returns 0 on success, negative value on failure
9986 static enum i40e_status_code
9987 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9989 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9990 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9991 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9992 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9993 enum i40e_status_code ret = I40E_SUCCESS;
9997 /* Check if enabled_tc is same as existing or new TCs */
9998 if (veb->enabled_tc == tc_map)
10001 /* configure tc bandwidth */
10002 memset(&veb_bw, 0, sizeof(veb_bw));
10003 veb_bw.tc_valid_bits = tc_map;
10004 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10005 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10006 if (tc_map & BIT_ULL(i))
10007 veb_bw.tc_bw_share_credits[i] = 1;
10009 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10013 "AQ command Config switch_comp BW allocation per TC failed = %d",
10014 hw->aq.asq_last_status);
10018 memset(&ets_query, 0, sizeof(ets_query));
10019 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10021 if (ret != I40E_SUCCESS) {
10023 "Failed to get switch_comp ETS configuration %u",
10024 hw->aq.asq_last_status);
10027 memset(&bw_query, 0, sizeof(bw_query));
10028 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10030 if (ret != I40E_SUCCESS) {
10032 "Failed to get switch_comp bandwidth configuration %u",
10033 hw->aq.asq_last_status);
10037 /* store and print out BW info */
10038 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10039 veb->bw_info.bw_max = ets_query.tc_bw_max;
10040 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10041 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10042 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10043 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10044 I40E_16_BIT_WIDTH);
10045 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10046 veb->bw_info.bw_ets_share_credits[i] =
10047 bw_query.tc_bw_share_credits[i];
10048 veb->bw_info.bw_ets_credits[i] =
10049 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10050 /* 4 bits per TC, 4th bit is reserved */
10051 veb->bw_info.bw_ets_max[i] =
10052 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10053 RTE_LEN2MASK(3, uint8_t));
10054 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10055 veb->bw_info.bw_ets_share_credits[i]);
10056 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10057 veb->bw_info.bw_ets_credits[i]);
10058 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10059 veb->bw_info.bw_ets_max[i]);
10062 veb->enabled_tc = tc_map;
10069 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10070 * @vsi: VSI to be configured
10071 * @tc_map: enabled TC bitmap
10073 * Returns 0 on success, negative value on failure
10075 static enum i40e_status_code
10076 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10078 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10079 struct i40e_vsi_context ctxt;
10080 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10081 enum i40e_status_code ret = I40E_SUCCESS;
10084 /* Check if enabled_tc is same as existing or new TCs */
10085 if (vsi->enabled_tc == tc_map)
10088 /* configure tc bandwidth */
10089 memset(&bw_data, 0, sizeof(bw_data));
10090 bw_data.tc_valid_bits = tc_map;
10091 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10092 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10093 if (tc_map & BIT_ULL(i))
10094 bw_data.tc_bw_credits[i] = 1;
10096 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10099 "AQ command Config VSI BW allocation per TC failed = %d",
10100 hw->aq.asq_last_status);
10103 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10104 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10106 /* Update Queue Pairs Mapping for currently enabled UPs */
10107 ctxt.seid = vsi->seid;
10108 ctxt.pf_num = hw->pf_id;
10110 ctxt.uplink_seid = vsi->uplink_seid;
10111 ctxt.info = vsi->info;
10113 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10117 /* Update the VSI after updating the VSI queue-mapping information */
10118 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10120 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10121 hw->aq.asq_last_status);
10124 /* update the local VSI info with updated queue map */
10125 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10126 sizeof(vsi->info.tc_mapping));
10127 (void)rte_memcpy(&vsi->info.queue_mapping,
10128 &ctxt.info.queue_mapping,
10129 sizeof(vsi->info.queue_mapping));
10130 vsi->info.mapping_flags = ctxt.info.mapping_flags;
10131 vsi->info.valid_sections = 0;
10133 /* query and update current VSI BW information */
10134 ret = i40e_vsi_get_bw_config(vsi);
10137 "Failed updating vsi bw info, err %s aq_err %s",
10138 i40e_stat_str(hw, ret),
10139 i40e_aq_str(hw, hw->aq.asq_last_status));
10143 vsi->enabled_tc = tc_map;
10150 * i40e_dcb_hw_configure - program the dcb setting to hw
10151 * @pf: pf the configuration is taken on
10152 * @new_cfg: new configuration
10153 * @tc_map: enabled TC bitmap
10155 * Returns 0 on success, negative value on failure
10157 static enum i40e_status_code
10158 i40e_dcb_hw_configure(struct i40e_pf *pf,
10159 struct i40e_dcbx_config *new_cfg,
10162 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10163 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10164 struct i40e_vsi *main_vsi = pf->main_vsi;
10165 struct i40e_vsi_list *vsi_list;
10166 enum i40e_status_code ret;
10170 /* Use the FW API if FW > v4.4*/
10171 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10172 (hw->aq.fw_maj_ver >= 5))) {
10174 "FW < v4.4, can not use FW LLDP API to configure DCB");
10175 return I40E_ERR_FIRMWARE_API_VERSION;
10178 /* Check if need reconfiguration */
10179 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10180 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10181 return I40E_SUCCESS;
10184 /* Copy the new config to the current config */
10185 *old_cfg = *new_cfg;
10186 old_cfg->etsrec = old_cfg->etscfg;
10187 ret = i40e_set_dcb_config(hw);
10189 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10190 i40e_stat_str(hw, ret),
10191 i40e_aq_str(hw, hw->aq.asq_last_status));
10194 /* set receive Arbiter to RR mode and ETS scheme by default */
10195 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10196 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10197 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
10198 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10199 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10200 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10201 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10202 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10203 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10204 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10205 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10206 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10207 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10209 /* get local mib to check whether it is configured correctly */
10211 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10212 /* Get Local DCB Config */
10213 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10214 &hw->local_dcbx_config);
10216 /* if Veb is created, need to update TC of it at first */
10217 if (main_vsi->veb) {
10218 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10220 PMD_INIT_LOG(WARNING,
10221 "Failed configuring TC for VEB seid=%d",
10222 main_vsi->veb->seid);
10224 /* Update each VSI */
10225 i40e_vsi_config_tc(main_vsi, tc_map);
10226 if (main_vsi->veb) {
10227 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10228 /* Beside main VSI and VMDQ VSIs, only enable default
10229 * TC for other VSIs
10231 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10232 ret = i40e_vsi_config_tc(vsi_list->vsi,
10235 ret = i40e_vsi_config_tc(vsi_list->vsi,
10236 I40E_DEFAULT_TCMAP);
10238 PMD_INIT_LOG(WARNING,
10239 "Failed configuring TC for VSI seid=%d",
10240 vsi_list->vsi->seid);
10244 return I40E_SUCCESS;
10248 * i40e_dcb_init_configure - initial dcb config
10249 * @dev: device being configured
10250 * @sw_dcb: indicate whether dcb is sw configured or hw offload
10252 * Returns 0 on success, negative value on failure
10255 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10257 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10258 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10261 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10262 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10266 /* DCB initialization:
10267 * Update DCB configuration from the Firmware and configure
10268 * LLDP MIB change event.
10270 if (sw_dcb == TRUE) {
10271 ret = i40e_init_dcb(hw);
10272 /* If lldp agent is stopped, the return value from
10273 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10274 * adminq status. Otherwise, it should return success.
10276 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10277 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10278 memset(&hw->local_dcbx_config, 0,
10279 sizeof(struct i40e_dcbx_config));
10280 /* set dcb default configuration */
10281 hw->local_dcbx_config.etscfg.willing = 0;
10282 hw->local_dcbx_config.etscfg.maxtcs = 0;
10283 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10284 hw->local_dcbx_config.etscfg.tsatable[0] =
10286 /* all UPs mapping to TC0 */
10287 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10288 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10289 hw->local_dcbx_config.etsrec =
10290 hw->local_dcbx_config.etscfg;
10291 hw->local_dcbx_config.pfc.willing = 0;
10292 hw->local_dcbx_config.pfc.pfccap =
10293 I40E_MAX_TRAFFIC_CLASS;
10294 /* FW needs one App to configure HW */
10295 hw->local_dcbx_config.numapps = 1;
10296 hw->local_dcbx_config.app[0].selector =
10297 I40E_APP_SEL_ETHTYPE;
10298 hw->local_dcbx_config.app[0].priority = 3;
10299 hw->local_dcbx_config.app[0].protocolid =
10300 I40E_APP_PROTOID_FCOE;
10301 ret = i40e_set_dcb_config(hw);
10304 "default dcb config fails. err = %d, aq_err = %d.",
10305 ret, hw->aq.asq_last_status);
10310 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10311 ret, hw->aq.asq_last_status);
10315 ret = i40e_aq_start_lldp(hw, NULL);
10316 if (ret != I40E_SUCCESS)
10317 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10319 ret = i40e_init_dcb(hw);
10321 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10323 "HW doesn't support DCBX offload.");
10328 "DCBX configuration failed, err = %d, aq_err = %d.",
10329 ret, hw->aq.asq_last_status);
10337 * i40e_dcb_setup - setup dcb related config
10338 * @dev: device being configured
10340 * Returns 0 on success, negative value on failure
10343 i40e_dcb_setup(struct rte_eth_dev *dev)
10345 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10346 struct i40e_dcbx_config dcb_cfg;
10347 uint8_t tc_map = 0;
10350 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10351 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10355 if (pf->vf_num != 0)
10356 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10358 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10360 PMD_INIT_LOG(ERR, "invalid dcb config");
10363 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10365 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10373 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10374 struct rte_eth_dcb_info *dcb_info)
10376 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10377 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10378 struct i40e_vsi *vsi = pf->main_vsi;
10379 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10380 uint16_t bsf, tc_mapping;
10383 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10384 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10386 dcb_info->nb_tcs = 1;
10387 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10388 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10389 for (i = 0; i < dcb_info->nb_tcs; i++)
10390 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10392 /* get queue mapping if vmdq is disabled */
10393 if (!pf->nb_cfg_vmdq_vsi) {
10394 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10395 if (!(vsi->enabled_tc & (1 << i)))
10397 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10398 dcb_info->tc_queue.tc_rxq[j][i].base =
10399 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10400 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10401 dcb_info->tc_queue.tc_txq[j][i].base =
10402 dcb_info->tc_queue.tc_rxq[j][i].base;
10403 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10404 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10405 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10406 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10407 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10412 /* get queue mapping if vmdq is enabled */
10414 vsi = pf->vmdq[j].vsi;
10415 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10416 if (!(vsi->enabled_tc & (1 << i)))
10418 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10419 dcb_info->tc_queue.tc_rxq[j][i].base =
10420 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10421 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10422 dcb_info->tc_queue.tc_txq[j][i].base =
10423 dcb_info->tc_queue.tc_rxq[j][i].base;
10424 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10425 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10426 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10427 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10428 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10431 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10436 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10438 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10439 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10440 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10441 uint16_t interval =
10442 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10443 uint16_t msix_intr;
10445 msix_intr = intr_handle->intr_vec[queue_id];
10446 if (msix_intr == I40E_MISC_VEC_ID)
10447 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10448 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10449 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10450 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10452 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10455 I40E_PFINT_DYN_CTLN(msix_intr -
10456 I40E_RX_VEC_START),
10457 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10458 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10459 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10461 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10463 I40E_WRITE_FLUSH(hw);
10464 rte_intr_enable(&pci_dev->intr_handle);
10470 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10472 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10473 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10474 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10475 uint16_t msix_intr;
10477 msix_intr = intr_handle->intr_vec[queue_id];
10478 if (msix_intr == I40E_MISC_VEC_ID)
10479 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10482 I40E_PFINT_DYN_CTLN(msix_intr -
10483 I40E_RX_VEC_START),
10485 I40E_WRITE_FLUSH(hw);
10490 static int i40e_get_regs(struct rte_eth_dev *dev,
10491 struct rte_dev_reg_info *regs)
10493 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10494 uint32_t *ptr_data = regs->data;
10495 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10496 const struct i40e_reg_info *reg_info;
10498 if (ptr_data == NULL) {
10499 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10500 regs->width = sizeof(uint32_t);
10504 /* The first few registers have to be read using AQ operations */
10506 while (i40e_regs_adminq[reg_idx].name) {
10507 reg_info = &i40e_regs_adminq[reg_idx++];
10508 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10510 arr_idx2 <= reg_info->count2;
10512 reg_offset = arr_idx * reg_info->stride1 +
10513 arr_idx2 * reg_info->stride2;
10514 reg_offset += reg_info->base_addr;
10515 ptr_data[reg_offset >> 2] =
10516 i40e_read_rx_ctl(hw, reg_offset);
10520 /* The remaining registers can be read using primitives */
10522 while (i40e_regs_others[reg_idx].name) {
10523 reg_info = &i40e_regs_others[reg_idx++];
10524 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10526 arr_idx2 <= reg_info->count2;
10528 reg_offset = arr_idx * reg_info->stride1 +
10529 arr_idx2 * reg_info->stride2;
10530 reg_offset += reg_info->base_addr;
10531 ptr_data[reg_offset >> 2] =
10532 I40E_READ_REG(hw, reg_offset);
10539 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10541 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10543 /* Convert word count to byte count */
10544 return hw->nvm.sr_size << 1;
10547 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10548 struct rte_dev_eeprom_info *eeprom)
10550 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10551 uint16_t *data = eeprom->data;
10552 uint16_t offset, length, cnt_words;
10555 offset = eeprom->offset >> 1;
10556 length = eeprom->length >> 1;
10557 cnt_words = length;
10559 if (offset > hw->nvm.sr_size ||
10560 offset + length > hw->nvm.sr_size) {
10561 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10565 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10567 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10568 if (ret_code != I40E_SUCCESS || cnt_words != length) {
10569 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10576 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10577 struct ether_addr *mac_addr)
10579 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10581 if (!is_valid_assigned_ether_addr(mac_addr)) {
10582 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10586 /* Flags: 0x3 updates port address */
10587 i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10591 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10593 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10594 struct rte_eth_dev_data *dev_data = pf->dev_data;
10595 uint32_t frame_size = mtu + ETHER_HDR_LEN
10596 + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
10599 /* check if mtu is within the allowed range */
10600 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10603 /* mtu setting is forbidden if port is start */
10604 if (dev_data->dev_started) {
10605 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10606 dev_data->port_id);
10610 if (frame_size > ETHER_MAX_LEN)
10611 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10613 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10615 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10620 /* Restore ethertype filter */
10622 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10624 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10625 struct i40e_ethertype_filter_list
10626 *ethertype_list = &pf->ethertype.ethertype_list;
10627 struct i40e_ethertype_filter *f;
10628 struct i40e_control_filter_stats stats;
10631 TAILQ_FOREACH(f, ethertype_list, rules) {
10633 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10634 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10635 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10636 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10637 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10639 memset(&stats, 0, sizeof(stats));
10640 i40e_aq_add_rem_control_packet_filter(hw,
10641 f->input.mac_addr.addr_bytes,
10642 f->input.ether_type,
10643 flags, pf->main_vsi->seid,
10644 f->queue, 1, &stats, NULL);
10646 PMD_DRV_LOG(INFO, "Ethertype filter:"
10647 " mac_etype_used = %u, etype_used = %u,"
10648 " mac_etype_free = %u, etype_free = %u",
10649 stats.mac_etype_used, stats.etype_used,
10650 stats.mac_etype_free, stats.etype_free);
10653 /* Restore tunnel filter */
10655 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10657 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10658 struct i40e_vsi *vsi;
10659 struct i40e_pf_vf *vf;
10660 struct i40e_tunnel_filter_list
10661 *tunnel_list = &pf->tunnel.tunnel_list;
10662 struct i40e_tunnel_filter *f;
10663 struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
10664 bool big_buffer = 0;
10666 TAILQ_FOREACH(f, tunnel_list, rules) {
10668 vsi = pf->main_vsi;
10670 vf = &pf->vfs[f->vf_id];
10673 memset(&cld_filter, 0, sizeof(cld_filter));
10674 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
10675 (struct ether_addr *)&cld_filter.element.outer_mac);
10676 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
10677 (struct ether_addr *)&cld_filter.element.inner_mac);
10678 cld_filter.element.inner_vlan = f->input.inner_vlan;
10679 cld_filter.element.flags = f->input.flags;
10680 cld_filter.element.tenant_id = f->input.tenant_id;
10681 cld_filter.element.queue_number = f->queue;
10682 rte_memcpy(cld_filter.general_fields,
10683 f->input.general_fields,
10684 sizeof(f->input.general_fields));
10686 if (((f->input.flags &
10687 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ==
10688 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ||
10690 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ==
10691 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ||
10693 I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ) ==
10694 I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ))
10698 i40e_aq_add_cloud_filters_big_buffer(hw,
10699 vsi->seid, &cld_filter, 1);
10701 i40e_aq_add_cloud_filters(hw, vsi->seid,
10702 &cld_filter.element, 1);
10707 i40e_filter_restore(struct i40e_pf *pf)
10709 i40e_ethertype_filter_restore(pf);
10710 i40e_tunnel_filter_restore(pf);
10711 i40e_fdir_filter_restore(pf);
10715 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
10717 if (strcmp(dev->data->drv_name,
10725 is_i40e_supported(struct rte_eth_dev *dev)
10727 return is_device_supported(dev, &rte_i40e_pmd);
10730 /* Create a QinQ cloud filter
10732 * The Fortville NIC has limited resources for tunnel filters,
10733 * so we can only reuse existing filters.
10735 * In step 1 we define which Field Vector fields can be used for
10737 * As we do not have the inner tag defined as a field,
10738 * we have to define it first, by reusing one of L1 entries.
10740 * In step 2 we are replacing one of existing filter types with
10741 * a new one for QinQ.
10742 * As we reusing L1 and replacing L2, some of the default filter
10743 * types will disappear,which depends on L1 and L2 entries we reuse.
10745 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
10747 * 1. Create L1 filter of outer vlan (12b) which will be in use
10748 * later when we define the cloud filter.
10749 * a. Valid_flags.replace_cloud = 0
10750 * b. Old_filter = 10 (Stag_Inner_Vlan)
10751 * c. New_filter = 0x10
10752 * d. TR bit = 0xff (optional, not used here)
10753 * e. Buffer – 2 entries:
10754 * i. Byte 0 = 8 (outer vlan FV index).
10756 * Byte 2-3 = 0x0fff
10757 * ii. Byte 0 = 37 (inner vlan FV index).
10759 * Byte 2-3 = 0x0fff
10762 * 2. Create cloud filter using two L1 filters entries: stag and
10763 * new filter(outer vlan+ inner vlan)
10764 * a. Valid_flags.replace_cloud = 1
10765 * b. Old_filter = 1 (instead of outer IP)
10766 * c. New_filter = 0x10
10767 * d. Buffer – 2 entries:
10768 * i. Byte 0 = 0x80 | 7 (valid | Stag).
10769 * Byte 1-3 = 0 (rsv)
10770 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
10771 * Byte 9-11 = 0 (rsv)
10774 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
10776 int ret = -ENOTSUP;
10777 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
10778 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
10779 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10782 memset(&filter_replace, 0,
10783 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
10784 memset(&filter_replace_buf, 0,
10785 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
10787 /* create L1 filter */
10788 filter_replace.old_filter_type =
10789 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
10790 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10791 filter_replace.tr_bit = 0;
10793 /* Prepare the buffer, 2 entries */
10794 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
10795 filter_replace_buf.data[0] |=
10796 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10797 /* Field Vector 12b mask */
10798 filter_replace_buf.data[2] = 0xff;
10799 filter_replace_buf.data[3] = 0x0f;
10800 filter_replace_buf.data[4] =
10801 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
10802 filter_replace_buf.data[4] |=
10803 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10804 /* Field Vector 12b mask */
10805 filter_replace_buf.data[6] = 0xff;
10806 filter_replace_buf.data[7] = 0x0f;
10807 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
10808 &filter_replace_buf);
10809 if (ret != I40E_SUCCESS)
10812 /* Apply the second L2 cloud filter */
10813 memset(&filter_replace, 0,
10814 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
10815 memset(&filter_replace_buf, 0,
10816 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
10818 /* create L2 filter, input for L2 filter will be L1 filter */
10819 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
10820 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
10821 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10823 /* Prepare the buffer, 2 entries */
10824 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
10825 filter_replace_buf.data[0] |=
10826 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10827 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10828 filter_replace_buf.data[4] |=
10829 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10830 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
10831 &filter_replace_buf);
10835 RTE_INIT(i40e_init_log);
10837 i40e_init_log(void)
10839 i40e_logtype_init = rte_log_register("pmd.i40e.init");
10840 if (i40e_logtype_init >= 0)
10841 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
10842 i40e_logtype_driver = rte_log_register("pmd.i40e.driver");
10843 if (i40e_logtype_driver >= 0)
10844 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);