4 * Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
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13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
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22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 #include <rte_string_fns.h>
45 #include <rte_ether.h>
46 #include <rte_ethdev.h>
47 #include <rte_memzone.h>
48 #include <rte_malloc.h>
49 #include <rte_memcpy.h>
50 #include <rte_alarm.h>
52 #include <rte_eth_ctrl.h>
53 #include <rte_tailq.h>
55 #include "i40e_logs.h"
56 #include "base/i40e_prototype.h"
57 #include "base/i40e_adminq_cmd.h"
58 #include "base/i40e_type.h"
59 #include "base/i40e_register.h"
60 #include "base/i40e_dcb.h"
61 #include "i40e_ethdev.h"
62 #include "i40e_rxtx.h"
64 #include "i40e_regs.h"
66 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
67 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
69 #define I40E_CLEAR_PXE_WAIT_MS 200
71 /* Maximun number of capability elements */
72 #define I40E_MAX_CAP_ELE_NUM 128
74 /* Wait count and inteval */
75 #define I40E_CHK_Q_ENA_COUNT 1000
76 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
78 /* Maximun number of VSI */
79 #define I40E_MAX_NUM_VSIS (384UL)
81 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
83 /* Flow control default timer */
84 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
86 /* Flow control default high water */
87 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
89 /* Flow control default low water */
90 #define I40E_DEFAULT_LOW_WATER (0x1A40/1024)
92 /* Flow control enable fwd bit */
93 #define I40E_PRTMAC_FWD_CTRL 0x00000001
95 /* Receive Packet Buffer size */
96 #define I40E_RXPBSIZE (968 * 1024)
99 #define I40E_KILOSHIFT 10
101 /* Receive Average Packet Size in Byte*/
102 #define I40E_PACKET_AVERAGE_SIZE 128
104 /* Mask of PF interrupt causes */
105 #define I40E_PFINT_ICR0_ENA_MASK ( \
106 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
107 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
108 I40E_PFINT_ICR0_ENA_GRST_MASK | \
109 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
110 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
111 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
112 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
113 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
114 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
115 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
117 #define I40E_FLOW_TYPES ( \
118 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
119 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
120 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
121 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
122 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
123 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
124 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
125 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
126 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
127 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
128 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
130 /* Additional timesync values. */
131 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
132 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
133 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
134 #define I40E_PRTTSYN_TSYNENA 0x80000000
135 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
136 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
138 #define I40E_MAX_PERCENT 100
139 #define I40E_DEFAULT_DCB_APP_NUM 1
140 #define I40E_DEFAULT_DCB_APP_PRIO 3
142 #define I40E_INSET_NONE 0x00000000000000000ULL
145 #define I40E_INSET_DMAC 0x0000000000000001ULL
146 #define I40E_INSET_SMAC 0x0000000000000002ULL
147 #define I40E_INSET_VLAN_OUTER 0x0000000000000004ULL
148 #define I40E_INSET_VLAN_INNER 0x0000000000000008ULL
149 #define I40E_INSET_VLAN_TUNNEL 0x0000000000000010ULL
152 #define I40E_INSET_IPV4_SRC 0x0000000000000100ULL
153 #define I40E_INSET_IPV4_DST 0x0000000000000200ULL
154 #define I40E_INSET_IPV6_SRC 0x0000000000000400ULL
155 #define I40E_INSET_IPV6_DST 0x0000000000000800ULL
156 #define I40E_INSET_SRC_PORT 0x0000000000001000ULL
157 #define I40E_INSET_DST_PORT 0x0000000000002000ULL
158 #define I40E_INSET_SCTP_VT 0x0000000000004000ULL
160 /* bit 16 ~ bit 31 */
161 #define I40E_INSET_IPV4_TOS 0x0000000000010000ULL
162 #define I40E_INSET_IPV4_PROTO 0x0000000000020000ULL
163 #define I40E_INSET_IPV4_TTL 0x0000000000040000ULL
164 #define I40E_INSET_IPV6_TC 0x0000000000080000ULL
165 #define I40E_INSET_IPV6_FLOW 0x0000000000100000ULL
166 #define I40E_INSET_IPV6_NEXT_HDR 0x0000000000200000ULL
167 #define I40E_INSET_IPV6_HOP_LIMIT 0x0000000000400000ULL
168 #define I40E_INSET_TCP_FLAGS 0x0000000000800000ULL
170 /* bit 32 ~ bit 47, tunnel fields */
171 #define I40E_INSET_TUNNEL_IPV4_DST 0x0000000100000000ULL
172 #define I40E_INSET_TUNNEL_IPV6_DST 0x0000000200000000ULL
173 #define I40E_INSET_TUNNEL_DMAC 0x0000000400000000ULL
174 #define I40E_INSET_TUNNEL_SRC_PORT 0x0000000800000000ULL
175 #define I40E_INSET_TUNNEL_DST_PORT 0x0000001000000000ULL
176 #define I40E_INSET_TUNNEL_ID 0x0000002000000000ULL
178 /* bit 48 ~ bit 55 */
179 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
181 /* bit 56 ~ bit 63, Flex Payload */
182 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
183 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
184 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
185 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
186 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
187 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
188 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
189 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
190 #define I40E_INSET_FLEX_PAYLOAD \
191 (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
192 I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
193 I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
194 I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
197 * Below are values for writing un-exposed registers suggested
200 /* Destination MAC address */
201 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
202 /* Source MAC address */
203 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
204 /* Outer (S-Tag) VLAN tag in the outer L2 header */
205 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
206 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
207 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
208 /* Single VLAN tag in the inner L2 header */
209 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
210 /* Source IPv4 address */
211 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
212 /* Destination IPv4 address */
213 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
214 /* Source IPv4 address for X722 */
215 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
216 /* Destination IPv4 address for X722 */
217 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
218 /* IPv4 Protocol for X722 */
219 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
220 /* IPv4 Time to Live for X722 */
221 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
222 /* IPv4 Type of Service (TOS) */
223 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
225 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
226 /* IPv4 Time to Live */
227 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
228 /* Source IPv6 address */
229 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
230 /* Destination IPv6 address */
231 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
232 /* IPv6 Traffic Class (TC) */
233 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
234 /* IPv6 Next Header */
235 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
237 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
239 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
240 /* Destination L4 port */
241 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
242 /* SCTP verification tag */
243 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
244 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
245 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
246 /* Source port of tunneling UDP */
247 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
248 /* Destination port of tunneling UDP */
249 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
250 /* UDP Tunneling ID, NVGRE/GRE key */
251 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
252 /* Last ether type */
253 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
254 /* Tunneling outer destination IPv4 address */
255 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
256 /* Tunneling outer destination IPv6 address */
257 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
258 /* 1st word of flex payload */
259 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
260 /* 2nd word of flex payload */
261 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
262 /* 3rd word of flex payload */
263 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
264 /* 4th word of flex payload */
265 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
266 /* 5th word of flex payload */
267 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
268 /* 6th word of flex payload */
269 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
270 /* 7th word of flex payload */
271 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
272 /* 8th word of flex payload */
273 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
274 /* all 8 words flex payload */
275 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
276 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
278 #define I40E_TRANSLATE_INSET 0
279 #define I40E_TRANSLATE_REG 1
281 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
282 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
283 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
284 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
285 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
286 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
288 #define I40E_GL_SWT_L2TAGCTRL(_i) (0x001C0A70 + ((_i) * 4))
289 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
290 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK \
291 I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
293 /* PCI offset for querying capability */
294 #define PCI_DEV_CAP_REG 0xA4
295 /* PCI offset for enabling/disabling Extended Tag */
296 #define PCI_DEV_CTRL_REG 0xA8
297 /* Bit mask of Extended Tag capability */
298 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
299 /* Bit shift of Extended Tag enable/disable */
300 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
301 /* Bit mask of Extended Tag enable/disable */
302 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
304 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
305 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
306 static int i40e_dev_configure(struct rte_eth_dev *dev);
307 static int i40e_dev_start(struct rte_eth_dev *dev);
308 static void i40e_dev_stop(struct rte_eth_dev *dev);
309 static void i40e_dev_close(struct rte_eth_dev *dev);
310 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
311 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
312 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
313 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
314 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
315 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
316 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
317 struct rte_eth_stats *stats);
318 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
319 struct rte_eth_xstat *xstats, unsigned n);
320 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
321 struct rte_eth_xstat_name *xstats_names,
323 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
324 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
328 static void i40e_dev_info_get(struct rte_eth_dev *dev,
329 struct rte_eth_dev_info *dev_info);
330 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
333 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
334 enum rte_vlan_type vlan_type,
336 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
337 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
340 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
341 static int i40e_dev_led_on(struct rte_eth_dev *dev);
342 static int i40e_dev_led_off(struct rte_eth_dev *dev);
343 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
344 struct rte_eth_fc_conf *fc_conf);
345 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
346 struct rte_eth_fc_conf *fc_conf);
347 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
348 struct rte_eth_pfc_conf *pfc_conf);
349 static void i40e_macaddr_add(struct rte_eth_dev *dev,
350 struct ether_addr *mac_addr,
353 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
354 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
355 struct rte_eth_rss_reta_entry64 *reta_conf,
357 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
358 struct rte_eth_rss_reta_entry64 *reta_conf,
361 static int i40e_get_cap(struct i40e_hw *hw);
362 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
363 static int i40e_pf_setup(struct i40e_pf *pf);
364 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
365 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
366 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
367 static int i40e_dcb_setup(struct rte_eth_dev *dev);
368 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
369 bool offset_loaded, uint64_t *offset, uint64_t *stat);
370 static void i40e_stat_update_48(struct i40e_hw *hw,
376 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
377 static void i40e_dev_interrupt_handler(
378 __rte_unused struct rte_intr_handle *handle, void *param);
379 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
380 uint32_t base, uint32_t num);
381 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
382 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
384 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
386 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
387 static int i40e_veb_release(struct i40e_veb *veb);
388 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
389 struct i40e_vsi *vsi);
390 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
391 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
392 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
393 struct i40e_macvlan_filter *mv_f,
395 struct ether_addr *addr);
396 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
397 struct i40e_macvlan_filter *mv_f,
400 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
401 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
402 struct rte_eth_rss_conf *rss_conf);
403 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
404 struct rte_eth_rss_conf *rss_conf);
405 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
406 struct rte_eth_udp_tunnel *udp_tunnel);
407 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
408 struct rte_eth_udp_tunnel *udp_tunnel);
409 static void i40e_filter_input_set_init(struct i40e_pf *pf);
410 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
411 struct rte_eth_ethertype_filter *filter,
413 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
414 enum rte_filter_op filter_op,
416 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
417 enum rte_filter_type filter_type,
418 enum rte_filter_op filter_op,
420 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
421 struct rte_eth_dcb_info *dcb_info);
422 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
423 static void i40e_configure_registers(struct i40e_hw *hw);
424 static void i40e_hw_init(struct rte_eth_dev *dev);
425 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
426 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
427 struct rte_eth_mirror_conf *mirror_conf,
428 uint8_t sw_id, uint8_t on);
429 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
431 static int i40e_timesync_enable(struct rte_eth_dev *dev);
432 static int i40e_timesync_disable(struct rte_eth_dev *dev);
433 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
434 struct timespec *timestamp,
436 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
437 struct timespec *timestamp);
438 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
440 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
442 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
443 struct timespec *timestamp);
444 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
445 const struct timespec *timestamp);
447 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
449 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
452 static int i40e_get_regs(struct rte_eth_dev *dev,
453 struct rte_dev_reg_info *regs);
455 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
457 static int i40e_get_eeprom(struct rte_eth_dev *dev,
458 struct rte_dev_eeprom_info *eeprom);
460 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
461 struct ether_addr *mac_addr);
463 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
465 static const struct rte_pci_id pci_id_i40e_map[] = {
466 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
467 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
468 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
469 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
470 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
471 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
472 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
473 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
474 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
475 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
476 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
477 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
478 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
479 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
480 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
481 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
482 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
483 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
484 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
485 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
486 { .vendor_id = 0, /* sentinel */ },
489 static const struct eth_dev_ops i40e_eth_dev_ops = {
490 .dev_configure = i40e_dev_configure,
491 .dev_start = i40e_dev_start,
492 .dev_stop = i40e_dev_stop,
493 .dev_close = i40e_dev_close,
494 .promiscuous_enable = i40e_dev_promiscuous_enable,
495 .promiscuous_disable = i40e_dev_promiscuous_disable,
496 .allmulticast_enable = i40e_dev_allmulticast_enable,
497 .allmulticast_disable = i40e_dev_allmulticast_disable,
498 .dev_set_link_up = i40e_dev_set_link_up,
499 .dev_set_link_down = i40e_dev_set_link_down,
500 .link_update = i40e_dev_link_update,
501 .stats_get = i40e_dev_stats_get,
502 .xstats_get = i40e_dev_xstats_get,
503 .xstats_get_names = i40e_dev_xstats_get_names,
504 .stats_reset = i40e_dev_stats_reset,
505 .xstats_reset = i40e_dev_stats_reset,
506 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
507 .dev_infos_get = i40e_dev_info_get,
508 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
509 .vlan_filter_set = i40e_vlan_filter_set,
510 .vlan_tpid_set = i40e_vlan_tpid_set,
511 .vlan_offload_set = i40e_vlan_offload_set,
512 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
513 .vlan_pvid_set = i40e_vlan_pvid_set,
514 .rx_queue_start = i40e_dev_rx_queue_start,
515 .rx_queue_stop = i40e_dev_rx_queue_stop,
516 .tx_queue_start = i40e_dev_tx_queue_start,
517 .tx_queue_stop = i40e_dev_tx_queue_stop,
518 .rx_queue_setup = i40e_dev_rx_queue_setup,
519 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
520 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
521 .rx_queue_release = i40e_dev_rx_queue_release,
522 .rx_queue_count = i40e_dev_rx_queue_count,
523 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
524 .tx_queue_setup = i40e_dev_tx_queue_setup,
525 .tx_queue_release = i40e_dev_tx_queue_release,
526 .dev_led_on = i40e_dev_led_on,
527 .dev_led_off = i40e_dev_led_off,
528 .flow_ctrl_get = i40e_flow_ctrl_get,
529 .flow_ctrl_set = i40e_flow_ctrl_set,
530 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
531 .mac_addr_add = i40e_macaddr_add,
532 .mac_addr_remove = i40e_macaddr_remove,
533 .reta_update = i40e_dev_rss_reta_update,
534 .reta_query = i40e_dev_rss_reta_query,
535 .rss_hash_update = i40e_dev_rss_hash_update,
536 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
537 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
538 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
539 .filter_ctrl = i40e_dev_filter_ctrl,
540 .rxq_info_get = i40e_rxq_info_get,
541 .txq_info_get = i40e_txq_info_get,
542 .mirror_rule_set = i40e_mirror_rule_set,
543 .mirror_rule_reset = i40e_mirror_rule_reset,
544 .timesync_enable = i40e_timesync_enable,
545 .timesync_disable = i40e_timesync_disable,
546 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
547 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
548 .get_dcb_info = i40e_dev_get_dcb_info,
549 .timesync_adjust_time = i40e_timesync_adjust_time,
550 .timesync_read_time = i40e_timesync_read_time,
551 .timesync_write_time = i40e_timesync_write_time,
552 .get_reg = i40e_get_regs,
553 .get_eeprom_length = i40e_get_eeprom_length,
554 .get_eeprom = i40e_get_eeprom,
555 .mac_addr_set = i40e_set_default_mac_addr,
556 .mtu_set = i40e_dev_mtu_set,
559 /* store statistics names and its offset in stats structure */
560 struct rte_i40e_xstats_name_off {
561 char name[RTE_ETH_XSTATS_NAME_SIZE];
565 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
566 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
567 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
568 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
569 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
570 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
571 rx_unknown_protocol)},
572 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
573 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
574 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
575 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
578 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
579 sizeof(rte_i40e_stats_strings[0]))
581 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
582 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
583 tx_dropped_link_down)},
584 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
585 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
587 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
588 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
590 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
592 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
594 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
595 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
596 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
597 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
598 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
599 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
601 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
603 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
605 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
607 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
609 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
611 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
613 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
615 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
616 mac_short_packet_dropped)},
617 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
619 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
620 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
621 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
623 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
625 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
627 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
629 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
631 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
633 {"rx_flow_director_atr_match_packets",
634 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
635 {"rx_flow_director_sb_match_packets",
636 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
637 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
639 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
641 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
643 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
647 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
648 sizeof(rte_i40e_hw_port_strings[0]))
650 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
651 {"xon_packets", offsetof(struct i40e_hw_port_stats,
653 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
657 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
658 sizeof(rte_i40e_rxq_prio_strings[0]))
660 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
661 {"xon_packets", offsetof(struct i40e_hw_port_stats,
663 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
665 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
666 priority_xon_2_xoff)},
669 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
670 sizeof(rte_i40e_txq_prio_strings[0]))
672 static struct eth_driver rte_i40e_pmd = {
674 .id_table = pci_id_i40e_map,
675 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
676 RTE_PCI_DRV_DETACHABLE,
677 .probe = rte_eth_dev_pci_probe,
678 .remove = rte_eth_dev_pci_remove,
680 .eth_dev_init = eth_i40e_dev_init,
681 .eth_dev_uninit = eth_i40e_dev_uninit,
682 .dev_private_size = sizeof(struct i40e_adapter),
686 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
687 struct rte_eth_link *link)
689 struct rte_eth_link *dst = link;
690 struct rte_eth_link *src = &(dev->data->dev_link);
692 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
693 *(uint64_t *)src) == 0)
700 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
701 struct rte_eth_link *link)
703 struct rte_eth_link *dst = &(dev->data->dev_link);
704 struct rte_eth_link *src = link;
706 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
707 *(uint64_t *)src) == 0)
713 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
714 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
716 #ifndef I40E_GLQF_ORT
717 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
719 #ifndef I40E_GLQF_PIT
720 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
723 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
726 * Initialize registers for flexible payload, which should be set by NVM.
727 * This should be removed from code once it is fixed in NVM.
729 I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
730 I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
731 I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
732 I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
733 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
734 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
735 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
736 I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
737 I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
738 I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
739 I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
740 I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
742 /* Initialize registers for parsing packet type of QinQ */
743 I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
744 I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
747 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
750 * Add a ethertype filter to drop all flow control frames transmitted
754 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
756 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
757 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
758 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
759 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
762 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
763 I40E_FLOW_CONTROL_ETHERTYPE, flags,
764 pf->main_vsi_seid, 0,
767 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
768 " frames from VSIs.");
772 floating_veb_list_handler(__rte_unused const char *key,
773 const char *floating_veb_value,
777 unsigned int count = 0;
780 bool *vf_floating_veb = opaque;
782 while (isblank(*floating_veb_value))
783 floating_veb_value++;
785 /* Reset floating VEB configuration for VFs */
786 for (idx = 0; idx < I40E_MAX_VF; idx++)
787 vf_floating_veb[idx] = false;
791 while (isblank(*floating_veb_value))
792 floating_veb_value++;
793 if (*floating_veb_value == '\0')
796 idx = strtoul(floating_veb_value, &end, 10);
797 if (errno || end == NULL)
799 while (isblank(*end))
803 } else if ((*end == ';') || (*end == '\0')) {
805 if (min == I40E_MAX_VF)
807 if (max >= I40E_MAX_VF)
808 max = I40E_MAX_VF - 1;
809 for (idx = min; idx <= max; idx++) {
810 vf_floating_veb[idx] = true;
817 floating_veb_value = end + 1;
818 } while (*end != '\0');
827 config_vf_floating_veb(struct rte_devargs *devargs,
828 uint16_t floating_veb,
829 bool *vf_floating_veb)
831 struct rte_kvargs *kvlist;
833 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
837 /* All the VFs attach to the floating VEB by default
838 * when the floating VEB is enabled.
840 for (i = 0; i < I40E_MAX_VF; i++)
841 vf_floating_veb[i] = true;
846 kvlist = rte_kvargs_parse(devargs->args, NULL);
850 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
851 rte_kvargs_free(kvlist);
854 /* When the floating_veb_list parameter exists, all the VFs
855 * will attach to the legacy VEB firstly, then configure VFs
856 * to the floating VEB according to the floating_veb_list.
858 if (rte_kvargs_process(kvlist, floating_veb_list,
859 floating_veb_list_handler,
860 vf_floating_veb) < 0) {
861 rte_kvargs_free(kvlist);
864 rte_kvargs_free(kvlist);
868 i40e_check_floating_handler(__rte_unused const char *key,
870 __rte_unused void *opaque)
872 if (strcmp(value, "1"))
879 is_floating_veb_supported(struct rte_devargs *devargs)
881 struct rte_kvargs *kvlist;
882 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
887 kvlist = rte_kvargs_parse(devargs->args, NULL);
891 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
892 rte_kvargs_free(kvlist);
895 /* Floating VEB is enabled when there's key-value:
896 * enable_floating_veb=1
898 if (rte_kvargs_process(kvlist, floating_veb_key,
899 i40e_check_floating_handler, NULL) < 0) {
900 rte_kvargs_free(kvlist);
903 rte_kvargs_free(kvlist);
909 config_floating_veb(struct rte_eth_dev *dev)
911 struct rte_pci_device *pci_dev = dev->pci_dev;
912 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
913 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
915 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
917 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
919 is_floating_veb_supported(pci_dev->device.devargs);
920 config_vf_floating_veb(pci_dev->device.devargs,
922 pf->floating_veb_list);
924 pf->floating_veb = false;
928 #define I40E_L2_TAGS_S_TAG_SHIFT 1
929 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
932 eth_i40e_dev_init(struct rte_eth_dev *dev)
934 struct rte_pci_device *pci_dev;
935 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
936 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
937 struct i40e_vsi *vsi;
942 PMD_INIT_FUNC_TRACE();
944 dev->dev_ops = &i40e_eth_dev_ops;
945 dev->rx_pkt_burst = i40e_recv_pkts;
946 dev->tx_pkt_burst = i40e_xmit_pkts;
948 /* for secondary processes, we don't initialise any further as primary
949 * has already done this work. Only check we don't need a different
951 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
952 i40e_set_rx_function(dev);
953 i40e_set_tx_function(dev);
956 pci_dev = dev->pci_dev;
958 rte_eth_copy_pci_info(dev, pci_dev);
960 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
961 pf->adapter->eth_dev = dev;
962 pf->dev_data = dev->data;
964 hw->back = I40E_PF_TO_ADAPTER(pf);
965 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
967 PMD_INIT_LOG(ERR, "Hardware is not available, "
968 "as address is NULL");
972 hw->vendor_id = pci_dev->id.vendor_id;
973 hw->device_id = pci_dev->id.device_id;
974 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
975 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
976 hw->bus.device = pci_dev->addr.devid;
977 hw->bus.func = pci_dev->addr.function;
978 hw->adapter_stopped = 0;
980 /* Make sure all is clean before doing PF reset */
983 /* Initialize the hardware */
986 /* Reset here to make sure all is clean for each PF */
987 ret = i40e_pf_reset(hw);
989 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
993 /* Initialize the shared code (base driver) */
994 ret = i40e_init_shared_code(hw);
996 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1001 * To work around the NVM issue, initialize registers
1002 * for flexible payload and packet type of QinQ by
1003 * software. It should be removed once issues are fixed
1006 i40e_GLQF_reg_init(hw);
1008 /* Initialize the input set for filters (hash and fd) to default value */
1009 i40e_filter_input_set_init(pf);
1011 /* Initialize the parameters for adminq */
1012 i40e_init_adminq_parameter(hw);
1013 ret = i40e_init_adminq(hw);
1014 if (ret != I40E_SUCCESS) {
1015 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1018 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1019 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1020 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1021 ((hw->nvm.version >> 12) & 0xf),
1022 ((hw->nvm.version >> 4) & 0xff),
1023 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1025 /* Need the special FW version to support floating VEB */
1026 config_floating_veb(dev);
1027 /* Clear PXE mode */
1028 i40e_clear_pxe_mode(hw);
1029 ret = i40e_dev_sync_phy_type(hw);
1031 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1032 goto err_sync_phy_type;
1035 * On X710, performance number is far from the expectation on recent
1036 * firmware versions. The fix for this issue may not be integrated in
1037 * the following firmware version. So the workaround in software driver
1038 * is needed. It needs to modify the initial values of 3 internal only
1039 * registers. Note that the workaround can be removed when it is fixed
1040 * in firmware in the future.
1042 i40e_configure_registers(hw);
1044 /* Get hw capabilities */
1045 ret = i40e_get_cap(hw);
1046 if (ret != I40E_SUCCESS) {
1047 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1048 goto err_get_capabilities;
1051 /* Initialize parameters for PF */
1052 ret = i40e_pf_parameter_init(dev);
1054 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1055 goto err_parameter_init;
1058 /* Initialize the queue management */
1059 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1061 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1062 goto err_qp_pool_init;
1064 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1065 hw->func_caps.num_msix_vectors - 1);
1067 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1068 goto err_msix_pool_init;
1071 /* Initialize lan hmc */
1072 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1073 hw->func_caps.num_rx_qp, 0, 0);
1074 if (ret != I40E_SUCCESS) {
1075 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1076 goto err_init_lan_hmc;
1079 /* Configure lan hmc */
1080 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1081 if (ret != I40E_SUCCESS) {
1082 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1083 goto err_configure_lan_hmc;
1086 /* Get and check the mac address */
1087 i40e_get_mac_addr(hw, hw->mac.addr);
1088 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1089 PMD_INIT_LOG(ERR, "mac address is not valid");
1091 goto err_get_mac_addr;
1093 /* Copy the permanent MAC address */
1094 ether_addr_copy((struct ether_addr *) hw->mac.addr,
1095 (struct ether_addr *) hw->mac.perm_addr);
1097 /* Disable flow control */
1098 hw->fc.requested_mode = I40E_FC_NONE;
1099 i40e_set_fc(hw, &aq_fail, TRUE);
1101 /* Set the global registers with default ether type value */
1102 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1103 if (ret != I40E_SUCCESS) {
1104 PMD_INIT_LOG(ERR, "Failed to set the default outer "
1106 goto err_setup_pf_switch;
1109 /* PF setup, which includes VSI setup */
1110 ret = i40e_pf_setup(pf);
1112 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1113 goto err_setup_pf_switch;
1116 /* reset all stats of the device, including pf and main vsi */
1117 i40e_dev_stats_reset(dev);
1121 /* Disable double vlan by default */
1122 i40e_vsi_config_double_vlan(vsi, FALSE);
1124 /* Disable S-TAG identification by default */
1125 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1126 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1127 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1128 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1131 if (!vsi->max_macaddrs)
1132 len = ETHER_ADDR_LEN;
1134 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1136 /* Should be after VSI initialized */
1137 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1138 if (!dev->data->mac_addrs) {
1139 PMD_INIT_LOG(ERR, "Failed to allocated memory "
1140 "for storing mac address");
1143 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1144 &dev->data->mac_addrs[0]);
1146 /* initialize pf host driver to setup SRIOV resource if applicable */
1147 i40e_pf_host_init(dev);
1149 /* register callback func to eal lib */
1150 rte_intr_callback_register(&(pci_dev->intr_handle),
1151 i40e_dev_interrupt_handler, (void *)dev);
1153 /* configure and enable device interrupt */
1154 i40e_pf_config_irq0(hw, TRUE);
1155 i40e_pf_enable_irq0(hw);
1157 /* enable uio intr after callback register */
1158 rte_intr_enable(&(pci_dev->intr_handle));
1160 * Add an ethertype filter to drop all flow control frames transmitted
1161 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1164 i40e_add_tx_flow_control_drop_filter(pf);
1166 /* Set the max frame size to 0x2600 by default,
1167 * in case other drivers changed the default value.
1169 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1171 /* initialize mirror rule list */
1172 TAILQ_INIT(&pf->mirror_list);
1174 /* Init dcb to sw mode by default */
1175 ret = i40e_dcb_init_configure(dev, TRUE);
1176 if (ret != I40E_SUCCESS) {
1177 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1178 pf->flags &= ~I40E_FLAG_DCB;
1184 i40e_vsi_release(pf->main_vsi);
1185 err_setup_pf_switch:
1187 err_configure_lan_hmc:
1188 (void)i40e_shutdown_lan_hmc(hw);
1190 i40e_res_pool_destroy(&pf->msix_pool);
1192 i40e_res_pool_destroy(&pf->qp_pool);
1195 err_get_capabilities:
1197 (void)i40e_shutdown_adminq(hw);
1203 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1205 struct rte_pci_device *pci_dev;
1207 struct i40e_filter_control_settings settings;
1209 uint8_t aq_fail = 0;
1211 PMD_INIT_FUNC_TRACE();
1213 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1216 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1217 pci_dev = dev->pci_dev;
1219 if (hw->adapter_stopped == 0)
1220 i40e_dev_close(dev);
1222 dev->dev_ops = NULL;
1223 dev->rx_pkt_burst = NULL;
1224 dev->tx_pkt_burst = NULL;
1227 ret = i40e_aq_stop_lldp(hw, true, NULL);
1228 if (ret != I40E_SUCCESS) /* Its failure can be ignored */
1229 PMD_INIT_LOG(INFO, "Failed to stop lldp");
1231 /* Clear PXE mode */
1232 i40e_clear_pxe_mode(hw);
1234 /* Unconfigure filter control */
1235 memset(&settings, 0, sizeof(settings));
1236 ret = i40e_set_filter_control(hw, &settings);
1238 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1241 /* Disable flow control */
1242 hw->fc.requested_mode = I40E_FC_NONE;
1243 i40e_set_fc(hw, &aq_fail, TRUE);
1245 /* uninitialize pf host driver */
1246 i40e_pf_host_uninit(dev);
1248 rte_free(dev->data->mac_addrs);
1249 dev->data->mac_addrs = NULL;
1251 /* disable uio intr before callback unregister */
1252 rte_intr_disable(&(pci_dev->intr_handle));
1254 /* register callback func to eal lib */
1255 rte_intr_callback_unregister(&(pci_dev->intr_handle),
1256 i40e_dev_interrupt_handler, (void *)dev);
1262 i40e_dev_configure(struct rte_eth_dev *dev)
1264 struct i40e_adapter *ad =
1265 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1266 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1267 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1270 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1271 * bulk allocation or vector Rx preconditions we will reset it.
1273 ad->rx_bulk_alloc_allowed = true;
1274 ad->rx_vec_allowed = true;
1275 ad->tx_simple_allowed = true;
1276 ad->tx_vec_allowed = true;
1278 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1279 ret = i40e_fdir_setup(pf);
1280 if (ret != I40E_SUCCESS) {
1281 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1284 ret = i40e_fdir_configure(dev);
1286 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1290 i40e_fdir_teardown(pf);
1292 ret = i40e_dev_init_vlan(dev);
1297 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1298 * RSS setting have different requirements.
1299 * General PMD driver call sequence are NIC init, configure,
1300 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1301 * will try to lookup the VSI that specific queue belongs to if VMDQ
1302 * applicable. So, VMDQ setting has to be done before
1303 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1304 * For RSS setting, it will try to calculate actual configured RX queue
1305 * number, which will be available after rx_queue_setup(). dev_start()
1306 * function is good to place RSS setup.
1308 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1309 ret = i40e_vmdq_setup(dev);
1314 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1315 ret = i40e_dcb_setup(dev);
1317 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1325 /* need to release vmdq resource if exists */
1326 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1327 i40e_vsi_release(pf->vmdq[i].vsi);
1328 pf->vmdq[i].vsi = NULL;
1333 /* need to release fdir resource if exists */
1334 i40e_fdir_teardown(pf);
1339 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1341 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1342 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1343 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1344 uint16_t msix_vect = vsi->msix_intr;
1347 for (i = 0; i < vsi->nb_qps; i++) {
1348 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1349 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1353 if (vsi->type != I40E_VSI_SRIOV) {
1354 if (!rte_intr_allow_others(intr_handle)) {
1355 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1356 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1358 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1361 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1362 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1364 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1369 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1370 vsi->user_param + (msix_vect - 1);
1372 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1373 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1375 I40E_WRITE_FLUSH(hw);
1379 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1380 int base_queue, int nb_queue)
1384 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1386 /* Bind all RX queues to allocated MSIX interrupt */
1387 for (i = 0; i < nb_queue; i++) {
1388 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1389 I40E_QINT_RQCTL_ITR_INDX_MASK |
1390 ((base_queue + i + 1) <<
1391 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1392 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1393 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1395 if (i == nb_queue - 1)
1396 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1397 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1400 /* Write first RX queue to Link list register as the head element */
1401 if (vsi->type != I40E_VSI_SRIOV) {
1403 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1405 if (msix_vect == I40E_MISC_VEC_ID) {
1406 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1408 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1410 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1412 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1415 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1417 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1419 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1421 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1428 if (msix_vect == I40E_MISC_VEC_ID) {
1430 I40E_VPINT_LNKLST0(vsi->user_param),
1432 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1434 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1436 /* num_msix_vectors_vf needs to minus irq0 */
1437 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1438 vsi->user_param + (msix_vect - 1);
1440 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1442 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1444 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1448 I40E_WRITE_FLUSH(hw);
1452 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1454 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1455 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1456 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1457 uint16_t msix_vect = vsi->msix_intr;
1458 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1459 uint16_t queue_idx = 0;
1464 for (i = 0; i < vsi->nb_qps; i++) {
1465 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1466 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1469 /* INTENA flag is not auto-cleared for interrupt */
1470 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1471 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1472 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1473 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1474 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1476 /* VF bind interrupt */
1477 if (vsi->type == I40E_VSI_SRIOV) {
1478 __vsi_queues_bind_intr(vsi, msix_vect,
1479 vsi->base_queue, vsi->nb_qps);
1483 /* PF & VMDq bind interrupt */
1484 if (rte_intr_dp_is_en(intr_handle)) {
1485 if (vsi->type == I40E_VSI_MAIN) {
1488 } else if (vsi->type == I40E_VSI_VMDQ2) {
1489 struct i40e_vsi *main_vsi =
1490 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1491 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1496 for (i = 0; i < vsi->nb_used_qps; i++) {
1498 if (!rte_intr_allow_others(intr_handle))
1499 /* allow to share MISC_VEC_ID */
1500 msix_vect = I40E_MISC_VEC_ID;
1502 /* no enough msix_vect, map all to one */
1503 __vsi_queues_bind_intr(vsi, msix_vect,
1504 vsi->base_queue + i,
1505 vsi->nb_used_qps - i);
1506 for (; !!record && i < vsi->nb_used_qps; i++)
1507 intr_handle->intr_vec[queue_idx + i] =
1511 /* 1:1 queue/msix_vect mapping */
1512 __vsi_queues_bind_intr(vsi, msix_vect,
1513 vsi->base_queue + i, 1);
1515 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1523 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1525 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1526 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1527 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1528 uint16_t interval = i40e_calc_itr_interval(\
1529 RTE_LIBRTE_I40E_ITR_INTERVAL);
1530 uint16_t msix_intr, i;
1532 if (rte_intr_allow_others(intr_handle))
1533 for (i = 0; i < vsi->nb_msix; i++) {
1534 msix_intr = vsi->msix_intr + i;
1535 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1536 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1537 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1538 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1540 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1543 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1544 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1545 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1546 (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1548 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1550 I40E_WRITE_FLUSH(hw);
1554 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1556 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1557 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1558 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1559 uint16_t msix_intr, i;
1561 if (rte_intr_allow_others(intr_handle))
1562 for (i = 0; i < vsi->nb_msix; i++) {
1563 msix_intr = vsi->msix_intr + i;
1564 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1568 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1570 I40E_WRITE_FLUSH(hw);
1573 static inline uint8_t
1574 i40e_parse_link_speeds(uint16_t link_speeds)
1576 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1578 if (link_speeds & ETH_LINK_SPEED_40G)
1579 link_speed |= I40E_LINK_SPEED_40GB;
1580 if (link_speeds & ETH_LINK_SPEED_25G)
1581 link_speed |= I40E_LINK_SPEED_25GB;
1582 if (link_speeds & ETH_LINK_SPEED_20G)
1583 link_speed |= I40E_LINK_SPEED_20GB;
1584 if (link_speeds & ETH_LINK_SPEED_10G)
1585 link_speed |= I40E_LINK_SPEED_10GB;
1586 if (link_speeds & ETH_LINK_SPEED_1G)
1587 link_speed |= I40E_LINK_SPEED_1GB;
1588 if (link_speeds & ETH_LINK_SPEED_100M)
1589 link_speed |= I40E_LINK_SPEED_100MB;
1595 i40e_phy_conf_link(struct i40e_hw *hw,
1597 uint8_t force_speed)
1599 enum i40e_status_code status;
1600 struct i40e_aq_get_phy_abilities_resp phy_ab;
1601 struct i40e_aq_set_phy_config phy_conf;
1602 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1603 I40E_AQ_PHY_FLAG_PAUSE_RX |
1604 I40E_AQ_PHY_FLAG_PAUSE_RX |
1605 I40E_AQ_PHY_FLAG_LOW_POWER;
1606 const uint8_t advt = I40E_LINK_SPEED_40GB |
1607 I40E_LINK_SPEED_25GB |
1608 I40E_LINK_SPEED_10GB |
1609 I40E_LINK_SPEED_1GB |
1610 I40E_LINK_SPEED_100MB;
1614 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1619 memset(&phy_conf, 0, sizeof(phy_conf));
1621 /* bits 0-2 use the values from get_phy_abilities_resp */
1623 abilities |= phy_ab.abilities & mask;
1625 /* update ablities and speed */
1626 if (abilities & I40E_AQ_PHY_AN_ENABLED)
1627 phy_conf.link_speed = advt;
1629 phy_conf.link_speed = force_speed;
1631 phy_conf.abilities = abilities;
1633 /* use get_phy_abilities_resp value for the rest */
1634 phy_conf.phy_type = phy_ab.phy_type;
1635 phy_conf.eee_capability = phy_ab.eee_capability;
1636 phy_conf.eeer = phy_ab.eeer_val;
1637 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1639 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1640 phy_ab.abilities, phy_ab.link_speed);
1641 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
1642 phy_conf.abilities, phy_conf.link_speed);
1644 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1648 return I40E_SUCCESS;
1652 i40e_apply_link_speed(struct rte_eth_dev *dev)
1655 uint8_t abilities = 0;
1656 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1657 struct rte_eth_conf *conf = &dev->data->dev_conf;
1659 speed = i40e_parse_link_speeds(conf->link_speeds);
1660 if (!I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
1661 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1662 if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1663 abilities |= I40E_AQ_PHY_AN_ENABLED;
1664 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1666 /* Skip changing speed on 40G interfaces, FW does not support */
1667 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1668 speed = I40E_LINK_SPEED_UNKNOWN;
1669 abilities |= I40E_AQ_PHY_AN_ENABLED;
1672 return i40e_phy_conf_link(hw, abilities, speed);
1676 i40e_dev_start(struct rte_eth_dev *dev)
1678 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1679 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1680 struct i40e_vsi *main_vsi = pf->main_vsi;
1682 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1683 uint32_t intr_vector = 0;
1685 hw->adapter_stopped = 0;
1687 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1688 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1689 dev->data->port_id);
1693 rte_intr_disable(intr_handle);
1695 if ((rte_intr_cap_multiple(intr_handle) ||
1696 !RTE_ETH_DEV_SRIOV(dev).active) &&
1697 dev->data->dev_conf.intr_conf.rxq != 0) {
1698 intr_vector = dev->data->nb_rx_queues;
1699 if (rte_intr_efd_enable(intr_handle, intr_vector))
1703 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1704 intr_handle->intr_vec =
1705 rte_zmalloc("intr_vec",
1706 dev->data->nb_rx_queues * sizeof(int),
1708 if (!intr_handle->intr_vec) {
1709 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1710 " intr_vec\n", dev->data->nb_rx_queues);
1715 /* Initialize VSI */
1716 ret = i40e_dev_rxtx_init(pf);
1717 if (ret != I40E_SUCCESS) {
1718 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1722 /* Map queues with MSIX interrupt */
1723 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1724 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1725 i40e_vsi_queues_bind_intr(main_vsi);
1726 i40e_vsi_enable_queues_intr(main_vsi);
1728 /* Map VMDQ VSI queues with MSIX interrupt */
1729 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1730 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1731 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1732 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1735 /* enable FDIR MSIX interrupt */
1736 if (pf->fdir.fdir_vsi) {
1737 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1738 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1741 /* Enable all queues which have been configured */
1742 ret = i40e_dev_switch_queues(pf, TRUE);
1743 if (ret != I40E_SUCCESS) {
1744 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1748 /* Enable receiving broadcast packets */
1749 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1750 if (ret != I40E_SUCCESS)
1751 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1753 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1754 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1756 if (ret != I40E_SUCCESS)
1757 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1760 /* Apply link configure */
1761 if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1762 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1763 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1764 ETH_LINK_SPEED_40G)) {
1765 PMD_DRV_LOG(ERR, "Invalid link setting");
1768 ret = i40e_apply_link_speed(dev);
1769 if (I40E_SUCCESS != ret) {
1770 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1774 if (!rte_intr_allow_others(intr_handle)) {
1775 rte_intr_callback_unregister(intr_handle,
1776 i40e_dev_interrupt_handler,
1778 /* configure and enable device interrupt */
1779 i40e_pf_config_irq0(hw, FALSE);
1780 i40e_pf_enable_irq0(hw);
1782 if (dev->data->dev_conf.intr_conf.lsc != 0)
1783 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1784 " no intr multiplex\n");
1787 /* enable uio intr after callback register */
1788 rte_intr_enable(intr_handle);
1790 return I40E_SUCCESS;
1793 i40e_dev_switch_queues(pf, FALSE);
1794 i40e_dev_clear_queues(dev);
1800 i40e_dev_stop(struct rte_eth_dev *dev)
1802 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1803 struct i40e_vsi *main_vsi = pf->main_vsi;
1804 struct i40e_mirror_rule *p_mirror;
1805 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1808 /* Disable all queues */
1809 i40e_dev_switch_queues(pf, FALSE);
1811 /* un-map queues with interrupt registers */
1812 i40e_vsi_disable_queues_intr(main_vsi);
1813 i40e_vsi_queues_unbind_intr(main_vsi);
1815 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1816 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1817 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1820 if (pf->fdir.fdir_vsi) {
1821 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1822 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1824 /* Clear all queues and release memory */
1825 i40e_dev_clear_queues(dev);
1828 i40e_dev_set_link_down(dev);
1830 /* Remove all mirror rules */
1831 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1832 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1835 pf->nb_mirror_rule = 0;
1837 if (!rte_intr_allow_others(intr_handle))
1838 /* resume to the default handler */
1839 rte_intr_callback_register(intr_handle,
1840 i40e_dev_interrupt_handler,
1843 /* Clean datapath event and queue/vec mapping */
1844 rte_intr_efd_disable(intr_handle);
1845 if (intr_handle->intr_vec) {
1846 rte_free(intr_handle->intr_vec);
1847 intr_handle->intr_vec = NULL;
1852 i40e_dev_close(struct rte_eth_dev *dev)
1854 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1855 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1859 PMD_INIT_FUNC_TRACE();
1862 hw->adapter_stopped = 1;
1863 i40e_dev_free_queues(dev);
1865 /* Disable interrupt */
1866 i40e_pf_disable_irq0(hw);
1867 rte_intr_disable(&(dev->pci_dev->intr_handle));
1869 /* shutdown and destroy the HMC */
1870 i40e_shutdown_lan_hmc(hw);
1872 /* release all the existing VSIs and VEBs */
1873 i40e_fdir_teardown(pf);
1874 i40e_vsi_release(pf->main_vsi);
1876 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1877 i40e_vsi_release(pf->vmdq[i].vsi);
1878 pf->vmdq[i].vsi = NULL;
1884 /* shutdown the adminq */
1885 i40e_aq_queue_shutdown(hw, true);
1886 i40e_shutdown_adminq(hw);
1888 i40e_res_pool_destroy(&pf->qp_pool);
1889 i40e_res_pool_destroy(&pf->msix_pool);
1891 /* force a PF reset to clean anything leftover */
1892 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1893 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1894 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1895 I40E_WRITE_FLUSH(hw);
1899 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1901 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1902 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1903 struct i40e_vsi *vsi = pf->main_vsi;
1906 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1908 if (status != I40E_SUCCESS)
1909 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1911 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1913 if (status != I40E_SUCCESS)
1914 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1919 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1921 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1922 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1923 struct i40e_vsi *vsi = pf->main_vsi;
1926 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1928 if (status != I40E_SUCCESS)
1929 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1931 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1933 if (status != I40E_SUCCESS)
1934 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1938 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1940 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1941 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1942 struct i40e_vsi *vsi = pf->main_vsi;
1945 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1946 if (ret != I40E_SUCCESS)
1947 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1951 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1953 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1954 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1955 struct i40e_vsi *vsi = pf->main_vsi;
1958 if (dev->data->promiscuous == 1)
1959 return; /* must remain in all_multicast mode */
1961 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1962 vsi->seid, FALSE, NULL);
1963 if (ret != I40E_SUCCESS)
1964 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1968 * Set device link up.
1971 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1973 /* re-apply link speed setting */
1974 return i40e_apply_link_speed(dev);
1978 * Set device link down.
1981 i40e_dev_set_link_down(struct rte_eth_dev *dev)
1983 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1984 uint8_t abilities = 0;
1985 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1987 if (!I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
1988 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1989 return i40e_phy_conf_link(hw, abilities, speed);
1993 i40e_dev_link_update(struct rte_eth_dev *dev,
1994 int wait_to_complete)
1996 #define CHECK_INTERVAL 100 /* 100ms */
1997 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
1998 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1999 struct i40e_link_status link_status;
2000 struct rte_eth_link link, old;
2002 unsigned rep_cnt = MAX_REPEAT_TIME;
2004 memset(&link, 0, sizeof(link));
2005 memset(&old, 0, sizeof(old));
2006 memset(&link_status, 0, sizeof(link_status));
2007 rte_i40e_dev_atomic_read_link_status(dev, &old);
2010 /* Get link status information from hardware */
2011 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
2012 if (status != I40E_SUCCESS) {
2013 link.link_speed = ETH_SPEED_NUM_100M;
2014 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2015 PMD_DRV_LOG(ERR, "Failed to get link info");
2019 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2020 if (!wait_to_complete)
2023 rte_delay_ms(CHECK_INTERVAL);
2024 } while (!link.link_status && rep_cnt--);
2026 if (!link.link_status)
2029 /* i40e uses full duplex only */
2030 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2032 /* Parse the link status */
2033 switch (link_status.link_speed) {
2034 case I40E_LINK_SPEED_100MB:
2035 link.link_speed = ETH_SPEED_NUM_100M;
2037 case I40E_LINK_SPEED_1GB:
2038 link.link_speed = ETH_SPEED_NUM_1G;
2040 case I40E_LINK_SPEED_10GB:
2041 link.link_speed = ETH_SPEED_NUM_10G;
2043 case I40E_LINK_SPEED_20GB:
2044 link.link_speed = ETH_SPEED_NUM_20G;
2046 case I40E_LINK_SPEED_25GB:
2047 link.link_speed = ETH_SPEED_NUM_25G;
2049 case I40E_LINK_SPEED_40GB:
2050 link.link_speed = ETH_SPEED_NUM_40G;
2053 link.link_speed = ETH_SPEED_NUM_100M;
2057 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2058 ETH_LINK_SPEED_FIXED);
2061 rte_i40e_dev_atomic_write_link_status(dev, &link);
2062 if (link.link_status == old.link_status)
2068 /* Get all the statistics of a VSI */
2070 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2072 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2073 struct i40e_eth_stats *nes = &vsi->eth_stats;
2074 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2075 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2077 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2078 vsi->offset_loaded, &oes->rx_bytes,
2080 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2081 vsi->offset_loaded, &oes->rx_unicast,
2083 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2084 vsi->offset_loaded, &oes->rx_multicast,
2085 &nes->rx_multicast);
2086 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2087 vsi->offset_loaded, &oes->rx_broadcast,
2088 &nes->rx_broadcast);
2089 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2090 &oes->rx_discards, &nes->rx_discards);
2091 /* GLV_REPC not supported */
2092 /* GLV_RMPC not supported */
2093 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2094 &oes->rx_unknown_protocol,
2095 &nes->rx_unknown_protocol);
2096 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2097 vsi->offset_loaded, &oes->tx_bytes,
2099 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2100 vsi->offset_loaded, &oes->tx_unicast,
2102 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2103 vsi->offset_loaded, &oes->tx_multicast,
2104 &nes->tx_multicast);
2105 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2106 vsi->offset_loaded, &oes->tx_broadcast,
2107 &nes->tx_broadcast);
2108 /* GLV_TDPC not supported */
2109 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2110 &oes->tx_errors, &nes->tx_errors);
2111 vsi->offset_loaded = true;
2113 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2115 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2116 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2117 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2118 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2119 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2120 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2121 nes->rx_unknown_protocol);
2122 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2123 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2124 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2125 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2126 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2127 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2128 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2133 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2136 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2137 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2139 /* Get statistics of struct i40e_eth_stats */
2140 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2141 I40E_GLPRT_GORCL(hw->port),
2142 pf->offset_loaded, &os->eth.rx_bytes,
2144 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2145 I40E_GLPRT_UPRCL(hw->port),
2146 pf->offset_loaded, &os->eth.rx_unicast,
2147 &ns->eth.rx_unicast);
2148 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2149 I40E_GLPRT_MPRCL(hw->port),
2150 pf->offset_loaded, &os->eth.rx_multicast,
2151 &ns->eth.rx_multicast);
2152 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2153 I40E_GLPRT_BPRCL(hw->port),
2154 pf->offset_loaded, &os->eth.rx_broadcast,
2155 &ns->eth.rx_broadcast);
2156 /* Workaround: CRC size should not be included in byte statistics,
2157 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2159 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2160 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2162 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2163 pf->offset_loaded, &os->eth.rx_discards,
2164 &ns->eth.rx_discards);
2165 /* GLPRT_REPC not supported */
2166 /* GLPRT_RMPC not supported */
2167 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2169 &os->eth.rx_unknown_protocol,
2170 &ns->eth.rx_unknown_protocol);
2171 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2172 I40E_GLPRT_GOTCL(hw->port),
2173 pf->offset_loaded, &os->eth.tx_bytes,
2175 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2176 I40E_GLPRT_UPTCL(hw->port),
2177 pf->offset_loaded, &os->eth.tx_unicast,
2178 &ns->eth.tx_unicast);
2179 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2180 I40E_GLPRT_MPTCL(hw->port),
2181 pf->offset_loaded, &os->eth.tx_multicast,
2182 &ns->eth.tx_multicast);
2183 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2184 I40E_GLPRT_BPTCL(hw->port),
2185 pf->offset_loaded, &os->eth.tx_broadcast,
2186 &ns->eth.tx_broadcast);
2187 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2188 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2189 /* GLPRT_TEPC not supported */
2191 /* additional port specific stats */
2192 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2193 pf->offset_loaded, &os->tx_dropped_link_down,
2194 &ns->tx_dropped_link_down);
2195 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2196 pf->offset_loaded, &os->crc_errors,
2198 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2199 pf->offset_loaded, &os->illegal_bytes,
2200 &ns->illegal_bytes);
2201 /* GLPRT_ERRBC not supported */
2202 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2203 pf->offset_loaded, &os->mac_local_faults,
2204 &ns->mac_local_faults);
2205 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2206 pf->offset_loaded, &os->mac_remote_faults,
2207 &ns->mac_remote_faults);
2208 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2209 pf->offset_loaded, &os->rx_length_errors,
2210 &ns->rx_length_errors);
2211 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2212 pf->offset_loaded, &os->link_xon_rx,
2214 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2215 pf->offset_loaded, &os->link_xoff_rx,
2217 for (i = 0; i < 8; i++) {
2218 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2220 &os->priority_xon_rx[i],
2221 &ns->priority_xon_rx[i]);
2222 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2224 &os->priority_xoff_rx[i],
2225 &ns->priority_xoff_rx[i]);
2227 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2228 pf->offset_loaded, &os->link_xon_tx,
2230 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2231 pf->offset_loaded, &os->link_xoff_tx,
2233 for (i = 0; i < 8; i++) {
2234 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2236 &os->priority_xon_tx[i],
2237 &ns->priority_xon_tx[i]);
2238 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2240 &os->priority_xoff_tx[i],
2241 &ns->priority_xoff_tx[i]);
2242 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2244 &os->priority_xon_2_xoff[i],
2245 &ns->priority_xon_2_xoff[i]);
2247 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2248 I40E_GLPRT_PRC64L(hw->port),
2249 pf->offset_loaded, &os->rx_size_64,
2251 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2252 I40E_GLPRT_PRC127L(hw->port),
2253 pf->offset_loaded, &os->rx_size_127,
2255 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2256 I40E_GLPRT_PRC255L(hw->port),
2257 pf->offset_loaded, &os->rx_size_255,
2259 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2260 I40E_GLPRT_PRC511L(hw->port),
2261 pf->offset_loaded, &os->rx_size_511,
2263 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2264 I40E_GLPRT_PRC1023L(hw->port),
2265 pf->offset_loaded, &os->rx_size_1023,
2267 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2268 I40E_GLPRT_PRC1522L(hw->port),
2269 pf->offset_loaded, &os->rx_size_1522,
2271 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2272 I40E_GLPRT_PRC9522L(hw->port),
2273 pf->offset_loaded, &os->rx_size_big,
2275 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2276 pf->offset_loaded, &os->rx_undersize,
2278 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2279 pf->offset_loaded, &os->rx_fragments,
2281 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2282 pf->offset_loaded, &os->rx_oversize,
2284 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2285 pf->offset_loaded, &os->rx_jabber,
2287 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2288 I40E_GLPRT_PTC64L(hw->port),
2289 pf->offset_loaded, &os->tx_size_64,
2291 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2292 I40E_GLPRT_PTC127L(hw->port),
2293 pf->offset_loaded, &os->tx_size_127,
2295 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2296 I40E_GLPRT_PTC255L(hw->port),
2297 pf->offset_loaded, &os->tx_size_255,
2299 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2300 I40E_GLPRT_PTC511L(hw->port),
2301 pf->offset_loaded, &os->tx_size_511,
2303 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2304 I40E_GLPRT_PTC1023L(hw->port),
2305 pf->offset_loaded, &os->tx_size_1023,
2307 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2308 I40E_GLPRT_PTC1522L(hw->port),
2309 pf->offset_loaded, &os->tx_size_1522,
2311 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2312 I40E_GLPRT_PTC9522L(hw->port),
2313 pf->offset_loaded, &os->tx_size_big,
2315 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2317 &os->fd_sb_match, &ns->fd_sb_match);
2318 /* GLPRT_MSPDC not supported */
2319 /* GLPRT_XEC not supported */
2321 pf->offset_loaded = true;
2324 i40e_update_vsi_stats(pf->main_vsi);
2327 /* Get all statistics of a port */
2329 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2331 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2332 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2333 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2336 /* call read registers - updates values, now write them to struct */
2337 i40e_read_stats_registers(pf, hw);
2339 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2340 pf->main_vsi->eth_stats.rx_multicast +
2341 pf->main_vsi->eth_stats.rx_broadcast -
2342 pf->main_vsi->eth_stats.rx_discards;
2343 stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2344 pf->main_vsi->eth_stats.tx_multicast +
2345 pf->main_vsi->eth_stats.tx_broadcast;
2346 stats->ibytes = ns->eth.rx_bytes;
2347 stats->obytes = ns->eth.tx_bytes;
2348 stats->oerrors = ns->eth.tx_errors +
2349 pf->main_vsi->eth_stats.tx_errors;
2352 stats->imissed = ns->eth.rx_discards +
2353 pf->main_vsi->eth_stats.rx_discards;
2354 stats->ierrors = ns->crc_errors +
2355 ns->rx_length_errors + ns->rx_undersize +
2356 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2358 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2359 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
2360 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
2361 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
2362 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
2363 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
2364 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2365 ns->eth.rx_unknown_protocol);
2366 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
2367 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
2368 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
2369 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
2370 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
2371 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
2373 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
2374 ns->tx_dropped_link_down);
2375 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
2376 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
2378 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
2379 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
2380 ns->mac_local_faults);
2381 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
2382 ns->mac_remote_faults);
2383 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
2384 ns->rx_length_errors);
2385 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
2386 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
2387 for (i = 0; i < 8; i++) {
2388 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
2389 i, ns->priority_xon_rx[i]);
2390 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
2391 i, ns->priority_xoff_rx[i]);
2393 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
2394 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
2395 for (i = 0; i < 8; i++) {
2396 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
2397 i, ns->priority_xon_tx[i]);
2398 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
2399 i, ns->priority_xoff_tx[i]);
2400 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
2401 i, ns->priority_xon_2_xoff[i]);
2403 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
2404 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
2405 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
2406 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
2407 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
2408 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
2409 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
2410 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
2411 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
2412 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
2413 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
2414 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
2415 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
2416 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
2417 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
2418 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
2419 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
2420 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
2421 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2422 ns->mac_short_packet_dropped);
2423 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
2424 ns->checksum_error);
2425 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
2426 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2429 /* Reset the statistics */
2431 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2433 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2434 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2436 /* Mark PF and VSI stats to update the offset, aka "reset" */
2437 pf->offset_loaded = false;
2439 pf->main_vsi->offset_loaded = false;
2441 /* read the stats, reading current register values into offset */
2442 i40e_read_stats_registers(pf, hw);
2446 i40e_xstats_calc_num(void)
2448 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2449 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2450 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2453 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2454 struct rte_eth_xstat_name *xstats_names,
2455 __rte_unused unsigned limit)
2460 if (xstats_names == NULL)
2461 return i40e_xstats_calc_num();
2463 /* Note: limit checked in rte_eth_xstats_names() */
2465 /* Get stats from i40e_eth_stats struct */
2466 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2467 snprintf(xstats_names[count].name,
2468 sizeof(xstats_names[count].name),
2469 "%s", rte_i40e_stats_strings[i].name);
2473 /* Get individiual stats from i40e_hw_port struct */
2474 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2475 snprintf(xstats_names[count].name,
2476 sizeof(xstats_names[count].name),
2477 "%s", rte_i40e_hw_port_strings[i].name);
2481 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2482 for (prio = 0; prio < 8; prio++) {
2483 snprintf(xstats_names[count].name,
2484 sizeof(xstats_names[count].name),
2485 "rx_priority%u_%s", prio,
2486 rte_i40e_rxq_prio_strings[i].name);
2491 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2492 for (prio = 0; prio < 8; prio++) {
2493 snprintf(xstats_names[count].name,
2494 sizeof(xstats_names[count].name),
2495 "tx_priority%u_%s", prio,
2496 rte_i40e_txq_prio_strings[i].name);
2504 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2507 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2508 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2509 unsigned i, count, prio;
2510 struct i40e_hw_port_stats *hw_stats = &pf->stats;
2512 count = i40e_xstats_calc_num();
2516 i40e_read_stats_registers(pf, hw);
2523 /* Get stats from i40e_eth_stats struct */
2524 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2525 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2526 rte_i40e_stats_strings[i].offset);
2530 /* Get individiual stats from i40e_hw_port struct */
2531 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2532 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2533 rte_i40e_hw_port_strings[i].offset);
2537 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2538 for (prio = 0; prio < 8; prio++) {
2539 xstats[count].value =
2540 *(uint64_t *)(((char *)hw_stats) +
2541 rte_i40e_rxq_prio_strings[i].offset +
2542 (sizeof(uint64_t) * prio));
2547 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2548 for (prio = 0; prio < 8; prio++) {
2549 xstats[count].value =
2550 *(uint64_t *)(((char *)hw_stats) +
2551 rte_i40e_txq_prio_strings[i].offset +
2552 (sizeof(uint64_t) * prio));
2561 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2562 __rte_unused uint16_t queue_id,
2563 __rte_unused uint8_t stat_idx,
2564 __rte_unused uint8_t is_rx)
2566 PMD_INIT_FUNC_TRACE();
2572 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2574 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2575 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2576 struct i40e_vsi *vsi = pf->main_vsi;
2578 dev_info->max_rx_queues = vsi->nb_qps;
2579 dev_info->max_tx_queues = vsi->nb_qps;
2580 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2581 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2582 dev_info->max_mac_addrs = vsi->max_macaddrs;
2583 dev_info->max_vfs = dev->pci_dev->max_vfs;
2584 dev_info->rx_offload_capa =
2585 DEV_RX_OFFLOAD_VLAN_STRIP |
2586 DEV_RX_OFFLOAD_QINQ_STRIP |
2587 DEV_RX_OFFLOAD_IPV4_CKSUM |
2588 DEV_RX_OFFLOAD_UDP_CKSUM |
2589 DEV_RX_OFFLOAD_TCP_CKSUM;
2590 dev_info->tx_offload_capa =
2591 DEV_TX_OFFLOAD_VLAN_INSERT |
2592 DEV_TX_OFFLOAD_QINQ_INSERT |
2593 DEV_TX_OFFLOAD_IPV4_CKSUM |
2594 DEV_TX_OFFLOAD_UDP_CKSUM |
2595 DEV_TX_OFFLOAD_TCP_CKSUM |
2596 DEV_TX_OFFLOAD_SCTP_CKSUM |
2597 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2598 DEV_TX_OFFLOAD_TCP_TSO |
2599 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2600 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2601 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2602 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2603 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2605 dev_info->reta_size = pf->hash_lut_size;
2606 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2608 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2610 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2611 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2612 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2614 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2618 dev_info->default_txconf = (struct rte_eth_txconf) {
2620 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2621 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2622 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2624 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2625 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2626 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2627 ETH_TXQ_FLAGS_NOOFFLOADS,
2630 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2631 .nb_max = I40E_MAX_RING_DESC,
2632 .nb_min = I40E_MIN_RING_DESC,
2633 .nb_align = I40E_ALIGN_RING_DESC,
2636 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2637 .nb_max = I40E_MAX_RING_DESC,
2638 .nb_min = I40E_MIN_RING_DESC,
2639 .nb_align = I40E_ALIGN_RING_DESC,
2642 if (pf->flags & I40E_FLAG_VMDQ) {
2643 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2644 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2645 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2646 pf->max_nb_vmdq_vsi;
2647 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2648 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2649 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2652 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2654 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2655 else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2657 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2660 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2664 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2666 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2667 struct i40e_vsi *vsi = pf->main_vsi;
2668 PMD_INIT_FUNC_TRACE();
2671 return i40e_vsi_add_vlan(vsi, vlan_id);
2673 return i40e_vsi_delete_vlan(vsi, vlan_id);
2677 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2678 enum rte_vlan_type vlan_type,
2681 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2682 uint64_t reg_r = 0, reg_w = 0;
2683 uint16_t reg_id = 0;
2685 int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2687 switch (vlan_type) {
2688 case ETH_VLAN_TYPE_OUTER:
2694 case ETH_VLAN_TYPE_INNER:
2700 "Unsupported vlan type in single vlan.\n");
2706 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2709 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2711 if (ret != I40E_SUCCESS) {
2712 PMD_DRV_LOG(ERR, "Fail to debug read from "
2713 "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2717 PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2718 "0x%08"PRIx64"", reg_id, reg_r);
2720 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2721 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2722 if (reg_r == reg_w) {
2724 PMD_DRV_LOG(DEBUG, "No need to write");
2728 ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2730 if (ret != I40E_SUCCESS) {
2732 PMD_DRV_LOG(ERR, "Fail to debug write to "
2733 "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2736 PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2737 "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2743 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2745 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2746 struct i40e_vsi *vsi = pf->main_vsi;
2748 if (mask & ETH_VLAN_FILTER_MASK) {
2749 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2750 i40e_vsi_config_vlan_filter(vsi, TRUE);
2752 i40e_vsi_config_vlan_filter(vsi, FALSE);
2755 if (mask & ETH_VLAN_STRIP_MASK) {
2756 /* Enable or disable VLAN stripping */
2757 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2758 i40e_vsi_config_vlan_stripping(vsi, TRUE);
2760 i40e_vsi_config_vlan_stripping(vsi, FALSE);
2763 if (mask & ETH_VLAN_EXTEND_MASK) {
2764 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
2765 i40e_vsi_config_double_vlan(vsi, TRUE);
2766 /* Set global registers with default ether type value */
2767 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
2769 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
2773 i40e_vsi_config_double_vlan(vsi, FALSE);
2778 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2779 __rte_unused uint16_t queue,
2780 __rte_unused int on)
2782 PMD_INIT_FUNC_TRACE();
2786 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2788 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2789 struct i40e_vsi *vsi = pf->main_vsi;
2790 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2791 struct i40e_vsi_vlan_pvid_info info;
2793 memset(&info, 0, sizeof(info));
2796 info.config.pvid = pvid;
2798 info.config.reject.tagged =
2799 data->dev_conf.txmode.hw_vlan_reject_tagged;
2800 info.config.reject.untagged =
2801 data->dev_conf.txmode.hw_vlan_reject_untagged;
2804 return i40e_vsi_vlan_pvid_set(vsi, &info);
2808 i40e_dev_led_on(struct rte_eth_dev *dev)
2810 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2811 uint32_t mode = i40e_led_get(hw);
2814 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2820 i40e_dev_led_off(struct rte_eth_dev *dev)
2822 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2823 uint32_t mode = i40e_led_get(hw);
2826 i40e_led_set(hw, 0, false);
2832 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2834 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2835 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2837 fc_conf->pause_time = pf->fc_conf.pause_time;
2838 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2839 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2841 /* Return current mode according to actual setting*/
2842 switch (hw->fc.current_mode) {
2844 fc_conf->mode = RTE_FC_FULL;
2846 case I40E_FC_TX_PAUSE:
2847 fc_conf->mode = RTE_FC_TX_PAUSE;
2849 case I40E_FC_RX_PAUSE:
2850 fc_conf->mode = RTE_FC_RX_PAUSE;
2854 fc_conf->mode = RTE_FC_NONE;
2861 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2863 uint32_t mflcn_reg, fctrl_reg, reg;
2864 uint32_t max_high_water;
2865 uint8_t i, aq_failure;
2869 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2870 [RTE_FC_NONE] = I40E_FC_NONE,
2871 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2872 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2873 [RTE_FC_FULL] = I40E_FC_FULL
2876 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2878 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2879 if ((fc_conf->high_water > max_high_water) ||
2880 (fc_conf->high_water < fc_conf->low_water)) {
2881 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2882 "High_water must <= %d.", max_high_water);
2886 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2887 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2888 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2890 pf->fc_conf.pause_time = fc_conf->pause_time;
2891 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2892 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2894 PMD_INIT_FUNC_TRACE();
2896 /* All the link flow control related enable/disable register
2897 * configuration is handle by the F/W
2899 err = i40e_set_fc(hw, &aq_failure, true);
2903 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
2904 /* Configure flow control refresh threshold,
2905 * the value for stat_tx_pause_refresh_timer[8]
2906 * is used for global pause operation.
2910 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2911 pf->fc_conf.pause_time);
2913 /* configure the timer value included in transmitted pause
2915 * the value for stat_tx_pause_quanta[8] is used for global
2918 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2919 pf->fc_conf.pause_time);
2921 fctrl_reg = I40E_READ_REG(hw,
2922 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2924 if (fc_conf->mac_ctrl_frame_fwd != 0)
2925 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2927 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2929 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2932 /* Configure pause time (2 TCs per register) */
2933 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2934 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2935 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2937 /* Configure flow control refresh threshold value */
2938 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2939 pf->fc_conf.pause_time / 2);
2941 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2943 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2944 *depending on configuration
2946 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2947 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2948 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2950 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2951 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2954 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2957 /* config the water marker both based on the packets and bytes */
2958 I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2959 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2960 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2961 I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2962 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2963 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2964 I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2965 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2967 I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2968 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2971 I40E_WRITE_FLUSH(hw);
2977 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2978 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2980 PMD_INIT_FUNC_TRACE();
2985 /* Add a MAC address, and update filters */
2987 i40e_macaddr_add(struct rte_eth_dev *dev,
2988 struct ether_addr *mac_addr,
2989 __rte_unused uint32_t index,
2992 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2993 struct i40e_mac_filter_info mac_filter;
2994 struct i40e_vsi *vsi;
2997 /* If VMDQ not enabled or configured, return */
2998 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
2999 !pf->nb_cfg_vmdq_vsi)) {
3000 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3001 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3006 if (pool > pf->nb_cfg_vmdq_vsi) {
3007 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3008 pool, pf->nb_cfg_vmdq_vsi);
3012 (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3013 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3014 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3016 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3021 vsi = pf->vmdq[pool - 1].vsi;
3023 ret = i40e_vsi_add_mac(vsi, &mac_filter);
3024 if (ret != I40E_SUCCESS) {
3025 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3030 /* Remove a MAC address, and update filters */
3032 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3034 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3035 struct i40e_vsi *vsi;
3036 struct rte_eth_dev_data *data = dev->data;
3037 struct ether_addr *macaddr;
3042 macaddr = &(data->mac_addrs[index]);
3044 pool_sel = dev->data->mac_pool_sel[index];
3046 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3047 if (pool_sel & (1ULL << i)) {
3051 /* No VMDQ pool enabled or configured */
3052 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3053 (i > pf->nb_cfg_vmdq_vsi)) {
3054 PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
3058 vsi = pf->vmdq[i - 1].vsi;
3060 ret = i40e_vsi_delete_mac(vsi, macaddr);
3063 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3070 /* Set perfect match or hash match of MAC and VLAN for a VF */
3072 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3073 struct rte_eth_mac_filter *filter,
3077 struct i40e_mac_filter_info mac_filter;
3078 struct ether_addr old_mac;
3079 struct ether_addr *new_mac;
3080 struct i40e_pf_vf *vf = NULL;
3085 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3088 hw = I40E_PF_TO_HW(pf);
3090 if (filter == NULL) {
3091 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3095 new_mac = &filter->mac_addr;
3097 if (is_zero_ether_addr(new_mac)) {
3098 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3102 vf_id = filter->dst_id;
3104 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3105 PMD_DRV_LOG(ERR, "Invalid argument.");
3108 vf = &pf->vfs[vf_id];
3110 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3111 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3116 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3117 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3119 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3122 mac_filter.filter_type = filter->filter_type;
3123 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3124 if (ret != I40E_SUCCESS) {
3125 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3128 ether_addr_copy(new_mac, &pf->dev_addr);
3130 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3132 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3133 if (ret != I40E_SUCCESS) {
3134 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3138 /* Clear device address as it has been removed */
3139 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3140 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3146 /* MAC filter handle */
3148 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3151 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3152 struct rte_eth_mac_filter *filter;
3153 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3154 int ret = I40E_NOT_SUPPORTED;
3156 filter = (struct rte_eth_mac_filter *)(arg);
3158 switch (filter_op) {
3159 case RTE_ETH_FILTER_NOP:
3162 case RTE_ETH_FILTER_ADD:
3163 i40e_pf_disable_irq0(hw);
3165 ret = i40e_vf_mac_filter_set(pf, filter, 1);
3166 i40e_pf_enable_irq0(hw);
3168 case RTE_ETH_FILTER_DELETE:
3169 i40e_pf_disable_irq0(hw);
3171 ret = i40e_vf_mac_filter_set(pf, filter, 0);
3172 i40e_pf_enable_irq0(hw);
3175 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3176 ret = I40E_ERR_PARAM;
3184 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3186 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3187 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3193 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3194 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3197 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3201 uint32_t *lut_dw = (uint32_t *)lut;
3202 uint16_t i, lut_size_dw = lut_size / 4;
3204 for (i = 0; i < lut_size_dw; i++)
3205 lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3212 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3221 pf = I40E_VSI_TO_PF(vsi);
3222 hw = I40E_VSI_TO_HW(vsi);
3224 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3225 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3228 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3232 uint32_t *lut_dw = (uint32_t *)lut;
3233 uint16_t i, lut_size_dw = lut_size / 4;
3235 for (i = 0; i < lut_size_dw; i++)
3236 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3237 I40E_WRITE_FLUSH(hw);
3244 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3245 struct rte_eth_rss_reta_entry64 *reta_conf,
3248 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3249 uint16_t i, lut_size = pf->hash_lut_size;
3250 uint16_t idx, shift;
3254 if (reta_size != lut_size ||
3255 reta_size > ETH_RSS_RETA_SIZE_512) {
3256 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3257 "(%d) doesn't match the number hardware can supported "
3258 "(%d)\n", reta_size, lut_size);
3262 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3264 PMD_DRV_LOG(ERR, "No memory can be allocated");
3267 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3270 for (i = 0; i < reta_size; i++) {
3271 idx = i / RTE_RETA_GROUP_SIZE;
3272 shift = i % RTE_RETA_GROUP_SIZE;
3273 if (reta_conf[idx].mask & (1ULL << shift))
3274 lut[i] = reta_conf[idx].reta[shift];
3276 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3285 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3286 struct rte_eth_rss_reta_entry64 *reta_conf,
3289 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3290 uint16_t i, lut_size = pf->hash_lut_size;
3291 uint16_t idx, shift;
3295 if (reta_size != lut_size ||
3296 reta_size > ETH_RSS_RETA_SIZE_512) {
3297 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3298 "(%d) doesn't match the number hardware can supported "
3299 "(%d)\n", reta_size, lut_size);
3303 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3305 PMD_DRV_LOG(ERR, "No memory can be allocated");
3309 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3312 for (i = 0; i < reta_size; i++) {
3313 idx = i / RTE_RETA_GROUP_SIZE;
3314 shift = i % RTE_RETA_GROUP_SIZE;
3315 if (reta_conf[idx].mask & (1ULL << shift))
3316 reta_conf[idx].reta[shift] = lut[i];
3326 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3327 * @hw: pointer to the HW structure
3328 * @mem: pointer to mem struct to fill out
3329 * @size: size of memory requested
3330 * @alignment: what to align the allocation to
3332 enum i40e_status_code
3333 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3334 struct i40e_dma_mem *mem,
3338 const struct rte_memzone *mz = NULL;
3339 char z_name[RTE_MEMZONE_NAMESIZE];
3342 return I40E_ERR_PARAM;
3344 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3345 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3346 alignment, RTE_PGSIZE_2M);
3348 return I40E_ERR_NO_MEMORY;
3352 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3353 mem->zone = (const void *)mz;
3354 PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3355 "%"PRIu64, mz->name, mem->pa);
3357 return I40E_SUCCESS;
3361 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3362 * @hw: pointer to the HW structure
3363 * @mem: ptr to mem struct to free
3365 enum i40e_status_code
3366 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3367 struct i40e_dma_mem *mem)
3370 return I40E_ERR_PARAM;
3372 PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3373 "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3375 rte_memzone_free((const struct rte_memzone *)mem->zone);
3380 return I40E_SUCCESS;
3384 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3385 * @hw: pointer to the HW structure
3386 * @mem: pointer to mem struct to fill out
3387 * @size: size of memory requested
3389 enum i40e_status_code
3390 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3391 struct i40e_virt_mem *mem,
3395 return I40E_ERR_PARAM;
3398 mem->va = rte_zmalloc("i40e", size, 0);
3401 return I40E_SUCCESS;
3403 return I40E_ERR_NO_MEMORY;
3407 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3408 * @hw: pointer to the HW structure
3409 * @mem: pointer to mem struct to free
3411 enum i40e_status_code
3412 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3413 struct i40e_virt_mem *mem)
3416 return I40E_ERR_PARAM;
3421 return I40E_SUCCESS;
3425 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3427 rte_spinlock_init(&sp->spinlock);
3431 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3433 rte_spinlock_lock(&sp->spinlock);
3437 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3439 rte_spinlock_unlock(&sp->spinlock);
3443 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3449 * Get the hardware capabilities, which will be parsed
3450 * and saved into struct i40e_hw.
3453 i40e_get_cap(struct i40e_hw *hw)
3455 struct i40e_aqc_list_capabilities_element_resp *buf;
3456 uint16_t len, size = 0;
3459 /* Calculate a huge enough buff for saving response data temporarily */
3460 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3461 I40E_MAX_CAP_ELE_NUM;
3462 buf = rte_zmalloc("i40e", len, 0);
3464 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3465 return I40E_ERR_NO_MEMORY;
3468 /* Get, parse the capabilities and save it to hw */
3469 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3470 i40e_aqc_opc_list_func_capabilities, NULL);
3471 if (ret != I40E_SUCCESS)
3472 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3474 /* Free the temporary buffer after being used */
3481 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3483 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3484 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3485 uint16_t qp_count = 0, vsi_count = 0;
3487 if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3488 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3491 /* Add the parameter init for LFC */
3492 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3493 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3494 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3496 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3497 pf->max_num_vsi = hw->func_caps.num_vsis;
3498 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3499 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3500 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3502 /* FDir queue/VSI allocation */
3503 pf->fdir_qp_offset = 0;
3504 if (hw->func_caps.fd) {
3505 pf->flags |= I40E_FLAG_FDIR;
3506 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3508 pf->fdir_nb_qps = 0;
3510 qp_count += pf->fdir_nb_qps;
3513 /* LAN queue/VSI allocation */
3514 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3515 if (!hw->func_caps.rss) {
3518 pf->flags |= I40E_FLAG_RSS;
3519 if (hw->mac.type == I40E_MAC_X722)
3520 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3521 pf->lan_nb_qps = pf->lan_nb_qp_max;
3523 qp_count += pf->lan_nb_qps;
3526 /* VF queue/VSI allocation */
3527 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3528 if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3529 pf->flags |= I40E_FLAG_SRIOV;
3530 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3531 pf->vf_num = dev->pci_dev->max_vfs;
3532 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3533 "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3534 pf->vf_nb_qps * pf->vf_num);
3539 qp_count += pf->vf_nb_qps * pf->vf_num;
3540 vsi_count += pf->vf_num;
3542 /* VMDq queue/VSI allocation */
3543 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3544 pf->vmdq_nb_qps = 0;
3545 pf->max_nb_vmdq_vsi = 0;
3546 if (hw->func_caps.vmdq) {
3547 if (qp_count < hw->func_caps.num_tx_qp &&
3548 vsi_count < hw->func_caps.num_vsis) {
3549 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3550 qp_count) / pf->vmdq_nb_qp_max;
3552 /* Limit the maximum number of VMDq vsi to the maximum
3553 * ethdev can support
3555 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3556 hw->func_caps.num_vsis - vsi_count);
3557 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3559 if (pf->max_nb_vmdq_vsi) {
3560 pf->flags |= I40E_FLAG_VMDQ;
3561 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3562 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3563 "per VMDQ VSI, in total %u queues",
3564 pf->max_nb_vmdq_vsi,
3565 pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3566 pf->max_nb_vmdq_vsi);
3568 PMD_DRV_LOG(INFO, "No enough queues left for "
3572 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3575 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3576 vsi_count += pf->max_nb_vmdq_vsi;
3578 if (hw->func_caps.dcb)
3579 pf->flags |= I40E_FLAG_DCB;
3581 if (qp_count > hw->func_caps.num_tx_qp) {
3582 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3583 "the hardware maximum %u", qp_count,
3584 hw->func_caps.num_tx_qp);
3587 if (vsi_count > hw->func_caps.num_vsis) {
3588 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3589 "the hardware maximum %u", vsi_count,
3590 hw->func_caps.num_vsis);
3598 i40e_pf_get_switch_config(struct i40e_pf *pf)
3600 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3601 struct i40e_aqc_get_switch_config_resp *switch_config;
3602 struct i40e_aqc_switch_config_element_resp *element;
3603 uint16_t start_seid = 0, num_reported;
3606 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3607 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3608 if (!switch_config) {
3609 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3613 /* Get the switch configurations */
3614 ret = i40e_aq_get_switch_config(hw, switch_config,
3615 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3616 if (ret != I40E_SUCCESS) {
3617 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3620 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3621 if (num_reported != 1) { /* The number should be 1 */
3622 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3626 /* Parse the switch configuration elements */
3627 element = &(switch_config->element[0]);
3628 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3629 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3630 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3632 PMD_DRV_LOG(INFO, "Unknown element type");
3635 rte_free(switch_config);
3641 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3644 struct pool_entry *entry;
3646 if (pool == NULL || num == 0)
3649 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3650 if (entry == NULL) {
3651 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3655 /* queue heap initialize */
3656 pool->num_free = num;
3657 pool->num_alloc = 0;
3659 LIST_INIT(&pool->alloc_list);
3660 LIST_INIT(&pool->free_list);
3662 /* Initialize element */
3666 LIST_INSERT_HEAD(&pool->free_list, entry, next);
3671 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3673 struct pool_entry *entry, *next_entry;
3678 for (entry = LIST_FIRST(&pool->alloc_list);
3679 entry && (next_entry = LIST_NEXT(entry, next), 1);
3680 entry = next_entry) {
3681 LIST_REMOVE(entry, next);
3685 for (entry = LIST_FIRST(&pool->free_list);
3686 entry && (next_entry = LIST_NEXT(entry, next), 1);
3687 entry = next_entry) {
3688 LIST_REMOVE(entry, next);
3693 pool->num_alloc = 0;
3695 LIST_INIT(&pool->alloc_list);
3696 LIST_INIT(&pool->free_list);
3700 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3703 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3704 uint32_t pool_offset;
3708 PMD_DRV_LOG(ERR, "Invalid parameter");
3712 pool_offset = base - pool->base;
3713 /* Lookup in alloc list */
3714 LIST_FOREACH(entry, &pool->alloc_list, next) {
3715 if (entry->base == pool_offset) {
3716 valid_entry = entry;
3717 LIST_REMOVE(entry, next);
3722 /* Not find, return */
3723 if (valid_entry == NULL) {
3724 PMD_DRV_LOG(ERR, "Failed to find entry");
3729 * Found it, move it to free list and try to merge.
3730 * In order to make merge easier, always sort it by qbase.
3731 * Find adjacent prev and last entries.
3734 LIST_FOREACH(entry, &pool->free_list, next) {
3735 if (entry->base > valid_entry->base) {
3743 /* Try to merge with next one*/
3745 /* Merge with next one */
3746 if (valid_entry->base + valid_entry->len == next->base) {
3747 next->base = valid_entry->base;
3748 next->len += valid_entry->len;
3749 rte_free(valid_entry);
3756 /* Merge with previous one */
3757 if (prev->base + prev->len == valid_entry->base) {
3758 prev->len += valid_entry->len;
3759 /* If it merge with next one, remove next node */
3761 LIST_REMOVE(valid_entry, next);
3762 rte_free(valid_entry);
3764 rte_free(valid_entry);
3770 /* Not find any entry to merge, insert */
3773 LIST_INSERT_AFTER(prev, valid_entry, next);
3774 else if (next != NULL)
3775 LIST_INSERT_BEFORE(next, valid_entry, next);
3776 else /* It's empty list, insert to head */
3777 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3780 pool->num_free += valid_entry->len;
3781 pool->num_alloc -= valid_entry->len;
3787 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3790 struct pool_entry *entry, *valid_entry;
3792 if (pool == NULL || num == 0) {
3793 PMD_DRV_LOG(ERR, "Invalid parameter");
3797 if (pool->num_free < num) {
3798 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3799 num, pool->num_free);
3804 /* Lookup in free list and find most fit one */
3805 LIST_FOREACH(entry, &pool->free_list, next) {
3806 if (entry->len >= num) {
3808 if (entry->len == num) {
3809 valid_entry = entry;
3812 if (valid_entry == NULL || valid_entry->len > entry->len)
3813 valid_entry = entry;
3817 /* Not find one to satisfy the request, return */
3818 if (valid_entry == NULL) {
3819 PMD_DRV_LOG(ERR, "No valid entry found");
3823 * The entry have equal queue number as requested,
3824 * remove it from alloc_list.
3826 if (valid_entry->len == num) {
3827 LIST_REMOVE(valid_entry, next);
3830 * The entry have more numbers than requested,
3831 * create a new entry for alloc_list and minus its
3832 * queue base and number in free_list.
3834 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3835 if (entry == NULL) {
3836 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3840 entry->base = valid_entry->base;
3842 valid_entry->base += num;
3843 valid_entry->len -= num;
3844 valid_entry = entry;
3847 /* Insert it into alloc list, not sorted */
3848 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3850 pool->num_free -= valid_entry->len;
3851 pool->num_alloc += valid_entry->len;
3853 return valid_entry->base + pool->base;
3857 * bitmap_is_subset - Check whether src2 is subset of src1
3860 bitmap_is_subset(uint8_t src1, uint8_t src2)
3862 return !((src1 ^ src2) & src2);
3865 static enum i40e_status_code
3866 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3868 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3870 /* If DCB is not supported, only default TC is supported */
3871 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3872 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3873 return I40E_NOT_SUPPORTED;
3876 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3877 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3878 "HW support 0x%x", hw->func_caps.enabled_tcmap,
3880 return I40E_NOT_SUPPORTED;
3882 return I40E_SUCCESS;
3886 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3887 struct i40e_vsi_vlan_pvid_info *info)
3890 struct i40e_vsi_context ctxt;
3891 uint8_t vlan_flags = 0;
3894 if (vsi == NULL || info == NULL) {
3895 PMD_DRV_LOG(ERR, "invalid parameters");
3896 return I40E_ERR_PARAM;
3900 vsi->info.pvid = info->config.pvid;
3902 * If insert pvid is enabled, only tagged pkts are
3903 * allowed to be sent out.
3905 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3906 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3909 if (info->config.reject.tagged == 0)
3910 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3912 if (info->config.reject.untagged == 0)
3913 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3915 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3916 I40E_AQ_VSI_PVLAN_MODE_MASK);
3917 vsi->info.port_vlan_flags |= vlan_flags;
3918 vsi->info.valid_sections =
3919 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3920 memset(&ctxt, 0, sizeof(ctxt));
3921 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3922 ctxt.seid = vsi->seid;
3924 hw = I40E_VSI_TO_HW(vsi);
3925 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3926 if (ret != I40E_SUCCESS)
3927 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3933 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3935 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3937 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3939 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3940 if (ret != I40E_SUCCESS)
3944 PMD_DRV_LOG(ERR, "seid not valid");
3948 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3949 tc_bw_data.tc_valid_bits = enabled_tcmap;
3950 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3951 tc_bw_data.tc_bw_credits[i] =
3952 (enabled_tcmap & (1 << i)) ? 1 : 0;
3954 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3955 if (ret != I40E_SUCCESS) {
3956 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3960 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3961 sizeof(vsi->info.qs_handle));
3962 return I40E_SUCCESS;
3965 static enum i40e_status_code
3966 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3967 struct i40e_aqc_vsi_properties_data *info,
3968 uint8_t enabled_tcmap)
3970 enum i40e_status_code ret;
3971 int i, total_tc = 0;
3972 uint16_t qpnum_per_tc, bsf, qp_idx;
3974 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3975 if (ret != I40E_SUCCESS)
3978 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3979 if (enabled_tcmap & (1 << i))
3981 vsi->enabled_tc = enabled_tcmap;
3983 /* Number of queues per enabled TC */
3984 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3985 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3986 bsf = rte_bsf32(qpnum_per_tc);
3988 /* Adjust the queue number to actual queues that can be applied */
3989 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3990 vsi->nb_qps = qpnum_per_tc * total_tc;
3993 * Configure TC and queue mapping parameters, for enabled TC,
3994 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3995 * default queue will serve it.
3998 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3999 if (vsi->enabled_tc & (1 << i)) {
4000 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4001 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4002 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4003 qp_idx += qpnum_per_tc;
4005 info->tc_mapping[i] = 0;
4008 /* Associate queue number with VSI */
4009 if (vsi->type == I40E_VSI_SRIOV) {
4010 info->mapping_flags |=
4011 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4012 for (i = 0; i < vsi->nb_qps; i++)
4013 info->queue_mapping[i] =
4014 rte_cpu_to_le_16(vsi->base_queue + i);
4016 info->mapping_flags |=
4017 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4018 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4020 info->valid_sections |=
4021 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4023 return I40E_SUCCESS;
4027 i40e_veb_release(struct i40e_veb *veb)
4029 struct i40e_vsi *vsi;
4035 if (!TAILQ_EMPTY(&veb->head)) {
4036 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4039 /* associate_vsi field is NULL for floating VEB */
4040 if (veb->associate_vsi != NULL) {
4041 vsi = veb->associate_vsi;
4042 hw = I40E_VSI_TO_HW(vsi);
4044 vsi->uplink_seid = veb->uplink_seid;
4047 veb->associate_pf->main_vsi->floating_veb = NULL;
4048 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4051 i40e_aq_delete_element(hw, veb->seid, NULL);
4053 return I40E_SUCCESS;
4057 static struct i40e_veb *
4058 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4060 struct i40e_veb *veb;
4066 "veb setup failed, associated PF shouldn't null");
4069 hw = I40E_PF_TO_HW(pf);
4071 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4073 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4077 veb->associate_vsi = vsi;
4078 veb->associate_pf = pf;
4079 TAILQ_INIT(&veb->head);
4080 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4082 /* create floating veb if vsi is NULL */
4084 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4085 I40E_DEFAULT_TCMAP, false,
4086 &veb->seid, false, NULL);
4088 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4089 true, &veb->seid, false, NULL);
4092 if (ret != I40E_SUCCESS) {
4093 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4094 hw->aq.asq_last_status);
4098 /* get statistics index */
4099 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4100 &veb->stats_idx, NULL, NULL, NULL);
4101 if (ret != I40E_SUCCESS) {
4102 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
4103 hw->aq.asq_last_status);
4106 /* Get VEB bandwidth, to be implemented */
4107 /* Now associated vsi binding to the VEB, set uplink to this VEB */
4109 vsi->uplink_seid = veb->seid;
4118 i40e_vsi_release(struct i40e_vsi *vsi)
4122 struct i40e_vsi_list *vsi_list;
4125 struct i40e_mac_filter *f;
4126 uint16_t user_param;
4129 return I40E_SUCCESS;
4131 user_param = vsi->user_param;
4133 pf = I40E_VSI_TO_PF(vsi);
4134 hw = I40E_VSI_TO_HW(vsi);
4136 /* VSI has child to attach, release child first */
4138 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4139 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4142 i40e_veb_release(vsi->veb);
4145 if (vsi->floating_veb) {
4146 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4147 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4152 /* Remove all macvlan filters of the VSI */
4153 i40e_vsi_remove_all_macvlan_filter(vsi);
4154 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4157 if (vsi->type != I40E_VSI_MAIN &&
4158 ((vsi->type != I40E_VSI_SRIOV) ||
4159 !pf->floating_veb_list[user_param])) {
4160 /* Remove vsi from parent's sibling list */
4161 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4162 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4163 return I40E_ERR_PARAM;
4165 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4166 &vsi->sib_vsi_list, list);
4168 /* Remove all switch element of the VSI */
4169 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4170 if (ret != I40E_SUCCESS)
4171 PMD_DRV_LOG(ERR, "Failed to delete element");
4174 if ((vsi->type == I40E_VSI_SRIOV) &&
4175 pf->floating_veb_list[user_param]) {
4176 /* Remove vsi from parent's sibling list */
4177 if (vsi->parent_vsi == NULL ||
4178 vsi->parent_vsi->floating_veb == NULL) {
4179 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4180 return I40E_ERR_PARAM;
4182 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4183 &vsi->sib_vsi_list, list);
4185 /* Remove all switch element of the VSI */
4186 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4187 if (ret != I40E_SUCCESS)
4188 PMD_DRV_LOG(ERR, "Failed to delete element");
4191 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4193 if (vsi->type != I40E_VSI_SRIOV)
4194 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4197 return I40E_SUCCESS;
4201 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4203 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4204 struct i40e_aqc_remove_macvlan_element_data def_filter;
4205 struct i40e_mac_filter_info filter;
4208 if (vsi->type != I40E_VSI_MAIN)
4209 return I40E_ERR_CONFIG;
4210 memset(&def_filter, 0, sizeof(def_filter));
4211 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4213 def_filter.vlan_tag = 0;
4214 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4215 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4216 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4217 if (ret != I40E_SUCCESS) {
4218 struct i40e_mac_filter *f;
4219 struct ether_addr *mac;
4221 PMD_DRV_LOG(WARNING, "Cannot remove the default "
4223 /* It needs to add the permanent mac into mac list */
4224 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4226 PMD_DRV_LOG(ERR, "failed to allocate memory");
4227 return I40E_ERR_NO_MEMORY;
4229 mac = &f->mac_info.mac_addr;
4230 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4232 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4233 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4238 (void)rte_memcpy(&filter.mac_addr,
4239 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4240 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4241 return i40e_vsi_add_mac(vsi, &filter);
4245 * i40e_vsi_get_bw_config - Query VSI BW Information
4246 * @vsi: the VSI to be queried
4248 * Returns 0 on success, negative value on failure
4250 static enum i40e_status_code
4251 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4253 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4254 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4255 struct i40e_hw *hw = &vsi->adapter->hw;
4260 memset(&bw_config, 0, sizeof(bw_config));
4261 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4262 if (ret != I40E_SUCCESS) {
4263 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4264 hw->aq.asq_last_status);
4268 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4269 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4270 &ets_sla_config, NULL);
4271 if (ret != I40E_SUCCESS) {
4272 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
4273 "configuration %u", hw->aq.asq_last_status);
4277 /* store and print out BW info */
4278 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4279 vsi->bw_info.bw_max = bw_config.max_bw;
4280 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4281 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4282 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4283 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4285 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4286 vsi->bw_info.bw_ets_share_credits[i] =
4287 ets_sla_config.share_credits[i];
4288 vsi->bw_info.bw_ets_credits[i] =
4289 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4290 /* 4 bits per TC, 4th bit is reserved */
4291 vsi->bw_info.bw_ets_max[i] =
4292 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4293 RTE_LEN2MASK(3, uint8_t));
4294 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4295 vsi->bw_info.bw_ets_share_credits[i]);
4296 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4297 vsi->bw_info.bw_ets_credits[i]);
4298 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4299 vsi->bw_info.bw_ets_max[i]);
4302 return I40E_SUCCESS;
4305 /* i40e_enable_pf_lb
4306 * @pf: pointer to the pf structure
4308 * allow loopback on pf
4311 i40e_enable_pf_lb(struct i40e_pf *pf)
4313 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4314 struct i40e_vsi_context ctxt;
4317 /* Use the FW API if FW >= v5.0 */
4318 if (hw->aq.fw_maj_ver < 5) {
4319 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4323 memset(&ctxt, 0, sizeof(ctxt));
4324 ctxt.seid = pf->main_vsi_seid;
4325 ctxt.pf_num = hw->pf_id;
4326 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4328 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4329 ret, hw->aq.asq_last_status);
4332 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4333 ctxt.info.valid_sections =
4334 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4335 ctxt.info.switch_id |=
4336 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4338 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4340 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
4341 hw->aq.asq_last_status);
4346 i40e_vsi_setup(struct i40e_pf *pf,
4347 enum i40e_vsi_type type,
4348 struct i40e_vsi *uplink_vsi,
4349 uint16_t user_param)
4351 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4352 struct i40e_vsi *vsi;
4353 struct i40e_mac_filter_info filter;
4355 struct i40e_vsi_context ctxt;
4356 struct ether_addr broadcast =
4357 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4359 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4360 uplink_vsi == NULL) {
4361 PMD_DRV_LOG(ERR, "VSI setup failed, "
4362 "VSI link shouldn't be NULL");
4366 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4367 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
4368 "uplink VSI should be NULL");
4373 * 1.type is not MAIN and uplink vsi is not NULL
4374 * If uplink vsi didn't setup VEB, create one first under veb field
4375 * 2.type is SRIOV and the uplink is NULL
4376 * If floating VEB is NULL, create one veb under floating veb field
4379 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4380 uplink_vsi->veb == NULL) {
4381 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4383 if (uplink_vsi->veb == NULL) {
4384 PMD_DRV_LOG(ERR, "VEB setup failed");
4387 /* set ALLOWLOOPBACk on pf, when veb is created */
4388 i40e_enable_pf_lb(pf);
4391 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4392 pf->main_vsi->floating_veb == NULL) {
4393 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4395 if (pf->main_vsi->floating_veb == NULL) {
4396 PMD_DRV_LOG(ERR, "VEB setup failed");
4401 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4403 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4406 TAILQ_INIT(&vsi->mac_list);
4408 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4409 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4410 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4411 vsi->user_param = user_param;
4412 /* Allocate queues */
4413 switch (vsi->type) {
4414 case I40E_VSI_MAIN :
4415 vsi->nb_qps = pf->lan_nb_qps;
4417 case I40E_VSI_SRIOV :
4418 vsi->nb_qps = pf->vf_nb_qps;
4420 case I40E_VSI_VMDQ2:
4421 vsi->nb_qps = pf->vmdq_nb_qps;
4424 vsi->nb_qps = pf->fdir_nb_qps;
4430 * The filter status descriptor is reported in rx queue 0,
4431 * while the tx queue for fdir filter programming has no
4432 * such constraints, can be non-zero queues.
4433 * To simplify it, choose FDIR vsi use queue 0 pair.
4434 * To make sure it will use queue 0 pair, queue allocation
4435 * need be done before this function is called
4437 if (type != I40E_VSI_FDIR) {
4438 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4440 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4444 vsi->base_queue = ret;
4446 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4448 /* VF has MSIX interrupt in VF range, don't allocate here */
4449 if (type == I40E_VSI_MAIN) {
4450 ret = i40e_res_pool_alloc(&pf->msix_pool,
4451 RTE_MIN(vsi->nb_qps,
4452 RTE_MAX_RXTX_INTR_VEC_ID));
4454 PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4456 goto fail_queue_alloc;
4458 vsi->msix_intr = ret;
4459 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4460 } else if (type != I40E_VSI_SRIOV) {
4461 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4463 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4464 goto fail_queue_alloc;
4466 vsi->msix_intr = ret;
4474 if (type == I40E_VSI_MAIN) {
4475 /* For main VSI, no need to add since it's default one */
4476 vsi->uplink_seid = pf->mac_seid;
4477 vsi->seid = pf->main_vsi_seid;
4478 /* Bind queues with specific MSIX interrupt */
4480 * Needs 2 interrupt at least, one for misc cause which will
4481 * enabled from OS side, Another for queues binding the
4482 * interrupt from device side only.
4485 /* Get default VSI parameters from hardware */
4486 memset(&ctxt, 0, sizeof(ctxt));
4487 ctxt.seid = vsi->seid;
4488 ctxt.pf_num = hw->pf_id;
4489 ctxt.uplink_seid = vsi->uplink_seid;
4491 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4492 if (ret != I40E_SUCCESS) {
4493 PMD_DRV_LOG(ERR, "Failed to get VSI params");
4494 goto fail_msix_alloc;
4496 (void)rte_memcpy(&vsi->info, &ctxt.info,
4497 sizeof(struct i40e_aqc_vsi_properties_data));
4498 vsi->vsi_id = ctxt.vsi_number;
4499 vsi->info.valid_sections = 0;
4501 /* Configure tc, enabled TC0 only */
4502 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4504 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4505 goto fail_msix_alloc;
4508 /* TC, queue mapping */
4509 memset(&ctxt, 0, sizeof(ctxt));
4510 vsi->info.valid_sections |=
4511 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4512 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4513 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4514 (void)rte_memcpy(&ctxt.info, &vsi->info,
4515 sizeof(struct i40e_aqc_vsi_properties_data));
4516 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4517 I40E_DEFAULT_TCMAP);
4518 if (ret != I40E_SUCCESS) {
4519 PMD_DRV_LOG(ERR, "Failed to configure "
4520 "TC queue mapping");
4521 goto fail_msix_alloc;
4523 ctxt.seid = vsi->seid;
4524 ctxt.pf_num = hw->pf_id;
4525 ctxt.uplink_seid = vsi->uplink_seid;
4528 /* Update VSI parameters */
4529 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4530 if (ret != I40E_SUCCESS) {
4531 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4532 goto fail_msix_alloc;
4535 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4536 sizeof(vsi->info.tc_mapping));
4537 (void)rte_memcpy(&vsi->info.queue_mapping,
4538 &ctxt.info.queue_mapping,
4539 sizeof(vsi->info.queue_mapping));
4540 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4541 vsi->info.valid_sections = 0;
4543 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4547 * Updating default filter settings are necessary to prevent
4548 * reception of tagged packets.
4549 * Some old firmware configurations load a default macvlan
4550 * filter which accepts both tagged and untagged packets.
4551 * The updating is to use a normal filter instead if needed.
4552 * For NVM 4.2.2 or after, the updating is not needed anymore.
4553 * The firmware with correct configurations load the default
4554 * macvlan filter which is expected and cannot be removed.
4556 i40e_update_default_filter_setting(vsi);
4557 i40e_config_qinq(hw, vsi);
4558 } else if (type == I40E_VSI_SRIOV) {
4559 memset(&ctxt, 0, sizeof(ctxt));
4561 * For other VSI, the uplink_seid equals to uplink VSI's
4562 * uplink_seid since they share same VEB
4564 if (uplink_vsi == NULL)
4565 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4567 vsi->uplink_seid = uplink_vsi->uplink_seid;
4568 ctxt.pf_num = hw->pf_id;
4569 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4570 ctxt.uplink_seid = vsi->uplink_seid;
4571 ctxt.connection_type = 0x1;
4572 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4574 /* Use the VEB configuration if FW >= v5.0 */
4575 if (hw->aq.fw_maj_ver >= 5) {
4576 /* Configure switch ID */
4577 ctxt.info.valid_sections |=
4578 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4579 ctxt.info.switch_id =
4580 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4583 /* Configure port/vlan */
4584 ctxt.info.valid_sections |=
4585 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4586 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4587 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4588 I40E_DEFAULT_TCMAP);
4589 if (ret != I40E_SUCCESS) {
4590 PMD_DRV_LOG(ERR, "Failed to configure "
4591 "TC queue mapping");
4592 goto fail_msix_alloc;
4594 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4595 ctxt.info.valid_sections |=
4596 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4598 * Since VSI is not created yet, only configure parameter,
4599 * will add vsi below.
4602 i40e_config_qinq(hw, vsi);
4603 } else if (type == I40E_VSI_VMDQ2) {
4604 memset(&ctxt, 0, sizeof(ctxt));
4606 * For other VSI, the uplink_seid equals to uplink VSI's
4607 * uplink_seid since they share same VEB
4609 vsi->uplink_seid = uplink_vsi->uplink_seid;
4610 ctxt.pf_num = hw->pf_id;
4612 ctxt.uplink_seid = vsi->uplink_seid;
4613 ctxt.connection_type = 0x1;
4614 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4616 ctxt.info.valid_sections |=
4617 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4618 /* user_param carries flag to enable loop back */
4620 ctxt.info.switch_id =
4621 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4622 ctxt.info.switch_id |=
4623 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4626 /* Configure port/vlan */
4627 ctxt.info.valid_sections |=
4628 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4629 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4630 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4631 I40E_DEFAULT_TCMAP);
4632 if (ret != I40E_SUCCESS) {
4633 PMD_DRV_LOG(ERR, "Failed to configure "
4634 "TC queue mapping");
4635 goto fail_msix_alloc;
4637 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4638 ctxt.info.valid_sections |=
4639 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4640 } else if (type == I40E_VSI_FDIR) {
4641 memset(&ctxt, 0, sizeof(ctxt));
4642 vsi->uplink_seid = uplink_vsi->uplink_seid;
4643 ctxt.pf_num = hw->pf_id;
4645 ctxt.uplink_seid = vsi->uplink_seid;
4646 ctxt.connection_type = 0x1; /* regular data port */
4647 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4648 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4649 I40E_DEFAULT_TCMAP);
4650 if (ret != I40E_SUCCESS) {
4651 PMD_DRV_LOG(ERR, "Failed to configure "
4652 "TC queue mapping.");
4653 goto fail_msix_alloc;
4655 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4656 ctxt.info.valid_sections |=
4657 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4659 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4660 goto fail_msix_alloc;
4663 if (vsi->type != I40E_VSI_MAIN) {
4664 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4665 if (ret != I40E_SUCCESS) {
4666 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4667 hw->aq.asq_last_status);
4668 goto fail_msix_alloc;
4670 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4671 vsi->info.valid_sections = 0;
4672 vsi->seid = ctxt.seid;
4673 vsi->vsi_id = ctxt.vsi_number;
4674 vsi->sib_vsi_list.vsi = vsi;
4675 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4676 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4677 &vsi->sib_vsi_list, list);
4679 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4680 &vsi->sib_vsi_list, list);
4684 /* MAC/VLAN configuration */
4685 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4686 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4688 ret = i40e_vsi_add_mac(vsi, &filter);
4689 if (ret != I40E_SUCCESS) {
4690 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4691 goto fail_msix_alloc;
4694 /* Get VSI BW information */
4695 i40e_vsi_get_bw_config(vsi);
4698 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4700 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4706 /* Configure vlan filter on or off */
4708 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4711 struct i40e_mac_filter *f;
4713 struct i40e_mac_filter_info *mac_filter;
4714 enum rte_mac_filter_type desired_filter;
4715 int ret = I40E_SUCCESS;
4718 /* Filter to match MAC and VLAN */
4719 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4721 /* Filter to match only MAC */
4722 desired_filter = RTE_MAC_PERFECT_MATCH;
4727 mac_filter = rte_zmalloc("mac_filter_info_data",
4728 num * sizeof(*mac_filter), 0);
4729 if (mac_filter == NULL) {
4730 PMD_DRV_LOG(ERR, "failed to allocate memory");
4731 return I40E_ERR_NO_MEMORY;
4736 /* Remove all existing mac */
4737 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
4738 mac_filter[i] = f->mac_info;
4739 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4741 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4742 on ? "enable" : "disable");
4748 /* Override with new filter */
4749 for (i = 0; i < num; i++) {
4750 mac_filter[i].filter_type = desired_filter;
4751 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4753 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4754 on ? "enable" : "disable");
4760 rte_free(mac_filter);
4764 /* Configure vlan stripping on or off */
4766 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4768 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4769 struct i40e_vsi_context ctxt;
4771 int ret = I40E_SUCCESS;
4773 /* Check if it has been already on or off */
4774 if (vsi->info.valid_sections &
4775 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4777 if ((vsi->info.port_vlan_flags &
4778 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4779 return 0; /* already on */
4781 if ((vsi->info.port_vlan_flags &
4782 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4783 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4784 return 0; /* already off */
4789 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4791 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4792 vsi->info.valid_sections =
4793 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4794 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4795 vsi->info.port_vlan_flags |= vlan_flags;
4796 ctxt.seid = vsi->seid;
4797 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4798 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4800 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4801 on ? "enable" : "disable");
4807 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4809 struct rte_eth_dev_data *data = dev->data;
4813 /* Apply vlan offload setting */
4814 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
4815 i40e_vlan_offload_set(dev, mask);
4817 /* Apply double-vlan setting, not implemented yet */
4819 /* Apply pvid setting */
4820 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4821 data->dev_conf.txmode.hw_vlan_insert_pvid);
4823 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4829 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4831 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4833 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4837 i40e_update_flow_control(struct i40e_hw *hw)
4839 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4840 struct i40e_link_status link_status;
4841 uint32_t rxfc = 0, txfc = 0, reg;
4845 memset(&link_status, 0, sizeof(link_status));
4846 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4847 if (ret != I40E_SUCCESS) {
4848 PMD_DRV_LOG(ERR, "Failed to get link status information");
4849 goto write_reg; /* Disable flow control */
4852 an_info = hw->phy.link_info.an_info;
4853 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4854 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4855 ret = I40E_ERR_NOT_READY;
4856 goto write_reg; /* Disable flow control */
4859 * If link auto negotiation is enabled, flow control needs to
4860 * be configured according to it
4862 switch (an_info & I40E_LINK_PAUSE_RXTX) {
4863 case I40E_LINK_PAUSE_RXTX:
4866 hw->fc.current_mode = I40E_FC_FULL;
4868 case I40E_AQ_LINK_PAUSE_RX:
4870 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4872 case I40E_AQ_LINK_PAUSE_TX:
4874 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4877 hw->fc.current_mode = I40E_FC_NONE;
4882 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4883 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4884 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4885 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4886 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4887 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4894 i40e_pf_setup(struct i40e_pf *pf)
4896 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4897 struct i40e_filter_control_settings settings;
4898 struct i40e_vsi *vsi;
4901 /* Clear all stats counters */
4902 pf->offset_loaded = FALSE;
4903 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4904 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4906 ret = i40e_pf_get_switch_config(pf);
4907 if (ret != I40E_SUCCESS) {
4908 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4911 if (pf->flags & I40E_FLAG_FDIR) {
4912 /* make queue allocated first, let FDIR use queue pair 0*/
4913 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4914 if (ret != I40E_FDIR_QUEUE_ID) {
4915 PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4917 pf->flags &= ~I40E_FLAG_FDIR;
4920 /* main VSI setup */
4921 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4923 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4924 return I40E_ERR_NOT_READY;
4928 /* Configure filter control */
4929 memset(&settings, 0, sizeof(settings));
4930 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4931 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4932 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4933 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4935 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4936 hw->func_caps.rss_table_size);
4937 return I40E_ERR_PARAM;
4939 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4940 "size: %u\n", hw->func_caps.rss_table_size);
4941 pf->hash_lut_size = hw->func_caps.rss_table_size;
4943 /* Enable ethtype and macvlan filters */
4944 settings.enable_ethtype = TRUE;
4945 settings.enable_macvlan = TRUE;
4946 ret = i40e_set_filter_control(hw, &settings);
4948 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4951 /* Update flow control according to the auto negotiation */
4952 i40e_update_flow_control(hw);
4954 return I40E_SUCCESS;
4958 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4964 * Set or clear TX Queue Disable flags,
4965 * which is required by hardware.
4967 i40e_pre_tx_queue_cfg(hw, q_idx, on);
4968 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4970 /* Wait until the request is finished */
4971 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4972 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4973 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4974 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4975 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4981 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4982 return I40E_SUCCESS; /* already on, skip next steps */
4984 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4985 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4987 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4988 return I40E_SUCCESS; /* already off, skip next steps */
4989 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4991 /* Write the register */
4992 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4993 /* Check the result */
4994 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4995 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4996 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4998 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4999 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5002 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5003 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5007 /* Check if it is timeout */
5008 if (j >= I40E_CHK_Q_ENA_COUNT) {
5009 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5010 (on ? "enable" : "disable"), q_idx);
5011 return I40E_ERR_TIMEOUT;
5014 return I40E_SUCCESS;
5017 /* Swith on or off the tx queues */
5019 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5021 struct rte_eth_dev_data *dev_data = pf->dev_data;
5022 struct i40e_tx_queue *txq;
5023 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5027 for (i = 0; i < dev_data->nb_tx_queues; i++) {
5028 txq = dev_data->tx_queues[i];
5029 /* Don't operate the queue if not configured or
5030 * if starting only per queue */
5031 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5034 ret = i40e_dev_tx_queue_start(dev, i);
5036 ret = i40e_dev_tx_queue_stop(dev, i);
5037 if ( ret != I40E_SUCCESS)
5041 return I40E_SUCCESS;
5045 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5050 /* Wait until the request is finished */
5051 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5052 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5053 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5054 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5055 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5060 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5061 return I40E_SUCCESS; /* Already on, skip next steps */
5062 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5064 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5065 return I40E_SUCCESS; /* Already off, skip next steps */
5066 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5069 /* Write the register */
5070 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5071 /* Check the result */
5072 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5073 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5074 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5076 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5077 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5080 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5081 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5086 /* Check if it is timeout */
5087 if (j >= I40E_CHK_Q_ENA_COUNT) {
5088 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5089 (on ? "enable" : "disable"), q_idx);
5090 return I40E_ERR_TIMEOUT;
5093 return I40E_SUCCESS;
5095 /* Switch on or off the rx queues */
5097 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5099 struct rte_eth_dev_data *dev_data = pf->dev_data;
5100 struct i40e_rx_queue *rxq;
5101 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5105 for (i = 0; i < dev_data->nb_rx_queues; i++) {
5106 rxq = dev_data->rx_queues[i];
5107 /* Don't operate the queue if not configured or
5108 * if starting only per queue */
5109 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5112 ret = i40e_dev_rx_queue_start(dev, i);
5114 ret = i40e_dev_rx_queue_stop(dev, i);
5115 if (ret != I40E_SUCCESS)
5119 return I40E_SUCCESS;
5122 /* Switch on or off all the rx/tx queues */
5124 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5129 /* enable rx queues before enabling tx queues */
5130 ret = i40e_dev_switch_rx_queues(pf, on);
5132 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5135 ret = i40e_dev_switch_tx_queues(pf, on);
5137 /* Stop tx queues before stopping rx queues */
5138 ret = i40e_dev_switch_tx_queues(pf, on);
5140 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5143 ret = i40e_dev_switch_rx_queues(pf, on);
5149 /* Initialize VSI for TX */
5151 i40e_dev_tx_init(struct i40e_pf *pf)
5153 struct rte_eth_dev_data *data = pf->dev_data;
5155 uint32_t ret = I40E_SUCCESS;
5156 struct i40e_tx_queue *txq;
5158 for (i = 0; i < data->nb_tx_queues; i++) {
5159 txq = data->tx_queues[i];
5160 if (!txq || !txq->q_set)
5162 ret = i40e_tx_queue_init(txq);
5163 if (ret != I40E_SUCCESS)
5166 if (ret == I40E_SUCCESS)
5167 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5173 /* Initialize VSI for RX */
5175 i40e_dev_rx_init(struct i40e_pf *pf)
5177 struct rte_eth_dev_data *data = pf->dev_data;
5178 int ret = I40E_SUCCESS;
5180 struct i40e_rx_queue *rxq;
5182 i40e_pf_config_mq_rx(pf);
5183 for (i = 0; i < data->nb_rx_queues; i++) {
5184 rxq = data->rx_queues[i];
5185 if (!rxq || !rxq->q_set)
5188 ret = i40e_rx_queue_init(rxq);
5189 if (ret != I40E_SUCCESS) {
5190 PMD_DRV_LOG(ERR, "Failed to do RX queue "
5195 if (ret == I40E_SUCCESS)
5196 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5203 i40e_dev_rxtx_init(struct i40e_pf *pf)
5207 err = i40e_dev_tx_init(pf);
5209 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5212 err = i40e_dev_rx_init(pf);
5214 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5222 i40e_vmdq_setup(struct rte_eth_dev *dev)
5224 struct rte_eth_conf *conf = &dev->data->dev_conf;
5225 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5226 int i, err, conf_vsis, j, loop;
5227 struct i40e_vsi *vsi;
5228 struct i40e_vmdq_info *vmdq_info;
5229 struct rte_eth_vmdq_rx_conf *vmdq_conf;
5230 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5233 * Disable interrupt to avoid message from VF. Furthermore, it will
5234 * avoid race condition in VSI creation/destroy.
5236 i40e_pf_disable_irq0(hw);
5238 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5239 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5243 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5244 if (conf_vsis > pf->max_nb_vmdq_vsi) {
5245 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5246 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5247 pf->max_nb_vmdq_vsi);
5251 if (pf->vmdq != NULL) {
5252 PMD_INIT_LOG(INFO, "VMDQ already configured");
5256 pf->vmdq = rte_zmalloc("vmdq_info_struct",
5257 sizeof(*vmdq_info) * conf_vsis, 0);
5259 if (pf->vmdq == NULL) {
5260 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5264 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5266 /* Create VMDQ VSI */
5267 for (i = 0; i < conf_vsis; i++) {
5268 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5269 vmdq_conf->enable_loop_back);
5271 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5275 vmdq_info = &pf->vmdq[i];
5277 vmdq_info->vsi = vsi;
5279 pf->nb_cfg_vmdq_vsi = conf_vsis;
5281 /* Configure Vlan */
5282 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5283 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5284 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5285 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5286 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5287 vmdq_conf->pool_map[i].vlan_id, j);
5289 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5290 vmdq_conf->pool_map[i].vlan_id);
5292 PMD_INIT_LOG(ERR, "Failed to add vlan");
5300 i40e_pf_enable_irq0(hw);
5305 for (i = 0; i < conf_vsis; i++)
5306 if (pf->vmdq[i].vsi == NULL)
5309 i40e_vsi_release(pf->vmdq[i].vsi);
5313 i40e_pf_enable_irq0(hw);
5318 i40e_stat_update_32(struct i40e_hw *hw,
5326 new_data = (uint64_t)I40E_READ_REG(hw, reg);
5330 if (new_data >= *offset)
5331 *stat = (uint64_t)(new_data - *offset);
5333 *stat = (uint64_t)((new_data +
5334 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5338 i40e_stat_update_48(struct i40e_hw *hw,
5347 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5348 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5349 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5354 if (new_data >= *offset)
5355 *stat = new_data - *offset;
5357 *stat = (uint64_t)((new_data +
5358 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5360 *stat &= I40E_48_BIT_MASK;
5365 i40e_pf_disable_irq0(struct i40e_hw *hw)
5367 /* Disable all interrupt types */
5368 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5369 I40E_WRITE_FLUSH(hw);
5374 i40e_pf_enable_irq0(struct i40e_hw *hw)
5376 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5377 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5378 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5379 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5380 I40E_WRITE_FLUSH(hw);
5384 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5386 /* read pending request and disable first */
5387 i40e_pf_disable_irq0(hw);
5388 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5389 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5390 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5393 /* Link no queues with irq0 */
5394 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5395 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5399 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5401 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5402 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5405 uint32_t index, offset, val;
5410 * Try to find which VF trigger a reset, use absolute VF id to access
5411 * since the reg is global register.
5413 for (i = 0; i < pf->vf_num; i++) {
5414 abs_vf_id = hw->func_caps.vf_base_id + i;
5415 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5416 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5417 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5418 /* VFR event occured */
5419 if (val & (0x1 << offset)) {
5422 /* Clear the event first */
5423 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5425 PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5427 * Only notify a VF reset event occured,
5428 * don't trigger another SW reset
5430 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5431 if (ret != I40E_SUCCESS)
5432 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5438 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5440 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5441 struct i40e_arq_event_info info;
5442 uint16_t pending, opcode;
5445 info.buf_len = I40E_AQ_BUF_SZ;
5446 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5447 if (!info.msg_buf) {
5448 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5454 ret = i40e_clean_arq_element(hw, &info, &pending);
5456 if (ret != I40E_SUCCESS) {
5457 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5458 "aq_err: %u", hw->aq.asq_last_status);
5461 opcode = rte_le_to_cpu_16(info.desc.opcode);
5464 case i40e_aqc_opc_send_msg_to_pf:
5465 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5466 i40e_pf_host_handle_vf_msg(dev,
5467 rte_le_to_cpu_16(info.desc.retval),
5468 rte_le_to_cpu_32(info.desc.cookie_high),
5469 rte_le_to_cpu_32(info.desc.cookie_low),
5474 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5479 rte_free(info.msg_buf);
5483 * Interrupt handler is registered as the alarm callback for handling LSC
5484 * interrupt in a definite of time, in order to wait the NIC into a stable
5485 * state. Currently it waits 1 sec in i40e for the link up interrupt, and
5486 * no need for link down interrupt.
5489 i40e_dev_interrupt_delayed_handler(void *param)
5491 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5492 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5495 /* read interrupt causes again */
5496 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5498 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5499 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5500 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
5501 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5502 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
5503 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5504 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
5505 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5506 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
5507 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5508 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
5510 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5511 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
5512 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5513 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
5514 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5516 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5517 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
5518 i40e_dev_handle_vfr_event(dev);
5520 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5521 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
5522 i40e_dev_handle_aq_msg(dev);
5525 /* handle the link up interrupt in an alarm callback */
5526 i40e_dev_link_update(dev, 0);
5527 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
5529 i40e_pf_enable_irq0(hw);
5530 rte_intr_enable(&(dev->pci_dev->intr_handle));
5534 * Interrupt handler triggered by NIC for handling
5535 * specific interrupt.
5538 * Pointer to interrupt handle.
5540 * The address of parameter (struct rte_eth_dev *) regsitered before.
5546 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
5549 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5550 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5553 /* Disable interrupt */
5554 i40e_pf_disable_irq0(hw);
5556 /* read out interrupt causes */
5557 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5559 /* No interrupt event indicated */
5560 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5561 PMD_DRV_LOG(INFO, "No interrupt event");
5564 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5565 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5566 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5567 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5568 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5569 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5570 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5571 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5572 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5573 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5574 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5575 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5576 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5577 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5578 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5579 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5581 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5582 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5583 i40e_dev_handle_vfr_event(dev);
5585 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5586 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5587 i40e_dev_handle_aq_msg(dev);
5590 /* Link Status Change interrupt */
5591 if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
5592 #define I40E_US_PER_SECOND 1000000
5593 struct rte_eth_link link;
5595 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
5596 memset(&link, 0, sizeof(link));
5597 rte_i40e_dev_atomic_read_link_status(dev, &link);
5598 i40e_dev_link_update(dev, 0);
5601 * For link up interrupt, it needs to wait 1 second to let the
5602 * hardware be a stable state. Otherwise several consecutive
5603 * interrupts can be observed.
5604 * For link down interrupt, no need to wait.
5606 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
5607 i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
5610 _rte_eth_dev_callback_process(dev,
5611 RTE_ETH_EVENT_INTR_LSC, NULL);
5615 /* Enable interrupt */
5616 i40e_pf_enable_irq0(hw);
5617 rte_intr_enable(&(dev->pci_dev->intr_handle));
5621 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5622 struct i40e_macvlan_filter *filter,
5625 int ele_num, ele_buff_size;
5626 int num, actual_num, i;
5628 int ret = I40E_SUCCESS;
5629 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5630 struct i40e_aqc_add_macvlan_element_data *req_list;
5632 if (filter == NULL || total == 0)
5633 return I40E_ERR_PARAM;
5634 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5635 ele_buff_size = hw->aq.asq_buf_size;
5637 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5638 if (req_list == NULL) {
5639 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5640 return I40E_ERR_NO_MEMORY;
5645 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5646 memset(req_list, 0, ele_buff_size);
5648 for (i = 0; i < actual_num; i++) {
5649 (void)rte_memcpy(req_list[i].mac_addr,
5650 &filter[num + i].macaddr, ETH_ADDR_LEN);
5651 req_list[i].vlan_tag =
5652 rte_cpu_to_le_16(filter[num + i].vlan_id);
5654 switch (filter[num + i].filter_type) {
5655 case RTE_MAC_PERFECT_MATCH:
5656 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5657 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5659 case RTE_MACVLAN_PERFECT_MATCH:
5660 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5662 case RTE_MAC_HASH_MATCH:
5663 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5664 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5666 case RTE_MACVLAN_HASH_MATCH:
5667 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5670 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5671 ret = I40E_ERR_PARAM;
5675 req_list[i].queue_number = 0;
5677 req_list[i].flags = rte_cpu_to_le_16(flags);
5680 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5682 if (ret != I40E_SUCCESS) {
5683 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5687 } while (num < total);
5695 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5696 struct i40e_macvlan_filter *filter,
5699 int ele_num, ele_buff_size;
5700 int num, actual_num, i;
5702 int ret = I40E_SUCCESS;
5703 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5704 struct i40e_aqc_remove_macvlan_element_data *req_list;
5706 if (filter == NULL || total == 0)
5707 return I40E_ERR_PARAM;
5709 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5710 ele_buff_size = hw->aq.asq_buf_size;
5712 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5713 if (req_list == NULL) {
5714 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5715 return I40E_ERR_NO_MEMORY;
5720 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5721 memset(req_list, 0, ele_buff_size);
5723 for (i = 0; i < actual_num; i++) {
5724 (void)rte_memcpy(req_list[i].mac_addr,
5725 &filter[num + i].macaddr, ETH_ADDR_LEN);
5726 req_list[i].vlan_tag =
5727 rte_cpu_to_le_16(filter[num + i].vlan_id);
5729 switch (filter[num + i].filter_type) {
5730 case RTE_MAC_PERFECT_MATCH:
5731 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5732 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5734 case RTE_MACVLAN_PERFECT_MATCH:
5735 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5737 case RTE_MAC_HASH_MATCH:
5738 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5739 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5741 case RTE_MACVLAN_HASH_MATCH:
5742 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5745 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5746 ret = I40E_ERR_PARAM;
5749 req_list[i].flags = rte_cpu_to_le_16(flags);
5752 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5754 if (ret != I40E_SUCCESS) {
5755 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5759 } while (num < total);
5766 /* Find out specific MAC filter */
5767 static struct i40e_mac_filter *
5768 i40e_find_mac_filter(struct i40e_vsi *vsi,
5769 struct ether_addr *macaddr)
5771 struct i40e_mac_filter *f;
5773 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5774 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5782 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5785 uint32_t vid_idx, vid_bit;
5787 if (vlan_id > ETH_VLAN_ID_MAX)
5790 vid_idx = I40E_VFTA_IDX(vlan_id);
5791 vid_bit = I40E_VFTA_BIT(vlan_id);
5793 if (vsi->vfta[vid_idx] & vid_bit)
5800 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5801 uint16_t vlan_id, bool on)
5803 uint32_t vid_idx, vid_bit;
5805 if (vlan_id > ETH_VLAN_ID_MAX)
5808 vid_idx = I40E_VFTA_IDX(vlan_id);
5809 vid_bit = I40E_VFTA_BIT(vlan_id);
5812 vsi->vfta[vid_idx] |= vid_bit;
5814 vsi->vfta[vid_idx] &= ~vid_bit;
5818 * Find all vlan options for specific mac addr,
5819 * return with actual vlan found.
5822 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5823 struct i40e_macvlan_filter *mv_f,
5824 int num, struct ether_addr *addr)
5830 * Not to use i40e_find_vlan_filter to decrease the loop time,
5831 * although the code looks complex.
5833 if (num < vsi->vlan_num)
5834 return I40E_ERR_PARAM;
5837 for (j = 0; j < I40E_VFTA_SIZE; j++) {
5839 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5840 if (vsi->vfta[j] & (1 << k)) {
5842 PMD_DRV_LOG(ERR, "vlan number "
5844 return I40E_ERR_PARAM;
5846 (void)rte_memcpy(&mv_f[i].macaddr,
5847 addr, ETH_ADDR_LEN);
5849 j * I40E_UINT32_BIT_SIZE + k;
5855 return I40E_SUCCESS;
5859 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5860 struct i40e_macvlan_filter *mv_f,
5865 struct i40e_mac_filter *f;
5867 if (num < vsi->mac_num)
5868 return I40E_ERR_PARAM;
5870 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5872 PMD_DRV_LOG(ERR, "buffer number not match");
5873 return I40E_ERR_PARAM;
5875 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5877 mv_f[i].vlan_id = vlan;
5878 mv_f[i].filter_type = f->mac_info.filter_type;
5882 return I40E_SUCCESS;
5886 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5889 struct i40e_mac_filter *f;
5890 struct i40e_macvlan_filter *mv_f;
5891 int ret = I40E_SUCCESS;
5893 if (vsi == NULL || vsi->mac_num == 0)
5894 return I40E_ERR_PARAM;
5896 /* Case that no vlan is set */
5897 if (vsi->vlan_num == 0)
5900 num = vsi->mac_num * vsi->vlan_num;
5902 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5904 PMD_DRV_LOG(ERR, "failed to allocate memory");
5905 return I40E_ERR_NO_MEMORY;
5909 if (vsi->vlan_num == 0) {
5910 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5911 (void)rte_memcpy(&mv_f[i].macaddr,
5912 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5913 mv_f[i].vlan_id = 0;
5917 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5918 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5919 vsi->vlan_num, &f->mac_info.mac_addr);
5920 if (ret != I40E_SUCCESS)
5926 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5934 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5936 struct i40e_macvlan_filter *mv_f;
5938 int ret = I40E_SUCCESS;
5940 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5941 return I40E_ERR_PARAM;
5943 /* If it's already set, just return */
5944 if (i40e_find_vlan_filter(vsi,vlan))
5945 return I40E_SUCCESS;
5947 mac_num = vsi->mac_num;
5950 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5951 return I40E_ERR_PARAM;
5954 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5957 PMD_DRV_LOG(ERR, "failed to allocate memory");
5958 return I40E_ERR_NO_MEMORY;
5961 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5963 if (ret != I40E_SUCCESS)
5966 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5968 if (ret != I40E_SUCCESS)
5971 i40e_set_vlan_filter(vsi, vlan, 1);
5981 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5983 struct i40e_macvlan_filter *mv_f;
5985 int ret = I40E_SUCCESS;
5988 * Vlan 0 is the generic filter for untagged packets
5989 * and can't be removed.
5991 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5992 return I40E_ERR_PARAM;
5994 /* If can't find it, just return */
5995 if (!i40e_find_vlan_filter(vsi, vlan))
5996 return I40E_ERR_PARAM;
5998 mac_num = vsi->mac_num;
6001 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6002 return I40E_ERR_PARAM;
6005 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6008 PMD_DRV_LOG(ERR, "failed to allocate memory");
6009 return I40E_ERR_NO_MEMORY;
6012 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6014 if (ret != I40E_SUCCESS)
6017 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6019 if (ret != I40E_SUCCESS)
6022 /* This is last vlan to remove, replace all mac filter with vlan 0 */
6023 if (vsi->vlan_num == 1) {
6024 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6025 if (ret != I40E_SUCCESS)
6028 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6029 if (ret != I40E_SUCCESS)
6033 i40e_set_vlan_filter(vsi, vlan, 0);
6043 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6045 struct i40e_mac_filter *f;
6046 struct i40e_macvlan_filter *mv_f;
6047 int i, vlan_num = 0;
6048 int ret = I40E_SUCCESS;
6050 /* If it's add and we've config it, return */
6051 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6053 return I40E_SUCCESS;
6054 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6055 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6058 * If vlan_num is 0, that's the first time to add mac,
6059 * set mask for vlan_id 0.
6061 if (vsi->vlan_num == 0) {
6062 i40e_set_vlan_filter(vsi, 0, 1);
6065 vlan_num = vsi->vlan_num;
6066 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6067 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6070 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6072 PMD_DRV_LOG(ERR, "failed to allocate memory");
6073 return I40E_ERR_NO_MEMORY;
6076 for (i = 0; i < vlan_num; i++) {
6077 mv_f[i].filter_type = mac_filter->filter_type;
6078 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6082 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6083 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6084 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6085 &mac_filter->mac_addr);
6086 if (ret != I40E_SUCCESS)
6090 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6091 if (ret != I40E_SUCCESS)
6094 /* Add the mac addr into mac list */
6095 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6097 PMD_DRV_LOG(ERR, "failed to allocate memory");
6098 ret = I40E_ERR_NO_MEMORY;
6101 (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6103 f->mac_info.filter_type = mac_filter->filter_type;
6104 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6115 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6117 struct i40e_mac_filter *f;
6118 struct i40e_macvlan_filter *mv_f;
6120 enum rte_mac_filter_type filter_type;
6121 int ret = I40E_SUCCESS;
6123 /* Can't find it, return an error */
6124 f = i40e_find_mac_filter(vsi, addr);
6126 return I40E_ERR_PARAM;
6128 vlan_num = vsi->vlan_num;
6129 filter_type = f->mac_info.filter_type;
6130 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6131 filter_type == RTE_MACVLAN_HASH_MATCH) {
6132 if (vlan_num == 0) {
6133 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
6134 return I40E_ERR_PARAM;
6136 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6137 filter_type == RTE_MAC_HASH_MATCH)
6140 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6142 PMD_DRV_LOG(ERR, "failed to allocate memory");
6143 return I40E_ERR_NO_MEMORY;
6146 for (i = 0; i < vlan_num; i++) {
6147 mv_f[i].filter_type = filter_type;
6148 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6151 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6152 filter_type == RTE_MACVLAN_HASH_MATCH) {
6153 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6154 if (ret != I40E_SUCCESS)
6158 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6159 if (ret != I40E_SUCCESS)
6162 /* Remove the mac addr into mac list */
6163 TAILQ_REMOVE(&vsi->mac_list, f, next);
6173 /* Configure hash enable flags for RSS */
6175 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6182 if (flags & ETH_RSS_FRAG_IPV4)
6183 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6184 if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6185 if (type == I40E_MAC_X722) {
6186 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6187 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6189 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6191 if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6192 if (type == I40E_MAC_X722) {
6193 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6194 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6195 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6197 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6199 if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6200 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6201 if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6202 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6203 if (flags & ETH_RSS_FRAG_IPV6)
6204 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6205 if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6206 if (type == I40E_MAC_X722) {
6207 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6208 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6210 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6212 if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6213 if (type == I40E_MAC_X722) {
6214 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6215 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6216 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6218 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6220 if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6221 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6222 if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6223 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6224 if (flags & ETH_RSS_L2_PAYLOAD)
6225 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6230 /* Parse the hash enable flags */
6232 i40e_parse_hena(uint64_t flags)
6234 uint64_t rss_hf = 0;
6238 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6239 rss_hf |= ETH_RSS_FRAG_IPV4;
6240 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6241 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6243 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6244 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6246 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6247 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6249 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6250 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6251 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6252 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6254 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6255 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6256 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6257 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6258 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6259 rss_hf |= ETH_RSS_FRAG_IPV6;
6260 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6261 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6263 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6264 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6266 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6267 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6269 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6270 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6271 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6272 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6274 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6275 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6276 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6277 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6278 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6279 rss_hf |= ETH_RSS_L2_PAYLOAD;
6286 i40e_pf_disable_rss(struct i40e_pf *pf)
6288 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6291 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6292 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6293 if (hw->mac.type == I40E_MAC_X722)
6294 hena &= ~I40E_RSS_HENA_ALL_X722;
6296 hena &= ~I40E_RSS_HENA_ALL;
6297 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6298 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6299 I40E_WRITE_FLUSH(hw);
6303 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6305 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6306 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6309 if (!key || key_len == 0) {
6310 PMD_DRV_LOG(DEBUG, "No key to be configured");
6312 } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6314 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6318 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6319 struct i40e_aqc_get_set_rss_key_data *key_dw =
6320 (struct i40e_aqc_get_set_rss_key_data *)key;
6322 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6324 PMD_INIT_LOG(ERR, "Failed to configure RSS key "
6327 uint32_t *hash_key = (uint32_t *)key;
6330 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6331 i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6332 I40E_WRITE_FLUSH(hw);
6339 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6341 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6342 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6345 if (!key || !key_len)
6348 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6349 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6350 (struct i40e_aqc_get_set_rss_key_data *)key);
6352 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6356 uint32_t *key_dw = (uint32_t *)key;
6359 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6360 key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6362 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6368 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6370 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6375 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6376 rss_conf->rss_key_len);
6380 rss_hf = rss_conf->rss_hf;
6381 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6382 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6383 if (hw->mac.type == I40E_MAC_X722)
6384 hena &= ~I40E_RSS_HENA_ALL_X722;
6386 hena &= ~I40E_RSS_HENA_ALL;
6387 hena |= i40e_config_hena(rss_hf, hw->mac.type);
6388 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6389 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6390 I40E_WRITE_FLUSH(hw);
6396 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6397 struct rte_eth_rss_conf *rss_conf)
6399 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6400 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6401 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6404 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6405 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6406 if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6407 ? I40E_RSS_HENA_ALL_X722
6408 : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6409 if (rss_hf != 0) /* Enable RSS */
6411 return 0; /* Nothing to do */
6414 if (rss_hf == 0) /* Disable RSS */
6417 return i40e_hw_rss_hash_set(pf, rss_conf);
6421 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6422 struct rte_eth_rss_conf *rss_conf)
6424 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6425 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6428 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6429 &rss_conf->rss_key_len);
6431 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6432 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6433 rss_conf->rss_hf = i40e_parse_hena(hena);
6439 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6441 switch (filter_type) {
6442 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6443 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6445 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6446 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6448 case RTE_TUNNEL_FILTER_IMAC_TENID:
6449 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6451 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6452 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6454 case ETH_TUNNEL_FILTER_IMAC:
6455 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6457 case ETH_TUNNEL_FILTER_OIP:
6458 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6460 case ETH_TUNNEL_FILTER_IIP:
6461 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6464 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6472 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6473 struct rte_eth_tunnel_filter_conf *tunnel_filter,
6478 uint8_t i, tun_type = 0;
6479 /* internal varialbe to convert ipv6 byte order */
6480 uint32_t convert_ipv6[4];
6482 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6483 struct i40e_vsi *vsi = pf->main_vsi;
6484 struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter;
6485 struct i40e_aqc_add_remove_cloud_filters_element_data *pfilter;
6487 cld_filter = rte_zmalloc("tunnel_filter",
6488 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6491 if (NULL == cld_filter) {
6492 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6495 pfilter = cld_filter;
6497 ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6498 ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6500 pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6501 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6502 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6503 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6504 rte_memcpy(&pfilter->ipaddr.v4.data,
6505 &rte_cpu_to_le_32(ipv4_addr),
6506 sizeof(pfilter->ipaddr.v4.data));
6508 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6509 for (i = 0; i < 4; i++) {
6511 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6513 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6514 sizeof(pfilter->ipaddr.v6.data));
6517 /* check tunneled type */
6518 switch (tunnel_filter->tunnel_type) {
6519 case RTE_TUNNEL_TYPE_VXLAN:
6520 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6522 case RTE_TUNNEL_TYPE_NVGRE:
6523 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6525 case RTE_TUNNEL_TYPE_IP_IN_GRE:
6526 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6529 /* Other tunnel types is not supported. */
6530 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6531 rte_free(cld_filter);
6535 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6538 rte_free(cld_filter);
6542 pfilter->flags |= rte_cpu_to_le_16(
6543 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6544 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6545 pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6546 pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6549 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6551 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6554 rte_free(cld_filter);
6559 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6563 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6564 if (pf->vxlan_ports[i] == port)
6572 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6576 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6578 idx = i40e_get_vxlan_port_idx(pf, port);
6580 /* Check if port already exists */
6582 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6586 /* Now check if there is space to add the new port */
6587 idx = i40e_get_vxlan_port_idx(pf, 0);
6589 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6590 "not adding port %d", port);
6594 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6597 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6601 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6604 /* New port: add it and mark its index in the bitmap */
6605 pf->vxlan_ports[idx] = port;
6606 pf->vxlan_bitmap |= (1 << idx);
6608 if (!(pf->flags & I40E_FLAG_VXLAN))
6609 pf->flags |= I40E_FLAG_VXLAN;
6615 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6618 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6620 if (!(pf->flags & I40E_FLAG_VXLAN)) {
6621 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6625 idx = i40e_get_vxlan_port_idx(pf, port);
6628 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6632 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6633 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6637 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6640 pf->vxlan_ports[idx] = 0;
6641 pf->vxlan_bitmap &= ~(1 << idx);
6643 if (!pf->vxlan_bitmap)
6644 pf->flags &= ~I40E_FLAG_VXLAN;
6649 /* Add UDP tunneling port */
6651 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6652 struct rte_eth_udp_tunnel *udp_tunnel)
6655 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6657 if (udp_tunnel == NULL)
6660 switch (udp_tunnel->prot_type) {
6661 case RTE_TUNNEL_TYPE_VXLAN:
6662 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6665 case RTE_TUNNEL_TYPE_GENEVE:
6666 case RTE_TUNNEL_TYPE_TEREDO:
6667 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6672 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6680 /* Remove UDP tunneling port */
6682 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6683 struct rte_eth_udp_tunnel *udp_tunnel)
6686 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6688 if (udp_tunnel == NULL)
6691 switch (udp_tunnel->prot_type) {
6692 case RTE_TUNNEL_TYPE_VXLAN:
6693 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6695 case RTE_TUNNEL_TYPE_GENEVE:
6696 case RTE_TUNNEL_TYPE_TEREDO:
6697 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6701 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6709 /* Calculate the maximum number of contiguous PF queues that are configured */
6711 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6713 struct rte_eth_dev_data *data = pf->dev_data;
6715 struct i40e_rx_queue *rxq;
6718 for (i = 0; i < pf->lan_nb_qps; i++) {
6719 rxq = data->rx_queues[i];
6720 if (rxq && rxq->q_set)
6731 i40e_pf_config_rss(struct i40e_pf *pf)
6733 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6734 struct rte_eth_rss_conf rss_conf;
6735 uint32_t i, lut = 0;
6739 * If both VMDQ and RSS enabled, not all of PF queues are configured.
6740 * It's necessary to calulate the actual PF queues that are configured.
6742 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6743 num = i40e_pf_calc_configured_queues_num(pf);
6745 num = pf->dev_data->nb_rx_queues;
6747 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6748 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6752 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6756 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6759 lut = (lut << 8) | (j & ((0x1 <<
6760 hw->func_caps.rss_table_entry_width) - 1));
6762 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6765 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6766 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6767 i40e_pf_disable_rss(pf);
6770 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6771 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6772 /* Random default keys */
6773 static uint32_t rss_key_default[] = {0x6b793944,
6774 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6775 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6776 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6778 rss_conf.rss_key = (uint8_t *)rss_key_default;
6779 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6783 return i40e_hw_rss_hash_set(pf, &rss_conf);
6787 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6788 struct rte_eth_tunnel_filter_conf *filter)
6790 if (pf == NULL || filter == NULL) {
6791 PMD_DRV_LOG(ERR, "Invalid parameter");
6795 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6796 PMD_DRV_LOG(ERR, "Invalid queue ID");
6800 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6801 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6805 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6806 (is_zero_ether_addr(&filter->outer_mac))) {
6807 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6811 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6812 (is_zero_ether_addr(&filter->inner_mac))) {
6813 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6820 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6821 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
6823 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6828 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6829 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6832 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6833 } else if (len == 4) {
6834 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6836 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6841 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6848 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6849 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6855 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6862 switch (cfg->cfg_type) {
6863 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6864 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6867 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6875 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6876 enum rte_filter_op filter_op,
6879 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6880 int ret = I40E_ERR_PARAM;
6882 switch (filter_op) {
6883 case RTE_ETH_FILTER_SET:
6884 ret = i40e_dev_global_config_set(hw,
6885 (struct rte_eth_global_cfg *)arg);
6888 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6896 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6897 enum rte_filter_op filter_op,
6900 struct rte_eth_tunnel_filter_conf *filter;
6901 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6902 int ret = I40E_SUCCESS;
6904 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6906 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6907 return I40E_ERR_PARAM;
6909 switch (filter_op) {
6910 case RTE_ETH_FILTER_NOP:
6911 if (!(pf->flags & I40E_FLAG_VXLAN))
6912 ret = I40E_NOT_SUPPORTED;
6914 case RTE_ETH_FILTER_ADD:
6915 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6917 case RTE_ETH_FILTER_DELETE:
6918 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6921 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6922 ret = I40E_ERR_PARAM;
6930 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6933 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6936 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6937 ret = i40e_pf_config_rss(pf);
6939 i40e_pf_disable_rss(pf);
6944 /* Get the symmetric hash enable configurations per port */
6946 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6948 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6950 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6953 /* Set the symmetric hash enable configurations per port */
6955 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6957 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6960 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6961 PMD_DRV_LOG(INFO, "Symmetric hash has already "
6965 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6967 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6968 PMD_DRV_LOG(INFO, "Symmetric hash has already "
6972 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6974 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
6975 I40E_WRITE_FLUSH(hw);
6979 * Get global configurations of hash function type and symmetric hash enable
6980 * per flow type (pctype). Note that global configuration means it affects all
6981 * the ports on the same NIC.
6984 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6985 struct rte_eth_hash_global_conf *g_cfg)
6987 uint32_t reg, mask = I40E_FLOW_TYPES;
6989 enum i40e_filter_pctype pctype;
6991 memset(g_cfg, 0, sizeof(*g_cfg));
6992 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6993 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6994 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6996 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6997 PMD_DRV_LOG(DEBUG, "Hash function is %s",
6998 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7000 for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7001 if (!(mask & (1UL << i)))
7003 mask &= ~(1UL << i);
7004 /* Bit set indicats the coresponding flow type is supported */
7005 g_cfg->valid_bit_mask[0] |= (1UL << i);
7006 /* if flowtype is invalid, continue */
7007 if (!I40E_VALID_FLOW(i))
7009 pctype = i40e_flowtype_to_pctype(i);
7010 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7011 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7012 g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7019 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7022 uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7024 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7025 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7026 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7027 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7033 * As i40e supports less than 32 flow types, only first 32 bits need to
7036 mask0 = g_cfg->valid_bit_mask[0];
7037 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7039 /* Check if any unsupported flow type configured */
7040 if ((mask0 | i40e_mask) ^ i40e_mask)
7043 if (g_cfg->valid_bit_mask[i])
7051 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7057 * Set global configurations of hash function type and symmetric hash enable
7058 * per flow type (pctype). Note any modifying global configuration will affect
7059 * all the ports on the same NIC.
7062 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7063 struct rte_eth_hash_global_conf *g_cfg)
7068 uint32_t mask0 = g_cfg->valid_bit_mask[0];
7069 enum i40e_filter_pctype pctype;
7071 /* Check the input parameters */
7072 ret = i40e_hash_global_config_check(g_cfg);
7076 for (i = 0; mask0 && i < UINT32_BIT; i++) {
7077 if (!(mask0 & (1UL << i)))
7079 mask0 &= ~(1UL << i);
7080 /* if flowtype is invalid, continue */
7081 if (!I40E_VALID_FLOW(i))
7083 pctype = i40e_flowtype_to_pctype(i);
7084 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7085 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7086 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7089 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7090 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7092 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7093 PMD_DRV_LOG(DEBUG, "Hash function already set to "
7097 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7098 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7100 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7101 PMD_DRV_LOG(DEBUG, "Hash function already set to "
7105 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7107 /* Use the default, and keep it as it is */
7110 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7113 I40E_WRITE_FLUSH(hw);
7119 * Valid input sets for hash and flow director filters per PCTYPE
7122 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7123 enum rte_filter_type filter)
7127 static const uint64_t valid_hash_inset_table[] = {
7128 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7129 I40E_INSET_DMAC | I40E_INSET_SMAC |
7130 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7131 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7132 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7133 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7134 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7135 I40E_INSET_FLEX_PAYLOAD,
7136 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7137 I40E_INSET_DMAC | I40E_INSET_SMAC |
7138 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7139 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7140 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7141 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7142 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7143 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7144 I40E_INSET_FLEX_PAYLOAD,
7146 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7147 I40E_INSET_DMAC | I40E_INSET_SMAC |
7148 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7149 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7150 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7151 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7152 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7153 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7154 I40E_INSET_FLEX_PAYLOAD,
7155 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7156 I40E_INSET_DMAC | I40E_INSET_SMAC |
7157 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7158 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7159 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7160 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7161 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7162 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7163 I40E_INSET_FLEX_PAYLOAD,
7165 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7166 I40E_INSET_DMAC | I40E_INSET_SMAC |
7167 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7168 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7169 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7170 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7171 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7172 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7173 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7175 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7176 I40E_INSET_DMAC | I40E_INSET_SMAC |
7177 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7178 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7179 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7180 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7181 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7182 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7183 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7185 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7186 I40E_INSET_DMAC | I40E_INSET_SMAC |
7187 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7188 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7189 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7190 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7191 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7192 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7193 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7194 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7195 I40E_INSET_DMAC | I40E_INSET_SMAC |
7196 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7197 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7198 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7199 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7200 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7201 I40E_INSET_FLEX_PAYLOAD,
7202 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7203 I40E_INSET_DMAC | I40E_INSET_SMAC |
7204 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7205 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7206 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7207 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7208 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7209 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7210 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7211 I40E_INSET_DMAC | I40E_INSET_SMAC |
7212 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7213 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7214 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7215 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7216 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7217 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7219 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7220 I40E_INSET_DMAC | I40E_INSET_SMAC |
7221 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7222 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7223 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7224 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7225 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7226 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7227 I40E_INSET_FLEX_PAYLOAD,
7228 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7229 I40E_INSET_DMAC | I40E_INSET_SMAC |
7230 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7231 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7232 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7233 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7234 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7235 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7236 I40E_INSET_FLEX_PAYLOAD,
7238 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7239 I40E_INSET_DMAC | I40E_INSET_SMAC |
7240 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7241 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7242 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7243 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7244 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7245 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7246 I40E_INSET_FLEX_PAYLOAD,
7248 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7249 I40E_INSET_DMAC | I40E_INSET_SMAC |
7250 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7251 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7252 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7253 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7254 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7255 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7256 I40E_INSET_FLEX_PAYLOAD,
7258 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7259 I40E_INSET_DMAC | I40E_INSET_SMAC |
7260 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7261 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7262 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7263 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7264 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7265 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7266 I40E_INSET_FLEX_PAYLOAD,
7267 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7268 I40E_INSET_DMAC | I40E_INSET_SMAC |
7269 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7270 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7271 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7272 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7273 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7274 I40E_INSET_FLEX_PAYLOAD,
7275 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7276 I40E_INSET_DMAC | I40E_INSET_SMAC |
7277 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7278 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7279 I40E_INSET_FLEX_PAYLOAD,
7283 * Flow director supports only fields defined in
7284 * union rte_eth_fdir_flow.
7286 static const uint64_t valid_fdir_inset_table[] = {
7287 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7288 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7289 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7290 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7291 I40E_INSET_IPV4_TTL,
7292 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7293 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7294 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7295 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7296 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7298 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7299 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7300 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7301 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7302 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7303 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7304 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7305 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7306 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7307 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7309 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7310 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7311 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7312 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7313 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7315 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7316 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7317 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7318 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7319 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7321 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7322 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7323 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7324 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7325 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7327 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7328 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7329 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7330 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7331 I40E_INSET_IPV4_TTL,
7332 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7333 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7334 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7335 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7336 I40E_INSET_IPV6_HOP_LIMIT,
7337 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7338 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7339 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7340 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7341 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7343 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7344 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7345 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7346 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7347 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7348 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7349 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7350 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7351 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7352 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7354 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7355 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7356 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7357 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7358 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7360 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7361 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7362 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7363 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7364 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7366 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7367 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7368 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7369 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7370 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7372 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7373 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7374 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7375 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7376 I40E_INSET_IPV6_HOP_LIMIT,
7377 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7378 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7379 I40E_INSET_LAST_ETHER_TYPE,
7382 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7384 if (filter == RTE_ETH_FILTER_HASH)
7385 valid = valid_hash_inset_table[pctype];
7387 valid = valid_fdir_inset_table[pctype];
7393 * Validate if the input set is allowed for a specific PCTYPE
7396 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7397 enum rte_filter_type filter, uint64_t inset)
7401 valid = i40e_get_valid_input_set(pctype, filter);
7402 if (inset & (~valid))
7408 /* default input set fields combination per pctype */
7410 i40e_get_default_input_set(uint16_t pctype)
7412 static const uint64_t default_inset_table[] = {
7413 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7414 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7415 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7416 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7417 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7419 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7420 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7421 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7422 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7423 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7424 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7426 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7427 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7428 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7430 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7431 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7432 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7434 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7435 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7436 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7438 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7439 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7440 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7441 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7442 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7443 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7444 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7446 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7447 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7448 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7449 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7450 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7451 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7453 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7454 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7455 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7457 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7458 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7459 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7461 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7462 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7463 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7465 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7466 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7467 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7468 I40E_INSET_LAST_ETHER_TYPE,
7471 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7474 return default_inset_table[pctype];
7478 * Parse the input set from index to logical bit masks
7481 i40e_parse_input_set(uint64_t *inset,
7482 enum i40e_filter_pctype pctype,
7483 enum rte_eth_input_set_field *field,
7489 static const struct {
7490 enum rte_eth_input_set_field field;
7492 } inset_convert_table[] = {
7493 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7494 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7495 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7496 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7497 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7498 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7499 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7500 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7501 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7502 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7503 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7504 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7505 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7506 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7507 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7508 I40E_INSET_IPV6_NEXT_HDR},
7509 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7510 I40E_INSET_IPV6_HOP_LIMIT},
7511 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7512 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7513 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7514 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7515 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7516 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7517 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7518 I40E_INSET_SCTP_VT},
7519 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7520 I40E_INSET_TUNNEL_DMAC},
7521 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7522 I40E_INSET_VLAN_TUNNEL},
7523 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7524 I40E_INSET_TUNNEL_ID},
7525 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7526 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7527 I40E_INSET_FLEX_PAYLOAD_W1},
7528 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7529 I40E_INSET_FLEX_PAYLOAD_W2},
7530 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7531 I40E_INSET_FLEX_PAYLOAD_W3},
7532 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7533 I40E_INSET_FLEX_PAYLOAD_W4},
7534 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7535 I40E_INSET_FLEX_PAYLOAD_W5},
7536 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7537 I40E_INSET_FLEX_PAYLOAD_W6},
7538 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7539 I40E_INSET_FLEX_PAYLOAD_W7},
7540 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7541 I40E_INSET_FLEX_PAYLOAD_W8},
7544 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7547 /* Only one item allowed for default or all */
7549 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7550 *inset = i40e_get_default_input_set(pctype);
7552 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7553 *inset = I40E_INSET_NONE;
7558 for (i = 0, *inset = 0; i < size; i++) {
7559 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7560 if (field[i] == inset_convert_table[j].field) {
7561 *inset |= inset_convert_table[j].inset;
7566 /* It contains unsupported input set, return immediately */
7567 if (j == RTE_DIM(inset_convert_table))
7575 * Translate the input set from bit masks to register aware bit masks
7579 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
7589 static const struct inset_map inset_map_common[] = {
7590 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7591 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7592 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7593 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7594 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7595 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7596 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7597 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7598 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7599 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7600 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7601 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7602 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7603 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7604 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7605 {I40E_INSET_TUNNEL_DMAC,
7606 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7607 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7608 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7609 {I40E_INSET_TUNNEL_SRC_PORT,
7610 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7611 {I40E_INSET_TUNNEL_DST_PORT,
7612 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7613 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7614 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7615 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7616 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7617 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7618 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7619 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7620 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7621 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7624 /* some different registers map in x722*/
7625 static const struct inset_map inset_map_diff_x722[] = {
7626 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
7627 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
7628 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
7629 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
7632 static const struct inset_map inset_map_diff_not_x722[] = {
7633 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7634 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7635 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7636 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7642 /* Translate input set to register aware inset */
7643 if (type == I40E_MAC_X722) {
7644 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
7645 if (input & inset_map_diff_x722[i].inset)
7646 val |= inset_map_diff_x722[i].inset_reg;
7649 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
7650 if (input & inset_map_diff_not_x722[i].inset)
7651 val |= inset_map_diff_not_x722[i].inset_reg;
7655 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
7656 if (input & inset_map_common[i].inset)
7657 val |= inset_map_common[i].inset_reg;
7664 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7667 uint64_t inset_need_mask = inset;
7669 static const struct {
7672 } inset_mask_map[] = {
7673 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7674 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7675 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7676 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7677 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7678 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7679 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7680 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7683 if (!inset || !mask || !nb_elem)
7686 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7687 /* Clear the inset bit, if no MASK is required,
7688 * for example proto + ttl
7690 if ((inset & inset_mask_map[i].inset) ==
7691 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
7692 inset_need_mask &= ~inset_mask_map[i].inset;
7693 if (!inset_need_mask)
7696 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7697 if ((inset_need_mask & inset_mask_map[i].inset) ==
7698 inset_mask_map[i].inset) {
7699 if (idx >= nb_elem) {
7700 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
7703 mask[idx] = inset_mask_map[i].mask;
7712 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7714 uint32_t reg = i40e_read_rx_ctl(hw, addr);
7716 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7718 i40e_write_rx_ctl(hw, addr, val);
7719 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7720 (uint32_t)i40e_read_rx_ctl(hw, addr));
7724 i40e_filter_input_set_init(struct i40e_pf *pf)
7726 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7727 enum i40e_filter_pctype pctype;
7728 uint64_t input_set, inset_reg;
7729 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7732 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
7733 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
7734 if (hw->mac.type == I40E_MAC_X722) {
7735 if (!I40E_VALID_PCTYPE_X722(pctype))
7738 if (!I40E_VALID_PCTYPE(pctype))
7742 input_set = i40e_get_default_input_set(pctype);
7744 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7745 I40E_INSET_MASK_NUM_REG);
7748 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
7751 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7752 (uint32_t)(inset_reg & UINT32_MAX));
7753 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7754 (uint32_t)((inset_reg >>
7755 I40E_32_BIT_WIDTH) & UINT32_MAX));
7756 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7757 (uint32_t)(inset_reg & UINT32_MAX));
7758 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7759 (uint32_t)((inset_reg >>
7760 I40E_32_BIT_WIDTH) & UINT32_MAX));
7762 for (i = 0; i < num; i++) {
7763 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7765 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7768 /*clear unused mask registers of the pctype */
7769 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
7770 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7772 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7775 I40E_WRITE_FLUSH(hw);
7777 /* store the default input set */
7778 pf->hash_input_set[pctype] = input_set;
7779 pf->fdir.input_set[pctype] = input_set;
7784 i40e_hash_filter_inset_select(struct i40e_hw *hw,
7785 struct rte_eth_input_set_conf *conf)
7787 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
7788 enum i40e_filter_pctype pctype;
7789 uint64_t input_set, inset_reg = 0;
7790 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7794 PMD_DRV_LOG(ERR, "Invalid pointer");
7797 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7798 conf->op != RTE_ETH_INPUT_SET_ADD) {
7799 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7803 if (!I40E_VALID_FLOW(conf->flow_type)) {
7804 PMD_DRV_LOG(ERR, "invalid flow_type input.");
7808 if (hw->mac.type == I40E_MAC_X722) {
7809 /* get translated pctype value in fd pctype register */
7810 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
7811 I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
7814 pctype = i40e_flowtype_to_pctype(conf->flow_type);
7816 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7819 PMD_DRV_LOG(ERR, "Failed to parse input set");
7822 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
7824 PMD_DRV_LOG(ERR, "Invalid input set");
7827 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
7828 /* get inset value in register */
7829 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
7830 inset_reg <<= I40E_32_BIT_WIDTH;
7831 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
7832 input_set |= pf->hash_input_set[pctype];
7834 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7835 I40E_INSET_MASK_NUM_REG);
7839 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
7841 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7842 (uint32_t)(inset_reg & UINT32_MAX));
7843 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7844 (uint32_t)((inset_reg >>
7845 I40E_32_BIT_WIDTH) & UINT32_MAX));
7847 for (i = 0; i < num; i++)
7848 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7850 /*clear unused mask registers of the pctype */
7851 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7852 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7854 I40E_WRITE_FLUSH(hw);
7856 pf->hash_input_set[pctype] = input_set;
7861 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
7862 struct rte_eth_input_set_conf *conf)
7864 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7865 enum i40e_filter_pctype pctype;
7866 uint64_t input_set, inset_reg = 0;
7867 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7871 PMD_DRV_LOG(ERR, "Invalid pointer");
7874 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7875 conf->op != RTE_ETH_INPUT_SET_ADD) {
7876 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7880 if (!I40E_VALID_FLOW(conf->flow_type)) {
7881 PMD_DRV_LOG(ERR, "invalid flow_type input.");
7885 pctype = i40e_flowtype_to_pctype(conf->flow_type);
7887 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7890 PMD_DRV_LOG(ERR, "Failed to parse input set");
7893 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
7895 PMD_DRV_LOG(ERR, "Invalid input set");
7899 /* get inset value in register */
7900 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
7901 inset_reg <<= I40E_32_BIT_WIDTH;
7902 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
7904 /* Can not change the inset reg for flex payload for fdir,
7905 * it is done by writing I40E_PRTQF_FD_FLXINSET
7906 * in i40e_set_flex_mask_on_pctype.
7908 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
7909 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
7911 input_set |= pf->fdir.input_set[pctype];
7912 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7913 I40E_INSET_MASK_NUM_REG);
7917 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
7919 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7920 (uint32_t)(inset_reg & UINT32_MAX));
7921 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7922 (uint32_t)((inset_reg >>
7923 I40E_32_BIT_WIDTH) & UINT32_MAX));
7925 for (i = 0; i < num; i++)
7926 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7928 /*clear unused mask registers of the pctype */
7929 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7930 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7932 I40E_WRITE_FLUSH(hw);
7934 pf->fdir.input_set[pctype] = input_set;
7939 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7944 PMD_DRV_LOG(ERR, "Invalid pointer");
7948 switch (info->info_type) {
7949 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7950 i40e_get_symmetric_hash_enable_per_port(hw,
7951 &(info->info.enable));
7953 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7954 ret = i40e_get_hash_filter_global_config(hw,
7955 &(info->info.global_conf));
7958 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7968 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7973 PMD_DRV_LOG(ERR, "Invalid pointer");
7977 switch (info->info_type) {
7978 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7979 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7981 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7982 ret = i40e_set_hash_filter_global_config(hw,
7983 &(info->info.global_conf));
7985 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7986 ret = i40e_hash_filter_inset_select(hw,
7987 &(info->info.input_set_conf));
7991 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8000 /* Operations for hash function */
8002 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8003 enum rte_filter_op filter_op,
8006 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8009 switch (filter_op) {
8010 case RTE_ETH_FILTER_NOP:
8012 case RTE_ETH_FILTER_GET:
8013 ret = i40e_hash_filter_get(hw,
8014 (struct rte_eth_hash_filter_info *)arg);
8016 case RTE_ETH_FILTER_SET:
8017 ret = i40e_hash_filter_set(hw,
8018 (struct rte_eth_hash_filter_info *)arg);
8021 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8031 * Configure ethertype filter, which can director packet by filtering
8032 * with mac address and ether_type or only ether_type
8035 i40e_ethertype_filter_set(struct i40e_pf *pf,
8036 struct rte_eth_ethertype_filter *filter,
8039 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8040 struct i40e_control_filter_stats stats;
8044 if (filter->queue >= pf->dev_data->nb_rx_queues) {
8045 PMD_DRV_LOG(ERR, "Invalid queue ID");
8048 if (filter->ether_type == ETHER_TYPE_IPv4 ||
8049 filter->ether_type == ETHER_TYPE_IPv6) {
8050 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
8051 " control packet filter.", filter->ether_type);
8054 if (filter->ether_type == ETHER_TYPE_VLAN)
8055 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
8058 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8059 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8060 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8061 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8062 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8064 memset(&stats, 0, sizeof(stats));
8065 ret = i40e_aq_add_rem_control_packet_filter(hw,
8066 filter->mac_addr.addr_bytes,
8067 filter->ether_type, flags,
8069 filter->queue, add, &stats, NULL);
8071 PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
8072 " mac_etype_used = %u, etype_used = %u,"
8073 " mac_etype_free = %u, etype_free = %u\n",
8074 ret, stats.mac_etype_used, stats.etype_used,
8075 stats.mac_etype_free, stats.etype_free);
8082 * Handle operations for ethertype filter.
8085 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8086 enum rte_filter_op filter_op,
8089 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8092 if (filter_op == RTE_ETH_FILTER_NOP)
8096 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8101 switch (filter_op) {
8102 case RTE_ETH_FILTER_ADD:
8103 ret = i40e_ethertype_filter_set(pf,
8104 (struct rte_eth_ethertype_filter *)arg,
8107 case RTE_ETH_FILTER_DELETE:
8108 ret = i40e_ethertype_filter_set(pf,
8109 (struct rte_eth_ethertype_filter *)arg,
8113 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
8121 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8122 enum rte_filter_type filter_type,
8123 enum rte_filter_op filter_op,
8131 switch (filter_type) {
8132 case RTE_ETH_FILTER_NONE:
8133 /* For global configuration */
8134 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8136 case RTE_ETH_FILTER_HASH:
8137 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8139 case RTE_ETH_FILTER_MACVLAN:
8140 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8142 case RTE_ETH_FILTER_ETHERTYPE:
8143 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8145 case RTE_ETH_FILTER_TUNNEL:
8146 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8148 case RTE_ETH_FILTER_FDIR:
8149 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8152 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8162 * Check and enable Extended Tag.
8163 * Enabling Extended Tag is important for 40G performance.
8166 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8171 ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
8174 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8178 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
8179 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
8184 ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
8187 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8191 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
8192 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
8195 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
8196 ret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf),
8199 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
8206 * As some registers wouldn't be reset unless a global hardware reset,
8207 * hardware initialization is needed to put those registers into an
8208 * expected initial state.
8211 i40e_hw_init(struct rte_eth_dev *dev)
8213 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8215 i40e_enable_extended_tag(dev);
8217 /* clear the PF Queue Filter control register */
8218 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
8220 /* Disable symmetric hash per port */
8221 i40e_set_symmetric_hash_enable_per_port(hw, 0);
8224 enum i40e_filter_pctype
8225 i40e_flowtype_to_pctype(uint16_t flow_type)
8227 static const enum i40e_filter_pctype pctype_table[] = {
8228 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
8229 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
8230 I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
8231 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
8232 I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
8233 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
8234 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
8235 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
8236 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
8237 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
8238 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
8239 I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
8240 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
8241 I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
8242 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
8243 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
8244 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
8245 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
8246 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
8249 return pctype_table[flow_type];
8253 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
8255 static const uint16_t flowtype_table[] = {
8256 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
8257 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8258 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8260 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8261 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8262 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8263 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8265 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8266 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8268 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8269 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8271 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8272 RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
8273 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8274 RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
8275 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
8276 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8277 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8279 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8280 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8281 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8282 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8284 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8285 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8287 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8288 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8290 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8291 RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8292 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8293 RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8294 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8297 return flowtype_table[pctype];
8301 * On X710, performance number is far from the expectation on recent firmware
8302 * versions; on XL710, performance number is also far from the expectation on
8303 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8304 * mode is enabled and port MAC address is equal to the packet destination MAC
8305 * address. The fix for this issue may not be integrated in the following
8306 * firmware version. So the workaround in software driver is needed. It needs
8307 * to modify the initial values of 3 internal only registers for both X710 and
8308 * XL710. Note that the values for X710 or XL710 could be different, and the
8309 * workaround can be removed when it is fixed in firmware in the future.
8312 /* For both X710 and XL710 */
8313 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
8314 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
8316 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8317 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
8320 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
8322 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
8323 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
8326 i40e_dev_sync_phy_type(struct i40e_hw *hw)
8328 enum i40e_status_code status;
8329 struct i40e_aq_get_phy_abilities_resp phy_ab;
8332 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
8343 i40e_configure_registers(struct i40e_hw *hw)
8349 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
8350 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
8351 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8357 for (i = 0; i < RTE_DIM(reg_table); i++) {
8358 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8359 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
8360 I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
8362 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
8365 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
8368 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8371 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8375 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8376 reg_table[i].addr, reg);
8377 if (reg == reg_table[i].val)
8380 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
8381 reg_table[i].val, NULL);
8383 PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
8384 "address of 0x%"PRIx32, reg_table[i].val,
8388 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
8389 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
8393 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
8394 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
8395 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
8396 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
8398 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
8403 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
8404 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
8408 /* Configure for double VLAN RX stripping */
8409 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
8410 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
8411 reg |= I40E_VSI_TSR_QINQ_CONFIG;
8412 ret = i40e_aq_debug_write_register(hw,
8413 I40E_VSI_TSR(vsi->vsi_id),
8416 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
8418 return I40E_ERR_CONFIG;
8422 /* Configure for double VLAN TX insertion */
8423 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
8424 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
8425 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
8426 ret = i40e_aq_debug_write_register(hw,
8427 I40E_VSI_L2TAGSTXVALID(
8428 vsi->vsi_id), reg, NULL);
8430 PMD_DRV_LOG(ERR, "Failed to update "
8431 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
8432 return I40E_ERR_CONFIG;
8440 * i40e_aq_add_mirror_rule
8441 * @hw: pointer to the hardware structure
8442 * @seid: VEB seid to add mirror rule to
8443 * @dst_id: destination vsi seid
8444 * @entries: Buffer which contains the entities to be mirrored
8445 * @count: number of entities contained in the buffer
8446 * @rule_id:the rule_id of the rule to be added
8448 * Add a mirror rule for a given veb.
8451 static enum i40e_status_code
8452 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
8453 uint16_t seid, uint16_t dst_id,
8454 uint16_t rule_type, uint16_t *entries,
8455 uint16_t count, uint16_t *rule_id)
8457 struct i40e_aq_desc desc;
8458 struct i40e_aqc_add_delete_mirror_rule cmd;
8459 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8460 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8463 enum i40e_status_code status;
8465 i40e_fill_default_direct_cmd_desc(&desc,
8466 i40e_aqc_opc_add_mirror_rule);
8467 memset(&cmd, 0, sizeof(cmd));
8469 buff_len = sizeof(uint16_t) * count;
8470 desc.datalen = rte_cpu_to_le_16(buff_len);
8472 desc.flags |= rte_cpu_to_le_16(
8473 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8474 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8475 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8476 cmd.num_entries = rte_cpu_to_le_16(count);
8477 cmd.seid = rte_cpu_to_le_16(seid);
8478 cmd.destination = rte_cpu_to_le_16(dst_id);
8480 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8481 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8482 PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
8484 " mirror_rules_used = %u, mirror_rules_free = %u,",
8485 hw->aq.asq_last_status, resp->rule_id,
8486 resp->mirror_rules_used, resp->mirror_rules_free);
8487 *rule_id = rte_le_to_cpu_16(resp->rule_id);
8493 * i40e_aq_del_mirror_rule
8494 * @hw: pointer to the hardware structure
8495 * @seid: VEB seid to add mirror rule to
8496 * @entries: Buffer which contains the entities to be mirrored
8497 * @count: number of entities contained in the buffer
8498 * @rule_id:the rule_id of the rule to be delete
8500 * Delete a mirror rule for a given veb.
8503 static enum i40e_status_code
8504 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8505 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8506 uint16_t count, uint16_t rule_id)
8508 struct i40e_aq_desc desc;
8509 struct i40e_aqc_add_delete_mirror_rule cmd;
8510 uint16_t buff_len = 0;
8511 enum i40e_status_code status;
8514 i40e_fill_default_direct_cmd_desc(&desc,
8515 i40e_aqc_opc_delete_mirror_rule);
8516 memset(&cmd, 0, sizeof(cmd));
8517 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8518 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8520 cmd.num_entries = count;
8521 buff_len = sizeof(uint16_t) * count;
8522 desc.datalen = rte_cpu_to_le_16(buff_len);
8523 buff = (void *)entries;
8525 /* rule id is filled in destination field for deleting mirror rule */
8526 cmd.destination = rte_cpu_to_le_16(rule_id);
8528 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8529 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8530 cmd.seid = rte_cpu_to_le_16(seid);
8532 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8533 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
8539 * i40e_mirror_rule_set
8540 * @dev: pointer to the hardware structure
8541 * @mirror_conf: mirror rule info
8542 * @sw_id: mirror rule's sw_id
8543 * @on: enable/disable
8545 * set a mirror rule.
8549 i40e_mirror_rule_set(struct rte_eth_dev *dev,
8550 struct rte_eth_mirror_conf *mirror_conf,
8551 uint8_t sw_id, uint8_t on)
8553 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8554 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8555 struct i40e_mirror_rule *it, *mirr_rule = NULL;
8556 struct i40e_mirror_rule *parent = NULL;
8557 uint16_t seid, dst_seid, rule_id;
8561 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
8563 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
8564 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
8565 " without veb or vfs.");
8568 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
8569 PMD_DRV_LOG(ERR, "mirror table is full.");
8572 if (mirror_conf->dst_pool > pf->vf_num) {
8573 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
8574 mirror_conf->dst_pool);
8578 seid = pf->main_vsi->veb->seid;
8580 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8581 if (sw_id <= it->index) {
8587 if (mirr_rule && sw_id == mirr_rule->index) {
8589 PMD_DRV_LOG(ERR, "mirror rule exists.");
8592 ret = i40e_aq_del_mirror_rule(hw, seid,
8593 mirr_rule->rule_type,
8595 mirr_rule->num_entries, mirr_rule->id);
8597 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8598 " ret = %d, aq_err = %d.",
8599 ret, hw->aq.asq_last_status);
8602 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8603 rte_free(mirr_rule);
8604 pf->nb_mirror_rule--;
8608 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8612 mirr_rule = rte_zmalloc("i40e_mirror_rule",
8613 sizeof(struct i40e_mirror_rule) , 0);
8615 PMD_DRV_LOG(ERR, "failed to allocate memory");
8616 return I40E_ERR_NO_MEMORY;
8618 switch (mirror_conf->rule_type) {
8619 case ETH_MIRROR_VLAN:
8620 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
8621 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
8622 mirr_rule->entries[j] =
8623 mirror_conf->vlan.vlan_id[i];
8628 PMD_DRV_LOG(ERR, "vlan is not specified.");
8629 rte_free(mirr_rule);
8632 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
8634 case ETH_MIRROR_VIRTUAL_POOL_UP:
8635 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
8636 /* check if the specified pool bit is out of range */
8637 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
8638 PMD_DRV_LOG(ERR, "pool mask is out of range.");
8639 rte_free(mirr_rule);
8642 for (i = 0, j = 0; i < pf->vf_num; i++) {
8643 if (mirror_conf->pool_mask & (1ULL << i)) {
8644 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
8648 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
8649 /* add pf vsi to entries */
8650 mirr_rule->entries[j] = pf->main_vsi_seid;
8654 PMD_DRV_LOG(ERR, "pool is not specified.");
8655 rte_free(mirr_rule);
8658 /* egress and ingress in aq commands means from switch but not port */
8659 mirr_rule->rule_type =
8660 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
8661 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
8662 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
8664 case ETH_MIRROR_UPLINK_PORT:
8665 /* egress and ingress in aq commands means from switch but not port*/
8666 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
8668 case ETH_MIRROR_DOWNLINK_PORT:
8669 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
8672 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
8673 mirror_conf->rule_type);
8674 rte_free(mirr_rule);
8678 /* If the dst_pool is equal to vf_num, consider it as PF */
8679 if (mirror_conf->dst_pool == pf->vf_num)
8680 dst_seid = pf->main_vsi_seid;
8682 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
8684 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
8685 mirr_rule->rule_type, mirr_rule->entries,
8688 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
8689 " ret = %d, aq_err = %d.",
8690 ret, hw->aq.asq_last_status);
8691 rte_free(mirr_rule);
8695 mirr_rule->index = sw_id;
8696 mirr_rule->num_entries = j;
8697 mirr_rule->id = rule_id;
8698 mirr_rule->dst_vsi_seid = dst_seid;
8701 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
8703 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
8705 pf->nb_mirror_rule++;
8710 * i40e_mirror_rule_reset
8711 * @dev: pointer to the device
8712 * @sw_id: mirror rule's sw_id
8714 * reset a mirror rule.
8718 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
8720 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8721 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8722 struct i40e_mirror_rule *it, *mirr_rule = NULL;
8726 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
8728 seid = pf->main_vsi->veb->seid;
8730 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8731 if (sw_id == it->index) {
8737 ret = i40e_aq_del_mirror_rule(hw, seid,
8738 mirr_rule->rule_type,
8740 mirr_rule->num_entries, mirr_rule->id);
8742 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8743 " status = %d, aq_err = %d.",
8744 ret, hw->aq.asq_last_status);
8747 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8748 rte_free(mirr_rule);
8749 pf->nb_mirror_rule--;
8751 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8758 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
8760 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8761 uint64_t systim_cycles;
8763 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
8764 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
8767 return systim_cycles;
8771 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
8773 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8776 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
8777 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
8784 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
8786 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8789 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
8790 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
8797 i40e_start_timecounters(struct rte_eth_dev *dev)
8799 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8800 struct i40e_adapter *adapter =
8801 (struct i40e_adapter *)dev->data->dev_private;
8802 struct rte_eth_link link;
8803 uint32_t tsync_inc_l;
8804 uint32_t tsync_inc_h;
8806 /* Get current link speed. */
8807 memset(&link, 0, sizeof(link));
8808 i40e_dev_link_update(dev, 1);
8809 rte_i40e_dev_atomic_read_link_status(dev, &link);
8811 switch (link.link_speed) {
8812 case ETH_SPEED_NUM_40G:
8813 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
8814 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
8816 case ETH_SPEED_NUM_10G:
8817 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
8818 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
8820 case ETH_SPEED_NUM_1G:
8821 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
8822 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
8829 /* Set the timesync increment value. */
8830 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
8831 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
8833 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
8834 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8835 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8837 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8838 adapter->systime_tc.cc_shift = 0;
8839 adapter->systime_tc.nsec_mask = 0;
8841 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8842 adapter->rx_tstamp_tc.cc_shift = 0;
8843 adapter->rx_tstamp_tc.nsec_mask = 0;
8845 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8846 adapter->tx_tstamp_tc.cc_shift = 0;
8847 adapter->tx_tstamp_tc.nsec_mask = 0;
8851 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
8853 struct i40e_adapter *adapter =
8854 (struct i40e_adapter *)dev->data->dev_private;
8856 adapter->systime_tc.nsec += delta;
8857 adapter->rx_tstamp_tc.nsec += delta;
8858 adapter->tx_tstamp_tc.nsec += delta;
8864 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
8867 struct i40e_adapter *adapter =
8868 (struct i40e_adapter *)dev->data->dev_private;
8870 ns = rte_timespec_to_ns(ts);
8872 /* Set the timecounters to a new value. */
8873 adapter->systime_tc.nsec = ns;
8874 adapter->rx_tstamp_tc.nsec = ns;
8875 adapter->tx_tstamp_tc.nsec = ns;
8881 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
8883 uint64_t ns, systime_cycles;
8884 struct i40e_adapter *adapter =
8885 (struct i40e_adapter *)dev->data->dev_private;
8887 systime_cycles = i40e_read_systime_cyclecounter(dev);
8888 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
8889 *ts = rte_ns_to_timespec(ns);
8895 i40e_timesync_enable(struct rte_eth_dev *dev)
8897 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8898 uint32_t tsync_ctl_l;
8899 uint32_t tsync_ctl_h;
8901 /* Stop the timesync system time. */
8902 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8903 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8904 /* Reset the timesync system time value. */
8905 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
8906 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
8908 i40e_start_timecounters(dev);
8910 /* Clear timesync registers. */
8911 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8912 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
8913 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
8914 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
8915 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
8916 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
8918 /* Enable timestamping of PTP packets. */
8919 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8920 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
8922 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8923 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
8924 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
8926 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8927 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8933 i40e_timesync_disable(struct rte_eth_dev *dev)
8935 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8936 uint32_t tsync_ctl_l;
8937 uint32_t tsync_ctl_h;
8939 /* Disable timestamping of transmitted PTP packets. */
8940 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8941 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
8943 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8944 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
8946 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8947 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8949 /* Reset the timesync increment value. */
8950 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8951 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8957 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
8958 struct timespec *timestamp, uint32_t flags)
8960 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8961 struct i40e_adapter *adapter =
8962 (struct i40e_adapter *)dev->data->dev_private;
8964 uint32_t sync_status;
8965 uint32_t index = flags & 0x03;
8966 uint64_t rx_tstamp_cycles;
8969 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
8970 if ((sync_status & (1 << index)) == 0)
8973 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
8974 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
8975 *timestamp = rte_ns_to_timespec(ns);
8981 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
8982 struct timespec *timestamp)
8984 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8985 struct i40e_adapter *adapter =
8986 (struct i40e_adapter *)dev->data->dev_private;
8988 uint32_t sync_status;
8989 uint64_t tx_tstamp_cycles;
8992 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8993 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
8996 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
8997 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
8998 *timestamp = rte_ns_to_timespec(ns);
9004 * i40e_parse_dcb_configure - parse dcb configure from user
9005 * @dev: the device being configured
9006 * @dcb_cfg: pointer of the result of parse
9007 * @*tc_map: bit map of enabled traffic classes
9009 * Returns 0 on success, negative value on failure
9012 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9013 struct i40e_dcbx_config *dcb_cfg,
9016 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9017 uint8_t i, tc_bw, bw_lf;
9019 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9021 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9022 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9023 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9027 /* assume each tc has the same bw */
9028 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9029 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9030 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9031 /* to ensure the sum of tcbw is equal to 100 */
9032 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9033 for (i = 0; i < bw_lf; i++)
9034 dcb_cfg->etscfg.tcbwtable[i]++;
9036 /* assume each tc has the same Transmission Selection Algorithm */
9037 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9038 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9040 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9041 dcb_cfg->etscfg.prioritytable[i] =
9042 dcb_rx_conf->dcb_tc[i];
9044 /* FW needs one App to configure HW */
9045 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9046 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9047 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9048 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9050 if (dcb_rx_conf->nb_tcs == 0)
9051 *tc_map = 1; /* tc0 only */
9053 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9055 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9056 dcb_cfg->pfc.willing = 0;
9057 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9058 dcb_cfg->pfc.pfcenable = *tc_map;
9064 static enum i40e_status_code
9065 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9066 struct i40e_aqc_vsi_properties_data *info,
9067 uint8_t enabled_tcmap)
9069 enum i40e_status_code ret;
9070 int i, total_tc = 0;
9071 uint16_t qpnum_per_tc, bsf, qp_idx;
9072 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9073 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9074 uint16_t used_queues;
9076 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9077 if (ret != I40E_SUCCESS)
9080 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9081 if (enabled_tcmap & (1 << i))
9086 vsi->enabled_tc = enabled_tcmap;
9088 /* different VSI has different queues assigned */
9089 if (vsi->type == I40E_VSI_MAIN)
9090 used_queues = dev_data->nb_rx_queues -
9091 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9092 else if (vsi->type == I40E_VSI_VMDQ2)
9093 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9095 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9096 return I40E_ERR_NO_AVAILABLE_VSI;
9099 qpnum_per_tc = used_queues / total_tc;
9100 /* Number of queues per enabled TC */
9101 if (qpnum_per_tc == 0) {
9102 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9103 return I40E_ERR_INVALID_QP_ID;
9105 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9107 bsf = rte_bsf32(qpnum_per_tc);
9110 * Configure TC and queue mapping parameters, for enabled TC,
9111 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9112 * default queue will serve it.
9115 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9116 if (vsi->enabled_tc & (1 << i)) {
9117 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9118 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9119 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9120 qp_idx += qpnum_per_tc;
9122 info->tc_mapping[i] = 0;
9125 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9126 if (vsi->type == I40E_VSI_SRIOV) {
9127 info->mapping_flags |=
9128 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9129 for (i = 0; i < vsi->nb_qps; i++)
9130 info->queue_mapping[i] =
9131 rte_cpu_to_le_16(vsi->base_queue + i);
9133 info->mapping_flags |=
9134 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9135 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9137 info->valid_sections |=
9138 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9140 return I40E_SUCCESS;
9144 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9145 * @veb: VEB to be configured
9146 * @tc_map: enabled TC bitmap
9148 * Returns 0 on success, negative value on failure
9150 static enum i40e_status_code
9151 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9153 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9154 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9155 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9156 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9157 enum i40e_status_code ret = I40E_SUCCESS;
9161 /* Check if enabled_tc is same as existing or new TCs */
9162 if (veb->enabled_tc == tc_map)
9165 /* configure tc bandwidth */
9166 memset(&veb_bw, 0, sizeof(veb_bw));
9167 veb_bw.tc_valid_bits = tc_map;
9168 /* Enable ETS TCs with equal BW Share for now across all VSIs */
9169 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9170 if (tc_map & BIT_ULL(i))
9171 veb_bw.tc_bw_share_credits[i] = 1;
9173 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
9176 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
9177 " per TC failed = %d",
9178 hw->aq.asq_last_status);
9182 memset(&ets_query, 0, sizeof(ets_query));
9183 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9185 if (ret != I40E_SUCCESS) {
9186 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
9187 " configuration %u", hw->aq.asq_last_status);
9190 memset(&bw_query, 0, sizeof(bw_query));
9191 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9193 if (ret != I40E_SUCCESS) {
9194 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
9195 " configuration %u", hw->aq.asq_last_status);
9199 /* store and print out BW info */
9200 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
9201 veb->bw_info.bw_max = ets_query.tc_bw_max;
9202 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
9203 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
9204 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
9205 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
9207 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9208 veb->bw_info.bw_ets_share_credits[i] =
9209 bw_query.tc_bw_share_credits[i];
9210 veb->bw_info.bw_ets_credits[i] =
9211 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
9212 /* 4 bits per TC, 4th bit is reserved */
9213 veb->bw_info.bw_ets_max[i] =
9214 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
9215 RTE_LEN2MASK(3, uint8_t));
9216 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
9217 veb->bw_info.bw_ets_share_credits[i]);
9218 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
9219 veb->bw_info.bw_ets_credits[i]);
9220 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
9221 veb->bw_info.bw_ets_max[i]);
9224 veb->enabled_tc = tc_map;
9231 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
9232 * @vsi: VSI to be configured
9233 * @tc_map: enabled TC bitmap
9235 * Returns 0 on success, negative value on failure
9237 static enum i40e_status_code
9238 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
9240 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
9241 struct i40e_vsi_context ctxt;
9242 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
9243 enum i40e_status_code ret = I40E_SUCCESS;
9246 /* Check if enabled_tc is same as existing or new TCs */
9247 if (vsi->enabled_tc == tc_map)
9250 /* configure tc bandwidth */
9251 memset(&bw_data, 0, sizeof(bw_data));
9252 bw_data.tc_valid_bits = tc_map;
9253 /* Enable ETS TCs with equal BW Share for now across all VSIs */
9254 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9255 if (tc_map & BIT_ULL(i))
9256 bw_data.tc_bw_credits[i] = 1;
9258 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
9260 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
9261 " per TC failed = %d",
9262 hw->aq.asq_last_status);
9265 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
9266 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
9268 /* Update Queue Pairs Mapping for currently enabled UPs */
9269 ctxt.seid = vsi->seid;
9270 ctxt.pf_num = hw->pf_id;
9272 ctxt.uplink_seid = vsi->uplink_seid;
9273 ctxt.info = vsi->info;
9275 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
9279 /* Update the VSI after updating the VSI queue-mapping information */
9280 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9282 PMD_INIT_LOG(ERR, "Failed to configure "
9283 "TC queue mapping = %d",
9284 hw->aq.asq_last_status);
9287 /* update the local VSI info with updated queue map */
9288 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
9289 sizeof(vsi->info.tc_mapping));
9290 (void)rte_memcpy(&vsi->info.queue_mapping,
9291 &ctxt.info.queue_mapping,
9292 sizeof(vsi->info.queue_mapping));
9293 vsi->info.mapping_flags = ctxt.info.mapping_flags;
9294 vsi->info.valid_sections = 0;
9296 /* query and update current VSI BW information */
9297 ret = i40e_vsi_get_bw_config(vsi);
9300 "Failed updating vsi bw info, err %s aq_err %s",
9301 i40e_stat_str(hw, ret),
9302 i40e_aq_str(hw, hw->aq.asq_last_status));
9306 vsi->enabled_tc = tc_map;
9313 * i40e_dcb_hw_configure - program the dcb setting to hw
9314 * @pf: pf the configuration is taken on
9315 * @new_cfg: new configuration
9316 * @tc_map: enabled TC bitmap
9318 * Returns 0 on success, negative value on failure
9320 static enum i40e_status_code
9321 i40e_dcb_hw_configure(struct i40e_pf *pf,
9322 struct i40e_dcbx_config *new_cfg,
9325 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9326 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9327 struct i40e_vsi *main_vsi = pf->main_vsi;
9328 struct i40e_vsi_list *vsi_list;
9329 enum i40e_status_code ret;
9333 /* Use the FW API if FW > v4.4*/
9334 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9335 (hw->aq.fw_maj_ver >= 5))) {
9336 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
9337 " to configure DCB");
9338 return I40E_ERR_FIRMWARE_API_VERSION;
9341 /* Check if need reconfiguration */
9342 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9343 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9344 return I40E_SUCCESS;
9347 /* Copy the new config to the current config */
9348 *old_cfg = *new_cfg;
9349 old_cfg->etsrec = old_cfg->etscfg;
9350 ret = i40e_set_dcb_config(hw);
9353 "Set DCB Config failed, err %s aq_err %s\n",
9354 i40e_stat_str(hw, ret),
9355 i40e_aq_str(hw, hw->aq.asq_last_status));
9358 /* set receive Arbiter to RR mode and ETS scheme by default */
9359 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9360 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9361 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
9362 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9363 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9364 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9365 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9366 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9367 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9368 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9369 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9370 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9371 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9373 /* get local mib to check whether it is configured correctly */
9375 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9376 /* Get Local DCB Config */
9377 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9378 &hw->local_dcbx_config);
9380 /* if Veb is created, need to update TC of it at first */
9381 if (main_vsi->veb) {
9382 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
9384 PMD_INIT_LOG(WARNING,
9385 "Failed configuring TC for VEB seid=%d\n",
9386 main_vsi->veb->seid);
9388 /* Update each VSI */
9389 i40e_vsi_config_tc(main_vsi, tc_map);
9390 if (main_vsi->veb) {
9391 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
9392 /* Beside main VSI and VMDQ VSIs, only enable default
9395 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
9396 ret = i40e_vsi_config_tc(vsi_list->vsi,
9399 ret = i40e_vsi_config_tc(vsi_list->vsi,
9400 I40E_DEFAULT_TCMAP);
9402 PMD_INIT_LOG(WARNING,
9403 "Failed configuring TC for VSI seid=%d\n",
9404 vsi_list->vsi->seid);
9408 return I40E_SUCCESS;
9412 * i40e_dcb_init_configure - initial dcb config
9413 * @dev: device being configured
9414 * @sw_dcb: indicate whether dcb is sw configured or hw offload
9416 * Returns 0 on success, negative value on failure
9419 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
9421 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9422 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9425 if ((pf->flags & I40E_FLAG_DCB) == 0) {
9426 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9430 /* DCB initialization:
9431 * Update DCB configuration from the Firmware and configure
9432 * LLDP MIB change event.
9434 if (sw_dcb == TRUE) {
9435 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
9436 if (ret != I40E_SUCCESS)
9437 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
9439 ret = i40e_init_dcb(hw);
9440 /* if sw_dcb, lldp agent is stopped, the return from
9441 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
9444 if (ret != I40E_SUCCESS &&
9445 hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
9446 memset(&hw->local_dcbx_config, 0,
9447 sizeof(struct i40e_dcbx_config));
9448 /* set dcb default configuration */
9449 hw->local_dcbx_config.etscfg.willing = 0;
9450 hw->local_dcbx_config.etscfg.maxtcs = 0;
9451 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
9452 hw->local_dcbx_config.etscfg.tsatable[0] =
9454 hw->local_dcbx_config.etsrec =
9455 hw->local_dcbx_config.etscfg;
9456 hw->local_dcbx_config.pfc.willing = 0;
9457 hw->local_dcbx_config.pfc.pfccap =
9458 I40E_MAX_TRAFFIC_CLASS;
9459 /* FW needs one App to configure HW */
9460 hw->local_dcbx_config.numapps = 1;
9461 hw->local_dcbx_config.app[0].selector =
9462 I40E_APP_SEL_ETHTYPE;
9463 hw->local_dcbx_config.app[0].priority = 3;
9464 hw->local_dcbx_config.app[0].protocolid =
9465 I40E_APP_PROTOID_FCOE;
9466 ret = i40e_set_dcb_config(hw);
9468 PMD_INIT_LOG(ERR, "default dcb config fails."
9469 " err = %d, aq_err = %d.", ret,
9470 hw->aq.asq_last_status);
9474 PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9475 " aq_err = %d.", ret,
9476 hw->aq.asq_last_status);
9480 ret = i40e_aq_start_lldp(hw, NULL);
9481 if (ret != I40E_SUCCESS)
9482 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9484 ret = i40e_init_dcb(hw);
9486 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9487 PMD_INIT_LOG(ERR, "HW doesn't support"
9492 PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9493 " aq_err = %d.", ret,
9494 hw->aq.asq_last_status);
9502 * i40e_dcb_setup - setup dcb related config
9503 * @dev: device being configured
9505 * Returns 0 on success, negative value on failure
9508 i40e_dcb_setup(struct rte_eth_dev *dev)
9510 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9511 struct i40e_dcbx_config dcb_cfg;
9515 if ((pf->flags & I40E_FLAG_DCB) == 0) {
9516 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9520 if (pf->vf_num != 0)
9521 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9523 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9525 PMD_INIT_LOG(ERR, "invalid dcb config");
9528 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9530 PMD_INIT_LOG(ERR, "dcb sw configure fails");
9538 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
9539 struct rte_eth_dcb_info *dcb_info)
9541 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9542 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9543 struct i40e_vsi *vsi = pf->main_vsi;
9544 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
9545 uint16_t bsf, tc_mapping;
9548 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
9549 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
9551 dcb_info->nb_tcs = 1;
9552 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9553 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
9554 for (i = 0; i < dcb_info->nb_tcs; i++)
9555 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
9557 /* get queue mapping if vmdq is disabled */
9558 if (!pf->nb_cfg_vmdq_vsi) {
9559 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9560 if (!(vsi->enabled_tc & (1 << i)))
9562 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9563 dcb_info->tc_queue.tc_rxq[j][i].base =
9564 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9565 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9566 dcb_info->tc_queue.tc_txq[j][i].base =
9567 dcb_info->tc_queue.tc_rxq[j][i].base;
9568 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9569 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9570 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9571 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9572 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9577 /* get queue mapping if vmdq is enabled */
9579 vsi = pf->vmdq[j].vsi;
9580 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9581 if (!(vsi->enabled_tc & (1 << i)))
9583 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9584 dcb_info->tc_queue.tc_rxq[j][i].base =
9585 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9586 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9587 dcb_info->tc_queue.tc_txq[j][i].base =
9588 dcb_info->tc_queue.tc_rxq[j][i].base;
9589 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9590 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9591 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9592 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9593 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9596 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
9601 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
9603 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9604 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9606 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
9609 msix_intr = intr_handle->intr_vec[queue_id];
9610 if (msix_intr == I40E_MISC_VEC_ID)
9611 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
9612 I40E_PFINT_DYN_CTLN_INTENA_MASK |
9613 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9614 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9616 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9619 I40E_PFINT_DYN_CTLN(msix_intr -
9621 I40E_PFINT_DYN_CTLN_INTENA_MASK |
9622 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9623 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9625 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9627 I40E_WRITE_FLUSH(hw);
9628 rte_intr_enable(&dev->pci_dev->intr_handle);
9634 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
9636 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9637 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9640 msix_intr = intr_handle->intr_vec[queue_id];
9641 if (msix_intr == I40E_MISC_VEC_ID)
9642 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
9645 I40E_PFINT_DYN_CTLN(msix_intr -
9648 I40E_WRITE_FLUSH(hw);
9653 static int i40e_get_regs(struct rte_eth_dev *dev,
9654 struct rte_dev_reg_info *regs)
9656 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9657 uint32_t *ptr_data = regs->data;
9658 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
9659 const struct i40e_reg_info *reg_info;
9661 if (ptr_data == NULL) {
9662 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
9663 regs->width = sizeof(uint32_t);
9667 /* The first few registers have to be read using AQ operations */
9669 while (i40e_regs_adminq[reg_idx].name) {
9670 reg_info = &i40e_regs_adminq[reg_idx++];
9671 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9673 arr_idx2 <= reg_info->count2;
9675 reg_offset = arr_idx * reg_info->stride1 +
9676 arr_idx2 * reg_info->stride2;
9677 reg_offset += reg_info->base_addr;
9678 ptr_data[reg_offset >> 2] =
9679 i40e_read_rx_ctl(hw, reg_offset);
9683 /* The remaining registers can be read using primitives */
9685 while (i40e_regs_others[reg_idx].name) {
9686 reg_info = &i40e_regs_others[reg_idx++];
9687 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9689 arr_idx2 <= reg_info->count2;
9691 reg_offset = arr_idx * reg_info->stride1 +
9692 arr_idx2 * reg_info->stride2;
9693 reg_offset += reg_info->base_addr;
9694 ptr_data[reg_offset >> 2] =
9695 I40E_READ_REG(hw, reg_offset);
9702 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
9704 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9706 /* Convert word count to byte count */
9707 return hw->nvm.sr_size << 1;
9710 static int i40e_get_eeprom(struct rte_eth_dev *dev,
9711 struct rte_dev_eeprom_info *eeprom)
9713 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9714 uint16_t *data = eeprom->data;
9715 uint16_t offset, length, cnt_words;
9718 offset = eeprom->offset >> 1;
9719 length = eeprom->length >> 1;
9722 if (offset > hw->nvm.sr_size ||
9723 offset + length > hw->nvm.sr_size) {
9724 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
9728 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
9730 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
9731 if (ret_code != I40E_SUCCESS || cnt_words != length) {
9732 PMD_DRV_LOG(ERR, "EEPROM read failed.");
9739 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
9740 struct ether_addr *mac_addr)
9742 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9744 if (!is_valid_assigned_ether_addr(mac_addr)) {
9745 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
9749 /* Flags: 0x3 updates port address */
9750 i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
9754 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
9756 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9757 struct rte_eth_dev_data *dev_data = pf->dev_data;
9758 uint32_t frame_size = mtu + ETHER_HDR_LEN
9759 + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
9762 /* check if mtu is within the allowed range */
9763 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
9766 /* mtu setting is forbidden if port is start */
9767 if (dev_data->dev_started) {
9769 "port %d must be stopped before configuration\n",
9774 if (frame_size > ETHER_MAX_LEN)
9775 dev_data->dev_conf.rxmode.jumbo_frame = 1;
9777 dev_data->dev_conf.rxmode.jumbo_frame = 0;
9779 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;