4 * Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 #include <rte_string_fns.h>
45 #include <rte_ether.h>
46 #include <rte_ethdev.h>
47 #include <rte_memzone.h>
48 #include <rte_malloc.h>
49 #include <rte_memcpy.h>
50 #include <rte_alarm.h>
52 #include <rte_eth_ctrl.h>
53 #include <rte_tailq.h>
54 #include <rte_hash_crc.h>
56 #include "i40e_logs.h"
57 #include "base/i40e_prototype.h"
58 #include "base/i40e_adminq_cmd.h"
59 #include "base/i40e_type.h"
60 #include "base/i40e_register.h"
61 #include "base/i40e_dcb.h"
62 #include "i40e_ethdev.h"
63 #include "i40e_rxtx.h"
65 #include "i40e_regs.h"
66 #include "rte_pmd_i40e.h"
68 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
69 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
71 #define I40E_CLEAR_PXE_WAIT_MS 200
73 /* Maximun number of capability elements */
74 #define I40E_MAX_CAP_ELE_NUM 128
76 /* Wait count and inteval */
77 #define I40E_CHK_Q_ENA_COUNT 1000
78 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
80 /* Maximun number of VSI */
81 #define I40E_MAX_NUM_VSIS (384UL)
83 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
85 /* Flow control default timer */
86 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
88 /* Flow control default high water */
89 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
91 /* Flow control default low water */
92 #define I40E_DEFAULT_LOW_WATER (0x1A40/1024)
94 /* Flow control enable fwd bit */
95 #define I40E_PRTMAC_FWD_CTRL 0x00000001
97 /* Receive Packet Buffer size */
98 #define I40E_RXPBSIZE (968 * 1024)
100 /* Kilobytes shift */
101 #define I40E_KILOSHIFT 10
103 /* Receive Average Packet Size in Byte*/
104 #define I40E_PACKET_AVERAGE_SIZE 128
106 /* Mask of PF interrupt causes */
107 #define I40E_PFINT_ICR0_ENA_MASK ( \
108 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
109 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
110 I40E_PFINT_ICR0_ENA_GRST_MASK | \
111 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
112 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
113 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
114 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
115 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
116 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
118 #define I40E_FLOW_TYPES ( \
119 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
120 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
121 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
122 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
123 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
124 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
125 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
126 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
127 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
128 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
129 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
131 /* Additional timesync values. */
132 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
133 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
134 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
135 #define I40E_PRTTSYN_TSYNENA 0x80000000
136 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
137 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
139 #define I40E_MAX_PERCENT 100
140 #define I40E_DEFAULT_DCB_APP_NUM 1
141 #define I40E_DEFAULT_DCB_APP_PRIO 3
144 * Below are values for writing un-exposed registers suggested
147 /* Destination MAC address */
148 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
149 /* Source MAC address */
150 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
151 /* Outer (S-Tag) VLAN tag in the outer L2 header */
152 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
153 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
154 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
155 /* Single VLAN tag in the inner L2 header */
156 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
157 /* Source IPv4 address */
158 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
159 /* Destination IPv4 address */
160 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
161 /* Source IPv4 address for X722 */
162 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
163 /* Destination IPv4 address for X722 */
164 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
165 /* IPv4 Protocol for X722 */
166 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
167 /* IPv4 Time to Live for X722 */
168 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
169 /* IPv4 Type of Service (TOS) */
170 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
172 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
173 /* IPv4 Time to Live */
174 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
175 /* Source IPv6 address */
176 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
177 /* Destination IPv6 address */
178 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
179 /* IPv6 Traffic Class (TC) */
180 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
181 /* IPv6 Next Header */
182 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
184 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
186 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
187 /* Destination L4 port */
188 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
189 /* SCTP verification tag */
190 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
191 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
192 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
193 /* Source port of tunneling UDP */
194 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
195 /* Destination port of tunneling UDP */
196 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
197 /* UDP Tunneling ID, NVGRE/GRE key */
198 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
199 /* Last ether type */
200 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
201 /* Tunneling outer destination IPv4 address */
202 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
203 /* Tunneling outer destination IPv6 address */
204 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
205 /* 1st word of flex payload */
206 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
207 /* 2nd word of flex payload */
208 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
209 /* 3rd word of flex payload */
210 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
211 /* 4th word of flex payload */
212 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
213 /* 5th word of flex payload */
214 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
215 /* 6th word of flex payload */
216 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
217 /* 7th word of flex payload */
218 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
219 /* 8th word of flex payload */
220 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
221 /* all 8 words flex payload */
222 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
223 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
225 #define I40E_TRANSLATE_INSET 0
226 #define I40E_TRANSLATE_REG 1
228 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
229 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
230 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
231 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
232 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
233 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
235 /* PCI offset for querying capability */
236 #define PCI_DEV_CAP_REG 0xA4
237 /* PCI offset for enabling/disabling Extended Tag */
238 #define PCI_DEV_CTRL_REG 0xA8
239 /* Bit mask of Extended Tag capability */
240 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
241 /* Bit shift of Extended Tag enable/disable */
242 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
243 /* Bit mask of Extended Tag enable/disable */
244 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
246 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
247 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
248 static int i40e_dev_configure(struct rte_eth_dev *dev);
249 static int i40e_dev_start(struct rte_eth_dev *dev);
250 static void i40e_dev_stop(struct rte_eth_dev *dev);
251 static void i40e_dev_close(struct rte_eth_dev *dev);
252 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
253 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
254 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
255 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
256 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
257 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
258 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
259 struct rte_eth_stats *stats);
260 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
261 struct rte_eth_xstat *xstats, unsigned n);
262 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
263 struct rte_eth_xstat_name *xstats_names,
265 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
266 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
270 static int i40e_fw_version_get(struct rte_eth_dev *dev,
271 char *fw_version, size_t fw_size);
272 static void i40e_dev_info_get(struct rte_eth_dev *dev,
273 struct rte_eth_dev_info *dev_info);
274 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
277 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
278 enum rte_vlan_type vlan_type,
280 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
281 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
284 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
285 static int i40e_dev_led_on(struct rte_eth_dev *dev);
286 static int i40e_dev_led_off(struct rte_eth_dev *dev);
287 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
288 struct rte_eth_fc_conf *fc_conf);
289 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
290 struct rte_eth_fc_conf *fc_conf);
291 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
292 struct rte_eth_pfc_conf *pfc_conf);
293 static void i40e_macaddr_add(struct rte_eth_dev *dev,
294 struct ether_addr *mac_addr,
297 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
298 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
299 struct rte_eth_rss_reta_entry64 *reta_conf,
301 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
302 struct rte_eth_rss_reta_entry64 *reta_conf,
305 static int i40e_get_cap(struct i40e_hw *hw);
306 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
307 static int i40e_pf_setup(struct i40e_pf *pf);
308 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
309 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
310 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
311 static int i40e_dcb_setup(struct rte_eth_dev *dev);
312 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
313 bool offset_loaded, uint64_t *offset, uint64_t *stat);
314 static void i40e_stat_update_48(struct i40e_hw *hw,
320 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
321 static void i40e_dev_interrupt_handler(struct rte_intr_handle *handle,
323 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
324 uint32_t base, uint32_t num);
325 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
326 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
328 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
330 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
331 static int i40e_veb_release(struct i40e_veb *veb);
332 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
333 struct i40e_vsi *vsi);
334 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
335 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
336 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
337 struct i40e_macvlan_filter *mv_f,
339 struct ether_addr *addr);
340 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
341 struct i40e_macvlan_filter *mv_f,
344 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
345 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
346 struct rte_eth_rss_conf *rss_conf);
347 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
348 struct rte_eth_rss_conf *rss_conf);
349 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
350 struct rte_eth_udp_tunnel *udp_tunnel);
351 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
352 struct rte_eth_udp_tunnel *udp_tunnel);
353 static void i40e_filter_input_set_init(struct i40e_pf *pf);
354 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
355 enum rte_filter_op filter_op,
357 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
358 enum rte_filter_type filter_type,
359 enum rte_filter_op filter_op,
361 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
362 struct rte_eth_dcb_info *dcb_info);
363 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
364 static void i40e_configure_registers(struct i40e_hw *hw);
365 static void i40e_hw_init(struct rte_eth_dev *dev);
366 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
367 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
368 struct rte_eth_mirror_conf *mirror_conf,
369 uint8_t sw_id, uint8_t on);
370 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
372 static int i40e_timesync_enable(struct rte_eth_dev *dev);
373 static int i40e_timesync_disable(struct rte_eth_dev *dev);
374 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
375 struct timespec *timestamp,
377 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
378 struct timespec *timestamp);
379 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
381 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
383 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
384 struct timespec *timestamp);
385 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
386 const struct timespec *timestamp);
388 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
390 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
393 static int i40e_get_regs(struct rte_eth_dev *dev,
394 struct rte_dev_reg_info *regs);
396 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
398 static int i40e_get_eeprom(struct rte_eth_dev *dev,
399 struct rte_dev_eeprom_info *eeprom);
401 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
402 struct ether_addr *mac_addr);
404 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
406 static int i40e_ethertype_filter_convert(
407 const struct rte_eth_ethertype_filter *input,
408 struct i40e_ethertype_filter *filter);
409 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
410 struct i40e_ethertype_filter *filter);
412 static int i40e_tunnel_filter_convert(
413 struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter,
414 struct i40e_tunnel_filter *tunnel_filter);
415 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
416 struct i40e_tunnel_filter *tunnel_filter);
418 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
419 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
420 static void i40e_filter_restore(struct i40e_pf *pf);
422 static const struct rte_pci_id pci_id_i40e_map[] = {
423 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
424 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
425 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
426 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
427 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
428 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
429 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
430 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
431 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
432 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
435 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
436 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
437 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
438 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
439 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
440 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
441 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
442 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
443 { .vendor_id = 0, /* sentinel */ },
446 static const struct eth_dev_ops i40e_eth_dev_ops = {
447 .dev_configure = i40e_dev_configure,
448 .dev_start = i40e_dev_start,
449 .dev_stop = i40e_dev_stop,
450 .dev_close = i40e_dev_close,
451 .promiscuous_enable = i40e_dev_promiscuous_enable,
452 .promiscuous_disable = i40e_dev_promiscuous_disable,
453 .allmulticast_enable = i40e_dev_allmulticast_enable,
454 .allmulticast_disable = i40e_dev_allmulticast_disable,
455 .dev_set_link_up = i40e_dev_set_link_up,
456 .dev_set_link_down = i40e_dev_set_link_down,
457 .link_update = i40e_dev_link_update,
458 .stats_get = i40e_dev_stats_get,
459 .xstats_get = i40e_dev_xstats_get,
460 .xstats_get_names = i40e_dev_xstats_get_names,
461 .stats_reset = i40e_dev_stats_reset,
462 .xstats_reset = i40e_dev_stats_reset,
463 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
464 .fw_version_get = i40e_fw_version_get,
465 .dev_infos_get = i40e_dev_info_get,
466 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
467 .vlan_filter_set = i40e_vlan_filter_set,
468 .vlan_tpid_set = i40e_vlan_tpid_set,
469 .vlan_offload_set = i40e_vlan_offload_set,
470 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
471 .vlan_pvid_set = i40e_vlan_pvid_set,
472 .rx_queue_start = i40e_dev_rx_queue_start,
473 .rx_queue_stop = i40e_dev_rx_queue_stop,
474 .tx_queue_start = i40e_dev_tx_queue_start,
475 .tx_queue_stop = i40e_dev_tx_queue_stop,
476 .rx_queue_setup = i40e_dev_rx_queue_setup,
477 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
478 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
479 .rx_queue_release = i40e_dev_rx_queue_release,
480 .rx_queue_count = i40e_dev_rx_queue_count,
481 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
482 .tx_queue_setup = i40e_dev_tx_queue_setup,
483 .tx_queue_release = i40e_dev_tx_queue_release,
484 .dev_led_on = i40e_dev_led_on,
485 .dev_led_off = i40e_dev_led_off,
486 .flow_ctrl_get = i40e_flow_ctrl_get,
487 .flow_ctrl_set = i40e_flow_ctrl_set,
488 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
489 .mac_addr_add = i40e_macaddr_add,
490 .mac_addr_remove = i40e_macaddr_remove,
491 .reta_update = i40e_dev_rss_reta_update,
492 .reta_query = i40e_dev_rss_reta_query,
493 .rss_hash_update = i40e_dev_rss_hash_update,
494 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
495 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
496 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
497 .filter_ctrl = i40e_dev_filter_ctrl,
498 .rxq_info_get = i40e_rxq_info_get,
499 .txq_info_get = i40e_txq_info_get,
500 .mirror_rule_set = i40e_mirror_rule_set,
501 .mirror_rule_reset = i40e_mirror_rule_reset,
502 .timesync_enable = i40e_timesync_enable,
503 .timesync_disable = i40e_timesync_disable,
504 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
505 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
506 .get_dcb_info = i40e_dev_get_dcb_info,
507 .timesync_adjust_time = i40e_timesync_adjust_time,
508 .timesync_read_time = i40e_timesync_read_time,
509 .timesync_write_time = i40e_timesync_write_time,
510 .get_reg = i40e_get_regs,
511 .get_eeprom_length = i40e_get_eeprom_length,
512 .get_eeprom = i40e_get_eeprom,
513 .mac_addr_set = i40e_set_default_mac_addr,
514 .mtu_set = i40e_dev_mtu_set,
517 /* store statistics names and its offset in stats structure */
518 struct rte_i40e_xstats_name_off {
519 char name[RTE_ETH_XSTATS_NAME_SIZE];
523 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
524 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
525 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
526 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
527 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
528 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
529 rx_unknown_protocol)},
530 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
531 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
532 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
533 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
536 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
537 sizeof(rte_i40e_stats_strings[0]))
539 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
540 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
541 tx_dropped_link_down)},
542 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
543 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
545 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
546 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
548 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
550 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
552 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
553 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
554 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
555 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
556 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
557 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
559 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
561 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
563 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
565 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
567 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
569 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
571 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
573 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
574 mac_short_packet_dropped)},
575 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
577 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
578 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
579 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
581 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
583 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
585 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
587 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
589 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
591 {"rx_flow_director_atr_match_packets",
592 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
593 {"rx_flow_director_sb_match_packets",
594 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
595 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
597 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
599 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
601 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
605 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
606 sizeof(rte_i40e_hw_port_strings[0]))
608 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
609 {"xon_packets", offsetof(struct i40e_hw_port_stats,
611 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
615 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
616 sizeof(rte_i40e_rxq_prio_strings[0]))
618 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
619 {"xon_packets", offsetof(struct i40e_hw_port_stats,
621 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
623 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
624 priority_xon_2_xoff)},
627 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
628 sizeof(rte_i40e_txq_prio_strings[0]))
630 static struct eth_driver rte_i40e_pmd = {
632 .id_table = pci_id_i40e_map,
633 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
634 .probe = rte_eth_dev_pci_probe,
635 .remove = rte_eth_dev_pci_remove,
637 .eth_dev_init = eth_i40e_dev_init,
638 .eth_dev_uninit = eth_i40e_dev_uninit,
639 .dev_private_size = sizeof(struct i40e_adapter),
643 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
644 struct rte_eth_link *link)
646 struct rte_eth_link *dst = link;
647 struct rte_eth_link *src = &(dev->data->dev_link);
649 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
650 *(uint64_t *)src) == 0)
657 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
658 struct rte_eth_link *link)
660 struct rte_eth_link *dst = &(dev->data->dev_link);
661 struct rte_eth_link *src = link;
663 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
664 *(uint64_t *)src) == 0)
670 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
671 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
672 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio");
674 #ifndef I40E_GLQF_ORT
675 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
677 #ifndef I40E_GLQF_PIT
678 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
681 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
684 * Initialize registers for flexible payload, which should be set by NVM.
685 * This should be removed from code once it is fixed in NVM.
687 I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
688 I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
689 I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
690 I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
691 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
692 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
693 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
694 I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
695 I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
696 I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
697 I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
698 I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
700 /* Initialize registers for parsing packet type of QinQ */
701 I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
702 I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
705 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
708 * Add a ethertype filter to drop all flow control frames transmitted
712 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
714 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
715 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
716 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
717 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
720 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
721 I40E_FLOW_CONTROL_ETHERTYPE, flags,
722 pf->main_vsi_seid, 0,
726 "Failed to add filter to drop flow control frames from VSIs.");
730 floating_veb_list_handler(__rte_unused const char *key,
731 const char *floating_veb_value,
735 unsigned int count = 0;
738 bool *vf_floating_veb = opaque;
740 while (isblank(*floating_veb_value))
741 floating_veb_value++;
743 /* Reset floating VEB configuration for VFs */
744 for (idx = 0; idx < I40E_MAX_VF; idx++)
745 vf_floating_veb[idx] = false;
749 while (isblank(*floating_veb_value))
750 floating_veb_value++;
751 if (*floating_veb_value == '\0')
754 idx = strtoul(floating_veb_value, &end, 10);
755 if (errno || end == NULL)
757 while (isblank(*end))
761 } else if ((*end == ';') || (*end == '\0')) {
763 if (min == I40E_MAX_VF)
765 if (max >= I40E_MAX_VF)
766 max = I40E_MAX_VF - 1;
767 for (idx = min; idx <= max; idx++) {
768 vf_floating_veb[idx] = true;
775 floating_veb_value = end + 1;
776 } while (*end != '\0');
785 config_vf_floating_veb(struct rte_devargs *devargs,
786 uint16_t floating_veb,
787 bool *vf_floating_veb)
789 struct rte_kvargs *kvlist;
791 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
795 /* All the VFs attach to the floating VEB by default
796 * when the floating VEB is enabled.
798 for (i = 0; i < I40E_MAX_VF; i++)
799 vf_floating_veb[i] = true;
804 kvlist = rte_kvargs_parse(devargs->args, NULL);
808 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
809 rte_kvargs_free(kvlist);
812 /* When the floating_veb_list parameter exists, all the VFs
813 * will attach to the legacy VEB firstly, then configure VFs
814 * to the floating VEB according to the floating_veb_list.
816 if (rte_kvargs_process(kvlist, floating_veb_list,
817 floating_veb_list_handler,
818 vf_floating_veb) < 0) {
819 rte_kvargs_free(kvlist);
822 rte_kvargs_free(kvlist);
826 i40e_check_floating_handler(__rte_unused const char *key,
828 __rte_unused void *opaque)
830 if (strcmp(value, "1"))
837 is_floating_veb_supported(struct rte_devargs *devargs)
839 struct rte_kvargs *kvlist;
840 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
845 kvlist = rte_kvargs_parse(devargs->args, NULL);
849 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
850 rte_kvargs_free(kvlist);
853 /* Floating VEB is enabled when there's key-value:
854 * enable_floating_veb=1
856 if (rte_kvargs_process(kvlist, floating_veb_key,
857 i40e_check_floating_handler, NULL) < 0) {
858 rte_kvargs_free(kvlist);
861 rte_kvargs_free(kvlist);
867 config_floating_veb(struct rte_eth_dev *dev)
869 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
870 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
871 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
873 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
875 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
877 is_floating_veb_supported(pci_dev->device.devargs);
878 config_vf_floating_veb(pci_dev->device.devargs,
880 pf->floating_veb_list);
882 pf->floating_veb = false;
886 #define I40E_L2_TAGS_S_TAG_SHIFT 1
887 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
890 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
892 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
893 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
894 char ethertype_hash_name[RTE_HASH_NAMESIZE];
897 struct rte_hash_parameters ethertype_hash_params = {
898 .name = ethertype_hash_name,
899 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
900 .key_len = sizeof(struct i40e_ethertype_filter_input),
901 .hash_func = rte_hash_crc,
904 /* Initialize ethertype filter rule list and hash */
905 TAILQ_INIT(ðertype_rule->ethertype_list);
906 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
907 "ethertype_%s", dev->data->name);
908 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
909 if (!ethertype_rule->hash_table) {
910 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
913 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
914 sizeof(struct i40e_ethertype_filter *) *
915 I40E_MAX_ETHERTYPE_FILTER_NUM,
917 if (!ethertype_rule->hash_map) {
919 "Failed to allocate memory for ethertype hash map!");
921 goto err_ethertype_hash_map_alloc;
926 err_ethertype_hash_map_alloc:
927 rte_hash_free(ethertype_rule->hash_table);
933 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
935 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
936 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
937 char tunnel_hash_name[RTE_HASH_NAMESIZE];
940 struct rte_hash_parameters tunnel_hash_params = {
941 .name = tunnel_hash_name,
942 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
943 .key_len = sizeof(struct i40e_tunnel_filter_input),
944 .hash_func = rte_hash_crc,
947 /* Initialize tunnel filter rule list and hash */
948 TAILQ_INIT(&tunnel_rule->tunnel_list);
949 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
950 "tunnel_%s", dev->data->name);
951 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
952 if (!tunnel_rule->hash_table) {
953 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
956 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
957 sizeof(struct i40e_tunnel_filter *) *
958 I40E_MAX_TUNNEL_FILTER_NUM,
960 if (!tunnel_rule->hash_map) {
962 "Failed to allocate memory for tunnel hash map!");
964 goto err_tunnel_hash_map_alloc;
969 err_tunnel_hash_map_alloc:
970 rte_hash_free(tunnel_rule->hash_table);
976 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
978 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
979 struct i40e_fdir_info *fdir_info = &pf->fdir;
980 char fdir_hash_name[RTE_HASH_NAMESIZE];
983 struct rte_hash_parameters fdir_hash_params = {
984 .name = fdir_hash_name,
985 .entries = I40E_MAX_FDIR_FILTER_NUM,
986 .key_len = sizeof(struct rte_eth_fdir_input),
987 .hash_func = rte_hash_crc,
990 /* Initialize flow director filter rule list and hash */
991 TAILQ_INIT(&fdir_info->fdir_list);
992 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
993 "fdir_%s", dev->data->name);
994 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
995 if (!fdir_info->hash_table) {
996 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
999 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1000 sizeof(struct i40e_fdir_filter *) *
1001 I40E_MAX_FDIR_FILTER_NUM,
1003 if (!fdir_info->hash_map) {
1005 "Failed to allocate memory for fdir hash map!");
1007 goto err_fdir_hash_map_alloc;
1011 err_fdir_hash_map_alloc:
1012 rte_hash_free(fdir_info->hash_table);
1018 eth_i40e_dev_init(struct rte_eth_dev *dev)
1020 struct rte_pci_device *pci_dev;
1021 struct rte_intr_handle *intr_handle;
1022 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1023 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1024 struct i40e_vsi *vsi;
1027 uint8_t aq_fail = 0;
1029 PMD_INIT_FUNC_TRACE();
1031 dev->dev_ops = &i40e_eth_dev_ops;
1032 dev->rx_pkt_burst = i40e_recv_pkts;
1033 dev->tx_pkt_burst = i40e_xmit_pkts;
1034 dev->tx_pkt_prepare = i40e_prep_pkts;
1036 /* for secondary processes, we don't initialise any further as primary
1037 * has already done this work. Only check we don't need a different
1039 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1040 i40e_set_rx_function(dev);
1041 i40e_set_tx_function(dev);
1044 pci_dev = I40E_DEV_TO_PCI(dev);
1045 intr_handle = &pci_dev->intr_handle;
1047 rte_eth_copy_pci_info(dev, pci_dev);
1048 dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
1050 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1051 pf->adapter->eth_dev = dev;
1052 pf->dev_data = dev->data;
1054 hw->back = I40E_PF_TO_ADAPTER(pf);
1055 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1058 "Hardware is not available, as address is NULL");
1062 hw->vendor_id = pci_dev->id.vendor_id;
1063 hw->device_id = pci_dev->id.device_id;
1064 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1065 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1066 hw->bus.device = pci_dev->addr.devid;
1067 hw->bus.func = pci_dev->addr.function;
1068 hw->adapter_stopped = 0;
1070 /* Make sure all is clean before doing PF reset */
1073 /* Initialize the hardware */
1076 /* Reset here to make sure all is clean for each PF */
1077 ret = i40e_pf_reset(hw);
1079 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1083 /* Initialize the shared code (base driver) */
1084 ret = i40e_init_shared_code(hw);
1086 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1091 * To work around the NVM issue, initialize registers
1092 * for flexible payload and packet type of QinQ by
1093 * software. It should be removed once issues are fixed
1096 i40e_GLQF_reg_init(hw);
1098 /* Initialize the input set for filters (hash and fd) to default value */
1099 i40e_filter_input_set_init(pf);
1101 /* Initialize the parameters for adminq */
1102 i40e_init_adminq_parameter(hw);
1103 ret = i40e_init_adminq(hw);
1104 if (ret != I40E_SUCCESS) {
1105 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1108 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1109 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1110 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1111 ((hw->nvm.version >> 12) & 0xf),
1112 ((hw->nvm.version >> 4) & 0xff),
1113 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1115 /* Need the special FW version to support floating VEB */
1116 config_floating_veb(dev);
1117 /* Clear PXE mode */
1118 i40e_clear_pxe_mode(hw);
1119 ret = i40e_dev_sync_phy_type(hw);
1121 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1122 goto err_sync_phy_type;
1125 * On X710, performance number is far from the expectation on recent
1126 * firmware versions. The fix for this issue may not be integrated in
1127 * the following firmware version. So the workaround in software driver
1128 * is needed. It needs to modify the initial values of 3 internal only
1129 * registers. Note that the workaround can be removed when it is fixed
1130 * in firmware in the future.
1132 i40e_configure_registers(hw);
1134 /* Get hw capabilities */
1135 ret = i40e_get_cap(hw);
1136 if (ret != I40E_SUCCESS) {
1137 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1138 goto err_get_capabilities;
1141 /* Initialize parameters for PF */
1142 ret = i40e_pf_parameter_init(dev);
1144 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1145 goto err_parameter_init;
1148 /* Initialize the queue management */
1149 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1151 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1152 goto err_qp_pool_init;
1154 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1155 hw->func_caps.num_msix_vectors - 1);
1157 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1158 goto err_msix_pool_init;
1161 /* Initialize lan hmc */
1162 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1163 hw->func_caps.num_rx_qp, 0, 0);
1164 if (ret != I40E_SUCCESS) {
1165 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1166 goto err_init_lan_hmc;
1169 /* Configure lan hmc */
1170 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1171 if (ret != I40E_SUCCESS) {
1172 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1173 goto err_configure_lan_hmc;
1176 /* Get and check the mac address */
1177 i40e_get_mac_addr(hw, hw->mac.addr);
1178 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1179 PMD_INIT_LOG(ERR, "mac address is not valid");
1181 goto err_get_mac_addr;
1183 /* Copy the permanent MAC address */
1184 ether_addr_copy((struct ether_addr *) hw->mac.addr,
1185 (struct ether_addr *) hw->mac.perm_addr);
1187 /* Disable flow control */
1188 hw->fc.requested_mode = I40E_FC_NONE;
1189 i40e_set_fc(hw, &aq_fail, TRUE);
1191 /* Set the global registers with default ether type value */
1192 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1193 if (ret != I40E_SUCCESS) {
1195 "Failed to set the default outer VLAN ether type");
1196 goto err_setup_pf_switch;
1199 /* PF setup, which includes VSI setup */
1200 ret = i40e_pf_setup(pf);
1202 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1203 goto err_setup_pf_switch;
1206 /* reset all stats of the device, including pf and main vsi */
1207 i40e_dev_stats_reset(dev);
1211 /* Disable double vlan by default */
1212 i40e_vsi_config_double_vlan(vsi, FALSE);
1214 /* Disable S-TAG identification when floating_veb is disabled */
1215 if (!pf->floating_veb) {
1216 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1217 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1218 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1219 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1223 if (!vsi->max_macaddrs)
1224 len = ETHER_ADDR_LEN;
1226 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1228 /* Should be after VSI initialized */
1229 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1230 if (!dev->data->mac_addrs) {
1232 "Failed to allocated memory for storing mac address");
1235 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1236 &dev->data->mac_addrs[0]);
1238 /* initialize pf host driver to setup SRIOV resource if applicable */
1239 i40e_pf_host_init(dev);
1241 /* register callback func to eal lib */
1242 rte_intr_callback_register(intr_handle,
1243 i40e_dev_interrupt_handler, dev);
1245 /* configure and enable device interrupt */
1246 i40e_pf_config_irq0(hw, TRUE);
1247 i40e_pf_enable_irq0(hw);
1249 /* enable uio intr after callback register */
1250 rte_intr_enable(intr_handle);
1252 * Add an ethertype filter to drop all flow control frames transmitted
1253 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1256 i40e_add_tx_flow_control_drop_filter(pf);
1258 /* Set the max frame size to 0x2600 by default,
1259 * in case other drivers changed the default value.
1261 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1263 /* initialize mirror rule list */
1264 TAILQ_INIT(&pf->mirror_list);
1266 /* Init dcb to sw mode by default */
1267 ret = i40e_dcb_init_configure(dev, TRUE);
1268 if (ret != I40E_SUCCESS) {
1269 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1270 pf->flags &= ~I40E_FLAG_DCB;
1273 ret = i40e_init_ethtype_filter_list(dev);
1275 goto err_init_ethtype_filter_list;
1276 ret = i40e_init_tunnel_filter_list(dev);
1278 goto err_init_tunnel_filter_list;
1279 ret = i40e_init_fdir_filter_list(dev);
1281 goto err_init_fdir_filter_list;
1285 err_init_fdir_filter_list:
1286 rte_free(pf->tunnel.hash_table);
1287 rte_free(pf->tunnel.hash_map);
1288 err_init_tunnel_filter_list:
1289 rte_free(pf->ethertype.hash_table);
1290 rte_free(pf->ethertype.hash_map);
1291 err_init_ethtype_filter_list:
1292 rte_free(dev->data->mac_addrs);
1294 i40e_vsi_release(pf->main_vsi);
1295 err_setup_pf_switch:
1297 err_configure_lan_hmc:
1298 (void)i40e_shutdown_lan_hmc(hw);
1300 i40e_res_pool_destroy(&pf->msix_pool);
1302 i40e_res_pool_destroy(&pf->qp_pool);
1305 err_get_capabilities:
1307 (void)i40e_shutdown_adminq(hw);
1313 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1315 struct i40e_ethertype_filter *p_ethertype;
1316 struct i40e_ethertype_rule *ethertype_rule;
1318 ethertype_rule = &pf->ethertype;
1319 /* Remove all ethertype filter rules and hash */
1320 if (ethertype_rule->hash_map)
1321 rte_free(ethertype_rule->hash_map);
1322 if (ethertype_rule->hash_table)
1323 rte_hash_free(ethertype_rule->hash_table);
1325 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1326 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1327 p_ethertype, rules);
1328 rte_free(p_ethertype);
1333 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1335 struct i40e_tunnel_filter *p_tunnel;
1336 struct i40e_tunnel_rule *tunnel_rule;
1338 tunnel_rule = &pf->tunnel;
1339 /* Remove all tunnel director rules and hash */
1340 if (tunnel_rule->hash_map)
1341 rte_free(tunnel_rule->hash_map);
1342 if (tunnel_rule->hash_table)
1343 rte_hash_free(tunnel_rule->hash_table);
1345 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1346 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1352 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1354 struct i40e_fdir_filter *p_fdir;
1355 struct i40e_fdir_info *fdir_info;
1357 fdir_info = &pf->fdir;
1358 /* Remove all flow director rules and hash */
1359 if (fdir_info->hash_map)
1360 rte_free(fdir_info->hash_map);
1361 if (fdir_info->hash_table)
1362 rte_hash_free(fdir_info->hash_table);
1364 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1365 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1371 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1374 struct rte_pci_device *pci_dev;
1375 struct rte_intr_handle *intr_handle;
1377 struct i40e_filter_control_settings settings;
1378 struct rte_flow *p_flow;
1380 uint8_t aq_fail = 0;
1382 PMD_INIT_FUNC_TRACE();
1384 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1387 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1388 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1389 pci_dev = I40E_DEV_TO_PCI(dev);
1390 intr_handle = &pci_dev->intr_handle;
1392 if (hw->adapter_stopped == 0)
1393 i40e_dev_close(dev);
1395 dev->dev_ops = NULL;
1396 dev->rx_pkt_burst = NULL;
1397 dev->tx_pkt_burst = NULL;
1399 /* Clear PXE mode */
1400 i40e_clear_pxe_mode(hw);
1402 /* Unconfigure filter control */
1403 memset(&settings, 0, sizeof(settings));
1404 ret = i40e_set_filter_control(hw, &settings);
1406 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1409 /* Disable flow control */
1410 hw->fc.requested_mode = I40E_FC_NONE;
1411 i40e_set_fc(hw, &aq_fail, TRUE);
1413 /* uninitialize pf host driver */
1414 i40e_pf_host_uninit(dev);
1416 rte_free(dev->data->mac_addrs);
1417 dev->data->mac_addrs = NULL;
1419 /* disable uio intr before callback unregister */
1420 rte_intr_disable(intr_handle);
1422 /* register callback func to eal lib */
1423 rte_intr_callback_unregister(intr_handle,
1424 i40e_dev_interrupt_handler, dev);
1426 i40e_rm_ethtype_filter_list(pf);
1427 i40e_rm_tunnel_filter_list(pf);
1428 i40e_rm_fdir_filter_list(pf);
1430 /* Remove all flows */
1431 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1432 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1440 i40e_dev_configure(struct rte_eth_dev *dev)
1442 struct i40e_adapter *ad =
1443 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1444 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1445 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1448 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1449 * bulk allocation or vector Rx preconditions we will reset it.
1451 ad->rx_bulk_alloc_allowed = true;
1452 ad->rx_vec_allowed = true;
1453 ad->tx_simple_allowed = true;
1454 ad->tx_vec_allowed = true;
1456 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1457 ret = i40e_fdir_setup(pf);
1458 if (ret != I40E_SUCCESS) {
1459 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1462 ret = i40e_fdir_configure(dev);
1464 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1468 i40e_fdir_teardown(pf);
1470 ret = i40e_dev_init_vlan(dev);
1475 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1476 * RSS setting have different requirements.
1477 * General PMD driver call sequence are NIC init, configure,
1478 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1479 * will try to lookup the VSI that specific queue belongs to if VMDQ
1480 * applicable. So, VMDQ setting has to be done before
1481 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1482 * For RSS setting, it will try to calculate actual configured RX queue
1483 * number, which will be available after rx_queue_setup(). dev_start()
1484 * function is good to place RSS setup.
1486 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1487 ret = i40e_vmdq_setup(dev);
1492 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1493 ret = i40e_dcb_setup(dev);
1495 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1500 TAILQ_INIT(&pf->flow_list);
1505 /* need to release vmdq resource if exists */
1506 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1507 i40e_vsi_release(pf->vmdq[i].vsi);
1508 pf->vmdq[i].vsi = NULL;
1513 /* need to release fdir resource if exists */
1514 i40e_fdir_teardown(pf);
1519 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1521 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1522 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1523 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1524 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1525 uint16_t msix_vect = vsi->msix_intr;
1528 for (i = 0; i < vsi->nb_qps; i++) {
1529 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1530 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1534 if (vsi->type != I40E_VSI_SRIOV) {
1535 if (!rte_intr_allow_others(intr_handle)) {
1536 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1537 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1539 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1542 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1543 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1545 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1550 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1551 vsi->user_param + (msix_vect - 1);
1553 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1554 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1556 I40E_WRITE_FLUSH(hw);
1560 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1561 int base_queue, int nb_queue)
1565 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1567 /* Bind all RX queues to allocated MSIX interrupt */
1568 for (i = 0; i < nb_queue; i++) {
1569 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1570 I40E_QINT_RQCTL_ITR_INDX_MASK |
1571 ((base_queue + i + 1) <<
1572 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1573 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1574 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1576 if (i == nb_queue - 1)
1577 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1578 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1581 /* Write first RX queue to Link list register as the head element */
1582 if (vsi->type != I40E_VSI_SRIOV) {
1584 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1586 if (msix_vect == I40E_MISC_VEC_ID) {
1587 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1589 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1591 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1593 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1596 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1598 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1600 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1602 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1609 if (msix_vect == I40E_MISC_VEC_ID) {
1611 I40E_VPINT_LNKLST0(vsi->user_param),
1613 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1615 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1617 /* num_msix_vectors_vf needs to minus irq0 */
1618 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1619 vsi->user_param + (msix_vect - 1);
1621 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1623 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1625 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1629 I40E_WRITE_FLUSH(hw);
1633 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1635 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1636 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1637 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1638 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1639 uint16_t msix_vect = vsi->msix_intr;
1640 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1641 uint16_t queue_idx = 0;
1646 for (i = 0; i < vsi->nb_qps; i++) {
1647 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1648 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1651 /* INTENA flag is not auto-cleared for interrupt */
1652 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1653 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1654 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1655 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1656 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1658 /* VF bind interrupt */
1659 if (vsi->type == I40E_VSI_SRIOV) {
1660 __vsi_queues_bind_intr(vsi, msix_vect,
1661 vsi->base_queue, vsi->nb_qps);
1665 /* PF & VMDq bind interrupt */
1666 if (rte_intr_dp_is_en(intr_handle)) {
1667 if (vsi->type == I40E_VSI_MAIN) {
1670 } else if (vsi->type == I40E_VSI_VMDQ2) {
1671 struct i40e_vsi *main_vsi =
1672 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1673 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1678 for (i = 0; i < vsi->nb_used_qps; i++) {
1680 if (!rte_intr_allow_others(intr_handle))
1681 /* allow to share MISC_VEC_ID */
1682 msix_vect = I40E_MISC_VEC_ID;
1684 /* no enough msix_vect, map all to one */
1685 __vsi_queues_bind_intr(vsi, msix_vect,
1686 vsi->base_queue + i,
1687 vsi->nb_used_qps - i);
1688 for (; !!record && i < vsi->nb_used_qps; i++)
1689 intr_handle->intr_vec[queue_idx + i] =
1693 /* 1:1 queue/msix_vect mapping */
1694 __vsi_queues_bind_intr(vsi, msix_vect,
1695 vsi->base_queue + i, 1);
1697 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1705 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1707 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1708 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1709 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1710 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1711 uint16_t interval = i40e_calc_itr_interval(\
1712 RTE_LIBRTE_I40E_ITR_INTERVAL);
1713 uint16_t msix_intr, i;
1715 if (rte_intr_allow_others(intr_handle))
1716 for (i = 0; i < vsi->nb_msix; i++) {
1717 msix_intr = vsi->msix_intr + i;
1718 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1719 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1720 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1721 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1723 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1726 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1727 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1728 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1729 (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1731 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1733 I40E_WRITE_FLUSH(hw);
1737 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1739 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1740 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1741 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1742 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1743 uint16_t msix_intr, i;
1745 if (rte_intr_allow_others(intr_handle))
1746 for (i = 0; i < vsi->nb_msix; i++) {
1747 msix_intr = vsi->msix_intr + i;
1748 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1752 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1754 I40E_WRITE_FLUSH(hw);
1757 static inline uint8_t
1758 i40e_parse_link_speeds(uint16_t link_speeds)
1760 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1762 if (link_speeds & ETH_LINK_SPEED_40G)
1763 link_speed |= I40E_LINK_SPEED_40GB;
1764 if (link_speeds & ETH_LINK_SPEED_25G)
1765 link_speed |= I40E_LINK_SPEED_25GB;
1766 if (link_speeds & ETH_LINK_SPEED_20G)
1767 link_speed |= I40E_LINK_SPEED_20GB;
1768 if (link_speeds & ETH_LINK_SPEED_10G)
1769 link_speed |= I40E_LINK_SPEED_10GB;
1770 if (link_speeds & ETH_LINK_SPEED_1G)
1771 link_speed |= I40E_LINK_SPEED_1GB;
1772 if (link_speeds & ETH_LINK_SPEED_100M)
1773 link_speed |= I40E_LINK_SPEED_100MB;
1779 i40e_phy_conf_link(struct i40e_hw *hw,
1781 uint8_t force_speed)
1783 enum i40e_status_code status;
1784 struct i40e_aq_get_phy_abilities_resp phy_ab;
1785 struct i40e_aq_set_phy_config phy_conf;
1786 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1787 I40E_AQ_PHY_FLAG_PAUSE_RX |
1788 I40E_AQ_PHY_FLAG_PAUSE_RX |
1789 I40E_AQ_PHY_FLAG_LOW_POWER;
1790 const uint8_t advt = I40E_LINK_SPEED_40GB |
1791 I40E_LINK_SPEED_25GB |
1792 I40E_LINK_SPEED_10GB |
1793 I40E_LINK_SPEED_1GB |
1794 I40E_LINK_SPEED_100MB;
1798 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1803 memset(&phy_conf, 0, sizeof(phy_conf));
1805 /* bits 0-2 use the values from get_phy_abilities_resp */
1807 abilities |= phy_ab.abilities & mask;
1809 /* update ablities and speed */
1810 if (abilities & I40E_AQ_PHY_AN_ENABLED)
1811 phy_conf.link_speed = advt;
1813 phy_conf.link_speed = force_speed;
1815 phy_conf.abilities = abilities;
1817 /* use get_phy_abilities_resp value for the rest */
1818 phy_conf.phy_type = phy_ab.phy_type;
1819 phy_conf.phy_type_ext = phy_ab.phy_type_ext;
1820 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1821 phy_conf.eee_capability = phy_ab.eee_capability;
1822 phy_conf.eeer = phy_ab.eeer_val;
1823 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1825 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1826 phy_ab.abilities, phy_ab.link_speed);
1827 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
1828 phy_conf.abilities, phy_conf.link_speed);
1830 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1834 return I40E_SUCCESS;
1838 i40e_apply_link_speed(struct rte_eth_dev *dev)
1841 uint8_t abilities = 0;
1842 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1843 struct rte_eth_conf *conf = &dev->data->dev_conf;
1845 speed = i40e_parse_link_speeds(conf->link_speeds);
1846 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1847 if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1848 abilities |= I40E_AQ_PHY_AN_ENABLED;
1849 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1851 /* Skip changing speed on 40G interfaces, FW does not support */
1852 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1853 speed = I40E_LINK_SPEED_UNKNOWN;
1854 abilities |= I40E_AQ_PHY_AN_ENABLED;
1857 return i40e_phy_conf_link(hw, abilities, speed);
1861 i40e_dev_start(struct rte_eth_dev *dev)
1863 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1864 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1865 struct i40e_vsi *main_vsi = pf->main_vsi;
1867 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1868 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1869 uint32_t intr_vector = 0;
1871 hw->adapter_stopped = 0;
1873 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1874 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1875 dev->data->port_id);
1879 rte_intr_disable(intr_handle);
1881 if ((rte_intr_cap_multiple(intr_handle) ||
1882 !RTE_ETH_DEV_SRIOV(dev).active) &&
1883 dev->data->dev_conf.intr_conf.rxq != 0) {
1884 intr_vector = dev->data->nb_rx_queues;
1885 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1890 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1891 intr_handle->intr_vec =
1892 rte_zmalloc("intr_vec",
1893 dev->data->nb_rx_queues * sizeof(int),
1895 if (!intr_handle->intr_vec) {
1897 "Failed to allocate %d rx_queues intr_vec\n",
1898 dev->data->nb_rx_queues);
1903 /* Initialize VSI */
1904 ret = i40e_dev_rxtx_init(pf);
1905 if (ret != I40E_SUCCESS) {
1906 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1910 /* Map queues with MSIX interrupt */
1911 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1912 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1913 i40e_vsi_queues_bind_intr(main_vsi);
1914 i40e_vsi_enable_queues_intr(main_vsi);
1916 /* Map VMDQ VSI queues with MSIX interrupt */
1917 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1918 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1919 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1920 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1923 /* enable FDIR MSIX interrupt */
1924 if (pf->fdir.fdir_vsi) {
1925 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1926 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1929 /* Enable all queues which have been configured */
1930 ret = i40e_dev_switch_queues(pf, TRUE);
1931 if (ret != I40E_SUCCESS) {
1932 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1936 /* Enable receiving broadcast packets */
1937 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1938 if (ret != I40E_SUCCESS)
1939 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1941 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1942 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1944 if (ret != I40E_SUCCESS)
1945 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1948 /* Apply link configure */
1949 if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1950 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1951 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1952 ETH_LINK_SPEED_40G)) {
1953 PMD_DRV_LOG(ERR, "Invalid link setting");
1956 ret = i40e_apply_link_speed(dev);
1957 if (I40E_SUCCESS != ret) {
1958 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1962 if (!rte_intr_allow_others(intr_handle)) {
1963 rte_intr_callback_unregister(intr_handle,
1964 i40e_dev_interrupt_handler,
1966 /* configure and enable device interrupt */
1967 i40e_pf_config_irq0(hw, FALSE);
1968 i40e_pf_enable_irq0(hw);
1970 if (dev->data->dev_conf.intr_conf.lsc != 0)
1972 "lsc won't enable because of no intr multiplex\n");
1973 } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
1974 ret = i40e_aq_set_phy_int_mask(hw,
1975 ~(I40E_AQ_EVENT_LINK_UPDOWN |
1976 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
1977 I40E_AQ_EVENT_MEDIA_NA), NULL);
1978 if (ret != I40E_SUCCESS)
1979 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
1981 /* Call get_link_info aq commond to enable LSE */
1982 i40e_dev_link_update(dev, 0);
1985 /* enable uio intr after callback register */
1986 rte_intr_enable(intr_handle);
1988 i40e_filter_restore(pf);
1990 return I40E_SUCCESS;
1993 i40e_dev_switch_queues(pf, FALSE);
1994 i40e_dev_clear_queues(dev);
2000 i40e_dev_stop(struct rte_eth_dev *dev)
2002 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2003 struct i40e_vsi *main_vsi = pf->main_vsi;
2004 struct i40e_mirror_rule *p_mirror;
2005 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2006 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2009 /* Disable all queues */
2010 i40e_dev_switch_queues(pf, FALSE);
2012 /* un-map queues with interrupt registers */
2013 i40e_vsi_disable_queues_intr(main_vsi);
2014 i40e_vsi_queues_unbind_intr(main_vsi);
2016 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2017 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2018 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2021 if (pf->fdir.fdir_vsi) {
2022 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2023 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2025 /* Clear all queues and release memory */
2026 i40e_dev_clear_queues(dev);
2029 i40e_dev_set_link_down(dev);
2031 /* Remove all mirror rules */
2032 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2033 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2036 pf->nb_mirror_rule = 0;
2038 if (!rte_intr_allow_others(intr_handle))
2039 /* resume to the default handler */
2040 rte_intr_callback_register(intr_handle,
2041 i40e_dev_interrupt_handler,
2044 /* Clean datapath event and queue/vec mapping */
2045 rte_intr_efd_disable(intr_handle);
2046 if (intr_handle->intr_vec) {
2047 rte_free(intr_handle->intr_vec);
2048 intr_handle->intr_vec = NULL;
2053 i40e_dev_close(struct rte_eth_dev *dev)
2055 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2056 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2057 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2058 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2062 PMD_INIT_FUNC_TRACE();
2065 hw->adapter_stopped = 1;
2066 i40e_dev_free_queues(dev);
2068 /* Disable interrupt */
2069 i40e_pf_disable_irq0(hw);
2070 rte_intr_disable(intr_handle);
2072 /* shutdown and destroy the HMC */
2073 i40e_shutdown_lan_hmc(hw);
2075 /* release all the existing VSIs and VEBs */
2076 i40e_fdir_teardown(pf);
2077 i40e_vsi_release(pf->main_vsi);
2079 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2080 i40e_vsi_release(pf->vmdq[i].vsi);
2081 pf->vmdq[i].vsi = NULL;
2087 /* shutdown the adminq */
2088 i40e_aq_queue_shutdown(hw, true);
2089 i40e_shutdown_adminq(hw);
2091 i40e_res_pool_destroy(&pf->qp_pool);
2092 i40e_res_pool_destroy(&pf->msix_pool);
2094 /* force a PF reset to clean anything leftover */
2095 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2096 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2097 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2098 I40E_WRITE_FLUSH(hw);
2102 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2104 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2105 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2106 struct i40e_vsi *vsi = pf->main_vsi;
2109 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2111 if (status != I40E_SUCCESS)
2112 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2114 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2116 if (status != I40E_SUCCESS)
2117 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2122 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2124 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2125 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2126 struct i40e_vsi *vsi = pf->main_vsi;
2129 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2131 if (status != I40E_SUCCESS)
2132 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2134 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2136 if (status != I40E_SUCCESS)
2137 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2141 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2143 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2144 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2145 struct i40e_vsi *vsi = pf->main_vsi;
2148 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2149 if (ret != I40E_SUCCESS)
2150 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2154 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2156 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2157 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2158 struct i40e_vsi *vsi = pf->main_vsi;
2161 if (dev->data->promiscuous == 1)
2162 return; /* must remain in all_multicast mode */
2164 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2165 vsi->seid, FALSE, NULL);
2166 if (ret != I40E_SUCCESS)
2167 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2171 * Set device link up.
2174 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2176 /* re-apply link speed setting */
2177 return i40e_apply_link_speed(dev);
2181 * Set device link down.
2184 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2186 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2187 uint8_t abilities = 0;
2188 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2190 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2191 return i40e_phy_conf_link(hw, abilities, speed);
2195 i40e_dev_link_update(struct rte_eth_dev *dev,
2196 int wait_to_complete)
2198 #define CHECK_INTERVAL 100 /* 100ms */
2199 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2200 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2201 struct i40e_link_status link_status;
2202 struct rte_eth_link link, old;
2204 unsigned rep_cnt = MAX_REPEAT_TIME;
2205 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2207 memset(&link, 0, sizeof(link));
2208 memset(&old, 0, sizeof(old));
2209 memset(&link_status, 0, sizeof(link_status));
2210 rte_i40e_dev_atomic_read_link_status(dev, &old);
2213 /* Get link status information from hardware */
2214 status = i40e_aq_get_link_info(hw, enable_lse,
2215 &link_status, NULL);
2216 if (status != I40E_SUCCESS) {
2217 link.link_speed = ETH_SPEED_NUM_100M;
2218 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2219 PMD_DRV_LOG(ERR, "Failed to get link info");
2223 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2224 if (!wait_to_complete)
2227 rte_delay_ms(CHECK_INTERVAL);
2228 } while (!link.link_status && rep_cnt--);
2230 if (!link.link_status)
2233 /* i40e uses full duplex only */
2234 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2236 /* Parse the link status */
2237 switch (link_status.link_speed) {
2238 case I40E_LINK_SPEED_100MB:
2239 link.link_speed = ETH_SPEED_NUM_100M;
2241 case I40E_LINK_SPEED_1GB:
2242 link.link_speed = ETH_SPEED_NUM_1G;
2244 case I40E_LINK_SPEED_10GB:
2245 link.link_speed = ETH_SPEED_NUM_10G;
2247 case I40E_LINK_SPEED_20GB:
2248 link.link_speed = ETH_SPEED_NUM_20G;
2250 case I40E_LINK_SPEED_25GB:
2251 link.link_speed = ETH_SPEED_NUM_25G;
2253 case I40E_LINK_SPEED_40GB:
2254 link.link_speed = ETH_SPEED_NUM_40G;
2257 link.link_speed = ETH_SPEED_NUM_100M;
2261 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2262 ETH_LINK_SPEED_FIXED);
2265 rte_i40e_dev_atomic_write_link_status(dev, &link);
2266 if (link.link_status == old.link_status)
2272 /* Get all the statistics of a VSI */
2274 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2276 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2277 struct i40e_eth_stats *nes = &vsi->eth_stats;
2278 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2279 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2281 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2282 vsi->offset_loaded, &oes->rx_bytes,
2284 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2285 vsi->offset_loaded, &oes->rx_unicast,
2287 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2288 vsi->offset_loaded, &oes->rx_multicast,
2289 &nes->rx_multicast);
2290 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2291 vsi->offset_loaded, &oes->rx_broadcast,
2292 &nes->rx_broadcast);
2293 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2294 &oes->rx_discards, &nes->rx_discards);
2295 /* GLV_REPC not supported */
2296 /* GLV_RMPC not supported */
2297 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2298 &oes->rx_unknown_protocol,
2299 &nes->rx_unknown_protocol);
2300 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2301 vsi->offset_loaded, &oes->tx_bytes,
2303 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2304 vsi->offset_loaded, &oes->tx_unicast,
2306 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2307 vsi->offset_loaded, &oes->tx_multicast,
2308 &nes->tx_multicast);
2309 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2310 vsi->offset_loaded, &oes->tx_broadcast,
2311 &nes->tx_broadcast);
2312 /* GLV_TDPC not supported */
2313 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2314 &oes->tx_errors, &nes->tx_errors);
2315 vsi->offset_loaded = true;
2317 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2319 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2320 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2321 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2322 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2323 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2324 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2325 nes->rx_unknown_protocol);
2326 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2327 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2328 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2329 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2330 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2331 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2332 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2337 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2340 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2341 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2343 /* Get statistics of struct i40e_eth_stats */
2344 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2345 I40E_GLPRT_GORCL(hw->port),
2346 pf->offset_loaded, &os->eth.rx_bytes,
2348 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2349 I40E_GLPRT_UPRCL(hw->port),
2350 pf->offset_loaded, &os->eth.rx_unicast,
2351 &ns->eth.rx_unicast);
2352 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2353 I40E_GLPRT_MPRCL(hw->port),
2354 pf->offset_loaded, &os->eth.rx_multicast,
2355 &ns->eth.rx_multicast);
2356 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2357 I40E_GLPRT_BPRCL(hw->port),
2358 pf->offset_loaded, &os->eth.rx_broadcast,
2359 &ns->eth.rx_broadcast);
2360 /* Workaround: CRC size should not be included in byte statistics,
2361 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2363 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2364 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2366 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2367 pf->offset_loaded, &os->eth.rx_discards,
2368 &ns->eth.rx_discards);
2369 /* GLPRT_REPC not supported */
2370 /* GLPRT_RMPC not supported */
2371 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2373 &os->eth.rx_unknown_protocol,
2374 &ns->eth.rx_unknown_protocol);
2375 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2376 I40E_GLPRT_GOTCL(hw->port),
2377 pf->offset_loaded, &os->eth.tx_bytes,
2379 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2380 I40E_GLPRT_UPTCL(hw->port),
2381 pf->offset_loaded, &os->eth.tx_unicast,
2382 &ns->eth.tx_unicast);
2383 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2384 I40E_GLPRT_MPTCL(hw->port),
2385 pf->offset_loaded, &os->eth.tx_multicast,
2386 &ns->eth.tx_multicast);
2387 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2388 I40E_GLPRT_BPTCL(hw->port),
2389 pf->offset_loaded, &os->eth.tx_broadcast,
2390 &ns->eth.tx_broadcast);
2391 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2392 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2393 /* GLPRT_TEPC not supported */
2395 /* additional port specific stats */
2396 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2397 pf->offset_loaded, &os->tx_dropped_link_down,
2398 &ns->tx_dropped_link_down);
2399 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2400 pf->offset_loaded, &os->crc_errors,
2402 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2403 pf->offset_loaded, &os->illegal_bytes,
2404 &ns->illegal_bytes);
2405 /* GLPRT_ERRBC not supported */
2406 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2407 pf->offset_loaded, &os->mac_local_faults,
2408 &ns->mac_local_faults);
2409 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2410 pf->offset_loaded, &os->mac_remote_faults,
2411 &ns->mac_remote_faults);
2412 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2413 pf->offset_loaded, &os->rx_length_errors,
2414 &ns->rx_length_errors);
2415 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2416 pf->offset_loaded, &os->link_xon_rx,
2418 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2419 pf->offset_loaded, &os->link_xoff_rx,
2421 for (i = 0; i < 8; i++) {
2422 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2424 &os->priority_xon_rx[i],
2425 &ns->priority_xon_rx[i]);
2426 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2428 &os->priority_xoff_rx[i],
2429 &ns->priority_xoff_rx[i]);
2431 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2432 pf->offset_loaded, &os->link_xon_tx,
2434 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2435 pf->offset_loaded, &os->link_xoff_tx,
2437 for (i = 0; i < 8; i++) {
2438 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2440 &os->priority_xon_tx[i],
2441 &ns->priority_xon_tx[i]);
2442 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2444 &os->priority_xoff_tx[i],
2445 &ns->priority_xoff_tx[i]);
2446 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2448 &os->priority_xon_2_xoff[i],
2449 &ns->priority_xon_2_xoff[i]);
2451 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2452 I40E_GLPRT_PRC64L(hw->port),
2453 pf->offset_loaded, &os->rx_size_64,
2455 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2456 I40E_GLPRT_PRC127L(hw->port),
2457 pf->offset_loaded, &os->rx_size_127,
2459 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2460 I40E_GLPRT_PRC255L(hw->port),
2461 pf->offset_loaded, &os->rx_size_255,
2463 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2464 I40E_GLPRT_PRC511L(hw->port),
2465 pf->offset_loaded, &os->rx_size_511,
2467 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2468 I40E_GLPRT_PRC1023L(hw->port),
2469 pf->offset_loaded, &os->rx_size_1023,
2471 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2472 I40E_GLPRT_PRC1522L(hw->port),
2473 pf->offset_loaded, &os->rx_size_1522,
2475 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2476 I40E_GLPRT_PRC9522L(hw->port),
2477 pf->offset_loaded, &os->rx_size_big,
2479 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2480 pf->offset_loaded, &os->rx_undersize,
2482 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2483 pf->offset_loaded, &os->rx_fragments,
2485 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2486 pf->offset_loaded, &os->rx_oversize,
2488 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2489 pf->offset_loaded, &os->rx_jabber,
2491 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2492 I40E_GLPRT_PTC64L(hw->port),
2493 pf->offset_loaded, &os->tx_size_64,
2495 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2496 I40E_GLPRT_PTC127L(hw->port),
2497 pf->offset_loaded, &os->tx_size_127,
2499 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2500 I40E_GLPRT_PTC255L(hw->port),
2501 pf->offset_loaded, &os->tx_size_255,
2503 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2504 I40E_GLPRT_PTC511L(hw->port),
2505 pf->offset_loaded, &os->tx_size_511,
2507 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2508 I40E_GLPRT_PTC1023L(hw->port),
2509 pf->offset_loaded, &os->tx_size_1023,
2511 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2512 I40E_GLPRT_PTC1522L(hw->port),
2513 pf->offset_loaded, &os->tx_size_1522,
2515 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2516 I40E_GLPRT_PTC9522L(hw->port),
2517 pf->offset_loaded, &os->tx_size_big,
2519 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2521 &os->fd_sb_match, &ns->fd_sb_match);
2522 /* GLPRT_MSPDC not supported */
2523 /* GLPRT_XEC not supported */
2525 pf->offset_loaded = true;
2528 i40e_update_vsi_stats(pf->main_vsi);
2531 /* Get all statistics of a port */
2533 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2535 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2536 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2537 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2540 /* call read registers - updates values, now write them to struct */
2541 i40e_read_stats_registers(pf, hw);
2543 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2544 pf->main_vsi->eth_stats.rx_multicast +
2545 pf->main_vsi->eth_stats.rx_broadcast -
2546 pf->main_vsi->eth_stats.rx_discards;
2547 stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2548 pf->main_vsi->eth_stats.tx_multicast +
2549 pf->main_vsi->eth_stats.tx_broadcast;
2550 stats->ibytes = ns->eth.rx_bytes;
2551 stats->obytes = ns->eth.tx_bytes;
2552 stats->oerrors = ns->eth.tx_errors +
2553 pf->main_vsi->eth_stats.tx_errors;
2556 stats->imissed = ns->eth.rx_discards +
2557 pf->main_vsi->eth_stats.rx_discards;
2558 stats->ierrors = ns->crc_errors +
2559 ns->rx_length_errors + ns->rx_undersize +
2560 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2562 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2563 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
2564 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
2565 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
2566 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
2567 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
2568 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2569 ns->eth.rx_unknown_protocol);
2570 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
2571 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
2572 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
2573 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
2574 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
2575 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
2577 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
2578 ns->tx_dropped_link_down);
2579 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
2580 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
2582 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
2583 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
2584 ns->mac_local_faults);
2585 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
2586 ns->mac_remote_faults);
2587 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
2588 ns->rx_length_errors);
2589 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
2590 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
2591 for (i = 0; i < 8; i++) {
2592 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
2593 i, ns->priority_xon_rx[i]);
2594 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
2595 i, ns->priority_xoff_rx[i]);
2597 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
2598 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
2599 for (i = 0; i < 8; i++) {
2600 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
2601 i, ns->priority_xon_tx[i]);
2602 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
2603 i, ns->priority_xoff_tx[i]);
2604 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
2605 i, ns->priority_xon_2_xoff[i]);
2607 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
2608 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
2609 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
2610 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
2611 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
2612 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
2613 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
2614 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
2615 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
2616 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
2617 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
2618 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
2619 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
2620 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
2621 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
2622 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
2623 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
2624 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
2625 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2626 ns->mac_short_packet_dropped);
2627 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
2628 ns->checksum_error);
2629 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
2630 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2633 /* Reset the statistics */
2635 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2637 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2638 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2640 /* Mark PF and VSI stats to update the offset, aka "reset" */
2641 pf->offset_loaded = false;
2643 pf->main_vsi->offset_loaded = false;
2645 /* read the stats, reading current register values into offset */
2646 i40e_read_stats_registers(pf, hw);
2650 i40e_xstats_calc_num(void)
2652 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2653 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2654 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2657 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2658 struct rte_eth_xstat_name *xstats_names,
2659 __rte_unused unsigned limit)
2664 if (xstats_names == NULL)
2665 return i40e_xstats_calc_num();
2667 /* Note: limit checked in rte_eth_xstats_names() */
2669 /* Get stats from i40e_eth_stats struct */
2670 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2671 snprintf(xstats_names[count].name,
2672 sizeof(xstats_names[count].name),
2673 "%s", rte_i40e_stats_strings[i].name);
2677 /* Get individiual stats from i40e_hw_port struct */
2678 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2679 snprintf(xstats_names[count].name,
2680 sizeof(xstats_names[count].name),
2681 "%s", rte_i40e_hw_port_strings[i].name);
2685 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2686 for (prio = 0; prio < 8; prio++) {
2687 snprintf(xstats_names[count].name,
2688 sizeof(xstats_names[count].name),
2689 "rx_priority%u_%s", prio,
2690 rte_i40e_rxq_prio_strings[i].name);
2695 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2696 for (prio = 0; prio < 8; prio++) {
2697 snprintf(xstats_names[count].name,
2698 sizeof(xstats_names[count].name),
2699 "tx_priority%u_%s", prio,
2700 rte_i40e_txq_prio_strings[i].name);
2708 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2711 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2712 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2713 unsigned i, count, prio;
2714 struct i40e_hw_port_stats *hw_stats = &pf->stats;
2716 count = i40e_xstats_calc_num();
2720 i40e_read_stats_registers(pf, hw);
2727 /* Get stats from i40e_eth_stats struct */
2728 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2729 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2730 rte_i40e_stats_strings[i].offset);
2731 xstats[count].id = count;
2735 /* Get individiual stats from i40e_hw_port struct */
2736 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2737 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2738 rte_i40e_hw_port_strings[i].offset);
2739 xstats[count].id = count;
2743 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2744 for (prio = 0; prio < 8; prio++) {
2745 xstats[count].value =
2746 *(uint64_t *)(((char *)hw_stats) +
2747 rte_i40e_rxq_prio_strings[i].offset +
2748 (sizeof(uint64_t) * prio));
2749 xstats[count].id = count;
2754 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2755 for (prio = 0; prio < 8; prio++) {
2756 xstats[count].value =
2757 *(uint64_t *)(((char *)hw_stats) +
2758 rte_i40e_txq_prio_strings[i].offset +
2759 (sizeof(uint64_t) * prio));
2760 xstats[count].id = count;
2769 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2770 __rte_unused uint16_t queue_id,
2771 __rte_unused uint8_t stat_idx,
2772 __rte_unused uint8_t is_rx)
2774 PMD_INIT_FUNC_TRACE();
2780 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2782 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2788 full_ver = hw->nvm.oem_ver;
2789 ver = (u8)(full_ver >> 24);
2790 build = (u16)((full_ver >> 8) & 0xffff);
2791 patch = (u8)(full_ver & 0xff);
2793 ret = snprintf(fw_version, fw_size,
2794 "%d.%d%d 0x%08x %d.%d.%d",
2795 ((hw->nvm.version >> 12) & 0xf),
2796 ((hw->nvm.version >> 4) & 0xff),
2797 (hw->nvm.version & 0xf), hw->nvm.eetrack,
2800 ret += 1; /* add the size of '\0' */
2801 if (fw_size < (u32)ret)
2808 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2810 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2811 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2812 struct i40e_vsi *vsi = pf->main_vsi;
2813 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2815 dev_info->pci_dev = pci_dev;
2816 dev_info->max_rx_queues = vsi->nb_qps;
2817 dev_info->max_tx_queues = vsi->nb_qps;
2818 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2819 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2820 dev_info->max_mac_addrs = vsi->max_macaddrs;
2821 dev_info->max_vfs = pci_dev->max_vfs;
2822 dev_info->rx_offload_capa =
2823 DEV_RX_OFFLOAD_VLAN_STRIP |
2824 DEV_RX_OFFLOAD_QINQ_STRIP |
2825 DEV_RX_OFFLOAD_IPV4_CKSUM |
2826 DEV_RX_OFFLOAD_UDP_CKSUM |
2827 DEV_RX_OFFLOAD_TCP_CKSUM;
2828 dev_info->tx_offload_capa =
2829 DEV_TX_OFFLOAD_VLAN_INSERT |
2830 DEV_TX_OFFLOAD_QINQ_INSERT |
2831 DEV_TX_OFFLOAD_IPV4_CKSUM |
2832 DEV_TX_OFFLOAD_UDP_CKSUM |
2833 DEV_TX_OFFLOAD_TCP_CKSUM |
2834 DEV_TX_OFFLOAD_SCTP_CKSUM |
2835 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2836 DEV_TX_OFFLOAD_TCP_TSO |
2837 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2838 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2839 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2840 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2841 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2843 dev_info->reta_size = pf->hash_lut_size;
2844 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2846 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2848 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2849 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2850 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2852 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2856 dev_info->default_txconf = (struct rte_eth_txconf) {
2858 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2859 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2860 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2862 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2863 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2864 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2865 ETH_TXQ_FLAGS_NOOFFLOADS,
2868 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2869 .nb_max = I40E_MAX_RING_DESC,
2870 .nb_min = I40E_MIN_RING_DESC,
2871 .nb_align = I40E_ALIGN_RING_DESC,
2874 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2875 .nb_max = I40E_MAX_RING_DESC,
2876 .nb_min = I40E_MIN_RING_DESC,
2877 .nb_align = I40E_ALIGN_RING_DESC,
2878 .nb_seg_max = I40E_TX_MAX_SEG,
2879 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
2882 if (pf->flags & I40E_FLAG_VMDQ) {
2883 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2884 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2885 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2886 pf->max_nb_vmdq_vsi;
2887 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2888 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2889 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2892 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2894 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2895 else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2897 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2900 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2904 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2906 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2907 struct i40e_vsi *vsi = pf->main_vsi;
2908 PMD_INIT_FUNC_TRACE();
2911 return i40e_vsi_add_vlan(vsi, vlan_id);
2913 return i40e_vsi_delete_vlan(vsi, vlan_id);
2917 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2918 enum rte_vlan_type vlan_type,
2921 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2922 uint64_t reg_r = 0, reg_w = 0;
2923 uint16_t reg_id = 0;
2925 int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2927 switch (vlan_type) {
2928 case ETH_VLAN_TYPE_OUTER:
2934 case ETH_VLAN_TYPE_INNER:
2940 "Unsupported vlan type in single vlan.\n");
2946 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2949 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2951 if (ret != I40E_SUCCESS) {
2953 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
2959 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
2962 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2963 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2964 if (reg_r == reg_w) {
2966 PMD_DRV_LOG(DEBUG, "No need to write");
2970 ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2972 if (ret != I40E_SUCCESS) {
2975 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
2980 "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
2987 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2989 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2990 struct i40e_vsi *vsi = pf->main_vsi;
2992 if (mask & ETH_VLAN_FILTER_MASK) {
2993 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2994 i40e_vsi_config_vlan_filter(vsi, TRUE);
2996 i40e_vsi_config_vlan_filter(vsi, FALSE);
2999 if (mask & ETH_VLAN_STRIP_MASK) {
3000 /* Enable or disable VLAN stripping */
3001 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3002 i40e_vsi_config_vlan_stripping(vsi, TRUE);
3004 i40e_vsi_config_vlan_stripping(vsi, FALSE);
3007 if (mask & ETH_VLAN_EXTEND_MASK) {
3008 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3009 i40e_vsi_config_double_vlan(vsi, TRUE);
3010 /* Set global registers with default ether type value */
3011 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3013 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3017 i40e_vsi_config_double_vlan(vsi, FALSE);
3022 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3023 __rte_unused uint16_t queue,
3024 __rte_unused int on)
3026 PMD_INIT_FUNC_TRACE();
3030 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3032 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3033 struct i40e_vsi *vsi = pf->main_vsi;
3034 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3035 struct i40e_vsi_vlan_pvid_info info;
3037 memset(&info, 0, sizeof(info));
3040 info.config.pvid = pvid;
3042 info.config.reject.tagged =
3043 data->dev_conf.txmode.hw_vlan_reject_tagged;
3044 info.config.reject.untagged =
3045 data->dev_conf.txmode.hw_vlan_reject_untagged;
3048 return i40e_vsi_vlan_pvid_set(vsi, &info);
3052 i40e_dev_led_on(struct rte_eth_dev *dev)
3054 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3055 uint32_t mode = i40e_led_get(hw);
3058 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3064 i40e_dev_led_off(struct rte_eth_dev *dev)
3066 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3067 uint32_t mode = i40e_led_get(hw);
3070 i40e_led_set(hw, 0, false);
3076 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3078 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3079 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3081 fc_conf->pause_time = pf->fc_conf.pause_time;
3082 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3083 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3085 /* Return current mode according to actual setting*/
3086 switch (hw->fc.current_mode) {
3088 fc_conf->mode = RTE_FC_FULL;
3090 case I40E_FC_TX_PAUSE:
3091 fc_conf->mode = RTE_FC_TX_PAUSE;
3093 case I40E_FC_RX_PAUSE:
3094 fc_conf->mode = RTE_FC_RX_PAUSE;
3098 fc_conf->mode = RTE_FC_NONE;
3105 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3107 uint32_t mflcn_reg, fctrl_reg, reg;
3108 uint32_t max_high_water;
3109 uint8_t i, aq_failure;
3113 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3114 [RTE_FC_NONE] = I40E_FC_NONE,
3115 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3116 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3117 [RTE_FC_FULL] = I40E_FC_FULL
3120 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3122 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3123 if ((fc_conf->high_water > max_high_water) ||
3124 (fc_conf->high_water < fc_conf->low_water)) {
3126 "Invalid high/low water setup value in KB, High_water must be <= %d.",
3131 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3132 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3133 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3135 pf->fc_conf.pause_time = fc_conf->pause_time;
3136 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3137 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3139 PMD_INIT_FUNC_TRACE();
3141 /* All the link flow control related enable/disable register
3142 * configuration is handle by the F/W
3144 err = i40e_set_fc(hw, &aq_failure, true);
3148 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3149 /* Configure flow control refresh threshold,
3150 * the value for stat_tx_pause_refresh_timer[8]
3151 * is used for global pause operation.
3155 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3156 pf->fc_conf.pause_time);
3158 /* configure the timer value included in transmitted pause
3160 * the value for stat_tx_pause_quanta[8] is used for global
3163 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3164 pf->fc_conf.pause_time);
3166 fctrl_reg = I40E_READ_REG(hw,
3167 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3169 if (fc_conf->mac_ctrl_frame_fwd != 0)
3170 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3172 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3174 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3177 /* Configure pause time (2 TCs per register) */
3178 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3179 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3180 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3182 /* Configure flow control refresh threshold value */
3183 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3184 pf->fc_conf.pause_time / 2);
3186 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3188 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3189 *depending on configuration
3191 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3192 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3193 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3195 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3196 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3199 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3202 /* config the water marker both based on the packets and bytes */
3203 I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3204 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3205 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3206 I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3207 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3208 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3209 I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3210 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3212 I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3213 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3216 I40E_WRITE_FLUSH(hw);
3222 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3223 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3225 PMD_INIT_FUNC_TRACE();
3230 /* Add a MAC address, and update filters */
3232 i40e_macaddr_add(struct rte_eth_dev *dev,
3233 struct ether_addr *mac_addr,
3234 __rte_unused uint32_t index,
3237 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3238 struct i40e_mac_filter_info mac_filter;
3239 struct i40e_vsi *vsi;
3242 /* If VMDQ not enabled or configured, return */
3243 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3244 !pf->nb_cfg_vmdq_vsi)) {
3245 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3246 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3251 if (pool > pf->nb_cfg_vmdq_vsi) {
3252 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3253 pool, pf->nb_cfg_vmdq_vsi);
3257 (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3258 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3259 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3261 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3266 vsi = pf->vmdq[pool - 1].vsi;
3268 ret = i40e_vsi_add_mac(vsi, &mac_filter);
3269 if (ret != I40E_SUCCESS) {
3270 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3275 /* Remove a MAC address, and update filters */
3277 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3279 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3280 struct i40e_vsi *vsi;
3281 struct rte_eth_dev_data *data = dev->data;
3282 struct ether_addr *macaddr;
3287 macaddr = &(data->mac_addrs[index]);
3289 pool_sel = dev->data->mac_pool_sel[index];
3291 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3292 if (pool_sel & (1ULL << i)) {
3296 /* No VMDQ pool enabled or configured */
3297 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3298 (i > pf->nb_cfg_vmdq_vsi)) {
3300 "No VMDQ pool enabled/configured");
3303 vsi = pf->vmdq[i - 1].vsi;
3305 ret = i40e_vsi_delete_mac(vsi, macaddr);
3308 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3315 /* Set perfect match or hash match of MAC and VLAN for a VF */
3317 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3318 struct rte_eth_mac_filter *filter,
3322 struct i40e_mac_filter_info mac_filter;
3323 struct ether_addr old_mac;
3324 struct ether_addr *new_mac;
3325 struct i40e_pf_vf *vf = NULL;
3330 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3333 hw = I40E_PF_TO_HW(pf);
3335 if (filter == NULL) {
3336 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3340 new_mac = &filter->mac_addr;
3342 if (is_zero_ether_addr(new_mac)) {
3343 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3347 vf_id = filter->dst_id;
3349 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3350 PMD_DRV_LOG(ERR, "Invalid argument.");
3353 vf = &pf->vfs[vf_id];
3355 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3356 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3361 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3362 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3364 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3367 mac_filter.filter_type = filter->filter_type;
3368 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3369 if (ret != I40E_SUCCESS) {
3370 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3373 ether_addr_copy(new_mac, &pf->dev_addr);
3375 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3377 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3378 if (ret != I40E_SUCCESS) {
3379 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3383 /* Clear device address as it has been removed */
3384 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3385 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3391 /* MAC filter handle */
3393 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3396 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3397 struct rte_eth_mac_filter *filter;
3398 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3399 int ret = I40E_NOT_SUPPORTED;
3401 filter = (struct rte_eth_mac_filter *)(arg);
3403 switch (filter_op) {
3404 case RTE_ETH_FILTER_NOP:
3407 case RTE_ETH_FILTER_ADD:
3408 i40e_pf_disable_irq0(hw);
3410 ret = i40e_vf_mac_filter_set(pf, filter, 1);
3411 i40e_pf_enable_irq0(hw);
3413 case RTE_ETH_FILTER_DELETE:
3414 i40e_pf_disable_irq0(hw);
3416 ret = i40e_vf_mac_filter_set(pf, filter, 0);
3417 i40e_pf_enable_irq0(hw);
3420 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3421 ret = I40E_ERR_PARAM;
3429 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3431 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3432 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3438 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3439 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3442 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3446 uint32_t *lut_dw = (uint32_t *)lut;
3447 uint16_t i, lut_size_dw = lut_size / 4;
3449 for (i = 0; i < lut_size_dw; i++)
3450 lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3457 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3466 pf = I40E_VSI_TO_PF(vsi);
3467 hw = I40E_VSI_TO_HW(vsi);
3469 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3470 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3473 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3477 uint32_t *lut_dw = (uint32_t *)lut;
3478 uint16_t i, lut_size_dw = lut_size / 4;
3480 for (i = 0; i < lut_size_dw; i++)
3481 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3482 I40E_WRITE_FLUSH(hw);
3489 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3490 struct rte_eth_rss_reta_entry64 *reta_conf,
3493 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3494 uint16_t i, lut_size = pf->hash_lut_size;
3495 uint16_t idx, shift;
3499 if (reta_size != lut_size ||
3500 reta_size > ETH_RSS_RETA_SIZE_512) {
3502 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)\n",
3503 reta_size, lut_size);
3507 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3509 PMD_DRV_LOG(ERR, "No memory can be allocated");
3512 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3515 for (i = 0; i < reta_size; i++) {
3516 idx = i / RTE_RETA_GROUP_SIZE;
3517 shift = i % RTE_RETA_GROUP_SIZE;
3518 if (reta_conf[idx].mask & (1ULL << shift))
3519 lut[i] = reta_conf[idx].reta[shift];
3521 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3530 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3531 struct rte_eth_rss_reta_entry64 *reta_conf,
3534 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3535 uint16_t i, lut_size = pf->hash_lut_size;
3536 uint16_t idx, shift;
3540 if (reta_size != lut_size ||
3541 reta_size > ETH_RSS_RETA_SIZE_512) {
3543 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)\n",
3544 reta_size, lut_size);
3548 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3550 PMD_DRV_LOG(ERR, "No memory can be allocated");
3554 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3557 for (i = 0; i < reta_size; i++) {
3558 idx = i / RTE_RETA_GROUP_SIZE;
3559 shift = i % RTE_RETA_GROUP_SIZE;
3560 if (reta_conf[idx].mask & (1ULL << shift))
3561 reta_conf[idx].reta[shift] = lut[i];
3571 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3572 * @hw: pointer to the HW structure
3573 * @mem: pointer to mem struct to fill out
3574 * @size: size of memory requested
3575 * @alignment: what to align the allocation to
3577 enum i40e_status_code
3578 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3579 struct i40e_dma_mem *mem,
3583 const struct rte_memzone *mz = NULL;
3584 char z_name[RTE_MEMZONE_NAMESIZE];
3587 return I40E_ERR_PARAM;
3589 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3590 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3591 alignment, RTE_PGSIZE_2M);
3593 return I40E_ERR_NO_MEMORY;
3597 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3598 mem->zone = (const void *)mz;
3600 "memzone %s allocated with physical address: %"PRIu64,
3603 return I40E_SUCCESS;
3607 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3608 * @hw: pointer to the HW structure
3609 * @mem: ptr to mem struct to free
3611 enum i40e_status_code
3612 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3613 struct i40e_dma_mem *mem)
3616 return I40E_ERR_PARAM;
3619 "memzone %s to be freed with physical address: %"PRIu64,
3620 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3621 rte_memzone_free((const struct rte_memzone *)mem->zone);
3626 return I40E_SUCCESS;
3630 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3631 * @hw: pointer to the HW structure
3632 * @mem: pointer to mem struct to fill out
3633 * @size: size of memory requested
3635 enum i40e_status_code
3636 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3637 struct i40e_virt_mem *mem,
3641 return I40E_ERR_PARAM;
3644 mem->va = rte_zmalloc("i40e", size, 0);
3647 return I40E_SUCCESS;
3649 return I40E_ERR_NO_MEMORY;
3653 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3654 * @hw: pointer to the HW structure
3655 * @mem: pointer to mem struct to free
3657 enum i40e_status_code
3658 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3659 struct i40e_virt_mem *mem)
3662 return I40E_ERR_PARAM;
3667 return I40E_SUCCESS;
3671 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3673 rte_spinlock_init(&sp->spinlock);
3677 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3679 rte_spinlock_lock(&sp->spinlock);
3683 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3685 rte_spinlock_unlock(&sp->spinlock);
3689 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3695 * Get the hardware capabilities, which will be parsed
3696 * and saved into struct i40e_hw.
3699 i40e_get_cap(struct i40e_hw *hw)
3701 struct i40e_aqc_list_capabilities_element_resp *buf;
3702 uint16_t len, size = 0;
3705 /* Calculate a huge enough buff for saving response data temporarily */
3706 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3707 I40E_MAX_CAP_ELE_NUM;
3708 buf = rte_zmalloc("i40e", len, 0);
3710 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3711 return I40E_ERR_NO_MEMORY;
3714 /* Get, parse the capabilities and save it to hw */
3715 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3716 i40e_aqc_opc_list_func_capabilities, NULL);
3717 if (ret != I40E_SUCCESS)
3718 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3720 /* Free the temporary buffer after being used */
3727 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3729 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3730 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3731 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
3732 uint16_t qp_count = 0, vsi_count = 0;
3734 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3735 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3738 /* Add the parameter init for LFC */
3739 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3740 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3741 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3743 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3744 pf->max_num_vsi = hw->func_caps.num_vsis;
3745 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3746 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3747 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3749 /* FDir queue/VSI allocation */
3750 pf->fdir_qp_offset = 0;
3751 if (hw->func_caps.fd) {
3752 pf->flags |= I40E_FLAG_FDIR;
3753 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3755 pf->fdir_nb_qps = 0;
3757 qp_count += pf->fdir_nb_qps;
3760 /* LAN queue/VSI allocation */
3761 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3762 if (!hw->func_caps.rss) {
3765 pf->flags |= I40E_FLAG_RSS;
3766 if (hw->mac.type == I40E_MAC_X722)
3767 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3768 pf->lan_nb_qps = pf->lan_nb_qp_max;
3770 qp_count += pf->lan_nb_qps;
3773 /* VF queue/VSI allocation */
3774 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3775 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3776 pf->flags |= I40E_FLAG_SRIOV;
3777 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3778 pf->vf_num = pci_dev->max_vfs;
3780 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
3781 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
3786 qp_count += pf->vf_nb_qps * pf->vf_num;
3787 vsi_count += pf->vf_num;
3789 /* VMDq queue/VSI allocation */
3790 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3791 pf->vmdq_nb_qps = 0;
3792 pf->max_nb_vmdq_vsi = 0;
3793 if (hw->func_caps.vmdq) {
3794 if (qp_count < hw->func_caps.num_tx_qp &&
3795 vsi_count < hw->func_caps.num_vsis) {
3796 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3797 qp_count) / pf->vmdq_nb_qp_max;
3799 /* Limit the maximum number of VMDq vsi to the maximum
3800 * ethdev can support
3802 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3803 hw->func_caps.num_vsis - vsi_count);
3804 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3806 if (pf->max_nb_vmdq_vsi) {
3807 pf->flags |= I40E_FLAG_VMDQ;
3808 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3810 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
3811 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
3812 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
3815 "No enough queues left for VMDq");
3818 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3821 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3822 vsi_count += pf->max_nb_vmdq_vsi;
3824 if (hw->func_caps.dcb)
3825 pf->flags |= I40E_FLAG_DCB;
3827 if (qp_count > hw->func_caps.num_tx_qp) {
3829 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
3830 qp_count, hw->func_caps.num_tx_qp);
3833 if (vsi_count > hw->func_caps.num_vsis) {
3835 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
3836 vsi_count, hw->func_caps.num_vsis);
3844 i40e_pf_get_switch_config(struct i40e_pf *pf)
3846 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3847 struct i40e_aqc_get_switch_config_resp *switch_config;
3848 struct i40e_aqc_switch_config_element_resp *element;
3849 uint16_t start_seid = 0, num_reported;
3852 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3853 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3854 if (!switch_config) {
3855 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3859 /* Get the switch configurations */
3860 ret = i40e_aq_get_switch_config(hw, switch_config,
3861 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3862 if (ret != I40E_SUCCESS) {
3863 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3866 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3867 if (num_reported != 1) { /* The number should be 1 */
3868 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3872 /* Parse the switch configuration elements */
3873 element = &(switch_config->element[0]);
3874 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3875 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3876 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3878 PMD_DRV_LOG(INFO, "Unknown element type");
3881 rte_free(switch_config);
3887 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3890 struct pool_entry *entry;
3892 if (pool == NULL || num == 0)
3895 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3896 if (entry == NULL) {
3897 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3901 /* queue heap initialize */
3902 pool->num_free = num;
3903 pool->num_alloc = 0;
3905 LIST_INIT(&pool->alloc_list);
3906 LIST_INIT(&pool->free_list);
3908 /* Initialize element */
3912 LIST_INSERT_HEAD(&pool->free_list, entry, next);
3917 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3919 struct pool_entry *entry, *next_entry;
3924 for (entry = LIST_FIRST(&pool->alloc_list);
3925 entry && (next_entry = LIST_NEXT(entry, next), 1);
3926 entry = next_entry) {
3927 LIST_REMOVE(entry, next);
3931 for (entry = LIST_FIRST(&pool->free_list);
3932 entry && (next_entry = LIST_NEXT(entry, next), 1);
3933 entry = next_entry) {
3934 LIST_REMOVE(entry, next);
3939 pool->num_alloc = 0;
3941 LIST_INIT(&pool->alloc_list);
3942 LIST_INIT(&pool->free_list);
3946 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3949 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3950 uint32_t pool_offset;
3954 PMD_DRV_LOG(ERR, "Invalid parameter");
3958 pool_offset = base - pool->base;
3959 /* Lookup in alloc list */
3960 LIST_FOREACH(entry, &pool->alloc_list, next) {
3961 if (entry->base == pool_offset) {
3962 valid_entry = entry;
3963 LIST_REMOVE(entry, next);
3968 /* Not find, return */
3969 if (valid_entry == NULL) {
3970 PMD_DRV_LOG(ERR, "Failed to find entry");
3975 * Found it, move it to free list and try to merge.
3976 * In order to make merge easier, always sort it by qbase.
3977 * Find adjacent prev and last entries.
3980 LIST_FOREACH(entry, &pool->free_list, next) {
3981 if (entry->base > valid_entry->base) {
3989 /* Try to merge with next one*/
3991 /* Merge with next one */
3992 if (valid_entry->base + valid_entry->len == next->base) {
3993 next->base = valid_entry->base;
3994 next->len += valid_entry->len;
3995 rte_free(valid_entry);
4002 /* Merge with previous one */
4003 if (prev->base + prev->len == valid_entry->base) {
4004 prev->len += valid_entry->len;
4005 /* If it merge with next one, remove next node */
4007 LIST_REMOVE(valid_entry, next);
4008 rte_free(valid_entry);
4010 rte_free(valid_entry);
4016 /* Not find any entry to merge, insert */
4019 LIST_INSERT_AFTER(prev, valid_entry, next);
4020 else if (next != NULL)
4021 LIST_INSERT_BEFORE(next, valid_entry, next);
4022 else /* It's empty list, insert to head */
4023 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4026 pool->num_free += valid_entry->len;
4027 pool->num_alloc -= valid_entry->len;
4033 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4036 struct pool_entry *entry, *valid_entry;
4038 if (pool == NULL || num == 0) {
4039 PMD_DRV_LOG(ERR, "Invalid parameter");
4043 if (pool->num_free < num) {
4044 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4045 num, pool->num_free);
4050 /* Lookup in free list and find most fit one */
4051 LIST_FOREACH(entry, &pool->free_list, next) {
4052 if (entry->len >= num) {
4054 if (entry->len == num) {
4055 valid_entry = entry;
4058 if (valid_entry == NULL || valid_entry->len > entry->len)
4059 valid_entry = entry;
4063 /* Not find one to satisfy the request, return */
4064 if (valid_entry == NULL) {
4065 PMD_DRV_LOG(ERR, "No valid entry found");
4069 * The entry have equal queue number as requested,
4070 * remove it from alloc_list.
4072 if (valid_entry->len == num) {
4073 LIST_REMOVE(valid_entry, next);
4076 * The entry have more numbers than requested,
4077 * create a new entry for alloc_list and minus its
4078 * queue base and number in free_list.
4080 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4081 if (entry == NULL) {
4083 "Failed to allocate memory for resource pool");
4086 entry->base = valid_entry->base;
4088 valid_entry->base += num;
4089 valid_entry->len -= num;
4090 valid_entry = entry;
4093 /* Insert it into alloc list, not sorted */
4094 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4096 pool->num_free -= valid_entry->len;
4097 pool->num_alloc += valid_entry->len;
4099 return valid_entry->base + pool->base;
4103 * bitmap_is_subset - Check whether src2 is subset of src1
4106 bitmap_is_subset(uint8_t src1, uint8_t src2)
4108 return !((src1 ^ src2) & src2);
4111 static enum i40e_status_code
4112 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4114 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4116 /* If DCB is not supported, only default TC is supported */
4117 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4118 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4119 return I40E_NOT_SUPPORTED;
4122 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4124 "Enabled TC map 0x%x not applicable to HW support 0x%x",
4125 hw->func_caps.enabled_tcmap, enabled_tcmap);
4126 return I40E_NOT_SUPPORTED;
4128 return I40E_SUCCESS;
4132 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4133 struct i40e_vsi_vlan_pvid_info *info)
4136 struct i40e_vsi_context ctxt;
4137 uint8_t vlan_flags = 0;
4140 if (vsi == NULL || info == NULL) {
4141 PMD_DRV_LOG(ERR, "invalid parameters");
4142 return I40E_ERR_PARAM;
4146 vsi->info.pvid = info->config.pvid;
4148 * If insert pvid is enabled, only tagged pkts are
4149 * allowed to be sent out.
4151 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4152 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4155 if (info->config.reject.tagged == 0)
4156 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4158 if (info->config.reject.untagged == 0)
4159 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4161 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4162 I40E_AQ_VSI_PVLAN_MODE_MASK);
4163 vsi->info.port_vlan_flags |= vlan_flags;
4164 vsi->info.valid_sections =
4165 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4166 memset(&ctxt, 0, sizeof(ctxt));
4167 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4168 ctxt.seid = vsi->seid;
4170 hw = I40E_VSI_TO_HW(vsi);
4171 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4172 if (ret != I40E_SUCCESS)
4173 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4179 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4181 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4183 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4185 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4186 if (ret != I40E_SUCCESS)
4190 PMD_DRV_LOG(ERR, "seid not valid");
4194 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4195 tc_bw_data.tc_valid_bits = enabled_tcmap;
4196 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4197 tc_bw_data.tc_bw_credits[i] =
4198 (enabled_tcmap & (1 << i)) ? 1 : 0;
4200 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4201 if (ret != I40E_SUCCESS) {
4202 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4206 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4207 sizeof(vsi->info.qs_handle));
4208 return I40E_SUCCESS;
4211 static enum i40e_status_code
4212 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4213 struct i40e_aqc_vsi_properties_data *info,
4214 uint8_t enabled_tcmap)
4216 enum i40e_status_code ret;
4217 int i, total_tc = 0;
4218 uint16_t qpnum_per_tc, bsf, qp_idx;
4220 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4221 if (ret != I40E_SUCCESS)
4224 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4225 if (enabled_tcmap & (1 << i))
4227 vsi->enabled_tc = enabled_tcmap;
4229 /* Number of queues per enabled TC */
4230 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4231 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4232 bsf = rte_bsf32(qpnum_per_tc);
4234 /* Adjust the queue number to actual queues that can be applied */
4235 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4236 vsi->nb_qps = qpnum_per_tc * total_tc;
4239 * Configure TC and queue mapping parameters, for enabled TC,
4240 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4241 * default queue will serve it.
4244 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4245 if (vsi->enabled_tc & (1 << i)) {
4246 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4247 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4248 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4249 qp_idx += qpnum_per_tc;
4251 info->tc_mapping[i] = 0;
4254 /* Associate queue number with VSI */
4255 if (vsi->type == I40E_VSI_SRIOV) {
4256 info->mapping_flags |=
4257 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4258 for (i = 0; i < vsi->nb_qps; i++)
4259 info->queue_mapping[i] =
4260 rte_cpu_to_le_16(vsi->base_queue + i);
4262 info->mapping_flags |=
4263 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4264 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4266 info->valid_sections |=
4267 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4269 return I40E_SUCCESS;
4273 i40e_veb_release(struct i40e_veb *veb)
4275 struct i40e_vsi *vsi;
4281 if (!TAILQ_EMPTY(&veb->head)) {
4282 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4285 /* associate_vsi field is NULL for floating VEB */
4286 if (veb->associate_vsi != NULL) {
4287 vsi = veb->associate_vsi;
4288 hw = I40E_VSI_TO_HW(vsi);
4290 vsi->uplink_seid = veb->uplink_seid;
4293 veb->associate_pf->main_vsi->floating_veb = NULL;
4294 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4297 i40e_aq_delete_element(hw, veb->seid, NULL);
4299 return I40E_SUCCESS;
4303 static struct i40e_veb *
4304 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4306 struct i40e_veb *veb;
4312 "veb setup failed, associated PF shouldn't null");
4315 hw = I40E_PF_TO_HW(pf);
4317 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4319 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4323 veb->associate_vsi = vsi;
4324 veb->associate_pf = pf;
4325 TAILQ_INIT(&veb->head);
4326 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4328 /* create floating veb if vsi is NULL */
4330 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4331 I40E_DEFAULT_TCMAP, false,
4332 &veb->seid, false, NULL);
4334 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4335 true, &veb->seid, false, NULL);
4338 if (ret != I40E_SUCCESS) {
4339 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4340 hw->aq.asq_last_status);
4344 /* get statistics index */
4345 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4346 &veb->stats_idx, NULL, NULL, NULL);
4347 if (ret != I40E_SUCCESS) {
4348 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4349 hw->aq.asq_last_status);
4352 /* Get VEB bandwidth, to be implemented */
4353 /* Now associated vsi binding to the VEB, set uplink to this VEB */
4355 vsi->uplink_seid = veb->seid;
4364 i40e_vsi_release(struct i40e_vsi *vsi)
4368 struct i40e_vsi_list *vsi_list;
4371 struct i40e_mac_filter *f;
4372 uint16_t user_param;
4375 return I40E_SUCCESS;
4377 user_param = vsi->user_param;
4379 pf = I40E_VSI_TO_PF(vsi);
4380 hw = I40E_VSI_TO_HW(vsi);
4382 /* VSI has child to attach, release child first */
4384 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4385 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4388 i40e_veb_release(vsi->veb);
4391 if (vsi->floating_veb) {
4392 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4393 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4398 /* Remove all macvlan filters of the VSI */
4399 i40e_vsi_remove_all_macvlan_filter(vsi);
4400 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4403 if (vsi->type != I40E_VSI_MAIN &&
4404 ((vsi->type != I40E_VSI_SRIOV) ||
4405 !pf->floating_veb_list[user_param])) {
4406 /* Remove vsi from parent's sibling list */
4407 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4408 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4409 return I40E_ERR_PARAM;
4411 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4412 &vsi->sib_vsi_list, list);
4414 /* Remove all switch element of the VSI */
4415 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4416 if (ret != I40E_SUCCESS)
4417 PMD_DRV_LOG(ERR, "Failed to delete element");
4420 if ((vsi->type == I40E_VSI_SRIOV) &&
4421 pf->floating_veb_list[user_param]) {
4422 /* Remove vsi from parent's sibling list */
4423 if (vsi->parent_vsi == NULL ||
4424 vsi->parent_vsi->floating_veb == NULL) {
4425 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4426 return I40E_ERR_PARAM;
4428 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4429 &vsi->sib_vsi_list, list);
4431 /* Remove all switch element of the VSI */
4432 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4433 if (ret != I40E_SUCCESS)
4434 PMD_DRV_LOG(ERR, "Failed to delete element");
4437 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4439 if (vsi->type != I40E_VSI_SRIOV)
4440 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4443 return I40E_SUCCESS;
4447 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4449 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4450 struct i40e_aqc_remove_macvlan_element_data def_filter;
4451 struct i40e_mac_filter_info filter;
4454 if (vsi->type != I40E_VSI_MAIN)
4455 return I40E_ERR_CONFIG;
4456 memset(&def_filter, 0, sizeof(def_filter));
4457 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4459 def_filter.vlan_tag = 0;
4460 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4461 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4462 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4463 if (ret != I40E_SUCCESS) {
4464 struct i40e_mac_filter *f;
4465 struct ether_addr *mac;
4467 PMD_DRV_LOG(WARNING,
4468 "Cannot remove the default macvlan filter");
4469 /* It needs to add the permanent mac into mac list */
4470 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4472 PMD_DRV_LOG(ERR, "failed to allocate memory");
4473 return I40E_ERR_NO_MEMORY;
4475 mac = &f->mac_info.mac_addr;
4476 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4478 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4479 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4484 (void)rte_memcpy(&filter.mac_addr,
4485 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4486 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4487 return i40e_vsi_add_mac(vsi, &filter);
4491 * i40e_vsi_get_bw_config - Query VSI BW Information
4492 * @vsi: the VSI to be queried
4494 * Returns 0 on success, negative value on failure
4496 static enum i40e_status_code
4497 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4499 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4500 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4501 struct i40e_hw *hw = &vsi->adapter->hw;
4506 memset(&bw_config, 0, sizeof(bw_config));
4507 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4508 if (ret != I40E_SUCCESS) {
4509 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4510 hw->aq.asq_last_status);
4514 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4515 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4516 &ets_sla_config, NULL);
4517 if (ret != I40E_SUCCESS) {
4519 "VSI failed to get TC bandwdith configuration %u",
4520 hw->aq.asq_last_status);
4524 /* store and print out BW info */
4525 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4526 vsi->bw_info.bw_max = bw_config.max_bw;
4527 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4528 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4529 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4530 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4532 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4533 vsi->bw_info.bw_ets_share_credits[i] =
4534 ets_sla_config.share_credits[i];
4535 vsi->bw_info.bw_ets_credits[i] =
4536 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4537 /* 4 bits per TC, 4th bit is reserved */
4538 vsi->bw_info.bw_ets_max[i] =
4539 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4540 RTE_LEN2MASK(3, uint8_t));
4541 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4542 vsi->bw_info.bw_ets_share_credits[i]);
4543 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4544 vsi->bw_info.bw_ets_credits[i]);
4545 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4546 vsi->bw_info.bw_ets_max[i]);
4549 return I40E_SUCCESS;
4552 /* i40e_enable_pf_lb
4553 * @pf: pointer to the pf structure
4555 * allow loopback on pf
4558 i40e_enable_pf_lb(struct i40e_pf *pf)
4560 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4561 struct i40e_vsi_context ctxt;
4564 /* Use the FW API if FW >= v5.0 */
4565 if (hw->aq.fw_maj_ver < 5) {
4566 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4570 memset(&ctxt, 0, sizeof(ctxt));
4571 ctxt.seid = pf->main_vsi_seid;
4572 ctxt.pf_num = hw->pf_id;
4573 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4575 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4576 ret, hw->aq.asq_last_status);
4579 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4580 ctxt.info.valid_sections =
4581 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4582 ctxt.info.switch_id |=
4583 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4585 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4587 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
4588 hw->aq.asq_last_status);
4593 i40e_vsi_setup(struct i40e_pf *pf,
4594 enum i40e_vsi_type type,
4595 struct i40e_vsi *uplink_vsi,
4596 uint16_t user_param)
4598 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4599 struct i40e_vsi *vsi;
4600 struct i40e_mac_filter_info filter;
4602 struct i40e_vsi_context ctxt;
4603 struct ether_addr broadcast =
4604 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4606 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4607 uplink_vsi == NULL) {
4609 "VSI setup failed, VSI link shouldn't be NULL");
4613 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4615 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4620 * 1.type is not MAIN and uplink vsi is not NULL
4621 * If uplink vsi didn't setup VEB, create one first under veb field
4622 * 2.type is SRIOV and the uplink is NULL
4623 * If floating VEB is NULL, create one veb under floating veb field
4626 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4627 uplink_vsi->veb == NULL) {
4628 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4630 if (uplink_vsi->veb == NULL) {
4631 PMD_DRV_LOG(ERR, "VEB setup failed");
4634 /* set ALLOWLOOPBACk on pf, when veb is created */
4635 i40e_enable_pf_lb(pf);
4638 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4639 pf->main_vsi->floating_veb == NULL) {
4640 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4642 if (pf->main_vsi->floating_veb == NULL) {
4643 PMD_DRV_LOG(ERR, "VEB setup failed");
4648 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4650 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4653 TAILQ_INIT(&vsi->mac_list);
4655 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4656 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4657 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4658 vsi->user_param = user_param;
4659 /* Allocate queues */
4660 switch (vsi->type) {
4661 case I40E_VSI_MAIN :
4662 vsi->nb_qps = pf->lan_nb_qps;
4664 case I40E_VSI_SRIOV :
4665 vsi->nb_qps = pf->vf_nb_qps;
4667 case I40E_VSI_VMDQ2:
4668 vsi->nb_qps = pf->vmdq_nb_qps;
4671 vsi->nb_qps = pf->fdir_nb_qps;
4677 * The filter status descriptor is reported in rx queue 0,
4678 * while the tx queue for fdir filter programming has no
4679 * such constraints, can be non-zero queues.
4680 * To simplify it, choose FDIR vsi use queue 0 pair.
4681 * To make sure it will use queue 0 pair, queue allocation
4682 * need be done before this function is called
4684 if (type != I40E_VSI_FDIR) {
4685 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4687 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4691 vsi->base_queue = ret;
4693 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4695 /* VF has MSIX interrupt in VF range, don't allocate here */
4696 if (type == I40E_VSI_MAIN) {
4697 ret = i40e_res_pool_alloc(&pf->msix_pool,
4698 RTE_MIN(vsi->nb_qps,
4699 RTE_MAX_RXTX_INTR_VEC_ID));
4701 PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4703 goto fail_queue_alloc;
4705 vsi->msix_intr = ret;
4706 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4707 } else if (type != I40E_VSI_SRIOV) {
4708 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4710 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4711 goto fail_queue_alloc;
4713 vsi->msix_intr = ret;
4721 if (type == I40E_VSI_MAIN) {
4722 /* For main VSI, no need to add since it's default one */
4723 vsi->uplink_seid = pf->mac_seid;
4724 vsi->seid = pf->main_vsi_seid;
4725 /* Bind queues with specific MSIX interrupt */
4727 * Needs 2 interrupt at least, one for misc cause which will
4728 * enabled from OS side, Another for queues binding the
4729 * interrupt from device side only.
4732 /* Get default VSI parameters from hardware */
4733 memset(&ctxt, 0, sizeof(ctxt));
4734 ctxt.seid = vsi->seid;
4735 ctxt.pf_num = hw->pf_id;
4736 ctxt.uplink_seid = vsi->uplink_seid;
4738 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4739 if (ret != I40E_SUCCESS) {
4740 PMD_DRV_LOG(ERR, "Failed to get VSI params");
4741 goto fail_msix_alloc;
4743 (void)rte_memcpy(&vsi->info, &ctxt.info,
4744 sizeof(struct i40e_aqc_vsi_properties_data));
4745 vsi->vsi_id = ctxt.vsi_number;
4746 vsi->info.valid_sections = 0;
4748 /* Configure tc, enabled TC0 only */
4749 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4751 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4752 goto fail_msix_alloc;
4755 /* TC, queue mapping */
4756 memset(&ctxt, 0, sizeof(ctxt));
4757 vsi->info.valid_sections |=
4758 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4759 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4760 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4761 (void)rte_memcpy(&ctxt.info, &vsi->info,
4762 sizeof(struct i40e_aqc_vsi_properties_data));
4763 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4764 I40E_DEFAULT_TCMAP);
4765 if (ret != I40E_SUCCESS) {
4767 "Failed to configure TC queue mapping");
4768 goto fail_msix_alloc;
4770 ctxt.seid = vsi->seid;
4771 ctxt.pf_num = hw->pf_id;
4772 ctxt.uplink_seid = vsi->uplink_seid;
4775 /* Update VSI parameters */
4776 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4777 if (ret != I40E_SUCCESS) {
4778 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4779 goto fail_msix_alloc;
4782 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4783 sizeof(vsi->info.tc_mapping));
4784 (void)rte_memcpy(&vsi->info.queue_mapping,
4785 &ctxt.info.queue_mapping,
4786 sizeof(vsi->info.queue_mapping));
4787 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4788 vsi->info.valid_sections = 0;
4790 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4794 * Updating default filter settings are necessary to prevent
4795 * reception of tagged packets.
4796 * Some old firmware configurations load a default macvlan
4797 * filter which accepts both tagged and untagged packets.
4798 * The updating is to use a normal filter instead if needed.
4799 * For NVM 4.2.2 or after, the updating is not needed anymore.
4800 * The firmware with correct configurations load the default
4801 * macvlan filter which is expected and cannot be removed.
4803 i40e_update_default_filter_setting(vsi);
4804 i40e_config_qinq(hw, vsi);
4805 } else if (type == I40E_VSI_SRIOV) {
4806 memset(&ctxt, 0, sizeof(ctxt));
4808 * For other VSI, the uplink_seid equals to uplink VSI's
4809 * uplink_seid since they share same VEB
4811 if (uplink_vsi == NULL)
4812 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4814 vsi->uplink_seid = uplink_vsi->uplink_seid;
4815 ctxt.pf_num = hw->pf_id;
4816 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4817 ctxt.uplink_seid = vsi->uplink_seid;
4818 ctxt.connection_type = 0x1;
4819 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4821 /* Use the VEB configuration if FW >= v5.0 */
4822 if (hw->aq.fw_maj_ver >= 5) {
4823 /* Configure switch ID */
4824 ctxt.info.valid_sections |=
4825 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4826 ctxt.info.switch_id =
4827 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4830 /* Configure port/vlan */
4831 ctxt.info.valid_sections |=
4832 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4833 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4834 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4835 I40E_DEFAULT_TCMAP);
4836 if (ret != I40E_SUCCESS) {
4838 "Failed to configure TC queue mapping");
4839 goto fail_msix_alloc;
4841 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4842 ctxt.info.valid_sections |=
4843 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4845 * Since VSI is not created yet, only configure parameter,
4846 * will add vsi below.
4849 i40e_config_qinq(hw, vsi);
4850 } else if (type == I40E_VSI_VMDQ2) {
4851 memset(&ctxt, 0, sizeof(ctxt));
4853 * For other VSI, the uplink_seid equals to uplink VSI's
4854 * uplink_seid since they share same VEB
4856 vsi->uplink_seid = uplink_vsi->uplink_seid;
4857 ctxt.pf_num = hw->pf_id;
4859 ctxt.uplink_seid = vsi->uplink_seid;
4860 ctxt.connection_type = 0x1;
4861 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4863 ctxt.info.valid_sections |=
4864 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4865 /* user_param carries flag to enable loop back */
4867 ctxt.info.switch_id =
4868 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4869 ctxt.info.switch_id |=
4870 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4873 /* Configure port/vlan */
4874 ctxt.info.valid_sections |=
4875 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4876 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4877 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4878 I40E_DEFAULT_TCMAP);
4879 if (ret != I40E_SUCCESS) {
4881 "Failed to configure TC queue mapping");
4882 goto fail_msix_alloc;
4884 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4885 ctxt.info.valid_sections |=
4886 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4887 } else if (type == I40E_VSI_FDIR) {
4888 memset(&ctxt, 0, sizeof(ctxt));
4889 vsi->uplink_seid = uplink_vsi->uplink_seid;
4890 ctxt.pf_num = hw->pf_id;
4892 ctxt.uplink_seid = vsi->uplink_seid;
4893 ctxt.connection_type = 0x1; /* regular data port */
4894 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4895 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4896 I40E_DEFAULT_TCMAP);
4897 if (ret != I40E_SUCCESS) {
4899 "Failed to configure TC queue mapping.");
4900 goto fail_msix_alloc;
4902 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4903 ctxt.info.valid_sections |=
4904 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4906 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4907 goto fail_msix_alloc;
4910 if (vsi->type != I40E_VSI_MAIN) {
4911 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4912 if (ret != I40E_SUCCESS) {
4913 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4914 hw->aq.asq_last_status);
4915 goto fail_msix_alloc;
4917 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4918 vsi->info.valid_sections = 0;
4919 vsi->seid = ctxt.seid;
4920 vsi->vsi_id = ctxt.vsi_number;
4921 vsi->sib_vsi_list.vsi = vsi;
4922 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4923 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4924 &vsi->sib_vsi_list, list);
4926 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4927 &vsi->sib_vsi_list, list);
4931 /* MAC/VLAN configuration */
4932 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4933 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4935 ret = i40e_vsi_add_mac(vsi, &filter);
4936 if (ret != I40E_SUCCESS) {
4937 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4938 goto fail_msix_alloc;
4941 /* Get VSI BW information */
4942 i40e_vsi_get_bw_config(vsi);
4945 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4947 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4953 /* Configure vlan filter on or off */
4955 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4958 struct i40e_mac_filter *f;
4960 struct i40e_mac_filter_info *mac_filter;
4961 enum rte_mac_filter_type desired_filter;
4962 int ret = I40E_SUCCESS;
4965 /* Filter to match MAC and VLAN */
4966 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4968 /* Filter to match only MAC */
4969 desired_filter = RTE_MAC_PERFECT_MATCH;
4974 mac_filter = rte_zmalloc("mac_filter_info_data",
4975 num * sizeof(*mac_filter), 0);
4976 if (mac_filter == NULL) {
4977 PMD_DRV_LOG(ERR, "failed to allocate memory");
4978 return I40E_ERR_NO_MEMORY;
4983 /* Remove all existing mac */
4984 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
4985 mac_filter[i] = f->mac_info;
4986 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4988 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4989 on ? "enable" : "disable");
4995 /* Override with new filter */
4996 for (i = 0; i < num; i++) {
4997 mac_filter[i].filter_type = desired_filter;
4998 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5000 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5001 on ? "enable" : "disable");
5007 rte_free(mac_filter);
5011 /* Configure vlan stripping on or off */
5013 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5015 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5016 struct i40e_vsi_context ctxt;
5018 int ret = I40E_SUCCESS;
5020 /* Check if it has been already on or off */
5021 if (vsi->info.valid_sections &
5022 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5024 if ((vsi->info.port_vlan_flags &
5025 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5026 return 0; /* already on */
5028 if ((vsi->info.port_vlan_flags &
5029 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5030 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5031 return 0; /* already off */
5036 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5038 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5039 vsi->info.valid_sections =
5040 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5041 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5042 vsi->info.port_vlan_flags |= vlan_flags;
5043 ctxt.seid = vsi->seid;
5044 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5045 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5047 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5048 on ? "enable" : "disable");
5054 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5056 struct rte_eth_dev_data *data = dev->data;
5060 /* Apply vlan offload setting */
5061 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5062 i40e_vlan_offload_set(dev, mask);
5064 /* Apply double-vlan setting, not implemented yet */
5066 /* Apply pvid setting */
5067 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5068 data->dev_conf.txmode.hw_vlan_insert_pvid);
5070 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5076 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5078 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5080 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5084 i40e_update_flow_control(struct i40e_hw *hw)
5086 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5087 struct i40e_link_status link_status;
5088 uint32_t rxfc = 0, txfc = 0, reg;
5092 memset(&link_status, 0, sizeof(link_status));
5093 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5094 if (ret != I40E_SUCCESS) {
5095 PMD_DRV_LOG(ERR, "Failed to get link status information");
5096 goto write_reg; /* Disable flow control */
5099 an_info = hw->phy.link_info.an_info;
5100 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5101 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5102 ret = I40E_ERR_NOT_READY;
5103 goto write_reg; /* Disable flow control */
5106 * If link auto negotiation is enabled, flow control needs to
5107 * be configured according to it
5109 switch (an_info & I40E_LINK_PAUSE_RXTX) {
5110 case I40E_LINK_PAUSE_RXTX:
5113 hw->fc.current_mode = I40E_FC_FULL;
5115 case I40E_AQ_LINK_PAUSE_RX:
5117 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5119 case I40E_AQ_LINK_PAUSE_TX:
5121 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5124 hw->fc.current_mode = I40E_FC_NONE;
5129 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5130 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5131 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5132 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5133 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5134 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5141 i40e_pf_setup(struct i40e_pf *pf)
5143 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5144 struct i40e_filter_control_settings settings;
5145 struct i40e_vsi *vsi;
5148 /* Clear all stats counters */
5149 pf->offset_loaded = FALSE;
5150 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5151 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5153 ret = i40e_pf_get_switch_config(pf);
5154 if (ret != I40E_SUCCESS) {
5155 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5158 if (pf->flags & I40E_FLAG_FDIR) {
5159 /* make queue allocated first, let FDIR use queue pair 0*/
5160 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5161 if (ret != I40E_FDIR_QUEUE_ID) {
5163 "queue allocation fails for FDIR: ret =%d",
5165 pf->flags &= ~I40E_FLAG_FDIR;
5168 /* main VSI setup */
5169 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5171 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5172 return I40E_ERR_NOT_READY;
5176 /* Configure filter control */
5177 memset(&settings, 0, sizeof(settings));
5178 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5179 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5180 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5181 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5183 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
5184 hw->func_caps.rss_table_size);
5185 return I40E_ERR_PARAM;
5187 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u\n",
5188 hw->func_caps.rss_table_size);
5189 pf->hash_lut_size = hw->func_caps.rss_table_size;
5191 /* Enable ethtype and macvlan filters */
5192 settings.enable_ethtype = TRUE;
5193 settings.enable_macvlan = TRUE;
5194 ret = i40e_set_filter_control(hw, &settings);
5196 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5199 /* Update flow control according to the auto negotiation */
5200 i40e_update_flow_control(hw);
5202 return I40E_SUCCESS;
5206 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5212 * Set or clear TX Queue Disable flags,
5213 * which is required by hardware.
5215 i40e_pre_tx_queue_cfg(hw, q_idx, on);
5216 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5218 /* Wait until the request is finished */
5219 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5220 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5221 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5222 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5223 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5229 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5230 return I40E_SUCCESS; /* already on, skip next steps */
5232 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5233 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5235 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5236 return I40E_SUCCESS; /* already off, skip next steps */
5237 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5239 /* Write the register */
5240 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5241 /* Check the result */
5242 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5243 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5244 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5246 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5247 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5250 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5251 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5255 /* Check if it is timeout */
5256 if (j >= I40E_CHK_Q_ENA_COUNT) {
5257 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5258 (on ? "enable" : "disable"), q_idx);
5259 return I40E_ERR_TIMEOUT;
5262 return I40E_SUCCESS;
5265 /* Swith on or off the tx queues */
5267 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5269 struct rte_eth_dev_data *dev_data = pf->dev_data;
5270 struct i40e_tx_queue *txq;
5271 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5275 for (i = 0; i < dev_data->nb_tx_queues; i++) {
5276 txq = dev_data->tx_queues[i];
5277 /* Don't operate the queue if not configured or
5278 * if starting only per queue */
5279 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5282 ret = i40e_dev_tx_queue_start(dev, i);
5284 ret = i40e_dev_tx_queue_stop(dev, i);
5285 if ( ret != I40E_SUCCESS)
5289 return I40E_SUCCESS;
5293 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5298 /* Wait until the request is finished */
5299 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5300 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5301 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5302 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5303 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5308 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5309 return I40E_SUCCESS; /* Already on, skip next steps */
5310 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5312 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5313 return I40E_SUCCESS; /* Already off, skip next steps */
5314 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5317 /* Write the register */
5318 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5319 /* Check the result */
5320 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5321 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5322 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5324 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5325 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5328 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5329 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5334 /* Check if it is timeout */
5335 if (j >= I40E_CHK_Q_ENA_COUNT) {
5336 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5337 (on ? "enable" : "disable"), q_idx);
5338 return I40E_ERR_TIMEOUT;
5341 return I40E_SUCCESS;
5343 /* Switch on or off the rx queues */
5345 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5347 struct rte_eth_dev_data *dev_data = pf->dev_data;
5348 struct i40e_rx_queue *rxq;
5349 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5353 for (i = 0; i < dev_data->nb_rx_queues; i++) {
5354 rxq = dev_data->rx_queues[i];
5355 /* Don't operate the queue if not configured or
5356 * if starting only per queue */
5357 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5360 ret = i40e_dev_rx_queue_start(dev, i);
5362 ret = i40e_dev_rx_queue_stop(dev, i);
5363 if (ret != I40E_SUCCESS)
5367 return I40E_SUCCESS;
5370 /* Switch on or off all the rx/tx queues */
5372 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5377 /* enable rx queues before enabling tx queues */
5378 ret = i40e_dev_switch_rx_queues(pf, on);
5380 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5383 ret = i40e_dev_switch_tx_queues(pf, on);
5385 /* Stop tx queues before stopping rx queues */
5386 ret = i40e_dev_switch_tx_queues(pf, on);
5388 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5391 ret = i40e_dev_switch_rx_queues(pf, on);
5397 /* Initialize VSI for TX */
5399 i40e_dev_tx_init(struct i40e_pf *pf)
5401 struct rte_eth_dev_data *data = pf->dev_data;
5403 uint32_t ret = I40E_SUCCESS;
5404 struct i40e_tx_queue *txq;
5406 for (i = 0; i < data->nb_tx_queues; i++) {
5407 txq = data->tx_queues[i];
5408 if (!txq || !txq->q_set)
5410 ret = i40e_tx_queue_init(txq);
5411 if (ret != I40E_SUCCESS)
5414 if (ret == I40E_SUCCESS)
5415 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5421 /* Initialize VSI for RX */
5423 i40e_dev_rx_init(struct i40e_pf *pf)
5425 struct rte_eth_dev_data *data = pf->dev_data;
5426 int ret = I40E_SUCCESS;
5428 struct i40e_rx_queue *rxq;
5430 i40e_pf_config_mq_rx(pf);
5431 for (i = 0; i < data->nb_rx_queues; i++) {
5432 rxq = data->rx_queues[i];
5433 if (!rxq || !rxq->q_set)
5436 ret = i40e_rx_queue_init(rxq);
5437 if (ret != I40E_SUCCESS) {
5439 "Failed to do RX queue initialization");
5443 if (ret == I40E_SUCCESS)
5444 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5451 i40e_dev_rxtx_init(struct i40e_pf *pf)
5455 err = i40e_dev_tx_init(pf);
5457 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5460 err = i40e_dev_rx_init(pf);
5462 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5470 i40e_vmdq_setup(struct rte_eth_dev *dev)
5472 struct rte_eth_conf *conf = &dev->data->dev_conf;
5473 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5474 int i, err, conf_vsis, j, loop;
5475 struct i40e_vsi *vsi;
5476 struct i40e_vmdq_info *vmdq_info;
5477 struct rte_eth_vmdq_rx_conf *vmdq_conf;
5478 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5481 * Disable interrupt to avoid message from VF. Furthermore, it will
5482 * avoid race condition in VSI creation/destroy.
5484 i40e_pf_disable_irq0(hw);
5486 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5487 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5491 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5492 if (conf_vsis > pf->max_nb_vmdq_vsi) {
5493 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5494 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5495 pf->max_nb_vmdq_vsi);
5499 if (pf->vmdq != NULL) {
5500 PMD_INIT_LOG(INFO, "VMDQ already configured");
5504 pf->vmdq = rte_zmalloc("vmdq_info_struct",
5505 sizeof(*vmdq_info) * conf_vsis, 0);
5507 if (pf->vmdq == NULL) {
5508 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5512 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5514 /* Create VMDQ VSI */
5515 for (i = 0; i < conf_vsis; i++) {
5516 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5517 vmdq_conf->enable_loop_back);
5519 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5523 vmdq_info = &pf->vmdq[i];
5525 vmdq_info->vsi = vsi;
5527 pf->nb_cfg_vmdq_vsi = conf_vsis;
5529 /* Configure Vlan */
5530 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5531 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5532 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5533 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5534 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5535 vmdq_conf->pool_map[i].vlan_id, j);
5537 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5538 vmdq_conf->pool_map[i].vlan_id);
5540 PMD_INIT_LOG(ERR, "Failed to add vlan");
5548 i40e_pf_enable_irq0(hw);
5553 for (i = 0; i < conf_vsis; i++)
5554 if (pf->vmdq[i].vsi == NULL)
5557 i40e_vsi_release(pf->vmdq[i].vsi);
5561 i40e_pf_enable_irq0(hw);
5566 i40e_stat_update_32(struct i40e_hw *hw,
5574 new_data = (uint64_t)I40E_READ_REG(hw, reg);
5578 if (new_data >= *offset)
5579 *stat = (uint64_t)(new_data - *offset);
5581 *stat = (uint64_t)((new_data +
5582 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5586 i40e_stat_update_48(struct i40e_hw *hw,
5595 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5596 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5597 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5602 if (new_data >= *offset)
5603 *stat = new_data - *offset;
5605 *stat = (uint64_t)((new_data +
5606 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5608 *stat &= I40E_48_BIT_MASK;
5613 i40e_pf_disable_irq0(struct i40e_hw *hw)
5615 /* Disable all interrupt types */
5616 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5617 I40E_WRITE_FLUSH(hw);
5622 i40e_pf_enable_irq0(struct i40e_hw *hw)
5624 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5625 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5626 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5627 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5628 I40E_WRITE_FLUSH(hw);
5632 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5634 /* read pending request and disable first */
5635 i40e_pf_disable_irq0(hw);
5636 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5637 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5638 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5641 /* Link no queues with irq0 */
5642 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5643 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5647 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5649 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5650 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5653 uint32_t index, offset, val;
5658 * Try to find which VF trigger a reset, use absolute VF id to access
5659 * since the reg is global register.
5661 for (i = 0; i < pf->vf_num; i++) {
5662 abs_vf_id = hw->func_caps.vf_base_id + i;
5663 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5664 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5665 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5666 /* VFR event occured */
5667 if (val & (0x1 << offset)) {
5670 /* Clear the event first */
5671 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5673 PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5675 * Only notify a VF reset event occured,
5676 * don't trigger another SW reset
5678 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5679 if (ret != I40E_SUCCESS)
5680 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5686 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5688 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5689 struct i40e_virtchnl_pf_event event;
5692 event.event = I40E_VIRTCHNL_EVENT_LINK_CHANGE;
5693 event.event_data.link_event.link_status =
5694 dev->data->dev_link.link_status;
5695 event.event_data.link_event.link_speed =
5696 (enum i40e_aq_link_speed)dev->data->dev_link.link_speed;
5698 for (i = 0; i < pf->vf_num; i++)
5699 i40e_pf_host_send_msg_to_vf(&pf->vfs[i], I40E_VIRTCHNL_OP_EVENT,
5700 I40E_SUCCESS, (uint8_t *)&event, sizeof(event));
5704 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5706 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5707 struct i40e_arq_event_info info;
5708 uint16_t pending, opcode;
5711 info.buf_len = I40E_AQ_BUF_SZ;
5712 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5713 if (!info.msg_buf) {
5714 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5720 ret = i40e_clean_arq_element(hw, &info, &pending);
5722 if (ret != I40E_SUCCESS) {
5724 "Failed to read msg from AdminQ, aq_err: %u",
5725 hw->aq.asq_last_status);
5728 opcode = rte_le_to_cpu_16(info.desc.opcode);
5731 case i40e_aqc_opc_send_msg_to_pf:
5732 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5733 i40e_pf_host_handle_vf_msg(dev,
5734 rte_le_to_cpu_16(info.desc.retval),
5735 rte_le_to_cpu_32(info.desc.cookie_high),
5736 rte_le_to_cpu_32(info.desc.cookie_low),
5740 case i40e_aqc_opc_get_link_status:
5741 ret = i40e_dev_link_update(dev, 0);
5743 i40e_notify_all_vfs_link_status(dev);
5744 _rte_eth_dev_callback_process(dev,
5745 RTE_ETH_EVENT_INTR_LSC, NULL);
5749 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5754 rte_free(info.msg_buf);
5758 * Interrupt handler triggered by NIC for handling
5759 * specific interrupt.
5762 * Pointer to interrupt handle.
5764 * The address of parameter (struct rte_eth_dev *) regsitered before.
5770 i40e_dev_interrupt_handler(struct rte_intr_handle *intr_handle,
5773 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5774 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5777 /* Disable interrupt */
5778 i40e_pf_disable_irq0(hw);
5780 /* read out interrupt causes */
5781 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5783 /* No interrupt event indicated */
5784 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5785 PMD_DRV_LOG(INFO, "No interrupt event");
5788 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5789 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5790 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5791 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5792 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5793 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5794 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5795 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5796 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5797 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5798 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5799 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5800 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5801 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5802 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5803 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5805 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5806 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5807 i40e_dev_handle_vfr_event(dev);
5809 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5810 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5811 i40e_dev_handle_aq_msg(dev);
5815 /* Enable interrupt */
5816 i40e_pf_enable_irq0(hw);
5817 rte_intr_enable(intr_handle);
5821 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5822 struct i40e_macvlan_filter *filter,
5825 int ele_num, ele_buff_size;
5826 int num, actual_num, i;
5828 int ret = I40E_SUCCESS;
5829 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5830 struct i40e_aqc_add_macvlan_element_data *req_list;
5832 if (filter == NULL || total == 0)
5833 return I40E_ERR_PARAM;
5834 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5835 ele_buff_size = hw->aq.asq_buf_size;
5837 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5838 if (req_list == NULL) {
5839 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5840 return I40E_ERR_NO_MEMORY;
5845 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5846 memset(req_list, 0, ele_buff_size);
5848 for (i = 0; i < actual_num; i++) {
5849 (void)rte_memcpy(req_list[i].mac_addr,
5850 &filter[num + i].macaddr, ETH_ADDR_LEN);
5851 req_list[i].vlan_tag =
5852 rte_cpu_to_le_16(filter[num + i].vlan_id);
5854 switch (filter[num + i].filter_type) {
5855 case RTE_MAC_PERFECT_MATCH:
5856 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5857 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5859 case RTE_MACVLAN_PERFECT_MATCH:
5860 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5862 case RTE_MAC_HASH_MATCH:
5863 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5864 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5866 case RTE_MACVLAN_HASH_MATCH:
5867 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5870 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5871 ret = I40E_ERR_PARAM;
5875 req_list[i].queue_number = 0;
5877 req_list[i].flags = rte_cpu_to_le_16(flags);
5880 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5882 if (ret != I40E_SUCCESS) {
5883 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5887 } while (num < total);
5895 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5896 struct i40e_macvlan_filter *filter,
5899 int ele_num, ele_buff_size;
5900 int num, actual_num, i;
5902 int ret = I40E_SUCCESS;
5903 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5904 struct i40e_aqc_remove_macvlan_element_data *req_list;
5906 if (filter == NULL || total == 0)
5907 return I40E_ERR_PARAM;
5909 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5910 ele_buff_size = hw->aq.asq_buf_size;
5912 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5913 if (req_list == NULL) {
5914 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5915 return I40E_ERR_NO_MEMORY;
5920 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5921 memset(req_list, 0, ele_buff_size);
5923 for (i = 0; i < actual_num; i++) {
5924 (void)rte_memcpy(req_list[i].mac_addr,
5925 &filter[num + i].macaddr, ETH_ADDR_LEN);
5926 req_list[i].vlan_tag =
5927 rte_cpu_to_le_16(filter[num + i].vlan_id);
5929 switch (filter[num + i].filter_type) {
5930 case RTE_MAC_PERFECT_MATCH:
5931 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5932 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5934 case RTE_MACVLAN_PERFECT_MATCH:
5935 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5937 case RTE_MAC_HASH_MATCH:
5938 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5939 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5941 case RTE_MACVLAN_HASH_MATCH:
5942 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5945 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5946 ret = I40E_ERR_PARAM;
5949 req_list[i].flags = rte_cpu_to_le_16(flags);
5952 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5954 if (ret != I40E_SUCCESS) {
5955 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5959 } while (num < total);
5966 /* Find out specific MAC filter */
5967 static struct i40e_mac_filter *
5968 i40e_find_mac_filter(struct i40e_vsi *vsi,
5969 struct ether_addr *macaddr)
5971 struct i40e_mac_filter *f;
5973 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5974 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5982 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5985 uint32_t vid_idx, vid_bit;
5987 if (vlan_id > ETH_VLAN_ID_MAX)
5990 vid_idx = I40E_VFTA_IDX(vlan_id);
5991 vid_bit = I40E_VFTA_BIT(vlan_id);
5993 if (vsi->vfta[vid_idx] & vid_bit)
6000 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6001 uint16_t vlan_id, bool on)
6003 uint32_t vid_idx, vid_bit;
6005 if (vlan_id > ETH_VLAN_ID_MAX)
6008 vid_idx = I40E_VFTA_IDX(vlan_id);
6009 vid_bit = I40E_VFTA_BIT(vlan_id);
6012 vsi->vfta[vid_idx] |= vid_bit;
6014 vsi->vfta[vid_idx] &= ~vid_bit;
6018 * Find all vlan options for specific mac addr,
6019 * return with actual vlan found.
6022 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6023 struct i40e_macvlan_filter *mv_f,
6024 int num, struct ether_addr *addr)
6030 * Not to use i40e_find_vlan_filter to decrease the loop time,
6031 * although the code looks complex.
6033 if (num < vsi->vlan_num)
6034 return I40E_ERR_PARAM;
6037 for (j = 0; j < I40E_VFTA_SIZE; j++) {
6039 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6040 if (vsi->vfta[j] & (1 << k)) {
6043 "vlan number doesn't match");
6044 return I40E_ERR_PARAM;
6046 (void)rte_memcpy(&mv_f[i].macaddr,
6047 addr, ETH_ADDR_LEN);
6049 j * I40E_UINT32_BIT_SIZE + k;
6055 return I40E_SUCCESS;
6059 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6060 struct i40e_macvlan_filter *mv_f,
6065 struct i40e_mac_filter *f;
6067 if (num < vsi->mac_num)
6068 return I40E_ERR_PARAM;
6070 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6072 PMD_DRV_LOG(ERR, "buffer number not match");
6073 return I40E_ERR_PARAM;
6075 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6077 mv_f[i].vlan_id = vlan;
6078 mv_f[i].filter_type = f->mac_info.filter_type;
6082 return I40E_SUCCESS;
6086 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6089 struct i40e_mac_filter *f;
6090 struct i40e_macvlan_filter *mv_f;
6091 int ret = I40E_SUCCESS;
6093 if (vsi == NULL || vsi->mac_num == 0)
6094 return I40E_ERR_PARAM;
6096 /* Case that no vlan is set */
6097 if (vsi->vlan_num == 0)
6100 num = vsi->mac_num * vsi->vlan_num;
6102 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6104 PMD_DRV_LOG(ERR, "failed to allocate memory");
6105 return I40E_ERR_NO_MEMORY;
6109 if (vsi->vlan_num == 0) {
6110 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6111 (void)rte_memcpy(&mv_f[i].macaddr,
6112 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6113 mv_f[i].vlan_id = 0;
6117 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6118 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6119 vsi->vlan_num, &f->mac_info.mac_addr);
6120 if (ret != I40E_SUCCESS)
6126 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6134 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6136 struct i40e_macvlan_filter *mv_f;
6138 int ret = I40E_SUCCESS;
6140 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6141 return I40E_ERR_PARAM;
6143 /* If it's already set, just return */
6144 if (i40e_find_vlan_filter(vsi,vlan))
6145 return I40E_SUCCESS;
6147 mac_num = vsi->mac_num;
6150 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6151 return I40E_ERR_PARAM;
6154 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6157 PMD_DRV_LOG(ERR, "failed to allocate memory");
6158 return I40E_ERR_NO_MEMORY;
6161 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6163 if (ret != I40E_SUCCESS)
6166 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6168 if (ret != I40E_SUCCESS)
6171 i40e_set_vlan_filter(vsi, vlan, 1);
6181 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6183 struct i40e_macvlan_filter *mv_f;
6185 int ret = I40E_SUCCESS;
6188 * Vlan 0 is the generic filter for untagged packets
6189 * and can't be removed.
6191 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6192 return I40E_ERR_PARAM;
6194 /* If can't find it, just return */
6195 if (!i40e_find_vlan_filter(vsi, vlan))
6196 return I40E_ERR_PARAM;
6198 mac_num = vsi->mac_num;
6201 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6202 return I40E_ERR_PARAM;
6205 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6208 PMD_DRV_LOG(ERR, "failed to allocate memory");
6209 return I40E_ERR_NO_MEMORY;
6212 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6214 if (ret != I40E_SUCCESS)
6217 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6219 if (ret != I40E_SUCCESS)
6222 /* This is last vlan to remove, replace all mac filter with vlan 0 */
6223 if (vsi->vlan_num == 1) {
6224 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6225 if (ret != I40E_SUCCESS)
6228 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6229 if (ret != I40E_SUCCESS)
6233 i40e_set_vlan_filter(vsi, vlan, 0);
6243 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6245 struct i40e_mac_filter *f;
6246 struct i40e_macvlan_filter *mv_f;
6247 int i, vlan_num = 0;
6248 int ret = I40E_SUCCESS;
6250 /* If it's add and we've config it, return */
6251 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6253 return I40E_SUCCESS;
6254 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6255 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6258 * If vlan_num is 0, that's the first time to add mac,
6259 * set mask for vlan_id 0.
6261 if (vsi->vlan_num == 0) {
6262 i40e_set_vlan_filter(vsi, 0, 1);
6265 vlan_num = vsi->vlan_num;
6266 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6267 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6270 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6272 PMD_DRV_LOG(ERR, "failed to allocate memory");
6273 return I40E_ERR_NO_MEMORY;
6276 for (i = 0; i < vlan_num; i++) {
6277 mv_f[i].filter_type = mac_filter->filter_type;
6278 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6282 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6283 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6284 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6285 &mac_filter->mac_addr);
6286 if (ret != I40E_SUCCESS)
6290 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6291 if (ret != I40E_SUCCESS)
6294 /* Add the mac addr into mac list */
6295 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6297 PMD_DRV_LOG(ERR, "failed to allocate memory");
6298 ret = I40E_ERR_NO_MEMORY;
6301 (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6303 f->mac_info.filter_type = mac_filter->filter_type;
6304 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6315 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6317 struct i40e_mac_filter *f;
6318 struct i40e_macvlan_filter *mv_f;
6320 enum rte_mac_filter_type filter_type;
6321 int ret = I40E_SUCCESS;
6323 /* Can't find it, return an error */
6324 f = i40e_find_mac_filter(vsi, addr);
6326 return I40E_ERR_PARAM;
6328 vlan_num = vsi->vlan_num;
6329 filter_type = f->mac_info.filter_type;
6330 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6331 filter_type == RTE_MACVLAN_HASH_MATCH) {
6332 if (vlan_num == 0) {
6333 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
6334 return I40E_ERR_PARAM;
6336 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6337 filter_type == RTE_MAC_HASH_MATCH)
6340 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6342 PMD_DRV_LOG(ERR, "failed to allocate memory");
6343 return I40E_ERR_NO_MEMORY;
6346 for (i = 0; i < vlan_num; i++) {
6347 mv_f[i].filter_type = filter_type;
6348 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6351 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6352 filter_type == RTE_MACVLAN_HASH_MATCH) {
6353 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6354 if (ret != I40E_SUCCESS)
6358 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6359 if (ret != I40E_SUCCESS)
6362 /* Remove the mac addr into mac list */
6363 TAILQ_REMOVE(&vsi->mac_list, f, next);
6373 /* Configure hash enable flags for RSS */
6375 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6382 if (flags & ETH_RSS_FRAG_IPV4)
6383 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6384 if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6385 if (type == I40E_MAC_X722) {
6386 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6387 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6389 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6391 if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6392 if (type == I40E_MAC_X722) {
6393 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6394 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6395 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6397 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6399 if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6400 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6401 if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6402 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6403 if (flags & ETH_RSS_FRAG_IPV6)
6404 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6405 if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6406 if (type == I40E_MAC_X722) {
6407 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6408 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6410 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6412 if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6413 if (type == I40E_MAC_X722) {
6414 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6415 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6416 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6418 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6420 if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6421 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6422 if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6423 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6424 if (flags & ETH_RSS_L2_PAYLOAD)
6425 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6430 /* Parse the hash enable flags */
6432 i40e_parse_hena(uint64_t flags)
6434 uint64_t rss_hf = 0;
6438 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6439 rss_hf |= ETH_RSS_FRAG_IPV4;
6440 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6441 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6442 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6443 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6444 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6445 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6446 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6447 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6448 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6449 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6450 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6451 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6452 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6453 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6454 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6455 rss_hf |= ETH_RSS_FRAG_IPV6;
6456 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6457 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6458 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6459 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6460 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6461 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6462 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6463 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6464 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6465 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6466 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6467 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6468 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6469 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6470 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6471 rss_hf |= ETH_RSS_L2_PAYLOAD;
6478 i40e_pf_disable_rss(struct i40e_pf *pf)
6480 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6483 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6484 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6485 if (hw->mac.type == I40E_MAC_X722)
6486 hena &= ~I40E_RSS_HENA_ALL_X722;
6488 hena &= ~I40E_RSS_HENA_ALL;
6489 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6490 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6491 I40E_WRITE_FLUSH(hw);
6495 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6497 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6498 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6501 if (!key || key_len == 0) {
6502 PMD_DRV_LOG(DEBUG, "No key to be configured");
6504 } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6506 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6510 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6511 struct i40e_aqc_get_set_rss_key_data *key_dw =
6512 (struct i40e_aqc_get_set_rss_key_data *)key;
6514 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6516 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6518 uint32_t *hash_key = (uint32_t *)key;
6521 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6522 i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6523 I40E_WRITE_FLUSH(hw);
6530 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6532 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6533 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6536 if (!key || !key_len)
6539 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6540 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6541 (struct i40e_aqc_get_set_rss_key_data *)key);
6543 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6547 uint32_t *key_dw = (uint32_t *)key;
6550 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6551 key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6553 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6559 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6561 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6566 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6567 rss_conf->rss_key_len);
6571 rss_hf = rss_conf->rss_hf;
6572 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6573 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6574 if (hw->mac.type == I40E_MAC_X722)
6575 hena &= ~I40E_RSS_HENA_ALL_X722;
6577 hena &= ~I40E_RSS_HENA_ALL;
6578 hena |= i40e_config_hena(rss_hf, hw->mac.type);
6579 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6580 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6581 I40E_WRITE_FLUSH(hw);
6587 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6588 struct rte_eth_rss_conf *rss_conf)
6590 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6591 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6592 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6595 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6596 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6597 if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6598 ? I40E_RSS_HENA_ALL_X722
6599 : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6600 if (rss_hf != 0) /* Enable RSS */
6602 return 0; /* Nothing to do */
6605 if (rss_hf == 0) /* Disable RSS */
6608 return i40e_hw_rss_hash_set(pf, rss_conf);
6612 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6613 struct rte_eth_rss_conf *rss_conf)
6615 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6616 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6619 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6620 &rss_conf->rss_key_len);
6622 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6623 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6624 rss_conf->rss_hf = i40e_parse_hena(hena);
6630 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6632 switch (filter_type) {
6633 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6634 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6636 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6637 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6639 case RTE_TUNNEL_FILTER_IMAC_TENID:
6640 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6642 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6643 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6645 case ETH_TUNNEL_FILTER_IMAC:
6646 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6648 case ETH_TUNNEL_FILTER_OIP:
6649 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6651 case ETH_TUNNEL_FILTER_IIP:
6652 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6655 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6662 /* Convert tunnel filter structure */
6664 i40e_tunnel_filter_convert(struct i40e_aqc_add_remove_cloud_filters_element_data
6666 struct i40e_tunnel_filter *tunnel_filter)
6668 ether_addr_copy((struct ether_addr *)&cld_filter->outer_mac,
6669 (struct ether_addr *)&tunnel_filter->input.outer_mac);
6670 ether_addr_copy((struct ether_addr *)&cld_filter->inner_mac,
6671 (struct ether_addr *)&tunnel_filter->input.inner_mac);
6672 tunnel_filter->input.inner_vlan = cld_filter->inner_vlan;
6673 tunnel_filter->input.flags = cld_filter->flags;
6674 tunnel_filter->input.tenant_id = cld_filter->tenant_id;
6675 tunnel_filter->queue = cld_filter->queue_number;
6680 /* Check if there exists the tunnel filter */
6681 struct i40e_tunnel_filter *
6682 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6683 const struct i40e_tunnel_filter_input *input)
6687 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6691 return tunnel_rule->hash_map[ret];
6694 /* Add a tunnel filter into the SW list */
6696 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6697 struct i40e_tunnel_filter *tunnel_filter)
6699 struct i40e_tunnel_rule *rule = &pf->tunnel;
6702 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6705 "Failed to insert tunnel filter to hash table %d!",
6709 rule->hash_map[ret] = tunnel_filter;
6711 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6716 /* Delete a tunnel filter from the SW list */
6718 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6719 struct i40e_tunnel_filter_input *input)
6721 struct i40e_tunnel_rule *rule = &pf->tunnel;
6722 struct i40e_tunnel_filter *tunnel_filter;
6725 ret = rte_hash_del_key(rule->hash_table, input);
6728 "Failed to delete tunnel filter to hash table %d!",
6732 tunnel_filter = rule->hash_map[ret];
6733 rule->hash_map[ret] = NULL;
6735 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6736 rte_free(tunnel_filter);
6742 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6743 struct rte_eth_tunnel_filter_conf *tunnel_filter,
6748 uint8_t i, tun_type = 0;
6749 /* internal varialbe to convert ipv6 byte order */
6750 uint32_t convert_ipv6[4];
6752 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6753 struct i40e_vsi *vsi = pf->main_vsi;
6754 struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter;
6755 struct i40e_aqc_add_remove_cloud_filters_element_data *pfilter;
6756 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6757 struct i40e_tunnel_filter *tunnel, *node;
6758 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6760 cld_filter = rte_zmalloc("tunnel_filter",
6761 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6764 if (NULL == cld_filter) {
6765 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6768 pfilter = cld_filter;
6770 ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6771 ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6773 pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6774 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6775 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6776 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6777 rte_memcpy(&pfilter->ipaddr.v4.data,
6778 &rte_cpu_to_le_32(ipv4_addr),
6779 sizeof(pfilter->ipaddr.v4.data));
6781 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6782 for (i = 0; i < 4; i++) {
6784 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6786 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6787 sizeof(pfilter->ipaddr.v6.data));
6790 /* check tunneled type */
6791 switch (tunnel_filter->tunnel_type) {
6792 case RTE_TUNNEL_TYPE_VXLAN:
6793 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6795 case RTE_TUNNEL_TYPE_NVGRE:
6796 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6798 case RTE_TUNNEL_TYPE_IP_IN_GRE:
6799 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6802 /* Other tunnel types is not supported. */
6803 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6804 rte_free(cld_filter);
6808 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6811 rte_free(cld_filter);
6815 pfilter->flags |= rte_cpu_to_le_16(
6816 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6817 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6818 pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6819 pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6821 /* Check if there is the filter in SW list */
6822 memset(&check_filter, 0, sizeof(check_filter));
6823 i40e_tunnel_filter_convert(cld_filter, &check_filter);
6824 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
6826 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
6830 if (!add && !node) {
6831 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
6836 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6838 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
6841 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
6842 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
6843 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
6845 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6848 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
6851 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
6854 rte_free(cld_filter);
6859 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6863 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6864 if (pf->vxlan_ports[i] == port)
6872 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6876 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6878 idx = i40e_get_vxlan_port_idx(pf, port);
6880 /* Check if port already exists */
6882 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6886 /* Now check if there is space to add the new port */
6887 idx = i40e_get_vxlan_port_idx(pf, 0);
6890 "Maximum number of UDP ports reached, not adding port %d",
6895 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6898 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6902 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6905 /* New port: add it and mark its index in the bitmap */
6906 pf->vxlan_ports[idx] = port;
6907 pf->vxlan_bitmap |= (1 << idx);
6909 if (!(pf->flags & I40E_FLAG_VXLAN))
6910 pf->flags |= I40E_FLAG_VXLAN;
6916 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6919 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6921 if (!(pf->flags & I40E_FLAG_VXLAN)) {
6922 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6926 idx = i40e_get_vxlan_port_idx(pf, port);
6929 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6933 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6934 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6938 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6941 pf->vxlan_ports[idx] = 0;
6942 pf->vxlan_bitmap &= ~(1 << idx);
6944 if (!pf->vxlan_bitmap)
6945 pf->flags &= ~I40E_FLAG_VXLAN;
6950 /* Add UDP tunneling port */
6952 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6953 struct rte_eth_udp_tunnel *udp_tunnel)
6956 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6958 if (udp_tunnel == NULL)
6961 switch (udp_tunnel->prot_type) {
6962 case RTE_TUNNEL_TYPE_VXLAN:
6963 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6966 case RTE_TUNNEL_TYPE_GENEVE:
6967 case RTE_TUNNEL_TYPE_TEREDO:
6968 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6973 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6981 /* Remove UDP tunneling port */
6983 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6984 struct rte_eth_udp_tunnel *udp_tunnel)
6987 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6989 if (udp_tunnel == NULL)
6992 switch (udp_tunnel->prot_type) {
6993 case RTE_TUNNEL_TYPE_VXLAN:
6994 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6996 case RTE_TUNNEL_TYPE_GENEVE:
6997 case RTE_TUNNEL_TYPE_TEREDO:
6998 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7002 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7010 /* Calculate the maximum number of contiguous PF queues that are configured */
7012 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7014 struct rte_eth_dev_data *data = pf->dev_data;
7016 struct i40e_rx_queue *rxq;
7019 for (i = 0; i < pf->lan_nb_qps; i++) {
7020 rxq = data->rx_queues[i];
7021 if (rxq && rxq->q_set)
7032 i40e_pf_config_rss(struct i40e_pf *pf)
7034 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7035 struct rte_eth_rss_conf rss_conf;
7036 uint32_t i, lut = 0;
7040 * If both VMDQ and RSS enabled, not all of PF queues are configured.
7041 * It's necessary to calulate the actual PF queues that are configured.
7043 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7044 num = i40e_pf_calc_configured_queues_num(pf);
7046 num = pf->dev_data->nb_rx_queues;
7048 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7049 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7053 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7057 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7060 lut = (lut << 8) | (j & ((0x1 <<
7061 hw->func_caps.rss_table_entry_width) - 1));
7063 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7066 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7067 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
7068 i40e_pf_disable_rss(pf);
7071 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7072 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7073 /* Random default keys */
7074 static uint32_t rss_key_default[] = {0x6b793944,
7075 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7076 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7077 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7079 rss_conf.rss_key = (uint8_t *)rss_key_default;
7080 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7084 return i40e_hw_rss_hash_set(pf, &rss_conf);
7088 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7089 struct rte_eth_tunnel_filter_conf *filter)
7091 if (pf == NULL || filter == NULL) {
7092 PMD_DRV_LOG(ERR, "Invalid parameter");
7096 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7097 PMD_DRV_LOG(ERR, "Invalid queue ID");
7101 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7102 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7106 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7107 (is_zero_ether_addr(&filter->outer_mac))) {
7108 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7112 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7113 (is_zero_ether_addr(&filter->inner_mac))) {
7114 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7121 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7122 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
7124 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7129 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7130 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
7133 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7134 } else if (len == 4) {
7135 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7137 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7142 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7149 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
7150 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7156 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7163 switch (cfg->cfg_type) {
7164 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7165 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7168 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7176 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7177 enum rte_filter_op filter_op,
7180 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7181 int ret = I40E_ERR_PARAM;
7183 switch (filter_op) {
7184 case RTE_ETH_FILTER_SET:
7185 ret = i40e_dev_global_config_set(hw,
7186 (struct rte_eth_global_cfg *)arg);
7189 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7197 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7198 enum rte_filter_op filter_op,
7201 struct rte_eth_tunnel_filter_conf *filter;
7202 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7203 int ret = I40E_SUCCESS;
7205 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7207 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7208 return I40E_ERR_PARAM;
7210 switch (filter_op) {
7211 case RTE_ETH_FILTER_NOP:
7212 if (!(pf->flags & I40E_FLAG_VXLAN))
7213 ret = I40E_NOT_SUPPORTED;
7215 case RTE_ETH_FILTER_ADD:
7216 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7218 case RTE_ETH_FILTER_DELETE:
7219 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7222 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7223 ret = I40E_ERR_PARAM;
7231 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7234 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7237 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7238 ret = i40e_pf_config_rss(pf);
7240 i40e_pf_disable_rss(pf);
7245 /* Get the symmetric hash enable configurations per port */
7247 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7249 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7251 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7254 /* Set the symmetric hash enable configurations per port */
7256 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7258 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7261 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7263 "Symmetric hash has already been enabled");
7266 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7268 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7270 "Symmetric hash has already been disabled");
7273 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7275 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7276 I40E_WRITE_FLUSH(hw);
7280 * Get global configurations of hash function type and symmetric hash enable
7281 * per flow type (pctype). Note that global configuration means it affects all
7282 * the ports on the same NIC.
7285 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7286 struct rte_eth_hash_global_conf *g_cfg)
7288 uint32_t reg, mask = I40E_FLOW_TYPES;
7290 enum i40e_filter_pctype pctype;
7292 memset(g_cfg, 0, sizeof(*g_cfg));
7293 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7294 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7295 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7297 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7298 PMD_DRV_LOG(DEBUG, "Hash function is %s",
7299 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7301 for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7302 if (!(mask & (1UL << i)))
7304 mask &= ~(1UL << i);
7305 /* Bit set indicats the coresponding flow type is supported */
7306 g_cfg->valid_bit_mask[0] |= (1UL << i);
7307 /* if flowtype is invalid, continue */
7308 if (!I40E_VALID_FLOW(i))
7310 pctype = i40e_flowtype_to_pctype(i);
7311 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7312 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7313 g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7320 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7323 uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7325 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7326 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7327 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7328 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7334 * As i40e supports less than 32 flow types, only first 32 bits need to
7337 mask0 = g_cfg->valid_bit_mask[0];
7338 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7340 /* Check if any unsupported flow type configured */
7341 if ((mask0 | i40e_mask) ^ i40e_mask)
7344 if (g_cfg->valid_bit_mask[i])
7352 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7358 * Set global configurations of hash function type and symmetric hash enable
7359 * per flow type (pctype). Note any modifying global configuration will affect
7360 * all the ports on the same NIC.
7363 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7364 struct rte_eth_hash_global_conf *g_cfg)
7369 uint32_t mask0 = g_cfg->valid_bit_mask[0];
7370 enum i40e_filter_pctype pctype;
7372 /* Check the input parameters */
7373 ret = i40e_hash_global_config_check(g_cfg);
7377 for (i = 0; mask0 && i < UINT32_BIT; i++) {
7378 if (!(mask0 & (1UL << i)))
7380 mask0 &= ~(1UL << i);
7381 /* if flowtype is invalid, continue */
7382 if (!I40E_VALID_FLOW(i))
7384 pctype = i40e_flowtype_to_pctype(i);
7385 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7386 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7387 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7390 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7391 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7393 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7395 "Hash function already set to Toeplitz");
7398 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7399 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7401 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7403 "Hash function already set to Simple XOR");
7406 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7408 /* Use the default, and keep it as it is */
7411 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7414 I40E_WRITE_FLUSH(hw);
7420 * Valid input sets for hash and flow director filters per PCTYPE
7423 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7424 enum rte_filter_type filter)
7428 static const uint64_t valid_hash_inset_table[] = {
7429 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7430 I40E_INSET_DMAC | I40E_INSET_SMAC |
7431 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7432 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7433 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7434 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7435 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7436 I40E_INSET_FLEX_PAYLOAD,
7437 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7438 I40E_INSET_DMAC | I40E_INSET_SMAC |
7439 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7440 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7441 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7442 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7443 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7444 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7445 I40E_INSET_FLEX_PAYLOAD,
7446 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7447 I40E_INSET_DMAC | I40E_INSET_SMAC |
7448 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7449 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7450 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7451 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7452 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7453 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7454 I40E_INSET_FLEX_PAYLOAD,
7455 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7456 I40E_INSET_DMAC | I40E_INSET_SMAC |
7457 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7458 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7459 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7460 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7461 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7462 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7463 I40E_INSET_FLEX_PAYLOAD,
7464 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7465 I40E_INSET_DMAC | I40E_INSET_SMAC |
7466 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7467 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7468 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7469 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7470 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7471 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7472 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7473 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7474 I40E_INSET_DMAC | I40E_INSET_SMAC |
7475 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7476 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7477 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7478 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7479 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7480 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7481 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7482 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7483 I40E_INSET_DMAC | I40E_INSET_SMAC |
7484 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7485 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7486 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7487 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7488 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7489 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7490 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7491 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7492 I40E_INSET_DMAC | I40E_INSET_SMAC |
7493 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7494 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7495 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7496 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7497 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7498 I40E_INSET_FLEX_PAYLOAD,
7499 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7500 I40E_INSET_DMAC | I40E_INSET_SMAC |
7501 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7502 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7503 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7504 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7505 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7506 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7507 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7508 I40E_INSET_DMAC | I40E_INSET_SMAC |
7509 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7510 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7511 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7512 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7513 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7514 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7515 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7516 I40E_INSET_DMAC | I40E_INSET_SMAC |
7517 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7518 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7519 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7520 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7521 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7522 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7523 I40E_INSET_FLEX_PAYLOAD,
7524 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7525 I40E_INSET_DMAC | I40E_INSET_SMAC |
7526 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7527 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7528 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7529 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7530 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7531 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7532 I40E_INSET_FLEX_PAYLOAD,
7533 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7534 I40E_INSET_DMAC | I40E_INSET_SMAC |
7535 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7536 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7537 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7538 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7539 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7540 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7541 I40E_INSET_FLEX_PAYLOAD,
7542 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7543 I40E_INSET_DMAC | I40E_INSET_SMAC |
7544 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7545 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7546 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7547 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7548 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7549 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7550 I40E_INSET_FLEX_PAYLOAD,
7551 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7552 I40E_INSET_DMAC | I40E_INSET_SMAC |
7553 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7554 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7555 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7556 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7557 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7558 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7559 I40E_INSET_FLEX_PAYLOAD,
7560 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7561 I40E_INSET_DMAC | I40E_INSET_SMAC |
7562 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7563 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7564 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7565 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7566 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7567 I40E_INSET_FLEX_PAYLOAD,
7568 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7569 I40E_INSET_DMAC | I40E_INSET_SMAC |
7570 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7571 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7572 I40E_INSET_FLEX_PAYLOAD,
7576 * Flow director supports only fields defined in
7577 * union rte_eth_fdir_flow.
7579 static const uint64_t valid_fdir_inset_table[] = {
7580 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7581 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7582 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7583 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7584 I40E_INSET_IPV4_TTL,
7585 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7586 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7587 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7588 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7589 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7590 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7591 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7592 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7593 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7594 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7595 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7596 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7597 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7598 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7599 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7600 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7601 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7602 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7603 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7604 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7605 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7606 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7607 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7608 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7609 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7610 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7611 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7612 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7613 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7614 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7616 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7617 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7618 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7619 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7620 I40E_INSET_IPV4_TTL,
7621 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7622 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7623 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7624 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7625 I40E_INSET_IPV6_HOP_LIMIT,
7626 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7627 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7628 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7629 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7630 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7631 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7632 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7633 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7634 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7635 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7636 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7637 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7638 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7639 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7640 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7641 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7642 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7643 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7644 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7645 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7646 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7647 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7648 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7649 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7650 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7651 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7652 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7653 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7654 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7655 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7657 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7658 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7659 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7660 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7661 I40E_INSET_IPV6_HOP_LIMIT,
7662 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7663 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7664 I40E_INSET_LAST_ETHER_TYPE,
7667 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7669 if (filter == RTE_ETH_FILTER_HASH)
7670 valid = valid_hash_inset_table[pctype];
7672 valid = valid_fdir_inset_table[pctype];
7678 * Validate if the input set is allowed for a specific PCTYPE
7681 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7682 enum rte_filter_type filter, uint64_t inset)
7686 valid = i40e_get_valid_input_set(pctype, filter);
7687 if (inset & (~valid))
7693 /* default input set fields combination per pctype */
7695 i40e_get_default_input_set(uint16_t pctype)
7697 static const uint64_t default_inset_table[] = {
7698 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7699 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7700 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7701 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7702 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7703 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7704 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7705 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7706 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7707 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7708 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7709 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7710 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7711 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7712 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7713 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7714 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7715 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7716 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7717 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7719 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7720 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7721 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7722 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7723 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7724 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7725 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7726 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7727 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7728 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7729 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7730 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7731 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7732 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7733 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7734 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7735 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7736 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7737 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7738 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7739 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7740 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7742 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7743 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7744 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7745 I40E_INSET_LAST_ETHER_TYPE,
7748 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7751 return default_inset_table[pctype];
7755 * Parse the input set from index to logical bit masks
7758 i40e_parse_input_set(uint64_t *inset,
7759 enum i40e_filter_pctype pctype,
7760 enum rte_eth_input_set_field *field,
7766 static const struct {
7767 enum rte_eth_input_set_field field;
7769 } inset_convert_table[] = {
7770 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7771 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7772 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7773 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7774 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7775 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7776 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7777 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7778 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7779 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7780 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7781 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7782 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7783 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7784 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7785 I40E_INSET_IPV6_NEXT_HDR},
7786 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7787 I40E_INSET_IPV6_HOP_LIMIT},
7788 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7789 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7790 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7791 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7792 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7793 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7794 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7795 I40E_INSET_SCTP_VT},
7796 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7797 I40E_INSET_TUNNEL_DMAC},
7798 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7799 I40E_INSET_VLAN_TUNNEL},
7800 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7801 I40E_INSET_TUNNEL_ID},
7802 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7803 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7804 I40E_INSET_FLEX_PAYLOAD_W1},
7805 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7806 I40E_INSET_FLEX_PAYLOAD_W2},
7807 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7808 I40E_INSET_FLEX_PAYLOAD_W3},
7809 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7810 I40E_INSET_FLEX_PAYLOAD_W4},
7811 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7812 I40E_INSET_FLEX_PAYLOAD_W5},
7813 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7814 I40E_INSET_FLEX_PAYLOAD_W6},
7815 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7816 I40E_INSET_FLEX_PAYLOAD_W7},
7817 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7818 I40E_INSET_FLEX_PAYLOAD_W8},
7821 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7824 /* Only one item allowed for default or all */
7826 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7827 *inset = i40e_get_default_input_set(pctype);
7829 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7830 *inset = I40E_INSET_NONE;
7835 for (i = 0, *inset = 0; i < size; i++) {
7836 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7837 if (field[i] == inset_convert_table[j].field) {
7838 *inset |= inset_convert_table[j].inset;
7843 /* It contains unsupported input set, return immediately */
7844 if (j == RTE_DIM(inset_convert_table))
7852 * Translate the input set from bit masks to register aware bit masks
7856 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
7866 static const struct inset_map inset_map_common[] = {
7867 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7868 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7869 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7870 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7871 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7872 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7873 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7874 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7875 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7876 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7877 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7878 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7879 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7880 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7881 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7882 {I40E_INSET_TUNNEL_DMAC,
7883 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7884 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7885 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7886 {I40E_INSET_TUNNEL_SRC_PORT,
7887 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7888 {I40E_INSET_TUNNEL_DST_PORT,
7889 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7890 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7891 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7892 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7893 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7894 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7895 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7896 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7897 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7898 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7901 /* some different registers map in x722*/
7902 static const struct inset_map inset_map_diff_x722[] = {
7903 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
7904 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
7905 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
7906 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
7909 static const struct inset_map inset_map_diff_not_x722[] = {
7910 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7911 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7912 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7913 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7919 /* Translate input set to register aware inset */
7920 if (type == I40E_MAC_X722) {
7921 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
7922 if (input & inset_map_diff_x722[i].inset)
7923 val |= inset_map_diff_x722[i].inset_reg;
7926 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
7927 if (input & inset_map_diff_not_x722[i].inset)
7928 val |= inset_map_diff_not_x722[i].inset_reg;
7932 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
7933 if (input & inset_map_common[i].inset)
7934 val |= inset_map_common[i].inset_reg;
7941 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7944 uint64_t inset_need_mask = inset;
7946 static const struct {
7949 } inset_mask_map[] = {
7950 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7951 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7952 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7953 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7954 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7955 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7956 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7957 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7960 if (!inset || !mask || !nb_elem)
7963 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7964 /* Clear the inset bit, if no MASK is required,
7965 * for example proto + ttl
7967 if ((inset & inset_mask_map[i].inset) ==
7968 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
7969 inset_need_mask &= ~inset_mask_map[i].inset;
7970 if (!inset_need_mask)
7973 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7974 if ((inset_need_mask & inset_mask_map[i].inset) ==
7975 inset_mask_map[i].inset) {
7976 if (idx >= nb_elem) {
7977 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
7980 mask[idx] = inset_mask_map[i].mask;
7989 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7991 uint32_t reg = i40e_read_rx_ctl(hw, addr);
7993 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7995 i40e_write_rx_ctl(hw, addr, val);
7996 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7997 (uint32_t)i40e_read_rx_ctl(hw, addr));
8001 i40e_filter_input_set_init(struct i40e_pf *pf)
8003 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8004 enum i40e_filter_pctype pctype;
8005 uint64_t input_set, inset_reg;
8006 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8009 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8010 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8011 if (hw->mac.type == I40E_MAC_X722) {
8012 if (!I40E_VALID_PCTYPE_X722(pctype))
8015 if (!I40E_VALID_PCTYPE(pctype))
8019 input_set = i40e_get_default_input_set(pctype);
8021 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8022 I40E_INSET_MASK_NUM_REG);
8025 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8028 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8029 (uint32_t)(inset_reg & UINT32_MAX));
8030 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8031 (uint32_t)((inset_reg >>
8032 I40E_32_BIT_WIDTH) & UINT32_MAX));
8033 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8034 (uint32_t)(inset_reg & UINT32_MAX));
8035 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8036 (uint32_t)((inset_reg >>
8037 I40E_32_BIT_WIDTH) & UINT32_MAX));
8039 for (i = 0; i < num; i++) {
8040 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8042 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8045 /*clear unused mask registers of the pctype */
8046 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8047 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8049 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8052 I40E_WRITE_FLUSH(hw);
8054 /* store the default input set */
8055 pf->hash_input_set[pctype] = input_set;
8056 pf->fdir.input_set[pctype] = input_set;
8061 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8062 struct rte_eth_input_set_conf *conf)
8064 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8065 enum i40e_filter_pctype pctype;
8066 uint64_t input_set, inset_reg = 0;
8067 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8071 PMD_DRV_LOG(ERR, "Invalid pointer");
8074 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8075 conf->op != RTE_ETH_INPUT_SET_ADD) {
8076 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8080 if (!I40E_VALID_FLOW(conf->flow_type)) {
8081 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8085 if (hw->mac.type == I40E_MAC_X722) {
8086 /* get translated pctype value in fd pctype register */
8087 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8088 I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8091 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8093 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8096 PMD_DRV_LOG(ERR, "Failed to parse input set");
8099 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8101 PMD_DRV_LOG(ERR, "Invalid input set");
8104 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8105 /* get inset value in register */
8106 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8107 inset_reg <<= I40E_32_BIT_WIDTH;
8108 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8109 input_set |= pf->hash_input_set[pctype];
8111 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8112 I40E_INSET_MASK_NUM_REG);
8116 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8118 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8119 (uint32_t)(inset_reg & UINT32_MAX));
8120 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8121 (uint32_t)((inset_reg >>
8122 I40E_32_BIT_WIDTH) & UINT32_MAX));
8124 for (i = 0; i < num; i++)
8125 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8127 /*clear unused mask registers of the pctype */
8128 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8129 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8131 I40E_WRITE_FLUSH(hw);
8133 pf->hash_input_set[pctype] = input_set;
8138 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8139 struct rte_eth_input_set_conf *conf)
8141 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8142 enum i40e_filter_pctype pctype;
8143 uint64_t input_set, inset_reg = 0;
8144 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8148 PMD_DRV_LOG(ERR, "Invalid pointer");
8151 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8152 conf->op != RTE_ETH_INPUT_SET_ADD) {
8153 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8157 if (!I40E_VALID_FLOW(conf->flow_type)) {
8158 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8162 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8164 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8167 PMD_DRV_LOG(ERR, "Failed to parse input set");
8170 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8172 PMD_DRV_LOG(ERR, "Invalid input set");
8176 /* get inset value in register */
8177 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8178 inset_reg <<= I40E_32_BIT_WIDTH;
8179 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8181 /* Can not change the inset reg for flex payload for fdir,
8182 * it is done by writing I40E_PRTQF_FD_FLXINSET
8183 * in i40e_set_flex_mask_on_pctype.
8185 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8186 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8188 input_set |= pf->fdir.input_set[pctype];
8189 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8190 I40E_INSET_MASK_NUM_REG);
8194 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8196 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8197 (uint32_t)(inset_reg & UINT32_MAX));
8198 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8199 (uint32_t)((inset_reg >>
8200 I40E_32_BIT_WIDTH) & UINT32_MAX));
8202 for (i = 0; i < num; i++)
8203 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8205 /*clear unused mask registers of the pctype */
8206 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8207 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8209 I40E_WRITE_FLUSH(hw);
8211 pf->fdir.input_set[pctype] = input_set;
8216 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8221 PMD_DRV_LOG(ERR, "Invalid pointer");
8225 switch (info->info_type) {
8226 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8227 i40e_get_symmetric_hash_enable_per_port(hw,
8228 &(info->info.enable));
8230 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8231 ret = i40e_get_hash_filter_global_config(hw,
8232 &(info->info.global_conf));
8235 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8245 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8250 PMD_DRV_LOG(ERR, "Invalid pointer");
8254 switch (info->info_type) {
8255 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8256 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8258 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8259 ret = i40e_set_hash_filter_global_config(hw,
8260 &(info->info.global_conf));
8262 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8263 ret = i40e_hash_filter_inset_select(hw,
8264 &(info->info.input_set_conf));
8268 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8277 /* Operations for hash function */
8279 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8280 enum rte_filter_op filter_op,
8283 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8286 switch (filter_op) {
8287 case RTE_ETH_FILTER_NOP:
8289 case RTE_ETH_FILTER_GET:
8290 ret = i40e_hash_filter_get(hw,
8291 (struct rte_eth_hash_filter_info *)arg);
8293 case RTE_ETH_FILTER_SET:
8294 ret = i40e_hash_filter_set(hw,
8295 (struct rte_eth_hash_filter_info *)arg);
8298 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8307 /* Convert ethertype filter structure */
8309 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8310 struct i40e_ethertype_filter *filter)
8312 rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8313 filter->input.ether_type = input->ether_type;
8314 filter->flags = input->flags;
8315 filter->queue = input->queue;
8320 /* Check if there exists the ehtertype filter */
8321 struct i40e_ethertype_filter *
8322 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8323 const struct i40e_ethertype_filter_input *input)
8327 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8331 return ethertype_rule->hash_map[ret];
8334 /* Add ethertype filter in SW list */
8336 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8337 struct i40e_ethertype_filter *filter)
8339 struct i40e_ethertype_rule *rule = &pf->ethertype;
8342 ret = rte_hash_add_key(rule->hash_table, &filter->input);
8345 "Failed to insert ethertype filter"
8346 " to hash table %d!",
8350 rule->hash_map[ret] = filter;
8352 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8357 /* Delete ethertype filter in SW list */
8359 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8360 struct i40e_ethertype_filter_input *input)
8362 struct i40e_ethertype_rule *rule = &pf->ethertype;
8363 struct i40e_ethertype_filter *filter;
8366 ret = rte_hash_del_key(rule->hash_table, input);
8369 "Failed to delete ethertype filter"
8370 " to hash table %d!",
8374 filter = rule->hash_map[ret];
8375 rule->hash_map[ret] = NULL;
8377 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8384 * Configure ethertype filter, which can director packet by filtering
8385 * with mac address and ether_type or only ether_type
8388 i40e_ethertype_filter_set(struct i40e_pf *pf,
8389 struct rte_eth_ethertype_filter *filter,
8392 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8393 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
8394 struct i40e_ethertype_filter *ethertype_filter, *node;
8395 struct i40e_ethertype_filter check_filter;
8396 struct i40e_control_filter_stats stats;
8400 if (filter->queue >= pf->dev_data->nb_rx_queues) {
8401 PMD_DRV_LOG(ERR, "Invalid queue ID");
8404 if (filter->ether_type == ETHER_TYPE_IPv4 ||
8405 filter->ether_type == ETHER_TYPE_IPv6) {
8407 "unsupported ether_type(0x%04x) in control packet filter.",
8408 filter->ether_type);
8411 if (filter->ether_type == ETHER_TYPE_VLAN)
8412 PMD_DRV_LOG(WARNING,
8413 "filter vlan ether_type in first tag is not supported.");
8415 /* Check if there is the filter in SW list */
8416 memset(&check_filter, 0, sizeof(check_filter));
8417 i40e_ethertype_filter_convert(filter, &check_filter);
8418 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
8419 &check_filter.input);
8421 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
8425 if (!add && !node) {
8426 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
8430 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8431 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8432 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8433 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8434 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8436 memset(&stats, 0, sizeof(stats));
8437 ret = i40e_aq_add_rem_control_packet_filter(hw,
8438 filter->mac_addr.addr_bytes,
8439 filter->ether_type, flags,
8441 filter->queue, add, &stats, NULL);
8444 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u\n",
8445 ret, stats.mac_etype_used, stats.etype_used,
8446 stats.mac_etype_free, stats.etype_free);
8450 /* Add or delete a filter in SW list */
8452 ethertype_filter = rte_zmalloc("ethertype_filter",
8453 sizeof(*ethertype_filter), 0);
8454 rte_memcpy(ethertype_filter, &check_filter,
8455 sizeof(check_filter));
8456 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
8458 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
8465 * Handle operations for ethertype filter.
8468 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8469 enum rte_filter_op filter_op,
8472 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8475 if (filter_op == RTE_ETH_FILTER_NOP)
8479 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8484 switch (filter_op) {
8485 case RTE_ETH_FILTER_ADD:
8486 ret = i40e_ethertype_filter_set(pf,
8487 (struct rte_eth_ethertype_filter *)arg,
8490 case RTE_ETH_FILTER_DELETE:
8491 ret = i40e_ethertype_filter_set(pf,
8492 (struct rte_eth_ethertype_filter *)arg,
8496 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
8504 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8505 enum rte_filter_type filter_type,
8506 enum rte_filter_op filter_op,
8514 switch (filter_type) {
8515 case RTE_ETH_FILTER_NONE:
8516 /* For global configuration */
8517 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8519 case RTE_ETH_FILTER_HASH:
8520 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8522 case RTE_ETH_FILTER_MACVLAN:
8523 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8525 case RTE_ETH_FILTER_ETHERTYPE:
8526 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8528 case RTE_ETH_FILTER_TUNNEL:
8529 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8531 case RTE_ETH_FILTER_FDIR:
8532 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8534 case RTE_ETH_FILTER_GENERIC:
8535 if (filter_op != RTE_ETH_FILTER_GET)
8537 *(const void **)arg = &i40e_flow_ops;
8540 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8550 * Check and enable Extended Tag.
8551 * Enabling Extended Tag is important for 40G performance.
8554 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8556 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
8560 ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8563 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8567 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
8568 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
8573 ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8576 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8580 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
8581 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
8584 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
8585 ret = rte_eal_pci_write_config(pci_dev, &buf, sizeof(buf),
8588 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
8595 * As some registers wouldn't be reset unless a global hardware reset,
8596 * hardware initialization is needed to put those registers into an
8597 * expected initial state.
8600 i40e_hw_init(struct rte_eth_dev *dev)
8602 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8604 i40e_enable_extended_tag(dev);
8606 /* clear the PF Queue Filter control register */
8607 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
8609 /* Disable symmetric hash per port */
8610 i40e_set_symmetric_hash_enable_per_port(hw, 0);
8613 enum i40e_filter_pctype
8614 i40e_flowtype_to_pctype(uint16_t flow_type)
8616 static const enum i40e_filter_pctype pctype_table[] = {
8617 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
8618 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
8619 I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
8620 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
8621 I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
8622 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
8623 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
8624 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
8625 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
8626 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
8627 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
8628 I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
8629 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
8630 I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
8631 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
8632 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
8633 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
8634 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
8635 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
8638 return pctype_table[flow_type];
8642 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
8644 static const uint16_t flowtype_table[] = {
8645 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
8646 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8647 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8648 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8649 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8650 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8651 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8652 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8653 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8654 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8655 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8656 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8657 RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
8658 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8659 RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
8660 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
8661 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8662 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8663 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8664 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8665 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8666 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8667 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8668 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8669 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8670 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8671 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8672 RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8673 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8674 RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8675 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8678 return flowtype_table[pctype];
8682 * On X710, performance number is far from the expectation on recent firmware
8683 * versions; on XL710, performance number is also far from the expectation on
8684 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8685 * mode is enabled and port MAC address is equal to the packet destination MAC
8686 * address. The fix for this issue may not be integrated in the following
8687 * firmware version. So the workaround in software driver is needed. It needs
8688 * to modify the initial values of 3 internal only registers for both X710 and
8689 * XL710. Note that the values for X710 or XL710 could be different, and the
8690 * workaround can be removed when it is fixed in firmware in the future.
8693 /* For both X710 and XL710 */
8694 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
8695 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
8697 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8698 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
8701 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
8703 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
8704 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
8707 i40e_dev_sync_phy_type(struct i40e_hw *hw)
8709 enum i40e_status_code status;
8710 struct i40e_aq_get_phy_abilities_resp phy_ab;
8713 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
8724 i40e_configure_registers(struct i40e_hw *hw)
8730 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
8731 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
8732 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8738 for (i = 0; i < RTE_DIM(reg_table); i++) {
8739 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8740 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
8741 I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
8743 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
8746 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
8749 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8752 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8756 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8757 reg_table[i].addr, reg);
8758 if (reg == reg_table[i].val)
8761 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
8762 reg_table[i].val, NULL);
8765 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
8766 reg_table[i].val, reg_table[i].addr);
8769 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
8770 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
8774 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
8775 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
8776 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
8777 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
8779 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
8784 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
8785 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
8789 /* Configure for double VLAN RX stripping */
8790 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
8791 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
8792 reg |= I40E_VSI_TSR_QINQ_CONFIG;
8793 ret = i40e_aq_debug_write_register(hw,
8794 I40E_VSI_TSR(vsi->vsi_id),
8797 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
8799 return I40E_ERR_CONFIG;
8803 /* Configure for double VLAN TX insertion */
8804 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
8805 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
8806 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
8807 ret = i40e_aq_debug_write_register(hw,
8808 I40E_VSI_L2TAGSTXVALID(
8809 vsi->vsi_id), reg, NULL);
8812 "Failed to update VSI_L2TAGSTXVALID[%d]",
8814 return I40E_ERR_CONFIG;
8822 * i40e_aq_add_mirror_rule
8823 * @hw: pointer to the hardware structure
8824 * @seid: VEB seid to add mirror rule to
8825 * @dst_id: destination vsi seid
8826 * @entries: Buffer which contains the entities to be mirrored
8827 * @count: number of entities contained in the buffer
8828 * @rule_id:the rule_id of the rule to be added
8830 * Add a mirror rule for a given veb.
8833 static enum i40e_status_code
8834 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
8835 uint16_t seid, uint16_t dst_id,
8836 uint16_t rule_type, uint16_t *entries,
8837 uint16_t count, uint16_t *rule_id)
8839 struct i40e_aq_desc desc;
8840 struct i40e_aqc_add_delete_mirror_rule cmd;
8841 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8842 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8845 enum i40e_status_code status;
8847 i40e_fill_default_direct_cmd_desc(&desc,
8848 i40e_aqc_opc_add_mirror_rule);
8849 memset(&cmd, 0, sizeof(cmd));
8851 buff_len = sizeof(uint16_t) * count;
8852 desc.datalen = rte_cpu_to_le_16(buff_len);
8854 desc.flags |= rte_cpu_to_le_16(
8855 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8856 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8857 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8858 cmd.num_entries = rte_cpu_to_le_16(count);
8859 cmd.seid = rte_cpu_to_le_16(seid);
8860 cmd.destination = rte_cpu_to_le_16(dst_id);
8862 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8863 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8865 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
8866 hw->aq.asq_last_status, resp->rule_id,
8867 resp->mirror_rules_used, resp->mirror_rules_free);
8868 *rule_id = rte_le_to_cpu_16(resp->rule_id);
8874 * i40e_aq_del_mirror_rule
8875 * @hw: pointer to the hardware structure
8876 * @seid: VEB seid to add mirror rule to
8877 * @entries: Buffer which contains the entities to be mirrored
8878 * @count: number of entities contained in the buffer
8879 * @rule_id:the rule_id of the rule to be delete
8881 * Delete a mirror rule for a given veb.
8884 static enum i40e_status_code
8885 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8886 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8887 uint16_t count, uint16_t rule_id)
8889 struct i40e_aq_desc desc;
8890 struct i40e_aqc_add_delete_mirror_rule cmd;
8891 uint16_t buff_len = 0;
8892 enum i40e_status_code status;
8895 i40e_fill_default_direct_cmd_desc(&desc,
8896 i40e_aqc_opc_delete_mirror_rule);
8897 memset(&cmd, 0, sizeof(cmd));
8898 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8899 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8901 cmd.num_entries = count;
8902 buff_len = sizeof(uint16_t) * count;
8903 desc.datalen = rte_cpu_to_le_16(buff_len);
8904 buff = (void *)entries;
8906 /* rule id is filled in destination field for deleting mirror rule */
8907 cmd.destination = rte_cpu_to_le_16(rule_id);
8909 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8910 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8911 cmd.seid = rte_cpu_to_le_16(seid);
8913 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8914 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
8920 * i40e_mirror_rule_set
8921 * @dev: pointer to the hardware structure
8922 * @mirror_conf: mirror rule info
8923 * @sw_id: mirror rule's sw_id
8924 * @on: enable/disable
8926 * set a mirror rule.
8930 i40e_mirror_rule_set(struct rte_eth_dev *dev,
8931 struct rte_eth_mirror_conf *mirror_conf,
8932 uint8_t sw_id, uint8_t on)
8934 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8935 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8936 struct i40e_mirror_rule *it, *mirr_rule = NULL;
8937 struct i40e_mirror_rule *parent = NULL;
8938 uint16_t seid, dst_seid, rule_id;
8942 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
8944 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
8946 "mirror rule can not be configured without veb or vfs.");
8949 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
8950 PMD_DRV_LOG(ERR, "mirror table is full.");
8953 if (mirror_conf->dst_pool > pf->vf_num) {
8954 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
8955 mirror_conf->dst_pool);
8959 seid = pf->main_vsi->veb->seid;
8961 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8962 if (sw_id <= it->index) {
8968 if (mirr_rule && sw_id == mirr_rule->index) {
8970 PMD_DRV_LOG(ERR, "mirror rule exists.");
8973 ret = i40e_aq_del_mirror_rule(hw, seid,
8974 mirr_rule->rule_type,
8976 mirr_rule->num_entries, mirr_rule->id);
8979 "failed to remove mirror rule: ret = %d, aq_err = %d.",
8980 ret, hw->aq.asq_last_status);
8983 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8984 rte_free(mirr_rule);
8985 pf->nb_mirror_rule--;
8989 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8993 mirr_rule = rte_zmalloc("i40e_mirror_rule",
8994 sizeof(struct i40e_mirror_rule) , 0);
8996 PMD_DRV_LOG(ERR, "failed to allocate memory");
8997 return I40E_ERR_NO_MEMORY;
8999 switch (mirror_conf->rule_type) {
9000 case ETH_MIRROR_VLAN:
9001 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9002 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9003 mirr_rule->entries[j] =
9004 mirror_conf->vlan.vlan_id[i];
9009 PMD_DRV_LOG(ERR, "vlan is not specified.");
9010 rte_free(mirr_rule);
9013 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9015 case ETH_MIRROR_VIRTUAL_POOL_UP:
9016 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9017 /* check if the specified pool bit is out of range */
9018 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9019 PMD_DRV_LOG(ERR, "pool mask is out of range.");
9020 rte_free(mirr_rule);
9023 for (i = 0, j = 0; i < pf->vf_num; i++) {
9024 if (mirror_conf->pool_mask & (1ULL << i)) {
9025 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9029 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9030 /* add pf vsi to entries */
9031 mirr_rule->entries[j] = pf->main_vsi_seid;
9035 PMD_DRV_LOG(ERR, "pool is not specified.");
9036 rte_free(mirr_rule);
9039 /* egress and ingress in aq commands means from switch but not port */
9040 mirr_rule->rule_type =
9041 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9042 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9043 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9045 case ETH_MIRROR_UPLINK_PORT:
9046 /* egress and ingress in aq commands means from switch but not port*/
9047 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9049 case ETH_MIRROR_DOWNLINK_PORT:
9050 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9053 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9054 mirror_conf->rule_type);
9055 rte_free(mirr_rule);
9059 /* If the dst_pool is equal to vf_num, consider it as PF */
9060 if (mirror_conf->dst_pool == pf->vf_num)
9061 dst_seid = pf->main_vsi_seid;
9063 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9065 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9066 mirr_rule->rule_type, mirr_rule->entries,
9070 "failed to add mirror rule: ret = %d, aq_err = %d.",
9071 ret, hw->aq.asq_last_status);
9072 rte_free(mirr_rule);
9076 mirr_rule->index = sw_id;
9077 mirr_rule->num_entries = j;
9078 mirr_rule->id = rule_id;
9079 mirr_rule->dst_vsi_seid = dst_seid;
9082 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9084 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9086 pf->nb_mirror_rule++;
9091 * i40e_mirror_rule_reset
9092 * @dev: pointer to the device
9093 * @sw_id: mirror rule's sw_id
9095 * reset a mirror rule.
9099 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9101 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9102 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9103 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9107 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9109 seid = pf->main_vsi->veb->seid;
9111 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9112 if (sw_id == it->index) {
9118 ret = i40e_aq_del_mirror_rule(hw, seid,
9119 mirr_rule->rule_type,
9121 mirr_rule->num_entries, mirr_rule->id);
9124 "failed to remove mirror rule: status = %d, aq_err = %d.",
9125 ret, hw->aq.asq_last_status);
9128 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9129 rte_free(mirr_rule);
9130 pf->nb_mirror_rule--;
9132 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9139 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9141 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9142 uint64_t systim_cycles;
9144 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9145 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9148 return systim_cycles;
9152 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9154 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9157 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9158 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9165 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9167 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9170 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9171 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9178 i40e_start_timecounters(struct rte_eth_dev *dev)
9180 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9181 struct i40e_adapter *adapter =
9182 (struct i40e_adapter *)dev->data->dev_private;
9183 struct rte_eth_link link;
9184 uint32_t tsync_inc_l;
9185 uint32_t tsync_inc_h;
9187 /* Get current link speed. */
9188 memset(&link, 0, sizeof(link));
9189 i40e_dev_link_update(dev, 1);
9190 rte_i40e_dev_atomic_read_link_status(dev, &link);
9192 switch (link.link_speed) {
9193 case ETH_SPEED_NUM_40G:
9194 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9195 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9197 case ETH_SPEED_NUM_10G:
9198 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9199 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9201 case ETH_SPEED_NUM_1G:
9202 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9203 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9210 /* Set the timesync increment value. */
9211 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9212 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9214 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9215 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9216 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9218 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9219 adapter->systime_tc.cc_shift = 0;
9220 adapter->systime_tc.nsec_mask = 0;
9222 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9223 adapter->rx_tstamp_tc.cc_shift = 0;
9224 adapter->rx_tstamp_tc.nsec_mask = 0;
9226 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9227 adapter->tx_tstamp_tc.cc_shift = 0;
9228 adapter->tx_tstamp_tc.nsec_mask = 0;
9232 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9234 struct i40e_adapter *adapter =
9235 (struct i40e_adapter *)dev->data->dev_private;
9237 adapter->systime_tc.nsec += delta;
9238 adapter->rx_tstamp_tc.nsec += delta;
9239 adapter->tx_tstamp_tc.nsec += delta;
9245 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9248 struct i40e_adapter *adapter =
9249 (struct i40e_adapter *)dev->data->dev_private;
9251 ns = rte_timespec_to_ns(ts);
9253 /* Set the timecounters to a new value. */
9254 adapter->systime_tc.nsec = ns;
9255 adapter->rx_tstamp_tc.nsec = ns;
9256 adapter->tx_tstamp_tc.nsec = ns;
9262 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9264 uint64_t ns, systime_cycles;
9265 struct i40e_adapter *adapter =
9266 (struct i40e_adapter *)dev->data->dev_private;
9268 systime_cycles = i40e_read_systime_cyclecounter(dev);
9269 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9270 *ts = rte_ns_to_timespec(ns);
9276 i40e_timesync_enable(struct rte_eth_dev *dev)
9278 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9279 uint32_t tsync_ctl_l;
9280 uint32_t tsync_ctl_h;
9282 /* Stop the timesync system time. */
9283 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9284 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9285 /* Reset the timesync system time value. */
9286 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9287 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9289 i40e_start_timecounters(dev);
9291 /* Clear timesync registers. */
9292 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9293 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9294 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9295 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9296 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9297 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9299 /* Enable timestamping of PTP packets. */
9300 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9301 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9303 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9304 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9305 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9307 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9308 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9314 i40e_timesync_disable(struct rte_eth_dev *dev)
9316 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9317 uint32_t tsync_ctl_l;
9318 uint32_t tsync_ctl_h;
9320 /* Disable timestamping of transmitted PTP packets. */
9321 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9322 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9324 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9325 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9327 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9328 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9330 /* Reset the timesync increment value. */
9331 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9332 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9338 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9339 struct timespec *timestamp, uint32_t flags)
9341 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9342 struct i40e_adapter *adapter =
9343 (struct i40e_adapter *)dev->data->dev_private;
9345 uint32_t sync_status;
9346 uint32_t index = flags & 0x03;
9347 uint64_t rx_tstamp_cycles;
9350 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9351 if ((sync_status & (1 << index)) == 0)
9354 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9355 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9356 *timestamp = rte_ns_to_timespec(ns);
9362 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9363 struct timespec *timestamp)
9365 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9366 struct i40e_adapter *adapter =
9367 (struct i40e_adapter *)dev->data->dev_private;
9369 uint32_t sync_status;
9370 uint64_t tx_tstamp_cycles;
9373 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9374 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9377 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9378 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9379 *timestamp = rte_ns_to_timespec(ns);
9385 * i40e_parse_dcb_configure - parse dcb configure from user
9386 * @dev: the device being configured
9387 * @dcb_cfg: pointer of the result of parse
9388 * @*tc_map: bit map of enabled traffic classes
9390 * Returns 0 on success, negative value on failure
9393 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9394 struct i40e_dcbx_config *dcb_cfg,
9397 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9398 uint8_t i, tc_bw, bw_lf;
9400 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9402 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9403 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9404 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9408 /* assume each tc has the same bw */
9409 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9410 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9411 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9412 /* to ensure the sum of tcbw is equal to 100 */
9413 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9414 for (i = 0; i < bw_lf; i++)
9415 dcb_cfg->etscfg.tcbwtable[i]++;
9417 /* assume each tc has the same Transmission Selection Algorithm */
9418 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9419 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9421 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9422 dcb_cfg->etscfg.prioritytable[i] =
9423 dcb_rx_conf->dcb_tc[i];
9425 /* FW needs one App to configure HW */
9426 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9427 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9428 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9429 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9431 if (dcb_rx_conf->nb_tcs == 0)
9432 *tc_map = 1; /* tc0 only */
9434 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9436 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9437 dcb_cfg->pfc.willing = 0;
9438 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9439 dcb_cfg->pfc.pfcenable = *tc_map;
9445 static enum i40e_status_code
9446 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9447 struct i40e_aqc_vsi_properties_data *info,
9448 uint8_t enabled_tcmap)
9450 enum i40e_status_code ret;
9451 int i, total_tc = 0;
9452 uint16_t qpnum_per_tc, bsf, qp_idx;
9453 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9454 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9455 uint16_t used_queues;
9457 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9458 if (ret != I40E_SUCCESS)
9461 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9462 if (enabled_tcmap & (1 << i))
9467 vsi->enabled_tc = enabled_tcmap;
9469 /* different VSI has different queues assigned */
9470 if (vsi->type == I40E_VSI_MAIN)
9471 used_queues = dev_data->nb_rx_queues -
9472 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9473 else if (vsi->type == I40E_VSI_VMDQ2)
9474 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9476 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9477 return I40E_ERR_NO_AVAILABLE_VSI;
9480 qpnum_per_tc = used_queues / total_tc;
9481 /* Number of queues per enabled TC */
9482 if (qpnum_per_tc == 0) {
9483 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9484 return I40E_ERR_INVALID_QP_ID;
9486 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9488 bsf = rte_bsf32(qpnum_per_tc);
9491 * Configure TC and queue mapping parameters, for enabled TC,
9492 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9493 * default queue will serve it.
9496 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9497 if (vsi->enabled_tc & (1 << i)) {
9498 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9499 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9500 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9501 qp_idx += qpnum_per_tc;
9503 info->tc_mapping[i] = 0;
9506 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9507 if (vsi->type == I40E_VSI_SRIOV) {
9508 info->mapping_flags |=
9509 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9510 for (i = 0; i < vsi->nb_qps; i++)
9511 info->queue_mapping[i] =
9512 rte_cpu_to_le_16(vsi->base_queue + i);
9514 info->mapping_flags |=
9515 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9516 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9518 info->valid_sections |=
9519 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9521 return I40E_SUCCESS;
9525 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9526 * @veb: VEB to be configured
9527 * @tc_map: enabled TC bitmap
9529 * Returns 0 on success, negative value on failure
9531 static enum i40e_status_code
9532 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9534 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9535 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9536 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9537 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9538 enum i40e_status_code ret = I40E_SUCCESS;
9542 /* Check if enabled_tc is same as existing or new TCs */
9543 if (veb->enabled_tc == tc_map)
9546 /* configure tc bandwidth */
9547 memset(&veb_bw, 0, sizeof(veb_bw));
9548 veb_bw.tc_valid_bits = tc_map;
9549 /* Enable ETS TCs with equal BW Share for now across all VSIs */
9550 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9551 if (tc_map & BIT_ULL(i))
9552 veb_bw.tc_bw_share_credits[i] = 1;
9554 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
9558 "AQ command Config switch_comp BW allocation per TC failed = %d",
9559 hw->aq.asq_last_status);
9563 memset(&ets_query, 0, sizeof(ets_query));
9564 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9566 if (ret != I40E_SUCCESS) {
9568 "Failed to get switch_comp ETS configuration %u",
9569 hw->aq.asq_last_status);
9572 memset(&bw_query, 0, sizeof(bw_query));
9573 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9575 if (ret != I40E_SUCCESS) {
9577 "Failed to get switch_comp bandwidth configuration %u",
9578 hw->aq.asq_last_status);
9582 /* store and print out BW info */
9583 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
9584 veb->bw_info.bw_max = ets_query.tc_bw_max;
9585 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
9586 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
9587 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
9588 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
9590 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9591 veb->bw_info.bw_ets_share_credits[i] =
9592 bw_query.tc_bw_share_credits[i];
9593 veb->bw_info.bw_ets_credits[i] =
9594 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
9595 /* 4 bits per TC, 4th bit is reserved */
9596 veb->bw_info.bw_ets_max[i] =
9597 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
9598 RTE_LEN2MASK(3, uint8_t));
9599 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
9600 veb->bw_info.bw_ets_share_credits[i]);
9601 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
9602 veb->bw_info.bw_ets_credits[i]);
9603 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
9604 veb->bw_info.bw_ets_max[i]);
9607 veb->enabled_tc = tc_map;
9614 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
9615 * @vsi: VSI to be configured
9616 * @tc_map: enabled TC bitmap
9618 * Returns 0 on success, negative value on failure
9620 static enum i40e_status_code
9621 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
9623 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
9624 struct i40e_vsi_context ctxt;
9625 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
9626 enum i40e_status_code ret = I40E_SUCCESS;
9629 /* Check if enabled_tc is same as existing or new TCs */
9630 if (vsi->enabled_tc == tc_map)
9633 /* configure tc bandwidth */
9634 memset(&bw_data, 0, sizeof(bw_data));
9635 bw_data.tc_valid_bits = tc_map;
9636 /* Enable ETS TCs with equal BW Share for now across all VSIs */
9637 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9638 if (tc_map & BIT_ULL(i))
9639 bw_data.tc_bw_credits[i] = 1;
9641 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
9644 "AQ command Config VSI BW allocation per TC failed = %d",
9645 hw->aq.asq_last_status);
9648 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
9649 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
9651 /* Update Queue Pairs Mapping for currently enabled UPs */
9652 ctxt.seid = vsi->seid;
9653 ctxt.pf_num = hw->pf_id;
9655 ctxt.uplink_seid = vsi->uplink_seid;
9656 ctxt.info = vsi->info;
9658 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
9662 /* Update the VSI after updating the VSI queue-mapping information */
9663 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9665 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
9666 hw->aq.asq_last_status);
9669 /* update the local VSI info with updated queue map */
9670 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
9671 sizeof(vsi->info.tc_mapping));
9672 (void)rte_memcpy(&vsi->info.queue_mapping,
9673 &ctxt.info.queue_mapping,
9674 sizeof(vsi->info.queue_mapping));
9675 vsi->info.mapping_flags = ctxt.info.mapping_flags;
9676 vsi->info.valid_sections = 0;
9678 /* query and update current VSI BW information */
9679 ret = i40e_vsi_get_bw_config(vsi);
9682 "Failed updating vsi bw info, err %s aq_err %s",
9683 i40e_stat_str(hw, ret),
9684 i40e_aq_str(hw, hw->aq.asq_last_status));
9688 vsi->enabled_tc = tc_map;
9695 * i40e_dcb_hw_configure - program the dcb setting to hw
9696 * @pf: pf the configuration is taken on
9697 * @new_cfg: new configuration
9698 * @tc_map: enabled TC bitmap
9700 * Returns 0 on success, negative value on failure
9702 static enum i40e_status_code
9703 i40e_dcb_hw_configure(struct i40e_pf *pf,
9704 struct i40e_dcbx_config *new_cfg,
9707 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9708 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9709 struct i40e_vsi *main_vsi = pf->main_vsi;
9710 struct i40e_vsi_list *vsi_list;
9711 enum i40e_status_code ret;
9715 /* Use the FW API if FW > v4.4*/
9716 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9717 (hw->aq.fw_maj_ver >= 5))) {
9719 "FW < v4.4, can not use FW LLDP API to configure DCB");
9720 return I40E_ERR_FIRMWARE_API_VERSION;
9723 /* Check if need reconfiguration */
9724 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9725 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9726 return I40E_SUCCESS;
9729 /* Copy the new config to the current config */
9730 *old_cfg = *new_cfg;
9731 old_cfg->etsrec = old_cfg->etscfg;
9732 ret = i40e_set_dcb_config(hw);
9735 "Set DCB Config failed, err %s aq_err %s\n",
9736 i40e_stat_str(hw, ret),
9737 i40e_aq_str(hw, hw->aq.asq_last_status));
9740 /* set receive Arbiter to RR mode and ETS scheme by default */
9741 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9742 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9743 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
9744 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9745 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9746 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9747 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9748 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9749 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9750 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9751 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9752 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9753 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9755 /* get local mib to check whether it is configured correctly */
9757 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9758 /* Get Local DCB Config */
9759 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9760 &hw->local_dcbx_config);
9762 /* if Veb is created, need to update TC of it at first */
9763 if (main_vsi->veb) {
9764 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
9766 PMD_INIT_LOG(WARNING,
9767 "Failed configuring TC for VEB seid=%d\n",
9768 main_vsi->veb->seid);
9770 /* Update each VSI */
9771 i40e_vsi_config_tc(main_vsi, tc_map);
9772 if (main_vsi->veb) {
9773 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
9774 /* Beside main VSI and VMDQ VSIs, only enable default
9777 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
9778 ret = i40e_vsi_config_tc(vsi_list->vsi,
9781 ret = i40e_vsi_config_tc(vsi_list->vsi,
9782 I40E_DEFAULT_TCMAP);
9784 PMD_INIT_LOG(WARNING,
9785 "Failed configuring TC for VSI seid=%d\n",
9786 vsi_list->vsi->seid);
9790 return I40E_SUCCESS;
9794 * i40e_dcb_init_configure - initial dcb config
9795 * @dev: device being configured
9796 * @sw_dcb: indicate whether dcb is sw configured or hw offload
9798 * Returns 0 on success, negative value on failure
9801 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
9803 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9804 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9807 if ((pf->flags & I40E_FLAG_DCB) == 0) {
9808 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9812 /* DCB initialization:
9813 * Update DCB configuration from the Firmware and configure
9814 * LLDP MIB change event.
9816 if (sw_dcb == TRUE) {
9817 ret = i40e_init_dcb(hw);
9818 /* If lldp agent is stopped, the return value from
9819 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
9820 * adminq status. Otherwise, it should return success.
9822 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
9823 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
9824 memset(&hw->local_dcbx_config, 0,
9825 sizeof(struct i40e_dcbx_config));
9826 /* set dcb default configuration */
9827 hw->local_dcbx_config.etscfg.willing = 0;
9828 hw->local_dcbx_config.etscfg.maxtcs = 0;
9829 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
9830 hw->local_dcbx_config.etscfg.tsatable[0] =
9832 hw->local_dcbx_config.etsrec =
9833 hw->local_dcbx_config.etscfg;
9834 hw->local_dcbx_config.pfc.willing = 0;
9835 hw->local_dcbx_config.pfc.pfccap =
9836 I40E_MAX_TRAFFIC_CLASS;
9837 /* FW needs one App to configure HW */
9838 hw->local_dcbx_config.numapps = 1;
9839 hw->local_dcbx_config.app[0].selector =
9840 I40E_APP_SEL_ETHTYPE;
9841 hw->local_dcbx_config.app[0].priority = 3;
9842 hw->local_dcbx_config.app[0].protocolid =
9843 I40E_APP_PROTOID_FCOE;
9844 ret = i40e_set_dcb_config(hw);
9847 "default dcb config fails. err = %d, aq_err = %d.",
9848 ret, hw->aq.asq_last_status);
9853 "DCB initialization in FW fails, err = %d, aq_err = %d.",
9854 ret, hw->aq.asq_last_status);
9858 ret = i40e_aq_start_lldp(hw, NULL);
9859 if (ret != I40E_SUCCESS)
9860 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9862 ret = i40e_init_dcb(hw);
9864 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9866 "HW doesn't support DCBX offload.");
9871 "DCBX configuration failed, err = %d, aq_err = %d.",
9872 ret, hw->aq.asq_last_status);
9880 * i40e_dcb_setup - setup dcb related config
9881 * @dev: device being configured
9883 * Returns 0 on success, negative value on failure
9886 i40e_dcb_setup(struct rte_eth_dev *dev)
9888 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9889 struct i40e_dcbx_config dcb_cfg;
9893 if ((pf->flags & I40E_FLAG_DCB) == 0) {
9894 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9898 if (pf->vf_num != 0)
9899 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9901 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9903 PMD_INIT_LOG(ERR, "invalid dcb config");
9906 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9908 PMD_INIT_LOG(ERR, "dcb sw configure fails");
9916 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
9917 struct rte_eth_dcb_info *dcb_info)
9919 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9920 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9921 struct i40e_vsi *vsi = pf->main_vsi;
9922 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
9923 uint16_t bsf, tc_mapping;
9926 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
9927 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
9929 dcb_info->nb_tcs = 1;
9930 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9931 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
9932 for (i = 0; i < dcb_info->nb_tcs; i++)
9933 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
9935 /* get queue mapping if vmdq is disabled */
9936 if (!pf->nb_cfg_vmdq_vsi) {
9937 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9938 if (!(vsi->enabled_tc & (1 << i)))
9940 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9941 dcb_info->tc_queue.tc_rxq[j][i].base =
9942 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9943 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9944 dcb_info->tc_queue.tc_txq[j][i].base =
9945 dcb_info->tc_queue.tc_rxq[j][i].base;
9946 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9947 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9948 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9949 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9950 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9955 /* get queue mapping if vmdq is enabled */
9957 vsi = pf->vmdq[j].vsi;
9958 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9959 if (!(vsi->enabled_tc & (1 << i)))
9961 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9962 dcb_info->tc_queue.tc_rxq[j][i].base =
9963 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9964 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9965 dcb_info->tc_queue.tc_txq[j][i].base =
9966 dcb_info->tc_queue.tc_rxq[j][i].base;
9967 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9968 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9969 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9970 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9971 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9974 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
9979 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
9981 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
9982 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
9983 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9985 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
9988 msix_intr = intr_handle->intr_vec[queue_id];
9989 if (msix_intr == I40E_MISC_VEC_ID)
9990 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
9991 I40E_PFINT_DYN_CTLN_INTENA_MASK |
9992 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9993 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9995 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9998 I40E_PFINT_DYN_CTLN(msix_intr -
10000 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10001 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10002 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10004 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10006 I40E_WRITE_FLUSH(hw);
10007 rte_intr_enable(&pci_dev->intr_handle);
10013 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10015 struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10016 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10017 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10018 uint16_t msix_intr;
10020 msix_intr = intr_handle->intr_vec[queue_id];
10021 if (msix_intr == I40E_MISC_VEC_ID)
10022 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10025 I40E_PFINT_DYN_CTLN(msix_intr -
10026 I40E_RX_VEC_START),
10028 I40E_WRITE_FLUSH(hw);
10033 static int i40e_get_regs(struct rte_eth_dev *dev,
10034 struct rte_dev_reg_info *regs)
10036 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10037 uint32_t *ptr_data = regs->data;
10038 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10039 const struct i40e_reg_info *reg_info;
10041 if (ptr_data == NULL) {
10042 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10043 regs->width = sizeof(uint32_t);
10047 /* The first few registers have to be read using AQ operations */
10049 while (i40e_regs_adminq[reg_idx].name) {
10050 reg_info = &i40e_regs_adminq[reg_idx++];
10051 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10053 arr_idx2 <= reg_info->count2;
10055 reg_offset = arr_idx * reg_info->stride1 +
10056 arr_idx2 * reg_info->stride2;
10057 reg_offset += reg_info->base_addr;
10058 ptr_data[reg_offset >> 2] =
10059 i40e_read_rx_ctl(hw, reg_offset);
10063 /* The remaining registers can be read using primitives */
10065 while (i40e_regs_others[reg_idx].name) {
10066 reg_info = &i40e_regs_others[reg_idx++];
10067 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10069 arr_idx2 <= reg_info->count2;
10071 reg_offset = arr_idx * reg_info->stride1 +
10072 arr_idx2 * reg_info->stride2;
10073 reg_offset += reg_info->base_addr;
10074 ptr_data[reg_offset >> 2] =
10075 I40E_READ_REG(hw, reg_offset);
10082 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10084 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10086 /* Convert word count to byte count */
10087 return hw->nvm.sr_size << 1;
10090 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10091 struct rte_dev_eeprom_info *eeprom)
10093 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10094 uint16_t *data = eeprom->data;
10095 uint16_t offset, length, cnt_words;
10098 offset = eeprom->offset >> 1;
10099 length = eeprom->length >> 1;
10100 cnt_words = length;
10102 if (offset > hw->nvm.sr_size ||
10103 offset + length > hw->nvm.sr_size) {
10104 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10108 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10110 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10111 if (ret_code != I40E_SUCCESS || cnt_words != length) {
10112 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10119 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10120 struct ether_addr *mac_addr)
10122 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10124 if (!is_valid_assigned_ether_addr(mac_addr)) {
10125 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10129 /* Flags: 0x3 updates port address */
10130 i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10134 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10136 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10137 struct rte_eth_dev_data *dev_data = pf->dev_data;
10138 uint32_t frame_size = mtu + ETHER_HDR_LEN
10139 + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
10142 /* check if mtu is within the allowed range */
10143 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10146 /* mtu setting is forbidden if port is start */
10147 if (dev_data->dev_started) {
10149 "port %d must be stopped before configuration\n",
10150 dev_data->port_id);
10154 if (frame_size > ETHER_MAX_LEN)
10155 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10157 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10159 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10164 /* Restore ethertype filter */
10166 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10168 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10169 struct i40e_ethertype_filter_list
10170 *ethertype_list = &pf->ethertype.ethertype_list;
10171 struct i40e_ethertype_filter *f;
10172 struct i40e_control_filter_stats stats;
10175 TAILQ_FOREACH(f, ethertype_list, rules) {
10177 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10178 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10179 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10180 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10181 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10183 memset(&stats, 0, sizeof(stats));
10184 i40e_aq_add_rem_control_packet_filter(hw,
10185 f->input.mac_addr.addr_bytes,
10186 f->input.ether_type,
10187 flags, pf->main_vsi->seid,
10188 f->queue, 1, &stats, NULL);
10190 PMD_DRV_LOG(INFO, "Ethertype filter:"
10191 " mac_etype_used = %u, etype_used = %u,"
10192 " mac_etype_free = %u, etype_free = %u\n",
10193 stats.mac_etype_used, stats.etype_used,
10194 stats.mac_etype_free, stats.etype_free);
10197 /* Restore tunnel filter */
10199 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10201 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10202 struct i40e_vsi *vsi = pf->main_vsi;
10203 struct i40e_tunnel_filter_list
10204 *tunnel_list = &pf->tunnel.tunnel_list;
10205 struct i40e_tunnel_filter *f;
10206 struct i40e_aqc_add_remove_cloud_filters_element_data cld_filter;
10208 TAILQ_FOREACH(f, tunnel_list, rules) {
10209 memset(&cld_filter, 0, sizeof(cld_filter));
10210 rte_memcpy(&cld_filter, &f->input, sizeof(f->input));
10211 cld_filter.queue_number = f->queue;
10212 i40e_aq_add_cloud_filters(hw, vsi->seid, &cld_filter, 1);
10217 i40e_filter_restore(struct i40e_pf *pf)
10219 i40e_ethertype_filter_restore(pf);
10220 i40e_tunnel_filter_restore(pf);
10221 i40e_fdir_filter_restore(pf);
10225 is_i40e_pmd(const char *driver_name)
10227 if (!strstr(driver_name, "i40e"))
10230 if (strstr(driver_name, "i40e_vf"))
10237 rte_pmd_i40e_ping_vfs(uint8_t port, uint16_t vf)
10239 struct rte_eth_dev *dev;
10240 struct i40e_pf *pf;
10242 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10244 dev = &rte_eth_devices[port];
10246 if (is_i40e_pmd(dev->data->drv_name))
10249 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10251 if (vf >= pf->vf_num || !pf->vfs) {
10252 PMD_DRV_LOG(ERR, "Invalid argument.");
10256 i40e_notify_vf_link_status(dev, &pf->vfs[vf]);