4 * Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
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14 * notice, this list of conditions and the following disclaimer in
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
44 #include <rte_string_fns.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memzone.h>
49 #include <rte_malloc.h>
50 #include <rte_memcpy.h>
51 #include <rte_alarm.h>
53 #include <rte_eth_ctrl.h>
55 #include "i40e_logs.h"
56 #include "base/i40e_prototype.h"
57 #include "base/i40e_adminq_cmd.h"
58 #include "base/i40e_type.h"
59 #include "base/i40e_register.h"
60 #include "base/i40e_dcb.h"
61 #include "i40e_ethdev.h"
62 #include "i40e_rxtx.h"
64 #include "i40e_regs.h"
66 #define I40E_CLEAR_PXE_WAIT_MS 200
68 /* Maximun number of capability elements */
69 #define I40E_MAX_CAP_ELE_NUM 128
71 /* Wait count and inteval */
72 #define I40E_CHK_Q_ENA_COUNT 1000
73 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
75 /* Maximun number of VSI */
76 #define I40E_MAX_NUM_VSIS (384UL)
78 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
80 /* Flow control default timer */
81 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
83 /* Flow control default high water */
84 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
86 /* Flow control default low water */
87 #define I40E_DEFAULT_LOW_WATER (0x1A40/1024)
89 /* Flow control enable fwd bit */
90 #define I40E_PRTMAC_FWD_CTRL 0x00000001
92 /* Receive Packet Buffer size */
93 #define I40E_RXPBSIZE (968 * 1024)
96 #define I40E_KILOSHIFT 10
98 /* Receive Average Packet Size in Byte*/
99 #define I40E_PACKET_AVERAGE_SIZE 128
101 /* Mask of PF interrupt causes */
102 #define I40E_PFINT_ICR0_ENA_MASK ( \
103 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
104 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
105 I40E_PFINT_ICR0_ENA_GRST_MASK | \
106 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
107 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
108 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
109 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
110 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
111 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
112 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
114 #define I40E_FLOW_TYPES ( \
115 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
116 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
117 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
118 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
119 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
120 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
121 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
122 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
123 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
124 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
125 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
127 /* Additional timesync values. */
128 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
129 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
130 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
131 #define I40E_PRTTSYN_TSYNENA 0x80000000
132 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
133 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
135 #define I40E_MAX_PERCENT 100
136 #define I40E_DEFAULT_DCB_APP_NUM 1
137 #define I40E_DEFAULT_DCB_APP_PRIO 3
139 #define I40E_INSET_NONE 0x00000000000000000ULL
142 #define I40E_INSET_DMAC 0x0000000000000001ULL
143 #define I40E_INSET_SMAC 0x0000000000000002ULL
144 #define I40E_INSET_VLAN_OUTER 0x0000000000000004ULL
145 #define I40E_INSET_VLAN_INNER 0x0000000000000008ULL
146 #define I40E_INSET_VLAN_TUNNEL 0x0000000000000010ULL
149 #define I40E_INSET_IPV4_SRC 0x0000000000000100ULL
150 #define I40E_INSET_IPV4_DST 0x0000000000000200ULL
151 #define I40E_INSET_IPV6_SRC 0x0000000000000400ULL
152 #define I40E_INSET_IPV6_DST 0x0000000000000800ULL
153 #define I40E_INSET_SRC_PORT 0x0000000000001000ULL
154 #define I40E_INSET_DST_PORT 0x0000000000002000ULL
155 #define I40E_INSET_SCTP_VT 0x0000000000004000ULL
157 /* bit 16 ~ bit 31 */
158 #define I40E_INSET_IPV4_TOS 0x0000000000010000ULL
159 #define I40E_INSET_IPV4_PROTO 0x0000000000020000ULL
160 #define I40E_INSET_IPV4_TTL 0x0000000000040000ULL
161 #define I40E_INSET_IPV6_TC 0x0000000000080000ULL
162 #define I40E_INSET_IPV6_FLOW 0x0000000000100000ULL
163 #define I40E_INSET_IPV6_NEXT_HDR 0x0000000000200000ULL
164 #define I40E_INSET_IPV6_HOP_LIMIT 0x0000000000400000ULL
165 #define I40E_INSET_TCP_FLAGS 0x0000000000800000ULL
167 /* bit 32 ~ bit 47, tunnel fields */
168 #define I40E_INSET_TUNNEL_IPV4_DST 0x0000000100000000ULL
169 #define I40E_INSET_TUNNEL_IPV6_DST 0x0000000200000000ULL
170 #define I40E_INSET_TUNNEL_DMAC 0x0000000400000000ULL
171 #define I40E_INSET_TUNNEL_SRC_PORT 0x0000000800000000ULL
172 #define I40E_INSET_TUNNEL_DST_PORT 0x0000001000000000ULL
173 #define I40E_INSET_TUNNEL_ID 0x0000002000000000ULL
175 /* bit 48 ~ bit 55 */
176 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
178 /* bit 56 ~ bit 63, Flex Payload */
179 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
180 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
181 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
182 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
183 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
184 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
185 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
186 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
187 #define I40E_INSET_FLEX_PAYLOAD \
188 (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
189 I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
190 I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
191 I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
194 * Below are values for writing un-exposed registers suggested
197 /* Destination MAC address */
198 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
199 /* Source MAC address */
200 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
201 /* Outer (S-Tag) VLAN tag in the outer L2 header */
202 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0200000000000000ULL
203 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
204 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
205 /* Single VLAN tag in the inner L2 header */
206 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
207 /* Source IPv4 address */
208 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
209 /* Destination IPv4 address */
210 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
211 /* IPv4 Type of Service (TOS) */
212 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
214 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
215 /* IPv4 Time to Live */
216 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
217 /* Source IPv6 address */
218 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
219 /* Destination IPv6 address */
220 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
221 /* IPv6 Traffic Class (TC) */
222 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
223 /* IPv6 Next Header */
224 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
226 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
228 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
229 /* Destination L4 port */
230 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
231 /* SCTP verification tag */
232 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
233 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
234 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
235 /* Source port of tunneling UDP */
236 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
237 /* Destination port of tunneling UDP */
238 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
239 /* UDP Tunneling ID, NVGRE/GRE key */
240 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
241 /* Last ether type */
242 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
243 /* Tunneling outer destination IPv4 address */
244 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
245 /* Tunneling outer destination IPv6 address */
246 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
247 /* 1st word of flex payload */
248 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
249 /* 2nd word of flex payload */
250 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
251 /* 3rd word of flex payload */
252 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
253 /* 4th word of flex payload */
254 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
255 /* 5th word of flex payload */
256 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
257 /* 6th word of flex payload */
258 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
259 /* 7th word of flex payload */
260 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
261 /* 8th word of flex payload */
262 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
263 /* all 8 words flex payload */
264 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
265 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
267 #define I40E_TRANSLATE_INSET 0
268 #define I40E_TRANSLATE_REG 1
270 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
271 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
272 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
273 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
274 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
275 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
277 #define I40E_GL_SWT_L2TAGCTRL(_i) (0x001C0A70 + ((_i) * 4))
278 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
279 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK \
280 I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
282 /* PCI offset for querying capability */
283 #define PCI_DEV_CAP_REG 0xA4
284 /* PCI offset for enabling/disabling Extended Tag */
285 #define PCI_DEV_CTRL_REG 0xA8
286 /* Bit mask of Extended Tag capability */
287 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
288 /* Bit shift of Extended Tag enable/disable */
289 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
290 /* Bit mask of Extended Tag enable/disable */
291 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
293 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
294 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
295 static int i40e_dev_configure(struct rte_eth_dev *dev);
296 static int i40e_dev_start(struct rte_eth_dev *dev);
297 static void i40e_dev_stop(struct rte_eth_dev *dev);
298 static void i40e_dev_close(struct rte_eth_dev *dev);
299 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
300 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
301 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
302 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
303 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
304 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
305 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
306 struct rte_eth_stats *stats);
307 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
308 struct rte_eth_xstat *xstats, unsigned n);
309 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
310 struct rte_eth_xstat_name *xstats_names,
312 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
313 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
317 static void i40e_dev_info_get(struct rte_eth_dev *dev,
318 struct rte_eth_dev_info *dev_info);
319 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
322 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
323 enum rte_vlan_type vlan_type,
325 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
326 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
329 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
330 static int i40e_dev_led_on(struct rte_eth_dev *dev);
331 static int i40e_dev_led_off(struct rte_eth_dev *dev);
332 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
333 struct rte_eth_fc_conf *fc_conf);
334 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
335 struct rte_eth_fc_conf *fc_conf);
336 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
337 struct rte_eth_pfc_conf *pfc_conf);
338 static void i40e_macaddr_add(struct rte_eth_dev *dev,
339 struct ether_addr *mac_addr,
342 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
343 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
344 struct rte_eth_rss_reta_entry64 *reta_conf,
346 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
347 struct rte_eth_rss_reta_entry64 *reta_conf,
350 static int i40e_get_cap(struct i40e_hw *hw);
351 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
352 static int i40e_pf_setup(struct i40e_pf *pf);
353 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
354 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
355 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
356 static int i40e_dcb_setup(struct rte_eth_dev *dev);
357 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
358 bool offset_loaded, uint64_t *offset, uint64_t *stat);
359 static void i40e_stat_update_48(struct i40e_hw *hw,
365 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
366 static void i40e_dev_interrupt_handler(
367 __rte_unused struct rte_intr_handle *handle, void *param);
368 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
369 uint32_t base, uint32_t num);
370 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
371 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
373 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
375 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
376 static int i40e_veb_release(struct i40e_veb *veb);
377 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
378 struct i40e_vsi *vsi);
379 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
380 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
381 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
382 struct i40e_macvlan_filter *mv_f,
384 struct ether_addr *addr);
385 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
386 struct i40e_macvlan_filter *mv_f,
389 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
390 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
391 struct rte_eth_rss_conf *rss_conf);
392 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
393 struct rte_eth_rss_conf *rss_conf);
394 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
395 struct rte_eth_udp_tunnel *udp_tunnel);
396 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
397 struct rte_eth_udp_tunnel *udp_tunnel);
398 static void i40e_filter_input_set_init(struct i40e_pf *pf);
399 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
400 struct rte_eth_ethertype_filter *filter,
402 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
403 enum rte_filter_op filter_op,
405 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
406 enum rte_filter_type filter_type,
407 enum rte_filter_op filter_op,
409 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
410 struct rte_eth_dcb_info *dcb_info);
411 static void i40e_configure_registers(struct i40e_hw *hw);
412 static void i40e_hw_init(struct rte_eth_dev *dev);
413 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
414 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
415 struct rte_eth_mirror_conf *mirror_conf,
416 uint8_t sw_id, uint8_t on);
417 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
419 static int i40e_timesync_enable(struct rte_eth_dev *dev);
420 static int i40e_timesync_disable(struct rte_eth_dev *dev);
421 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
422 struct timespec *timestamp,
424 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
425 struct timespec *timestamp);
426 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
428 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
430 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
431 struct timespec *timestamp);
432 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
433 const struct timespec *timestamp);
435 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
437 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
440 static int i40e_get_reg_length(struct rte_eth_dev *dev);
442 static int i40e_get_regs(struct rte_eth_dev *dev,
443 struct rte_dev_reg_info *regs);
445 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
447 static int i40e_get_eeprom(struct rte_eth_dev *dev,
448 struct rte_dev_eeprom_info *eeprom);
450 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
451 struct ether_addr *mac_addr);
453 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
455 static const struct rte_pci_id pci_id_i40e_map[] = {
456 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
457 #include "rte_pci_dev_ids.h"
458 { .vendor_id = 0, /* sentinel */ },
461 static const struct eth_dev_ops i40e_eth_dev_ops = {
462 .dev_configure = i40e_dev_configure,
463 .dev_start = i40e_dev_start,
464 .dev_stop = i40e_dev_stop,
465 .dev_close = i40e_dev_close,
466 .promiscuous_enable = i40e_dev_promiscuous_enable,
467 .promiscuous_disable = i40e_dev_promiscuous_disable,
468 .allmulticast_enable = i40e_dev_allmulticast_enable,
469 .allmulticast_disable = i40e_dev_allmulticast_disable,
470 .dev_set_link_up = i40e_dev_set_link_up,
471 .dev_set_link_down = i40e_dev_set_link_down,
472 .link_update = i40e_dev_link_update,
473 .stats_get = i40e_dev_stats_get,
474 .xstats_get = i40e_dev_xstats_get,
475 .xstats_get_names = i40e_dev_xstats_get_names,
476 .stats_reset = i40e_dev_stats_reset,
477 .xstats_reset = i40e_dev_stats_reset,
478 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
479 .dev_infos_get = i40e_dev_info_get,
480 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
481 .vlan_filter_set = i40e_vlan_filter_set,
482 .vlan_tpid_set = i40e_vlan_tpid_set,
483 .vlan_offload_set = i40e_vlan_offload_set,
484 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
485 .vlan_pvid_set = i40e_vlan_pvid_set,
486 .rx_queue_start = i40e_dev_rx_queue_start,
487 .rx_queue_stop = i40e_dev_rx_queue_stop,
488 .tx_queue_start = i40e_dev_tx_queue_start,
489 .tx_queue_stop = i40e_dev_tx_queue_stop,
490 .rx_queue_setup = i40e_dev_rx_queue_setup,
491 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
492 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
493 .rx_queue_release = i40e_dev_rx_queue_release,
494 .rx_queue_count = i40e_dev_rx_queue_count,
495 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
496 .tx_queue_setup = i40e_dev_tx_queue_setup,
497 .tx_queue_release = i40e_dev_tx_queue_release,
498 .dev_led_on = i40e_dev_led_on,
499 .dev_led_off = i40e_dev_led_off,
500 .flow_ctrl_get = i40e_flow_ctrl_get,
501 .flow_ctrl_set = i40e_flow_ctrl_set,
502 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
503 .mac_addr_add = i40e_macaddr_add,
504 .mac_addr_remove = i40e_macaddr_remove,
505 .reta_update = i40e_dev_rss_reta_update,
506 .reta_query = i40e_dev_rss_reta_query,
507 .rss_hash_update = i40e_dev_rss_hash_update,
508 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
509 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
510 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
511 .filter_ctrl = i40e_dev_filter_ctrl,
512 .rxq_info_get = i40e_rxq_info_get,
513 .txq_info_get = i40e_txq_info_get,
514 .mirror_rule_set = i40e_mirror_rule_set,
515 .mirror_rule_reset = i40e_mirror_rule_reset,
516 .timesync_enable = i40e_timesync_enable,
517 .timesync_disable = i40e_timesync_disable,
518 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
519 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
520 .get_dcb_info = i40e_dev_get_dcb_info,
521 .timesync_adjust_time = i40e_timesync_adjust_time,
522 .timesync_read_time = i40e_timesync_read_time,
523 .timesync_write_time = i40e_timesync_write_time,
524 .get_reg_length = i40e_get_reg_length,
525 .get_reg = i40e_get_regs,
526 .get_eeprom_length = i40e_get_eeprom_length,
527 .get_eeprom = i40e_get_eeprom,
528 .mac_addr_set = i40e_set_default_mac_addr,
529 .mtu_set = i40e_dev_mtu_set,
532 /* store statistics names and its offset in stats structure */
533 struct rte_i40e_xstats_name_off {
534 char name[RTE_ETH_XSTATS_NAME_SIZE];
538 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
539 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
540 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
541 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
542 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
543 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
544 rx_unknown_protocol)},
545 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
546 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
547 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
548 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
551 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
552 sizeof(rte_i40e_stats_strings[0]))
554 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
555 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
556 tx_dropped_link_down)},
557 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
558 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
560 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
561 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
563 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
565 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
567 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
568 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
569 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
570 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
571 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
572 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
574 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
576 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
578 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
580 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
582 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
584 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
586 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
588 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
589 mac_short_packet_dropped)},
590 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
592 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
593 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
594 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
596 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
598 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
600 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
602 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
604 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
606 {"rx_flow_director_atr_match_packets",
607 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
608 {"rx_flow_director_sb_match_packets",
609 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
610 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
612 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
614 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
616 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
620 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
621 sizeof(rte_i40e_hw_port_strings[0]))
623 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
624 {"xon_packets", offsetof(struct i40e_hw_port_stats,
626 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
630 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
631 sizeof(rte_i40e_rxq_prio_strings[0]))
633 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
634 {"xon_packets", offsetof(struct i40e_hw_port_stats,
636 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
638 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
639 priority_xon_2_xoff)},
642 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
643 sizeof(rte_i40e_txq_prio_strings[0]))
645 static struct eth_driver rte_i40e_pmd = {
647 .name = "rte_i40e_pmd",
648 .id_table = pci_id_i40e_map,
649 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
650 RTE_PCI_DRV_DETACHABLE,
652 .eth_dev_init = eth_i40e_dev_init,
653 .eth_dev_uninit = eth_i40e_dev_uninit,
654 .dev_private_size = sizeof(struct i40e_adapter),
658 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
659 struct rte_eth_link *link)
661 struct rte_eth_link *dst = link;
662 struct rte_eth_link *src = &(dev->data->dev_link);
664 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
665 *(uint64_t *)src) == 0)
672 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
673 struct rte_eth_link *link)
675 struct rte_eth_link *dst = &(dev->data->dev_link);
676 struct rte_eth_link *src = link;
678 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
679 *(uint64_t *)src) == 0)
686 * Driver initialization routine.
687 * Invoked once at EAL init time.
688 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
691 rte_i40e_pmd_init(const char *name __rte_unused,
692 const char *params __rte_unused)
694 PMD_INIT_FUNC_TRACE();
695 rte_eth_driver_register(&rte_i40e_pmd);
700 static struct rte_driver rte_i40e_driver = {
702 .init = rte_i40e_pmd_init,
705 PMD_REGISTER_DRIVER(rte_i40e_driver);
708 * Initialize registers for flexible payload, which should be set by NVM.
709 * This should be removed from code once it is fixed in NVM.
711 #ifndef I40E_GLQF_ORT
712 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
714 #ifndef I40E_GLQF_PIT
715 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
718 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
720 I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
721 I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
722 I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
723 I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
724 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
725 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
726 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
727 I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
728 I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
729 I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
731 /* GLQF_PIT Registers */
732 I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
733 I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
736 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
739 * Add a ethertype filter to drop all flow control frames transmitted
743 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
745 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
746 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
747 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
748 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
751 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
752 I40E_FLOW_CONTROL_ETHERTYPE, flags,
753 pf->main_vsi_seid, 0,
756 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
757 " frames from VSIs.");
761 eth_i40e_dev_init(struct rte_eth_dev *dev)
763 struct rte_pci_device *pci_dev;
764 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
765 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
766 struct i40e_vsi *vsi;
771 PMD_INIT_FUNC_TRACE();
773 dev->dev_ops = &i40e_eth_dev_ops;
774 dev->rx_pkt_burst = i40e_recv_pkts;
775 dev->tx_pkt_burst = i40e_xmit_pkts;
777 /* for secondary processes, we don't initialise any further as primary
778 * has already done this work. Only check we don't need a different
780 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
781 i40e_set_rx_function(dev);
782 i40e_set_tx_function(dev);
785 pci_dev = dev->pci_dev;
787 rte_eth_copy_pci_info(dev, pci_dev);
789 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
790 pf->adapter->eth_dev = dev;
791 pf->dev_data = dev->data;
793 hw->back = I40E_PF_TO_ADAPTER(pf);
794 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
796 PMD_INIT_LOG(ERR, "Hardware is not available, "
797 "as address is NULL");
801 hw->vendor_id = pci_dev->id.vendor_id;
802 hw->device_id = pci_dev->id.device_id;
803 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
804 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
805 hw->bus.device = pci_dev->addr.devid;
806 hw->bus.func = pci_dev->addr.function;
807 hw->adapter_stopped = 0;
809 /* Make sure all is clean before doing PF reset */
812 /* Initialize the hardware */
815 /* Reset here to make sure all is clean for each PF */
816 ret = i40e_pf_reset(hw);
818 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
822 /* Initialize the shared code (base driver) */
823 ret = i40e_init_shared_code(hw);
825 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
830 * To work around the NVM issue,initialize registers
831 * for flexible payload by software.
832 * It should be removed once issues are fixed in NVM.
834 i40e_flex_payload_reg_init(hw);
836 /* Initialize the input set for filters (hash and fd) to default value */
837 i40e_filter_input_set_init(pf);
839 /* Initialize the parameters for adminq */
840 i40e_init_adminq_parameter(hw);
841 ret = i40e_init_adminq(hw);
842 if (ret != I40E_SUCCESS) {
843 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
846 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
847 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
848 hw->aq.api_maj_ver, hw->aq.api_min_ver,
849 ((hw->nvm.version >> 12) & 0xf),
850 ((hw->nvm.version >> 4) & 0xff),
851 (hw->nvm.version & 0xf), hw->nvm.eetrack);
854 i40e_clear_pxe_mode(hw);
857 * On X710, performance number is far from the expectation on recent
858 * firmware versions. The fix for this issue may not be integrated in
859 * the following firmware version. So the workaround in software driver
860 * is needed. It needs to modify the initial values of 3 internal only
861 * registers. Note that the workaround can be removed when it is fixed
862 * in firmware in the future.
864 i40e_configure_registers(hw);
866 /* Get hw capabilities */
867 ret = i40e_get_cap(hw);
868 if (ret != I40E_SUCCESS) {
869 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
870 goto err_get_capabilities;
873 /* Initialize parameters for PF */
874 ret = i40e_pf_parameter_init(dev);
876 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
877 goto err_parameter_init;
880 /* Initialize the queue management */
881 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
883 PMD_INIT_LOG(ERR, "Failed to init queue pool");
884 goto err_qp_pool_init;
886 ret = i40e_res_pool_init(&pf->msix_pool, 1,
887 hw->func_caps.num_msix_vectors - 1);
889 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
890 goto err_msix_pool_init;
893 /* Initialize lan hmc */
894 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
895 hw->func_caps.num_rx_qp, 0, 0);
896 if (ret != I40E_SUCCESS) {
897 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
898 goto err_init_lan_hmc;
901 /* Configure lan hmc */
902 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
903 if (ret != I40E_SUCCESS) {
904 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
905 goto err_configure_lan_hmc;
908 /* Get and check the mac address */
909 i40e_get_mac_addr(hw, hw->mac.addr);
910 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
911 PMD_INIT_LOG(ERR, "mac address is not valid");
913 goto err_get_mac_addr;
915 /* Copy the permanent MAC address */
916 ether_addr_copy((struct ether_addr *) hw->mac.addr,
917 (struct ether_addr *) hw->mac.perm_addr);
919 /* Disable flow control */
920 hw->fc.requested_mode = I40E_FC_NONE;
921 i40e_set_fc(hw, &aq_fail, TRUE);
923 /* Set the global registers with default ether type value */
924 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
925 if (ret != I40E_SUCCESS) {
926 PMD_INIT_LOG(ERR, "Failed to set the default outer "
928 goto err_setup_pf_switch;
931 /* PF setup, which includes VSI setup */
932 ret = i40e_pf_setup(pf);
934 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
935 goto err_setup_pf_switch;
938 /* reset all stats of the device, including pf and main vsi */
939 i40e_dev_stats_reset(dev);
943 /* Disable double vlan by default */
944 i40e_vsi_config_double_vlan(vsi, FALSE);
946 if (!vsi->max_macaddrs)
947 len = ETHER_ADDR_LEN;
949 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
951 /* Should be after VSI initialized */
952 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
953 if (!dev->data->mac_addrs) {
954 PMD_INIT_LOG(ERR, "Failed to allocated memory "
955 "for storing mac address");
958 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
959 &dev->data->mac_addrs[0]);
961 /* initialize pf host driver to setup SRIOV resource if applicable */
962 i40e_pf_host_init(dev);
964 /* register callback func to eal lib */
965 rte_intr_callback_register(&(pci_dev->intr_handle),
966 i40e_dev_interrupt_handler, (void *)dev);
968 /* configure and enable device interrupt */
969 i40e_pf_config_irq0(hw, TRUE);
970 i40e_pf_enable_irq0(hw);
972 /* enable uio intr after callback register */
973 rte_intr_enable(&(pci_dev->intr_handle));
975 * Add an ethertype filter to drop all flow control frames transmitted
976 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
979 i40e_add_tx_flow_control_drop_filter(pf);
981 /* Set the max frame size to 0x2600 by default,
982 * in case other drivers changed the default value.
984 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
986 /* initialize mirror rule list */
987 TAILQ_INIT(&pf->mirror_list);
989 /* Init dcb to sw mode by default */
990 ret = i40e_dcb_init_configure(dev, TRUE);
991 if (ret != I40E_SUCCESS) {
992 PMD_INIT_LOG(INFO, "Failed to init dcb.");
993 pf->flags &= ~I40E_FLAG_DCB;
999 i40e_vsi_release(pf->main_vsi);
1000 err_setup_pf_switch:
1002 err_configure_lan_hmc:
1003 (void)i40e_shutdown_lan_hmc(hw);
1005 i40e_res_pool_destroy(&pf->msix_pool);
1007 i40e_res_pool_destroy(&pf->qp_pool);
1010 err_get_capabilities:
1011 (void)i40e_shutdown_adminq(hw);
1017 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1019 struct rte_pci_device *pci_dev;
1021 struct i40e_filter_control_settings settings;
1023 uint8_t aq_fail = 0;
1025 PMD_INIT_FUNC_TRACE();
1027 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1030 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1031 pci_dev = dev->pci_dev;
1033 if (hw->adapter_stopped == 0)
1034 i40e_dev_close(dev);
1036 dev->dev_ops = NULL;
1037 dev->rx_pkt_burst = NULL;
1038 dev->tx_pkt_burst = NULL;
1041 ret = i40e_aq_stop_lldp(hw, true, NULL);
1042 if (ret != I40E_SUCCESS) /* Its failure can be ignored */
1043 PMD_INIT_LOG(INFO, "Failed to stop lldp");
1045 /* Clear PXE mode */
1046 i40e_clear_pxe_mode(hw);
1048 /* Unconfigure filter control */
1049 memset(&settings, 0, sizeof(settings));
1050 ret = i40e_set_filter_control(hw, &settings);
1052 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1055 /* Disable flow control */
1056 hw->fc.requested_mode = I40E_FC_NONE;
1057 i40e_set_fc(hw, &aq_fail, TRUE);
1059 /* uninitialize pf host driver */
1060 i40e_pf_host_uninit(dev);
1062 rte_free(dev->data->mac_addrs);
1063 dev->data->mac_addrs = NULL;
1065 /* disable uio intr before callback unregister */
1066 rte_intr_disable(&(pci_dev->intr_handle));
1068 /* register callback func to eal lib */
1069 rte_intr_callback_unregister(&(pci_dev->intr_handle),
1070 i40e_dev_interrupt_handler, (void *)dev);
1076 i40e_dev_configure(struct rte_eth_dev *dev)
1078 struct i40e_adapter *ad =
1079 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1080 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1081 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1084 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1085 * bulk allocation or vector Rx preconditions we will reset it.
1087 ad->rx_bulk_alloc_allowed = true;
1088 ad->rx_vec_allowed = true;
1089 ad->tx_simple_allowed = true;
1090 ad->tx_vec_allowed = true;
1092 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1093 ret = i40e_fdir_setup(pf);
1094 if (ret != I40E_SUCCESS) {
1095 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1098 ret = i40e_fdir_configure(dev);
1100 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1104 i40e_fdir_teardown(pf);
1106 ret = i40e_dev_init_vlan(dev);
1111 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1112 * RSS setting have different requirements.
1113 * General PMD driver call sequence are NIC init, configure,
1114 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1115 * will try to lookup the VSI that specific queue belongs to if VMDQ
1116 * applicable. So, VMDQ setting has to be done before
1117 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1118 * For RSS setting, it will try to calculate actual configured RX queue
1119 * number, which will be available after rx_queue_setup(). dev_start()
1120 * function is good to place RSS setup.
1122 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1123 ret = i40e_vmdq_setup(dev);
1128 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1129 ret = i40e_dcb_setup(dev);
1131 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1139 /* need to release vmdq resource if exists */
1140 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1141 i40e_vsi_release(pf->vmdq[i].vsi);
1142 pf->vmdq[i].vsi = NULL;
1147 /* need to release fdir resource if exists */
1148 i40e_fdir_teardown(pf);
1153 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1155 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1156 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1157 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1158 uint16_t msix_vect = vsi->msix_intr;
1161 for (i = 0; i < vsi->nb_qps; i++) {
1162 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1163 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1167 if (vsi->type != I40E_VSI_SRIOV) {
1168 if (!rte_intr_allow_others(intr_handle)) {
1169 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1170 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1172 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1175 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1176 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1178 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1183 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1184 vsi->user_param + (msix_vect - 1);
1186 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1187 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1189 I40E_WRITE_FLUSH(hw);
1193 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1194 int base_queue, int nb_queue)
1198 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1200 /* Bind all RX queues to allocated MSIX interrupt */
1201 for (i = 0; i < nb_queue; i++) {
1202 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1203 I40E_QINT_RQCTL_ITR_INDX_MASK |
1204 ((base_queue + i + 1) <<
1205 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1206 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1207 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1209 if (i == nb_queue - 1)
1210 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1211 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1214 /* Write first RX queue to Link list register as the head element */
1215 if (vsi->type != I40E_VSI_SRIOV) {
1217 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1219 if (msix_vect == I40E_MISC_VEC_ID) {
1220 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1222 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1224 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1226 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1229 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1231 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1233 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1235 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1242 if (msix_vect == I40E_MISC_VEC_ID) {
1244 I40E_VPINT_LNKLST0(vsi->user_param),
1246 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1248 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1250 /* num_msix_vectors_vf needs to minus irq0 */
1251 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1252 vsi->user_param + (msix_vect - 1);
1254 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1256 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1258 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1262 I40E_WRITE_FLUSH(hw);
1266 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1268 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1269 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1270 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1271 uint16_t msix_vect = vsi->msix_intr;
1272 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1273 uint16_t queue_idx = 0;
1278 for (i = 0; i < vsi->nb_qps; i++) {
1279 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1280 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1283 /* INTENA flag is not auto-cleared for interrupt */
1284 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1285 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1286 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1287 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1288 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1290 /* VF bind interrupt */
1291 if (vsi->type == I40E_VSI_SRIOV) {
1292 __vsi_queues_bind_intr(vsi, msix_vect,
1293 vsi->base_queue, vsi->nb_qps);
1297 /* PF & VMDq bind interrupt */
1298 if (rte_intr_dp_is_en(intr_handle)) {
1299 if (vsi->type == I40E_VSI_MAIN) {
1302 } else if (vsi->type == I40E_VSI_VMDQ2) {
1303 struct i40e_vsi *main_vsi =
1304 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1305 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1310 for (i = 0; i < vsi->nb_used_qps; i++) {
1312 if (!rte_intr_allow_others(intr_handle))
1313 /* allow to share MISC_VEC_ID */
1314 msix_vect = I40E_MISC_VEC_ID;
1316 /* no enough msix_vect, map all to one */
1317 __vsi_queues_bind_intr(vsi, msix_vect,
1318 vsi->base_queue + i,
1319 vsi->nb_used_qps - i);
1320 for (; !!record && i < vsi->nb_used_qps; i++)
1321 intr_handle->intr_vec[queue_idx + i] =
1325 /* 1:1 queue/msix_vect mapping */
1326 __vsi_queues_bind_intr(vsi, msix_vect,
1327 vsi->base_queue + i, 1);
1329 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1337 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1339 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1340 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1341 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1342 uint16_t interval = i40e_calc_itr_interval(\
1343 RTE_LIBRTE_I40E_ITR_INTERVAL);
1344 uint16_t msix_intr, i;
1346 if (rte_intr_allow_others(intr_handle))
1347 for (i = 0; i < vsi->nb_msix; i++) {
1348 msix_intr = vsi->msix_intr + i;
1349 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1350 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1351 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1352 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1354 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1357 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1358 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1359 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1360 (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1362 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1364 I40E_WRITE_FLUSH(hw);
1368 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1370 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1371 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1372 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1373 uint16_t msix_intr, i;
1375 if (rte_intr_allow_others(intr_handle))
1376 for (i = 0; i < vsi->nb_msix; i++) {
1377 msix_intr = vsi->msix_intr + i;
1378 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1382 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1384 I40E_WRITE_FLUSH(hw);
1387 static inline uint8_t
1388 i40e_parse_link_speeds(uint16_t link_speeds)
1390 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1392 if (link_speeds & ETH_LINK_SPEED_40G)
1393 link_speed |= I40E_LINK_SPEED_40GB;
1394 if (link_speeds & ETH_LINK_SPEED_20G)
1395 link_speed |= I40E_LINK_SPEED_20GB;
1396 if (link_speeds & ETH_LINK_SPEED_10G)
1397 link_speed |= I40E_LINK_SPEED_10GB;
1398 if (link_speeds & ETH_LINK_SPEED_1G)
1399 link_speed |= I40E_LINK_SPEED_1GB;
1400 if (link_speeds & ETH_LINK_SPEED_100M)
1401 link_speed |= I40E_LINK_SPEED_100MB;
1407 i40e_phy_conf_link(struct i40e_hw *hw,
1409 uint8_t force_speed)
1411 enum i40e_status_code status;
1412 struct i40e_aq_get_phy_abilities_resp phy_ab;
1413 struct i40e_aq_set_phy_config phy_conf;
1414 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1415 I40E_AQ_PHY_FLAG_PAUSE_RX |
1416 I40E_AQ_PHY_FLAG_PAUSE_RX |
1417 I40E_AQ_PHY_FLAG_LOW_POWER;
1418 const uint8_t advt = I40E_LINK_SPEED_40GB |
1419 I40E_LINK_SPEED_10GB |
1420 I40E_LINK_SPEED_1GB |
1421 I40E_LINK_SPEED_100MB;
1425 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1430 memset(&phy_conf, 0, sizeof(phy_conf));
1432 /* bits 0-2 use the values from get_phy_abilities_resp */
1434 abilities |= phy_ab.abilities & mask;
1436 /* update ablities and speed */
1437 if (abilities & I40E_AQ_PHY_AN_ENABLED)
1438 phy_conf.link_speed = advt;
1440 phy_conf.link_speed = force_speed;
1442 phy_conf.abilities = abilities;
1444 /* use get_phy_abilities_resp value for the rest */
1445 phy_conf.phy_type = phy_ab.phy_type;
1446 phy_conf.eee_capability = phy_ab.eee_capability;
1447 phy_conf.eeer = phy_ab.eeer_val;
1448 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1450 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1451 phy_ab.abilities, phy_ab.link_speed);
1452 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
1453 phy_conf.abilities, phy_conf.link_speed);
1455 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1459 return I40E_SUCCESS;
1463 i40e_apply_link_speed(struct rte_eth_dev *dev)
1466 uint8_t abilities = 0;
1467 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1468 struct rte_eth_conf *conf = &dev->data->dev_conf;
1470 speed = i40e_parse_link_speeds(conf->link_speeds);
1471 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1472 if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1473 abilities |= I40E_AQ_PHY_AN_ENABLED;
1474 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1476 /* Skip changing speed on 40G interfaces, FW does not support */
1477 if (i40e_is_40G_device(hw->device_id)) {
1478 speed = I40E_LINK_SPEED_UNKNOWN;
1479 abilities |= I40E_AQ_PHY_AN_ENABLED;
1482 return i40e_phy_conf_link(hw, abilities, speed);
1486 i40e_dev_start(struct rte_eth_dev *dev)
1488 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1489 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1490 struct i40e_vsi *main_vsi = pf->main_vsi;
1492 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1493 uint32_t intr_vector = 0;
1495 hw->adapter_stopped = 0;
1497 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1498 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1499 dev->data->port_id);
1503 rte_intr_disable(intr_handle);
1505 if ((rte_intr_cap_multiple(intr_handle) ||
1506 !RTE_ETH_DEV_SRIOV(dev).active) &&
1507 dev->data->dev_conf.intr_conf.rxq != 0) {
1508 intr_vector = dev->data->nb_rx_queues;
1509 if (rte_intr_efd_enable(intr_handle, intr_vector))
1513 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1514 intr_handle->intr_vec =
1515 rte_zmalloc("intr_vec",
1516 dev->data->nb_rx_queues * sizeof(int),
1518 if (!intr_handle->intr_vec) {
1519 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1520 " intr_vec\n", dev->data->nb_rx_queues);
1525 /* Initialize VSI */
1526 ret = i40e_dev_rxtx_init(pf);
1527 if (ret != I40E_SUCCESS) {
1528 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1532 /* Map queues with MSIX interrupt */
1533 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1534 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1535 i40e_vsi_queues_bind_intr(main_vsi);
1536 i40e_vsi_enable_queues_intr(main_vsi);
1538 /* Map VMDQ VSI queues with MSIX interrupt */
1539 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1540 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1541 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1542 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1545 /* enable FDIR MSIX interrupt */
1546 if (pf->fdir.fdir_vsi) {
1547 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1548 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1551 /* Enable all queues which have been configured */
1552 ret = i40e_dev_switch_queues(pf, TRUE);
1553 if (ret != I40E_SUCCESS) {
1554 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1558 /* Enable receiving broadcast packets */
1559 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1560 if (ret != I40E_SUCCESS)
1561 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1563 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1564 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1566 if (ret != I40E_SUCCESS)
1567 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1570 /* Apply link configure */
1571 if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1572 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1573 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_40G)) {
1574 PMD_DRV_LOG(ERR, "Invalid link setting");
1577 ret = i40e_apply_link_speed(dev);
1578 if (I40E_SUCCESS != ret) {
1579 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1583 if (!rte_intr_allow_others(intr_handle)) {
1584 rte_intr_callback_unregister(intr_handle,
1585 i40e_dev_interrupt_handler,
1587 /* configure and enable device interrupt */
1588 i40e_pf_config_irq0(hw, FALSE);
1589 i40e_pf_enable_irq0(hw);
1591 if (dev->data->dev_conf.intr_conf.lsc != 0)
1592 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1593 " no intr multiplex\n");
1596 /* enable uio intr after callback register */
1597 rte_intr_enable(intr_handle);
1599 return I40E_SUCCESS;
1602 i40e_dev_switch_queues(pf, FALSE);
1603 i40e_dev_clear_queues(dev);
1609 i40e_dev_stop(struct rte_eth_dev *dev)
1611 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1612 struct i40e_vsi *main_vsi = pf->main_vsi;
1613 struct i40e_mirror_rule *p_mirror;
1614 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1617 /* Disable all queues */
1618 i40e_dev_switch_queues(pf, FALSE);
1620 /* un-map queues with interrupt registers */
1621 i40e_vsi_disable_queues_intr(main_vsi);
1622 i40e_vsi_queues_unbind_intr(main_vsi);
1624 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1625 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1626 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1629 if (pf->fdir.fdir_vsi) {
1630 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1631 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1633 /* Clear all queues and release memory */
1634 i40e_dev_clear_queues(dev);
1637 i40e_dev_set_link_down(dev);
1639 /* Remove all mirror rules */
1640 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1641 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1644 pf->nb_mirror_rule = 0;
1646 if (!rte_intr_allow_others(intr_handle))
1647 /* resume to the default handler */
1648 rte_intr_callback_register(intr_handle,
1649 i40e_dev_interrupt_handler,
1652 /* Clean datapath event and queue/vec mapping */
1653 rte_intr_efd_disable(intr_handle);
1654 if (intr_handle->intr_vec) {
1655 rte_free(intr_handle->intr_vec);
1656 intr_handle->intr_vec = NULL;
1661 i40e_dev_close(struct rte_eth_dev *dev)
1663 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1664 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1668 PMD_INIT_FUNC_TRACE();
1671 hw->adapter_stopped = 1;
1672 i40e_dev_free_queues(dev);
1674 /* Disable interrupt */
1675 i40e_pf_disable_irq0(hw);
1676 rte_intr_disable(&(dev->pci_dev->intr_handle));
1678 /* shutdown and destroy the HMC */
1679 i40e_shutdown_lan_hmc(hw);
1681 /* release all the existing VSIs and VEBs */
1682 i40e_fdir_teardown(pf);
1683 i40e_vsi_release(pf->main_vsi);
1685 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1686 i40e_vsi_release(pf->vmdq[i].vsi);
1687 pf->vmdq[i].vsi = NULL;
1693 /* shutdown the adminq */
1694 i40e_aq_queue_shutdown(hw, true);
1695 i40e_shutdown_adminq(hw);
1697 i40e_res_pool_destroy(&pf->qp_pool);
1698 i40e_res_pool_destroy(&pf->msix_pool);
1700 /* force a PF reset to clean anything leftover */
1701 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1702 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1703 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1704 I40E_WRITE_FLUSH(hw);
1708 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1710 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1711 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1712 struct i40e_vsi *vsi = pf->main_vsi;
1715 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1717 if (status != I40E_SUCCESS)
1718 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1720 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1722 if (status != I40E_SUCCESS)
1723 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1728 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1730 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1731 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1732 struct i40e_vsi *vsi = pf->main_vsi;
1735 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1737 if (status != I40E_SUCCESS)
1738 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1740 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1742 if (status != I40E_SUCCESS)
1743 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1747 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1749 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1750 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1751 struct i40e_vsi *vsi = pf->main_vsi;
1754 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1755 if (ret != I40E_SUCCESS)
1756 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1760 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1762 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1763 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1764 struct i40e_vsi *vsi = pf->main_vsi;
1767 if (dev->data->promiscuous == 1)
1768 return; /* must remain in all_multicast mode */
1770 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1771 vsi->seid, FALSE, NULL);
1772 if (ret != I40E_SUCCESS)
1773 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1777 * Set device link up.
1780 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1782 /* re-apply link speed setting */
1783 return i40e_apply_link_speed(dev);
1787 * Set device link down.
1790 i40e_dev_set_link_down(struct rte_eth_dev *dev)
1792 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1793 uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1794 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1796 return i40e_phy_conf_link(hw, abilities, speed);
1800 i40e_dev_link_update(struct rte_eth_dev *dev,
1801 int wait_to_complete)
1803 #define CHECK_INTERVAL 100 /* 100ms */
1804 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
1805 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1806 struct i40e_link_status link_status;
1807 struct rte_eth_link link, old;
1809 unsigned rep_cnt = MAX_REPEAT_TIME;
1811 memset(&link, 0, sizeof(link));
1812 memset(&old, 0, sizeof(old));
1813 memset(&link_status, 0, sizeof(link_status));
1814 rte_i40e_dev_atomic_read_link_status(dev, &old);
1817 /* Get link status information from hardware */
1818 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1819 if (status != I40E_SUCCESS) {
1820 link.link_speed = ETH_SPEED_NUM_100M;
1821 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1822 PMD_DRV_LOG(ERR, "Failed to get link info");
1826 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1827 if (!wait_to_complete)
1830 rte_delay_ms(CHECK_INTERVAL);
1831 } while (!link.link_status && rep_cnt--);
1833 if (!link.link_status)
1836 /* i40e uses full duplex only */
1837 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1839 /* Parse the link status */
1840 switch (link_status.link_speed) {
1841 case I40E_LINK_SPEED_100MB:
1842 link.link_speed = ETH_SPEED_NUM_100M;
1844 case I40E_LINK_SPEED_1GB:
1845 link.link_speed = ETH_SPEED_NUM_1G;
1847 case I40E_LINK_SPEED_10GB:
1848 link.link_speed = ETH_SPEED_NUM_10G;
1850 case I40E_LINK_SPEED_20GB:
1851 link.link_speed = ETH_SPEED_NUM_20G;
1853 case I40E_LINK_SPEED_40GB:
1854 link.link_speed = ETH_SPEED_NUM_40G;
1857 link.link_speed = ETH_SPEED_NUM_100M;
1861 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
1862 ETH_LINK_SPEED_FIXED);
1865 rte_i40e_dev_atomic_write_link_status(dev, &link);
1866 if (link.link_status == old.link_status)
1872 /* Get all the statistics of a VSI */
1874 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1876 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1877 struct i40e_eth_stats *nes = &vsi->eth_stats;
1878 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1879 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1881 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1882 vsi->offset_loaded, &oes->rx_bytes,
1884 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1885 vsi->offset_loaded, &oes->rx_unicast,
1887 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1888 vsi->offset_loaded, &oes->rx_multicast,
1889 &nes->rx_multicast);
1890 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1891 vsi->offset_loaded, &oes->rx_broadcast,
1892 &nes->rx_broadcast);
1893 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1894 &oes->rx_discards, &nes->rx_discards);
1895 /* GLV_REPC not supported */
1896 /* GLV_RMPC not supported */
1897 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1898 &oes->rx_unknown_protocol,
1899 &nes->rx_unknown_protocol);
1900 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1901 vsi->offset_loaded, &oes->tx_bytes,
1903 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1904 vsi->offset_loaded, &oes->tx_unicast,
1906 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1907 vsi->offset_loaded, &oes->tx_multicast,
1908 &nes->tx_multicast);
1909 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1910 vsi->offset_loaded, &oes->tx_broadcast,
1911 &nes->tx_broadcast);
1912 /* GLV_TDPC not supported */
1913 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1914 &oes->tx_errors, &nes->tx_errors);
1915 vsi->offset_loaded = true;
1917 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1919 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
1920 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
1921 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
1922 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
1923 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
1924 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1925 nes->rx_unknown_protocol);
1926 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
1927 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
1928 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
1929 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
1930 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
1931 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
1932 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1937 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
1940 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1941 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1943 /* Get statistics of struct i40e_eth_stats */
1944 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1945 I40E_GLPRT_GORCL(hw->port),
1946 pf->offset_loaded, &os->eth.rx_bytes,
1948 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1949 I40E_GLPRT_UPRCL(hw->port),
1950 pf->offset_loaded, &os->eth.rx_unicast,
1951 &ns->eth.rx_unicast);
1952 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1953 I40E_GLPRT_MPRCL(hw->port),
1954 pf->offset_loaded, &os->eth.rx_multicast,
1955 &ns->eth.rx_multicast);
1956 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1957 I40E_GLPRT_BPRCL(hw->port),
1958 pf->offset_loaded, &os->eth.rx_broadcast,
1959 &ns->eth.rx_broadcast);
1960 /* Workaround: CRC size should not be included in byte statistics,
1961 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
1963 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
1964 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
1966 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1967 pf->offset_loaded, &os->eth.rx_discards,
1968 &ns->eth.rx_discards);
1969 /* GLPRT_REPC not supported */
1970 /* GLPRT_RMPC not supported */
1971 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1973 &os->eth.rx_unknown_protocol,
1974 &ns->eth.rx_unknown_protocol);
1975 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1976 I40E_GLPRT_GOTCL(hw->port),
1977 pf->offset_loaded, &os->eth.tx_bytes,
1979 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1980 I40E_GLPRT_UPTCL(hw->port),
1981 pf->offset_loaded, &os->eth.tx_unicast,
1982 &ns->eth.tx_unicast);
1983 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1984 I40E_GLPRT_MPTCL(hw->port),
1985 pf->offset_loaded, &os->eth.tx_multicast,
1986 &ns->eth.tx_multicast);
1987 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1988 I40E_GLPRT_BPTCL(hw->port),
1989 pf->offset_loaded, &os->eth.tx_broadcast,
1990 &ns->eth.tx_broadcast);
1991 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
1992 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
1993 /* GLPRT_TEPC not supported */
1995 /* additional port specific stats */
1996 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1997 pf->offset_loaded, &os->tx_dropped_link_down,
1998 &ns->tx_dropped_link_down);
1999 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2000 pf->offset_loaded, &os->crc_errors,
2002 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2003 pf->offset_loaded, &os->illegal_bytes,
2004 &ns->illegal_bytes);
2005 /* GLPRT_ERRBC not supported */
2006 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2007 pf->offset_loaded, &os->mac_local_faults,
2008 &ns->mac_local_faults);
2009 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2010 pf->offset_loaded, &os->mac_remote_faults,
2011 &ns->mac_remote_faults);
2012 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2013 pf->offset_loaded, &os->rx_length_errors,
2014 &ns->rx_length_errors);
2015 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2016 pf->offset_loaded, &os->link_xon_rx,
2018 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2019 pf->offset_loaded, &os->link_xoff_rx,
2021 for (i = 0; i < 8; i++) {
2022 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2024 &os->priority_xon_rx[i],
2025 &ns->priority_xon_rx[i]);
2026 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2028 &os->priority_xoff_rx[i],
2029 &ns->priority_xoff_rx[i]);
2031 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2032 pf->offset_loaded, &os->link_xon_tx,
2034 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2035 pf->offset_loaded, &os->link_xoff_tx,
2037 for (i = 0; i < 8; i++) {
2038 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2040 &os->priority_xon_tx[i],
2041 &ns->priority_xon_tx[i]);
2042 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2044 &os->priority_xoff_tx[i],
2045 &ns->priority_xoff_tx[i]);
2046 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2048 &os->priority_xon_2_xoff[i],
2049 &ns->priority_xon_2_xoff[i]);
2051 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2052 I40E_GLPRT_PRC64L(hw->port),
2053 pf->offset_loaded, &os->rx_size_64,
2055 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2056 I40E_GLPRT_PRC127L(hw->port),
2057 pf->offset_loaded, &os->rx_size_127,
2059 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2060 I40E_GLPRT_PRC255L(hw->port),
2061 pf->offset_loaded, &os->rx_size_255,
2063 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2064 I40E_GLPRT_PRC511L(hw->port),
2065 pf->offset_loaded, &os->rx_size_511,
2067 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2068 I40E_GLPRT_PRC1023L(hw->port),
2069 pf->offset_loaded, &os->rx_size_1023,
2071 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2072 I40E_GLPRT_PRC1522L(hw->port),
2073 pf->offset_loaded, &os->rx_size_1522,
2075 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2076 I40E_GLPRT_PRC9522L(hw->port),
2077 pf->offset_loaded, &os->rx_size_big,
2079 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2080 pf->offset_loaded, &os->rx_undersize,
2082 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2083 pf->offset_loaded, &os->rx_fragments,
2085 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2086 pf->offset_loaded, &os->rx_oversize,
2088 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2089 pf->offset_loaded, &os->rx_jabber,
2091 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2092 I40E_GLPRT_PTC64L(hw->port),
2093 pf->offset_loaded, &os->tx_size_64,
2095 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2096 I40E_GLPRT_PTC127L(hw->port),
2097 pf->offset_loaded, &os->tx_size_127,
2099 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2100 I40E_GLPRT_PTC255L(hw->port),
2101 pf->offset_loaded, &os->tx_size_255,
2103 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2104 I40E_GLPRT_PTC511L(hw->port),
2105 pf->offset_loaded, &os->tx_size_511,
2107 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2108 I40E_GLPRT_PTC1023L(hw->port),
2109 pf->offset_loaded, &os->tx_size_1023,
2111 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2112 I40E_GLPRT_PTC1522L(hw->port),
2113 pf->offset_loaded, &os->tx_size_1522,
2115 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2116 I40E_GLPRT_PTC9522L(hw->port),
2117 pf->offset_loaded, &os->tx_size_big,
2119 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2121 &os->fd_sb_match, &ns->fd_sb_match);
2122 /* GLPRT_MSPDC not supported */
2123 /* GLPRT_XEC not supported */
2125 pf->offset_loaded = true;
2128 i40e_update_vsi_stats(pf->main_vsi);
2131 /* Get all statistics of a port */
2133 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2135 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2136 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2137 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2140 /* call read registers - updates values, now write them to struct */
2141 i40e_read_stats_registers(pf, hw);
2143 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2144 pf->main_vsi->eth_stats.rx_multicast +
2145 pf->main_vsi->eth_stats.rx_broadcast -
2146 pf->main_vsi->eth_stats.rx_discards;
2147 stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2148 pf->main_vsi->eth_stats.tx_multicast +
2149 pf->main_vsi->eth_stats.tx_broadcast;
2150 stats->ibytes = ns->eth.rx_bytes;
2151 stats->obytes = ns->eth.tx_bytes;
2152 stats->oerrors = ns->eth.tx_errors +
2153 pf->main_vsi->eth_stats.tx_errors;
2156 stats->imissed = ns->eth.rx_discards +
2157 pf->main_vsi->eth_stats.rx_discards;
2158 stats->ierrors = ns->crc_errors +
2159 ns->rx_length_errors + ns->rx_undersize +
2160 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2162 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2163 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
2164 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
2165 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
2166 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
2167 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
2168 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2169 ns->eth.rx_unknown_protocol);
2170 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
2171 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
2172 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
2173 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
2174 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
2175 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
2177 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
2178 ns->tx_dropped_link_down);
2179 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
2180 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
2182 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
2183 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
2184 ns->mac_local_faults);
2185 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
2186 ns->mac_remote_faults);
2187 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
2188 ns->rx_length_errors);
2189 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
2190 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
2191 for (i = 0; i < 8; i++) {
2192 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
2193 i, ns->priority_xon_rx[i]);
2194 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
2195 i, ns->priority_xoff_rx[i]);
2197 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
2198 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
2199 for (i = 0; i < 8; i++) {
2200 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
2201 i, ns->priority_xon_tx[i]);
2202 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
2203 i, ns->priority_xoff_tx[i]);
2204 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
2205 i, ns->priority_xon_2_xoff[i]);
2207 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
2208 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
2209 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
2210 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
2211 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
2212 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
2213 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
2214 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
2215 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
2216 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
2217 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
2218 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
2219 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
2220 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
2221 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
2222 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
2223 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
2224 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
2225 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2226 ns->mac_short_packet_dropped);
2227 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
2228 ns->checksum_error);
2229 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
2230 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2233 /* Reset the statistics */
2235 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2237 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2238 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2240 /* Mark PF and VSI stats to update the offset, aka "reset" */
2241 pf->offset_loaded = false;
2243 pf->main_vsi->offset_loaded = false;
2245 /* read the stats, reading current register values into offset */
2246 i40e_read_stats_registers(pf, hw);
2250 i40e_xstats_calc_num(void)
2252 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2253 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2254 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2257 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2258 struct rte_eth_xstat_name *xstats_names,
2259 __rte_unused unsigned limit)
2264 if (xstats_names == NULL)
2265 return i40e_xstats_calc_num();
2267 /* Note: limit checked in rte_eth_xstats_names() */
2269 /* Get stats from i40e_eth_stats struct */
2270 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2271 snprintf(xstats_names[count].name,
2272 sizeof(xstats_names[count].name),
2273 "%s", rte_i40e_stats_strings[i].name);
2274 xstats_names[count].id = count;
2278 /* Get individiual stats from i40e_hw_port struct */
2279 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2280 snprintf(xstats_names[count].name,
2281 sizeof(xstats_names[count].name),
2282 "%s", rte_i40e_hw_port_strings[i].name);
2283 xstats_names[count].id = count;
2287 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2288 for (prio = 0; prio < 8; prio++) {
2289 snprintf(xstats_names[count].name,
2290 sizeof(xstats_names[count].name),
2291 "rx_priority%u_%s", prio,
2292 rte_i40e_rxq_prio_strings[i].name);
2293 xstats_names[count].id = count;
2298 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2299 for (prio = 0; prio < 8; prio++) {
2300 snprintf(xstats_names[count].name,
2301 sizeof(xstats_names[count].name),
2302 "tx_priority%u_%s", prio,
2303 rte_i40e_txq_prio_strings[i].name);
2304 xstats_names[count].id = count;
2312 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2315 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2316 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2317 unsigned i, count, prio;
2318 struct i40e_hw_port_stats *hw_stats = &pf->stats;
2320 count = i40e_xstats_calc_num();
2324 i40e_read_stats_registers(pf, hw);
2331 /* Get stats from i40e_eth_stats struct */
2332 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2333 xstats[count].id = count;
2334 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2335 rte_i40e_stats_strings[i].offset);
2339 /* Get individiual stats from i40e_hw_port struct */
2340 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2341 xstats[count].id = count;
2342 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2343 rte_i40e_hw_port_strings[i].offset);
2347 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2348 for (prio = 0; prio < 8; prio++) {
2349 xstats[count].id = count;
2350 xstats[count].value =
2351 *(uint64_t *)(((char *)hw_stats) +
2352 rte_i40e_rxq_prio_strings[i].offset +
2353 (sizeof(uint64_t) * prio));
2358 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2359 for (prio = 0; prio < 8; prio++) {
2360 xstats[count].id = count;
2361 xstats[count].value =
2362 *(uint64_t *)(((char *)hw_stats) +
2363 rte_i40e_txq_prio_strings[i].offset +
2364 (sizeof(uint64_t) * prio));
2373 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2374 __rte_unused uint16_t queue_id,
2375 __rte_unused uint8_t stat_idx,
2376 __rte_unused uint8_t is_rx)
2378 PMD_INIT_FUNC_TRACE();
2384 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2386 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2387 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2388 struct i40e_vsi *vsi = pf->main_vsi;
2390 dev_info->max_rx_queues = vsi->nb_qps;
2391 dev_info->max_tx_queues = vsi->nb_qps;
2392 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2393 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2394 dev_info->max_mac_addrs = vsi->max_macaddrs;
2395 dev_info->max_vfs = dev->pci_dev->max_vfs;
2396 dev_info->rx_offload_capa =
2397 DEV_RX_OFFLOAD_VLAN_STRIP |
2398 DEV_RX_OFFLOAD_QINQ_STRIP |
2399 DEV_RX_OFFLOAD_IPV4_CKSUM |
2400 DEV_RX_OFFLOAD_UDP_CKSUM |
2401 DEV_RX_OFFLOAD_TCP_CKSUM;
2402 dev_info->tx_offload_capa =
2403 DEV_TX_OFFLOAD_VLAN_INSERT |
2404 DEV_TX_OFFLOAD_QINQ_INSERT |
2405 DEV_TX_OFFLOAD_IPV4_CKSUM |
2406 DEV_TX_OFFLOAD_UDP_CKSUM |
2407 DEV_TX_OFFLOAD_TCP_CKSUM |
2408 DEV_TX_OFFLOAD_SCTP_CKSUM |
2409 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2410 DEV_TX_OFFLOAD_TCP_TSO;
2411 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2413 dev_info->reta_size = pf->hash_lut_size;
2414 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2416 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2418 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2419 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2420 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2422 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2426 dev_info->default_txconf = (struct rte_eth_txconf) {
2428 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2429 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2430 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2432 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2433 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2434 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2435 ETH_TXQ_FLAGS_NOOFFLOADS,
2438 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2439 .nb_max = I40E_MAX_RING_DESC,
2440 .nb_min = I40E_MIN_RING_DESC,
2441 .nb_align = I40E_ALIGN_RING_DESC,
2444 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2445 .nb_max = I40E_MAX_RING_DESC,
2446 .nb_min = I40E_MIN_RING_DESC,
2447 .nb_align = I40E_ALIGN_RING_DESC,
2450 if (pf->flags & I40E_FLAG_VMDQ) {
2451 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2452 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2453 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2454 pf->max_nb_vmdq_vsi;
2455 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2456 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2457 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2460 if (i40e_is_40G_device(hw->device_id))
2462 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2465 dev_info->speed_capa = ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G;
2469 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2471 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2472 struct i40e_vsi *vsi = pf->main_vsi;
2473 PMD_INIT_FUNC_TRACE();
2476 return i40e_vsi_add_vlan(vsi, vlan_id);
2478 return i40e_vsi_delete_vlan(vsi, vlan_id);
2482 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2483 enum rte_vlan_type vlan_type,
2486 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2487 uint64_t reg_r = 0, reg_w = 0;
2488 uint16_t reg_id = 0;
2490 int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2492 switch (vlan_type) {
2493 case ETH_VLAN_TYPE_OUTER:
2499 case ETH_VLAN_TYPE_INNER:
2505 "Unsupported vlan type in single vlan.\n");
2511 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2514 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2516 if (ret != I40E_SUCCESS) {
2517 PMD_DRV_LOG(ERR, "Fail to debug read from "
2518 "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2522 PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2523 "0x%08"PRIx64"", reg_id, reg_r);
2525 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2526 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2527 if (reg_r == reg_w) {
2529 PMD_DRV_LOG(DEBUG, "No need to write");
2533 ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2535 if (ret != I40E_SUCCESS) {
2537 PMD_DRV_LOG(ERR, "Fail to debug write to "
2538 "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2541 PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2542 "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2548 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2550 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2551 struct i40e_vsi *vsi = pf->main_vsi;
2553 if (mask & ETH_VLAN_FILTER_MASK) {
2554 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2555 i40e_vsi_config_vlan_filter(vsi, TRUE);
2557 i40e_vsi_config_vlan_filter(vsi, FALSE);
2560 if (mask & ETH_VLAN_STRIP_MASK) {
2561 /* Enable or disable VLAN stripping */
2562 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2563 i40e_vsi_config_vlan_stripping(vsi, TRUE);
2565 i40e_vsi_config_vlan_stripping(vsi, FALSE);
2568 if (mask & ETH_VLAN_EXTEND_MASK) {
2569 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
2570 i40e_vsi_config_double_vlan(vsi, TRUE);
2571 /* Set global registers with default ether type value */
2572 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
2574 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
2578 i40e_vsi_config_double_vlan(vsi, FALSE);
2583 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2584 __rte_unused uint16_t queue,
2585 __rte_unused int on)
2587 PMD_INIT_FUNC_TRACE();
2591 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2593 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2594 struct i40e_vsi *vsi = pf->main_vsi;
2595 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2596 struct i40e_vsi_vlan_pvid_info info;
2598 memset(&info, 0, sizeof(info));
2601 info.config.pvid = pvid;
2603 info.config.reject.tagged =
2604 data->dev_conf.txmode.hw_vlan_reject_tagged;
2605 info.config.reject.untagged =
2606 data->dev_conf.txmode.hw_vlan_reject_untagged;
2609 return i40e_vsi_vlan_pvid_set(vsi, &info);
2613 i40e_dev_led_on(struct rte_eth_dev *dev)
2615 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2616 uint32_t mode = i40e_led_get(hw);
2619 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2625 i40e_dev_led_off(struct rte_eth_dev *dev)
2627 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2628 uint32_t mode = i40e_led_get(hw);
2631 i40e_led_set(hw, 0, false);
2637 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2639 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2640 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2642 fc_conf->pause_time = pf->fc_conf.pause_time;
2643 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2644 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2646 /* Return current mode according to actual setting*/
2647 switch (hw->fc.current_mode) {
2649 fc_conf->mode = RTE_FC_FULL;
2651 case I40E_FC_TX_PAUSE:
2652 fc_conf->mode = RTE_FC_TX_PAUSE;
2654 case I40E_FC_RX_PAUSE:
2655 fc_conf->mode = RTE_FC_RX_PAUSE;
2659 fc_conf->mode = RTE_FC_NONE;
2666 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2668 uint32_t mflcn_reg, fctrl_reg, reg;
2669 uint32_t max_high_water;
2670 uint8_t i, aq_failure;
2674 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2675 [RTE_FC_NONE] = I40E_FC_NONE,
2676 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2677 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2678 [RTE_FC_FULL] = I40E_FC_FULL
2681 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2683 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2684 if ((fc_conf->high_water > max_high_water) ||
2685 (fc_conf->high_water < fc_conf->low_water)) {
2686 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2687 "High_water must <= %d.", max_high_water);
2691 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2692 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2693 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2695 pf->fc_conf.pause_time = fc_conf->pause_time;
2696 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2697 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2699 PMD_INIT_FUNC_TRACE();
2701 /* All the link flow control related enable/disable register
2702 * configuration is handle by the F/W
2704 err = i40e_set_fc(hw, &aq_failure, true);
2708 if (i40e_is_40G_device(hw->device_id)) {
2709 /* Configure flow control refresh threshold,
2710 * the value for stat_tx_pause_refresh_timer[8]
2711 * is used for global pause operation.
2715 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2716 pf->fc_conf.pause_time);
2718 /* configure the timer value included in transmitted pause
2720 * the value for stat_tx_pause_quanta[8] is used for global
2723 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2724 pf->fc_conf.pause_time);
2726 fctrl_reg = I40E_READ_REG(hw,
2727 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2729 if (fc_conf->mac_ctrl_frame_fwd != 0)
2730 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2732 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2734 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2737 /* Configure pause time (2 TCs per register) */
2738 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2739 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2740 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2742 /* Configure flow control refresh threshold value */
2743 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2744 pf->fc_conf.pause_time / 2);
2746 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2748 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2749 *depending on configuration
2751 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2752 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2753 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2755 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2756 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2759 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2762 /* config the water marker both based on the packets and bytes */
2763 I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2764 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2765 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2766 I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2767 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2768 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2769 I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2770 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2772 I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2773 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2776 I40E_WRITE_FLUSH(hw);
2782 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2783 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2785 PMD_INIT_FUNC_TRACE();
2790 /* Add a MAC address, and update filters */
2792 i40e_macaddr_add(struct rte_eth_dev *dev,
2793 struct ether_addr *mac_addr,
2794 __rte_unused uint32_t index,
2797 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2798 struct i40e_mac_filter_info mac_filter;
2799 struct i40e_vsi *vsi;
2802 /* If VMDQ not enabled or configured, return */
2803 if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
2804 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2805 pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
2810 if (pool > pf->nb_cfg_vmdq_vsi) {
2811 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2812 pool, pf->nb_cfg_vmdq_vsi);
2816 (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2817 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2818 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2820 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
2825 vsi = pf->vmdq[pool - 1].vsi;
2827 ret = i40e_vsi_add_mac(vsi, &mac_filter);
2828 if (ret != I40E_SUCCESS) {
2829 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2834 /* Remove a MAC address, and update filters */
2836 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2838 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2839 struct i40e_vsi *vsi;
2840 struct rte_eth_dev_data *data = dev->data;
2841 struct ether_addr *macaddr;
2846 macaddr = &(data->mac_addrs[index]);
2848 pool_sel = dev->data->mac_pool_sel[index];
2850 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
2851 if (pool_sel & (1ULL << i)) {
2855 /* No VMDQ pool enabled or configured */
2856 if (!(pf->flags | I40E_FLAG_VMDQ) ||
2857 (i > pf->nb_cfg_vmdq_vsi)) {
2858 PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
2862 vsi = pf->vmdq[i - 1].vsi;
2864 ret = i40e_vsi_delete_mac(vsi, macaddr);
2867 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
2874 /* Set perfect match or hash match of MAC and VLAN for a VF */
2876 i40e_vf_mac_filter_set(struct i40e_pf *pf,
2877 struct rte_eth_mac_filter *filter,
2881 struct i40e_mac_filter_info mac_filter;
2882 struct ether_addr old_mac;
2883 struct ether_addr *new_mac;
2884 struct i40e_pf_vf *vf = NULL;
2889 PMD_DRV_LOG(ERR, "Invalid PF argument.");
2892 hw = I40E_PF_TO_HW(pf);
2894 if (filter == NULL) {
2895 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
2899 new_mac = &filter->mac_addr;
2901 if (is_zero_ether_addr(new_mac)) {
2902 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
2906 vf_id = filter->dst_id;
2908 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
2909 PMD_DRV_LOG(ERR, "Invalid argument.");
2912 vf = &pf->vfs[vf_id];
2914 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
2915 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
2920 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
2921 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
2923 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
2926 mac_filter.filter_type = filter->filter_type;
2927 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
2928 if (ret != I40E_SUCCESS) {
2929 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
2932 ether_addr_copy(new_mac, &pf->dev_addr);
2934 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
2936 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
2937 if (ret != I40E_SUCCESS) {
2938 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
2942 /* Clear device address as it has been removed */
2943 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
2944 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
2950 /* MAC filter handle */
2952 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
2955 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2956 struct rte_eth_mac_filter *filter;
2957 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2958 int ret = I40E_NOT_SUPPORTED;
2960 filter = (struct rte_eth_mac_filter *)(arg);
2962 switch (filter_op) {
2963 case RTE_ETH_FILTER_NOP:
2966 case RTE_ETH_FILTER_ADD:
2967 i40e_pf_disable_irq0(hw);
2969 ret = i40e_vf_mac_filter_set(pf, filter, 1);
2970 i40e_pf_enable_irq0(hw);
2972 case RTE_ETH_FILTER_DELETE:
2973 i40e_pf_disable_irq0(hw);
2975 ret = i40e_vf_mac_filter_set(pf, filter, 0);
2976 i40e_pf_enable_irq0(hw);
2979 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2980 ret = I40E_ERR_PARAM;
2988 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2990 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2991 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2997 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2998 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3001 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3005 uint32_t *lut_dw = (uint32_t *)lut;
3006 uint16_t i, lut_size_dw = lut_size / 4;
3008 for (i = 0; i < lut_size_dw; i++)
3009 lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3016 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3018 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3019 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3025 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3026 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3029 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3033 uint32_t *lut_dw = (uint32_t *)lut;
3034 uint16_t i, lut_size_dw = lut_size / 4;
3036 for (i = 0; i < lut_size_dw; i++)
3037 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3038 I40E_WRITE_FLUSH(hw);
3045 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3046 struct rte_eth_rss_reta_entry64 *reta_conf,
3049 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3050 uint16_t i, lut_size = pf->hash_lut_size;
3051 uint16_t idx, shift;
3055 if (reta_size != lut_size ||
3056 reta_size > ETH_RSS_RETA_SIZE_512) {
3057 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3058 "(%d) doesn't match the number hardware can supported "
3059 "(%d)\n", reta_size, lut_size);
3063 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3065 PMD_DRV_LOG(ERR, "No memory can be allocated");
3068 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3071 for (i = 0; i < reta_size; i++) {
3072 idx = i / RTE_RETA_GROUP_SIZE;
3073 shift = i % RTE_RETA_GROUP_SIZE;
3074 if (reta_conf[idx].mask & (1ULL << shift))
3075 lut[i] = reta_conf[idx].reta[shift];
3077 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3086 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3087 struct rte_eth_rss_reta_entry64 *reta_conf,
3090 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3091 uint16_t i, lut_size = pf->hash_lut_size;
3092 uint16_t idx, shift;
3096 if (reta_size != lut_size ||
3097 reta_size > ETH_RSS_RETA_SIZE_512) {
3098 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3099 "(%d) doesn't match the number hardware can supported "
3100 "(%d)\n", reta_size, lut_size);
3104 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3106 PMD_DRV_LOG(ERR, "No memory can be allocated");
3110 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3113 for (i = 0; i < reta_size; i++) {
3114 idx = i / RTE_RETA_GROUP_SIZE;
3115 shift = i % RTE_RETA_GROUP_SIZE;
3116 if (reta_conf[idx].mask & (1ULL << shift))
3117 reta_conf[idx].reta[shift] = lut[i];
3127 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3128 * @hw: pointer to the HW structure
3129 * @mem: pointer to mem struct to fill out
3130 * @size: size of memory requested
3131 * @alignment: what to align the allocation to
3133 enum i40e_status_code
3134 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3135 struct i40e_dma_mem *mem,
3139 const struct rte_memzone *mz = NULL;
3140 char z_name[RTE_MEMZONE_NAMESIZE];
3143 return I40E_ERR_PARAM;
3145 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3146 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3147 alignment, RTE_PGSIZE_2M);
3149 return I40E_ERR_NO_MEMORY;
3153 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3154 mem->zone = (const void *)mz;
3155 PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3156 "%"PRIu64, mz->name, mem->pa);
3158 return I40E_SUCCESS;
3162 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3163 * @hw: pointer to the HW structure
3164 * @mem: ptr to mem struct to free
3166 enum i40e_status_code
3167 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3168 struct i40e_dma_mem *mem)
3171 return I40E_ERR_PARAM;
3173 PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3174 "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3176 rte_memzone_free((const struct rte_memzone *)mem->zone);
3181 return I40E_SUCCESS;
3185 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3186 * @hw: pointer to the HW structure
3187 * @mem: pointer to mem struct to fill out
3188 * @size: size of memory requested
3190 enum i40e_status_code
3191 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3192 struct i40e_virt_mem *mem,
3196 return I40E_ERR_PARAM;
3199 mem->va = rte_zmalloc("i40e", size, 0);
3202 return I40E_SUCCESS;
3204 return I40E_ERR_NO_MEMORY;
3208 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3209 * @hw: pointer to the HW structure
3210 * @mem: pointer to mem struct to free
3212 enum i40e_status_code
3213 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3214 struct i40e_virt_mem *mem)
3217 return I40E_ERR_PARAM;
3222 return I40E_SUCCESS;
3226 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3228 rte_spinlock_init(&sp->spinlock);
3232 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3234 rte_spinlock_lock(&sp->spinlock);
3238 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3240 rte_spinlock_unlock(&sp->spinlock);
3244 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3250 * Get the hardware capabilities, which will be parsed
3251 * and saved into struct i40e_hw.
3254 i40e_get_cap(struct i40e_hw *hw)
3256 struct i40e_aqc_list_capabilities_element_resp *buf;
3257 uint16_t len, size = 0;
3260 /* Calculate a huge enough buff for saving response data temporarily */
3261 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3262 I40E_MAX_CAP_ELE_NUM;
3263 buf = rte_zmalloc("i40e", len, 0);
3265 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3266 return I40E_ERR_NO_MEMORY;
3269 /* Get, parse the capabilities and save it to hw */
3270 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3271 i40e_aqc_opc_list_func_capabilities, NULL);
3272 if (ret != I40E_SUCCESS)
3273 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3275 /* Free the temporary buffer after being used */
3282 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3284 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3285 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3286 uint16_t qp_count = 0, vsi_count = 0;
3288 if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3289 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3292 /* Add the parameter init for LFC */
3293 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3294 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3295 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3297 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3298 pf->max_num_vsi = hw->func_caps.num_vsis;
3299 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3300 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3301 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3303 /* FDir queue/VSI allocation */
3304 pf->fdir_qp_offset = 0;
3305 if (hw->func_caps.fd) {
3306 pf->flags |= I40E_FLAG_FDIR;
3307 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3309 pf->fdir_nb_qps = 0;
3311 qp_count += pf->fdir_nb_qps;
3314 /* LAN queue/VSI allocation */
3315 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3316 if (!hw->func_caps.rss) {
3319 pf->flags |= I40E_FLAG_RSS;
3320 if (hw->mac.type == I40E_MAC_X722)
3321 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3322 pf->lan_nb_qps = pf->lan_nb_qp_max;
3324 qp_count += pf->lan_nb_qps;
3327 /* VF queue/VSI allocation */
3328 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3329 if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3330 pf->flags |= I40E_FLAG_SRIOV;
3331 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3332 pf->vf_num = dev->pci_dev->max_vfs;
3333 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3334 "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3335 pf->vf_nb_qps * pf->vf_num);
3340 qp_count += pf->vf_nb_qps * pf->vf_num;
3341 vsi_count += pf->vf_num;
3343 /* VMDq queue/VSI allocation */
3344 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3345 pf->vmdq_nb_qps = 0;
3346 pf->max_nb_vmdq_vsi = 0;
3347 if (hw->func_caps.vmdq) {
3348 if (qp_count < hw->func_caps.num_tx_qp &&
3349 vsi_count < hw->func_caps.num_vsis) {
3350 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3351 qp_count) / pf->vmdq_nb_qp_max;
3353 /* Limit the maximum number of VMDq vsi to the maximum
3354 * ethdev can support
3356 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3357 hw->func_caps.num_vsis - vsi_count);
3358 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3360 if (pf->max_nb_vmdq_vsi) {
3361 pf->flags |= I40E_FLAG_VMDQ;
3362 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3363 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3364 "per VMDQ VSI, in total %u queues",
3365 pf->max_nb_vmdq_vsi,
3366 pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3367 pf->max_nb_vmdq_vsi);
3369 PMD_DRV_LOG(INFO, "No enough queues left for "
3373 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3376 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3377 vsi_count += pf->max_nb_vmdq_vsi;
3379 if (hw->func_caps.dcb)
3380 pf->flags |= I40E_FLAG_DCB;
3382 if (qp_count > hw->func_caps.num_tx_qp) {
3383 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3384 "the hardware maximum %u", qp_count,
3385 hw->func_caps.num_tx_qp);
3388 if (vsi_count > hw->func_caps.num_vsis) {
3389 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3390 "the hardware maximum %u", vsi_count,
3391 hw->func_caps.num_vsis);
3399 i40e_pf_get_switch_config(struct i40e_pf *pf)
3401 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3402 struct i40e_aqc_get_switch_config_resp *switch_config;
3403 struct i40e_aqc_switch_config_element_resp *element;
3404 uint16_t start_seid = 0, num_reported;
3407 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3408 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3409 if (!switch_config) {
3410 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3414 /* Get the switch configurations */
3415 ret = i40e_aq_get_switch_config(hw, switch_config,
3416 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3417 if (ret != I40E_SUCCESS) {
3418 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3421 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3422 if (num_reported != 1) { /* The number should be 1 */
3423 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3427 /* Parse the switch configuration elements */
3428 element = &(switch_config->element[0]);
3429 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3430 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3431 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3433 PMD_DRV_LOG(INFO, "Unknown element type");
3436 rte_free(switch_config);
3442 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3445 struct pool_entry *entry;
3447 if (pool == NULL || num == 0)
3450 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3451 if (entry == NULL) {
3452 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3456 /* queue heap initialize */
3457 pool->num_free = num;
3458 pool->num_alloc = 0;
3460 LIST_INIT(&pool->alloc_list);
3461 LIST_INIT(&pool->free_list);
3463 /* Initialize element */
3467 LIST_INSERT_HEAD(&pool->free_list, entry, next);
3472 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3474 struct pool_entry *entry, *next_entry;
3479 for (entry = LIST_FIRST(&pool->alloc_list);
3480 entry && (next_entry = LIST_NEXT(entry, next), 1);
3481 entry = next_entry) {
3482 LIST_REMOVE(entry, next);
3486 for (entry = LIST_FIRST(&pool->free_list);
3487 entry && (next_entry = LIST_NEXT(entry, next), 1);
3488 entry = next_entry) {
3489 LIST_REMOVE(entry, next);
3494 pool->num_alloc = 0;
3496 LIST_INIT(&pool->alloc_list);
3497 LIST_INIT(&pool->free_list);
3501 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3504 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3505 uint32_t pool_offset;
3509 PMD_DRV_LOG(ERR, "Invalid parameter");
3513 pool_offset = base - pool->base;
3514 /* Lookup in alloc list */
3515 LIST_FOREACH(entry, &pool->alloc_list, next) {
3516 if (entry->base == pool_offset) {
3517 valid_entry = entry;
3518 LIST_REMOVE(entry, next);
3523 /* Not find, return */
3524 if (valid_entry == NULL) {
3525 PMD_DRV_LOG(ERR, "Failed to find entry");
3530 * Found it, move it to free list and try to merge.
3531 * In order to make merge easier, always sort it by qbase.
3532 * Find adjacent prev and last entries.
3535 LIST_FOREACH(entry, &pool->free_list, next) {
3536 if (entry->base > valid_entry->base) {
3544 /* Try to merge with next one*/
3546 /* Merge with next one */
3547 if (valid_entry->base + valid_entry->len == next->base) {
3548 next->base = valid_entry->base;
3549 next->len += valid_entry->len;
3550 rte_free(valid_entry);
3557 /* Merge with previous one */
3558 if (prev->base + prev->len == valid_entry->base) {
3559 prev->len += valid_entry->len;
3560 /* If it merge with next one, remove next node */
3562 LIST_REMOVE(valid_entry, next);
3563 rte_free(valid_entry);
3565 rte_free(valid_entry);
3571 /* Not find any entry to merge, insert */
3574 LIST_INSERT_AFTER(prev, valid_entry, next);
3575 else if (next != NULL)
3576 LIST_INSERT_BEFORE(next, valid_entry, next);
3577 else /* It's empty list, insert to head */
3578 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3581 pool->num_free += valid_entry->len;
3582 pool->num_alloc -= valid_entry->len;
3588 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3591 struct pool_entry *entry, *valid_entry;
3593 if (pool == NULL || num == 0) {
3594 PMD_DRV_LOG(ERR, "Invalid parameter");
3598 if (pool->num_free < num) {
3599 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3600 num, pool->num_free);
3605 /* Lookup in free list and find most fit one */
3606 LIST_FOREACH(entry, &pool->free_list, next) {
3607 if (entry->len >= num) {
3609 if (entry->len == num) {
3610 valid_entry = entry;
3613 if (valid_entry == NULL || valid_entry->len > entry->len)
3614 valid_entry = entry;
3618 /* Not find one to satisfy the request, return */
3619 if (valid_entry == NULL) {
3620 PMD_DRV_LOG(ERR, "No valid entry found");
3624 * The entry have equal queue number as requested,
3625 * remove it from alloc_list.
3627 if (valid_entry->len == num) {
3628 LIST_REMOVE(valid_entry, next);
3631 * The entry have more numbers than requested,
3632 * create a new entry for alloc_list and minus its
3633 * queue base and number in free_list.
3635 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3636 if (entry == NULL) {
3637 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3641 entry->base = valid_entry->base;
3643 valid_entry->base += num;
3644 valid_entry->len -= num;
3645 valid_entry = entry;
3648 /* Insert it into alloc list, not sorted */
3649 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3651 pool->num_free -= valid_entry->len;
3652 pool->num_alloc += valid_entry->len;
3654 return valid_entry->base + pool->base;
3658 * bitmap_is_subset - Check whether src2 is subset of src1
3661 bitmap_is_subset(uint8_t src1, uint8_t src2)
3663 return !((src1 ^ src2) & src2);
3666 static enum i40e_status_code
3667 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3669 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3671 /* If DCB is not supported, only default TC is supported */
3672 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3673 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3674 return I40E_NOT_SUPPORTED;
3677 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3678 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3679 "HW support 0x%x", hw->func_caps.enabled_tcmap,
3681 return I40E_NOT_SUPPORTED;
3683 return I40E_SUCCESS;
3687 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3688 struct i40e_vsi_vlan_pvid_info *info)
3691 struct i40e_vsi_context ctxt;
3692 uint8_t vlan_flags = 0;
3695 if (vsi == NULL || info == NULL) {
3696 PMD_DRV_LOG(ERR, "invalid parameters");
3697 return I40E_ERR_PARAM;
3701 vsi->info.pvid = info->config.pvid;
3703 * If insert pvid is enabled, only tagged pkts are
3704 * allowed to be sent out.
3706 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3707 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3710 if (info->config.reject.tagged == 0)
3711 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3713 if (info->config.reject.untagged == 0)
3714 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3716 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3717 I40E_AQ_VSI_PVLAN_MODE_MASK);
3718 vsi->info.port_vlan_flags |= vlan_flags;
3719 vsi->info.valid_sections =
3720 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3721 memset(&ctxt, 0, sizeof(ctxt));
3722 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3723 ctxt.seid = vsi->seid;
3725 hw = I40E_VSI_TO_HW(vsi);
3726 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3727 if (ret != I40E_SUCCESS)
3728 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3734 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3736 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3738 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3740 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3741 if (ret != I40E_SUCCESS)
3745 PMD_DRV_LOG(ERR, "seid not valid");
3749 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3750 tc_bw_data.tc_valid_bits = enabled_tcmap;
3751 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3752 tc_bw_data.tc_bw_credits[i] =
3753 (enabled_tcmap & (1 << i)) ? 1 : 0;
3755 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3756 if (ret != I40E_SUCCESS) {
3757 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3761 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3762 sizeof(vsi->info.qs_handle));
3763 return I40E_SUCCESS;
3766 static enum i40e_status_code
3767 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3768 struct i40e_aqc_vsi_properties_data *info,
3769 uint8_t enabled_tcmap)
3771 enum i40e_status_code ret;
3772 int i, total_tc = 0;
3773 uint16_t qpnum_per_tc, bsf, qp_idx;
3775 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3776 if (ret != I40E_SUCCESS)
3779 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3780 if (enabled_tcmap & (1 << i))
3782 vsi->enabled_tc = enabled_tcmap;
3784 /* Number of queues per enabled TC */
3785 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3786 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3787 bsf = rte_bsf32(qpnum_per_tc);
3789 /* Adjust the queue number to actual queues that can be applied */
3790 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3791 vsi->nb_qps = qpnum_per_tc * total_tc;
3794 * Configure TC and queue mapping parameters, for enabled TC,
3795 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3796 * default queue will serve it.
3799 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3800 if (vsi->enabled_tc & (1 << i)) {
3801 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3802 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3803 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
3804 qp_idx += qpnum_per_tc;
3806 info->tc_mapping[i] = 0;
3809 /* Associate queue number with VSI */
3810 if (vsi->type == I40E_VSI_SRIOV) {
3811 info->mapping_flags |=
3812 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
3813 for (i = 0; i < vsi->nb_qps; i++)
3814 info->queue_mapping[i] =
3815 rte_cpu_to_le_16(vsi->base_queue + i);
3817 info->mapping_flags |=
3818 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3819 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3821 info->valid_sections |=
3822 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
3824 return I40E_SUCCESS;
3828 i40e_veb_release(struct i40e_veb *veb)
3830 struct i40e_vsi *vsi;
3833 if (veb == NULL || veb->associate_vsi == NULL)
3836 if (!TAILQ_EMPTY(&veb->head)) {
3837 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
3841 vsi = veb->associate_vsi;
3842 hw = I40E_VSI_TO_HW(vsi);
3844 vsi->uplink_seid = veb->uplink_seid;
3845 i40e_aq_delete_element(hw, veb->seid, NULL);
3848 return I40E_SUCCESS;
3852 static struct i40e_veb *
3853 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
3855 struct i40e_veb *veb;
3859 if (NULL == pf || vsi == NULL) {
3860 PMD_DRV_LOG(ERR, "veb setup failed, "
3861 "associated VSI shouldn't null");
3864 hw = I40E_PF_TO_HW(pf);
3866 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
3868 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
3872 veb->associate_vsi = vsi;
3873 TAILQ_INIT(&veb->head);
3874 veb->uplink_seid = vsi->uplink_seid;
3876 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
3877 I40E_DEFAULT_TCMAP, false, &veb->seid, false, NULL);
3879 if (ret != I40E_SUCCESS) {
3880 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
3881 hw->aq.asq_last_status);
3885 /* get statistics index */
3886 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
3887 &veb->stats_idx, NULL, NULL, NULL);
3888 if (ret != I40E_SUCCESS) {
3889 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
3890 hw->aq.asq_last_status);
3894 /* Get VEB bandwidth, to be implemented */
3895 /* Now associated vsi binding to the VEB, set uplink to this VEB */
3896 vsi->uplink_seid = veb->seid;
3905 i40e_vsi_release(struct i40e_vsi *vsi)
3909 struct i40e_vsi_list *vsi_list;
3911 struct i40e_mac_filter *f;
3914 return I40E_SUCCESS;
3916 pf = I40E_VSI_TO_PF(vsi);
3917 hw = I40E_VSI_TO_HW(vsi);
3919 /* VSI has child to attach, release child first */
3921 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
3922 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
3924 TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
3926 i40e_veb_release(vsi->veb);
3929 /* Remove all macvlan filters of the VSI */
3930 i40e_vsi_remove_all_macvlan_filter(vsi);
3931 TAILQ_FOREACH(f, &vsi->mac_list, next)
3934 if (vsi->type != I40E_VSI_MAIN) {
3935 /* Remove vsi from parent's sibling list */
3936 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
3937 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
3938 return I40E_ERR_PARAM;
3940 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
3941 &vsi->sib_vsi_list, list);
3943 /* Remove all switch element of the VSI */
3944 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
3945 if (ret != I40E_SUCCESS)
3946 PMD_DRV_LOG(ERR, "Failed to delete element");
3948 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
3950 if (vsi->type != I40E_VSI_SRIOV)
3951 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
3954 return I40E_SUCCESS;
3958 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
3960 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3961 struct i40e_aqc_remove_macvlan_element_data def_filter;
3962 struct i40e_mac_filter_info filter;
3965 if (vsi->type != I40E_VSI_MAIN)
3966 return I40E_ERR_CONFIG;
3967 memset(&def_filter, 0, sizeof(def_filter));
3968 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
3970 def_filter.vlan_tag = 0;
3971 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
3972 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
3973 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
3974 if (ret != I40E_SUCCESS) {
3975 struct i40e_mac_filter *f;
3976 struct ether_addr *mac;
3978 PMD_DRV_LOG(WARNING, "Cannot remove the default "
3980 /* It needs to add the permanent mac into mac list */
3981 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3983 PMD_DRV_LOG(ERR, "failed to allocate memory");
3984 return I40E_ERR_NO_MEMORY;
3986 mac = &f->mac_info.mac_addr;
3987 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
3989 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3990 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3995 (void)rte_memcpy(&filter.mac_addr,
3996 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
3997 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3998 return i40e_vsi_add_mac(vsi, &filter);
4002 * i40e_vsi_get_bw_config - Query VSI BW Information
4003 * @vsi: the VSI to be queried
4005 * Returns 0 on success, negative value on failure
4007 static enum i40e_status_code
4008 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4010 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4011 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4012 struct i40e_hw *hw = &vsi->adapter->hw;
4017 memset(&bw_config, 0, sizeof(bw_config));
4018 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4019 if (ret != I40E_SUCCESS) {
4020 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4021 hw->aq.asq_last_status);
4025 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4026 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4027 &ets_sla_config, NULL);
4028 if (ret != I40E_SUCCESS) {
4029 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
4030 "configuration %u", hw->aq.asq_last_status);
4034 /* store and print out BW info */
4035 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4036 vsi->bw_info.bw_max = bw_config.max_bw;
4037 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4038 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4039 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4040 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4042 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4043 vsi->bw_info.bw_ets_share_credits[i] =
4044 ets_sla_config.share_credits[i];
4045 vsi->bw_info.bw_ets_credits[i] =
4046 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4047 /* 4 bits per TC, 4th bit is reserved */
4048 vsi->bw_info.bw_ets_max[i] =
4049 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4050 RTE_LEN2MASK(3, uint8_t));
4051 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4052 vsi->bw_info.bw_ets_share_credits[i]);
4053 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4054 vsi->bw_info.bw_ets_credits[i]);
4055 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4056 vsi->bw_info.bw_ets_max[i]);
4059 return I40E_SUCCESS;
4062 /* i40e_enable_pf_lb
4063 * @pf: pointer to the pf structure
4065 * allow loopback on pf
4068 i40e_enable_pf_lb(struct i40e_pf *pf)
4070 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4071 struct i40e_vsi_context ctxt;
4074 /* Use the FW API if FW >= v5.0 */
4075 if (hw->aq.fw_maj_ver < 5) {
4076 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4080 memset(&ctxt, 0, sizeof(ctxt));
4081 ctxt.seid = pf->main_vsi_seid;
4082 ctxt.pf_num = hw->pf_id;
4083 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4085 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4086 ret, hw->aq.asq_last_status);
4089 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4090 ctxt.info.valid_sections =
4091 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4092 ctxt.info.switch_id |=
4093 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4095 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4097 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
4098 hw->aq.asq_last_status);
4103 i40e_vsi_setup(struct i40e_pf *pf,
4104 enum i40e_vsi_type type,
4105 struct i40e_vsi *uplink_vsi,
4106 uint16_t user_param)
4108 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4109 struct i40e_vsi *vsi;
4110 struct i40e_mac_filter_info filter;
4112 struct i40e_vsi_context ctxt;
4113 struct ether_addr broadcast =
4114 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4116 if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
4117 PMD_DRV_LOG(ERR, "VSI setup failed, "
4118 "VSI link shouldn't be NULL");
4122 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4123 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
4124 "uplink VSI should be NULL");
4128 /* If uplink vsi didn't setup VEB, create one first */
4129 if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
4130 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4132 if (NULL == uplink_vsi->veb) {
4133 PMD_DRV_LOG(ERR, "VEB setup failed");
4136 /* set ALLOWLOOPBACk on pf, when veb is created */
4137 i40e_enable_pf_lb(pf);
4140 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4142 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4145 TAILQ_INIT(&vsi->mac_list);
4147 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4148 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4149 vsi->parent_vsi = uplink_vsi;
4150 vsi->user_param = user_param;
4151 /* Allocate queues */
4152 switch (vsi->type) {
4153 case I40E_VSI_MAIN :
4154 vsi->nb_qps = pf->lan_nb_qps;
4156 case I40E_VSI_SRIOV :
4157 vsi->nb_qps = pf->vf_nb_qps;
4159 case I40E_VSI_VMDQ2:
4160 vsi->nb_qps = pf->vmdq_nb_qps;
4163 vsi->nb_qps = pf->fdir_nb_qps;
4169 * The filter status descriptor is reported in rx queue 0,
4170 * while the tx queue for fdir filter programming has no
4171 * such constraints, can be non-zero queues.
4172 * To simplify it, choose FDIR vsi use queue 0 pair.
4173 * To make sure it will use queue 0 pair, queue allocation
4174 * need be done before this function is called
4176 if (type != I40E_VSI_FDIR) {
4177 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4179 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4183 vsi->base_queue = ret;
4185 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4187 /* VF has MSIX interrupt in VF range, don't allocate here */
4188 if (type == I40E_VSI_MAIN) {
4189 ret = i40e_res_pool_alloc(&pf->msix_pool,
4190 RTE_MIN(vsi->nb_qps,
4191 RTE_MAX_RXTX_INTR_VEC_ID));
4193 PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4195 goto fail_queue_alloc;
4197 vsi->msix_intr = ret;
4198 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4199 } else if (type != I40E_VSI_SRIOV) {
4200 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4202 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4203 goto fail_queue_alloc;
4205 vsi->msix_intr = ret;
4213 if (type == I40E_VSI_MAIN) {
4214 /* For main VSI, no need to add since it's default one */
4215 vsi->uplink_seid = pf->mac_seid;
4216 vsi->seid = pf->main_vsi_seid;
4217 /* Bind queues with specific MSIX interrupt */
4219 * Needs 2 interrupt at least, one for misc cause which will
4220 * enabled from OS side, Another for queues binding the
4221 * interrupt from device side only.
4224 /* Get default VSI parameters from hardware */
4225 memset(&ctxt, 0, sizeof(ctxt));
4226 ctxt.seid = vsi->seid;
4227 ctxt.pf_num = hw->pf_id;
4228 ctxt.uplink_seid = vsi->uplink_seid;
4230 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4231 if (ret != I40E_SUCCESS) {
4232 PMD_DRV_LOG(ERR, "Failed to get VSI params");
4233 goto fail_msix_alloc;
4235 (void)rte_memcpy(&vsi->info, &ctxt.info,
4236 sizeof(struct i40e_aqc_vsi_properties_data));
4237 vsi->vsi_id = ctxt.vsi_number;
4238 vsi->info.valid_sections = 0;
4240 /* Configure tc, enabled TC0 only */
4241 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4243 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4244 goto fail_msix_alloc;
4247 /* TC, queue mapping */
4248 memset(&ctxt, 0, sizeof(ctxt));
4249 vsi->info.valid_sections |=
4250 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4251 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4252 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4253 (void)rte_memcpy(&ctxt.info, &vsi->info,
4254 sizeof(struct i40e_aqc_vsi_properties_data));
4255 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4256 I40E_DEFAULT_TCMAP);
4257 if (ret != I40E_SUCCESS) {
4258 PMD_DRV_LOG(ERR, "Failed to configure "
4259 "TC queue mapping");
4260 goto fail_msix_alloc;
4262 ctxt.seid = vsi->seid;
4263 ctxt.pf_num = hw->pf_id;
4264 ctxt.uplink_seid = vsi->uplink_seid;
4267 /* Update VSI parameters */
4268 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4269 if (ret != I40E_SUCCESS) {
4270 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4271 goto fail_msix_alloc;
4274 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4275 sizeof(vsi->info.tc_mapping));
4276 (void)rte_memcpy(&vsi->info.queue_mapping,
4277 &ctxt.info.queue_mapping,
4278 sizeof(vsi->info.queue_mapping));
4279 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4280 vsi->info.valid_sections = 0;
4282 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4286 * Updating default filter settings are necessary to prevent
4287 * reception of tagged packets.
4288 * Some old firmware configurations load a default macvlan
4289 * filter which accepts both tagged and untagged packets.
4290 * The updating is to use a normal filter instead if needed.
4291 * For NVM 4.2.2 or after, the updating is not needed anymore.
4292 * The firmware with correct configurations load the default
4293 * macvlan filter which is expected and cannot be removed.
4295 i40e_update_default_filter_setting(vsi);
4296 i40e_config_qinq(hw, vsi);
4297 } else if (type == I40E_VSI_SRIOV) {
4298 memset(&ctxt, 0, sizeof(ctxt));
4300 * For other VSI, the uplink_seid equals to uplink VSI's
4301 * uplink_seid since they share same VEB
4303 vsi->uplink_seid = uplink_vsi->uplink_seid;
4304 ctxt.pf_num = hw->pf_id;
4305 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4306 ctxt.uplink_seid = vsi->uplink_seid;
4307 ctxt.connection_type = 0x1;
4308 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4310 /* Use the VEB configuration if FW >= v5.0 */
4311 if (hw->aq.fw_maj_ver >= 5) {
4312 /* Configure switch ID */
4313 ctxt.info.valid_sections |=
4314 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4315 ctxt.info.switch_id =
4316 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4319 /* Configure port/vlan */
4320 ctxt.info.valid_sections |=
4321 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4322 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4323 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4324 I40E_DEFAULT_TCMAP);
4325 if (ret != I40E_SUCCESS) {
4326 PMD_DRV_LOG(ERR, "Failed to configure "
4327 "TC queue mapping");
4328 goto fail_msix_alloc;
4330 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4331 ctxt.info.valid_sections |=
4332 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4334 * Since VSI is not created yet, only configure parameter,
4335 * will add vsi below.
4338 i40e_config_qinq(hw, vsi);
4339 } else if (type == I40E_VSI_VMDQ2) {
4340 memset(&ctxt, 0, sizeof(ctxt));
4342 * For other VSI, the uplink_seid equals to uplink VSI's
4343 * uplink_seid since they share same VEB
4345 vsi->uplink_seid = uplink_vsi->uplink_seid;
4346 ctxt.pf_num = hw->pf_id;
4348 ctxt.uplink_seid = vsi->uplink_seid;
4349 ctxt.connection_type = 0x1;
4350 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4352 ctxt.info.valid_sections |=
4353 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4354 /* user_param carries flag to enable loop back */
4356 ctxt.info.switch_id =
4357 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4358 ctxt.info.switch_id |=
4359 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4362 /* Configure port/vlan */
4363 ctxt.info.valid_sections |=
4364 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4365 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4366 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4367 I40E_DEFAULT_TCMAP);
4368 if (ret != I40E_SUCCESS) {
4369 PMD_DRV_LOG(ERR, "Failed to configure "
4370 "TC queue mapping");
4371 goto fail_msix_alloc;
4373 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4374 ctxt.info.valid_sections |=
4375 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4376 } else if (type == I40E_VSI_FDIR) {
4377 memset(&ctxt, 0, sizeof(ctxt));
4378 vsi->uplink_seid = uplink_vsi->uplink_seid;
4379 ctxt.pf_num = hw->pf_id;
4381 ctxt.uplink_seid = vsi->uplink_seid;
4382 ctxt.connection_type = 0x1; /* regular data port */
4383 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4384 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4385 I40E_DEFAULT_TCMAP);
4386 if (ret != I40E_SUCCESS) {
4387 PMD_DRV_LOG(ERR, "Failed to configure "
4388 "TC queue mapping.");
4389 goto fail_msix_alloc;
4391 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4392 ctxt.info.valid_sections |=
4393 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4395 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4396 goto fail_msix_alloc;
4399 if (vsi->type != I40E_VSI_MAIN) {
4400 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4401 if (ret != I40E_SUCCESS) {
4402 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4403 hw->aq.asq_last_status);
4404 goto fail_msix_alloc;
4406 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4407 vsi->info.valid_sections = 0;
4408 vsi->seid = ctxt.seid;
4409 vsi->vsi_id = ctxt.vsi_number;
4410 vsi->sib_vsi_list.vsi = vsi;
4411 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4412 &vsi->sib_vsi_list, list);
4415 /* MAC/VLAN configuration */
4416 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4417 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4419 ret = i40e_vsi_add_mac(vsi, &filter);
4420 if (ret != I40E_SUCCESS) {
4421 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4422 goto fail_msix_alloc;
4425 /* Get VSI BW information */
4426 i40e_vsi_get_bw_config(vsi);
4429 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4431 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4437 /* Configure vlan filter on or off */
4439 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4442 struct i40e_mac_filter *f;
4443 struct i40e_mac_filter_info *mac_filter;
4444 enum rte_mac_filter_type desired_filter;
4445 int ret = I40E_SUCCESS;
4448 /* Filter to match MAC and VLAN */
4449 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4451 /* Filter to match only MAC */
4452 desired_filter = RTE_MAC_PERFECT_MATCH;
4457 mac_filter = rte_zmalloc("mac_filter_info_data",
4458 num * sizeof(*mac_filter), 0);
4459 if (mac_filter == NULL) {
4460 PMD_DRV_LOG(ERR, "failed to allocate memory");
4461 return I40E_ERR_NO_MEMORY;
4466 /* Remove all existing mac */
4467 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4468 mac_filter[i] = f->mac_info;
4469 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4471 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4472 on ? "enable" : "disable");
4478 /* Override with new filter */
4479 for (i = 0; i < num; i++) {
4480 mac_filter[i].filter_type = desired_filter;
4481 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4483 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4484 on ? "enable" : "disable");
4490 rte_free(mac_filter);
4494 /* Configure vlan stripping on or off */
4496 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4498 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4499 struct i40e_vsi_context ctxt;
4501 int ret = I40E_SUCCESS;
4503 /* Check if it has been already on or off */
4504 if (vsi->info.valid_sections &
4505 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4507 if ((vsi->info.port_vlan_flags &
4508 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4509 return 0; /* already on */
4511 if ((vsi->info.port_vlan_flags &
4512 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4513 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4514 return 0; /* already off */
4519 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4521 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4522 vsi->info.valid_sections =
4523 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4524 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4525 vsi->info.port_vlan_flags |= vlan_flags;
4526 ctxt.seid = vsi->seid;
4527 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4528 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4530 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4531 on ? "enable" : "disable");
4537 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4539 struct rte_eth_dev_data *data = dev->data;
4543 /* Apply vlan offload setting */
4544 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
4545 i40e_vlan_offload_set(dev, mask);
4547 /* Apply double-vlan setting, not implemented yet */
4549 /* Apply pvid setting */
4550 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4551 data->dev_conf.txmode.hw_vlan_insert_pvid);
4553 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4559 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4561 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4563 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4567 i40e_update_flow_control(struct i40e_hw *hw)
4569 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4570 struct i40e_link_status link_status;
4571 uint32_t rxfc = 0, txfc = 0, reg;
4575 memset(&link_status, 0, sizeof(link_status));
4576 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4577 if (ret != I40E_SUCCESS) {
4578 PMD_DRV_LOG(ERR, "Failed to get link status information");
4579 goto write_reg; /* Disable flow control */
4582 an_info = hw->phy.link_info.an_info;
4583 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4584 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4585 ret = I40E_ERR_NOT_READY;
4586 goto write_reg; /* Disable flow control */
4589 * If link auto negotiation is enabled, flow control needs to
4590 * be configured according to it
4592 switch (an_info & I40E_LINK_PAUSE_RXTX) {
4593 case I40E_LINK_PAUSE_RXTX:
4596 hw->fc.current_mode = I40E_FC_FULL;
4598 case I40E_AQ_LINK_PAUSE_RX:
4600 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4602 case I40E_AQ_LINK_PAUSE_TX:
4604 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4607 hw->fc.current_mode = I40E_FC_NONE;
4612 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4613 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4614 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4615 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4616 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4617 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4624 i40e_pf_setup(struct i40e_pf *pf)
4626 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4627 struct i40e_filter_control_settings settings;
4628 struct i40e_vsi *vsi;
4631 /* Clear all stats counters */
4632 pf->offset_loaded = FALSE;
4633 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4634 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4636 ret = i40e_pf_get_switch_config(pf);
4637 if (ret != I40E_SUCCESS) {
4638 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4641 if (pf->flags & I40E_FLAG_FDIR) {
4642 /* make queue allocated first, let FDIR use queue pair 0*/
4643 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4644 if (ret != I40E_FDIR_QUEUE_ID) {
4645 PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4647 pf->flags &= ~I40E_FLAG_FDIR;
4650 /* main VSI setup */
4651 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4653 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4654 return I40E_ERR_NOT_READY;
4658 /* Configure filter control */
4659 memset(&settings, 0, sizeof(settings));
4660 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4661 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4662 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4663 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4665 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4666 hw->func_caps.rss_table_size);
4667 return I40E_ERR_PARAM;
4669 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4670 "size: %u\n", hw->func_caps.rss_table_size);
4671 pf->hash_lut_size = hw->func_caps.rss_table_size;
4673 /* Enable ethtype and macvlan filters */
4674 settings.enable_ethtype = TRUE;
4675 settings.enable_macvlan = TRUE;
4676 ret = i40e_set_filter_control(hw, &settings);
4678 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4681 /* Update flow control according to the auto negotiation */
4682 i40e_update_flow_control(hw);
4684 return I40E_SUCCESS;
4688 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4694 * Set or clear TX Queue Disable flags,
4695 * which is required by hardware.
4697 i40e_pre_tx_queue_cfg(hw, q_idx, on);
4698 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4700 /* Wait until the request is finished */
4701 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4702 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4703 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4704 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4705 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4711 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4712 return I40E_SUCCESS; /* already on, skip next steps */
4714 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4715 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4717 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4718 return I40E_SUCCESS; /* already off, skip next steps */
4719 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4721 /* Write the register */
4722 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4723 /* Check the result */
4724 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4725 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4726 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4728 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4729 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
4732 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4733 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4737 /* Check if it is timeout */
4738 if (j >= I40E_CHK_Q_ENA_COUNT) {
4739 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
4740 (on ? "enable" : "disable"), q_idx);
4741 return I40E_ERR_TIMEOUT;
4744 return I40E_SUCCESS;
4747 /* Swith on or off the tx queues */
4749 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
4751 struct rte_eth_dev_data *dev_data = pf->dev_data;
4752 struct i40e_tx_queue *txq;
4753 struct rte_eth_dev *dev = pf->adapter->eth_dev;
4757 for (i = 0; i < dev_data->nb_tx_queues; i++) {
4758 txq = dev_data->tx_queues[i];
4759 /* Don't operate the queue if not configured or
4760 * if starting only per queue */
4761 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
4764 ret = i40e_dev_tx_queue_start(dev, i);
4766 ret = i40e_dev_tx_queue_stop(dev, i);
4767 if ( ret != I40E_SUCCESS)
4771 return I40E_SUCCESS;
4775 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4780 /* Wait until the request is finished */
4781 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4782 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4783 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4784 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4785 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
4790 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
4791 return I40E_SUCCESS; /* Already on, skip next steps */
4792 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
4794 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4795 return I40E_SUCCESS; /* Already off, skip next steps */
4796 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
4799 /* Write the register */
4800 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
4801 /* Check the result */
4802 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4803 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4804 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4806 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4807 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
4810 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4811 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4816 /* Check if it is timeout */
4817 if (j >= I40E_CHK_Q_ENA_COUNT) {
4818 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
4819 (on ? "enable" : "disable"), q_idx);
4820 return I40E_ERR_TIMEOUT;
4823 return I40E_SUCCESS;
4825 /* Switch on or off the rx queues */
4827 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
4829 struct rte_eth_dev_data *dev_data = pf->dev_data;
4830 struct i40e_rx_queue *rxq;
4831 struct rte_eth_dev *dev = pf->adapter->eth_dev;
4835 for (i = 0; i < dev_data->nb_rx_queues; i++) {
4836 rxq = dev_data->rx_queues[i];
4837 /* Don't operate the queue if not configured or
4838 * if starting only per queue */
4839 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
4842 ret = i40e_dev_rx_queue_start(dev, i);
4844 ret = i40e_dev_rx_queue_stop(dev, i);
4845 if (ret != I40E_SUCCESS)
4849 return I40E_SUCCESS;
4852 /* Switch on or off all the rx/tx queues */
4854 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
4859 /* enable rx queues before enabling tx queues */
4860 ret = i40e_dev_switch_rx_queues(pf, on);
4862 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
4865 ret = i40e_dev_switch_tx_queues(pf, on);
4867 /* Stop tx queues before stopping rx queues */
4868 ret = i40e_dev_switch_tx_queues(pf, on);
4870 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
4873 ret = i40e_dev_switch_rx_queues(pf, on);
4879 /* Initialize VSI for TX */
4881 i40e_dev_tx_init(struct i40e_pf *pf)
4883 struct rte_eth_dev_data *data = pf->dev_data;
4885 uint32_t ret = I40E_SUCCESS;
4886 struct i40e_tx_queue *txq;
4888 for (i = 0; i < data->nb_tx_queues; i++) {
4889 txq = data->tx_queues[i];
4890 if (!txq || !txq->q_set)
4892 ret = i40e_tx_queue_init(txq);
4893 if (ret != I40E_SUCCESS)
4896 if (ret == I40E_SUCCESS)
4897 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
4903 /* Initialize VSI for RX */
4905 i40e_dev_rx_init(struct i40e_pf *pf)
4907 struct rte_eth_dev_data *data = pf->dev_data;
4908 int ret = I40E_SUCCESS;
4910 struct i40e_rx_queue *rxq;
4912 i40e_pf_config_mq_rx(pf);
4913 for (i = 0; i < data->nb_rx_queues; i++) {
4914 rxq = data->rx_queues[i];
4915 if (!rxq || !rxq->q_set)
4918 ret = i40e_rx_queue_init(rxq);
4919 if (ret != I40E_SUCCESS) {
4920 PMD_DRV_LOG(ERR, "Failed to do RX queue "
4925 if (ret == I40E_SUCCESS)
4926 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
4933 i40e_dev_rxtx_init(struct i40e_pf *pf)
4937 err = i40e_dev_tx_init(pf);
4939 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
4942 err = i40e_dev_rx_init(pf);
4944 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
4952 i40e_vmdq_setup(struct rte_eth_dev *dev)
4954 struct rte_eth_conf *conf = &dev->data->dev_conf;
4955 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4956 int i, err, conf_vsis, j, loop;
4957 struct i40e_vsi *vsi;
4958 struct i40e_vmdq_info *vmdq_info;
4959 struct rte_eth_vmdq_rx_conf *vmdq_conf;
4960 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4963 * Disable interrupt to avoid message from VF. Furthermore, it will
4964 * avoid race condition in VSI creation/destroy.
4966 i40e_pf_disable_irq0(hw);
4968 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
4969 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
4973 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
4974 if (conf_vsis > pf->max_nb_vmdq_vsi) {
4975 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
4976 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
4977 pf->max_nb_vmdq_vsi);
4981 if (pf->vmdq != NULL) {
4982 PMD_INIT_LOG(INFO, "VMDQ already configured");
4986 pf->vmdq = rte_zmalloc("vmdq_info_struct",
4987 sizeof(*vmdq_info) * conf_vsis, 0);
4989 if (pf->vmdq == NULL) {
4990 PMD_INIT_LOG(ERR, "Failed to allocate memory");
4994 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
4996 /* Create VMDQ VSI */
4997 for (i = 0; i < conf_vsis; i++) {
4998 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
4999 vmdq_conf->enable_loop_back);
5001 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5005 vmdq_info = &pf->vmdq[i];
5007 vmdq_info->vsi = vsi;
5009 pf->nb_cfg_vmdq_vsi = conf_vsis;
5011 /* Configure Vlan */
5012 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5013 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5014 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5015 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5016 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5017 vmdq_conf->pool_map[i].vlan_id, j);
5019 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5020 vmdq_conf->pool_map[i].vlan_id);
5022 PMD_INIT_LOG(ERR, "Failed to add vlan");
5030 i40e_pf_enable_irq0(hw);
5035 for (i = 0; i < conf_vsis; i++)
5036 if (pf->vmdq[i].vsi == NULL)
5039 i40e_vsi_release(pf->vmdq[i].vsi);
5043 i40e_pf_enable_irq0(hw);
5048 i40e_stat_update_32(struct i40e_hw *hw,
5056 new_data = (uint64_t)I40E_READ_REG(hw, reg);
5060 if (new_data >= *offset)
5061 *stat = (uint64_t)(new_data - *offset);
5063 *stat = (uint64_t)((new_data +
5064 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5068 i40e_stat_update_48(struct i40e_hw *hw,
5077 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5078 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5079 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5084 if (new_data >= *offset)
5085 *stat = new_data - *offset;
5087 *stat = (uint64_t)((new_data +
5088 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5090 *stat &= I40E_48_BIT_MASK;
5095 i40e_pf_disable_irq0(struct i40e_hw *hw)
5097 /* Disable all interrupt types */
5098 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5099 I40E_WRITE_FLUSH(hw);
5104 i40e_pf_enable_irq0(struct i40e_hw *hw)
5106 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5107 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5108 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5109 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5110 I40E_WRITE_FLUSH(hw);
5114 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5116 /* read pending request and disable first */
5117 i40e_pf_disable_irq0(hw);
5118 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5119 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5120 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5123 /* Link no queues with irq0 */
5124 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5125 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5129 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5131 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5132 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5135 uint32_t index, offset, val;
5140 * Try to find which VF trigger a reset, use absolute VF id to access
5141 * since the reg is global register.
5143 for (i = 0; i < pf->vf_num; i++) {
5144 abs_vf_id = hw->func_caps.vf_base_id + i;
5145 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5146 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5147 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5148 /* VFR event occured */
5149 if (val & (0x1 << offset)) {
5152 /* Clear the event first */
5153 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5155 PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5157 * Only notify a VF reset event occured,
5158 * don't trigger another SW reset
5160 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5161 if (ret != I40E_SUCCESS)
5162 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5168 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5170 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5171 struct i40e_arq_event_info info;
5172 uint16_t pending, opcode;
5175 info.buf_len = I40E_AQ_BUF_SZ;
5176 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5177 if (!info.msg_buf) {
5178 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5184 ret = i40e_clean_arq_element(hw, &info, &pending);
5186 if (ret != I40E_SUCCESS) {
5187 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5188 "aq_err: %u", hw->aq.asq_last_status);
5191 opcode = rte_le_to_cpu_16(info.desc.opcode);
5194 case i40e_aqc_opc_send_msg_to_pf:
5195 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5196 i40e_pf_host_handle_vf_msg(dev,
5197 rte_le_to_cpu_16(info.desc.retval),
5198 rte_le_to_cpu_32(info.desc.cookie_high),
5199 rte_le_to_cpu_32(info.desc.cookie_low),
5204 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5209 rte_free(info.msg_buf);
5213 * Interrupt handler is registered as the alarm callback for handling LSC
5214 * interrupt in a definite of time, in order to wait the NIC into a stable
5215 * state. Currently it waits 1 sec in i40e for the link up interrupt, and
5216 * no need for link down interrupt.
5219 i40e_dev_interrupt_delayed_handler(void *param)
5221 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5222 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5225 /* read interrupt causes again */
5226 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5228 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5229 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5230 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
5231 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5232 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
5233 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5234 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
5235 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5236 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
5237 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5238 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
5240 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5241 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
5242 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5243 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
5244 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5246 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5247 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
5248 i40e_dev_handle_vfr_event(dev);
5250 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5251 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
5252 i40e_dev_handle_aq_msg(dev);
5255 /* handle the link up interrupt in an alarm callback */
5256 i40e_dev_link_update(dev, 0);
5257 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
5259 i40e_pf_enable_irq0(hw);
5260 rte_intr_enable(&(dev->pci_dev->intr_handle));
5264 * Interrupt handler triggered by NIC for handling
5265 * specific interrupt.
5268 * Pointer to interrupt handle.
5270 * The address of parameter (struct rte_eth_dev *) regsitered before.
5276 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
5279 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5280 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5283 /* Disable interrupt */
5284 i40e_pf_disable_irq0(hw);
5286 /* read out interrupt causes */
5287 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5289 /* No interrupt event indicated */
5290 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5291 PMD_DRV_LOG(INFO, "No interrupt event");
5294 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5295 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5296 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5297 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5298 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5299 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5300 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5301 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5302 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5303 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5304 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5305 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5306 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5307 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5308 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5309 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5311 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5312 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5313 i40e_dev_handle_vfr_event(dev);
5315 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5316 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5317 i40e_dev_handle_aq_msg(dev);
5320 /* Link Status Change interrupt */
5321 if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
5322 #define I40E_US_PER_SECOND 1000000
5323 struct rte_eth_link link;
5325 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
5326 memset(&link, 0, sizeof(link));
5327 rte_i40e_dev_atomic_read_link_status(dev, &link);
5328 i40e_dev_link_update(dev, 0);
5331 * For link up interrupt, it needs to wait 1 second to let the
5332 * hardware be a stable state. Otherwise several consecutive
5333 * interrupts can be observed.
5334 * For link down interrupt, no need to wait.
5336 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
5337 i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
5340 _rte_eth_dev_callback_process(dev,
5341 RTE_ETH_EVENT_INTR_LSC);
5345 /* Enable interrupt */
5346 i40e_pf_enable_irq0(hw);
5347 rte_intr_enable(&(dev->pci_dev->intr_handle));
5351 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5352 struct i40e_macvlan_filter *filter,
5355 int ele_num, ele_buff_size;
5356 int num, actual_num, i;
5358 int ret = I40E_SUCCESS;
5359 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5360 struct i40e_aqc_add_macvlan_element_data *req_list;
5362 if (filter == NULL || total == 0)
5363 return I40E_ERR_PARAM;
5364 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5365 ele_buff_size = hw->aq.asq_buf_size;
5367 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5368 if (req_list == NULL) {
5369 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5370 return I40E_ERR_NO_MEMORY;
5375 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5376 memset(req_list, 0, ele_buff_size);
5378 for (i = 0; i < actual_num; i++) {
5379 (void)rte_memcpy(req_list[i].mac_addr,
5380 &filter[num + i].macaddr, ETH_ADDR_LEN);
5381 req_list[i].vlan_tag =
5382 rte_cpu_to_le_16(filter[num + i].vlan_id);
5384 switch (filter[num + i].filter_type) {
5385 case RTE_MAC_PERFECT_MATCH:
5386 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5387 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5389 case RTE_MACVLAN_PERFECT_MATCH:
5390 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5392 case RTE_MAC_HASH_MATCH:
5393 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5394 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5396 case RTE_MACVLAN_HASH_MATCH:
5397 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5400 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5401 ret = I40E_ERR_PARAM;
5405 req_list[i].queue_number = 0;
5407 req_list[i].flags = rte_cpu_to_le_16(flags);
5410 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5412 if (ret != I40E_SUCCESS) {
5413 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5417 } while (num < total);
5425 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5426 struct i40e_macvlan_filter *filter,
5429 int ele_num, ele_buff_size;
5430 int num, actual_num, i;
5432 int ret = I40E_SUCCESS;
5433 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5434 struct i40e_aqc_remove_macvlan_element_data *req_list;
5436 if (filter == NULL || total == 0)
5437 return I40E_ERR_PARAM;
5439 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5440 ele_buff_size = hw->aq.asq_buf_size;
5442 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5443 if (req_list == NULL) {
5444 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5445 return I40E_ERR_NO_MEMORY;
5450 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5451 memset(req_list, 0, ele_buff_size);
5453 for (i = 0; i < actual_num; i++) {
5454 (void)rte_memcpy(req_list[i].mac_addr,
5455 &filter[num + i].macaddr, ETH_ADDR_LEN);
5456 req_list[i].vlan_tag =
5457 rte_cpu_to_le_16(filter[num + i].vlan_id);
5459 switch (filter[num + i].filter_type) {
5460 case RTE_MAC_PERFECT_MATCH:
5461 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5462 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5464 case RTE_MACVLAN_PERFECT_MATCH:
5465 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5467 case RTE_MAC_HASH_MATCH:
5468 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5469 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5471 case RTE_MACVLAN_HASH_MATCH:
5472 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5475 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5476 ret = I40E_ERR_PARAM;
5479 req_list[i].flags = rte_cpu_to_le_16(flags);
5482 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5484 if (ret != I40E_SUCCESS) {
5485 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5489 } while (num < total);
5496 /* Find out specific MAC filter */
5497 static struct i40e_mac_filter *
5498 i40e_find_mac_filter(struct i40e_vsi *vsi,
5499 struct ether_addr *macaddr)
5501 struct i40e_mac_filter *f;
5503 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5504 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5512 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5515 uint32_t vid_idx, vid_bit;
5517 if (vlan_id > ETH_VLAN_ID_MAX)
5520 vid_idx = I40E_VFTA_IDX(vlan_id);
5521 vid_bit = I40E_VFTA_BIT(vlan_id);
5523 if (vsi->vfta[vid_idx] & vid_bit)
5530 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5531 uint16_t vlan_id, bool on)
5533 uint32_t vid_idx, vid_bit;
5535 if (vlan_id > ETH_VLAN_ID_MAX)
5538 vid_idx = I40E_VFTA_IDX(vlan_id);
5539 vid_bit = I40E_VFTA_BIT(vlan_id);
5542 vsi->vfta[vid_idx] |= vid_bit;
5544 vsi->vfta[vid_idx] &= ~vid_bit;
5548 * Find all vlan options for specific mac addr,
5549 * return with actual vlan found.
5552 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5553 struct i40e_macvlan_filter *mv_f,
5554 int num, struct ether_addr *addr)
5560 * Not to use i40e_find_vlan_filter to decrease the loop time,
5561 * although the code looks complex.
5563 if (num < vsi->vlan_num)
5564 return I40E_ERR_PARAM;
5567 for (j = 0; j < I40E_VFTA_SIZE; j++) {
5569 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5570 if (vsi->vfta[j] & (1 << k)) {
5572 PMD_DRV_LOG(ERR, "vlan number "
5574 return I40E_ERR_PARAM;
5576 (void)rte_memcpy(&mv_f[i].macaddr,
5577 addr, ETH_ADDR_LEN);
5579 j * I40E_UINT32_BIT_SIZE + k;
5585 return I40E_SUCCESS;
5589 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5590 struct i40e_macvlan_filter *mv_f,
5595 struct i40e_mac_filter *f;
5597 if (num < vsi->mac_num)
5598 return I40E_ERR_PARAM;
5600 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5602 PMD_DRV_LOG(ERR, "buffer number not match");
5603 return I40E_ERR_PARAM;
5605 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5607 mv_f[i].vlan_id = vlan;
5608 mv_f[i].filter_type = f->mac_info.filter_type;
5612 return I40E_SUCCESS;
5616 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5619 struct i40e_mac_filter *f;
5620 struct i40e_macvlan_filter *mv_f;
5621 int ret = I40E_SUCCESS;
5623 if (vsi == NULL || vsi->mac_num == 0)
5624 return I40E_ERR_PARAM;
5626 /* Case that no vlan is set */
5627 if (vsi->vlan_num == 0)
5630 num = vsi->mac_num * vsi->vlan_num;
5632 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5634 PMD_DRV_LOG(ERR, "failed to allocate memory");
5635 return I40E_ERR_NO_MEMORY;
5639 if (vsi->vlan_num == 0) {
5640 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5641 (void)rte_memcpy(&mv_f[i].macaddr,
5642 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5643 mv_f[i].vlan_id = 0;
5647 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5648 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5649 vsi->vlan_num, &f->mac_info.mac_addr);
5650 if (ret != I40E_SUCCESS)
5656 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5664 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5666 struct i40e_macvlan_filter *mv_f;
5668 int ret = I40E_SUCCESS;
5670 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5671 return I40E_ERR_PARAM;
5673 /* If it's already set, just return */
5674 if (i40e_find_vlan_filter(vsi,vlan))
5675 return I40E_SUCCESS;
5677 mac_num = vsi->mac_num;
5680 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5681 return I40E_ERR_PARAM;
5684 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5687 PMD_DRV_LOG(ERR, "failed to allocate memory");
5688 return I40E_ERR_NO_MEMORY;
5691 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5693 if (ret != I40E_SUCCESS)
5696 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5698 if (ret != I40E_SUCCESS)
5701 i40e_set_vlan_filter(vsi, vlan, 1);
5711 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5713 struct i40e_macvlan_filter *mv_f;
5715 int ret = I40E_SUCCESS;
5718 * Vlan 0 is the generic filter for untagged packets
5719 * and can't be removed.
5721 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5722 return I40E_ERR_PARAM;
5724 /* If can't find it, just return */
5725 if (!i40e_find_vlan_filter(vsi, vlan))
5726 return I40E_ERR_PARAM;
5728 mac_num = vsi->mac_num;
5731 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5732 return I40E_ERR_PARAM;
5735 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5738 PMD_DRV_LOG(ERR, "failed to allocate memory");
5739 return I40E_ERR_NO_MEMORY;
5742 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5744 if (ret != I40E_SUCCESS)
5747 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5749 if (ret != I40E_SUCCESS)
5752 /* This is last vlan to remove, replace all mac filter with vlan 0 */
5753 if (vsi->vlan_num == 1) {
5754 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5755 if (ret != I40E_SUCCESS)
5758 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5759 if (ret != I40E_SUCCESS)
5763 i40e_set_vlan_filter(vsi, vlan, 0);
5773 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
5775 struct i40e_mac_filter *f;
5776 struct i40e_macvlan_filter *mv_f;
5777 int i, vlan_num = 0;
5778 int ret = I40E_SUCCESS;
5780 /* If it's add and we've config it, return */
5781 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
5783 return I40E_SUCCESS;
5784 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
5785 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
5788 * If vlan_num is 0, that's the first time to add mac,
5789 * set mask for vlan_id 0.
5791 if (vsi->vlan_num == 0) {
5792 i40e_set_vlan_filter(vsi, 0, 1);
5795 vlan_num = vsi->vlan_num;
5796 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
5797 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
5800 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5802 PMD_DRV_LOG(ERR, "failed to allocate memory");
5803 return I40E_ERR_NO_MEMORY;
5806 for (i = 0; i < vlan_num; i++) {
5807 mv_f[i].filter_type = mac_filter->filter_type;
5808 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
5812 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5813 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
5814 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
5815 &mac_filter->mac_addr);
5816 if (ret != I40E_SUCCESS)
5820 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
5821 if (ret != I40E_SUCCESS)
5824 /* Add the mac addr into mac list */
5825 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5827 PMD_DRV_LOG(ERR, "failed to allocate memory");
5828 ret = I40E_ERR_NO_MEMORY;
5831 (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
5833 f->mac_info.filter_type = mac_filter->filter_type;
5834 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5845 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
5847 struct i40e_mac_filter *f;
5848 struct i40e_macvlan_filter *mv_f;
5850 enum rte_mac_filter_type filter_type;
5851 int ret = I40E_SUCCESS;
5853 /* Can't find it, return an error */
5854 f = i40e_find_mac_filter(vsi, addr);
5856 return I40E_ERR_PARAM;
5858 vlan_num = vsi->vlan_num;
5859 filter_type = f->mac_info.filter_type;
5860 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5861 filter_type == RTE_MACVLAN_HASH_MATCH) {
5862 if (vlan_num == 0) {
5863 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
5864 return I40E_ERR_PARAM;
5866 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
5867 filter_type == RTE_MAC_HASH_MATCH)
5870 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5872 PMD_DRV_LOG(ERR, "failed to allocate memory");
5873 return I40E_ERR_NO_MEMORY;
5876 for (i = 0; i < vlan_num; i++) {
5877 mv_f[i].filter_type = filter_type;
5878 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5881 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5882 filter_type == RTE_MACVLAN_HASH_MATCH) {
5883 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
5884 if (ret != I40E_SUCCESS)
5888 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
5889 if (ret != I40E_SUCCESS)
5892 /* Remove the mac addr into mac list */
5893 TAILQ_REMOVE(&vsi->mac_list, f, next);
5903 /* Configure hash enable flags for RSS */
5905 i40e_config_hena(uint64_t flags)
5912 if (flags & ETH_RSS_FRAG_IPV4)
5913 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
5914 if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
5915 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
5916 if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
5917 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
5918 if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
5919 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
5920 if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
5921 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
5922 if (flags & ETH_RSS_FRAG_IPV6)
5923 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
5924 if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
5925 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
5926 if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
5927 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
5928 if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
5929 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
5930 if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
5931 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
5932 if (flags & ETH_RSS_L2_PAYLOAD)
5933 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
5938 /* Parse the hash enable flags */
5940 i40e_parse_hena(uint64_t flags)
5942 uint64_t rss_hf = 0;
5946 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
5947 rss_hf |= ETH_RSS_FRAG_IPV4;
5948 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
5949 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
5950 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
5951 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
5952 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
5953 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
5954 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
5955 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
5956 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
5957 rss_hf |= ETH_RSS_FRAG_IPV6;
5958 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
5959 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
5960 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
5961 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
5962 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
5963 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
5964 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
5965 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
5966 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
5967 rss_hf |= ETH_RSS_L2_PAYLOAD;
5974 i40e_pf_disable_rss(struct i40e_pf *pf)
5976 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5979 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
5980 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
5981 hena &= ~I40E_RSS_HENA_ALL;
5982 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5983 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5984 I40E_WRITE_FLUSH(hw);
5988 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
5990 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5991 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5994 if (!key || key_len == 0) {
5995 PMD_DRV_LOG(DEBUG, "No key to be configured");
5997 } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5999 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6003 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6004 struct i40e_aqc_get_set_rss_key_data *key_dw =
6005 (struct i40e_aqc_get_set_rss_key_data *)key;
6007 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6009 PMD_INIT_LOG(ERR, "Failed to configure RSS key "
6012 uint32_t *hash_key = (uint32_t *)key;
6015 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6016 i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6017 I40E_WRITE_FLUSH(hw);
6024 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6026 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6027 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6030 if (!key || !key_len)
6033 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6034 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6035 (struct i40e_aqc_get_set_rss_key_data *)key);
6037 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6041 uint32_t *key_dw = (uint32_t *)key;
6044 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6045 key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6047 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6053 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6055 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6060 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6061 rss_conf->rss_key_len);
6065 rss_hf = rss_conf->rss_hf;
6066 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6067 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6068 hena &= ~I40E_RSS_HENA_ALL;
6069 hena |= i40e_config_hena(rss_hf);
6070 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6071 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6072 I40E_WRITE_FLUSH(hw);
6078 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6079 struct rte_eth_rss_conf *rss_conf)
6081 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6082 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6083 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6086 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6087 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6088 if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
6089 if (rss_hf != 0) /* Enable RSS */
6091 return 0; /* Nothing to do */
6094 if (rss_hf == 0) /* Disable RSS */
6097 return i40e_hw_rss_hash_set(pf, rss_conf);
6101 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6102 struct rte_eth_rss_conf *rss_conf)
6104 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6105 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6108 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6109 &rss_conf->rss_key_len);
6111 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6112 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6113 rss_conf->rss_hf = i40e_parse_hena(hena);
6119 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6121 switch (filter_type) {
6122 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6123 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6125 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6126 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6128 case RTE_TUNNEL_FILTER_IMAC_TENID:
6129 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6131 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6132 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6134 case ETH_TUNNEL_FILTER_IMAC:
6135 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6137 case ETH_TUNNEL_FILTER_OIP:
6138 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6140 case ETH_TUNNEL_FILTER_IIP:
6141 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6144 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6152 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6153 struct rte_eth_tunnel_filter_conf *tunnel_filter,
6158 uint8_t i, tun_type = 0;
6159 /* internal varialbe to convert ipv6 byte order */
6160 uint32_t convert_ipv6[4];
6162 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6163 struct i40e_vsi *vsi = pf->main_vsi;
6164 struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter;
6165 struct i40e_aqc_add_remove_cloud_filters_element_data *pfilter;
6167 cld_filter = rte_zmalloc("tunnel_filter",
6168 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6171 if (NULL == cld_filter) {
6172 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6175 pfilter = cld_filter;
6177 ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6178 ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6180 pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6181 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6182 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6183 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6184 rte_memcpy(&pfilter->ipaddr.v4.data,
6185 &rte_cpu_to_le_32(ipv4_addr),
6186 sizeof(pfilter->ipaddr.v4.data));
6188 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6189 for (i = 0; i < 4; i++) {
6191 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6193 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6194 sizeof(pfilter->ipaddr.v6.data));
6197 /* check tunneled type */
6198 switch (tunnel_filter->tunnel_type) {
6199 case RTE_TUNNEL_TYPE_VXLAN:
6200 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6202 case RTE_TUNNEL_TYPE_NVGRE:
6203 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6205 case RTE_TUNNEL_TYPE_IP_IN_GRE:
6206 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6209 /* Other tunnel types is not supported. */
6210 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6211 rte_free(cld_filter);
6215 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6218 rte_free(cld_filter);
6222 pfilter->flags |= rte_cpu_to_le_16(
6223 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6224 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6225 pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6226 pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6229 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6231 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6234 rte_free(cld_filter);
6239 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6243 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6244 if (pf->vxlan_ports[i] == port)
6252 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6256 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6258 idx = i40e_get_vxlan_port_idx(pf, port);
6260 /* Check if port already exists */
6262 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6266 /* Now check if there is space to add the new port */
6267 idx = i40e_get_vxlan_port_idx(pf, 0);
6269 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6270 "not adding port %d", port);
6274 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6277 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6281 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6284 /* New port: add it and mark its index in the bitmap */
6285 pf->vxlan_ports[idx] = port;
6286 pf->vxlan_bitmap |= (1 << idx);
6288 if (!(pf->flags & I40E_FLAG_VXLAN))
6289 pf->flags |= I40E_FLAG_VXLAN;
6295 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6298 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6300 if (!(pf->flags & I40E_FLAG_VXLAN)) {
6301 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6305 idx = i40e_get_vxlan_port_idx(pf, port);
6308 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6312 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6313 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6317 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6320 pf->vxlan_ports[idx] = 0;
6321 pf->vxlan_bitmap &= ~(1 << idx);
6323 if (!pf->vxlan_bitmap)
6324 pf->flags &= ~I40E_FLAG_VXLAN;
6329 /* Add UDP tunneling port */
6331 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6332 struct rte_eth_udp_tunnel *udp_tunnel)
6335 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6337 if (udp_tunnel == NULL)
6340 switch (udp_tunnel->prot_type) {
6341 case RTE_TUNNEL_TYPE_VXLAN:
6342 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6345 case RTE_TUNNEL_TYPE_GENEVE:
6346 case RTE_TUNNEL_TYPE_TEREDO:
6347 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6352 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6360 /* Remove UDP tunneling port */
6362 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6363 struct rte_eth_udp_tunnel *udp_tunnel)
6366 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6368 if (udp_tunnel == NULL)
6371 switch (udp_tunnel->prot_type) {
6372 case RTE_TUNNEL_TYPE_VXLAN:
6373 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6375 case RTE_TUNNEL_TYPE_GENEVE:
6376 case RTE_TUNNEL_TYPE_TEREDO:
6377 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6381 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6389 /* Calculate the maximum number of contiguous PF queues that are configured */
6391 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6393 struct rte_eth_dev_data *data = pf->dev_data;
6395 struct i40e_rx_queue *rxq;
6398 for (i = 0; i < pf->lan_nb_qps; i++) {
6399 rxq = data->rx_queues[i];
6400 if (rxq && rxq->q_set)
6411 i40e_pf_config_rss(struct i40e_pf *pf)
6413 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6414 struct rte_eth_rss_conf rss_conf;
6415 uint32_t i, lut = 0;
6419 * If both VMDQ and RSS enabled, not all of PF queues are configured.
6420 * It's necessary to calulate the actual PF queues that are configured.
6422 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6423 num = i40e_pf_calc_configured_queues_num(pf);
6425 num = pf->dev_data->nb_rx_queues;
6427 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6428 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6432 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6436 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6439 lut = (lut << 8) | (j & ((0x1 <<
6440 hw->func_caps.rss_table_entry_width) - 1));
6442 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6445 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6446 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6447 i40e_pf_disable_rss(pf);
6450 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6451 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6452 /* Random default keys */
6453 static uint32_t rss_key_default[] = {0x6b793944,
6454 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6455 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6456 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6458 rss_conf.rss_key = (uint8_t *)rss_key_default;
6459 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6463 return i40e_hw_rss_hash_set(pf, &rss_conf);
6467 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6468 struct rte_eth_tunnel_filter_conf *filter)
6470 if (pf == NULL || filter == NULL) {
6471 PMD_DRV_LOG(ERR, "Invalid parameter");
6475 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6476 PMD_DRV_LOG(ERR, "Invalid queue ID");
6480 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6481 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6485 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6486 (is_zero_ether_addr(&filter->outer_mac))) {
6487 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6491 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6492 (is_zero_ether_addr(&filter->inner_mac))) {
6493 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6500 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6501 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
6503 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6508 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6509 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6512 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6513 } else if (len == 4) {
6514 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6516 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6521 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6528 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6529 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6535 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6542 switch (cfg->cfg_type) {
6543 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6544 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6547 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6555 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6556 enum rte_filter_op filter_op,
6559 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6560 int ret = I40E_ERR_PARAM;
6562 switch (filter_op) {
6563 case RTE_ETH_FILTER_SET:
6564 ret = i40e_dev_global_config_set(hw,
6565 (struct rte_eth_global_cfg *)arg);
6568 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6576 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6577 enum rte_filter_op filter_op,
6580 struct rte_eth_tunnel_filter_conf *filter;
6581 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6582 int ret = I40E_SUCCESS;
6584 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6586 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6587 return I40E_ERR_PARAM;
6589 switch (filter_op) {
6590 case RTE_ETH_FILTER_NOP:
6591 if (!(pf->flags & I40E_FLAG_VXLAN))
6592 ret = I40E_NOT_SUPPORTED;
6594 case RTE_ETH_FILTER_ADD:
6595 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6597 case RTE_ETH_FILTER_DELETE:
6598 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6601 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6602 ret = I40E_ERR_PARAM;
6610 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6613 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6616 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6617 ret = i40e_pf_config_rss(pf);
6619 i40e_pf_disable_rss(pf);
6624 /* Get the symmetric hash enable configurations per port */
6626 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6628 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6630 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6633 /* Set the symmetric hash enable configurations per port */
6635 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6637 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6640 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6641 PMD_DRV_LOG(INFO, "Symmetric hash has already "
6645 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6647 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6648 PMD_DRV_LOG(INFO, "Symmetric hash has already "
6652 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6654 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
6655 I40E_WRITE_FLUSH(hw);
6659 * Get global configurations of hash function type and symmetric hash enable
6660 * per flow type (pctype). Note that global configuration means it affects all
6661 * the ports on the same NIC.
6664 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6665 struct rte_eth_hash_global_conf *g_cfg)
6667 uint32_t reg, mask = I40E_FLOW_TYPES;
6669 enum i40e_filter_pctype pctype;
6671 memset(g_cfg, 0, sizeof(*g_cfg));
6672 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6673 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6674 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6676 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6677 PMD_DRV_LOG(DEBUG, "Hash function is %s",
6678 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6680 for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6681 if (!(mask & (1UL << i)))
6683 mask &= ~(1UL << i);
6684 /* Bit set indicats the coresponding flow type is supported */
6685 g_cfg->valid_bit_mask[0] |= (1UL << i);
6686 pctype = i40e_flowtype_to_pctype(i);
6687 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
6688 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6689 g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6696 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6699 uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6701 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
6702 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
6703 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
6704 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
6710 * As i40e supports less than 32 flow types, only first 32 bits need to
6713 mask0 = g_cfg->valid_bit_mask[0];
6714 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
6716 /* Check if any unsupported flow type configured */
6717 if ((mask0 | i40e_mask) ^ i40e_mask)
6720 if (g_cfg->valid_bit_mask[i])
6728 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
6734 * Set global configurations of hash function type and symmetric hash enable
6735 * per flow type (pctype). Note any modifying global configuration will affect
6736 * all the ports on the same NIC.
6739 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
6740 struct rte_eth_hash_global_conf *g_cfg)
6745 uint32_t mask0 = g_cfg->valid_bit_mask[0];
6746 enum i40e_filter_pctype pctype;
6748 /* Check the input parameters */
6749 ret = i40e_hash_global_config_check(g_cfg);
6753 for (i = 0; mask0 && i < UINT32_BIT; i++) {
6754 if (!(mask0 & (1UL << i)))
6756 mask0 &= ~(1UL << i);
6757 pctype = i40e_flowtype_to_pctype(i);
6758 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
6759 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
6760 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
6763 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6764 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
6766 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
6767 PMD_DRV_LOG(DEBUG, "Hash function already set to "
6771 reg |= I40E_GLQF_CTL_HTOEP_MASK;
6772 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
6774 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
6775 PMD_DRV_LOG(DEBUG, "Hash function already set to "
6779 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
6781 /* Use the default, and keep it as it is */
6784 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
6787 I40E_WRITE_FLUSH(hw);
6793 * Valid input sets for hash and flow director filters per PCTYPE
6796 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
6797 enum rte_filter_type filter)
6801 static const uint64_t valid_hash_inset_table[] = {
6802 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6803 I40E_INSET_DMAC | I40E_INSET_SMAC |
6804 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6805 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
6806 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
6807 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6808 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6809 I40E_INSET_FLEX_PAYLOAD,
6810 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6811 I40E_INSET_DMAC | I40E_INSET_SMAC |
6812 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6813 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6814 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6815 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6816 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6817 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6818 I40E_INSET_FLEX_PAYLOAD,
6819 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6820 I40E_INSET_DMAC | I40E_INSET_SMAC |
6821 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6822 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6823 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6824 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6825 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6826 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6827 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
6828 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6829 I40E_INSET_DMAC | I40E_INSET_SMAC |
6830 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6831 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6832 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6833 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6834 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6835 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6836 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6837 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6838 I40E_INSET_DMAC | I40E_INSET_SMAC |
6839 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6840 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6841 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6842 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6843 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6844 I40E_INSET_FLEX_PAYLOAD,
6845 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6846 I40E_INSET_DMAC | I40E_INSET_SMAC |
6847 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6848 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6849 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6850 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
6851 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
6852 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
6853 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6854 I40E_INSET_DMAC | I40E_INSET_SMAC |
6855 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6856 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6857 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6858 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6859 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6860 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
6861 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6862 I40E_INSET_DMAC | I40E_INSET_SMAC |
6863 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6864 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6865 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6866 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6867 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6868 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
6869 I40E_INSET_FLEX_PAYLOAD,
6870 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6871 I40E_INSET_DMAC | I40E_INSET_SMAC |
6872 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6873 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6874 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6875 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6876 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6877 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
6878 I40E_INSET_FLEX_PAYLOAD,
6879 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6880 I40E_INSET_DMAC | I40E_INSET_SMAC |
6881 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6882 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6883 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6884 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6885 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
6886 I40E_INSET_FLEX_PAYLOAD,
6887 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6888 I40E_INSET_DMAC | I40E_INSET_SMAC |
6889 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6890 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
6891 I40E_INSET_FLEX_PAYLOAD,
6895 * Flow director supports only fields defined in
6896 * union rte_eth_fdir_flow.
6898 static const uint64_t valid_fdir_inset_table[] = {
6899 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6900 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6901 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6902 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
6903 I40E_INSET_IPV4_TTL,
6904 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6905 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6906 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6907 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
6908 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6909 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6910 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6911 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6912 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
6913 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6914 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6915 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6916 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6917 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
6918 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6920 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6921 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6922 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6923 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
6924 I40E_INSET_IPV4_TTL,
6925 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6926 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6927 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6928 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
6929 I40E_INSET_IPV6_HOP_LIMIT,
6930 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6931 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6932 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6933 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
6934 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6935 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6936 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6937 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6938 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
6939 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6940 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6941 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6942 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6943 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
6944 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6946 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6947 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6948 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6949 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
6950 I40E_INSET_IPV6_HOP_LIMIT,
6951 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6952 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6953 I40E_INSET_LAST_ETHER_TYPE,
6956 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6958 if (filter == RTE_ETH_FILTER_HASH)
6959 valid = valid_hash_inset_table[pctype];
6961 valid = valid_fdir_inset_table[pctype];
6967 * Validate if the input set is allowed for a specific PCTYPE
6970 i40e_validate_input_set(enum i40e_filter_pctype pctype,
6971 enum rte_filter_type filter, uint64_t inset)
6975 valid = i40e_get_valid_input_set(pctype, filter);
6976 if (inset & (~valid))
6982 /* default input set fields combination per pctype */
6984 i40e_get_default_input_set(uint16_t pctype)
6986 static const uint64_t default_inset_table[] = {
6987 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6988 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6989 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6990 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6991 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6992 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6993 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6994 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6995 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6996 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6997 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6999 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7000 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7001 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7002 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7003 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7004 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7005 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7006 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7007 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7008 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7009 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7010 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7011 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7013 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7014 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7015 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7016 I40E_INSET_LAST_ETHER_TYPE,
7019 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7022 return default_inset_table[pctype];
7026 * Parse the input set from index to logical bit masks
7029 i40e_parse_input_set(uint64_t *inset,
7030 enum i40e_filter_pctype pctype,
7031 enum rte_eth_input_set_field *field,
7037 static const struct {
7038 enum rte_eth_input_set_field field;
7040 } inset_convert_table[] = {
7041 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7042 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7043 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7044 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7045 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7046 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7047 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7048 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7049 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7050 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7051 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7052 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7053 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7054 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7055 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7056 I40E_INSET_IPV6_NEXT_HDR},
7057 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7058 I40E_INSET_IPV6_HOP_LIMIT},
7059 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7060 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7061 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7062 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7063 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7064 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7065 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7066 I40E_INSET_SCTP_VT},
7067 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7068 I40E_INSET_TUNNEL_DMAC},
7069 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7070 I40E_INSET_VLAN_TUNNEL},
7071 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7072 I40E_INSET_TUNNEL_ID},
7073 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7074 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7075 I40E_INSET_FLEX_PAYLOAD_W1},
7076 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7077 I40E_INSET_FLEX_PAYLOAD_W2},
7078 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7079 I40E_INSET_FLEX_PAYLOAD_W3},
7080 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7081 I40E_INSET_FLEX_PAYLOAD_W4},
7082 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7083 I40E_INSET_FLEX_PAYLOAD_W5},
7084 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7085 I40E_INSET_FLEX_PAYLOAD_W6},
7086 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7087 I40E_INSET_FLEX_PAYLOAD_W7},
7088 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7089 I40E_INSET_FLEX_PAYLOAD_W8},
7092 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7095 /* Only one item allowed for default or all */
7097 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7098 *inset = i40e_get_default_input_set(pctype);
7100 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7101 *inset = I40E_INSET_NONE;
7106 for (i = 0, *inset = 0; i < size; i++) {
7107 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7108 if (field[i] == inset_convert_table[j].field) {
7109 *inset |= inset_convert_table[j].inset;
7114 /* It contains unsupported input set, return immediately */
7115 if (j == RTE_DIM(inset_convert_table))
7123 * Translate the input set from bit masks to register aware bit masks
7127 i40e_translate_input_set_reg(uint64_t input)
7132 static const struct {
7136 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7137 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7138 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7139 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7140 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7141 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7142 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7143 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7144 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7145 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7146 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7147 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7148 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7149 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7150 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7151 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7152 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7153 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7154 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7155 {I40E_INSET_TUNNEL_DMAC,
7156 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7157 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7158 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7159 {I40E_INSET_TUNNEL_SRC_PORT,
7160 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7161 {I40E_INSET_TUNNEL_DST_PORT,
7162 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7163 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7164 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7165 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7166 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7167 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7168 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7169 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7170 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7171 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7177 /* Translate input set to register aware inset */
7178 for (i = 0; i < RTE_DIM(inset_map); i++) {
7179 if (input & inset_map[i].inset)
7180 val |= inset_map[i].inset_reg;
7187 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7190 uint64_t inset_need_mask = inset;
7192 static const struct {
7195 } inset_mask_map[] = {
7196 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7197 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7198 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7199 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7200 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7201 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7202 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7203 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7206 if (!inset || !mask || !nb_elem)
7209 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7210 /* Clear the inset bit, if no MASK is required,
7211 * for example proto + ttl
7213 if ((inset & inset_mask_map[i].inset) ==
7214 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
7215 inset_need_mask &= ~inset_mask_map[i].inset;
7216 if (!inset_need_mask)
7219 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7220 if ((inset_need_mask & inset_mask_map[i].inset) ==
7221 inset_mask_map[i].inset) {
7222 if (idx >= nb_elem) {
7223 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
7226 mask[idx] = inset_mask_map[i].mask;
7235 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7237 uint32_t reg = i40e_read_rx_ctl(hw, addr);
7239 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7241 i40e_write_rx_ctl(hw, addr, val);
7242 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7243 (uint32_t)i40e_read_rx_ctl(hw, addr));
7247 i40e_filter_input_set_init(struct i40e_pf *pf)
7249 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7250 enum i40e_filter_pctype pctype;
7251 uint64_t input_set, inset_reg;
7252 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7255 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
7256 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
7257 if (!I40E_VALID_PCTYPE(pctype))
7259 input_set = i40e_get_default_input_set(pctype);
7261 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7262 I40E_INSET_MASK_NUM_REG);
7265 inset_reg = i40e_translate_input_set_reg(input_set);
7267 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7268 (uint32_t)(inset_reg & UINT32_MAX));
7269 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7270 (uint32_t)((inset_reg >>
7271 I40E_32_BIT_WIDTH) & UINT32_MAX));
7272 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7273 (uint32_t)(inset_reg & UINT32_MAX));
7274 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7275 (uint32_t)((inset_reg >>
7276 I40E_32_BIT_WIDTH) & UINT32_MAX));
7278 for (i = 0; i < num; i++) {
7279 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7281 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7284 /*clear unused mask registers of the pctype */
7285 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
7286 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7288 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7291 I40E_WRITE_FLUSH(hw);
7293 /* store the default input set */
7294 pf->hash_input_set[pctype] = input_set;
7295 pf->fdir.input_set[pctype] = input_set;
7300 i40e_hash_filter_inset_select(struct i40e_hw *hw,
7301 struct rte_eth_input_set_conf *conf)
7303 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
7304 enum i40e_filter_pctype pctype;
7305 uint64_t input_set, inset_reg = 0;
7306 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7310 PMD_DRV_LOG(ERR, "Invalid pointer");
7313 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7314 conf->op != RTE_ETH_INPUT_SET_ADD) {
7315 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7319 pctype = i40e_flowtype_to_pctype(conf->flow_type);
7320 if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
7321 PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
7326 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7329 PMD_DRV_LOG(ERR, "Failed to parse input set");
7332 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
7334 PMD_DRV_LOG(ERR, "Invalid input set");
7337 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
7338 /* get inset value in register */
7339 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
7340 inset_reg <<= I40E_32_BIT_WIDTH;
7341 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
7342 input_set |= pf->hash_input_set[pctype];
7344 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7345 I40E_INSET_MASK_NUM_REG);
7349 inset_reg |= i40e_translate_input_set_reg(input_set);
7351 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7352 (uint32_t)(inset_reg & UINT32_MAX));
7353 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7354 (uint32_t)((inset_reg >>
7355 I40E_32_BIT_WIDTH) & UINT32_MAX));
7357 for (i = 0; i < num; i++)
7358 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7360 /*clear unused mask registers of the pctype */
7361 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7362 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7364 I40E_WRITE_FLUSH(hw);
7366 pf->hash_input_set[pctype] = input_set;
7371 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
7372 struct rte_eth_input_set_conf *conf)
7374 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7375 enum i40e_filter_pctype pctype;
7376 uint64_t input_set, inset_reg = 0;
7377 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7381 PMD_DRV_LOG(ERR, "Invalid pointer");
7384 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7385 conf->op != RTE_ETH_INPUT_SET_ADD) {
7386 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7390 pctype = i40e_flowtype_to_pctype(conf->flow_type);
7391 if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
7392 PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
7396 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7399 PMD_DRV_LOG(ERR, "Failed to parse input set");
7402 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
7404 PMD_DRV_LOG(ERR, "Invalid input set");
7408 /* get inset value in register */
7409 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
7410 inset_reg <<= I40E_32_BIT_WIDTH;
7411 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
7413 /* Can not change the inset reg for flex payload for fdir,
7414 * it is done by writing I40E_PRTQF_FD_FLXINSET
7415 * in i40e_set_flex_mask_on_pctype.
7417 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
7418 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
7420 input_set |= pf->fdir.input_set[pctype];
7421 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7422 I40E_INSET_MASK_NUM_REG);
7426 inset_reg |= i40e_translate_input_set_reg(input_set);
7428 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7429 (uint32_t)(inset_reg & UINT32_MAX));
7430 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7431 (uint32_t)((inset_reg >>
7432 I40E_32_BIT_WIDTH) & UINT32_MAX));
7434 for (i = 0; i < num; i++)
7435 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7437 /*clear unused mask registers of the pctype */
7438 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7439 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7441 I40E_WRITE_FLUSH(hw);
7443 pf->fdir.input_set[pctype] = input_set;
7448 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7453 PMD_DRV_LOG(ERR, "Invalid pointer");
7457 switch (info->info_type) {
7458 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7459 i40e_get_symmetric_hash_enable_per_port(hw,
7460 &(info->info.enable));
7462 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7463 ret = i40e_get_hash_filter_global_config(hw,
7464 &(info->info.global_conf));
7467 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7477 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7482 PMD_DRV_LOG(ERR, "Invalid pointer");
7486 switch (info->info_type) {
7487 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7488 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7490 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7491 ret = i40e_set_hash_filter_global_config(hw,
7492 &(info->info.global_conf));
7494 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7495 ret = i40e_hash_filter_inset_select(hw,
7496 &(info->info.input_set_conf));
7500 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7509 /* Operations for hash function */
7511 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7512 enum rte_filter_op filter_op,
7515 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7518 switch (filter_op) {
7519 case RTE_ETH_FILTER_NOP:
7521 case RTE_ETH_FILTER_GET:
7522 ret = i40e_hash_filter_get(hw,
7523 (struct rte_eth_hash_filter_info *)arg);
7525 case RTE_ETH_FILTER_SET:
7526 ret = i40e_hash_filter_set(hw,
7527 (struct rte_eth_hash_filter_info *)arg);
7530 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
7540 * Configure ethertype filter, which can director packet by filtering
7541 * with mac address and ether_type or only ether_type
7544 i40e_ethertype_filter_set(struct i40e_pf *pf,
7545 struct rte_eth_ethertype_filter *filter,
7548 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7549 struct i40e_control_filter_stats stats;
7553 if (filter->queue >= pf->dev_data->nb_rx_queues) {
7554 PMD_DRV_LOG(ERR, "Invalid queue ID");
7557 if (filter->ether_type == ETHER_TYPE_IPv4 ||
7558 filter->ether_type == ETHER_TYPE_IPv6) {
7559 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
7560 " control packet filter.", filter->ether_type);
7563 if (filter->ether_type == ETHER_TYPE_VLAN)
7564 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
7567 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
7568 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
7569 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
7570 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
7571 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
7573 memset(&stats, 0, sizeof(stats));
7574 ret = i40e_aq_add_rem_control_packet_filter(hw,
7575 filter->mac_addr.addr_bytes,
7576 filter->ether_type, flags,
7578 filter->queue, add, &stats, NULL);
7580 PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
7581 " mac_etype_used = %u, etype_used = %u,"
7582 " mac_etype_free = %u, etype_free = %u\n",
7583 ret, stats.mac_etype_used, stats.etype_used,
7584 stats.mac_etype_free, stats.etype_free);
7591 * Handle operations for ethertype filter.
7594 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
7595 enum rte_filter_op filter_op,
7598 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7601 if (filter_op == RTE_ETH_FILTER_NOP)
7605 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
7610 switch (filter_op) {
7611 case RTE_ETH_FILTER_ADD:
7612 ret = i40e_ethertype_filter_set(pf,
7613 (struct rte_eth_ethertype_filter *)arg,
7616 case RTE_ETH_FILTER_DELETE:
7617 ret = i40e_ethertype_filter_set(pf,
7618 (struct rte_eth_ethertype_filter *)arg,
7622 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
7630 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
7631 enum rte_filter_type filter_type,
7632 enum rte_filter_op filter_op,
7640 switch (filter_type) {
7641 case RTE_ETH_FILTER_NONE:
7642 /* For global configuration */
7643 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
7645 case RTE_ETH_FILTER_HASH:
7646 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
7648 case RTE_ETH_FILTER_MACVLAN:
7649 ret = i40e_mac_filter_handle(dev, filter_op, arg);
7651 case RTE_ETH_FILTER_ETHERTYPE:
7652 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
7654 case RTE_ETH_FILTER_TUNNEL:
7655 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
7657 case RTE_ETH_FILTER_FDIR:
7658 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
7661 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7671 * Check and enable Extended Tag.
7672 * Enabling Extended Tag is important for 40G performance.
7675 i40e_enable_extended_tag(struct rte_eth_dev *dev)
7680 ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7683 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7687 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
7688 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
7693 ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7696 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7700 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
7701 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
7704 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
7705 ret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf),
7708 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
7715 * As some registers wouldn't be reset unless a global hardware reset,
7716 * hardware initialization is needed to put those registers into an
7717 * expected initial state.
7720 i40e_hw_init(struct rte_eth_dev *dev)
7722 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7724 i40e_enable_extended_tag(dev);
7726 /* clear the PF Queue Filter control register */
7727 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
7729 /* Disable symmetric hash per port */
7730 i40e_set_symmetric_hash_enable_per_port(hw, 0);
7733 enum i40e_filter_pctype
7734 i40e_flowtype_to_pctype(uint16_t flow_type)
7736 static const enum i40e_filter_pctype pctype_table[] = {
7737 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
7738 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
7739 I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
7740 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
7741 I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
7742 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
7743 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
7744 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
7745 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
7746 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
7747 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
7748 I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
7749 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
7750 I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
7751 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
7752 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
7753 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
7754 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
7755 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
7758 return pctype_table[flow_type];
7762 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
7764 static const uint16_t flowtype_table[] = {
7765 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
7766 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7767 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
7768 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7769 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
7770 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7771 RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
7772 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7773 RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
7774 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
7775 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7776 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
7777 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7778 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
7779 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7780 RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
7781 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7782 RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
7783 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
7786 return flowtype_table[pctype];
7790 * On X710, performance number is far from the expectation on recent firmware
7791 * versions; on XL710, performance number is also far from the expectation on
7792 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
7793 * mode is enabled and port MAC address is equal to the packet destination MAC
7794 * address. The fix for this issue may not be integrated in the following
7795 * firmware version. So the workaround in software driver is needed. It needs
7796 * to modify the initial values of 3 internal only registers for both X710 and
7797 * XL710. Note that the values for X710 or XL710 could be different, and the
7798 * workaround can be removed when it is fixed in firmware in the future.
7801 /* For both X710 and XL710 */
7802 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
7803 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
7805 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
7806 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
7809 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
7811 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
7812 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
7815 i40e_configure_registers(struct i40e_hw *hw)
7821 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
7822 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
7823 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
7829 for (i = 0; i < RTE_DIM(reg_table); i++) {
7830 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
7831 if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
7833 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
7836 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
7839 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
7842 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
7846 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
7847 reg_table[i].addr, reg);
7848 if (reg == reg_table[i].val)
7851 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
7852 reg_table[i].val, NULL);
7854 PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
7855 "address of 0x%"PRIx32, reg_table[i].val,
7859 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
7860 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
7864 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
7865 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
7866 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
7867 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
7869 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
7874 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
7875 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
7879 /* Configure for double VLAN RX stripping */
7880 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
7881 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
7882 reg |= I40E_VSI_TSR_QINQ_CONFIG;
7883 ret = i40e_aq_debug_write_register(hw,
7884 I40E_VSI_TSR(vsi->vsi_id),
7887 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
7889 return I40E_ERR_CONFIG;
7893 /* Configure for double VLAN TX insertion */
7894 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
7895 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
7896 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
7897 ret = i40e_aq_debug_write_register(hw,
7898 I40E_VSI_L2TAGSTXVALID(
7899 vsi->vsi_id), reg, NULL);
7901 PMD_DRV_LOG(ERR, "Failed to update "
7902 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
7903 return I40E_ERR_CONFIG;
7911 * i40e_aq_add_mirror_rule
7912 * @hw: pointer to the hardware structure
7913 * @seid: VEB seid to add mirror rule to
7914 * @dst_id: destination vsi seid
7915 * @entries: Buffer which contains the entities to be mirrored
7916 * @count: number of entities contained in the buffer
7917 * @rule_id:the rule_id of the rule to be added
7919 * Add a mirror rule for a given veb.
7922 static enum i40e_status_code
7923 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
7924 uint16_t seid, uint16_t dst_id,
7925 uint16_t rule_type, uint16_t *entries,
7926 uint16_t count, uint16_t *rule_id)
7928 struct i40e_aq_desc desc;
7929 struct i40e_aqc_add_delete_mirror_rule cmd;
7930 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
7931 (struct i40e_aqc_add_delete_mirror_rule_completion *)
7934 enum i40e_status_code status;
7936 i40e_fill_default_direct_cmd_desc(&desc,
7937 i40e_aqc_opc_add_mirror_rule);
7938 memset(&cmd, 0, sizeof(cmd));
7940 buff_len = sizeof(uint16_t) * count;
7941 desc.datalen = rte_cpu_to_le_16(buff_len);
7943 desc.flags |= rte_cpu_to_le_16(
7944 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
7945 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7946 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7947 cmd.num_entries = rte_cpu_to_le_16(count);
7948 cmd.seid = rte_cpu_to_le_16(seid);
7949 cmd.destination = rte_cpu_to_le_16(dst_id);
7951 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7952 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
7953 PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
7955 " mirror_rules_used = %u, mirror_rules_free = %u,",
7956 hw->aq.asq_last_status, resp->rule_id,
7957 resp->mirror_rules_used, resp->mirror_rules_free);
7958 *rule_id = rte_le_to_cpu_16(resp->rule_id);
7964 * i40e_aq_del_mirror_rule
7965 * @hw: pointer to the hardware structure
7966 * @seid: VEB seid to add mirror rule to
7967 * @entries: Buffer which contains the entities to be mirrored
7968 * @count: number of entities contained in the buffer
7969 * @rule_id:the rule_id of the rule to be delete
7971 * Delete a mirror rule for a given veb.
7974 static enum i40e_status_code
7975 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
7976 uint16_t seid, uint16_t rule_type, uint16_t *entries,
7977 uint16_t count, uint16_t rule_id)
7979 struct i40e_aq_desc desc;
7980 struct i40e_aqc_add_delete_mirror_rule cmd;
7981 uint16_t buff_len = 0;
7982 enum i40e_status_code status;
7985 i40e_fill_default_direct_cmd_desc(&desc,
7986 i40e_aqc_opc_delete_mirror_rule);
7987 memset(&cmd, 0, sizeof(cmd));
7988 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
7989 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
7991 cmd.num_entries = count;
7992 buff_len = sizeof(uint16_t) * count;
7993 desc.datalen = rte_cpu_to_le_16(buff_len);
7994 buff = (void *)entries;
7996 /* rule id is filled in destination field for deleting mirror rule */
7997 cmd.destination = rte_cpu_to_le_16(rule_id);
7999 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8000 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8001 cmd.seid = rte_cpu_to_le_16(seid);
8003 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8004 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
8010 * i40e_mirror_rule_set
8011 * @dev: pointer to the hardware structure
8012 * @mirror_conf: mirror rule info
8013 * @sw_id: mirror rule's sw_id
8014 * @on: enable/disable
8016 * set a mirror rule.
8020 i40e_mirror_rule_set(struct rte_eth_dev *dev,
8021 struct rte_eth_mirror_conf *mirror_conf,
8022 uint8_t sw_id, uint8_t on)
8024 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8025 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8026 struct i40e_mirror_rule *it, *mirr_rule = NULL;
8027 struct i40e_mirror_rule *parent = NULL;
8028 uint16_t seid, dst_seid, rule_id;
8032 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
8034 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
8035 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
8036 " without veb or vfs.");
8039 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
8040 PMD_DRV_LOG(ERR, "mirror table is full.");
8043 if (mirror_conf->dst_pool > pf->vf_num) {
8044 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
8045 mirror_conf->dst_pool);
8049 seid = pf->main_vsi->veb->seid;
8051 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8052 if (sw_id <= it->index) {
8058 if (mirr_rule && sw_id == mirr_rule->index) {
8060 PMD_DRV_LOG(ERR, "mirror rule exists.");
8063 ret = i40e_aq_del_mirror_rule(hw, seid,
8064 mirr_rule->rule_type,
8066 mirr_rule->num_entries, mirr_rule->id);
8068 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8069 " ret = %d, aq_err = %d.",
8070 ret, hw->aq.asq_last_status);
8073 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8074 rte_free(mirr_rule);
8075 pf->nb_mirror_rule--;
8079 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8083 mirr_rule = rte_zmalloc("i40e_mirror_rule",
8084 sizeof(struct i40e_mirror_rule) , 0);
8086 PMD_DRV_LOG(ERR, "failed to allocate memory");
8087 return I40E_ERR_NO_MEMORY;
8089 switch (mirror_conf->rule_type) {
8090 case ETH_MIRROR_VLAN:
8091 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
8092 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
8093 mirr_rule->entries[j] =
8094 mirror_conf->vlan.vlan_id[i];
8099 PMD_DRV_LOG(ERR, "vlan is not specified.");
8100 rte_free(mirr_rule);
8103 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
8105 case ETH_MIRROR_VIRTUAL_POOL_UP:
8106 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
8107 /* check if the specified pool bit is out of range */
8108 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
8109 PMD_DRV_LOG(ERR, "pool mask is out of range.");
8110 rte_free(mirr_rule);
8113 for (i = 0, j = 0; i < pf->vf_num; i++) {
8114 if (mirror_conf->pool_mask & (1ULL << i)) {
8115 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
8119 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
8120 /* add pf vsi to entries */
8121 mirr_rule->entries[j] = pf->main_vsi_seid;
8125 PMD_DRV_LOG(ERR, "pool is not specified.");
8126 rte_free(mirr_rule);
8129 /* egress and ingress in aq commands means from switch but not port */
8130 mirr_rule->rule_type =
8131 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
8132 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
8133 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
8135 case ETH_MIRROR_UPLINK_PORT:
8136 /* egress and ingress in aq commands means from switch but not port*/
8137 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
8139 case ETH_MIRROR_DOWNLINK_PORT:
8140 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
8143 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
8144 mirror_conf->rule_type);
8145 rte_free(mirr_rule);
8149 /* If the dst_pool is equal to vf_num, consider it as PF */
8150 if (mirror_conf->dst_pool == pf->vf_num)
8151 dst_seid = pf->main_vsi_seid;
8153 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
8155 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
8156 mirr_rule->rule_type, mirr_rule->entries,
8159 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
8160 " ret = %d, aq_err = %d.",
8161 ret, hw->aq.asq_last_status);
8162 rte_free(mirr_rule);
8166 mirr_rule->index = sw_id;
8167 mirr_rule->num_entries = j;
8168 mirr_rule->id = rule_id;
8169 mirr_rule->dst_vsi_seid = dst_seid;
8172 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
8174 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
8176 pf->nb_mirror_rule++;
8181 * i40e_mirror_rule_reset
8182 * @dev: pointer to the device
8183 * @sw_id: mirror rule's sw_id
8185 * reset a mirror rule.
8189 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
8191 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8192 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8193 struct i40e_mirror_rule *it, *mirr_rule = NULL;
8197 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
8199 seid = pf->main_vsi->veb->seid;
8201 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8202 if (sw_id == it->index) {
8208 ret = i40e_aq_del_mirror_rule(hw, seid,
8209 mirr_rule->rule_type,
8211 mirr_rule->num_entries, mirr_rule->id);
8213 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8214 " status = %d, aq_err = %d.",
8215 ret, hw->aq.asq_last_status);
8218 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8219 rte_free(mirr_rule);
8220 pf->nb_mirror_rule--;
8222 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8229 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
8231 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8232 uint64_t systim_cycles;
8234 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
8235 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
8238 return systim_cycles;
8242 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
8244 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8247 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
8248 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
8255 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
8257 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8260 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
8261 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
8268 i40e_start_timecounters(struct rte_eth_dev *dev)
8270 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8271 struct i40e_adapter *adapter =
8272 (struct i40e_adapter *)dev->data->dev_private;
8273 struct rte_eth_link link;
8274 uint32_t tsync_inc_l;
8275 uint32_t tsync_inc_h;
8277 /* Get current link speed. */
8278 memset(&link, 0, sizeof(link));
8279 i40e_dev_link_update(dev, 1);
8280 rte_i40e_dev_atomic_read_link_status(dev, &link);
8282 switch (link.link_speed) {
8283 case ETH_SPEED_NUM_40G:
8284 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
8285 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
8287 case ETH_SPEED_NUM_10G:
8288 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
8289 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
8291 case ETH_SPEED_NUM_1G:
8292 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
8293 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
8300 /* Set the timesync increment value. */
8301 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
8302 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
8304 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
8305 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8306 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8308 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8309 adapter->systime_tc.cc_shift = 0;
8310 adapter->systime_tc.nsec_mask = 0;
8312 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8313 adapter->rx_tstamp_tc.cc_shift = 0;
8314 adapter->rx_tstamp_tc.nsec_mask = 0;
8316 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8317 adapter->tx_tstamp_tc.cc_shift = 0;
8318 adapter->tx_tstamp_tc.nsec_mask = 0;
8322 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
8324 struct i40e_adapter *adapter =
8325 (struct i40e_adapter *)dev->data->dev_private;
8327 adapter->systime_tc.nsec += delta;
8328 adapter->rx_tstamp_tc.nsec += delta;
8329 adapter->tx_tstamp_tc.nsec += delta;
8335 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
8338 struct i40e_adapter *adapter =
8339 (struct i40e_adapter *)dev->data->dev_private;
8341 ns = rte_timespec_to_ns(ts);
8343 /* Set the timecounters to a new value. */
8344 adapter->systime_tc.nsec = ns;
8345 adapter->rx_tstamp_tc.nsec = ns;
8346 adapter->tx_tstamp_tc.nsec = ns;
8352 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
8354 uint64_t ns, systime_cycles;
8355 struct i40e_adapter *adapter =
8356 (struct i40e_adapter *)dev->data->dev_private;
8358 systime_cycles = i40e_read_systime_cyclecounter(dev);
8359 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
8360 *ts = rte_ns_to_timespec(ns);
8366 i40e_timesync_enable(struct rte_eth_dev *dev)
8368 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8369 uint32_t tsync_ctl_l;
8370 uint32_t tsync_ctl_h;
8372 /* Stop the timesync system time. */
8373 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8374 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8375 /* Reset the timesync system time value. */
8376 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
8377 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
8379 i40e_start_timecounters(dev);
8381 /* Clear timesync registers. */
8382 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8383 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
8384 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
8385 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
8386 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
8387 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
8389 /* Enable timestamping of PTP packets. */
8390 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8391 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
8393 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8394 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
8395 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
8397 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8398 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8404 i40e_timesync_disable(struct rte_eth_dev *dev)
8406 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8407 uint32_t tsync_ctl_l;
8408 uint32_t tsync_ctl_h;
8410 /* Disable timestamping of transmitted PTP packets. */
8411 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8412 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
8414 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8415 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
8417 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8418 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8420 /* Reset the timesync increment value. */
8421 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8422 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8428 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
8429 struct timespec *timestamp, uint32_t flags)
8431 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8432 struct i40e_adapter *adapter =
8433 (struct i40e_adapter *)dev->data->dev_private;
8435 uint32_t sync_status;
8436 uint32_t index = flags & 0x03;
8437 uint64_t rx_tstamp_cycles;
8440 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
8441 if ((sync_status & (1 << index)) == 0)
8444 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
8445 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
8446 *timestamp = rte_ns_to_timespec(ns);
8452 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
8453 struct timespec *timestamp)
8455 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8456 struct i40e_adapter *adapter =
8457 (struct i40e_adapter *)dev->data->dev_private;
8459 uint32_t sync_status;
8460 uint64_t tx_tstamp_cycles;
8463 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8464 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
8467 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
8468 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
8469 *timestamp = rte_ns_to_timespec(ns);
8475 * i40e_parse_dcb_configure - parse dcb configure from user
8476 * @dev: the device being configured
8477 * @dcb_cfg: pointer of the result of parse
8478 * @*tc_map: bit map of enabled traffic classes
8480 * Returns 0 on success, negative value on failure
8483 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
8484 struct i40e_dcbx_config *dcb_cfg,
8487 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
8488 uint8_t i, tc_bw, bw_lf;
8490 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
8492 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
8493 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
8494 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
8498 /* assume each tc has the same bw */
8499 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
8500 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8501 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
8502 /* to ensure the sum of tcbw is equal to 100 */
8503 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
8504 for (i = 0; i < bw_lf; i++)
8505 dcb_cfg->etscfg.tcbwtable[i]++;
8507 /* assume each tc has the same Transmission Selection Algorithm */
8508 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8509 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
8511 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8512 dcb_cfg->etscfg.prioritytable[i] =
8513 dcb_rx_conf->dcb_tc[i];
8515 /* FW needs one App to configure HW */
8516 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
8517 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
8518 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
8519 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
8521 if (dcb_rx_conf->nb_tcs == 0)
8522 *tc_map = 1; /* tc0 only */
8524 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
8526 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
8527 dcb_cfg->pfc.willing = 0;
8528 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
8529 dcb_cfg->pfc.pfcenable = *tc_map;
8535 static enum i40e_status_code
8536 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
8537 struct i40e_aqc_vsi_properties_data *info,
8538 uint8_t enabled_tcmap)
8540 enum i40e_status_code ret;
8541 int i, total_tc = 0;
8542 uint16_t qpnum_per_tc, bsf, qp_idx;
8543 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
8544 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
8545 uint16_t used_queues;
8547 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
8548 if (ret != I40E_SUCCESS)
8551 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8552 if (enabled_tcmap & (1 << i))
8557 vsi->enabled_tc = enabled_tcmap;
8559 /* different VSI has different queues assigned */
8560 if (vsi->type == I40E_VSI_MAIN)
8561 used_queues = dev_data->nb_rx_queues -
8562 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8563 else if (vsi->type == I40E_VSI_VMDQ2)
8564 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8566 PMD_INIT_LOG(ERR, "unsupported VSI type.");
8567 return I40E_ERR_NO_AVAILABLE_VSI;
8570 qpnum_per_tc = used_queues / total_tc;
8571 /* Number of queues per enabled TC */
8572 if (qpnum_per_tc == 0) {
8573 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
8574 return I40E_ERR_INVALID_QP_ID;
8576 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
8578 bsf = rte_bsf32(qpnum_per_tc);
8581 * Configure TC and queue mapping parameters, for enabled TC,
8582 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
8583 * default queue will serve it.
8586 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8587 if (vsi->enabled_tc & (1 << i)) {
8588 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
8589 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
8590 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
8591 qp_idx += qpnum_per_tc;
8593 info->tc_mapping[i] = 0;
8596 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
8597 if (vsi->type == I40E_VSI_SRIOV) {
8598 info->mapping_flags |=
8599 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
8600 for (i = 0; i < vsi->nb_qps; i++)
8601 info->queue_mapping[i] =
8602 rte_cpu_to_le_16(vsi->base_queue + i);
8604 info->mapping_flags |=
8605 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
8606 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
8608 info->valid_sections |=
8609 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
8611 return I40E_SUCCESS;
8615 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
8616 * @veb: VEB to be configured
8617 * @tc_map: enabled TC bitmap
8619 * Returns 0 on success, negative value on failure
8621 static enum i40e_status_code
8622 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
8624 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
8625 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
8626 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
8627 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
8628 enum i40e_status_code ret = I40E_SUCCESS;
8632 /* Check if enabled_tc is same as existing or new TCs */
8633 if (veb->enabled_tc == tc_map)
8636 /* configure tc bandwidth */
8637 memset(&veb_bw, 0, sizeof(veb_bw));
8638 veb_bw.tc_valid_bits = tc_map;
8639 /* Enable ETS TCs with equal BW Share for now across all VSIs */
8640 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8641 if (tc_map & BIT_ULL(i))
8642 veb_bw.tc_bw_share_credits[i] = 1;
8644 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
8647 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
8648 " per TC failed = %d",
8649 hw->aq.asq_last_status);
8653 memset(&ets_query, 0, sizeof(ets_query));
8654 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
8656 if (ret != I40E_SUCCESS) {
8657 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
8658 " configuration %u", hw->aq.asq_last_status);
8661 memset(&bw_query, 0, sizeof(bw_query));
8662 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
8664 if (ret != I40E_SUCCESS) {
8665 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
8666 " configuration %u", hw->aq.asq_last_status);
8670 /* store and print out BW info */
8671 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
8672 veb->bw_info.bw_max = ets_query.tc_bw_max;
8673 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
8674 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
8675 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
8676 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
8678 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8679 veb->bw_info.bw_ets_share_credits[i] =
8680 bw_query.tc_bw_share_credits[i];
8681 veb->bw_info.bw_ets_credits[i] =
8682 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
8683 /* 4 bits per TC, 4th bit is reserved */
8684 veb->bw_info.bw_ets_max[i] =
8685 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
8686 RTE_LEN2MASK(3, uint8_t));
8687 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
8688 veb->bw_info.bw_ets_share_credits[i]);
8689 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
8690 veb->bw_info.bw_ets_credits[i]);
8691 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
8692 veb->bw_info.bw_ets_max[i]);
8695 veb->enabled_tc = tc_map;
8702 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
8703 * @vsi: VSI to be configured
8704 * @tc_map: enabled TC bitmap
8706 * Returns 0 on success, negative value on failure
8708 static enum i40e_status_code
8709 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
8711 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
8712 struct i40e_vsi_context ctxt;
8713 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
8714 enum i40e_status_code ret = I40E_SUCCESS;
8717 /* Check if enabled_tc is same as existing or new TCs */
8718 if (vsi->enabled_tc == tc_map)
8721 /* configure tc bandwidth */
8722 memset(&bw_data, 0, sizeof(bw_data));
8723 bw_data.tc_valid_bits = tc_map;
8724 /* Enable ETS TCs with equal BW Share for now across all VSIs */
8725 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8726 if (tc_map & BIT_ULL(i))
8727 bw_data.tc_bw_credits[i] = 1;
8729 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
8731 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
8732 " per TC failed = %d",
8733 hw->aq.asq_last_status);
8736 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
8737 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
8739 /* Update Queue Pairs Mapping for currently enabled UPs */
8740 ctxt.seid = vsi->seid;
8741 ctxt.pf_num = hw->pf_id;
8743 ctxt.uplink_seid = vsi->uplink_seid;
8744 ctxt.info = vsi->info;
8746 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
8750 /* Update the VSI after updating the VSI queue-mapping information */
8751 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8753 PMD_INIT_LOG(ERR, "Failed to configure "
8754 "TC queue mapping = %d",
8755 hw->aq.asq_last_status);
8758 /* update the local VSI info with updated queue map */
8759 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
8760 sizeof(vsi->info.tc_mapping));
8761 (void)rte_memcpy(&vsi->info.queue_mapping,
8762 &ctxt.info.queue_mapping,
8763 sizeof(vsi->info.queue_mapping));
8764 vsi->info.mapping_flags = ctxt.info.mapping_flags;
8765 vsi->info.valid_sections = 0;
8767 /* query and update current VSI BW information */
8768 ret = i40e_vsi_get_bw_config(vsi);
8771 "Failed updating vsi bw info, err %s aq_err %s",
8772 i40e_stat_str(hw, ret),
8773 i40e_aq_str(hw, hw->aq.asq_last_status));
8777 vsi->enabled_tc = tc_map;
8784 * i40e_dcb_hw_configure - program the dcb setting to hw
8785 * @pf: pf the configuration is taken on
8786 * @new_cfg: new configuration
8787 * @tc_map: enabled TC bitmap
8789 * Returns 0 on success, negative value on failure
8791 static enum i40e_status_code
8792 i40e_dcb_hw_configure(struct i40e_pf *pf,
8793 struct i40e_dcbx_config *new_cfg,
8796 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8797 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
8798 struct i40e_vsi *main_vsi = pf->main_vsi;
8799 struct i40e_vsi_list *vsi_list;
8800 enum i40e_status_code ret;
8804 /* Use the FW API if FW > v4.4*/
8805 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
8806 (hw->aq.fw_maj_ver >= 5))) {
8807 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
8808 " to configure DCB");
8809 return I40E_ERR_FIRMWARE_API_VERSION;
8812 /* Check if need reconfiguration */
8813 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
8814 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
8815 return I40E_SUCCESS;
8818 /* Copy the new config to the current config */
8819 *old_cfg = *new_cfg;
8820 old_cfg->etsrec = old_cfg->etscfg;
8821 ret = i40e_set_dcb_config(hw);
8824 "Set DCB Config failed, err %s aq_err %s\n",
8825 i40e_stat_str(hw, ret),
8826 i40e_aq_str(hw, hw->aq.asq_last_status));
8829 /* set receive Arbiter to RR mode and ETS scheme by default */
8830 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
8831 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
8832 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
8833 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
8834 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
8835 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
8836 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
8837 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
8838 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
8839 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
8840 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
8841 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
8842 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
8844 /* get local mib to check whether it is configured correctly */
8846 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
8847 /* Get Local DCB Config */
8848 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
8849 &hw->local_dcbx_config);
8851 /* if Veb is created, need to update TC of it at first */
8852 if (main_vsi->veb) {
8853 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
8855 PMD_INIT_LOG(WARNING,
8856 "Failed configuring TC for VEB seid=%d\n",
8857 main_vsi->veb->seid);
8859 /* Update each VSI */
8860 i40e_vsi_config_tc(main_vsi, tc_map);
8861 if (main_vsi->veb) {
8862 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
8863 /* Beside main VSI and VMDQ VSIs, only enable default
8866 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
8867 ret = i40e_vsi_config_tc(vsi_list->vsi,
8870 ret = i40e_vsi_config_tc(vsi_list->vsi,
8871 I40E_DEFAULT_TCMAP);
8873 PMD_INIT_LOG(WARNING,
8874 "Failed configuring TC for VSI seid=%d\n",
8875 vsi_list->vsi->seid);
8879 return I40E_SUCCESS;
8883 * i40e_dcb_init_configure - initial dcb config
8884 * @dev: device being configured
8885 * @sw_dcb: indicate whether dcb is sw configured or hw offload
8887 * Returns 0 on success, negative value on failure
8890 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
8892 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8893 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8896 if ((pf->flags & I40E_FLAG_DCB) == 0) {
8897 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8901 /* DCB initialization:
8902 * Update DCB configuration from the Firmware and configure
8903 * LLDP MIB change event.
8905 if (sw_dcb == TRUE) {
8906 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
8907 if (ret != I40E_SUCCESS)
8908 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
8910 ret = i40e_init_dcb(hw);
8911 /* if sw_dcb, lldp agent is stopped, the return from
8912 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
8915 if (ret != I40E_SUCCESS &&
8916 hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
8917 memset(&hw->local_dcbx_config, 0,
8918 sizeof(struct i40e_dcbx_config));
8919 /* set dcb default configuration */
8920 hw->local_dcbx_config.etscfg.willing = 0;
8921 hw->local_dcbx_config.etscfg.maxtcs = 0;
8922 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
8923 hw->local_dcbx_config.etscfg.tsatable[0] =
8925 hw->local_dcbx_config.etsrec =
8926 hw->local_dcbx_config.etscfg;
8927 hw->local_dcbx_config.pfc.willing = 0;
8928 hw->local_dcbx_config.pfc.pfccap =
8929 I40E_MAX_TRAFFIC_CLASS;
8930 /* FW needs one App to configure HW */
8931 hw->local_dcbx_config.numapps = 1;
8932 hw->local_dcbx_config.app[0].selector =
8933 I40E_APP_SEL_ETHTYPE;
8934 hw->local_dcbx_config.app[0].priority = 3;
8935 hw->local_dcbx_config.app[0].protocolid =
8936 I40E_APP_PROTOID_FCOE;
8937 ret = i40e_set_dcb_config(hw);
8939 PMD_INIT_LOG(ERR, "default dcb config fails."
8940 " err = %d, aq_err = %d.", ret,
8941 hw->aq.asq_last_status);
8945 PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8946 " aq_err = %d.", ret,
8947 hw->aq.asq_last_status);
8951 ret = i40e_aq_start_lldp(hw, NULL);
8952 if (ret != I40E_SUCCESS)
8953 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
8955 ret = i40e_init_dcb(hw);
8957 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
8958 PMD_INIT_LOG(ERR, "HW doesn't support"
8963 PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8964 " aq_err = %d.", ret,
8965 hw->aq.asq_last_status);
8973 * i40e_dcb_setup - setup dcb related config
8974 * @dev: device being configured
8976 * Returns 0 on success, negative value on failure
8979 i40e_dcb_setup(struct rte_eth_dev *dev)
8981 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8982 struct i40e_dcbx_config dcb_cfg;
8986 if ((pf->flags & I40E_FLAG_DCB) == 0) {
8987 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8991 if (pf->vf_num != 0)
8992 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
8994 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
8996 PMD_INIT_LOG(ERR, "invalid dcb config");
8999 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9001 PMD_INIT_LOG(ERR, "dcb sw configure fails");
9009 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
9010 struct rte_eth_dcb_info *dcb_info)
9012 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9013 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9014 struct i40e_vsi *vsi = pf->main_vsi;
9015 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
9016 uint16_t bsf, tc_mapping;
9019 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
9020 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
9022 dcb_info->nb_tcs = 1;
9023 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9024 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
9025 for (i = 0; i < dcb_info->nb_tcs; i++)
9026 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
9028 /* get queue mapping if vmdq is disabled */
9029 if (!pf->nb_cfg_vmdq_vsi) {
9030 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9031 if (!(vsi->enabled_tc & (1 << i)))
9033 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9034 dcb_info->tc_queue.tc_rxq[j][i].base =
9035 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9036 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9037 dcb_info->tc_queue.tc_txq[j][i].base =
9038 dcb_info->tc_queue.tc_rxq[j][i].base;
9039 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9040 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9041 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9042 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9043 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9048 /* get queue mapping if vmdq is enabled */
9050 vsi = pf->vmdq[j].vsi;
9051 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9052 if (!(vsi->enabled_tc & (1 << i)))
9054 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9055 dcb_info->tc_queue.tc_rxq[j][i].base =
9056 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9057 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9058 dcb_info->tc_queue.tc_txq[j][i].base =
9059 dcb_info->tc_queue.tc_rxq[j][i].base;
9060 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9061 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9062 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9063 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9064 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9067 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
9072 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
9074 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9075 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9077 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
9080 msix_intr = intr_handle->intr_vec[queue_id];
9081 if (msix_intr == I40E_MISC_VEC_ID)
9082 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
9083 I40E_PFINT_DYN_CTLN_INTENA_MASK |
9084 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9085 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9087 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9090 I40E_PFINT_DYN_CTLN(msix_intr -
9092 I40E_PFINT_DYN_CTLN_INTENA_MASK |
9093 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9094 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9096 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9098 I40E_WRITE_FLUSH(hw);
9099 rte_intr_enable(&dev->pci_dev->intr_handle);
9105 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
9107 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9108 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9111 msix_intr = intr_handle->intr_vec[queue_id];
9112 if (msix_intr == I40E_MISC_VEC_ID)
9113 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
9116 I40E_PFINT_DYN_CTLN(msix_intr -
9119 I40E_WRITE_FLUSH(hw);
9124 static int i40e_get_reg_length(__rte_unused struct rte_eth_dev *dev)
9126 /* Highest base addr + 32-bit word */
9127 return I40E_GLGEN_STAT_CLEAR + 4;
9130 static int i40e_get_regs(struct rte_eth_dev *dev,
9131 struct rte_dev_reg_info *regs)
9133 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9134 uint32_t *ptr_data = regs->data;
9135 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
9136 const struct i40e_reg_info *reg_info;
9138 /* The first few registers have to be read using AQ operations */
9140 while (i40e_regs_adminq[reg_idx].name) {
9141 reg_info = &i40e_regs_adminq[reg_idx++];
9142 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9144 arr_idx2 <= reg_info->count2;
9146 reg_offset = arr_idx * reg_info->stride1 +
9147 arr_idx2 * reg_info->stride2;
9148 reg_offset += reg_info->base_addr;
9149 ptr_data[reg_offset >> 2] =
9150 i40e_read_rx_ctl(hw, reg_offset);
9154 /* The remaining registers can be read using primitives */
9156 while (i40e_regs_others[reg_idx].name) {
9157 reg_info = &i40e_regs_others[reg_idx++];
9158 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9160 arr_idx2 <= reg_info->count2;
9162 reg_offset = arr_idx * reg_info->stride1 +
9163 arr_idx2 * reg_info->stride2;
9164 reg_offset += reg_info->base_addr;
9165 ptr_data[reg_offset >> 2] =
9166 I40E_READ_REG(hw, reg_offset);
9173 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
9175 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9177 /* Convert word count to byte count */
9178 return hw->nvm.sr_size << 1;
9181 static int i40e_get_eeprom(struct rte_eth_dev *dev,
9182 struct rte_dev_eeprom_info *eeprom)
9184 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9185 uint16_t *data = eeprom->data;
9186 uint16_t offset, length, cnt_words;
9189 offset = eeprom->offset >> 1;
9190 length = eeprom->length >> 1;
9193 if (offset > hw->nvm.sr_size ||
9194 offset + length > hw->nvm.sr_size) {
9195 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
9199 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
9201 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
9202 if (ret_code != I40E_SUCCESS || cnt_words != length) {
9203 PMD_DRV_LOG(ERR, "EEPROM read failed.");
9210 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
9211 struct ether_addr *mac_addr)
9213 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9215 if (!is_valid_assigned_ether_addr(mac_addr)) {
9216 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
9220 /* Flags: 0x3 updates port address */
9221 i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
9225 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
9227 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9228 struct rte_eth_dev_data *dev_data = pf->dev_data;
9229 uint32_t frame_size = mtu + ETHER_HDR_LEN
9230 + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
9233 /* check if mtu is within the allowed range */
9234 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
9237 /* mtu setting is forbidden if port is start */
9238 if (dev_data->dev_started) {
9240 "port %d must be stopped before configuration\n",
9245 if (frame_size > ETHER_MAX_LEN)
9246 dev_data->dev_conf.rxmode.jumbo_frame = 1;
9248 dev_data->dev_conf.rxmode.jumbo_frame = 0;
9250 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;