1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
14 #include <rte_common.h>
16 #include <rte_string_fns.h>
18 #include <rte_bus_pci.h>
19 #include <rte_ether.h>
20 #include <rte_ethdev_driver.h>
21 #include <rte_ethdev_pci.h>
22 #include <rte_memzone.h>
23 #include <rte_malloc.h>
24 #include <rte_memcpy.h>
25 #include <rte_alarm.h>
27 #include <rte_eth_ctrl.h>
28 #include <rte_tailq.h>
29 #include <rte_hash_crc.h>
31 #include "i40e_logs.h"
32 #include "base/i40e_prototype.h"
33 #include "base/i40e_adminq_cmd.h"
34 #include "base/i40e_type.h"
35 #include "base/i40e_register.h"
36 #include "base/i40e_dcb.h"
37 #include "i40e_ethdev.h"
38 #include "i40e_rxtx.h"
40 #include "i40e_regs.h"
41 #include "rte_pmd_i40e.h"
43 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
44 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
46 #define I40E_CLEAR_PXE_WAIT_MS 200
48 /* Maximun number of capability elements */
49 #define I40E_MAX_CAP_ELE_NUM 128
51 /* Wait count and interval */
52 #define I40E_CHK_Q_ENA_COUNT 1000
53 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
55 /* Maximun number of VSI */
56 #define I40E_MAX_NUM_VSIS (384UL)
58 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
60 /* Flow control default timer */
61 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
63 /* Flow control enable fwd bit */
64 #define I40E_PRTMAC_FWD_CTRL 0x00000001
66 /* Receive Packet Buffer size */
67 #define I40E_RXPBSIZE (968 * 1024)
70 #define I40E_KILOSHIFT 10
72 /* Flow control default high water */
73 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
75 /* Flow control default low water */
76 #define I40E_DEFAULT_LOW_WATER (0xF2000 >> I40E_KILOSHIFT)
78 /* Receive Average Packet Size in Byte*/
79 #define I40E_PACKET_AVERAGE_SIZE 128
81 /* Mask of PF interrupt causes */
82 #define I40E_PFINT_ICR0_ENA_MASK ( \
83 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
84 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
85 I40E_PFINT_ICR0_ENA_GRST_MASK | \
86 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
87 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
88 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
89 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
90 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
91 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
93 #define I40E_FLOW_TYPES ( \
94 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
95 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
96 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
97 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
98 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
99 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
100 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
101 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
102 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
103 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
104 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
106 /* Additional timesync values. */
107 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
108 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
109 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
110 #define I40E_PRTTSYN_TSYNENA 0x80000000
111 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
112 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
115 * Below are values for writing un-exposed registers suggested
118 /* Destination MAC address */
119 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
120 /* Source MAC address */
121 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
122 /* Outer (S-Tag) VLAN tag in the outer L2 header */
123 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
124 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
125 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
126 /* Single VLAN tag in the inner L2 header */
127 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
128 /* Source IPv4 address */
129 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
130 /* Destination IPv4 address */
131 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
132 /* Source IPv4 address for X722 */
133 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
134 /* Destination IPv4 address for X722 */
135 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
136 /* IPv4 Protocol for X722 */
137 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
138 /* IPv4 Time to Live for X722 */
139 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
140 /* IPv4 Type of Service (TOS) */
141 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
143 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
144 /* IPv4 Time to Live */
145 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
146 /* Source IPv6 address */
147 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
148 /* Destination IPv6 address */
149 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
150 /* IPv6 Traffic Class (TC) */
151 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
152 /* IPv6 Next Header */
153 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
155 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
157 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
158 /* Destination L4 port */
159 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
160 /* SCTP verification tag */
161 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
162 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
163 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
164 /* Source port of tunneling UDP */
165 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
166 /* Destination port of tunneling UDP */
167 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
168 /* UDP Tunneling ID, NVGRE/GRE key */
169 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
170 /* Last ether type */
171 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
172 /* Tunneling outer destination IPv4 address */
173 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
174 /* Tunneling outer destination IPv6 address */
175 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
176 /* 1st word of flex payload */
177 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
178 /* 2nd word of flex payload */
179 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
180 /* 3rd word of flex payload */
181 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
182 /* 4th word of flex payload */
183 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
184 /* 5th word of flex payload */
185 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
186 /* 6th word of flex payload */
187 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
188 /* 7th word of flex payload */
189 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
190 /* 8th word of flex payload */
191 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
192 /* all 8 words flex payload */
193 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
194 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
196 #define I40E_TRANSLATE_INSET 0
197 #define I40E_TRANSLATE_REG 1
199 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
200 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
201 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
202 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
203 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
204 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
206 /* PCI offset for querying capability */
207 #define PCI_DEV_CAP_REG 0xA4
208 /* PCI offset for enabling/disabling Extended Tag */
209 #define PCI_DEV_CTRL_REG 0xA8
210 /* Bit mask of Extended Tag capability */
211 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
212 /* Bit shift of Extended Tag enable/disable */
213 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
214 /* Bit mask of Extended Tag enable/disable */
215 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
217 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
218 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
219 static int i40e_dev_configure(struct rte_eth_dev *dev);
220 static int i40e_dev_start(struct rte_eth_dev *dev);
221 static void i40e_dev_stop(struct rte_eth_dev *dev);
222 static void i40e_dev_close(struct rte_eth_dev *dev);
223 static int i40e_dev_reset(struct rte_eth_dev *dev);
224 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
225 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
226 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
227 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
228 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
229 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
230 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
231 struct rte_eth_stats *stats);
232 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
233 struct rte_eth_xstat *xstats, unsigned n);
234 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
235 struct rte_eth_xstat_name *xstats_names,
237 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
238 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
242 static int i40e_fw_version_get(struct rte_eth_dev *dev,
243 char *fw_version, size_t fw_size);
244 static void i40e_dev_info_get(struct rte_eth_dev *dev,
245 struct rte_eth_dev_info *dev_info);
246 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
249 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
250 enum rte_vlan_type vlan_type,
252 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
253 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
256 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
257 static int i40e_dev_led_on(struct rte_eth_dev *dev);
258 static int i40e_dev_led_off(struct rte_eth_dev *dev);
259 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
260 struct rte_eth_fc_conf *fc_conf);
261 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
262 struct rte_eth_fc_conf *fc_conf);
263 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
264 struct rte_eth_pfc_conf *pfc_conf);
265 static int i40e_macaddr_add(struct rte_eth_dev *dev,
266 struct ether_addr *mac_addr,
269 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
270 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
271 struct rte_eth_rss_reta_entry64 *reta_conf,
273 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
274 struct rte_eth_rss_reta_entry64 *reta_conf,
277 static int i40e_get_cap(struct i40e_hw *hw);
278 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
279 static int i40e_pf_setup(struct i40e_pf *pf);
280 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
281 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
282 static int i40e_dcb_setup(struct rte_eth_dev *dev);
283 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
284 bool offset_loaded, uint64_t *offset, uint64_t *stat);
285 static void i40e_stat_update_48(struct i40e_hw *hw,
291 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
292 static void i40e_dev_interrupt_handler(void *param);
293 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
294 uint32_t base, uint32_t num);
295 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
296 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
298 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
300 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
301 static int i40e_veb_release(struct i40e_veb *veb);
302 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
303 struct i40e_vsi *vsi);
304 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
305 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
306 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
307 struct i40e_macvlan_filter *mv_f,
310 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
311 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
312 struct rte_eth_rss_conf *rss_conf);
313 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
314 struct rte_eth_rss_conf *rss_conf);
315 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
316 struct rte_eth_udp_tunnel *udp_tunnel);
317 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
318 struct rte_eth_udp_tunnel *udp_tunnel);
319 static void i40e_filter_input_set_init(struct i40e_pf *pf);
320 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
321 enum rte_filter_op filter_op,
323 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
324 enum rte_filter_type filter_type,
325 enum rte_filter_op filter_op,
327 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
328 struct rte_eth_dcb_info *dcb_info);
329 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
330 static void i40e_configure_registers(struct i40e_hw *hw);
331 static void i40e_hw_init(struct rte_eth_dev *dev);
332 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
333 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
339 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
340 struct rte_eth_mirror_conf *mirror_conf,
341 uint8_t sw_id, uint8_t on);
342 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
344 static int i40e_timesync_enable(struct rte_eth_dev *dev);
345 static int i40e_timesync_disable(struct rte_eth_dev *dev);
346 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
347 struct timespec *timestamp,
349 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
350 struct timespec *timestamp);
351 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
353 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
355 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
356 struct timespec *timestamp);
357 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
358 const struct timespec *timestamp);
360 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
362 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
365 static int i40e_get_regs(struct rte_eth_dev *dev,
366 struct rte_dev_reg_info *regs);
368 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
370 static int i40e_get_eeprom(struct rte_eth_dev *dev,
371 struct rte_dev_eeprom_info *eeprom);
373 static int i40e_get_module_info(struct rte_eth_dev *dev,
374 struct rte_eth_dev_module_info *modinfo);
375 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
376 struct rte_dev_eeprom_info *info);
378 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
379 struct ether_addr *mac_addr);
381 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
383 static int i40e_ethertype_filter_convert(
384 const struct rte_eth_ethertype_filter *input,
385 struct i40e_ethertype_filter *filter);
386 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
387 struct i40e_ethertype_filter *filter);
389 static int i40e_tunnel_filter_convert(
390 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
391 struct i40e_tunnel_filter *tunnel_filter);
392 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
393 struct i40e_tunnel_filter *tunnel_filter);
394 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
396 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
397 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
398 static void i40e_filter_restore(struct i40e_pf *pf);
399 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
401 int i40e_logtype_init;
402 int i40e_logtype_driver;
404 static const struct rte_pci_id pci_id_i40e_map[] = {
405 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
406 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
407 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
408 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
409 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
410 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
411 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
412 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
413 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
414 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
415 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
416 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
417 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
418 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
419 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
420 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
421 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
422 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
423 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
424 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
425 { .vendor_id = 0, /* sentinel */ },
428 static const struct eth_dev_ops i40e_eth_dev_ops = {
429 .dev_configure = i40e_dev_configure,
430 .dev_start = i40e_dev_start,
431 .dev_stop = i40e_dev_stop,
432 .dev_close = i40e_dev_close,
433 .dev_reset = i40e_dev_reset,
434 .promiscuous_enable = i40e_dev_promiscuous_enable,
435 .promiscuous_disable = i40e_dev_promiscuous_disable,
436 .allmulticast_enable = i40e_dev_allmulticast_enable,
437 .allmulticast_disable = i40e_dev_allmulticast_disable,
438 .dev_set_link_up = i40e_dev_set_link_up,
439 .dev_set_link_down = i40e_dev_set_link_down,
440 .link_update = i40e_dev_link_update,
441 .stats_get = i40e_dev_stats_get,
442 .xstats_get = i40e_dev_xstats_get,
443 .xstats_get_names = i40e_dev_xstats_get_names,
444 .stats_reset = i40e_dev_stats_reset,
445 .xstats_reset = i40e_dev_stats_reset,
446 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
447 .fw_version_get = i40e_fw_version_get,
448 .dev_infos_get = i40e_dev_info_get,
449 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
450 .vlan_filter_set = i40e_vlan_filter_set,
451 .vlan_tpid_set = i40e_vlan_tpid_set,
452 .vlan_offload_set = i40e_vlan_offload_set,
453 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
454 .vlan_pvid_set = i40e_vlan_pvid_set,
455 .rx_queue_start = i40e_dev_rx_queue_start,
456 .rx_queue_stop = i40e_dev_rx_queue_stop,
457 .tx_queue_start = i40e_dev_tx_queue_start,
458 .tx_queue_stop = i40e_dev_tx_queue_stop,
459 .rx_queue_setup = i40e_dev_rx_queue_setup,
460 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
461 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
462 .rx_queue_release = i40e_dev_rx_queue_release,
463 .rx_queue_count = i40e_dev_rx_queue_count,
464 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
465 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
466 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
467 .tx_queue_setup = i40e_dev_tx_queue_setup,
468 .tx_queue_release = i40e_dev_tx_queue_release,
469 .dev_led_on = i40e_dev_led_on,
470 .dev_led_off = i40e_dev_led_off,
471 .flow_ctrl_get = i40e_flow_ctrl_get,
472 .flow_ctrl_set = i40e_flow_ctrl_set,
473 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
474 .mac_addr_add = i40e_macaddr_add,
475 .mac_addr_remove = i40e_macaddr_remove,
476 .reta_update = i40e_dev_rss_reta_update,
477 .reta_query = i40e_dev_rss_reta_query,
478 .rss_hash_update = i40e_dev_rss_hash_update,
479 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
480 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
481 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
482 .filter_ctrl = i40e_dev_filter_ctrl,
483 .rxq_info_get = i40e_rxq_info_get,
484 .txq_info_get = i40e_txq_info_get,
485 .mirror_rule_set = i40e_mirror_rule_set,
486 .mirror_rule_reset = i40e_mirror_rule_reset,
487 .timesync_enable = i40e_timesync_enable,
488 .timesync_disable = i40e_timesync_disable,
489 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
490 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
491 .get_dcb_info = i40e_dev_get_dcb_info,
492 .timesync_adjust_time = i40e_timesync_adjust_time,
493 .timesync_read_time = i40e_timesync_read_time,
494 .timesync_write_time = i40e_timesync_write_time,
495 .get_reg = i40e_get_regs,
496 .get_eeprom_length = i40e_get_eeprom_length,
497 .get_eeprom = i40e_get_eeprom,
498 .get_module_info = i40e_get_module_info,
499 .get_module_eeprom = i40e_get_module_eeprom,
500 .mac_addr_set = i40e_set_default_mac_addr,
501 .mtu_set = i40e_dev_mtu_set,
502 .tm_ops_get = i40e_tm_ops_get,
505 /* store statistics names and its offset in stats structure */
506 struct rte_i40e_xstats_name_off {
507 char name[RTE_ETH_XSTATS_NAME_SIZE];
511 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
512 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
513 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
514 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
515 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
516 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
517 rx_unknown_protocol)},
518 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
519 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
520 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
521 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
524 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
525 sizeof(rte_i40e_stats_strings[0]))
527 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
528 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
529 tx_dropped_link_down)},
530 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
531 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
533 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
534 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
536 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
538 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
540 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
541 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
542 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
543 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
544 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
545 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
547 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
549 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
551 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
553 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
555 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
557 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
559 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
561 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
562 mac_short_packet_dropped)},
563 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
565 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
566 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
567 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
569 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
571 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
573 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
575 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
577 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
579 {"rx_flow_director_atr_match_packets",
580 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
581 {"rx_flow_director_sb_match_packets",
582 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
583 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
585 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
587 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
589 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
593 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
594 sizeof(rte_i40e_hw_port_strings[0]))
596 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
597 {"xon_packets", offsetof(struct i40e_hw_port_stats,
599 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
603 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
604 sizeof(rte_i40e_rxq_prio_strings[0]))
606 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
607 {"xon_packets", offsetof(struct i40e_hw_port_stats,
609 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
611 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
612 priority_xon_2_xoff)},
615 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
616 sizeof(rte_i40e_txq_prio_strings[0]))
618 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
619 struct rte_pci_device *pci_dev)
621 return rte_eth_dev_pci_generic_probe(pci_dev,
622 sizeof(struct i40e_adapter), eth_i40e_dev_init);
625 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
627 return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
630 static struct rte_pci_driver rte_i40e_pmd = {
631 .id_table = pci_id_i40e_map,
632 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
633 RTE_PCI_DRV_IOVA_AS_VA,
634 .probe = eth_i40e_pci_probe,
635 .remove = eth_i40e_pci_remove,
639 i40e_write_global_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
641 i40e_write_rx_ctl(hw, reg_addr, reg_val);
642 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is modified "
647 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
648 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
649 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
651 #ifndef I40E_GLQF_ORT
652 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
654 #ifndef I40E_GLQF_PIT
655 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
657 #ifndef I40E_GLQF_L3_MAP
658 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
661 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
664 * Initialize registers for parsing packet type of QinQ
665 * This should be removed from code once proper
666 * configuration API is added to avoid configuration conflicts
667 * between ports of the same device.
669 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
670 I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
671 i40e_global_cfg_warning(I40E_WARNING_QINQ_PARSER);
674 static inline void i40e_config_automask(struct i40e_pf *pf)
676 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
679 /* INTENA flag is not auto-cleared for interrupt */
680 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
681 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
682 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
684 /* If support multi-driver, PF will use INT0. */
685 if (!pf->support_multi_driver)
686 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
688 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
691 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
694 * Add a ethertype filter to drop all flow control frames transmitted
698 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
700 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
701 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
702 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
703 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
706 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
707 I40E_FLOW_CONTROL_ETHERTYPE, flags,
708 pf->main_vsi_seid, 0,
712 "Failed to add filter to drop flow control frames from VSIs.");
716 floating_veb_list_handler(__rte_unused const char *key,
717 const char *floating_veb_value,
721 unsigned int count = 0;
724 bool *vf_floating_veb = opaque;
726 while (isblank(*floating_veb_value))
727 floating_veb_value++;
729 /* Reset floating VEB configuration for VFs */
730 for (idx = 0; idx < I40E_MAX_VF; idx++)
731 vf_floating_veb[idx] = false;
735 while (isblank(*floating_veb_value))
736 floating_veb_value++;
737 if (*floating_veb_value == '\0')
740 idx = strtoul(floating_veb_value, &end, 10);
741 if (errno || end == NULL)
743 while (isblank(*end))
747 } else if ((*end == ';') || (*end == '\0')) {
749 if (min == I40E_MAX_VF)
751 if (max >= I40E_MAX_VF)
752 max = I40E_MAX_VF - 1;
753 for (idx = min; idx <= max; idx++) {
754 vf_floating_veb[idx] = true;
761 floating_veb_value = end + 1;
762 } while (*end != '\0');
771 config_vf_floating_veb(struct rte_devargs *devargs,
772 uint16_t floating_veb,
773 bool *vf_floating_veb)
775 struct rte_kvargs *kvlist;
777 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
781 /* All the VFs attach to the floating VEB by default
782 * when the floating VEB is enabled.
784 for (i = 0; i < I40E_MAX_VF; i++)
785 vf_floating_veb[i] = true;
790 kvlist = rte_kvargs_parse(devargs->args, NULL);
794 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
795 rte_kvargs_free(kvlist);
798 /* When the floating_veb_list parameter exists, all the VFs
799 * will attach to the legacy VEB firstly, then configure VFs
800 * to the floating VEB according to the floating_veb_list.
802 if (rte_kvargs_process(kvlist, floating_veb_list,
803 floating_veb_list_handler,
804 vf_floating_veb) < 0) {
805 rte_kvargs_free(kvlist);
808 rte_kvargs_free(kvlist);
812 i40e_check_floating_handler(__rte_unused const char *key,
814 __rte_unused void *opaque)
816 if (strcmp(value, "1"))
823 is_floating_veb_supported(struct rte_devargs *devargs)
825 struct rte_kvargs *kvlist;
826 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
831 kvlist = rte_kvargs_parse(devargs->args, NULL);
835 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
836 rte_kvargs_free(kvlist);
839 /* Floating VEB is enabled when there's key-value:
840 * enable_floating_veb=1
842 if (rte_kvargs_process(kvlist, floating_veb_key,
843 i40e_check_floating_handler, NULL) < 0) {
844 rte_kvargs_free(kvlist);
847 rte_kvargs_free(kvlist);
853 config_floating_veb(struct rte_eth_dev *dev)
855 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
856 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
857 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
859 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
861 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
863 is_floating_veb_supported(pci_dev->device.devargs);
864 config_vf_floating_veb(pci_dev->device.devargs,
866 pf->floating_veb_list);
868 pf->floating_veb = false;
872 #define I40E_L2_TAGS_S_TAG_SHIFT 1
873 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
876 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
878 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
879 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
880 char ethertype_hash_name[RTE_HASH_NAMESIZE];
883 struct rte_hash_parameters ethertype_hash_params = {
884 .name = ethertype_hash_name,
885 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
886 .key_len = sizeof(struct i40e_ethertype_filter_input),
887 .hash_func = rte_hash_crc,
888 .hash_func_init_val = 0,
889 .socket_id = rte_socket_id(),
892 /* Initialize ethertype filter rule list and hash */
893 TAILQ_INIT(ðertype_rule->ethertype_list);
894 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
895 "ethertype_%s", dev->device->name);
896 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
897 if (!ethertype_rule->hash_table) {
898 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
901 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
902 sizeof(struct i40e_ethertype_filter *) *
903 I40E_MAX_ETHERTYPE_FILTER_NUM,
905 if (!ethertype_rule->hash_map) {
907 "Failed to allocate memory for ethertype hash map!");
909 goto err_ethertype_hash_map_alloc;
914 err_ethertype_hash_map_alloc:
915 rte_hash_free(ethertype_rule->hash_table);
921 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
923 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
924 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
925 char tunnel_hash_name[RTE_HASH_NAMESIZE];
928 struct rte_hash_parameters tunnel_hash_params = {
929 .name = tunnel_hash_name,
930 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
931 .key_len = sizeof(struct i40e_tunnel_filter_input),
932 .hash_func = rte_hash_crc,
933 .hash_func_init_val = 0,
934 .socket_id = rte_socket_id(),
937 /* Initialize tunnel filter rule list and hash */
938 TAILQ_INIT(&tunnel_rule->tunnel_list);
939 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
940 "tunnel_%s", dev->device->name);
941 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
942 if (!tunnel_rule->hash_table) {
943 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
946 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
947 sizeof(struct i40e_tunnel_filter *) *
948 I40E_MAX_TUNNEL_FILTER_NUM,
950 if (!tunnel_rule->hash_map) {
952 "Failed to allocate memory for tunnel hash map!");
954 goto err_tunnel_hash_map_alloc;
959 err_tunnel_hash_map_alloc:
960 rte_hash_free(tunnel_rule->hash_table);
966 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
968 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
969 struct i40e_fdir_info *fdir_info = &pf->fdir;
970 char fdir_hash_name[RTE_HASH_NAMESIZE];
973 struct rte_hash_parameters fdir_hash_params = {
974 .name = fdir_hash_name,
975 .entries = I40E_MAX_FDIR_FILTER_NUM,
976 .key_len = sizeof(struct i40e_fdir_input),
977 .hash_func = rte_hash_crc,
978 .hash_func_init_val = 0,
979 .socket_id = rte_socket_id(),
982 /* Initialize flow director filter rule list and hash */
983 TAILQ_INIT(&fdir_info->fdir_list);
984 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
985 "fdir_%s", dev->device->name);
986 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
987 if (!fdir_info->hash_table) {
988 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
991 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
992 sizeof(struct i40e_fdir_filter *) *
993 I40E_MAX_FDIR_FILTER_NUM,
995 if (!fdir_info->hash_map) {
997 "Failed to allocate memory for fdir hash map!");
999 goto err_fdir_hash_map_alloc;
1003 err_fdir_hash_map_alloc:
1004 rte_hash_free(fdir_info->hash_table);
1010 i40e_init_customized_info(struct i40e_pf *pf)
1014 /* Initialize customized pctype */
1015 for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1016 pf->customized_pctype[i].index = i;
1017 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1018 pf->customized_pctype[i].valid = false;
1021 pf->gtp_support = false;
1025 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1027 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1028 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1029 struct i40e_queue_regions *info = &pf->queue_region;
1032 for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1033 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1035 memset(info, 0, sizeof(struct i40e_queue_regions));
1038 #define ETH_I40E_SUPPORT_MULTI_DRIVER "support-multi-driver"
1041 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1046 unsigned long support_multi_driver;
1049 pf = (struct i40e_pf *)opaque;
1052 support_multi_driver = strtoul(value, &end, 10);
1053 if (errno != 0 || end == value || *end != 0) {
1054 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1058 if (support_multi_driver == 1 || support_multi_driver == 0)
1059 pf->support_multi_driver = (bool)support_multi_driver;
1061 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1062 "enable global configuration by default."
1063 ETH_I40E_SUPPORT_MULTI_DRIVER);
1068 i40e_support_multi_driver(struct rte_eth_dev *dev)
1070 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1071 static const char *const valid_keys[] = {
1072 ETH_I40E_SUPPORT_MULTI_DRIVER, NULL};
1073 struct rte_kvargs *kvlist;
1075 /* Enable global configuration by default */
1076 pf->support_multi_driver = false;
1078 if (!dev->device->devargs)
1081 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1085 if (rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER) > 1)
1086 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1087 "the first invalid or last valid one is used !",
1088 ETH_I40E_SUPPORT_MULTI_DRIVER);
1090 if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1091 i40e_parse_multi_drv_handler, pf) < 0) {
1092 rte_kvargs_free(kvlist);
1096 rte_kvargs_free(kvlist);
1101 eth_i40e_dev_init(struct rte_eth_dev *dev)
1103 struct rte_pci_device *pci_dev;
1104 struct rte_intr_handle *intr_handle;
1105 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1106 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1107 struct i40e_vsi *vsi;
1110 uint8_t aq_fail = 0;
1112 PMD_INIT_FUNC_TRACE();
1114 dev->dev_ops = &i40e_eth_dev_ops;
1115 dev->rx_pkt_burst = i40e_recv_pkts;
1116 dev->tx_pkt_burst = i40e_xmit_pkts;
1117 dev->tx_pkt_prepare = i40e_prep_pkts;
1119 /* for secondary processes, we don't initialise any further as primary
1120 * has already done this work. Only check we don't need a different
1122 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1123 i40e_set_rx_function(dev);
1124 i40e_set_tx_function(dev);
1127 i40e_set_default_ptype_table(dev);
1128 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1129 intr_handle = &pci_dev->intr_handle;
1131 rte_eth_copy_pci_info(dev, pci_dev);
1133 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1134 pf->adapter->eth_dev = dev;
1135 pf->dev_data = dev->data;
1137 hw->back = I40E_PF_TO_ADAPTER(pf);
1138 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1141 "Hardware is not available, as address is NULL");
1145 hw->vendor_id = pci_dev->id.vendor_id;
1146 hw->device_id = pci_dev->id.device_id;
1147 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1148 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1149 hw->bus.device = pci_dev->addr.devid;
1150 hw->bus.func = pci_dev->addr.function;
1151 hw->adapter_stopped = 0;
1153 /* Check if need to support multi-driver */
1154 i40e_support_multi_driver(dev);
1156 /* Make sure all is clean before doing PF reset */
1159 /* Initialize the hardware */
1162 /* Reset here to make sure all is clean for each PF */
1163 ret = i40e_pf_reset(hw);
1165 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1169 /* Initialize the shared code (base driver) */
1170 ret = i40e_init_shared_code(hw);
1172 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1176 i40e_config_automask(pf);
1178 i40e_set_default_pctype_table(dev);
1181 * To work around the NVM issue, initialize registers
1182 * for packet type of QinQ by software.
1183 * It should be removed once issues are fixed in NVM.
1185 if (!pf->support_multi_driver)
1186 i40e_GLQF_reg_init(hw);
1188 /* Initialize the input set for filters (hash and fd) to default value */
1189 i40e_filter_input_set_init(pf);
1191 /* Initialize the parameters for adminq */
1192 i40e_init_adminq_parameter(hw);
1193 ret = i40e_init_adminq(hw);
1194 if (ret != I40E_SUCCESS) {
1195 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1198 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1199 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1200 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1201 ((hw->nvm.version >> 12) & 0xf),
1202 ((hw->nvm.version >> 4) & 0xff),
1203 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1205 /* initialise the L3_MAP register */
1206 if (!pf->support_multi_driver) {
1207 ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1210 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1213 "Global register 0x%08x is changed with 0x28",
1214 I40E_GLQF_L3_MAP(40));
1215 i40e_global_cfg_warning(I40E_WARNING_QINQ_CLOUD_FILTER);
1218 /* Need the special FW version to support floating VEB */
1219 config_floating_veb(dev);
1220 /* Clear PXE mode */
1221 i40e_clear_pxe_mode(hw);
1222 i40e_dev_sync_phy_type(hw);
1225 * On X710, performance number is far from the expectation on recent
1226 * firmware versions. The fix for this issue may not be integrated in
1227 * the following firmware version. So the workaround in software driver
1228 * is needed. It needs to modify the initial values of 3 internal only
1229 * registers. Note that the workaround can be removed when it is fixed
1230 * in firmware in the future.
1232 i40e_configure_registers(hw);
1234 /* Get hw capabilities */
1235 ret = i40e_get_cap(hw);
1236 if (ret != I40E_SUCCESS) {
1237 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1238 goto err_get_capabilities;
1241 /* Initialize parameters for PF */
1242 ret = i40e_pf_parameter_init(dev);
1244 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1245 goto err_parameter_init;
1248 /* Initialize the queue management */
1249 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1251 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1252 goto err_qp_pool_init;
1254 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1255 hw->func_caps.num_msix_vectors - 1);
1257 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1258 goto err_msix_pool_init;
1261 /* Initialize lan hmc */
1262 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1263 hw->func_caps.num_rx_qp, 0, 0);
1264 if (ret != I40E_SUCCESS) {
1265 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1266 goto err_init_lan_hmc;
1269 /* Configure lan hmc */
1270 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1271 if (ret != I40E_SUCCESS) {
1272 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1273 goto err_configure_lan_hmc;
1276 /* Get and check the mac address */
1277 i40e_get_mac_addr(hw, hw->mac.addr);
1278 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1279 PMD_INIT_LOG(ERR, "mac address is not valid");
1281 goto err_get_mac_addr;
1283 /* Copy the permanent MAC address */
1284 ether_addr_copy((struct ether_addr *) hw->mac.addr,
1285 (struct ether_addr *) hw->mac.perm_addr);
1287 /* Disable flow control */
1288 hw->fc.requested_mode = I40E_FC_NONE;
1289 i40e_set_fc(hw, &aq_fail, TRUE);
1291 /* Set the global registers with default ether type value */
1292 if (!pf->support_multi_driver) {
1293 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1295 if (ret != I40E_SUCCESS) {
1297 "Failed to set the default outer "
1299 goto err_setup_pf_switch;
1303 /* PF setup, which includes VSI setup */
1304 ret = i40e_pf_setup(pf);
1306 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1307 goto err_setup_pf_switch;
1310 /* reset all stats of the device, including pf and main vsi */
1311 i40e_dev_stats_reset(dev);
1315 /* Disable double vlan by default */
1316 i40e_vsi_config_double_vlan(vsi, FALSE);
1318 /* Disable S-TAG identification when floating_veb is disabled */
1319 if (!pf->floating_veb) {
1320 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1321 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1322 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1323 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1327 if (!vsi->max_macaddrs)
1328 len = ETHER_ADDR_LEN;
1330 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1332 /* Should be after VSI initialized */
1333 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1334 if (!dev->data->mac_addrs) {
1336 "Failed to allocated memory for storing mac address");
1339 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1340 &dev->data->mac_addrs[0]);
1342 /* Init dcb to sw mode by default */
1343 ret = i40e_dcb_init_configure(dev, TRUE);
1344 if (ret != I40E_SUCCESS) {
1345 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1346 pf->flags &= ~I40E_FLAG_DCB;
1348 /* Update HW struct after DCB configuration */
1351 /* initialize pf host driver to setup SRIOV resource if applicable */
1352 i40e_pf_host_init(dev);
1354 /* register callback func to eal lib */
1355 rte_intr_callback_register(intr_handle,
1356 i40e_dev_interrupt_handler, dev);
1358 /* configure and enable device interrupt */
1359 i40e_pf_config_irq0(hw, TRUE);
1360 i40e_pf_enable_irq0(hw);
1362 /* enable uio intr after callback register */
1363 rte_intr_enable(intr_handle);
1365 /* By default disable flexible payload in global configuration */
1366 if (!pf->support_multi_driver)
1367 i40e_flex_payload_reg_set_default(hw);
1370 * Add an ethertype filter to drop all flow control frames transmitted
1371 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1374 i40e_add_tx_flow_control_drop_filter(pf);
1376 /* Set the max frame size to 0x2600 by default,
1377 * in case other drivers changed the default value.
1379 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1381 /* initialize mirror rule list */
1382 TAILQ_INIT(&pf->mirror_list);
1384 /* initialize Traffic Manager configuration */
1385 i40e_tm_conf_init(dev);
1387 /* Initialize customized information */
1388 i40e_init_customized_info(pf);
1390 ret = i40e_init_ethtype_filter_list(dev);
1392 goto err_init_ethtype_filter_list;
1393 ret = i40e_init_tunnel_filter_list(dev);
1395 goto err_init_tunnel_filter_list;
1396 ret = i40e_init_fdir_filter_list(dev);
1398 goto err_init_fdir_filter_list;
1400 /* initialize queue region configuration */
1401 i40e_init_queue_region_conf(dev);
1403 /* initialize rss configuration from rte_flow */
1404 memset(&pf->rss_info, 0,
1405 sizeof(struct i40e_rte_flow_rss_conf));
1409 err_init_fdir_filter_list:
1410 rte_free(pf->tunnel.hash_table);
1411 rte_free(pf->tunnel.hash_map);
1412 err_init_tunnel_filter_list:
1413 rte_free(pf->ethertype.hash_table);
1414 rte_free(pf->ethertype.hash_map);
1415 err_init_ethtype_filter_list:
1416 rte_free(dev->data->mac_addrs);
1418 i40e_vsi_release(pf->main_vsi);
1419 err_setup_pf_switch:
1421 err_configure_lan_hmc:
1422 (void)i40e_shutdown_lan_hmc(hw);
1424 i40e_res_pool_destroy(&pf->msix_pool);
1426 i40e_res_pool_destroy(&pf->qp_pool);
1429 err_get_capabilities:
1430 (void)i40e_shutdown_adminq(hw);
1436 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1438 struct i40e_ethertype_filter *p_ethertype;
1439 struct i40e_ethertype_rule *ethertype_rule;
1441 ethertype_rule = &pf->ethertype;
1442 /* Remove all ethertype filter rules and hash */
1443 if (ethertype_rule->hash_map)
1444 rte_free(ethertype_rule->hash_map);
1445 if (ethertype_rule->hash_table)
1446 rte_hash_free(ethertype_rule->hash_table);
1448 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1449 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1450 p_ethertype, rules);
1451 rte_free(p_ethertype);
1456 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1458 struct i40e_tunnel_filter *p_tunnel;
1459 struct i40e_tunnel_rule *tunnel_rule;
1461 tunnel_rule = &pf->tunnel;
1462 /* Remove all tunnel director rules and hash */
1463 if (tunnel_rule->hash_map)
1464 rte_free(tunnel_rule->hash_map);
1465 if (tunnel_rule->hash_table)
1466 rte_hash_free(tunnel_rule->hash_table);
1468 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1469 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1475 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1477 struct i40e_fdir_filter *p_fdir;
1478 struct i40e_fdir_info *fdir_info;
1480 fdir_info = &pf->fdir;
1481 /* Remove all flow director rules and hash */
1482 if (fdir_info->hash_map)
1483 rte_free(fdir_info->hash_map);
1484 if (fdir_info->hash_table)
1485 rte_hash_free(fdir_info->hash_table);
1487 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1488 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1493 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1496 * Disable by default flexible payload
1497 * for corresponding L2/L3/L4 layers.
1499 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1500 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1501 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1502 i40e_global_cfg_warning(I40E_WARNING_DIS_FLX_PLD);
1506 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1509 struct rte_pci_device *pci_dev;
1510 struct rte_intr_handle *intr_handle;
1512 struct i40e_filter_control_settings settings;
1513 struct rte_flow *p_flow;
1515 uint8_t aq_fail = 0;
1518 PMD_INIT_FUNC_TRACE();
1520 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1523 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1524 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1525 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1526 intr_handle = &pci_dev->intr_handle;
1528 if (hw->adapter_stopped == 0)
1529 i40e_dev_close(dev);
1531 dev->dev_ops = NULL;
1532 dev->rx_pkt_burst = NULL;
1533 dev->tx_pkt_burst = NULL;
1535 /* Clear PXE mode */
1536 i40e_clear_pxe_mode(hw);
1538 /* Unconfigure filter control */
1539 memset(&settings, 0, sizeof(settings));
1540 ret = i40e_set_filter_control(hw, &settings);
1542 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1545 /* Disable flow control */
1546 hw->fc.requested_mode = I40E_FC_NONE;
1547 i40e_set_fc(hw, &aq_fail, TRUE);
1549 /* uninitialize pf host driver */
1550 i40e_pf_host_uninit(dev);
1552 rte_free(dev->data->mac_addrs);
1553 dev->data->mac_addrs = NULL;
1555 /* disable uio intr before callback unregister */
1556 rte_intr_disable(intr_handle);
1558 /* unregister callback func to eal lib */
1560 ret = rte_intr_callback_unregister(intr_handle,
1561 i40e_dev_interrupt_handler, dev);
1564 } else if (ret != -EAGAIN) {
1566 "intr callback unregister failed: %d",
1570 i40e_msec_delay(500);
1571 } while (retries++ < 5);
1573 i40e_rm_ethtype_filter_list(pf);
1574 i40e_rm_tunnel_filter_list(pf);
1575 i40e_rm_fdir_filter_list(pf);
1577 /* Remove all flows */
1578 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1579 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1583 /* Remove all Traffic Manager configuration */
1584 i40e_tm_conf_uninit(dev);
1590 i40e_dev_configure(struct rte_eth_dev *dev)
1592 struct i40e_adapter *ad =
1593 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1594 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1595 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1596 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1599 ret = i40e_dev_sync_phy_type(hw);
1603 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1604 * bulk allocation or vector Rx preconditions we will reset it.
1606 ad->rx_bulk_alloc_allowed = true;
1607 ad->rx_vec_allowed = true;
1608 ad->tx_simple_allowed = true;
1609 ad->tx_vec_allowed = true;
1611 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1612 ret = i40e_fdir_setup(pf);
1613 if (ret != I40E_SUCCESS) {
1614 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1617 ret = i40e_fdir_configure(dev);
1619 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1623 i40e_fdir_teardown(pf);
1625 ret = i40e_dev_init_vlan(dev);
1630 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1631 * RSS setting have different requirements.
1632 * General PMD driver call sequence are NIC init, configure,
1633 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1634 * will try to lookup the VSI that specific queue belongs to if VMDQ
1635 * applicable. So, VMDQ setting has to be done before
1636 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1637 * For RSS setting, it will try to calculate actual configured RX queue
1638 * number, which will be available after rx_queue_setup(). dev_start()
1639 * function is good to place RSS setup.
1641 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1642 ret = i40e_vmdq_setup(dev);
1647 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1648 ret = i40e_dcb_setup(dev);
1650 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1655 TAILQ_INIT(&pf->flow_list);
1660 /* need to release vmdq resource if exists */
1661 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1662 i40e_vsi_release(pf->vmdq[i].vsi);
1663 pf->vmdq[i].vsi = NULL;
1668 /* need to release fdir resource if exists */
1669 i40e_fdir_teardown(pf);
1674 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1676 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1677 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1678 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1679 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1680 uint16_t msix_vect = vsi->msix_intr;
1683 for (i = 0; i < vsi->nb_qps; i++) {
1684 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1685 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1689 if (vsi->type != I40E_VSI_SRIOV) {
1690 if (!rte_intr_allow_others(intr_handle)) {
1691 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1692 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1694 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1697 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1698 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1700 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1705 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1706 vsi->user_param + (msix_vect - 1);
1708 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1709 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1711 I40E_WRITE_FLUSH(hw);
1715 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1716 int base_queue, int nb_queue,
1721 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1722 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1724 /* Bind all RX queues to allocated MSIX interrupt */
1725 for (i = 0; i < nb_queue; i++) {
1726 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1727 itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1728 ((base_queue + i + 1) <<
1729 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1730 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1731 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1733 if (i == nb_queue - 1)
1734 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1735 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1738 /* Write first RX queue to Link list register as the head element */
1739 if (vsi->type != I40E_VSI_SRIOV) {
1741 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL, 1,
1742 pf->support_multi_driver);
1744 if (msix_vect == I40E_MISC_VEC_ID) {
1745 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1747 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1749 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1751 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1754 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1756 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1758 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1760 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1767 if (msix_vect == I40E_MISC_VEC_ID) {
1769 I40E_VPINT_LNKLST0(vsi->user_param),
1771 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1773 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1775 /* num_msix_vectors_vf needs to minus irq0 */
1776 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1777 vsi->user_param + (msix_vect - 1);
1779 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1781 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1783 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1787 I40E_WRITE_FLUSH(hw);
1791 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1793 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1794 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1795 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1796 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1797 uint16_t msix_vect = vsi->msix_intr;
1798 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1799 uint16_t queue_idx = 0;
1803 for (i = 0; i < vsi->nb_qps; i++) {
1804 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1805 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1808 /* VF bind interrupt */
1809 if (vsi->type == I40E_VSI_SRIOV) {
1810 __vsi_queues_bind_intr(vsi, msix_vect,
1811 vsi->base_queue, vsi->nb_qps,
1816 /* PF & VMDq bind interrupt */
1817 if (rte_intr_dp_is_en(intr_handle)) {
1818 if (vsi->type == I40E_VSI_MAIN) {
1821 } else if (vsi->type == I40E_VSI_VMDQ2) {
1822 struct i40e_vsi *main_vsi =
1823 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1824 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1829 for (i = 0; i < vsi->nb_used_qps; i++) {
1831 if (!rte_intr_allow_others(intr_handle))
1832 /* allow to share MISC_VEC_ID */
1833 msix_vect = I40E_MISC_VEC_ID;
1835 /* no enough msix_vect, map all to one */
1836 __vsi_queues_bind_intr(vsi, msix_vect,
1837 vsi->base_queue + i,
1838 vsi->nb_used_qps - i,
1840 for (; !!record && i < vsi->nb_used_qps; i++)
1841 intr_handle->intr_vec[queue_idx + i] =
1845 /* 1:1 queue/msix_vect mapping */
1846 __vsi_queues_bind_intr(vsi, msix_vect,
1847 vsi->base_queue + i, 1,
1850 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1858 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1860 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1861 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1862 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1863 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1864 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1865 uint16_t msix_intr, i;
1867 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
1868 for (i = 0; i < vsi->nb_msix; i++) {
1869 msix_intr = vsi->msix_intr + i;
1870 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1871 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1872 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1873 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
1876 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1877 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1878 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1879 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
1881 I40E_WRITE_FLUSH(hw);
1885 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1887 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1888 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1889 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1890 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1891 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1892 uint16_t msix_intr, i;
1894 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
1895 for (i = 0; i < vsi->nb_msix; i++) {
1896 msix_intr = vsi->msix_intr + i;
1897 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1898 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
1901 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1902 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
1904 I40E_WRITE_FLUSH(hw);
1907 static inline uint8_t
1908 i40e_parse_link_speeds(uint16_t link_speeds)
1910 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1912 if (link_speeds & ETH_LINK_SPEED_40G)
1913 link_speed |= I40E_LINK_SPEED_40GB;
1914 if (link_speeds & ETH_LINK_SPEED_25G)
1915 link_speed |= I40E_LINK_SPEED_25GB;
1916 if (link_speeds & ETH_LINK_SPEED_20G)
1917 link_speed |= I40E_LINK_SPEED_20GB;
1918 if (link_speeds & ETH_LINK_SPEED_10G)
1919 link_speed |= I40E_LINK_SPEED_10GB;
1920 if (link_speeds & ETH_LINK_SPEED_1G)
1921 link_speed |= I40E_LINK_SPEED_1GB;
1922 if (link_speeds & ETH_LINK_SPEED_100M)
1923 link_speed |= I40E_LINK_SPEED_100MB;
1929 i40e_phy_conf_link(struct i40e_hw *hw,
1931 uint8_t force_speed,
1934 enum i40e_status_code status;
1935 struct i40e_aq_get_phy_abilities_resp phy_ab;
1936 struct i40e_aq_set_phy_config phy_conf;
1937 enum i40e_aq_phy_type cnt;
1938 uint32_t phy_type_mask = 0;
1940 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1941 I40E_AQ_PHY_FLAG_PAUSE_RX |
1942 I40E_AQ_PHY_FLAG_PAUSE_RX |
1943 I40E_AQ_PHY_FLAG_LOW_POWER;
1944 const uint8_t advt = I40E_LINK_SPEED_40GB |
1945 I40E_LINK_SPEED_25GB |
1946 I40E_LINK_SPEED_10GB |
1947 I40E_LINK_SPEED_1GB |
1948 I40E_LINK_SPEED_100MB;
1952 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1957 /* If link already up, no need to set up again */
1958 if (is_up && phy_ab.phy_type != 0)
1959 return I40E_SUCCESS;
1961 memset(&phy_conf, 0, sizeof(phy_conf));
1963 /* bits 0-2 use the values from get_phy_abilities_resp */
1965 abilities |= phy_ab.abilities & mask;
1967 /* update ablities and speed */
1968 if (abilities & I40E_AQ_PHY_AN_ENABLED)
1969 phy_conf.link_speed = advt;
1971 phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed;
1973 phy_conf.abilities = abilities;
1977 /* To enable link, phy_type mask needs to include each type */
1978 for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_MAX; cnt++)
1979 phy_type_mask |= 1 << cnt;
1981 /* use get_phy_abilities_resp value for the rest */
1982 phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
1983 phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
1984 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
1985 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
1986 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1987 phy_conf.eee_capability = phy_ab.eee_capability;
1988 phy_conf.eeer = phy_ab.eeer_val;
1989 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1991 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1992 phy_ab.abilities, phy_ab.link_speed);
1993 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
1994 phy_conf.abilities, phy_conf.link_speed);
1996 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2000 return I40E_SUCCESS;
2004 i40e_apply_link_speed(struct rte_eth_dev *dev)
2007 uint8_t abilities = 0;
2008 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2009 struct rte_eth_conf *conf = &dev->data->dev_conf;
2011 speed = i40e_parse_link_speeds(conf->link_speeds);
2012 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2013 if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
2014 abilities |= I40E_AQ_PHY_AN_ENABLED;
2015 abilities |= I40E_AQ_PHY_LINK_ENABLED;
2017 return i40e_phy_conf_link(hw, abilities, speed, true);
2021 i40e_dev_start(struct rte_eth_dev *dev)
2023 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2024 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2025 struct i40e_vsi *main_vsi = pf->main_vsi;
2027 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2028 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2029 uint32_t intr_vector = 0;
2030 struct i40e_vsi *vsi;
2032 hw->adapter_stopped = 0;
2034 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2036 "Invalid link_speeds for port %u, autonegotiation disabled",
2037 dev->data->port_id);
2041 rte_intr_disable(intr_handle);
2043 if ((rte_intr_cap_multiple(intr_handle) ||
2044 !RTE_ETH_DEV_SRIOV(dev).active) &&
2045 dev->data->dev_conf.intr_conf.rxq != 0) {
2046 intr_vector = dev->data->nb_rx_queues;
2047 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2052 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2053 intr_handle->intr_vec =
2054 rte_zmalloc("intr_vec",
2055 dev->data->nb_rx_queues * sizeof(int),
2057 if (!intr_handle->intr_vec) {
2059 "Failed to allocate %d rx_queues intr_vec",
2060 dev->data->nb_rx_queues);
2065 /* Initialize VSI */
2066 ret = i40e_dev_rxtx_init(pf);
2067 if (ret != I40E_SUCCESS) {
2068 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2072 /* Map queues with MSIX interrupt */
2073 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2074 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2075 i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2076 i40e_vsi_enable_queues_intr(main_vsi);
2078 /* Map VMDQ VSI queues with MSIX interrupt */
2079 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2080 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2081 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2082 I40E_ITR_INDEX_DEFAULT);
2083 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2086 /* enable FDIR MSIX interrupt */
2087 if (pf->fdir.fdir_vsi) {
2088 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2089 I40E_ITR_INDEX_NONE);
2090 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2093 /* Enable all queues which have been configured */
2094 ret = i40e_dev_switch_queues(pf, TRUE);
2095 if (ret != I40E_SUCCESS) {
2096 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2100 /* Enable receiving broadcast packets */
2101 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2102 if (ret != I40E_SUCCESS)
2103 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2105 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2106 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2108 if (ret != I40E_SUCCESS)
2109 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2112 /* Enable the VLAN promiscuous mode. */
2114 for (i = 0; i < pf->vf_num; i++) {
2115 vsi = pf->vfs[i].vsi;
2116 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2121 /* Enable mac loopback mode */
2122 if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2123 dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2124 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2125 if (ret != I40E_SUCCESS) {
2126 PMD_DRV_LOG(ERR, "fail to set loopback link");
2131 /* Apply link configure */
2132 if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
2133 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
2134 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
2135 ETH_LINK_SPEED_40G)) {
2136 PMD_DRV_LOG(ERR, "Invalid link setting");
2139 ret = i40e_apply_link_speed(dev);
2140 if (I40E_SUCCESS != ret) {
2141 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2145 if (!rte_intr_allow_others(intr_handle)) {
2146 rte_intr_callback_unregister(intr_handle,
2147 i40e_dev_interrupt_handler,
2149 /* configure and enable device interrupt */
2150 i40e_pf_config_irq0(hw, FALSE);
2151 i40e_pf_enable_irq0(hw);
2153 if (dev->data->dev_conf.intr_conf.lsc != 0)
2155 "lsc won't enable because of no intr multiplex");
2157 ret = i40e_aq_set_phy_int_mask(hw,
2158 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2159 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2160 I40E_AQ_EVENT_MEDIA_NA), NULL);
2161 if (ret != I40E_SUCCESS)
2162 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2164 /* Call get_link_info aq commond to enable/disable LSE */
2165 i40e_dev_link_update(dev, 0);
2168 /* enable uio intr after callback register */
2169 rte_intr_enable(intr_handle);
2171 i40e_filter_restore(pf);
2173 if (pf->tm_conf.root && !pf->tm_conf.committed)
2174 PMD_DRV_LOG(WARNING,
2175 "please call hierarchy_commit() "
2176 "before starting the port");
2178 return I40E_SUCCESS;
2181 i40e_dev_switch_queues(pf, FALSE);
2182 i40e_dev_clear_queues(dev);
2188 i40e_dev_stop(struct rte_eth_dev *dev)
2190 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2191 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2192 struct i40e_vsi *main_vsi = pf->main_vsi;
2193 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2194 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2197 if (hw->adapter_stopped == 1)
2199 /* Disable all queues */
2200 i40e_dev_switch_queues(pf, FALSE);
2202 /* un-map queues with interrupt registers */
2203 i40e_vsi_disable_queues_intr(main_vsi);
2204 i40e_vsi_queues_unbind_intr(main_vsi);
2206 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2207 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2208 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2211 if (pf->fdir.fdir_vsi) {
2212 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2213 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2215 /* Clear all queues and release memory */
2216 i40e_dev_clear_queues(dev);
2219 i40e_dev_set_link_down(dev);
2221 if (!rte_intr_allow_others(intr_handle))
2222 /* resume to the default handler */
2223 rte_intr_callback_register(intr_handle,
2224 i40e_dev_interrupt_handler,
2227 /* Clean datapath event and queue/vec mapping */
2228 rte_intr_efd_disable(intr_handle);
2229 if (intr_handle->intr_vec) {
2230 rte_free(intr_handle->intr_vec);
2231 intr_handle->intr_vec = NULL;
2234 /* reset hierarchy commit */
2235 pf->tm_conf.committed = false;
2237 hw->adapter_stopped = 1;
2241 i40e_dev_close(struct rte_eth_dev *dev)
2243 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2244 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2245 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2246 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2247 struct i40e_mirror_rule *p_mirror;
2252 PMD_INIT_FUNC_TRACE();
2256 /* Remove all mirror rules */
2257 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2258 ret = i40e_aq_del_mirror_rule(hw,
2259 pf->main_vsi->veb->seid,
2260 p_mirror->rule_type,
2262 p_mirror->num_entries,
2265 PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2266 "status = %d, aq_err = %d.", ret,
2267 hw->aq.asq_last_status);
2269 /* remove mirror software resource anyway */
2270 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2272 pf->nb_mirror_rule--;
2275 i40e_dev_free_queues(dev);
2277 /* Disable interrupt */
2278 i40e_pf_disable_irq0(hw);
2279 rte_intr_disable(intr_handle);
2281 /* shutdown and destroy the HMC */
2282 i40e_shutdown_lan_hmc(hw);
2284 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2285 i40e_vsi_release(pf->vmdq[i].vsi);
2286 pf->vmdq[i].vsi = NULL;
2291 /* release all the existing VSIs and VEBs */
2292 i40e_fdir_teardown(pf);
2293 i40e_vsi_release(pf->main_vsi);
2295 /* shutdown the adminq */
2296 i40e_aq_queue_shutdown(hw, true);
2297 i40e_shutdown_adminq(hw);
2299 i40e_res_pool_destroy(&pf->qp_pool);
2300 i40e_res_pool_destroy(&pf->msix_pool);
2302 /* Disable flexible payload in global configuration */
2303 if (!pf->support_multi_driver)
2304 i40e_flex_payload_reg_set_default(hw);
2306 /* force a PF reset to clean anything leftover */
2307 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2308 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2309 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2310 I40E_WRITE_FLUSH(hw);
2314 * Reset PF device only to re-initialize resources in PMD layer
2317 i40e_dev_reset(struct rte_eth_dev *dev)
2321 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2322 * its VF to make them align with it. The detailed notification
2323 * mechanism is PMD specific. As to i40e PF, it is rather complex.
2324 * To avoid unexpected behavior in VF, currently reset of PF with
2325 * SR-IOV activation is not supported. It might be supported later.
2327 if (dev->data->sriov.active)
2330 ret = eth_i40e_dev_uninit(dev);
2334 ret = eth_i40e_dev_init(dev);
2340 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2342 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2343 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2344 struct i40e_vsi *vsi = pf->main_vsi;
2347 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2349 if (status != I40E_SUCCESS)
2350 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2352 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2354 if (status != I40E_SUCCESS)
2355 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2360 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2362 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2363 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2364 struct i40e_vsi *vsi = pf->main_vsi;
2367 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2369 if (status != I40E_SUCCESS)
2370 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2372 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2374 if (status != I40E_SUCCESS)
2375 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2379 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2381 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2382 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2383 struct i40e_vsi *vsi = pf->main_vsi;
2386 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2387 if (ret != I40E_SUCCESS)
2388 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2392 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2394 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2395 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2396 struct i40e_vsi *vsi = pf->main_vsi;
2399 if (dev->data->promiscuous == 1)
2400 return; /* must remain in all_multicast mode */
2402 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2403 vsi->seid, FALSE, NULL);
2404 if (ret != I40E_SUCCESS)
2405 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2409 * Set device link up.
2412 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2414 /* re-apply link speed setting */
2415 return i40e_apply_link_speed(dev);
2419 * Set device link down.
2422 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2424 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2425 uint8_t abilities = 0;
2426 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2428 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2429 return i40e_phy_conf_link(hw, abilities, speed, false);
2432 static __rte_always_inline void
2433 update_link_no_wait(struct i40e_hw *hw, struct rte_eth_link *link)
2435 /* Link status registers and values*/
2436 #define I40E_PRTMAC_LINKSTA 0x001E2420
2437 #define I40E_REG_LINK_UP 0x40000080
2438 #define I40E_PRTMAC_MACC 0x001E24E0
2439 #define I40E_REG_MACC_25GB 0x00020000
2440 #define I40E_REG_SPEED_MASK 0x38000000
2441 #define I40E_REG_SPEED_100MB 0x00000000
2442 #define I40E_REG_SPEED_1GB 0x08000000
2443 #define I40E_REG_SPEED_10GB 0x10000000
2444 #define I40E_REG_SPEED_20GB 0x20000000
2445 #define I40E_REG_SPEED_25_40GB 0x18000000
2446 uint32_t link_speed;
2449 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2450 link_speed = reg_val & I40E_REG_SPEED_MASK;
2451 reg_val &= I40E_REG_LINK_UP;
2452 link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2454 if (unlikely(link->link_status != 0))
2457 /* Parse the link status */
2458 switch (link_speed) {
2459 case I40E_REG_SPEED_100MB:
2460 link->link_speed = ETH_SPEED_NUM_100M;
2462 case I40E_REG_SPEED_1GB:
2463 link->link_speed = ETH_SPEED_NUM_1G;
2465 case I40E_REG_SPEED_10GB:
2466 link->link_speed = ETH_SPEED_NUM_10G;
2468 case I40E_REG_SPEED_20GB:
2469 link->link_speed = ETH_SPEED_NUM_20G;
2471 case I40E_REG_SPEED_25_40GB:
2472 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2474 if (reg_val & I40E_REG_MACC_25GB)
2475 link->link_speed = ETH_SPEED_NUM_25G;
2477 link->link_speed = ETH_SPEED_NUM_40G;
2481 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2486 static __rte_always_inline void
2487 update_link_wait(struct i40e_hw *hw, struct rte_eth_link *link,
2490 #define CHECK_INTERVAL 100 /* 100ms */
2491 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2492 uint32_t rep_cnt = MAX_REPEAT_TIME;
2493 struct i40e_link_status link_status;
2496 memset(&link_status, 0, sizeof(link_status));
2499 memset(&link_status, 0, sizeof(link_status));
2501 /* Get link status information from hardware */
2502 status = i40e_aq_get_link_info(hw, enable_lse,
2503 &link_status, NULL);
2504 if (unlikely(status != I40E_SUCCESS)) {
2505 link->link_speed = ETH_SPEED_NUM_100M;
2506 link->link_duplex = ETH_LINK_FULL_DUPLEX;
2507 PMD_DRV_LOG(ERR, "Failed to get link info");
2511 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2512 if (unlikely(link->link_status != 0))
2515 rte_delay_ms(CHECK_INTERVAL);
2516 } while (--rep_cnt);
2518 /* Parse the link status */
2519 switch (link_status.link_speed) {
2520 case I40E_LINK_SPEED_100MB:
2521 link->link_speed = ETH_SPEED_NUM_100M;
2523 case I40E_LINK_SPEED_1GB:
2524 link->link_speed = ETH_SPEED_NUM_1G;
2526 case I40E_LINK_SPEED_10GB:
2527 link->link_speed = ETH_SPEED_NUM_10G;
2529 case I40E_LINK_SPEED_20GB:
2530 link->link_speed = ETH_SPEED_NUM_20G;
2532 case I40E_LINK_SPEED_25GB:
2533 link->link_speed = ETH_SPEED_NUM_25G;
2535 case I40E_LINK_SPEED_40GB:
2536 link->link_speed = ETH_SPEED_NUM_40G;
2539 link->link_speed = ETH_SPEED_NUM_100M;
2545 i40e_dev_link_update(struct rte_eth_dev *dev,
2546 int wait_to_complete)
2548 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2549 struct rte_eth_link link;
2550 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2553 memset(&link, 0, sizeof(link));
2555 /* i40e uses full duplex only */
2556 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2557 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2558 ETH_LINK_SPEED_FIXED);
2560 if (!wait_to_complete)
2561 update_link_no_wait(hw, &link);
2563 update_link_wait(hw, &link, enable_lse);
2565 ret = rte_eth_linkstatus_set(dev, &link);
2566 i40e_notify_all_vfs_link_status(dev);
2571 /* Get all the statistics of a VSI */
2573 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2575 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2576 struct i40e_eth_stats *nes = &vsi->eth_stats;
2577 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2578 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2580 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2581 vsi->offset_loaded, &oes->rx_bytes,
2583 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2584 vsi->offset_loaded, &oes->rx_unicast,
2586 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2587 vsi->offset_loaded, &oes->rx_multicast,
2588 &nes->rx_multicast);
2589 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2590 vsi->offset_loaded, &oes->rx_broadcast,
2591 &nes->rx_broadcast);
2592 /* exclude CRC bytes */
2593 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2594 nes->rx_broadcast) * ETHER_CRC_LEN;
2596 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2597 &oes->rx_discards, &nes->rx_discards);
2598 /* GLV_REPC not supported */
2599 /* GLV_RMPC not supported */
2600 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2601 &oes->rx_unknown_protocol,
2602 &nes->rx_unknown_protocol);
2603 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2604 vsi->offset_loaded, &oes->tx_bytes,
2606 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2607 vsi->offset_loaded, &oes->tx_unicast,
2609 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2610 vsi->offset_loaded, &oes->tx_multicast,
2611 &nes->tx_multicast);
2612 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2613 vsi->offset_loaded, &oes->tx_broadcast,
2614 &nes->tx_broadcast);
2615 /* GLV_TDPC not supported */
2616 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2617 &oes->tx_errors, &nes->tx_errors);
2618 vsi->offset_loaded = true;
2620 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2622 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2623 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2624 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2625 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2626 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2627 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2628 nes->rx_unknown_protocol);
2629 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2630 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2631 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2632 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2633 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2634 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2635 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2640 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2643 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2644 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2646 /* Get rx/tx bytes of internal transfer packets */
2647 i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2648 I40E_GLV_GORCL(hw->port),
2650 &pf->internal_stats_offset.rx_bytes,
2651 &pf->internal_stats.rx_bytes);
2653 i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2654 I40E_GLV_GOTCL(hw->port),
2656 &pf->internal_stats_offset.tx_bytes,
2657 &pf->internal_stats.tx_bytes);
2658 /* Get total internal rx packet count */
2659 i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2660 I40E_GLV_UPRCL(hw->port),
2662 &pf->internal_stats_offset.rx_unicast,
2663 &pf->internal_stats.rx_unicast);
2664 i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2665 I40E_GLV_MPRCL(hw->port),
2667 &pf->internal_stats_offset.rx_multicast,
2668 &pf->internal_stats.rx_multicast);
2669 i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2670 I40E_GLV_BPRCL(hw->port),
2672 &pf->internal_stats_offset.rx_broadcast,
2673 &pf->internal_stats.rx_broadcast);
2674 /* Get total internal tx packet count */
2675 i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
2676 I40E_GLV_UPTCL(hw->port),
2678 &pf->internal_stats_offset.tx_unicast,
2679 &pf->internal_stats.tx_unicast);
2680 i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
2681 I40E_GLV_MPTCL(hw->port),
2683 &pf->internal_stats_offset.tx_multicast,
2684 &pf->internal_stats.tx_multicast);
2685 i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
2686 I40E_GLV_BPTCL(hw->port),
2688 &pf->internal_stats_offset.tx_broadcast,
2689 &pf->internal_stats.tx_broadcast);
2691 /* exclude CRC size */
2692 pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2693 pf->internal_stats.rx_multicast +
2694 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2696 /* Get statistics of struct i40e_eth_stats */
2697 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2698 I40E_GLPRT_GORCL(hw->port),
2699 pf->offset_loaded, &os->eth.rx_bytes,
2701 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2702 I40E_GLPRT_UPRCL(hw->port),
2703 pf->offset_loaded, &os->eth.rx_unicast,
2704 &ns->eth.rx_unicast);
2705 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2706 I40E_GLPRT_MPRCL(hw->port),
2707 pf->offset_loaded, &os->eth.rx_multicast,
2708 &ns->eth.rx_multicast);
2709 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2710 I40E_GLPRT_BPRCL(hw->port),
2711 pf->offset_loaded, &os->eth.rx_broadcast,
2712 &ns->eth.rx_broadcast);
2713 /* Workaround: CRC size should not be included in byte statistics,
2714 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2716 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2717 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2719 /* exclude internal rx bytes
2720 * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2721 * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
2723 * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
2725 if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2726 ns->eth.rx_bytes = 0;
2728 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2730 if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
2731 ns->eth.rx_unicast = 0;
2733 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
2735 if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
2736 ns->eth.rx_multicast = 0;
2738 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
2740 if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
2741 ns->eth.rx_broadcast = 0;
2743 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
2745 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2746 pf->offset_loaded, &os->eth.rx_discards,
2747 &ns->eth.rx_discards);
2748 /* GLPRT_REPC not supported */
2749 /* GLPRT_RMPC not supported */
2750 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2752 &os->eth.rx_unknown_protocol,
2753 &ns->eth.rx_unknown_protocol);
2754 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2755 I40E_GLPRT_GOTCL(hw->port),
2756 pf->offset_loaded, &os->eth.tx_bytes,
2758 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2759 I40E_GLPRT_UPTCL(hw->port),
2760 pf->offset_loaded, &os->eth.tx_unicast,
2761 &ns->eth.tx_unicast);
2762 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2763 I40E_GLPRT_MPTCL(hw->port),
2764 pf->offset_loaded, &os->eth.tx_multicast,
2765 &ns->eth.tx_multicast);
2766 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2767 I40E_GLPRT_BPTCL(hw->port),
2768 pf->offset_loaded, &os->eth.tx_broadcast,
2769 &ns->eth.tx_broadcast);
2770 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2771 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2773 /* exclude internal tx bytes
2774 * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
2775 * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
2777 * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
2779 if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2780 ns->eth.tx_bytes = 0;
2782 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2784 if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
2785 ns->eth.tx_unicast = 0;
2787 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
2789 if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
2790 ns->eth.tx_multicast = 0;
2792 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
2794 if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
2795 ns->eth.tx_broadcast = 0;
2797 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
2799 /* GLPRT_TEPC not supported */
2801 /* additional port specific stats */
2802 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2803 pf->offset_loaded, &os->tx_dropped_link_down,
2804 &ns->tx_dropped_link_down);
2805 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2806 pf->offset_loaded, &os->crc_errors,
2808 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2809 pf->offset_loaded, &os->illegal_bytes,
2810 &ns->illegal_bytes);
2811 /* GLPRT_ERRBC not supported */
2812 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2813 pf->offset_loaded, &os->mac_local_faults,
2814 &ns->mac_local_faults);
2815 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2816 pf->offset_loaded, &os->mac_remote_faults,
2817 &ns->mac_remote_faults);
2818 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2819 pf->offset_loaded, &os->rx_length_errors,
2820 &ns->rx_length_errors);
2821 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2822 pf->offset_loaded, &os->link_xon_rx,
2824 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2825 pf->offset_loaded, &os->link_xoff_rx,
2827 for (i = 0; i < 8; i++) {
2828 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2830 &os->priority_xon_rx[i],
2831 &ns->priority_xon_rx[i]);
2832 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2834 &os->priority_xoff_rx[i],
2835 &ns->priority_xoff_rx[i]);
2837 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2838 pf->offset_loaded, &os->link_xon_tx,
2840 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2841 pf->offset_loaded, &os->link_xoff_tx,
2843 for (i = 0; i < 8; i++) {
2844 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2846 &os->priority_xon_tx[i],
2847 &ns->priority_xon_tx[i]);
2848 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2850 &os->priority_xoff_tx[i],
2851 &ns->priority_xoff_tx[i]);
2852 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2854 &os->priority_xon_2_xoff[i],
2855 &ns->priority_xon_2_xoff[i]);
2857 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2858 I40E_GLPRT_PRC64L(hw->port),
2859 pf->offset_loaded, &os->rx_size_64,
2861 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2862 I40E_GLPRT_PRC127L(hw->port),
2863 pf->offset_loaded, &os->rx_size_127,
2865 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2866 I40E_GLPRT_PRC255L(hw->port),
2867 pf->offset_loaded, &os->rx_size_255,
2869 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2870 I40E_GLPRT_PRC511L(hw->port),
2871 pf->offset_loaded, &os->rx_size_511,
2873 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2874 I40E_GLPRT_PRC1023L(hw->port),
2875 pf->offset_loaded, &os->rx_size_1023,
2877 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2878 I40E_GLPRT_PRC1522L(hw->port),
2879 pf->offset_loaded, &os->rx_size_1522,
2881 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2882 I40E_GLPRT_PRC9522L(hw->port),
2883 pf->offset_loaded, &os->rx_size_big,
2885 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2886 pf->offset_loaded, &os->rx_undersize,
2888 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2889 pf->offset_loaded, &os->rx_fragments,
2891 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2892 pf->offset_loaded, &os->rx_oversize,
2894 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2895 pf->offset_loaded, &os->rx_jabber,
2897 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2898 I40E_GLPRT_PTC64L(hw->port),
2899 pf->offset_loaded, &os->tx_size_64,
2901 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2902 I40E_GLPRT_PTC127L(hw->port),
2903 pf->offset_loaded, &os->tx_size_127,
2905 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2906 I40E_GLPRT_PTC255L(hw->port),
2907 pf->offset_loaded, &os->tx_size_255,
2909 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2910 I40E_GLPRT_PTC511L(hw->port),
2911 pf->offset_loaded, &os->tx_size_511,
2913 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2914 I40E_GLPRT_PTC1023L(hw->port),
2915 pf->offset_loaded, &os->tx_size_1023,
2917 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2918 I40E_GLPRT_PTC1522L(hw->port),
2919 pf->offset_loaded, &os->tx_size_1522,
2921 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2922 I40E_GLPRT_PTC9522L(hw->port),
2923 pf->offset_loaded, &os->tx_size_big,
2925 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2927 &os->fd_sb_match, &ns->fd_sb_match);
2928 /* GLPRT_MSPDC not supported */
2929 /* GLPRT_XEC not supported */
2931 pf->offset_loaded = true;
2934 i40e_update_vsi_stats(pf->main_vsi);
2937 /* Get all statistics of a port */
2939 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2941 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2942 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2943 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2946 /* call read registers - updates values, now write them to struct */
2947 i40e_read_stats_registers(pf, hw);
2949 stats->ipackets = ns->eth.rx_unicast +
2950 ns->eth.rx_multicast +
2951 ns->eth.rx_broadcast -
2952 ns->eth.rx_discards -
2953 pf->main_vsi->eth_stats.rx_discards;
2954 stats->opackets = ns->eth.tx_unicast +
2955 ns->eth.tx_multicast +
2956 ns->eth.tx_broadcast;
2957 stats->ibytes = ns->eth.rx_bytes;
2958 stats->obytes = ns->eth.tx_bytes;
2959 stats->oerrors = ns->eth.tx_errors +
2960 pf->main_vsi->eth_stats.tx_errors;
2963 stats->imissed = ns->eth.rx_discards +
2964 pf->main_vsi->eth_stats.rx_discards;
2965 stats->ierrors = ns->crc_errors +
2966 ns->rx_length_errors + ns->rx_undersize +
2967 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2969 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2970 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
2971 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
2972 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
2973 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
2974 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
2975 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2976 ns->eth.rx_unknown_protocol);
2977 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
2978 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
2979 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
2980 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
2981 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
2982 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
2984 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
2985 ns->tx_dropped_link_down);
2986 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
2987 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
2989 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
2990 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
2991 ns->mac_local_faults);
2992 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
2993 ns->mac_remote_faults);
2994 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
2995 ns->rx_length_errors);
2996 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
2997 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
2998 for (i = 0; i < 8; i++) {
2999 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
3000 i, ns->priority_xon_rx[i]);
3001 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
3002 i, ns->priority_xoff_rx[i]);
3004 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
3005 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
3006 for (i = 0; i < 8; i++) {
3007 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
3008 i, ns->priority_xon_tx[i]);
3009 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
3010 i, ns->priority_xoff_tx[i]);
3011 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
3012 i, ns->priority_xon_2_xoff[i]);
3014 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
3015 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
3016 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
3017 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
3018 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
3019 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
3020 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
3021 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
3022 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
3023 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
3024 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
3025 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
3026 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
3027 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
3028 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
3029 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
3030 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
3031 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
3032 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3033 ns->mac_short_packet_dropped);
3034 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
3035 ns->checksum_error);
3036 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
3037 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3041 /* Reset the statistics */
3043 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3045 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3046 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3048 /* Mark PF and VSI stats to update the offset, aka "reset" */
3049 pf->offset_loaded = false;
3051 pf->main_vsi->offset_loaded = false;
3053 /* read the stats, reading current register values into offset */
3054 i40e_read_stats_registers(pf, hw);
3058 i40e_xstats_calc_num(void)
3060 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3061 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3062 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3065 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3066 struct rte_eth_xstat_name *xstats_names,
3067 __rte_unused unsigned limit)
3072 if (xstats_names == NULL)
3073 return i40e_xstats_calc_num();
3075 /* Note: limit checked in rte_eth_xstats_names() */
3077 /* Get stats from i40e_eth_stats struct */
3078 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3079 snprintf(xstats_names[count].name,
3080 sizeof(xstats_names[count].name),
3081 "%s", rte_i40e_stats_strings[i].name);
3085 /* Get individiual stats from i40e_hw_port struct */
3086 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3087 snprintf(xstats_names[count].name,
3088 sizeof(xstats_names[count].name),
3089 "%s", rte_i40e_hw_port_strings[i].name);
3093 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3094 for (prio = 0; prio < 8; prio++) {
3095 snprintf(xstats_names[count].name,
3096 sizeof(xstats_names[count].name),
3097 "rx_priority%u_%s", prio,
3098 rte_i40e_rxq_prio_strings[i].name);
3103 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3104 for (prio = 0; prio < 8; prio++) {
3105 snprintf(xstats_names[count].name,
3106 sizeof(xstats_names[count].name),
3107 "tx_priority%u_%s", prio,
3108 rte_i40e_txq_prio_strings[i].name);
3116 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3119 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3120 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3121 unsigned i, count, prio;
3122 struct i40e_hw_port_stats *hw_stats = &pf->stats;
3124 count = i40e_xstats_calc_num();
3128 i40e_read_stats_registers(pf, hw);
3135 /* Get stats from i40e_eth_stats struct */
3136 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3137 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3138 rte_i40e_stats_strings[i].offset);
3139 xstats[count].id = count;
3143 /* Get individiual stats from i40e_hw_port struct */
3144 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3145 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3146 rte_i40e_hw_port_strings[i].offset);
3147 xstats[count].id = count;
3151 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3152 for (prio = 0; prio < 8; prio++) {
3153 xstats[count].value =
3154 *(uint64_t *)(((char *)hw_stats) +
3155 rte_i40e_rxq_prio_strings[i].offset +
3156 (sizeof(uint64_t) * prio));
3157 xstats[count].id = count;
3162 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3163 for (prio = 0; prio < 8; prio++) {
3164 xstats[count].value =
3165 *(uint64_t *)(((char *)hw_stats) +
3166 rte_i40e_txq_prio_strings[i].offset +
3167 (sizeof(uint64_t) * prio));
3168 xstats[count].id = count;
3177 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
3178 __rte_unused uint16_t queue_id,
3179 __rte_unused uint8_t stat_idx,
3180 __rte_unused uint8_t is_rx)
3182 PMD_INIT_FUNC_TRACE();
3188 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3190 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3196 full_ver = hw->nvm.oem_ver;
3197 ver = (u8)(full_ver >> 24);
3198 build = (u16)((full_ver >> 8) & 0xffff);
3199 patch = (u8)(full_ver & 0xff);
3201 ret = snprintf(fw_version, fw_size,
3202 "%d.%d%d 0x%08x %d.%d.%d",
3203 ((hw->nvm.version >> 12) & 0xf),
3204 ((hw->nvm.version >> 4) & 0xff),
3205 (hw->nvm.version & 0xf), hw->nvm.eetrack,
3208 ret += 1; /* add the size of '\0' */
3209 if (fw_size < (u32)ret)
3216 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3218 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3219 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3220 struct i40e_vsi *vsi = pf->main_vsi;
3221 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3223 dev_info->max_rx_queues = vsi->nb_qps;
3224 dev_info->max_tx_queues = vsi->nb_qps;
3225 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3226 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3227 dev_info->max_mac_addrs = vsi->max_macaddrs;
3228 dev_info->max_vfs = pci_dev->max_vfs;
3229 dev_info->rx_queue_offload_capa = 0;
3230 dev_info->rx_offload_capa =
3231 DEV_RX_OFFLOAD_VLAN_STRIP |
3232 DEV_RX_OFFLOAD_QINQ_STRIP |
3233 DEV_RX_OFFLOAD_IPV4_CKSUM |
3234 DEV_RX_OFFLOAD_UDP_CKSUM |
3235 DEV_RX_OFFLOAD_TCP_CKSUM |
3236 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3237 DEV_RX_OFFLOAD_CRC_STRIP |
3238 DEV_RX_OFFLOAD_VLAN_EXTEND |
3239 DEV_RX_OFFLOAD_VLAN_FILTER;
3241 dev_info->tx_queue_offload_capa = 0;
3242 dev_info->tx_offload_capa =
3243 DEV_TX_OFFLOAD_VLAN_INSERT |
3244 DEV_TX_OFFLOAD_QINQ_INSERT |
3245 DEV_TX_OFFLOAD_IPV4_CKSUM |
3246 DEV_TX_OFFLOAD_UDP_CKSUM |
3247 DEV_TX_OFFLOAD_TCP_CKSUM |
3248 DEV_TX_OFFLOAD_SCTP_CKSUM |
3249 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3250 DEV_TX_OFFLOAD_TCP_TSO |
3251 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3252 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3253 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3254 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
3255 dev_info->dev_capa =
3256 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3257 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3259 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3261 dev_info->reta_size = pf->hash_lut_size;
3262 dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3264 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3266 .pthresh = I40E_DEFAULT_RX_PTHRESH,
3267 .hthresh = I40E_DEFAULT_RX_HTHRESH,
3268 .wthresh = I40E_DEFAULT_RX_WTHRESH,
3270 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3275 dev_info->default_txconf = (struct rte_eth_txconf) {
3277 .pthresh = I40E_DEFAULT_TX_PTHRESH,
3278 .hthresh = I40E_DEFAULT_TX_HTHRESH,
3279 .wthresh = I40E_DEFAULT_TX_WTHRESH,
3281 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3282 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3283 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3284 ETH_TXQ_FLAGS_NOOFFLOADS,
3287 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3288 .nb_max = I40E_MAX_RING_DESC,
3289 .nb_min = I40E_MIN_RING_DESC,
3290 .nb_align = I40E_ALIGN_RING_DESC,
3293 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3294 .nb_max = I40E_MAX_RING_DESC,
3295 .nb_min = I40E_MIN_RING_DESC,
3296 .nb_align = I40E_ALIGN_RING_DESC,
3297 .nb_seg_max = I40E_TX_MAX_SEG,
3298 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3301 if (pf->flags & I40E_FLAG_VMDQ) {
3302 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3303 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3304 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3305 pf->max_nb_vmdq_vsi;
3306 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3307 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3308 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3311 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3313 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3314 dev_info->default_rxportconf.nb_queues = 2;
3315 dev_info->default_txportconf.nb_queues = 2;
3316 if (dev->data->nb_rx_queues == 1)
3317 dev_info->default_rxportconf.ring_size = 2048;
3319 dev_info->default_rxportconf.ring_size = 1024;
3320 if (dev->data->nb_tx_queues == 1)
3321 dev_info->default_txportconf.ring_size = 1024;
3323 dev_info->default_txportconf.ring_size = 512;
3325 } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3327 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3328 dev_info->default_rxportconf.nb_queues = 1;
3329 dev_info->default_txportconf.nb_queues = 1;
3330 dev_info->default_rxportconf.ring_size = 256;
3331 dev_info->default_txportconf.ring_size = 256;
3334 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3335 dev_info->default_rxportconf.nb_queues = 1;
3336 dev_info->default_txportconf.nb_queues = 1;
3337 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3338 dev_info->default_rxportconf.ring_size = 512;
3339 dev_info->default_txportconf.ring_size = 256;
3341 dev_info->default_rxportconf.ring_size = 256;
3342 dev_info->default_txportconf.ring_size = 256;
3345 dev_info->default_rxportconf.burst_size = 32;
3346 dev_info->default_txportconf.burst_size = 32;
3350 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3352 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3353 struct i40e_vsi *vsi = pf->main_vsi;
3354 PMD_INIT_FUNC_TRACE();
3357 return i40e_vsi_add_vlan(vsi, vlan_id);
3359 return i40e_vsi_delete_vlan(vsi, vlan_id);
3363 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3364 enum rte_vlan_type vlan_type,
3365 uint16_t tpid, int qinq)
3367 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3370 uint16_t reg_id = 3;
3374 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3378 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3380 if (ret != I40E_SUCCESS) {
3382 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3387 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3390 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3391 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3392 if (reg_r == reg_w) {
3393 PMD_DRV_LOG(DEBUG, "No need to write");
3397 ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3399 if (ret != I40E_SUCCESS) {
3401 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3406 "Global register 0x%08x is changed with value 0x%08x",
3407 I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3413 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3414 enum rte_vlan_type vlan_type,
3417 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3418 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3419 int qinq = dev->data->dev_conf.rxmode.offloads &
3420 DEV_RX_OFFLOAD_VLAN_EXTEND;
3423 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3424 vlan_type != ETH_VLAN_TYPE_OUTER) ||
3425 (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3427 "Unsupported vlan type.");
3431 if (pf->support_multi_driver) {
3432 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3436 /* 802.1ad frames ability is added in NVM API 1.7*/
3437 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3439 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3440 hw->first_tag = rte_cpu_to_le_16(tpid);
3441 else if (vlan_type == ETH_VLAN_TYPE_INNER)
3442 hw->second_tag = rte_cpu_to_le_16(tpid);
3444 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3445 hw->second_tag = rte_cpu_to_le_16(tpid);
3447 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3448 if (ret != I40E_SUCCESS) {
3450 "Set switch config failed aq_err: %d",
3451 hw->aq.asq_last_status);
3455 /* If NVM API < 1.7, keep the register setting */
3456 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3458 i40e_global_cfg_warning(I40E_WARNING_TPID);
3464 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3466 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3467 struct i40e_vsi *vsi = pf->main_vsi;
3468 struct rte_eth_rxmode *rxmode;
3470 rxmode = &dev->data->dev_conf.rxmode;
3471 if (mask & ETH_VLAN_FILTER_MASK) {
3472 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3473 i40e_vsi_config_vlan_filter(vsi, TRUE);
3475 i40e_vsi_config_vlan_filter(vsi, FALSE);
3478 if (mask & ETH_VLAN_STRIP_MASK) {
3479 /* Enable or disable VLAN stripping */
3480 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3481 i40e_vsi_config_vlan_stripping(vsi, TRUE);
3483 i40e_vsi_config_vlan_stripping(vsi, FALSE);
3486 if (mask & ETH_VLAN_EXTEND_MASK) {
3487 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
3488 i40e_vsi_config_double_vlan(vsi, TRUE);
3489 /* Set global registers with default ethertype. */
3490 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3492 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3496 i40e_vsi_config_double_vlan(vsi, FALSE);
3503 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3504 __rte_unused uint16_t queue,
3505 __rte_unused int on)
3507 PMD_INIT_FUNC_TRACE();
3511 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3513 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3514 struct i40e_vsi *vsi = pf->main_vsi;
3515 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3516 struct i40e_vsi_vlan_pvid_info info;
3518 memset(&info, 0, sizeof(info));
3521 info.config.pvid = pvid;
3523 info.config.reject.tagged =
3524 data->dev_conf.txmode.hw_vlan_reject_tagged;
3525 info.config.reject.untagged =
3526 data->dev_conf.txmode.hw_vlan_reject_untagged;
3529 return i40e_vsi_vlan_pvid_set(vsi, &info);
3533 i40e_dev_led_on(struct rte_eth_dev *dev)
3535 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3536 uint32_t mode = i40e_led_get(hw);
3539 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3545 i40e_dev_led_off(struct rte_eth_dev *dev)
3547 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3548 uint32_t mode = i40e_led_get(hw);
3551 i40e_led_set(hw, 0, false);
3557 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3559 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3560 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3562 fc_conf->pause_time = pf->fc_conf.pause_time;
3564 /* read out from register, in case they are modified by other port */
3565 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3566 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3567 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3568 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3570 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3571 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3573 /* Return current mode according to actual setting*/
3574 switch (hw->fc.current_mode) {
3576 fc_conf->mode = RTE_FC_FULL;
3578 case I40E_FC_TX_PAUSE:
3579 fc_conf->mode = RTE_FC_TX_PAUSE;
3581 case I40E_FC_RX_PAUSE:
3582 fc_conf->mode = RTE_FC_RX_PAUSE;
3586 fc_conf->mode = RTE_FC_NONE;
3593 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3595 uint32_t mflcn_reg, fctrl_reg, reg;
3596 uint32_t max_high_water;
3597 uint8_t i, aq_failure;
3601 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3602 [RTE_FC_NONE] = I40E_FC_NONE,
3603 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3604 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3605 [RTE_FC_FULL] = I40E_FC_FULL
3608 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3610 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3611 if ((fc_conf->high_water > max_high_water) ||
3612 (fc_conf->high_water < fc_conf->low_water)) {
3614 "Invalid high/low water setup value in KB, High_water must be <= %d.",
3619 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3620 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3621 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3623 pf->fc_conf.pause_time = fc_conf->pause_time;
3624 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3625 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3627 PMD_INIT_FUNC_TRACE();
3629 /* All the link flow control related enable/disable register
3630 * configuration is handle by the F/W
3632 err = i40e_set_fc(hw, &aq_failure, true);
3636 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3637 /* Configure flow control refresh threshold,
3638 * the value for stat_tx_pause_refresh_timer[8]
3639 * is used for global pause operation.
3643 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3644 pf->fc_conf.pause_time);
3646 /* configure the timer value included in transmitted pause
3648 * the value for stat_tx_pause_quanta[8] is used for global
3651 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3652 pf->fc_conf.pause_time);
3654 fctrl_reg = I40E_READ_REG(hw,
3655 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3657 if (fc_conf->mac_ctrl_frame_fwd != 0)
3658 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3660 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3662 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3665 /* Configure pause time (2 TCs per register) */
3666 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3667 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3668 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3670 /* Configure flow control refresh threshold value */
3671 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3672 pf->fc_conf.pause_time / 2);
3674 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3676 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3677 *depending on configuration
3679 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3680 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3681 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3683 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3684 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3687 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3690 if (!pf->support_multi_driver) {
3691 /* config water marker both based on the packets and bytes */
3692 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
3693 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3694 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3695 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
3696 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3697 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3698 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
3699 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3701 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
3702 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3704 i40e_global_cfg_warning(I40E_WARNING_FLOW_CTL);
3707 "Water marker configuration is not supported.");
3710 I40E_WRITE_FLUSH(hw);
3716 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3717 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3719 PMD_INIT_FUNC_TRACE();
3724 /* Add a MAC address, and update filters */
3726 i40e_macaddr_add(struct rte_eth_dev *dev,
3727 struct ether_addr *mac_addr,
3728 __rte_unused uint32_t index,
3731 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3732 struct i40e_mac_filter_info mac_filter;
3733 struct i40e_vsi *vsi;
3734 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
3737 /* If VMDQ not enabled or configured, return */
3738 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3739 !pf->nb_cfg_vmdq_vsi)) {
3740 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3741 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3746 if (pool > pf->nb_cfg_vmdq_vsi) {
3747 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3748 pool, pf->nb_cfg_vmdq_vsi);
3752 rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3753 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3754 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3756 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3761 vsi = pf->vmdq[pool - 1].vsi;
3763 ret = i40e_vsi_add_mac(vsi, &mac_filter);
3764 if (ret != I40E_SUCCESS) {
3765 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3771 /* Remove a MAC address, and update filters */
3773 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3775 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3776 struct i40e_vsi *vsi;
3777 struct rte_eth_dev_data *data = dev->data;
3778 struct ether_addr *macaddr;
3783 macaddr = &(data->mac_addrs[index]);
3785 pool_sel = dev->data->mac_pool_sel[index];
3787 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3788 if (pool_sel & (1ULL << i)) {
3792 /* No VMDQ pool enabled or configured */
3793 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3794 (i > pf->nb_cfg_vmdq_vsi)) {
3796 "No VMDQ pool enabled/configured");
3799 vsi = pf->vmdq[i - 1].vsi;
3801 ret = i40e_vsi_delete_mac(vsi, macaddr);
3804 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3811 /* Set perfect match or hash match of MAC and VLAN for a VF */
3813 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3814 struct rte_eth_mac_filter *filter,
3818 struct i40e_mac_filter_info mac_filter;
3819 struct ether_addr old_mac;
3820 struct ether_addr *new_mac;
3821 struct i40e_pf_vf *vf = NULL;
3826 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3829 hw = I40E_PF_TO_HW(pf);
3831 if (filter == NULL) {
3832 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3836 new_mac = &filter->mac_addr;
3838 if (is_zero_ether_addr(new_mac)) {
3839 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3843 vf_id = filter->dst_id;
3845 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3846 PMD_DRV_LOG(ERR, "Invalid argument.");
3849 vf = &pf->vfs[vf_id];
3851 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3852 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3857 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3858 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3860 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3863 mac_filter.filter_type = filter->filter_type;
3864 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3865 if (ret != I40E_SUCCESS) {
3866 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3869 ether_addr_copy(new_mac, &pf->dev_addr);
3871 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3873 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3874 if (ret != I40E_SUCCESS) {
3875 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3879 /* Clear device address as it has been removed */
3880 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3881 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3887 /* MAC filter handle */
3889 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3892 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3893 struct rte_eth_mac_filter *filter;
3894 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3895 int ret = I40E_NOT_SUPPORTED;
3897 filter = (struct rte_eth_mac_filter *)(arg);
3899 switch (filter_op) {
3900 case RTE_ETH_FILTER_NOP:
3903 case RTE_ETH_FILTER_ADD:
3904 i40e_pf_disable_irq0(hw);
3906 ret = i40e_vf_mac_filter_set(pf, filter, 1);
3907 i40e_pf_enable_irq0(hw);
3909 case RTE_ETH_FILTER_DELETE:
3910 i40e_pf_disable_irq0(hw);
3912 ret = i40e_vf_mac_filter_set(pf, filter, 0);
3913 i40e_pf_enable_irq0(hw);
3916 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3917 ret = I40E_ERR_PARAM;
3925 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3927 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3928 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3935 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3936 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3939 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3943 uint32_t *lut_dw = (uint32_t *)lut;
3944 uint16_t i, lut_size_dw = lut_size / 4;
3946 if (vsi->type == I40E_VSI_SRIOV) {
3947 for (i = 0; i <= lut_size_dw; i++) {
3948 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
3949 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
3952 for (i = 0; i < lut_size_dw; i++)
3953 lut_dw[i] = I40E_READ_REG(hw,
3962 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3971 pf = I40E_VSI_TO_PF(vsi);
3972 hw = I40E_VSI_TO_HW(vsi);
3974 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3975 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3978 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3982 uint32_t *lut_dw = (uint32_t *)lut;
3983 uint16_t i, lut_size_dw = lut_size / 4;
3985 if (vsi->type == I40E_VSI_SRIOV) {
3986 for (i = 0; i < lut_size_dw; i++)
3989 I40E_VFQF_HLUT1(i, vsi->user_param),
3992 for (i = 0; i < lut_size_dw; i++)
3993 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
3996 I40E_WRITE_FLUSH(hw);
4003 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4004 struct rte_eth_rss_reta_entry64 *reta_conf,
4007 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4008 uint16_t i, lut_size = pf->hash_lut_size;
4009 uint16_t idx, shift;
4013 if (reta_size != lut_size ||
4014 reta_size > ETH_RSS_RETA_SIZE_512) {
4016 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4017 reta_size, lut_size);
4021 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4023 PMD_DRV_LOG(ERR, "No memory can be allocated");
4026 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4029 for (i = 0; i < reta_size; i++) {
4030 idx = i / RTE_RETA_GROUP_SIZE;
4031 shift = i % RTE_RETA_GROUP_SIZE;
4032 if (reta_conf[idx].mask & (1ULL << shift))
4033 lut[i] = reta_conf[idx].reta[shift];
4035 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4044 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4045 struct rte_eth_rss_reta_entry64 *reta_conf,
4048 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4049 uint16_t i, lut_size = pf->hash_lut_size;
4050 uint16_t idx, shift;
4054 if (reta_size != lut_size ||
4055 reta_size > ETH_RSS_RETA_SIZE_512) {
4057 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4058 reta_size, lut_size);
4062 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4064 PMD_DRV_LOG(ERR, "No memory can be allocated");
4068 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4071 for (i = 0; i < reta_size; i++) {
4072 idx = i / RTE_RETA_GROUP_SIZE;
4073 shift = i % RTE_RETA_GROUP_SIZE;
4074 if (reta_conf[idx].mask & (1ULL << shift))
4075 reta_conf[idx].reta[shift] = lut[i];
4085 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4086 * @hw: pointer to the HW structure
4087 * @mem: pointer to mem struct to fill out
4088 * @size: size of memory requested
4089 * @alignment: what to align the allocation to
4091 enum i40e_status_code
4092 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4093 struct i40e_dma_mem *mem,
4097 const struct rte_memzone *mz = NULL;
4098 char z_name[RTE_MEMZONE_NAMESIZE];
4101 return I40E_ERR_PARAM;
4103 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4104 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4105 RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4107 return I40E_ERR_NO_MEMORY;
4112 mem->zone = (const void *)mz;
4114 "memzone %s allocated with physical address: %"PRIu64,
4117 return I40E_SUCCESS;
4121 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4122 * @hw: pointer to the HW structure
4123 * @mem: ptr to mem struct to free
4125 enum i40e_status_code
4126 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4127 struct i40e_dma_mem *mem)
4130 return I40E_ERR_PARAM;
4133 "memzone %s to be freed with physical address: %"PRIu64,
4134 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4135 rte_memzone_free((const struct rte_memzone *)mem->zone);
4140 return I40E_SUCCESS;
4144 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4145 * @hw: pointer to the HW structure
4146 * @mem: pointer to mem struct to fill out
4147 * @size: size of memory requested
4149 enum i40e_status_code
4150 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4151 struct i40e_virt_mem *mem,
4155 return I40E_ERR_PARAM;
4158 mem->va = rte_zmalloc("i40e", size, 0);
4161 return I40E_SUCCESS;
4163 return I40E_ERR_NO_MEMORY;
4167 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4168 * @hw: pointer to the HW structure
4169 * @mem: pointer to mem struct to free
4171 enum i40e_status_code
4172 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4173 struct i40e_virt_mem *mem)
4176 return I40E_ERR_PARAM;
4181 return I40E_SUCCESS;
4185 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4187 rte_spinlock_init(&sp->spinlock);
4191 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4193 rte_spinlock_lock(&sp->spinlock);
4197 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4199 rte_spinlock_unlock(&sp->spinlock);
4203 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4209 * Get the hardware capabilities, which will be parsed
4210 * and saved into struct i40e_hw.
4213 i40e_get_cap(struct i40e_hw *hw)
4215 struct i40e_aqc_list_capabilities_element_resp *buf;
4216 uint16_t len, size = 0;
4219 /* Calculate a huge enough buff for saving response data temporarily */
4220 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4221 I40E_MAX_CAP_ELE_NUM;
4222 buf = rte_zmalloc("i40e", len, 0);
4224 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4225 return I40E_ERR_NO_MEMORY;
4228 /* Get, parse the capabilities and save it to hw */
4229 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4230 i40e_aqc_opc_list_func_capabilities, NULL);
4231 if (ret != I40E_SUCCESS)
4232 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4234 /* Free the temporary buffer after being used */
4240 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4
4241 #define QUEUE_NUM_PER_VF_ARG "queue-num-per-vf"
4243 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4251 pf = (struct i40e_pf *)opaque;
4255 num = strtoul(value, &end, 0);
4256 if (errno != 0 || end == value || *end != 0) {
4257 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4258 "kept the value = %hu", value, pf->vf_nb_qp_max);
4262 if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4263 pf->vf_nb_qp_max = (uint16_t)num;
4265 /* here return 0 to make next valid same argument work */
4266 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4267 "power of 2 and equal or less than 16 !, Now it is "
4268 "kept the value = %hu", num, pf->vf_nb_qp_max);
4273 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4275 static const char * const valid_keys[] = {QUEUE_NUM_PER_VF_ARG, NULL};
4276 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4277 struct rte_kvargs *kvlist;
4279 /* set default queue number per VF as 4 */
4280 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4282 if (dev->device->devargs == NULL)
4285 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4289 if (rte_kvargs_count(kvlist, QUEUE_NUM_PER_VF_ARG) > 1)
4290 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4291 "the first invalid or last valid one is used !",
4292 QUEUE_NUM_PER_VF_ARG);
4294 rte_kvargs_process(kvlist, QUEUE_NUM_PER_VF_ARG,
4295 i40e_pf_parse_vf_queue_number_handler, pf);
4297 rte_kvargs_free(kvlist);
4303 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4305 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4306 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4307 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4308 uint16_t qp_count = 0, vsi_count = 0;
4310 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4311 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4315 i40e_pf_config_vf_rxq_number(dev);
4317 /* Add the parameter init for LFC */
4318 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4319 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4320 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4322 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4323 pf->max_num_vsi = hw->func_caps.num_vsis;
4324 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4325 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4327 /* FDir queue/VSI allocation */
4328 pf->fdir_qp_offset = 0;
4329 if (hw->func_caps.fd) {
4330 pf->flags |= I40E_FLAG_FDIR;
4331 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4333 pf->fdir_nb_qps = 0;
4335 qp_count += pf->fdir_nb_qps;
4338 /* LAN queue/VSI allocation */
4339 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4340 if (!hw->func_caps.rss) {
4343 pf->flags |= I40E_FLAG_RSS;
4344 if (hw->mac.type == I40E_MAC_X722)
4345 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4346 pf->lan_nb_qps = pf->lan_nb_qp_max;
4348 qp_count += pf->lan_nb_qps;
4351 /* VF queue/VSI allocation */
4352 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4353 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4354 pf->flags |= I40E_FLAG_SRIOV;
4355 pf->vf_nb_qps = pf->vf_nb_qp_max;
4356 pf->vf_num = pci_dev->max_vfs;
4358 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4359 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4364 qp_count += pf->vf_nb_qps * pf->vf_num;
4365 vsi_count += pf->vf_num;
4367 /* VMDq queue/VSI allocation */
4368 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4369 pf->vmdq_nb_qps = 0;
4370 pf->max_nb_vmdq_vsi = 0;
4371 if (hw->func_caps.vmdq) {
4372 if (qp_count < hw->func_caps.num_tx_qp &&
4373 vsi_count < hw->func_caps.num_vsis) {
4374 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4375 qp_count) / pf->vmdq_nb_qp_max;
4377 /* Limit the maximum number of VMDq vsi to the maximum
4378 * ethdev can support
4380 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4381 hw->func_caps.num_vsis - vsi_count);
4382 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4384 if (pf->max_nb_vmdq_vsi) {
4385 pf->flags |= I40E_FLAG_VMDQ;
4386 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4388 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4389 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4390 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4393 "No enough queues left for VMDq");
4396 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4399 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4400 vsi_count += pf->max_nb_vmdq_vsi;
4402 if (hw->func_caps.dcb)
4403 pf->flags |= I40E_FLAG_DCB;
4405 if (qp_count > hw->func_caps.num_tx_qp) {
4407 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4408 qp_count, hw->func_caps.num_tx_qp);
4411 if (vsi_count > hw->func_caps.num_vsis) {
4413 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4414 vsi_count, hw->func_caps.num_vsis);
4422 i40e_pf_get_switch_config(struct i40e_pf *pf)
4424 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4425 struct i40e_aqc_get_switch_config_resp *switch_config;
4426 struct i40e_aqc_switch_config_element_resp *element;
4427 uint16_t start_seid = 0, num_reported;
4430 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4431 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4432 if (!switch_config) {
4433 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4437 /* Get the switch configurations */
4438 ret = i40e_aq_get_switch_config(hw, switch_config,
4439 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4440 if (ret != I40E_SUCCESS) {
4441 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4444 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4445 if (num_reported != 1) { /* The number should be 1 */
4446 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4450 /* Parse the switch configuration elements */
4451 element = &(switch_config->element[0]);
4452 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4453 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4454 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4456 PMD_DRV_LOG(INFO, "Unknown element type");
4459 rte_free(switch_config);
4465 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4468 struct pool_entry *entry;
4470 if (pool == NULL || num == 0)
4473 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4474 if (entry == NULL) {
4475 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4479 /* queue heap initialize */
4480 pool->num_free = num;
4481 pool->num_alloc = 0;
4483 LIST_INIT(&pool->alloc_list);
4484 LIST_INIT(&pool->free_list);
4486 /* Initialize element */
4490 LIST_INSERT_HEAD(&pool->free_list, entry, next);
4495 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4497 struct pool_entry *entry, *next_entry;
4502 for (entry = LIST_FIRST(&pool->alloc_list);
4503 entry && (next_entry = LIST_NEXT(entry, next), 1);
4504 entry = next_entry) {
4505 LIST_REMOVE(entry, next);
4509 for (entry = LIST_FIRST(&pool->free_list);
4510 entry && (next_entry = LIST_NEXT(entry, next), 1);
4511 entry = next_entry) {
4512 LIST_REMOVE(entry, next);
4517 pool->num_alloc = 0;
4519 LIST_INIT(&pool->alloc_list);
4520 LIST_INIT(&pool->free_list);
4524 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4527 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4528 uint32_t pool_offset;
4532 PMD_DRV_LOG(ERR, "Invalid parameter");
4536 pool_offset = base - pool->base;
4537 /* Lookup in alloc list */
4538 LIST_FOREACH(entry, &pool->alloc_list, next) {
4539 if (entry->base == pool_offset) {
4540 valid_entry = entry;
4541 LIST_REMOVE(entry, next);
4546 /* Not find, return */
4547 if (valid_entry == NULL) {
4548 PMD_DRV_LOG(ERR, "Failed to find entry");
4553 * Found it, move it to free list and try to merge.
4554 * In order to make merge easier, always sort it by qbase.
4555 * Find adjacent prev and last entries.
4558 LIST_FOREACH(entry, &pool->free_list, next) {
4559 if (entry->base > valid_entry->base) {
4567 /* Try to merge with next one*/
4569 /* Merge with next one */
4570 if (valid_entry->base + valid_entry->len == next->base) {
4571 next->base = valid_entry->base;
4572 next->len += valid_entry->len;
4573 rte_free(valid_entry);
4580 /* Merge with previous one */
4581 if (prev->base + prev->len == valid_entry->base) {
4582 prev->len += valid_entry->len;
4583 /* If it merge with next one, remove next node */
4585 LIST_REMOVE(valid_entry, next);
4586 rte_free(valid_entry);
4588 rte_free(valid_entry);
4594 /* Not find any entry to merge, insert */
4597 LIST_INSERT_AFTER(prev, valid_entry, next);
4598 else if (next != NULL)
4599 LIST_INSERT_BEFORE(next, valid_entry, next);
4600 else /* It's empty list, insert to head */
4601 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4604 pool->num_free += valid_entry->len;
4605 pool->num_alloc -= valid_entry->len;
4611 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4614 struct pool_entry *entry, *valid_entry;
4616 if (pool == NULL || num == 0) {
4617 PMD_DRV_LOG(ERR, "Invalid parameter");
4621 if (pool->num_free < num) {
4622 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4623 num, pool->num_free);
4628 /* Lookup in free list and find most fit one */
4629 LIST_FOREACH(entry, &pool->free_list, next) {
4630 if (entry->len >= num) {
4632 if (entry->len == num) {
4633 valid_entry = entry;
4636 if (valid_entry == NULL || valid_entry->len > entry->len)
4637 valid_entry = entry;
4641 /* Not find one to satisfy the request, return */
4642 if (valid_entry == NULL) {
4643 PMD_DRV_LOG(ERR, "No valid entry found");
4647 * The entry have equal queue number as requested,
4648 * remove it from alloc_list.
4650 if (valid_entry->len == num) {
4651 LIST_REMOVE(valid_entry, next);
4654 * The entry have more numbers than requested,
4655 * create a new entry for alloc_list and minus its
4656 * queue base and number in free_list.
4658 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4659 if (entry == NULL) {
4661 "Failed to allocate memory for resource pool");
4664 entry->base = valid_entry->base;
4666 valid_entry->base += num;
4667 valid_entry->len -= num;
4668 valid_entry = entry;
4671 /* Insert it into alloc list, not sorted */
4672 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4674 pool->num_free -= valid_entry->len;
4675 pool->num_alloc += valid_entry->len;
4677 return valid_entry->base + pool->base;
4681 * bitmap_is_subset - Check whether src2 is subset of src1
4684 bitmap_is_subset(uint8_t src1, uint8_t src2)
4686 return !((src1 ^ src2) & src2);
4689 static enum i40e_status_code
4690 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4692 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4694 /* If DCB is not supported, only default TC is supported */
4695 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4696 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4697 return I40E_NOT_SUPPORTED;
4700 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4702 "Enabled TC map 0x%x not applicable to HW support 0x%x",
4703 hw->func_caps.enabled_tcmap, enabled_tcmap);
4704 return I40E_NOT_SUPPORTED;
4706 return I40E_SUCCESS;
4710 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4711 struct i40e_vsi_vlan_pvid_info *info)
4714 struct i40e_vsi_context ctxt;
4715 uint8_t vlan_flags = 0;
4718 if (vsi == NULL || info == NULL) {
4719 PMD_DRV_LOG(ERR, "invalid parameters");
4720 return I40E_ERR_PARAM;
4724 vsi->info.pvid = info->config.pvid;
4726 * If insert pvid is enabled, only tagged pkts are
4727 * allowed to be sent out.
4729 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4730 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4733 if (info->config.reject.tagged == 0)
4734 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4736 if (info->config.reject.untagged == 0)
4737 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4739 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4740 I40E_AQ_VSI_PVLAN_MODE_MASK);
4741 vsi->info.port_vlan_flags |= vlan_flags;
4742 vsi->info.valid_sections =
4743 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4744 memset(&ctxt, 0, sizeof(ctxt));
4745 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4746 ctxt.seid = vsi->seid;
4748 hw = I40E_VSI_TO_HW(vsi);
4749 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4750 if (ret != I40E_SUCCESS)
4751 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4757 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4759 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4761 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4763 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4764 if (ret != I40E_SUCCESS)
4768 PMD_DRV_LOG(ERR, "seid not valid");
4772 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4773 tc_bw_data.tc_valid_bits = enabled_tcmap;
4774 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4775 tc_bw_data.tc_bw_credits[i] =
4776 (enabled_tcmap & (1 << i)) ? 1 : 0;
4778 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4779 if (ret != I40E_SUCCESS) {
4780 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4784 rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4785 sizeof(vsi->info.qs_handle));
4786 return I40E_SUCCESS;
4789 static enum i40e_status_code
4790 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4791 struct i40e_aqc_vsi_properties_data *info,
4792 uint8_t enabled_tcmap)
4794 enum i40e_status_code ret;
4795 int i, total_tc = 0;
4796 uint16_t qpnum_per_tc, bsf, qp_idx;
4798 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4799 if (ret != I40E_SUCCESS)
4802 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4803 if (enabled_tcmap & (1 << i))
4807 vsi->enabled_tc = enabled_tcmap;
4809 /* Number of queues per enabled TC */
4810 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4811 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4812 bsf = rte_bsf32(qpnum_per_tc);
4814 /* Adjust the queue number to actual queues that can be applied */
4815 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4816 vsi->nb_qps = qpnum_per_tc * total_tc;
4819 * Configure TC and queue mapping parameters, for enabled TC,
4820 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4821 * default queue will serve it.
4824 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4825 if (vsi->enabled_tc & (1 << i)) {
4826 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4827 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4828 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4829 qp_idx += qpnum_per_tc;
4831 info->tc_mapping[i] = 0;
4834 /* Associate queue number with VSI */
4835 if (vsi->type == I40E_VSI_SRIOV) {
4836 info->mapping_flags |=
4837 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4838 for (i = 0; i < vsi->nb_qps; i++)
4839 info->queue_mapping[i] =
4840 rte_cpu_to_le_16(vsi->base_queue + i);
4842 info->mapping_flags |=
4843 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4844 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4846 info->valid_sections |=
4847 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4849 return I40E_SUCCESS;
4853 i40e_veb_release(struct i40e_veb *veb)
4855 struct i40e_vsi *vsi;
4861 if (!TAILQ_EMPTY(&veb->head)) {
4862 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4865 /* associate_vsi field is NULL for floating VEB */
4866 if (veb->associate_vsi != NULL) {
4867 vsi = veb->associate_vsi;
4868 hw = I40E_VSI_TO_HW(vsi);
4870 vsi->uplink_seid = veb->uplink_seid;
4873 veb->associate_pf->main_vsi->floating_veb = NULL;
4874 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4877 i40e_aq_delete_element(hw, veb->seid, NULL);
4879 return I40E_SUCCESS;
4883 static struct i40e_veb *
4884 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4886 struct i40e_veb *veb;
4892 "veb setup failed, associated PF shouldn't null");
4895 hw = I40E_PF_TO_HW(pf);
4897 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4899 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4903 veb->associate_vsi = vsi;
4904 veb->associate_pf = pf;
4905 TAILQ_INIT(&veb->head);
4906 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4908 /* create floating veb if vsi is NULL */
4910 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4911 I40E_DEFAULT_TCMAP, false,
4912 &veb->seid, false, NULL);
4914 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4915 true, &veb->seid, false, NULL);
4918 if (ret != I40E_SUCCESS) {
4919 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4920 hw->aq.asq_last_status);
4923 veb->enabled_tc = I40E_DEFAULT_TCMAP;
4925 /* get statistics index */
4926 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4927 &veb->stats_idx, NULL, NULL, NULL);
4928 if (ret != I40E_SUCCESS) {
4929 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4930 hw->aq.asq_last_status);
4933 /* Get VEB bandwidth, to be implemented */
4934 /* Now associated vsi binding to the VEB, set uplink to this VEB */
4936 vsi->uplink_seid = veb->seid;
4945 i40e_vsi_release(struct i40e_vsi *vsi)
4949 struct i40e_vsi_list *vsi_list;
4952 struct i40e_mac_filter *f;
4953 uint16_t user_param;
4956 return I40E_SUCCESS;
4961 user_param = vsi->user_param;
4963 pf = I40E_VSI_TO_PF(vsi);
4964 hw = I40E_VSI_TO_HW(vsi);
4966 /* VSI has child to attach, release child first */
4968 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4969 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4972 i40e_veb_release(vsi->veb);
4975 if (vsi->floating_veb) {
4976 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4977 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4982 /* Remove all macvlan filters of the VSI */
4983 i40e_vsi_remove_all_macvlan_filter(vsi);
4984 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4987 if (vsi->type != I40E_VSI_MAIN &&
4988 ((vsi->type != I40E_VSI_SRIOV) ||
4989 !pf->floating_veb_list[user_param])) {
4990 /* Remove vsi from parent's sibling list */
4991 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4992 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4993 return I40E_ERR_PARAM;
4995 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4996 &vsi->sib_vsi_list, list);
4998 /* Remove all switch element of the VSI */
4999 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5000 if (ret != I40E_SUCCESS)
5001 PMD_DRV_LOG(ERR, "Failed to delete element");
5004 if ((vsi->type == I40E_VSI_SRIOV) &&
5005 pf->floating_veb_list[user_param]) {
5006 /* Remove vsi from parent's sibling list */
5007 if (vsi->parent_vsi == NULL ||
5008 vsi->parent_vsi->floating_veb == NULL) {
5009 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5010 return I40E_ERR_PARAM;
5012 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5013 &vsi->sib_vsi_list, list);
5015 /* Remove all switch element of the VSI */
5016 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5017 if (ret != I40E_SUCCESS)
5018 PMD_DRV_LOG(ERR, "Failed to delete element");
5021 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5023 if (vsi->type != I40E_VSI_SRIOV)
5024 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5027 return I40E_SUCCESS;
5031 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5033 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5034 struct i40e_aqc_remove_macvlan_element_data def_filter;
5035 struct i40e_mac_filter_info filter;
5038 if (vsi->type != I40E_VSI_MAIN)
5039 return I40E_ERR_CONFIG;
5040 memset(&def_filter, 0, sizeof(def_filter));
5041 rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5043 def_filter.vlan_tag = 0;
5044 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5045 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5046 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5047 if (ret != I40E_SUCCESS) {
5048 struct i40e_mac_filter *f;
5049 struct ether_addr *mac;
5052 "Cannot remove the default macvlan filter");
5053 /* It needs to add the permanent mac into mac list */
5054 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5056 PMD_DRV_LOG(ERR, "failed to allocate memory");
5057 return I40E_ERR_NO_MEMORY;
5059 mac = &f->mac_info.mac_addr;
5060 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5062 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5063 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5068 rte_memcpy(&filter.mac_addr,
5069 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5070 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5071 return i40e_vsi_add_mac(vsi, &filter);
5075 * i40e_vsi_get_bw_config - Query VSI BW Information
5076 * @vsi: the VSI to be queried
5078 * Returns 0 on success, negative value on failure
5080 static enum i40e_status_code
5081 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5083 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5084 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5085 struct i40e_hw *hw = &vsi->adapter->hw;
5090 memset(&bw_config, 0, sizeof(bw_config));
5091 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5092 if (ret != I40E_SUCCESS) {
5093 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5094 hw->aq.asq_last_status);
5098 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5099 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5100 &ets_sla_config, NULL);
5101 if (ret != I40E_SUCCESS) {
5103 "VSI failed to get TC bandwdith configuration %u",
5104 hw->aq.asq_last_status);
5108 /* store and print out BW info */
5109 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5110 vsi->bw_info.bw_max = bw_config.max_bw;
5111 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5112 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5113 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5114 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5116 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5117 vsi->bw_info.bw_ets_share_credits[i] =
5118 ets_sla_config.share_credits[i];
5119 vsi->bw_info.bw_ets_credits[i] =
5120 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5121 /* 4 bits per TC, 4th bit is reserved */
5122 vsi->bw_info.bw_ets_max[i] =
5123 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5124 RTE_LEN2MASK(3, uint8_t));
5125 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5126 vsi->bw_info.bw_ets_share_credits[i]);
5127 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5128 vsi->bw_info.bw_ets_credits[i]);
5129 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5130 vsi->bw_info.bw_ets_max[i]);
5133 return I40E_SUCCESS;
5136 /* i40e_enable_pf_lb
5137 * @pf: pointer to the pf structure
5139 * allow loopback on pf
5142 i40e_enable_pf_lb(struct i40e_pf *pf)
5144 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5145 struct i40e_vsi_context ctxt;
5148 /* Use the FW API if FW >= v5.0 */
5149 if (hw->aq.fw_maj_ver < 5) {
5150 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5154 memset(&ctxt, 0, sizeof(ctxt));
5155 ctxt.seid = pf->main_vsi_seid;
5156 ctxt.pf_num = hw->pf_id;
5157 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5159 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5160 ret, hw->aq.asq_last_status);
5163 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5164 ctxt.info.valid_sections =
5165 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5166 ctxt.info.switch_id |=
5167 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5169 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5171 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5172 hw->aq.asq_last_status);
5177 i40e_vsi_setup(struct i40e_pf *pf,
5178 enum i40e_vsi_type type,
5179 struct i40e_vsi *uplink_vsi,
5180 uint16_t user_param)
5182 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5183 struct i40e_vsi *vsi;
5184 struct i40e_mac_filter_info filter;
5186 struct i40e_vsi_context ctxt;
5187 struct ether_addr broadcast =
5188 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5190 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5191 uplink_vsi == NULL) {
5193 "VSI setup failed, VSI link shouldn't be NULL");
5197 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5199 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5204 * 1.type is not MAIN and uplink vsi is not NULL
5205 * If uplink vsi didn't setup VEB, create one first under veb field
5206 * 2.type is SRIOV and the uplink is NULL
5207 * If floating VEB is NULL, create one veb under floating veb field
5210 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5211 uplink_vsi->veb == NULL) {
5212 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5214 if (uplink_vsi->veb == NULL) {
5215 PMD_DRV_LOG(ERR, "VEB setup failed");
5218 /* set ALLOWLOOPBACk on pf, when veb is created */
5219 i40e_enable_pf_lb(pf);
5222 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5223 pf->main_vsi->floating_veb == NULL) {
5224 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5226 if (pf->main_vsi->floating_veb == NULL) {
5227 PMD_DRV_LOG(ERR, "VEB setup failed");
5232 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5234 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5237 TAILQ_INIT(&vsi->mac_list);
5239 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5240 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5241 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5242 vsi->user_param = user_param;
5243 vsi->vlan_anti_spoof_on = 0;
5244 vsi->vlan_filter_on = 0;
5245 /* Allocate queues */
5246 switch (vsi->type) {
5247 case I40E_VSI_MAIN :
5248 vsi->nb_qps = pf->lan_nb_qps;
5250 case I40E_VSI_SRIOV :
5251 vsi->nb_qps = pf->vf_nb_qps;
5253 case I40E_VSI_VMDQ2:
5254 vsi->nb_qps = pf->vmdq_nb_qps;
5257 vsi->nb_qps = pf->fdir_nb_qps;
5263 * The filter status descriptor is reported in rx queue 0,
5264 * while the tx queue for fdir filter programming has no
5265 * such constraints, can be non-zero queues.
5266 * To simplify it, choose FDIR vsi use queue 0 pair.
5267 * To make sure it will use queue 0 pair, queue allocation
5268 * need be done before this function is called
5270 if (type != I40E_VSI_FDIR) {
5271 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5273 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5277 vsi->base_queue = ret;
5279 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5281 /* VF has MSIX interrupt in VF range, don't allocate here */
5282 if (type == I40E_VSI_MAIN) {
5283 if (pf->support_multi_driver) {
5284 /* If support multi-driver, need to use INT0 instead of
5285 * allocating from msix pool. The Msix pool is init from
5286 * INT1, so it's OK just set msix_intr to 0 and nb_msix
5287 * to 1 without calling i40e_res_pool_alloc.
5292 ret = i40e_res_pool_alloc(&pf->msix_pool,
5293 RTE_MIN(vsi->nb_qps,
5294 RTE_MAX_RXTX_INTR_VEC_ID));
5297 "VSI MAIN %d get heap failed %d",
5299 goto fail_queue_alloc;
5301 vsi->msix_intr = ret;
5302 vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5303 RTE_MAX_RXTX_INTR_VEC_ID);
5305 } else if (type != I40E_VSI_SRIOV) {
5306 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5308 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5309 goto fail_queue_alloc;
5311 vsi->msix_intr = ret;
5319 if (type == I40E_VSI_MAIN) {
5320 /* For main VSI, no need to add since it's default one */
5321 vsi->uplink_seid = pf->mac_seid;
5322 vsi->seid = pf->main_vsi_seid;
5323 /* Bind queues with specific MSIX interrupt */
5325 * Needs 2 interrupt at least, one for misc cause which will
5326 * enabled from OS side, Another for queues binding the
5327 * interrupt from device side only.
5330 /* Get default VSI parameters from hardware */
5331 memset(&ctxt, 0, sizeof(ctxt));
5332 ctxt.seid = vsi->seid;
5333 ctxt.pf_num = hw->pf_id;
5334 ctxt.uplink_seid = vsi->uplink_seid;
5336 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5337 if (ret != I40E_SUCCESS) {
5338 PMD_DRV_LOG(ERR, "Failed to get VSI params");
5339 goto fail_msix_alloc;
5341 rte_memcpy(&vsi->info, &ctxt.info,
5342 sizeof(struct i40e_aqc_vsi_properties_data));
5343 vsi->vsi_id = ctxt.vsi_number;
5344 vsi->info.valid_sections = 0;
5346 /* Configure tc, enabled TC0 only */
5347 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5349 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5350 goto fail_msix_alloc;
5353 /* TC, queue mapping */
5354 memset(&ctxt, 0, sizeof(ctxt));
5355 vsi->info.valid_sections |=
5356 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5357 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5358 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5359 rte_memcpy(&ctxt.info, &vsi->info,
5360 sizeof(struct i40e_aqc_vsi_properties_data));
5361 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5362 I40E_DEFAULT_TCMAP);
5363 if (ret != I40E_SUCCESS) {
5365 "Failed to configure TC queue mapping");
5366 goto fail_msix_alloc;
5368 ctxt.seid = vsi->seid;
5369 ctxt.pf_num = hw->pf_id;
5370 ctxt.uplink_seid = vsi->uplink_seid;
5373 /* Update VSI parameters */
5374 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5375 if (ret != I40E_SUCCESS) {
5376 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5377 goto fail_msix_alloc;
5380 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5381 sizeof(vsi->info.tc_mapping));
5382 rte_memcpy(&vsi->info.queue_mapping,
5383 &ctxt.info.queue_mapping,
5384 sizeof(vsi->info.queue_mapping));
5385 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5386 vsi->info.valid_sections = 0;
5388 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5392 * Updating default filter settings are necessary to prevent
5393 * reception of tagged packets.
5394 * Some old firmware configurations load a default macvlan
5395 * filter which accepts both tagged and untagged packets.
5396 * The updating is to use a normal filter instead if needed.
5397 * For NVM 4.2.2 or after, the updating is not needed anymore.
5398 * The firmware with correct configurations load the default
5399 * macvlan filter which is expected and cannot be removed.
5401 i40e_update_default_filter_setting(vsi);
5402 i40e_config_qinq(hw, vsi);
5403 } else if (type == I40E_VSI_SRIOV) {
5404 memset(&ctxt, 0, sizeof(ctxt));
5406 * For other VSI, the uplink_seid equals to uplink VSI's
5407 * uplink_seid since they share same VEB
5409 if (uplink_vsi == NULL)
5410 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5412 vsi->uplink_seid = uplink_vsi->uplink_seid;
5413 ctxt.pf_num = hw->pf_id;
5414 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5415 ctxt.uplink_seid = vsi->uplink_seid;
5416 ctxt.connection_type = 0x1;
5417 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5419 /* Use the VEB configuration if FW >= v5.0 */
5420 if (hw->aq.fw_maj_ver >= 5) {
5421 /* Configure switch ID */
5422 ctxt.info.valid_sections |=
5423 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5424 ctxt.info.switch_id =
5425 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5428 /* Configure port/vlan */
5429 ctxt.info.valid_sections |=
5430 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5431 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5432 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5433 hw->func_caps.enabled_tcmap);
5434 if (ret != I40E_SUCCESS) {
5436 "Failed to configure TC queue mapping");
5437 goto fail_msix_alloc;
5440 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5441 ctxt.info.valid_sections |=
5442 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5444 * Since VSI is not created yet, only configure parameter,
5445 * will add vsi below.
5448 i40e_config_qinq(hw, vsi);
5449 } else if (type == I40E_VSI_VMDQ2) {
5450 memset(&ctxt, 0, sizeof(ctxt));
5452 * For other VSI, the uplink_seid equals to uplink VSI's
5453 * uplink_seid since they share same VEB
5455 vsi->uplink_seid = uplink_vsi->uplink_seid;
5456 ctxt.pf_num = hw->pf_id;
5458 ctxt.uplink_seid = vsi->uplink_seid;
5459 ctxt.connection_type = 0x1;
5460 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5462 ctxt.info.valid_sections |=
5463 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5464 /* user_param carries flag to enable loop back */
5466 ctxt.info.switch_id =
5467 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5468 ctxt.info.switch_id |=
5469 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5472 /* Configure port/vlan */
5473 ctxt.info.valid_sections |=
5474 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5475 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5476 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5477 I40E_DEFAULT_TCMAP);
5478 if (ret != I40E_SUCCESS) {
5480 "Failed to configure TC queue mapping");
5481 goto fail_msix_alloc;
5483 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5484 ctxt.info.valid_sections |=
5485 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5486 } else if (type == I40E_VSI_FDIR) {
5487 memset(&ctxt, 0, sizeof(ctxt));
5488 vsi->uplink_seid = uplink_vsi->uplink_seid;
5489 ctxt.pf_num = hw->pf_id;
5491 ctxt.uplink_seid = vsi->uplink_seid;
5492 ctxt.connection_type = 0x1; /* regular data port */
5493 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5494 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5495 I40E_DEFAULT_TCMAP);
5496 if (ret != I40E_SUCCESS) {
5498 "Failed to configure TC queue mapping.");
5499 goto fail_msix_alloc;
5501 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5502 ctxt.info.valid_sections |=
5503 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5505 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5506 goto fail_msix_alloc;
5509 if (vsi->type != I40E_VSI_MAIN) {
5510 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5511 if (ret != I40E_SUCCESS) {
5512 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5513 hw->aq.asq_last_status);
5514 goto fail_msix_alloc;
5516 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5517 vsi->info.valid_sections = 0;
5518 vsi->seid = ctxt.seid;
5519 vsi->vsi_id = ctxt.vsi_number;
5520 vsi->sib_vsi_list.vsi = vsi;
5521 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5522 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5523 &vsi->sib_vsi_list, list);
5525 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5526 &vsi->sib_vsi_list, list);
5530 /* MAC/VLAN configuration */
5531 rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5532 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5534 ret = i40e_vsi_add_mac(vsi, &filter);
5535 if (ret != I40E_SUCCESS) {
5536 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5537 goto fail_msix_alloc;
5540 /* Get VSI BW information */
5541 i40e_vsi_get_bw_config(vsi);
5544 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5546 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5552 /* Configure vlan filter on or off */
5554 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5557 struct i40e_mac_filter *f;
5559 struct i40e_mac_filter_info *mac_filter;
5560 enum rte_mac_filter_type desired_filter;
5561 int ret = I40E_SUCCESS;
5564 /* Filter to match MAC and VLAN */
5565 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5567 /* Filter to match only MAC */
5568 desired_filter = RTE_MAC_PERFECT_MATCH;
5573 mac_filter = rte_zmalloc("mac_filter_info_data",
5574 num * sizeof(*mac_filter), 0);
5575 if (mac_filter == NULL) {
5576 PMD_DRV_LOG(ERR, "failed to allocate memory");
5577 return I40E_ERR_NO_MEMORY;
5582 /* Remove all existing mac */
5583 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5584 mac_filter[i] = f->mac_info;
5585 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5587 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5588 on ? "enable" : "disable");
5594 /* Override with new filter */
5595 for (i = 0; i < num; i++) {
5596 mac_filter[i].filter_type = desired_filter;
5597 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5599 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5600 on ? "enable" : "disable");
5606 rte_free(mac_filter);
5610 /* Configure vlan stripping on or off */
5612 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5614 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5615 struct i40e_vsi_context ctxt;
5617 int ret = I40E_SUCCESS;
5619 /* Check if it has been already on or off */
5620 if (vsi->info.valid_sections &
5621 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5623 if ((vsi->info.port_vlan_flags &
5624 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5625 return 0; /* already on */
5627 if ((vsi->info.port_vlan_flags &
5628 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5629 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5630 return 0; /* already off */
5635 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5637 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5638 vsi->info.valid_sections =
5639 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5640 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5641 vsi->info.port_vlan_flags |= vlan_flags;
5642 ctxt.seid = vsi->seid;
5643 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5644 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5646 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5647 on ? "enable" : "disable");
5653 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5655 struct rte_eth_dev_data *data = dev->data;
5659 /* Apply vlan offload setting */
5660 mask = ETH_VLAN_STRIP_MASK |
5661 ETH_VLAN_FILTER_MASK |
5662 ETH_VLAN_EXTEND_MASK;
5663 ret = i40e_vlan_offload_set(dev, mask);
5665 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5669 /* Apply pvid setting */
5670 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5671 data->dev_conf.txmode.hw_vlan_insert_pvid);
5673 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5679 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5681 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5683 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5687 i40e_update_flow_control(struct i40e_hw *hw)
5689 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5690 struct i40e_link_status link_status;
5691 uint32_t rxfc = 0, txfc = 0, reg;
5695 memset(&link_status, 0, sizeof(link_status));
5696 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5697 if (ret != I40E_SUCCESS) {
5698 PMD_DRV_LOG(ERR, "Failed to get link status information");
5699 goto write_reg; /* Disable flow control */
5702 an_info = hw->phy.link_info.an_info;
5703 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5704 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5705 ret = I40E_ERR_NOT_READY;
5706 goto write_reg; /* Disable flow control */
5709 * If link auto negotiation is enabled, flow control needs to
5710 * be configured according to it
5712 switch (an_info & I40E_LINK_PAUSE_RXTX) {
5713 case I40E_LINK_PAUSE_RXTX:
5716 hw->fc.current_mode = I40E_FC_FULL;
5718 case I40E_AQ_LINK_PAUSE_RX:
5720 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5722 case I40E_AQ_LINK_PAUSE_TX:
5724 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5727 hw->fc.current_mode = I40E_FC_NONE;
5732 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5733 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5734 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5735 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5736 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5737 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5744 i40e_pf_setup(struct i40e_pf *pf)
5746 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5747 struct i40e_filter_control_settings settings;
5748 struct i40e_vsi *vsi;
5751 /* Clear all stats counters */
5752 pf->offset_loaded = FALSE;
5753 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5754 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5755 memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5756 memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5758 ret = i40e_pf_get_switch_config(pf);
5759 if (ret != I40E_SUCCESS) {
5760 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5763 if (pf->flags & I40E_FLAG_FDIR) {
5764 /* make queue allocated first, let FDIR use queue pair 0*/
5765 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5766 if (ret != I40E_FDIR_QUEUE_ID) {
5768 "queue allocation fails for FDIR: ret =%d",
5770 pf->flags &= ~I40E_FLAG_FDIR;
5773 /* main VSI setup */
5774 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5776 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5777 return I40E_ERR_NOT_READY;
5781 /* Configure filter control */
5782 memset(&settings, 0, sizeof(settings));
5783 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5784 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5785 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5786 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5788 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5789 hw->func_caps.rss_table_size);
5790 return I40E_ERR_PARAM;
5792 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5793 hw->func_caps.rss_table_size);
5794 pf->hash_lut_size = hw->func_caps.rss_table_size;
5796 /* Enable ethtype and macvlan filters */
5797 settings.enable_ethtype = TRUE;
5798 settings.enable_macvlan = TRUE;
5799 ret = i40e_set_filter_control(hw, &settings);
5801 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5804 /* Update flow control according to the auto negotiation */
5805 i40e_update_flow_control(hw);
5807 return I40E_SUCCESS;
5811 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5817 * Set or clear TX Queue Disable flags,
5818 * which is required by hardware.
5820 i40e_pre_tx_queue_cfg(hw, q_idx, on);
5821 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5823 /* Wait until the request is finished */
5824 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5825 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5826 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5827 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5828 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5834 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5835 return I40E_SUCCESS; /* already on, skip next steps */
5837 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5838 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5840 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5841 return I40E_SUCCESS; /* already off, skip next steps */
5842 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5844 /* Write the register */
5845 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5846 /* Check the result */
5847 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5848 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5849 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5851 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5852 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5855 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5856 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5860 /* Check if it is timeout */
5861 if (j >= I40E_CHK_Q_ENA_COUNT) {
5862 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5863 (on ? "enable" : "disable"), q_idx);
5864 return I40E_ERR_TIMEOUT;
5867 return I40E_SUCCESS;
5870 /* Swith on or off the tx queues */
5872 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5874 struct rte_eth_dev_data *dev_data = pf->dev_data;
5875 struct i40e_tx_queue *txq;
5876 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5880 for (i = 0; i < dev_data->nb_tx_queues; i++) {
5881 txq = dev_data->tx_queues[i];
5882 /* Don't operate the queue if not configured or
5883 * if starting only per queue */
5884 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5887 ret = i40e_dev_tx_queue_start(dev, i);
5889 ret = i40e_dev_tx_queue_stop(dev, i);
5890 if ( ret != I40E_SUCCESS)
5894 return I40E_SUCCESS;
5898 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5903 /* Wait until the request is finished */
5904 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5905 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5906 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5907 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5908 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5913 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5914 return I40E_SUCCESS; /* Already on, skip next steps */
5915 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5917 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5918 return I40E_SUCCESS; /* Already off, skip next steps */
5919 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5922 /* Write the register */
5923 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5924 /* Check the result */
5925 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5926 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5927 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5929 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5930 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5933 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5934 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5939 /* Check if it is timeout */
5940 if (j >= I40E_CHK_Q_ENA_COUNT) {
5941 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5942 (on ? "enable" : "disable"), q_idx);
5943 return I40E_ERR_TIMEOUT;
5946 return I40E_SUCCESS;
5948 /* Switch on or off the rx queues */
5950 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5952 struct rte_eth_dev_data *dev_data = pf->dev_data;
5953 struct i40e_rx_queue *rxq;
5954 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5958 for (i = 0; i < dev_data->nb_rx_queues; i++) {
5959 rxq = dev_data->rx_queues[i];
5960 /* Don't operate the queue if not configured or
5961 * if starting only per queue */
5962 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5965 ret = i40e_dev_rx_queue_start(dev, i);
5967 ret = i40e_dev_rx_queue_stop(dev, i);
5968 if (ret != I40E_SUCCESS)
5972 return I40E_SUCCESS;
5975 /* Switch on or off all the rx/tx queues */
5977 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5982 /* enable rx queues before enabling tx queues */
5983 ret = i40e_dev_switch_rx_queues(pf, on);
5985 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5988 ret = i40e_dev_switch_tx_queues(pf, on);
5990 /* Stop tx queues before stopping rx queues */
5991 ret = i40e_dev_switch_tx_queues(pf, on);
5993 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5996 ret = i40e_dev_switch_rx_queues(pf, on);
6002 /* Initialize VSI for TX */
6004 i40e_dev_tx_init(struct i40e_pf *pf)
6006 struct rte_eth_dev_data *data = pf->dev_data;
6008 uint32_t ret = I40E_SUCCESS;
6009 struct i40e_tx_queue *txq;
6011 for (i = 0; i < data->nb_tx_queues; i++) {
6012 txq = data->tx_queues[i];
6013 if (!txq || !txq->q_set)
6015 ret = i40e_tx_queue_init(txq);
6016 if (ret != I40E_SUCCESS)
6019 if (ret == I40E_SUCCESS)
6020 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6026 /* Initialize VSI for RX */
6028 i40e_dev_rx_init(struct i40e_pf *pf)
6030 struct rte_eth_dev_data *data = pf->dev_data;
6031 int ret = I40E_SUCCESS;
6033 struct i40e_rx_queue *rxq;
6035 i40e_pf_config_mq_rx(pf);
6036 for (i = 0; i < data->nb_rx_queues; i++) {
6037 rxq = data->rx_queues[i];
6038 if (!rxq || !rxq->q_set)
6041 ret = i40e_rx_queue_init(rxq);
6042 if (ret != I40E_SUCCESS) {
6044 "Failed to do RX queue initialization");
6048 if (ret == I40E_SUCCESS)
6049 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6056 i40e_dev_rxtx_init(struct i40e_pf *pf)
6060 err = i40e_dev_tx_init(pf);
6062 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6065 err = i40e_dev_rx_init(pf);
6067 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6075 i40e_vmdq_setup(struct rte_eth_dev *dev)
6077 struct rte_eth_conf *conf = &dev->data->dev_conf;
6078 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6079 int i, err, conf_vsis, j, loop;
6080 struct i40e_vsi *vsi;
6081 struct i40e_vmdq_info *vmdq_info;
6082 struct rte_eth_vmdq_rx_conf *vmdq_conf;
6083 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6086 * Disable interrupt to avoid message from VF. Furthermore, it will
6087 * avoid race condition in VSI creation/destroy.
6089 i40e_pf_disable_irq0(hw);
6091 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6092 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6096 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6097 if (conf_vsis > pf->max_nb_vmdq_vsi) {
6098 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6099 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6100 pf->max_nb_vmdq_vsi);
6104 if (pf->vmdq != NULL) {
6105 PMD_INIT_LOG(INFO, "VMDQ already configured");
6109 pf->vmdq = rte_zmalloc("vmdq_info_struct",
6110 sizeof(*vmdq_info) * conf_vsis, 0);
6112 if (pf->vmdq == NULL) {
6113 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6117 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6119 /* Create VMDQ VSI */
6120 for (i = 0; i < conf_vsis; i++) {
6121 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6122 vmdq_conf->enable_loop_back);
6124 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6128 vmdq_info = &pf->vmdq[i];
6130 vmdq_info->vsi = vsi;
6132 pf->nb_cfg_vmdq_vsi = conf_vsis;
6134 /* Configure Vlan */
6135 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6136 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6137 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6138 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6139 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6140 vmdq_conf->pool_map[i].vlan_id, j);
6142 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6143 vmdq_conf->pool_map[i].vlan_id);
6145 PMD_INIT_LOG(ERR, "Failed to add vlan");
6153 i40e_pf_enable_irq0(hw);
6158 for (i = 0; i < conf_vsis; i++)
6159 if (pf->vmdq[i].vsi == NULL)
6162 i40e_vsi_release(pf->vmdq[i].vsi);
6166 i40e_pf_enable_irq0(hw);
6171 i40e_stat_update_32(struct i40e_hw *hw,
6179 new_data = (uint64_t)I40E_READ_REG(hw, reg);
6183 if (new_data >= *offset)
6184 *stat = (uint64_t)(new_data - *offset);
6186 *stat = (uint64_t)((new_data +
6187 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6191 i40e_stat_update_48(struct i40e_hw *hw,
6200 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6201 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6202 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6207 if (new_data >= *offset)
6208 *stat = new_data - *offset;
6210 *stat = (uint64_t)((new_data +
6211 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6213 *stat &= I40E_48_BIT_MASK;
6218 i40e_pf_disable_irq0(struct i40e_hw *hw)
6220 /* Disable all interrupt types */
6221 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6222 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6223 I40E_WRITE_FLUSH(hw);
6228 i40e_pf_enable_irq0(struct i40e_hw *hw)
6230 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6231 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6232 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6233 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6234 I40E_WRITE_FLUSH(hw);
6238 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6240 /* read pending request and disable first */
6241 i40e_pf_disable_irq0(hw);
6242 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6243 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6244 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6247 /* Link no queues with irq0 */
6248 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6249 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6253 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6255 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6256 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6259 uint32_t index, offset, val;
6264 * Try to find which VF trigger a reset, use absolute VF id to access
6265 * since the reg is global register.
6267 for (i = 0; i < pf->vf_num; i++) {
6268 abs_vf_id = hw->func_caps.vf_base_id + i;
6269 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6270 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6271 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6272 /* VFR event occurred */
6273 if (val & (0x1 << offset)) {
6276 /* Clear the event first */
6277 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6279 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6281 * Only notify a VF reset event occurred,
6282 * don't trigger another SW reset
6284 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6285 if (ret != I40E_SUCCESS)
6286 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6292 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6294 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6297 for (i = 0; i < pf->vf_num; i++)
6298 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6302 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6304 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6305 struct i40e_arq_event_info info;
6306 uint16_t pending, opcode;
6309 info.buf_len = I40E_AQ_BUF_SZ;
6310 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6311 if (!info.msg_buf) {
6312 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6318 ret = i40e_clean_arq_element(hw, &info, &pending);
6320 if (ret != I40E_SUCCESS) {
6322 "Failed to read msg from AdminQ, aq_err: %u",
6323 hw->aq.asq_last_status);
6326 opcode = rte_le_to_cpu_16(info.desc.opcode);
6329 case i40e_aqc_opc_send_msg_to_pf:
6330 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6331 i40e_pf_host_handle_vf_msg(dev,
6332 rte_le_to_cpu_16(info.desc.retval),
6333 rte_le_to_cpu_32(info.desc.cookie_high),
6334 rte_le_to_cpu_32(info.desc.cookie_low),
6338 case i40e_aqc_opc_get_link_status:
6339 ret = i40e_dev_link_update(dev, 0);
6341 _rte_eth_dev_callback_process(dev,
6342 RTE_ETH_EVENT_INTR_LSC, NULL);
6345 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6350 rte_free(info.msg_buf);
6354 * Interrupt handler triggered by NIC for handling
6355 * specific interrupt.
6358 * Pointer to interrupt handle.
6360 * The address of parameter (struct rte_eth_dev *) regsitered before.
6366 i40e_dev_interrupt_handler(void *param)
6368 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6369 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6372 /* Disable interrupt */
6373 i40e_pf_disable_irq0(hw);
6375 /* read out interrupt causes */
6376 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6378 /* No interrupt event indicated */
6379 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6380 PMD_DRV_LOG(INFO, "No interrupt event");
6383 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6384 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6385 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6386 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6387 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6388 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6389 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6390 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6391 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6392 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6393 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6394 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6395 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6396 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6398 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6399 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6400 i40e_dev_handle_vfr_event(dev);
6402 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6403 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6404 i40e_dev_handle_aq_msg(dev);
6408 /* Enable interrupt */
6409 i40e_pf_enable_irq0(hw);
6410 rte_intr_enable(dev->intr_handle);
6414 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6415 struct i40e_macvlan_filter *filter,
6418 int ele_num, ele_buff_size;
6419 int num, actual_num, i;
6421 int ret = I40E_SUCCESS;
6422 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6423 struct i40e_aqc_add_macvlan_element_data *req_list;
6425 if (filter == NULL || total == 0)
6426 return I40E_ERR_PARAM;
6427 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6428 ele_buff_size = hw->aq.asq_buf_size;
6430 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6431 if (req_list == NULL) {
6432 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6433 return I40E_ERR_NO_MEMORY;
6438 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6439 memset(req_list, 0, ele_buff_size);
6441 for (i = 0; i < actual_num; i++) {
6442 rte_memcpy(req_list[i].mac_addr,
6443 &filter[num + i].macaddr, ETH_ADDR_LEN);
6444 req_list[i].vlan_tag =
6445 rte_cpu_to_le_16(filter[num + i].vlan_id);
6447 switch (filter[num + i].filter_type) {
6448 case RTE_MAC_PERFECT_MATCH:
6449 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6450 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6452 case RTE_MACVLAN_PERFECT_MATCH:
6453 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6455 case RTE_MAC_HASH_MATCH:
6456 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6457 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6459 case RTE_MACVLAN_HASH_MATCH:
6460 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6463 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6464 ret = I40E_ERR_PARAM;
6468 req_list[i].queue_number = 0;
6470 req_list[i].flags = rte_cpu_to_le_16(flags);
6473 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6475 if (ret != I40E_SUCCESS) {
6476 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6480 } while (num < total);
6488 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6489 struct i40e_macvlan_filter *filter,
6492 int ele_num, ele_buff_size;
6493 int num, actual_num, i;
6495 int ret = I40E_SUCCESS;
6496 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6497 struct i40e_aqc_remove_macvlan_element_data *req_list;
6499 if (filter == NULL || total == 0)
6500 return I40E_ERR_PARAM;
6502 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6503 ele_buff_size = hw->aq.asq_buf_size;
6505 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6506 if (req_list == NULL) {
6507 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6508 return I40E_ERR_NO_MEMORY;
6513 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6514 memset(req_list, 0, ele_buff_size);
6516 for (i = 0; i < actual_num; i++) {
6517 rte_memcpy(req_list[i].mac_addr,
6518 &filter[num + i].macaddr, ETH_ADDR_LEN);
6519 req_list[i].vlan_tag =
6520 rte_cpu_to_le_16(filter[num + i].vlan_id);
6522 switch (filter[num + i].filter_type) {
6523 case RTE_MAC_PERFECT_MATCH:
6524 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6525 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6527 case RTE_MACVLAN_PERFECT_MATCH:
6528 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6530 case RTE_MAC_HASH_MATCH:
6531 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6532 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6534 case RTE_MACVLAN_HASH_MATCH:
6535 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6538 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6539 ret = I40E_ERR_PARAM;
6542 req_list[i].flags = rte_cpu_to_le_16(flags);
6545 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6547 if (ret != I40E_SUCCESS) {
6548 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6552 } while (num < total);
6559 /* Find out specific MAC filter */
6560 static struct i40e_mac_filter *
6561 i40e_find_mac_filter(struct i40e_vsi *vsi,
6562 struct ether_addr *macaddr)
6564 struct i40e_mac_filter *f;
6566 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6567 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6575 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6578 uint32_t vid_idx, vid_bit;
6580 if (vlan_id > ETH_VLAN_ID_MAX)
6583 vid_idx = I40E_VFTA_IDX(vlan_id);
6584 vid_bit = I40E_VFTA_BIT(vlan_id);
6586 if (vsi->vfta[vid_idx] & vid_bit)
6593 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6594 uint16_t vlan_id, bool on)
6596 uint32_t vid_idx, vid_bit;
6598 vid_idx = I40E_VFTA_IDX(vlan_id);
6599 vid_bit = I40E_VFTA_BIT(vlan_id);
6602 vsi->vfta[vid_idx] |= vid_bit;
6604 vsi->vfta[vid_idx] &= ~vid_bit;
6608 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6609 uint16_t vlan_id, bool on)
6611 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6612 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6615 if (vlan_id > ETH_VLAN_ID_MAX)
6618 i40e_store_vlan_filter(vsi, vlan_id, on);
6620 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6623 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6626 ret = i40e_aq_add_vlan(hw, vsi->seid,
6627 &vlan_data, 1, NULL);
6628 if (ret != I40E_SUCCESS)
6629 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6631 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6632 &vlan_data, 1, NULL);
6633 if (ret != I40E_SUCCESS)
6635 "Failed to remove vlan filter");
6640 * Find all vlan options for specific mac addr,
6641 * return with actual vlan found.
6644 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6645 struct i40e_macvlan_filter *mv_f,
6646 int num, struct ether_addr *addr)
6652 * Not to use i40e_find_vlan_filter to decrease the loop time,
6653 * although the code looks complex.
6655 if (num < vsi->vlan_num)
6656 return I40E_ERR_PARAM;
6659 for (j = 0; j < I40E_VFTA_SIZE; j++) {
6661 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6662 if (vsi->vfta[j] & (1 << k)) {
6665 "vlan number doesn't match");
6666 return I40E_ERR_PARAM;
6668 rte_memcpy(&mv_f[i].macaddr,
6669 addr, ETH_ADDR_LEN);
6671 j * I40E_UINT32_BIT_SIZE + k;
6677 return I40E_SUCCESS;
6681 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6682 struct i40e_macvlan_filter *mv_f,
6687 struct i40e_mac_filter *f;
6689 if (num < vsi->mac_num)
6690 return I40E_ERR_PARAM;
6692 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6694 PMD_DRV_LOG(ERR, "buffer number not match");
6695 return I40E_ERR_PARAM;
6697 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6699 mv_f[i].vlan_id = vlan;
6700 mv_f[i].filter_type = f->mac_info.filter_type;
6704 return I40E_SUCCESS;
6708 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6711 struct i40e_mac_filter *f;
6712 struct i40e_macvlan_filter *mv_f;
6713 int ret = I40E_SUCCESS;
6715 if (vsi == NULL || vsi->mac_num == 0)
6716 return I40E_ERR_PARAM;
6718 /* Case that no vlan is set */
6719 if (vsi->vlan_num == 0)
6722 num = vsi->mac_num * vsi->vlan_num;
6724 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6726 PMD_DRV_LOG(ERR, "failed to allocate memory");
6727 return I40E_ERR_NO_MEMORY;
6731 if (vsi->vlan_num == 0) {
6732 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6733 rte_memcpy(&mv_f[i].macaddr,
6734 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6735 mv_f[i].filter_type = f->mac_info.filter_type;
6736 mv_f[i].vlan_id = 0;
6740 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6741 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6742 vsi->vlan_num, &f->mac_info.mac_addr);
6743 if (ret != I40E_SUCCESS)
6745 for (j = i; j < i + vsi->vlan_num; j++)
6746 mv_f[j].filter_type = f->mac_info.filter_type;
6751 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6759 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6761 struct i40e_macvlan_filter *mv_f;
6763 int ret = I40E_SUCCESS;
6765 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6766 return I40E_ERR_PARAM;
6768 /* If it's already set, just return */
6769 if (i40e_find_vlan_filter(vsi,vlan))
6770 return I40E_SUCCESS;
6772 mac_num = vsi->mac_num;
6775 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6776 return I40E_ERR_PARAM;
6779 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6782 PMD_DRV_LOG(ERR, "failed to allocate memory");
6783 return I40E_ERR_NO_MEMORY;
6786 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6788 if (ret != I40E_SUCCESS)
6791 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6793 if (ret != I40E_SUCCESS)
6796 i40e_set_vlan_filter(vsi, vlan, 1);
6806 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6808 struct i40e_macvlan_filter *mv_f;
6810 int ret = I40E_SUCCESS;
6813 * Vlan 0 is the generic filter for untagged packets
6814 * and can't be removed.
6816 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6817 return I40E_ERR_PARAM;
6819 /* If can't find it, just return */
6820 if (!i40e_find_vlan_filter(vsi, vlan))
6821 return I40E_ERR_PARAM;
6823 mac_num = vsi->mac_num;
6826 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6827 return I40E_ERR_PARAM;
6830 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6833 PMD_DRV_LOG(ERR, "failed to allocate memory");
6834 return I40E_ERR_NO_MEMORY;
6837 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6839 if (ret != I40E_SUCCESS)
6842 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6844 if (ret != I40E_SUCCESS)
6847 /* This is last vlan to remove, replace all mac filter with vlan 0 */
6848 if (vsi->vlan_num == 1) {
6849 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6850 if (ret != I40E_SUCCESS)
6853 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6854 if (ret != I40E_SUCCESS)
6858 i40e_set_vlan_filter(vsi, vlan, 0);
6868 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6870 struct i40e_mac_filter *f;
6871 struct i40e_macvlan_filter *mv_f;
6872 int i, vlan_num = 0;
6873 int ret = I40E_SUCCESS;
6875 /* If it's add and we've config it, return */
6876 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6878 return I40E_SUCCESS;
6879 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6880 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6883 * If vlan_num is 0, that's the first time to add mac,
6884 * set mask for vlan_id 0.
6886 if (vsi->vlan_num == 0) {
6887 i40e_set_vlan_filter(vsi, 0, 1);
6890 vlan_num = vsi->vlan_num;
6891 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6892 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6895 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6897 PMD_DRV_LOG(ERR, "failed to allocate memory");
6898 return I40E_ERR_NO_MEMORY;
6901 for (i = 0; i < vlan_num; i++) {
6902 mv_f[i].filter_type = mac_filter->filter_type;
6903 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6907 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6908 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6909 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6910 &mac_filter->mac_addr);
6911 if (ret != I40E_SUCCESS)
6915 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6916 if (ret != I40E_SUCCESS)
6919 /* Add the mac addr into mac list */
6920 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6922 PMD_DRV_LOG(ERR, "failed to allocate memory");
6923 ret = I40E_ERR_NO_MEMORY;
6926 rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6928 f->mac_info.filter_type = mac_filter->filter_type;
6929 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6940 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6942 struct i40e_mac_filter *f;
6943 struct i40e_macvlan_filter *mv_f;
6945 enum rte_mac_filter_type filter_type;
6946 int ret = I40E_SUCCESS;
6948 /* Can't find it, return an error */
6949 f = i40e_find_mac_filter(vsi, addr);
6951 return I40E_ERR_PARAM;
6953 vlan_num = vsi->vlan_num;
6954 filter_type = f->mac_info.filter_type;
6955 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6956 filter_type == RTE_MACVLAN_HASH_MATCH) {
6957 if (vlan_num == 0) {
6958 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6959 return I40E_ERR_PARAM;
6961 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6962 filter_type == RTE_MAC_HASH_MATCH)
6965 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6967 PMD_DRV_LOG(ERR, "failed to allocate memory");
6968 return I40E_ERR_NO_MEMORY;
6971 for (i = 0; i < vlan_num; i++) {
6972 mv_f[i].filter_type = filter_type;
6973 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6976 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6977 filter_type == RTE_MACVLAN_HASH_MATCH) {
6978 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6979 if (ret != I40E_SUCCESS)
6983 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6984 if (ret != I40E_SUCCESS)
6987 /* Remove the mac addr into mac list */
6988 TAILQ_REMOVE(&vsi->mac_list, f, next);
6998 /* Configure hash enable flags for RSS */
7000 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7008 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7009 if (flags & (1ULL << i))
7010 hena |= adapter->pctypes_tbl[i];
7016 /* Parse the hash enable flags */
7018 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7020 uint64_t rss_hf = 0;
7026 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7027 if (flags & adapter->pctypes_tbl[i])
7028 rss_hf |= (1ULL << i);
7035 i40e_pf_disable_rss(struct i40e_pf *pf)
7037 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7039 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7040 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7041 I40E_WRITE_FLUSH(hw);
7045 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7047 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7048 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7049 uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7050 I40E_VFQF_HKEY_MAX_INDEX :
7051 I40E_PFQF_HKEY_MAX_INDEX;
7054 if (!key || key_len == 0) {
7055 PMD_DRV_LOG(DEBUG, "No key to be configured");
7057 } else if (key_len != (key_idx + 1) *
7059 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7063 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7064 struct i40e_aqc_get_set_rss_key_data *key_dw =
7065 (struct i40e_aqc_get_set_rss_key_data *)key;
7067 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7069 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7071 uint32_t *hash_key = (uint32_t *)key;
7074 if (vsi->type == I40E_VSI_SRIOV) {
7075 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7078 I40E_VFQF_HKEY1(i, vsi->user_param),
7082 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7083 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7086 I40E_WRITE_FLUSH(hw);
7093 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7095 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7096 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7100 if (!key || !key_len)
7103 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7104 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7105 (struct i40e_aqc_get_set_rss_key_data *)key);
7107 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7111 uint32_t *key_dw = (uint32_t *)key;
7114 if (vsi->type == I40E_VSI_SRIOV) {
7115 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7116 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7117 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7119 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7122 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7123 reg = I40E_PFQF_HKEY(i);
7124 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7126 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7134 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7136 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7140 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7141 rss_conf->rss_key_len);
7145 hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7146 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7147 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7148 I40E_WRITE_FLUSH(hw);
7154 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7155 struct rte_eth_rss_conf *rss_conf)
7157 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7158 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7159 uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7162 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7163 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7165 if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7166 if (rss_hf != 0) /* Enable RSS */
7168 return 0; /* Nothing to do */
7171 if (rss_hf == 0) /* Disable RSS */
7174 return i40e_hw_rss_hash_set(pf, rss_conf);
7178 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7179 struct rte_eth_rss_conf *rss_conf)
7181 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7182 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7185 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7186 &rss_conf->rss_key_len);
7188 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7189 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7190 rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7196 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7198 switch (filter_type) {
7199 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7200 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7202 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7203 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7205 case RTE_TUNNEL_FILTER_IMAC_TENID:
7206 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7208 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7209 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7211 case ETH_TUNNEL_FILTER_IMAC:
7212 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7214 case ETH_TUNNEL_FILTER_OIP:
7215 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7217 case ETH_TUNNEL_FILTER_IIP:
7218 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7221 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7228 /* Convert tunnel filter structure */
7230 i40e_tunnel_filter_convert(
7231 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
7232 struct i40e_tunnel_filter *tunnel_filter)
7234 ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
7235 (struct ether_addr *)&tunnel_filter->input.outer_mac);
7236 ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
7237 (struct ether_addr *)&tunnel_filter->input.inner_mac);
7238 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7239 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7240 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7241 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7242 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7244 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7245 tunnel_filter->input.flags = cld_filter->element.flags;
7246 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7247 tunnel_filter->queue = cld_filter->element.queue_number;
7248 rte_memcpy(tunnel_filter->input.general_fields,
7249 cld_filter->general_fields,
7250 sizeof(cld_filter->general_fields));
7255 /* Check if there exists the tunnel filter */
7256 struct i40e_tunnel_filter *
7257 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7258 const struct i40e_tunnel_filter_input *input)
7262 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7266 return tunnel_rule->hash_map[ret];
7269 /* Add a tunnel filter into the SW list */
7271 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7272 struct i40e_tunnel_filter *tunnel_filter)
7274 struct i40e_tunnel_rule *rule = &pf->tunnel;
7277 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7280 "Failed to insert tunnel filter to hash table %d!",
7284 rule->hash_map[ret] = tunnel_filter;
7286 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7291 /* Delete a tunnel filter from the SW list */
7293 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7294 struct i40e_tunnel_filter_input *input)
7296 struct i40e_tunnel_rule *rule = &pf->tunnel;
7297 struct i40e_tunnel_filter *tunnel_filter;
7300 ret = rte_hash_del_key(rule->hash_table, input);
7303 "Failed to delete tunnel filter to hash table %d!",
7307 tunnel_filter = rule->hash_map[ret];
7308 rule->hash_map[ret] = NULL;
7310 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7311 rte_free(tunnel_filter);
7317 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7318 struct rte_eth_tunnel_filter_conf *tunnel_filter,
7322 uint32_t ipv4_addr, ipv4_addr_le;
7323 uint8_t i, tun_type = 0;
7324 /* internal varialbe to convert ipv6 byte order */
7325 uint32_t convert_ipv6[4];
7327 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7328 struct i40e_vsi *vsi = pf->main_vsi;
7329 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7330 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7331 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7332 struct i40e_tunnel_filter *tunnel, *node;
7333 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7335 cld_filter = rte_zmalloc("tunnel_filter",
7336 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7339 if (NULL == cld_filter) {
7340 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7343 pfilter = cld_filter;
7345 ether_addr_copy(&tunnel_filter->outer_mac,
7346 (struct ether_addr *)&pfilter->element.outer_mac);
7347 ether_addr_copy(&tunnel_filter->inner_mac,
7348 (struct ether_addr *)&pfilter->element.inner_mac);
7350 pfilter->element.inner_vlan =
7351 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7352 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7353 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7354 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7355 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7356 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7358 sizeof(pfilter->element.ipaddr.v4.data));
7360 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7361 for (i = 0; i < 4; i++) {
7363 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7365 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7367 sizeof(pfilter->element.ipaddr.v6.data));
7370 /* check tunneled type */
7371 switch (tunnel_filter->tunnel_type) {
7372 case RTE_TUNNEL_TYPE_VXLAN:
7373 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7375 case RTE_TUNNEL_TYPE_NVGRE:
7376 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7378 case RTE_TUNNEL_TYPE_IP_IN_GRE:
7379 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7382 /* Other tunnel types is not supported. */
7383 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7384 rte_free(cld_filter);
7388 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7389 &pfilter->element.flags);
7391 rte_free(cld_filter);
7395 pfilter->element.flags |= rte_cpu_to_le_16(
7396 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7397 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7398 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7399 pfilter->element.queue_number =
7400 rte_cpu_to_le_16(tunnel_filter->queue_id);
7402 /* Check if there is the filter in SW list */
7403 memset(&check_filter, 0, sizeof(check_filter));
7404 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7405 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7407 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7408 rte_free(cld_filter);
7412 if (!add && !node) {
7413 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7414 rte_free(cld_filter);
7419 ret = i40e_aq_add_cloud_filters(hw,
7420 vsi->seid, &cld_filter->element, 1);
7422 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7423 rte_free(cld_filter);
7426 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7427 if (tunnel == NULL) {
7428 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7429 rte_free(cld_filter);
7433 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7434 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7438 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7439 &cld_filter->element, 1);
7441 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7442 rte_free(cld_filter);
7445 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7448 rte_free(cld_filter);
7452 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7453 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
7454 #define I40E_TR_GENEVE_KEY_MASK 0x8
7455 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
7456 #define I40E_TR_GRE_KEY_MASK 0x400
7457 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
7458 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
7461 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7463 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7464 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7465 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7466 enum i40e_status_code status = I40E_SUCCESS;
7468 if (pf->support_multi_driver) {
7469 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7470 return I40E_NOT_SUPPORTED;
7473 memset(&filter_replace, 0,
7474 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7475 memset(&filter_replace_buf, 0,
7476 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7478 /* create L1 filter */
7479 filter_replace.old_filter_type =
7480 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7481 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7482 filter_replace.tr_bit = 0;
7484 /* Prepare the buffer, 3 entries */
7485 filter_replace_buf.data[0] =
7486 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7487 filter_replace_buf.data[0] |=
7488 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7489 filter_replace_buf.data[2] = 0xFF;
7490 filter_replace_buf.data[3] = 0xFF;
7491 filter_replace_buf.data[4] =
7492 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7493 filter_replace_buf.data[4] |=
7494 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7495 filter_replace_buf.data[7] = 0xF0;
7496 filter_replace_buf.data[8]
7497 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7498 filter_replace_buf.data[8] |=
7499 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7500 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7501 I40E_TR_GENEVE_KEY_MASK |
7502 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7503 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7504 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7505 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7507 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7508 &filter_replace_buf);
7510 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7511 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7512 "cloud l1 type is changed from 0x%x to 0x%x",
7513 filter_replace.old_filter_type,
7514 filter_replace.new_filter_type);
7520 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7522 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7523 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7524 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7525 enum i40e_status_code status = I40E_SUCCESS;
7527 if (pf->support_multi_driver) {
7528 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7529 return I40E_NOT_SUPPORTED;
7533 memset(&filter_replace, 0,
7534 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7535 memset(&filter_replace_buf, 0,
7536 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7537 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7538 I40E_AQC_MIRROR_CLOUD_FILTER;
7539 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7540 filter_replace.new_filter_type =
7541 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7542 /* Prepare the buffer, 2 entries */
7543 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7544 filter_replace_buf.data[0] |=
7545 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7546 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7547 filter_replace_buf.data[4] |=
7548 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7549 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7550 &filter_replace_buf);
7553 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7554 "cloud filter type is changed from 0x%x to 0x%x",
7555 filter_replace.old_filter_type,
7556 filter_replace.new_filter_type);
7559 memset(&filter_replace, 0,
7560 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7561 memset(&filter_replace_buf, 0,
7562 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7564 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7565 I40E_AQC_MIRROR_CLOUD_FILTER;
7566 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7567 filter_replace.new_filter_type =
7568 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7569 /* Prepare the buffer, 2 entries */
7570 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7571 filter_replace_buf.data[0] |=
7572 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7573 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7574 filter_replace_buf.data[4] |=
7575 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7577 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7578 &filter_replace_buf);
7580 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7581 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7582 "cloud filter type is changed from 0x%x to 0x%x",
7583 filter_replace.old_filter_type,
7584 filter_replace.new_filter_type);
7589 static enum i40e_status_code
7590 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7592 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7593 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7594 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7595 enum i40e_status_code status = I40E_SUCCESS;
7597 if (pf->support_multi_driver) {
7598 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7599 return I40E_NOT_SUPPORTED;
7603 memset(&filter_replace, 0,
7604 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7605 memset(&filter_replace_buf, 0,
7606 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7607 /* create L1 filter */
7608 filter_replace.old_filter_type =
7609 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7610 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7611 filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7612 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7613 /* Prepare the buffer, 2 entries */
7614 filter_replace_buf.data[0] =
7615 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7616 filter_replace_buf.data[0] |=
7617 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7618 filter_replace_buf.data[2] = 0xFF;
7619 filter_replace_buf.data[3] = 0xFF;
7620 filter_replace_buf.data[4] =
7621 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7622 filter_replace_buf.data[4] |=
7623 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7624 filter_replace_buf.data[6] = 0xFF;
7625 filter_replace_buf.data[7] = 0xFF;
7626 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7627 &filter_replace_buf);
7630 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7631 "cloud l1 type is changed from 0x%x to 0x%x",
7632 filter_replace.old_filter_type,
7633 filter_replace.new_filter_type);
7636 memset(&filter_replace, 0,
7637 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7638 memset(&filter_replace_buf, 0,
7639 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7640 /* create L1 filter */
7641 filter_replace.old_filter_type =
7642 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
7643 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
7644 filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
7645 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7646 /* Prepare the buffer, 2 entries */
7647 filter_replace_buf.data[0] =
7648 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7649 filter_replace_buf.data[0] |=
7650 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7651 filter_replace_buf.data[2] = 0xFF;
7652 filter_replace_buf.data[3] = 0xFF;
7653 filter_replace_buf.data[4] =
7654 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7655 filter_replace_buf.data[4] |=
7656 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7657 filter_replace_buf.data[6] = 0xFF;
7658 filter_replace_buf.data[7] = 0xFF;
7660 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7661 &filter_replace_buf);
7663 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7664 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7665 "cloud l1 type is changed from 0x%x to 0x%x",
7666 filter_replace.old_filter_type,
7667 filter_replace.new_filter_type);
7673 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
7675 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7676 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7677 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7678 enum i40e_status_code status = I40E_SUCCESS;
7680 if (pf->support_multi_driver) {
7681 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7682 return I40E_NOT_SUPPORTED;
7686 memset(&filter_replace, 0,
7687 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7688 memset(&filter_replace_buf, 0,
7689 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7690 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7691 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7692 filter_replace.new_filter_type =
7693 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7694 /* Prepare the buffer, 2 entries */
7695 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
7696 filter_replace_buf.data[0] |=
7697 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7698 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7699 filter_replace_buf.data[4] |=
7700 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7701 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7702 &filter_replace_buf);
7705 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7706 "cloud filter type is changed from 0x%x to 0x%x",
7707 filter_replace.old_filter_type,
7708 filter_replace.new_filter_type);
7711 memset(&filter_replace, 0,
7712 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7713 memset(&filter_replace_buf, 0,
7714 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7715 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7716 filter_replace.old_filter_type =
7717 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7718 filter_replace.new_filter_type =
7719 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7720 /* Prepare the buffer, 2 entries */
7721 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
7722 filter_replace_buf.data[0] |=
7723 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7724 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7725 filter_replace_buf.data[4] |=
7726 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7728 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7729 &filter_replace_buf);
7731 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7732 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7733 "cloud filter type is changed from 0x%x to 0x%x",
7734 filter_replace.old_filter_type,
7735 filter_replace.new_filter_type);
7741 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7742 struct i40e_tunnel_filter_conf *tunnel_filter,
7746 uint32_t ipv4_addr, ipv4_addr_le;
7747 uint8_t i, tun_type = 0;
7748 /* internal variable to convert ipv6 byte order */
7749 uint32_t convert_ipv6[4];
7751 struct i40e_pf_vf *vf = NULL;
7752 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7753 struct i40e_vsi *vsi;
7754 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7755 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7756 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7757 struct i40e_tunnel_filter *tunnel, *node;
7758 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7760 bool big_buffer = 0;
7762 cld_filter = rte_zmalloc("tunnel_filter",
7763 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7766 if (cld_filter == NULL) {
7767 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7770 pfilter = cld_filter;
7772 ether_addr_copy(&tunnel_filter->outer_mac,
7773 (struct ether_addr *)&pfilter->element.outer_mac);
7774 ether_addr_copy(&tunnel_filter->inner_mac,
7775 (struct ether_addr *)&pfilter->element.inner_mac);
7777 pfilter->element.inner_vlan =
7778 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7779 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7780 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7781 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7782 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7783 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7785 sizeof(pfilter->element.ipaddr.v4.data));
7787 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7788 for (i = 0; i < 4; i++) {
7790 rte_cpu_to_le_32(rte_be_to_cpu_32(
7791 tunnel_filter->ip_addr.ipv6_addr[i]));
7793 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7795 sizeof(pfilter->element.ipaddr.v6.data));
7798 /* check tunneled type */
7799 switch (tunnel_filter->tunnel_type) {
7800 case I40E_TUNNEL_TYPE_VXLAN:
7801 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7803 case I40E_TUNNEL_TYPE_NVGRE:
7804 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7806 case I40E_TUNNEL_TYPE_IP_IN_GRE:
7807 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7809 case I40E_TUNNEL_TYPE_MPLSoUDP:
7810 if (!pf->mpls_replace_flag) {
7811 i40e_replace_mpls_l1_filter(pf);
7812 i40e_replace_mpls_cloud_filter(pf);
7813 pf->mpls_replace_flag = 1;
7815 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7816 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7818 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7819 (teid_le & 0xF) << 12;
7820 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7823 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
7825 case I40E_TUNNEL_TYPE_MPLSoGRE:
7826 if (!pf->mpls_replace_flag) {
7827 i40e_replace_mpls_l1_filter(pf);
7828 i40e_replace_mpls_cloud_filter(pf);
7829 pf->mpls_replace_flag = 1;
7831 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7832 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7834 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7835 (teid_le & 0xF) << 12;
7836 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7839 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
7841 case I40E_TUNNEL_TYPE_GTPC:
7842 if (!pf->gtp_replace_flag) {
7843 i40e_replace_gtp_l1_filter(pf);
7844 i40e_replace_gtp_cloud_filter(pf);
7845 pf->gtp_replace_flag = 1;
7847 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7848 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
7849 (teid_le >> 16) & 0xFFFF;
7850 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
7852 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
7856 case I40E_TUNNEL_TYPE_GTPU:
7857 if (!pf->gtp_replace_flag) {
7858 i40e_replace_gtp_l1_filter(pf);
7859 i40e_replace_gtp_cloud_filter(pf);
7860 pf->gtp_replace_flag = 1;
7862 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7863 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
7864 (teid_le >> 16) & 0xFFFF;
7865 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
7867 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
7871 case I40E_TUNNEL_TYPE_QINQ:
7872 if (!pf->qinq_replace_flag) {
7873 ret = i40e_cloud_filter_qinq_create(pf);
7876 "QinQ tunnel filter already created.");
7877 pf->qinq_replace_flag = 1;
7879 /* Add in the General fields the values of
7880 * the Outer and Inner VLAN
7881 * Big Buffer should be set, see changes in
7882 * i40e_aq_add_cloud_filters
7884 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7885 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7889 /* Other tunnel types is not supported. */
7890 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7891 rte_free(cld_filter);
7895 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7896 pfilter->element.flags =
7897 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7898 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7899 pfilter->element.flags =
7900 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7901 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
7902 pfilter->element.flags =
7903 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7904 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
7905 pfilter->element.flags =
7906 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7907 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7908 pfilter->element.flags |=
7909 I40E_AQC_ADD_CLOUD_FILTER_0X10;
7911 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7912 &pfilter->element.flags);
7914 rte_free(cld_filter);
7919 pfilter->element.flags |= rte_cpu_to_le_16(
7920 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7921 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7922 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7923 pfilter->element.queue_number =
7924 rte_cpu_to_le_16(tunnel_filter->queue_id);
7926 if (!tunnel_filter->is_to_vf)
7929 if (tunnel_filter->vf_id >= pf->vf_num) {
7930 PMD_DRV_LOG(ERR, "Invalid argument.");
7931 rte_free(cld_filter);
7934 vf = &pf->vfs[tunnel_filter->vf_id];
7938 /* Check if there is the filter in SW list */
7939 memset(&check_filter, 0, sizeof(check_filter));
7940 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7941 check_filter.is_to_vf = tunnel_filter->is_to_vf;
7942 check_filter.vf_id = tunnel_filter->vf_id;
7943 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7945 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7946 rte_free(cld_filter);
7950 if (!add && !node) {
7951 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7952 rte_free(cld_filter);
7958 ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7959 vsi->seid, cld_filter, 1);
7961 ret = i40e_aq_add_cloud_filters(hw,
7962 vsi->seid, &cld_filter->element, 1);
7964 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7965 rte_free(cld_filter);
7968 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7969 if (tunnel == NULL) {
7970 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7971 rte_free(cld_filter);
7975 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7976 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7981 ret = i40e_aq_remove_cloud_filters_big_buffer(
7982 hw, vsi->seid, cld_filter, 1);
7984 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7985 &cld_filter->element, 1);
7987 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7988 rte_free(cld_filter);
7991 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7994 rte_free(cld_filter);
7999 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8003 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8004 if (pf->vxlan_ports[i] == port)
8012 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
8016 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8018 idx = i40e_get_vxlan_port_idx(pf, port);
8020 /* Check if port already exists */
8022 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8026 /* Now check if there is space to add the new port */
8027 idx = i40e_get_vxlan_port_idx(pf, 0);
8030 "Maximum number of UDP ports reached, not adding port %d",
8035 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
8038 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8042 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8045 /* New port: add it and mark its index in the bitmap */
8046 pf->vxlan_ports[idx] = port;
8047 pf->vxlan_bitmap |= (1 << idx);
8049 if (!(pf->flags & I40E_FLAG_VXLAN))
8050 pf->flags |= I40E_FLAG_VXLAN;
8056 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8059 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8061 if (!(pf->flags & I40E_FLAG_VXLAN)) {
8062 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8066 idx = i40e_get_vxlan_port_idx(pf, port);
8069 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8073 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8074 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8078 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8081 pf->vxlan_ports[idx] = 0;
8082 pf->vxlan_bitmap &= ~(1 << idx);
8084 if (!pf->vxlan_bitmap)
8085 pf->flags &= ~I40E_FLAG_VXLAN;
8090 /* Add UDP tunneling port */
8092 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8093 struct rte_eth_udp_tunnel *udp_tunnel)
8096 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8098 if (udp_tunnel == NULL)
8101 switch (udp_tunnel->prot_type) {
8102 case RTE_TUNNEL_TYPE_VXLAN:
8103 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
8106 case RTE_TUNNEL_TYPE_GENEVE:
8107 case RTE_TUNNEL_TYPE_TEREDO:
8108 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8113 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8121 /* Remove UDP tunneling port */
8123 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8124 struct rte_eth_udp_tunnel *udp_tunnel)
8127 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8129 if (udp_tunnel == NULL)
8132 switch (udp_tunnel->prot_type) {
8133 case RTE_TUNNEL_TYPE_VXLAN:
8134 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8136 case RTE_TUNNEL_TYPE_GENEVE:
8137 case RTE_TUNNEL_TYPE_TEREDO:
8138 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8142 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8150 /* Calculate the maximum number of contiguous PF queues that are configured */
8152 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8154 struct rte_eth_dev_data *data = pf->dev_data;
8156 struct i40e_rx_queue *rxq;
8159 for (i = 0; i < pf->lan_nb_qps; i++) {
8160 rxq = data->rx_queues[i];
8161 if (rxq && rxq->q_set)
8172 i40e_pf_config_rss(struct i40e_pf *pf)
8174 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8175 struct rte_eth_rss_conf rss_conf;
8176 uint32_t i, lut = 0;
8180 * If both VMDQ and RSS enabled, not all of PF queues are configured.
8181 * It's necessary to calculate the actual PF queues that are configured.
8183 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8184 num = i40e_pf_calc_configured_queues_num(pf);
8186 num = pf->dev_data->nb_rx_queues;
8188 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8189 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8193 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
8197 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8200 lut = (lut << 8) | (j & ((0x1 <<
8201 hw->func_caps.rss_table_entry_width) - 1));
8203 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
8206 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8207 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8208 i40e_pf_disable_rss(pf);
8211 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8212 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8213 /* Random default keys */
8214 static uint32_t rss_key_default[] = {0x6b793944,
8215 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8216 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8217 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8219 rss_conf.rss_key = (uint8_t *)rss_key_default;
8220 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8224 return i40e_hw_rss_hash_set(pf, &rss_conf);
8228 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8229 struct rte_eth_tunnel_filter_conf *filter)
8231 if (pf == NULL || filter == NULL) {
8232 PMD_DRV_LOG(ERR, "Invalid parameter");
8236 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8237 PMD_DRV_LOG(ERR, "Invalid queue ID");
8241 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
8242 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8246 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8247 (is_zero_ether_addr(&filter->outer_mac))) {
8248 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8252 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8253 (is_zero_ether_addr(&filter->inner_mac))) {
8254 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8261 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8262 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
8264 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8266 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8270 if (pf->support_multi_driver) {
8271 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8275 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8276 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8279 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8280 } else if (len == 4) {
8281 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8283 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8288 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
8292 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8293 "with value 0x%08x",
8294 I40E_GL_PRS_FVBM(2), reg);
8295 i40e_global_cfg_warning(I40E_WARNING_GRE_KEY_LEN);
8299 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8300 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8306 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8313 switch (cfg->cfg_type) {
8314 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8315 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8318 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8326 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8327 enum rte_filter_op filter_op,
8330 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8331 int ret = I40E_ERR_PARAM;
8333 switch (filter_op) {
8334 case RTE_ETH_FILTER_SET:
8335 ret = i40e_dev_global_config_set(hw,
8336 (struct rte_eth_global_cfg *)arg);
8339 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8347 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8348 enum rte_filter_op filter_op,
8351 struct rte_eth_tunnel_filter_conf *filter;
8352 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8353 int ret = I40E_SUCCESS;
8355 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8357 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8358 return I40E_ERR_PARAM;
8360 switch (filter_op) {
8361 case RTE_ETH_FILTER_NOP:
8362 if (!(pf->flags & I40E_FLAG_VXLAN))
8363 ret = I40E_NOT_SUPPORTED;
8365 case RTE_ETH_FILTER_ADD:
8366 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8368 case RTE_ETH_FILTER_DELETE:
8369 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8372 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8373 ret = I40E_ERR_PARAM;
8381 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8384 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8387 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8388 ret = i40e_pf_config_rss(pf);
8390 i40e_pf_disable_rss(pf);
8395 /* Get the symmetric hash enable configurations per port */
8397 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8399 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8401 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8404 /* Set the symmetric hash enable configurations per port */
8406 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8408 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8411 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8413 "Symmetric hash has already been enabled");
8416 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8418 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8420 "Symmetric hash has already been disabled");
8423 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8425 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8426 I40E_WRITE_FLUSH(hw);
8430 * Get global configurations of hash function type and symmetric hash enable
8431 * per flow type (pctype). Note that global configuration means it affects all
8432 * the ports on the same NIC.
8435 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8436 struct rte_eth_hash_global_conf *g_cfg)
8438 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8442 memset(g_cfg, 0, sizeof(*g_cfg));
8443 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8444 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8445 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8447 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8448 PMD_DRV_LOG(DEBUG, "Hash function is %s",
8449 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8452 * As i40e supports less than 64 flow types, only first 64 bits need to
8455 for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8456 g_cfg->valid_bit_mask[i] = 0ULL;
8457 g_cfg->sym_hash_enable_mask[i] = 0ULL;
8460 g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
8462 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
8463 if (!adapter->pctypes_tbl[i])
8465 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8466 j < I40E_FILTER_PCTYPE_MAX; j++) {
8467 if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8468 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8469 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8470 g_cfg->sym_hash_enable_mask[0] |=
8481 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8482 const struct rte_eth_hash_global_conf *g_cfg)
8485 uint64_t mask0, i40e_mask = adapter->flow_types_mask;
8487 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8488 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8489 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8490 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8496 * As i40e supports less than 64 flow types, only first 64 bits need to
8499 mask0 = g_cfg->valid_bit_mask[0];
8500 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8502 /* Check if any unsupported flow type configured */
8503 if ((mask0 | i40e_mask) ^ i40e_mask)
8506 if (g_cfg->valid_bit_mask[i])
8514 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8520 * Set global configurations of hash function type and symmetric hash enable
8521 * per flow type (pctype). Note any modifying global configuration will affect
8522 * all the ports on the same NIC.
8525 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8526 struct rte_eth_hash_global_conf *g_cfg)
8528 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8529 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8533 uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
8535 if (pf->support_multi_driver) {
8536 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
8540 /* Check the input parameters */
8541 ret = i40e_hash_global_config_check(adapter, g_cfg);
8546 * As i40e supports less than 64 flow types, only first 64 bits need to
8549 for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
8550 if (mask0 & (1UL << i)) {
8551 reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
8552 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8554 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8555 j < I40E_FILTER_PCTYPE_MAX; j++) {
8556 if (adapter->pctypes_tbl[i] & (1ULL << j))
8557 i40e_write_global_rx_ctl(hw,
8561 i40e_global_cfg_warning(I40E_WARNING_HSYM);
8565 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8566 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8568 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8570 "Hash function already set to Toeplitz");
8573 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8574 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8576 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8578 "Hash function already set to Simple XOR");
8581 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8583 /* Use the default, and keep it as it is */
8586 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
8587 i40e_global_cfg_warning(I40E_WARNING_QF_CTL);
8590 I40E_WRITE_FLUSH(hw);
8596 * Valid input sets for hash and flow director filters per PCTYPE
8599 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8600 enum rte_filter_type filter)
8604 static const uint64_t valid_hash_inset_table[] = {
8605 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8606 I40E_INSET_DMAC | I40E_INSET_SMAC |
8607 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8608 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8609 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8610 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8611 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8612 I40E_INSET_FLEX_PAYLOAD,
8613 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8614 I40E_INSET_DMAC | I40E_INSET_SMAC |
8615 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8616 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8617 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8618 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8619 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8620 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8621 I40E_INSET_FLEX_PAYLOAD,
8622 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8623 I40E_INSET_DMAC | I40E_INSET_SMAC |
8624 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8625 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8626 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8627 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8628 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8629 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8630 I40E_INSET_FLEX_PAYLOAD,
8631 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8632 I40E_INSET_DMAC | I40E_INSET_SMAC |
8633 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8634 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8635 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8636 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8637 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8638 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8639 I40E_INSET_FLEX_PAYLOAD,
8640 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8641 I40E_INSET_DMAC | I40E_INSET_SMAC |
8642 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8643 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8644 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8645 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8646 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8647 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8648 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8649 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8650 I40E_INSET_DMAC | I40E_INSET_SMAC |
8651 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8652 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8653 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8654 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8655 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8656 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8657 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8658 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8659 I40E_INSET_DMAC | I40E_INSET_SMAC |
8660 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8661 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8662 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8663 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8664 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8665 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8666 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8667 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8668 I40E_INSET_DMAC | I40E_INSET_SMAC |
8669 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8670 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8671 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8672 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8673 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8674 I40E_INSET_FLEX_PAYLOAD,
8675 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8676 I40E_INSET_DMAC | I40E_INSET_SMAC |
8677 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8678 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8679 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8680 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8681 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8682 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8683 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8684 I40E_INSET_DMAC | I40E_INSET_SMAC |
8685 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8686 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8687 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8688 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8689 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8690 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8691 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8692 I40E_INSET_DMAC | I40E_INSET_SMAC |
8693 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8694 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8695 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8696 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8697 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8698 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8699 I40E_INSET_FLEX_PAYLOAD,
8700 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8701 I40E_INSET_DMAC | I40E_INSET_SMAC |
8702 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8703 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8704 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8705 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8706 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8707 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8708 I40E_INSET_FLEX_PAYLOAD,
8709 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8710 I40E_INSET_DMAC | I40E_INSET_SMAC |
8711 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8712 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8713 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8714 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8715 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8716 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8717 I40E_INSET_FLEX_PAYLOAD,
8718 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8719 I40E_INSET_DMAC | I40E_INSET_SMAC |
8720 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8721 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8722 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8723 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8724 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8725 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8726 I40E_INSET_FLEX_PAYLOAD,
8727 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8728 I40E_INSET_DMAC | I40E_INSET_SMAC |
8729 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8730 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8731 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8732 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8733 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8734 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8735 I40E_INSET_FLEX_PAYLOAD,
8736 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8737 I40E_INSET_DMAC | I40E_INSET_SMAC |
8738 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8739 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8740 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8741 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8742 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8743 I40E_INSET_FLEX_PAYLOAD,
8744 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8745 I40E_INSET_DMAC | I40E_INSET_SMAC |
8746 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8747 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8748 I40E_INSET_FLEX_PAYLOAD,
8752 * Flow director supports only fields defined in
8753 * union rte_eth_fdir_flow.
8755 static const uint64_t valid_fdir_inset_table[] = {
8756 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8757 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8758 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8759 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8760 I40E_INSET_IPV4_TTL,
8761 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8762 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8763 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8764 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8765 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8766 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8767 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8768 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8769 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8770 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8771 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8772 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8773 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8774 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8775 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8776 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8777 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8778 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8779 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8780 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8781 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8782 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8783 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8784 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8785 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8786 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8787 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8788 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8789 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8790 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8792 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8793 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8794 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8795 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8796 I40E_INSET_IPV4_TTL,
8797 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8798 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8799 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8800 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8801 I40E_INSET_IPV6_HOP_LIMIT,
8802 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8803 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8804 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8805 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8806 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8807 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8808 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8809 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8810 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8811 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8812 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8813 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8814 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8815 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8816 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8817 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8818 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8819 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8820 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8821 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8822 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8823 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8824 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8825 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8826 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8827 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8828 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8829 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8830 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8831 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8833 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8834 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8835 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8836 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8837 I40E_INSET_IPV6_HOP_LIMIT,
8838 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8839 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8840 I40E_INSET_LAST_ETHER_TYPE,
8843 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8845 if (filter == RTE_ETH_FILTER_HASH)
8846 valid = valid_hash_inset_table[pctype];
8848 valid = valid_fdir_inset_table[pctype];
8854 * Validate if the input set is allowed for a specific PCTYPE
8857 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8858 enum rte_filter_type filter, uint64_t inset)
8862 valid = i40e_get_valid_input_set(pctype, filter);
8863 if (inset & (~valid))
8869 /* default input set fields combination per pctype */
8871 i40e_get_default_input_set(uint16_t pctype)
8873 static const uint64_t default_inset_table[] = {
8874 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8875 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8876 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8877 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8878 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8879 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8880 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8881 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8882 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8883 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8884 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8885 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8886 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8887 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8888 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8889 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8890 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8891 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8892 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8893 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8895 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8896 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8897 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8898 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8899 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8900 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8901 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8902 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8903 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8904 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8905 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8906 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8907 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8908 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8909 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8910 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8911 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8912 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8913 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8914 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8915 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8916 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8918 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8919 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8920 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8921 I40E_INSET_LAST_ETHER_TYPE,
8924 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8927 return default_inset_table[pctype];
8931 * Parse the input set from index to logical bit masks
8934 i40e_parse_input_set(uint64_t *inset,
8935 enum i40e_filter_pctype pctype,
8936 enum rte_eth_input_set_field *field,
8942 static const struct {
8943 enum rte_eth_input_set_field field;
8945 } inset_convert_table[] = {
8946 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8947 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8948 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8949 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8950 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8951 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8952 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8953 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8954 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8955 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8956 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8957 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8958 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8959 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8960 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8961 I40E_INSET_IPV6_NEXT_HDR},
8962 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8963 I40E_INSET_IPV6_HOP_LIMIT},
8964 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8965 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8966 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8967 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8968 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8969 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8970 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8971 I40E_INSET_SCTP_VT},
8972 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8973 I40E_INSET_TUNNEL_DMAC},
8974 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8975 I40E_INSET_VLAN_TUNNEL},
8976 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8977 I40E_INSET_TUNNEL_ID},
8978 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8979 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8980 I40E_INSET_FLEX_PAYLOAD_W1},
8981 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8982 I40E_INSET_FLEX_PAYLOAD_W2},
8983 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8984 I40E_INSET_FLEX_PAYLOAD_W3},
8985 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8986 I40E_INSET_FLEX_PAYLOAD_W4},
8987 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8988 I40E_INSET_FLEX_PAYLOAD_W5},
8989 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8990 I40E_INSET_FLEX_PAYLOAD_W6},
8991 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8992 I40E_INSET_FLEX_PAYLOAD_W7},
8993 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8994 I40E_INSET_FLEX_PAYLOAD_W8},
8997 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9000 /* Only one item allowed for default or all */
9002 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9003 *inset = i40e_get_default_input_set(pctype);
9005 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9006 *inset = I40E_INSET_NONE;
9011 for (i = 0, *inset = 0; i < size; i++) {
9012 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9013 if (field[i] == inset_convert_table[j].field) {
9014 *inset |= inset_convert_table[j].inset;
9019 /* It contains unsupported input set, return immediately */
9020 if (j == RTE_DIM(inset_convert_table))
9028 * Translate the input set from bit masks to register aware bit masks
9032 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9042 static const struct inset_map inset_map_common[] = {
9043 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9044 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9045 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9046 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9047 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9048 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9049 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9050 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9051 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9052 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9053 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9054 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9055 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9056 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9057 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9058 {I40E_INSET_TUNNEL_DMAC,
9059 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9060 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9061 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9062 {I40E_INSET_TUNNEL_SRC_PORT,
9063 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9064 {I40E_INSET_TUNNEL_DST_PORT,
9065 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9066 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9067 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9068 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9069 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9070 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9071 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9072 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9073 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9074 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9077 /* some different registers map in x722*/
9078 static const struct inset_map inset_map_diff_x722[] = {
9079 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9080 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9081 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9082 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9085 static const struct inset_map inset_map_diff_not_x722[] = {
9086 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9087 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9088 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9089 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9095 /* Translate input set to register aware inset */
9096 if (type == I40E_MAC_X722) {
9097 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9098 if (input & inset_map_diff_x722[i].inset)
9099 val |= inset_map_diff_x722[i].inset_reg;
9102 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9103 if (input & inset_map_diff_not_x722[i].inset)
9104 val |= inset_map_diff_not_x722[i].inset_reg;
9108 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9109 if (input & inset_map_common[i].inset)
9110 val |= inset_map_common[i].inset_reg;
9117 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9120 uint64_t inset_need_mask = inset;
9122 static const struct {
9125 } inset_mask_map[] = {
9126 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9127 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9128 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9129 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9130 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9131 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9132 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9133 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9136 if (!inset || !mask || !nb_elem)
9139 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9140 /* Clear the inset bit, if no MASK is required,
9141 * for example proto + ttl
9143 if ((inset & inset_mask_map[i].inset) ==
9144 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9145 inset_need_mask &= ~inset_mask_map[i].inset;
9146 if (!inset_need_mask)
9149 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9150 if ((inset_need_mask & inset_mask_map[i].inset) ==
9151 inset_mask_map[i].inset) {
9152 if (idx >= nb_elem) {
9153 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9156 mask[idx] = inset_mask_map[i].mask;
9165 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9167 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9169 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9171 i40e_write_rx_ctl(hw, addr, val);
9172 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9173 (uint32_t)i40e_read_rx_ctl(hw, addr));
9177 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9179 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9181 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9183 i40e_write_global_rx_ctl(hw, addr, val);
9184 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9185 (uint32_t)i40e_read_rx_ctl(hw, addr));
9189 i40e_filter_input_set_init(struct i40e_pf *pf)
9191 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9192 enum i40e_filter_pctype pctype;
9193 uint64_t input_set, inset_reg;
9194 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9198 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9199 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9200 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9202 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9205 input_set = i40e_get_default_input_set(pctype);
9207 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9208 I40E_INSET_MASK_NUM_REG);
9211 if (pf->support_multi_driver && num > 0) {
9212 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9215 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9218 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9219 (uint32_t)(inset_reg & UINT32_MAX));
9220 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9221 (uint32_t)((inset_reg >>
9222 I40E_32_BIT_WIDTH) & UINT32_MAX));
9223 if (!pf->support_multi_driver) {
9224 i40e_check_write_global_reg(hw,
9225 I40E_GLQF_HASH_INSET(0, pctype),
9226 (uint32_t)(inset_reg & UINT32_MAX));
9227 i40e_check_write_global_reg(hw,
9228 I40E_GLQF_HASH_INSET(1, pctype),
9229 (uint32_t)((inset_reg >>
9230 I40E_32_BIT_WIDTH) & UINT32_MAX));
9232 for (i = 0; i < num; i++) {
9233 i40e_check_write_global_reg(hw,
9234 I40E_GLQF_FD_MSK(i, pctype),
9236 i40e_check_write_global_reg(hw,
9237 I40E_GLQF_HASH_MSK(i, pctype),
9240 /*clear unused mask registers of the pctype */
9241 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9242 i40e_check_write_global_reg(hw,
9243 I40E_GLQF_FD_MSK(i, pctype),
9245 i40e_check_write_global_reg(hw,
9246 I40E_GLQF_HASH_MSK(i, pctype),
9250 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9252 I40E_WRITE_FLUSH(hw);
9254 /* store the default input set */
9255 if (!pf->support_multi_driver)
9256 pf->hash_input_set[pctype] = input_set;
9257 pf->fdir.input_set[pctype] = input_set;
9260 if (!pf->support_multi_driver) {
9261 i40e_global_cfg_warning(I40E_WARNING_HASH_INSET);
9262 i40e_global_cfg_warning(I40E_WARNING_FD_MSK);
9263 i40e_global_cfg_warning(I40E_WARNING_HASH_MSK);
9268 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9269 struct rte_eth_input_set_conf *conf)
9271 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9272 enum i40e_filter_pctype pctype;
9273 uint64_t input_set, inset_reg = 0;
9274 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9278 PMD_DRV_LOG(ERR, "Invalid pointer");
9281 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9282 conf->op != RTE_ETH_INPUT_SET_ADD) {
9283 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9287 if (pf->support_multi_driver) {
9288 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9292 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9293 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9294 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9298 if (hw->mac.type == I40E_MAC_X722) {
9299 /* get translated pctype value in fd pctype register */
9300 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9301 I40E_GLQF_FD_PCTYPES((int)pctype));
9304 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9307 PMD_DRV_LOG(ERR, "Failed to parse input set");
9311 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9312 /* get inset value in register */
9313 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9314 inset_reg <<= I40E_32_BIT_WIDTH;
9315 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9316 input_set |= pf->hash_input_set[pctype];
9318 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9319 I40E_INSET_MASK_NUM_REG);
9323 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9325 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9326 (uint32_t)(inset_reg & UINT32_MAX));
9327 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9328 (uint32_t)((inset_reg >>
9329 I40E_32_BIT_WIDTH) & UINT32_MAX));
9330 i40e_global_cfg_warning(I40E_WARNING_HASH_INSET);
9332 for (i = 0; i < num; i++)
9333 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9335 /*clear unused mask registers of the pctype */
9336 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9337 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9339 i40e_global_cfg_warning(I40E_WARNING_HASH_MSK);
9340 I40E_WRITE_FLUSH(hw);
9342 pf->hash_input_set[pctype] = input_set;
9347 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9348 struct rte_eth_input_set_conf *conf)
9350 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9351 enum i40e_filter_pctype pctype;
9352 uint64_t input_set, inset_reg = 0;
9353 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9357 PMD_DRV_LOG(ERR, "Invalid pointer");
9360 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9361 conf->op != RTE_ETH_INPUT_SET_ADD) {
9362 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9366 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9368 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9369 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9373 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9376 PMD_DRV_LOG(ERR, "Failed to parse input set");
9380 /* get inset value in register */
9381 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9382 inset_reg <<= I40E_32_BIT_WIDTH;
9383 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9385 /* Can not change the inset reg for flex payload for fdir,
9386 * it is done by writing I40E_PRTQF_FD_FLXINSET
9387 * in i40e_set_flex_mask_on_pctype.
9389 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9390 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9392 input_set |= pf->fdir.input_set[pctype];
9393 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9394 I40E_INSET_MASK_NUM_REG);
9397 if (pf->support_multi_driver && num > 0) {
9398 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9402 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9404 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9405 (uint32_t)(inset_reg & UINT32_MAX));
9406 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9407 (uint32_t)((inset_reg >>
9408 I40E_32_BIT_WIDTH) & UINT32_MAX));
9410 if (!pf->support_multi_driver) {
9411 for (i = 0; i < num; i++)
9412 i40e_check_write_global_reg(hw,
9413 I40E_GLQF_FD_MSK(i, pctype),
9415 /*clear unused mask registers of the pctype */
9416 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9417 i40e_check_write_global_reg(hw,
9418 I40E_GLQF_FD_MSK(i, pctype),
9420 i40e_global_cfg_warning(I40E_WARNING_FD_MSK);
9422 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9424 I40E_WRITE_FLUSH(hw);
9426 pf->fdir.input_set[pctype] = input_set;
9431 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9436 PMD_DRV_LOG(ERR, "Invalid pointer");
9440 switch (info->info_type) {
9441 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9442 i40e_get_symmetric_hash_enable_per_port(hw,
9443 &(info->info.enable));
9445 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9446 ret = i40e_get_hash_filter_global_config(hw,
9447 &(info->info.global_conf));
9450 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9460 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9465 PMD_DRV_LOG(ERR, "Invalid pointer");
9469 switch (info->info_type) {
9470 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9471 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9473 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9474 ret = i40e_set_hash_filter_global_config(hw,
9475 &(info->info.global_conf));
9477 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9478 ret = i40e_hash_filter_inset_select(hw,
9479 &(info->info.input_set_conf));
9483 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9492 /* Operations for hash function */
9494 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9495 enum rte_filter_op filter_op,
9498 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9501 switch (filter_op) {
9502 case RTE_ETH_FILTER_NOP:
9504 case RTE_ETH_FILTER_GET:
9505 ret = i40e_hash_filter_get(hw,
9506 (struct rte_eth_hash_filter_info *)arg);
9508 case RTE_ETH_FILTER_SET:
9509 ret = i40e_hash_filter_set(hw,
9510 (struct rte_eth_hash_filter_info *)arg);
9513 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9522 /* Convert ethertype filter structure */
9524 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9525 struct i40e_ethertype_filter *filter)
9527 rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
9528 filter->input.ether_type = input->ether_type;
9529 filter->flags = input->flags;
9530 filter->queue = input->queue;
9535 /* Check if there exists the ehtertype filter */
9536 struct i40e_ethertype_filter *
9537 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9538 const struct i40e_ethertype_filter_input *input)
9542 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9546 return ethertype_rule->hash_map[ret];
9549 /* Add ethertype filter in SW list */
9551 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9552 struct i40e_ethertype_filter *filter)
9554 struct i40e_ethertype_rule *rule = &pf->ethertype;
9557 ret = rte_hash_add_key(rule->hash_table, &filter->input);
9560 "Failed to insert ethertype filter"
9561 " to hash table %d!",
9565 rule->hash_map[ret] = filter;
9567 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9572 /* Delete ethertype filter in SW list */
9574 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9575 struct i40e_ethertype_filter_input *input)
9577 struct i40e_ethertype_rule *rule = &pf->ethertype;
9578 struct i40e_ethertype_filter *filter;
9581 ret = rte_hash_del_key(rule->hash_table, input);
9584 "Failed to delete ethertype filter"
9585 " to hash table %d!",
9589 filter = rule->hash_map[ret];
9590 rule->hash_map[ret] = NULL;
9592 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9599 * Configure ethertype filter, which can director packet by filtering
9600 * with mac address and ether_type or only ether_type
9603 i40e_ethertype_filter_set(struct i40e_pf *pf,
9604 struct rte_eth_ethertype_filter *filter,
9607 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9608 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9609 struct i40e_ethertype_filter *ethertype_filter, *node;
9610 struct i40e_ethertype_filter check_filter;
9611 struct i40e_control_filter_stats stats;
9615 if (filter->queue >= pf->dev_data->nb_rx_queues) {
9616 PMD_DRV_LOG(ERR, "Invalid queue ID");
9619 if (filter->ether_type == ETHER_TYPE_IPv4 ||
9620 filter->ether_type == ETHER_TYPE_IPv6) {
9622 "unsupported ether_type(0x%04x) in control packet filter.",
9623 filter->ether_type);
9626 if (filter->ether_type == ETHER_TYPE_VLAN)
9627 PMD_DRV_LOG(WARNING,
9628 "filter vlan ether_type in first tag is not supported.");
9630 /* Check if there is the filter in SW list */
9631 memset(&check_filter, 0, sizeof(check_filter));
9632 i40e_ethertype_filter_convert(filter, &check_filter);
9633 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9634 &check_filter.input);
9636 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9640 if (!add && !node) {
9641 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9645 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9646 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9647 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9648 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9649 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9651 memset(&stats, 0, sizeof(stats));
9652 ret = i40e_aq_add_rem_control_packet_filter(hw,
9653 filter->mac_addr.addr_bytes,
9654 filter->ether_type, flags,
9656 filter->queue, add, &stats, NULL);
9659 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9660 ret, stats.mac_etype_used, stats.etype_used,
9661 stats.mac_etype_free, stats.etype_free);
9665 /* Add or delete a filter in SW list */
9667 ethertype_filter = rte_zmalloc("ethertype_filter",
9668 sizeof(*ethertype_filter), 0);
9669 if (ethertype_filter == NULL) {
9670 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
9674 rte_memcpy(ethertype_filter, &check_filter,
9675 sizeof(check_filter));
9676 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9678 rte_free(ethertype_filter);
9680 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9687 * Handle operations for ethertype filter.
9690 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9691 enum rte_filter_op filter_op,
9694 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9697 if (filter_op == RTE_ETH_FILTER_NOP)
9701 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9706 switch (filter_op) {
9707 case RTE_ETH_FILTER_ADD:
9708 ret = i40e_ethertype_filter_set(pf,
9709 (struct rte_eth_ethertype_filter *)arg,
9712 case RTE_ETH_FILTER_DELETE:
9713 ret = i40e_ethertype_filter_set(pf,
9714 (struct rte_eth_ethertype_filter *)arg,
9718 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9726 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9727 enum rte_filter_type filter_type,
9728 enum rte_filter_op filter_op,
9736 switch (filter_type) {
9737 case RTE_ETH_FILTER_NONE:
9738 /* For global configuration */
9739 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9741 case RTE_ETH_FILTER_HASH:
9742 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9744 case RTE_ETH_FILTER_MACVLAN:
9745 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9747 case RTE_ETH_FILTER_ETHERTYPE:
9748 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9750 case RTE_ETH_FILTER_TUNNEL:
9751 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9753 case RTE_ETH_FILTER_FDIR:
9754 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9756 case RTE_ETH_FILTER_GENERIC:
9757 if (filter_op != RTE_ETH_FILTER_GET)
9759 *(const void **)arg = &i40e_flow_ops;
9762 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9772 * Check and enable Extended Tag.
9773 * Enabling Extended Tag is important for 40G performance.
9776 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9778 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9782 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9785 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9789 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9790 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9795 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9798 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9802 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9803 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9806 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9807 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9810 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9817 * As some registers wouldn't be reset unless a global hardware reset,
9818 * hardware initialization is needed to put those registers into an
9819 * expected initial state.
9822 i40e_hw_init(struct rte_eth_dev *dev)
9824 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9826 i40e_enable_extended_tag(dev);
9828 /* clear the PF Queue Filter control register */
9829 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9831 /* Disable symmetric hash per port */
9832 i40e_set_symmetric_hash_enable_per_port(hw, 0);
9836 * For X722 it is possible to have multiple pctypes mapped to the same flowtype
9837 * however this function will return only one highest pctype index,
9838 * which is not quite correct. This is known problem of i40e driver
9839 * and needs to be fixed later.
9841 enum i40e_filter_pctype
9842 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
9845 uint64_t pctype_mask;
9847 if (flow_type < I40E_FLOW_TYPE_MAX) {
9848 pctype_mask = adapter->pctypes_tbl[flow_type];
9849 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
9850 if (pctype_mask & (1ULL << i))
9851 return (enum i40e_filter_pctype)i;
9854 return I40E_FILTER_PCTYPE_INVALID;
9858 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
9859 enum i40e_filter_pctype pctype)
9862 uint64_t pctype_mask = 1ULL << pctype;
9864 for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
9866 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
9870 return RTE_ETH_FLOW_UNKNOWN;
9874 * On X710, performance number is far from the expectation on recent firmware
9875 * versions; on XL710, performance number is also far from the expectation on
9876 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9877 * mode is enabled and port MAC address is equal to the packet destination MAC
9878 * address. The fix for this issue may not be integrated in the following
9879 * firmware version. So the workaround in software driver is needed. It needs
9880 * to modify the initial values of 3 internal only registers for both X710 and
9881 * XL710. Note that the values for X710 or XL710 could be different, and the
9882 * workaround can be removed when it is fixed in firmware in the future.
9885 /* For both X710 and XL710 */
9886 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1 0x10000200
9887 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x203F0200
9888 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
9890 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9891 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
9894 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9895 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9898 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
9900 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
9901 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
9904 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9906 enum i40e_status_code status;
9907 struct i40e_aq_get_phy_abilities_resp phy_ab;
9911 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9915 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
9918 rte_delay_us(100000);
9920 status = i40e_aq_get_phy_capabilities(hw, false,
9921 true, &phy_ab, NULL);
9929 i40e_configure_registers(struct i40e_hw *hw)
9935 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9936 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9937 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9943 for (i = 0; i < RTE_DIM(reg_table); i++) {
9944 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9945 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9947 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9948 else /* For X710/XL710/XXV710 */
9949 if (hw->aq.fw_maj_ver < 6)
9951 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
9954 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
9957 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9958 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9960 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9961 else /* For X710/XL710/XXV710 */
9963 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9966 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9967 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9968 I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9970 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9973 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9976 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9979 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9983 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9984 reg_table[i].addr, reg);
9985 if (reg == reg_table[i].val)
9988 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9989 reg_table[i].val, NULL);
9992 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9993 reg_table[i].val, reg_table[i].addr);
9996 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9997 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10001 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
10002 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
10003 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
10004 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10006 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10011 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10012 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10016 /* Configure for double VLAN RX stripping */
10017 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10018 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10019 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10020 ret = i40e_aq_debug_write_register(hw,
10021 I40E_VSI_TSR(vsi->vsi_id),
10024 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10026 return I40E_ERR_CONFIG;
10030 /* Configure for double VLAN TX insertion */
10031 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10032 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10033 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10034 ret = i40e_aq_debug_write_register(hw,
10035 I40E_VSI_L2TAGSTXVALID(
10036 vsi->vsi_id), reg, NULL);
10039 "Failed to update VSI_L2TAGSTXVALID[%d]",
10041 return I40E_ERR_CONFIG;
10049 * i40e_aq_add_mirror_rule
10050 * @hw: pointer to the hardware structure
10051 * @seid: VEB seid to add mirror rule to
10052 * @dst_id: destination vsi seid
10053 * @entries: Buffer which contains the entities to be mirrored
10054 * @count: number of entities contained in the buffer
10055 * @rule_id:the rule_id of the rule to be added
10057 * Add a mirror rule for a given veb.
10060 static enum i40e_status_code
10061 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10062 uint16_t seid, uint16_t dst_id,
10063 uint16_t rule_type, uint16_t *entries,
10064 uint16_t count, uint16_t *rule_id)
10066 struct i40e_aq_desc desc;
10067 struct i40e_aqc_add_delete_mirror_rule cmd;
10068 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10069 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10072 enum i40e_status_code status;
10074 i40e_fill_default_direct_cmd_desc(&desc,
10075 i40e_aqc_opc_add_mirror_rule);
10076 memset(&cmd, 0, sizeof(cmd));
10078 buff_len = sizeof(uint16_t) * count;
10079 desc.datalen = rte_cpu_to_le_16(buff_len);
10081 desc.flags |= rte_cpu_to_le_16(
10082 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10083 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10084 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10085 cmd.num_entries = rte_cpu_to_le_16(count);
10086 cmd.seid = rte_cpu_to_le_16(seid);
10087 cmd.destination = rte_cpu_to_le_16(dst_id);
10089 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10090 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10092 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10093 hw->aq.asq_last_status, resp->rule_id,
10094 resp->mirror_rules_used, resp->mirror_rules_free);
10095 *rule_id = rte_le_to_cpu_16(resp->rule_id);
10101 * i40e_aq_del_mirror_rule
10102 * @hw: pointer to the hardware structure
10103 * @seid: VEB seid to add mirror rule to
10104 * @entries: Buffer which contains the entities to be mirrored
10105 * @count: number of entities contained in the buffer
10106 * @rule_id:the rule_id of the rule to be delete
10108 * Delete a mirror rule for a given veb.
10111 static enum i40e_status_code
10112 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10113 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10114 uint16_t count, uint16_t rule_id)
10116 struct i40e_aq_desc desc;
10117 struct i40e_aqc_add_delete_mirror_rule cmd;
10118 uint16_t buff_len = 0;
10119 enum i40e_status_code status;
10122 i40e_fill_default_direct_cmd_desc(&desc,
10123 i40e_aqc_opc_delete_mirror_rule);
10124 memset(&cmd, 0, sizeof(cmd));
10125 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10126 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10128 cmd.num_entries = count;
10129 buff_len = sizeof(uint16_t) * count;
10130 desc.datalen = rte_cpu_to_le_16(buff_len);
10131 buff = (void *)entries;
10133 /* rule id is filled in destination field for deleting mirror rule */
10134 cmd.destination = rte_cpu_to_le_16(rule_id);
10136 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10137 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10138 cmd.seid = rte_cpu_to_le_16(seid);
10140 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10141 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10147 * i40e_mirror_rule_set
10148 * @dev: pointer to the hardware structure
10149 * @mirror_conf: mirror rule info
10150 * @sw_id: mirror rule's sw_id
10151 * @on: enable/disable
10153 * set a mirror rule.
10157 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10158 struct rte_eth_mirror_conf *mirror_conf,
10159 uint8_t sw_id, uint8_t on)
10161 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10162 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10163 struct i40e_mirror_rule *it, *mirr_rule = NULL;
10164 struct i40e_mirror_rule *parent = NULL;
10165 uint16_t seid, dst_seid, rule_id;
10169 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10171 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10173 "mirror rule can not be configured without veb or vfs.");
10176 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10177 PMD_DRV_LOG(ERR, "mirror table is full.");
10180 if (mirror_conf->dst_pool > pf->vf_num) {
10181 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10182 mirror_conf->dst_pool);
10186 seid = pf->main_vsi->veb->seid;
10188 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10189 if (sw_id <= it->index) {
10195 if (mirr_rule && sw_id == mirr_rule->index) {
10197 PMD_DRV_LOG(ERR, "mirror rule exists.");
10200 ret = i40e_aq_del_mirror_rule(hw, seid,
10201 mirr_rule->rule_type,
10202 mirr_rule->entries,
10203 mirr_rule->num_entries, mirr_rule->id);
10206 "failed to remove mirror rule: ret = %d, aq_err = %d.",
10207 ret, hw->aq.asq_last_status);
10210 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10211 rte_free(mirr_rule);
10212 pf->nb_mirror_rule--;
10216 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10220 mirr_rule = rte_zmalloc("i40e_mirror_rule",
10221 sizeof(struct i40e_mirror_rule) , 0);
10223 PMD_DRV_LOG(ERR, "failed to allocate memory");
10224 return I40E_ERR_NO_MEMORY;
10226 switch (mirror_conf->rule_type) {
10227 case ETH_MIRROR_VLAN:
10228 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10229 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10230 mirr_rule->entries[j] =
10231 mirror_conf->vlan.vlan_id[i];
10236 PMD_DRV_LOG(ERR, "vlan is not specified.");
10237 rte_free(mirr_rule);
10240 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10242 case ETH_MIRROR_VIRTUAL_POOL_UP:
10243 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10244 /* check if the specified pool bit is out of range */
10245 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10246 PMD_DRV_LOG(ERR, "pool mask is out of range.");
10247 rte_free(mirr_rule);
10250 for (i = 0, j = 0; i < pf->vf_num; i++) {
10251 if (mirror_conf->pool_mask & (1ULL << i)) {
10252 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10256 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10257 /* add pf vsi to entries */
10258 mirr_rule->entries[j] = pf->main_vsi_seid;
10262 PMD_DRV_LOG(ERR, "pool is not specified.");
10263 rte_free(mirr_rule);
10266 /* egress and ingress in aq commands means from switch but not port */
10267 mirr_rule->rule_type =
10268 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10269 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10270 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10272 case ETH_MIRROR_UPLINK_PORT:
10273 /* egress and ingress in aq commands means from switch but not port*/
10274 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10276 case ETH_MIRROR_DOWNLINK_PORT:
10277 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10280 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10281 mirror_conf->rule_type);
10282 rte_free(mirr_rule);
10286 /* If the dst_pool is equal to vf_num, consider it as PF */
10287 if (mirror_conf->dst_pool == pf->vf_num)
10288 dst_seid = pf->main_vsi_seid;
10290 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10292 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10293 mirr_rule->rule_type, mirr_rule->entries,
10297 "failed to add mirror rule: ret = %d, aq_err = %d.",
10298 ret, hw->aq.asq_last_status);
10299 rte_free(mirr_rule);
10303 mirr_rule->index = sw_id;
10304 mirr_rule->num_entries = j;
10305 mirr_rule->id = rule_id;
10306 mirr_rule->dst_vsi_seid = dst_seid;
10309 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10311 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10313 pf->nb_mirror_rule++;
10318 * i40e_mirror_rule_reset
10319 * @dev: pointer to the device
10320 * @sw_id: mirror rule's sw_id
10322 * reset a mirror rule.
10326 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10328 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10329 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10330 struct i40e_mirror_rule *it, *mirr_rule = NULL;
10334 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10336 seid = pf->main_vsi->veb->seid;
10338 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10339 if (sw_id == it->index) {
10345 ret = i40e_aq_del_mirror_rule(hw, seid,
10346 mirr_rule->rule_type,
10347 mirr_rule->entries,
10348 mirr_rule->num_entries, mirr_rule->id);
10351 "failed to remove mirror rule: status = %d, aq_err = %d.",
10352 ret, hw->aq.asq_last_status);
10355 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10356 rte_free(mirr_rule);
10357 pf->nb_mirror_rule--;
10359 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10366 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10368 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10369 uint64_t systim_cycles;
10371 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10372 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10375 return systim_cycles;
10379 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10381 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10382 uint64_t rx_tstamp;
10384 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10385 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10392 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10394 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10395 uint64_t tx_tstamp;
10397 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10398 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10405 i40e_start_timecounters(struct rte_eth_dev *dev)
10407 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10408 struct i40e_adapter *adapter =
10409 (struct i40e_adapter *)dev->data->dev_private;
10410 struct rte_eth_link link;
10411 uint32_t tsync_inc_l;
10412 uint32_t tsync_inc_h;
10414 /* Get current link speed. */
10415 i40e_dev_link_update(dev, 1);
10416 rte_eth_linkstatus_get(dev, &link);
10418 switch (link.link_speed) {
10419 case ETH_SPEED_NUM_40G:
10420 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10421 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10423 case ETH_SPEED_NUM_10G:
10424 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10425 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10427 case ETH_SPEED_NUM_1G:
10428 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10429 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10436 /* Set the timesync increment value. */
10437 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10438 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10440 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10441 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10442 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10444 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10445 adapter->systime_tc.cc_shift = 0;
10446 adapter->systime_tc.nsec_mask = 0;
10448 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10449 adapter->rx_tstamp_tc.cc_shift = 0;
10450 adapter->rx_tstamp_tc.nsec_mask = 0;
10452 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10453 adapter->tx_tstamp_tc.cc_shift = 0;
10454 adapter->tx_tstamp_tc.nsec_mask = 0;
10458 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10460 struct i40e_adapter *adapter =
10461 (struct i40e_adapter *)dev->data->dev_private;
10463 adapter->systime_tc.nsec += delta;
10464 adapter->rx_tstamp_tc.nsec += delta;
10465 adapter->tx_tstamp_tc.nsec += delta;
10471 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10474 struct i40e_adapter *adapter =
10475 (struct i40e_adapter *)dev->data->dev_private;
10477 ns = rte_timespec_to_ns(ts);
10479 /* Set the timecounters to a new value. */
10480 adapter->systime_tc.nsec = ns;
10481 adapter->rx_tstamp_tc.nsec = ns;
10482 adapter->tx_tstamp_tc.nsec = ns;
10488 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10490 uint64_t ns, systime_cycles;
10491 struct i40e_adapter *adapter =
10492 (struct i40e_adapter *)dev->data->dev_private;
10494 systime_cycles = i40e_read_systime_cyclecounter(dev);
10495 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10496 *ts = rte_ns_to_timespec(ns);
10502 i40e_timesync_enable(struct rte_eth_dev *dev)
10504 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10505 uint32_t tsync_ctl_l;
10506 uint32_t tsync_ctl_h;
10508 /* Stop the timesync system time. */
10509 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10510 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10511 /* Reset the timesync system time value. */
10512 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10513 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10515 i40e_start_timecounters(dev);
10517 /* Clear timesync registers. */
10518 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10519 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10520 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10521 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10522 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10523 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10525 /* Enable timestamping of PTP packets. */
10526 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10527 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10529 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10530 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10531 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10533 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10534 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10540 i40e_timesync_disable(struct rte_eth_dev *dev)
10542 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10543 uint32_t tsync_ctl_l;
10544 uint32_t tsync_ctl_h;
10546 /* Disable timestamping of transmitted PTP packets. */
10547 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10548 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10550 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10551 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10553 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10554 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10556 /* Reset the timesync increment value. */
10557 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10558 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10564 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10565 struct timespec *timestamp, uint32_t flags)
10567 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10568 struct i40e_adapter *adapter =
10569 (struct i40e_adapter *)dev->data->dev_private;
10571 uint32_t sync_status;
10572 uint32_t index = flags & 0x03;
10573 uint64_t rx_tstamp_cycles;
10576 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10577 if ((sync_status & (1 << index)) == 0)
10580 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10581 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10582 *timestamp = rte_ns_to_timespec(ns);
10588 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10589 struct timespec *timestamp)
10591 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10592 struct i40e_adapter *adapter =
10593 (struct i40e_adapter *)dev->data->dev_private;
10595 uint32_t sync_status;
10596 uint64_t tx_tstamp_cycles;
10599 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10600 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10603 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10604 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10605 *timestamp = rte_ns_to_timespec(ns);
10611 * i40e_parse_dcb_configure - parse dcb configure from user
10612 * @dev: the device being configured
10613 * @dcb_cfg: pointer of the result of parse
10614 * @*tc_map: bit map of enabled traffic classes
10616 * Returns 0 on success, negative value on failure
10619 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10620 struct i40e_dcbx_config *dcb_cfg,
10623 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10624 uint8_t i, tc_bw, bw_lf;
10626 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10628 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10629 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10630 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10634 /* assume each tc has the same bw */
10635 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10636 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10637 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10638 /* to ensure the sum of tcbw is equal to 100 */
10639 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10640 for (i = 0; i < bw_lf; i++)
10641 dcb_cfg->etscfg.tcbwtable[i]++;
10643 /* assume each tc has the same Transmission Selection Algorithm */
10644 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10645 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10647 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10648 dcb_cfg->etscfg.prioritytable[i] =
10649 dcb_rx_conf->dcb_tc[i];
10651 /* FW needs one App to configure HW */
10652 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10653 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10654 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10655 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10657 if (dcb_rx_conf->nb_tcs == 0)
10658 *tc_map = 1; /* tc0 only */
10660 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10662 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10663 dcb_cfg->pfc.willing = 0;
10664 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10665 dcb_cfg->pfc.pfcenable = *tc_map;
10671 static enum i40e_status_code
10672 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10673 struct i40e_aqc_vsi_properties_data *info,
10674 uint8_t enabled_tcmap)
10676 enum i40e_status_code ret;
10677 int i, total_tc = 0;
10678 uint16_t qpnum_per_tc, bsf, qp_idx;
10679 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10680 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10681 uint16_t used_queues;
10683 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10684 if (ret != I40E_SUCCESS)
10687 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10688 if (enabled_tcmap & (1 << i))
10693 vsi->enabled_tc = enabled_tcmap;
10695 /* different VSI has different queues assigned */
10696 if (vsi->type == I40E_VSI_MAIN)
10697 used_queues = dev_data->nb_rx_queues -
10698 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10699 else if (vsi->type == I40E_VSI_VMDQ2)
10700 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10702 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10703 return I40E_ERR_NO_AVAILABLE_VSI;
10706 qpnum_per_tc = used_queues / total_tc;
10707 /* Number of queues per enabled TC */
10708 if (qpnum_per_tc == 0) {
10709 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10710 return I40E_ERR_INVALID_QP_ID;
10712 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10713 I40E_MAX_Q_PER_TC);
10714 bsf = rte_bsf32(qpnum_per_tc);
10717 * Configure TC and queue mapping parameters, for enabled TC,
10718 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10719 * default queue will serve it.
10722 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10723 if (vsi->enabled_tc & (1 << i)) {
10724 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10725 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10726 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10727 qp_idx += qpnum_per_tc;
10729 info->tc_mapping[i] = 0;
10732 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10733 if (vsi->type == I40E_VSI_SRIOV) {
10734 info->mapping_flags |=
10735 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10736 for (i = 0; i < vsi->nb_qps; i++)
10737 info->queue_mapping[i] =
10738 rte_cpu_to_le_16(vsi->base_queue + i);
10740 info->mapping_flags |=
10741 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10742 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10744 info->valid_sections |=
10745 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10747 return I40E_SUCCESS;
10751 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10752 * @veb: VEB to be configured
10753 * @tc_map: enabled TC bitmap
10755 * Returns 0 on success, negative value on failure
10757 static enum i40e_status_code
10758 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10760 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10761 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10762 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10763 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10764 enum i40e_status_code ret = I40E_SUCCESS;
10768 /* Check if enabled_tc is same as existing or new TCs */
10769 if (veb->enabled_tc == tc_map)
10772 /* configure tc bandwidth */
10773 memset(&veb_bw, 0, sizeof(veb_bw));
10774 veb_bw.tc_valid_bits = tc_map;
10775 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10776 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10777 if (tc_map & BIT_ULL(i))
10778 veb_bw.tc_bw_share_credits[i] = 1;
10780 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10784 "AQ command Config switch_comp BW allocation per TC failed = %d",
10785 hw->aq.asq_last_status);
10789 memset(&ets_query, 0, sizeof(ets_query));
10790 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10792 if (ret != I40E_SUCCESS) {
10794 "Failed to get switch_comp ETS configuration %u",
10795 hw->aq.asq_last_status);
10798 memset(&bw_query, 0, sizeof(bw_query));
10799 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10801 if (ret != I40E_SUCCESS) {
10803 "Failed to get switch_comp bandwidth configuration %u",
10804 hw->aq.asq_last_status);
10808 /* store and print out BW info */
10809 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10810 veb->bw_info.bw_max = ets_query.tc_bw_max;
10811 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10812 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10813 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10814 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10815 I40E_16_BIT_WIDTH);
10816 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10817 veb->bw_info.bw_ets_share_credits[i] =
10818 bw_query.tc_bw_share_credits[i];
10819 veb->bw_info.bw_ets_credits[i] =
10820 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10821 /* 4 bits per TC, 4th bit is reserved */
10822 veb->bw_info.bw_ets_max[i] =
10823 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10824 RTE_LEN2MASK(3, uint8_t));
10825 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10826 veb->bw_info.bw_ets_share_credits[i]);
10827 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10828 veb->bw_info.bw_ets_credits[i]);
10829 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10830 veb->bw_info.bw_ets_max[i]);
10833 veb->enabled_tc = tc_map;
10840 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10841 * @vsi: VSI to be configured
10842 * @tc_map: enabled TC bitmap
10844 * Returns 0 on success, negative value on failure
10846 static enum i40e_status_code
10847 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10849 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10850 struct i40e_vsi_context ctxt;
10851 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10852 enum i40e_status_code ret = I40E_SUCCESS;
10855 /* Check if enabled_tc is same as existing or new TCs */
10856 if (vsi->enabled_tc == tc_map)
10859 /* configure tc bandwidth */
10860 memset(&bw_data, 0, sizeof(bw_data));
10861 bw_data.tc_valid_bits = tc_map;
10862 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10863 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10864 if (tc_map & BIT_ULL(i))
10865 bw_data.tc_bw_credits[i] = 1;
10867 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10870 "AQ command Config VSI BW allocation per TC failed = %d",
10871 hw->aq.asq_last_status);
10874 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10875 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10877 /* Update Queue Pairs Mapping for currently enabled UPs */
10878 ctxt.seid = vsi->seid;
10879 ctxt.pf_num = hw->pf_id;
10881 ctxt.uplink_seid = vsi->uplink_seid;
10882 ctxt.info = vsi->info;
10884 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10888 /* Update the VSI after updating the VSI queue-mapping information */
10889 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10891 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10892 hw->aq.asq_last_status);
10895 /* update the local VSI info with updated queue map */
10896 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10897 sizeof(vsi->info.tc_mapping));
10898 rte_memcpy(&vsi->info.queue_mapping,
10899 &ctxt.info.queue_mapping,
10900 sizeof(vsi->info.queue_mapping));
10901 vsi->info.mapping_flags = ctxt.info.mapping_flags;
10902 vsi->info.valid_sections = 0;
10904 /* query and update current VSI BW information */
10905 ret = i40e_vsi_get_bw_config(vsi);
10908 "Failed updating vsi bw info, err %s aq_err %s",
10909 i40e_stat_str(hw, ret),
10910 i40e_aq_str(hw, hw->aq.asq_last_status));
10914 vsi->enabled_tc = tc_map;
10921 * i40e_dcb_hw_configure - program the dcb setting to hw
10922 * @pf: pf the configuration is taken on
10923 * @new_cfg: new configuration
10924 * @tc_map: enabled TC bitmap
10926 * Returns 0 on success, negative value on failure
10928 static enum i40e_status_code
10929 i40e_dcb_hw_configure(struct i40e_pf *pf,
10930 struct i40e_dcbx_config *new_cfg,
10933 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10934 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10935 struct i40e_vsi *main_vsi = pf->main_vsi;
10936 struct i40e_vsi_list *vsi_list;
10937 enum i40e_status_code ret;
10941 /* Use the FW API if FW > v4.4*/
10942 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10943 (hw->aq.fw_maj_ver >= 5))) {
10945 "FW < v4.4, can not use FW LLDP API to configure DCB");
10946 return I40E_ERR_FIRMWARE_API_VERSION;
10949 /* Check if need reconfiguration */
10950 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10951 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10952 return I40E_SUCCESS;
10955 /* Copy the new config to the current config */
10956 *old_cfg = *new_cfg;
10957 old_cfg->etsrec = old_cfg->etscfg;
10958 ret = i40e_set_dcb_config(hw);
10960 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10961 i40e_stat_str(hw, ret),
10962 i40e_aq_str(hw, hw->aq.asq_last_status));
10965 /* set receive Arbiter to RR mode and ETS scheme by default */
10966 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10967 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10968 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
10969 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10970 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10971 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10972 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10973 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10974 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10975 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10976 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10977 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10978 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10980 /* get local mib to check whether it is configured correctly */
10982 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10983 /* Get Local DCB Config */
10984 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10985 &hw->local_dcbx_config);
10987 /* if Veb is created, need to update TC of it at first */
10988 if (main_vsi->veb) {
10989 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10991 PMD_INIT_LOG(WARNING,
10992 "Failed configuring TC for VEB seid=%d",
10993 main_vsi->veb->seid);
10995 /* Update each VSI */
10996 i40e_vsi_config_tc(main_vsi, tc_map);
10997 if (main_vsi->veb) {
10998 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10999 /* Beside main VSI and VMDQ VSIs, only enable default
11000 * TC for other VSIs
11002 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11003 ret = i40e_vsi_config_tc(vsi_list->vsi,
11006 ret = i40e_vsi_config_tc(vsi_list->vsi,
11007 I40E_DEFAULT_TCMAP);
11009 PMD_INIT_LOG(WARNING,
11010 "Failed configuring TC for VSI seid=%d",
11011 vsi_list->vsi->seid);
11015 return I40E_SUCCESS;
11019 * i40e_dcb_init_configure - initial dcb config
11020 * @dev: device being configured
11021 * @sw_dcb: indicate whether dcb is sw configured or hw offload
11023 * Returns 0 on success, negative value on failure
11026 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11028 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11029 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11032 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11033 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11037 /* DCB initialization:
11038 * Update DCB configuration from the Firmware and configure
11039 * LLDP MIB change event.
11041 if (sw_dcb == TRUE) {
11042 ret = i40e_init_dcb(hw);
11043 /* If lldp agent is stopped, the return value from
11044 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11045 * adminq status. Otherwise, it should return success.
11047 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11048 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11049 memset(&hw->local_dcbx_config, 0,
11050 sizeof(struct i40e_dcbx_config));
11051 /* set dcb default configuration */
11052 hw->local_dcbx_config.etscfg.willing = 0;
11053 hw->local_dcbx_config.etscfg.maxtcs = 0;
11054 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11055 hw->local_dcbx_config.etscfg.tsatable[0] =
11057 /* all UPs mapping to TC0 */
11058 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11059 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11060 hw->local_dcbx_config.etsrec =
11061 hw->local_dcbx_config.etscfg;
11062 hw->local_dcbx_config.pfc.willing = 0;
11063 hw->local_dcbx_config.pfc.pfccap =
11064 I40E_MAX_TRAFFIC_CLASS;
11065 /* FW needs one App to configure HW */
11066 hw->local_dcbx_config.numapps = 1;
11067 hw->local_dcbx_config.app[0].selector =
11068 I40E_APP_SEL_ETHTYPE;
11069 hw->local_dcbx_config.app[0].priority = 3;
11070 hw->local_dcbx_config.app[0].protocolid =
11071 I40E_APP_PROTOID_FCOE;
11072 ret = i40e_set_dcb_config(hw);
11075 "default dcb config fails. err = %d, aq_err = %d.",
11076 ret, hw->aq.asq_last_status);
11081 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11082 ret, hw->aq.asq_last_status);
11086 ret = i40e_aq_start_lldp(hw, NULL);
11087 if (ret != I40E_SUCCESS)
11088 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11090 ret = i40e_init_dcb(hw);
11092 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11094 "HW doesn't support DCBX offload.");
11099 "DCBX configuration failed, err = %d, aq_err = %d.",
11100 ret, hw->aq.asq_last_status);
11108 * i40e_dcb_setup - setup dcb related config
11109 * @dev: device being configured
11111 * Returns 0 on success, negative value on failure
11114 i40e_dcb_setup(struct rte_eth_dev *dev)
11116 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11117 struct i40e_dcbx_config dcb_cfg;
11118 uint8_t tc_map = 0;
11121 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11122 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11126 if (pf->vf_num != 0)
11127 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11129 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11131 PMD_INIT_LOG(ERR, "invalid dcb config");
11134 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11136 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11144 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11145 struct rte_eth_dcb_info *dcb_info)
11147 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11148 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11149 struct i40e_vsi *vsi = pf->main_vsi;
11150 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11151 uint16_t bsf, tc_mapping;
11154 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11155 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11157 dcb_info->nb_tcs = 1;
11158 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11159 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11160 for (i = 0; i < dcb_info->nb_tcs; i++)
11161 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11163 /* get queue mapping if vmdq is disabled */
11164 if (!pf->nb_cfg_vmdq_vsi) {
11165 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11166 if (!(vsi->enabled_tc & (1 << i)))
11168 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11169 dcb_info->tc_queue.tc_rxq[j][i].base =
11170 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11171 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11172 dcb_info->tc_queue.tc_txq[j][i].base =
11173 dcb_info->tc_queue.tc_rxq[j][i].base;
11174 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11175 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11176 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11177 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11178 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11183 /* get queue mapping if vmdq is enabled */
11185 vsi = pf->vmdq[j].vsi;
11186 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11187 if (!(vsi->enabled_tc & (1 << i)))
11189 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11190 dcb_info->tc_queue.tc_rxq[j][i].base =
11191 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11192 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11193 dcb_info->tc_queue.tc_txq[j][i].base =
11194 dcb_info->tc_queue.tc_rxq[j][i].base;
11195 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11196 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11197 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11198 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11199 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11202 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11207 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11209 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11210 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11211 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11212 uint16_t msix_intr;
11214 msix_intr = intr_handle->intr_vec[queue_id];
11215 if (msix_intr == I40E_MISC_VEC_ID)
11216 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11217 I40E_PFINT_DYN_CTL0_INTENA_MASK |
11218 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11219 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11222 I40E_PFINT_DYN_CTLN(msix_intr -
11223 I40E_RX_VEC_START),
11224 I40E_PFINT_DYN_CTLN_INTENA_MASK |
11225 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11226 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11228 I40E_WRITE_FLUSH(hw);
11229 rte_intr_enable(&pci_dev->intr_handle);
11235 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11237 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11238 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11239 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11240 uint16_t msix_intr;
11242 msix_intr = intr_handle->intr_vec[queue_id];
11243 if (msix_intr == I40E_MISC_VEC_ID)
11244 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11245 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11248 I40E_PFINT_DYN_CTLN(msix_intr -
11249 I40E_RX_VEC_START),
11250 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11251 I40E_WRITE_FLUSH(hw);
11256 static int i40e_get_regs(struct rte_eth_dev *dev,
11257 struct rte_dev_reg_info *regs)
11259 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11260 uint32_t *ptr_data = regs->data;
11261 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11262 const struct i40e_reg_info *reg_info;
11264 if (ptr_data == NULL) {
11265 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11266 regs->width = sizeof(uint32_t);
11270 /* The first few registers have to be read using AQ operations */
11272 while (i40e_regs_adminq[reg_idx].name) {
11273 reg_info = &i40e_regs_adminq[reg_idx++];
11274 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11276 arr_idx2 <= reg_info->count2;
11278 reg_offset = arr_idx * reg_info->stride1 +
11279 arr_idx2 * reg_info->stride2;
11280 reg_offset += reg_info->base_addr;
11281 ptr_data[reg_offset >> 2] =
11282 i40e_read_rx_ctl(hw, reg_offset);
11286 /* The remaining registers can be read using primitives */
11288 while (i40e_regs_others[reg_idx].name) {
11289 reg_info = &i40e_regs_others[reg_idx++];
11290 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11292 arr_idx2 <= reg_info->count2;
11294 reg_offset = arr_idx * reg_info->stride1 +
11295 arr_idx2 * reg_info->stride2;
11296 reg_offset += reg_info->base_addr;
11297 ptr_data[reg_offset >> 2] =
11298 I40E_READ_REG(hw, reg_offset);
11305 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11307 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11309 /* Convert word count to byte count */
11310 return hw->nvm.sr_size << 1;
11313 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11314 struct rte_dev_eeprom_info *eeprom)
11316 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11317 uint16_t *data = eeprom->data;
11318 uint16_t offset, length, cnt_words;
11321 offset = eeprom->offset >> 1;
11322 length = eeprom->length >> 1;
11323 cnt_words = length;
11325 if (offset > hw->nvm.sr_size ||
11326 offset + length > hw->nvm.sr_size) {
11327 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11331 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11333 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11334 if (ret_code != I40E_SUCCESS || cnt_words != length) {
11335 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11342 static int i40e_get_module_info(struct rte_eth_dev *dev,
11343 struct rte_eth_dev_module_info *modinfo)
11345 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11346 uint32_t sff8472_comp = 0;
11347 uint32_t sff8472_swap = 0;
11348 uint32_t sff8636_rev = 0;
11349 i40e_status status;
11352 /* Check if firmware supports reading module EEPROM. */
11353 if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
11355 "Module EEPROM memory read not supported. "
11356 "Please update the NVM image.\n");
11360 status = i40e_update_link_info(hw);
11364 if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
11366 "Cannot read module EEPROM memory. "
11367 "No module connected.\n");
11371 type = hw->phy.link_info.module_type[0];
11374 case I40E_MODULE_TYPE_SFP:
11375 status = i40e_aq_get_phy_register(hw,
11376 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11377 I40E_I2C_EEPROM_DEV_ADDR,
11378 I40E_MODULE_SFF_8472_COMP,
11379 &sff8472_comp, NULL);
11383 status = i40e_aq_get_phy_register(hw,
11384 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11385 I40E_I2C_EEPROM_DEV_ADDR,
11386 I40E_MODULE_SFF_8472_SWAP,
11387 &sff8472_swap, NULL);
11391 /* Check if the module requires address swap to access
11392 * the other EEPROM memory page.
11394 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
11395 PMD_DRV_LOG(WARNING,
11396 "Module address swap to access "
11397 "page 0xA2 is not supported.\n");
11398 modinfo->type = RTE_ETH_MODULE_SFF_8079;
11399 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11400 } else if (sff8472_comp == 0x00) {
11401 /* Module is not SFF-8472 compliant */
11402 modinfo->type = RTE_ETH_MODULE_SFF_8079;
11403 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11405 modinfo->type = RTE_ETH_MODULE_SFF_8472;
11406 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
11409 case I40E_MODULE_TYPE_QSFP_PLUS:
11410 /* Read from memory page 0. */
11411 status = i40e_aq_get_phy_register(hw,
11412 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11414 I40E_MODULE_REVISION_ADDR,
11415 &sff8636_rev, NULL);
11418 /* Determine revision compliance byte */
11419 if (sff8636_rev > 0x02) {
11420 /* Module is SFF-8636 compliant */
11421 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11422 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11424 modinfo->type = RTE_ETH_MODULE_SFF_8436;
11425 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11428 case I40E_MODULE_TYPE_QSFP28:
11429 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11430 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11433 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
11439 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
11440 struct rte_dev_eeprom_info *info)
11442 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11443 bool is_sfp = false;
11444 i40e_status status;
11445 uint8_t *data = info->data;
11446 uint32_t value = 0;
11449 if (!info || !info->length || !data)
11452 if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
11455 for (i = 0; i < info->length; i++) {
11456 u32 offset = i + info->offset;
11457 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
11459 /* Check if we need to access the other memory page */
11461 if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
11462 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
11463 addr = I40E_I2C_EEPROM_DEV_ADDR2;
11466 while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
11467 /* Compute memory page number and offset. */
11468 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
11472 status = i40e_aq_get_phy_register(hw,
11473 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11474 addr, offset, &value, NULL);
11477 data[i] = (uint8_t)value;
11482 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11483 struct ether_addr *mac_addr)
11485 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11486 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11487 struct i40e_vsi *vsi = pf->main_vsi;
11488 struct i40e_mac_filter_info mac_filter;
11489 struct i40e_mac_filter *f;
11492 if (!is_valid_assigned_ether_addr(mac_addr)) {
11493 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11497 TAILQ_FOREACH(f, &vsi->mac_list, next) {
11498 if (is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
11503 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11507 mac_filter = f->mac_info;
11508 ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11509 if (ret != I40E_SUCCESS) {
11510 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11513 memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11514 ret = i40e_vsi_add_mac(vsi, &mac_filter);
11515 if (ret != I40E_SUCCESS) {
11516 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11519 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11521 ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11522 mac_addr->addr_bytes, NULL);
11523 if (ret != I40E_SUCCESS) {
11524 PMD_DRV_LOG(ERR, "Failed to change mac");
11532 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
11534 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11535 struct rte_eth_dev_data *dev_data = pf->dev_data;
11536 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
11539 /* check if mtu is within the allowed range */
11540 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
11543 /* mtu setting is forbidden if port is start */
11544 if (dev_data->dev_started) {
11545 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
11546 dev_data->port_id);
11550 if (frame_size > ETHER_MAX_LEN)
11551 dev_data->dev_conf.rxmode.offloads |=
11552 DEV_RX_OFFLOAD_JUMBO_FRAME;
11554 dev_data->dev_conf.rxmode.offloads &=
11555 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
11557 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
11562 /* Restore ethertype filter */
11564 i40e_ethertype_filter_restore(struct i40e_pf *pf)
11566 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11567 struct i40e_ethertype_filter_list
11568 *ethertype_list = &pf->ethertype.ethertype_list;
11569 struct i40e_ethertype_filter *f;
11570 struct i40e_control_filter_stats stats;
11573 TAILQ_FOREACH(f, ethertype_list, rules) {
11575 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
11576 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
11577 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
11578 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
11579 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
11581 memset(&stats, 0, sizeof(stats));
11582 i40e_aq_add_rem_control_packet_filter(hw,
11583 f->input.mac_addr.addr_bytes,
11584 f->input.ether_type,
11585 flags, pf->main_vsi->seid,
11586 f->queue, 1, &stats, NULL);
11588 PMD_DRV_LOG(INFO, "Ethertype filter:"
11589 " mac_etype_used = %u, etype_used = %u,"
11590 " mac_etype_free = %u, etype_free = %u",
11591 stats.mac_etype_used, stats.etype_used,
11592 stats.mac_etype_free, stats.etype_free);
11595 /* Restore tunnel filter */
11597 i40e_tunnel_filter_restore(struct i40e_pf *pf)
11599 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11600 struct i40e_vsi *vsi;
11601 struct i40e_pf_vf *vf;
11602 struct i40e_tunnel_filter_list
11603 *tunnel_list = &pf->tunnel.tunnel_list;
11604 struct i40e_tunnel_filter *f;
11605 struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
11606 bool big_buffer = 0;
11608 TAILQ_FOREACH(f, tunnel_list, rules) {
11610 vsi = pf->main_vsi;
11612 vf = &pf->vfs[f->vf_id];
11615 memset(&cld_filter, 0, sizeof(cld_filter));
11616 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
11617 (struct ether_addr *)&cld_filter.element.outer_mac);
11618 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
11619 (struct ether_addr *)&cld_filter.element.inner_mac);
11620 cld_filter.element.inner_vlan = f->input.inner_vlan;
11621 cld_filter.element.flags = f->input.flags;
11622 cld_filter.element.tenant_id = f->input.tenant_id;
11623 cld_filter.element.queue_number = f->queue;
11624 rte_memcpy(cld_filter.general_fields,
11625 f->input.general_fields,
11626 sizeof(f->input.general_fields));
11628 if (((f->input.flags &
11629 I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
11630 I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
11632 I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
11633 I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
11635 I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
11636 I40E_AQC_ADD_CLOUD_FILTER_0X10))
11640 i40e_aq_add_cloud_filters_big_buffer(hw,
11641 vsi->seid, &cld_filter, 1);
11643 i40e_aq_add_cloud_filters(hw, vsi->seid,
11644 &cld_filter.element, 1);
11648 /* Restore rss filter */
11650 i40e_rss_filter_restore(struct i40e_pf *pf)
11652 struct i40e_rte_flow_rss_conf *conf =
11654 if (conf->conf.queue_num)
11655 i40e_config_rss_filter(pf, conf, TRUE);
11659 i40e_filter_restore(struct i40e_pf *pf)
11661 i40e_ethertype_filter_restore(pf);
11662 i40e_tunnel_filter_restore(pf);
11663 i40e_fdir_filter_restore(pf);
11664 i40e_rss_filter_restore(pf);
11668 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
11670 if (strcmp(dev->device->driver->name, drv->driver.name))
11677 is_i40e_supported(struct rte_eth_dev *dev)
11679 return is_device_supported(dev, &rte_i40e_pmd);
11682 struct i40e_customized_pctype*
11683 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
11687 for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
11688 if (pf->customized_pctype[i].index == index)
11689 return &pf->customized_pctype[i];
11695 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
11696 uint32_t pkg_size, uint32_t proto_num,
11697 struct rte_pmd_i40e_proto_info *proto,
11698 enum rte_pmd_i40e_package_op op)
11700 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11701 uint32_t pctype_num;
11702 struct rte_pmd_i40e_ptype_info *pctype;
11703 uint32_t buff_size;
11704 struct i40e_customized_pctype *new_pctype = NULL;
11706 uint8_t pctype_value;
11711 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11712 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11713 PMD_DRV_LOG(ERR, "Unsupported operation.");
11717 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11718 (uint8_t *)&pctype_num, sizeof(pctype_num),
11719 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
11721 PMD_DRV_LOG(ERR, "Failed to get pctype number");
11725 PMD_DRV_LOG(INFO, "No new pctype added");
11729 buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
11730 pctype = rte_zmalloc("new_pctype", buff_size, 0);
11732 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11735 /* get information about new pctype list */
11736 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11737 (uint8_t *)pctype, buff_size,
11738 RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
11740 PMD_DRV_LOG(ERR, "Failed to get pctype list");
11745 /* Update customized pctype. */
11746 for (i = 0; i < pctype_num; i++) {
11747 pctype_value = pctype[i].ptype_id;
11748 memset(name, 0, sizeof(name));
11749 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11750 proto_id = pctype[i].protocols[j];
11751 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11753 for (n = 0; n < proto_num; n++) {
11754 if (proto[n].proto_id != proto_id)
11756 strcat(name, proto[n].name);
11761 name[strlen(name) - 1] = '\0';
11762 if (!strcmp(name, "GTPC"))
11764 i40e_find_customized_pctype(pf,
11765 I40E_CUSTOMIZED_GTPC);
11766 else if (!strcmp(name, "GTPU_IPV4"))
11768 i40e_find_customized_pctype(pf,
11769 I40E_CUSTOMIZED_GTPU_IPV4);
11770 else if (!strcmp(name, "GTPU_IPV6"))
11772 i40e_find_customized_pctype(pf,
11773 I40E_CUSTOMIZED_GTPU_IPV6);
11774 else if (!strcmp(name, "GTPU"))
11776 i40e_find_customized_pctype(pf,
11777 I40E_CUSTOMIZED_GTPU);
11779 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
11780 new_pctype->pctype = pctype_value;
11781 new_pctype->valid = true;
11783 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
11784 new_pctype->valid = false;
11794 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
11795 uint32_t pkg_size, uint32_t proto_num,
11796 struct rte_pmd_i40e_proto_info *proto,
11797 enum rte_pmd_i40e_package_op op)
11799 struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
11800 uint16_t port_id = dev->data->port_id;
11801 uint32_t ptype_num;
11802 struct rte_pmd_i40e_ptype_info *ptype;
11803 uint32_t buff_size;
11805 char name[RTE_PMD_I40E_DDP_NAME_SIZE];
11810 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11811 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11812 PMD_DRV_LOG(ERR, "Unsupported operation.");
11816 if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
11817 rte_pmd_i40e_ptype_mapping_reset(port_id);
11821 /* get information about new ptype num */
11822 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11823 (uint8_t *)&ptype_num, sizeof(ptype_num),
11824 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
11826 PMD_DRV_LOG(ERR, "Failed to get ptype number");
11830 PMD_DRV_LOG(INFO, "No new ptype added");
11834 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
11835 ptype = rte_zmalloc("new_ptype", buff_size, 0);
11837 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11841 /* get information about new ptype list */
11842 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11843 (uint8_t *)ptype, buff_size,
11844 RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
11846 PMD_DRV_LOG(ERR, "Failed to get ptype list");
11851 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
11852 ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
11853 if (!ptype_mapping) {
11854 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11859 /* Update ptype mapping table. */
11860 for (i = 0; i < ptype_num; i++) {
11861 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
11862 ptype_mapping[i].sw_ptype = 0;
11864 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11865 proto_id = ptype[i].protocols[j];
11866 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11868 for (n = 0; n < proto_num; n++) {
11869 if (proto[n].proto_id != proto_id)
11871 memset(name, 0, sizeof(name));
11872 strcpy(name, proto[n].name);
11873 if (!strncasecmp(name, "PPPOE", 5))
11874 ptype_mapping[i].sw_ptype |=
11875 RTE_PTYPE_L2_ETHER_PPPOE;
11876 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
11878 ptype_mapping[i].sw_ptype |=
11879 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11880 ptype_mapping[i].sw_ptype |=
11882 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
11884 ptype_mapping[i].sw_ptype |=
11885 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11886 ptype_mapping[i].sw_ptype |=
11887 RTE_PTYPE_INNER_L4_FRAG;
11888 } else if (!strncasecmp(name, "OIPV4", 5)) {
11889 ptype_mapping[i].sw_ptype |=
11890 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11892 } else if (!strncasecmp(name, "IPV4", 4) &&
11894 ptype_mapping[i].sw_ptype |=
11895 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11896 else if (!strncasecmp(name, "IPV4", 4) &&
11898 ptype_mapping[i].sw_ptype |=
11899 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11900 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
11902 ptype_mapping[i].sw_ptype |=
11903 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11904 ptype_mapping[i].sw_ptype |=
11906 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
11908 ptype_mapping[i].sw_ptype |=
11909 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11910 ptype_mapping[i].sw_ptype |=
11911 RTE_PTYPE_INNER_L4_FRAG;
11912 } else if (!strncasecmp(name, "OIPV6", 5)) {
11913 ptype_mapping[i].sw_ptype |=
11914 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11916 } else if (!strncasecmp(name, "IPV6", 4) &&
11918 ptype_mapping[i].sw_ptype |=
11919 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11920 else if (!strncasecmp(name, "IPV6", 4) &&
11922 ptype_mapping[i].sw_ptype |=
11923 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11924 else if (!strncasecmp(name, "UDP", 3) &&
11926 ptype_mapping[i].sw_ptype |=
11928 else if (!strncasecmp(name, "UDP", 3) &&
11930 ptype_mapping[i].sw_ptype |=
11931 RTE_PTYPE_INNER_L4_UDP;
11932 else if (!strncasecmp(name, "TCP", 3) &&
11934 ptype_mapping[i].sw_ptype |=
11936 else if (!strncasecmp(name, "TCP", 3) &&
11938 ptype_mapping[i].sw_ptype |=
11939 RTE_PTYPE_INNER_L4_TCP;
11940 else if (!strncasecmp(name, "SCTP", 4) &&
11942 ptype_mapping[i].sw_ptype |=
11944 else if (!strncasecmp(name, "SCTP", 4) &&
11946 ptype_mapping[i].sw_ptype |=
11947 RTE_PTYPE_INNER_L4_SCTP;
11948 else if ((!strncasecmp(name, "ICMP", 4) ||
11949 !strncasecmp(name, "ICMPV6", 6)) &&
11951 ptype_mapping[i].sw_ptype |=
11953 else if ((!strncasecmp(name, "ICMP", 4) ||
11954 !strncasecmp(name, "ICMPV6", 6)) &&
11956 ptype_mapping[i].sw_ptype |=
11957 RTE_PTYPE_INNER_L4_ICMP;
11958 else if (!strncasecmp(name, "GTPC", 4)) {
11959 ptype_mapping[i].sw_ptype |=
11960 RTE_PTYPE_TUNNEL_GTPC;
11962 } else if (!strncasecmp(name, "GTPU", 4)) {
11963 ptype_mapping[i].sw_ptype |=
11964 RTE_PTYPE_TUNNEL_GTPU;
11966 } else if (!strncasecmp(name, "GRENAT", 6)) {
11967 ptype_mapping[i].sw_ptype |=
11968 RTE_PTYPE_TUNNEL_GRENAT;
11970 } else if (!strncasecmp(name, "L2TPV2CTL", 9)) {
11971 ptype_mapping[i].sw_ptype |=
11972 RTE_PTYPE_TUNNEL_L2TP;
11981 ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
11984 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
11986 rte_free(ptype_mapping);
11992 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
11993 uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
11995 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11996 uint32_t proto_num;
11997 struct rte_pmd_i40e_proto_info *proto;
11998 uint32_t buff_size;
12002 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12003 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12004 PMD_DRV_LOG(ERR, "Unsupported operation.");
12008 /* get information about protocol number */
12009 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12010 (uint8_t *)&proto_num, sizeof(proto_num),
12011 RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12013 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12017 PMD_DRV_LOG(INFO, "No new protocol added");
12021 buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12022 proto = rte_zmalloc("new_proto", buff_size, 0);
12024 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12028 /* get information about protocol list */
12029 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12030 (uint8_t *)proto, buff_size,
12031 RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12033 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12038 /* Check if GTP is supported. */
12039 for (i = 0; i < proto_num; i++) {
12040 if (!strncmp(proto[i].name, "GTP", 3)) {
12041 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12042 pf->gtp_support = true;
12044 pf->gtp_support = false;
12049 /* Update customized pctype info */
12050 ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12051 proto_num, proto, op);
12053 PMD_DRV_LOG(INFO, "No pctype is updated.");
12055 /* Update customized ptype info */
12056 ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12057 proto_num, proto, op);
12059 PMD_DRV_LOG(INFO, "No ptype is updated.");
12064 /* Create a QinQ cloud filter
12066 * The Fortville NIC has limited resources for tunnel filters,
12067 * so we can only reuse existing filters.
12069 * In step 1 we define which Field Vector fields can be used for
12071 * As we do not have the inner tag defined as a field,
12072 * we have to define it first, by reusing one of L1 entries.
12074 * In step 2 we are replacing one of existing filter types with
12075 * a new one for QinQ.
12076 * As we reusing L1 and replacing L2, some of the default filter
12077 * types will disappear,which depends on L1 and L2 entries we reuse.
12079 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12081 * 1. Create L1 filter of outer vlan (12b) which will be in use
12082 * later when we define the cloud filter.
12083 * a. Valid_flags.replace_cloud = 0
12084 * b. Old_filter = 10 (Stag_Inner_Vlan)
12085 * c. New_filter = 0x10
12086 * d. TR bit = 0xff (optional, not used here)
12087 * e. Buffer – 2 entries:
12088 * i. Byte 0 = 8 (outer vlan FV index).
12090 * Byte 2-3 = 0x0fff
12091 * ii. Byte 0 = 37 (inner vlan FV index).
12093 * Byte 2-3 = 0x0fff
12096 * 2. Create cloud filter using two L1 filters entries: stag and
12097 * new filter(outer vlan+ inner vlan)
12098 * a. Valid_flags.replace_cloud = 1
12099 * b. Old_filter = 1 (instead of outer IP)
12100 * c. New_filter = 0x10
12101 * d. Buffer – 2 entries:
12102 * i. Byte 0 = 0x80 | 7 (valid | Stag).
12103 * Byte 1-3 = 0 (rsv)
12104 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12105 * Byte 9-11 = 0 (rsv)
12108 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12110 int ret = -ENOTSUP;
12111 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
12112 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
12113 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12115 if (pf->support_multi_driver) {
12116 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12121 memset(&filter_replace, 0,
12122 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12123 memset(&filter_replace_buf, 0,
12124 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12126 /* create L1 filter */
12127 filter_replace.old_filter_type =
12128 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12129 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12130 filter_replace.tr_bit = 0;
12132 /* Prepare the buffer, 2 entries */
12133 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12134 filter_replace_buf.data[0] |=
12135 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12136 /* Field Vector 12b mask */
12137 filter_replace_buf.data[2] = 0xff;
12138 filter_replace_buf.data[3] = 0x0f;
12139 filter_replace_buf.data[4] =
12140 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12141 filter_replace_buf.data[4] |=
12142 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12143 /* Field Vector 12b mask */
12144 filter_replace_buf.data[6] = 0xff;
12145 filter_replace_buf.data[7] = 0x0f;
12146 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12147 &filter_replace_buf);
12148 if (ret != I40E_SUCCESS)
12150 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
12151 "cloud l1 type is changed from 0x%x to 0x%x",
12152 filter_replace.old_filter_type,
12153 filter_replace.new_filter_type);
12155 /* Apply the second L2 cloud filter */
12156 memset(&filter_replace, 0,
12157 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12158 memset(&filter_replace_buf, 0,
12159 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12161 /* create L2 filter, input for L2 filter will be L1 filter */
12162 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12163 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12164 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12166 /* Prepare the buffer, 2 entries */
12167 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12168 filter_replace_buf.data[0] |=
12169 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12170 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12171 filter_replace_buf.data[4] |=
12172 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12173 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12174 &filter_replace_buf);
12176 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
12177 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
12178 "cloud filter type is changed from 0x%x to 0x%x",
12179 filter_replace.old_filter_type,
12180 filter_replace.new_filter_type);
12186 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
12187 const struct rte_flow_action_rss *in)
12189 if (in->key_len > RTE_DIM(out->key) ||
12190 in->queue_num > RTE_DIM(out->queue))
12192 out->conf = (struct rte_flow_action_rss){
12194 .types = in->types,
12195 .key_len = in->key_len,
12196 .queue_num = in->queue_num,
12197 .key = memcpy(out->key, in->key, in->key_len),
12198 .queue = memcpy(out->queue, in->queue,
12199 sizeof(*in->queue) * in->queue_num),
12205 i40e_action_rss_same(const struct rte_flow_action_rss *comp,
12206 const struct rte_flow_action_rss *with)
12208 return (comp->func == with->func &&
12209 comp->types == with->types &&
12210 comp->key_len == with->key_len &&
12211 comp->queue_num == with->queue_num &&
12212 !memcmp(comp->key, with->key, with->key_len) &&
12213 !memcmp(comp->queue, with->queue,
12214 sizeof(*with->queue) * with->queue_num));
12218 i40e_config_rss_filter(struct i40e_pf *pf,
12219 struct i40e_rte_flow_rss_conf *conf, bool add)
12221 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12222 uint32_t i, lut = 0;
12224 struct rte_eth_rss_conf rss_conf = {
12225 .rss_key = conf->conf.key_len ?
12226 (void *)(uintptr_t)conf->conf.key : NULL,
12227 .rss_key_len = conf->conf.key_len,
12228 .rss_hf = conf->conf.types,
12230 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
12233 if (i40e_action_rss_same(&rss_info->conf, &conf->conf)) {
12234 i40e_pf_disable_rss(pf);
12235 memset(rss_info, 0,
12236 sizeof(struct i40e_rte_flow_rss_conf));
12242 if (rss_info->conf.queue_num)
12245 /* If both VMDQ and RSS enabled, not all of PF queues are configured.
12246 * It's necessary to calculate the actual PF queues that are configured.
12248 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
12249 num = i40e_pf_calc_configured_queues_num(pf);
12251 num = pf->dev_data->nb_rx_queues;
12253 num = RTE_MIN(num, conf->conf.queue_num);
12254 PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
12258 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS");
12262 /* Fill in redirection table */
12263 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
12266 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
12267 hw->func_caps.rss_table_entry_width) - 1));
12269 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
12272 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
12273 i40e_pf_disable_rss(pf);
12276 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
12277 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
12278 /* Random default keys */
12279 static uint32_t rss_key_default[] = {0x6b793944,
12280 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
12281 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
12282 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
12284 rss_conf.rss_key = (uint8_t *)rss_key_default;
12285 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
12289 i40e_hw_rss_hash_set(pf, &rss_conf);
12291 if (i40e_rss_conf_init(rss_info, &conf->conf))
12297 RTE_INIT(i40e_init_log);
12299 i40e_init_log(void)
12301 i40e_logtype_init = rte_log_register("pmd.net.i40e.init");
12302 if (i40e_logtype_init >= 0)
12303 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
12304 i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver");
12305 if (i40e_logtype_driver >= 0)
12306 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
12309 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12310 QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12311 ETH_I40E_SUPPORT_MULTI_DRIVER "=1");