4 * Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 #include <rte_string_fns.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_ethdev_pci.h>
49 #include <rte_memzone.h>
50 #include <rte_malloc.h>
51 #include <rte_memcpy.h>
52 #include <rte_alarm.h>
54 #include <rte_eth_ctrl.h>
55 #include <rte_tailq.h>
56 #include <rte_hash_crc.h>
58 #include "i40e_logs.h"
59 #include "base/i40e_prototype.h"
60 #include "base/i40e_adminq_cmd.h"
61 #include "base/i40e_type.h"
62 #include "base/i40e_register.h"
63 #include "base/i40e_dcb.h"
64 #include "i40e_ethdev.h"
65 #include "i40e_rxtx.h"
67 #include "i40e_regs.h"
69 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
70 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
72 #define I40E_CLEAR_PXE_WAIT_MS 200
74 /* Maximun number of capability elements */
75 #define I40E_MAX_CAP_ELE_NUM 128
77 /* Wait count and interval */
78 #define I40E_CHK_Q_ENA_COUNT 1000
79 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
81 /* Maximun number of VSI */
82 #define I40E_MAX_NUM_VSIS (384UL)
84 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
86 /* Flow control default timer */
87 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
89 /* Flow control enable fwd bit */
90 #define I40E_PRTMAC_FWD_CTRL 0x00000001
92 /* Receive Packet Buffer size */
93 #define I40E_RXPBSIZE (968 * 1024)
96 #define I40E_KILOSHIFT 10
98 /* Flow control default high water */
99 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
101 /* Flow control default low water */
102 #define I40E_DEFAULT_LOW_WATER (0xF2000 >> I40E_KILOSHIFT)
104 /* Receive Average Packet Size in Byte*/
105 #define I40E_PACKET_AVERAGE_SIZE 128
107 /* Mask of PF interrupt causes */
108 #define I40E_PFINT_ICR0_ENA_MASK ( \
109 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
110 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
111 I40E_PFINT_ICR0_ENA_GRST_MASK | \
112 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
113 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
114 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
115 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
116 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
117 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
119 #define I40E_FLOW_TYPES ( \
120 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
121 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
122 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
123 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
124 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
125 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
126 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
127 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
128 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
129 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
130 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
132 /* Additional timesync values. */
133 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
134 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
135 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
136 #define I40E_PRTTSYN_TSYNENA 0x80000000
137 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
138 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
140 #define I40E_MAX_PERCENT 100
141 #define I40E_DEFAULT_DCB_APP_NUM 1
142 #define I40E_DEFAULT_DCB_APP_PRIO 3
145 * Below are values for writing un-exposed registers suggested
148 /* Destination MAC address */
149 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
150 /* Source MAC address */
151 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
152 /* Outer (S-Tag) VLAN tag in the outer L2 header */
153 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
154 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
155 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
156 /* Single VLAN tag in the inner L2 header */
157 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
158 /* Source IPv4 address */
159 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
160 /* Destination IPv4 address */
161 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
162 /* Source IPv4 address for X722 */
163 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
164 /* Destination IPv4 address for X722 */
165 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
166 /* IPv4 Protocol for X722 */
167 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
168 /* IPv4 Time to Live for X722 */
169 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
170 /* IPv4 Type of Service (TOS) */
171 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
173 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
174 /* IPv4 Time to Live */
175 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
176 /* Source IPv6 address */
177 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
178 /* Destination IPv6 address */
179 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
180 /* IPv6 Traffic Class (TC) */
181 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
182 /* IPv6 Next Header */
183 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
185 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
187 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
188 /* Destination L4 port */
189 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
190 /* SCTP verification tag */
191 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
192 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
193 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
194 /* Source port of tunneling UDP */
195 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
196 /* Destination port of tunneling UDP */
197 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
198 /* UDP Tunneling ID, NVGRE/GRE key */
199 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
200 /* Last ether type */
201 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
202 /* Tunneling outer destination IPv4 address */
203 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
204 /* Tunneling outer destination IPv6 address */
205 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
206 /* 1st word of flex payload */
207 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
208 /* 2nd word of flex payload */
209 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
210 /* 3rd word of flex payload */
211 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
212 /* 4th word of flex payload */
213 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
214 /* 5th word of flex payload */
215 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
216 /* 6th word of flex payload */
217 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
218 /* 7th word of flex payload */
219 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
220 /* 8th word of flex payload */
221 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
222 /* all 8 words flex payload */
223 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
224 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
226 #define I40E_TRANSLATE_INSET 0
227 #define I40E_TRANSLATE_REG 1
229 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
230 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
231 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
232 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
233 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
234 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
236 /* PCI offset for querying capability */
237 #define PCI_DEV_CAP_REG 0xA4
238 /* PCI offset for enabling/disabling Extended Tag */
239 #define PCI_DEV_CTRL_REG 0xA8
240 /* Bit mask of Extended Tag capability */
241 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
242 /* Bit shift of Extended Tag enable/disable */
243 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
244 /* Bit mask of Extended Tag enable/disable */
245 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
247 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
248 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
249 static int i40e_dev_configure(struct rte_eth_dev *dev);
250 static int i40e_dev_start(struct rte_eth_dev *dev);
251 static void i40e_dev_stop(struct rte_eth_dev *dev);
252 static void i40e_dev_close(struct rte_eth_dev *dev);
253 static int i40e_dev_reset(struct rte_eth_dev *dev);
254 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
255 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
256 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
257 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
258 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
259 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
260 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
261 struct rte_eth_stats *stats);
262 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
263 struct rte_eth_xstat *xstats, unsigned n);
264 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
265 struct rte_eth_xstat_name *xstats_names,
267 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
268 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
272 static int i40e_fw_version_get(struct rte_eth_dev *dev,
273 char *fw_version, size_t fw_size);
274 static void i40e_dev_info_get(struct rte_eth_dev *dev,
275 struct rte_eth_dev_info *dev_info);
276 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
279 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
280 enum rte_vlan_type vlan_type,
282 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
283 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
286 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
287 static int i40e_dev_led_on(struct rte_eth_dev *dev);
288 static int i40e_dev_led_off(struct rte_eth_dev *dev);
289 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
290 struct rte_eth_fc_conf *fc_conf);
291 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
292 struct rte_eth_fc_conf *fc_conf);
293 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
294 struct rte_eth_pfc_conf *pfc_conf);
295 static int i40e_macaddr_add(struct rte_eth_dev *dev,
296 struct ether_addr *mac_addr,
299 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
300 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
301 struct rte_eth_rss_reta_entry64 *reta_conf,
303 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
304 struct rte_eth_rss_reta_entry64 *reta_conf,
307 static int i40e_get_cap(struct i40e_hw *hw);
308 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
309 static int i40e_pf_setup(struct i40e_pf *pf);
310 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
311 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
312 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
313 static int i40e_dcb_setup(struct rte_eth_dev *dev);
314 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
315 bool offset_loaded, uint64_t *offset, uint64_t *stat);
316 static void i40e_stat_update_48(struct i40e_hw *hw,
322 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
323 static void i40e_dev_interrupt_handler(void *param);
324 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
325 uint32_t base, uint32_t num);
326 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
327 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
329 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
331 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
332 static int i40e_veb_release(struct i40e_veb *veb);
333 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
334 struct i40e_vsi *vsi);
335 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
336 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
337 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
338 struct i40e_macvlan_filter *mv_f,
341 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
342 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
343 struct rte_eth_rss_conf *rss_conf);
344 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
345 struct rte_eth_rss_conf *rss_conf);
346 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
347 struct rte_eth_udp_tunnel *udp_tunnel);
348 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
349 struct rte_eth_udp_tunnel *udp_tunnel);
350 static void i40e_filter_input_set_init(struct i40e_pf *pf);
351 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
352 enum rte_filter_op filter_op,
354 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
355 enum rte_filter_type filter_type,
356 enum rte_filter_op filter_op,
358 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
359 struct rte_eth_dcb_info *dcb_info);
360 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
361 static void i40e_configure_registers(struct i40e_hw *hw);
362 static void i40e_hw_init(struct rte_eth_dev *dev);
363 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
364 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
365 struct rte_eth_mirror_conf *mirror_conf,
366 uint8_t sw_id, uint8_t on);
367 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
369 static int i40e_timesync_enable(struct rte_eth_dev *dev);
370 static int i40e_timesync_disable(struct rte_eth_dev *dev);
371 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
372 struct timespec *timestamp,
374 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
375 struct timespec *timestamp);
376 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
378 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
380 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
381 struct timespec *timestamp);
382 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
383 const struct timespec *timestamp);
385 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
387 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
390 static int i40e_get_regs(struct rte_eth_dev *dev,
391 struct rte_dev_reg_info *regs);
393 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
395 static int i40e_get_eeprom(struct rte_eth_dev *dev,
396 struct rte_dev_eeprom_info *eeprom);
398 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
399 struct ether_addr *mac_addr);
401 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
403 static int i40e_ethertype_filter_convert(
404 const struct rte_eth_ethertype_filter *input,
405 struct i40e_ethertype_filter *filter);
406 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
407 struct i40e_ethertype_filter *filter);
409 static int i40e_tunnel_filter_convert(
410 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
411 struct i40e_tunnel_filter *tunnel_filter);
412 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
413 struct i40e_tunnel_filter *tunnel_filter);
414 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
416 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
417 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
418 static void i40e_filter_restore(struct i40e_pf *pf);
419 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
421 int i40e_logtype_init;
422 int i40e_logtype_driver;
424 static const struct rte_pci_id pci_id_i40e_map[] = {
425 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
426 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
427 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
428 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
429 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
430 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
431 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
432 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
435 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
436 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
437 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
438 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
439 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
440 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
441 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
442 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
443 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
444 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
445 { .vendor_id = 0, /* sentinel */ },
448 static const struct eth_dev_ops i40e_eth_dev_ops = {
449 .dev_configure = i40e_dev_configure,
450 .dev_start = i40e_dev_start,
451 .dev_stop = i40e_dev_stop,
452 .dev_close = i40e_dev_close,
453 .dev_reset = i40e_dev_reset,
454 .promiscuous_enable = i40e_dev_promiscuous_enable,
455 .promiscuous_disable = i40e_dev_promiscuous_disable,
456 .allmulticast_enable = i40e_dev_allmulticast_enable,
457 .allmulticast_disable = i40e_dev_allmulticast_disable,
458 .dev_set_link_up = i40e_dev_set_link_up,
459 .dev_set_link_down = i40e_dev_set_link_down,
460 .link_update = i40e_dev_link_update,
461 .stats_get = i40e_dev_stats_get,
462 .xstats_get = i40e_dev_xstats_get,
463 .xstats_get_names = i40e_dev_xstats_get_names,
464 .stats_reset = i40e_dev_stats_reset,
465 .xstats_reset = i40e_dev_stats_reset,
466 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
467 .fw_version_get = i40e_fw_version_get,
468 .dev_infos_get = i40e_dev_info_get,
469 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
470 .vlan_filter_set = i40e_vlan_filter_set,
471 .vlan_tpid_set = i40e_vlan_tpid_set,
472 .vlan_offload_set = i40e_vlan_offload_set,
473 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
474 .vlan_pvid_set = i40e_vlan_pvid_set,
475 .rx_queue_start = i40e_dev_rx_queue_start,
476 .rx_queue_stop = i40e_dev_rx_queue_stop,
477 .tx_queue_start = i40e_dev_tx_queue_start,
478 .tx_queue_stop = i40e_dev_tx_queue_stop,
479 .rx_queue_setup = i40e_dev_rx_queue_setup,
480 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
481 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
482 .rx_queue_release = i40e_dev_rx_queue_release,
483 .rx_queue_count = i40e_dev_rx_queue_count,
484 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
485 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
486 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
487 .tx_queue_setup = i40e_dev_tx_queue_setup,
488 .tx_queue_release = i40e_dev_tx_queue_release,
489 .dev_led_on = i40e_dev_led_on,
490 .dev_led_off = i40e_dev_led_off,
491 .flow_ctrl_get = i40e_flow_ctrl_get,
492 .flow_ctrl_set = i40e_flow_ctrl_set,
493 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
494 .mac_addr_add = i40e_macaddr_add,
495 .mac_addr_remove = i40e_macaddr_remove,
496 .reta_update = i40e_dev_rss_reta_update,
497 .reta_query = i40e_dev_rss_reta_query,
498 .rss_hash_update = i40e_dev_rss_hash_update,
499 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
500 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
501 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
502 .filter_ctrl = i40e_dev_filter_ctrl,
503 .rxq_info_get = i40e_rxq_info_get,
504 .txq_info_get = i40e_txq_info_get,
505 .mirror_rule_set = i40e_mirror_rule_set,
506 .mirror_rule_reset = i40e_mirror_rule_reset,
507 .timesync_enable = i40e_timesync_enable,
508 .timesync_disable = i40e_timesync_disable,
509 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
510 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
511 .get_dcb_info = i40e_dev_get_dcb_info,
512 .timesync_adjust_time = i40e_timesync_adjust_time,
513 .timesync_read_time = i40e_timesync_read_time,
514 .timesync_write_time = i40e_timesync_write_time,
515 .get_reg = i40e_get_regs,
516 .get_eeprom_length = i40e_get_eeprom_length,
517 .get_eeprom = i40e_get_eeprom,
518 .mac_addr_set = i40e_set_default_mac_addr,
519 .mtu_set = i40e_dev_mtu_set,
520 .tm_ops_get = i40e_tm_ops_get,
523 /* store statistics names and its offset in stats structure */
524 struct rte_i40e_xstats_name_off {
525 char name[RTE_ETH_XSTATS_NAME_SIZE];
529 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
530 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
531 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
532 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
533 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
534 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
535 rx_unknown_protocol)},
536 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
537 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
538 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
539 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
542 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
543 sizeof(rte_i40e_stats_strings[0]))
545 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
546 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
547 tx_dropped_link_down)},
548 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
549 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
551 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
552 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
554 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
556 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
558 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
559 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
560 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
561 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
562 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
563 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
565 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
567 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
569 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
571 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
573 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
575 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
577 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
579 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
580 mac_short_packet_dropped)},
581 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
583 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
584 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
585 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
587 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
589 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
591 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
593 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
595 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
597 {"rx_flow_director_atr_match_packets",
598 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
599 {"rx_flow_director_sb_match_packets",
600 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
601 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
603 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
605 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
607 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
611 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
612 sizeof(rte_i40e_hw_port_strings[0]))
614 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
615 {"xon_packets", offsetof(struct i40e_hw_port_stats,
617 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
621 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
622 sizeof(rte_i40e_rxq_prio_strings[0]))
624 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
625 {"xon_packets", offsetof(struct i40e_hw_port_stats,
627 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
629 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
630 priority_xon_2_xoff)},
633 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
634 sizeof(rte_i40e_txq_prio_strings[0]))
636 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
637 struct rte_pci_device *pci_dev)
639 return rte_eth_dev_pci_generic_probe(pci_dev,
640 sizeof(struct i40e_adapter), eth_i40e_dev_init);
643 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
645 return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
648 static struct rte_pci_driver rte_i40e_pmd = {
649 .id_table = pci_id_i40e_map,
650 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
651 .probe = eth_i40e_pci_probe,
652 .remove = eth_i40e_pci_remove,
656 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
657 struct rte_eth_link *link)
659 struct rte_eth_link *dst = link;
660 struct rte_eth_link *src = &(dev->data->dev_link);
662 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
663 *(uint64_t *)src) == 0)
670 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
671 struct rte_eth_link *link)
673 struct rte_eth_link *dst = &(dev->data->dev_link);
674 struct rte_eth_link *src = link;
676 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
677 *(uint64_t *)src) == 0)
683 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
684 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
685 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
687 #ifndef I40E_GLQF_ORT
688 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
690 #ifndef I40E_GLQF_PIT
691 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
693 #ifndef I40E_GLQF_L3_MAP
694 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
697 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
700 * Initialize registers for flexible payload, which should be set by NVM.
701 * This should be removed from code once it is fixed in NVM.
703 I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
704 I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
705 I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
706 I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
707 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
708 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
709 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
710 I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
711 I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
712 I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
713 I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
714 I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
716 /* Initialize registers for parsing packet type of QinQ */
717 I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
718 I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
721 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
724 * Add a ethertype filter to drop all flow control frames transmitted
728 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
730 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
731 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
732 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
733 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
736 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
737 I40E_FLOW_CONTROL_ETHERTYPE, flags,
738 pf->main_vsi_seid, 0,
742 "Failed to add filter to drop flow control frames from VSIs.");
746 floating_veb_list_handler(__rte_unused const char *key,
747 const char *floating_veb_value,
751 unsigned int count = 0;
754 bool *vf_floating_veb = opaque;
756 while (isblank(*floating_veb_value))
757 floating_veb_value++;
759 /* Reset floating VEB configuration for VFs */
760 for (idx = 0; idx < I40E_MAX_VF; idx++)
761 vf_floating_veb[idx] = false;
765 while (isblank(*floating_veb_value))
766 floating_veb_value++;
767 if (*floating_veb_value == '\0')
770 idx = strtoul(floating_veb_value, &end, 10);
771 if (errno || end == NULL)
773 while (isblank(*end))
777 } else if ((*end == ';') || (*end == '\0')) {
779 if (min == I40E_MAX_VF)
781 if (max >= I40E_MAX_VF)
782 max = I40E_MAX_VF - 1;
783 for (idx = min; idx <= max; idx++) {
784 vf_floating_veb[idx] = true;
791 floating_veb_value = end + 1;
792 } while (*end != '\0');
801 config_vf_floating_veb(struct rte_devargs *devargs,
802 uint16_t floating_veb,
803 bool *vf_floating_veb)
805 struct rte_kvargs *kvlist;
807 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
811 /* All the VFs attach to the floating VEB by default
812 * when the floating VEB is enabled.
814 for (i = 0; i < I40E_MAX_VF; i++)
815 vf_floating_veb[i] = true;
820 kvlist = rte_kvargs_parse(devargs->args, NULL);
824 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
825 rte_kvargs_free(kvlist);
828 /* When the floating_veb_list parameter exists, all the VFs
829 * will attach to the legacy VEB firstly, then configure VFs
830 * to the floating VEB according to the floating_veb_list.
832 if (rte_kvargs_process(kvlist, floating_veb_list,
833 floating_veb_list_handler,
834 vf_floating_veb) < 0) {
835 rte_kvargs_free(kvlist);
838 rte_kvargs_free(kvlist);
842 i40e_check_floating_handler(__rte_unused const char *key,
844 __rte_unused void *opaque)
846 if (strcmp(value, "1"))
853 is_floating_veb_supported(struct rte_devargs *devargs)
855 struct rte_kvargs *kvlist;
856 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
861 kvlist = rte_kvargs_parse(devargs->args, NULL);
865 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
866 rte_kvargs_free(kvlist);
869 /* Floating VEB is enabled when there's key-value:
870 * enable_floating_veb=1
872 if (rte_kvargs_process(kvlist, floating_veb_key,
873 i40e_check_floating_handler, NULL) < 0) {
874 rte_kvargs_free(kvlist);
877 rte_kvargs_free(kvlist);
883 config_floating_veb(struct rte_eth_dev *dev)
885 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
886 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
887 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
889 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
891 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
893 is_floating_veb_supported(pci_dev->device.devargs);
894 config_vf_floating_veb(pci_dev->device.devargs,
896 pf->floating_veb_list);
898 pf->floating_veb = false;
902 #define I40E_L2_TAGS_S_TAG_SHIFT 1
903 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
906 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
908 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
909 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
910 char ethertype_hash_name[RTE_HASH_NAMESIZE];
913 struct rte_hash_parameters ethertype_hash_params = {
914 .name = ethertype_hash_name,
915 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
916 .key_len = sizeof(struct i40e_ethertype_filter_input),
917 .hash_func = rte_hash_crc,
918 .hash_func_init_val = 0,
919 .socket_id = rte_socket_id(),
922 /* Initialize ethertype filter rule list and hash */
923 TAILQ_INIT(ðertype_rule->ethertype_list);
924 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
925 "ethertype_%s", dev->device->name);
926 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
927 if (!ethertype_rule->hash_table) {
928 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
931 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
932 sizeof(struct i40e_ethertype_filter *) *
933 I40E_MAX_ETHERTYPE_FILTER_NUM,
935 if (!ethertype_rule->hash_map) {
937 "Failed to allocate memory for ethertype hash map!");
939 goto err_ethertype_hash_map_alloc;
944 err_ethertype_hash_map_alloc:
945 rte_hash_free(ethertype_rule->hash_table);
951 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
953 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
954 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
955 char tunnel_hash_name[RTE_HASH_NAMESIZE];
958 struct rte_hash_parameters tunnel_hash_params = {
959 .name = tunnel_hash_name,
960 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
961 .key_len = sizeof(struct i40e_tunnel_filter_input),
962 .hash_func = rte_hash_crc,
963 .hash_func_init_val = 0,
964 .socket_id = rte_socket_id(),
967 /* Initialize tunnel filter rule list and hash */
968 TAILQ_INIT(&tunnel_rule->tunnel_list);
969 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
970 "tunnel_%s", dev->device->name);
971 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
972 if (!tunnel_rule->hash_table) {
973 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
976 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
977 sizeof(struct i40e_tunnel_filter *) *
978 I40E_MAX_TUNNEL_FILTER_NUM,
980 if (!tunnel_rule->hash_map) {
982 "Failed to allocate memory for tunnel hash map!");
984 goto err_tunnel_hash_map_alloc;
989 err_tunnel_hash_map_alloc:
990 rte_hash_free(tunnel_rule->hash_table);
996 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
998 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
999 struct i40e_fdir_info *fdir_info = &pf->fdir;
1000 char fdir_hash_name[RTE_HASH_NAMESIZE];
1003 struct rte_hash_parameters fdir_hash_params = {
1004 .name = fdir_hash_name,
1005 .entries = I40E_MAX_FDIR_FILTER_NUM,
1006 .key_len = sizeof(struct rte_eth_fdir_input),
1007 .hash_func = rte_hash_crc,
1008 .hash_func_init_val = 0,
1009 .socket_id = rte_socket_id(),
1012 /* Initialize flow director filter rule list and hash */
1013 TAILQ_INIT(&fdir_info->fdir_list);
1014 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1015 "fdir_%s", dev->device->name);
1016 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1017 if (!fdir_info->hash_table) {
1018 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1021 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1022 sizeof(struct i40e_fdir_filter *) *
1023 I40E_MAX_FDIR_FILTER_NUM,
1025 if (!fdir_info->hash_map) {
1027 "Failed to allocate memory for fdir hash map!");
1029 goto err_fdir_hash_map_alloc;
1033 err_fdir_hash_map_alloc:
1034 rte_hash_free(fdir_info->hash_table);
1040 eth_i40e_dev_init(struct rte_eth_dev *dev)
1042 struct rte_pci_device *pci_dev;
1043 struct rte_intr_handle *intr_handle;
1044 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1045 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1046 struct i40e_vsi *vsi;
1049 uint8_t aq_fail = 0;
1051 PMD_INIT_FUNC_TRACE();
1053 dev->dev_ops = &i40e_eth_dev_ops;
1054 dev->rx_pkt_burst = i40e_recv_pkts;
1055 dev->tx_pkt_burst = i40e_xmit_pkts;
1056 dev->tx_pkt_prepare = i40e_prep_pkts;
1058 /* for secondary processes, we don't initialise any further as primary
1059 * has already done this work. Only check we don't need a different
1061 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1062 i40e_set_rx_function(dev);
1063 i40e_set_tx_function(dev);
1066 i40e_set_default_ptype_table(dev);
1067 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1068 intr_handle = &pci_dev->intr_handle;
1070 rte_eth_copy_pci_info(dev, pci_dev);
1071 dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1073 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1074 pf->adapter->eth_dev = dev;
1075 pf->dev_data = dev->data;
1077 hw->back = I40E_PF_TO_ADAPTER(pf);
1078 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1081 "Hardware is not available, as address is NULL");
1085 hw->vendor_id = pci_dev->id.vendor_id;
1086 hw->device_id = pci_dev->id.device_id;
1087 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1088 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1089 hw->bus.device = pci_dev->addr.devid;
1090 hw->bus.func = pci_dev->addr.function;
1091 hw->adapter_stopped = 0;
1093 /* Make sure all is clean before doing PF reset */
1096 /* Initialize the hardware */
1099 /* Reset here to make sure all is clean for each PF */
1100 ret = i40e_pf_reset(hw);
1102 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1106 /* Initialize the shared code (base driver) */
1107 ret = i40e_init_shared_code(hw);
1109 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1114 * To work around the NVM issue, initialize registers
1115 * for flexible payload and packet type of QinQ by
1116 * software. It should be removed once issues are fixed
1119 i40e_GLQF_reg_init(hw);
1121 /* Initialize the input set for filters (hash and fd) to default value */
1122 i40e_filter_input_set_init(pf);
1124 /* Initialize the parameters for adminq */
1125 i40e_init_adminq_parameter(hw);
1126 ret = i40e_init_adminq(hw);
1127 if (ret != I40E_SUCCESS) {
1128 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1131 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1132 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1133 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1134 ((hw->nvm.version >> 12) & 0xf),
1135 ((hw->nvm.version >> 4) & 0xff),
1136 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1138 /* initialise the L3_MAP register */
1139 ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1142 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
1144 /* Need the special FW version to support floating VEB */
1145 config_floating_veb(dev);
1146 /* Clear PXE mode */
1147 i40e_clear_pxe_mode(hw);
1148 i40e_dev_sync_phy_type(hw);
1151 * On X710, performance number is far from the expectation on recent
1152 * firmware versions. The fix for this issue may not be integrated in
1153 * the following firmware version. So the workaround in software driver
1154 * is needed. It needs to modify the initial values of 3 internal only
1155 * registers. Note that the workaround can be removed when it is fixed
1156 * in firmware in the future.
1158 i40e_configure_registers(hw);
1160 /* Get hw capabilities */
1161 ret = i40e_get_cap(hw);
1162 if (ret != I40E_SUCCESS) {
1163 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1164 goto err_get_capabilities;
1167 /* Initialize parameters for PF */
1168 ret = i40e_pf_parameter_init(dev);
1170 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1171 goto err_parameter_init;
1174 /* Initialize the queue management */
1175 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1177 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1178 goto err_qp_pool_init;
1180 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1181 hw->func_caps.num_msix_vectors - 1);
1183 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1184 goto err_msix_pool_init;
1187 /* Initialize lan hmc */
1188 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1189 hw->func_caps.num_rx_qp, 0, 0);
1190 if (ret != I40E_SUCCESS) {
1191 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1192 goto err_init_lan_hmc;
1195 /* Configure lan hmc */
1196 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1197 if (ret != I40E_SUCCESS) {
1198 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1199 goto err_configure_lan_hmc;
1202 /* Get and check the mac address */
1203 i40e_get_mac_addr(hw, hw->mac.addr);
1204 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1205 PMD_INIT_LOG(ERR, "mac address is not valid");
1207 goto err_get_mac_addr;
1209 /* Copy the permanent MAC address */
1210 ether_addr_copy((struct ether_addr *) hw->mac.addr,
1211 (struct ether_addr *) hw->mac.perm_addr);
1213 /* Disable flow control */
1214 hw->fc.requested_mode = I40E_FC_NONE;
1215 i40e_set_fc(hw, &aq_fail, TRUE);
1217 /* Set the global registers with default ether type value */
1218 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1219 if (ret != I40E_SUCCESS) {
1221 "Failed to set the default outer VLAN ether type");
1222 goto err_setup_pf_switch;
1225 /* PF setup, which includes VSI setup */
1226 ret = i40e_pf_setup(pf);
1228 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1229 goto err_setup_pf_switch;
1232 /* reset all stats of the device, including pf and main vsi */
1233 i40e_dev_stats_reset(dev);
1237 /* Disable double vlan by default */
1238 i40e_vsi_config_double_vlan(vsi, FALSE);
1240 /* Disable S-TAG identification when floating_veb is disabled */
1241 if (!pf->floating_veb) {
1242 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1243 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1244 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1245 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1249 if (!vsi->max_macaddrs)
1250 len = ETHER_ADDR_LEN;
1252 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1254 /* Should be after VSI initialized */
1255 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1256 if (!dev->data->mac_addrs) {
1258 "Failed to allocated memory for storing mac address");
1261 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1262 &dev->data->mac_addrs[0]);
1264 /* Init dcb to sw mode by default */
1265 ret = i40e_dcb_init_configure(dev, TRUE);
1266 if (ret != I40E_SUCCESS) {
1267 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1268 pf->flags &= ~I40E_FLAG_DCB;
1270 /* Update HW struct after DCB configuration */
1273 /* initialize pf host driver to setup SRIOV resource if applicable */
1274 i40e_pf_host_init(dev);
1276 /* register callback func to eal lib */
1277 rte_intr_callback_register(intr_handle,
1278 i40e_dev_interrupt_handler, dev);
1280 /* configure and enable device interrupt */
1281 i40e_pf_config_irq0(hw, TRUE);
1282 i40e_pf_enable_irq0(hw);
1284 /* enable uio intr after callback register */
1285 rte_intr_enable(intr_handle);
1287 * Add an ethertype filter to drop all flow control frames transmitted
1288 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1291 i40e_add_tx_flow_control_drop_filter(pf);
1293 /* Set the max frame size to 0x2600 by default,
1294 * in case other drivers changed the default value.
1296 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1298 /* initialize mirror rule list */
1299 TAILQ_INIT(&pf->mirror_list);
1301 /* initialize Traffic Manager configuration */
1302 i40e_tm_conf_init(dev);
1304 ret = i40e_init_ethtype_filter_list(dev);
1306 goto err_init_ethtype_filter_list;
1307 ret = i40e_init_tunnel_filter_list(dev);
1309 goto err_init_tunnel_filter_list;
1310 ret = i40e_init_fdir_filter_list(dev);
1312 goto err_init_fdir_filter_list;
1316 err_init_fdir_filter_list:
1317 rte_free(pf->tunnel.hash_table);
1318 rte_free(pf->tunnel.hash_map);
1319 err_init_tunnel_filter_list:
1320 rte_free(pf->ethertype.hash_table);
1321 rte_free(pf->ethertype.hash_map);
1322 err_init_ethtype_filter_list:
1323 rte_free(dev->data->mac_addrs);
1325 i40e_vsi_release(pf->main_vsi);
1326 err_setup_pf_switch:
1328 err_configure_lan_hmc:
1329 (void)i40e_shutdown_lan_hmc(hw);
1331 i40e_res_pool_destroy(&pf->msix_pool);
1333 i40e_res_pool_destroy(&pf->qp_pool);
1336 err_get_capabilities:
1337 (void)i40e_shutdown_adminq(hw);
1343 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1345 struct i40e_ethertype_filter *p_ethertype;
1346 struct i40e_ethertype_rule *ethertype_rule;
1348 ethertype_rule = &pf->ethertype;
1349 /* Remove all ethertype filter rules and hash */
1350 if (ethertype_rule->hash_map)
1351 rte_free(ethertype_rule->hash_map);
1352 if (ethertype_rule->hash_table)
1353 rte_hash_free(ethertype_rule->hash_table);
1355 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1356 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1357 p_ethertype, rules);
1358 rte_free(p_ethertype);
1363 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1365 struct i40e_tunnel_filter *p_tunnel;
1366 struct i40e_tunnel_rule *tunnel_rule;
1368 tunnel_rule = &pf->tunnel;
1369 /* Remove all tunnel director rules and hash */
1370 if (tunnel_rule->hash_map)
1371 rte_free(tunnel_rule->hash_map);
1372 if (tunnel_rule->hash_table)
1373 rte_hash_free(tunnel_rule->hash_table);
1375 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1376 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1382 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1384 struct i40e_fdir_filter *p_fdir;
1385 struct i40e_fdir_info *fdir_info;
1387 fdir_info = &pf->fdir;
1388 /* Remove all flow director rules and hash */
1389 if (fdir_info->hash_map)
1390 rte_free(fdir_info->hash_map);
1391 if (fdir_info->hash_table)
1392 rte_hash_free(fdir_info->hash_table);
1394 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1395 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1401 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1404 struct rte_pci_device *pci_dev;
1405 struct rte_intr_handle *intr_handle;
1407 struct i40e_filter_control_settings settings;
1408 struct rte_flow *p_flow;
1410 uint8_t aq_fail = 0;
1412 PMD_INIT_FUNC_TRACE();
1414 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1417 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1418 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1419 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1420 intr_handle = &pci_dev->intr_handle;
1422 if (hw->adapter_stopped == 0)
1423 i40e_dev_close(dev);
1425 dev->dev_ops = NULL;
1426 dev->rx_pkt_burst = NULL;
1427 dev->tx_pkt_burst = NULL;
1429 /* Clear PXE mode */
1430 i40e_clear_pxe_mode(hw);
1432 /* Unconfigure filter control */
1433 memset(&settings, 0, sizeof(settings));
1434 ret = i40e_set_filter_control(hw, &settings);
1436 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1439 /* Disable flow control */
1440 hw->fc.requested_mode = I40E_FC_NONE;
1441 i40e_set_fc(hw, &aq_fail, TRUE);
1443 /* uninitialize pf host driver */
1444 i40e_pf_host_uninit(dev);
1446 rte_free(dev->data->mac_addrs);
1447 dev->data->mac_addrs = NULL;
1449 /* disable uio intr before callback unregister */
1450 rte_intr_disable(intr_handle);
1452 /* register callback func to eal lib */
1453 rte_intr_callback_unregister(intr_handle,
1454 i40e_dev_interrupt_handler, dev);
1456 i40e_rm_ethtype_filter_list(pf);
1457 i40e_rm_tunnel_filter_list(pf);
1458 i40e_rm_fdir_filter_list(pf);
1460 /* Remove all flows */
1461 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1462 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1466 /* Remove all Traffic Manager configuration */
1467 i40e_tm_conf_uninit(dev);
1473 i40e_dev_configure(struct rte_eth_dev *dev)
1475 struct i40e_adapter *ad =
1476 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1477 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1478 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1479 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1482 ret = i40e_dev_sync_phy_type(hw);
1486 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1487 * bulk allocation or vector Rx preconditions we will reset it.
1489 ad->rx_bulk_alloc_allowed = true;
1490 ad->rx_vec_allowed = true;
1491 ad->tx_simple_allowed = true;
1492 ad->tx_vec_allowed = true;
1494 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1495 ret = i40e_fdir_setup(pf);
1496 if (ret != I40E_SUCCESS) {
1497 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1500 ret = i40e_fdir_configure(dev);
1502 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1506 i40e_fdir_teardown(pf);
1508 ret = i40e_dev_init_vlan(dev);
1513 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1514 * RSS setting have different requirements.
1515 * General PMD driver call sequence are NIC init, configure,
1516 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1517 * will try to lookup the VSI that specific queue belongs to if VMDQ
1518 * applicable. So, VMDQ setting has to be done before
1519 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1520 * For RSS setting, it will try to calculate actual configured RX queue
1521 * number, which will be available after rx_queue_setup(). dev_start()
1522 * function is good to place RSS setup.
1524 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1525 ret = i40e_vmdq_setup(dev);
1530 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1531 ret = i40e_dcb_setup(dev);
1533 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1538 TAILQ_INIT(&pf->flow_list);
1543 /* need to release vmdq resource if exists */
1544 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1545 i40e_vsi_release(pf->vmdq[i].vsi);
1546 pf->vmdq[i].vsi = NULL;
1551 /* need to release fdir resource if exists */
1552 i40e_fdir_teardown(pf);
1557 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1559 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1560 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1561 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1562 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1563 uint16_t msix_vect = vsi->msix_intr;
1566 for (i = 0; i < vsi->nb_qps; i++) {
1567 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1568 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1572 if (vsi->type != I40E_VSI_SRIOV) {
1573 if (!rte_intr_allow_others(intr_handle)) {
1574 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1575 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1577 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1580 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1581 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1583 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1588 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1589 vsi->user_param + (msix_vect - 1);
1591 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1592 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1594 I40E_WRITE_FLUSH(hw);
1598 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1599 int base_queue, int nb_queue)
1603 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1605 /* Bind all RX queues to allocated MSIX interrupt */
1606 for (i = 0; i < nb_queue; i++) {
1607 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1608 I40E_QINT_RQCTL_ITR_INDX_MASK |
1609 ((base_queue + i + 1) <<
1610 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1611 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1612 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1614 if (i == nb_queue - 1)
1615 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1616 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1619 /* Write first RX queue to Link list register as the head element */
1620 if (vsi->type != I40E_VSI_SRIOV) {
1622 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1624 if (msix_vect == I40E_MISC_VEC_ID) {
1625 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1627 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1629 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1631 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1634 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1636 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1638 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1640 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1647 if (msix_vect == I40E_MISC_VEC_ID) {
1649 I40E_VPINT_LNKLST0(vsi->user_param),
1651 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1653 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1655 /* num_msix_vectors_vf needs to minus irq0 */
1656 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1657 vsi->user_param + (msix_vect - 1);
1659 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1661 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1663 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1667 I40E_WRITE_FLUSH(hw);
1671 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1673 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1674 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1675 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1676 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1677 uint16_t msix_vect = vsi->msix_intr;
1678 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1679 uint16_t queue_idx = 0;
1684 for (i = 0; i < vsi->nb_qps; i++) {
1685 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1686 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1689 /* INTENA flag is not auto-cleared for interrupt */
1690 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1691 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1692 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1693 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1694 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1696 /* VF bind interrupt */
1697 if (vsi->type == I40E_VSI_SRIOV) {
1698 __vsi_queues_bind_intr(vsi, msix_vect,
1699 vsi->base_queue, vsi->nb_qps);
1703 /* PF & VMDq bind interrupt */
1704 if (rte_intr_dp_is_en(intr_handle)) {
1705 if (vsi->type == I40E_VSI_MAIN) {
1708 } else if (vsi->type == I40E_VSI_VMDQ2) {
1709 struct i40e_vsi *main_vsi =
1710 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1711 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1716 for (i = 0; i < vsi->nb_used_qps; i++) {
1718 if (!rte_intr_allow_others(intr_handle))
1719 /* allow to share MISC_VEC_ID */
1720 msix_vect = I40E_MISC_VEC_ID;
1722 /* no enough msix_vect, map all to one */
1723 __vsi_queues_bind_intr(vsi, msix_vect,
1724 vsi->base_queue + i,
1725 vsi->nb_used_qps - i);
1726 for (; !!record && i < vsi->nb_used_qps; i++)
1727 intr_handle->intr_vec[queue_idx + i] =
1731 /* 1:1 queue/msix_vect mapping */
1732 __vsi_queues_bind_intr(vsi, msix_vect,
1733 vsi->base_queue + i, 1);
1735 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1743 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1745 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1746 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1747 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1748 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1749 uint16_t interval = i40e_calc_itr_interval(\
1750 RTE_LIBRTE_I40E_ITR_INTERVAL);
1751 uint16_t msix_intr, i;
1753 if (rte_intr_allow_others(intr_handle))
1754 for (i = 0; i < vsi->nb_msix; i++) {
1755 msix_intr = vsi->msix_intr + i;
1756 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1757 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1758 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1759 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1761 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1764 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1765 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1766 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1767 (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1769 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1771 I40E_WRITE_FLUSH(hw);
1775 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1777 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1778 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1779 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1780 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1781 uint16_t msix_intr, i;
1783 if (rte_intr_allow_others(intr_handle))
1784 for (i = 0; i < vsi->nb_msix; i++) {
1785 msix_intr = vsi->msix_intr + i;
1786 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1790 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1792 I40E_WRITE_FLUSH(hw);
1795 static inline uint8_t
1796 i40e_parse_link_speeds(uint16_t link_speeds)
1798 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1800 if (link_speeds & ETH_LINK_SPEED_40G)
1801 link_speed |= I40E_LINK_SPEED_40GB;
1802 if (link_speeds & ETH_LINK_SPEED_25G)
1803 link_speed |= I40E_LINK_SPEED_25GB;
1804 if (link_speeds & ETH_LINK_SPEED_20G)
1805 link_speed |= I40E_LINK_SPEED_20GB;
1806 if (link_speeds & ETH_LINK_SPEED_10G)
1807 link_speed |= I40E_LINK_SPEED_10GB;
1808 if (link_speeds & ETH_LINK_SPEED_1G)
1809 link_speed |= I40E_LINK_SPEED_1GB;
1810 if (link_speeds & ETH_LINK_SPEED_100M)
1811 link_speed |= I40E_LINK_SPEED_100MB;
1817 i40e_phy_conf_link(struct i40e_hw *hw,
1819 uint8_t force_speed,
1822 enum i40e_status_code status;
1823 struct i40e_aq_get_phy_abilities_resp phy_ab;
1824 struct i40e_aq_set_phy_config phy_conf;
1825 enum i40e_aq_phy_type cnt;
1826 uint32_t phy_type_mask = 0;
1828 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1829 I40E_AQ_PHY_FLAG_PAUSE_RX |
1830 I40E_AQ_PHY_FLAG_PAUSE_RX |
1831 I40E_AQ_PHY_FLAG_LOW_POWER;
1832 const uint8_t advt = I40E_LINK_SPEED_40GB |
1833 I40E_LINK_SPEED_25GB |
1834 I40E_LINK_SPEED_10GB |
1835 I40E_LINK_SPEED_1GB |
1836 I40E_LINK_SPEED_100MB;
1840 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1845 /* If link already up, no need to set up again */
1846 if (is_up && phy_ab.phy_type != 0)
1847 return I40E_SUCCESS;
1849 memset(&phy_conf, 0, sizeof(phy_conf));
1851 /* bits 0-2 use the values from get_phy_abilities_resp */
1853 abilities |= phy_ab.abilities & mask;
1855 /* update ablities and speed */
1856 if (abilities & I40E_AQ_PHY_AN_ENABLED)
1857 phy_conf.link_speed = advt;
1859 phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed;
1861 phy_conf.abilities = abilities;
1865 /* To enable link, phy_type mask needs to include each type */
1866 for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_MAX; cnt++)
1867 phy_type_mask |= 1 << cnt;
1869 /* use get_phy_abilities_resp value for the rest */
1870 phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
1871 phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
1872 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
1873 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
1874 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1875 phy_conf.eee_capability = phy_ab.eee_capability;
1876 phy_conf.eeer = phy_ab.eeer_val;
1877 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1879 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1880 phy_ab.abilities, phy_ab.link_speed);
1881 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
1882 phy_conf.abilities, phy_conf.link_speed);
1884 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1888 return I40E_SUCCESS;
1892 i40e_apply_link_speed(struct rte_eth_dev *dev)
1895 uint8_t abilities = 0;
1896 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1897 struct rte_eth_conf *conf = &dev->data->dev_conf;
1899 speed = i40e_parse_link_speeds(conf->link_speeds);
1900 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1901 if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1902 abilities |= I40E_AQ_PHY_AN_ENABLED;
1903 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1905 return i40e_phy_conf_link(hw, abilities, speed, true);
1909 i40e_dev_start(struct rte_eth_dev *dev)
1911 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1912 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1913 struct i40e_vsi *main_vsi = pf->main_vsi;
1915 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1916 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1917 uint32_t intr_vector = 0;
1918 struct i40e_vsi *vsi;
1920 hw->adapter_stopped = 0;
1922 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1923 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1924 dev->data->port_id);
1928 rte_intr_disable(intr_handle);
1930 if ((rte_intr_cap_multiple(intr_handle) ||
1931 !RTE_ETH_DEV_SRIOV(dev).active) &&
1932 dev->data->dev_conf.intr_conf.rxq != 0) {
1933 intr_vector = dev->data->nb_rx_queues;
1934 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1939 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1940 intr_handle->intr_vec =
1941 rte_zmalloc("intr_vec",
1942 dev->data->nb_rx_queues * sizeof(int),
1944 if (!intr_handle->intr_vec) {
1946 "Failed to allocate %d rx_queues intr_vec",
1947 dev->data->nb_rx_queues);
1952 /* Initialize VSI */
1953 ret = i40e_dev_rxtx_init(pf);
1954 if (ret != I40E_SUCCESS) {
1955 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1959 /* Map queues with MSIX interrupt */
1960 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1961 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1962 i40e_vsi_queues_bind_intr(main_vsi);
1963 i40e_vsi_enable_queues_intr(main_vsi);
1965 /* Map VMDQ VSI queues with MSIX interrupt */
1966 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1967 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1968 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1969 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1972 /* enable FDIR MSIX interrupt */
1973 if (pf->fdir.fdir_vsi) {
1974 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1975 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1978 /* Enable all queues which have been configured */
1979 ret = i40e_dev_switch_queues(pf, TRUE);
1980 if (ret != I40E_SUCCESS) {
1981 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1985 /* Enable receiving broadcast packets */
1986 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1987 if (ret != I40E_SUCCESS)
1988 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1990 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1991 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1993 if (ret != I40E_SUCCESS)
1994 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1997 /* Enable the VLAN promiscuous mode. */
1999 for (i = 0; i < pf->vf_num; i++) {
2000 vsi = pf->vfs[i].vsi;
2001 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2006 /* Apply link configure */
2007 if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
2008 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
2009 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
2010 ETH_LINK_SPEED_40G)) {
2011 PMD_DRV_LOG(ERR, "Invalid link setting");
2014 ret = i40e_apply_link_speed(dev);
2015 if (I40E_SUCCESS != ret) {
2016 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2020 if (!rte_intr_allow_others(intr_handle)) {
2021 rte_intr_callback_unregister(intr_handle,
2022 i40e_dev_interrupt_handler,
2024 /* configure and enable device interrupt */
2025 i40e_pf_config_irq0(hw, FALSE);
2026 i40e_pf_enable_irq0(hw);
2028 if (dev->data->dev_conf.intr_conf.lsc != 0)
2030 "lsc won't enable because of no intr multiplex");
2032 ret = i40e_aq_set_phy_int_mask(hw,
2033 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2034 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2035 I40E_AQ_EVENT_MEDIA_NA), NULL);
2036 if (ret != I40E_SUCCESS)
2037 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2039 /* Call get_link_info aq commond to enable/disable LSE */
2040 i40e_dev_link_update(dev, 0);
2043 /* enable uio intr after callback register */
2044 rte_intr_enable(intr_handle);
2046 i40e_filter_restore(pf);
2048 if (pf->tm_conf.root && !pf->tm_conf.committed)
2049 PMD_DRV_LOG(WARNING,
2050 "please call hierarchy_commit() "
2051 "before starting the port");
2053 return I40E_SUCCESS;
2056 i40e_dev_switch_queues(pf, FALSE);
2057 i40e_dev_clear_queues(dev);
2063 i40e_dev_stop(struct rte_eth_dev *dev)
2065 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2066 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2067 struct i40e_vsi *main_vsi = pf->main_vsi;
2068 struct i40e_mirror_rule *p_mirror;
2069 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2070 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2073 if (hw->adapter_stopped == 1)
2075 /* Disable all queues */
2076 i40e_dev_switch_queues(pf, FALSE);
2078 /* un-map queues with interrupt registers */
2079 i40e_vsi_disable_queues_intr(main_vsi);
2080 i40e_vsi_queues_unbind_intr(main_vsi);
2082 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2083 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2084 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2087 if (pf->fdir.fdir_vsi) {
2088 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2089 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2091 /* Clear all queues and release memory */
2092 i40e_dev_clear_queues(dev);
2095 i40e_dev_set_link_down(dev);
2097 /* Remove all mirror rules */
2098 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2099 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2102 pf->nb_mirror_rule = 0;
2104 if (!rte_intr_allow_others(intr_handle))
2105 /* resume to the default handler */
2106 rte_intr_callback_register(intr_handle,
2107 i40e_dev_interrupt_handler,
2110 /* Clean datapath event and queue/vec mapping */
2111 rte_intr_efd_disable(intr_handle);
2112 if (intr_handle->intr_vec) {
2113 rte_free(intr_handle->intr_vec);
2114 intr_handle->intr_vec = NULL;
2117 /* reset hierarchy commit */
2118 pf->tm_conf.committed = false;
2120 hw->adapter_stopped = 1;
2124 i40e_dev_close(struct rte_eth_dev *dev)
2126 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2127 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2128 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2129 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2133 PMD_INIT_FUNC_TRACE();
2136 i40e_dev_free_queues(dev);
2138 /* Disable interrupt */
2139 i40e_pf_disable_irq0(hw);
2140 rte_intr_disable(intr_handle);
2142 /* shutdown and destroy the HMC */
2143 i40e_shutdown_lan_hmc(hw);
2145 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2146 i40e_vsi_release(pf->vmdq[i].vsi);
2147 pf->vmdq[i].vsi = NULL;
2152 /* release all the existing VSIs and VEBs */
2153 i40e_fdir_teardown(pf);
2154 i40e_vsi_release(pf->main_vsi);
2156 /* shutdown the adminq */
2157 i40e_aq_queue_shutdown(hw, true);
2158 i40e_shutdown_adminq(hw);
2160 i40e_res_pool_destroy(&pf->qp_pool);
2161 i40e_res_pool_destroy(&pf->msix_pool);
2163 /* force a PF reset to clean anything leftover */
2164 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2165 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2166 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2167 I40E_WRITE_FLUSH(hw);
2171 * Reset PF device only to re-initialize resources in PMD layer
2174 i40e_dev_reset(struct rte_eth_dev *dev)
2178 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2179 * its VF to make them align with it. The detailed notification
2180 * mechanism is PMD specific. As to i40e PF, it is rather complex.
2181 * To avoid unexpected behavior in VF, currently reset of PF with
2182 * SR-IOV activation is not supported. It might be supported later.
2184 if (dev->data->sriov.active)
2187 ret = eth_i40e_dev_uninit(dev);
2191 ret = eth_i40e_dev_init(dev);
2197 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2199 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2200 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2201 struct i40e_vsi *vsi = pf->main_vsi;
2204 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2206 if (status != I40E_SUCCESS)
2207 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2209 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2211 if (status != I40E_SUCCESS)
2212 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2217 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2219 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2220 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2221 struct i40e_vsi *vsi = pf->main_vsi;
2224 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2226 if (status != I40E_SUCCESS)
2227 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2229 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2231 if (status != I40E_SUCCESS)
2232 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2236 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2238 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2239 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2240 struct i40e_vsi *vsi = pf->main_vsi;
2243 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2244 if (ret != I40E_SUCCESS)
2245 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2249 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2251 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2252 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2253 struct i40e_vsi *vsi = pf->main_vsi;
2256 if (dev->data->promiscuous == 1)
2257 return; /* must remain in all_multicast mode */
2259 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2260 vsi->seid, FALSE, NULL);
2261 if (ret != I40E_SUCCESS)
2262 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2266 * Set device link up.
2269 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2271 /* re-apply link speed setting */
2272 return i40e_apply_link_speed(dev);
2276 * Set device link down.
2279 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2281 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2282 uint8_t abilities = 0;
2283 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2285 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2286 return i40e_phy_conf_link(hw, abilities, speed, false);
2290 i40e_dev_link_update(struct rte_eth_dev *dev,
2291 int wait_to_complete)
2293 #define CHECK_INTERVAL 100 /* 100ms */
2294 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2295 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2296 struct i40e_link_status link_status;
2297 struct rte_eth_link link, old;
2299 unsigned rep_cnt = MAX_REPEAT_TIME;
2300 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2302 memset(&link, 0, sizeof(link));
2303 memset(&old, 0, sizeof(old));
2304 memset(&link_status, 0, sizeof(link_status));
2305 rte_i40e_dev_atomic_read_link_status(dev, &old);
2308 /* Get link status information from hardware */
2309 status = i40e_aq_get_link_info(hw, enable_lse,
2310 &link_status, NULL);
2311 if (status != I40E_SUCCESS) {
2312 link.link_speed = ETH_SPEED_NUM_100M;
2313 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2314 PMD_DRV_LOG(ERR, "Failed to get link info");
2318 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2319 if (!wait_to_complete || link.link_status)
2322 rte_delay_ms(CHECK_INTERVAL);
2323 } while (--rep_cnt);
2325 if (!link.link_status)
2328 /* i40e uses full duplex only */
2329 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2331 /* Parse the link status */
2332 switch (link_status.link_speed) {
2333 case I40E_LINK_SPEED_100MB:
2334 link.link_speed = ETH_SPEED_NUM_100M;
2336 case I40E_LINK_SPEED_1GB:
2337 link.link_speed = ETH_SPEED_NUM_1G;
2339 case I40E_LINK_SPEED_10GB:
2340 link.link_speed = ETH_SPEED_NUM_10G;
2342 case I40E_LINK_SPEED_20GB:
2343 link.link_speed = ETH_SPEED_NUM_20G;
2345 case I40E_LINK_SPEED_25GB:
2346 link.link_speed = ETH_SPEED_NUM_25G;
2348 case I40E_LINK_SPEED_40GB:
2349 link.link_speed = ETH_SPEED_NUM_40G;
2352 link.link_speed = ETH_SPEED_NUM_100M;
2356 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2357 ETH_LINK_SPEED_FIXED);
2360 rte_i40e_dev_atomic_write_link_status(dev, &link);
2361 if (link.link_status == old.link_status)
2364 i40e_notify_all_vfs_link_status(dev);
2369 /* Get all the statistics of a VSI */
2371 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2373 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2374 struct i40e_eth_stats *nes = &vsi->eth_stats;
2375 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2376 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2378 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2379 vsi->offset_loaded, &oes->rx_bytes,
2381 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2382 vsi->offset_loaded, &oes->rx_unicast,
2384 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2385 vsi->offset_loaded, &oes->rx_multicast,
2386 &nes->rx_multicast);
2387 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2388 vsi->offset_loaded, &oes->rx_broadcast,
2389 &nes->rx_broadcast);
2390 /* exclude CRC bytes */
2391 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2392 nes->rx_broadcast) * ETHER_CRC_LEN;
2394 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2395 &oes->rx_discards, &nes->rx_discards);
2396 /* GLV_REPC not supported */
2397 /* GLV_RMPC not supported */
2398 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2399 &oes->rx_unknown_protocol,
2400 &nes->rx_unknown_protocol);
2401 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2402 vsi->offset_loaded, &oes->tx_bytes,
2404 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2405 vsi->offset_loaded, &oes->tx_unicast,
2407 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2408 vsi->offset_loaded, &oes->tx_multicast,
2409 &nes->tx_multicast);
2410 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2411 vsi->offset_loaded, &oes->tx_broadcast,
2412 &nes->tx_broadcast);
2413 /* GLV_TDPC not supported */
2414 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2415 &oes->tx_errors, &nes->tx_errors);
2416 vsi->offset_loaded = true;
2418 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2420 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2421 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2422 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2423 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2424 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2425 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2426 nes->rx_unknown_protocol);
2427 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2428 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2429 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2430 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2431 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2432 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2433 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2438 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2441 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2442 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2444 /* Get rx/tx bytes of internal transfer packets */
2445 i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2446 I40E_GLV_GORCL(hw->port),
2448 &pf->internal_stats_offset.rx_bytes,
2449 &pf->internal_stats.rx_bytes);
2451 i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2452 I40E_GLV_GOTCL(hw->port),
2454 &pf->internal_stats_offset.tx_bytes,
2455 &pf->internal_stats.tx_bytes);
2456 /* Get total internal rx packet count */
2457 i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2458 I40E_GLV_UPRCL(hw->port),
2460 &pf->internal_stats_offset.rx_unicast,
2461 &pf->internal_stats.rx_unicast);
2462 i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2463 I40E_GLV_MPRCL(hw->port),
2465 &pf->internal_stats_offset.rx_multicast,
2466 &pf->internal_stats.rx_multicast);
2467 i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2468 I40E_GLV_BPRCL(hw->port),
2470 &pf->internal_stats_offset.rx_broadcast,
2471 &pf->internal_stats.rx_broadcast);
2473 /* exclude CRC size */
2474 pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2475 pf->internal_stats.rx_multicast +
2476 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2478 /* Get statistics of struct i40e_eth_stats */
2479 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2480 I40E_GLPRT_GORCL(hw->port),
2481 pf->offset_loaded, &os->eth.rx_bytes,
2483 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2484 I40E_GLPRT_UPRCL(hw->port),
2485 pf->offset_loaded, &os->eth.rx_unicast,
2486 &ns->eth.rx_unicast);
2487 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2488 I40E_GLPRT_MPRCL(hw->port),
2489 pf->offset_loaded, &os->eth.rx_multicast,
2490 &ns->eth.rx_multicast);
2491 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2492 I40E_GLPRT_BPRCL(hw->port),
2493 pf->offset_loaded, &os->eth.rx_broadcast,
2494 &ns->eth.rx_broadcast);
2495 /* Workaround: CRC size should not be included in byte statistics,
2496 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2498 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2499 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2501 /* Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2502 * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negtive
2505 if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2506 ns->eth.rx_bytes = 0;
2507 /* exlude internal rx bytes */
2509 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2511 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2512 pf->offset_loaded, &os->eth.rx_discards,
2513 &ns->eth.rx_discards);
2514 /* GLPRT_REPC not supported */
2515 /* GLPRT_RMPC not supported */
2516 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2518 &os->eth.rx_unknown_protocol,
2519 &ns->eth.rx_unknown_protocol);
2520 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2521 I40E_GLPRT_GOTCL(hw->port),
2522 pf->offset_loaded, &os->eth.tx_bytes,
2524 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2525 I40E_GLPRT_UPTCL(hw->port),
2526 pf->offset_loaded, &os->eth.tx_unicast,
2527 &ns->eth.tx_unicast);
2528 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2529 I40E_GLPRT_MPTCL(hw->port),
2530 pf->offset_loaded, &os->eth.tx_multicast,
2531 &ns->eth.tx_multicast);
2532 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2533 I40E_GLPRT_BPTCL(hw->port),
2534 pf->offset_loaded, &os->eth.tx_broadcast,
2535 &ns->eth.tx_broadcast);
2536 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2537 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2539 /* exclude internal tx bytes */
2540 if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2541 ns->eth.tx_bytes = 0;
2543 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2545 /* GLPRT_TEPC not supported */
2547 /* additional port specific stats */
2548 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2549 pf->offset_loaded, &os->tx_dropped_link_down,
2550 &ns->tx_dropped_link_down);
2551 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2552 pf->offset_loaded, &os->crc_errors,
2554 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2555 pf->offset_loaded, &os->illegal_bytes,
2556 &ns->illegal_bytes);
2557 /* GLPRT_ERRBC not supported */
2558 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2559 pf->offset_loaded, &os->mac_local_faults,
2560 &ns->mac_local_faults);
2561 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2562 pf->offset_loaded, &os->mac_remote_faults,
2563 &ns->mac_remote_faults);
2564 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2565 pf->offset_loaded, &os->rx_length_errors,
2566 &ns->rx_length_errors);
2567 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2568 pf->offset_loaded, &os->link_xon_rx,
2570 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2571 pf->offset_loaded, &os->link_xoff_rx,
2573 for (i = 0; i < 8; i++) {
2574 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2576 &os->priority_xon_rx[i],
2577 &ns->priority_xon_rx[i]);
2578 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2580 &os->priority_xoff_rx[i],
2581 &ns->priority_xoff_rx[i]);
2583 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2584 pf->offset_loaded, &os->link_xon_tx,
2586 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2587 pf->offset_loaded, &os->link_xoff_tx,
2589 for (i = 0; i < 8; i++) {
2590 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2592 &os->priority_xon_tx[i],
2593 &ns->priority_xon_tx[i]);
2594 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2596 &os->priority_xoff_tx[i],
2597 &ns->priority_xoff_tx[i]);
2598 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2600 &os->priority_xon_2_xoff[i],
2601 &ns->priority_xon_2_xoff[i]);
2603 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2604 I40E_GLPRT_PRC64L(hw->port),
2605 pf->offset_loaded, &os->rx_size_64,
2607 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2608 I40E_GLPRT_PRC127L(hw->port),
2609 pf->offset_loaded, &os->rx_size_127,
2611 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2612 I40E_GLPRT_PRC255L(hw->port),
2613 pf->offset_loaded, &os->rx_size_255,
2615 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2616 I40E_GLPRT_PRC511L(hw->port),
2617 pf->offset_loaded, &os->rx_size_511,
2619 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2620 I40E_GLPRT_PRC1023L(hw->port),
2621 pf->offset_loaded, &os->rx_size_1023,
2623 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2624 I40E_GLPRT_PRC1522L(hw->port),
2625 pf->offset_loaded, &os->rx_size_1522,
2627 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2628 I40E_GLPRT_PRC9522L(hw->port),
2629 pf->offset_loaded, &os->rx_size_big,
2631 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2632 pf->offset_loaded, &os->rx_undersize,
2634 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2635 pf->offset_loaded, &os->rx_fragments,
2637 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2638 pf->offset_loaded, &os->rx_oversize,
2640 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2641 pf->offset_loaded, &os->rx_jabber,
2643 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2644 I40E_GLPRT_PTC64L(hw->port),
2645 pf->offset_loaded, &os->tx_size_64,
2647 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2648 I40E_GLPRT_PTC127L(hw->port),
2649 pf->offset_loaded, &os->tx_size_127,
2651 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2652 I40E_GLPRT_PTC255L(hw->port),
2653 pf->offset_loaded, &os->tx_size_255,
2655 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2656 I40E_GLPRT_PTC511L(hw->port),
2657 pf->offset_loaded, &os->tx_size_511,
2659 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2660 I40E_GLPRT_PTC1023L(hw->port),
2661 pf->offset_loaded, &os->tx_size_1023,
2663 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2664 I40E_GLPRT_PTC1522L(hw->port),
2665 pf->offset_loaded, &os->tx_size_1522,
2667 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2668 I40E_GLPRT_PTC9522L(hw->port),
2669 pf->offset_loaded, &os->tx_size_big,
2671 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2673 &os->fd_sb_match, &ns->fd_sb_match);
2674 /* GLPRT_MSPDC not supported */
2675 /* GLPRT_XEC not supported */
2677 pf->offset_loaded = true;
2680 i40e_update_vsi_stats(pf->main_vsi);
2683 /* Get all statistics of a port */
2685 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2687 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2688 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2689 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2692 /* call read registers - updates values, now write them to struct */
2693 i40e_read_stats_registers(pf, hw);
2695 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2696 pf->main_vsi->eth_stats.rx_multicast +
2697 pf->main_vsi->eth_stats.rx_broadcast -
2698 pf->main_vsi->eth_stats.rx_discards;
2699 stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2700 pf->main_vsi->eth_stats.tx_multicast +
2701 pf->main_vsi->eth_stats.tx_broadcast;
2702 stats->ibytes = ns->eth.rx_bytes;
2703 stats->obytes = ns->eth.tx_bytes;
2704 stats->oerrors = ns->eth.tx_errors +
2705 pf->main_vsi->eth_stats.tx_errors;
2708 stats->imissed = ns->eth.rx_discards +
2709 pf->main_vsi->eth_stats.rx_discards;
2710 stats->ierrors = ns->crc_errors +
2711 ns->rx_length_errors + ns->rx_undersize +
2712 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2714 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2715 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
2716 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
2717 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
2718 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
2719 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
2720 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2721 ns->eth.rx_unknown_protocol);
2722 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
2723 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
2724 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
2725 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
2726 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
2727 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
2729 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
2730 ns->tx_dropped_link_down);
2731 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
2732 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
2734 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
2735 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
2736 ns->mac_local_faults);
2737 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
2738 ns->mac_remote_faults);
2739 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
2740 ns->rx_length_errors);
2741 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
2742 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
2743 for (i = 0; i < 8; i++) {
2744 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
2745 i, ns->priority_xon_rx[i]);
2746 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
2747 i, ns->priority_xoff_rx[i]);
2749 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
2750 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
2751 for (i = 0; i < 8; i++) {
2752 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
2753 i, ns->priority_xon_tx[i]);
2754 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
2755 i, ns->priority_xoff_tx[i]);
2756 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
2757 i, ns->priority_xon_2_xoff[i]);
2759 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
2760 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
2761 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
2762 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
2763 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
2764 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
2765 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
2766 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
2767 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
2768 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
2769 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
2770 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
2771 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
2772 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
2773 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
2774 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
2775 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
2776 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
2777 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2778 ns->mac_short_packet_dropped);
2779 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
2780 ns->checksum_error);
2781 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
2782 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2785 /* Reset the statistics */
2787 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2789 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2790 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2792 /* Mark PF and VSI stats to update the offset, aka "reset" */
2793 pf->offset_loaded = false;
2795 pf->main_vsi->offset_loaded = false;
2797 /* read the stats, reading current register values into offset */
2798 i40e_read_stats_registers(pf, hw);
2802 i40e_xstats_calc_num(void)
2804 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2805 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2806 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2809 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2810 struct rte_eth_xstat_name *xstats_names,
2811 __rte_unused unsigned limit)
2816 if (xstats_names == NULL)
2817 return i40e_xstats_calc_num();
2819 /* Note: limit checked in rte_eth_xstats_names() */
2821 /* Get stats from i40e_eth_stats struct */
2822 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2823 snprintf(xstats_names[count].name,
2824 sizeof(xstats_names[count].name),
2825 "%s", rte_i40e_stats_strings[i].name);
2829 /* Get individiual stats from i40e_hw_port struct */
2830 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2831 snprintf(xstats_names[count].name,
2832 sizeof(xstats_names[count].name),
2833 "%s", rte_i40e_hw_port_strings[i].name);
2837 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2838 for (prio = 0; prio < 8; prio++) {
2839 snprintf(xstats_names[count].name,
2840 sizeof(xstats_names[count].name),
2841 "rx_priority%u_%s", prio,
2842 rte_i40e_rxq_prio_strings[i].name);
2847 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2848 for (prio = 0; prio < 8; prio++) {
2849 snprintf(xstats_names[count].name,
2850 sizeof(xstats_names[count].name),
2851 "tx_priority%u_%s", prio,
2852 rte_i40e_txq_prio_strings[i].name);
2860 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2863 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2864 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2865 unsigned i, count, prio;
2866 struct i40e_hw_port_stats *hw_stats = &pf->stats;
2868 count = i40e_xstats_calc_num();
2872 i40e_read_stats_registers(pf, hw);
2879 /* Get stats from i40e_eth_stats struct */
2880 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2881 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2882 rte_i40e_stats_strings[i].offset);
2883 xstats[count].id = count;
2887 /* Get individiual stats from i40e_hw_port struct */
2888 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2889 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2890 rte_i40e_hw_port_strings[i].offset);
2891 xstats[count].id = count;
2895 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2896 for (prio = 0; prio < 8; prio++) {
2897 xstats[count].value =
2898 *(uint64_t *)(((char *)hw_stats) +
2899 rte_i40e_rxq_prio_strings[i].offset +
2900 (sizeof(uint64_t) * prio));
2901 xstats[count].id = count;
2906 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2907 for (prio = 0; prio < 8; prio++) {
2908 xstats[count].value =
2909 *(uint64_t *)(((char *)hw_stats) +
2910 rte_i40e_txq_prio_strings[i].offset +
2911 (sizeof(uint64_t) * prio));
2912 xstats[count].id = count;
2921 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2922 __rte_unused uint16_t queue_id,
2923 __rte_unused uint8_t stat_idx,
2924 __rte_unused uint8_t is_rx)
2926 PMD_INIT_FUNC_TRACE();
2932 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2934 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2940 full_ver = hw->nvm.oem_ver;
2941 ver = (u8)(full_ver >> 24);
2942 build = (u16)((full_ver >> 8) & 0xffff);
2943 patch = (u8)(full_ver & 0xff);
2945 ret = snprintf(fw_version, fw_size,
2946 "%d.%d%d 0x%08x %d.%d.%d",
2947 ((hw->nvm.version >> 12) & 0xf),
2948 ((hw->nvm.version >> 4) & 0xff),
2949 (hw->nvm.version & 0xf), hw->nvm.eetrack,
2952 ret += 1; /* add the size of '\0' */
2953 if (fw_size < (u32)ret)
2960 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2962 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2963 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2964 struct i40e_vsi *vsi = pf->main_vsi;
2965 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2967 dev_info->pci_dev = pci_dev;
2968 dev_info->max_rx_queues = vsi->nb_qps;
2969 dev_info->max_tx_queues = vsi->nb_qps;
2970 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2971 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2972 dev_info->max_mac_addrs = vsi->max_macaddrs;
2973 dev_info->max_vfs = pci_dev->max_vfs;
2974 dev_info->rx_offload_capa =
2975 DEV_RX_OFFLOAD_VLAN_STRIP |
2976 DEV_RX_OFFLOAD_QINQ_STRIP |
2977 DEV_RX_OFFLOAD_IPV4_CKSUM |
2978 DEV_RX_OFFLOAD_UDP_CKSUM |
2979 DEV_RX_OFFLOAD_TCP_CKSUM;
2980 dev_info->tx_offload_capa =
2981 DEV_TX_OFFLOAD_VLAN_INSERT |
2982 DEV_TX_OFFLOAD_QINQ_INSERT |
2983 DEV_TX_OFFLOAD_IPV4_CKSUM |
2984 DEV_TX_OFFLOAD_UDP_CKSUM |
2985 DEV_TX_OFFLOAD_TCP_CKSUM |
2986 DEV_TX_OFFLOAD_SCTP_CKSUM |
2987 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2988 DEV_TX_OFFLOAD_TCP_TSO |
2989 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2990 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2991 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2992 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2993 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2995 dev_info->reta_size = pf->hash_lut_size;
2996 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2998 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3000 .pthresh = I40E_DEFAULT_RX_PTHRESH,
3001 .hthresh = I40E_DEFAULT_RX_HTHRESH,
3002 .wthresh = I40E_DEFAULT_RX_WTHRESH,
3004 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3008 dev_info->default_txconf = (struct rte_eth_txconf) {
3010 .pthresh = I40E_DEFAULT_TX_PTHRESH,
3011 .hthresh = I40E_DEFAULT_TX_HTHRESH,
3012 .wthresh = I40E_DEFAULT_TX_WTHRESH,
3014 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3015 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3016 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3017 ETH_TXQ_FLAGS_NOOFFLOADS,
3020 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3021 .nb_max = I40E_MAX_RING_DESC,
3022 .nb_min = I40E_MIN_RING_DESC,
3023 .nb_align = I40E_ALIGN_RING_DESC,
3026 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3027 .nb_max = I40E_MAX_RING_DESC,
3028 .nb_min = I40E_MIN_RING_DESC,
3029 .nb_align = I40E_ALIGN_RING_DESC,
3030 .nb_seg_max = I40E_TX_MAX_SEG,
3031 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3034 if (pf->flags & I40E_FLAG_VMDQ) {
3035 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3036 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3037 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3038 pf->max_nb_vmdq_vsi;
3039 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3040 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3041 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3044 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
3046 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3047 else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
3049 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3052 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3056 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3058 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3059 struct i40e_vsi *vsi = pf->main_vsi;
3060 PMD_INIT_FUNC_TRACE();
3063 return i40e_vsi_add_vlan(vsi, vlan_id);
3065 return i40e_vsi_delete_vlan(vsi, vlan_id);
3069 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3070 enum rte_vlan_type vlan_type,
3071 uint16_t tpid, int qinq)
3073 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3076 uint16_t reg_id = 3;
3080 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3084 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3086 if (ret != I40E_SUCCESS) {
3088 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3093 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3096 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3097 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3098 if (reg_r == reg_w) {
3099 PMD_DRV_LOG(DEBUG, "No need to write");
3103 ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3105 if (ret != I40E_SUCCESS) {
3107 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3112 "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3119 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3120 enum rte_vlan_type vlan_type,
3123 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3124 int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
3127 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3128 vlan_type != ETH_VLAN_TYPE_OUTER) ||
3129 (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3131 "Unsupported vlan type.");
3134 /* 802.1ad frames ability is added in NVM API 1.7*/
3135 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3137 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3138 hw->first_tag = rte_cpu_to_le_16(tpid);
3139 else if (vlan_type == ETH_VLAN_TYPE_INNER)
3140 hw->second_tag = rte_cpu_to_le_16(tpid);
3142 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3143 hw->second_tag = rte_cpu_to_le_16(tpid);
3145 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3146 if (ret != I40E_SUCCESS) {
3148 "Set switch config failed aq_err: %d",
3149 hw->aq.asq_last_status);
3153 /* If NVM API < 1.7, keep the register setting */
3154 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3161 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3163 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3164 struct i40e_vsi *vsi = pf->main_vsi;
3166 if (mask & ETH_VLAN_FILTER_MASK) {
3167 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3168 i40e_vsi_config_vlan_filter(vsi, TRUE);
3170 i40e_vsi_config_vlan_filter(vsi, FALSE);
3173 if (mask & ETH_VLAN_STRIP_MASK) {
3174 /* Enable or disable VLAN stripping */
3175 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3176 i40e_vsi_config_vlan_stripping(vsi, TRUE);
3178 i40e_vsi_config_vlan_stripping(vsi, FALSE);
3181 if (mask & ETH_VLAN_EXTEND_MASK) {
3182 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3183 i40e_vsi_config_double_vlan(vsi, TRUE);
3184 /* Set global registers with default ethertype. */
3185 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3187 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3191 i40e_vsi_config_double_vlan(vsi, FALSE);
3196 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3197 __rte_unused uint16_t queue,
3198 __rte_unused int on)
3200 PMD_INIT_FUNC_TRACE();
3204 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3206 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3207 struct i40e_vsi *vsi = pf->main_vsi;
3208 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3209 struct i40e_vsi_vlan_pvid_info info;
3211 memset(&info, 0, sizeof(info));
3214 info.config.pvid = pvid;
3216 info.config.reject.tagged =
3217 data->dev_conf.txmode.hw_vlan_reject_tagged;
3218 info.config.reject.untagged =
3219 data->dev_conf.txmode.hw_vlan_reject_untagged;
3222 return i40e_vsi_vlan_pvid_set(vsi, &info);
3226 i40e_dev_led_on(struct rte_eth_dev *dev)
3228 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3229 uint32_t mode = i40e_led_get(hw);
3232 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3238 i40e_dev_led_off(struct rte_eth_dev *dev)
3240 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3241 uint32_t mode = i40e_led_get(hw);
3244 i40e_led_set(hw, 0, false);
3250 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3252 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3253 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3255 fc_conf->pause_time = pf->fc_conf.pause_time;
3257 /* read out from register, in case they are modified by other port */
3258 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3259 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3260 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3261 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3263 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3264 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3266 /* Return current mode according to actual setting*/
3267 switch (hw->fc.current_mode) {
3269 fc_conf->mode = RTE_FC_FULL;
3271 case I40E_FC_TX_PAUSE:
3272 fc_conf->mode = RTE_FC_TX_PAUSE;
3274 case I40E_FC_RX_PAUSE:
3275 fc_conf->mode = RTE_FC_RX_PAUSE;
3279 fc_conf->mode = RTE_FC_NONE;
3286 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3288 uint32_t mflcn_reg, fctrl_reg, reg;
3289 uint32_t max_high_water;
3290 uint8_t i, aq_failure;
3294 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3295 [RTE_FC_NONE] = I40E_FC_NONE,
3296 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3297 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3298 [RTE_FC_FULL] = I40E_FC_FULL
3301 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3303 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3304 if ((fc_conf->high_water > max_high_water) ||
3305 (fc_conf->high_water < fc_conf->low_water)) {
3307 "Invalid high/low water setup value in KB, High_water must be <= %d.",
3312 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3313 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3314 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3316 pf->fc_conf.pause_time = fc_conf->pause_time;
3317 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3318 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3320 PMD_INIT_FUNC_TRACE();
3322 /* All the link flow control related enable/disable register
3323 * configuration is handle by the F/W
3325 err = i40e_set_fc(hw, &aq_failure, true);
3329 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3330 /* Configure flow control refresh threshold,
3331 * the value for stat_tx_pause_refresh_timer[8]
3332 * is used for global pause operation.
3336 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3337 pf->fc_conf.pause_time);
3339 /* configure the timer value included in transmitted pause
3341 * the value for stat_tx_pause_quanta[8] is used for global
3344 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3345 pf->fc_conf.pause_time);
3347 fctrl_reg = I40E_READ_REG(hw,
3348 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3350 if (fc_conf->mac_ctrl_frame_fwd != 0)
3351 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3353 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3355 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3358 /* Configure pause time (2 TCs per register) */
3359 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3360 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3361 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3363 /* Configure flow control refresh threshold value */
3364 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3365 pf->fc_conf.pause_time / 2);
3367 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3369 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3370 *depending on configuration
3372 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3373 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3374 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3376 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3377 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3380 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3383 /* config the water marker both based on the packets and bytes */
3384 I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3385 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3386 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3387 I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3388 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3389 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3390 I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3391 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3393 I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3394 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3397 I40E_WRITE_FLUSH(hw);
3403 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3404 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3406 PMD_INIT_FUNC_TRACE();
3411 /* Add a MAC address, and update filters */
3413 i40e_macaddr_add(struct rte_eth_dev *dev,
3414 struct ether_addr *mac_addr,
3415 __rte_unused uint32_t index,
3418 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3419 struct i40e_mac_filter_info mac_filter;
3420 struct i40e_vsi *vsi;
3423 /* If VMDQ not enabled or configured, return */
3424 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3425 !pf->nb_cfg_vmdq_vsi)) {
3426 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3427 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3432 if (pool > pf->nb_cfg_vmdq_vsi) {
3433 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3434 pool, pf->nb_cfg_vmdq_vsi);
3438 (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3439 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3440 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3442 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3447 vsi = pf->vmdq[pool - 1].vsi;
3449 ret = i40e_vsi_add_mac(vsi, &mac_filter);
3450 if (ret != I40E_SUCCESS) {
3451 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3457 /* Remove a MAC address, and update filters */
3459 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3461 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3462 struct i40e_vsi *vsi;
3463 struct rte_eth_dev_data *data = dev->data;
3464 struct ether_addr *macaddr;
3469 macaddr = &(data->mac_addrs[index]);
3471 pool_sel = dev->data->mac_pool_sel[index];
3473 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3474 if (pool_sel & (1ULL << i)) {
3478 /* No VMDQ pool enabled or configured */
3479 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3480 (i > pf->nb_cfg_vmdq_vsi)) {
3482 "No VMDQ pool enabled/configured");
3485 vsi = pf->vmdq[i - 1].vsi;
3487 ret = i40e_vsi_delete_mac(vsi, macaddr);
3490 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3497 /* Set perfect match or hash match of MAC and VLAN for a VF */
3499 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3500 struct rte_eth_mac_filter *filter,
3504 struct i40e_mac_filter_info mac_filter;
3505 struct ether_addr old_mac;
3506 struct ether_addr *new_mac;
3507 struct i40e_pf_vf *vf = NULL;
3512 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3515 hw = I40E_PF_TO_HW(pf);
3517 if (filter == NULL) {
3518 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3522 new_mac = &filter->mac_addr;
3524 if (is_zero_ether_addr(new_mac)) {
3525 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3529 vf_id = filter->dst_id;
3531 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3532 PMD_DRV_LOG(ERR, "Invalid argument.");
3535 vf = &pf->vfs[vf_id];
3537 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3538 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3543 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3544 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3546 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3549 mac_filter.filter_type = filter->filter_type;
3550 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3551 if (ret != I40E_SUCCESS) {
3552 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3555 ether_addr_copy(new_mac, &pf->dev_addr);
3557 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3559 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3560 if (ret != I40E_SUCCESS) {
3561 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3565 /* Clear device address as it has been removed */
3566 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3567 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3573 /* MAC filter handle */
3575 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3578 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3579 struct rte_eth_mac_filter *filter;
3580 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3581 int ret = I40E_NOT_SUPPORTED;
3583 filter = (struct rte_eth_mac_filter *)(arg);
3585 switch (filter_op) {
3586 case RTE_ETH_FILTER_NOP:
3589 case RTE_ETH_FILTER_ADD:
3590 i40e_pf_disable_irq0(hw);
3592 ret = i40e_vf_mac_filter_set(pf, filter, 1);
3593 i40e_pf_enable_irq0(hw);
3595 case RTE_ETH_FILTER_DELETE:
3596 i40e_pf_disable_irq0(hw);
3598 ret = i40e_vf_mac_filter_set(pf, filter, 0);
3599 i40e_pf_enable_irq0(hw);
3602 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3603 ret = I40E_ERR_PARAM;
3611 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3613 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3614 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3620 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3621 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3624 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3628 uint32_t *lut_dw = (uint32_t *)lut;
3629 uint16_t i, lut_size_dw = lut_size / 4;
3631 for (i = 0; i < lut_size_dw; i++)
3632 lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3639 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3648 pf = I40E_VSI_TO_PF(vsi);
3649 hw = I40E_VSI_TO_HW(vsi);
3651 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3652 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3655 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3659 uint32_t *lut_dw = (uint32_t *)lut;
3660 uint16_t i, lut_size_dw = lut_size / 4;
3662 for (i = 0; i < lut_size_dw; i++)
3663 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3664 I40E_WRITE_FLUSH(hw);
3671 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3672 struct rte_eth_rss_reta_entry64 *reta_conf,
3675 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3676 uint16_t i, lut_size = pf->hash_lut_size;
3677 uint16_t idx, shift;
3681 if (reta_size != lut_size ||
3682 reta_size > ETH_RSS_RETA_SIZE_512) {
3684 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3685 reta_size, lut_size);
3689 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3691 PMD_DRV_LOG(ERR, "No memory can be allocated");
3694 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3697 for (i = 0; i < reta_size; i++) {
3698 idx = i / RTE_RETA_GROUP_SIZE;
3699 shift = i % RTE_RETA_GROUP_SIZE;
3700 if (reta_conf[idx].mask & (1ULL << shift))
3701 lut[i] = reta_conf[idx].reta[shift];
3703 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3712 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3713 struct rte_eth_rss_reta_entry64 *reta_conf,
3716 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3717 uint16_t i, lut_size = pf->hash_lut_size;
3718 uint16_t idx, shift;
3722 if (reta_size != lut_size ||
3723 reta_size > ETH_RSS_RETA_SIZE_512) {
3725 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3726 reta_size, lut_size);
3730 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3732 PMD_DRV_LOG(ERR, "No memory can be allocated");
3736 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3739 for (i = 0; i < reta_size; i++) {
3740 idx = i / RTE_RETA_GROUP_SIZE;
3741 shift = i % RTE_RETA_GROUP_SIZE;
3742 if (reta_conf[idx].mask & (1ULL << shift))
3743 reta_conf[idx].reta[shift] = lut[i];
3753 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3754 * @hw: pointer to the HW structure
3755 * @mem: pointer to mem struct to fill out
3756 * @size: size of memory requested
3757 * @alignment: what to align the allocation to
3759 enum i40e_status_code
3760 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3761 struct i40e_dma_mem *mem,
3765 const struct rte_memzone *mz = NULL;
3766 char z_name[RTE_MEMZONE_NAMESIZE];
3769 return I40E_ERR_PARAM;
3771 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3772 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3773 alignment, RTE_PGSIZE_2M);
3775 return I40E_ERR_NO_MEMORY;
3779 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3780 mem->zone = (const void *)mz;
3782 "memzone %s allocated with physical address: %"PRIu64,
3785 return I40E_SUCCESS;
3789 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3790 * @hw: pointer to the HW structure
3791 * @mem: ptr to mem struct to free
3793 enum i40e_status_code
3794 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3795 struct i40e_dma_mem *mem)
3798 return I40E_ERR_PARAM;
3801 "memzone %s to be freed with physical address: %"PRIu64,
3802 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3803 rte_memzone_free((const struct rte_memzone *)mem->zone);
3808 return I40E_SUCCESS;
3812 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3813 * @hw: pointer to the HW structure
3814 * @mem: pointer to mem struct to fill out
3815 * @size: size of memory requested
3817 enum i40e_status_code
3818 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3819 struct i40e_virt_mem *mem,
3823 return I40E_ERR_PARAM;
3826 mem->va = rte_zmalloc("i40e", size, 0);
3829 return I40E_SUCCESS;
3831 return I40E_ERR_NO_MEMORY;
3835 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3836 * @hw: pointer to the HW structure
3837 * @mem: pointer to mem struct to free
3839 enum i40e_status_code
3840 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3841 struct i40e_virt_mem *mem)
3844 return I40E_ERR_PARAM;
3849 return I40E_SUCCESS;
3853 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3855 rte_spinlock_init(&sp->spinlock);
3859 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3861 rte_spinlock_lock(&sp->spinlock);
3865 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3867 rte_spinlock_unlock(&sp->spinlock);
3871 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3877 * Get the hardware capabilities, which will be parsed
3878 * and saved into struct i40e_hw.
3881 i40e_get_cap(struct i40e_hw *hw)
3883 struct i40e_aqc_list_capabilities_element_resp *buf;
3884 uint16_t len, size = 0;
3887 /* Calculate a huge enough buff for saving response data temporarily */
3888 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3889 I40E_MAX_CAP_ELE_NUM;
3890 buf = rte_zmalloc("i40e", len, 0);
3892 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3893 return I40E_ERR_NO_MEMORY;
3896 /* Get, parse the capabilities and save it to hw */
3897 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3898 i40e_aqc_opc_list_func_capabilities, NULL);
3899 if (ret != I40E_SUCCESS)
3900 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3902 /* Free the temporary buffer after being used */
3909 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3911 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3912 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3913 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3914 uint16_t qp_count = 0, vsi_count = 0;
3916 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3917 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3920 /* Add the parameter init for LFC */
3921 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3922 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3923 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3925 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3926 pf->max_num_vsi = hw->func_caps.num_vsis;
3927 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3928 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3929 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3931 /* FDir queue/VSI allocation */
3932 pf->fdir_qp_offset = 0;
3933 if (hw->func_caps.fd) {
3934 pf->flags |= I40E_FLAG_FDIR;
3935 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3937 pf->fdir_nb_qps = 0;
3939 qp_count += pf->fdir_nb_qps;
3942 /* LAN queue/VSI allocation */
3943 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3944 if (!hw->func_caps.rss) {
3947 pf->flags |= I40E_FLAG_RSS;
3948 if (hw->mac.type == I40E_MAC_X722)
3949 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3950 pf->lan_nb_qps = pf->lan_nb_qp_max;
3952 qp_count += pf->lan_nb_qps;
3955 /* VF queue/VSI allocation */
3956 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3957 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3958 pf->flags |= I40E_FLAG_SRIOV;
3959 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3960 pf->vf_num = pci_dev->max_vfs;
3962 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
3963 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
3968 qp_count += pf->vf_nb_qps * pf->vf_num;
3969 vsi_count += pf->vf_num;
3971 /* VMDq queue/VSI allocation */
3972 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3973 pf->vmdq_nb_qps = 0;
3974 pf->max_nb_vmdq_vsi = 0;
3975 if (hw->func_caps.vmdq) {
3976 if (qp_count < hw->func_caps.num_tx_qp &&
3977 vsi_count < hw->func_caps.num_vsis) {
3978 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3979 qp_count) / pf->vmdq_nb_qp_max;
3981 /* Limit the maximum number of VMDq vsi to the maximum
3982 * ethdev can support
3984 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3985 hw->func_caps.num_vsis - vsi_count);
3986 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3988 if (pf->max_nb_vmdq_vsi) {
3989 pf->flags |= I40E_FLAG_VMDQ;
3990 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3992 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
3993 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
3994 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
3997 "No enough queues left for VMDq");
4000 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4003 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4004 vsi_count += pf->max_nb_vmdq_vsi;
4006 if (hw->func_caps.dcb)
4007 pf->flags |= I40E_FLAG_DCB;
4009 if (qp_count > hw->func_caps.num_tx_qp) {
4011 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4012 qp_count, hw->func_caps.num_tx_qp);
4015 if (vsi_count > hw->func_caps.num_vsis) {
4017 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4018 vsi_count, hw->func_caps.num_vsis);
4026 i40e_pf_get_switch_config(struct i40e_pf *pf)
4028 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4029 struct i40e_aqc_get_switch_config_resp *switch_config;
4030 struct i40e_aqc_switch_config_element_resp *element;
4031 uint16_t start_seid = 0, num_reported;
4034 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4035 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4036 if (!switch_config) {
4037 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4041 /* Get the switch configurations */
4042 ret = i40e_aq_get_switch_config(hw, switch_config,
4043 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4044 if (ret != I40E_SUCCESS) {
4045 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4048 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4049 if (num_reported != 1) { /* The number should be 1 */
4050 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4054 /* Parse the switch configuration elements */
4055 element = &(switch_config->element[0]);
4056 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4057 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4058 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4060 PMD_DRV_LOG(INFO, "Unknown element type");
4063 rte_free(switch_config);
4069 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4072 struct pool_entry *entry;
4074 if (pool == NULL || num == 0)
4077 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4078 if (entry == NULL) {
4079 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4083 /* queue heap initialize */
4084 pool->num_free = num;
4085 pool->num_alloc = 0;
4087 LIST_INIT(&pool->alloc_list);
4088 LIST_INIT(&pool->free_list);
4090 /* Initialize element */
4094 LIST_INSERT_HEAD(&pool->free_list, entry, next);
4099 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4101 struct pool_entry *entry, *next_entry;
4106 for (entry = LIST_FIRST(&pool->alloc_list);
4107 entry && (next_entry = LIST_NEXT(entry, next), 1);
4108 entry = next_entry) {
4109 LIST_REMOVE(entry, next);
4113 for (entry = LIST_FIRST(&pool->free_list);
4114 entry && (next_entry = LIST_NEXT(entry, next), 1);
4115 entry = next_entry) {
4116 LIST_REMOVE(entry, next);
4121 pool->num_alloc = 0;
4123 LIST_INIT(&pool->alloc_list);
4124 LIST_INIT(&pool->free_list);
4128 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4131 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4132 uint32_t pool_offset;
4136 PMD_DRV_LOG(ERR, "Invalid parameter");
4140 pool_offset = base - pool->base;
4141 /* Lookup in alloc list */
4142 LIST_FOREACH(entry, &pool->alloc_list, next) {
4143 if (entry->base == pool_offset) {
4144 valid_entry = entry;
4145 LIST_REMOVE(entry, next);
4150 /* Not find, return */
4151 if (valid_entry == NULL) {
4152 PMD_DRV_LOG(ERR, "Failed to find entry");
4157 * Found it, move it to free list and try to merge.
4158 * In order to make merge easier, always sort it by qbase.
4159 * Find adjacent prev and last entries.
4162 LIST_FOREACH(entry, &pool->free_list, next) {
4163 if (entry->base > valid_entry->base) {
4171 /* Try to merge with next one*/
4173 /* Merge with next one */
4174 if (valid_entry->base + valid_entry->len == next->base) {
4175 next->base = valid_entry->base;
4176 next->len += valid_entry->len;
4177 rte_free(valid_entry);
4184 /* Merge with previous one */
4185 if (prev->base + prev->len == valid_entry->base) {
4186 prev->len += valid_entry->len;
4187 /* If it merge with next one, remove next node */
4189 LIST_REMOVE(valid_entry, next);
4190 rte_free(valid_entry);
4192 rte_free(valid_entry);
4198 /* Not find any entry to merge, insert */
4201 LIST_INSERT_AFTER(prev, valid_entry, next);
4202 else if (next != NULL)
4203 LIST_INSERT_BEFORE(next, valid_entry, next);
4204 else /* It's empty list, insert to head */
4205 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4208 pool->num_free += valid_entry->len;
4209 pool->num_alloc -= valid_entry->len;
4215 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4218 struct pool_entry *entry, *valid_entry;
4220 if (pool == NULL || num == 0) {
4221 PMD_DRV_LOG(ERR, "Invalid parameter");
4225 if (pool->num_free < num) {
4226 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4227 num, pool->num_free);
4232 /* Lookup in free list and find most fit one */
4233 LIST_FOREACH(entry, &pool->free_list, next) {
4234 if (entry->len >= num) {
4236 if (entry->len == num) {
4237 valid_entry = entry;
4240 if (valid_entry == NULL || valid_entry->len > entry->len)
4241 valid_entry = entry;
4245 /* Not find one to satisfy the request, return */
4246 if (valid_entry == NULL) {
4247 PMD_DRV_LOG(ERR, "No valid entry found");
4251 * The entry have equal queue number as requested,
4252 * remove it from alloc_list.
4254 if (valid_entry->len == num) {
4255 LIST_REMOVE(valid_entry, next);
4258 * The entry have more numbers than requested,
4259 * create a new entry for alloc_list and minus its
4260 * queue base and number in free_list.
4262 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4263 if (entry == NULL) {
4265 "Failed to allocate memory for resource pool");
4268 entry->base = valid_entry->base;
4270 valid_entry->base += num;
4271 valid_entry->len -= num;
4272 valid_entry = entry;
4275 /* Insert it into alloc list, not sorted */
4276 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4278 pool->num_free -= valid_entry->len;
4279 pool->num_alloc += valid_entry->len;
4281 return valid_entry->base + pool->base;
4285 * bitmap_is_subset - Check whether src2 is subset of src1
4288 bitmap_is_subset(uint8_t src1, uint8_t src2)
4290 return !((src1 ^ src2) & src2);
4293 static enum i40e_status_code
4294 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4296 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4298 /* If DCB is not supported, only default TC is supported */
4299 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4300 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4301 return I40E_NOT_SUPPORTED;
4304 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4306 "Enabled TC map 0x%x not applicable to HW support 0x%x",
4307 hw->func_caps.enabled_tcmap, enabled_tcmap);
4308 return I40E_NOT_SUPPORTED;
4310 return I40E_SUCCESS;
4314 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4315 struct i40e_vsi_vlan_pvid_info *info)
4318 struct i40e_vsi_context ctxt;
4319 uint8_t vlan_flags = 0;
4322 if (vsi == NULL || info == NULL) {
4323 PMD_DRV_LOG(ERR, "invalid parameters");
4324 return I40E_ERR_PARAM;
4328 vsi->info.pvid = info->config.pvid;
4330 * If insert pvid is enabled, only tagged pkts are
4331 * allowed to be sent out.
4333 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4334 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4337 if (info->config.reject.tagged == 0)
4338 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4340 if (info->config.reject.untagged == 0)
4341 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4343 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4344 I40E_AQ_VSI_PVLAN_MODE_MASK);
4345 vsi->info.port_vlan_flags |= vlan_flags;
4346 vsi->info.valid_sections =
4347 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4348 memset(&ctxt, 0, sizeof(ctxt));
4349 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4350 ctxt.seid = vsi->seid;
4352 hw = I40E_VSI_TO_HW(vsi);
4353 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4354 if (ret != I40E_SUCCESS)
4355 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4361 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4363 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4365 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4367 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4368 if (ret != I40E_SUCCESS)
4372 PMD_DRV_LOG(ERR, "seid not valid");
4376 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4377 tc_bw_data.tc_valid_bits = enabled_tcmap;
4378 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4379 tc_bw_data.tc_bw_credits[i] =
4380 (enabled_tcmap & (1 << i)) ? 1 : 0;
4382 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4383 if (ret != I40E_SUCCESS) {
4384 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4388 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4389 sizeof(vsi->info.qs_handle));
4390 return I40E_SUCCESS;
4393 static enum i40e_status_code
4394 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4395 struct i40e_aqc_vsi_properties_data *info,
4396 uint8_t enabled_tcmap)
4398 enum i40e_status_code ret;
4399 int i, total_tc = 0;
4400 uint16_t qpnum_per_tc, bsf, qp_idx;
4402 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4403 if (ret != I40E_SUCCESS)
4406 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4407 if (enabled_tcmap & (1 << i))
4411 vsi->enabled_tc = enabled_tcmap;
4413 /* Number of queues per enabled TC */
4414 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4415 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4416 bsf = rte_bsf32(qpnum_per_tc);
4418 /* Adjust the queue number to actual queues that can be applied */
4419 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4420 vsi->nb_qps = qpnum_per_tc * total_tc;
4423 * Configure TC and queue mapping parameters, for enabled TC,
4424 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4425 * default queue will serve it.
4428 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4429 if (vsi->enabled_tc & (1 << i)) {
4430 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4431 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4432 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4433 qp_idx += qpnum_per_tc;
4435 info->tc_mapping[i] = 0;
4438 /* Associate queue number with VSI */
4439 if (vsi->type == I40E_VSI_SRIOV) {
4440 info->mapping_flags |=
4441 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4442 for (i = 0; i < vsi->nb_qps; i++)
4443 info->queue_mapping[i] =
4444 rte_cpu_to_le_16(vsi->base_queue + i);
4446 info->mapping_flags |=
4447 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4448 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4450 info->valid_sections |=
4451 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4453 return I40E_SUCCESS;
4457 i40e_veb_release(struct i40e_veb *veb)
4459 struct i40e_vsi *vsi;
4465 if (!TAILQ_EMPTY(&veb->head)) {
4466 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4469 /* associate_vsi field is NULL for floating VEB */
4470 if (veb->associate_vsi != NULL) {
4471 vsi = veb->associate_vsi;
4472 hw = I40E_VSI_TO_HW(vsi);
4474 vsi->uplink_seid = veb->uplink_seid;
4477 veb->associate_pf->main_vsi->floating_veb = NULL;
4478 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4481 i40e_aq_delete_element(hw, veb->seid, NULL);
4483 return I40E_SUCCESS;
4487 static struct i40e_veb *
4488 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4490 struct i40e_veb *veb;
4496 "veb setup failed, associated PF shouldn't null");
4499 hw = I40E_PF_TO_HW(pf);
4501 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4503 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4507 veb->associate_vsi = vsi;
4508 veb->associate_pf = pf;
4509 TAILQ_INIT(&veb->head);
4510 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4512 /* create floating veb if vsi is NULL */
4514 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4515 I40E_DEFAULT_TCMAP, false,
4516 &veb->seid, false, NULL);
4518 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4519 true, &veb->seid, false, NULL);
4522 if (ret != I40E_SUCCESS) {
4523 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4524 hw->aq.asq_last_status);
4527 veb->enabled_tc = I40E_DEFAULT_TCMAP;
4529 /* get statistics index */
4530 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4531 &veb->stats_idx, NULL, NULL, NULL);
4532 if (ret != I40E_SUCCESS) {
4533 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4534 hw->aq.asq_last_status);
4537 /* Get VEB bandwidth, to be implemented */
4538 /* Now associated vsi binding to the VEB, set uplink to this VEB */
4540 vsi->uplink_seid = veb->seid;
4549 i40e_vsi_release(struct i40e_vsi *vsi)
4553 struct i40e_vsi_list *vsi_list;
4556 struct i40e_mac_filter *f;
4557 uint16_t user_param;
4560 return I40E_SUCCESS;
4565 user_param = vsi->user_param;
4567 pf = I40E_VSI_TO_PF(vsi);
4568 hw = I40E_VSI_TO_HW(vsi);
4570 /* VSI has child to attach, release child first */
4572 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4573 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4576 i40e_veb_release(vsi->veb);
4579 if (vsi->floating_veb) {
4580 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4581 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4586 /* Remove all macvlan filters of the VSI */
4587 i40e_vsi_remove_all_macvlan_filter(vsi);
4588 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4591 if (vsi->type != I40E_VSI_MAIN &&
4592 ((vsi->type != I40E_VSI_SRIOV) ||
4593 !pf->floating_veb_list[user_param])) {
4594 /* Remove vsi from parent's sibling list */
4595 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4596 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4597 return I40E_ERR_PARAM;
4599 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4600 &vsi->sib_vsi_list, list);
4602 /* Remove all switch element of the VSI */
4603 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4604 if (ret != I40E_SUCCESS)
4605 PMD_DRV_LOG(ERR, "Failed to delete element");
4608 if ((vsi->type == I40E_VSI_SRIOV) &&
4609 pf->floating_veb_list[user_param]) {
4610 /* Remove vsi from parent's sibling list */
4611 if (vsi->parent_vsi == NULL ||
4612 vsi->parent_vsi->floating_veb == NULL) {
4613 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4614 return I40E_ERR_PARAM;
4616 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4617 &vsi->sib_vsi_list, list);
4619 /* Remove all switch element of the VSI */
4620 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4621 if (ret != I40E_SUCCESS)
4622 PMD_DRV_LOG(ERR, "Failed to delete element");
4625 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4627 if (vsi->type != I40E_VSI_SRIOV)
4628 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4631 return I40E_SUCCESS;
4635 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4637 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4638 struct i40e_aqc_remove_macvlan_element_data def_filter;
4639 struct i40e_mac_filter_info filter;
4642 if (vsi->type != I40E_VSI_MAIN)
4643 return I40E_ERR_CONFIG;
4644 memset(&def_filter, 0, sizeof(def_filter));
4645 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4647 def_filter.vlan_tag = 0;
4648 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4649 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4650 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4651 if (ret != I40E_SUCCESS) {
4652 struct i40e_mac_filter *f;
4653 struct ether_addr *mac;
4656 "Cannot remove the default macvlan filter");
4657 /* It needs to add the permanent mac into mac list */
4658 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4660 PMD_DRV_LOG(ERR, "failed to allocate memory");
4661 return I40E_ERR_NO_MEMORY;
4663 mac = &f->mac_info.mac_addr;
4664 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4666 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4667 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4672 (void)rte_memcpy(&filter.mac_addr,
4673 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4674 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4675 return i40e_vsi_add_mac(vsi, &filter);
4679 * i40e_vsi_get_bw_config - Query VSI BW Information
4680 * @vsi: the VSI to be queried
4682 * Returns 0 on success, negative value on failure
4684 static enum i40e_status_code
4685 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4687 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4688 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4689 struct i40e_hw *hw = &vsi->adapter->hw;
4694 memset(&bw_config, 0, sizeof(bw_config));
4695 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4696 if (ret != I40E_SUCCESS) {
4697 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4698 hw->aq.asq_last_status);
4702 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4703 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4704 &ets_sla_config, NULL);
4705 if (ret != I40E_SUCCESS) {
4707 "VSI failed to get TC bandwdith configuration %u",
4708 hw->aq.asq_last_status);
4712 /* store and print out BW info */
4713 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4714 vsi->bw_info.bw_max = bw_config.max_bw;
4715 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4716 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4717 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4718 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4720 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4721 vsi->bw_info.bw_ets_share_credits[i] =
4722 ets_sla_config.share_credits[i];
4723 vsi->bw_info.bw_ets_credits[i] =
4724 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4725 /* 4 bits per TC, 4th bit is reserved */
4726 vsi->bw_info.bw_ets_max[i] =
4727 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4728 RTE_LEN2MASK(3, uint8_t));
4729 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4730 vsi->bw_info.bw_ets_share_credits[i]);
4731 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4732 vsi->bw_info.bw_ets_credits[i]);
4733 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4734 vsi->bw_info.bw_ets_max[i]);
4737 return I40E_SUCCESS;
4740 /* i40e_enable_pf_lb
4741 * @pf: pointer to the pf structure
4743 * allow loopback on pf
4746 i40e_enable_pf_lb(struct i40e_pf *pf)
4748 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4749 struct i40e_vsi_context ctxt;
4752 /* Use the FW API if FW >= v5.0 */
4753 if (hw->aq.fw_maj_ver < 5) {
4754 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4758 memset(&ctxt, 0, sizeof(ctxt));
4759 ctxt.seid = pf->main_vsi_seid;
4760 ctxt.pf_num = hw->pf_id;
4761 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4763 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4764 ret, hw->aq.asq_last_status);
4767 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4768 ctxt.info.valid_sections =
4769 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4770 ctxt.info.switch_id |=
4771 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4773 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4775 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4776 hw->aq.asq_last_status);
4781 i40e_vsi_setup(struct i40e_pf *pf,
4782 enum i40e_vsi_type type,
4783 struct i40e_vsi *uplink_vsi,
4784 uint16_t user_param)
4786 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4787 struct i40e_vsi *vsi;
4788 struct i40e_mac_filter_info filter;
4790 struct i40e_vsi_context ctxt;
4791 struct ether_addr broadcast =
4792 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4794 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4795 uplink_vsi == NULL) {
4797 "VSI setup failed, VSI link shouldn't be NULL");
4801 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4803 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4808 * 1.type is not MAIN and uplink vsi is not NULL
4809 * If uplink vsi didn't setup VEB, create one first under veb field
4810 * 2.type is SRIOV and the uplink is NULL
4811 * If floating VEB is NULL, create one veb under floating veb field
4814 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4815 uplink_vsi->veb == NULL) {
4816 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4818 if (uplink_vsi->veb == NULL) {
4819 PMD_DRV_LOG(ERR, "VEB setup failed");
4822 /* set ALLOWLOOPBACk on pf, when veb is created */
4823 i40e_enable_pf_lb(pf);
4826 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4827 pf->main_vsi->floating_veb == NULL) {
4828 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4830 if (pf->main_vsi->floating_veb == NULL) {
4831 PMD_DRV_LOG(ERR, "VEB setup failed");
4836 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4838 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4841 TAILQ_INIT(&vsi->mac_list);
4843 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4844 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4845 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4846 vsi->user_param = user_param;
4847 vsi->vlan_anti_spoof_on = 0;
4848 vsi->vlan_filter_on = 0;
4849 /* Allocate queues */
4850 switch (vsi->type) {
4851 case I40E_VSI_MAIN :
4852 vsi->nb_qps = pf->lan_nb_qps;
4854 case I40E_VSI_SRIOV :
4855 vsi->nb_qps = pf->vf_nb_qps;
4857 case I40E_VSI_VMDQ2:
4858 vsi->nb_qps = pf->vmdq_nb_qps;
4861 vsi->nb_qps = pf->fdir_nb_qps;
4867 * The filter status descriptor is reported in rx queue 0,
4868 * while the tx queue for fdir filter programming has no
4869 * such constraints, can be non-zero queues.
4870 * To simplify it, choose FDIR vsi use queue 0 pair.
4871 * To make sure it will use queue 0 pair, queue allocation
4872 * need be done before this function is called
4874 if (type != I40E_VSI_FDIR) {
4875 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4877 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4881 vsi->base_queue = ret;
4883 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4885 /* VF has MSIX interrupt in VF range, don't allocate here */
4886 if (type == I40E_VSI_MAIN) {
4887 ret = i40e_res_pool_alloc(&pf->msix_pool,
4888 RTE_MIN(vsi->nb_qps,
4889 RTE_MAX_RXTX_INTR_VEC_ID));
4891 PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4893 goto fail_queue_alloc;
4895 vsi->msix_intr = ret;
4896 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4897 } else if (type != I40E_VSI_SRIOV) {
4898 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4900 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4901 goto fail_queue_alloc;
4903 vsi->msix_intr = ret;
4911 if (type == I40E_VSI_MAIN) {
4912 /* For main VSI, no need to add since it's default one */
4913 vsi->uplink_seid = pf->mac_seid;
4914 vsi->seid = pf->main_vsi_seid;
4915 /* Bind queues with specific MSIX interrupt */
4917 * Needs 2 interrupt at least, one for misc cause which will
4918 * enabled from OS side, Another for queues binding the
4919 * interrupt from device side only.
4922 /* Get default VSI parameters from hardware */
4923 memset(&ctxt, 0, sizeof(ctxt));
4924 ctxt.seid = vsi->seid;
4925 ctxt.pf_num = hw->pf_id;
4926 ctxt.uplink_seid = vsi->uplink_seid;
4928 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4929 if (ret != I40E_SUCCESS) {
4930 PMD_DRV_LOG(ERR, "Failed to get VSI params");
4931 goto fail_msix_alloc;
4933 (void)rte_memcpy(&vsi->info, &ctxt.info,
4934 sizeof(struct i40e_aqc_vsi_properties_data));
4935 vsi->vsi_id = ctxt.vsi_number;
4936 vsi->info.valid_sections = 0;
4938 /* Configure tc, enabled TC0 only */
4939 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4941 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4942 goto fail_msix_alloc;
4945 /* TC, queue mapping */
4946 memset(&ctxt, 0, sizeof(ctxt));
4947 vsi->info.valid_sections |=
4948 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4949 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4950 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4951 (void)rte_memcpy(&ctxt.info, &vsi->info,
4952 sizeof(struct i40e_aqc_vsi_properties_data));
4953 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4954 I40E_DEFAULT_TCMAP);
4955 if (ret != I40E_SUCCESS) {
4957 "Failed to configure TC queue mapping");
4958 goto fail_msix_alloc;
4960 ctxt.seid = vsi->seid;
4961 ctxt.pf_num = hw->pf_id;
4962 ctxt.uplink_seid = vsi->uplink_seid;
4965 /* Update VSI parameters */
4966 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4967 if (ret != I40E_SUCCESS) {
4968 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4969 goto fail_msix_alloc;
4972 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4973 sizeof(vsi->info.tc_mapping));
4974 (void)rte_memcpy(&vsi->info.queue_mapping,
4975 &ctxt.info.queue_mapping,
4976 sizeof(vsi->info.queue_mapping));
4977 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4978 vsi->info.valid_sections = 0;
4980 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4984 * Updating default filter settings are necessary to prevent
4985 * reception of tagged packets.
4986 * Some old firmware configurations load a default macvlan
4987 * filter which accepts both tagged and untagged packets.
4988 * The updating is to use a normal filter instead if needed.
4989 * For NVM 4.2.2 or after, the updating is not needed anymore.
4990 * The firmware with correct configurations load the default
4991 * macvlan filter which is expected and cannot be removed.
4993 i40e_update_default_filter_setting(vsi);
4994 i40e_config_qinq(hw, vsi);
4995 } else if (type == I40E_VSI_SRIOV) {
4996 memset(&ctxt, 0, sizeof(ctxt));
4998 * For other VSI, the uplink_seid equals to uplink VSI's
4999 * uplink_seid since they share same VEB
5001 if (uplink_vsi == NULL)
5002 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5004 vsi->uplink_seid = uplink_vsi->uplink_seid;
5005 ctxt.pf_num = hw->pf_id;
5006 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5007 ctxt.uplink_seid = vsi->uplink_seid;
5008 ctxt.connection_type = 0x1;
5009 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5011 /* Use the VEB configuration if FW >= v5.0 */
5012 if (hw->aq.fw_maj_ver >= 5) {
5013 /* Configure switch ID */
5014 ctxt.info.valid_sections |=
5015 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5016 ctxt.info.switch_id =
5017 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5020 /* Configure port/vlan */
5021 ctxt.info.valid_sections |=
5022 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5023 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5024 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5025 hw->func_caps.enabled_tcmap);
5026 if (ret != I40E_SUCCESS) {
5028 "Failed to configure TC queue mapping");
5029 goto fail_msix_alloc;
5032 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5033 ctxt.info.valid_sections |=
5034 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5036 * Since VSI is not created yet, only configure parameter,
5037 * will add vsi below.
5040 i40e_config_qinq(hw, vsi);
5041 } else if (type == I40E_VSI_VMDQ2) {
5042 memset(&ctxt, 0, sizeof(ctxt));
5044 * For other VSI, the uplink_seid equals to uplink VSI's
5045 * uplink_seid since they share same VEB
5047 vsi->uplink_seid = uplink_vsi->uplink_seid;
5048 ctxt.pf_num = hw->pf_id;
5050 ctxt.uplink_seid = vsi->uplink_seid;
5051 ctxt.connection_type = 0x1;
5052 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5054 ctxt.info.valid_sections |=
5055 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5056 /* user_param carries flag to enable loop back */
5058 ctxt.info.switch_id =
5059 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5060 ctxt.info.switch_id |=
5061 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5064 /* Configure port/vlan */
5065 ctxt.info.valid_sections |=
5066 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5067 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5068 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5069 I40E_DEFAULT_TCMAP);
5070 if (ret != I40E_SUCCESS) {
5072 "Failed to configure TC queue mapping");
5073 goto fail_msix_alloc;
5075 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5076 ctxt.info.valid_sections |=
5077 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5078 } else if (type == I40E_VSI_FDIR) {
5079 memset(&ctxt, 0, sizeof(ctxt));
5080 vsi->uplink_seid = uplink_vsi->uplink_seid;
5081 ctxt.pf_num = hw->pf_id;
5083 ctxt.uplink_seid = vsi->uplink_seid;
5084 ctxt.connection_type = 0x1; /* regular data port */
5085 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5086 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5087 I40E_DEFAULT_TCMAP);
5088 if (ret != I40E_SUCCESS) {
5090 "Failed to configure TC queue mapping.");
5091 goto fail_msix_alloc;
5093 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5094 ctxt.info.valid_sections |=
5095 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5097 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5098 goto fail_msix_alloc;
5101 if (vsi->type != I40E_VSI_MAIN) {
5102 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5103 if (ret != I40E_SUCCESS) {
5104 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5105 hw->aq.asq_last_status);
5106 goto fail_msix_alloc;
5108 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5109 vsi->info.valid_sections = 0;
5110 vsi->seid = ctxt.seid;
5111 vsi->vsi_id = ctxt.vsi_number;
5112 vsi->sib_vsi_list.vsi = vsi;
5113 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5114 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5115 &vsi->sib_vsi_list, list);
5117 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5118 &vsi->sib_vsi_list, list);
5122 /* MAC/VLAN configuration */
5123 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5124 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5126 ret = i40e_vsi_add_mac(vsi, &filter);
5127 if (ret != I40E_SUCCESS) {
5128 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5129 goto fail_msix_alloc;
5132 /* Get VSI BW information */
5133 i40e_vsi_get_bw_config(vsi);
5136 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5138 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5144 /* Configure vlan filter on or off */
5146 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5149 struct i40e_mac_filter *f;
5151 struct i40e_mac_filter_info *mac_filter;
5152 enum rte_mac_filter_type desired_filter;
5153 int ret = I40E_SUCCESS;
5156 /* Filter to match MAC and VLAN */
5157 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5159 /* Filter to match only MAC */
5160 desired_filter = RTE_MAC_PERFECT_MATCH;
5165 mac_filter = rte_zmalloc("mac_filter_info_data",
5166 num * sizeof(*mac_filter), 0);
5167 if (mac_filter == NULL) {
5168 PMD_DRV_LOG(ERR, "failed to allocate memory");
5169 return I40E_ERR_NO_MEMORY;
5174 /* Remove all existing mac */
5175 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5176 mac_filter[i] = f->mac_info;
5177 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5179 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5180 on ? "enable" : "disable");
5186 /* Override with new filter */
5187 for (i = 0; i < num; i++) {
5188 mac_filter[i].filter_type = desired_filter;
5189 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5191 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5192 on ? "enable" : "disable");
5198 rte_free(mac_filter);
5202 /* Configure vlan stripping on or off */
5204 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5206 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5207 struct i40e_vsi_context ctxt;
5209 int ret = I40E_SUCCESS;
5211 /* Check if it has been already on or off */
5212 if (vsi->info.valid_sections &
5213 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5215 if ((vsi->info.port_vlan_flags &
5216 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5217 return 0; /* already on */
5219 if ((vsi->info.port_vlan_flags &
5220 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5221 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5222 return 0; /* already off */
5227 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5229 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5230 vsi->info.valid_sections =
5231 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5232 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5233 vsi->info.port_vlan_flags |= vlan_flags;
5234 ctxt.seid = vsi->seid;
5235 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5236 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5238 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5239 on ? "enable" : "disable");
5245 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5247 struct rte_eth_dev_data *data = dev->data;
5251 /* Apply vlan offload setting */
5252 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5253 i40e_vlan_offload_set(dev, mask);
5255 /* Apply double-vlan setting, not implemented yet */
5257 /* Apply pvid setting */
5258 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5259 data->dev_conf.txmode.hw_vlan_insert_pvid);
5261 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5267 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5269 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5271 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5275 i40e_update_flow_control(struct i40e_hw *hw)
5277 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5278 struct i40e_link_status link_status;
5279 uint32_t rxfc = 0, txfc = 0, reg;
5283 memset(&link_status, 0, sizeof(link_status));
5284 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5285 if (ret != I40E_SUCCESS) {
5286 PMD_DRV_LOG(ERR, "Failed to get link status information");
5287 goto write_reg; /* Disable flow control */
5290 an_info = hw->phy.link_info.an_info;
5291 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5292 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5293 ret = I40E_ERR_NOT_READY;
5294 goto write_reg; /* Disable flow control */
5297 * If link auto negotiation is enabled, flow control needs to
5298 * be configured according to it
5300 switch (an_info & I40E_LINK_PAUSE_RXTX) {
5301 case I40E_LINK_PAUSE_RXTX:
5304 hw->fc.current_mode = I40E_FC_FULL;
5306 case I40E_AQ_LINK_PAUSE_RX:
5308 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5310 case I40E_AQ_LINK_PAUSE_TX:
5312 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5315 hw->fc.current_mode = I40E_FC_NONE;
5320 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5321 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5322 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5323 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5324 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5325 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5332 i40e_pf_setup(struct i40e_pf *pf)
5334 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5335 struct i40e_filter_control_settings settings;
5336 struct i40e_vsi *vsi;
5339 /* Clear all stats counters */
5340 pf->offset_loaded = FALSE;
5341 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5342 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5343 memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5344 memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5346 ret = i40e_pf_get_switch_config(pf);
5347 if (ret != I40E_SUCCESS) {
5348 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5351 if (pf->flags & I40E_FLAG_FDIR) {
5352 /* make queue allocated first, let FDIR use queue pair 0*/
5353 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5354 if (ret != I40E_FDIR_QUEUE_ID) {
5356 "queue allocation fails for FDIR: ret =%d",
5358 pf->flags &= ~I40E_FLAG_FDIR;
5361 /* main VSI setup */
5362 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5364 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5365 return I40E_ERR_NOT_READY;
5369 /* Configure filter control */
5370 memset(&settings, 0, sizeof(settings));
5371 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5372 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5373 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5374 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5376 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5377 hw->func_caps.rss_table_size);
5378 return I40E_ERR_PARAM;
5380 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5381 hw->func_caps.rss_table_size);
5382 pf->hash_lut_size = hw->func_caps.rss_table_size;
5384 /* Enable ethtype and macvlan filters */
5385 settings.enable_ethtype = TRUE;
5386 settings.enable_macvlan = TRUE;
5387 ret = i40e_set_filter_control(hw, &settings);
5389 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5392 /* Update flow control according to the auto negotiation */
5393 i40e_update_flow_control(hw);
5395 return I40E_SUCCESS;
5399 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5405 * Set or clear TX Queue Disable flags,
5406 * which is required by hardware.
5408 i40e_pre_tx_queue_cfg(hw, q_idx, on);
5409 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5411 /* Wait until the request is finished */
5412 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5413 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5414 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5415 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5416 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5422 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5423 return I40E_SUCCESS; /* already on, skip next steps */
5425 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5426 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5428 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5429 return I40E_SUCCESS; /* already off, skip next steps */
5430 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5432 /* Write the register */
5433 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5434 /* Check the result */
5435 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5436 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5437 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5439 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5440 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5443 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5444 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5448 /* Check if it is timeout */
5449 if (j >= I40E_CHK_Q_ENA_COUNT) {
5450 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5451 (on ? "enable" : "disable"), q_idx);
5452 return I40E_ERR_TIMEOUT;
5455 return I40E_SUCCESS;
5458 /* Swith on or off the tx queues */
5460 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5462 struct rte_eth_dev_data *dev_data = pf->dev_data;
5463 struct i40e_tx_queue *txq;
5464 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5468 for (i = 0; i < dev_data->nb_tx_queues; i++) {
5469 txq = dev_data->tx_queues[i];
5470 /* Don't operate the queue if not configured or
5471 * if starting only per queue */
5472 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5475 ret = i40e_dev_tx_queue_start(dev, i);
5477 ret = i40e_dev_tx_queue_stop(dev, i);
5478 if ( ret != I40E_SUCCESS)
5482 return I40E_SUCCESS;
5486 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5491 /* Wait until the request is finished */
5492 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5493 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5494 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5495 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5496 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5501 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5502 return I40E_SUCCESS; /* Already on, skip next steps */
5503 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5505 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5506 return I40E_SUCCESS; /* Already off, skip next steps */
5507 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5510 /* Write the register */
5511 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5512 /* Check the result */
5513 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5514 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5515 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5517 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5518 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5521 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5522 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5527 /* Check if it is timeout */
5528 if (j >= I40E_CHK_Q_ENA_COUNT) {
5529 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5530 (on ? "enable" : "disable"), q_idx);
5531 return I40E_ERR_TIMEOUT;
5534 return I40E_SUCCESS;
5536 /* Switch on or off the rx queues */
5538 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5540 struct rte_eth_dev_data *dev_data = pf->dev_data;
5541 struct i40e_rx_queue *rxq;
5542 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5546 for (i = 0; i < dev_data->nb_rx_queues; i++) {
5547 rxq = dev_data->rx_queues[i];
5548 /* Don't operate the queue if not configured or
5549 * if starting only per queue */
5550 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5553 ret = i40e_dev_rx_queue_start(dev, i);
5555 ret = i40e_dev_rx_queue_stop(dev, i);
5556 if (ret != I40E_SUCCESS)
5560 return I40E_SUCCESS;
5563 /* Switch on or off all the rx/tx queues */
5565 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5570 /* enable rx queues before enabling tx queues */
5571 ret = i40e_dev_switch_rx_queues(pf, on);
5573 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5576 ret = i40e_dev_switch_tx_queues(pf, on);
5578 /* Stop tx queues before stopping rx queues */
5579 ret = i40e_dev_switch_tx_queues(pf, on);
5581 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5584 ret = i40e_dev_switch_rx_queues(pf, on);
5590 /* Initialize VSI for TX */
5592 i40e_dev_tx_init(struct i40e_pf *pf)
5594 struct rte_eth_dev_data *data = pf->dev_data;
5596 uint32_t ret = I40E_SUCCESS;
5597 struct i40e_tx_queue *txq;
5599 for (i = 0; i < data->nb_tx_queues; i++) {
5600 txq = data->tx_queues[i];
5601 if (!txq || !txq->q_set)
5603 ret = i40e_tx_queue_init(txq);
5604 if (ret != I40E_SUCCESS)
5607 if (ret == I40E_SUCCESS)
5608 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5614 /* Initialize VSI for RX */
5616 i40e_dev_rx_init(struct i40e_pf *pf)
5618 struct rte_eth_dev_data *data = pf->dev_data;
5619 int ret = I40E_SUCCESS;
5621 struct i40e_rx_queue *rxq;
5623 i40e_pf_config_mq_rx(pf);
5624 for (i = 0; i < data->nb_rx_queues; i++) {
5625 rxq = data->rx_queues[i];
5626 if (!rxq || !rxq->q_set)
5629 ret = i40e_rx_queue_init(rxq);
5630 if (ret != I40E_SUCCESS) {
5632 "Failed to do RX queue initialization");
5636 if (ret == I40E_SUCCESS)
5637 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5644 i40e_dev_rxtx_init(struct i40e_pf *pf)
5648 err = i40e_dev_tx_init(pf);
5650 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5653 err = i40e_dev_rx_init(pf);
5655 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5663 i40e_vmdq_setup(struct rte_eth_dev *dev)
5665 struct rte_eth_conf *conf = &dev->data->dev_conf;
5666 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5667 int i, err, conf_vsis, j, loop;
5668 struct i40e_vsi *vsi;
5669 struct i40e_vmdq_info *vmdq_info;
5670 struct rte_eth_vmdq_rx_conf *vmdq_conf;
5671 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5674 * Disable interrupt to avoid message from VF. Furthermore, it will
5675 * avoid race condition in VSI creation/destroy.
5677 i40e_pf_disable_irq0(hw);
5679 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5680 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5684 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5685 if (conf_vsis > pf->max_nb_vmdq_vsi) {
5686 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5687 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5688 pf->max_nb_vmdq_vsi);
5692 if (pf->vmdq != NULL) {
5693 PMD_INIT_LOG(INFO, "VMDQ already configured");
5697 pf->vmdq = rte_zmalloc("vmdq_info_struct",
5698 sizeof(*vmdq_info) * conf_vsis, 0);
5700 if (pf->vmdq == NULL) {
5701 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5705 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5707 /* Create VMDQ VSI */
5708 for (i = 0; i < conf_vsis; i++) {
5709 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5710 vmdq_conf->enable_loop_back);
5712 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5716 vmdq_info = &pf->vmdq[i];
5718 vmdq_info->vsi = vsi;
5720 pf->nb_cfg_vmdq_vsi = conf_vsis;
5722 /* Configure Vlan */
5723 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5724 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5725 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5726 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5727 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5728 vmdq_conf->pool_map[i].vlan_id, j);
5730 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5731 vmdq_conf->pool_map[i].vlan_id);
5733 PMD_INIT_LOG(ERR, "Failed to add vlan");
5741 i40e_pf_enable_irq0(hw);
5746 for (i = 0; i < conf_vsis; i++)
5747 if (pf->vmdq[i].vsi == NULL)
5750 i40e_vsi_release(pf->vmdq[i].vsi);
5754 i40e_pf_enable_irq0(hw);
5759 i40e_stat_update_32(struct i40e_hw *hw,
5767 new_data = (uint64_t)I40E_READ_REG(hw, reg);
5771 if (new_data >= *offset)
5772 *stat = (uint64_t)(new_data - *offset);
5774 *stat = (uint64_t)((new_data +
5775 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5779 i40e_stat_update_48(struct i40e_hw *hw,
5788 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5789 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5790 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5795 if (new_data >= *offset)
5796 *stat = new_data - *offset;
5798 *stat = (uint64_t)((new_data +
5799 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5801 *stat &= I40E_48_BIT_MASK;
5806 i40e_pf_disable_irq0(struct i40e_hw *hw)
5808 /* Disable all interrupt types */
5809 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5810 I40E_WRITE_FLUSH(hw);
5815 i40e_pf_enable_irq0(struct i40e_hw *hw)
5817 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5818 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5819 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5820 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5821 I40E_WRITE_FLUSH(hw);
5825 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5827 /* read pending request and disable first */
5828 i40e_pf_disable_irq0(hw);
5829 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5830 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5831 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5834 /* Link no queues with irq0 */
5835 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5836 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5840 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5842 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5843 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5846 uint32_t index, offset, val;
5851 * Try to find which VF trigger a reset, use absolute VF id to access
5852 * since the reg is global register.
5854 for (i = 0; i < pf->vf_num; i++) {
5855 abs_vf_id = hw->func_caps.vf_base_id + i;
5856 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5857 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5858 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5859 /* VFR event occurred */
5860 if (val & (0x1 << offset)) {
5863 /* Clear the event first */
5864 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5866 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
5868 * Only notify a VF reset event occurred,
5869 * don't trigger another SW reset
5871 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5872 if (ret != I40E_SUCCESS)
5873 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5879 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5881 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5884 for (i = 0; i < pf->vf_num; i++)
5885 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
5889 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5891 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5892 struct i40e_arq_event_info info;
5893 uint16_t pending, opcode;
5896 info.buf_len = I40E_AQ_BUF_SZ;
5897 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5898 if (!info.msg_buf) {
5899 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5905 ret = i40e_clean_arq_element(hw, &info, &pending);
5907 if (ret != I40E_SUCCESS) {
5909 "Failed to read msg from AdminQ, aq_err: %u",
5910 hw->aq.asq_last_status);
5913 opcode = rte_le_to_cpu_16(info.desc.opcode);
5916 case i40e_aqc_opc_send_msg_to_pf:
5917 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5918 i40e_pf_host_handle_vf_msg(dev,
5919 rte_le_to_cpu_16(info.desc.retval),
5920 rte_le_to_cpu_32(info.desc.cookie_high),
5921 rte_le_to_cpu_32(info.desc.cookie_low),
5925 case i40e_aqc_opc_get_link_status:
5926 ret = i40e_dev_link_update(dev, 0);
5928 _rte_eth_dev_callback_process(dev,
5929 RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
5932 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
5937 rte_free(info.msg_buf);
5941 * Interrupt handler triggered by NIC for handling
5942 * specific interrupt.
5945 * Pointer to interrupt handle.
5947 * The address of parameter (struct rte_eth_dev *) regsitered before.
5953 i40e_dev_interrupt_handler(void *param)
5955 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5956 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5959 /* Disable interrupt */
5960 i40e_pf_disable_irq0(hw);
5962 /* read out interrupt causes */
5963 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5965 /* No interrupt event indicated */
5966 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5967 PMD_DRV_LOG(INFO, "No interrupt event");
5970 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5971 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5972 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5973 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5974 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5975 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5976 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5977 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5978 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5979 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5980 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5981 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5982 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5983 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5985 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5986 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5987 i40e_dev_handle_vfr_event(dev);
5989 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5990 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5991 i40e_dev_handle_aq_msg(dev);
5995 /* Enable interrupt */
5996 i40e_pf_enable_irq0(hw);
5997 rte_intr_enable(dev->intr_handle);
6001 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6002 struct i40e_macvlan_filter *filter,
6005 int ele_num, ele_buff_size;
6006 int num, actual_num, i;
6008 int ret = I40E_SUCCESS;
6009 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6010 struct i40e_aqc_add_macvlan_element_data *req_list;
6012 if (filter == NULL || total == 0)
6013 return I40E_ERR_PARAM;
6014 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6015 ele_buff_size = hw->aq.asq_buf_size;
6017 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6018 if (req_list == NULL) {
6019 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6020 return I40E_ERR_NO_MEMORY;
6025 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6026 memset(req_list, 0, ele_buff_size);
6028 for (i = 0; i < actual_num; i++) {
6029 (void)rte_memcpy(req_list[i].mac_addr,
6030 &filter[num + i].macaddr, ETH_ADDR_LEN);
6031 req_list[i].vlan_tag =
6032 rte_cpu_to_le_16(filter[num + i].vlan_id);
6034 switch (filter[num + i].filter_type) {
6035 case RTE_MAC_PERFECT_MATCH:
6036 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6037 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6039 case RTE_MACVLAN_PERFECT_MATCH:
6040 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6042 case RTE_MAC_HASH_MATCH:
6043 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6044 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6046 case RTE_MACVLAN_HASH_MATCH:
6047 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6050 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6051 ret = I40E_ERR_PARAM;
6055 req_list[i].queue_number = 0;
6057 req_list[i].flags = rte_cpu_to_le_16(flags);
6060 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6062 if (ret != I40E_SUCCESS) {
6063 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6067 } while (num < total);
6075 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6076 struct i40e_macvlan_filter *filter,
6079 int ele_num, ele_buff_size;
6080 int num, actual_num, i;
6082 int ret = I40E_SUCCESS;
6083 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6084 struct i40e_aqc_remove_macvlan_element_data *req_list;
6086 if (filter == NULL || total == 0)
6087 return I40E_ERR_PARAM;
6089 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6090 ele_buff_size = hw->aq.asq_buf_size;
6092 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6093 if (req_list == NULL) {
6094 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6095 return I40E_ERR_NO_MEMORY;
6100 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6101 memset(req_list, 0, ele_buff_size);
6103 for (i = 0; i < actual_num; i++) {
6104 (void)rte_memcpy(req_list[i].mac_addr,
6105 &filter[num + i].macaddr, ETH_ADDR_LEN);
6106 req_list[i].vlan_tag =
6107 rte_cpu_to_le_16(filter[num + i].vlan_id);
6109 switch (filter[num + i].filter_type) {
6110 case RTE_MAC_PERFECT_MATCH:
6111 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6112 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6114 case RTE_MACVLAN_PERFECT_MATCH:
6115 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6117 case RTE_MAC_HASH_MATCH:
6118 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6119 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6121 case RTE_MACVLAN_HASH_MATCH:
6122 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6125 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6126 ret = I40E_ERR_PARAM;
6129 req_list[i].flags = rte_cpu_to_le_16(flags);
6132 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6134 if (ret != I40E_SUCCESS) {
6135 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6139 } while (num < total);
6146 /* Find out specific MAC filter */
6147 static struct i40e_mac_filter *
6148 i40e_find_mac_filter(struct i40e_vsi *vsi,
6149 struct ether_addr *macaddr)
6151 struct i40e_mac_filter *f;
6153 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6154 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6162 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6165 uint32_t vid_idx, vid_bit;
6167 if (vlan_id > ETH_VLAN_ID_MAX)
6170 vid_idx = I40E_VFTA_IDX(vlan_id);
6171 vid_bit = I40E_VFTA_BIT(vlan_id);
6173 if (vsi->vfta[vid_idx] & vid_bit)
6180 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6181 uint16_t vlan_id, bool on)
6183 uint32_t vid_idx, vid_bit;
6185 vid_idx = I40E_VFTA_IDX(vlan_id);
6186 vid_bit = I40E_VFTA_BIT(vlan_id);
6189 vsi->vfta[vid_idx] |= vid_bit;
6191 vsi->vfta[vid_idx] &= ~vid_bit;
6195 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6196 uint16_t vlan_id, bool on)
6198 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6199 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6202 if (vlan_id > ETH_VLAN_ID_MAX)
6205 i40e_store_vlan_filter(vsi, vlan_id, on);
6207 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6210 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6213 ret = i40e_aq_add_vlan(hw, vsi->seid,
6214 &vlan_data, 1, NULL);
6215 if (ret != I40E_SUCCESS)
6216 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6218 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6219 &vlan_data, 1, NULL);
6220 if (ret != I40E_SUCCESS)
6222 "Failed to remove vlan filter");
6227 * Find all vlan options for specific mac addr,
6228 * return with actual vlan found.
6231 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6232 struct i40e_macvlan_filter *mv_f,
6233 int num, struct ether_addr *addr)
6239 * Not to use i40e_find_vlan_filter to decrease the loop time,
6240 * although the code looks complex.
6242 if (num < vsi->vlan_num)
6243 return I40E_ERR_PARAM;
6246 for (j = 0; j < I40E_VFTA_SIZE; j++) {
6248 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6249 if (vsi->vfta[j] & (1 << k)) {
6252 "vlan number doesn't match");
6253 return I40E_ERR_PARAM;
6255 (void)rte_memcpy(&mv_f[i].macaddr,
6256 addr, ETH_ADDR_LEN);
6258 j * I40E_UINT32_BIT_SIZE + k;
6264 return I40E_SUCCESS;
6268 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6269 struct i40e_macvlan_filter *mv_f,
6274 struct i40e_mac_filter *f;
6276 if (num < vsi->mac_num)
6277 return I40E_ERR_PARAM;
6279 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6281 PMD_DRV_LOG(ERR, "buffer number not match");
6282 return I40E_ERR_PARAM;
6284 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6286 mv_f[i].vlan_id = vlan;
6287 mv_f[i].filter_type = f->mac_info.filter_type;
6291 return I40E_SUCCESS;
6295 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6298 struct i40e_mac_filter *f;
6299 struct i40e_macvlan_filter *mv_f;
6300 int ret = I40E_SUCCESS;
6302 if (vsi == NULL || vsi->mac_num == 0)
6303 return I40E_ERR_PARAM;
6305 /* Case that no vlan is set */
6306 if (vsi->vlan_num == 0)
6309 num = vsi->mac_num * vsi->vlan_num;
6311 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6313 PMD_DRV_LOG(ERR, "failed to allocate memory");
6314 return I40E_ERR_NO_MEMORY;
6318 if (vsi->vlan_num == 0) {
6319 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6320 (void)rte_memcpy(&mv_f[i].macaddr,
6321 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6322 mv_f[i].filter_type = f->mac_info.filter_type;
6323 mv_f[i].vlan_id = 0;
6327 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6328 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6329 vsi->vlan_num, &f->mac_info.mac_addr);
6330 if (ret != I40E_SUCCESS)
6332 for (j = i; j < i + vsi->vlan_num; j++)
6333 mv_f[j].filter_type = f->mac_info.filter_type;
6338 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6346 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6348 struct i40e_macvlan_filter *mv_f;
6350 int ret = I40E_SUCCESS;
6352 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6353 return I40E_ERR_PARAM;
6355 /* If it's already set, just return */
6356 if (i40e_find_vlan_filter(vsi,vlan))
6357 return I40E_SUCCESS;
6359 mac_num = vsi->mac_num;
6362 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6363 return I40E_ERR_PARAM;
6366 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6369 PMD_DRV_LOG(ERR, "failed to allocate memory");
6370 return I40E_ERR_NO_MEMORY;
6373 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6375 if (ret != I40E_SUCCESS)
6378 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6380 if (ret != I40E_SUCCESS)
6383 i40e_set_vlan_filter(vsi, vlan, 1);
6393 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6395 struct i40e_macvlan_filter *mv_f;
6397 int ret = I40E_SUCCESS;
6400 * Vlan 0 is the generic filter for untagged packets
6401 * and can't be removed.
6403 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6404 return I40E_ERR_PARAM;
6406 /* If can't find it, just return */
6407 if (!i40e_find_vlan_filter(vsi, vlan))
6408 return I40E_ERR_PARAM;
6410 mac_num = vsi->mac_num;
6413 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6414 return I40E_ERR_PARAM;
6417 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6420 PMD_DRV_LOG(ERR, "failed to allocate memory");
6421 return I40E_ERR_NO_MEMORY;
6424 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6426 if (ret != I40E_SUCCESS)
6429 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6431 if (ret != I40E_SUCCESS)
6434 /* This is last vlan to remove, replace all mac filter with vlan 0 */
6435 if (vsi->vlan_num == 1) {
6436 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6437 if (ret != I40E_SUCCESS)
6440 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6441 if (ret != I40E_SUCCESS)
6445 i40e_set_vlan_filter(vsi, vlan, 0);
6455 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6457 struct i40e_mac_filter *f;
6458 struct i40e_macvlan_filter *mv_f;
6459 int i, vlan_num = 0;
6460 int ret = I40E_SUCCESS;
6462 /* If it's add and we've config it, return */
6463 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6465 return I40E_SUCCESS;
6466 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6467 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6470 * If vlan_num is 0, that's the first time to add mac,
6471 * set mask for vlan_id 0.
6473 if (vsi->vlan_num == 0) {
6474 i40e_set_vlan_filter(vsi, 0, 1);
6477 vlan_num = vsi->vlan_num;
6478 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6479 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6482 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6484 PMD_DRV_LOG(ERR, "failed to allocate memory");
6485 return I40E_ERR_NO_MEMORY;
6488 for (i = 0; i < vlan_num; i++) {
6489 mv_f[i].filter_type = mac_filter->filter_type;
6490 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6494 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6495 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6496 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6497 &mac_filter->mac_addr);
6498 if (ret != I40E_SUCCESS)
6502 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6503 if (ret != I40E_SUCCESS)
6506 /* Add the mac addr into mac list */
6507 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6509 PMD_DRV_LOG(ERR, "failed to allocate memory");
6510 ret = I40E_ERR_NO_MEMORY;
6513 (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6515 f->mac_info.filter_type = mac_filter->filter_type;
6516 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6527 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6529 struct i40e_mac_filter *f;
6530 struct i40e_macvlan_filter *mv_f;
6532 enum rte_mac_filter_type filter_type;
6533 int ret = I40E_SUCCESS;
6535 /* Can't find it, return an error */
6536 f = i40e_find_mac_filter(vsi, addr);
6538 return I40E_ERR_PARAM;
6540 vlan_num = vsi->vlan_num;
6541 filter_type = f->mac_info.filter_type;
6542 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6543 filter_type == RTE_MACVLAN_HASH_MATCH) {
6544 if (vlan_num == 0) {
6545 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6546 return I40E_ERR_PARAM;
6548 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6549 filter_type == RTE_MAC_HASH_MATCH)
6552 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6554 PMD_DRV_LOG(ERR, "failed to allocate memory");
6555 return I40E_ERR_NO_MEMORY;
6558 for (i = 0; i < vlan_num; i++) {
6559 mv_f[i].filter_type = filter_type;
6560 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6563 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6564 filter_type == RTE_MACVLAN_HASH_MATCH) {
6565 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6566 if (ret != I40E_SUCCESS)
6570 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6571 if (ret != I40E_SUCCESS)
6574 /* Remove the mac addr into mac list */
6575 TAILQ_REMOVE(&vsi->mac_list, f, next);
6585 /* Configure hash enable flags for RSS */
6587 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6594 if (flags & ETH_RSS_FRAG_IPV4)
6595 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6596 if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6597 if (type == I40E_MAC_X722) {
6598 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6599 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6601 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6603 if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6604 if (type == I40E_MAC_X722) {
6605 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6606 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6607 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6609 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6611 if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6612 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6613 if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6614 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6615 if (flags & ETH_RSS_FRAG_IPV6)
6616 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6617 if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6618 if (type == I40E_MAC_X722) {
6619 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6620 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6622 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6624 if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6625 if (type == I40E_MAC_X722) {
6626 hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6627 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6628 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6630 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6632 if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6633 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6634 if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6635 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6636 if (flags & ETH_RSS_L2_PAYLOAD)
6637 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6642 /* Parse the hash enable flags */
6644 i40e_parse_hena(uint64_t flags)
6646 uint64_t rss_hf = 0;
6650 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6651 rss_hf |= ETH_RSS_FRAG_IPV4;
6652 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6653 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6654 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6655 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6656 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6657 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6658 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6659 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6660 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6661 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6662 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6663 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6664 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6665 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6666 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6667 rss_hf |= ETH_RSS_FRAG_IPV6;
6668 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6669 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6670 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6671 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6672 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6673 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6674 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6675 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6676 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6677 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6678 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6679 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6680 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6681 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6682 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6683 rss_hf |= ETH_RSS_L2_PAYLOAD;
6690 i40e_pf_disable_rss(struct i40e_pf *pf)
6692 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6695 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6696 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6697 if (hw->mac.type == I40E_MAC_X722)
6698 hena &= ~I40E_RSS_HENA_ALL_X722;
6700 hena &= ~I40E_RSS_HENA_ALL;
6701 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6702 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6703 I40E_WRITE_FLUSH(hw);
6707 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6709 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6710 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6713 if (!key || key_len == 0) {
6714 PMD_DRV_LOG(DEBUG, "No key to be configured");
6716 } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6718 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6722 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6723 struct i40e_aqc_get_set_rss_key_data *key_dw =
6724 (struct i40e_aqc_get_set_rss_key_data *)key;
6726 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6728 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6730 uint32_t *hash_key = (uint32_t *)key;
6733 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6734 i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6735 I40E_WRITE_FLUSH(hw);
6742 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6744 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6745 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6748 if (!key || !key_len)
6751 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6752 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6753 (struct i40e_aqc_get_set_rss_key_data *)key);
6755 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6759 uint32_t *key_dw = (uint32_t *)key;
6762 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6763 key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6765 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6771 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6773 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6778 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6779 rss_conf->rss_key_len);
6783 rss_hf = rss_conf->rss_hf;
6784 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6785 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6786 if (hw->mac.type == I40E_MAC_X722)
6787 hena &= ~I40E_RSS_HENA_ALL_X722;
6789 hena &= ~I40E_RSS_HENA_ALL;
6790 hena |= i40e_config_hena(rss_hf, hw->mac.type);
6791 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6792 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6793 I40E_WRITE_FLUSH(hw);
6799 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6800 struct rte_eth_rss_conf *rss_conf)
6802 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6803 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6804 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6807 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6808 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6809 if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6810 ? I40E_RSS_HENA_ALL_X722
6811 : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6812 if (rss_hf != 0) /* Enable RSS */
6814 return 0; /* Nothing to do */
6817 if (rss_hf == 0) /* Disable RSS */
6820 return i40e_hw_rss_hash_set(pf, rss_conf);
6824 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6825 struct rte_eth_rss_conf *rss_conf)
6827 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6828 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6831 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6832 &rss_conf->rss_key_len);
6834 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6835 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6836 rss_conf->rss_hf = i40e_parse_hena(hena);
6842 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6844 switch (filter_type) {
6845 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6846 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6848 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6849 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6851 case RTE_TUNNEL_FILTER_IMAC_TENID:
6852 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6854 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6855 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6857 case ETH_TUNNEL_FILTER_IMAC:
6858 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6860 case ETH_TUNNEL_FILTER_OIP:
6861 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6863 case ETH_TUNNEL_FILTER_IIP:
6864 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6867 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6874 /* Convert tunnel filter structure */
6876 i40e_tunnel_filter_convert(
6877 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
6878 struct i40e_tunnel_filter *tunnel_filter)
6880 ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
6881 (struct ether_addr *)&tunnel_filter->input.outer_mac);
6882 ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
6883 (struct ether_addr *)&tunnel_filter->input.inner_mac);
6884 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
6885 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
6886 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6887 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6888 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6890 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6891 tunnel_filter->input.flags = cld_filter->element.flags;
6892 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
6893 tunnel_filter->queue = cld_filter->element.queue_number;
6894 rte_memcpy(tunnel_filter->input.general_fields,
6895 cld_filter->general_fields,
6896 sizeof(cld_filter->general_fields));
6901 /* Check if there exists the tunnel filter */
6902 struct i40e_tunnel_filter *
6903 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6904 const struct i40e_tunnel_filter_input *input)
6908 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6912 return tunnel_rule->hash_map[ret];
6915 /* Add a tunnel filter into the SW list */
6917 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6918 struct i40e_tunnel_filter *tunnel_filter)
6920 struct i40e_tunnel_rule *rule = &pf->tunnel;
6923 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6926 "Failed to insert tunnel filter to hash table %d!",
6930 rule->hash_map[ret] = tunnel_filter;
6932 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6937 /* Delete a tunnel filter from the SW list */
6939 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6940 struct i40e_tunnel_filter_input *input)
6942 struct i40e_tunnel_rule *rule = &pf->tunnel;
6943 struct i40e_tunnel_filter *tunnel_filter;
6946 ret = rte_hash_del_key(rule->hash_table, input);
6949 "Failed to delete tunnel filter to hash table %d!",
6953 tunnel_filter = rule->hash_map[ret];
6954 rule->hash_map[ret] = NULL;
6956 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6957 rte_free(tunnel_filter);
6963 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6964 struct rte_eth_tunnel_filter_conf *tunnel_filter,
6969 uint8_t i, tun_type = 0;
6970 /* internal varialbe to convert ipv6 byte order */
6971 uint32_t convert_ipv6[4];
6973 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6974 struct i40e_vsi *vsi = pf->main_vsi;
6975 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
6976 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
6977 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6978 struct i40e_tunnel_filter *tunnel, *node;
6979 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6981 cld_filter = rte_zmalloc("tunnel_filter",
6982 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
6985 if (NULL == cld_filter) {
6986 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6989 pfilter = cld_filter;
6991 ether_addr_copy(&tunnel_filter->outer_mac,
6992 (struct ether_addr *)&pfilter->element.outer_mac);
6993 ether_addr_copy(&tunnel_filter->inner_mac,
6994 (struct ether_addr *)&pfilter->element.inner_mac);
6996 pfilter->element.inner_vlan =
6997 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6998 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6999 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7000 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7001 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7002 &rte_cpu_to_le_32(ipv4_addr),
7003 sizeof(pfilter->element.ipaddr.v4.data));
7005 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7006 for (i = 0; i < 4; i++) {
7008 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7010 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7012 sizeof(pfilter->element.ipaddr.v6.data));
7015 /* check tunneled type */
7016 switch (tunnel_filter->tunnel_type) {
7017 case RTE_TUNNEL_TYPE_VXLAN:
7018 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7020 case RTE_TUNNEL_TYPE_NVGRE:
7021 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7023 case RTE_TUNNEL_TYPE_IP_IN_GRE:
7024 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7027 /* Other tunnel types is not supported. */
7028 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7029 rte_free(cld_filter);
7033 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7034 &pfilter->element.flags);
7036 rte_free(cld_filter);
7040 pfilter->element.flags |= rte_cpu_to_le_16(
7041 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7042 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7043 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7044 pfilter->element.queue_number =
7045 rte_cpu_to_le_16(tunnel_filter->queue_id);
7047 /* Check if there is the filter in SW list */
7048 memset(&check_filter, 0, sizeof(check_filter));
7049 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7050 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7052 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7056 if (!add && !node) {
7057 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7062 ret = i40e_aq_add_cloud_filters(hw,
7063 vsi->seid, &cld_filter->element, 1);
7065 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7068 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7069 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7070 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7072 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7073 &cld_filter->element, 1);
7075 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7078 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7081 rte_free(cld_filter);
7085 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7086 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
7087 #define I40E_TR_GENEVE_KEY_MASK 0x8
7088 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
7089 #define I40E_TR_GRE_KEY_MASK 0x400
7090 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
7091 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
7094 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7096 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7097 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7098 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7099 enum i40e_status_code status = I40E_SUCCESS;
7101 memset(&filter_replace, 0,
7102 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7103 memset(&filter_replace_buf, 0,
7104 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7106 /* create L1 filter */
7107 filter_replace.old_filter_type =
7108 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7109 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7110 filter_replace.tr_bit = 0;
7112 /* Prepare the buffer, 3 entries */
7113 filter_replace_buf.data[0] =
7114 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7115 filter_replace_buf.data[0] |=
7116 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7117 filter_replace_buf.data[2] = 0xFF;
7118 filter_replace_buf.data[3] = 0xFF;
7119 filter_replace_buf.data[4] =
7120 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7121 filter_replace_buf.data[4] |=
7122 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7123 filter_replace_buf.data[7] = 0xF0;
7124 filter_replace_buf.data[8]
7125 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7126 filter_replace_buf.data[8] |=
7127 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7128 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7129 I40E_TR_GENEVE_KEY_MASK |
7130 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7131 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7132 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7133 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7135 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7136 &filter_replace_buf);
7141 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7143 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7144 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7145 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7146 enum i40e_status_code status = I40E_SUCCESS;
7149 memset(&filter_replace, 0,
7150 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7151 memset(&filter_replace_buf, 0,
7152 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7153 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7154 I40E_AQC_MIRROR_CLOUD_FILTER;
7155 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7156 filter_replace.new_filter_type =
7157 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7158 /* Prepare the buffer, 2 entries */
7159 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7160 filter_replace_buf.data[0] |=
7161 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7162 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7163 filter_replace_buf.data[4] |=
7164 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7165 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7166 &filter_replace_buf);
7171 memset(&filter_replace, 0,
7172 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7173 memset(&filter_replace_buf, 0,
7174 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7176 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7177 I40E_AQC_MIRROR_CLOUD_FILTER;
7178 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7179 filter_replace.new_filter_type =
7180 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7181 /* Prepare the buffer, 2 entries */
7182 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7183 filter_replace_buf.data[0] |=
7184 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7185 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_TEID_MPLS;
7186 filter_replace_buf.data[4] |=
7187 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7189 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7190 &filter_replace_buf);
7195 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7196 struct i40e_tunnel_filter_conf *tunnel_filter,
7201 uint8_t i, tun_type = 0;
7202 /* internal variable to convert ipv6 byte order */
7203 uint32_t convert_ipv6[4];
7205 struct i40e_pf_vf *vf = NULL;
7206 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7207 struct i40e_vsi *vsi;
7208 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7209 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7210 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7211 struct i40e_tunnel_filter *tunnel, *node;
7212 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7214 bool big_buffer = 0;
7216 cld_filter = rte_zmalloc("tunnel_filter",
7217 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7220 if (cld_filter == NULL) {
7221 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7224 pfilter = cld_filter;
7226 ether_addr_copy(&tunnel_filter->outer_mac,
7227 (struct ether_addr *)&pfilter->element.outer_mac);
7228 ether_addr_copy(&tunnel_filter->inner_mac,
7229 (struct ether_addr *)&pfilter->element.inner_mac);
7231 pfilter->element.inner_vlan =
7232 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7233 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7234 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7235 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7236 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7237 &rte_cpu_to_le_32(ipv4_addr),
7238 sizeof(pfilter->element.ipaddr.v4.data));
7240 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7241 for (i = 0; i < 4; i++) {
7243 rte_cpu_to_le_32(rte_be_to_cpu_32(
7244 tunnel_filter->ip_addr.ipv6_addr[i]));
7246 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7248 sizeof(pfilter->element.ipaddr.v6.data));
7251 /* check tunneled type */
7252 switch (tunnel_filter->tunnel_type) {
7253 case I40E_TUNNEL_TYPE_VXLAN:
7254 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7256 case I40E_TUNNEL_TYPE_NVGRE:
7257 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7259 case I40E_TUNNEL_TYPE_IP_IN_GRE:
7260 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7262 case I40E_TUNNEL_TYPE_MPLSoUDP:
7263 if (!pf->mpls_replace_flag) {
7264 i40e_replace_mpls_l1_filter(pf);
7265 i40e_replace_mpls_cloud_filter(pf);
7266 pf->mpls_replace_flag = 1;
7268 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7269 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7271 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7272 (teid_le & 0xF) << 12;
7273 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7276 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoUDP;
7278 case I40E_TUNNEL_TYPE_MPLSoGRE:
7279 if (!pf->mpls_replace_flag) {
7280 i40e_replace_mpls_l1_filter(pf);
7281 i40e_replace_mpls_cloud_filter(pf);
7282 pf->mpls_replace_flag = 1;
7284 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7285 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7287 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7288 (teid_le & 0xF) << 12;
7289 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7292 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSoGRE;
7294 case I40E_TUNNEL_TYPE_QINQ:
7295 if (!pf->qinq_replace_flag) {
7296 ret = i40e_cloud_filter_qinq_create(pf);
7299 "QinQ tunnel filter already created.");
7300 pf->qinq_replace_flag = 1;
7302 /* Add in the General fields the values of
7303 * the Outer and Inner VLAN
7304 * Big Buffer should be set, see changes in
7305 * i40e_aq_add_cloud_filters
7307 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7308 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7312 /* Other tunnel types is not supported. */
7313 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7314 rte_free(cld_filter);
7318 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7319 pfilter->element.flags =
7320 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP;
7321 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7322 pfilter->element.flags =
7323 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE;
7324 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7325 pfilter->element.flags |=
7326 I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
7328 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7329 &pfilter->element.flags);
7331 rte_free(cld_filter);
7336 pfilter->element.flags |= rte_cpu_to_le_16(
7337 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7338 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7339 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7340 pfilter->element.queue_number =
7341 rte_cpu_to_le_16(tunnel_filter->queue_id);
7343 if (!tunnel_filter->is_to_vf)
7346 if (tunnel_filter->vf_id >= pf->vf_num) {
7347 PMD_DRV_LOG(ERR, "Invalid argument.");
7350 vf = &pf->vfs[tunnel_filter->vf_id];
7354 /* Check if there is the filter in SW list */
7355 memset(&check_filter, 0, sizeof(check_filter));
7356 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7357 check_filter.is_to_vf = tunnel_filter->is_to_vf;
7358 check_filter.vf_id = tunnel_filter->vf_id;
7359 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7361 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7365 if (!add && !node) {
7366 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7372 ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7373 vsi->seid, cld_filter, 1);
7375 ret = i40e_aq_add_cloud_filters(hw,
7376 vsi->seid, &cld_filter->element, 1);
7378 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7381 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7382 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7383 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7386 ret = i40e_aq_remove_cloud_filters_big_buffer(
7387 hw, vsi->seid, cld_filter, 1);
7389 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7390 &cld_filter->element, 1);
7392 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7395 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7398 rte_free(cld_filter);
7403 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7407 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7408 if (pf->vxlan_ports[i] == port)
7416 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7420 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7422 idx = i40e_get_vxlan_port_idx(pf, port);
7424 /* Check if port already exists */
7426 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7430 /* Now check if there is space to add the new port */
7431 idx = i40e_get_vxlan_port_idx(pf, 0);
7434 "Maximum number of UDP ports reached, not adding port %d",
7439 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7442 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7446 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7449 /* New port: add it and mark its index in the bitmap */
7450 pf->vxlan_ports[idx] = port;
7451 pf->vxlan_bitmap |= (1 << idx);
7453 if (!(pf->flags & I40E_FLAG_VXLAN))
7454 pf->flags |= I40E_FLAG_VXLAN;
7460 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7463 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7465 if (!(pf->flags & I40E_FLAG_VXLAN)) {
7466 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7470 idx = i40e_get_vxlan_port_idx(pf, port);
7473 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7477 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7478 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7482 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7485 pf->vxlan_ports[idx] = 0;
7486 pf->vxlan_bitmap &= ~(1 << idx);
7488 if (!pf->vxlan_bitmap)
7489 pf->flags &= ~I40E_FLAG_VXLAN;
7494 /* Add UDP tunneling port */
7496 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7497 struct rte_eth_udp_tunnel *udp_tunnel)
7500 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7502 if (udp_tunnel == NULL)
7505 switch (udp_tunnel->prot_type) {
7506 case RTE_TUNNEL_TYPE_VXLAN:
7507 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7510 case RTE_TUNNEL_TYPE_GENEVE:
7511 case RTE_TUNNEL_TYPE_TEREDO:
7512 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7517 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7525 /* Remove UDP tunneling port */
7527 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7528 struct rte_eth_udp_tunnel *udp_tunnel)
7531 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7533 if (udp_tunnel == NULL)
7536 switch (udp_tunnel->prot_type) {
7537 case RTE_TUNNEL_TYPE_VXLAN:
7538 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7540 case RTE_TUNNEL_TYPE_GENEVE:
7541 case RTE_TUNNEL_TYPE_TEREDO:
7542 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7546 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7554 /* Calculate the maximum number of contiguous PF queues that are configured */
7556 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7558 struct rte_eth_dev_data *data = pf->dev_data;
7560 struct i40e_rx_queue *rxq;
7563 for (i = 0; i < pf->lan_nb_qps; i++) {
7564 rxq = data->rx_queues[i];
7565 if (rxq && rxq->q_set)
7576 i40e_pf_config_rss(struct i40e_pf *pf)
7578 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7579 struct rte_eth_rss_conf rss_conf;
7580 uint32_t i, lut = 0;
7584 * If both VMDQ and RSS enabled, not all of PF queues are configured.
7585 * It's necessary to calculate the actual PF queues that are configured.
7587 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7588 num = i40e_pf_calc_configured_queues_num(pf);
7590 num = pf->dev_data->nb_rx_queues;
7592 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7593 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7597 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7601 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7604 lut = (lut << 8) | (j & ((0x1 <<
7605 hw->func_caps.rss_table_entry_width) - 1));
7607 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7610 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7611 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
7612 i40e_pf_disable_rss(pf);
7615 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7616 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7617 /* Random default keys */
7618 static uint32_t rss_key_default[] = {0x6b793944,
7619 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7620 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7621 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7623 rss_conf.rss_key = (uint8_t *)rss_key_default;
7624 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7628 return i40e_hw_rss_hash_set(pf, &rss_conf);
7632 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7633 struct rte_eth_tunnel_filter_conf *filter)
7635 if (pf == NULL || filter == NULL) {
7636 PMD_DRV_LOG(ERR, "Invalid parameter");
7640 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7641 PMD_DRV_LOG(ERR, "Invalid queue ID");
7645 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7646 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7650 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7651 (is_zero_ether_addr(&filter->outer_mac))) {
7652 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7656 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7657 (is_zero_ether_addr(&filter->inner_mac))) {
7658 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7665 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7666 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
7668 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7673 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7674 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7677 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7678 } else if (len == 4) {
7679 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7681 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7686 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7693 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7694 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7700 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7707 switch (cfg->cfg_type) {
7708 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7709 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7712 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7720 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7721 enum rte_filter_op filter_op,
7724 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7725 int ret = I40E_ERR_PARAM;
7727 switch (filter_op) {
7728 case RTE_ETH_FILTER_SET:
7729 ret = i40e_dev_global_config_set(hw,
7730 (struct rte_eth_global_cfg *)arg);
7733 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7741 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7742 enum rte_filter_op filter_op,
7745 struct rte_eth_tunnel_filter_conf *filter;
7746 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7747 int ret = I40E_SUCCESS;
7749 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7751 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7752 return I40E_ERR_PARAM;
7754 switch (filter_op) {
7755 case RTE_ETH_FILTER_NOP:
7756 if (!(pf->flags & I40E_FLAG_VXLAN))
7757 ret = I40E_NOT_SUPPORTED;
7759 case RTE_ETH_FILTER_ADD:
7760 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7762 case RTE_ETH_FILTER_DELETE:
7763 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7766 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7767 ret = I40E_ERR_PARAM;
7775 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7778 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7781 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7782 ret = i40e_pf_config_rss(pf);
7784 i40e_pf_disable_rss(pf);
7789 /* Get the symmetric hash enable configurations per port */
7791 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7793 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7795 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7798 /* Set the symmetric hash enable configurations per port */
7800 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7802 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7805 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7807 "Symmetric hash has already been enabled");
7810 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7812 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7814 "Symmetric hash has already been disabled");
7817 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7819 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7820 I40E_WRITE_FLUSH(hw);
7824 * Get global configurations of hash function type and symmetric hash enable
7825 * per flow type (pctype). Note that global configuration means it affects all
7826 * the ports on the same NIC.
7829 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7830 struct rte_eth_hash_global_conf *g_cfg)
7832 uint32_t reg, mask = I40E_FLOW_TYPES;
7834 enum i40e_filter_pctype pctype;
7836 memset(g_cfg, 0, sizeof(*g_cfg));
7837 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7838 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7839 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7841 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7842 PMD_DRV_LOG(DEBUG, "Hash function is %s",
7843 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7845 for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7846 if (!(mask & (1UL << i)))
7848 mask &= ~(1UL << i);
7849 /* Bit set indicats the coresponding flow type is supported */
7850 g_cfg->valid_bit_mask[0] |= (1UL << i);
7851 /* if flowtype is invalid, continue */
7852 if (!I40E_VALID_FLOW(i))
7854 pctype = i40e_flowtype_to_pctype(i);
7855 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7856 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7857 g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7864 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7867 uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7869 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7870 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7871 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7872 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7878 * As i40e supports less than 32 flow types, only first 32 bits need to
7881 mask0 = g_cfg->valid_bit_mask[0];
7882 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7884 /* Check if any unsupported flow type configured */
7885 if ((mask0 | i40e_mask) ^ i40e_mask)
7888 if (g_cfg->valid_bit_mask[i])
7896 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7902 * Set global configurations of hash function type and symmetric hash enable
7903 * per flow type (pctype). Note any modifying global configuration will affect
7904 * all the ports on the same NIC.
7907 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7908 struct rte_eth_hash_global_conf *g_cfg)
7913 uint32_t mask0 = g_cfg->valid_bit_mask[0];
7914 enum i40e_filter_pctype pctype;
7916 /* Check the input parameters */
7917 ret = i40e_hash_global_config_check(g_cfg);
7921 for (i = 0; mask0 && i < UINT32_BIT; i++) {
7922 if (!(mask0 & (1UL << i)))
7924 mask0 &= ~(1UL << i);
7925 /* if flowtype is invalid, continue */
7926 if (!I40E_VALID_FLOW(i))
7928 pctype = i40e_flowtype_to_pctype(i);
7929 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7930 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7931 if (hw->mac.type == I40E_MAC_X722) {
7932 if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_UDP) {
7933 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7934 I40E_FILTER_PCTYPE_NONF_IPV4_UDP), reg);
7935 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7936 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP),
7938 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7939 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP),
7941 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_TCP) {
7942 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7943 I40E_FILTER_PCTYPE_NONF_IPV4_TCP), reg);
7944 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7945 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK),
7947 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_UDP) {
7948 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7949 I40E_FILTER_PCTYPE_NONF_IPV6_UDP), reg);
7950 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7951 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP),
7953 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7954 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP),
7956 } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_TCP) {
7957 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7958 I40E_FILTER_PCTYPE_NONF_IPV6_TCP), reg);
7959 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(
7960 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK),
7963 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype),
7967 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7971 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7972 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7974 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7976 "Hash function already set to Toeplitz");
7979 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7980 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7982 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7984 "Hash function already set to Simple XOR");
7987 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7989 /* Use the default, and keep it as it is */
7992 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7995 I40E_WRITE_FLUSH(hw);
8001 * Valid input sets for hash and flow director filters per PCTYPE
8004 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8005 enum rte_filter_type filter)
8009 static const uint64_t valid_hash_inset_table[] = {
8010 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8011 I40E_INSET_DMAC | I40E_INSET_SMAC |
8012 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8013 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8014 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8015 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8016 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8017 I40E_INSET_FLEX_PAYLOAD,
8018 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8019 I40E_INSET_DMAC | I40E_INSET_SMAC |
8020 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8021 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8022 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8023 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8024 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8025 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8026 I40E_INSET_FLEX_PAYLOAD,
8027 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8028 I40E_INSET_DMAC | I40E_INSET_SMAC |
8029 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8030 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8031 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8032 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8033 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8034 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8035 I40E_INSET_FLEX_PAYLOAD,
8036 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8037 I40E_INSET_DMAC | I40E_INSET_SMAC |
8038 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8039 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8040 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8041 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8042 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8043 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8044 I40E_INSET_FLEX_PAYLOAD,
8045 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8046 I40E_INSET_DMAC | I40E_INSET_SMAC |
8047 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8048 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8049 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8050 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8051 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8052 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8053 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8054 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8055 I40E_INSET_DMAC | I40E_INSET_SMAC |
8056 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8057 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8058 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8059 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8060 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8061 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8062 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8063 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8064 I40E_INSET_DMAC | I40E_INSET_SMAC |
8065 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8066 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8067 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8068 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8069 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8070 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8071 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8072 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8073 I40E_INSET_DMAC | I40E_INSET_SMAC |
8074 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8075 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8076 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8077 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8078 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8079 I40E_INSET_FLEX_PAYLOAD,
8080 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8081 I40E_INSET_DMAC | I40E_INSET_SMAC |
8082 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8083 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8084 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8085 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8086 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8087 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8088 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8089 I40E_INSET_DMAC | I40E_INSET_SMAC |
8090 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8091 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8092 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8093 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8094 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8095 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8096 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8097 I40E_INSET_DMAC | I40E_INSET_SMAC |
8098 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8099 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8100 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8101 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8102 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8103 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8104 I40E_INSET_FLEX_PAYLOAD,
8105 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8106 I40E_INSET_DMAC | I40E_INSET_SMAC |
8107 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8108 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8109 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8110 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8111 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8112 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8113 I40E_INSET_FLEX_PAYLOAD,
8114 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8115 I40E_INSET_DMAC | I40E_INSET_SMAC |
8116 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8117 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8118 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8119 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8120 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8121 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8122 I40E_INSET_FLEX_PAYLOAD,
8123 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8124 I40E_INSET_DMAC | I40E_INSET_SMAC |
8125 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8126 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8127 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8128 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8129 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8130 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8131 I40E_INSET_FLEX_PAYLOAD,
8132 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8133 I40E_INSET_DMAC | I40E_INSET_SMAC |
8134 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8135 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8136 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8137 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8138 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8139 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8140 I40E_INSET_FLEX_PAYLOAD,
8141 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8142 I40E_INSET_DMAC | I40E_INSET_SMAC |
8143 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8144 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8145 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8146 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8147 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8148 I40E_INSET_FLEX_PAYLOAD,
8149 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8150 I40E_INSET_DMAC | I40E_INSET_SMAC |
8151 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8152 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8153 I40E_INSET_FLEX_PAYLOAD,
8157 * Flow director supports only fields defined in
8158 * union rte_eth_fdir_flow.
8160 static const uint64_t valid_fdir_inset_table[] = {
8161 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8162 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8163 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8164 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8165 I40E_INSET_IPV4_TTL,
8166 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8167 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8168 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8169 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8170 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8171 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8172 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8173 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8174 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8175 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8176 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8177 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8178 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8179 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8180 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8181 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8182 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8183 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8184 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8185 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8186 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8187 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8188 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8189 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8190 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8191 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8192 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8193 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8194 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8195 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8197 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8198 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8199 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8200 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8201 I40E_INSET_IPV4_TTL,
8202 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8203 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8204 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8205 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8206 I40E_INSET_IPV6_HOP_LIMIT,
8207 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8208 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8209 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8210 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8211 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8212 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8213 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8214 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8215 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8216 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8217 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8218 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8219 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8220 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8221 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8222 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8223 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8224 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8225 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8226 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8227 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8228 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8229 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8230 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8231 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8232 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8233 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8234 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8235 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8236 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8238 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8239 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8240 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8241 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8242 I40E_INSET_IPV6_HOP_LIMIT,
8243 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8244 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8245 I40E_INSET_LAST_ETHER_TYPE,
8248 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8250 if (filter == RTE_ETH_FILTER_HASH)
8251 valid = valid_hash_inset_table[pctype];
8253 valid = valid_fdir_inset_table[pctype];
8259 * Validate if the input set is allowed for a specific PCTYPE
8262 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8263 enum rte_filter_type filter, uint64_t inset)
8267 valid = i40e_get_valid_input_set(pctype, filter);
8268 if (inset & (~valid))
8274 /* default input set fields combination per pctype */
8276 i40e_get_default_input_set(uint16_t pctype)
8278 static const uint64_t default_inset_table[] = {
8279 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8280 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8281 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8282 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8283 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8284 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8285 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8286 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8287 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8288 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8289 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8290 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8291 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8292 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8293 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8294 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8295 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8296 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8297 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8298 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8300 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8301 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8302 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8303 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8304 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8305 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8306 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8307 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8308 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8309 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8310 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8311 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8312 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8313 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8314 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8315 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8316 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8317 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8318 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8319 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8320 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8321 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8323 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8324 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8325 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8326 I40E_INSET_LAST_ETHER_TYPE,
8329 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8332 return default_inset_table[pctype];
8336 * Parse the input set from index to logical bit masks
8339 i40e_parse_input_set(uint64_t *inset,
8340 enum i40e_filter_pctype pctype,
8341 enum rte_eth_input_set_field *field,
8347 static const struct {
8348 enum rte_eth_input_set_field field;
8350 } inset_convert_table[] = {
8351 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8352 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8353 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8354 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8355 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8356 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8357 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8358 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8359 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8360 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8361 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8362 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8363 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8364 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8365 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8366 I40E_INSET_IPV6_NEXT_HDR},
8367 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8368 I40E_INSET_IPV6_HOP_LIMIT},
8369 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8370 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8371 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8372 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8373 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8374 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8375 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8376 I40E_INSET_SCTP_VT},
8377 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8378 I40E_INSET_TUNNEL_DMAC},
8379 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8380 I40E_INSET_VLAN_TUNNEL},
8381 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8382 I40E_INSET_TUNNEL_ID},
8383 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8384 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8385 I40E_INSET_FLEX_PAYLOAD_W1},
8386 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8387 I40E_INSET_FLEX_PAYLOAD_W2},
8388 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8389 I40E_INSET_FLEX_PAYLOAD_W3},
8390 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8391 I40E_INSET_FLEX_PAYLOAD_W4},
8392 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8393 I40E_INSET_FLEX_PAYLOAD_W5},
8394 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8395 I40E_INSET_FLEX_PAYLOAD_W6},
8396 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8397 I40E_INSET_FLEX_PAYLOAD_W7},
8398 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8399 I40E_INSET_FLEX_PAYLOAD_W8},
8402 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8405 /* Only one item allowed for default or all */
8407 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8408 *inset = i40e_get_default_input_set(pctype);
8410 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8411 *inset = I40E_INSET_NONE;
8416 for (i = 0, *inset = 0; i < size; i++) {
8417 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8418 if (field[i] == inset_convert_table[j].field) {
8419 *inset |= inset_convert_table[j].inset;
8424 /* It contains unsupported input set, return immediately */
8425 if (j == RTE_DIM(inset_convert_table))
8433 * Translate the input set from bit masks to register aware bit masks
8437 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8447 static const struct inset_map inset_map_common[] = {
8448 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8449 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8450 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8451 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8452 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8453 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8454 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8455 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8456 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8457 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8458 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8459 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8460 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8461 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8462 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8463 {I40E_INSET_TUNNEL_DMAC,
8464 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8465 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8466 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8467 {I40E_INSET_TUNNEL_SRC_PORT,
8468 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8469 {I40E_INSET_TUNNEL_DST_PORT,
8470 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8471 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8472 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8473 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8474 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8475 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8476 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8477 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8478 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8479 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8482 /* some different registers map in x722*/
8483 static const struct inset_map inset_map_diff_x722[] = {
8484 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8485 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8486 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8487 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8490 static const struct inset_map inset_map_diff_not_x722[] = {
8491 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8492 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8493 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8494 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8500 /* Translate input set to register aware inset */
8501 if (type == I40E_MAC_X722) {
8502 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8503 if (input & inset_map_diff_x722[i].inset)
8504 val |= inset_map_diff_x722[i].inset_reg;
8507 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8508 if (input & inset_map_diff_not_x722[i].inset)
8509 val |= inset_map_diff_not_x722[i].inset_reg;
8513 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8514 if (input & inset_map_common[i].inset)
8515 val |= inset_map_common[i].inset_reg;
8522 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8525 uint64_t inset_need_mask = inset;
8527 static const struct {
8530 } inset_mask_map[] = {
8531 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8532 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8533 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8534 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8535 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8536 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8537 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8538 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8541 if (!inset || !mask || !nb_elem)
8544 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8545 /* Clear the inset bit, if no MASK is required,
8546 * for example proto + ttl
8548 if ((inset & inset_mask_map[i].inset) ==
8549 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8550 inset_need_mask &= ~inset_mask_map[i].inset;
8551 if (!inset_need_mask)
8554 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8555 if ((inset_need_mask & inset_mask_map[i].inset) ==
8556 inset_mask_map[i].inset) {
8557 if (idx >= nb_elem) {
8558 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8561 mask[idx] = inset_mask_map[i].mask;
8570 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8572 uint32_t reg = i40e_read_rx_ctl(hw, addr);
8574 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8576 i40e_write_rx_ctl(hw, addr, val);
8577 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8578 (uint32_t)i40e_read_rx_ctl(hw, addr));
8582 i40e_filter_input_set_init(struct i40e_pf *pf)
8584 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8585 enum i40e_filter_pctype pctype;
8586 uint64_t input_set, inset_reg;
8587 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8590 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8591 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8592 if (hw->mac.type == I40E_MAC_X722) {
8593 if (!I40E_VALID_PCTYPE_X722(pctype))
8596 if (!I40E_VALID_PCTYPE(pctype))
8600 input_set = i40e_get_default_input_set(pctype);
8602 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8603 I40E_INSET_MASK_NUM_REG);
8606 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8609 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8610 (uint32_t)(inset_reg & UINT32_MAX));
8611 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8612 (uint32_t)((inset_reg >>
8613 I40E_32_BIT_WIDTH) & UINT32_MAX));
8614 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8615 (uint32_t)(inset_reg & UINT32_MAX));
8616 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8617 (uint32_t)((inset_reg >>
8618 I40E_32_BIT_WIDTH) & UINT32_MAX));
8620 for (i = 0; i < num; i++) {
8621 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8623 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8626 /*clear unused mask registers of the pctype */
8627 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8628 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8630 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8633 I40E_WRITE_FLUSH(hw);
8635 /* store the default input set */
8636 pf->hash_input_set[pctype] = input_set;
8637 pf->fdir.input_set[pctype] = input_set;
8642 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8643 struct rte_eth_input_set_conf *conf)
8645 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8646 enum i40e_filter_pctype pctype;
8647 uint64_t input_set, inset_reg = 0;
8648 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8652 PMD_DRV_LOG(ERR, "Invalid pointer");
8655 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8656 conf->op != RTE_ETH_INPUT_SET_ADD) {
8657 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8661 if (!I40E_VALID_FLOW(conf->flow_type)) {
8662 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8666 if (hw->mac.type == I40E_MAC_X722) {
8667 /* get translated pctype value in fd pctype register */
8668 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8669 I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8672 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8674 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8677 PMD_DRV_LOG(ERR, "Failed to parse input set");
8680 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8682 PMD_DRV_LOG(ERR, "Invalid input set");
8685 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8686 /* get inset value in register */
8687 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8688 inset_reg <<= I40E_32_BIT_WIDTH;
8689 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8690 input_set |= pf->hash_input_set[pctype];
8692 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8693 I40E_INSET_MASK_NUM_REG);
8697 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8699 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8700 (uint32_t)(inset_reg & UINT32_MAX));
8701 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8702 (uint32_t)((inset_reg >>
8703 I40E_32_BIT_WIDTH) & UINT32_MAX));
8705 for (i = 0; i < num; i++)
8706 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8708 /*clear unused mask registers of the pctype */
8709 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8710 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8712 I40E_WRITE_FLUSH(hw);
8714 pf->hash_input_set[pctype] = input_set;
8719 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8720 struct rte_eth_input_set_conf *conf)
8722 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8723 enum i40e_filter_pctype pctype;
8724 uint64_t input_set, inset_reg = 0;
8725 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8729 PMD_DRV_LOG(ERR, "Invalid pointer");
8732 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8733 conf->op != RTE_ETH_INPUT_SET_ADD) {
8734 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8738 if (!I40E_VALID_FLOW(conf->flow_type)) {
8739 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8743 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8745 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8748 PMD_DRV_LOG(ERR, "Failed to parse input set");
8751 if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8753 PMD_DRV_LOG(ERR, "Invalid input set");
8757 /* get inset value in register */
8758 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8759 inset_reg <<= I40E_32_BIT_WIDTH;
8760 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8762 /* Can not change the inset reg for flex payload for fdir,
8763 * it is done by writing I40E_PRTQF_FD_FLXINSET
8764 * in i40e_set_flex_mask_on_pctype.
8766 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8767 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8769 input_set |= pf->fdir.input_set[pctype];
8770 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8771 I40E_INSET_MASK_NUM_REG);
8775 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8777 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8778 (uint32_t)(inset_reg & UINT32_MAX));
8779 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8780 (uint32_t)((inset_reg >>
8781 I40E_32_BIT_WIDTH) & UINT32_MAX));
8783 for (i = 0; i < num; i++)
8784 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8786 /*clear unused mask registers of the pctype */
8787 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8788 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8790 I40E_WRITE_FLUSH(hw);
8792 pf->fdir.input_set[pctype] = input_set;
8797 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8802 PMD_DRV_LOG(ERR, "Invalid pointer");
8806 switch (info->info_type) {
8807 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8808 i40e_get_symmetric_hash_enable_per_port(hw,
8809 &(info->info.enable));
8811 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8812 ret = i40e_get_hash_filter_global_config(hw,
8813 &(info->info.global_conf));
8816 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8826 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8831 PMD_DRV_LOG(ERR, "Invalid pointer");
8835 switch (info->info_type) {
8836 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8837 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8839 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8840 ret = i40e_set_hash_filter_global_config(hw,
8841 &(info->info.global_conf));
8843 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8844 ret = i40e_hash_filter_inset_select(hw,
8845 &(info->info.input_set_conf));
8849 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8858 /* Operations for hash function */
8860 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8861 enum rte_filter_op filter_op,
8864 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8867 switch (filter_op) {
8868 case RTE_ETH_FILTER_NOP:
8870 case RTE_ETH_FILTER_GET:
8871 ret = i40e_hash_filter_get(hw,
8872 (struct rte_eth_hash_filter_info *)arg);
8874 case RTE_ETH_FILTER_SET:
8875 ret = i40e_hash_filter_set(hw,
8876 (struct rte_eth_hash_filter_info *)arg);
8879 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8888 /* Convert ethertype filter structure */
8890 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8891 struct i40e_ethertype_filter *filter)
8893 rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8894 filter->input.ether_type = input->ether_type;
8895 filter->flags = input->flags;
8896 filter->queue = input->queue;
8901 /* Check if there exists the ehtertype filter */
8902 struct i40e_ethertype_filter *
8903 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8904 const struct i40e_ethertype_filter_input *input)
8908 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8912 return ethertype_rule->hash_map[ret];
8915 /* Add ethertype filter in SW list */
8917 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8918 struct i40e_ethertype_filter *filter)
8920 struct i40e_ethertype_rule *rule = &pf->ethertype;
8923 ret = rte_hash_add_key(rule->hash_table, &filter->input);
8926 "Failed to insert ethertype filter"
8927 " to hash table %d!",
8931 rule->hash_map[ret] = filter;
8933 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8938 /* Delete ethertype filter in SW list */
8940 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8941 struct i40e_ethertype_filter_input *input)
8943 struct i40e_ethertype_rule *rule = &pf->ethertype;
8944 struct i40e_ethertype_filter *filter;
8947 ret = rte_hash_del_key(rule->hash_table, input);
8950 "Failed to delete ethertype filter"
8951 " to hash table %d!",
8955 filter = rule->hash_map[ret];
8956 rule->hash_map[ret] = NULL;
8958 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8965 * Configure ethertype filter, which can director packet by filtering
8966 * with mac address and ether_type or only ether_type
8969 i40e_ethertype_filter_set(struct i40e_pf *pf,
8970 struct rte_eth_ethertype_filter *filter,
8973 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8974 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
8975 struct i40e_ethertype_filter *ethertype_filter, *node;
8976 struct i40e_ethertype_filter check_filter;
8977 struct i40e_control_filter_stats stats;
8981 if (filter->queue >= pf->dev_data->nb_rx_queues) {
8982 PMD_DRV_LOG(ERR, "Invalid queue ID");
8985 if (filter->ether_type == ETHER_TYPE_IPv4 ||
8986 filter->ether_type == ETHER_TYPE_IPv6) {
8988 "unsupported ether_type(0x%04x) in control packet filter.",
8989 filter->ether_type);
8992 if (filter->ether_type == ETHER_TYPE_VLAN)
8993 PMD_DRV_LOG(WARNING,
8994 "filter vlan ether_type in first tag is not supported.");
8996 /* Check if there is the filter in SW list */
8997 memset(&check_filter, 0, sizeof(check_filter));
8998 i40e_ethertype_filter_convert(filter, &check_filter);
8999 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9000 &check_filter.input);
9002 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9006 if (!add && !node) {
9007 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9011 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9012 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9013 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9014 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9015 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9017 memset(&stats, 0, sizeof(stats));
9018 ret = i40e_aq_add_rem_control_packet_filter(hw,
9019 filter->mac_addr.addr_bytes,
9020 filter->ether_type, flags,
9022 filter->queue, add, &stats, NULL);
9025 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9026 ret, stats.mac_etype_used, stats.etype_used,
9027 stats.mac_etype_free, stats.etype_free);
9031 /* Add or delete a filter in SW list */
9033 ethertype_filter = rte_zmalloc("ethertype_filter",
9034 sizeof(*ethertype_filter), 0);
9035 rte_memcpy(ethertype_filter, &check_filter,
9036 sizeof(check_filter));
9037 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9039 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9046 * Handle operations for ethertype filter.
9049 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9050 enum rte_filter_op filter_op,
9053 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9056 if (filter_op == RTE_ETH_FILTER_NOP)
9060 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9065 switch (filter_op) {
9066 case RTE_ETH_FILTER_ADD:
9067 ret = i40e_ethertype_filter_set(pf,
9068 (struct rte_eth_ethertype_filter *)arg,
9071 case RTE_ETH_FILTER_DELETE:
9072 ret = i40e_ethertype_filter_set(pf,
9073 (struct rte_eth_ethertype_filter *)arg,
9077 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9085 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9086 enum rte_filter_type filter_type,
9087 enum rte_filter_op filter_op,
9095 switch (filter_type) {
9096 case RTE_ETH_FILTER_NONE:
9097 /* For global configuration */
9098 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9100 case RTE_ETH_FILTER_HASH:
9101 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9103 case RTE_ETH_FILTER_MACVLAN:
9104 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9106 case RTE_ETH_FILTER_ETHERTYPE:
9107 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9109 case RTE_ETH_FILTER_TUNNEL:
9110 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9112 case RTE_ETH_FILTER_FDIR:
9113 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9115 case RTE_ETH_FILTER_GENERIC:
9116 if (filter_op != RTE_ETH_FILTER_GET)
9118 *(const void **)arg = &i40e_flow_ops;
9121 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9131 * Check and enable Extended Tag.
9132 * Enabling Extended Tag is important for 40G performance.
9135 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9137 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9141 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9144 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9148 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9149 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9154 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9157 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9161 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9162 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9165 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9166 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9169 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9176 * As some registers wouldn't be reset unless a global hardware reset,
9177 * hardware initialization is needed to put those registers into an
9178 * expected initial state.
9181 i40e_hw_init(struct rte_eth_dev *dev)
9183 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9185 i40e_enable_extended_tag(dev);
9187 /* clear the PF Queue Filter control register */
9188 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9190 /* Disable symmetric hash per port */
9191 i40e_set_symmetric_hash_enable_per_port(hw, 0);
9194 enum i40e_filter_pctype
9195 i40e_flowtype_to_pctype(uint16_t flow_type)
9197 static const enum i40e_filter_pctype pctype_table[] = {
9198 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
9199 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
9200 I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
9201 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
9202 I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
9203 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
9204 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
9205 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
9206 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
9207 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
9208 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
9209 I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
9210 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
9211 I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
9212 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
9213 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
9214 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
9215 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
9216 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
9219 return pctype_table[flow_type];
9223 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
9225 static const uint16_t flowtype_table[] = {
9226 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
9227 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9228 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9229 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9230 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9231 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9232 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
9233 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9234 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9235 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9236 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
9237 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9238 RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
9239 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9240 RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
9241 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
9242 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9243 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9244 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9245 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9246 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9247 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
9248 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9249 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9250 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9251 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
9252 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9253 RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
9254 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9255 RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
9256 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
9259 return flowtype_table[pctype];
9263 * On X710, performance number is far from the expectation on recent firmware
9264 * versions; on XL710, performance number is also far from the expectation on
9265 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9266 * mode is enabled and port MAC address is equal to the packet destination MAC
9267 * address. The fix for this issue may not be integrated in the following
9268 * firmware version. So the workaround in software driver is needed. It needs
9269 * to modify the initial values of 3 internal only registers for both X710 and
9270 * XL710. Note that the values for X710 or XL710 could be different, and the
9271 * workaround can be removed when it is fixed in firmware in the future.
9274 /* For both X710 and XL710 */
9275 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1 0x10000200
9276 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x20000200
9277 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
9279 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9280 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
9283 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9284 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9287 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
9289 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
9290 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
9293 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9295 enum i40e_status_code status;
9296 struct i40e_aq_get_phy_abilities_resp phy_ab;
9300 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9304 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
9307 rte_delay_us(100000);
9309 status = i40e_aq_get_phy_capabilities(hw, false,
9310 true, &phy_ab, NULL);
9318 i40e_configure_registers(struct i40e_hw *hw)
9324 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9325 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9326 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9332 for (i = 0; i < RTE_DIM(reg_table); i++) {
9333 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9334 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9336 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9337 else /* For X710/XL710/XXV710 */
9338 if (hw->aq.fw_maj_ver < 6)
9340 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
9343 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
9346 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9347 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9349 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9350 else /* For X710/XL710/XXV710 */
9352 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9355 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9356 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9357 I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9359 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9362 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9365 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9368 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9372 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9373 reg_table[i].addr, reg);
9374 if (reg == reg_table[i].val)
9377 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9378 reg_table[i].val, NULL);
9381 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9382 reg_table[i].val, reg_table[i].addr);
9385 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9386 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9390 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
9391 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
9392 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
9393 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9395 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9400 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9401 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9405 /* Configure for double VLAN RX stripping */
9406 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9407 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9408 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9409 ret = i40e_aq_debug_write_register(hw,
9410 I40E_VSI_TSR(vsi->vsi_id),
9413 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9415 return I40E_ERR_CONFIG;
9419 /* Configure for double VLAN TX insertion */
9420 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9421 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9422 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9423 ret = i40e_aq_debug_write_register(hw,
9424 I40E_VSI_L2TAGSTXVALID(
9425 vsi->vsi_id), reg, NULL);
9428 "Failed to update VSI_L2TAGSTXVALID[%d]",
9430 return I40E_ERR_CONFIG;
9438 * i40e_aq_add_mirror_rule
9439 * @hw: pointer to the hardware structure
9440 * @seid: VEB seid to add mirror rule to
9441 * @dst_id: destination vsi seid
9442 * @entries: Buffer which contains the entities to be mirrored
9443 * @count: number of entities contained in the buffer
9444 * @rule_id:the rule_id of the rule to be added
9446 * Add a mirror rule for a given veb.
9449 static enum i40e_status_code
9450 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9451 uint16_t seid, uint16_t dst_id,
9452 uint16_t rule_type, uint16_t *entries,
9453 uint16_t count, uint16_t *rule_id)
9455 struct i40e_aq_desc desc;
9456 struct i40e_aqc_add_delete_mirror_rule cmd;
9457 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9458 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9461 enum i40e_status_code status;
9463 i40e_fill_default_direct_cmd_desc(&desc,
9464 i40e_aqc_opc_add_mirror_rule);
9465 memset(&cmd, 0, sizeof(cmd));
9467 buff_len = sizeof(uint16_t) * count;
9468 desc.datalen = rte_cpu_to_le_16(buff_len);
9470 desc.flags |= rte_cpu_to_le_16(
9471 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9472 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9473 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9474 cmd.num_entries = rte_cpu_to_le_16(count);
9475 cmd.seid = rte_cpu_to_le_16(seid);
9476 cmd.destination = rte_cpu_to_le_16(dst_id);
9478 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9479 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9481 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9482 hw->aq.asq_last_status, resp->rule_id,
9483 resp->mirror_rules_used, resp->mirror_rules_free);
9484 *rule_id = rte_le_to_cpu_16(resp->rule_id);
9490 * i40e_aq_del_mirror_rule
9491 * @hw: pointer to the hardware structure
9492 * @seid: VEB seid to add mirror rule to
9493 * @entries: Buffer which contains the entities to be mirrored
9494 * @count: number of entities contained in the buffer
9495 * @rule_id:the rule_id of the rule to be delete
9497 * Delete a mirror rule for a given veb.
9500 static enum i40e_status_code
9501 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9502 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9503 uint16_t count, uint16_t rule_id)
9505 struct i40e_aq_desc desc;
9506 struct i40e_aqc_add_delete_mirror_rule cmd;
9507 uint16_t buff_len = 0;
9508 enum i40e_status_code status;
9511 i40e_fill_default_direct_cmd_desc(&desc,
9512 i40e_aqc_opc_delete_mirror_rule);
9513 memset(&cmd, 0, sizeof(cmd));
9514 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9515 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9517 cmd.num_entries = count;
9518 buff_len = sizeof(uint16_t) * count;
9519 desc.datalen = rte_cpu_to_le_16(buff_len);
9520 buff = (void *)entries;
9522 /* rule id is filled in destination field for deleting mirror rule */
9523 cmd.destination = rte_cpu_to_le_16(rule_id);
9525 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9526 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9527 cmd.seid = rte_cpu_to_le_16(seid);
9529 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9530 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9536 * i40e_mirror_rule_set
9537 * @dev: pointer to the hardware structure
9538 * @mirror_conf: mirror rule info
9539 * @sw_id: mirror rule's sw_id
9540 * @on: enable/disable
9542 * set a mirror rule.
9546 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9547 struct rte_eth_mirror_conf *mirror_conf,
9548 uint8_t sw_id, uint8_t on)
9550 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9551 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9552 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9553 struct i40e_mirror_rule *parent = NULL;
9554 uint16_t seid, dst_seid, rule_id;
9558 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9560 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9562 "mirror rule can not be configured without veb or vfs.");
9565 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9566 PMD_DRV_LOG(ERR, "mirror table is full.");
9569 if (mirror_conf->dst_pool > pf->vf_num) {
9570 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9571 mirror_conf->dst_pool);
9575 seid = pf->main_vsi->veb->seid;
9577 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9578 if (sw_id <= it->index) {
9584 if (mirr_rule && sw_id == mirr_rule->index) {
9586 PMD_DRV_LOG(ERR, "mirror rule exists.");
9589 ret = i40e_aq_del_mirror_rule(hw, seid,
9590 mirr_rule->rule_type,
9592 mirr_rule->num_entries, mirr_rule->id);
9595 "failed to remove mirror rule: ret = %d, aq_err = %d.",
9596 ret, hw->aq.asq_last_status);
9599 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9600 rte_free(mirr_rule);
9601 pf->nb_mirror_rule--;
9605 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9609 mirr_rule = rte_zmalloc("i40e_mirror_rule",
9610 sizeof(struct i40e_mirror_rule) , 0);
9612 PMD_DRV_LOG(ERR, "failed to allocate memory");
9613 return I40E_ERR_NO_MEMORY;
9615 switch (mirror_conf->rule_type) {
9616 case ETH_MIRROR_VLAN:
9617 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9618 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9619 mirr_rule->entries[j] =
9620 mirror_conf->vlan.vlan_id[i];
9625 PMD_DRV_LOG(ERR, "vlan is not specified.");
9626 rte_free(mirr_rule);
9629 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9631 case ETH_MIRROR_VIRTUAL_POOL_UP:
9632 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9633 /* check if the specified pool bit is out of range */
9634 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9635 PMD_DRV_LOG(ERR, "pool mask is out of range.");
9636 rte_free(mirr_rule);
9639 for (i = 0, j = 0; i < pf->vf_num; i++) {
9640 if (mirror_conf->pool_mask & (1ULL << i)) {
9641 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9645 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9646 /* add pf vsi to entries */
9647 mirr_rule->entries[j] = pf->main_vsi_seid;
9651 PMD_DRV_LOG(ERR, "pool is not specified.");
9652 rte_free(mirr_rule);
9655 /* egress and ingress in aq commands means from switch but not port */
9656 mirr_rule->rule_type =
9657 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9658 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9659 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9661 case ETH_MIRROR_UPLINK_PORT:
9662 /* egress and ingress in aq commands means from switch but not port*/
9663 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9665 case ETH_MIRROR_DOWNLINK_PORT:
9666 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9669 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9670 mirror_conf->rule_type);
9671 rte_free(mirr_rule);
9675 /* If the dst_pool is equal to vf_num, consider it as PF */
9676 if (mirror_conf->dst_pool == pf->vf_num)
9677 dst_seid = pf->main_vsi_seid;
9679 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9681 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9682 mirr_rule->rule_type, mirr_rule->entries,
9686 "failed to add mirror rule: ret = %d, aq_err = %d.",
9687 ret, hw->aq.asq_last_status);
9688 rte_free(mirr_rule);
9692 mirr_rule->index = sw_id;
9693 mirr_rule->num_entries = j;
9694 mirr_rule->id = rule_id;
9695 mirr_rule->dst_vsi_seid = dst_seid;
9698 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9700 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9702 pf->nb_mirror_rule++;
9707 * i40e_mirror_rule_reset
9708 * @dev: pointer to the device
9709 * @sw_id: mirror rule's sw_id
9711 * reset a mirror rule.
9715 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9717 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9718 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9719 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9723 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9725 seid = pf->main_vsi->veb->seid;
9727 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9728 if (sw_id == it->index) {
9734 ret = i40e_aq_del_mirror_rule(hw, seid,
9735 mirr_rule->rule_type,
9737 mirr_rule->num_entries, mirr_rule->id);
9740 "failed to remove mirror rule: status = %d, aq_err = %d.",
9741 ret, hw->aq.asq_last_status);
9744 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9745 rte_free(mirr_rule);
9746 pf->nb_mirror_rule--;
9748 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9755 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9757 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9758 uint64_t systim_cycles;
9760 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9761 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9764 return systim_cycles;
9768 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9770 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9773 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9774 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9781 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9783 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9786 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9787 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9794 i40e_start_timecounters(struct rte_eth_dev *dev)
9796 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9797 struct i40e_adapter *adapter =
9798 (struct i40e_adapter *)dev->data->dev_private;
9799 struct rte_eth_link link;
9800 uint32_t tsync_inc_l;
9801 uint32_t tsync_inc_h;
9803 /* Get current link speed. */
9804 memset(&link, 0, sizeof(link));
9805 i40e_dev_link_update(dev, 1);
9806 rte_i40e_dev_atomic_read_link_status(dev, &link);
9808 switch (link.link_speed) {
9809 case ETH_SPEED_NUM_40G:
9810 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9811 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9813 case ETH_SPEED_NUM_10G:
9814 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9815 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9817 case ETH_SPEED_NUM_1G:
9818 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9819 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9826 /* Set the timesync increment value. */
9827 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9828 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9830 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9831 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9832 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9834 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9835 adapter->systime_tc.cc_shift = 0;
9836 adapter->systime_tc.nsec_mask = 0;
9838 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9839 adapter->rx_tstamp_tc.cc_shift = 0;
9840 adapter->rx_tstamp_tc.nsec_mask = 0;
9842 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9843 adapter->tx_tstamp_tc.cc_shift = 0;
9844 adapter->tx_tstamp_tc.nsec_mask = 0;
9848 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9850 struct i40e_adapter *adapter =
9851 (struct i40e_adapter *)dev->data->dev_private;
9853 adapter->systime_tc.nsec += delta;
9854 adapter->rx_tstamp_tc.nsec += delta;
9855 adapter->tx_tstamp_tc.nsec += delta;
9861 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9864 struct i40e_adapter *adapter =
9865 (struct i40e_adapter *)dev->data->dev_private;
9867 ns = rte_timespec_to_ns(ts);
9869 /* Set the timecounters to a new value. */
9870 adapter->systime_tc.nsec = ns;
9871 adapter->rx_tstamp_tc.nsec = ns;
9872 adapter->tx_tstamp_tc.nsec = ns;
9878 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9880 uint64_t ns, systime_cycles;
9881 struct i40e_adapter *adapter =
9882 (struct i40e_adapter *)dev->data->dev_private;
9884 systime_cycles = i40e_read_systime_cyclecounter(dev);
9885 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9886 *ts = rte_ns_to_timespec(ns);
9892 i40e_timesync_enable(struct rte_eth_dev *dev)
9894 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9895 uint32_t tsync_ctl_l;
9896 uint32_t tsync_ctl_h;
9898 /* Stop the timesync system time. */
9899 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9900 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9901 /* Reset the timesync system time value. */
9902 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9903 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9905 i40e_start_timecounters(dev);
9907 /* Clear timesync registers. */
9908 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9909 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9910 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9911 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9912 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9913 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9915 /* Enable timestamping of PTP packets. */
9916 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9917 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9919 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9920 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9921 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9923 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9924 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9930 i40e_timesync_disable(struct rte_eth_dev *dev)
9932 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9933 uint32_t tsync_ctl_l;
9934 uint32_t tsync_ctl_h;
9936 /* Disable timestamping of transmitted PTP packets. */
9937 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9938 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9940 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9941 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9943 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9944 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9946 /* Reset the timesync increment value. */
9947 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9948 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9954 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9955 struct timespec *timestamp, uint32_t flags)
9957 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9958 struct i40e_adapter *adapter =
9959 (struct i40e_adapter *)dev->data->dev_private;
9961 uint32_t sync_status;
9962 uint32_t index = flags & 0x03;
9963 uint64_t rx_tstamp_cycles;
9966 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9967 if ((sync_status & (1 << index)) == 0)
9970 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9971 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9972 *timestamp = rte_ns_to_timespec(ns);
9978 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9979 struct timespec *timestamp)
9981 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9982 struct i40e_adapter *adapter =
9983 (struct i40e_adapter *)dev->data->dev_private;
9985 uint32_t sync_status;
9986 uint64_t tx_tstamp_cycles;
9989 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9990 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9993 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9994 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9995 *timestamp = rte_ns_to_timespec(ns);
10001 * i40e_parse_dcb_configure - parse dcb configure from user
10002 * @dev: the device being configured
10003 * @dcb_cfg: pointer of the result of parse
10004 * @*tc_map: bit map of enabled traffic classes
10006 * Returns 0 on success, negative value on failure
10009 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10010 struct i40e_dcbx_config *dcb_cfg,
10013 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10014 uint8_t i, tc_bw, bw_lf;
10016 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10018 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10019 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10020 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10024 /* assume each tc has the same bw */
10025 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10026 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10027 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10028 /* to ensure the sum of tcbw is equal to 100 */
10029 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10030 for (i = 0; i < bw_lf; i++)
10031 dcb_cfg->etscfg.tcbwtable[i]++;
10033 /* assume each tc has the same Transmission Selection Algorithm */
10034 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10035 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10037 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10038 dcb_cfg->etscfg.prioritytable[i] =
10039 dcb_rx_conf->dcb_tc[i];
10041 /* FW needs one App to configure HW */
10042 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10043 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10044 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10045 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10047 if (dcb_rx_conf->nb_tcs == 0)
10048 *tc_map = 1; /* tc0 only */
10050 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10052 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10053 dcb_cfg->pfc.willing = 0;
10054 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10055 dcb_cfg->pfc.pfcenable = *tc_map;
10061 static enum i40e_status_code
10062 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10063 struct i40e_aqc_vsi_properties_data *info,
10064 uint8_t enabled_tcmap)
10066 enum i40e_status_code ret;
10067 int i, total_tc = 0;
10068 uint16_t qpnum_per_tc, bsf, qp_idx;
10069 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10070 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10071 uint16_t used_queues;
10073 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10074 if (ret != I40E_SUCCESS)
10077 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10078 if (enabled_tcmap & (1 << i))
10083 vsi->enabled_tc = enabled_tcmap;
10085 /* different VSI has different queues assigned */
10086 if (vsi->type == I40E_VSI_MAIN)
10087 used_queues = dev_data->nb_rx_queues -
10088 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10089 else if (vsi->type == I40E_VSI_VMDQ2)
10090 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10092 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10093 return I40E_ERR_NO_AVAILABLE_VSI;
10096 qpnum_per_tc = used_queues / total_tc;
10097 /* Number of queues per enabled TC */
10098 if (qpnum_per_tc == 0) {
10099 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10100 return I40E_ERR_INVALID_QP_ID;
10102 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10103 I40E_MAX_Q_PER_TC);
10104 bsf = rte_bsf32(qpnum_per_tc);
10107 * Configure TC and queue mapping parameters, for enabled TC,
10108 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10109 * default queue will serve it.
10112 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10113 if (vsi->enabled_tc & (1 << i)) {
10114 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10115 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10116 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10117 qp_idx += qpnum_per_tc;
10119 info->tc_mapping[i] = 0;
10122 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10123 if (vsi->type == I40E_VSI_SRIOV) {
10124 info->mapping_flags |=
10125 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10126 for (i = 0; i < vsi->nb_qps; i++)
10127 info->queue_mapping[i] =
10128 rte_cpu_to_le_16(vsi->base_queue + i);
10130 info->mapping_flags |=
10131 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10132 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10134 info->valid_sections |=
10135 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10137 return I40E_SUCCESS;
10141 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10142 * @veb: VEB to be configured
10143 * @tc_map: enabled TC bitmap
10145 * Returns 0 on success, negative value on failure
10147 static enum i40e_status_code
10148 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10150 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10151 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10152 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10153 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10154 enum i40e_status_code ret = I40E_SUCCESS;
10158 /* Check if enabled_tc is same as existing or new TCs */
10159 if (veb->enabled_tc == tc_map)
10162 /* configure tc bandwidth */
10163 memset(&veb_bw, 0, sizeof(veb_bw));
10164 veb_bw.tc_valid_bits = tc_map;
10165 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10166 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10167 if (tc_map & BIT_ULL(i))
10168 veb_bw.tc_bw_share_credits[i] = 1;
10170 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10174 "AQ command Config switch_comp BW allocation per TC failed = %d",
10175 hw->aq.asq_last_status);
10179 memset(&ets_query, 0, sizeof(ets_query));
10180 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10182 if (ret != I40E_SUCCESS) {
10184 "Failed to get switch_comp ETS configuration %u",
10185 hw->aq.asq_last_status);
10188 memset(&bw_query, 0, sizeof(bw_query));
10189 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10191 if (ret != I40E_SUCCESS) {
10193 "Failed to get switch_comp bandwidth configuration %u",
10194 hw->aq.asq_last_status);
10198 /* store and print out BW info */
10199 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10200 veb->bw_info.bw_max = ets_query.tc_bw_max;
10201 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10202 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10203 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10204 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10205 I40E_16_BIT_WIDTH);
10206 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10207 veb->bw_info.bw_ets_share_credits[i] =
10208 bw_query.tc_bw_share_credits[i];
10209 veb->bw_info.bw_ets_credits[i] =
10210 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10211 /* 4 bits per TC, 4th bit is reserved */
10212 veb->bw_info.bw_ets_max[i] =
10213 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10214 RTE_LEN2MASK(3, uint8_t));
10215 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10216 veb->bw_info.bw_ets_share_credits[i]);
10217 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10218 veb->bw_info.bw_ets_credits[i]);
10219 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10220 veb->bw_info.bw_ets_max[i]);
10223 veb->enabled_tc = tc_map;
10230 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10231 * @vsi: VSI to be configured
10232 * @tc_map: enabled TC bitmap
10234 * Returns 0 on success, negative value on failure
10236 static enum i40e_status_code
10237 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10239 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10240 struct i40e_vsi_context ctxt;
10241 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10242 enum i40e_status_code ret = I40E_SUCCESS;
10245 /* Check if enabled_tc is same as existing or new TCs */
10246 if (vsi->enabled_tc == tc_map)
10249 /* configure tc bandwidth */
10250 memset(&bw_data, 0, sizeof(bw_data));
10251 bw_data.tc_valid_bits = tc_map;
10252 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10253 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10254 if (tc_map & BIT_ULL(i))
10255 bw_data.tc_bw_credits[i] = 1;
10257 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10260 "AQ command Config VSI BW allocation per TC failed = %d",
10261 hw->aq.asq_last_status);
10264 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10265 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10267 /* Update Queue Pairs Mapping for currently enabled UPs */
10268 ctxt.seid = vsi->seid;
10269 ctxt.pf_num = hw->pf_id;
10271 ctxt.uplink_seid = vsi->uplink_seid;
10272 ctxt.info = vsi->info;
10274 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10278 /* Update the VSI after updating the VSI queue-mapping information */
10279 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10281 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10282 hw->aq.asq_last_status);
10285 /* update the local VSI info with updated queue map */
10286 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10287 sizeof(vsi->info.tc_mapping));
10288 (void)rte_memcpy(&vsi->info.queue_mapping,
10289 &ctxt.info.queue_mapping,
10290 sizeof(vsi->info.queue_mapping));
10291 vsi->info.mapping_flags = ctxt.info.mapping_flags;
10292 vsi->info.valid_sections = 0;
10294 /* query and update current VSI BW information */
10295 ret = i40e_vsi_get_bw_config(vsi);
10298 "Failed updating vsi bw info, err %s aq_err %s",
10299 i40e_stat_str(hw, ret),
10300 i40e_aq_str(hw, hw->aq.asq_last_status));
10304 vsi->enabled_tc = tc_map;
10311 * i40e_dcb_hw_configure - program the dcb setting to hw
10312 * @pf: pf the configuration is taken on
10313 * @new_cfg: new configuration
10314 * @tc_map: enabled TC bitmap
10316 * Returns 0 on success, negative value on failure
10318 static enum i40e_status_code
10319 i40e_dcb_hw_configure(struct i40e_pf *pf,
10320 struct i40e_dcbx_config *new_cfg,
10323 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10324 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10325 struct i40e_vsi *main_vsi = pf->main_vsi;
10326 struct i40e_vsi_list *vsi_list;
10327 enum i40e_status_code ret;
10331 /* Use the FW API if FW > v4.4*/
10332 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10333 (hw->aq.fw_maj_ver >= 5))) {
10335 "FW < v4.4, can not use FW LLDP API to configure DCB");
10336 return I40E_ERR_FIRMWARE_API_VERSION;
10339 /* Check if need reconfiguration */
10340 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10341 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10342 return I40E_SUCCESS;
10345 /* Copy the new config to the current config */
10346 *old_cfg = *new_cfg;
10347 old_cfg->etsrec = old_cfg->etscfg;
10348 ret = i40e_set_dcb_config(hw);
10350 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10351 i40e_stat_str(hw, ret),
10352 i40e_aq_str(hw, hw->aq.asq_last_status));
10355 /* set receive Arbiter to RR mode and ETS scheme by default */
10356 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10357 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10358 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
10359 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10360 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10361 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10362 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10363 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10364 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10365 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10366 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10367 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10368 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10370 /* get local mib to check whether it is configured correctly */
10372 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10373 /* Get Local DCB Config */
10374 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10375 &hw->local_dcbx_config);
10377 /* if Veb is created, need to update TC of it at first */
10378 if (main_vsi->veb) {
10379 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10381 PMD_INIT_LOG(WARNING,
10382 "Failed configuring TC for VEB seid=%d",
10383 main_vsi->veb->seid);
10385 /* Update each VSI */
10386 i40e_vsi_config_tc(main_vsi, tc_map);
10387 if (main_vsi->veb) {
10388 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10389 /* Beside main VSI and VMDQ VSIs, only enable default
10390 * TC for other VSIs
10392 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10393 ret = i40e_vsi_config_tc(vsi_list->vsi,
10396 ret = i40e_vsi_config_tc(vsi_list->vsi,
10397 I40E_DEFAULT_TCMAP);
10399 PMD_INIT_LOG(WARNING,
10400 "Failed configuring TC for VSI seid=%d",
10401 vsi_list->vsi->seid);
10405 return I40E_SUCCESS;
10409 * i40e_dcb_init_configure - initial dcb config
10410 * @dev: device being configured
10411 * @sw_dcb: indicate whether dcb is sw configured or hw offload
10413 * Returns 0 on success, negative value on failure
10416 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10418 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10419 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10422 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10423 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10427 /* DCB initialization:
10428 * Update DCB configuration from the Firmware and configure
10429 * LLDP MIB change event.
10431 if (sw_dcb == TRUE) {
10432 ret = i40e_init_dcb(hw);
10433 /* If lldp agent is stopped, the return value from
10434 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10435 * adminq status. Otherwise, it should return success.
10437 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10438 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10439 memset(&hw->local_dcbx_config, 0,
10440 sizeof(struct i40e_dcbx_config));
10441 /* set dcb default configuration */
10442 hw->local_dcbx_config.etscfg.willing = 0;
10443 hw->local_dcbx_config.etscfg.maxtcs = 0;
10444 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10445 hw->local_dcbx_config.etscfg.tsatable[0] =
10447 /* all UPs mapping to TC0 */
10448 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10449 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10450 hw->local_dcbx_config.etsrec =
10451 hw->local_dcbx_config.etscfg;
10452 hw->local_dcbx_config.pfc.willing = 0;
10453 hw->local_dcbx_config.pfc.pfccap =
10454 I40E_MAX_TRAFFIC_CLASS;
10455 /* FW needs one App to configure HW */
10456 hw->local_dcbx_config.numapps = 1;
10457 hw->local_dcbx_config.app[0].selector =
10458 I40E_APP_SEL_ETHTYPE;
10459 hw->local_dcbx_config.app[0].priority = 3;
10460 hw->local_dcbx_config.app[0].protocolid =
10461 I40E_APP_PROTOID_FCOE;
10462 ret = i40e_set_dcb_config(hw);
10465 "default dcb config fails. err = %d, aq_err = %d.",
10466 ret, hw->aq.asq_last_status);
10471 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10472 ret, hw->aq.asq_last_status);
10476 ret = i40e_aq_start_lldp(hw, NULL);
10477 if (ret != I40E_SUCCESS)
10478 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10480 ret = i40e_init_dcb(hw);
10482 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10484 "HW doesn't support DCBX offload.");
10489 "DCBX configuration failed, err = %d, aq_err = %d.",
10490 ret, hw->aq.asq_last_status);
10498 * i40e_dcb_setup - setup dcb related config
10499 * @dev: device being configured
10501 * Returns 0 on success, negative value on failure
10504 i40e_dcb_setup(struct rte_eth_dev *dev)
10506 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10507 struct i40e_dcbx_config dcb_cfg;
10508 uint8_t tc_map = 0;
10511 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10512 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10516 if (pf->vf_num != 0)
10517 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10519 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10521 PMD_INIT_LOG(ERR, "invalid dcb config");
10524 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10526 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10534 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10535 struct rte_eth_dcb_info *dcb_info)
10537 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10538 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10539 struct i40e_vsi *vsi = pf->main_vsi;
10540 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10541 uint16_t bsf, tc_mapping;
10544 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10545 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10547 dcb_info->nb_tcs = 1;
10548 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10549 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10550 for (i = 0; i < dcb_info->nb_tcs; i++)
10551 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10553 /* get queue mapping if vmdq is disabled */
10554 if (!pf->nb_cfg_vmdq_vsi) {
10555 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10556 if (!(vsi->enabled_tc & (1 << i)))
10558 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10559 dcb_info->tc_queue.tc_rxq[j][i].base =
10560 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10561 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10562 dcb_info->tc_queue.tc_txq[j][i].base =
10563 dcb_info->tc_queue.tc_rxq[j][i].base;
10564 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10565 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10566 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10567 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10568 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10573 /* get queue mapping if vmdq is enabled */
10575 vsi = pf->vmdq[j].vsi;
10576 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10577 if (!(vsi->enabled_tc & (1 << i)))
10579 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10580 dcb_info->tc_queue.tc_rxq[j][i].base =
10581 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10582 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10583 dcb_info->tc_queue.tc_txq[j][i].base =
10584 dcb_info->tc_queue.tc_rxq[j][i].base;
10585 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10586 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10587 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10588 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10589 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10592 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10597 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10599 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10600 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10601 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10602 uint16_t interval =
10603 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10604 uint16_t msix_intr;
10606 msix_intr = intr_handle->intr_vec[queue_id];
10607 if (msix_intr == I40E_MISC_VEC_ID)
10608 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10609 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10610 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10611 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10613 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10616 I40E_PFINT_DYN_CTLN(msix_intr -
10617 I40E_RX_VEC_START),
10618 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10619 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10620 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10622 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10624 I40E_WRITE_FLUSH(hw);
10625 rte_intr_enable(&pci_dev->intr_handle);
10631 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10633 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10634 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10635 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10636 uint16_t msix_intr;
10638 msix_intr = intr_handle->intr_vec[queue_id];
10639 if (msix_intr == I40E_MISC_VEC_ID)
10640 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10643 I40E_PFINT_DYN_CTLN(msix_intr -
10644 I40E_RX_VEC_START),
10646 I40E_WRITE_FLUSH(hw);
10651 static int i40e_get_regs(struct rte_eth_dev *dev,
10652 struct rte_dev_reg_info *regs)
10654 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10655 uint32_t *ptr_data = regs->data;
10656 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10657 const struct i40e_reg_info *reg_info;
10659 if (ptr_data == NULL) {
10660 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10661 regs->width = sizeof(uint32_t);
10665 /* The first few registers have to be read using AQ operations */
10667 while (i40e_regs_adminq[reg_idx].name) {
10668 reg_info = &i40e_regs_adminq[reg_idx++];
10669 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10671 arr_idx2 <= reg_info->count2;
10673 reg_offset = arr_idx * reg_info->stride1 +
10674 arr_idx2 * reg_info->stride2;
10675 reg_offset += reg_info->base_addr;
10676 ptr_data[reg_offset >> 2] =
10677 i40e_read_rx_ctl(hw, reg_offset);
10681 /* The remaining registers can be read using primitives */
10683 while (i40e_regs_others[reg_idx].name) {
10684 reg_info = &i40e_regs_others[reg_idx++];
10685 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10687 arr_idx2 <= reg_info->count2;
10689 reg_offset = arr_idx * reg_info->stride1 +
10690 arr_idx2 * reg_info->stride2;
10691 reg_offset += reg_info->base_addr;
10692 ptr_data[reg_offset >> 2] =
10693 I40E_READ_REG(hw, reg_offset);
10700 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10702 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10704 /* Convert word count to byte count */
10705 return hw->nvm.sr_size << 1;
10708 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10709 struct rte_dev_eeprom_info *eeprom)
10711 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10712 uint16_t *data = eeprom->data;
10713 uint16_t offset, length, cnt_words;
10716 offset = eeprom->offset >> 1;
10717 length = eeprom->length >> 1;
10718 cnt_words = length;
10720 if (offset > hw->nvm.sr_size ||
10721 offset + length > hw->nvm.sr_size) {
10722 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10726 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10728 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10729 if (ret_code != I40E_SUCCESS || cnt_words != length) {
10730 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10737 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10738 struct ether_addr *mac_addr)
10740 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10742 if (!is_valid_assigned_ether_addr(mac_addr)) {
10743 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10747 /* Flags: 0x3 updates port address */
10748 i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10752 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10754 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10755 struct rte_eth_dev_data *dev_data = pf->dev_data;
10756 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
10759 /* check if mtu is within the allowed range */
10760 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10763 /* mtu setting is forbidden if port is start */
10764 if (dev_data->dev_started) {
10765 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10766 dev_data->port_id);
10770 if (frame_size > ETHER_MAX_LEN)
10771 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10773 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10775 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10780 /* Restore ethertype filter */
10782 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10784 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10785 struct i40e_ethertype_filter_list
10786 *ethertype_list = &pf->ethertype.ethertype_list;
10787 struct i40e_ethertype_filter *f;
10788 struct i40e_control_filter_stats stats;
10791 TAILQ_FOREACH(f, ethertype_list, rules) {
10793 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10794 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10795 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10796 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10797 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10799 memset(&stats, 0, sizeof(stats));
10800 i40e_aq_add_rem_control_packet_filter(hw,
10801 f->input.mac_addr.addr_bytes,
10802 f->input.ether_type,
10803 flags, pf->main_vsi->seid,
10804 f->queue, 1, &stats, NULL);
10806 PMD_DRV_LOG(INFO, "Ethertype filter:"
10807 " mac_etype_used = %u, etype_used = %u,"
10808 " mac_etype_free = %u, etype_free = %u",
10809 stats.mac_etype_used, stats.etype_used,
10810 stats.mac_etype_free, stats.etype_free);
10813 /* Restore tunnel filter */
10815 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10817 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10818 struct i40e_vsi *vsi;
10819 struct i40e_pf_vf *vf;
10820 struct i40e_tunnel_filter_list
10821 *tunnel_list = &pf->tunnel.tunnel_list;
10822 struct i40e_tunnel_filter *f;
10823 struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
10824 bool big_buffer = 0;
10826 TAILQ_FOREACH(f, tunnel_list, rules) {
10828 vsi = pf->main_vsi;
10830 vf = &pf->vfs[f->vf_id];
10833 memset(&cld_filter, 0, sizeof(cld_filter));
10834 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
10835 (struct ether_addr *)&cld_filter.element.outer_mac);
10836 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
10837 (struct ether_addr *)&cld_filter.element.inner_mac);
10838 cld_filter.element.inner_vlan = f->input.inner_vlan;
10839 cld_filter.element.flags = f->input.flags;
10840 cld_filter.element.tenant_id = f->input.tenant_id;
10841 cld_filter.element.queue_number = f->queue;
10842 rte_memcpy(cld_filter.general_fields,
10843 f->input.general_fields,
10844 sizeof(f->input.general_fields));
10846 if (((f->input.flags &
10847 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ==
10848 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoUDP) ||
10850 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ==
10851 I40E_AQC_ADD_CLOUD_FILTER_TEID_MPLSoGRE) ||
10853 I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ) ==
10854 I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ))
10858 i40e_aq_add_cloud_filters_big_buffer(hw,
10859 vsi->seid, &cld_filter, 1);
10861 i40e_aq_add_cloud_filters(hw, vsi->seid,
10862 &cld_filter.element, 1);
10867 i40e_filter_restore(struct i40e_pf *pf)
10869 i40e_ethertype_filter_restore(pf);
10870 i40e_tunnel_filter_restore(pf);
10871 i40e_fdir_filter_restore(pf);
10875 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
10877 if (strcmp(dev->device->driver->name, drv->driver.name))
10884 is_i40e_supported(struct rte_eth_dev *dev)
10886 return is_device_supported(dev, &rte_i40e_pmd);
10889 /* Create a QinQ cloud filter
10891 * The Fortville NIC has limited resources for tunnel filters,
10892 * so we can only reuse existing filters.
10894 * In step 1 we define which Field Vector fields can be used for
10896 * As we do not have the inner tag defined as a field,
10897 * we have to define it first, by reusing one of L1 entries.
10899 * In step 2 we are replacing one of existing filter types with
10900 * a new one for QinQ.
10901 * As we reusing L1 and replacing L2, some of the default filter
10902 * types will disappear,which depends on L1 and L2 entries we reuse.
10904 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
10906 * 1. Create L1 filter of outer vlan (12b) which will be in use
10907 * later when we define the cloud filter.
10908 * a. Valid_flags.replace_cloud = 0
10909 * b. Old_filter = 10 (Stag_Inner_Vlan)
10910 * c. New_filter = 0x10
10911 * d. TR bit = 0xff (optional, not used here)
10912 * e. Buffer – 2 entries:
10913 * i. Byte 0 = 8 (outer vlan FV index).
10915 * Byte 2-3 = 0x0fff
10916 * ii. Byte 0 = 37 (inner vlan FV index).
10918 * Byte 2-3 = 0x0fff
10921 * 2. Create cloud filter using two L1 filters entries: stag and
10922 * new filter(outer vlan+ inner vlan)
10923 * a. Valid_flags.replace_cloud = 1
10924 * b. Old_filter = 1 (instead of outer IP)
10925 * c. New_filter = 0x10
10926 * d. Buffer – 2 entries:
10927 * i. Byte 0 = 0x80 | 7 (valid | Stag).
10928 * Byte 1-3 = 0 (rsv)
10929 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
10930 * Byte 9-11 = 0 (rsv)
10933 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
10935 int ret = -ENOTSUP;
10936 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
10937 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
10938 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10941 memset(&filter_replace, 0,
10942 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
10943 memset(&filter_replace_buf, 0,
10944 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
10946 /* create L1 filter */
10947 filter_replace.old_filter_type =
10948 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
10949 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10950 filter_replace.tr_bit = 0;
10952 /* Prepare the buffer, 2 entries */
10953 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
10954 filter_replace_buf.data[0] |=
10955 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10956 /* Field Vector 12b mask */
10957 filter_replace_buf.data[2] = 0xff;
10958 filter_replace_buf.data[3] = 0x0f;
10959 filter_replace_buf.data[4] =
10960 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
10961 filter_replace_buf.data[4] |=
10962 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10963 /* Field Vector 12b mask */
10964 filter_replace_buf.data[6] = 0xff;
10965 filter_replace_buf.data[7] = 0x0f;
10966 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
10967 &filter_replace_buf);
10968 if (ret != I40E_SUCCESS)
10971 /* Apply the second L2 cloud filter */
10972 memset(&filter_replace, 0,
10973 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
10974 memset(&filter_replace_buf, 0,
10975 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
10977 /* create L2 filter, input for L2 filter will be L1 filter */
10978 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
10979 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
10980 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10982 /* Prepare the buffer, 2 entries */
10983 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
10984 filter_replace_buf.data[0] |=
10985 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10986 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_CUSTOM_QINQ;
10987 filter_replace_buf.data[4] |=
10988 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
10989 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
10990 &filter_replace_buf);
10994 RTE_INIT(i40e_init_log);
10996 i40e_init_log(void)
10998 i40e_logtype_init = rte_log_register("pmd.i40e.init");
10999 if (i40e_logtype_init >= 0)
11000 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
11001 i40e_logtype_driver = rte_log_register("pmd.i40e.driver");
11002 if (i40e_logtype_driver >= 0)
11003 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);