drivers/net/i40e/i40e_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10 #include <stdarg.h>
  11 #include <inttypes.h>
  12 #include <assert.h>
  13
  14 #include <rte_common.h>
  15 #include <rte_eal.h>
  16 #include <rte_string_fns.h>
  17 #include <rte_pci.h>
  18 #include <rte_bus_pci.h>
  19 #include <rte_ether.h>
  20 #include <ethdev_driver.h>
  21 #include <ethdev_pci.h>
  22 #include <rte_memzone.h>
  23 #include <rte_malloc.h>
  24 #include <rte_memcpy.h>
  25 #include <rte_alarm.h>
  26 #include <rte_dev.h>
  27 #include <rte_tailq.h>
  28 #include <rte_hash_crc.h>
  29 #include <rte_bitmap.h>
  30 #include <rte_os_shim.h>
  31
  32 #include "i40e_logs.h"
  33 #include "base/i40e_prototype.h"
  34 #include "base/i40e_adminq_cmd.h"
  35 #include "base/i40e_type.h"
  36 #include "base/i40e_register.h"
  37 #include "base/i40e_dcb.h"
  38 #include "i40e_ethdev.h"
  39 #include "i40e_rxtx.h"
  40 #include "i40e_pf.h"
  41 #include "i40e_regs.h"
  42 #include "rte_pmd_i40e.h"
  43 #include "i40e_hash.h"
  44
  45 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  46 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  47 #define ETH_I40E_SUPPORT_MULTI_DRIVER   "support-multi-driver"
  48 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG   "queue-num-per-vf"
  49 #define ETH_I40E_VF_MSG_CFG             "vf_msg_cfg"
  50
  51 #define I40E_CLEAR_PXE_WAIT_MS     200
  52 #define I40E_VSI_TSR_QINQ_STRIP         0x4010
  53 #define I40E_VSI_TSR(_i)        (0x00050800 + ((_i) * 4))
  54
  55 /* Maximun number of capability elements */
  56 #define I40E_MAX_CAP_ELE_NUM       128
  57
  58 /* Wait count and interval */
  59 #define I40E_CHK_Q_ENA_COUNT       1000
  60 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  61
  62 /* Maximun number of VSI */
  63 #define I40E_MAX_NUM_VSIS          (384UL)
  64
  65 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  66
  67 /* Flow control default timer */
  68 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  69
  70 /* Flow control enable fwd bit */
  71 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  72
  73 /* Receive Packet Buffer size */
  74 #define I40E_RXPBSIZE (968 * 1024)
  75
  76 /* Kilobytes shift */
  77 #define I40E_KILOSHIFT 10
  78
  79 /* Flow control default high water */
  80 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
  81
  82 /* Flow control default low water */
  83 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
  84
  85 /* Receive Average Packet Size in Byte*/
  86 #define I40E_PACKET_AVERAGE_SIZE 128
  87
  88 /* Mask of PF interrupt causes */
  89 #define I40E_PFINT_ICR0_ENA_MASK ( \
  90                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  91                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  92                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  93                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  94                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  95                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  96                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  97                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  98                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  99
 100 #define I40E_FLOW_TYPES ( \
 101         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 102         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 103         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 104         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 105         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 106         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 107         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 108         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 109         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 110         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 111         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 112
 113 /* Additional timesync values. */
 114 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 115 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 116 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 117 #define I40E_PRTTSYN_TSYNENA     0x80000000
 118 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 119 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 120
 121 /**
 122  * Below are values for writing un-exposed registers suggested
 123  * by silicon experts
 124  */
 125 /* Destination MAC address */
 126 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 127 /* Source MAC address */
 128 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 129 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 130 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 131 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 132 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 133 /* Single VLAN tag in the inner L2 header */
 134 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 135 /* Source IPv4 address */
 136 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 137 /* Destination IPv4 address */
 138 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 139 /* Source IPv4 address for X722 */
 140 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 141 /* Destination IPv4 address for X722 */
 142 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 143 /* IPv4 Protocol for X722 */
 144 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 145 /* IPv4 Time to Live for X722 */
 146 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 147 /* IPv4 Type of Service (TOS) */
 148 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 149 /* IPv4 Protocol */
 150 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 151 /* IPv4 Time to Live */
 152 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 153 /* Source IPv6 address */
 154 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 155 /* Destination IPv6 address */
 156 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 157 /* IPv6 Traffic Class (TC) */
 158 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 159 /* IPv6 Next Header */
 160 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 161 /* IPv6 Hop Limit */
 162 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 163 /* Source L4 port */
 164 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 165 /* Destination L4 port */
 166 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 167 /* SCTP verification tag */
 168 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 169 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 170 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 171 /* Source port of tunneling UDP */
 172 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 173 /* Destination port of tunneling UDP */
 174 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 175 /* UDP Tunneling ID, NVGRE/GRE key */
 176 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 177 /* Last ether type */
 178 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 179 /* Tunneling outer destination IPv4 address */
 180 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 181 /* Tunneling outer destination IPv6 address */
 182 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 183 /* 1st word of flex payload */
 184 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 185 /* 2nd word of flex payload */
 186 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 187 /* 3rd word of flex payload */
 188 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 189 /* 4th word of flex payload */
 190 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 191 /* 5th word of flex payload */
 192 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 193 /* 6th word of flex payload */
 194 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 195 /* 7th word of flex payload */
 196 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 197 /* 8th word of flex payload */
 198 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 199 /* all 8 words flex payload */
 200 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 201 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 202
 203 #define I40E_TRANSLATE_INSET 0
 204 #define I40E_TRANSLATE_REG   1
 205
 206 #define I40E_INSET_IPV4_TOS_MASK        0x0000FF00UL
 207 #define I40E_INSET_IPV4_TTL_MASK        0x000000FFUL
 208 #define I40E_INSET_IPV4_PROTO_MASK      0x0000FF00UL
 209 #define I40E_INSET_IPV6_TC_MASK         0x0000F00FUL
 210 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x0000FF00UL
 211 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000000FFUL
 212
 213 /* PCI offset for querying capability */
 214 #define PCI_DEV_CAP_REG            0xA4
 215 /* PCI offset for enabling/disabling Extended Tag */
 216 #define PCI_DEV_CTRL_REG           0xA8
 217 /* Bit mask of Extended Tag capability */
 218 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 219 /* Bit shift of Extended Tag enable/disable */
 220 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 221 /* Bit mask of Extended Tag enable/disable */
 222 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 223
 224 #define I40E_GLQF_PIT_IPV4_START        2
 225 #define I40E_GLQF_PIT_IPV4_COUNT        2
 226 #define I40E_GLQF_PIT_IPV6_START        4
 227 #define I40E_GLQF_PIT_IPV6_COUNT        2
 228
 229 #define I40E_GLQF_PIT_SOURCE_OFF_GET(a) \
 230                                 (((a) & I40E_GLQF_PIT_SOURCE_OFF_MASK) >> \
 231                                  I40E_GLQF_PIT_SOURCE_OFF_SHIFT)
 232
 233 #define I40E_GLQF_PIT_DEST_OFF_GET(a) \
 234                                 (((a) & I40E_GLQF_PIT_DEST_OFF_MASK) >> \
 235                                  I40E_GLQF_PIT_DEST_OFF_SHIFT)
 236
 237 #define I40E_GLQF_PIT_FSIZE_GET(a)      (((a) & I40E_GLQF_PIT_FSIZE_MASK) >> \
 238                                          I40E_GLQF_PIT_FSIZE_SHIFT)
 239
 240 #define I40E_GLQF_PIT_BUILD(off, mask)  (((off) << 16) | (mask))
 241 #define I40E_FDIR_FIELD_OFFSET(a)       ((a) >> 1)
 242
 243 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 244 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 245 static int i40e_dev_configure(struct rte_eth_dev *dev);
 246 static int i40e_dev_start(struct rte_eth_dev *dev);
 247 static int i40e_dev_stop(struct rte_eth_dev *dev);
 248 static int i40e_dev_close(struct rte_eth_dev *dev);
 249 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 250 static int i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 251 static int i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 252 static int i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 253 static int i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 254 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 255 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 256 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 257                                struct rte_eth_stats *stats);
 258 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 259                                struct rte_eth_xstat *xstats, unsigned n);
 260 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 261                                      struct rte_eth_xstat_name *xstats_names,
 262                                      unsigned limit);
 263 static int i40e_dev_stats_reset(struct rte_eth_dev *dev);
 264 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 265                                 char *fw_version, size_t fw_size);
 266 static int i40e_dev_info_get(struct rte_eth_dev *dev,
 267                              struct rte_eth_dev_info *dev_info);
 268 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 269                                 uint16_t vlan_id,
 270                                 int on);
 271 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 272                               enum rte_vlan_type vlan_type,
 273                               uint16_t tpid);
 274 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 275 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 276                                       uint16_t queue,
 277                                       int on);
 278 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 279 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 280 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 281 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 282                               struct rte_eth_fc_conf *fc_conf);
 283 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 284                               struct rte_eth_fc_conf *fc_conf);
 285 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 286                                        struct rte_eth_pfc_conf *pfc_conf);
 287 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 288                             struct rte_ether_addr *mac_addr,
 289                             uint32_t index,
 290                             uint32_t pool);
 291 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 292 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 293                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 294                                     uint16_t reta_size);
 295 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 296                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 297                                    uint16_t reta_size);
 298
 299 static int i40e_get_cap(struct i40e_hw *hw);
 300 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 301 static int i40e_pf_setup(struct i40e_pf *pf);
 302 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 303 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 304 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 305 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 306                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 307 static void i40e_stat_update_48(struct i40e_hw *hw,
 308                                uint32_t hireg,
 309                                uint32_t loreg,
 310                                bool offset_loaded,
 311                                uint64_t *offset,
 312                                uint64_t *stat);
 313 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 314 static void i40e_dev_interrupt_handler(void *param);
 315 static void i40e_dev_alarm_handler(void *param);
 316 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 317                                 uint32_t base, uint32_t num);
 318 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 319 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 320                         uint32_t base);
 321 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 322                         uint16_t num);
 323 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 324 static int i40e_veb_release(struct i40e_veb *veb);
 325 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 326                                                 struct i40e_vsi *vsi);
 327 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 328 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 329                                              struct i40e_macvlan_filter *mv_f,
 330                                              int num,
 331                                              uint16_t vlan);
 332 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 333 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 334                                     struct rte_eth_rss_conf *rss_conf);
 335 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 336                                       struct rte_eth_rss_conf *rss_conf);
 337 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 338                                         struct rte_eth_udp_tunnel *udp_tunnel);
 339 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 340                                         struct rte_eth_udp_tunnel *udp_tunnel);
 341 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 342 static int i40e_dev_flow_ops_get(struct rte_eth_dev *dev,
 343                                  const struct rte_flow_ops **ops);
 344 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 345                                   struct rte_eth_dcb_info *dcb_info);
 346 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 347 static void i40e_configure_registers(struct i40e_hw *hw);
 348 static void i40e_hw_init(struct rte_eth_dev *dev);
 349 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 350
 351 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 352 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 353 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 354                                            struct timespec *timestamp,
 355                                            uint32_t flags);
 356 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 357                                            struct timespec *timestamp);
 358 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 359
 360 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 361
 362 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 363                                    struct timespec *timestamp);
 364 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 365                                     const struct timespec *timestamp);
 366
 367 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 368                                          uint16_t queue_id);
 369 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 370                                           uint16_t queue_id);
 371
 372 static int i40e_get_regs(struct rte_eth_dev *dev,
 373                          struct rte_dev_reg_info *regs);
 374
 375 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 376
 377 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 378                            struct rte_dev_eeprom_info *eeprom);
 379
 380 static int i40e_get_module_info(struct rte_eth_dev *dev,
 381                                 struct rte_eth_dev_module_info *modinfo);
 382 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
 383                                   struct rte_dev_eeprom_info *info);
 384
 385 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 386                                       struct rte_ether_addr *mac_addr);
 387
 388 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 389 static void i40e_set_mac_max_frame(struct rte_eth_dev *dev, uint16_t size);
 390
 391 static int i40e_ethertype_filter_convert(
 392         const struct rte_eth_ethertype_filter *input,
 393         struct i40e_ethertype_filter *filter);
 394 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 395                                    struct i40e_ethertype_filter *filter);
 396
 397 static int i40e_tunnel_filter_convert(
 398         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
 399         struct i40e_tunnel_filter *tunnel_filter);
 400 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 401                                 struct i40e_tunnel_filter *tunnel_filter);
 402 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 403
 404 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 405 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 406 static void i40e_filter_restore(struct i40e_pf *pf);
 407 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 408
 409 static const char *const valid_keys[] = {
 410         ETH_I40E_FLOATING_VEB_ARG,
 411         ETH_I40E_FLOATING_VEB_LIST_ARG,
 412         ETH_I40E_SUPPORT_MULTI_DRIVER,
 413         ETH_I40E_QUEUE_NUM_PER_VF_ARG,
 414         ETH_I40E_VF_MSG_CFG,
 415         NULL};
 416
 417 static const struct rte_pci_id pci_id_i40e_map[] = {
 418         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 419         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 420         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 421         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 422         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 423         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 424         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 425         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 426         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 438         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X710_N3000) },
 439         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_XXV710_N3000) },
 440         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_BC) },
 441         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_5G_BASE_T_BC) },
 442         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_B) },
 443         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_SFP) },
 444         { .vendor_id = 0, /* sentinel */ },
 445 };
 446
 447 static const struct eth_dev_ops i40e_eth_dev_ops = {
 448         .dev_configure                = i40e_dev_configure,
 449         .dev_start                    = i40e_dev_start,
 450         .dev_stop                     = i40e_dev_stop,
 451         .dev_close                    = i40e_dev_close,
 452         .dev_reset                    = i40e_dev_reset,
 453         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 454         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 455         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 456         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 457         .dev_set_link_up              = i40e_dev_set_link_up,
 458         .dev_set_link_down            = i40e_dev_set_link_down,
 459         .link_update                  = i40e_dev_link_update,
 460         .stats_get                    = i40e_dev_stats_get,
 461         .xstats_get                   = i40e_dev_xstats_get,
 462         .xstats_get_names             = i40e_dev_xstats_get_names,
 463         .stats_reset                  = i40e_dev_stats_reset,
 464         .xstats_reset                 = i40e_dev_stats_reset,
 465         .fw_version_get               = i40e_fw_version_get,
 466         .dev_infos_get                = i40e_dev_info_get,
 467         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 468         .vlan_filter_set              = i40e_vlan_filter_set,
 469         .vlan_tpid_set                = i40e_vlan_tpid_set,
 470         .vlan_offload_set             = i40e_vlan_offload_set,
 471         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 472         .vlan_pvid_set                = i40e_vlan_pvid_set,
 473         .rx_queue_start               = i40e_dev_rx_queue_start,
 474         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 475         .tx_queue_start               = i40e_dev_tx_queue_start,
 476         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 477         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 478         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 479         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 480         .rx_queue_release             = i40e_dev_rx_queue_release,
 481         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 482         .tx_queue_release             = i40e_dev_tx_queue_release,
 483         .dev_led_on                   = i40e_dev_led_on,
 484         .dev_led_off                  = i40e_dev_led_off,
 485         .flow_ctrl_get                = i40e_flow_ctrl_get,
 486         .flow_ctrl_set                = i40e_flow_ctrl_set,
 487         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 488         .mac_addr_add                 = i40e_macaddr_add,
 489         .mac_addr_remove              = i40e_macaddr_remove,
 490         .reta_update                  = i40e_dev_rss_reta_update,
 491         .reta_query                   = i40e_dev_rss_reta_query,
 492         .rss_hash_update              = i40e_dev_rss_hash_update,
 493         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 494         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 495         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 496         .flow_ops_get                 = i40e_dev_flow_ops_get,
 497         .rxq_info_get                 = i40e_rxq_info_get,
 498         .txq_info_get                 = i40e_txq_info_get,
 499         .rx_burst_mode_get            = i40e_rx_burst_mode_get,
 500         .tx_burst_mode_get            = i40e_tx_burst_mode_get,
 501         .timesync_enable              = i40e_timesync_enable,
 502         .timesync_disable             = i40e_timesync_disable,
 503         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 504         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 505         .get_dcb_info                 = i40e_dev_get_dcb_info,
 506         .timesync_adjust_time         = i40e_timesync_adjust_time,
 507         .timesync_read_time           = i40e_timesync_read_time,
 508         .timesync_write_time          = i40e_timesync_write_time,
 509         .get_reg                      = i40e_get_regs,
 510         .get_eeprom_length            = i40e_get_eeprom_length,
 511         .get_eeprom                   = i40e_get_eeprom,
 512         .get_module_info              = i40e_get_module_info,
 513         .get_module_eeprom            = i40e_get_module_eeprom,
 514         .mac_addr_set                 = i40e_set_default_mac_addr,
 515         .mtu_set                      = i40e_dev_mtu_set,
 516         .tm_ops_get                   = i40e_tm_ops_get,
 517         .tx_done_cleanup              = i40e_tx_done_cleanup,
 518         .get_monitor_addr             = i40e_get_monitor_addr,
 519 };
 520
 521 /* store statistics names and its offset in stats structure */
 522 struct rte_i40e_xstats_name_off {
 523         char name[RTE_ETH_XSTATS_NAME_SIZE];
 524         int offset;
 525 };
 526
 527 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 528         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 529         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 530         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 531         {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
 532         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 533                 rx_unknown_protocol)},
 534         {"rx_size_error_packets", offsetof(struct i40e_pf, rx_err1) -
 535                                   offsetof(struct i40e_pf, stats)},
 536         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 537         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 538         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 539         {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
 540 };
 541
 542 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 543                 sizeof(rte_i40e_stats_strings[0]))
 544
 545 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 546         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 547                 tx_dropped_link_down)},
 548         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 549         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 550                 illegal_bytes)},
 551         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 552         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 553                 mac_local_faults)},
 554         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 555                 mac_remote_faults)},
 556         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 557                 rx_length_errors)},
 558         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 559         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 560         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 561         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 562         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 563         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 564                 rx_size_127)},
 565         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 566                 rx_size_255)},
 567         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 568                 rx_size_511)},
 569         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 570                 rx_size_1023)},
 571         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 572                 rx_size_1522)},
 573         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 574                 rx_size_big)},
 575         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 576                 rx_undersize)},
 577         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 578                 rx_oversize)},
 579         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 580                 mac_short_packet_dropped)},
 581         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 582                 rx_fragments)},
 583         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 584         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 585         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 586                 tx_size_127)},
 587         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 588                 tx_size_255)},
 589         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 590                 tx_size_511)},
 591         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 592                 tx_size_1023)},
 593         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 594                 tx_size_1522)},
 595         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 596                 tx_size_big)},
 597         {"rx_flow_director_atr_match_packets",
 598                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 599         {"rx_flow_director_sb_match_packets",
 600                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 601         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 602                 tx_lpi_status)},
 603         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 604                 rx_lpi_status)},
 605         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 606                 tx_lpi_count)},
 607         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 608                 rx_lpi_count)},
 609 };
 610
 611 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 612                 sizeof(rte_i40e_hw_port_strings[0]))
 613
 614 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 615         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 616                 priority_xon_rx)},
 617         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 618                 priority_xoff_rx)},
 619 };
 620
 621 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 622                 sizeof(rte_i40e_rxq_prio_strings[0]))
 623
 624 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 625         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 626                 priority_xon_tx)},
 627         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 628                 priority_xoff_tx)},
 629         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 630                 priority_xon_2_xoff)},
 631 };
 632
 633 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 634                 sizeof(rte_i40e_txq_prio_strings[0]))
 635
 636 static int
 637 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 638         struct rte_pci_device *pci_dev)
 639 {
 640         char name[RTE_ETH_NAME_MAX_LEN];
 641         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
 642         int i, retval;
 643
 644         if (pci_dev->device.devargs) {
 645                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
 646                                 &eth_da);
 647                 if (retval)
 648                         return retval;
 649         }
 650
 651         if (eth_da.nb_representor_ports > 0 &&
 652             eth_da.type != RTE_ETH_REPRESENTOR_VF) {
 653                 PMD_DRV_LOG(ERR, "unsupported representor type: %s\n",
 654                             pci_dev->device.devargs->args);
 655                 return -ENOTSUP;
 656         }
 657
 658         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
 659                 sizeof(struct i40e_adapter),
 660                 eth_dev_pci_specific_init, pci_dev,
 661                 eth_i40e_dev_init, NULL);
 662
 663         if (retval || eth_da.nb_representor_ports < 1)
 664                 return retval;
 665
 666         /* probe VF representor ports */
 667         struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
 668                 pci_dev->device.name);
 669
 670         if (pf_ethdev == NULL)
 671                 return -ENODEV;
 672
 673         for (i = 0; i < eth_da.nb_representor_ports; i++) {
 674                 struct i40e_vf_representor representor = {
 675                         .vf_id = eth_da.representor_ports[i],
 676                         .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
 677                                 pf_ethdev->data->dev_private)->switch_domain_id,
 678                         .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
 679                                 pf_ethdev->data->dev_private)
 680                 };
 681
 682                 /* representor port net_bdf_port */
 683                 snprintf(name, sizeof(name), "net_%s_representor_%d",
 684                         pci_dev->device.name, eth_da.representor_ports[i]);
 685
 686                 retval = rte_eth_dev_create(&pci_dev->device, name,
 687                         sizeof(struct i40e_vf_representor), NULL, NULL,
 688                         i40e_vf_representor_init, &representor);
 689
 690                 if (retval)
 691                         PMD_DRV_LOG(ERR, "failed to create i40e vf "
 692                                 "representor %s.", name);
 693         }
 694
 695         return 0;
 696 }
 697
 698 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 699 {
 700         struct rte_eth_dev *ethdev;
 701
 702         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 703         if (!ethdev)
 704                 return 0;
 705
 706         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
 707                 return rte_eth_dev_pci_generic_remove(pci_dev,
 708                                         i40e_vf_representor_uninit);
 709         else
 710                 return rte_eth_dev_pci_generic_remove(pci_dev,
 711                                                 eth_i40e_dev_uninit);
 712 }
 713
 714 static struct rte_pci_driver rte_i40e_pmd = {
 715         .id_table = pci_id_i40e_map,
 716         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 717         .probe = eth_i40e_pci_probe,
 718         .remove = eth_i40e_pci_remove,
 719 };
 720
 721 static inline void
 722 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
 723                          uint32_t reg_val)
 724 {
 725         uint32_t ori_reg_val;
 726         struct rte_eth_dev_data *dev_data =
 727                 ((struct i40e_adapter *)hw->back)->pf.dev_data;
 728         struct rte_eth_dev *dev = &rte_eth_devices[dev_data->port_id];
 729
 730         ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
 731         i40e_write_rx_ctl(hw, reg_addr, reg_val);
 732         if (ori_reg_val != reg_val)
 733                 PMD_DRV_LOG(WARNING,
 734                             "i40e device %s changed global register [0x%08x]."
 735                             " original: 0x%08x, new: 0x%08x",
 736                             dev->device->name, reg_addr, ori_reg_val, reg_val);
 737 }
 738
 739 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 740 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 741 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 742
 743 #ifndef I40E_GLQF_ORT
 744 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 745 #endif
 746 #ifndef I40E_GLQF_PIT
 747 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 748 #endif
 749 #ifndef I40E_GLQF_L3_MAP
 750 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 751 #endif
 752
 753 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 754 {
 755         /*
 756          * Initialize registers for parsing packet type of QinQ
 757          * This should be removed from code once proper
 758          * configuration API is added to avoid configuration conflicts
 759          * between ports of the same device.
 760          */
 761         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 762         I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 763 }
 764
 765 static inline void i40e_config_automask(struct i40e_pf *pf)
 766 {
 767         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 768         uint32_t val;
 769
 770         /* INTENA flag is not auto-cleared for interrupt */
 771         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
 772         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
 773                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
 774
 775         /* If support multi-driver, PF will use INT0. */
 776         if (!pf->support_multi_driver)
 777                 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
 778
 779         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
 780 }
 781
 782 static inline void i40e_clear_automask(struct i40e_pf *pf)
 783 {
 784         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 785         uint32_t val;
 786
 787         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
 788         val &= ~(I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
 789                  I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK);
 790
 791         if (!pf->support_multi_driver)
 792                 val &= ~I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
 793
 794         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
 795 }
 796
 797 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 798
 799 /*
 800  * Add a ethertype filter to drop all flow control frames transmitted
 801  * from VSIs.
 802 */
 803 static void
 804 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 805 {
 806         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 807         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 808                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 809                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 810         int ret;
 811
 812         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 813                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 814                                 pf->main_vsi_seid, 0,
 815                                 TRUE, NULL, NULL);
 816         if (ret)
 817                 PMD_INIT_LOG(ERR,
 818                         "Failed to add filter to drop flow control frames from VSIs.");
 819 }
 820
 821 static int
 822 floating_veb_list_handler(__rte_unused const char *key,
 823                           const char *floating_veb_value,
 824                           void *opaque)
 825 {
 826         int idx = 0;
 827         unsigned int count = 0;
 828         char *end = NULL;
 829         int min, max;
 830         bool *vf_floating_veb = opaque;
 831
 832         while (isblank(*floating_veb_value))
 833                 floating_veb_value++;
 834
 835         /* Reset floating VEB configuration for VFs */
 836         for (idx = 0; idx < I40E_MAX_VF; idx++)
 837                 vf_floating_veb[idx] = false;
 838
 839         min = I40E_MAX_VF;
 840         do {
 841                 while (isblank(*floating_veb_value))
 842                         floating_veb_value++;
 843                 if (*floating_veb_value == '\0')
 844                         return -1;
 845                 errno = 0;
 846                 idx = strtoul(floating_veb_value, &end, 10);
 847                 if (errno || end == NULL)
 848                         return -1;
 849                 if (idx < 0)
 850                         return -1;
 851                 while (isblank(*end))
 852                         end++;
 853                 if (*end == '-') {
 854                         min = idx;
 855                 } else if ((*end == ';') || (*end == '\0')) {
 856                         max = idx;
 857                         if (min == I40E_MAX_VF)
 858                                 min = idx;
 859                         if (max >= I40E_MAX_VF)
 860                                 max = I40E_MAX_VF - 1;
 861                         for (idx = min; idx <= max; idx++) {
 862                                 vf_floating_veb[idx] = true;
 863                                 count++;
 864                         }
 865                         min = I40E_MAX_VF;
 866                 } else {
 867                         return -1;
 868                 }
 869                 floating_veb_value = end + 1;
 870         } while (*end != '\0');
 871
 872         if (count == 0)
 873                 return -1;
 874
 875         return 0;
 876 }
 877
 878 static void
 879 config_vf_floating_veb(struct rte_devargs *devargs,
 880                        uint16_t floating_veb,
 881                        bool *vf_floating_veb)
 882 {
 883         struct rte_kvargs *kvlist;
 884         int i;
 885         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 886
 887         if (!floating_veb)
 888                 return;
 889         /* All the VFs attach to the floating VEB by default
 890          * when the floating VEB is enabled.
 891          */
 892         for (i = 0; i < I40E_MAX_VF; i++)
 893                 vf_floating_veb[i] = true;
 894
 895         if (devargs == NULL)
 896                 return;
 897
 898         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 899         if (kvlist == NULL)
 900                 return;
 901
 902         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 903                 rte_kvargs_free(kvlist);
 904                 return;
 905         }
 906         /* When the floating_veb_list parameter exists, all the VFs
 907          * will attach to the legacy VEB firstly, then configure VFs
 908          * to the floating VEB according to the floating_veb_list.
 909          */
 910         if (rte_kvargs_process(kvlist, floating_veb_list,
 911                                floating_veb_list_handler,
 912                                vf_floating_veb) < 0) {
 913                 rte_kvargs_free(kvlist);
 914                 return;
 915         }
 916         rte_kvargs_free(kvlist);
 917 }
 918
 919 static int
 920 i40e_check_floating_handler(__rte_unused const char *key,
 921                             const char *value,
 922                             __rte_unused void *opaque)
 923 {
 924         if (strcmp(value, "1"))
 925                 return -1;
 926
 927         return 0;
 928 }
 929
 930 static int
 931 is_floating_veb_supported(struct rte_devargs *devargs)
 932 {
 933         struct rte_kvargs *kvlist;
 934         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 935
 936         if (devargs == NULL)
 937                 return 0;
 938
 939         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 940         if (kvlist == NULL)
 941                 return 0;
 942
 943         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 944                 rte_kvargs_free(kvlist);
 945                 return 0;
 946         }
 947         /* Floating VEB is enabled when there's key-value:
 948          * enable_floating_veb=1
 949          */
 950         if (rte_kvargs_process(kvlist, floating_veb_key,
 951                                i40e_check_floating_handler, NULL) < 0) {
 952                 rte_kvargs_free(kvlist);
 953                 return 0;
 954         }
 955         rte_kvargs_free(kvlist);
 956
 957         return 1;
 958 }
 959
 960 static void
 961 config_floating_veb(struct rte_eth_dev *dev)
 962 {
 963         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 964         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 965         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 966
 967         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 968
 969         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 970                 pf->floating_veb =
 971                         is_floating_veb_supported(pci_dev->device.devargs);
 972                 config_vf_floating_veb(pci_dev->device.devargs,
 973                                        pf->floating_veb,
 974                                        pf->floating_veb_list);
 975         } else {
 976                 pf->floating_veb = false;
 977         }
 978 }
 979
 980 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 981 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 982
 983 static int
 984 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 985 {
 986         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 987         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 988         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 989         int ret;
 990
 991         struct rte_hash_parameters ethertype_hash_params = {
 992                 .name = ethertype_hash_name,
 993                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 994                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 995                 .hash_func = rte_hash_crc,
 996                 .hash_func_init_val = 0,
 997                 .socket_id = rte_socket_id(),
 998         };
 999
1000         /* Initialize ethertype filter rule list and hash */
1001         TAILQ_INIT(&ethertype_rule->ethertype_list);
1002         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
1003                  "ethertype_%s", dev->device->name);
1004         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
1005         if (!ethertype_rule->hash_table) {
1006                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
1007                 return -EINVAL;
1008         }
1009         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
1010                                        sizeof(struct i40e_ethertype_filter *) *
1011                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
1012                                        0);
1013         if (!ethertype_rule->hash_map) {
1014                 PMD_INIT_LOG(ERR,
1015                              "Failed to allocate memory for ethertype hash map!");
1016                 ret = -ENOMEM;
1017                 goto err_ethertype_hash_map_alloc;
1018         }
1019
1020         return 0;
1021
1022 err_ethertype_hash_map_alloc:
1023         rte_hash_free(ethertype_rule->hash_table);
1024
1025         return ret;
1026 }
1027
1028 static int
1029 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
1030 {
1031         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1032         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
1033         char tunnel_hash_name[RTE_HASH_NAMESIZE];
1034         int ret;
1035
1036         struct rte_hash_parameters tunnel_hash_params = {
1037                 .name = tunnel_hash_name,
1038                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1039                 .key_len = sizeof(struct i40e_tunnel_filter_input),
1040                 .hash_func = rte_hash_crc,
1041                 .hash_func_init_val = 0,
1042                 .socket_id = rte_socket_id(),
1043         };
1044
1045         /* Initialize tunnel filter rule list and hash */
1046         TAILQ_INIT(&tunnel_rule->tunnel_list);
1047         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1048                  "tunnel_%s", dev->device->name);
1049         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1050         if (!tunnel_rule->hash_table) {
1051                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1052                 return -EINVAL;
1053         }
1054         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1055                                     sizeof(struct i40e_tunnel_filter *) *
1056                                     I40E_MAX_TUNNEL_FILTER_NUM,
1057                                     0);
1058         if (!tunnel_rule->hash_map) {
1059                 PMD_INIT_LOG(ERR,
1060                              "Failed to allocate memory for tunnel hash map!");
1061                 ret = -ENOMEM;
1062                 goto err_tunnel_hash_map_alloc;
1063         }
1064
1065         return 0;
1066
1067 err_tunnel_hash_map_alloc:
1068         rte_hash_free(tunnel_rule->hash_table);
1069
1070         return ret;
1071 }
1072
1073 static int
1074 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1075 {
1076         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1077         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1078         struct i40e_fdir_info *fdir_info = &pf->fdir;
1079         char fdir_hash_name[RTE_HASH_NAMESIZE];
1080         uint32_t alloc = hw->func_caps.fd_filters_guaranteed;
1081         uint32_t best = hw->func_caps.fd_filters_best_effort;
1082         enum i40e_filter_pctype pctype;
1083         struct rte_bitmap *bmp = NULL;
1084         uint32_t bmp_size;
1085         void *mem = NULL;
1086         uint32_t i = 0;
1087         int ret;
1088
1089         struct rte_hash_parameters fdir_hash_params = {
1090                 .name = fdir_hash_name,
1091                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1092                 .key_len = sizeof(struct i40e_fdir_input),
1093                 .hash_func = rte_hash_crc,
1094                 .hash_func_init_val = 0,
1095                 .socket_id = rte_socket_id(),
1096         };
1097
1098         /* Initialize flow director filter rule list and hash */
1099         TAILQ_INIT(&fdir_info->fdir_list);
1100         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1101                  "fdir_%s", dev->device->name);
1102         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1103         if (!fdir_info->hash_table) {
1104                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1105                 return -EINVAL;
1106         }
1107
1108         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1109                                           sizeof(struct i40e_fdir_filter *) *
1110                                           I40E_MAX_FDIR_FILTER_NUM,
1111                                           0);
1112         if (!fdir_info->hash_map) {
1113                 PMD_INIT_LOG(ERR,
1114                              "Failed to allocate memory for fdir hash map!");
1115                 ret = -ENOMEM;
1116                 goto err_fdir_hash_map_alloc;
1117         }
1118
1119         fdir_info->fdir_filter_array = rte_zmalloc("fdir_filter",
1120                         sizeof(struct i40e_fdir_filter) *
1121                         I40E_MAX_FDIR_FILTER_NUM,
1122                         0);
1123
1124         if (!fdir_info->fdir_filter_array) {
1125                 PMD_INIT_LOG(ERR,
1126                              "Failed to allocate memory for fdir filter array!");
1127                 ret = -ENOMEM;
1128                 goto err_fdir_filter_array_alloc;
1129         }
1130
1131         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
1132              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++)
1133                 pf->fdir.flow_count[pctype] = 0;
1134
1135         fdir_info->fdir_space_size = alloc + best;
1136         fdir_info->fdir_actual_cnt = 0;
1137         fdir_info->fdir_guarantee_total_space = alloc;
1138         fdir_info->fdir_guarantee_free_space =
1139                 fdir_info->fdir_guarantee_total_space;
1140
1141         PMD_DRV_LOG(INFO, "FDIR guarantee space: %u, best_effort space %u.", alloc, best);
1142
1143         fdir_info->fdir_flow_pool.pool =
1144                         rte_zmalloc("i40e_fdir_entry",
1145                                 sizeof(struct i40e_fdir_entry) *
1146                                 fdir_info->fdir_space_size,
1147                                 0);
1148
1149         if (!fdir_info->fdir_flow_pool.pool) {
1150                 PMD_INIT_LOG(ERR,
1151                              "Failed to allocate memory for bitmap flow!");
1152                 ret = -ENOMEM;
1153                 goto err_fdir_bitmap_flow_alloc;
1154         }
1155
1156         for (i = 0; i < fdir_info->fdir_space_size; i++)
1157                 fdir_info->fdir_flow_pool.pool[i].idx = i;
1158
1159         bmp_size =
1160                 rte_bitmap_get_memory_footprint(fdir_info->fdir_space_size);
1161         mem = rte_zmalloc("fdir_bmap", bmp_size, RTE_CACHE_LINE_SIZE);
1162         if (mem == NULL) {
1163                 PMD_INIT_LOG(ERR,
1164                              "Failed to allocate memory for fdir bitmap!");
1165                 ret = -ENOMEM;
1166                 goto err_fdir_mem_alloc;
1167         }
1168         bmp = rte_bitmap_init(fdir_info->fdir_space_size, mem, bmp_size);
1169         if (bmp == NULL) {
1170                 PMD_INIT_LOG(ERR,
1171                              "Failed to initialization fdir bitmap!");
1172                 ret = -ENOMEM;
1173                 goto err_fdir_bmp_alloc;
1174         }
1175         for (i = 0; i < fdir_info->fdir_space_size; i++)
1176                 rte_bitmap_set(bmp, i);
1177
1178         fdir_info->fdir_flow_pool.bitmap = bmp;
1179
1180         return 0;
1181
1182 err_fdir_bmp_alloc:
1183         rte_free(mem);
1184 err_fdir_mem_alloc:
1185         rte_free(fdir_info->fdir_flow_pool.pool);
1186 err_fdir_bitmap_flow_alloc:
1187         rte_free(fdir_info->fdir_filter_array);
1188 err_fdir_filter_array_alloc:
1189         rte_free(fdir_info->hash_map);
1190 err_fdir_hash_map_alloc:
1191         rte_hash_free(fdir_info->hash_table);
1192
1193         return ret;
1194 }
1195
1196 static void
1197 i40e_init_customized_info(struct i40e_pf *pf)
1198 {
1199         int i;
1200
1201         /* Initialize customized pctype */
1202         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1203                 pf->customized_pctype[i].index = i;
1204                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1205                 pf->customized_pctype[i].valid = false;
1206         }
1207
1208         pf->gtp_support = false;
1209         pf->esp_support = false;
1210 }
1211
1212 static void
1213 i40e_init_filter_invalidation(struct i40e_pf *pf)
1214 {
1215         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1216         struct i40e_fdir_info *fdir_info = &pf->fdir;
1217         uint32_t glqf_ctl_reg = 0;
1218
1219         glqf_ctl_reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
1220         if (!pf->support_multi_driver) {
1221                 fdir_info->fdir_invalprio = 1;
1222                 glqf_ctl_reg |= I40E_GLQF_CTL_INVALPRIO_MASK;
1223                 PMD_DRV_LOG(INFO, "FDIR INVALPRIO set to guaranteed first");
1224                 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, glqf_ctl_reg);
1225         } else {
1226                 if (glqf_ctl_reg & I40E_GLQF_CTL_INVALPRIO_MASK) {
1227                         fdir_info->fdir_invalprio = 1;
1228                         PMD_DRV_LOG(INFO, "FDIR INVALPRIO is: guaranteed first");
1229                 } else {
1230                         fdir_info->fdir_invalprio = 0;
1231                         PMD_DRV_LOG(INFO, "FDIR INVALPRIO is: shared first");
1232                 }
1233         }
1234 }
1235
1236 void
1237 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1238 {
1239         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1240         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1241         struct i40e_queue_regions *info = &pf->queue_region;
1242         uint16_t i;
1243
1244         for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1245                 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1246
1247         memset(info, 0, sizeof(struct i40e_queue_regions));
1248 }
1249
1250 static int
1251 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1252                                const char *value,
1253                                void *opaque)
1254 {
1255         struct i40e_pf *pf;
1256         unsigned long support_multi_driver;
1257         char *end;
1258
1259         pf = (struct i40e_pf *)opaque;
1260
1261         errno = 0;
1262         support_multi_driver = strtoul(value, &end, 10);
1263         if (errno != 0 || end == value || *end != 0) {
1264                 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1265                 return -(EINVAL);
1266         }
1267
1268         if (support_multi_driver == 1 || support_multi_driver == 0)
1269                 pf->support_multi_driver = (bool)support_multi_driver;
1270         else
1271                 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1272                             "enable global configuration by default."
1273                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1274         return 0;
1275 }
1276
1277 static int
1278 i40e_support_multi_driver(struct rte_eth_dev *dev)
1279 {
1280         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1281         struct rte_kvargs *kvlist;
1282         int kvargs_count;
1283
1284         /* Enable global configuration by default */
1285         pf->support_multi_driver = false;
1286
1287         if (!dev->device->devargs)
1288                 return 0;
1289
1290         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1291         if (!kvlist)
1292                 return -EINVAL;
1293
1294         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1295         if (!kvargs_count) {
1296                 rte_kvargs_free(kvlist);
1297                 return 0;
1298         }
1299
1300         if (kvargs_count > 1)
1301                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1302                             "the first invalid or last valid one is used !",
1303                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1304
1305         if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1306                                i40e_parse_multi_drv_handler, pf) < 0) {
1307                 rte_kvargs_free(kvlist);
1308                 return -EINVAL;
1309         }
1310
1311         rte_kvargs_free(kvlist);
1312         return 0;
1313 }
1314
1315 static int
1316 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1317                                     uint32_t reg_addr, uint64_t reg_val,
1318                                     struct i40e_asq_cmd_details *cmd_details)
1319 {
1320         uint64_t ori_reg_val;
1321         struct rte_eth_dev_data *dev_data =
1322                 ((struct i40e_adapter *)hw->back)->pf.dev_data;
1323         struct rte_eth_dev *dev = &rte_eth_devices[dev_data->port_id];
1324         int ret;
1325
1326         ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1327         if (ret != I40E_SUCCESS) {
1328                 PMD_DRV_LOG(ERR,
1329                             "Fail to debug read from 0x%08x",
1330                             reg_addr);
1331                 return -EIO;
1332         }
1333
1334         if (ori_reg_val != reg_val)
1335                 PMD_DRV_LOG(WARNING,
1336                             "i40e device %s changed global register [0x%08x]."
1337                             " original: 0x%"PRIx64", after: 0x%"PRIx64,
1338                             dev->device->name, reg_addr, ori_reg_val, reg_val);
1339
1340         return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1341 }
1342
1343 static int
1344 read_vf_msg_config(__rte_unused const char *key,
1345                                const char *value,
1346                                void *opaque)
1347 {
1348         struct i40e_vf_msg_cfg *cfg = opaque;
1349
1350         if (sscanf(value, "%u@%u:%u", &cfg->max_msg, &cfg->period,
1351                         &cfg->ignore_second) != 3) {
1352                 memset(cfg, 0, sizeof(*cfg));
1353                 PMD_DRV_LOG(ERR, "format error! example: "
1354                                 "%s=60@120:180", ETH_I40E_VF_MSG_CFG);
1355                 return -EINVAL;
1356         }
1357
1358         /*
1359          * If the message validation function been enabled, the 'period'
1360          * and 'ignore_second' must greater than 0.
1361          */
1362         if (cfg->max_msg && (!cfg->period || !cfg->ignore_second)) {
1363                 memset(cfg, 0, sizeof(*cfg));
1364                 PMD_DRV_LOG(ERR, "%s error! the second and third"
1365                                 " number must be greater than 0!",
1366                                 ETH_I40E_VF_MSG_CFG);
1367                 return -EINVAL;
1368         }
1369
1370         return 0;
1371 }
1372
1373 static int
1374 i40e_parse_vf_msg_config(struct rte_eth_dev *dev,
1375                 struct i40e_vf_msg_cfg *msg_cfg)
1376 {
1377         struct rte_kvargs *kvlist;
1378         int kvargs_count;
1379         int ret = 0;
1380
1381         memset(msg_cfg, 0, sizeof(*msg_cfg));
1382
1383         if (!dev->device->devargs)
1384                 return ret;
1385
1386         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1387         if (!kvlist)
1388                 return -EINVAL;
1389
1390         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_VF_MSG_CFG);
1391         if (!kvargs_count)
1392                 goto free_end;
1393
1394         if (kvargs_count > 1) {
1395                 PMD_DRV_LOG(ERR, "More than one argument \"%s\"!",
1396                                 ETH_I40E_VF_MSG_CFG);
1397                 ret = -EINVAL;
1398                 goto free_end;
1399         }
1400
1401         if (rte_kvargs_process(kvlist, ETH_I40E_VF_MSG_CFG,
1402                         read_vf_msg_config, msg_cfg) < 0)
1403                 ret = -EINVAL;
1404
1405 free_end:
1406         rte_kvargs_free(kvlist);
1407         return ret;
1408 }
1409
1410 #define I40E_ALARM_INTERVAL 50000 /* us */
1411
1412 static int
1413 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1414 {
1415         struct rte_pci_device *pci_dev;
1416         struct rte_intr_handle *intr_handle;
1417         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1418         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1419         struct i40e_vsi *vsi;
1420         int ret;
1421         uint32_t len, val;
1422         uint8_t aq_fail = 0;
1423
1424         PMD_INIT_FUNC_TRACE();
1425
1426         dev->dev_ops = &i40e_eth_dev_ops;
1427         dev->rx_queue_count = i40e_dev_rx_queue_count;
1428         dev->rx_descriptor_status = i40e_dev_rx_descriptor_status;
1429         dev->tx_descriptor_status = i40e_dev_tx_descriptor_status;
1430         dev->rx_pkt_burst = i40e_recv_pkts;
1431         dev->tx_pkt_burst = i40e_xmit_pkts;
1432         dev->tx_pkt_prepare = i40e_prep_pkts;
1433
1434         /* for secondary processes, we don't initialise any further as primary
1435          * has already done this work. Only check we don't need a different
1436          * RX function */
1437         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1438                 i40e_set_rx_function(dev);
1439                 i40e_set_tx_function(dev);
1440                 return 0;
1441         }
1442         i40e_set_default_ptype_table(dev);
1443         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1444         intr_handle = pci_dev->intr_handle;
1445
1446         rte_eth_copy_pci_info(dev, pci_dev);
1447
1448         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1449         pf->dev_data = dev->data;
1450
1451         hw->back = I40E_PF_TO_ADAPTER(pf);
1452         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1453         if (!hw->hw_addr) {
1454                 PMD_INIT_LOG(ERR,
1455                         "Hardware is not available, as address is NULL");
1456                 return -ENODEV;
1457         }
1458
1459         hw->vendor_id = pci_dev->id.vendor_id;
1460         hw->device_id = pci_dev->id.device_id;
1461         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1462         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1463         hw->bus.device = pci_dev->addr.devid;
1464         hw->bus.func = pci_dev->addr.function;
1465         hw->adapter_stopped = 0;
1466         hw->adapter_closed = 0;
1467
1468         /* Init switch device pointer */
1469         hw->switch_dev = NULL;
1470
1471         /*
1472          * Switch Tag value should not be identical to either the First Tag
1473          * or Second Tag values. So set something other than common Ethertype
1474          * for internal switching.
1475          */
1476         hw->switch_tag = 0xffff;
1477
1478         val = I40E_READ_REG(hw, I40E_GL_FWSTS);
1479         if (val & I40E_GL_FWSTS_FWS1B_MASK) {
1480                 PMD_INIT_LOG(ERR, "\nERROR: "
1481                         "Firmware recovery mode detected. Limiting functionality.\n"
1482                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1483                         "User Guide for details on firmware recovery mode.");
1484                 return -EIO;
1485         }
1486
1487         i40e_parse_vf_msg_config(dev, &pf->vf_msg_cfg);
1488         /* Check if need to support multi-driver */
1489         i40e_support_multi_driver(dev);
1490
1491         /* Make sure all is clean before doing PF reset */
1492         i40e_clear_hw(hw);
1493
1494         /* Reset here to make sure all is clean for each PF */
1495         ret = i40e_pf_reset(hw);
1496         if (ret) {
1497                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1498                 return ret;
1499         }
1500
1501         /* Initialize the shared code (base driver) */
1502         ret = i40e_init_shared_code(hw);
1503         if (ret) {
1504                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1505                 return ret;
1506         }
1507
1508         /* Initialize the parameters for adminq */
1509         i40e_init_adminq_parameter(hw);
1510         ret = i40e_init_adminq(hw);
1511         if (ret != I40E_SUCCESS) {
1512                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1513                 return -EIO;
1514         }
1515         /* Firmware of SFP x722 does not support 802.1ad frames ability */
1516         if (hw->device_id == I40E_DEV_ID_SFP_X722 ||
1517                 hw->device_id == I40E_DEV_ID_SFP_I_X722)
1518                 hw->flags &= ~I40E_HW_FLAG_802_1AD_CAPABLE;
1519
1520         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1521                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1522                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1523                      ((hw->nvm.version >> 12) & 0xf),
1524                      ((hw->nvm.version >> 4) & 0xff),
1525                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1526
1527         /* Initialize the hardware */
1528         i40e_hw_init(dev);
1529
1530         i40e_config_automask(pf);
1531
1532         i40e_set_default_pctype_table(dev);
1533
1534         /*
1535          * To work around the NVM issue, initialize registers
1536          * for packet type of QinQ by software.
1537          * It should be removed once issues are fixed in NVM.
1538          */
1539         if (!pf->support_multi_driver)
1540                 i40e_GLQF_reg_init(hw);
1541
1542         /* Initialize the input set for filters (hash and fd) to default value */
1543         i40e_filter_input_set_init(pf);
1544
1545         /* initialise the L3_MAP register */
1546         if (!pf->support_multi_driver) {
1547                 ret = i40e_aq_debug_write_global_register(hw,
1548                                                    I40E_GLQF_L3_MAP(40),
1549                                                    0x00000028,  NULL);
1550                 if (ret)
1551                         PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1552                                      ret);
1553                 PMD_INIT_LOG(DEBUG,
1554                              "Global register 0x%08x is changed with 0x28",
1555                              I40E_GLQF_L3_MAP(40));
1556         }
1557
1558         /* Need the special FW version to support floating VEB */
1559         config_floating_veb(dev);
1560         /* Clear PXE mode */
1561         i40e_clear_pxe_mode(hw);
1562         i40e_dev_sync_phy_type(hw);
1563
1564         /*
1565          * On X710, performance number is far from the expectation on recent
1566          * firmware versions. The fix for this issue may not be integrated in
1567          * the following firmware version. So the workaround in software driver
1568          * is needed. It needs to modify the initial values of 3 internal only
1569          * registers. Note that the workaround can be removed when it is fixed
1570          * in firmware in the future.
1571          */
1572         i40e_configure_registers(hw);
1573
1574         /* Get hw capabilities */
1575         ret = i40e_get_cap(hw);
1576         if (ret != I40E_SUCCESS) {
1577                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1578                 goto err_get_capabilities;
1579         }
1580
1581         /* Initialize parameters for PF */
1582         ret = i40e_pf_parameter_init(dev);
1583         if (ret != 0) {
1584                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1585                 goto err_parameter_init;
1586         }
1587
1588         /* Initialize the queue management */
1589         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1590         if (ret < 0) {
1591                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1592                 goto err_qp_pool_init;
1593         }
1594         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1595                                 hw->func_caps.num_msix_vectors - 1);
1596         if (ret < 0) {
1597                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1598                 goto err_msix_pool_init;
1599         }
1600
1601         /* Initialize lan hmc */
1602         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1603                                 hw->func_caps.num_rx_qp, 0, 0);
1604         if (ret != I40E_SUCCESS) {
1605                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1606                 goto err_init_lan_hmc;
1607         }
1608
1609         /* Configure lan hmc */
1610         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1611         if (ret != I40E_SUCCESS) {
1612                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1613                 goto err_configure_lan_hmc;
1614         }
1615
1616         /* Get and check the mac address */
1617         i40e_get_mac_addr(hw, hw->mac.addr);
1618         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1619                 PMD_INIT_LOG(ERR, "mac address is not valid");
1620                 ret = -EIO;
1621                 goto err_get_mac_addr;
1622         }
1623         /* Copy the permanent MAC address */
1624         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1625                         (struct rte_ether_addr *)hw->mac.perm_addr);
1626
1627         /* Disable flow control */
1628         hw->fc.requested_mode = I40E_FC_NONE;
1629         i40e_set_fc(hw, &aq_fail, TRUE);
1630
1631         /* Set the global registers with default ether type value */
1632         if (!pf->support_multi_driver) {
1633                 ret = i40e_vlan_tpid_set(dev, RTE_ETH_VLAN_TYPE_OUTER,
1634                                          RTE_ETHER_TYPE_VLAN);
1635                 if (ret != I40E_SUCCESS) {
1636                         PMD_INIT_LOG(ERR,
1637                                      "Failed to set the default outer "
1638                                      "VLAN ether type");
1639                         goto err_setup_pf_switch;
1640                 }
1641         }
1642
1643         /* PF setup, which includes VSI setup */
1644         ret = i40e_pf_setup(pf);
1645         if (ret) {
1646                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1647                 goto err_setup_pf_switch;
1648         }
1649
1650         vsi = pf->main_vsi;
1651
1652         /* Disable double vlan by default */
1653         i40e_vsi_config_double_vlan(vsi, FALSE);
1654
1655         /* Disable S-TAG identification when floating_veb is disabled */
1656         if (!pf->floating_veb) {
1657                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1658                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1659                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1660                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1661                 }
1662         }
1663
1664         if (!vsi->max_macaddrs)
1665                 len = RTE_ETHER_ADDR_LEN;
1666         else
1667                 len = RTE_ETHER_ADDR_LEN * vsi->max_macaddrs;
1668
1669         /* Should be after VSI initialized */
1670         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1671         if (!dev->data->mac_addrs) {
1672                 PMD_INIT_LOG(ERR,
1673                         "Failed to allocated memory for storing mac address");
1674                 goto err_mac_alloc;
1675         }
1676         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1677                                         &dev->data->mac_addrs[0]);
1678
1679         /* Init dcb to sw mode by default */
1680         ret = i40e_dcb_init_configure(dev, TRUE);
1681         if (ret != I40E_SUCCESS) {
1682                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1683                 pf->flags &= ~I40E_FLAG_DCB;
1684         }
1685         /* Update HW struct after DCB configuration */
1686         i40e_get_cap(hw);
1687
1688         /* initialize pf host driver to setup SRIOV resource if applicable */
1689         i40e_pf_host_init(dev);
1690
1691         /* register callback func to eal lib */
1692         rte_intr_callback_register(intr_handle,
1693                                    i40e_dev_interrupt_handler, dev);
1694
1695         /* configure and enable device interrupt */
1696         i40e_pf_config_irq0(hw, TRUE);
1697         i40e_pf_enable_irq0(hw);
1698
1699         /* enable uio intr after callback register */
1700         rte_intr_enable(intr_handle);
1701
1702         /* By default disable flexible payload in global configuration */
1703         if (!pf->support_multi_driver)
1704                 i40e_flex_payload_reg_set_default(hw);
1705
1706         /*
1707          * Add an ethertype filter to drop all flow control frames transmitted
1708          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1709          * frames to wire.
1710          */
1711         i40e_add_tx_flow_control_drop_filter(pf);
1712
1713         /* initialize RSS rule list */
1714         TAILQ_INIT(&pf->rss_config_list);
1715
1716         /* initialize Traffic Manager configuration */
1717         i40e_tm_conf_init(dev);
1718
1719         /* Initialize customized information */
1720         i40e_init_customized_info(pf);
1721
1722         /* Initialize the filter invalidation configuration */
1723         i40e_init_filter_invalidation(pf);
1724
1725         ret = i40e_init_ethtype_filter_list(dev);
1726         if (ret < 0)
1727                 goto err_init_ethtype_filter_list;
1728         ret = i40e_init_tunnel_filter_list(dev);
1729         if (ret < 0)
1730                 goto err_init_tunnel_filter_list;
1731         ret = i40e_init_fdir_filter_list(dev);
1732         if (ret < 0)
1733                 goto err_init_fdir_filter_list;
1734
1735         /* initialize queue region configuration */
1736         i40e_init_queue_region_conf(dev);
1737
1738         /* reset all stats of the device, including pf and main vsi */
1739         i40e_dev_stats_reset(dev);
1740
1741         return 0;
1742
1743 err_init_fdir_filter_list:
1744         rte_hash_free(pf->tunnel.hash_table);
1745         rte_free(pf->tunnel.hash_map);
1746 err_init_tunnel_filter_list:
1747         rte_hash_free(pf->ethertype.hash_table);
1748         rte_free(pf->ethertype.hash_map);
1749 err_init_ethtype_filter_list:
1750         rte_intr_callback_unregister(intr_handle,
1751                 i40e_dev_interrupt_handler, dev);
1752         rte_free(dev->data->mac_addrs);
1753         dev->data->mac_addrs = NULL;
1754 err_mac_alloc:
1755         i40e_vsi_release(pf->main_vsi);
1756 err_setup_pf_switch:
1757 err_get_mac_addr:
1758 err_configure_lan_hmc:
1759         (void)i40e_shutdown_lan_hmc(hw);
1760 err_init_lan_hmc:
1761         i40e_res_pool_destroy(&pf->msix_pool);
1762 err_msix_pool_init:
1763         i40e_res_pool_destroy(&pf->qp_pool);
1764 err_qp_pool_init:
1765 err_parameter_init:
1766 err_get_capabilities:
1767         (void)i40e_shutdown_adminq(hw);
1768
1769         return ret;
1770 }
1771
1772 static void
1773 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1774 {
1775         struct i40e_ethertype_filter *p_ethertype;
1776         struct i40e_ethertype_rule *ethertype_rule;
1777
1778         ethertype_rule = &pf->ethertype;
1779         /* Remove all ethertype filter rules and hash */
1780         rte_free(ethertype_rule->hash_map);
1781         rte_hash_free(ethertype_rule->hash_table);
1782
1783         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1784                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1785                              p_ethertype, rules);
1786                 rte_free(p_ethertype);
1787         }
1788 }
1789
1790 static void
1791 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1792 {
1793         struct i40e_tunnel_filter *p_tunnel;
1794         struct i40e_tunnel_rule *tunnel_rule;
1795
1796         tunnel_rule = &pf->tunnel;
1797         /* Remove all tunnel director rules and hash */
1798         rte_free(tunnel_rule->hash_map);
1799         rte_hash_free(tunnel_rule->hash_table);
1800
1801         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1802                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1803                 rte_free(p_tunnel);
1804         }
1805 }
1806
1807 static void
1808 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1809 {
1810         struct i40e_fdir_filter *p_fdir;
1811         struct i40e_fdir_info *fdir_info;
1812
1813         fdir_info = &pf->fdir;
1814
1815         /* Remove all flow director rules */
1816         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list)))
1817                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1818 }
1819
1820 static void
1821 i40e_fdir_memory_cleanup(struct i40e_pf *pf)
1822 {
1823         struct i40e_fdir_info *fdir_info;
1824
1825         fdir_info = &pf->fdir;
1826
1827         /* flow director memory cleanup */
1828         rte_free(fdir_info->hash_map);
1829         rte_hash_free(fdir_info->hash_table);
1830         rte_free(fdir_info->fdir_flow_pool.bitmap);
1831         rte_free(fdir_info->fdir_flow_pool.pool);
1832         rte_free(fdir_info->fdir_filter_array);
1833 }
1834
1835 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1836 {
1837         /*
1838          * Disable by default flexible payload
1839          * for corresponding L2/L3/L4 layers.
1840          */
1841         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1842         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1843         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1844 }
1845
1846 static int
1847 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1848 {
1849         struct i40e_hw *hw;
1850
1851         PMD_INIT_FUNC_TRACE();
1852
1853         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1854                 return 0;
1855
1856         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1857
1858         if (hw->adapter_closed == 0)
1859                 i40e_dev_close(dev);
1860
1861         return 0;
1862 }
1863
1864 static int
1865 i40e_dev_configure(struct rte_eth_dev *dev)
1866 {
1867         struct i40e_adapter *ad =
1868                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1869         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1870         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1871         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1872         int i, ret;
1873
1874         ret = i40e_dev_sync_phy_type(hw);
1875         if (ret)
1876                 return ret;
1877
1878         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1879          * bulk allocation or vector Rx preconditions we will reset it.
1880          */
1881         ad->rx_bulk_alloc_allowed = true;
1882         ad->rx_vec_allowed = true;
1883         ad->tx_simple_allowed = true;
1884         ad->tx_vec_allowed = true;
1885
1886         if (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG)
1887                 dev->data->dev_conf.rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;
1888
1889         /* Only legacy filter API needs the following fdir config. So when the
1890          * legacy filter API is deprecated, the following codes should also be
1891          * removed.
1892          */
1893         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1894                 ret = i40e_fdir_setup(pf);
1895                 if (ret != I40E_SUCCESS) {
1896                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1897                         return -ENOTSUP;
1898                 }
1899                 ret = i40e_fdir_configure(dev);
1900                 if (ret < 0) {
1901                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1902                         goto err;
1903                 }
1904         } else
1905                 i40e_fdir_teardown(pf);
1906
1907         ret = i40e_dev_init_vlan(dev);
1908         if (ret < 0)
1909                 goto err;
1910
1911         /* VMDQ setup.
1912          *  General PMD call sequence are NIC init, configure,
1913          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1914          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1915          *  applicable. So, VMDQ setting has to be done before
1916          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1917          *  For RSS setting, it will try to calculate actual configured RX queue
1918          *  number, which will be available after rx_queue_setup(). dev_start()
1919          *  function is good to place RSS setup.
1920          */
1921         if (mq_mode & RTE_ETH_MQ_RX_VMDQ_FLAG) {
1922                 ret = i40e_vmdq_setup(dev);
1923                 if (ret)
1924                         goto err;
1925         }
1926
1927         if (mq_mode & RTE_ETH_MQ_RX_DCB_FLAG) {
1928                 ret = i40e_dcb_setup(dev);
1929                 if (ret) {
1930                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1931                         goto err_dcb;
1932                 }
1933         }
1934
1935         TAILQ_INIT(&pf->flow_list);
1936
1937         return 0;
1938
1939 err_dcb:
1940         /* need to release vmdq resource if exists */
1941         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1942                 i40e_vsi_release(pf->vmdq[i].vsi);
1943                 pf->vmdq[i].vsi = NULL;
1944         }
1945         rte_free(pf->vmdq);
1946         pf->vmdq = NULL;
1947 err:
1948         /* Need to release fdir resource if exists.
1949          * Only legacy filter API needs the following fdir config. So when the
1950          * legacy filter API is deprecated, the following code should also be
1951          * removed.
1952          */
1953         i40e_fdir_teardown(pf);
1954         return ret;
1955 }
1956
1957 void
1958 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1959 {
1960         struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
1961         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1962         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
1963         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1964         uint16_t msix_vect = vsi->msix_intr;
1965         uint16_t i;
1966
1967         for (i = 0; i < vsi->nb_qps; i++) {
1968                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1969                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1970                 rte_wmb();
1971         }
1972
1973         if (vsi->type != I40E_VSI_SRIOV) {
1974                 if (!rte_intr_allow_others(intr_handle)) {
1975                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1976                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1977                         I40E_WRITE_REG(hw,
1978                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1979                                        0);
1980                 } else {
1981                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1982                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1983                         I40E_WRITE_REG(hw,
1984                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1985                                                        msix_vect - 1), 0);
1986                 }
1987         } else {
1988                 uint32_t reg;
1989                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1990                         vsi->user_param + (msix_vect - 1);
1991
1992                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1993                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1994         }
1995         I40E_WRITE_FLUSH(hw);
1996 }
1997
1998 static void
1999 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
2000                        int base_queue, int nb_queue,
2001                        uint16_t itr_idx)
2002 {
2003         int i;
2004         uint32_t val;
2005         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2006         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2007
2008         /* Bind all RX queues to allocated MSIX interrupt */
2009         for (i = 0; i < nb_queue; i++) {
2010                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2011                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
2012                         ((base_queue + i + 1) <<
2013                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
2014                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
2015                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
2016
2017                 if (i == nb_queue - 1)
2018                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
2019                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
2020         }
2021
2022         /* Write first RX queue to Link list register as the head element */
2023         if (vsi->type != I40E_VSI_SRIOV) {
2024                 uint16_t interval =
2025                         i40e_calc_itr_interval(1, pf->support_multi_driver);
2026
2027                 if (msix_vect == I40E_MISC_VEC_ID) {
2028                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
2029                                        (base_queue <<
2030                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
2031                                        (0x0 <<
2032                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
2033                         I40E_WRITE_REG(hw,
2034                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
2035                                        interval);
2036                 } else {
2037                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
2038                                        (base_queue <<
2039                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
2040                                        (0x0 <<
2041                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2042                         I40E_WRITE_REG(hw,
2043                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
2044                                                        msix_vect - 1),
2045                                        interval);
2046                 }
2047         } else {
2048                 uint32_t reg;
2049
2050                 if (msix_vect == I40E_MISC_VEC_ID) {
2051                         I40E_WRITE_REG(hw,
2052                                        I40E_VPINT_LNKLST0(vsi->user_param),
2053                                        (base_queue <<
2054                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
2055                                        (0x0 <<
2056                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
2057                 } else {
2058                         /* num_msix_vectors_vf needs to minus irq0 */
2059                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
2060                                 vsi->user_param + (msix_vect - 1);
2061
2062                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
2063                                        (base_queue <<
2064                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
2065                                        (0x0 <<
2066                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2067                 }
2068         }
2069
2070         I40E_WRITE_FLUSH(hw);
2071 }
2072
2073 int
2074 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
2075 {
2076         struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
2077         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2078         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
2079         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2080         uint16_t msix_vect = vsi->msix_intr;
2081         uint16_t nb_msix = RTE_MIN(vsi->nb_msix,
2082                                    rte_intr_nb_efd_get(intr_handle));
2083         uint16_t queue_idx = 0;
2084         int record = 0;
2085         int i;
2086
2087         for (i = 0; i < vsi->nb_qps; i++) {
2088                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
2089                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2090         }
2091
2092         /* VF bind interrupt */
2093         if (vsi->type == I40E_VSI_SRIOV) {
2094                 if (vsi->nb_msix == 0) {
2095                         PMD_DRV_LOG(ERR, "No msix resource");
2096                         return -EINVAL;
2097                 }
2098                 __vsi_queues_bind_intr(vsi, msix_vect,
2099                                        vsi->base_queue, vsi->nb_qps,
2100                                        itr_idx);
2101                 return 0;
2102         }
2103
2104         /* PF & VMDq bind interrupt */
2105         if (rte_intr_dp_is_en(intr_handle)) {
2106                 if (vsi->type == I40E_VSI_MAIN) {
2107                         queue_idx = 0;
2108                         record = 1;
2109                 } else if (vsi->type == I40E_VSI_VMDQ2) {
2110                         struct i40e_vsi *main_vsi =
2111                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2112                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
2113                         record = 1;
2114                 }
2115         }
2116
2117         for (i = 0; i < vsi->nb_used_qps; i++) {
2118                 if (vsi->nb_msix == 0) {
2119                         PMD_DRV_LOG(ERR, "No msix resource");
2120                         return -EINVAL;
2121                 } else if (nb_msix <= 1) {
2122                         if (!rte_intr_allow_others(intr_handle))
2123                                 /* allow to share MISC_VEC_ID */
2124                                 msix_vect = I40E_MISC_VEC_ID;
2125
2126                         /* no enough msix_vect, map all to one */
2127                         __vsi_queues_bind_intr(vsi, msix_vect,
2128                                                vsi->base_queue + i,
2129                                                vsi->nb_used_qps - i,
2130                                                itr_idx);
2131                         for (; !!record && i < vsi->nb_used_qps; i++)
2132                                 rte_intr_vec_list_index_set(intr_handle,
2133                                                 queue_idx + i, msix_vect);
2134                         break;
2135                 }
2136                 /* 1:1 queue/msix_vect mapping */
2137                 __vsi_queues_bind_intr(vsi, msix_vect,
2138                                        vsi->base_queue + i, 1,
2139                                        itr_idx);
2140                 if (!!record)
2141                         if (rte_intr_vec_list_index_set(intr_handle,
2142                                                 queue_idx + i, msix_vect))
2143                                 return -rte_errno;
2144
2145                 msix_vect++;
2146                 nb_msix--;
2147         }
2148
2149         return 0;
2150 }
2151
2152 void
2153 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2154 {
2155         struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
2156         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2157         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
2158         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2159         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2160         uint16_t msix_intr, i;
2161
2162         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2163                 for (i = 0; i < vsi->nb_msix; i++) {
2164                         msix_intr = vsi->msix_intr + i;
2165                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2166                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2167                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2168                                 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2169                 }
2170         else
2171                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2172                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
2173                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2174                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2175
2176         I40E_WRITE_FLUSH(hw);
2177 }
2178
2179 void
2180 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2181 {
2182         struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
2183         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2184         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
2185         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2186         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2187         uint16_t msix_intr, i;
2188
2189         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2190                 for (i = 0; i < vsi->nb_msix; i++) {
2191                         msix_intr = vsi->msix_intr + i;
2192                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2193                                        I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2194                 }
2195         else
2196                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2197                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2198
2199         I40E_WRITE_FLUSH(hw);
2200 }
2201
2202 static inline uint8_t
2203 i40e_parse_link_speeds(uint16_t link_speeds)
2204 {
2205         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2206
2207         if (link_speeds & RTE_ETH_LINK_SPEED_40G)
2208                 link_speed |= I40E_LINK_SPEED_40GB;
2209         if (link_speeds & RTE_ETH_LINK_SPEED_25G)
2210                 link_speed |= I40E_LINK_SPEED_25GB;
2211         if (link_speeds & RTE_ETH_LINK_SPEED_20G)
2212                 link_speed |= I40E_LINK_SPEED_20GB;
2213         if (link_speeds & RTE_ETH_LINK_SPEED_10G)
2214                 link_speed |= I40E_LINK_SPEED_10GB;
2215         if (link_speeds & RTE_ETH_LINK_SPEED_1G)
2216                 link_speed |= I40E_LINK_SPEED_1GB;
2217         if (link_speeds & RTE_ETH_LINK_SPEED_100M)
2218                 link_speed |= I40E_LINK_SPEED_100MB;
2219
2220         return link_speed;
2221 }
2222
2223 static int
2224 i40e_phy_conf_link(struct i40e_hw *hw,
2225                    uint8_t abilities,
2226                    uint8_t force_speed,
2227                    bool is_up)
2228 {
2229         enum i40e_status_code status;
2230         struct i40e_aq_get_phy_abilities_resp phy_ab;
2231         struct i40e_aq_set_phy_config phy_conf;
2232         enum i40e_aq_phy_type cnt;
2233         uint8_t avail_speed;
2234         uint32_t phy_type_mask = 0;
2235
2236         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2237                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2238                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2239                         I40E_AQ_PHY_FLAG_LOW_POWER;
2240         int ret = -ENOTSUP;
2241
2242         /* To get phy capabilities of available speeds. */
2243         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2244                                               NULL);
2245         if (status) {
2246                 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2247                                 status);
2248                 return ret;
2249         }
2250         avail_speed = phy_ab.link_speed;
2251
2252         /* To get the current phy config. */
2253         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2254                                               NULL);
2255         if (status) {
2256                 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2257                                 status);
2258                 return ret;
2259         }
2260
2261         /* If link needs to go up and it is in autoneg mode the speed is OK,
2262          * no need to set up again.
2263          */
2264         if (is_up && phy_ab.phy_type != 0 &&
2265                      abilities & I40E_AQ_PHY_AN_ENABLED &&
2266                      phy_ab.link_speed != 0)
2267                 return I40E_SUCCESS;
2268
2269         memset(&phy_conf, 0, sizeof(phy_conf));
2270
2271         /* bits 0-2 use the values from get_phy_abilities_resp */
2272         abilities &= ~mask;
2273         abilities |= phy_ab.abilities & mask;
2274
2275         phy_conf.abilities = abilities;
2276
2277         /* If link needs to go up, but the force speed is not supported,
2278          * Warn users and config the default available speeds.
2279          */
2280         if (is_up && !(force_speed & avail_speed)) {
2281                 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2282                 phy_conf.link_speed = avail_speed;
2283         } else {
2284                 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2285         }
2286
2287         /* PHY type mask needs to include each type except PHY type extension */
2288         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2289                 phy_type_mask |= 1 << cnt;
2290
2291         /* use get_phy_abilities_resp value for the rest */
2292         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2293         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2294                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2295                 I40E_AQ_PHY_TYPE_EXT_25G_LR | I40E_AQ_PHY_TYPE_EXT_25G_AOC |
2296                 I40E_AQ_PHY_TYPE_EXT_25G_ACC) : 0;
2297         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2298         phy_conf.eee_capability = phy_ab.eee_capability;
2299         phy_conf.eeer = phy_ab.eeer_val;
2300         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2301
2302         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2303                     phy_ab.abilities, phy_ab.link_speed);
2304         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
2305                     phy_conf.abilities, phy_conf.link_speed);
2306
2307         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2308         if (status)
2309                 return ret;
2310
2311         return I40E_SUCCESS;
2312 }
2313
2314 static int
2315 i40e_apply_link_speed(struct rte_eth_dev *dev)
2316 {
2317         uint8_t speed;
2318         uint8_t abilities = 0;
2319         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2320         struct rte_eth_conf *conf = &dev->data->dev_conf;
2321
2322         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2323                      I40E_AQ_PHY_LINK_ENABLED;
2324
2325         if (conf->link_speeds == RTE_ETH_LINK_SPEED_AUTONEG) {
2326                 conf->link_speeds = RTE_ETH_LINK_SPEED_40G |
2327                                     RTE_ETH_LINK_SPEED_25G |
2328                                     RTE_ETH_LINK_SPEED_20G |
2329                                     RTE_ETH_LINK_SPEED_10G |
2330                                     RTE_ETH_LINK_SPEED_1G |
2331                                     RTE_ETH_LINK_SPEED_100M;
2332
2333                 abilities |= I40E_AQ_PHY_AN_ENABLED;
2334         } else {
2335                 abilities &= ~I40E_AQ_PHY_AN_ENABLED;
2336         }
2337         speed = i40e_parse_link_speeds(conf->link_speeds);
2338
2339         return i40e_phy_conf_link(hw, abilities, speed, true);
2340 }
2341
2342 static int
2343 i40e_dev_start(struct rte_eth_dev *dev)
2344 {
2345         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2346         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2347         struct i40e_vsi *main_vsi = pf->main_vsi;
2348         int ret, i;
2349         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2350         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
2351         uint32_t intr_vector = 0;
2352         struct i40e_vsi *vsi;
2353         uint16_t nb_rxq, nb_txq;
2354         uint16_t max_frame_size;
2355
2356         hw->adapter_stopped = 0;
2357
2358         rte_intr_disable(intr_handle);
2359
2360         if ((rte_intr_cap_multiple(intr_handle) ||
2361              !RTE_ETH_DEV_SRIOV(dev).active) &&
2362             dev->data->dev_conf.intr_conf.rxq != 0) {
2363                 intr_vector = dev->data->nb_rx_queues;
2364                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2365                 if (ret)
2366                         return ret;
2367         }
2368
2369         if (rte_intr_dp_is_en(intr_handle)) {
2370                 if (rte_intr_vec_list_alloc(intr_handle, "intr_vec",
2371                                                    dev->data->nb_rx_queues)) {
2372                         PMD_INIT_LOG(ERR,
2373                                 "Failed to allocate %d rx_queues intr_vec",
2374                                 dev->data->nb_rx_queues);
2375                         return -ENOMEM;
2376                 }
2377         }
2378
2379         /* Initialize VSI */
2380         ret = i40e_dev_rxtx_init(pf);
2381         if (ret != I40E_SUCCESS) {
2382                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2383                 return ret;
2384         }
2385
2386         /* Map queues with MSIX interrupt */
2387         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2388                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2389         ret = i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2390         if (ret < 0)
2391                 return ret;
2392         i40e_vsi_enable_queues_intr(main_vsi);
2393
2394         /* Map VMDQ VSI queues with MSIX interrupt */
2395         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2396                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2397                 ret = i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2398                                                 I40E_ITR_INDEX_DEFAULT);
2399                 if (ret < 0)
2400                         return ret;
2401                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2402         }
2403
2404         /* Enable all queues which have been configured */
2405         for (nb_rxq = 0; nb_rxq < dev->data->nb_rx_queues; nb_rxq++) {
2406                 ret = i40e_dev_rx_queue_start(dev, nb_rxq);
2407                 if (ret)
2408                         goto rx_err;
2409         }
2410
2411         for (nb_txq = 0; nb_txq < dev->data->nb_tx_queues; nb_txq++) {
2412                 ret = i40e_dev_tx_queue_start(dev, nb_txq);
2413                 if (ret)
2414                         goto tx_err;
2415         }
2416
2417         /* Enable receiving broadcast packets */
2418         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2419         if (ret != I40E_SUCCESS)
2420                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2421
2422         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2423                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2424                                                 true, NULL);
2425                 if (ret != I40E_SUCCESS)
2426                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2427         }
2428
2429         /* Enable the VLAN promiscuous mode. */
2430         if (pf->vfs) {
2431                 for (i = 0; i < pf->vf_num; i++) {
2432                         vsi = pf->vfs[i].vsi;
2433                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2434                                                      true, NULL);
2435                 }
2436         }
2437
2438         /* Enable mac loopback mode */
2439         if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2440             dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2441                 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2442                 if (ret != I40E_SUCCESS) {
2443                         PMD_DRV_LOG(ERR, "fail to set loopback link");
2444                         goto tx_err;
2445                 }
2446         }
2447
2448         /* Apply link configure */
2449         ret = i40e_apply_link_speed(dev);
2450         if (I40E_SUCCESS != ret) {
2451                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2452                 goto tx_err;
2453         }
2454
2455         if (!rte_intr_allow_others(intr_handle)) {
2456                 rte_intr_callback_unregister(intr_handle,
2457                                              i40e_dev_interrupt_handler,
2458                                              (void *)dev);
2459                 /* configure and enable device interrupt */
2460                 i40e_pf_config_irq0(hw, FALSE);
2461                 i40e_pf_enable_irq0(hw);
2462
2463                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2464                         PMD_INIT_LOG(INFO,
2465                                 "lsc won't enable because of no intr multiplex");
2466         } else {
2467                 ret = i40e_aq_set_phy_int_mask(hw,
2468                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2469                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2470                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2471                 if (ret != I40E_SUCCESS)
2472                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2473
2474                 /* Call get_link_info aq command to enable/disable LSE */
2475                 i40e_dev_link_update(dev, 0);
2476         }
2477
2478         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2479                 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2480                                   i40e_dev_alarm_handler, dev);
2481         } else {
2482                 /* enable uio intr after callback register */
2483                 rte_intr_enable(intr_handle);
2484         }
2485
2486         i40e_filter_restore(pf);
2487
2488         if (pf->tm_conf.root && !pf->tm_conf.committed)
2489                 PMD_DRV_LOG(WARNING,
2490                             "please call hierarchy_commit() "
2491                             "before starting the port");
2492
2493         max_frame_size = dev->data->mtu + I40E_ETH_OVERHEAD;
2494         i40e_set_mac_max_frame(dev, max_frame_size);
2495
2496         return I40E_SUCCESS;
2497
2498 tx_err:
2499         for (i = 0; i < nb_txq; i++)
2500                 i40e_dev_tx_queue_stop(dev, i);
2501 rx_err:
2502         for (i = 0; i < nb_rxq; i++)
2503                 i40e_dev_rx_queue_stop(dev, i);
2504
2505         return ret;
2506 }
2507
2508 static int
2509 i40e_dev_stop(struct rte_eth_dev *dev)
2510 {
2511         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2512         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2513         struct i40e_vsi *main_vsi = pf->main_vsi;
2514         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2515         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
2516         int i;
2517
2518         if (hw->adapter_stopped == 1)
2519                 return 0;
2520
2521         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2522                 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2523                 rte_intr_enable(intr_handle);
2524         }
2525
2526         /* Disable all queues */
2527         for (i = 0; i < dev->data->nb_tx_queues; i++)
2528                 i40e_dev_tx_queue_stop(dev, i);
2529
2530         for (i = 0; i < dev->data->nb_rx_queues; i++)
2531                 i40e_dev_rx_queue_stop(dev, i);
2532
2533         /* un-map queues with interrupt registers */
2534         i40e_vsi_disable_queues_intr(main_vsi);
2535         i40e_vsi_queues_unbind_intr(main_vsi);
2536
2537         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2538                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2539                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2540         }
2541
2542         /* Clear all queues and release memory */
2543         i40e_dev_clear_queues(dev);
2544
2545         /* Set link down */
2546         i40e_dev_set_link_down(dev);
2547
2548         if (!rte_intr_allow_others(intr_handle))
2549                 /* resume to the default handler */
2550                 rte_intr_callback_register(intr_handle,
2551                                            i40e_dev_interrupt_handler,
2552                                            (void *)dev);
2553
2554         /* Clean datapath event and queue/vec mapping */
2555         rte_intr_efd_disable(intr_handle);
2556
2557         /* Cleanup vector list */
2558         rte_intr_vec_list_free(intr_handle);
2559
2560         /* reset hierarchy commit */
2561         pf->tm_conf.committed = false;
2562
2563         hw->adapter_stopped = 1;
2564         dev->data->dev_started = 0;
2565
2566         pf->adapter->rss_reta_updated = 0;
2567
2568         return 0;
2569 }
2570
2571 static int
2572 i40e_dev_close(struct rte_eth_dev *dev)
2573 {
2574         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2575         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2576         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2577         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
2578         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
2579         struct i40e_filter_control_settings settings;
2580         struct rte_flow *p_flow;
2581         uint32_t reg;
2582         int i;
2583         int ret;
2584         uint8_t aq_fail = 0;
2585         int retries = 0;
2586
2587         PMD_INIT_FUNC_TRACE();
2588         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2589                 return 0;
2590
2591         /*
2592          * It is a workaround, if the double VLAN is disabled when
2593          * the program exits, an abnormal error will occur on the
2594          * NIC. Need to enable double VLAN when dev is closed.
2595          */
2596         if (pf->fw8_3gt) {
2597                 if (!(rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_EXTEND)) {
2598                         rxmode->offloads |= RTE_ETH_RX_OFFLOAD_VLAN_EXTEND;
2599                         i40e_vlan_offload_set(dev, RTE_ETH_VLAN_EXTEND_MASK);
2600                 }
2601         }
2602
2603         ret = rte_eth_switch_domain_free(pf->switch_domain_id);
2604         if (ret)
2605                 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
2606
2607
2608         ret = i40e_dev_stop(dev);
2609
2610         i40e_dev_free_queues(dev);
2611
2612         /* Disable interrupt */
2613         i40e_pf_disable_irq0(hw);
2614         rte_intr_disable(intr_handle);
2615
2616         /*
2617          * Only legacy filter API needs the following fdir config. So when the
2618          * legacy filter API is deprecated, the following code should also be
2619          * removed.
2620          */
2621         i40e_fdir_teardown(pf);
2622
2623         /* shutdown and destroy the HMC */
2624         i40e_shutdown_lan_hmc(hw);
2625
2626         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2627                 i40e_vsi_release(pf->vmdq[i].vsi);
2628                 pf->vmdq[i].vsi = NULL;
2629         }
2630         rte_free(pf->vmdq);
2631         pf->vmdq = NULL;
2632
2633         /* release all the existing VSIs and VEBs */
2634         i40e_vsi_release(pf->main_vsi);
2635
2636         /* shutdown the adminq */
2637         i40e_aq_queue_shutdown(hw, true);
2638         i40e_shutdown_adminq(hw);
2639
2640         i40e_res_pool_destroy(&pf->qp_pool);
2641         i40e_res_pool_destroy(&pf->msix_pool);
2642
2643         /* Disable flexible payload in global configuration */
2644         if (!pf->support_multi_driver)
2645                 i40e_flex_payload_reg_set_default(hw);
2646
2647         /* force a PF reset to clean anything leftover */
2648         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2649         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2650                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2651         I40E_WRITE_FLUSH(hw);
2652
2653         /* Clear PXE mode */
2654         i40e_clear_pxe_mode(hw);
2655
2656         /* Unconfigure filter control */
2657         memset(&settings, 0, sizeof(settings));
2658         ret = i40e_set_filter_control(hw, &settings);
2659         if (ret)
2660                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
2661                                         ret);
2662
2663         /* Disable flow control */
2664         hw->fc.requested_mode = I40E_FC_NONE;
2665         i40e_set_fc(hw, &aq_fail, TRUE);
2666
2667         /* uninitialize pf host driver */
2668         i40e_pf_host_uninit(dev);
2669
2670         do {
2671                 ret = rte_intr_callback_unregister(intr_handle,
2672                                 i40e_dev_interrupt_handler, dev);
2673                 if (ret >= 0 || ret == -ENOENT) {
2674                         break;
2675                 } else if (ret != -EAGAIN) {
2676                         PMD_INIT_LOG(ERR,
2677                                  "intr callback unregister failed: %d",
2678                                  ret);
2679                 }
2680                 i40e_msec_delay(500);
2681         } while (retries++ < 5);
2682
2683         i40e_rm_ethtype_filter_list(pf);
2684         i40e_rm_tunnel_filter_list(pf);
2685         i40e_rm_fdir_filter_list(pf);
2686
2687         /* Remove all flows */
2688         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
2689                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
2690                 /* Do not free FDIR flows since they are static allocated */
2691                 if (p_flow->filter_type != RTE_ETH_FILTER_FDIR)
2692                         rte_free(p_flow);
2693         }
2694
2695         /* release the fdir static allocated memory */
2696         i40e_fdir_memory_cleanup(pf);
2697
2698         /* Remove all Traffic Manager configuration */
2699         i40e_tm_conf_uninit(dev);
2700
2701         i40e_clear_automask(pf);
2702
2703         hw->adapter_closed = 1;
2704         return ret;
2705 }
2706
2707 /*
2708  * Reset PF device only to re-initialize resources in PMD layer
2709  */
2710 static int
2711 i40e_dev_reset(struct rte_eth_dev *dev)
2712 {
2713         int ret;
2714
2715         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2716          * its VF to make them align with it. The detailed notification
2717          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2718          * To avoid unexpected behavior in VF, currently reset of PF with
2719          * SR-IOV activation is not supported. It might be supported later.
2720          */
2721         if (dev->data->sriov.active)
2722                 return -ENOTSUP;
2723
2724         ret = eth_i40e_dev_uninit(dev);
2725         if (ret)
2726                 return ret;
2727
2728         ret = eth_i40e_dev_init(dev, NULL);
2729
2730         return ret;
2731 }
2732
2733 static int
2734 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2735 {
2736         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2737         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2738         struct i40e_vsi *vsi = pf->main_vsi;
2739         int status;
2740
2741         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2742                                                      true, NULL, true);
2743         if (status != I40E_SUCCESS) {
2744                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2745                 return -EAGAIN;
2746         }
2747
2748         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2749                                                         TRUE, NULL);
2750         if (status != I40E_SUCCESS) {
2751                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2752                 /* Rollback unicast promiscuous mode */
2753                 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2754                                                     false, NULL, true);
2755                 return -EAGAIN;
2756         }
2757
2758         return 0;
2759 }
2760
2761 static int
2762 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2763 {
2764         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2765         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2766         struct i40e_vsi *vsi = pf->main_vsi;
2767         int status;
2768
2769         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2770                                                      false, NULL, true);
2771         if (status != I40E_SUCCESS) {
2772                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2773                 return -EAGAIN;
2774         }
2775
2776         /* must remain in all_multicast mode */
2777         if (dev->data->all_multicast == 1)
2778                 return 0;
2779
2780         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2781                                                         false, NULL);
2782         if (status != I40E_SUCCESS) {
2783                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2784                 /* Rollback unicast promiscuous mode */
2785                 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2786                                                     true, NULL, true);
2787                 return -EAGAIN;
2788         }
2789
2790         return 0;
2791 }
2792
2793 static int
2794 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2795 {
2796         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2797         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2798         struct i40e_vsi *vsi = pf->main_vsi;
2799         int ret;
2800
2801         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2802         if (ret != I40E_SUCCESS) {
2803                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2804                 return -EAGAIN;
2805         }
2806
2807         return 0;
2808 }
2809
2810 static int
2811 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2812 {
2813         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2814         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2815         struct i40e_vsi *vsi = pf->main_vsi;
2816         int ret;
2817
2818         if (dev->data->promiscuous == 1)
2819                 return 0; /* must remain in all_multicast mode */
2820
2821         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2822                                 vsi->seid, FALSE, NULL);
2823         if (ret != I40E_SUCCESS) {
2824                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2825                 return -EAGAIN;
2826         }
2827
2828         return 0;
2829 }
2830
2831 /*
2832  * Set device link up.
2833  */
2834 static int
2835 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2836 {
2837         /* re-apply link speed setting */
2838         return i40e_apply_link_speed(dev);
2839 }
2840
2841 /*
2842  * Set device link down.
2843  */
2844 static int
2845 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2846 {
2847         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2848         uint8_t abilities = 0;
2849         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2850
2851         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2852         return i40e_phy_conf_link(hw, abilities, speed, false);
2853 }
2854
2855 #define CHECK_INTERVAL             100  /* 100ms */
2856 #define MAX_REPEAT_TIME            10  /* 1s (10 * 100ms) in total */
2857
2858 static __rte_always_inline void
2859 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2860 {
2861 /* Link status registers and values*/
2862 #define I40E_REG_LINK_UP                0x40000080
2863 #define I40E_PRTMAC_MACC                0x001E24E0
2864 #define I40E_REG_MACC_25GB              0x00020000
2865 #define I40E_REG_SPEED_MASK             0x38000000
2866 #define I40E_REG_SPEED_0                0x00000000
2867 #define I40E_REG_SPEED_1                0x08000000
2868 #define I40E_REG_SPEED_2                0x10000000
2869 #define I40E_REG_SPEED_3                0x18000000
2870 #define I40E_REG_SPEED_4                0x20000000
2871         uint32_t link_speed;
2872         uint32_t reg_val;
2873
2874         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA(0));
2875         link_speed = reg_val & I40E_REG_SPEED_MASK;
2876         reg_val &= I40E_REG_LINK_UP;
2877         link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2878
2879         if (unlikely(link->link_status == 0))
2880                 return;
2881
2882         /* Parse the link status */
2883         switch (link_speed) {
2884         case I40E_REG_SPEED_0:
2885                 link->link_speed = RTE_ETH_SPEED_NUM_100M;
2886                 break;
2887         case I40E_REG_SPEED_1:
2888                 link->link_speed = RTE_ETH_SPEED_NUM_1G;
2889                 break;
2890         case I40E_REG_SPEED_2:
2891                 if (hw->mac.type == I40E_MAC_X722)
2892                         link->link_speed = RTE_ETH_SPEED_NUM_2_5G;
2893                 else
2894                         link->link_speed = RTE_ETH_SPEED_NUM_10G;
2895                 break;
2896         case I40E_REG_SPEED_3:
2897                 if (hw->mac.type == I40E_MAC_X722) {
2898                         link->link_speed = RTE_ETH_SPEED_NUM_5G;
2899                 } else {
2900                         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2901
2902                         if (reg_val & I40E_REG_MACC_25GB)
2903                                 link->link_speed = RTE_ETH_SPEED_NUM_25G;
2904                         else
2905                                 link->link_speed = RTE_ETH_SPEED_NUM_40G;
2906                 }
2907                 break;
2908         case I40E_REG_SPEED_4:
2909                 if (hw->mac.type == I40E_MAC_X722)
2910                         link->link_speed = RTE_ETH_SPEED_NUM_10G;
2911                 else
2912                         link->link_speed = RTE_ETH_SPEED_NUM_20G;
2913                 break;
2914         default:
2915                 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2916                 break;
2917         }
2918 }
2919
2920 static __rte_always_inline void
2921 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2922         bool enable_lse, int wait_to_complete)
2923 {
2924         uint32_t rep_cnt = MAX_REPEAT_TIME;
2925         struct i40e_link_status link_status;
2926         int status;
2927
2928         memset(&link_status, 0, sizeof(link_status));
2929
2930         do {
2931                 memset(&link_status, 0, sizeof(link_status));
2932
2933                 /* Get link status information from hardware */
2934                 status = i40e_aq_get_link_info(hw, enable_lse,
2935                                                 &link_status, NULL);
2936                 if (unlikely(status != I40E_SUCCESS)) {
2937                         link->link_speed = RTE_ETH_SPEED_NUM_NONE;
2938                         link->link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
2939                         PMD_DRV_LOG(ERR, "Failed to get link info");
2940                         return;
2941                 }
2942
2943                 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2944                 if (!wait_to_complete || link->link_status)
2945                         break;
2946
2947                 rte_delay_ms(CHECK_INTERVAL);
2948         } while (--rep_cnt);
2949
2950         /* Parse the link status */
2951         switch (link_status.link_speed) {
2952         case I40E_LINK_SPEED_100MB:
2953                 link->link_speed = RTE_ETH_SPEED_NUM_100M;
2954                 break;
2955         case I40E_LINK_SPEED_1GB:
2956                 link->link_speed = RTE_ETH_SPEED_NUM_1G;
2957                 break;
2958         case I40E_LINK_SPEED_10GB:
2959                 link->link_speed = RTE_ETH_SPEED_NUM_10G;
2960                 break;
2961         case I40E_LINK_SPEED_20GB:
2962                 link->link_speed = RTE_ETH_SPEED_NUM_20G;
2963                 break;
2964         case I40E_LINK_SPEED_25GB:
2965                 link->link_speed = RTE_ETH_SPEED_NUM_25G;
2966                 break;
2967         case I40E_LINK_SPEED_40GB:
2968                 link->link_speed = RTE_ETH_SPEED_NUM_40G;
2969                 break;
2970         default:
2971                 if (link->link_status)
2972                         link->link_speed = RTE_ETH_SPEED_NUM_UNKNOWN;
2973                 else
2974                         link->link_speed = RTE_ETH_SPEED_NUM_NONE;
2975                 break;
2976         }
2977 }
2978
2979 int
2980 i40e_dev_link_update(struct rte_eth_dev *dev,
2981                      int wait_to_complete)
2982 {
2983         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2984         struct rte_eth_link link;
2985         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2986         int ret;
2987
2988         memset(&link, 0, sizeof(link));
2989
2990         /* i40e uses full duplex only */
2991         link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX;
2992         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2993                         RTE_ETH_LINK_SPEED_FIXED);
2994
2995         if (!wait_to_complete && !enable_lse)
2996                 update_link_reg(hw, &link);
2997         else
2998                 update_link_aq(hw, &link, enable_lse, wait_to_complete);
2999
3000         if (hw->switch_dev)
3001                 rte_eth_linkstatus_get(hw->switch_dev, &link);
3002
3003         ret = rte_eth_linkstatus_set(dev, &link);
3004         i40e_notify_all_vfs_link_status(dev);
3005
3006         return ret;
3007 }
3008
3009 static void
3010 i40e_stat_update_48_in_64(struct i40e_hw *hw, uint32_t hireg,
3011                           uint32_t loreg, bool offset_loaded, uint64_t *offset,
3012                           uint64_t *stat, uint64_t *prev_stat)
3013 {
3014         i40e_stat_update_48(hw, hireg, loreg, offset_loaded, offset, stat);
3015         /* enlarge the limitation when statistics counters overflowed */
3016         if (offset_loaded) {
3017                 if (I40E_RXTX_BYTES_L_48_BIT(*prev_stat) > *stat)
3018                         *stat += (uint64_t)1 << I40E_48_BIT_WIDTH;
3019                 *stat += I40E_RXTX_BYTES_H_16_BIT(*prev_stat);
3020         }
3021         *prev_stat = *stat;
3022 }
3023
3024 /* Get all the statistics of a VSI */
3025 void
3026 i40e_update_vsi_stats(struct i40e_vsi *vsi)
3027 {
3028         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
3029         struct i40e_eth_stats *nes = &vsi->eth_stats;
3030         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3031         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
3032
3033         i40e_stat_update_48_in_64(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
3034                                   vsi->offset_loaded, &oes->rx_bytes,
3035                                   &nes->rx_bytes, &vsi->prev_rx_bytes);
3036         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
3037                             vsi->offset_loaded, &oes->rx_unicast,
3038                             &nes->rx_unicast);
3039         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
3040                             vsi->offset_loaded, &oes->rx_multicast,
3041                             &nes->rx_multicast);
3042         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
3043                             vsi->offset_loaded, &oes->rx_broadcast,
3044                             &nes->rx_broadcast);
3045         /* exclude CRC bytes */
3046         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
3047                 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
3048
3049         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
3050                             &oes->rx_discards, &nes->rx_discards);
3051         /* GLV_REPC not supported */
3052         /* GLV_RMPC not supported */
3053         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
3054                             &oes->rx_unknown_protocol,
3055                             &nes->rx_unknown_protocol);
3056         i40e_stat_update_48_in_64(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
3057                                   vsi->offset_loaded, &oes->tx_bytes,
3058                                   &nes->tx_bytes, &vsi->prev_tx_bytes);
3059         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
3060                             vsi->offset_loaded, &oes->tx_unicast,
3061                             &nes->tx_unicast);
3062         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
3063                             vsi->offset_loaded, &oes->tx_multicast,
3064                             &nes->tx_multicast);
3065         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
3066                             vsi->offset_loaded,  &oes->tx_broadcast,
3067                             &nes->tx_broadcast);
3068         /* GLV_TDPC not supported */
3069         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
3070                             &oes->tx_errors, &nes->tx_errors);
3071         vsi->offset_loaded = true;
3072
3073         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
3074                     vsi->vsi_id);
3075         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
3076         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
3077         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
3078         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
3079         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
3080         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3081                     nes->rx_unknown_protocol);
3082         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
3083         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
3084         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
3085         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
3086         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
3087         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
3088         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
3089                     vsi->vsi_id);
3090 }
3091
3092 static void
3093 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
3094 {
3095         unsigned int i;
3096         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3097         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
3098
3099         /* Get rx/tx bytes of internal transfer packets */
3100         i40e_stat_update_48_in_64(hw, I40E_GLV_GORCH(hw->port),
3101                                   I40E_GLV_GORCL(hw->port),
3102                                   pf->offset_loaded,
3103                                   &pf->internal_stats_offset.rx_bytes,
3104                                   &pf->internal_stats.rx_bytes,
3105                                   &pf->internal_prev_rx_bytes);
3106         i40e_stat_update_48_in_64(hw, I40E_GLV_GOTCH(hw->port),
3107                                   I40E_GLV_GOTCL(hw->port),
3108                                   pf->offset_loaded,
3109                                   &pf->internal_stats_offset.tx_bytes,
3110                                   &pf->internal_stats.tx_bytes,
3111                                   &pf->internal_prev_tx_bytes);
3112         /* Get total internal rx packet count */
3113         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
3114                             I40E_GLV_UPRCL(hw->port),
3115                             pf->offset_loaded,
3116                             &pf->internal_stats_offset.rx_unicast,
3117                             &pf->internal_stats.rx_unicast);
3118         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
3119                             I40E_GLV_MPRCL(hw->port),
3120                             pf->offset_loaded,
3121                             &pf->internal_stats_offset.rx_multicast,
3122                             &pf->internal_stats.rx_multicast);
3123         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
3124                             I40E_GLV_BPRCL(hw->port),
3125                             pf->offset_loaded,
3126                             &pf->internal_stats_offset.rx_broadcast,
3127                             &pf->internal_stats.rx_broadcast);
3128         /* Get total internal tx packet count */
3129         i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
3130                             I40E_GLV_UPTCL(hw->port),
3131                             pf->offset_loaded,
3132                             &pf->internal_stats_offset.tx_unicast,
3133                             &pf->internal_stats.tx_unicast);
3134         i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
3135                             I40E_GLV_MPTCL(hw->port),
3136                             pf->offset_loaded,
3137                             &pf->internal_stats_offset.tx_multicast,
3138                             &pf->internal_stats.tx_multicast);
3139         i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
3140                             I40E_GLV_BPTCL(hw->port),
3141                             pf->offset_loaded,
3142                             &pf->internal_stats_offset.tx_broadcast,
3143                             &pf->internal_stats.tx_broadcast);
3144
3145         /* exclude CRC size */
3146         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
3147                 pf->internal_stats.rx_multicast +
3148                 pf->internal_stats.rx_broadcast) * RTE_ETHER_CRC_LEN;
3149
3150         /* Get statistics of struct i40e_eth_stats */
3151         i40e_stat_update_48_in_64(hw, I40E_GLPRT_GORCH(hw->port),
3152                                   I40E_GLPRT_GORCL(hw->port),
3153                                   pf->offset_loaded, &os->eth.rx_bytes,
3154                                   &ns->eth.rx_bytes, &pf->prev_rx_bytes);
3155         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
3156                             I40E_GLPRT_UPRCL(hw->port),
3157                             pf->offset_loaded, &os->eth.rx_unicast,
3158                             &ns->eth.rx_unicast);
3159         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
3160                             I40E_GLPRT_MPRCL(hw->port),
3161                             pf->offset_loaded, &os->eth.rx_multicast,
3162                             &ns->eth.rx_multicast);
3163         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
3164                             I40E_GLPRT_BPRCL(hw->port),
3165                             pf->offset_loaded, &os->eth.rx_broadcast,
3166                             &ns->eth.rx_broadcast);
3167         /* Workaround: CRC size should not be included in byte statistics,
3168          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
3169          * packet.
3170          */
3171         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
3172                 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
3173
3174         /* exclude internal rx bytes
3175          * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
3176          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
3177          * value.
3178          * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
3179          */
3180         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
3181                 ns->eth.rx_bytes = 0;
3182         else
3183                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
3184
3185         if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
3186                 ns->eth.rx_unicast = 0;
3187         else
3188                 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
3189
3190         if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
3191                 ns->eth.rx_multicast = 0;
3192         else
3193                 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
3194
3195         if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
3196                 ns->eth.rx_broadcast = 0;
3197         else
3198                 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
3199
3200         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
3201                             pf->offset_loaded, &os->eth.rx_discards,
3202                             &ns->eth.rx_discards);
3203         /* GLPRT_REPC not supported */
3204         /* GLPRT_RMPC not supported */
3205         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
3206                             pf->offset_loaded,
3207                             &os->eth.rx_unknown_protocol,
3208                             &ns->eth.rx_unknown_protocol);
3209         i40e_stat_update_48(hw, I40E_GL_RXERR1_H(hw->pf_id + I40E_MAX_VF),
3210                             I40E_GL_RXERR1_L(hw->pf_id + I40E_MAX_VF),
3211                             pf->offset_loaded, &pf->rx_err1_offset,
3212                             &pf->rx_err1);
3213         i40e_stat_update_48_in_64(hw, I40E_GLPRT_GOTCH(hw->port),
3214                                   I40E_GLPRT_GOTCL(hw->port),
3215                                   pf->offset_loaded, &os->eth.tx_bytes,
3216                                   &ns->eth.tx_bytes, &pf->prev_tx_bytes);
3217         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
3218                             I40E_GLPRT_UPTCL(hw->port),
3219                             pf->offset_loaded, &os->eth.tx_unicast,
3220                             &ns->eth.tx_unicast);
3221         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
3222                             I40E_GLPRT_MPTCL(hw->port),
3223                             pf->offset_loaded, &os->eth.tx_multicast,
3224                             &ns->eth.tx_multicast);
3225         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
3226                             I40E_GLPRT_BPTCL(hw->port),
3227                             pf->offset_loaded, &os->eth.tx_broadcast,
3228                             &ns->eth.tx_broadcast);
3229         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3230                 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3231
3232         /* exclude internal tx bytes
3233          * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
3234          * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
3235          * value.
3236          * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
3237          */
3238         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
3239                 ns->eth.tx_bytes = 0;
3240         else
3241                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3242
3243         if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3244                 ns->eth.tx_unicast = 0;
3245         else
3246                 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3247
3248         if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3249                 ns->eth.tx_multicast = 0;
3250         else
3251                 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3252
3253         if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3254                 ns->eth.tx_broadcast = 0;
3255         else
3256                 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3257
3258         /* GLPRT_TEPC not supported */
3259
3260         /* additional port specific stats */
3261         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3262                             pf->offset_loaded, &os->tx_dropped_link_down,
3263                             &ns->tx_dropped_link_down);
3264         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3265                             pf->offset_loaded, &os->crc_errors,
3266                             &ns->crc_errors);
3267         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3268                             pf->offset_loaded, &os->illegal_bytes,
3269                             &ns->illegal_bytes);
3270         /* GLPRT_ERRBC not supported */
3271         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3272                             pf->offset_loaded, &os->mac_local_faults,
3273                             &ns->mac_local_faults);
3274         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3275                             pf->offset_loaded, &os->mac_remote_faults,
3276                             &ns->mac_remote_faults);
3277         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3278                             pf->offset_loaded, &os->rx_length_errors,
3279                             &ns->rx_length_errors);
3280         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3281                             pf->offset_loaded, &os->link_xon_rx,
3282                             &ns->link_xon_rx);
3283         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3284                             pf->offset_loaded, &os->link_xoff_rx,
3285                             &ns->link_xoff_rx);
3286         for (i = 0; i < 8; i++) {
3287                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3288                                     pf->offset_loaded,
3289                                     &os->priority_xon_rx[i],
3290                                     &ns->priority_xon_rx[i]);
3291                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3292                                     pf->offset_loaded,
3293                                     &os->priority_xoff_rx[i],
3294                                     &ns->priority_xoff_rx[i]);
3295         }
3296         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3297                             pf->offset_loaded, &os->link_xon_tx,
3298                             &ns->link_xon_tx);
3299         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3300                             pf->offset_loaded, &os->link_xoff_tx,
3301                             &ns->link_xoff_tx);
3302         for (i = 0; i < 8; i++) {
3303                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3304                                     pf->offset_loaded,
3305                                     &os->priority_xon_tx[i],
3306                                     &ns->priority_xon_tx[i]);
3307                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3308                                     pf->offset_loaded,
3309                                     &os->priority_xoff_tx[i],
3310                                     &ns->priority_xoff_tx[i]);
3311                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3312                                     pf->offset_loaded,
3313                                     &os->priority_xon_2_xoff[i],
3314                                     &ns->priority_xon_2_xoff[i]);
3315         }
3316         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3317                             I40E_GLPRT_PRC64L(hw->port),
3318                             pf->offset_loaded, &os->rx_size_64,
3319                             &ns->rx_size_64);
3320         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3321                             I40E_GLPRT_PRC127L(hw->port),
3322                             pf->offset_loaded, &os->rx_size_127,
3323                             &ns->rx_size_127);
3324         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3325                             I40E_GLPRT_PRC255L(hw->port),
3326                             pf->offset_loaded, &os->rx_size_255,
3327                             &ns->rx_size_255);
3328         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3329                             I40E_GLPRT_PRC511L(hw->port),
3330                             pf->offset_loaded, &os->rx_size_511,
3331                             &ns->rx_size_511);
3332         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3333                             I40E_GLPRT_PRC1023L(hw->port),
3334                             pf->offset_loaded, &os->rx_size_1023,
3335                             &ns->rx_size_1023);
3336         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3337                             I40E_GLPRT_PRC1522L(hw->port),
3338                             pf->offset_loaded, &os->rx_size_1522,
3339                             &ns->rx_size_1522);
3340         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3341                             I40E_GLPRT_PRC9522L(hw->port),
3342                             pf->offset_loaded, &os->rx_size_big,
3343                             &ns->rx_size_big);
3344         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3345                             pf->offset_loaded, &os->rx_undersize,
3346                             &ns->rx_undersize);
3347         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3348                             pf->offset_loaded, &os->rx_fragments,
3349                             &ns->rx_fragments);
3350         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3351                             pf->offset_loaded, &os->rx_oversize,
3352                             &ns->rx_oversize);
3353         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3354                             pf->offset_loaded, &os->rx_jabber,
3355                             &ns->rx_jabber);
3356         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3357                             I40E_GLPRT_PTC64L(hw->port),
3358                             pf->offset_loaded, &os->tx_size_64,
3359                             &ns->tx_size_64);
3360         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3361                             I40E_GLPRT_PTC127L(hw->port),
3362                             pf->offset_loaded, &os->tx_size_127,
3363                             &ns->tx_size_127);
3364         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3365                             I40E_GLPRT_PTC255L(hw->port),
3366                             pf->offset_loaded, &os->tx_size_255,
3367                             &ns->tx_size_255);
3368         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3369                             I40E_GLPRT_PTC511L(hw->port),
3370                             pf->offset_loaded, &os->tx_size_511,
3371                             &ns->tx_size_511);
3372         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3373                             I40E_GLPRT_PTC1023L(hw->port),
3374                             pf->offset_loaded, &os->tx_size_1023,
3375                             &ns->tx_size_1023);
3376         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3377                             I40E_GLPRT_PTC1522L(hw->port),
3378                             pf->offset_loaded, &os->tx_size_1522,
3379                             &ns->tx_size_1522);
3380         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3381                             I40E_GLPRT_PTC9522L(hw->port),
3382                             pf->offset_loaded, &os->tx_size_big,
3383                             &ns->tx_size_big);
3384         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3385                            pf->offset_loaded,
3386                            &os->fd_sb_match, &ns->fd_sb_match);
3387         /* GLPRT_MSPDC not supported */
3388         /* GLPRT_XEC not supported */
3389
3390         pf->offset_loaded = true;
3391
3392         if (pf->main_vsi)
3393                 i40e_update_vsi_stats(pf->main_vsi);
3394 }
3395
3396 /* Get all statistics of a port */
3397 static int
3398 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3399 {
3400         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3401         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3402         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3403         struct i40e_vsi *vsi;
3404         unsigned i;
3405
3406         /* call read registers - updates values, now write them to struct */
3407         i40e_read_stats_registers(pf, hw);
3408
3409         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3410                         pf->main_vsi->eth_stats.rx_multicast +
3411                         pf->main_vsi->eth_stats.rx_broadcast -
3412                         pf->main_vsi->eth_stats.rx_discards -
3413                         pf->rx_err1;
3414         stats->opackets = ns->eth.tx_unicast +
3415                         ns->eth.tx_multicast +
3416                         ns->eth.tx_broadcast;
3417         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
3418         stats->obytes   = ns->eth.tx_bytes;
3419         stats->oerrors  = ns->eth.tx_errors +
3420                         pf->main_vsi->eth_stats.tx_errors;
3421
3422         /* Rx Errors */
3423         stats->imissed  = ns->eth.rx_discards +
3424                         pf->main_vsi->eth_stats.rx_discards;
3425         stats->ierrors  = ns->crc_errors +
3426                         ns->rx_length_errors + ns->rx_undersize +
3427                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber +
3428                         pf->rx_err1;
3429
3430         if (pf->vfs) {
3431                 for (i = 0; i < pf->vf_num; i++) {
3432                         vsi = pf->vfs[i].vsi;
3433                         i40e_update_vsi_stats(vsi);
3434
3435                         stats->ipackets += (vsi->eth_stats.rx_unicast +
3436                                         vsi->eth_stats.rx_multicast +
3437                                         vsi->eth_stats.rx_broadcast -
3438                                         vsi->eth_stats.rx_discards);
3439                         stats->ibytes   += vsi->eth_stats.rx_bytes;
3440                         stats->oerrors  += vsi->eth_stats.tx_errors;
3441                         stats->imissed  += vsi->eth_stats.rx_discards;
3442                 }
3443         }
3444
3445         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3446         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
3447         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
3448         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
3449         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
3450         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
3451         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3452                     ns->eth.rx_unknown_protocol);
3453         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
3454         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
3455         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
3456         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
3457         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
3458         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
3459
3460         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
3461                     ns->tx_dropped_link_down);
3462         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
3463         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
3464                     ns->illegal_bytes);
3465         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
3466         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
3467                     ns->mac_local_faults);
3468         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
3469                     ns->mac_remote_faults);
3470         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
3471                     ns->rx_length_errors);
3472         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
3473         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
3474         for (i = 0; i < 8; i++) {
3475                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
3476                                 i, ns->priority_xon_rx[i]);
3477                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
3478                                 i, ns->priority_xoff_rx[i]);
3479         }
3480         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
3481         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
3482         for (i = 0; i < 8; i++) {
3483                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
3484                                 i, ns->priority_xon_tx[i]);
3485                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
3486                                 i, ns->priority_xoff_tx[i]);
3487                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
3488                                 i, ns->priority_xon_2_xoff[i]);
3489         }
3490         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
3491         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
3492         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
3493         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
3494         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
3495         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
3496         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
3497         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
3498         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
3499         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
3500         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
3501         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
3502         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
3503         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
3504         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
3505         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
3506         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
3507         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
3508         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3509                         ns->mac_short_packet_dropped);
3510         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
3511                     ns->checksum_error);
3512         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
3513         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3514         return 0;
3515 }
3516
3517 /* Reset the statistics */
3518 static int
3519 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3520 {
3521         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3522         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3523
3524         /* Mark PF and VSI stats to update the offset, aka "reset" */
3525         pf->offset_loaded = false;
3526         if (pf->main_vsi)
3527                 pf->main_vsi->offset_loaded = false;
3528
3529         /* read the stats, reading current register values into offset */
3530         i40e_read_stats_registers(pf, hw);
3531
3532         return 0;
3533 }
3534
3535 static uint32_t
3536 i40e_xstats_calc_num(void)
3537 {
3538         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3539                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3540                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3541 }
3542
3543 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3544                                      struct rte_eth_xstat_name *xstats_names,
3545                                      __rte_unused unsigned limit)
3546 {
3547         unsigned count = 0;
3548         unsigned i, prio;
3549
3550         if (xstats_names == NULL)
3551                 return i40e_xstats_calc_num();
3552
3553         /* Note: limit checked in rte_eth_xstats_names() */
3554
3555         /* Get stats from i40e_eth_stats struct */
3556         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3557                 strlcpy(xstats_names[count].name,
3558                         rte_i40e_stats_strings[i].name,
3559                         sizeof(xstats_names[count].name));
3560                 count++;
3561         }
3562
3563         /* Get individual stats from i40e_hw_port struct */
3564         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3565                 strlcpy(xstats_names[count].name,
3566                         rte_i40e_hw_port_strings[i].name,
3567                         sizeof(xstats_names[count].name));
3568                 count++;
3569         }
3570
3571         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3572                 for (prio = 0; prio < 8; prio++) {
3573                         snprintf(xstats_names[count].name,
3574                                  sizeof(xstats_names[count].name),
3575                                  "rx_priority%u_%s", prio,
3576                                  rte_i40e_rxq_prio_strings[i].name);
3577                         count++;
3578                 }
3579         }
3580
3581         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3582                 for (prio = 0; prio < 8; prio++) {
3583                         snprintf(xstats_names[count].name,
3584                                  sizeof(xstats_names[count].name),
3585                                  "tx_priority%u_%s", prio,
3586                                  rte_i40e_txq_prio_strings[i].name);
3587                         count++;
3588                 }
3589         }
3590         return count;
3591 }
3592
3593 static int
3594 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3595                     unsigned n)
3596 {
3597         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3598         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3599         unsigned i, count, prio;
3600         struct i40e_hw_port_stats *hw_stats = &pf->stats;
3601
3602         count = i40e_xstats_calc_num();
3603         if (n < count)
3604                 return count;
3605
3606         i40e_read_stats_registers(pf, hw);
3607
3608         if (xstats == NULL)
3609                 return 0;
3610
3611         count = 0;
3612
3613         /* Get stats from i40e_eth_stats struct */
3614         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3615                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3616                         rte_i40e_stats_strings[i].offset);
3617                 xstats[count].id = count;
3618                 count++;
3619         }
3620
3621         /* Get individual stats from i40e_hw_port struct */
3622         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3623                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3624                         rte_i40e_hw_port_strings[i].offset);
3625                 xstats[count].id = count;
3626                 count++;
3627         }
3628
3629         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3630                 for (prio = 0; prio < 8; prio++) {
3631                         xstats[count].value =
3632                                 *(uint64_t *)(((char *)hw_stats) +
3633                                 rte_i40e_rxq_prio_strings[i].offset +
3634                                 (sizeof(uint64_t) * prio));
3635                         xstats[count].id = count;
3636                         count++;
3637                 }
3638         }
3639
3640         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3641                 for (prio = 0; prio < 8; prio++) {
3642                         xstats[count].value =
3643                                 *(uint64_t *)(((char *)hw_stats) +
3644                                 rte_i40e_txq_prio_strings[i].offset +
3645                                 (sizeof(uint64_t) * prio));
3646                         xstats[count].id = count;
3647                         count++;
3648                 }
3649         }
3650
3651         return count;
3652 }
3653
3654 static int
3655 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3656 {
3657         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3658         u32 full_ver;
3659         u8 ver, patch;
3660         u16 build;
3661         int ret;
3662
3663         full_ver = hw->nvm.oem_ver;
3664         ver = (u8)(full_ver >> 24);
3665         build = (u16)((full_ver >> 8) & 0xffff);
3666         patch = (u8)(full_ver & 0xff);
3667
3668         ret = snprintf(fw_version, fw_size,
3669                  "%d.%d%d 0x%08x %d.%d.%d",
3670                  ((hw->nvm.version >> 12) & 0xf),
3671                  ((hw->nvm.version >> 4) & 0xff),
3672                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
3673                  ver, build, patch);
3674         if (ret < 0)
3675                 return -EINVAL;
3676
3677         ret += 1; /* add the size of '\0' */
3678         if (fw_size < (size_t)ret)
3679                 return ret;
3680         else
3681                 return 0;
3682 }
3683
3684 /*
3685  * When using NVM 6.01(for X710 XL710 XXV710)/3.33(for X722) or later,
3686  * the Rx data path does not hang if the FW LLDP is stopped.
3687  * return true if lldp need to stop
3688  * return false if we cannot disable the LLDP to avoid Rx data path blocking.
3689  */
3690 static bool
3691 i40e_need_stop_lldp(struct rte_eth_dev *dev)
3692 {
3693         double nvm_ver;
3694         char ver_str[64] = {0};
3695         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3696
3697         i40e_fw_version_get(dev, ver_str, 64);
3698         nvm_ver = atof(ver_str);
3699         if ((hw->mac.type == I40E_MAC_X722 ||
3700              hw->mac.type == I40E_MAC_X722_VF) &&
3701              ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(3.33 * 1000)))
3702                 return true;
3703         else if ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(6.01 * 1000))
3704                 return true;
3705
3706         return false;
3707 }
3708
3709 static int
3710 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3711 {
3712         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3713         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3714         struct i40e_vsi *vsi = pf->main_vsi;
3715         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3716
3717         dev_info->max_rx_queues = vsi->nb_qps;
3718         dev_info->max_tx_queues = vsi->nb_qps;
3719         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3720         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3721         dev_info->max_mac_addrs = vsi->max_macaddrs;
3722         dev_info->max_vfs = pci_dev->max_vfs;
3723         dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
3724         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3725         dev_info->rx_queue_offload_capa = 0;
3726         dev_info->rx_offload_capa =
3727                 RTE_ETH_RX_OFFLOAD_VLAN_STRIP |
3728                 RTE_ETH_RX_OFFLOAD_QINQ_STRIP |
3729                 RTE_ETH_RX_OFFLOAD_IPV4_CKSUM |
3730                 RTE_ETH_RX_OFFLOAD_UDP_CKSUM |
3731                 RTE_ETH_RX_OFFLOAD_TCP_CKSUM |
3732                 RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3733                 RTE_ETH_RX_OFFLOAD_KEEP_CRC |
3734                 RTE_ETH_RX_OFFLOAD_SCATTER |
3735                 RTE_ETH_RX_OFFLOAD_VLAN_EXTEND |
3736                 RTE_ETH_RX_OFFLOAD_VLAN_FILTER |
3737                 RTE_ETH_RX_OFFLOAD_RSS_HASH;
3738
3739         dev_info->tx_queue_offload_capa = RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE;
3740         dev_info->tx_offload_capa =
3741                 RTE_ETH_TX_OFFLOAD_VLAN_INSERT |
3742                 RTE_ETH_TX_OFFLOAD_QINQ_INSERT |
3743                 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |
3744                 RTE_ETH_TX_OFFLOAD_UDP_CKSUM |
3745                 RTE_ETH_TX_OFFLOAD_TCP_CKSUM |
3746                 RTE_ETH_TX_OFFLOAD_SCTP_CKSUM |
3747                 RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3748                 RTE_ETH_TX_OFFLOAD_TCP_TSO |
3749                 RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO |
3750                 RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO |
3751                 RTE_ETH_TX_OFFLOAD_IPIP_TNL_TSO |
3752                 RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO |
3753                 RTE_ETH_TX_OFFLOAD_MULTI_SEGS |
3754                 RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM |
3755                 dev_info->tx_queue_offload_capa;
3756         dev_info->dev_capa =
3757                 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3758                 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3759         dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP;
3760
3761         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3762                                                 sizeof(uint32_t);
3763         dev_info->reta_size = pf->hash_lut_size;
3764         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3765
3766         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3767                 .rx_thresh = {
3768                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3769                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3770                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3771                 },
3772                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3773                 .rx_drop_en = 0,
3774                 .offloads = 0,
3775         };
3776
3777         dev_info->default_txconf = (struct rte_eth_txconf) {
3778                 .tx_thresh = {
3779                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3780                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3781                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3782                 },
3783                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3784                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3785                 .offloads = 0,
3786         };
3787
3788         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3789                 .nb_max = I40E_MAX_RING_DESC,
3790                 .nb_min = I40E_MIN_RING_DESC,
3791                 .nb_align = I40E_ALIGN_RING_DESC,
3792         };
3793
3794         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3795                 .nb_max = I40E_MAX_RING_DESC,
3796                 .nb_min = I40E_MIN_RING_DESC,
3797                 .nb_align = I40E_ALIGN_RING_DESC,
3798                 .nb_seg_max = I40E_TX_MAX_SEG,
3799                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3800         };
3801
3802         if (pf->flags & I40E_FLAG_VMDQ) {
3803                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3804                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3805                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3806                                                 pf->max_nb_vmdq_vsi;
3807                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3808                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3809                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3810         }
3811
3812         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3813                 /* For XL710 */
3814                 dev_info->speed_capa = RTE_ETH_LINK_SPEED_40G;
3815                 dev_info->default_rxportconf.nb_queues = 2;
3816                 dev_info->default_txportconf.nb_queues = 2;
3817                 if (dev->data->nb_rx_queues == 1)
3818                         dev_info->default_rxportconf.ring_size = 2048;
3819                 else
3820                         dev_info->default_rxportconf.ring_size = 1024;
3821                 if (dev->data->nb_tx_queues == 1)
3822                         dev_info->default_txportconf.ring_size = 1024;
3823                 else
3824                         dev_info->default_txportconf.ring_size = 512;
3825
3826         } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3827                 /* For XXV710 */
3828                 dev_info->speed_capa = RTE_ETH_LINK_SPEED_25G;
3829                 dev_info->default_rxportconf.nb_queues = 1;
3830                 dev_info->default_txportconf.nb_queues = 1;
3831                 dev_info->default_rxportconf.ring_size = 256;
3832                 dev_info->default_txportconf.ring_size = 256;
3833         } else {
3834                 /* For X710 */
3835                 dev_info->speed_capa = RTE_ETH_LINK_SPEED_1G | RTE_ETH_LINK_SPEED_10G;
3836                 dev_info->default_rxportconf.nb_queues = 1;
3837                 dev_info->default_txportconf.nb_queues = 1;
3838                 if (dev->data->dev_conf.link_speeds & RTE_ETH_LINK_SPEED_10G) {
3839                         dev_info->default_rxportconf.ring_size = 512;
3840                         dev_info->default_txportconf.ring_size = 256;
3841                 } else {
3842                         dev_info->default_rxportconf.ring_size = 256;
3843                         dev_info->default_txportconf.ring_size = 256;
3844                 }
3845         }
3846         dev_info->default_rxportconf.burst_size = 32;
3847         dev_info->default_txportconf.burst_size = 32;
3848
3849         return 0;
3850 }
3851
3852 static int
3853 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3854 {
3855         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3856         struct i40e_vsi *vsi = pf->main_vsi;
3857         PMD_INIT_FUNC_TRACE();
3858
3859         if (on)
3860                 return i40e_vsi_add_vlan(vsi, vlan_id);
3861         else
3862                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3863 }
3864
3865 static int
3866 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3867                                 enum rte_vlan_type vlan_type,
3868                                 uint16_t tpid, int qinq)
3869 {
3870         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3871         uint64_t reg_r = 0;
3872         uint64_t reg_w = 0;
3873         uint16_t reg_id = 3;
3874         int ret;
3875
3876         if (qinq) {
3877                 if (vlan_type == RTE_ETH_VLAN_TYPE_OUTER)
3878                         reg_id = 2;
3879         }
3880
3881         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3882                                           &reg_r, NULL);
3883         if (ret != I40E_SUCCESS) {
3884                 PMD_DRV_LOG(ERR,
3885                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3886                            reg_id);
3887                 return -EIO;
3888         }
3889         PMD_DRV_LOG(DEBUG,
3890                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3891                     reg_id, reg_r);
3892
3893         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3894         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3895         if (reg_r == reg_w) {
3896                 PMD_DRV_LOG(DEBUG, "No need to write");
3897                 return 0;
3898         }
3899
3900         ret = i40e_aq_debug_write_global_register(hw,
3901                                            I40E_GL_SWT_L2TAGCTRL(reg_id),
3902                                            reg_w, NULL);
3903         if (ret != I40E_SUCCESS) {
3904                 PMD_DRV_LOG(ERR,
3905                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3906                             reg_id);
3907                 return -EIO;
3908         }
3909         PMD_DRV_LOG(DEBUG,
3910                     "Global register 0x%08x is changed with value 0x%08x",
3911                     I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3912
3913         return 0;
3914 }
3915
3916 static int
3917 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3918                    enum rte_vlan_type vlan_type,
3919                    uint16_t tpid)
3920 {
3921         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3922         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3923         int qinq = dev->data->dev_conf.rxmode.offloads &
3924                    RTE_ETH_RX_OFFLOAD_VLAN_EXTEND;
3925         u16 sw_flags = 0, valid_flags = 0;
3926         int ret = 0;
3927
3928         if ((vlan_type != RTE_ETH_VLAN_TYPE_INNER &&
3929              vlan_type != RTE_ETH_VLAN_TYPE_OUTER) ||
3930             (!qinq && vlan_type == RTE_ETH_VLAN_TYPE_INNER)) {
3931                 PMD_DRV_LOG(ERR,
3932                             "Unsupported vlan type.");
3933                 return -EINVAL;
3934         }
3935
3936         if (pf->support_multi_driver) {
3937                 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3938                 return -ENOTSUP;
3939         }
3940
3941         /* 802.1ad frames ability is added in NVM API 1.7*/
3942         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3943                 if (qinq) {
3944                         if (pf->fw8_3gt) {
3945                                 sw_flags = I40E_AQ_SET_SWITCH_CFG_OUTER_VLAN;
3946                                 valid_flags = I40E_AQ_SET_SWITCH_CFG_OUTER_VLAN;
3947                         }
3948                         if (vlan_type == RTE_ETH_VLAN_TYPE_OUTER)
3949                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3950                         else if (vlan_type == RTE_ETH_VLAN_TYPE_INNER)
3951                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3952                 } else {
3953                         /*
3954                          * If tpid is equal to 0x88A8, indicates that the
3955                          * disable double VLAN operation is in progress.
3956                          * Need set switch configuration back to default.
3957                          */
3958                         if (pf->fw8_3gt && tpid == RTE_ETHER_TYPE_QINQ) {
3959                                 sw_flags = 0;
3960                                 valid_flags = I40E_AQ_SET_SWITCH_CFG_OUTER_VLAN;
3961                                 if (vlan_type == RTE_ETH_VLAN_TYPE_OUTER)
3962                                         hw->first_tag = rte_cpu_to_le_16(tpid);
3963                         } else {
3964                                 if (vlan_type == RTE_ETH_VLAN_TYPE_OUTER)
3965                                         hw->second_tag = rte_cpu_to_le_16(tpid);
3966                         }
3967                 }
3968                 ret = i40e_aq_set_switch_config(hw, sw_flags,
3969                                                 valid_flags, 0, NULL);
3970                 if (ret != I40E_SUCCESS) {
3971                         PMD_DRV_LOG(ERR,
3972                                     "Set switch config failed aq_err: %d",
3973                                     hw->aq.asq_last_status);
3974                         ret = -EIO;
3975                 }
3976         } else
3977                 /* If NVM API < 1.7, keep the register setting */
3978                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3979                                                       tpid, qinq);
3980
3981         return ret;
3982 }
3983
3984 /* Configure outer vlan stripping on or off in QinQ mode */
3985 static int
3986 i40e_vsi_config_outer_vlan_stripping(struct i40e_vsi *vsi, bool on)
3987 {
3988         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3989         int ret = I40E_SUCCESS;
3990         uint32_t reg;
3991
3992         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
3993                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
3994                 return -EINVAL;
3995         }
3996
3997         /* Configure for outer VLAN RX stripping */
3998         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
3999
4000         if (on)
4001                 reg |= I40E_VSI_TSR_QINQ_STRIP;
4002         else
4003                 reg &= ~I40E_VSI_TSR_QINQ_STRIP;
4004
4005         ret = i40e_aq_debug_write_register(hw,
4006                                                    I40E_VSI_TSR(vsi->vsi_id),
4007                                                    reg, NULL);
4008         if (ret < 0) {
4009                 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
4010                                     vsi->vsi_id);
4011                 return I40E_ERR_CONFIG;
4012         }
4013
4014         return ret;
4015 }
4016
4017 static int
4018 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4019 {
4020         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4021         struct i40e_mac_filter_info *mac_filter;
4022         struct i40e_vsi *vsi = pf->main_vsi;
4023         struct rte_eth_rxmode *rxmode;
4024         struct i40e_mac_filter *f;
4025         int i, num;
4026         void *temp;
4027         int ret;
4028
4029         rxmode = &dev->data->dev_conf.rxmode;
4030         if (mask & RTE_ETH_VLAN_FILTER_MASK) {
4031                 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)
4032                         i40e_vsi_config_vlan_filter(vsi, TRUE);
4033                 else
4034                         i40e_vsi_config_vlan_filter(vsi, FALSE);
4035         }
4036
4037         if (mask & RTE_ETH_VLAN_STRIP_MASK) {
4038                 /* Enable or disable VLAN stripping */
4039                 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP)
4040                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
4041                 else
4042                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
4043         }
4044
4045         if (mask & RTE_ETH_VLAN_EXTEND_MASK) {
4046                 i = 0;
4047                 num = vsi->mac_num;
4048                 mac_filter = rte_zmalloc("mac_filter_info_data",
4049                                  num * sizeof(*mac_filter), 0);
4050                 if (mac_filter == NULL) {
4051                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4052                         return I40E_ERR_NO_MEMORY;
4053                 }
4054
4055                 /*
4056                  * Outer VLAN processing is supported after firmware v8.4, kernel driver
4057                  * also change the default behavior to support this feature. To align with
4058                  * kernel driver, set switch config in 'i40e_vlan_tpie_set' to support for
4059                  * outer VLAN processing. But it is forbidden for firmware to change the
4060                  * Inner/Outer VLAN configuration while there are MAC/VLAN filters in the
4061                  * switch table. Therefore, we need to clear the MAC table before setting
4062                  * config, and then restore the MAC table after setting. This feature is
4063                  * recommended to be used in firmware v8.6.
4064                  */
4065                 /* Remove all existing mac */
4066                 RTE_TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
4067                         mac_filter[i] = f->mac_info;
4068                         ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4069                         if (ret)
4070                                 PMD_DRV_LOG(ERR, "i40e vsi delete mac fail.");
4071                         i++;
4072                 }
4073                 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_EXTEND) {
4074                         i40e_vsi_config_double_vlan(vsi, TRUE);
4075                         /* Set global registers with default ethertype. */
4076                         i40e_vlan_tpid_set(dev, RTE_ETH_VLAN_TYPE_OUTER,
4077                                            RTE_ETHER_TYPE_VLAN);
4078                         i40e_vlan_tpid_set(dev, RTE_ETH_VLAN_TYPE_INNER,
4079                                            RTE_ETHER_TYPE_VLAN);
4080                 } else {
4081                         if (pf->fw8_3gt)
4082                                 i40e_vlan_tpid_set(dev, RTE_ETH_VLAN_TYPE_OUTER,
4083                                            RTE_ETHER_TYPE_QINQ);
4084                         i40e_vsi_config_double_vlan(vsi, FALSE);
4085                 }
4086                 /* Restore all mac */
4087                 for (i = 0; i < num; i++) {
4088                         ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4089                         if (ret)
4090                                 PMD_DRV_LOG(ERR, "i40e vsi add mac fail.");
4091                 }
4092                 rte_free(mac_filter);
4093         }
4094
4095         if (mask & RTE_ETH_QINQ_STRIP_MASK) {
4096                 /* Enable or disable outer VLAN stripping */
4097                 if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_QINQ_STRIP)
4098                         i40e_vsi_config_outer_vlan_stripping(vsi, TRUE);
4099                 else
4100                         i40e_vsi_config_outer_vlan_stripping(vsi, FALSE);
4101         }
4102
4103         return 0;
4104 }
4105
4106 static void
4107 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
4108                           __rte_unused uint16_t queue,
4109                           __rte_unused int on)
4110 {
4111         PMD_INIT_FUNC_TRACE();
4112 }
4113
4114 static int
4115 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
4116 {
4117         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4118         struct i40e_vsi *vsi = pf->main_vsi;
4119         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
4120         struct i40e_vsi_vlan_pvid_info info;
4121
4122         memset(&info, 0, sizeof(info));
4123         info.on = on;
4124         if (info.on)
4125                 info.config.pvid = pvid;
4126         else {
4127                 info.config.reject.tagged =
4128                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
4129                 info.config.reject.untagged =
4130                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
4131         }
4132
4133         return i40e_vsi_vlan_pvid_set(vsi, &info);
4134 }
4135
4136 static int
4137 i40e_dev_led_on(struct rte_eth_dev *dev)
4138 {
4139         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4140         uint32_t mode = i40e_led_get(hw);
4141
4142         if (mode == 0)
4143                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
4144
4145         return 0;
4146 }
4147
4148 static int
4149 i40e_dev_led_off(struct rte_eth_dev *dev)
4150 {
4151         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4152         uint32_t mode = i40e_led_get(hw);
4153
4154         if (mode != 0)
4155                 i40e_led_set(hw, 0, false);
4156
4157         return 0;
4158 }
4159
4160 static int
4161 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4162 {
4163         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4164         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4165
4166         fc_conf->pause_time = pf->fc_conf.pause_time;
4167
4168         /* read out from register, in case they are modified by other port */
4169         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
4170                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
4171         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
4172                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
4173
4174         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
4175         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
4176
4177          /* Return current mode according to actual setting*/
4178         switch (hw->fc.current_mode) {
4179         case I40E_FC_FULL:
4180                 fc_conf->mode = RTE_ETH_FC_FULL;
4181                 break;
4182         case I40E_FC_TX_PAUSE:
4183                 fc_conf->mode = RTE_ETH_FC_TX_PAUSE;
4184                 break;
4185         case I40E_FC_RX_PAUSE:
4186                 fc_conf->mode = RTE_ETH_FC_RX_PAUSE;
4187                 break;
4188         case I40E_FC_NONE:
4189         default:
4190                 fc_conf->mode = RTE_ETH_FC_NONE;
4191         };
4192
4193         return 0;
4194 }
4195
4196 static int
4197 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4198 {
4199         uint32_t mflcn_reg, fctrl_reg, reg;
4200         uint32_t max_high_water;
4201         uint8_t i, aq_failure;
4202         int err;
4203         struct i40e_hw *hw;
4204         struct i40e_pf *pf;
4205         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
4206                 [RTE_ETH_FC_NONE] = I40E_FC_NONE,
4207                 [RTE_ETH_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
4208                 [RTE_ETH_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
4209                 [RTE_ETH_FC_FULL] = I40E_FC_FULL
4210         };
4211
4212         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
4213
4214         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
4215         if ((fc_conf->high_water > max_high_water) ||
4216                         (fc_conf->high_water < fc_conf->low_water)) {
4217                 PMD_INIT_LOG(ERR,
4218                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
4219                         max_high_water);
4220                 return -EINVAL;
4221         }
4222
4223         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4224         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4225         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
4226
4227         pf->fc_conf.pause_time = fc_conf->pause_time;
4228         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
4229         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
4230
4231         PMD_INIT_FUNC_TRACE();
4232
4233         /* All the link flow control related enable/disable register
4234          * configuration is handle by the F/W
4235          */
4236         err = i40e_set_fc(hw, &aq_failure, true);
4237         if (err < 0)
4238                 return -ENOSYS;
4239
4240         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
4241                 /* Configure flow control refresh threshold,
4242                  * the value for stat_tx_pause_refresh_timer[8]
4243                  * is used for global pause operation.
4244                  */
4245
4246                 I40E_WRITE_REG(hw,
4247                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
4248                                pf->fc_conf.pause_time);
4249
4250                 /* configure the timer value included in transmitted pause
4251                  * frame,
4252                  * the value for stat_tx_pause_quanta[8] is used for global
4253                  * pause operation
4254                  */
4255                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
4256                                pf->fc_conf.pause_time);
4257
4258                 fctrl_reg = I40E_READ_REG(hw,
4259                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
4260
4261                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4262                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
4263                 else
4264                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
4265
4266                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
4267                                fctrl_reg);
4268         } else {
4269                 /* Configure pause time (2 TCs per register) */
4270                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
4271                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
4272                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
4273
4274                 /* Configure flow control refresh threshold value */
4275                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
4276                                pf->fc_conf.pause_time / 2);
4277
4278                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4279
4280                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
4281                  *depending on configuration
4282                  */
4283                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
4284                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
4285                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
4286                 } else {
4287                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
4288                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
4289                 }
4290
4291                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
4292         }
4293
4294         if (!pf->support_multi_driver) {
4295                 /* config water marker both based on the packets and bytes */
4296                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
4297                                  (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4298                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4299                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
4300                                   (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4301                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4302                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
4303                                   pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4304                                   << I40E_KILOSHIFT);
4305                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
4306                                    pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4307                                    << I40E_KILOSHIFT);
4308         } else {
4309                 PMD_DRV_LOG(ERR,
4310                             "Water marker configuration is not supported.");
4311         }
4312
4313         I40E_WRITE_FLUSH(hw);
4314
4315         return 0;
4316 }
4317
4318 static int
4319 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
4320                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
4321 {
4322         PMD_INIT_FUNC_TRACE();
4323
4324         return -ENOSYS;
4325 }
4326
4327 /* Add a MAC address, and update filters */
4328 static int
4329 i40e_macaddr_add(struct rte_eth_dev *dev,
4330                  struct rte_ether_addr *mac_addr,
4331                  __rte_unused uint32_t index,
4332                  uint32_t pool)
4333 {
4334         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4335         struct i40e_mac_filter_info mac_filter;
4336         struct i40e_vsi *vsi;
4337         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
4338         int ret;
4339
4340         /* If VMDQ not enabled or configured, return */
4341         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
4342                           !pf->nb_cfg_vmdq_vsi)) {
4343                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
4344                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
4345                         pool);
4346                 return -ENOTSUP;
4347         }
4348
4349         if (pool > pf->nb_cfg_vmdq_vsi) {
4350                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
4351                                 pool, pf->nb_cfg_vmdq_vsi);
4352                 return -EINVAL;
4353         }
4354
4355         rte_memcpy(&mac_filter.mac_addr, mac_addr, RTE_ETHER_ADDR_LEN);
4356         if (rxmode->offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)
4357                 mac_filter.filter_type = I40E_MACVLAN_PERFECT_MATCH;
4358         else
4359                 mac_filter.filter_type = I40E_MAC_PERFECT_MATCH;
4360
4361         if (pool == 0)
4362                 vsi = pf->main_vsi;
4363         else
4364                 vsi = pf->vmdq[pool - 1].vsi;
4365
4366         ret = i40e_vsi_add_mac(vsi, &mac_filter);
4367         if (ret != I40E_SUCCESS) {
4368                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4369                 return -ENODEV;
4370         }
4371         return 0;
4372 }
4373
4374 /* Remove a MAC address, and update filters */
4375 static void
4376 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4377 {
4378         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4379         struct i40e_vsi *vsi;
4380         struct rte_eth_dev_data *data = dev->data;
4381         struct rte_ether_addr *macaddr;
4382         int ret;
4383         uint32_t i;
4384         uint64_t pool_sel;
4385
4386         macaddr = &(data->mac_addrs[index]);
4387
4388         pool_sel = dev->data->mac_pool_sel[index];
4389
4390         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4391                 if (pool_sel & (1ULL << i)) {
4392                         if (i == 0)
4393                                 vsi = pf->main_vsi;
4394                         else {
4395                                 /* No VMDQ pool enabled or configured */
4396                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4397                                         (i > pf->nb_cfg_vmdq_vsi)) {
4398                                         PMD_DRV_LOG(ERR,
4399                                                 "No VMDQ pool enabled/configured");
4400                                         return;
4401                                 }
4402                                 vsi = pf->vmdq[i - 1].vsi;
4403                         }
4404                         ret = i40e_vsi_delete_mac(vsi, macaddr);
4405
4406                         if (ret) {
4407                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4408                                 return;
4409                         }
4410                 }
4411         }
4412 }
4413
4414 static int
4415 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4416 {
4417         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4418         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4419         uint32_t reg;
4420         int ret;
4421
4422         if (!lut)
4423                 return -EINVAL;
4424
4425         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4426                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id,
4427                                           vsi->type != I40E_VSI_SRIOV,
4428                                           lut, lut_size);
4429                 if (ret) {
4430                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4431                         return ret;
4432                 }
4433         } else {
4434                 uint32_t *lut_dw = (uint32_t *)lut;
4435                 uint16_t i, lut_size_dw = lut_size / 4;
4436
4437                 if (vsi->type == I40E_VSI_SRIOV) {
4438                         for (i = 0; i <= lut_size_dw; i++) {
4439                                 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4440                                 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4441                         }
4442                 } else {
4443                         for (i = 0; i < lut_size_dw; i++)
4444                                 lut_dw[i] = I40E_READ_REG(hw,
4445                                                           I40E_PFQF_HLUT(i));
4446                 }
4447         }
4448
4449         return 0;
4450 }
4451
4452 int
4453 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4454 {
4455         struct i40e_pf *pf;
4456         struct i40e_hw *hw;
4457
4458         if (!vsi || !lut)
4459                 return -EINVAL;
4460
4461         pf = I40E_VSI_TO_PF(vsi);
4462         hw = I40E_VSI_TO_HW(vsi);
4463
4464         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4465                 enum i40e_status_code status;
4466
4467                 status = i40e_aq_set_rss_lut(hw, vsi->vsi_id,
4468                                              vsi->type != I40E_VSI_SRIOV,
4469                                              lut, lut_size);
4470                 if (status) {
4471                         PMD_DRV_LOG(ERR,
4472                                     "Failed to update RSS lookup table, error status: %d",
4473                                     status);
4474                         return -EIO;
4475                 }
4476         } else {
4477                 uint32_t *lut_dw = (uint32_t *)lut;
4478                 uint16_t i, lut_size_dw = lut_size / 4;
4479
4480                 if (vsi->type == I40E_VSI_SRIOV) {
4481                         for (i = 0; i < lut_size_dw; i++)
4482                                 I40E_WRITE_REG(
4483                                         hw,
4484                                         I40E_VFQF_HLUT1(i, vsi->user_param),
4485                                         lut_dw[i]);
4486                 } else {
4487                         for (i = 0; i < lut_size_dw; i++)
4488                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4489                                                lut_dw[i]);
4490                 }
4491                 I40E_WRITE_FLUSH(hw);
4492         }
4493
4494         return 0;
4495 }
4496
4497 static int
4498 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4499                          struct rte_eth_rss_reta_entry64 *reta_conf,
4500                          uint16_t reta_size)
4501 {
4502         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4503         uint16_t i, lut_size = pf->hash_lut_size;
4504         uint16_t idx, shift;
4505         uint8_t *lut;
4506         int ret;
4507
4508         if (reta_size != lut_size ||
4509                 reta_size > RTE_ETH_RSS_RETA_SIZE_512) {
4510                 PMD_DRV_LOG(ERR,
4511                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4512                         reta_size, lut_size);
4513                 return -EINVAL;
4514         }
4515
4516         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4517         if (!lut) {
4518                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4519                 return -ENOMEM;
4520         }
4521         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4522         if (ret)
4523                 goto out;
4524         for (i = 0; i < reta_size; i++) {
4525                 idx = i / RTE_ETH_RETA_GROUP_SIZE;
4526                 shift = i % RTE_ETH_RETA_GROUP_SIZE;
4527                 if (reta_conf[idx].mask & (1ULL << shift))
4528                         lut[i] = reta_conf[idx].reta[shift];
4529         }
4530         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4531
4532         pf->adapter->rss_reta_updated = 1;
4533
4534 out:
4535         rte_free(lut);
4536
4537         return ret;
4538 }
4539
4540 static int
4541 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4542                         struct rte_eth_rss_reta_entry64 *reta_conf,
4543                         uint16_t reta_size)
4544 {
4545         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4546         uint16_t i, lut_size = pf->hash_lut_size;
4547         uint16_t idx, shift;
4548         uint8_t *lut;
4549         int ret;
4550
4551         if (reta_size != lut_size ||
4552                 reta_size > RTE_ETH_RSS_RETA_SIZE_512) {
4553                 PMD_DRV_LOG(ERR,
4554                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4555                         reta_size, lut_size);
4556                 return -EINVAL;
4557         }
4558
4559         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4560         if (!lut) {
4561                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4562                 return -ENOMEM;
4563         }
4564
4565         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4566         if (ret)
4567                 goto out;
4568         for (i = 0; i < reta_size; i++) {
4569                 idx = i / RTE_ETH_RETA_GROUP_SIZE;
4570                 shift = i % RTE_ETH_RETA_GROUP_SIZE;
4571                 if (reta_conf[idx].mask & (1ULL << shift))
4572                         reta_conf[idx].reta[shift] = lut[i];
4573         }
4574
4575 out:
4576         rte_free(lut);
4577
4578         return ret;
4579 }
4580
4581 /**
4582  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4583  * @hw:   pointer to the HW structure
4584  * @mem:  pointer to mem struct to fill out
4585  * @size: size of memory requested
4586  * @alignment: what to align the allocation to
4587  **/
4588 enum i40e_status_code
4589 i40e_allocate_dma_mem_d(__rte_unused struct i40e_hw *hw,
4590                         struct i40e_dma_mem *mem,
4591                         u64 size,
4592                         u32 alignment)
4593 {
4594         static uint64_t i40e_dma_memzone_id;
4595         const struct rte_memzone *mz = NULL;
4596         char z_name[RTE_MEMZONE_NAMESIZE];
4597
4598         if (!mem)
4599                 return I40E_ERR_PARAM;
4600
4601         snprintf(z_name, sizeof(z_name), "i40e_dma_%" PRIu64,
4602                 __atomic_fetch_add(&i40e_dma_memzone_id, 1, __ATOMIC_RELAXED));
4603         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4604                         RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4605         if (!mz)
4606                 return I40E_ERR_NO_MEMORY;
4607
4608         mem->size = size;
4609         mem->va = mz->addr;
4610         mem->pa = mz->iova;
4611         mem->zone = (const void *)mz;
4612         PMD_DRV_LOG(DEBUG,
4613                 "memzone %s allocated with physical address: %"PRIu64,
4614                 mz->name, mem->pa);
4615
4616         return I40E_SUCCESS;
4617 }
4618
4619 /**
4620  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4621  * @hw:   pointer to the HW structure
4622  * @mem:  ptr to mem struct to free
4623  **/
4624 enum i40e_status_code
4625 i40e_free_dma_mem_d(__rte_unused struct i40e_hw *hw,
4626                     struct i40e_dma_mem *mem)
4627 {
4628         if (!mem)
4629                 return I40E_ERR_PARAM;
4630
4631         PMD_DRV_LOG(DEBUG,
4632                 "memzone %s to be freed with physical address: %"PRIu64,
4633                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4634         rte_memzone_free((const struct rte_memzone *)mem->zone);
4635         mem->zone = NULL;
4636         mem->va = NULL;
4637         mem->pa = (u64)0;
4638
4639         return I40E_SUCCESS;
4640 }
4641
4642 /**
4643  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4644  * @hw:   pointer to the HW structure
4645  * @mem:  pointer to mem struct to fill out
4646  * @size: size of memory requested
4647  **/
4648 enum i40e_status_code
4649 i40e_allocate_virt_mem_d(__rte_unused struct i40e_hw *hw,
4650                          struct i40e_virt_mem *mem,
4651                          u32 size)
4652 {
4653         if (!mem)
4654                 return I40E_ERR_PARAM;
4655
4656         mem->size = size;
4657         mem->va = rte_zmalloc("i40e", size, 0);
4658
4659         if (mem->va)
4660                 return I40E_SUCCESS;
4661         else
4662                 return I40E_ERR_NO_MEMORY;
4663 }
4664
4665 /**
4666  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4667  * @hw:   pointer to the HW structure
4668  * @mem:  pointer to mem struct to free
4669  **/
4670 enum i40e_status_code
4671 i40e_free_virt_mem_d(__rte_unused struct i40e_hw *hw,
4672                      struct i40e_virt_mem *mem)
4673 {
4674         if (!mem)
4675                 return I40E_ERR_PARAM;
4676
4677         rte_free(mem->va);
4678         mem->va = NULL;
4679
4680         return I40E_SUCCESS;
4681 }
4682
4683 void
4684 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4685 {
4686         rte_spinlock_init(&sp->spinlock);
4687 }
4688
4689 void
4690 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4691 {
4692         rte_spinlock_lock(&sp->spinlock);
4693 }
4694
4695 void
4696 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4697 {
4698         rte_spinlock_unlock(&sp->spinlock);
4699 }
4700
4701 void
4702 i40e_destroy_spinlock_d(__rte_unused struct i40e_spinlock *sp)
4703 {
4704         return;
4705 }
4706
4707 /**
4708  * Get the hardware capabilities, which will be parsed
4709  * and saved into struct i40e_hw.
4710  */
4711 static int
4712 i40e_get_cap(struct i40e_hw *hw)
4713 {
4714         struct i40e_aqc_list_capabilities_element_resp *buf;
4715         uint16_t len, size = 0;
4716         int ret;
4717
4718         /* Calculate a huge enough buff for saving response data temporarily */
4719         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4720                                                 I40E_MAX_CAP_ELE_NUM;
4721         buf = rte_zmalloc("i40e", len, 0);
4722         if (!buf) {
4723                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4724                 return I40E_ERR_NO_MEMORY;
4725         }
4726
4727         /* Get, parse the capabilities and save it to hw */
4728         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4729                         i40e_aqc_opc_list_func_capabilities, NULL);
4730         if (ret != I40E_SUCCESS)
4731                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4732
4733         /* Free the temporary buffer after being used */
4734         rte_free(buf);
4735
4736         return ret;
4737 }
4738
4739 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF        4
4740
4741 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4742                 const char *value,
4743                 void *opaque)
4744 {
4745         struct i40e_pf *pf;
4746         unsigned long num;
4747         char *end;
4748
4749         pf = (struct i40e_pf *)opaque;
4750         RTE_SET_USED(key);
4751
4752         errno = 0;
4753         num = strtoul(value, &end, 0);
4754         if (errno != 0 || end == value || *end != 0) {
4755                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4756                             "kept the value = %hu", value, pf->vf_nb_qp_max);
4757                 return -(EINVAL);
4758         }
4759
4760         if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4761                 pf->vf_nb_qp_max = (uint16_t)num;
4762         else
4763                 /* here return 0 to make next valid same argument work */
4764                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4765                             "power of 2 and equal or less than 16 !, Now it is "
4766                             "kept the value = %hu", num, pf->vf_nb_qp_max);
4767
4768         return 0;
4769 }
4770
4771 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4772 {
4773         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4774         struct rte_kvargs *kvlist;
4775         int kvargs_count;
4776
4777         /* set default queue number per VF as 4 */
4778         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4779
4780         if (dev->device->devargs == NULL)
4781                 return 0;
4782
4783         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4784         if (kvlist == NULL)
4785                 return -(EINVAL);
4786
4787         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4788         if (!kvargs_count) {
4789                 rte_kvargs_free(kvlist);
4790                 return 0;
4791         }
4792
4793         if (kvargs_count > 1)
4794                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4795                             "the first invalid or last valid one is used !",
4796                             ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4797
4798         rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4799                            i40e_pf_parse_vf_queue_number_handler, pf);
4800
4801         rte_kvargs_free(kvlist);
4802
4803         return 0;
4804 }
4805
4806 static int
4807 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4808 {
4809         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4810         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4811         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4812         uint16_t qp_count = 0, vsi_count = 0;
4813
4814         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4815                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4816                 return -EINVAL;
4817         }
4818
4819         i40e_pf_config_vf_rxq_number(dev);
4820
4821         /* Add the parameter init for LFC */
4822         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4823         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4824         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4825
4826         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4827         pf->max_num_vsi = hw->func_caps.num_vsis;
4828         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4829         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4830
4831         /* FDir queue/VSI allocation */
4832         pf->fdir_qp_offset = 0;
4833         if (hw->func_caps.fd) {
4834                 pf->flags |= I40E_FLAG_FDIR;
4835                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4836         } else {
4837                 pf->fdir_nb_qps = 0;
4838         }
4839         qp_count += pf->fdir_nb_qps;
4840         vsi_count += 1;
4841
4842         /* LAN queue/VSI allocation */
4843         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4844         if (!hw->func_caps.rss) {
4845                 pf->lan_nb_qps = 1;
4846         } else {
4847                 pf->flags |= I40E_FLAG_RSS;
4848                 if (hw->mac.type == I40E_MAC_X722)
4849                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4850                 pf->lan_nb_qps = pf->lan_nb_qp_max;
4851         }
4852         qp_count += pf->lan_nb_qps;
4853         vsi_count += 1;
4854
4855         /* VF queue/VSI allocation */
4856         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4857         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4858                 pf->flags |= I40E_FLAG_SRIOV;
4859                 pf->vf_nb_qps = pf->vf_nb_qp_max;
4860                 pf->vf_num = pci_dev->max_vfs;
4861                 PMD_DRV_LOG(DEBUG,
4862                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4863                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4864         } else {
4865                 pf->vf_nb_qps = 0;
4866                 pf->vf_num = 0;
4867         }
4868         qp_count += pf->vf_nb_qps * pf->vf_num;
4869         vsi_count += pf->vf_num;
4870
4871         /* VMDq queue/VSI allocation */
4872         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4873         pf->vmdq_nb_qps = 0;
4874         pf->max_nb_vmdq_vsi = 0;
4875         if (hw->func_caps.vmdq) {
4876                 if (qp_count < hw->func_caps.num_tx_qp &&
4877                         vsi_count < hw->func_caps.num_vsis) {
4878                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4879                                 qp_count) / pf->vmdq_nb_qp_max;
4880
4881                         /* Limit the maximum number of VMDq vsi to the maximum
4882                          * ethdev can support
4883                          */
4884                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4885                                 hw->func_caps.num_vsis - vsi_count);
4886                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4887                                 RTE_ETH_64_POOLS);
4888                         if (pf->max_nb_vmdq_vsi) {
4889                                 pf->flags |= I40E_FLAG_VMDQ;
4890                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4891                                 PMD_DRV_LOG(DEBUG,
4892                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4893                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4894                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4895                         } else {
4896                                 PMD_DRV_LOG(INFO,
4897                                         "No enough queues left for VMDq");
4898                         }
4899                 } else {
4900                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4901                 }
4902         }
4903         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4904         vsi_count += pf->max_nb_vmdq_vsi;
4905
4906         if (hw->func_caps.dcb)
4907                 pf->flags |= I40E_FLAG_DCB;
4908
4909         if (qp_count > hw->func_caps.num_tx_qp) {
4910                 PMD_DRV_LOG(ERR,
4911                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4912                         qp_count, hw->func_caps.num_tx_qp);
4913                 return -EINVAL;
4914         }
4915         if (vsi_count > hw->func_caps.num_vsis) {
4916                 PMD_DRV_LOG(ERR,
4917                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4918                         vsi_count, hw->func_caps.num_vsis);
4919                 return -EINVAL;
4920         }
4921
4922         /**
4923          * Enable outer VLAN processing if firmware version is greater
4924          * than v8.3
4925          */
4926         if (hw->aq.fw_maj_ver > 8 ||
4927             (hw->aq.fw_maj_ver == 8 && hw->aq.fw_min_ver > 3)) {
4928                 pf->fw8_3gt = true;
4929         } else {
4930                 pf->fw8_3gt = false;
4931         }
4932
4933         return 0;
4934 }
4935
4936 static int
4937 i40e_pf_get_switch_config(struct i40e_pf *pf)
4938 {
4939         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4940         struct i40e_aqc_get_switch_config_resp *switch_config;
4941         struct i40e_aqc_switch_config_element_resp *element;
4942         uint16_t start_seid = 0, num_reported;
4943         int ret;
4944
4945         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4946                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4947         if (!switch_config) {
4948                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4949                 return -ENOMEM;
4950         }
4951
4952         /* Get the switch configurations */
4953         ret = i40e_aq_get_switch_config(hw, switch_config,
4954                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4955         if (ret != I40E_SUCCESS) {
4956                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4957                 goto fail;
4958         }
4959         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4960         if (num_reported != 1) { /* The number should be 1 */
4961                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4962                 goto fail;
4963         }
4964
4965         /* Parse the switch configuration elements */
4966         element = &(switch_config->element[0]);
4967         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4968                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4969                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4970         } else
4971                 PMD_DRV_LOG(INFO, "Unknown element type");
4972
4973 fail:
4974         rte_free(switch_config);
4975
4976         return ret;
4977 }
4978
4979 static int
4980 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4981                         uint32_t num)
4982 {
4983         struct pool_entry *entry;
4984
4985         if (pool == NULL || num == 0)
4986                 return -EINVAL;
4987
4988         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4989         if (entry == NULL) {
4990                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4991                 return -ENOMEM;
4992         }
4993
4994         /* queue heap initialize */
4995         pool->num_free = num;
4996         pool->num_alloc = 0;
4997         pool->base = base;
4998         LIST_INIT(&pool->alloc_list);
4999         LIST_INIT(&pool->free_list);
5000
5001         /* Initialize element  */
5002         entry->base = 0;
5003         entry->len = num;
5004
5005         LIST_INSERT_HEAD(&pool->free_list, entry, next);
5006         return 0;
5007 }
5008
5009 static void
5010 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
5011 {
5012         struct pool_entry *entry, *next_entry;
5013
5014         if (pool == NULL)
5015                 return;
5016
5017         for (entry = LIST_FIRST(&pool->alloc_list);
5018                         entry && (next_entry = LIST_NEXT(entry, next), 1);
5019                         entry = next_entry) {
5020                 LIST_REMOVE(entry, next);
5021                 rte_free(entry);
5022         }
5023
5024         for (entry = LIST_FIRST(&pool->free_list);
5025                         entry && (next_entry = LIST_NEXT(entry, next), 1);
5026                         entry = next_entry) {
5027                 LIST_REMOVE(entry, next);
5028                 rte_free(entry);
5029         }
5030
5031         pool->num_free = 0;
5032         pool->num_alloc = 0;
5033         pool->base = 0;
5034         LIST_INIT(&pool->alloc_list);
5035         LIST_INIT(&pool->free_list);
5036 }
5037
5038 static int
5039 i40e_res_pool_free(struct i40e_res_pool_info *pool,
5040                        uint32_t base)
5041 {
5042         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
5043         uint32_t pool_offset;
5044         uint16_t len;
5045         int insert;
5046
5047         if (pool == NULL) {
5048                 PMD_DRV_LOG(ERR, "Invalid parameter");
5049                 return -EINVAL;
5050         }
5051
5052         pool_offset = base - pool->base;
5053         /* Lookup in alloc list */
5054         LIST_FOREACH(entry, &pool->alloc_list, next) {
5055                 if (entry->base == pool_offset) {
5056                         valid_entry = entry;
5057                         LIST_REMOVE(entry, next);
5058                         break;
5059                 }
5060         }
5061
5062         /* Not find, return */
5063         if (valid_entry == NULL) {
5064                 PMD_DRV_LOG(ERR, "Failed to find entry");
5065                 return -EINVAL;
5066         }
5067
5068         /**
5069          * Found it, move it to free list  and try to merge.
5070          * In order to make merge easier, always sort it by qbase.
5071          * Find adjacent prev and last entries.
5072          */
5073         prev = next = NULL;
5074         LIST_FOREACH(entry, &pool->free_list, next) {
5075                 if (entry->base > valid_entry->base) {
5076                         next = entry;
5077                         break;
5078                 }
5079                 prev = entry;
5080         }
5081
5082         insert = 0;
5083         len = valid_entry->len;
5084         /* Try to merge with next one*/
5085         if (next != NULL) {
5086                 /* Merge with next one */
5087                 if (valid_entry->base + len == next->base) {
5088                         next->base = valid_entry->base;
5089                         next->len += len;
5090                         rte_free(valid_entry);
5091                         valid_entry = next;
5092                         insert = 1;
5093                 }
5094         }
5095
5096         if (prev != NULL) {
5097                 /* Merge with previous one */
5098                 if (prev->base + prev->len == valid_entry->base) {
5099                         prev->len += len;
5100                         /* If it merge with next one, remove next node */
5101                         if (insert == 1) {
5102                                 LIST_REMOVE(valid_entry, next);
5103                                 rte_free(valid_entry);
5104                                 valid_entry = NULL;
5105                         } else {
5106                                 rte_free(valid_entry);
5107                                 valid_entry = NULL;
5108                                 insert = 1;
5109                         }
5110                 }
5111         }
5112
5113         /* Not find any entry to merge, insert */
5114         if (insert == 0) {
5115                 if (prev != NULL)
5116                         LIST_INSERT_AFTER(prev, valid_entry, next);
5117                 else if (next != NULL)
5118                         LIST_INSERT_BEFORE(next, valid_entry, next);
5119                 else /* It's empty list, insert to head */
5120                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
5121         }
5122
5123         pool->num_free += len;
5124         pool->num_alloc -= len;
5125
5126         return 0;
5127 }
5128
5129 static int
5130 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
5131                        uint16_t num)
5132 {
5133         struct pool_entry *entry, *valid_entry;
5134
5135         if (pool == NULL || num == 0) {
5136                 PMD_DRV_LOG(ERR, "Invalid parameter");
5137                 return -EINVAL;
5138         }
5139
5140         if (pool->num_free < num) {
5141                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
5142                             num, pool->num_free);
5143                 return -ENOMEM;
5144         }
5145
5146         valid_entry = NULL;
5147         /* Lookup  in free list and find most fit one */
5148         LIST_FOREACH(entry, &pool->free_list, next) {
5149                 if (entry->len >= num) {
5150                         /* Find best one */
5151                         if (entry->len == num) {
5152                                 valid_entry = entry;
5153                                 break;
5154                         }
5155                         if (valid_entry == NULL || valid_entry->len > entry->len)
5156                                 valid_entry = entry;
5157                 }
5158         }
5159
5160         /* Not find one to satisfy the request, return */
5161         if (valid_entry == NULL) {
5162                 PMD_DRV_LOG(ERR, "No valid entry found");
5163                 return -ENOMEM;
5164         }
5165         /**
5166          * The entry have equal queue number as requested,
5167          * remove it from alloc_list.
5168          */
5169         if (valid_entry->len == num) {
5170                 LIST_REMOVE(valid_entry, next);
5171         } else {
5172                 /**
5173                  * The entry have more numbers than requested,
5174                  * create a new entry for alloc_list and minus its
5175                  * queue base and number in free_list.
5176                  */
5177                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
5178                 if (entry == NULL) {
5179                         PMD_DRV_LOG(ERR,
5180                                 "Failed to allocate memory for resource pool");
5181                         return -ENOMEM;
5182                 }
5183                 entry->base = valid_entry->base;
5184                 entry->len = num;
5185                 valid_entry->base += num;
5186                 valid_entry->len -= num;
5187                 valid_entry = entry;
5188         }
5189
5190         /* Insert it into alloc list, not sorted */
5191         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
5192
5193         pool->num_free -= valid_entry->len;
5194         pool->num_alloc += valid_entry->len;
5195
5196         return valid_entry->base + pool->base;
5197 }
5198
5199 /**
5200  * bitmap_is_subset - Check whether src2 is subset of src1
5201  **/
5202 static inline int
5203 bitmap_is_subset(uint8_t src1, uint8_t src2)
5204 {
5205         return !((src1 ^ src2) & src2);
5206 }
5207
5208 static enum i40e_status_code
5209 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5210 {
5211         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5212
5213         /* If DCB is not supported, only default TC is supported */
5214         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
5215                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
5216                 return I40E_NOT_SUPPORTED;
5217         }
5218
5219         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
5220                 PMD_DRV_LOG(ERR,
5221                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
5222                         hw->func_caps.enabled_tcmap, enabled_tcmap);
5223                 return I40E_NOT_SUPPORTED;
5224         }
5225         return I40E_SUCCESS;
5226 }
5227
5228 int
5229 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
5230                                 struct i40e_vsi_vlan_pvid_info *info)
5231 {
5232         struct i40e_hw *hw;
5233         struct i40e_vsi_context ctxt;
5234         uint8_t vlan_flags = 0;
5235         int ret;
5236
5237         if (vsi == NULL || info == NULL) {
5238                 PMD_DRV_LOG(ERR, "invalid parameters");
5239                 return I40E_ERR_PARAM;
5240         }
5241
5242         if (info->on) {
5243                 vsi->info.pvid = info->config.pvid;
5244                 /**
5245                  * If insert pvid is enabled, only tagged pkts are
5246                  * allowed to be sent out.
5247                  */
5248                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
5249                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5250         } else {
5251                 vsi->info.pvid = 0;
5252                 if (info->config.reject.tagged == 0)
5253                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5254
5255                 if (info->config.reject.untagged == 0)
5256                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
5257         }
5258         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
5259                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
5260         vsi->info.port_vlan_flags |= vlan_flags;
5261         vsi->info.valid_sections =
5262                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5263         memset(&ctxt, 0, sizeof(ctxt));
5264         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5265         ctxt.seid = vsi->seid;
5266
5267         hw = I40E_VSI_TO_HW(vsi);
5268         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5269         if (ret != I40E_SUCCESS)
5270                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5271
5272         return ret;
5273 }
5274
5275 static int
5276 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5277 {
5278         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5279         int i, ret;
5280         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
5281
5282         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5283         if (ret != I40E_SUCCESS)
5284                 return ret;
5285
5286         if (!vsi->seid) {
5287                 PMD_DRV_LOG(ERR, "seid not valid");
5288                 return -EINVAL;
5289         }
5290
5291         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
5292         tc_bw_data.tc_valid_bits = enabled_tcmap;
5293         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5294                 tc_bw_data.tc_bw_credits[i] =
5295                         (enabled_tcmap & (1 << i)) ? 1 : 0;
5296
5297         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5298         if (ret != I40E_SUCCESS) {
5299                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5300                 return ret;
5301         }
5302
5303         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5304                                         sizeof(vsi->info.qs_handle));
5305         return I40E_SUCCESS;
5306 }
5307
5308 static enum i40e_status_code
5309 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5310                                  struct i40e_aqc_vsi_properties_data *info,
5311                                  uint8_t enabled_tcmap)
5312 {
5313         enum i40e_status_code ret;
5314         int i, total_tc = 0;
5315         uint16_t qpnum_per_tc, bsf, qp_idx;
5316
5317         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5318         if (ret != I40E_SUCCESS)
5319                 return ret;
5320
5321         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5322                 if (enabled_tcmap & (1 << i))
5323                         total_tc++;
5324         if (total_tc == 0)
5325                 total_tc = 1;
5326         vsi->enabled_tc = enabled_tcmap;
5327
5328         /* Number of queues per enabled TC */
5329         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5330         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5331         bsf = rte_bsf32(qpnum_per_tc);
5332
5333         /* Adjust the queue number to actual queues that can be applied */
5334         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5335                 vsi->nb_qps = qpnum_per_tc * total_tc;
5336
5337         /**
5338          * Configure TC and queue mapping parameters, for enabled TC,
5339          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5340          * default queue will serve it.
5341          */
5342         qp_idx = 0;
5343         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5344                 if (vsi->enabled_tc & (1 << i)) {
5345                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5346                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5347                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5348                         qp_idx += qpnum_per_tc;
5349                 } else
5350                         info->tc_mapping[i] = 0;
5351         }
5352
5353         /* Associate queue number with VSI */
5354         if (vsi->type == I40E_VSI_SRIOV) {
5355                 info->mapping_flags |=
5356                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5357                 for (i = 0; i < vsi->nb_qps; i++)
5358                         info->queue_mapping[i] =
5359                                 rte_cpu_to_le_16(vsi->base_queue + i);
5360         } else {
5361                 info->mapping_flags |=
5362                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5363                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5364         }
5365         info->valid_sections |=
5366                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5367
5368         return I40E_SUCCESS;
5369 }
5370
5371 static int
5372 i40e_veb_release(struct i40e_veb *veb)
5373 {
5374         struct i40e_vsi *vsi;
5375         struct i40e_hw *hw;
5376
5377         if (veb == NULL)
5378                 return -EINVAL;
5379
5380         if (!TAILQ_EMPTY(&veb->head)) {
5381                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5382                 return -EACCES;
5383         }
5384         /* associate_vsi field is NULL for floating VEB */
5385         if (veb->associate_vsi != NULL) {
5386                 vsi = veb->associate_vsi;
5387                 hw = I40E_VSI_TO_HW(vsi);
5388
5389                 vsi->uplink_seid = veb->uplink_seid;
5390                 vsi->veb = NULL;
5391         } else {
5392                 veb->associate_pf->main_vsi->floating_veb = NULL;
5393                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5394         }
5395
5396         i40e_aq_delete_element(hw, veb->seid, NULL);
5397         rte_free(veb);
5398         return I40E_SUCCESS;
5399 }
5400
5401 /* Setup a veb */
5402 static struct i40e_veb *
5403 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5404 {
5405         struct i40e_veb *veb;
5406         int ret;
5407         struct i40e_hw *hw;
5408
5409         if (pf == NULL) {
5410                 PMD_DRV_LOG(ERR,
5411                             "veb setup failed, associated PF shouldn't null");
5412                 return NULL;
5413         }
5414         hw = I40E_PF_TO_HW(pf);
5415
5416         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5417         if (!veb) {
5418                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5419                 goto fail;
5420         }
5421
5422         veb->associate_vsi = vsi;
5423         veb->associate_pf = pf;
5424         TAILQ_INIT(&veb->head);
5425         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5426
5427         /* create floating veb if vsi is NULL */
5428         if (vsi != NULL) {
5429                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5430                                       I40E_DEFAULT_TCMAP, false,
5431                                       &veb->seid, false, NULL);
5432         } else {
5433                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5434                                       true, &veb->seid, false, NULL);
5435         }
5436
5437         if (ret != I40E_SUCCESS) {
5438                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5439                             hw->aq.asq_last_status);
5440                 goto fail;
5441         }
5442         veb->enabled_tc = I40E_DEFAULT_TCMAP;
5443
5444         /* get statistics index */
5445         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5446                                 &veb->stats_idx, NULL, NULL, NULL);
5447         if (ret != I40E_SUCCESS) {
5448                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5449                             hw->aq.asq_last_status);
5450                 goto fail;
5451         }
5452         /* Get VEB bandwidth, to be implemented */
5453         /* Now associated vsi binding to the VEB, set uplink to this VEB */
5454         if (vsi)
5455                 vsi->uplink_seid = veb->seid;
5456
5457         return veb;
5458 fail:
5459         rte_free(veb);
5460         return NULL;
5461 }
5462
5463 int
5464 i40e_vsi_release(struct i40e_vsi *vsi)
5465 {
5466         struct i40e_pf *pf;
5467         struct i40e_hw *hw;
5468         struct i40e_vsi_list *vsi_list;
5469         void *temp;
5470         int ret;
5471         struct i40e_mac_filter *f;
5472         uint16_t user_param;
5473
5474         if (!vsi)
5475                 return I40E_SUCCESS;
5476
5477         if (!vsi->adapter)
5478                 return -EFAULT;
5479
5480         user_param = vsi->user_param;
5481
5482         pf = I40E_VSI_TO_PF(vsi);
5483         hw = I40E_VSI_TO_HW(vsi);
5484
5485         /* VSI has child to attach, release child first */
5486         if (vsi->veb) {
5487                 RTE_TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5488                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5489                                 return -1;
5490                 }
5491                 i40e_veb_release(vsi->veb);
5492         }
5493
5494         if (vsi->floating_veb) {
5495                 RTE_TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head,
5496                         list, temp) {
5497                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5498                                 return -1;
5499                 }
5500         }
5501
5502         /* Remove all macvlan filters of the VSI */
5503         i40e_vsi_remove_all_macvlan_filter(vsi);
5504         RTE_TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5505                 rte_free(f);
5506
5507         if (vsi->type != I40E_VSI_MAIN &&
5508             ((vsi->type != I40E_VSI_SRIOV) ||
5509             !pf->floating_veb_list[user_param])) {
5510                 /* Remove vsi from parent's sibling list */
5511                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5512                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5513                         return I40E_ERR_PARAM;
5514                 }
5515                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5516                                 &vsi->sib_vsi_list, list);
5517
5518                 /* Remove all switch element of the VSI */
5519                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5520                 if (ret != I40E_SUCCESS)
5521                         PMD_DRV_LOG(ERR, "Failed to delete element");
5522         }
5523
5524         if ((vsi->type == I40E_VSI_SRIOV) &&
5525             pf->floating_veb_list[user_param]) {
5526                 /* Remove vsi from parent's sibling list */
5527                 if (vsi->parent_vsi == NULL ||
5528                     vsi->parent_vsi->floating_veb == NULL) {
5529                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5530                         return I40E_ERR_PARAM;
5531                 }
5532                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5533                              &vsi->sib_vsi_list, list);
5534
5535                 /* Remove all switch element of the VSI */
5536                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5537                 if (ret != I40E_SUCCESS)
5538                         PMD_DRV_LOG(ERR, "Failed to delete element");
5539         }
5540
5541         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5542
5543         if (vsi->type != I40E_VSI_SRIOV)
5544                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5545         rte_free(vsi);
5546
5547         return I40E_SUCCESS;
5548 }
5549
5550 static int
5551 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5552 {
5553         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5554         struct i40e_aqc_remove_macvlan_element_data def_filter;
5555         struct i40e_mac_filter_info filter;
5556         int ret;
5557
5558         if (vsi->type != I40E_VSI_MAIN)
5559                 return I40E_ERR_CONFIG;
5560         memset(&def_filter, 0, sizeof(def_filter));
5561         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5562                                         ETH_ADDR_LEN);
5563         def_filter.vlan_tag = 0;
5564         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5565                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5566         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5567         if (ret != I40E_SUCCESS) {
5568                 struct i40e_mac_filter *f;
5569                 struct rte_ether_addr *mac;
5570
5571                 PMD_DRV_LOG(DEBUG,
5572                             "Cannot remove the default macvlan filter");
5573                 /* It needs to add the permanent mac into mac list */
5574                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5575                 if (f == NULL) {
5576                         PMD_DRV_LOG(ERR, "failed to allocate memory");
5577                         return I40E_ERR_NO_MEMORY;
5578                 }
5579                 mac = &f->mac_info.mac_addr;
5580                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5581                                 ETH_ADDR_LEN);
5582                 f->mac_info.filter_type = I40E_MACVLAN_PERFECT_MATCH;
5583                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5584                 vsi->mac_num++;
5585
5586                 return ret;
5587         }
5588         rte_memcpy(&filter.mac_addr,
5589                 (struct rte_ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5590         filter.filter_type = I40E_MACVLAN_PERFECT_MATCH;
5591         return i40e_vsi_add_mac(vsi, &filter);
5592 }
5593
5594 /*
5595  * i40e_vsi_get_bw_config - Query VSI BW Information
5596  * @vsi: the VSI to be queried
5597  *
5598  * Returns 0 on success, negative value on failure
5599  */
5600 static enum i40e_status_code
5601 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5602 {
5603         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5604         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5605         struct i40e_hw *hw = &vsi->adapter->hw;
5606         i40e_status ret;
5607         int i;
5608         uint32_t bw_max;
5609
5610         memset(&bw_config, 0, sizeof(bw_config));
5611         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5612         if (ret != I40E_SUCCESS) {
5613                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5614                             hw->aq.asq_last_status);
5615                 return ret;
5616         }
5617
5618         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5619         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5620                                         &ets_sla_config, NULL);
5621         if (ret != I40E_SUCCESS) {
5622                 PMD_DRV_LOG(ERR,
5623                         "VSI failed to get TC bandwidth configuration %u",
5624                         hw->aq.asq_last_status);
5625                 return ret;
5626         }
5627
5628         /* store and print out BW info */
5629         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5630         vsi->bw_info.bw_max = bw_config.max_bw;
5631         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5632         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5633         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5634                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5635                      I40E_16_BIT_WIDTH);
5636         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5637                 vsi->bw_info.bw_ets_share_credits[i] =
5638                                 ets_sla_config.share_credits[i];
5639                 vsi->bw_info.bw_ets_credits[i] =
5640                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5641                 /* 4 bits per TC, 4th bit is reserved */
5642                 vsi->bw_info.bw_ets_max[i] =
5643                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5644                                   RTE_LEN2MASK(3, uint8_t));
5645                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5646                             vsi->bw_info.bw_ets_share_credits[i]);
5647                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5648                             vsi->bw_info.bw_ets_credits[i]);
5649                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5650                             vsi->bw_info.bw_ets_max[i]);
5651         }
5652
5653         return I40E_SUCCESS;
5654 }
5655
5656 /* i40e_enable_pf_lb
5657  * @pf: pointer to the pf structure
5658  *
5659  * allow loopback on pf
5660  */
5661 static inline void
5662 i40e_enable_pf_lb(struct i40e_pf *pf)
5663 {
5664         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5665         struct i40e_vsi_context ctxt;
5666         int ret;
5667
5668         /* Use the FW API if FW >= v5.0 */
5669         if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
5670                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5671                 return;
5672         }
5673
5674         memset(&ctxt, 0, sizeof(ctxt));
5675         ctxt.seid = pf->main_vsi_seid;
5676         ctxt.pf_num = hw->pf_id;
5677         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5678         if (ret) {
5679                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5680                             ret, hw->aq.asq_last_status);
5681                 return;
5682         }
5683         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5684         ctxt.info.valid_sections =
5685                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5686         ctxt.info.switch_id |=
5687                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5688
5689         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5690         if (ret)
5691                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5692                             hw->aq.asq_last_status);
5693 }
5694
5695 /* Setup a VSI */
5696 struct i40e_vsi *
5697 i40e_vsi_setup(struct i40e_pf *pf,
5698                enum i40e_vsi_type type,
5699                struct i40e_vsi *uplink_vsi,
5700                uint16_t user_param)
5701 {
5702         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5703         struct i40e_vsi *vsi;
5704         struct i40e_mac_filter_info filter;
5705         int ret;
5706         struct i40e_vsi_context ctxt;
5707         struct rte_ether_addr broadcast =
5708                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5709
5710         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5711             uplink_vsi == NULL) {
5712                 PMD_DRV_LOG(ERR,
5713                         "VSI setup failed, VSI link shouldn't be NULL");
5714                 return NULL;
5715         }
5716
5717         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5718                 PMD_DRV_LOG(ERR,
5719                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5720                 return NULL;
5721         }
5722
5723         /* two situations
5724          * 1.type is not MAIN and uplink vsi is not NULL
5725          * If uplink vsi didn't setup VEB, create one first under veb field
5726          * 2.type is SRIOV and the uplink is NULL
5727          * If floating VEB is NULL, create one veb under floating veb field
5728          */
5729
5730         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5731             uplink_vsi->veb == NULL) {
5732                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5733
5734                 if (uplink_vsi->veb == NULL) {
5735                         PMD_DRV_LOG(ERR, "VEB setup failed");
5736                         return NULL;
5737                 }
5738                 /* set ALLOWLOOPBACk on pf, when veb is created */
5739                 i40e_enable_pf_lb(pf);
5740         }
5741
5742         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5743             pf->main_vsi->floating_veb == NULL) {
5744                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5745
5746                 if (pf->main_vsi->floating_veb == NULL) {
5747                         PMD_DRV_LOG(ERR, "VEB setup failed");
5748                         return NULL;
5749                 }
5750         }
5751
5752         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5753         if (!vsi) {
5754                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5755                 return NULL;
5756         }
5757         TAILQ_INIT(&vsi->mac_list);
5758         vsi->type = type;
5759         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5760         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5761         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5762         vsi->user_param = user_param;
5763         vsi->vlan_anti_spoof_on = 0;
5764         vsi->vlan_filter_on = 0;
5765         /* Allocate queues */
5766         switch (vsi->type) {
5767         case I40E_VSI_MAIN  :
5768                 vsi->nb_qps = pf->lan_nb_qps;
5769                 break;
5770         case I40E_VSI_SRIOV :
5771                 vsi->nb_qps = pf->vf_nb_qps;
5772                 break;
5773         case I40E_VSI_VMDQ2:
5774                 vsi->nb_qps = pf->vmdq_nb_qps;
5775                 break;
5776         case I40E_VSI_FDIR:
5777                 vsi->nb_qps = pf->fdir_nb_qps;
5778                 break;
5779         default:
5780                 goto fail_mem;
5781         }
5782         /*
5783          * The filter status descriptor is reported in rx queue 0,
5784          * while the tx queue for fdir filter programming has no
5785          * such constraints, can be non-zero queues.
5786          * To simplify it, choose FDIR vsi use queue 0 pair.
5787          * To make sure it will use queue 0 pair, queue allocation
5788          * need be done before this function is called
5789          */
5790         if (type != I40E_VSI_FDIR) {
5791                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5792                         if (ret < 0) {
5793                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5794                                                 vsi->seid, ret);
5795                                 goto fail_mem;
5796                         }
5797                         vsi->base_queue = ret;
5798         } else
5799                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5800
5801         /* VF has MSIX interrupt in VF range, don't allocate here */
5802         if (type == I40E_VSI_MAIN) {
5803                 if (pf->support_multi_driver) {
5804                         /* If support multi-driver, need to use INT0 instead of
5805                          * allocating from msix pool. The Msix pool is init from
5806                          * INT1, so it's OK just set msix_intr to 0 and nb_msix
5807                          * to 1 without calling i40e_res_pool_alloc.
5808                          */
5809                         vsi->msix_intr = 0;
5810                         vsi->nb_msix = 1;
5811                 } else {
5812                         ret = i40e_res_pool_alloc(&pf->msix_pool,
5813                                                   RTE_MIN(vsi->nb_qps,
5814                                                      RTE_MAX_RXTX_INTR_VEC_ID));
5815                         if (ret < 0) {
5816                                 PMD_DRV_LOG(ERR,
5817                                             "VSI MAIN %d get heap failed %d",
5818                                             vsi->seid, ret);
5819                                 goto fail_queue_alloc;
5820                         }
5821                         vsi->msix_intr = ret;
5822                         vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5823                                                RTE_MAX_RXTX_INTR_VEC_ID);
5824                 }
5825         } else if (type != I40E_VSI_SRIOV) {
5826                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5827                 if (ret < 0) {
5828                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5829                         if (type != I40E_VSI_FDIR)
5830                                 goto fail_queue_alloc;
5831                         vsi->msix_intr = 0;
5832                         vsi->nb_msix = 0;
5833                 } else {
5834                         vsi->msix_intr = ret;
5835                         vsi->nb_msix = 1;
5836                 }
5837         } else {
5838                 vsi->msix_intr = 0;
5839                 vsi->nb_msix = 0;
5840         }
5841
5842         /* Add VSI */
5843         if (type == I40E_VSI_MAIN) {
5844                 /* For main VSI, no need to add since it's default one */
5845                 vsi->uplink_seid = pf->mac_seid;
5846                 vsi->seid = pf->main_vsi_seid;
5847                 /* Bind queues with specific MSIX interrupt */
5848                 /**
5849                  * Needs 2 interrupt at least, one for misc cause which will
5850                  * enabled from OS side, Another for queues binding the
5851                  * interrupt from device side only.
5852                  */
5853
5854                 /* Get default VSI parameters from hardware */
5855                 memset(&ctxt, 0, sizeof(ctxt));
5856                 ctxt.seid = vsi->seid;
5857                 ctxt.pf_num = hw->pf_id;
5858                 ctxt.uplink_seid = vsi->uplink_seid;
5859                 ctxt.vf_num = 0;
5860                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5861                 if (ret != I40E_SUCCESS) {
5862                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
5863                         goto fail_msix_alloc;
5864                 }
5865                 rte_memcpy(&vsi->info, &ctxt.info,
5866                         sizeof(struct i40e_aqc_vsi_properties_data));
5867                 vsi->vsi_id = ctxt.vsi_number;
5868                 vsi->info.valid_sections = 0;
5869
5870                 /* Configure tc, enabled TC0 only */
5871                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5872                         I40E_SUCCESS) {
5873                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5874                         goto fail_msix_alloc;
5875                 }
5876
5877                 /* TC, queue mapping */
5878                 memset(&ctxt, 0, sizeof(ctxt));
5879                 vsi->info.valid_sections |=
5880                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5881                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5882                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5883                 rte_memcpy(&ctxt.info, &vsi->info,
5884                         sizeof(struct i40e_aqc_vsi_properties_data));
5885                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5886                                                 I40E_DEFAULT_TCMAP);
5887                 if (ret != I40E_SUCCESS) {
5888                         PMD_DRV_LOG(ERR,
5889                                 "Failed to configure TC queue mapping");
5890                         goto fail_msix_alloc;
5891                 }
5892                 ctxt.seid = vsi->seid;
5893                 ctxt.pf_num = hw->pf_id;
5894                 ctxt.uplink_seid = vsi->uplink_seid;
5895                 ctxt.vf_num = 0;
5896
5897                 /* Update VSI parameters */
5898                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5899                 if (ret != I40E_SUCCESS) {
5900                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5901                         goto fail_msix_alloc;
5902                 }
5903
5904                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5905                                                 sizeof(vsi->info.tc_mapping));
5906                 rte_memcpy(&vsi->info.queue_mapping,
5907                                 &ctxt.info.queue_mapping,
5908                         sizeof(vsi->info.queue_mapping));
5909                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5910                 vsi->info.valid_sections = 0;
5911
5912                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5913                                 ETH_ADDR_LEN);
5914
5915                 /**
5916                  * Updating default filter settings are necessary to prevent
5917                  * reception of tagged packets.
5918                  * Some old firmware configurations load a default macvlan
5919                  * filter which accepts both tagged and untagged packets.
5920                  * The updating is to use a normal filter instead if needed.
5921                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5922                  * The firmware with correct configurations load the default
5923                  * macvlan filter which is expected and cannot be removed.
5924                  */
5925                 i40e_update_default_filter_setting(vsi);
5926                 i40e_config_qinq(hw, vsi);
5927         } else if (type == I40E_VSI_SRIOV) {
5928                 memset(&ctxt, 0, sizeof(ctxt));
5929                 /**
5930                  * For other VSI, the uplink_seid equals to uplink VSI's
5931                  * uplink_seid since they share same VEB
5932                  */
5933                 if (uplink_vsi == NULL)
5934                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5935                 else
5936                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5937                 ctxt.pf_num = hw->pf_id;
5938                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5939                 ctxt.uplink_seid = vsi->uplink_seid;
5940                 ctxt.connection_type = 0x1;
5941                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5942
5943                 /* Use the VEB configuration if FW >= v5.0 */
5944                 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
5945                         /* Configure switch ID */
5946                         ctxt.info.valid_sections |=
5947                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5948                         ctxt.info.switch_id =
5949                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5950                 }
5951
5952                 /* Configure port/vlan */
5953                 ctxt.info.valid_sections |=
5954                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5955                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5956                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5957                                                 hw->func_caps.enabled_tcmap);
5958                 if (ret != I40E_SUCCESS) {
5959                         PMD_DRV_LOG(ERR,
5960                                 "Failed to configure TC queue mapping");
5961                         goto fail_msix_alloc;
5962                 }
5963
5964                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5965                 ctxt.info.valid_sections |=
5966                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5967                 /**
5968                  * Since VSI is not created yet, only configure parameter,
5969                  * will add vsi below.
5970                  */
5971
5972                 i40e_config_qinq(hw, vsi);
5973         } else if (type == I40E_VSI_VMDQ2) {
5974                 memset(&ctxt, 0, sizeof(ctxt));
5975                 /*
5976                  * For other VSI, the uplink_seid equals to uplink VSI's
5977                  * uplink_seid since they share same VEB
5978                  */
5979                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5980                 ctxt.pf_num = hw->pf_id;
5981                 ctxt.vf_num = 0;
5982                 ctxt.uplink_seid = vsi->uplink_seid;
5983                 ctxt.connection_type = 0x1;
5984                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5985
5986                 ctxt.info.valid_sections |=
5987                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5988                 /* user_param carries flag to enable loop back */
5989                 if (user_param) {
5990                         ctxt.info.switch_id =
5991                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5992                         ctxt.info.switch_id |=
5993                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5994                 }
5995
5996                 /* Configure port/vlan */
5997                 ctxt.info.valid_sections |=
5998                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5999                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
6000                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
6001                                                 I40E_DEFAULT_TCMAP);
6002                 if (ret != I40E_SUCCESS) {
6003                         PMD_DRV_LOG(ERR,
6004                                 "Failed to configure TC queue mapping");
6005                         goto fail_msix_alloc;
6006                 }
6007                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
6008                 ctxt.info.valid_sections |=
6009                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
6010         } else if (type == I40E_VSI_FDIR) {
6011                 memset(&ctxt, 0, sizeof(ctxt));
6012                 vsi->uplink_seid = uplink_vsi->uplink_seid;
6013                 ctxt.pf_num = hw->pf_id;
6014                 ctxt.vf_num = 0;
6015                 ctxt.uplink_seid = vsi->uplink_seid;
6016                 ctxt.connection_type = 0x1;     /* regular data port */
6017                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6018                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
6019                                                 I40E_DEFAULT_TCMAP);
6020                 if (ret != I40E_SUCCESS) {
6021                         PMD_DRV_LOG(ERR,
6022                                 "Failed to configure TC queue mapping.");
6023                         goto fail_msix_alloc;
6024                 }
6025                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
6026                 ctxt.info.valid_sections |=
6027                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
6028         } else {
6029                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
6030                 goto fail_msix_alloc;
6031         }
6032
6033         if (vsi->type != I40E_VSI_MAIN) {
6034                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
6035                 if (ret != I40E_SUCCESS) {
6036                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
6037                                     hw->aq.asq_last_status);
6038                         goto fail_msix_alloc;
6039                 }
6040                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
6041                 vsi->info.valid_sections = 0;
6042                 vsi->seid = ctxt.seid;
6043                 vsi->vsi_id = ctxt.vsi_number;
6044                 vsi->sib_vsi_list.vsi = vsi;
6045                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
6046                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
6047                                           &vsi->sib_vsi_list, list);
6048                 } else {
6049                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
6050                                           &vsi->sib_vsi_list, list);
6051                 }
6052         }
6053
6054         /* MAC/VLAN configuration */
6055         rte_memcpy(&filter.mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
6056         filter.filter_type = I40E_MACVLAN_PERFECT_MATCH;
6057
6058         ret = i40e_vsi_add_mac(vsi, &filter);
6059         if (ret != I40E_SUCCESS) {
6060                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
6061                 goto fail_msix_alloc;
6062         }
6063
6064         /* Get VSI BW information */
6065         i40e_vsi_get_bw_config(vsi);
6066         return vsi;
6067 fail_msix_alloc:
6068         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
6069 fail_queue_alloc:
6070         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
6071 fail_mem:
6072         rte_free(vsi);
6073         return NULL;
6074 }
6075
6076 /* Configure vlan filter on or off */
6077 int
6078 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
6079 {
6080         int i, num;
6081         struct i40e_mac_filter *f;
6082         void *temp;
6083         struct i40e_mac_filter_info *mac_filter;
6084         enum i40e_mac_filter_type desired_filter;
6085         int ret = I40E_SUCCESS;
6086
6087         if (on) {
6088                 /* Filter to match MAC and VLAN */
6089                 desired_filter = I40E_MACVLAN_PERFECT_MATCH;
6090         } else {
6091                 /* Filter to match only MAC */
6092                 desired_filter = I40E_MAC_PERFECT_MATCH;
6093         }
6094
6095         num = vsi->mac_num;
6096
6097         mac_filter = rte_zmalloc("mac_filter_info_data",
6098                                  num * sizeof(*mac_filter), 0);
6099         if (mac_filter == NULL) {
6100                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6101                 return I40E_ERR_NO_MEMORY;
6102         }
6103
6104         i = 0;
6105
6106         /* Remove all existing mac */
6107         RTE_TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
6108                 mac_filter[i] = f->mac_info;
6109                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
6110                 if (ret) {
6111                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6112                                     on ? "enable" : "disable");
6113                         goto DONE;
6114                 }
6115                 i++;
6116         }
6117
6118         /* Override with new filter */
6119         for (i = 0; i < num; i++) {
6120                 mac_filter[i].filter_type = desired_filter;
6121                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
6122                 if (ret) {
6123                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6124                                     on ? "enable" : "disable");
6125                         goto DONE;
6126                 }
6127         }
6128
6129 DONE:
6130         rte_free(mac_filter);
6131         return ret;
6132 }
6133
6134 /* Configure vlan stripping on or off */
6135 int
6136 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
6137 {
6138         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6139         struct i40e_vsi_context ctxt;
6140         uint8_t vlan_flags;
6141         int ret = I40E_SUCCESS;
6142
6143         /* Check if it has been already on or off */
6144         if (vsi->info.valid_sections &
6145                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
6146                 if (on) {
6147                         if ((vsi->info.port_vlan_flags &
6148                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
6149                                 return 0; /* already on */
6150                 } else {
6151                         if ((vsi->info.port_vlan_flags &
6152                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
6153                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
6154                                 return 0; /* already off */
6155                 }
6156         }
6157
6158         if (on)
6159                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
6160         else
6161                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
6162         vsi->info.valid_sections =
6163                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
6164         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
6165         vsi->info.port_vlan_flags |= vlan_flags;
6166         ctxt.seid = vsi->seid;
6167         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
6168         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6169         if (ret)
6170                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
6171                             on ? "enable" : "disable");
6172
6173         return ret;
6174 }
6175
6176 static int
6177 i40e_dev_init_vlan(struct rte_eth_dev *dev)
6178 {
6179         struct rte_eth_dev_data *data = dev->data;
6180         int ret;
6181         int mask = 0;
6182
6183         /* Apply vlan offload setting */
6184         mask = RTE_ETH_VLAN_STRIP_MASK |
6185                RTE_ETH_QINQ_STRIP_MASK |
6186                RTE_ETH_VLAN_FILTER_MASK |
6187                RTE_ETH_VLAN_EXTEND_MASK;
6188         ret = i40e_vlan_offload_set(dev, mask);
6189         if (ret) {
6190                 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
6191                 return ret;
6192         }
6193
6194         /* Apply pvid setting */
6195         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
6196                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
6197         if (ret)
6198                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
6199
6200         return ret;
6201 }
6202
6203 static int
6204 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
6205 {
6206         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6207
6208         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
6209 }
6210
6211 static int
6212 i40e_update_flow_control(struct i40e_hw *hw)
6213 {
6214 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
6215         struct i40e_link_status link_status;
6216         uint32_t rxfc = 0, txfc = 0, reg;
6217         uint8_t an_info;
6218         int ret;
6219
6220         memset(&link_status, 0, sizeof(link_status));
6221         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
6222         if (ret != I40E_SUCCESS) {
6223                 PMD_DRV_LOG(ERR, "Failed to get link status information");
6224                 goto write_reg; /* Disable flow control */
6225         }
6226
6227         an_info = hw->phy.link_info.an_info;
6228         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
6229                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
6230                 ret = I40E_ERR_NOT_READY;
6231                 goto write_reg; /* Disable flow control */
6232         }
6233         /**
6234          * If link auto negotiation is enabled, flow control needs to
6235          * be configured according to it
6236          */
6237         switch (an_info & I40E_LINK_PAUSE_RXTX) {
6238         case I40E_LINK_PAUSE_RXTX:
6239                 rxfc = 1;
6240                 txfc = 1;
6241                 hw->fc.current_mode = I40E_FC_FULL;
6242                 break;
6243         case I40E_AQ_LINK_PAUSE_RX:
6244                 rxfc = 1;
6245                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
6246                 break;
6247         case I40E_AQ_LINK_PAUSE_TX:
6248                 txfc = 1;
6249                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
6250                 break;
6251         default:
6252                 hw->fc.current_mode = I40E_FC_NONE;
6253                 break;
6254         }
6255
6256 write_reg:
6257         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
6258                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
6259         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
6260         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
6261         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
6262         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
6263
6264         return ret;
6265 }
6266
6267 /* PF setup */
6268 static int
6269 i40e_pf_setup(struct i40e_pf *pf)
6270 {
6271         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6272         struct i40e_filter_control_settings settings;
6273         struct i40e_vsi *vsi;
6274         int ret;
6275
6276         /* Clear all stats counters */
6277         pf->offset_loaded = FALSE;
6278         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
6279         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
6280         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
6281         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
6282         pf->rx_err1 = 0;
6283         pf->rx_err1_offset = 0;
6284
6285         ret = i40e_pf_get_switch_config(pf);
6286         if (ret != I40E_SUCCESS) {
6287                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
6288                 return ret;
6289         }
6290
6291         ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
6292         if (ret)
6293                 PMD_INIT_LOG(WARNING,
6294                         "failed to allocate switch domain for device %d", ret);
6295
6296         if (pf->flags & I40E_FLAG_FDIR) {
6297                 /* make queue allocated first, let FDIR use queue pair 0*/
6298                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
6299                 if (ret != I40E_FDIR_QUEUE_ID) {
6300                         PMD_DRV_LOG(ERR,
6301                                 "queue allocation fails for FDIR: ret =%d",
6302                                 ret);
6303                         pf->flags &= ~I40E_FLAG_FDIR;
6304                 }
6305         }
6306         /*  main VSI setup */
6307         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6308         if (!vsi) {
6309                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6310                 return I40E_ERR_NOT_READY;
6311         }
6312         pf->main_vsi = vsi;
6313
6314         /* Configure filter control */
6315         memset(&settings, 0, sizeof(settings));
6316         if (hw->func_caps.rss_table_size == RTE_ETH_RSS_RETA_SIZE_128)
6317                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6318         else if (hw->func_caps.rss_table_size == RTE_ETH_RSS_RETA_SIZE_512)
6319                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6320         else {
6321                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6322                         hw->func_caps.rss_table_size);
6323                 return I40E_ERR_PARAM;
6324         }
6325         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6326                 hw->func_caps.rss_table_size);
6327         pf->hash_lut_size = hw->func_caps.rss_table_size;
6328
6329         /* Enable ethtype and macvlan filters */
6330         settings.enable_ethtype = TRUE;
6331         settings.enable_macvlan = TRUE;
6332         ret = i40e_set_filter_control(hw, &settings);
6333         if (ret)
6334                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6335                                                                 ret);
6336
6337         /* Update flow control according to the auto negotiation */
6338         i40e_update_flow_control(hw);
6339
6340         return I40E_SUCCESS;
6341 }
6342
6343 int
6344 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6345 {
6346         uint32_t reg;
6347         uint16_t j;
6348
6349         /**
6350          * Set or clear TX Queue Disable flags,
6351          * which is required by hardware.
6352          */
6353         i40e_pre_tx_queue_cfg(hw, q_idx, on);
6354         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6355
6356         /* Wait until the request is finished */
6357         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6358                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6359                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6360                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6361                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6362                                                         & 0x1))) {
6363                         break;
6364                 }
6365         }
6366         if (on) {
6367                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6368                         return I40E_SUCCESS; /* already on, skip next steps */
6369
6370                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6371                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6372         } else {
6373                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6374                         return I40E_SUCCESS; /* already off, skip next steps */
6375                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6376         }
6377         /* Write the register */
6378         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6379         /* Check the result */
6380         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6381                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6382                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6383                 if (on) {
6384                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6385                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6386                                 break;
6387                 } else {
6388                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6389                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6390                                 break;
6391                 }
6392         }
6393         /* Check if it is timeout */
6394         if (j >= I40E_CHK_Q_ENA_COUNT) {
6395                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6396                             (on ? "enable" : "disable"), q_idx);
6397                 return I40E_ERR_TIMEOUT;
6398         }
6399
6400         return I40E_SUCCESS;
6401 }
6402
6403 int
6404 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6405 {
6406         uint32_t reg;
6407         uint16_t j;
6408
6409         /* Wait until the request is finished */
6410         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6411                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6412                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6413                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6414                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6415                         break;
6416         }
6417
6418         if (on) {
6419                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6420                         return I40E_SUCCESS; /* Already on, skip next steps */
6421                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6422         } else {
6423                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6424                         return I40E_SUCCESS; /* Already off, skip next steps */
6425                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6426         }
6427
6428         /* Write the register */
6429         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6430         /* Check the result */
6431         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6432                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6433                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6434                 if (on) {
6435                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6436                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6437                                 break;
6438                 } else {
6439                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6440                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6441                                 break;
6442                 }
6443         }
6444
6445         /* Check if it is timeout */
6446         if (j >= I40E_CHK_Q_ENA_COUNT) {
6447                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6448                             (on ? "enable" : "disable"), q_idx);
6449                 return I40E_ERR_TIMEOUT;
6450         }
6451
6452         return I40E_SUCCESS;
6453 }
6454
6455 /* Initialize VSI for TX */
6456 static int
6457 i40e_dev_tx_init(struct i40e_pf *pf)
6458 {
6459         struct rte_eth_dev_data *data = pf->dev_data;
6460         uint16_t i;
6461         uint32_t ret = I40E_SUCCESS;
6462         struct i40e_tx_queue *txq;
6463
6464         for (i = 0; i < data->nb_tx_queues; i++) {
6465                 txq = data->tx_queues[i];
6466                 if (!txq || !txq->q_set)
6467                         continue;
6468                 ret = i40e_tx_queue_init(txq);
6469                 if (ret != I40E_SUCCESS)
6470                         break;
6471         }
6472         if (ret == I40E_SUCCESS)
6473                 i40e_set_tx_function(&rte_eth_devices[pf->dev_data->port_id]);
6474
6475         return ret;
6476 }
6477
6478 /* Initialize VSI for RX */
6479 static int
6480 i40e_dev_rx_init(struct i40e_pf *pf)
6481 {
6482         struct rte_eth_dev_data *data = pf->dev_data;
6483         int ret = I40E_SUCCESS;
6484         uint16_t i;
6485         struct i40e_rx_queue *rxq;
6486
6487         i40e_pf_config_rss(pf);
6488         for (i = 0; i < data->nb_rx_queues; i++) {
6489                 rxq = data->rx_queues[i];
6490                 if (!rxq || !rxq->q_set)
6491                         continue;
6492
6493                 ret = i40e_rx_queue_init(rxq);
6494                 if (ret != I40E_SUCCESS) {
6495                         PMD_DRV_LOG(ERR,
6496                                 "Failed to do RX queue initialization");
6497                         break;
6498                 }
6499         }
6500         if (ret == I40E_SUCCESS)
6501                 i40e_set_rx_function(&rte_eth_devices[pf->dev_data->port_id]);
6502
6503         return ret;
6504 }
6505
6506 static int
6507 i40e_dev_rxtx_init(struct i40e_pf *pf)
6508 {
6509         int err;
6510
6511         err = i40e_dev_tx_init(pf);
6512         if (err) {
6513                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6514                 return err;
6515         }
6516         err = i40e_dev_rx_init(pf);
6517         if (err) {
6518                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6519                 return err;
6520         }
6521
6522         return err;
6523 }
6524
6525 static int
6526 i40e_vmdq_setup(struct rte_eth_dev *dev)
6527 {
6528         struct rte_eth_conf *conf = &dev->data->dev_conf;
6529         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6530         int i, err, conf_vsis, j, loop;
6531         struct i40e_vsi *vsi;
6532         struct i40e_vmdq_info *vmdq_info;
6533         struct rte_eth_vmdq_rx_conf *vmdq_conf;
6534         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6535
6536         /*
6537          * Disable interrupt to avoid message from VF. Furthermore, it will
6538          * avoid race condition in VSI creation/destroy.
6539          */
6540         i40e_pf_disable_irq0(hw);
6541
6542         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6543                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6544                 return -ENOTSUP;
6545         }
6546
6547         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6548         if (conf_vsis > pf->max_nb_vmdq_vsi) {
6549                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6550                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6551                         pf->max_nb_vmdq_vsi);
6552                 return -ENOTSUP;
6553         }
6554
6555         if (pf->vmdq != NULL) {
6556                 PMD_INIT_LOG(INFO, "VMDQ already configured");
6557                 return 0;
6558         }
6559
6560         pf->vmdq = rte_zmalloc("vmdq_info_struct",
6561                                 sizeof(*vmdq_info) * conf_vsis, 0);
6562
6563         if (pf->vmdq == NULL) {
6564                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6565                 return -ENOMEM;
6566         }
6567
6568         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6569
6570         /* Create VMDQ VSI */
6571         for (i = 0; i < conf_vsis; i++) {
6572                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6573                                 vmdq_conf->enable_loop_back);
6574                 if (vsi == NULL) {
6575                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6576                         err = -1;
6577                         goto err_vsi_setup;
6578                 }
6579                 vmdq_info = &pf->vmdq[i];
6580                 vmdq_info->pf = pf;
6581                 vmdq_info->vsi = vsi;
6582         }
6583         pf->nb_cfg_vmdq_vsi = conf_vsis;
6584
6585         /* Configure Vlan */
6586         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6587         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6588                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6589                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6590                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6591                                         vmdq_conf->pool_map[i].vlan_id, j);
6592
6593                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6594                                                 vmdq_conf->pool_map[i].vlan_id);
6595                                 if (err) {
6596                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
6597                                         err = -1;
6598                                         goto err_vsi_setup;
6599                                 }
6600                         }
6601                 }
6602         }
6603
6604         i40e_pf_enable_irq0(hw);
6605
6606         return 0;
6607
6608 err_vsi_setup:
6609         for (i = 0; i < conf_vsis; i++)
6610                 if (pf->vmdq[i].vsi == NULL)
6611                         break;
6612                 else
6613                         i40e_vsi_release(pf->vmdq[i].vsi);
6614
6615         rte_free(pf->vmdq);
6616         pf->vmdq = NULL;
6617         i40e_pf_enable_irq0(hw);
6618         return err;
6619 }
6620
6621 static void
6622 i40e_stat_update_32(struct i40e_hw *hw,
6623                    uint32_t reg,
6624                    bool offset_loaded,
6625                    uint64_t *offset,
6626                    uint64_t *stat)
6627 {
6628         uint64_t new_data;
6629
6630         new_data = (uint64_t)I40E_READ_REG(hw, reg);
6631         if (!offset_loaded)
6632                 *offset = new_data;
6633
6634         if (new_data >= *offset)
6635                 *stat = (uint64_t)(new_data - *offset);
6636         else
6637                 *stat = (uint64_t)((new_data +
6638                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6639 }
6640
6641 static void
6642 i40e_stat_update_48(struct i40e_hw *hw,
6643                    uint32_t hireg,
6644                    uint32_t loreg,
6645                    bool offset_loaded,
6646                    uint64_t *offset,
6647                    uint64_t *stat)
6648 {
6649         uint64_t new_data;
6650
6651         if (hw->device_id == I40E_DEV_ID_QEMU) {
6652                 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6653                 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6654                                 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6655         } else {
6656                 new_data = I40E_READ_REG64(hw, loreg);
6657         }
6658
6659         if (!offset_loaded)
6660                 *offset = new_data;
6661
6662         if (new_data >= *offset)
6663                 *stat = new_data - *offset;
6664         else
6665                 *stat = (uint64_t)((new_data +
6666                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6667
6668         *stat &= I40E_48_BIT_MASK;
6669 }
6670
6671 /* Disable IRQ0 */
6672 void
6673 i40e_pf_disable_irq0(struct i40e_hw *hw)
6674 {
6675         /* Disable all interrupt types */
6676         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6677                        I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6678         I40E_WRITE_FLUSH(hw);
6679 }
6680
6681 /* Enable IRQ0 */
6682 void
6683 i40e_pf_enable_irq0(struct i40e_hw *hw)
6684 {
6685         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6686                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6687                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6688                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6689         I40E_WRITE_FLUSH(hw);
6690 }
6691
6692 static void
6693 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6694 {
6695         /* read pending request and disable first */
6696         i40e_pf_disable_irq0(hw);
6697         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6698         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6699                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6700
6701         if (no_queue)
6702                 /* Link no queues with irq0 */
6703                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6704                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6705 }
6706
6707 static void
6708 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6709 {
6710         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6711         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6712         int i;
6713         uint16_t abs_vf_id;
6714         uint32_t index, offset, val;
6715
6716         if (!pf->vfs)
6717                 return;
6718         /**
6719          * Try to find which VF trigger a reset, use absolute VF id to access
6720          * since the reg is global register.
6721          */
6722         for (i = 0; i < pf->vf_num; i++) {
6723                 abs_vf_id = hw->func_caps.vf_base_id + i;
6724                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6725                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6726                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6727                 /* VFR event occurred */
6728                 if (val & (0x1 << offset)) {
6729                         int ret;
6730
6731                         /* Clear the event first */
6732                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6733                                                         (0x1 << offset));
6734                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6735                         /**
6736                          * Only notify a VF reset event occurred,
6737                          * don't trigger another SW reset
6738                          */
6739                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6740                         if (ret != I40E_SUCCESS)
6741                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6742                 }
6743         }
6744 }
6745
6746 static void
6747 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6748 {
6749         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6750         int i;
6751
6752         for (i = 0; i < pf->vf_num; i++)
6753                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6754 }
6755
6756 static void
6757 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6758 {
6759         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6760         struct i40e_arq_event_info info;
6761         uint16_t pending, opcode;
6762         int ret;
6763
6764         info.buf_len = I40E_AQ_BUF_SZ;
6765         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6766         if (!info.msg_buf) {
6767                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6768                 return;
6769         }
6770
6771         pending = 1;
6772         while (pending) {
6773                 ret = i40e_clean_arq_element(hw, &info, &pending);
6774
6775                 if (ret != I40E_SUCCESS) {
6776                         PMD_DRV_LOG(INFO,
6777                                 "Failed to read msg from AdminQ, aq_err: %u",
6778                                 hw->aq.asq_last_status);
6779                         break;
6780                 }
6781                 opcode = rte_le_to_cpu_16(info.desc.opcode);
6782
6783                 switch (opcode) {
6784                 case i40e_aqc_opc_send_msg_to_pf:
6785                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6786                         i40e_pf_host_handle_vf_msg(dev,
6787                                         rte_le_to_cpu_16(info.desc.retval),
6788                                         rte_le_to_cpu_32(info.desc.cookie_high),
6789                                         rte_le_to_cpu_32(info.desc.cookie_low),
6790                                         info.msg_buf,
6791                                         info.msg_len);
6792                         break;
6793                 case i40e_aqc_opc_get_link_status:
6794                         ret = i40e_dev_link_update(dev, 0);
6795                         if (!ret)
6796                                 rte_eth_dev_callback_process(dev,
6797                                         RTE_ETH_EVENT_INTR_LSC, NULL);
6798
6799                         break;
6800                 default:
6801                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6802                                     opcode);
6803                         break;
6804                 }
6805         }
6806         rte_free(info.msg_buf);
6807 }
6808
6809 static void
6810 i40e_handle_mdd_event(struct rte_eth_dev *dev)
6811 {
6812 #define I40E_MDD_CLEAR32 0xFFFFFFFF
6813 #define I40E_MDD_CLEAR16 0xFFFF
6814         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6815         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6816         bool mdd_detected = false;
6817         struct i40e_pf_vf *vf;
6818         uint32_t reg;
6819         int i;
6820
6821         /* find what triggered the MDD event */
6822         reg = I40E_READ_REG(hw, I40E_GL_MDET_TX);
6823         if (reg & I40E_GL_MDET_TX_VALID_MASK) {
6824                 uint8_t pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6825                                 I40E_GL_MDET_TX_PF_NUM_SHIFT;
6826                 uint16_t vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
6827                                 I40E_GL_MDET_TX_VF_NUM_SHIFT;
6828                 uint8_t event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
6829                                 I40E_GL_MDET_TX_EVENT_SHIFT;
6830                 uint16_t queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6831                                 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6832                                         hw->func_caps.base_queue;
6833                 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on TX "
6834                         "queue %d PF number 0x%02x VF number 0x%02x device %s\n",
6835                                 event, queue, pf_num, vf_num, dev->data->name);
6836                 I40E_WRITE_REG(hw, I40E_GL_MDET_TX, I40E_MDD_CLEAR32);
6837                 mdd_detected = true;
6838         }
6839         reg = I40E_READ_REG(hw, I40E_GL_MDET_RX);
6840         if (reg & I40E_GL_MDET_RX_VALID_MASK) {
6841                 uint8_t func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6842                                 I40E_GL_MDET_RX_FUNCTION_SHIFT;
6843                 uint8_t event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
6844                                 I40E_GL_MDET_RX_EVENT_SHIFT;
6845                 uint16_t queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6846                                 I40E_GL_MDET_RX_QUEUE_SHIFT) -
6847                                         hw->func_caps.base_queue;
6848
6849                 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on RX "
6850                                 "queue %d of function 0x%02x device %s\n",
6851                                         event, queue, func, dev->data->name);
6852                 I40E_WRITE_REG(hw, I40E_GL_MDET_RX, I40E_MDD_CLEAR32);
6853                 mdd_detected = true;
6854         }
6855
6856         if (mdd_detected) {
6857                 reg = I40E_READ_REG(hw, I40E_PF_MDET_TX);
6858                 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
6859                         I40E_WRITE_REG(hw, I40E_PF_MDET_TX, I40E_MDD_CLEAR16);
6860                         PMD_DRV_LOG(WARNING, "TX driver issue detected on PF\n");
6861                 }
6862                 reg = I40E_READ_REG(hw, I40E_PF_MDET_RX);
6863                 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
6864                         I40E_WRITE_REG(hw, I40E_PF_MDET_RX,
6865                                         I40E_MDD_CLEAR16);
6866                         PMD_DRV_LOG(WARNING, "RX driver issue detected on PF\n");
6867                 }
6868         }
6869
6870         /* see if one of the VFs needs its hand slapped */
6871         for (i = 0; i < pf->vf_num && mdd_detected; i++) {
6872                 vf = &pf->vfs[i];
6873                 reg = I40E_READ_REG(hw, I40E_VP_MDET_TX(i));
6874                 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
6875                         I40E_WRITE_REG(hw, I40E_VP_MDET_TX(i),
6876                                         I40E_MDD_CLEAR16);
6877                         vf->num_mdd_events++;
6878                         PMD_DRV_LOG(WARNING, "TX driver issue detected on VF %d %-"
6879                                         PRIu64 "times\n",
6880                                         i, vf->num_mdd_events);
6881                 }
6882
6883                 reg = I40E_READ_REG(hw, I40E_VP_MDET_RX(i));
6884                 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
6885                         I40E_WRITE_REG(hw, I40E_VP_MDET_RX(i),
6886                                         I40E_MDD_CLEAR16);
6887                         vf->num_mdd_events++;
6888                         PMD_DRV_LOG(WARNING, "RX driver issue detected on VF %d %-"
6889                                         PRIu64 "times\n",
6890                                         i, vf->num_mdd_events);
6891                 }
6892         }
6893 }
6894
6895 /**
6896  * Interrupt handler triggered by NIC  for handling
6897  * specific interrupt.
6898  *
6899  * @param handle
6900  *  Pointer to interrupt handle.
6901  * @param param
6902  *  The address of parameter (struct rte_eth_dev *) registered before.
6903  *
6904  * @return
6905  *  void
6906  */
6907 static void
6908 i40e_dev_interrupt_handler(void *param)
6909 {
6910         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6911         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6912         uint32_t icr0;
6913
6914         /* Disable interrupt */
6915         i40e_pf_disable_irq0(hw);
6916
6917         /* read out interrupt causes */
6918         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6919
6920         /* No interrupt event indicated */
6921         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6922                 PMD_DRV_LOG(INFO, "No interrupt event");
6923                 goto done;
6924         }
6925         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6926                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6927         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
6928                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6929                 i40e_handle_mdd_event(dev);
6930         }
6931         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6932                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6933         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6934                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6935         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6936                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6937         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6938                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6939         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6940                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6941
6942         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6943                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6944                 i40e_dev_handle_vfr_event(dev);
6945         }
6946         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6947                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6948                 i40e_dev_handle_aq_msg(dev);
6949         }
6950
6951 done:
6952         /* Enable interrupt */
6953         i40e_pf_enable_irq0(hw);
6954 }
6955
6956 static void
6957 i40e_dev_alarm_handler(void *param)
6958 {
6959         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6960         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6961         uint32_t icr0;
6962
6963         /* Disable interrupt */
6964         i40e_pf_disable_irq0(hw);
6965
6966         /* read out interrupt causes */
6967         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6968
6969         /* No interrupt event indicated */
6970         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
6971                 goto done;
6972         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6973                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6974         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
6975                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6976                 i40e_handle_mdd_event(dev);
6977         }
6978         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6979                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6980         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6981                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6982         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6983                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6984         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6985                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6986         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6987                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6988
6989         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6990                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6991                 i40e_dev_handle_vfr_event(dev);
6992         }
6993         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6994                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6995                 i40e_dev_handle_aq_msg(dev);
6996         }
6997
6998 done:
6999         /* Enable interrupt */
7000         i40e_pf_enable_irq0(hw);
7001         rte_eal_alarm_set(I40E_ALARM_INTERVAL,
7002                           i40e_dev_alarm_handler, dev);
7003 }
7004
7005 int
7006 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
7007                          struct i40e_macvlan_filter *filter,
7008                          int total)
7009 {
7010         int ele_num, ele_buff_size;
7011         int num, actual_num, i;
7012         uint16_t flags;
7013         int ret = I40E_SUCCESS;
7014         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7015         struct i40e_aqc_add_macvlan_element_data *req_list;
7016
7017         if (filter == NULL  || total == 0)
7018                 return I40E_ERR_PARAM;
7019         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
7020         ele_buff_size = hw->aq.asq_buf_size;
7021
7022         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
7023         if (req_list == NULL) {
7024                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
7025                 return I40E_ERR_NO_MEMORY;
7026         }
7027
7028         num = 0;
7029         do {
7030                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
7031                 memset(req_list, 0, ele_buff_size);
7032
7033                 for (i = 0; i < actual_num; i++) {
7034                         rte_memcpy(req_list[i].mac_addr,
7035                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
7036                         req_list[i].vlan_tag =
7037                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
7038
7039                         switch (filter[num + i].filter_type) {
7040                         case I40E_MAC_PERFECT_MATCH:
7041                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
7042                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
7043                                 break;
7044                         case I40E_MACVLAN_PERFECT_MATCH:
7045                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
7046                                 break;
7047                         case I40E_MAC_HASH_MATCH:
7048                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
7049                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
7050                                 break;
7051                         case I40E_MACVLAN_HASH_MATCH:
7052                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
7053                                 break;
7054                         default:
7055                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
7056                                 ret = I40E_ERR_PARAM;
7057                                 goto DONE;
7058                         }
7059
7060                         req_list[i].queue_number = 0;
7061
7062                         req_list[i].flags = rte_cpu_to_le_16(flags);
7063                 }
7064
7065                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
7066                                                 actual_num, NULL);
7067                 if (ret != I40E_SUCCESS) {
7068                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
7069                         goto DONE;
7070                 }
7071                 num += actual_num;
7072         } while (num < total);
7073
7074 DONE:
7075         rte_free(req_list);
7076         return ret;
7077 }
7078
7079 int
7080 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
7081                             struct i40e_macvlan_filter *filter,
7082                             int total)
7083 {
7084         int ele_num, ele_buff_size;
7085         int num, actual_num, i;
7086         uint16_t flags;
7087         int ret = I40E_SUCCESS;
7088         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7089         struct i40e_aqc_remove_macvlan_element_data *req_list;
7090         enum i40e_admin_queue_err aq_status;
7091
7092         if (filter == NULL  || total == 0)
7093                 return I40E_ERR_PARAM;
7094
7095         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
7096         ele_buff_size = hw->aq.asq_buf_size;
7097
7098         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
7099         if (req_list == NULL) {
7100                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
7101                 return I40E_ERR_NO_MEMORY;
7102         }
7103
7104         num = 0;
7105         do {
7106                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
7107                 memset(req_list, 0, ele_buff_size);
7108
7109                 for (i = 0; i < actual_num; i++) {
7110                         rte_memcpy(req_list[i].mac_addr,
7111                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
7112                         req_list[i].vlan_tag =
7113                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
7114
7115                         switch (filter[num + i].filter_type) {
7116                         case I40E_MAC_PERFECT_MATCH:
7117                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
7118                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7119                                 break;
7120                         case I40E_MACVLAN_PERFECT_MATCH:
7121                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
7122                                 break;
7123                         case I40E_MAC_HASH_MATCH:
7124                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
7125                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7126                                 break;
7127                         case I40E_MACVLAN_HASH_MATCH:
7128                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
7129                                 break;
7130                         default:
7131                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
7132                                 ret = I40E_ERR_PARAM;
7133                                 goto DONE;
7134                         }
7135                         req_list[i].flags = rte_cpu_to_le_16(flags);
7136                 }
7137
7138                 ret = i40e_aq_remove_macvlan_v2(hw, vsi->seid, req_list,
7139                                                 actual_num, NULL, &aq_status);
7140
7141                 if (ret != I40E_SUCCESS) {
7142                         /* Do not report as an error when firmware returns ENOENT */
7143                         if (aq_status == I40E_AQ_RC_ENOENT) {
7144                                 ret = I40E_SUCCESS;
7145                         } else {
7146                                 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
7147                                 goto DONE;
7148                         }
7149                 }
7150                 num += actual_num;
7151         } while (num < total);
7152
7153 DONE:
7154         rte_free(req_list);
7155         return ret;
7156 }
7157
7158 /* Find out specific MAC filter */
7159 static struct i40e_mac_filter *
7160 i40e_find_mac_filter(struct i40e_vsi *vsi,
7161                          struct rte_ether_addr *macaddr)
7162 {
7163         struct i40e_mac_filter *f;
7164
7165         TAILQ_FOREACH(f, &vsi->mac_list, next) {
7166                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
7167                         return f;
7168         }
7169
7170         return NULL;
7171 }
7172
7173 static bool
7174 i40e_find_vlan_filter(struct i40e_vsi *vsi,
7175                          uint16_t vlan_id)
7176 {
7177         uint32_t vid_idx, vid_bit;
7178
7179         if (vlan_id > RTE_ETH_VLAN_ID_MAX)
7180                 return 0;
7181
7182         vid_idx = I40E_VFTA_IDX(vlan_id);
7183         vid_bit = I40E_VFTA_BIT(vlan_id);
7184
7185         if (vsi->vfta[vid_idx] & vid_bit)
7186                 return 1;
7187         else
7188                 return 0;
7189 }
7190
7191 static void
7192 i40e_store_vlan_filter(struct i40e_vsi *vsi,
7193                        uint16_t vlan_id, bool on)
7194 {
7195         uint32_t vid_idx, vid_bit;
7196
7197         vid_idx = I40E_VFTA_IDX(vlan_id);
7198         vid_bit = I40E_VFTA_BIT(vlan_id);
7199
7200         if (on)
7201                 vsi->vfta[vid_idx] |= vid_bit;
7202         else
7203                 vsi->vfta[vid_idx] &= ~vid_bit;
7204 }
7205
7206 void
7207 i40e_set_vlan_filter(struct i40e_vsi *vsi,
7208                      uint16_t vlan_id, bool on)
7209 {
7210         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7211         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
7212         int ret;
7213
7214         if (vlan_id > RTE_ETH_VLAN_ID_MAX)
7215                 return;
7216
7217         i40e_store_vlan_filter(vsi, vlan_id, on);
7218
7219         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
7220                 return;
7221
7222         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
7223
7224         if (on) {
7225                 ret = i40e_aq_add_vlan(hw, vsi->seid,
7226                                        &vlan_data, 1, NULL);
7227                 if (ret != I40E_SUCCESS)
7228                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
7229         } else {
7230                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
7231                                           &vlan_data, 1, NULL);
7232                 if (ret != I40E_SUCCESS)
7233                         PMD_DRV_LOG(ERR,
7234                                     "Failed to remove vlan filter");
7235         }
7236 }
7237
7238 /**
7239  * Find all vlan options for specific mac addr,
7240  * return with actual vlan found.
7241  */
7242 int
7243 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
7244                            struct i40e_macvlan_filter *mv_f,
7245                            int num, struct rte_ether_addr *addr)
7246 {
7247         int i;
7248         uint32_t j, k;
7249
7250         /**
7251          * Not to use i40e_find_vlan_filter to decrease the loop time,
7252          * although the code looks complex.
7253           */
7254         if (num < vsi->vlan_num)
7255                 return I40E_ERR_PARAM;
7256
7257         i = 0;
7258         for (j = 0; j < I40E_VFTA_SIZE; j++) {
7259                 if (vsi->vfta[j]) {
7260                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
7261                                 if (vsi->vfta[j] & (1 << k)) {
7262                                         if (i > num - 1) {
7263                                                 PMD_DRV_LOG(ERR,
7264                                                         "vlan number doesn't match");
7265                                                 return I40E_ERR_PARAM;
7266                                         }
7267                                         rte_memcpy(&mv_f[i].macaddr,
7268                                                         addr, ETH_ADDR_LEN);
7269                                         mv_f[i].vlan_id =
7270                                                 j * I40E_UINT32_BIT_SIZE + k;
7271                                         i++;
7272                                 }
7273                         }
7274                 }
7275         }
7276         return I40E_SUCCESS;
7277 }
7278
7279 static inline int
7280 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
7281                            struct i40e_macvlan_filter *mv_f,
7282                            int num,
7283                            uint16_t vlan)
7284 {
7285         int i = 0;
7286         struct i40e_mac_filter *f;
7287
7288         if (num < vsi->mac_num)
7289                 return I40E_ERR_PARAM;
7290
7291         TAILQ_FOREACH(f, &vsi->mac_list, next) {
7292                 if (i > num - 1) {
7293                         PMD_DRV_LOG(ERR, "buffer number not match");
7294                         return I40E_ERR_PARAM;
7295                 }
7296                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7297                                 ETH_ADDR_LEN);
7298                 mv_f[i].vlan_id = vlan;
7299                 mv_f[i].filter_type = f->mac_info.filter_type;
7300                 i++;
7301         }
7302
7303         return I40E_SUCCESS;
7304 }
7305
7306 static int
7307 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
7308 {
7309         int i, j, num;
7310         struct i40e_mac_filter *f;
7311         struct i40e_macvlan_filter *mv_f;
7312         int ret = I40E_SUCCESS;
7313
7314         if (vsi == NULL || vsi->mac_num == 0)
7315                 return I40E_ERR_PARAM;
7316
7317         /* Case that no vlan is set */
7318         if (vsi->vlan_num == 0)
7319                 num = vsi->mac_num;
7320         else
7321                 num = vsi->mac_num * vsi->vlan_num;
7322
7323         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7324         if (mv_f == NULL) {
7325                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7326                 return I40E_ERR_NO_MEMORY;
7327         }
7328
7329         i = 0;
7330         if (vsi->vlan_num == 0) {
7331                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7332                         rte_memcpy(&mv_f[i].macaddr,
7333                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7334                         mv_f[i].filter_type = f->mac_info.filter_type;
7335                         mv_f[i].vlan_id = 0;
7336                         i++;
7337                 }
7338         } else {
7339                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7340                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7341                                         vsi->vlan_num, &f->mac_info.mac_addr);
7342                         if (ret != I40E_SUCCESS)
7343                                 goto DONE;
7344                         for (j = i; j < i + vsi->vlan_num; j++)
7345                                 mv_f[j].filter_type = f->mac_info.filter_type;
7346                         i += vsi->vlan_num;
7347                 }
7348         }
7349
7350         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7351 DONE:
7352         rte_free(mv_f);
7353
7354         return ret;
7355 }
7356
7357 int
7358 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7359 {
7360         struct i40e_macvlan_filter *mv_f;
7361         int mac_num;
7362         int ret = I40E_SUCCESS;
7363
7364         if (!vsi || vlan > RTE_ETHER_MAX_VLAN_ID)
7365                 return I40E_ERR_PARAM;
7366
7367         /* If it's already set, just return */
7368         if (i40e_find_vlan_filter(vsi,vlan))
7369                 return I40E_SUCCESS;
7370
7371         mac_num = vsi->mac_num;
7372
7373         if (mac_num == 0) {
7374                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7375                 return I40E_ERR_PARAM;
7376         }
7377
7378         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7379
7380         if (mv_f == NULL) {
7381                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7382                 return I40E_ERR_NO_MEMORY;
7383         }
7384
7385         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7386
7387         if (ret != I40E_SUCCESS)
7388                 goto DONE;
7389
7390         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7391
7392         if (ret != I40E_SUCCESS)
7393                 goto DONE;
7394
7395         i40e_set_vlan_filter(vsi, vlan, 1);
7396
7397         vsi->vlan_num++;
7398         ret = I40E_SUCCESS;
7399 DONE:
7400         rte_free(mv_f);
7401         return ret;
7402 }
7403
7404 int
7405 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7406 {
7407         struct i40e_macvlan_filter *mv_f;
7408         int mac_num;
7409         int ret = I40E_SUCCESS;
7410
7411         /**
7412          * Vlan 0 is the generic filter for untagged packets
7413          * and can't be removed.
7414          */
7415         if (!vsi || vlan == 0 || vlan > RTE_ETHER_MAX_VLAN_ID)
7416                 return I40E_ERR_PARAM;
7417
7418         /* If can't find it, just return */
7419         if (!i40e_find_vlan_filter(vsi, vlan))
7420                 return I40E_ERR_PARAM;
7421
7422         mac_num = vsi->mac_num;
7423
7424         if (mac_num == 0) {
7425                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7426                 return I40E_ERR_PARAM;
7427         }
7428
7429         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7430
7431         if (mv_f == NULL) {
7432                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7433                 return I40E_ERR_NO_MEMORY;
7434         }
7435
7436         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7437
7438         if (ret != I40E_SUCCESS)
7439                 goto DONE;
7440
7441         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7442
7443         if (ret != I40E_SUCCESS)
7444                 goto DONE;
7445
7446         /* This is last vlan to remove, replace all mac filter with vlan 0 */
7447         if (vsi->vlan_num == 1) {
7448                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7449                 if (ret != I40E_SUCCESS)
7450                         goto DONE;
7451
7452                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7453                 if (ret != I40E_SUCCESS)
7454                         goto DONE;
7455         }
7456
7457         i40e_set_vlan_filter(vsi, vlan, 0);
7458
7459         vsi->vlan_num--;
7460         ret = I40E_SUCCESS;
7461 DONE:
7462         rte_free(mv_f);
7463         return ret;
7464 }
7465
7466 int
7467 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7468 {
7469         struct i40e_mac_filter *f;
7470         struct i40e_macvlan_filter *mv_f;
7471         int i, vlan_num = 0;
7472         int ret = I40E_SUCCESS;
7473
7474         /* If it's add and we've config it, return */
7475         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7476         if (f != NULL)
7477                 return I40E_SUCCESS;
7478         if (mac_filter->filter_type == I40E_MACVLAN_PERFECT_MATCH ||
7479                 mac_filter->filter_type == I40E_MACVLAN_HASH_MATCH) {
7480
7481                 /**
7482                  * If vlan_num is 0, that's the first time to add mac,
7483                  * set mask for vlan_id 0.
7484                  */
7485                 if (vsi->vlan_num == 0) {
7486                         i40e_set_vlan_filter(vsi, 0, 1);
7487                         vsi->vlan_num = 1;
7488                 }
7489                 vlan_num = vsi->vlan_num;
7490         } else if (mac_filter->filter_type == I40E_MAC_PERFECT_MATCH ||
7491                         mac_filter->filter_type == I40E_MAC_HASH_MATCH)
7492                 vlan_num = 1;
7493
7494         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7495         if (mv_f == NULL) {
7496                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7497                 return I40E_ERR_NO_MEMORY;
7498         }
7499
7500         for (i = 0; i < vlan_num; i++) {
7501                 mv_f[i].filter_type = mac_filter->filter_type;
7502                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7503                                 ETH_ADDR_LEN);
7504         }
7505
7506         if (mac_filter->filter_type == I40E_MACVLAN_PERFECT_MATCH ||
7507                 mac_filter->filter_type == I40E_MACVLAN_HASH_MATCH) {
7508                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7509                                         &mac_filter->mac_addr);
7510                 if (ret != I40E_SUCCESS)
7511                         goto DONE;
7512         }
7513
7514         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7515         if (ret != I40E_SUCCESS)
7516                 goto DONE;
7517
7518         /* Add the mac addr into mac list */
7519         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7520         if (f == NULL) {
7521                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7522                 ret = I40E_ERR_NO_MEMORY;
7523                 goto DONE;
7524         }
7525         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7526                         ETH_ADDR_LEN);
7527         f->mac_info.filter_type = mac_filter->filter_type;
7528         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7529         vsi->mac_num++;
7530
7531         ret = I40E_SUCCESS;
7532 DONE:
7533         rte_free(mv_f);
7534
7535         return ret;
7536 }
7537
7538 int
7539 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr)
7540 {
7541         struct i40e_mac_filter *f;
7542         struct i40e_macvlan_filter *mv_f;
7543         int i, vlan_num;
7544         enum i40e_mac_filter_type filter_type;
7545         int ret = I40E_SUCCESS;
7546
7547         /* Can't find it, return an error */
7548         f = i40e_find_mac_filter(vsi, addr);
7549         if (f == NULL)
7550                 return I40E_ERR_PARAM;
7551
7552         vlan_num = vsi->vlan_num;
7553         filter_type = f->mac_info.filter_type;
7554         if (filter_type == I40E_MACVLAN_PERFECT_MATCH ||
7555                 filter_type == I40E_MACVLAN_HASH_MATCH) {
7556                 if (vlan_num == 0) {
7557                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7558                         return I40E_ERR_PARAM;
7559                 }
7560         } else if (filter_type == I40E_MAC_PERFECT_MATCH ||
7561                         filter_type == I40E_MAC_HASH_MATCH)
7562                 vlan_num = 1;
7563
7564         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7565         if (mv_f == NULL) {
7566                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7567                 return I40E_ERR_NO_MEMORY;
7568         }
7569
7570         for (i = 0; i < vlan_num; i++) {
7571                 mv_f[i].filter_type = filter_type;
7572                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7573                                 ETH_ADDR_LEN);
7574         }
7575         if (filter_type == I40E_MACVLAN_PERFECT_MATCH ||
7576                         filter_type == I40E_MACVLAN_HASH_MATCH) {
7577                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7578                 if (ret != I40E_SUCCESS)
7579                         goto DONE;
7580         }
7581
7582         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7583         if (ret != I40E_SUCCESS)
7584                 goto DONE;
7585
7586         /* Remove the mac addr into mac list */
7587         TAILQ_REMOVE(&vsi->mac_list, f, next);
7588         rte_free(f);
7589         vsi->mac_num--;
7590
7591         ret = I40E_SUCCESS;
7592 DONE:
7593         rte_free(mv_f);
7594         return ret;
7595 }
7596
7597 /* Configure hash enable flags for RSS */
7598 uint64_t
7599 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7600 {
7601         uint64_t hena = 0;
7602         int i;
7603
7604         if (!flags)
7605                 return hena;
7606
7607         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7608                 if (flags & (1ULL << i))
7609                         hena |= adapter->pctypes_tbl[i];
7610         }
7611
7612         return hena;
7613 }
7614
7615 /* Parse the hash enable flags */
7616 uint64_t
7617 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7618 {
7619         uint64_t rss_hf = 0;
7620
7621         if (!flags)
7622                 return rss_hf;
7623         int i;
7624
7625         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7626                 if (flags & adapter->pctypes_tbl[i])
7627                         rss_hf |= (1ULL << i);
7628         }
7629         return rss_hf;
7630 }
7631
7632 /* Disable RSS */
7633 void
7634 i40e_pf_disable_rss(struct i40e_pf *pf)
7635 {
7636         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7637
7638         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7639         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7640         I40E_WRITE_FLUSH(hw);
7641 }
7642
7643 int
7644 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7645 {
7646         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7647         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7648         uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7649                            I40E_VFQF_HKEY_MAX_INDEX :
7650                            I40E_PFQF_HKEY_MAX_INDEX;
7651
7652         if (!key || key_len == 0) {
7653                 PMD_DRV_LOG(DEBUG, "No key to be configured");
7654                 return 0;
7655         } else if (key_len != (key_idx + 1) *
7656                 sizeof(uint32_t)) {
7657                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7658                 return -EINVAL;
7659         }
7660
7661         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7662                 struct i40e_aqc_get_set_rss_key_data *key_dw =
7663                                 (struct i40e_aqc_get_set_rss_key_data *)key;
7664                 enum i40e_status_code status =
7665                                 i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7666
7667                 if (status) {
7668                         PMD_DRV_LOG(ERR,
7669                                     "Failed to configure RSS key via AQ, error status: %d",
7670                                     status);
7671                         return -EIO;
7672                 }
7673         } else {
7674                 uint32_t *hash_key = (uint32_t *)key;
7675                 uint16_t i;
7676
7677                 if (vsi->type == I40E_VSI_SRIOV) {
7678                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7679                                 I40E_WRITE_REG(
7680                                         hw,
7681                                         I40E_VFQF_HKEY1(i, vsi->user_param),
7682                                         hash_key[i]);
7683
7684                 } else {
7685                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7686                                 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7687                                                hash_key[i]);
7688                 }
7689                 I40E_WRITE_FLUSH(hw);
7690         }
7691
7692         return 0;
7693 }
7694
7695 static int
7696 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7697 {
7698         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7699         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7700         uint32_t reg;
7701         int ret;
7702
7703         if (!key || !key_len)
7704                 return 0;
7705
7706         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7707                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7708                         (struct i40e_aqc_get_set_rss_key_data *)key);
7709                 if (ret) {
7710                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7711                         return ret;
7712                 }
7713         } else {
7714                 uint32_t *key_dw = (uint32_t *)key;
7715                 uint16_t i;
7716
7717                 if (vsi->type == I40E_VSI_SRIOV) {
7718                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7719                                 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7720                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7721                         }
7722                         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7723                                    sizeof(uint32_t);
7724                 } else {
7725                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7726                                 reg = I40E_PFQF_HKEY(i);
7727                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7728                         }
7729                         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7730                                    sizeof(uint32_t);
7731                 }
7732         }
7733         return 0;
7734 }
7735
7736 static int
7737 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7738 {
7739         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7740         uint64_t hena;
7741         int ret;
7742
7743         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7744                                rss_conf->rss_key_len);
7745         if (ret)
7746                 return ret;
7747
7748         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7749         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7750         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7751         I40E_WRITE_FLUSH(hw);
7752
7753         return 0;
7754 }
7755
7756 static int
7757 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7758                          struct rte_eth_rss_conf *rss_conf)
7759 {
7760         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7761         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7762         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7763         uint64_t hena;
7764
7765         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7766         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7767
7768         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7769                 if (rss_hf != 0) /* Enable RSS */
7770                         return -EINVAL;
7771                 return 0; /* Nothing to do */
7772         }
7773         /* RSS enabled */
7774         if (rss_hf == 0) /* Disable RSS */
7775                 return -EINVAL;
7776
7777         return i40e_hw_rss_hash_set(pf, rss_conf);
7778 }
7779
7780 static int
7781 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7782                            struct rte_eth_rss_conf *rss_conf)
7783 {
7784         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7785         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7786         uint64_t hena;
7787         int ret;
7788
7789         if (!rss_conf)
7790                 return -EINVAL;
7791
7792         ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7793                          &rss_conf->rss_key_len);
7794         if (ret)
7795                 return ret;
7796
7797         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7798         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7799         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7800
7801         return 0;
7802 }
7803
7804 static int
7805 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7806 {
7807         switch (filter_type) {
7808         case RTE_ETH_TUNNEL_FILTER_IMAC_IVLAN:
7809                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7810                 break;
7811         case RTE_ETH_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7812                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7813                 break;
7814         case RTE_ETH_TUNNEL_FILTER_IMAC_TENID:
7815                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7816                 break;
7817         case RTE_ETH_TUNNEL_FILTER_OMAC_TENID_IMAC:
7818                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7819                 break;
7820         case RTE_ETH_TUNNEL_FILTER_IMAC:
7821                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7822                 break;
7823         case RTE_ETH_TUNNEL_FILTER_OIP:
7824                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7825                 break;
7826         case RTE_ETH_TUNNEL_FILTER_IIP:
7827                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7828                 break;
7829         default:
7830                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7831                 return -EINVAL;
7832         }
7833
7834         return 0;
7835 }
7836
7837 /* Convert tunnel filter structure */
7838 static int
7839 i40e_tunnel_filter_convert(
7840         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7841         struct i40e_tunnel_filter *tunnel_filter)
7842 {
7843         rte_ether_addr_copy((struct rte_ether_addr *)
7844                         &cld_filter->element.outer_mac,
7845                 (struct rte_ether_addr *)&tunnel_filter->input.outer_mac);
7846         rte_ether_addr_copy((struct rte_ether_addr *)
7847                         &cld_filter->element.inner_mac,
7848                 (struct rte_ether_addr *)&tunnel_filter->input.inner_mac);
7849         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7850         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7851              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7852             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7853                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7854         else
7855                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7856         tunnel_filter->input.flags = cld_filter->element.flags;
7857         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7858         tunnel_filter->queue = cld_filter->element.queue_number;
7859         rte_memcpy(tunnel_filter->input.general_fields,
7860                    cld_filter->general_fields,
7861                    sizeof(cld_filter->general_fields));
7862
7863         return 0;
7864 }
7865
7866 /* Check if there exists the tunnel filter */
7867 struct i40e_tunnel_filter *
7868 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7869                              const struct i40e_tunnel_filter_input *input)
7870 {
7871         int ret;
7872
7873         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7874         if (ret < 0)
7875                 return NULL;
7876
7877         return tunnel_rule->hash_map[ret];
7878 }
7879
7880 /* Add a tunnel filter into the SW list */
7881 static int
7882 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7883                              struct i40e_tunnel_filter *tunnel_filter)
7884 {
7885         struct i40e_tunnel_rule *rule = &pf->tunnel;
7886         int ret;
7887
7888         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7889         if (ret < 0) {
7890                 PMD_DRV_LOG(ERR,
7891                             "Failed to insert tunnel filter to hash table %d!",
7892                             ret);
7893                 return ret;
7894         }
7895         rule->hash_map[ret] = tunnel_filter;
7896
7897         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7898
7899         return 0;
7900 }
7901
7902 /* Delete a tunnel filter from the SW list */
7903 int
7904 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7905                           struct i40e_tunnel_filter_input *input)
7906 {
7907         struct i40e_tunnel_rule *rule = &pf->tunnel;
7908         struct i40e_tunnel_filter *tunnel_filter;
7909         int ret;
7910
7911         ret = rte_hash_del_key(rule->hash_table, input);
7912         if (ret < 0) {
7913                 PMD_DRV_LOG(ERR,
7914                             "Failed to delete tunnel filter to hash table %d!",
7915                             ret);
7916                 return ret;
7917         }
7918         tunnel_filter = rule->hash_map[ret];
7919         rule->hash_map[ret] = NULL;
7920
7921         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7922         rte_free(tunnel_filter);
7923
7924         return 0;
7925 }
7926
7927 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7928 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7929 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7930 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7931 #define I40E_TR_GRE_KEY_MASK                    0x400
7932 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7933 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7934 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_PORT_TR_WORD0 0x49
7935 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_DIRECTION_WORD0 0x41
7936 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_INGRESS_WORD0 0x80
7937 #define I40E_DIRECTION_INGRESS_KEY              0x8000
7938 #define I40E_TR_L4_TYPE_TCP                     0x2
7939 #define I40E_TR_L4_TYPE_UDP                     0x4
7940 #define I40E_TR_L4_TYPE_SCTP                    0x8
7941
7942 static enum
7943 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7944 {
7945         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7946         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7947         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7948         struct rte_eth_dev *dev = &rte_eth_devices[pf->dev_data->port_id];
7949         enum i40e_status_code status = I40E_SUCCESS;
7950
7951         if (pf->support_multi_driver) {
7952                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7953                 return I40E_NOT_SUPPORTED;
7954         }
7955
7956         memset(&filter_replace, 0,
7957                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7958         memset(&filter_replace_buf, 0,
7959                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7960
7961         /* create L1 filter */
7962         filter_replace.old_filter_type =
7963                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7964         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7965         filter_replace.tr_bit = 0;
7966
7967         /* Prepare the buffer, 3 entries */
7968         filter_replace_buf.data[0] =
7969                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7970         filter_replace_buf.data[0] |=
7971                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7972         filter_replace_buf.data[2] = 0xFF;
7973         filter_replace_buf.data[3] = 0xFF;
7974         filter_replace_buf.data[4] =
7975                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7976         filter_replace_buf.data[4] |=
7977                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7978         filter_replace_buf.data[7] = 0xF0;
7979         filter_replace_buf.data[8]
7980                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7981         filter_replace_buf.data[8] |=
7982                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7983         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7984                 I40E_TR_GENEVE_KEY_MASK |
7985                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7986         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7987                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7988                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7989
7990         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7991                                                &filter_replace_buf);
7992         if (!status && (filter_replace.old_filter_type !=
7993                         filter_replace.new_filter_type))
7994                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7995                             " original: 0x%x, new: 0x%x",
7996                             dev->device->name,
7997                             filter_replace.old_filter_type,
7998                             filter_replace.new_filter_type);
7999
8000         return status;
8001 }
8002
8003 static enum
8004 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
8005 {
8006         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8007         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8008         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8009         struct rte_eth_dev *dev = &rte_eth_devices[pf->dev_data->port_id];
8010         enum i40e_status_code status = I40E_SUCCESS;
8011
8012         if (pf->support_multi_driver) {
8013                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8014                 return I40E_NOT_SUPPORTED;
8015         }
8016
8017         /* For MPLSoUDP */
8018         memset(&filter_replace, 0,
8019                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8020         memset(&filter_replace_buf, 0,
8021                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8022         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
8023                 I40E_AQC_MIRROR_CLOUD_FILTER;
8024         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
8025         filter_replace.new_filter_type =
8026                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8027         /* Prepare the buffer, 2 entries */
8028         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8029         filter_replace_buf.data[0] |=
8030                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8031         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8032         filter_replace_buf.data[4] |=
8033                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8034         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8035                                                &filter_replace_buf);
8036         if (status < 0)
8037                 return status;
8038         if (filter_replace.old_filter_type !=
8039             filter_replace.new_filter_type)
8040                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8041                             " original: 0x%x, new: 0x%x",
8042                             dev->device->name,
8043                             filter_replace.old_filter_type,
8044                             filter_replace.new_filter_type);
8045
8046         /* For MPLSoGRE */
8047         memset(&filter_replace, 0,
8048                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8049         memset(&filter_replace_buf, 0,
8050                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8051
8052         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
8053                 I40E_AQC_MIRROR_CLOUD_FILTER;
8054         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
8055         filter_replace.new_filter_type =
8056                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8057         /* Prepare the buffer, 2 entries */
8058         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8059         filter_replace_buf.data[0] |=
8060                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8061         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8062         filter_replace_buf.data[4] |=
8063                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8064
8065         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8066                                                &filter_replace_buf);
8067         if (!status && (filter_replace.old_filter_type !=
8068                         filter_replace.new_filter_type))
8069                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8070                             " original: 0x%x, new: 0x%x",
8071                             dev->device->name,
8072                             filter_replace.old_filter_type,
8073                             filter_replace.new_filter_type);
8074
8075         return status;
8076 }
8077
8078 static enum i40e_status_code
8079 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
8080 {
8081         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8082         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8083         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8084         struct rte_eth_dev *dev = &rte_eth_devices[pf->dev_data->port_id];
8085         enum i40e_status_code status = I40E_SUCCESS;
8086
8087         if (pf->support_multi_driver) {
8088                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8089                 return I40E_NOT_SUPPORTED;
8090         }
8091
8092         /* For GTP-C */
8093         memset(&filter_replace, 0,
8094                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8095         memset(&filter_replace_buf, 0,
8096                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8097         /* create L1 filter */
8098         filter_replace.old_filter_type =
8099                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
8100         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
8101         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
8102                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8103         /* Prepare the buffer, 2 entries */
8104         filter_replace_buf.data[0] =
8105                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8106         filter_replace_buf.data[0] |=
8107                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8108         filter_replace_buf.data[2] = 0xFF;
8109         filter_replace_buf.data[3] = 0xFF;
8110         filter_replace_buf.data[4] =
8111                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8112         filter_replace_buf.data[4] |=
8113                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8114         filter_replace_buf.data[6] = 0xFF;
8115         filter_replace_buf.data[7] = 0xFF;
8116         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8117                                                &filter_replace_buf);
8118         if (status < 0)
8119                 return status;
8120         if (filter_replace.old_filter_type !=
8121             filter_replace.new_filter_type)
8122                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8123                             " original: 0x%x, new: 0x%x",
8124                             dev->device->name,
8125                             filter_replace.old_filter_type,
8126                             filter_replace.new_filter_type);
8127
8128         /* for GTP-U */
8129         memset(&filter_replace, 0,
8130                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8131         memset(&filter_replace_buf, 0,
8132                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8133         /* create L1 filter */
8134         filter_replace.old_filter_type =
8135                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8136         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
8137         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
8138                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8139         /* Prepare the buffer, 2 entries */
8140         filter_replace_buf.data[0] =
8141                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8142         filter_replace_buf.data[0] |=
8143                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8144         filter_replace_buf.data[2] = 0xFF;
8145         filter_replace_buf.data[3] = 0xFF;
8146         filter_replace_buf.data[4] =
8147                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8148         filter_replace_buf.data[4] |=
8149                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8150         filter_replace_buf.data[6] = 0xFF;
8151         filter_replace_buf.data[7] = 0xFF;
8152
8153         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8154                                                &filter_replace_buf);
8155         if (!status && (filter_replace.old_filter_type !=
8156                         filter_replace.new_filter_type))
8157                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8158                             " original: 0x%x, new: 0x%x",
8159                             dev->device->name,
8160                             filter_replace.old_filter_type,
8161                             filter_replace.new_filter_type);
8162
8163         return status;
8164 }
8165
8166 static enum
8167 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
8168 {
8169         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8170         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8171         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8172         struct rte_eth_dev *dev = &rte_eth_devices[pf->dev_data->port_id];
8173         enum i40e_status_code status = I40E_SUCCESS;
8174
8175         if (pf->support_multi_driver) {
8176                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8177                 return I40E_NOT_SUPPORTED;
8178         }
8179
8180         /* for GTP-C */
8181         memset(&filter_replace, 0,
8182                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8183         memset(&filter_replace_buf, 0,
8184                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8185         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8186         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
8187         filter_replace.new_filter_type =
8188                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8189         /* Prepare the buffer, 2 entries */
8190         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
8191         filter_replace_buf.data[0] |=
8192                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8193         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8194         filter_replace_buf.data[4] |=
8195                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8196         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8197                                                &filter_replace_buf);
8198         if (status < 0)
8199                 return status;
8200         if (filter_replace.old_filter_type !=
8201             filter_replace.new_filter_type)
8202                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8203                             " original: 0x%x, new: 0x%x",
8204                             dev->device->name,
8205                             filter_replace.old_filter_type,
8206                             filter_replace.new_filter_type);
8207
8208         /* for GTP-U */
8209         memset(&filter_replace, 0,
8210                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8211         memset(&filter_replace_buf, 0,
8212                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8213         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8214         filter_replace.old_filter_type =
8215                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8216         filter_replace.new_filter_type =
8217                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8218         /* Prepare the buffer, 2 entries */
8219         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8220         filter_replace_buf.data[0] |=
8221                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8222         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8223         filter_replace_buf.data[4] |=
8224                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8225
8226         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8227                                                &filter_replace_buf);
8228         if (!status && (filter_replace.old_filter_type !=
8229                         filter_replace.new_filter_type))
8230                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8231                             " original: 0x%x, new: 0x%x",
8232                             dev->device->name,
8233                             filter_replace.old_filter_type,
8234                             filter_replace.new_filter_type);
8235
8236         return status;
8237 }
8238
8239 static enum i40e_status_code
8240 i40e_replace_port_l1_filter(struct i40e_pf *pf,
8241                             enum i40e_l4_port_type l4_port_type)
8242 {
8243         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8244         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8245         enum i40e_status_code status = I40E_SUCCESS;
8246         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8247         struct rte_eth_dev *dev = &rte_eth_devices[pf->dev_data->port_id];
8248
8249         if (pf->support_multi_driver) {
8250                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8251                 return I40E_NOT_SUPPORTED;
8252         }
8253
8254         memset(&filter_replace, 0,
8255                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8256         memset(&filter_replace_buf, 0,
8257                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8258
8259         /* create L1 filter */
8260         if (l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8261                 filter_replace.old_filter_type =
8262                         I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8263                 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
8264                 filter_replace_buf.data[8] =
8265                         I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_SRC_PORT;
8266         } else {
8267                 filter_replace.old_filter_type =
8268                         I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
8269                 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X10;
8270                 filter_replace_buf.data[8] =
8271                         I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_DST_PORT;
8272         }
8273
8274         filter_replace.tr_bit = 0;
8275         /* Prepare the buffer, 3 entries */
8276         filter_replace_buf.data[0] =
8277                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_DIRECTION_WORD0;
8278         filter_replace_buf.data[0] |=
8279                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8280         filter_replace_buf.data[2] = 0x00;
8281         filter_replace_buf.data[3] =
8282                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_INGRESS_WORD0;
8283         filter_replace_buf.data[4] =
8284                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_PORT_TR_WORD0;
8285         filter_replace_buf.data[4] |=
8286                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8287         filter_replace_buf.data[5] = 0x00;
8288         filter_replace_buf.data[6] = I40E_TR_L4_TYPE_UDP |
8289                 I40E_TR_L4_TYPE_TCP |
8290                 I40E_TR_L4_TYPE_SCTP;
8291         filter_replace_buf.data[7] = 0x00;
8292         filter_replace_buf.data[8] |=
8293                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8294         filter_replace_buf.data[9] = 0x00;
8295         filter_replace_buf.data[10] = 0xFF;
8296         filter_replace_buf.data[11] = 0xFF;
8297
8298         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8299                                                &filter_replace_buf);
8300         if (!status && filter_replace.old_filter_type !=
8301             filter_replace.new_filter_type)
8302                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8303                             " original: 0x%x, new: 0x%x",
8304                             dev->device->name,
8305                             filter_replace.old_filter_type,
8306                             filter_replace.new_filter_type);
8307
8308         return status;
8309 }
8310
8311 static enum i40e_status_code
8312 i40e_replace_port_cloud_filter(struct i40e_pf *pf,
8313                                enum i40e_l4_port_type l4_port_type)
8314 {
8315         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8316         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8317         enum i40e_status_code status = I40E_SUCCESS;
8318         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8319         struct rte_eth_dev *dev = &rte_eth_devices[pf->dev_data->port_id];
8320
8321         if (pf->support_multi_driver) {
8322                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8323                 return I40E_NOT_SUPPORTED;
8324         }
8325
8326         memset(&filter_replace, 0,
8327                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8328         memset(&filter_replace_buf, 0,
8329                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8330
8331         if (l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8332                 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
8333                 filter_replace.new_filter_type =
8334                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8335                 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X11;
8336         } else {
8337                 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
8338                 filter_replace.new_filter_type =
8339                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
8340                 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
8341         }
8342
8343         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8344         filter_replace.tr_bit = 0;
8345         /* Prepare the buffer, 2 entries */
8346         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8347         filter_replace_buf.data[0] |=
8348                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8349         filter_replace_buf.data[4] |=
8350                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8351         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8352                                                &filter_replace_buf);
8353
8354         if (!status && filter_replace.old_filter_type !=
8355             filter_replace.new_filter_type)
8356                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8357                             " original: 0x%x, new: 0x%x",
8358                             dev->device->name,
8359                             filter_replace.old_filter_type,
8360                             filter_replace.new_filter_type);
8361
8362         return status;
8363 }
8364
8365 int
8366 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8367                       struct i40e_tunnel_filter_conf *tunnel_filter,
8368                       uint8_t add)
8369 {
8370         uint16_t ip_type;
8371         uint32_t ipv4_addr, ipv4_addr_le;
8372         uint8_t i, tun_type = 0;
8373         /* internal variable to convert ipv6 byte order */
8374         uint32_t convert_ipv6[4];
8375         int val, ret = 0;
8376         struct i40e_pf_vf *vf = NULL;
8377         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8378         struct i40e_vsi *vsi;
8379         struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8380         struct i40e_aqc_cloud_filters_element_bb *pfilter;
8381         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8382         struct i40e_tunnel_filter *tunnel, *node;
8383         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8384         uint32_t teid_le;
8385         bool big_buffer = 0;
8386
8387         cld_filter = rte_zmalloc("tunnel_filter",
8388                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8389                          0);
8390
8391         if (cld_filter == NULL) {
8392                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8393                 return -ENOMEM;
8394         }
8395         pfilter = cld_filter;
8396
8397         rte_ether_addr_copy(&tunnel_filter->outer_mac,
8398                         (struct rte_ether_addr *)&pfilter->element.outer_mac);
8399         rte_ether_addr_copy(&tunnel_filter->inner_mac,
8400                         (struct rte_ether_addr *)&pfilter->element.inner_mac);
8401
8402         pfilter->element.inner_vlan =
8403                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8404         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8405                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8406                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8407                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8408                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8409                                 &ipv4_addr_le,
8410                                 sizeof(pfilter->element.ipaddr.v4.data));
8411         } else {
8412                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8413                 for (i = 0; i < 4; i++) {
8414                         convert_ipv6[i] =
8415                         rte_cpu_to_le_32(rte_be_to_cpu_32(
8416                                          tunnel_filter->ip_addr.ipv6_addr[i]));
8417                 }
8418                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8419                            &convert_ipv6,
8420                            sizeof(pfilter->element.ipaddr.v6.data));
8421         }
8422
8423         /* check tunneled type */
8424         switch (tunnel_filter->tunnel_type) {
8425         case I40E_TUNNEL_TYPE_VXLAN:
8426                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8427                 break;
8428         case I40E_TUNNEL_TYPE_NVGRE:
8429                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8430                 break;
8431         case I40E_TUNNEL_TYPE_IP_IN_GRE:
8432                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8433                 break;
8434         case I40E_TUNNEL_TYPE_MPLSoUDP:
8435                 if (!pf->mpls_replace_flag) {
8436                         i40e_replace_mpls_l1_filter(pf);
8437                         i40e_replace_mpls_cloud_filter(pf);
8438                         pf->mpls_replace_flag = 1;
8439                 }
8440                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8441                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8442                         teid_le >> 4;
8443                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8444                         (teid_le & 0xF) << 12;
8445                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8446                         0x40;
8447                 big_buffer = 1;
8448                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8449                 break;
8450         case I40E_TUNNEL_TYPE_MPLSoGRE:
8451                 if (!pf->mpls_replace_flag) {
8452                         i40e_replace_mpls_l1_filter(pf);
8453                         i40e_replace_mpls_cloud_filter(pf);
8454                         pf->mpls_replace_flag = 1;
8455                 }
8456                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8457                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8458                         teid_le >> 4;
8459                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8460                         (teid_le & 0xF) << 12;
8461                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8462                         0x0;
8463                 big_buffer = 1;
8464                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8465                 break;
8466         case I40E_TUNNEL_TYPE_GTPC:
8467                 if (!pf->gtp_replace_flag) {
8468                         i40e_replace_gtp_l1_filter(pf);
8469                         i40e_replace_gtp_cloud_filter(pf);
8470                         pf->gtp_replace_flag = 1;
8471                 }
8472                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8473                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8474                         (teid_le >> 16) & 0xFFFF;
8475                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8476                         teid_le & 0xFFFF;
8477                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8478                         0x0;
8479                 big_buffer = 1;
8480                 break;
8481         case I40E_TUNNEL_TYPE_GTPU:
8482                 if (!pf->gtp_replace_flag) {
8483                         i40e_replace_gtp_l1_filter(pf);
8484                         i40e_replace_gtp_cloud_filter(pf);
8485                         pf->gtp_replace_flag = 1;
8486                 }
8487                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8488                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8489                         (teid_le >> 16) & 0xFFFF;
8490                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8491                         teid_le & 0xFFFF;
8492                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8493                         0x0;
8494                 big_buffer = 1;
8495                 break;
8496         case I40E_TUNNEL_TYPE_QINQ:
8497                 if (!pf->qinq_replace_flag) {
8498                         ret = i40e_cloud_filter_qinq_create(pf);
8499                         if (ret < 0)
8500                                 PMD_DRV_LOG(DEBUG,
8501                                             "QinQ tunnel filter already created.");
8502                         pf->qinq_replace_flag = 1;
8503                 }
8504                 /*      Add in the General fields the values of
8505                  *      the Outer and Inner VLAN
8506                  *      Big Buffer should be set, see changes in
8507                  *      i40e_aq_add_cloud_filters
8508                  */
8509                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8510                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8511                 big_buffer = 1;
8512                 break;
8513         case I40E_CLOUD_TYPE_UDP:
8514         case I40E_CLOUD_TYPE_TCP:
8515         case I40E_CLOUD_TYPE_SCTP:
8516                 if (tunnel_filter->l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8517                         if (!pf->sport_replace_flag) {
8518                                 i40e_replace_port_l1_filter(pf,
8519                                                 tunnel_filter->l4_port_type);
8520                                 i40e_replace_port_cloud_filter(pf,
8521                                                 tunnel_filter->l4_port_type);
8522                                 pf->sport_replace_flag = 1;
8523                         }
8524                         teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8525                         pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8526                                 I40E_DIRECTION_INGRESS_KEY;
8527
8528                         if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP)
8529                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8530                                         I40E_TR_L4_TYPE_UDP;
8531                         else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP)
8532                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8533                                         I40E_TR_L4_TYPE_TCP;
8534                         else
8535                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8536                                         I40E_TR_L4_TYPE_SCTP;
8537
8538                         pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8539                                 (teid_le >> 16) & 0xFFFF;
8540                         big_buffer = 1;
8541                 } else {
8542                         if (!pf->dport_replace_flag) {
8543                                 i40e_replace_port_l1_filter(pf,
8544                                                 tunnel_filter->l4_port_type);
8545                                 i40e_replace_port_cloud_filter(pf,
8546                                                 tunnel_filter->l4_port_type);
8547                                 pf->dport_replace_flag = 1;
8548                         }
8549                         teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8550                         pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0] =
8551                                 I40E_DIRECTION_INGRESS_KEY;
8552
8553                         if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP)
8554                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8555                                         I40E_TR_L4_TYPE_UDP;
8556                         else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP)
8557                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8558                                         I40E_TR_L4_TYPE_TCP;
8559                         else
8560                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8561                                         I40E_TR_L4_TYPE_SCTP;
8562
8563                         pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2] =
8564                                 (teid_le >> 16) & 0xFFFF;
8565                         big_buffer = 1;
8566                 }
8567
8568                 break;
8569         default:
8570                 /* Other tunnel types is not supported. */
8571                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8572                 rte_free(cld_filter);
8573                 return -EINVAL;
8574         }
8575
8576         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8577                 pfilter->element.flags =
8578                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8579         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8580                 pfilter->element.flags =
8581                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8582         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8583                 pfilter->element.flags =
8584                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8585         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8586                 pfilter->element.flags =
8587                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8588         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8589                 pfilter->element.flags |=
8590                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
8591         else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP ||
8592                  tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP ||
8593                  tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_SCTP) {
8594                 if (tunnel_filter->l4_port_type == I40E_L4_PORT_TYPE_SRC)
8595                         pfilter->element.flags |=
8596                                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8597                 else
8598                         pfilter->element.flags |=
8599                                 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8600         } else {
8601                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8602                                                 &pfilter->element.flags);
8603                 if (val < 0) {
8604                         rte_free(cld_filter);
8605                         return -EINVAL;
8606                 }
8607         }
8608
8609         pfilter->element.flags |= rte_cpu_to_le_16(
8610                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8611                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8612         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8613         pfilter->element.queue_number =
8614                 rte_cpu_to_le_16(tunnel_filter->queue_id);
8615
8616         if (!tunnel_filter->is_to_vf)
8617                 vsi = pf->main_vsi;
8618         else {
8619                 if (tunnel_filter->vf_id >= pf->vf_num) {
8620                         PMD_DRV_LOG(ERR, "Invalid argument.");
8621                         rte_free(cld_filter);
8622                         return -EINVAL;
8623                 }
8624                 vf = &pf->vfs[tunnel_filter->vf_id];
8625                 vsi = vf->vsi;
8626         }
8627
8628         /* Check if there is the filter in SW list */
8629         memset(&check_filter, 0, sizeof(check_filter));
8630         i40e_tunnel_filter_convert(cld_filter, &check_filter);
8631         check_filter.is_to_vf = tunnel_filter->is_to_vf;
8632         check_filter.vf_id = tunnel_filter->vf_id;
8633         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8634         if (add && node) {
8635                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8636                 rte_free(cld_filter);
8637                 return -EINVAL;
8638         }
8639
8640         if (!add && !node) {
8641                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8642                 rte_free(cld_filter);
8643                 return -EINVAL;
8644         }
8645
8646         if (add) {
8647                 if (big_buffer)
8648                         ret = i40e_aq_add_cloud_filters_bb(hw,
8649                                                    vsi->seid, cld_filter, 1);
8650                 else
8651                         ret = i40e_aq_add_cloud_filters(hw,
8652                                         vsi->seid, &cld_filter->element, 1);
8653                 if (ret < 0) {
8654                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8655                         rte_free(cld_filter);
8656                         return -ENOTSUP;
8657                 }
8658                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8659                 if (tunnel == NULL) {
8660                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8661                         rte_free(cld_filter);
8662                         return -ENOMEM;
8663                 }
8664
8665                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8666                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8667                 if (ret < 0)
8668                         rte_free(tunnel);
8669         } else {
8670                 if (big_buffer)
8671                         ret = i40e_aq_rem_cloud_filters_bb(
8672                                 hw, vsi->seid, cld_filter, 1);
8673                 else
8674                         ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8675                                                 &cld_filter->element, 1);
8676                 if (ret < 0) {
8677                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8678                         rte_free(cld_filter);
8679                         return -ENOTSUP;
8680                 }
8681                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8682         }
8683
8684         rte_free(cld_filter);
8685         return ret;
8686 }
8687
8688 static int
8689 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8690 {
8691         uint8_t i;
8692
8693         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8694                 if (pf->vxlan_ports[i] == port)
8695                         return i;
8696         }
8697
8698         return -1;
8699 }
8700
8701 static int
8702 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port, int udp_type)
8703 {
8704         int  idx, ret;
8705         uint8_t filter_idx = 0;
8706         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8707
8708         idx = i40e_get_vxlan_port_idx(pf, port);
8709
8710         /* Check if port already exists */
8711         if (idx >= 0) {
8712                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8713                 return -EINVAL;
8714         }
8715
8716         /* Now check if there is space to add the new port */
8717         idx = i40e_get_vxlan_port_idx(pf, 0);
8718         if (idx < 0) {
8719                 PMD_DRV_LOG(ERR,
8720                         "Maximum number of UDP ports reached, not adding port %d",
8721                         port);
8722                 return -ENOSPC;
8723         }
8724
8725         ret =  i40e_aq_add_udp_tunnel(hw, port, udp_type,
8726                                         &filter_idx, NULL);
8727         if (ret < 0) {
8728                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8729                 return -1;
8730         }
8731
8732         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8733                          port,  filter_idx);
8734
8735         /* New port: add it and mark its index in the bitmap */
8736         pf->vxlan_ports[idx] = port;
8737         pf->vxlan_bitmap |= (1 << idx);
8738
8739         if (!(pf->flags & I40E_FLAG_VXLAN))
8740                 pf->flags |= I40E_FLAG_VXLAN;
8741
8742         return 0;
8743 }
8744
8745 static int
8746 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8747 {
8748         int idx;
8749         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8750
8751         if (!(pf->flags & I40E_FLAG_VXLAN)) {
8752                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8753                 return -EINVAL;
8754         }
8755
8756         idx = i40e_get_vxlan_port_idx(pf, port);
8757
8758         if (idx < 0) {
8759                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8760                 return -EINVAL;
8761         }
8762
8763         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8764                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8765                 return -1;
8766         }
8767
8768         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8769                         port, idx);
8770
8771         pf->vxlan_ports[idx] = 0;
8772         pf->vxlan_bitmap &= ~(1 << idx);
8773
8774         if (!pf->vxlan_bitmap)
8775                 pf->flags &= ~I40E_FLAG_VXLAN;
8776
8777         return 0;
8778 }
8779
8780 /* Add UDP tunneling port */
8781 static int
8782 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8783                              struct rte_eth_udp_tunnel *udp_tunnel)
8784 {
8785         int ret = 0;
8786         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8787
8788         if (udp_tunnel == NULL)
8789                 return -EINVAL;
8790
8791         switch (udp_tunnel->prot_type) {
8792         case RTE_ETH_TUNNEL_TYPE_VXLAN:
8793                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8794                                           I40E_AQC_TUNNEL_TYPE_VXLAN);
8795                 break;
8796         case RTE_ETH_TUNNEL_TYPE_VXLAN_GPE:
8797                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8798                                           I40E_AQC_TUNNEL_TYPE_VXLAN_GPE);
8799                 break;
8800         case RTE_ETH_TUNNEL_TYPE_GENEVE:
8801         case RTE_ETH_TUNNEL_TYPE_TEREDO:
8802                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8803                 ret = -1;
8804                 break;
8805
8806         default:
8807                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8808                 ret = -1;
8809                 break;
8810         }
8811
8812         return ret;
8813 }
8814
8815 /* Remove UDP tunneling port */
8816 static int
8817 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8818                              struct rte_eth_udp_tunnel *udp_tunnel)
8819 {
8820         int ret = 0;
8821         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8822
8823         if (udp_tunnel == NULL)
8824                 return -EINVAL;
8825
8826         switch (udp_tunnel->prot_type) {
8827         case RTE_ETH_TUNNEL_TYPE_VXLAN:
8828         case RTE_ETH_TUNNEL_TYPE_VXLAN_GPE:
8829                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8830                 break;
8831         case RTE_ETH_TUNNEL_TYPE_GENEVE:
8832         case RTE_ETH_TUNNEL_TYPE_TEREDO:
8833                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8834                 ret = -1;
8835                 break;
8836         default:
8837                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8838                 ret = -1;
8839                 break;
8840         }
8841
8842         return ret;
8843 }
8844
8845 /* Calculate the maximum number of contiguous PF queues that are configured */
8846 int
8847 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8848 {
8849         struct rte_eth_dev_data *data = pf->dev_data;
8850         int i, num;
8851         struct i40e_rx_queue *rxq;
8852
8853         num = 0;
8854         for (i = 0; i < pf->lan_nb_qps; i++) {
8855                 rxq = data->rx_queues[i];
8856                 if (rxq && rxq->q_set)
8857                         num++;
8858                 else
8859                         break;
8860         }
8861
8862         return num;
8863 }
8864
8865 /* Reset the global configure of hash function and input sets */
8866 static void
8867 i40e_pf_global_rss_reset(struct i40e_pf *pf)
8868 {
8869         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8870         uint32_t reg, reg_val;
8871         int i;
8872
8873         /* Reset global RSS function sets */
8874         reg_val = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8875         if (!(reg_val & I40E_GLQF_CTL_HTOEP_MASK)) {
8876                 reg_val |= I40E_GLQF_CTL_HTOEP_MASK;
8877                 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg_val);
8878         }
8879
8880         for (i = 0; i <= I40E_FILTER_PCTYPE_L2_PAYLOAD; i++) {
8881                 uint64_t inset;
8882                 int j, pctype;
8883
8884                 if (hw->mac.type == I40E_MAC_X722)
8885                         pctype = i40e_read_rx_ctl(hw, I40E_GLQF_FD_PCTYPES(i));
8886                 else
8887                         pctype = i;
8888
8889                 /* Reset pctype insets */
8890                 inset = i40e_get_default_input_set(i);
8891                 if (inset) {
8892                         pf->hash_input_set[pctype] = inset;
8893                         inset = i40e_translate_input_set_reg(hw->mac.type,
8894                                                              inset);
8895
8896                         reg = I40E_GLQF_HASH_INSET(0, pctype);
8897                         i40e_check_write_global_reg(hw, reg, (uint32_t)inset);
8898                         reg = I40E_GLQF_HASH_INSET(1, pctype);
8899                         i40e_check_write_global_reg(hw, reg,
8900                                                     (uint32_t)(inset >> 32));
8901
8902                         /* Clear unused mask registers of the pctype */
8903                         for (j = 0; j < I40E_INSET_MASK_NUM_REG; j++) {
8904                                 reg = I40E_GLQF_HASH_MSK(j, pctype);
8905                                 i40e_check_write_global_reg(hw, reg, 0);
8906                         }
8907                 }
8908
8909                 /* Reset pctype symmetric sets */
8910                 reg = I40E_GLQF_HSYM(pctype);
8911                 reg_val = i40e_read_rx_ctl(hw, reg);
8912                 if (reg_val & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8913                         reg_val &= ~I40E_GLQF_HSYM_SYMH_ENA_MASK;
8914                         i40e_write_global_rx_ctl(hw, reg, reg_val);
8915                 }
8916         }
8917         I40E_WRITE_FLUSH(hw);
8918 }
8919
8920 int
8921 i40e_pf_reset_rss_reta(struct i40e_pf *pf)
8922 {
8923         struct i40e_hw *hw = &pf->adapter->hw;
8924         uint8_t lut[RTE_ETH_RSS_RETA_SIZE_512];
8925         uint32_t i;
8926         int num;
8927
8928         /* If both VMDQ and RSS enabled, not all of PF queues are
8929          * configured. It's necessary to calculate the actual PF
8930          * queues that are configured.
8931          */
8932         if (pf->dev_data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_VMDQ_FLAG)
8933                 num = i40e_pf_calc_configured_queues_num(pf);
8934         else
8935                 num = pf->dev_data->nb_rx_queues;
8936
8937         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8938         if (num <= 0)
8939                 return 0;
8940
8941         for (i = 0; i < hw->func_caps.rss_table_size; i++)
8942                 lut[i] = (uint8_t)(i % (uint32_t)num);
8943
8944         return i40e_set_rss_lut(pf->main_vsi, lut, (uint16_t)i);
8945 }
8946
8947 int
8948 i40e_pf_reset_rss_key(struct i40e_pf *pf)
8949 {
8950         const uint8_t key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8951                         sizeof(uint32_t);
8952         uint8_t *rss_key;
8953
8954         /* Reset key */
8955         rss_key = pf->dev_data->dev_conf.rx_adv_conf.rss_conf.rss_key;
8956         if (!rss_key ||
8957             pf->dev_data->dev_conf.rx_adv_conf.rss_conf.rss_key_len < key_len) {
8958                 static uint32_t rss_key_default[] = {0x6b793944,
8959                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8960                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8961                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8962
8963                 rss_key = (uint8_t *)rss_key_default;
8964         }
8965
8966         return i40e_set_rss_key(pf->main_vsi, rss_key, key_len);
8967 }
8968
8969 static int
8970 i40e_pf_rss_reset(struct i40e_pf *pf)
8971 {
8972         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8973
8974         int ret;
8975
8976         pf->hash_filter_enabled = 0;
8977         i40e_pf_disable_rss(pf);
8978         i40e_set_symmetric_hash_enable_per_port(hw, 0);
8979
8980         if (!pf->support_multi_driver)
8981                 i40e_pf_global_rss_reset(pf);
8982
8983         /* Reset RETA table */
8984         if (pf->adapter->rss_reta_updated == 0) {
8985                 ret = i40e_pf_reset_rss_reta(pf);
8986                 if (ret)
8987                         return ret;
8988         }
8989
8990         return i40e_pf_reset_rss_key(pf);
8991 }
8992
8993 /* Configure RSS */
8994 int
8995 i40e_pf_config_rss(struct i40e_pf *pf)
8996 {
8997         struct i40e_hw *hw;
8998         enum rte_eth_rx_mq_mode mq_mode;
8999         uint64_t rss_hf, hena;
9000         int ret;
9001
9002         ret = i40e_pf_rss_reset(pf);
9003         if (ret) {
9004                 PMD_DRV_LOG(ERR, "Reset RSS failed, RSS has been disabled");
9005                 return ret;
9006         }
9007
9008         rss_hf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf.rss_hf;
9009         mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
9010         if (!(rss_hf & pf->adapter->flow_types_mask) ||
9011             !(mq_mode & RTE_ETH_MQ_RX_RSS_FLAG))
9012                 return 0;
9013
9014         hw = I40E_PF_TO_HW(pf);
9015         hena = i40e_config_hena(pf->adapter, rss_hf);
9016         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
9017         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
9018         I40E_WRITE_FLUSH(hw);
9019
9020         return 0;
9021 }
9022
9023 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
9024 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
9025 int
9026 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
9027 {
9028         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9029         uint32_t val, reg;
9030         int ret = -EINVAL;
9031
9032         if (pf->support_multi_driver) {
9033                 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
9034                 return -ENOTSUP;
9035         }
9036
9037         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
9038         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
9039
9040         if (len == 3) {
9041                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
9042         } else if (len == 4) {
9043                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
9044         } else {
9045                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
9046                 return ret;
9047         }
9048
9049         if (reg != val) {
9050                 ret = i40e_aq_debug_write_global_register(hw,
9051                                                    I40E_GL_PRS_FVBM(2),
9052                                                    reg, NULL);
9053                 if (ret != 0)
9054                         return ret;
9055                 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
9056                             "with value 0x%08x",
9057                             I40E_GL_PRS_FVBM(2), reg);
9058         } else {
9059                 ret = 0;
9060         }
9061         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
9062                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
9063
9064         return ret;
9065 }
9066
9067 /* Set the symmetric hash enable configurations per port */
9068 void
9069 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
9070 {
9071         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
9072
9073         if (enable > 0) {
9074                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)
9075                         return;
9076
9077                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
9078         } else {
9079                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK))
9080                         return;
9081
9082                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
9083         }
9084         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
9085         I40E_WRITE_FLUSH(hw);
9086 }
9087
9088 /**
9089  * Valid input sets for hash and flow director filters per PCTYPE
9090  */
9091 static uint64_t
9092 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
9093                 enum rte_filter_type filter)
9094 {
9095         uint64_t valid;
9096
9097         static const uint64_t valid_hash_inset_table[] = {
9098                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9099                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9100                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9101                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
9102                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
9103                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9104                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9105                         I40E_INSET_FLEX_PAYLOAD,
9106                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9107                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9108                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9109                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9110                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9111                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9112                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9113                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9114                         I40E_INSET_FLEX_PAYLOAD,
9115                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9116                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9117                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9118                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9119                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9120                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9121                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9122                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9123                         I40E_INSET_FLEX_PAYLOAD,
9124                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9125                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9126                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9127                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9128                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9129                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9130                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9131                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9132                         I40E_INSET_FLEX_PAYLOAD,
9133                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9134                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9135                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9136                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9137                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9138                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9139                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9140                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9141                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9142                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9143                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9144                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9145                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9146                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9147                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9148                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9149                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9150                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9151                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9152                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9153                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9154                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9155                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9156                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9157                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9158                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9159                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
9160                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9161                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9162                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9163                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9164                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9165                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9166                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9167                         I40E_INSET_FLEX_PAYLOAD,
9168                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9169                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9170                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9171                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9172                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9173                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
9174                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
9175                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
9176                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9177                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9178                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9179                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9180                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9181                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9182                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9183                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
9184                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9185                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9186                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9187                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9188                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9189                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9190                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9191                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9192                         I40E_INSET_FLEX_PAYLOAD,
9193                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9194                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9195                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9196                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9197                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9198                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9199                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9200                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9201                         I40E_INSET_FLEX_PAYLOAD,
9202                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9203                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9204                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9205                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9206                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9207                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9208                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9209                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9210                         I40E_INSET_FLEX_PAYLOAD,
9211                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9212                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9213                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9214                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9215                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9216                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9217                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9218                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9219                         I40E_INSET_FLEX_PAYLOAD,
9220                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9221                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9222                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9223                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9224                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9225                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9226                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9227                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9228                         I40E_INSET_FLEX_PAYLOAD,
9229                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9230                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9231                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9232                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9233                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9234                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9235                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9236                         I40E_INSET_FLEX_PAYLOAD,
9237                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9238                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9239                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9240                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9241                         I40E_INSET_FLEX_PAYLOAD,
9242         };
9243
9244         /**
9245          * Flow director supports only fields defined in
9246          * union rte_eth_fdir_flow.
9247          */
9248         static const uint64_t valid_fdir_inset_table[] = {
9249                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9250                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9251                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9252                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9253                 I40E_INSET_IPV4_TTL,
9254                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9255                 I40E_INSET_DMAC | I40E_INSET_SMAC |
9256                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9257                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9258                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9259                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9260                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9261                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9262                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9263                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9264                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9265                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9266                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9267                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9268                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9269                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9270                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9271                 I40E_INSET_DMAC | I40E_INSET_SMAC |
9272                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9273                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9274                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9275                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9276                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9277                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9278                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9279                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9280                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9281                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9282                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9283                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9284                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9285                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9286                 I40E_INSET_SCTP_VT,
9287                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9288                 I40E_INSET_DMAC | I40E_INSET_SMAC |
9289                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9290                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9291                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9292                 I40E_INSET_IPV4_TTL,
9293                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9294                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9295                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9296                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9297                 I40E_INSET_IPV6_HOP_LIMIT,
9298                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9299                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9300                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9301                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9302                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9303                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9304                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9305                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9306                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9307                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9308                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9309                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9310                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9311                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9312                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9313                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9314                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9315                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9316                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9317                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9318                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9319                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9320                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9321                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9322                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9323                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9324                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9325                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9326                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9327                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9328                 I40E_INSET_SCTP_VT,
9329                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9330                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9331                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9332                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9333                 I40E_INSET_IPV6_HOP_LIMIT,
9334                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9335                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9336                 I40E_INSET_LAST_ETHER_TYPE,
9337         };
9338
9339         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9340                 return 0;
9341         if (filter == RTE_ETH_FILTER_HASH)
9342                 valid = valid_hash_inset_table[pctype];
9343         else
9344                 valid = valid_fdir_inset_table[pctype];
9345
9346         return valid;
9347 }
9348
9349 /**
9350  * Validate if the input set is allowed for a specific PCTYPE
9351  */
9352 int
9353 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9354                 enum rte_filter_type filter, uint64_t inset)
9355 {
9356         uint64_t valid;
9357
9358         valid = i40e_get_valid_input_set(pctype, filter);
9359         if (inset & (~valid))
9360                 return -EINVAL;
9361
9362         return 0;
9363 }
9364
9365 /* default input set fields combination per pctype */
9366 uint64_t
9367 i40e_get_default_input_set(uint16_t pctype)
9368 {
9369         static const uint64_t default_inset_table[] = {
9370                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9371                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9372                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9373                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9374                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9375                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9376                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9377                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9378                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9379                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9380                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9381                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9382                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9383                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9384                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9385                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9386                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9387                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9388                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9389                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9390                         I40E_INSET_SCTP_VT,
9391                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9392                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9393                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9394                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9395                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9396                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9397                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9398                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9399                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9400                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9401                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9402                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9403                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9404                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9405                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9406                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9407                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9408                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9409                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9410                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9411                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9412                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9413                         I40E_INSET_SCTP_VT,
9414                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9415                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9416                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9417                         I40E_INSET_LAST_ETHER_TYPE,
9418         };
9419
9420         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9421                 return 0;
9422
9423         return default_inset_table[pctype];
9424 }
9425
9426 /**
9427  * Translate the input set from bit masks to register aware bit masks
9428  * and vice versa
9429  */
9430 uint64_t
9431 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9432 {
9433         uint64_t val = 0;
9434         uint16_t i;
9435
9436         struct inset_map {
9437                 uint64_t inset;
9438                 uint64_t inset_reg;
9439         };
9440
9441         static const struct inset_map inset_map_common[] = {
9442                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9443                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9444                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9445                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9446                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9447                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9448                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9449                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9450                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9451                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9452                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9453                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9454                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9455                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9456                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9457                 {I40E_INSET_TUNNEL_DMAC,
9458                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9459                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9460                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9461                 {I40E_INSET_TUNNEL_SRC_PORT,
9462                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9463                 {I40E_INSET_TUNNEL_DST_PORT,
9464                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9465                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9466                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9467                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9468                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9469                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9470                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9471                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9472                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9473                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9474         };
9475
9476     /* some different registers map in x722*/
9477         static const struct inset_map inset_map_diff_x722[] = {
9478                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9479                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9480                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9481                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9482         };
9483
9484         static const struct inset_map inset_map_diff_not_x722[] = {
9485                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9486                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9487                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9488                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9489         };
9490
9491         if (input == 0)
9492                 return val;
9493
9494         /* Translate input set to register aware inset */
9495         if (type == I40E_MAC_X722) {
9496                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9497                         if (input & inset_map_diff_x722[i].inset)
9498                                 val |= inset_map_diff_x722[i].inset_reg;
9499                 }
9500         } else {
9501                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9502                         if (input & inset_map_diff_not_x722[i].inset)
9503                                 val |= inset_map_diff_not_x722[i].inset_reg;
9504                 }
9505         }
9506
9507         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9508                 if (input & inset_map_common[i].inset)
9509                         val |= inset_map_common[i].inset_reg;
9510         }
9511
9512         return val;
9513 }
9514
9515 static int
9516 i40e_get_inset_field_offset(struct i40e_hw *hw, uint32_t pit_reg_start,
9517                             uint32_t pit_reg_count, uint32_t hdr_off)
9518 {
9519         const uint32_t pit_reg_end = pit_reg_start + pit_reg_count;
9520         uint32_t field_off = I40E_FDIR_FIELD_OFFSET(hdr_off);
9521         uint32_t i, reg_val, src_off, count;
9522
9523         for (i = pit_reg_start; i < pit_reg_end; i++) {
9524                 reg_val = i40e_read_rx_ctl(hw, I40E_GLQF_PIT(i));
9525
9526                 src_off = I40E_GLQF_PIT_SOURCE_OFF_GET(reg_val);
9527                 count = I40E_GLQF_PIT_FSIZE_GET(reg_val);
9528
9529                 if (src_off <= field_off && (src_off + count) > field_off)
9530                         break;
9531         }
9532
9533         if (i >= pit_reg_end) {
9534                 PMD_DRV_LOG(ERR,
9535                             "Hardware GLQF_PIT configuration does not support this field mask");
9536                 return -1;
9537         }
9538
9539         return I40E_GLQF_PIT_DEST_OFF_GET(reg_val) + field_off - src_off;
9540 }
9541
9542 int
9543 i40e_generate_inset_mask_reg(struct i40e_hw *hw, uint64_t inset,
9544                              uint32_t *mask, uint8_t nb_elem)
9545 {
9546         static const uint64_t mask_inset[] = {
9547                 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL,
9548                 I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT };
9549
9550         static const struct {
9551                 uint64_t inset;
9552                 uint32_t mask;
9553                 uint32_t offset;
9554         } inset_mask_offset_map[] = {
9555                 { I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK,
9556                   offsetof(struct rte_ipv4_hdr, type_of_service) },
9557
9558                 { I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK,
9559                   offsetof(struct rte_ipv4_hdr, next_proto_id) },
9560
9561                 { I40E_INSET_IPV4_TTL, I40E_INSET_IPV4_TTL_MASK,
9562                   offsetof(struct rte_ipv4_hdr, time_to_live) },
9563
9564                 { I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK,
9565                   offsetof(struct rte_ipv6_hdr, vtc_flow) },
9566
9567                 { I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK,
9568                   offsetof(struct rte_ipv6_hdr, proto) },
9569
9570                 { I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK,
9571                   offsetof(struct rte_ipv6_hdr, hop_limits) },
9572         };
9573
9574         uint32_t i;
9575         int idx = 0;
9576
9577         assert(mask);
9578         if (!inset)
9579                 return 0;
9580
9581         for (i = 0; i < RTE_DIM(mask_inset); i++) {
9582                 /* Clear the inset bit, if no MASK is required,
9583                  * for example proto + ttl
9584                  */
9585                 if ((mask_inset[i] & inset) == mask_inset[i]) {
9586                         inset &= ~mask_inset[i];
9587                         if (!inset)
9588                                 return 0;
9589                 }
9590         }
9591
9592         for (i = 0; i < RTE_DIM(inset_mask_offset_map); i++) {
9593                 uint32_t pit_start, pit_count;
9594                 int offset;
9595
9596                 if (!(inset_mask_offset_map[i].inset & inset))
9597                         continue;
9598
9599                 if (inset_mask_offset_map[i].inset &
9600                     (I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9601                      I40E_INSET_IPV4_TTL)) {
9602                         pit_start = I40E_GLQF_PIT_IPV4_START;
9603                         pit_count = I40E_GLQF_PIT_IPV4_COUNT;
9604                 } else {
9605                         pit_start = I40E_GLQF_PIT_IPV6_START;
9606                         pit_count = I40E_GLQF_PIT_IPV6_COUNT;
9607                 }
9608
9609                 offset = i40e_get_inset_field_offset(hw, pit_start, pit_count,
9610                                 inset_mask_offset_map[i].offset);
9611
9612                 if (offset < 0)
9613                         return -EINVAL;
9614
9615                 if (idx >= nb_elem) {
9616                         PMD_DRV_LOG(ERR,
9617                                     "Configuration of inset mask out of range %u",
9618                                     nb_elem);
9619                         return -ERANGE;
9620                 }
9621
9622                 mask[idx] = I40E_GLQF_PIT_BUILD((uint32_t)offset,
9623                                                 inset_mask_offset_map[i].mask);
9624                 idx++;
9625         }
9626
9627         return idx;
9628 }
9629
9630 void
9631 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9632 {
9633         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9634
9635         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9636         if (reg != val)
9637                 i40e_write_rx_ctl(hw, addr, val);
9638         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9639                     (uint32_t)i40e_read_rx_ctl(hw, addr));
9640 }
9641
9642 void
9643 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9644 {
9645         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9646         struct rte_eth_dev_data *dev_data =
9647                 ((struct i40e_adapter *)hw->back)->pf.dev_data;
9648         struct rte_eth_dev *dev = &rte_eth_devices[dev_data->port_id];
9649
9650         if (reg != val) {
9651                 i40e_write_rx_ctl(hw, addr, val);
9652                 PMD_DRV_LOG(WARNING,
9653                             "i40e device %s changed global register [0x%08x]."
9654                             " original: 0x%08x, new: 0x%08x",
9655                             dev->device->name, addr, reg,
9656                             (uint32_t)i40e_read_rx_ctl(hw, addr));
9657         }
9658 }
9659
9660 static void
9661 i40e_filter_input_set_init(struct i40e_pf *pf)
9662 {
9663         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9664         enum i40e_filter_pctype pctype;
9665         uint64_t input_set, inset_reg;
9666         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9667         int num, i;
9668         uint16_t flow_type;
9669
9670         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9671              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9672                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9673
9674                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9675                         continue;
9676
9677                 input_set = i40e_get_default_input_set(pctype);
9678
9679                 num = i40e_generate_inset_mask_reg(hw, input_set, mask_reg,
9680                                                    I40E_INSET_MASK_NUM_REG);
9681                 if (num < 0)
9682                         return;
9683                 if (pf->support_multi_driver && num > 0) {
9684                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9685                         return;
9686                 }
9687                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9688                                         input_set);
9689
9690                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9691                                       (uint32_t)(inset_reg & UINT32_MAX));
9692                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9693                                      (uint32_t)((inset_reg >>
9694                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
9695                 if (!pf->support_multi_driver) {
9696                         i40e_check_write_global_reg(hw,
9697                                             I40E_GLQF_HASH_INSET(0, pctype),
9698                                             (uint32_t)(inset_reg & UINT32_MAX));
9699                         i40e_check_write_global_reg(hw,
9700                                              I40E_GLQF_HASH_INSET(1, pctype),
9701                                              (uint32_t)((inset_reg >>
9702                                               I40E_32_BIT_WIDTH) & UINT32_MAX));
9703
9704                         for (i = 0; i < num; i++) {
9705                                 i40e_check_write_global_reg(hw,
9706                                                     I40E_GLQF_FD_MSK(i, pctype),
9707                                                     mask_reg[i]);
9708                                 i40e_check_write_global_reg(hw,
9709                                                   I40E_GLQF_HASH_MSK(i, pctype),
9710                                                   mask_reg[i]);
9711                         }
9712                         /*clear unused mask registers of the pctype */
9713                         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9714                                 i40e_check_write_global_reg(hw,
9715                                                     I40E_GLQF_FD_MSK(i, pctype),
9716                                                     0);
9717                                 i40e_check_write_global_reg(hw,
9718                                                   I40E_GLQF_HASH_MSK(i, pctype),
9719                                                   0);
9720                         }
9721                 } else {
9722                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9723                 }
9724                 I40E_WRITE_FLUSH(hw);
9725
9726                 /* store the default input set */
9727                 if (!pf->support_multi_driver)
9728                         pf->hash_input_set[pctype] = input_set;
9729                 pf->fdir.input_set[pctype] = input_set;
9730         }
9731 }
9732
9733 int
9734 i40e_set_hash_inset(struct i40e_hw *hw, uint64_t input_set,
9735                     uint32_t pctype, bool add)
9736 {
9737         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9738         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9739         uint64_t inset_reg = 0;
9740         int num, i;
9741
9742         if (pf->support_multi_driver) {
9743                 PMD_DRV_LOG(ERR,
9744                             "Modify input set is not permitted when multi-driver enabled.");
9745                 return -EPERM;
9746         }
9747
9748         /* For X722, get translated pctype in fd pctype register */
9749         if (hw->mac.type == I40E_MAC_X722)
9750                 pctype = i40e_read_rx_ctl(hw, I40E_GLQF_FD_PCTYPES(pctype));
9751
9752         if (add) {
9753                 /* get inset value in register */
9754                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9755                 inset_reg <<= I40E_32_BIT_WIDTH;
9756                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9757                 input_set |= pf->hash_input_set[pctype];
9758         }
9759         num = i40e_generate_inset_mask_reg(hw, input_set, mask_reg,
9760                                            I40E_INSET_MASK_NUM_REG);
9761         if (num < 0)
9762                 return -EINVAL;
9763
9764         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9765
9766         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9767                                     (uint32_t)(inset_reg & UINT32_MAX));
9768         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9769                                     (uint32_t)((inset_reg >>
9770                                     I40E_32_BIT_WIDTH) & UINT32_MAX));
9771
9772         for (i = 0; i < num; i++)
9773                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9774                                             mask_reg[i]);
9775         /*clear unused mask registers of the pctype */
9776         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9777                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9778                                             0);
9779         I40E_WRITE_FLUSH(hw);
9780
9781         pf->hash_input_set[pctype] = input_set;
9782         return 0;
9783 }
9784
9785 /* Convert ethertype filter structure */
9786 static int
9787 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9788                               struct i40e_ethertype_filter *filter)
9789 {
9790         rte_memcpy(&filter->input.mac_addr, &input->mac_addr,
9791                 RTE_ETHER_ADDR_LEN);
9792         filter->input.ether_type = input->ether_type;
9793         filter->flags = input->flags;
9794         filter->queue = input->queue;
9795
9796         return 0;
9797 }
9798
9799 /* Check if there exists the ethertype filter */
9800 struct i40e_ethertype_filter *
9801 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9802                                 const struct i40e_ethertype_filter_input *input)
9803 {
9804         int ret;
9805
9806         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9807         if (ret < 0)
9808                 return NULL;
9809
9810         return ethertype_rule->hash_map[ret];
9811 }
9812
9813 /* Add ethertype filter in SW list */
9814 static int
9815 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9816                                 struct i40e_ethertype_filter *filter)
9817 {
9818         struct i40e_ethertype_rule *rule = &pf->ethertype;
9819         int ret;
9820
9821         ret = rte_hash_add_key(rule->hash_table, &filter->input);
9822         if (ret < 0) {
9823                 PMD_DRV_LOG(ERR,
9824                             "Failed to insert ethertype filter"
9825                             " to hash table %d!",
9826                             ret);
9827                 return ret;
9828         }
9829         rule->hash_map[ret] = filter;
9830
9831         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9832
9833         return 0;
9834 }
9835
9836 /* Delete ethertype filter in SW list */
9837 int
9838 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9839                              struct i40e_ethertype_filter_input *input)
9840 {
9841         struct i40e_ethertype_rule *rule = &pf->ethertype;
9842         struct i40e_ethertype_filter *filter;
9843         int ret;
9844
9845         ret = rte_hash_del_key(rule->hash_table, input);
9846         if (ret < 0) {
9847                 PMD_DRV_LOG(ERR,
9848                             "Failed to delete ethertype filter"
9849                             " to hash table %d!",
9850                             ret);
9851                 return ret;
9852         }
9853         filter = rule->hash_map[ret];
9854         rule->hash_map[ret] = NULL;
9855
9856         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9857         rte_free(filter);
9858
9859         return 0;
9860 }
9861
9862 /*
9863  * Configure ethertype filter, which can director packet by filtering
9864  * with mac address and ether_type or only ether_type
9865  */
9866 int
9867 i40e_ethertype_filter_set(struct i40e_pf *pf,
9868                         struct rte_eth_ethertype_filter *filter,
9869                         bool add)
9870 {
9871         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9872         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9873         struct i40e_ethertype_filter *ethertype_filter, *node;
9874         struct i40e_ethertype_filter check_filter;
9875         struct i40e_control_filter_stats stats;
9876         uint16_t flags = 0;
9877         int ret;
9878
9879         if (filter->queue >= pf->dev_data->nb_rx_queues) {
9880                 PMD_DRV_LOG(ERR, "Invalid queue ID");
9881                 return -EINVAL;
9882         }
9883         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
9884                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
9885                 PMD_DRV_LOG(ERR,
9886                         "unsupported ether_type(0x%04x) in control packet filter.",
9887                         filter->ether_type);
9888                 return -EINVAL;
9889         }
9890         if (filter->ether_type == RTE_ETHER_TYPE_VLAN)
9891                 PMD_DRV_LOG(WARNING,
9892                         "filter vlan ether_type in first tag is not supported.");
9893
9894         /* Check if there is the filter in SW list */
9895         memset(&check_filter, 0, sizeof(check_filter));
9896         i40e_ethertype_filter_convert(filter, &check_filter);
9897         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9898                                                &check_filter.input);
9899         if (add && node) {
9900                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9901                 return -EINVAL;
9902         }
9903
9904         if (!add && !node) {
9905                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9906                 return -EINVAL;
9907         }
9908
9909         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9910                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9911         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9912                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9913         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9914
9915         memset(&stats, 0, sizeof(stats));
9916         ret = i40e_aq_add_rem_control_packet_filter(hw,
9917                         filter->mac_addr.addr_bytes,
9918                         filter->ether_type, flags,
9919                         pf->main_vsi->seid,
9920                         filter->queue, add, &stats, NULL);
9921
9922         PMD_DRV_LOG(INFO,
9923                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9924                 ret, stats.mac_etype_used, stats.etype_used,
9925                 stats.mac_etype_free, stats.etype_free);
9926         if (ret < 0)
9927                 return -ENOSYS;
9928
9929         /* Add or delete a filter in SW list */
9930         if (add) {
9931                 ethertype_filter = rte_zmalloc("ethertype_filter",
9932                                        sizeof(*ethertype_filter), 0);
9933                 if (ethertype_filter == NULL) {
9934                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
9935                         return -ENOMEM;
9936                 }
9937
9938                 rte_memcpy(ethertype_filter, &check_filter,
9939                            sizeof(check_filter));
9940                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9941                 if (ret < 0)
9942                         rte_free(ethertype_filter);
9943         } else {
9944                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9945         }
9946
9947         return ret;
9948 }
9949
9950 static int
9951 i40e_dev_flow_ops_get(struct rte_eth_dev *dev,
9952                       const struct rte_flow_ops **ops)
9953 {
9954         if (dev == NULL)
9955                 return -EINVAL;
9956
9957         *ops = &i40e_flow_ops;
9958         return 0;
9959 }
9960
9961 /*
9962  * Check and enable Extended Tag.
9963  * Enabling Extended Tag is important for 40G performance.
9964  */
9965 static void
9966 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9967 {
9968         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9969         uint32_t buf = 0;
9970         int ret;
9971
9972         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9973                                       PCI_DEV_CAP_REG);
9974         if (ret < 0) {
9975                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9976                             PCI_DEV_CAP_REG);
9977                 return;
9978         }
9979         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9980                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9981                 return;
9982         }
9983
9984         buf = 0;
9985         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9986                                       PCI_DEV_CTRL_REG);
9987         if (ret < 0) {
9988                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9989                             PCI_DEV_CTRL_REG);
9990                 return;
9991         }
9992         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9993                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9994                 return;
9995         }
9996         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9997         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9998                                        PCI_DEV_CTRL_REG);
9999         if (ret < 0) {
10000                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
10001                             PCI_DEV_CTRL_REG);
10002                 return;
10003         }
10004 }
10005
10006 /*
10007  * As some registers wouldn't be reset unless a global hardware reset,
10008  * hardware initialization is needed to put those registers into an
10009  * expected initial state.
10010  */
10011 static void
10012 i40e_hw_init(struct rte_eth_dev *dev)
10013 {
10014         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10015
10016         i40e_enable_extended_tag(dev);
10017
10018         /* clear the PF Queue Filter control register */
10019         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
10020
10021         /* Disable symmetric hash per port */
10022         i40e_set_symmetric_hash_enable_per_port(hw, 0);
10023 }
10024
10025 /*
10026  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
10027  * however this function will return only one highest pctype index,
10028  * which is not quite correct. This is known problem of i40e driver
10029  * and needs to be fixed later.
10030  */
10031 enum i40e_filter_pctype
10032 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
10033 {
10034         int i;
10035         uint64_t pctype_mask;
10036
10037         if (flow_type < I40E_FLOW_TYPE_MAX) {
10038                 pctype_mask = adapter->pctypes_tbl[flow_type];
10039                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
10040                         if (pctype_mask & (1ULL << i))
10041                                 return (enum i40e_filter_pctype)i;
10042                 }
10043         }
10044         return I40E_FILTER_PCTYPE_INVALID;
10045 }
10046
10047 uint16_t
10048 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
10049                         enum i40e_filter_pctype pctype)
10050 {
10051         uint16_t flowtype;
10052         uint64_t pctype_mask = 1ULL << pctype;
10053
10054         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
10055              flowtype++) {
10056                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
10057                         return flowtype;
10058         }
10059
10060         return RTE_ETH_FLOW_UNKNOWN;
10061 }
10062
10063 /*
10064  * On X710, performance number is far from the expectation on recent firmware
10065  * versions; on XL710, performance number is also far from the expectation on
10066  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10067  * mode is enabled and port MAC address is equal to the packet destination MAC
10068  * address. The fix for this issue may not be integrated in the following
10069  * firmware version. So the workaround in software driver is needed. It needs
10070  * to modify the initial values of 3 internal only registers for both X710 and
10071  * XL710. Note that the values for X710 or XL710 could be different, and the
10072  * workaround can be removed when it is fixed in firmware in the future.
10073  */
10074
10075 /* For both X710 and XL710 */
10076 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
10077 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
10078 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
10079
10080 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10081 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
10082
10083 /* For X722 */
10084 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10085 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10086
10087 /* For X710 */
10088 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
10089 /* For XL710 */
10090 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
10091 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
10092
10093 /*
10094  * GL_SWR_PM_UP_THR:
10095  * The value is not impacted from the link speed, its value is set according
10096  * to the total number of ports for a better pipe-monitor configuration.
10097  */
10098 static bool
10099 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10100 {
10101 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10102                 .device_id = (dev),   \
10103                 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10104
10105 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10106                 .device_id = (dev),   \
10107                 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10108
10109         static const struct {
10110                 uint16_t device_id;
10111                 uint32_t val;
10112         } swr_pm_table[] = {
10113                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10114                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10115                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10116                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10117                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_X722) },
10118
10119                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10120                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10121                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10122                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10123                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10124                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10125                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10126         };
10127         uint32_t i;
10128
10129         if (value == NULL) {
10130                 PMD_DRV_LOG(ERR, "value is NULL");
10131                 return false;
10132         }
10133
10134         for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10135                 if (hw->device_id == swr_pm_table[i].device_id) {
10136                         *value = swr_pm_table[i].val;
10137
10138                         PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10139                                     "value - 0x%08x",
10140                                     hw->device_id, *value);
10141                         return true;
10142                 }
10143         }
10144
10145         return false;
10146 }
10147
10148 static int
10149 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10150 {
10151         enum i40e_status_code status;
10152         struct i40e_aq_get_phy_abilities_resp phy_ab;
10153         int ret = -ENOTSUP;
10154         int retries = 0;
10155
10156         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10157                                               NULL);
10158
10159         while (status) {
10160                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10161                         status);
10162                 retries++;
10163                 rte_delay_us(100000);
10164                 if  (retries < 5)
10165                         status = i40e_aq_get_phy_capabilities(hw, false,
10166                                         true, &phy_ab, NULL);
10167                 else
10168                         return ret;
10169         }
10170         return 0;
10171 }
10172
10173 static void
10174 i40e_configure_registers(struct i40e_hw *hw)
10175 {
10176         static struct {
10177                 uint32_t addr;
10178                 uint64_t val;
10179         } reg_table[] = {
10180                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10181                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10182                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10183         };
10184         uint64_t reg;
10185         uint32_t i;
10186         int ret;
10187
10188         for (i = 0; i < RTE_DIM(reg_table); i++) {
10189                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10190                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10191                                 reg_table[i].val =
10192                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10193                         else /* For X710/XL710/XXV710 */
10194                                 if (hw->aq.fw_maj_ver < 6)
10195                                         reg_table[i].val =
10196                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10197                                 else
10198                                         reg_table[i].val =
10199                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10200                 }
10201
10202                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10203                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10204                                 reg_table[i].val =
10205                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10206                         else /* For X710/XL710/XXV710 */
10207                                 reg_table[i].val =
10208                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10209                 }
10210
10211                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10212                         uint32_t cfg_val;
10213
10214                         if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10215                                 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10216                                             "GL_SWR_PM_UP_THR value fixup",
10217                                             hw->device_id);
10218                                 continue;
10219                         }
10220
10221                         reg_table[i].val = cfg_val;
10222                 }
10223
10224                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10225                                                         &reg, NULL);
10226                 if (ret < 0) {
10227                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10228                                                         reg_table[i].addr);
10229                         break;
10230                 }
10231                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10232                                                 reg_table[i].addr, reg);
10233                 if (reg == reg_table[i].val)
10234                         continue;
10235
10236                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10237                                                 reg_table[i].val, NULL);
10238                 if (ret < 0) {
10239                         PMD_DRV_LOG(ERR,
10240                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10241                                 reg_table[i].val, reg_table[i].addr);
10242                         break;
10243                 }
10244                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10245                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10246         }
10247 }
10248
10249 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
10250 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
10251 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10252 static int
10253 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10254 {
10255         uint32_t reg;
10256         int ret;
10257
10258         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10259                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10260                 return -EINVAL;
10261         }
10262
10263         /* Configure for double VLAN RX stripping */
10264         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10265         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10266                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10267                 ret = i40e_aq_debug_write_register(hw,
10268                                                    I40E_VSI_TSR(vsi->vsi_id),
10269                                                    reg, NULL);
10270                 if (ret < 0) {
10271                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10272                                     vsi->vsi_id);
10273                         return I40E_ERR_CONFIG;
10274                 }
10275         }
10276
10277         /* Configure for double VLAN TX insertion */
10278         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10279         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10280                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10281                 ret = i40e_aq_debug_write_register(hw,
10282                                                    I40E_VSI_L2TAGSTXVALID(
10283                                                    vsi->vsi_id), reg, NULL);
10284                 if (ret < 0) {
10285                         PMD_DRV_LOG(ERR,
10286                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
10287                                 vsi->vsi_id);
10288                         return I40E_ERR_CONFIG;
10289                 }
10290         }
10291
10292         return 0;
10293 }
10294
10295 static uint64_t
10296 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10297 {
10298         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10299         uint64_t systim_cycles;
10300
10301         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10302         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10303                         << 32;
10304
10305         return systim_cycles;
10306 }
10307
10308 static uint64_t
10309 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10310 {
10311         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10312         uint64_t rx_tstamp;
10313
10314         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10315         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10316                         << 32;
10317
10318         return rx_tstamp;
10319 }
10320
10321 static uint64_t
10322 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10323 {
10324         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10325         uint64_t tx_tstamp;
10326
10327         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10328         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10329                         << 32;
10330
10331         return tx_tstamp;
10332 }
10333
10334 static void
10335 i40e_start_timecounters(struct rte_eth_dev *dev)
10336 {
10337         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10338         struct i40e_adapter *adapter = dev->data->dev_private;
10339         struct rte_eth_link link;
10340         uint32_t tsync_inc_l;
10341         uint32_t tsync_inc_h;
10342
10343         /* Get current link speed. */
10344         i40e_dev_link_update(dev, 1);
10345         rte_eth_linkstatus_get(dev, &link);
10346
10347         switch (link.link_speed) {
10348         case RTE_ETH_SPEED_NUM_40G:
10349         case RTE_ETH_SPEED_NUM_25G:
10350                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10351                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10352                 break;
10353         case RTE_ETH_SPEED_NUM_10G:
10354                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10355                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10356                 break;
10357         case RTE_ETH_SPEED_NUM_1G:
10358                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10359                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10360                 break;
10361         default:
10362                 tsync_inc_l = 0x0;
10363                 tsync_inc_h = 0x0;
10364         }
10365
10366         /* Set the timesync increment value. */
10367         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10368         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10369
10370         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10371         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10372         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10373
10374         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10375         adapter->systime_tc.cc_shift = 0;
10376         adapter->systime_tc.nsec_mask = 0;
10377
10378         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10379         adapter->rx_tstamp_tc.cc_shift = 0;
10380         adapter->rx_tstamp_tc.nsec_mask = 0;
10381
10382         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10383         adapter->tx_tstamp_tc.cc_shift = 0;
10384         adapter->tx_tstamp_tc.nsec_mask = 0;
10385 }
10386
10387 static int
10388 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10389 {
10390         struct i40e_adapter *adapter = dev->data->dev_private;
10391
10392         adapter->systime_tc.nsec += delta;
10393         adapter->rx_tstamp_tc.nsec += delta;
10394         adapter->tx_tstamp_tc.nsec += delta;
10395
10396         return 0;
10397 }
10398
10399 static int
10400 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10401 {
10402         uint64_t ns;
10403         struct i40e_adapter *adapter = dev->data->dev_private;
10404
10405         ns = rte_timespec_to_ns(ts);
10406
10407         /* Set the timecounters to a new value. */
10408         adapter->systime_tc.nsec = ns;
10409         adapter->rx_tstamp_tc.nsec = ns;
10410         adapter->tx_tstamp_tc.nsec = ns;
10411
10412         return 0;
10413 }
10414
10415 static int
10416 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10417 {
10418         uint64_t ns, systime_cycles;
10419         struct i40e_adapter *adapter = dev->data->dev_private;
10420
10421         systime_cycles = i40e_read_systime_cyclecounter(dev);
10422         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10423         *ts = rte_ns_to_timespec(ns);
10424
10425         return 0;
10426 }
10427
10428 static int
10429 i40e_timesync_enable(struct rte_eth_dev *dev)
10430 {
10431         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10432         uint32_t tsync_ctl_l;
10433         uint32_t tsync_ctl_h;
10434
10435         /* Stop the timesync system time. */
10436         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10437         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10438         /* Reset the timesync system time value. */
10439         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10440         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10441
10442         i40e_start_timecounters(dev);
10443
10444         /* Clear timesync registers. */
10445         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10446         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10447         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10448         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10449         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10450         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10451
10452         /* Enable timestamping of PTP packets. */
10453         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10454         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10455
10456         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10457         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10458         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10459
10460         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10461         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10462
10463         return 0;
10464 }
10465
10466 static int
10467 i40e_timesync_disable(struct rte_eth_dev *dev)
10468 {
10469         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10470         uint32_t tsync_ctl_l;
10471         uint32_t tsync_ctl_h;
10472
10473         /* Disable timestamping of transmitted PTP packets. */
10474         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10475         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10476
10477         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10478         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10479
10480         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10481         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10482
10483         /* Reset the timesync increment value. */
10484         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10485         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10486
10487         return 0;
10488 }
10489
10490 static int
10491 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10492                                 struct timespec *timestamp, uint32_t flags)
10493 {
10494         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10495         struct i40e_adapter *adapter = dev->data->dev_private;
10496         uint32_t sync_status;
10497         uint32_t index = flags & 0x03;
10498         uint64_t rx_tstamp_cycles;
10499         uint64_t ns;
10500
10501         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10502         if ((sync_status & (1 << index)) == 0)
10503                 return -EINVAL;
10504
10505         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10506         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10507         *timestamp = rte_ns_to_timespec(ns);
10508
10509         return 0;
10510 }
10511
10512 static int
10513 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10514                                 struct timespec *timestamp)
10515 {
10516         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10517         struct i40e_adapter *adapter = dev->data->dev_private;
10518         uint32_t sync_status;
10519         uint64_t tx_tstamp_cycles;
10520         uint64_t ns;
10521
10522         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10523         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10524                 return -EINVAL;
10525
10526         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10527         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10528         *timestamp = rte_ns_to_timespec(ns);
10529
10530         return 0;
10531 }
10532
10533 /*
10534  * i40e_parse_dcb_configure - parse dcb configure from user
10535  * @dev: the device being configured
10536  * @dcb_cfg: pointer of the result of parse
10537  * @*tc_map: bit map of enabled traffic classes
10538  *
10539  * Returns 0 on success, negative value on failure
10540  */
10541 static int
10542 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10543                          struct i40e_dcbx_config *dcb_cfg,
10544                          uint8_t *tc_map)
10545 {
10546         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10547         uint8_t i, tc_bw, bw_lf;
10548
10549         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10550
10551         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10552         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10553                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10554                 return -EINVAL;
10555         }
10556
10557         /* assume each tc has the same bw */
10558         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10559         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10560                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10561         /* to ensure the sum of tcbw is equal to 100 */
10562         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10563         for (i = 0; i < bw_lf; i++)
10564                 dcb_cfg->etscfg.tcbwtable[i]++;
10565
10566         /* assume each tc has the same Transmission Selection Algorithm */
10567         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10568                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10569
10570         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10571                 dcb_cfg->etscfg.prioritytable[i] =
10572                                 dcb_rx_conf->dcb_tc[i];
10573
10574         /* FW needs one App to configure HW */
10575         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10576         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10577         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10578         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10579
10580         if (dcb_rx_conf->nb_tcs == 0)
10581                 *tc_map = 1; /* tc0 only */
10582         else
10583                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10584
10585         if (dev->data->dev_conf.dcb_capability_en & RTE_ETH_DCB_PFC_SUPPORT) {
10586                 dcb_cfg->pfc.willing = 0;
10587                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10588                 dcb_cfg->pfc.pfcenable = *tc_map;
10589         }
10590         return 0;
10591 }
10592
10593
10594 static enum i40e_status_code
10595 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10596                               struct i40e_aqc_vsi_properties_data *info,
10597                               uint8_t enabled_tcmap)
10598 {
10599         enum i40e_status_code ret;
10600         int i, total_tc = 0;
10601         uint16_t qpnum_per_tc, bsf, qp_idx;
10602         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10603         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10604         uint16_t used_queues;
10605
10606         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10607         if (ret != I40E_SUCCESS)
10608                 return ret;
10609
10610         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10611                 if (enabled_tcmap & (1 << i))
10612                         total_tc++;
10613         }
10614         if (total_tc == 0)
10615                 total_tc = 1;
10616         vsi->enabled_tc = enabled_tcmap;
10617
10618         /* different VSI has different queues assigned */
10619         if (vsi->type == I40E_VSI_MAIN)
10620                 used_queues = dev_data->nb_rx_queues -
10621                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10622         else if (vsi->type == I40E_VSI_VMDQ2)
10623                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10624         else {
10625                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10626                 return I40E_ERR_NO_AVAILABLE_VSI;
10627         }
10628
10629         qpnum_per_tc = used_queues / total_tc;
10630         /* Number of queues per enabled TC */
10631         if (qpnum_per_tc == 0) {
10632                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10633                 return I40E_ERR_INVALID_QP_ID;
10634         }
10635         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10636                                 I40E_MAX_Q_PER_TC);
10637         bsf = rte_bsf32(qpnum_per_tc);
10638
10639         /**
10640          * Configure TC and queue mapping parameters, for enabled TC,
10641          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10642          * default queue will serve it.
10643          */
10644         qp_idx = 0;
10645         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10646                 if (vsi->enabled_tc & (1 << i)) {
10647                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10648                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10649                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10650                         qp_idx += qpnum_per_tc;
10651                 } else
10652                         info->tc_mapping[i] = 0;
10653         }
10654
10655         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10656         if (vsi->type == I40E_VSI_SRIOV) {
10657                 info->mapping_flags |=
10658                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10659                 for (i = 0; i < vsi->nb_qps; i++)
10660                         info->queue_mapping[i] =
10661                                 rte_cpu_to_le_16(vsi->base_queue + i);
10662         } else {
10663                 info->mapping_flags |=
10664                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10665                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10666         }
10667         info->valid_sections |=
10668                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10669
10670         return I40E_SUCCESS;
10671 }
10672
10673 /*
10674  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10675  * @veb: VEB to be configured
10676  * @tc_map: enabled TC bitmap
10677  *
10678  * Returns 0 on success, negative value on failure
10679  */
10680 static enum i40e_status_code
10681 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10682 {
10683         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10684         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10685         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10686         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10687         enum i40e_status_code ret = I40E_SUCCESS;
10688         int i;
10689         uint32_t bw_max;
10690
10691         /* Check if enabled_tc is same as existing or new TCs */
10692         if (veb->enabled_tc == tc_map)
10693                 return ret;
10694
10695         /* configure tc bandwidth */
10696         memset(&veb_bw, 0, sizeof(veb_bw));
10697         veb_bw.tc_valid_bits = tc_map;
10698         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10699         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10700                 if (tc_map & BIT_ULL(i))
10701                         veb_bw.tc_bw_share_credits[i] = 1;
10702         }
10703         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10704                                                    &veb_bw, NULL);
10705         if (ret) {
10706                 PMD_INIT_LOG(ERR,
10707                         "AQ command Config switch_comp BW allocation per TC failed = %d",
10708                         hw->aq.asq_last_status);
10709                 return ret;
10710         }
10711
10712         memset(&ets_query, 0, sizeof(ets_query));
10713         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10714                                                    &ets_query, NULL);
10715         if (ret != I40E_SUCCESS) {
10716                 PMD_DRV_LOG(ERR,
10717                         "Failed to get switch_comp ETS configuration %u",
10718                         hw->aq.asq_last_status);
10719                 return ret;
10720         }
10721         memset(&bw_query, 0, sizeof(bw_query));
10722         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10723                                                   &bw_query, NULL);
10724         if (ret != I40E_SUCCESS) {
10725                 PMD_DRV_LOG(ERR,
10726                         "Failed to get switch_comp bandwidth configuration %u",
10727                         hw->aq.asq_last_status);
10728                 return ret;
10729         }
10730
10731         /* store and print out BW info */
10732         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10733         veb->bw_info.bw_max = ets_query.tc_bw_max;
10734         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10735         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10736         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10737                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10738                      I40E_16_BIT_WIDTH);
10739         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10740                 veb->bw_info.bw_ets_share_credits[i] =
10741                                 bw_query.tc_bw_share_credits[i];
10742                 veb->bw_info.bw_ets_credits[i] =
10743                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10744                 /* 4 bits per TC, 4th bit is reserved */
10745                 veb->bw_info.bw_ets_max[i] =
10746                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10747                                   RTE_LEN2MASK(3, uint8_t));
10748                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10749                             veb->bw_info.bw_ets_share_credits[i]);
10750                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10751                             veb->bw_info.bw_ets_credits[i]);
10752                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10753                             veb->bw_info.bw_ets_max[i]);
10754         }
10755
10756         veb->enabled_tc = tc_map;
10757
10758         return ret;
10759 }
10760
10761
10762 /*
10763  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10764  * @vsi: VSI to be configured
10765  * @tc_map: enabled TC bitmap
10766  *
10767  * Returns 0 on success, negative value on failure
10768  */
10769 static enum i40e_status_code
10770 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10771 {
10772         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10773         struct i40e_vsi_context ctxt;
10774         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10775         enum i40e_status_code ret = I40E_SUCCESS;
10776         int i;
10777
10778         /* Check if enabled_tc is same as existing or new TCs */
10779         if (vsi->enabled_tc == tc_map)
10780                 return ret;
10781
10782         /* configure tc bandwidth */
10783         memset(&bw_data, 0, sizeof(bw_data));
10784         bw_data.tc_valid_bits = tc_map;
10785         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10786         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10787                 if (tc_map & BIT_ULL(i))
10788                         bw_data.tc_bw_credits[i] = 1;
10789         }
10790         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10791         if (ret) {
10792                 PMD_INIT_LOG(ERR,
10793                         "AQ command Config VSI BW allocation per TC failed = %d",
10794                         hw->aq.asq_last_status);
10795                 goto out;
10796         }
10797         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10798                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10799
10800         /* Update Queue Pairs Mapping for currently enabled UPs */
10801         ctxt.seid = vsi->seid;
10802         ctxt.pf_num = hw->pf_id;
10803         ctxt.vf_num = 0;
10804         ctxt.uplink_seid = vsi->uplink_seid;
10805         ctxt.info = vsi->info;
10806         i40e_get_cap(hw);
10807         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10808         if (ret)
10809                 goto out;
10810
10811         /* Update the VSI after updating the VSI queue-mapping information */
10812         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10813         if (ret) {
10814                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10815                         hw->aq.asq_last_status);
10816                 goto out;
10817         }
10818         /* update the local VSI info with updated queue map */
10819         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10820                                         sizeof(vsi->info.tc_mapping));
10821         rte_memcpy(&vsi->info.queue_mapping,
10822                         &ctxt.info.queue_mapping,
10823                 sizeof(vsi->info.queue_mapping));
10824         vsi->info.mapping_flags = ctxt.info.mapping_flags;
10825         vsi->info.valid_sections = 0;
10826
10827         /* query and update current VSI BW information */
10828         ret = i40e_vsi_get_bw_config(vsi);
10829         if (ret) {
10830                 PMD_INIT_LOG(ERR,
10831                          "Failed updating vsi bw info, err %s aq_err %s",
10832                          i40e_stat_str(hw, ret),
10833                          i40e_aq_str(hw, hw->aq.asq_last_status));
10834                 goto out;
10835         }
10836
10837         vsi->enabled_tc = tc_map;
10838
10839 out:
10840         return ret;
10841 }
10842
10843 /*
10844  * i40e_dcb_hw_configure - program the dcb setting to hw
10845  * @pf: pf the configuration is taken on
10846  * @new_cfg: new configuration
10847  * @tc_map: enabled TC bitmap
10848  *
10849  * Returns 0 on success, negative value on failure
10850  */
10851 static enum i40e_status_code
10852 i40e_dcb_hw_configure(struct i40e_pf *pf,
10853                       struct i40e_dcbx_config *new_cfg,
10854                       uint8_t tc_map)
10855 {
10856         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10857         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10858         struct i40e_vsi *main_vsi = pf->main_vsi;
10859         struct i40e_vsi_list *vsi_list;
10860         enum i40e_status_code ret;
10861         int i;
10862         uint32_t val;
10863
10864         /* Use the FW API if FW > v4.4*/
10865         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10866               (hw->aq.fw_maj_ver >= 5))) {
10867                 PMD_INIT_LOG(ERR,
10868                         "FW < v4.4, can not use FW LLDP API to configure DCB");
10869                 return I40E_ERR_FIRMWARE_API_VERSION;
10870         }
10871
10872         /* Check if need reconfiguration */
10873         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10874                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10875                 return I40E_SUCCESS;
10876         }
10877
10878         /* Copy the new config to the current config */
10879         *old_cfg = *new_cfg;
10880         old_cfg->etsrec = old_cfg->etscfg;
10881         ret = i40e_set_dcb_config(hw);
10882         if (ret) {
10883                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10884                          i40e_stat_str(hw, ret),
10885                          i40e_aq_str(hw, hw->aq.asq_last_status));
10886                 return ret;
10887         }
10888         /* set receive Arbiter to RR mode and ETS scheme by default */
10889         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10890                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10891                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
10892                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10893                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10894                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10895                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10896                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10897                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10898                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10899                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10900                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10901                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10902         }
10903         /* get local mib to check whether it is configured correctly */
10904         /* IEEE mode */
10905         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10906         /* Get Local DCB Config */
10907         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10908                                      &hw->local_dcbx_config);
10909
10910         /* if Veb is created, need to update TC of it at first */
10911         if (main_vsi->veb) {
10912                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10913                 if (ret)
10914                         PMD_INIT_LOG(WARNING,
10915                                  "Failed configuring TC for VEB seid=%d",
10916                                  main_vsi->veb->seid);
10917         }
10918         /* Update each VSI */
10919         i40e_vsi_config_tc(main_vsi, tc_map);
10920         if (main_vsi->veb) {
10921                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10922                         /* Beside main VSI and VMDQ VSIs, only enable default
10923                          * TC for other VSIs
10924                          */
10925                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10926                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10927                                                          tc_map);
10928                         else
10929                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10930                                                          I40E_DEFAULT_TCMAP);
10931                         if (ret)
10932                                 PMD_INIT_LOG(WARNING,
10933                                         "Failed configuring TC for VSI seid=%d",
10934                                         vsi_list->vsi->seid);
10935                         /* continue */
10936                 }
10937         }
10938         return I40E_SUCCESS;
10939 }
10940
10941 /*
10942  * i40e_dcb_init_configure - initial dcb config
10943  * @dev: device being configured
10944  * @sw_dcb: indicate whether dcb is sw configured or hw offload
10945  *
10946  * Returns 0 on success, negative value on failure
10947  */
10948 int
10949 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10950 {
10951         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10952         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10953         int i, ret = 0;
10954
10955         if ((pf->flags & I40E_FLAG_DCB) == 0) {
10956                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10957                 return -ENOTSUP;
10958         }
10959
10960         /* DCB initialization:
10961          * Update DCB configuration from the Firmware and configure
10962          * LLDP MIB change event.
10963          */
10964         if (sw_dcb == TRUE) {
10965                 /* Stopping lldp is necessary for DPDK, but it will cause
10966                  * DCB init failed. For i40e_init_dcb(), the prerequisite
10967                  * for successful initialization of DCB is that LLDP is
10968                  * enabled. So it is needed to start lldp before DCB init
10969                  * and stop it after initialization.
10970                  */
10971                 ret = i40e_aq_start_lldp(hw, true, NULL);
10972                 if (ret != I40E_SUCCESS)
10973                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10974
10975                 ret = i40e_init_dcb(hw, true);
10976                 /* If lldp agent is stopped, the return value from
10977                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10978                  * adminq status. Otherwise, it should return success.
10979                  */
10980                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10981                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10982                         memset(&hw->local_dcbx_config, 0,
10983                                 sizeof(struct i40e_dcbx_config));
10984                         /* set dcb default configuration */
10985                         hw->local_dcbx_config.etscfg.willing = 0;
10986                         hw->local_dcbx_config.etscfg.maxtcs = 0;
10987                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10988                         hw->local_dcbx_config.etscfg.tsatable[0] =
10989                                                 I40E_IEEE_TSA_ETS;
10990                         /* all UPs mapping to TC0 */
10991                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10992                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10993                         hw->local_dcbx_config.etsrec =
10994                                 hw->local_dcbx_config.etscfg;
10995                         hw->local_dcbx_config.pfc.willing = 0;
10996                         hw->local_dcbx_config.pfc.pfccap =
10997                                                 I40E_MAX_TRAFFIC_CLASS;
10998                         /* FW needs one App to configure HW */
10999                         hw->local_dcbx_config.numapps = 1;
11000                         hw->local_dcbx_config.app[0].selector =
11001                                                 I40E_APP_SEL_ETHTYPE;
11002                         hw->local_dcbx_config.app[0].priority = 3;
11003                         hw->local_dcbx_config.app[0].protocolid =
11004                                                 I40E_APP_PROTOID_FCOE;
11005                         ret = i40e_set_dcb_config(hw);
11006                         if (ret) {
11007                                 PMD_INIT_LOG(ERR,
11008                                         "default dcb config fails. err = %d, aq_err = %d.",
11009                                         ret, hw->aq.asq_last_status);
11010                                 return -ENOSYS;
11011                         }
11012                 } else {
11013                         PMD_INIT_LOG(ERR,
11014                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11015                                 ret, hw->aq.asq_last_status);
11016                         return -ENOTSUP;
11017                 }
11018
11019                 if (i40e_need_stop_lldp(dev)) {
11020                         ret = i40e_aq_stop_lldp(hw, true, true, NULL);
11021                         if (ret != I40E_SUCCESS)
11022                                 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
11023                 }
11024         } else {
11025                 ret = i40e_aq_start_lldp(hw, true, NULL);
11026                 if (ret != I40E_SUCCESS)
11027                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11028
11029                 ret = i40e_init_dcb(hw, true);
11030                 if (!ret) {
11031                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11032                                 PMD_INIT_LOG(ERR,
11033                                         "HW doesn't support DCBX offload.");
11034                                 return -ENOTSUP;
11035                         }
11036                 } else {
11037                         PMD_INIT_LOG(ERR,
11038                                 "DCBX configuration failed, err = %d, aq_err = %d.",
11039                                 ret, hw->aq.asq_last_status);
11040                         return -ENOTSUP;
11041                 }
11042         }
11043         return 0;
11044 }
11045
11046 /*
11047  * i40e_dcb_setup - setup dcb related config
11048  * @dev: device being configured
11049  *
11050  * Returns 0 on success, negative value on failure
11051  */
11052 static int
11053 i40e_dcb_setup(struct rte_eth_dev *dev)
11054 {
11055         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11056         struct i40e_dcbx_config dcb_cfg;
11057         uint8_t tc_map = 0;
11058         int ret = 0;
11059
11060         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11061                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11062                 return -ENOTSUP;
11063         }
11064
11065         if (pf->vf_num != 0)
11066                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11067
11068         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11069         if (ret) {
11070                 PMD_INIT_LOG(ERR, "invalid dcb config");
11071                 return -EINVAL;
11072         }
11073         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11074         if (ret) {
11075                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11076                 return -ENOSYS;
11077         }
11078
11079         return 0;
11080 }
11081
11082 static int
11083 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11084                       struct rte_eth_dcb_info *dcb_info)
11085 {
11086         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11087         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11088         struct i40e_vsi *vsi = pf->main_vsi;
11089         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11090         uint16_t bsf, tc_mapping;
11091         int i, j = 0;
11092
11093         if (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_DCB_FLAG)
11094                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11095         else
11096                 dcb_info->nb_tcs = 1;
11097         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11098                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11099         for (i = 0; i < dcb_info->nb_tcs; i++)
11100                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11101
11102         /* get queue mapping if vmdq is disabled */
11103         if (!pf->nb_cfg_vmdq_vsi) {
11104                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11105                         if (!(vsi->enabled_tc & (1 << i)))
11106                                 continue;
11107                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11108                         dcb_info->tc_queue.tc_rxq[j][i].base =
11109                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11110                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11111                         dcb_info->tc_queue.tc_txq[j][i].base =
11112                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11113                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11114                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11115                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11116                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11117                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11118                 }
11119                 return 0;
11120         }
11121
11122         /* get queue mapping if vmdq is enabled */
11123         do {
11124                 vsi = pf->vmdq[j].vsi;
11125                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11126                         if (!(vsi->enabled_tc & (1 << i)))
11127                                 continue;
11128                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11129                         dcb_info->tc_queue.tc_rxq[j][i].base =
11130                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11131                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11132                         dcb_info->tc_queue.tc_txq[j][i].base =
11133                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11134                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11135                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11136                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11137                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11138                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11139                 }
11140                 j++;
11141         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, RTE_ETH_MAX_VMDQ_POOL));
11142         return 0;
11143 }
11144
11145 static int
11146 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11147 {
11148         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11149         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
11150         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11151         uint16_t msix_intr;
11152
11153         msix_intr = rte_intr_vec_list_index_get(intr_handle, queue_id);
11154         if (msix_intr == I40E_MISC_VEC_ID)
11155                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11156                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
11157                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11158                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11159         else
11160                 I40E_WRITE_REG(hw,
11161                                I40E_PFINT_DYN_CTLN(msix_intr -
11162                                                    I40E_RX_VEC_START),
11163                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
11164                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11165                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11166
11167         I40E_WRITE_FLUSH(hw);
11168         rte_intr_ack(pci_dev->intr_handle);
11169
11170         return 0;
11171 }
11172
11173 static int
11174 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11175 {
11176         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11177         struct rte_intr_handle *intr_handle = pci_dev->intr_handle;
11178         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11179         uint16_t msix_intr;
11180
11181         msix_intr = rte_intr_vec_list_index_get(intr_handle, queue_id);
11182         if (msix_intr == I40E_MISC_VEC_ID)
11183                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11184                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11185         else
11186                 I40E_WRITE_REG(hw,
11187                                I40E_PFINT_DYN_CTLN(msix_intr -
11188                                                    I40E_RX_VEC_START),
11189                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11190         I40E_WRITE_FLUSH(hw);
11191
11192         return 0;
11193 }
11194
11195 /**
11196  * This function is used to check if the register is valid.
11197  * Below is the valid registers list for X722 only:
11198  * 0x2b800--0x2bb00
11199  * 0x38700--0x38a00
11200  * 0x3d800--0x3db00
11201  * 0x208e00--0x209000
11202  * 0x20be00--0x20c000
11203  * 0x263c00--0x264000
11204  * 0x265c00--0x266000
11205  */
11206 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset)
11207 {
11208         if ((type != I40E_MAC_X722) &&
11209             ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) ||
11210              (reg_offset >= 0x38700 && reg_offset <= 0x38a00) ||
11211              (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) ||
11212              (reg_offset >= 0x208e00 && reg_offset <= 0x209000) ||
11213              (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) ||
11214              (reg_offset >= 0x263c00 && reg_offset <= 0x264000) ||
11215              (reg_offset >= 0x265c00 && reg_offset <= 0x266000)))
11216                 return 0;
11217         else
11218                 return 1;
11219 }
11220
11221 static int i40e_get_regs(struct rte_eth_dev *dev,
11222                          struct rte_dev_reg_info *regs)
11223 {
11224         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11225         uint32_t *ptr_data = regs->data;
11226         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11227         const struct i40e_reg_info *reg_info;
11228
11229         if (ptr_data == NULL) {
11230                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11231                 regs->width = sizeof(uint32_t);
11232                 return 0;
11233         }
11234
11235         /* The first few registers have to be read using AQ operations */
11236         reg_idx = 0;
11237         while (i40e_regs_adminq[reg_idx].name) {
11238                 reg_info = &i40e_regs_adminq[reg_idx++];
11239                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11240                         for (arr_idx2 = 0;
11241                                         arr_idx2 <= reg_info->count2;
11242                                         arr_idx2++) {
11243                                 reg_offset = arr_idx * reg_info->stride1 +
11244                                         arr_idx2 * reg_info->stride2;
11245                                 reg_offset += reg_info->base_addr;
11246                                 ptr_data[reg_offset >> 2] =
11247                                         i40e_read_rx_ctl(hw, reg_offset);
11248                         }
11249         }
11250
11251         /* The remaining registers can be read using primitives */
11252         reg_idx = 0;
11253         while (i40e_regs_others[reg_idx].name) {
11254                 reg_info = &i40e_regs_others[reg_idx++];
11255                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11256                         for (arr_idx2 = 0;
11257                                         arr_idx2 <= reg_info->count2;
11258                                         arr_idx2++) {
11259                                 reg_offset = arr_idx * reg_info->stride1 +
11260                                         arr_idx2 * reg_info->stride2;
11261                                 reg_offset += reg_info->base_addr;
11262                                 if (!i40e_valid_regs(hw->mac.type, reg_offset))
11263                                         ptr_data[reg_offset >> 2] = 0;
11264                                 else
11265                                         ptr_data[reg_offset >> 2] =
11266                                                 I40E_READ_REG(hw, reg_offset);
11267                         }
11268         }
11269
11270         return 0;
11271 }
11272
11273 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11274 {
11275         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11276
11277         /* Convert word count to byte count */
11278         return hw->nvm.sr_size << 1;
11279 }
11280
11281 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11282                            struct rte_dev_eeprom_info *eeprom)
11283 {
11284         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11285         uint16_t *data = eeprom->data;
11286         uint16_t offset, length, cnt_words;
11287         int ret_code;
11288
11289         offset = eeprom->offset >> 1;
11290         length = eeprom->length >> 1;
11291         cnt_words = length;
11292
11293         if (offset > hw->nvm.sr_size ||
11294                 offset + length > hw->nvm.sr_size) {
11295                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11296                 return -EINVAL;
11297         }
11298
11299         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11300
11301         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11302         if (ret_code != I40E_SUCCESS || cnt_words != length) {
11303                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11304                 return -EIO;
11305         }
11306
11307         return 0;
11308 }
11309
11310 static int i40e_get_module_info(struct rte_eth_dev *dev,
11311                                 struct rte_eth_dev_module_info *modinfo)
11312 {
11313         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11314         uint32_t sff8472_comp = 0;
11315         uint32_t sff8472_swap = 0;
11316         uint32_t sff8636_rev = 0;
11317         i40e_status status;
11318         uint32_t type = 0;
11319
11320         /* Check if firmware supports reading module EEPROM. */
11321         if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
11322                 PMD_DRV_LOG(ERR,
11323                             "Module EEPROM memory read not supported. "
11324                             "Please update the NVM image.\n");
11325                 return -EINVAL;
11326         }
11327
11328         status = i40e_update_link_info(hw);
11329         if (status)
11330                 return -EIO;
11331
11332         if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
11333                 PMD_DRV_LOG(ERR,
11334                             "Cannot read module EEPROM memory. "
11335                             "No module connected.\n");
11336                 return -EINVAL;
11337         }
11338
11339         type = hw->phy.link_info.module_type[0];
11340
11341         switch (type) {
11342         case I40E_MODULE_TYPE_SFP:
11343                 status = i40e_aq_get_phy_register(hw,
11344                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11345                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
11346                                 I40E_MODULE_SFF_8472_COMP,
11347                                 &sff8472_comp, NULL);
11348                 if (status)
11349                         return -EIO;
11350
11351                 status = i40e_aq_get_phy_register(hw,
11352                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11353                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
11354                                 I40E_MODULE_SFF_8472_SWAP,
11355                                 &sff8472_swap, NULL);
11356                 if (status)
11357                         return -EIO;
11358
11359                 /* Check if the module requires address swap to access
11360                  * the other EEPROM memory page.
11361                  */
11362                 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
11363                         PMD_DRV_LOG(WARNING,
11364                                     "Module address swap to access "
11365                                     "page 0xA2 is not supported.\n");
11366                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
11367                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11368                 } else if (sff8472_comp == 0x00) {
11369                         /* Module is not SFF-8472 compliant */
11370                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
11371                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11372                 } else {
11373                         modinfo->type = RTE_ETH_MODULE_SFF_8472;
11374                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
11375                 }
11376                 break;
11377         case I40E_MODULE_TYPE_QSFP_PLUS:
11378                 /* Read from memory page 0. */
11379                 status = i40e_aq_get_phy_register(hw,
11380                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11381                                 0, 1,
11382                                 I40E_MODULE_REVISION_ADDR,
11383                                 &sff8636_rev, NULL);
11384                 if (status)
11385                         return -EIO;
11386                 /* Determine revision compliance byte */
11387                 if (sff8636_rev > 0x02) {
11388                         /* Module is SFF-8636 compliant */
11389                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
11390                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11391                 } else {
11392                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
11393                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11394                 }
11395                 break;
11396         case I40E_MODULE_TYPE_QSFP28:
11397                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11398                 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11399                 break;
11400         default:
11401                 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
11402                 return -EINVAL;
11403         }
11404         return 0;
11405 }
11406
11407 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
11408                                   struct rte_dev_eeprom_info *info)
11409 {
11410         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11411         bool is_sfp = false;
11412         i40e_status status;
11413         uint8_t *data;
11414         uint32_t value = 0;
11415         uint32_t i;
11416
11417         if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
11418                 is_sfp = true;
11419
11420         data = info->data;
11421         for (i = 0; i < info->length; i++) {
11422                 u32 offset = i + info->offset;
11423                 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
11424
11425                 /* Check if we need to access the other memory page */
11426                 if (is_sfp) {
11427                         if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
11428                                 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
11429                                 addr = I40E_I2C_EEPROM_DEV_ADDR2;
11430                         }
11431                 } else {
11432                         while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
11433                                 /* Compute memory page number and offset. */
11434                                 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
11435                                 addr++;
11436                         }
11437                 }
11438                 status = i40e_aq_get_phy_register(hw,
11439                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11440                                 addr, 1, offset, &value, NULL);
11441                 if (status)
11442                         return -EIO;
11443                 data[i] = (uint8_t)value;
11444         }
11445         return 0;
11446 }
11447
11448 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11449                                      struct rte_ether_addr *mac_addr)
11450 {
11451         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11452         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11453         struct i40e_vsi *vsi = pf->main_vsi;
11454         struct i40e_mac_filter_info mac_filter;
11455         struct i40e_mac_filter *f;
11456         int ret;
11457
11458         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
11459                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11460                 return -EINVAL;
11461         }
11462
11463         TAILQ_FOREACH(f, &vsi->mac_list, next) {
11464                 if (rte_is_same_ether_addr(&pf->dev_addr,
11465                                                 &f->mac_info.mac_addr))
11466                         break;
11467         }
11468
11469         if (f == NULL) {
11470                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11471                 return -EIO;
11472         }
11473
11474         mac_filter = f->mac_info;
11475         ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11476         if (ret != I40E_SUCCESS) {
11477                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11478                 return -EIO;
11479         }
11480         memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11481         ret = i40e_vsi_add_mac(vsi, &mac_filter);
11482         if (ret != I40E_SUCCESS) {
11483                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11484                 return -EIO;
11485         }
11486         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11487
11488         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11489                                         mac_addr->addr_bytes, NULL);
11490         if (ret != I40E_SUCCESS) {
11491                 PMD_DRV_LOG(ERR, "Failed to change mac");
11492                 return -EIO;
11493         }
11494
11495         return 0;
11496 }
11497
11498 static int
11499 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu __rte_unused)
11500 {
11501         /* mtu setting is forbidden if port is start */
11502         if (dev->data->dev_started != 0) {
11503                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
11504                             dev->data->port_id);
11505                 return -EBUSY;
11506         }
11507
11508         return 0;
11509 }
11510
11511 /* Restore ethertype filter */
11512 static void
11513 i40e_ethertype_filter_restore(struct i40e_pf *pf)
11514 {
11515         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11516         struct i40e_ethertype_filter_list
11517                 *ethertype_list = &pf->ethertype.ethertype_list;
11518         struct i40e_ethertype_filter *f;
11519         struct i40e_control_filter_stats stats;
11520         uint16_t flags;
11521
11522         TAILQ_FOREACH(f, ethertype_list, rules) {
11523                 flags = 0;
11524                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
11525                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
11526                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
11527                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
11528                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
11529
11530                 memset(&stats, 0, sizeof(stats));
11531                 i40e_aq_add_rem_control_packet_filter(hw,
11532                                             f->input.mac_addr.addr_bytes,
11533                                             f->input.ether_type,
11534                                             flags, pf->main_vsi->seid,
11535                                             f->queue, 1, &stats, NULL);
11536         }
11537         PMD_DRV_LOG(INFO, "Ethertype filter:"
11538                     " mac_etype_used = %u, etype_used = %u,"
11539                     " mac_etype_free = %u, etype_free = %u",
11540                     stats.mac_etype_used, stats.etype_used,
11541                     stats.mac_etype_free, stats.etype_free);
11542 }
11543
11544 /* Restore tunnel filter */
11545 static void
11546 i40e_tunnel_filter_restore(struct i40e_pf *pf)
11547 {
11548         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11549         struct i40e_vsi *vsi;
11550         struct i40e_pf_vf *vf;
11551         struct i40e_tunnel_filter_list
11552                 *tunnel_list = &pf->tunnel.tunnel_list;
11553         struct i40e_tunnel_filter *f;
11554         struct i40e_aqc_cloud_filters_element_bb cld_filter;
11555         bool big_buffer = 0;
11556
11557         TAILQ_FOREACH(f, tunnel_list, rules) {
11558                 if (!f->is_to_vf)
11559                         vsi = pf->main_vsi;
11560                 else {
11561                         vf = &pf->vfs[f->vf_id];
11562                         vsi = vf->vsi;
11563                 }
11564                 memset(&cld_filter, 0, sizeof(cld_filter));
11565                 rte_ether_addr_copy((struct rte_ether_addr *)
11566                                 &f->input.outer_mac,
11567                         (struct rte_ether_addr *)&cld_filter.element.outer_mac);
11568                 rte_ether_addr_copy((struct rte_ether_addr *)
11569                                 &f->input.inner_mac,
11570                         (struct rte_ether_addr *)&cld_filter.element.inner_mac);
11571                 cld_filter.element.inner_vlan = f->input.inner_vlan;
11572                 cld_filter.element.flags = f->input.flags;
11573                 cld_filter.element.tenant_id = f->input.tenant_id;
11574                 cld_filter.element.queue_number = f->queue;
11575                 rte_memcpy(cld_filter.general_fields,
11576                            f->input.general_fields,
11577                            sizeof(f->input.general_fields));
11578
11579                 if (((f->input.flags &
11580                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
11581                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
11582                     ((f->input.flags &
11583                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
11584                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
11585                     ((f->input.flags &
11586                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
11587                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
11588                         big_buffer = 1;
11589
11590                 if (big_buffer)
11591                         i40e_aq_add_cloud_filters_bb(hw,
11592                                         vsi->seid, &cld_filter, 1);
11593                 else
11594                         i40e_aq_add_cloud_filters(hw, vsi->seid,
11595                                                   &cld_filter.element, 1);
11596         }
11597 }
11598
11599 static void
11600 i40e_filter_restore(struct i40e_pf *pf)
11601 {
11602         i40e_ethertype_filter_restore(pf);
11603         i40e_tunnel_filter_restore(pf);
11604         i40e_fdir_filter_restore(pf);
11605         (void)i40e_hash_filter_restore(pf);
11606 }
11607
11608 bool
11609 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
11610 {
11611         if (strcmp(dev->device->driver->name, drv->driver.name))
11612                 return false;
11613
11614         return true;
11615 }
11616
11617 bool
11618 is_i40e_supported(struct rte_eth_dev *dev)
11619 {
11620         return is_device_supported(dev, &rte_i40e_pmd);
11621 }
11622
11623 struct i40e_customized_pctype*
11624 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
11625 {
11626         int i;
11627
11628         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
11629                 if (pf->customized_pctype[i].index == index)
11630                         return &pf->customized_pctype[i];
11631         }
11632         return NULL;
11633 }
11634
11635 static int
11636 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
11637                               uint32_t pkg_size, uint32_t proto_num,
11638                               struct rte_pmd_i40e_proto_info *proto,
11639                               enum rte_pmd_i40e_package_op op)
11640 {
11641         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11642         uint32_t pctype_num;
11643         struct rte_pmd_i40e_ptype_info *pctype;
11644         uint32_t buff_size;
11645         struct i40e_customized_pctype *new_pctype = NULL;
11646         uint8_t proto_id;
11647         uint8_t pctype_value;
11648         char name[64];
11649         uint32_t i, j, n;
11650         int ret;
11651
11652         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11653             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11654                 PMD_DRV_LOG(ERR, "Unsupported operation.");
11655                 return -1;
11656         }
11657
11658         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11659                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
11660                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
11661         if (ret) {
11662                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
11663                 return -1;
11664         }
11665         if (!pctype_num) {
11666                 PMD_DRV_LOG(INFO, "No new pctype added");
11667                 return -1;
11668         }
11669
11670         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
11671         pctype = rte_zmalloc("new_pctype", buff_size, 0);
11672         if (!pctype) {
11673                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11674                 return -1;
11675         }
11676         /* get information about new pctype list */
11677         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11678                                         (uint8_t *)pctype, buff_size,
11679                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
11680         if (ret) {
11681                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
11682                 rte_free(pctype);
11683                 return -1;
11684         }
11685
11686         /* Update customized pctype. */
11687         for (i = 0; i < pctype_num; i++) {
11688                 pctype_value = pctype[i].ptype_id;
11689                 memset(name, 0, sizeof(name));
11690                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11691                         proto_id = pctype[i].protocols[j];
11692                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11693                                 continue;
11694                         for (n = 0; n < proto_num; n++) {
11695                                 if (proto[n].proto_id != proto_id)
11696                                         continue;
11697                                 strlcat(name, proto[n].name, sizeof(name));
11698                                 strlcat(name, "_", sizeof(name));
11699                                 break;
11700                         }
11701                 }
11702                 name[strlen(name) - 1] = '\0';
11703                 PMD_DRV_LOG(INFO, "name = %s\n", name);
11704                 if (!strcmp(name, "GTPC"))
11705                         new_pctype =
11706                                 i40e_find_customized_pctype(pf,
11707                                                       I40E_CUSTOMIZED_GTPC);
11708                 else if (!strcmp(name, "GTPU_IPV4"))
11709                         new_pctype =
11710                                 i40e_find_customized_pctype(pf,
11711                                                    I40E_CUSTOMIZED_GTPU_IPV4);
11712                 else if (!strcmp(name, "GTPU_IPV6"))
11713                         new_pctype =
11714                                 i40e_find_customized_pctype(pf,
11715                                                    I40E_CUSTOMIZED_GTPU_IPV6);
11716                 else if (!strcmp(name, "GTPU"))
11717                         new_pctype =
11718                                 i40e_find_customized_pctype(pf,
11719                                                       I40E_CUSTOMIZED_GTPU);
11720                 else if (!strcmp(name, "IPV4_L2TPV3"))
11721                         new_pctype =
11722                                 i40e_find_customized_pctype(pf,
11723                                                 I40E_CUSTOMIZED_IPV4_L2TPV3);
11724                 else if (!strcmp(name, "IPV6_L2TPV3"))
11725                         new_pctype =
11726                                 i40e_find_customized_pctype(pf,
11727                                                 I40E_CUSTOMIZED_IPV6_L2TPV3);
11728                 else if (!strcmp(name, "IPV4_ESP"))
11729                         new_pctype =
11730                                 i40e_find_customized_pctype(pf,
11731                                                 I40E_CUSTOMIZED_ESP_IPV4);
11732                 else if (!strcmp(name, "IPV6_ESP"))
11733                         new_pctype =
11734                                 i40e_find_customized_pctype(pf,
11735                                                 I40E_CUSTOMIZED_ESP_IPV6);
11736                 else if (!strcmp(name, "IPV4_UDP_ESP"))
11737                         new_pctype =
11738                                 i40e_find_customized_pctype(pf,
11739                                                 I40E_CUSTOMIZED_ESP_IPV4_UDP);
11740                 else if (!strcmp(name, "IPV6_UDP_ESP"))
11741                         new_pctype =
11742                                 i40e_find_customized_pctype(pf,
11743                                                 I40E_CUSTOMIZED_ESP_IPV6_UDP);
11744                 else if (!strcmp(name, "IPV4_AH"))
11745                         new_pctype =
11746                                 i40e_find_customized_pctype(pf,
11747                                                 I40E_CUSTOMIZED_AH_IPV4);
11748                 else if (!strcmp(name, "IPV6_AH"))
11749                         new_pctype =
11750                                 i40e_find_customized_pctype(pf,
11751                                                 I40E_CUSTOMIZED_AH_IPV6);
11752                 if (new_pctype) {
11753                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
11754                                 new_pctype->pctype = pctype_value;
11755                                 new_pctype->valid = true;
11756                         } else {
11757                                 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
11758                                 new_pctype->valid = false;
11759                         }
11760                 }
11761         }
11762
11763         rte_free(pctype);
11764         return 0;
11765 }
11766
11767 static int
11768 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
11769                              uint32_t pkg_size, uint32_t proto_num,
11770                              struct rte_pmd_i40e_proto_info *proto,
11771                              enum rte_pmd_i40e_package_op op)
11772 {
11773         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
11774         uint16_t port_id = dev->data->port_id;
11775         uint32_t ptype_num;
11776         struct rte_pmd_i40e_ptype_info *ptype;
11777         uint32_t buff_size;
11778         uint8_t proto_id;
11779         char name[RTE_PMD_I40E_DDP_NAME_SIZE];
11780         uint32_t i, j, n;
11781         bool in_tunnel;
11782         int ret;
11783
11784         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11785             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11786                 PMD_DRV_LOG(ERR, "Unsupported operation.");
11787                 return -1;
11788         }
11789
11790         if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
11791                 rte_pmd_i40e_ptype_mapping_reset(port_id);
11792                 return 0;
11793         }
11794
11795         /* get information about new ptype num */
11796         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11797                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
11798                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
11799         if (ret) {
11800                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
11801                 return ret;
11802         }
11803         if (!ptype_num) {
11804                 PMD_DRV_LOG(INFO, "No new ptype added");
11805                 return -1;
11806         }
11807
11808         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
11809         ptype = rte_zmalloc("new_ptype", buff_size, 0);
11810         if (!ptype) {
11811                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11812                 return -1;
11813         }
11814
11815         /* get information about new ptype list */
11816         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11817                                         (uint8_t *)ptype, buff_size,
11818                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
11819         if (ret) {
11820                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
11821                 rte_free(ptype);
11822                 return ret;
11823         }
11824
11825         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
11826         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
11827         if (!ptype_mapping) {
11828                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11829                 rte_free(ptype);
11830                 return -1;
11831         }
11832
11833         /* Update ptype mapping table. */
11834         for (i = 0; i < ptype_num; i++) {
11835                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
11836                 ptype_mapping[i].sw_ptype = 0;
11837                 in_tunnel = false;
11838                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11839                         proto_id = ptype[i].protocols[j];
11840                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11841                                 continue;
11842                         for (n = 0; n < proto_num; n++) {
11843                                 if (proto[n].proto_id != proto_id)
11844                                         continue;
11845                                 memset(name, 0, sizeof(name));
11846                                 strcpy(name, proto[n].name);
11847                                 PMD_DRV_LOG(INFO, "name = %s\n", name);
11848                                 if (!strncasecmp(name, "PPPOE", 5))
11849                                         ptype_mapping[i].sw_ptype |=
11850                                                 RTE_PTYPE_L2_ETHER_PPPOE;
11851                                 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
11852                                          !in_tunnel) {
11853                                         ptype_mapping[i].sw_ptype |=
11854                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11855                                         ptype_mapping[i].sw_ptype |=
11856                                                 RTE_PTYPE_L4_FRAG;
11857                                 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
11858                                            in_tunnel) {
11859                                         ptype_mapping[i].sw_ptype |=
11860                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11861                                         ptype_mapping[i].sw_ptype |=
11862                                                 RTE_PTYPE_INNER_L4_FRAG;
11863                                 } else if (!strncasecmp(name, "OIPV4", 5)) {
11864                                         ptype_mapping[i].sw_ptype |=
11865                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11866                                         in_tunnel = true;
11867                                 } else if (!strncasecmp(name, "IPV4", 4) &&
11868                                            !in_tunnel)
11869                                         ptype_mapping[i].sw_ptype |=
11870                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11871                                 else if (!strncasecmp(name, "IPV4", 4) &&
11872                                          in_tunnel)
11873                                         ptype_mapping[i].sw_ptype |=
11874                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11875                                 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
11876                                          !in_tunnel) {
11877                                         ptype_mapping[i].sw_ptype |=
11878                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11879                                         ptype_mapping[i].sw_ptype |=
11880                                                 RTE_PTYPE_L4_FRAG;
11881                                 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
11882                                            in_tunnel) {
11883                                         ptype_mapping[i].sw_ptype |=
11884                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11885                                         ptype_mapping[i].sw_ptype |=
11886                                                 RTE_PTYPE_INNER_L4_FRAG;
11887                                 } else if (!strncasecmp(name, "OIPV6", 5)) {
11888                                         ptype_mapping[i].sw_ptype |=
11889                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11890                                         in_tunnel = true;
11891                                 } else if (!strncasecmp(name, "IPV6", 4) &&
11892                                            !in_tunnel)
11893                                         ptype_mapping[i].sw_ptype |=
11894                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11895                                 else if (!strncasecmp(name, "IPV6", 4) &&
11896                                          in_tunnel)
11897                                         ptype_mapping[i].sw_ptype |=
11898                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11899                                 else if (!strncasecmp(name, "UDP", 3) &&
11900                                          !in_tunnel)
11901                                         ptype_mapping[i].sw_ptype |=
11902                                                 RTE_PTYPE_L4_UDP;
11903                                 else if (!strncasecmp(name, "UDP", 3) &&
11904                                          in_tunnel)
11905                                         ptype_mapping[i].sw_ptype |=
11906                                                 RTE_PTYPE_INNER_L4_UDP;
11907                                 else if (!strncasecmp(name, "TCP", 3) &&
11908                                          !in_tunnel)
11909                                         ptype_mapping[i].sw_ptype |=
11910                                                 RTE_PTYPE_L4_TCP;
11911                                 else if (!strncasecmp(name, "TCP", 3) &&
11912                                          in_tunnel)
11913                                         ptype_mapping[i].sw_ptype |=
11914                                                 RTE_PTYPE_INNER_L4_TCP;
11915                                 else if (!strncasecmp(name, "SCTP", 4) &&
11916                                          !in_tunnel)
11917                                         ptype_mapping[i].sw_ptype |=
11918                                                 RTE_PTYPE_L4_SCTP;
11919                                 else if (!strncasecmp(name, "SCTP", 4) &&
11920                                          in_tunnel)
11921                                         ptype_mapping[i].sw_ptype |=
11922                                                 RTE_PTYPE_INNER_L4_SCTP;
11923                                 else if ((!strncasecmp(name, "ICMP", 4) ||
11924                                           !strncasecmp(name, "ICMPV6", 6)) &&
11925                                          !in_tunnel)
11926                                         ptype_mapping[i].sw_ptype |=
11927                                                 RTE_PTYPE_L4_ICMP;
11928                                 else if ((!strncasecmp(name, "ICMP", 4) ||
11929                                           !strncasecmp(name, "ICMPV6", 6)) &&
11930                                          in_tunnel)
11931                                         ptype_mapping[i].sw_ptype |=
11932                                                 RTE_PTYPE_INNER_L4_ICMP;
11933                                 else if (!strncasecmp(name, "GTPC", 4)) {
11934                                         ptype_mapping[i].sw_ptype |=
11935                                                 RTE_PTYPE_TUNNEL_GTPC;
11936                                         in_tunnel = true;
11937                                 } else if (!strncasecmp(name, "GTPU", 4)) {
11938                                         ptype_mapping[i].sw_ptype |=
11939                                                 RTE_PTYPE_TUNNEL_GTPU;
11940                                         in_tunnel = true;
11941                                 } else if (!strncasecmp(name, "ESP", 3)) {
11942                                         ptype_mapping[i].sw_ptype |=
11943                                                 RTE_PTYPE_TUNNEL_ESP;
11944                                         in_tunnel = true;
11945                                 } else if (!strncasecmp(name, "GRENAT", 6)) {
11946                                         ptype_mapping[i].sw_ptype |=
11947                                                 RTE_PTYPE_TUNNEL_GRENAT;
11948                                         in_tunnel = true;
11949                                 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
11950                                            !strncasecmp(name, "L2TPV2", 6) ||
11951                                            !strncasecmp(name, "L2TPV3", 6)) {
11952                                         ptype_mapping[i].sw_ptype |=
11953                                                 RTE_PTYPE_TUNNEL_L2TP;
11954                                         in_tunnel = true;
11955                                 }
11956
11957                                 break;
11958                         }
11959                 }
11960         }
11961
11962         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
11963                                                 ptype_num, 0);
11964         if (ret)
11965                 PMD_DRV_LOG(ERR, "Failed to update ptype mapping table.");
11966
11967         rte_free(ptype_mapping);
11968         rte_free(ptype);
11969         return ret;
11970 }
11971
11972 void
11973 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
11974                             uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
11975 {
11976         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11977         uint32_t proto_num;
11978         struct rte_pmd_i40e_proto_info *proto;
11979         uint32_t buff_size;
11980         uint32_t i;
11981         int ret;
11982
11983         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11984             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11985                 PMD_DRV_LOG(ERR, "Unsupported operation.");
11986                 return;
11987         }
11988
11989         /* get information about protocol number */
11990         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11991                                        (uint8_t *)&proto_num, sizeof(proto_num),
11992                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
11993         if (ret) {
11994                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
11995                 return;
11996         }
11997         if (!proto_num) {
11998                 PMD_DRV_LOG(INFO, "No new protocol added");
11999                 return;
12000         }
12001
12002         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12003         proto = rte_zmalloc("new_proto", buff_size, 0);
12004         if (!proto) {
12005                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12006                 return;
12007         }
12008
12009         /* get information about protocol list */
12010         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12011                                         (uint8_t *)proto, buff_size,
12012                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12013         if (ret) {
12014                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12015                 rte_free(proto);
12016                 return;
12017         }
12018
12019         /* Check if GTP is supported. */
12020         for (i = 0; i < proto_num; i++) {
12021                 if (!strncmp(proto[i].name, "GTP", 3)) {
12022                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12023                                 pf->gtp_support = true;
12024                         else
12025                                 pf->gtp_support = false;
12026                         break;
12027                 }
12028         }
12029
12030         /* Check if ESP is supported. */
12031         for (i = 0; i < proto_num; i++) {
12032                 if (!strncmp(proto[i].name, "ESP", 3)) {
12033                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12034                                 pf->esp_support = true;
12035                         else
12036                                 pf->esp_support = false;
12037                         break;
12038                 }
12039         }
12040
12041         /* Update customized pctype info */
12042         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12043                                             proto_num, proto, op);
12044         if (ret)
12045                 PMD_DRV_LOG(INFO, "No pctype is updated.");
12046
12047         /* Update customized ptype info */
12048         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12049                                            proto_num, proto, op);
12050         if (ret)
12051                 PMD_DRV_LOG(INFO, "No ptype is updated.");
12052
12053         rte_free(proto);
12054 }
12055
12056 /* Create a QinQ cloud filter
12057  *
12058  * The Fortville NIC has limited resources for tunnel filters,
12059  * so we can only reuse existing filters.
12060  *
12061  * In step 1 we define which Field Vector fields can be used for
12062  * filter types.
12063  * As we do not have the inner tag defined as a field,
12064  * we have to define it first, by reusing one of L1 entries.
12065  *
12066  * In step 2 we are replacing one of existing filter types with
12067  * a new one for QinQ.
12068  * As we reusing L1 and replacing L2, some of the default filter
12069  * types will disappear,which depends on L1 and L2 entries we reuse.
12070  *
12071  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12072  *
12073  * 1.   Create L1 filter of outer vlan (12b) which will be in use
12074  *              later when we define the cloud filter.
12075  *      a.      Valid_flags.replace_cloud = 0
12076  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
12077  *      c.      New_filter = 0x10
12078  *      d.      TR bit = 0xff (optional, not used here)
12079  *      e.      Buffer – 2 entries:
12080  *              i.      Byte 0 = 8 (outer vlan FV index).
12081  *                      Byte 1 = 0 (rsv)
12082  *                      Byte 2-3 = 0x0fff
12083  *              ii.     Byte 0 = 37 (inner vlan FV index).
12084  *                      Byte 1 =0 (rsv)
12085  *                      Byte 2-3 = 0x0fff
12086  *
12087  * Step 2:
12088  * 2.   Create cloud filter using two L1 filters entries: stag and
12089  *              new filter(outer vlan+ inner vlan)
12090  *      a.      Valid_flags.replace_cloud = 1
12091  *      b.      Old_filter = 1 (instead of outer IP)
12092  *      c.      New_filter = 0x10
12093  *      d.      Buffer – 2 entries:
12094  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
12095  *                      Byte 1-3 = 0 (rsv)
12096  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12097  *                      Byte 9-11 = 0 (rsv)
12098  */
12099 static int
12100 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12101 {
12102         int ret = -ENOTSUP;
12103         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
12104         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
12105         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12106         struct rte_eth_dev *dev = &rte_eth_devices[pf->dev_data->port_id];
12107
12108         if (pf->support_multi_driver) {
12109                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12110                 return ret;
12111         }
12112
12113         /* Init */
12114         memset(&filter_replace, 0,
12115                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12116         memset(&filter_replace_buf, 0,
12117                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12118
12119         /* create L1 filter */
12120         filter_replace.old_filter_type =
12121                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12122         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12123         filter_replace.tr_bit = 0;
12124
12125         /* Prepare the buffer, 2 entries */
12126         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12127         filter_replace_buf.data[0] |=
12128                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12129         /* Field Vector 12b mask */
12130         filter_replace_buf.data[2] = 0xff;
12131         filter_replace_buf.data[3] = 0x0f;
12132         filter_replace_buf.data[4] =
12133                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12134         filter_replace_buf.data[4] |=
12135                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12136         /* Field Vector 12b mask */
12137         filter_replace_buf.data[6] = 0xff;
12138         filter_replace_buf.data[7] = 0x0f;
12139         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12140                         &filter_replace_buf);
12141         if (ret != I40E_SUCCESS)
12142                 return ret;
12143
12144         if (filter_replace.old_filter_type !=
12145             filter_replace.new_filter_type)
12146                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
12147                             " original: 0x%x, new: 0x%x",
12148                             dev->device->name,
12149                             filter_replace.old_filter_type,
12150                             filter_replace.new_filter_type);
12151
12152         /* Apply the second L2 cloud filter */
12153         memset(&filter_replace, 0,
12154                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12155         memset(&filter_replace_buf, 0,
12156                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12157
12158         /* create L2 filter, input for L2 filter will be L1 filter  */
12159         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12160         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12161         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12162
12163         /* Prepare the buffer, 2 entries */
12164         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12165         filter_replace_buf.data[0] |=
12166                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12167         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12168         filter_replace_buf.data[4] |=
12169                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12170         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12171                         &filter_replace_buf);
12172         if (!ret && (filter_replace.old_filter_type !=
12173                      filter_replace.new_filter_type))
12174                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
12175                             " original: 0x%x, new: 0x%x",
12176                             dev->device->name,
12177                             filter_replace.old_filter_type,
12178                             filter_replace.new_filter_type);
12179
12180         return ret;
12181 }
12182
12183 static void
12184 i40e_set_mac_max_frame(struct rte_eth_dev *dev, uint16_t size)
12185 {
12186         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12187         uint32_t rep_cnt = MAX_REPEAT_TIME;
12188         struct rte_eth_link link;
12189         enum i40e_status_code status;
12190         bool can_be_set = true;
12191
12192         /* I40E_MEDIA_TYPE_BASET link up can be ignored */
12193         if (hw->phy.media_type != I40E_MEDIA_TYPE_BASET) {
12194                 do {
12195                         update_link_reg(hw, &link);
12196                         if (link.link_status)
12197                                 break;
12198                         rte_delay_ms(CHECK_INTERVAL);
12199                 } while (--rep_cnt);
12200                 can_be_set = !!link.link_status;
12201         }
12202
12203         if (can_be_set) {
12204                 status = i40e_aq_set_mac_config(hw, size, TRUE, 0, false, NULL);
12205                 if (status != I40E_SUCCESS)
12206                         PMD_DRV_LOG(ERR, "Failed to set max frame size at port level");
12207         } else {
12208                 PMD_DRV_LOG(ERR, "Set max frame size at port level not applicable on link down");
12209         }
12210 }
12211
12212 RTE_LOG_REGISTER_SUFFIX(i40e_logtype_init, init, NOTICE);
12213 RTE_LOG_REGISTER_SUFFIX(i40e_logtype_driver, driver, NOTICE);
12214 #ifdef RTE_ETHDEV_DEBUG_RX
12215 RTE_LOG_REGISTER_SUFFIX(i40e_logtype_rx, rx, DEBUG);
12216 #endif
12217 #ifdef RTE_ETHDEV_DEBUG_TX
12218 RTE_LOG_REGISTER_SUFFIX(i40e_logtype_tx, tx, DEBUG);
12219 #endif
12220
12221 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12222                               ETH_I40E_FLOATING_VEB_ARG "=1"
12223                               ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
12224                               ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12225                               ETH_I40E_SUPPORT_MULTI_DRIVER "=1");