1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
14 #include <rte_common.h>
16 #include <rte_string_fns.h>
18 #include <rte_bus_pci.h>
19 #include <rte_ether.h>
20 #include <ethdev_driver.h>
21 #include <ethdev_pci.h>
22 #include <rte_memzone.h>
23 #include <rte_malloc.h>
24 #include <rte_memcpy.h>
25 #include <rte_alarm.h>
27 #include <rte_tailq.h>
28 #include <rte_hash_crc.h>
29 #include <rte_bitmap.h>
30 #include <rte_os_shim.h>
32 #include "i40e_logs.h"
33 #include "base/i40e_prototype.h"
34 #include "base/i40e_adminq_cmd.h"
35 #include "base/i40e_type.h"
36 #include "base/i40e_register.h"
37 #include "base/i40e_dcb.h"
38 #include "i40e_ethdev.h"
39 #include "i40e_rxtx.h"
41 #include "i40e_regs.h"
42 #include "rte_pmd_i40e.h"
43 #include "i40e_hash.h"
45 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
46 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
47 #define ETH_I40E_SUPPORT_MULTI_DRIVER "support-multi-driver"
48 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG "queue-num-per-vf"
49 #define ETH_I40E_VF_MSG_CFG "vf_msg_cfg"
51 #define I40E_CLEAR_PXE_WAIT_MS 200
52 #define I40E_VSI_TSR_QINQ_STRIP 0x4010
53 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
55 /* Maximun number of capability elements */
56 #define I40E_MAX_CAP_ELE_NUM 128
58 /* Wait count and interval */
59 #define I40E_CHK_Q_ENA_COUNT 1000
60 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
62 /* Maximun number of VSI */
63 #define I40E_MAX_NUM_VSIS (384UL)
65 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
67 /* Flow control default timer */
68 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
70 /* Flow control enable fwd bit */
71 #define I40E_PRTMAC_FWD_CTRL 0x00000001
73 /* Receive Packet Buffer size */
74 #define I40E_RXPBSIZE (968 * 1024)
77 #define I40E_KILOSHIFT 10
79 /* Flow control default high water */
80 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
82 /* Flow control default low water */
83 #define I40E_DEFAULT_LOW_WATER (0xF2000 >> I40E_KILOSHIFT)
85 /* Receive Average Packet Size in Byte*/
86 #define I40E_PACKET_AVERAGE_SIZE 128
88 /* Mask of PF interrupt causes */
89 #define I40E_PFINT_ICR0_ENA_MASK ( \
90 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
91 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
92 I40E_PFINT_ICR0_ENA_GRST_MASK | \
93 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
94 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
95 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
96 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
97 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
98 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
100 #define I40E_FLOW_TYPES ( \
101 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
102 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
103 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
104 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
105 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
106 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
107 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
108 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
109 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
110 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
111 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
113 /* Additional timesync values. */
114 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
115 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
116 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
117 #define I40E_PRTTSYN_TSYNENA 0x80000000
118 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
119 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
122 * Below are values for writing un-exposed registers suggested
125 /* Destination MAC address */
126 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
127 /* Source MAC address */
128 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
129 /* Outer (S-Tag) VLAN tag in the outer L2 header */
130 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
131 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
132 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
133 /* Single VLAN tag in the inner L2 header */
134 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
135 /* Source IPv4 address */
136 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
137 /* Destination IPv4 address */
138 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
139 /* Source IPv4 address for X722 */
140 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
141 /* Destination IPv4 address for X722 */
142 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
143 /* IPv4 Protocol for X722 */
144 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
145 /* IPv4 Time to Live for X722 */
146 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
147 /* IPv4 Type of Service (TOS) */
148 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
150 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
151 /* IPv4 Time to Live */
152 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
153 /* Source IPv6 address */
154 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
155 /* Destination IPv6 address */
156 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
157 /* IPv6 Traffic Class (TC) */
158 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
159 /* IPv6 Next Header */
160 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
162 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
164 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
165 /* Destination L4 port */
166 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
167 /* SCTP verification tag */
168 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
169 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
170 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
171 /* Source port of tunneling UDP */
172 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
173 /* Destination port of tunneling UDP */
174 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
175 /* UDP Tunneling ID, NVGRE/GRE key */
176 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
177 /* Last ether type */
178 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
179 /* Tunneling outer destination IPv4 address */
180 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
181 /* Tunneling outer destination IPv6 address */
182 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
183 /* 1st word of flex payload */
184 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
185 /* 2nd word of flex payload */
186 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
187 /* 3rd word of flex payload */
188 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
189 /* 4th word of flex payload */
190 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
191 /* 5th word of flex payload */
192 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
193 /* 6th word of flex payload */
194 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
195 /* 7th word of flex payload */
196 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
197 /* 8th word of flex payload */
198 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
199 /* all 8 words flex payload */
200 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
201 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
203 #define I40E_TRANSLATE_INSET 0
204 #define I40E_TRANSLATE_REG 1
206 #define I40E_INSET_IPV4_TOS_MASK 0x0000FF00UL
207 #define I40E_INSET_IPV4_TTL_MASK 0x000000FFUL
208 #define I40E_INSET_IPV4_PROTO_MASK 0x0000FF00UL
209 #define I40E_INSET_IPV6_TC_MASK 0x0000F00FUL
210 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x0000FF00UL
211 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000000FFUL
213 /* PCI offset for querying capability */
214 #define PCI_DEV_CAP_REG 0xA4
215 /* PCI offset for enabling/disabling Extended Tag */
216 #define PCI_DEV_CTRL_REG 0xA8
217 /* Bit mask of Extended Tag capability */
218 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
219 /* Bit shift of Extended Tag enable/disable */
220 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
221 /* Bit mask of Extended Tag enable/disable */
222 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
224 #define I40E_GLQF_PIT_IPV4_START 2
225 #define I40E_GLQF_PIT_IPV4_COUNT 2
226 #define I40E_GLQF_PIT_IPV6_START 4
227 #define I40E_GLQF_PIT_IPV6_COUNT 2
229 #define I40E_GLQF_PIT_SOURCE_OFF_GET(a) \
230 (((a) & I40E_GLQF_PIT_SOURCE_OFF_MASK) >> \
231 I40E_GLQF_PIT_SOURCE_OFF_SHIFT)
233 #define I40E_GLQF_PIT_DEST_OFF_GET(a) \
234 (((a) & I40E_GLQF_PIT_DEST_OFF_MASK) >> \
235 I40E_GLQF_PIT_DEST_OFF_SHIFT)
237 #define I40E_GLQF_PIT_FSIZE_GET(a) (((a) & I40E_GLQF_PIT_FSIZE_MASK) >> \
238 I40E_GLQF_PIT_FSIZE_SHIFT)
240 #define I40E_GLQF_PIT_BUILD(off, mask) (((off) << 16) | (mask))
241 #define I40E_FDIR_FIELD_OFFSET(a) ((a) >> 1)
243 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
244 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
245 static int i40e_dev_configure(struct rte_eth_dev *dev);
246 static int i40e_dev_start(struct rte_eth_dev *dev);
247 static int i40e_dev_stop(struct rte_eth_dev *dev);
248 static int i40e_dev_close(struct rte_eth_dev *dev);
249 static int i40e_dev_reset(struct rte_eth_dev *dev);
250 static int i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
251 static int i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
252 static int i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
253 static int i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
254 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
255 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
256 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
257 struct rte_eth_stats *stats);
258 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
259 struct rte_eth_xstat *xstats, unsigned n);
260 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
261 struct rte_eth_xstat_name *xstats_names,
263 static int i40e_dev_stats_reset(struct rte_eth_dev *dev);
264 static int i40e_fw_version_get(struct rte_eth_dev *dev,
265 char *fw_version, size_t fw_size);
266 static int i40e_dev_info_get(struct rte_eth_dev *dev,
267 struct rte_eth_dev_info *dev_info);
268 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
271 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
272 enum rte_vlan_type vlan_type,
274 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
275 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
278 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
279 static int i40e_dev_led_on(struct rte_eth_dev *dev);
280 static int i40e_dev_led_off(struct rte_eth_dev *dev);
281 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
282 struct rte_eth_fc_conf *fc_conf);
283 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
284 struct rte_eth_fc_conf *fc_conf);
285 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
286 struct rte_eth_pfc_conf *pfc_conf);
287 static int i40e_macaddr_add(struct rte_eth_dev *dev,
288 struct rte_ether_addr *mac_addr,
291 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
292 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
293 struct rte_eth_rss_reta_entry64 *reta_conf,
295 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
296 struct rte_eth_rss_reta_entry64 *reta_conf,
299 static int i40e_get_cap(struct i40e_hw *hw);
300 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
301 static int i40e_pf_setup(struct i40e_pf *pf);
302 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
303 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
304 static int i40e_dcb_setup(struct rte_eth_dev *dev);
305 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
306 bool offset_loaded, uint64_t *offset, uint64_t *stat);
307 static void i40e_stat_update_48(struct i40e_hw *hw,
313 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
314 static void i40e_dev_interrupt_handler(void *param);
315 static void i40e_dev_alarm_handler(void *param);
316 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
317 uint32_t base, uint32_t num);
318 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
319 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
321 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
323 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
324 static int i40e_veb_release(struct i40e_veb *veb);
325 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
326 struct i40e_vsi *vsi);
327 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
328 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
329 struct i40e_macvlan_filter *mv_f,
332 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
333 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
334 struct rte_eth_rss_conf *rss_conf);
335 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
336 struct rte_eth_rss_conf *rss_conf);
337 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
338 struct rte_eth_udp_tunnel *udp_tunnel);
339 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
340 struct rte_eth_udp_tunnel *udp_tunnel);
341 static void i40e_filter_input_set_init(struct i40e_pf *pf);
342 static int i40e_dev_flow_ops_get(struct rte_eth_dev *dev,
343 const struct rte_flow_ops **ops);
344 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
345 struct rte_eth_dcb_info *dcb_info);
346 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
347 static void i40e_configure_registers(struct i40e_hw *hw);
348 static void i40e_hw_init(struct rte_eth_dev *dev);
349 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
350 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
356 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
357 struct rte_eth_mirror_conf *mirror_conf,
358 uint8_t sw_id, uint8_t on);
359 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
361 static int i40e_timesync_enable(struct rte_eth_dev *dev);
362 static int i40e_timesync_disable(struct rte_eth_dev *dev);
363 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
364 struct timespec *timestamp,
366 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
367 struct timespec *timestamp);
368 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
370 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
372 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
373 struct timespec *timestamp);
374 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
375 const struct timespec *timestamp);
377 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
379 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
382 static int i40e_get_regs(struct rte_eth_dev *dev,
383 struct rte_dev_reg_info *regs);
385 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
387 static int i40e_get_eeprom(struct rte_eth_dev *dev,
388 struct rte_dev_eeprom_info *eeprom);
390 static int i40e_get_module_info(struct rte_eth_dev *dev,
391 struct rte_eth_dev_module_info *modinfo);
392 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
393 struct rte_dev_eeprom_info *info);
395 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
396 struct rte_ether_addr *mac_addr);
398 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
400 static int i40e_ethertype_filter_convert(
401 const struct rte_eth_ethertype_filter *input,
402 struct i40e_ethertype_filter *filter);
403 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
404 struct i40e_ethertype_filter *filter);
406 static int i40e_tunnel_filter_convert(
407 struct i40e_aqc_cloud_filters_element_bb *cld_filter,
408 struct i40e_tunnel_filter *tunnel_filter);
409 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
410 struct i40e_tunnel_filter *tunnel_filter);
411 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
413 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
414 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
415 static void i40e_filter_restore(struct i40e_pf *pf);
416 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
418 static const char *const valid_keys[] = {
419 ETH_I40E_FLOATING_VEB_ARG,
420 ETH_I40E_FLOATING_VEB_LIST_ARG,
421 ETH_I40E_SUPPORT_MULTI_DRIVER,
422 ETH_I40E_QUEUE_NUM_PER_VF_ARG,
426 static const struct rte_pci_id pci_id_i40e_map[] = {
427 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
428 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
429 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
430 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
431 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
432 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
435 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
436 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
437 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
438 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
439 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
440 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
441 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
442 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
443 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
444 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
445 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
446 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
447 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X710_N3000) },
448 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_XXV710_N3000) },
449 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_BC) },
450 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_5G_BASE_T_BC) },
451 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_B) },
452 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_SFP) },
453 { .vendor_id = 0, /* sentinel */ },
456 static const struct eth_dev_ops i40e_eth_dev_ops = {
457 .dev_configure = i40e_dev_configure,
458 .dev_start = i40e_dev_start,
459 .dev_stop = i40e_dev_stop,
460 .dev_close = i40e_dev_close,
461 .dev_reset = i40e_dev_reset,
462 .promiscuous_enable = i40e_dev_promiscuous_enable,
463 .promiscuous_disable = i40e_dev_promiscuous_disable,
464 .allmulticast_enable = i40e_dev_allmulticast_enable,
465 .allmulticast_disable = i40e_dev_allmulticast_disable,
466 .dev_set_link_up = i40e_dev_set_link_up,
467 .dev_set_link_down = i40e_dev_set_link_down,
468 .link_update = i40e_dev_link_update,
469 .stats_get = i40e_dev_stats_get,
470 .xstats_get = i40e_dev_xstats_get,
471 .xstats_get_names = i40e_dev_xstats_get_names,
472 .stats_reset = i40e_dev_stats_reset,
473 .xstats_reset = i40e_dev_stats_reset,
474 .fw_version_get = i40e_fw_version_get,
475 .dev_infos_get = i40e_dev_info_get,
476 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
477 .vlan_filter_set = i40e_vlan_filter_set,
478 .vlan_tpid_set = i40e_vlan_tpid_set,
479 .vlan_offload_set = i40e_vlan_offload_set,
480 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
481 .vlan_pvid_set = i40e_vlan_pvid_set,
482 .rx_queue_start = i40e_dev_rx_queue_start,
483 .rx_queue_stop = i40e_dev_rx_queue_stop,
484 .tx_queue_start = i40e_dev_tx_queue_start,
485 .tx_queue_stop = i40e_dev_tx_queue_stop,
486 .rx_queue_setup = i40e_dev_rx_queue_setup,
487 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
488 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
489 .rx_queue_release = i40e_dev_rx_queue_release,
490 .tx_queue_setup = i40e_dev_tx_queue_setup,
491 .tx_queue_release = i40e_dev_tx_queue_release,
492 .dev_led_on = i40e_dev_led_on,
493 .dev_led_off = i40e_dev_led_off,
494 .flow_ctrl_get = i40e_flow_ctrl_get,
495 .flow_ctrl_set = i40e_flow_ctrl_set,
496 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
497 .mac_addr_add = i40e_macaddr_add,
498 .mac_addr_remove = i40e_macaddr_remove,
499 .reta_update = i40e_dev_rss_reta_update,
500 .reta_query = i40e_dev_rss_reta_query,
501 .rss_hash_update = i40e_dev_rss_hash_update,
502 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
503 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
504 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
505 .flow_ops_get = i40e_dev_flow_ops_get,
506 .rxq_info_get = i40e_rxq_info_get,
507 .txq_info_get = i40e_txq_info_get,
508 .rx_burst_mode_get = i40e_rx_burst_mode_get,
509 .tx_burst_mode_get = i40e_tx_burst_mode_get,
510 .mirror_rule_set = i40e_mirror_rule_set,
511 .mirror_rule_reset = i40e_mirror_rule_reset,
512 .timesync_enable = i40e_timesync_enable,
513 .timesync_disable = i40e_timesync_disable,
514 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
515 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
516 .get_dcb_info = i40e_dev_get_dcb_info,
517 .timesync_adjust_time = i40e_timesync_adjust_time,
518 .timesync_read_time = i40e_timesync_read_time,
519 .timesync_write_time = i40e_timesync_write_time,
520 .get_reg = i40e_get_regs,
521 .get_eeprom_length = i40e_get_eeprom_length,
522 .get_eeprom = i40e_get_eeprom,
523 .get_module_info = i40e_get_module_info,
524 .get_module_eeprom = i40e_get_module_eeprom,
525 .mac_addr_set = i40e_set_default_mac_addr,
526 .mtu_set = i40e_dev_mtu_set,
527 .tm_ops_get = i40e_tm_ops_get,
528 .tx_done_cleanup = i40e_tx_done_cleanup,
529 .get_monitor_addr = i40e_get_monitor_addr,
532 /* store statistics names and its offset in stats structure */
533 struct rte_i40e_xstats_name_off {
534 char name[RTE_ETH_XSTATS_NAME_SIZE];
538 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
539 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
540 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
541 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
542 {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
543 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
544 rx_unknown_protocol)},
545 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
546 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
547 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
548 {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
551 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
552 sizeof(rte_i40e_stats_strings[0]))
554 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
555 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
556 tx_dropped_link_down)},
557 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
558 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
560 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
561 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
563 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
565 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
567 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
568 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
569 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
570 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
571 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
572 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
574 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
576 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
578 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
580 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
582 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
584 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
586 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
588 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
589 mac_short_packet_dropped)},
590 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
592 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
593 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
594 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
596 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
598 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
600 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
602 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
604 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
606 {"rx_flow_director_atr_match_packets",
607 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
608 {"rx_flow_director_sb_match_packets",
609 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
610 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
612 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
614 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
616 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
620 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
621 sizeof(rte_i40e_hw_port_strings[0]))
623 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
624 {"xon_packets", offsetof(struct i40e_hw_port_stats,
626 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
630 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
631 sizeof(rte_i40e_rxq_prio_strings[0]))
633 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
634 {"xon_packets", offsetof(struct i40e_hw_port_stats,
636 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
638 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
639 priority_xon_2_xoff)},
642 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
643 sizeof(rte_i40e_txq_prio_strings[0]))
646 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
647 struct rte_pci_device *pci_dev)
649 char name[RTE_ETH_NAME_MAX_LEN];
650 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
653 if (pci_dev->device.devargs) {
654 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
660 if (eth_da.nb_representor_ports > 0 &&
661 eth_da.type != RTE_ETH_REPRESENTOR_VF) {
662 PMD_DRV_LOG(ERR, "unsupported representor type: %s\n",
663 pci_dev->device.devargs->args);
667 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
668 sizeof(struct i40e_adapter),
669 eth_dev_pci_specific_init, pci_dev,
670 eth_i40e_dev_init, NULL);
672 if (retval || eth_da.nb_representor_ports < 1)
675 /* probe VF representor ports */
676 struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
677 pci_dev->device.name);
679 if (pf_ethdev == NULL)
682 for (i = 0; i < eth_da.nb_representor_ports; i++) {
683 struct i40e_vf_representor representor = {
684 .vf_id = eth_da.representor_ports[i],
685 .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
686 pf_ethdev->data->dev_private)->switch_domain_id,
687 .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
688 pf_ethdev->data->dev_private)
691 /* representor port net_bdf_port */
692 snprintf(name, sizeof(name), "net_%s_representor_%d",
693 pci_dev->device.name, eth_da.representor_ports[i]);
695 retval = rte_eth_dev_create(&pci_dev->device, name,
696 sizeof(struct i40e_vf_representor), NULL, NULL,
697 i40e_vf_representor_init, &representor);
700 PMD_DRV_LOG(ERR, "failed to create i40e vf "
701 "representor %s.", name);
707 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
709 struct rte_eth_dev *ethdev;
711 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
715 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
716 return rte_eth_dev_pci_generic_remove(pci_dev,
717 i40e_vf_representor_uninit);
719 return rte_eth_dev_pci_generic_remove(pci_dev,
720 eth_i40e_dev_uninit);
723 static struct rte_pci_driver rte_i40e_pmd = {
724 .id_table = pci_id_i40e_map,
725 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
726 .probe = eth_i40e_pci_probe,
727 .remove = eth_i40e_pci_remove,
731 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
734 uint32_t ori_reg_val;
735 struct rte_eth_dev *dev;
737 ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
738 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
739 i40e_write_rx_ctl(hw, reg_addr, reg_val);
740 if (ori_reg_val != reg_val)
742 "i40e device %s changed global register [0x%08x]."
743 " original: 0x%08x, new: 0x%08x",
744 dev->device->name, reg_addr, ori_reg_val, reg_val);
747 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
748 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
749 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
751 #ifndef I40E_GLQF_ORT
752 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
754 #ifndef I40E_GLQF_PIT
755 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
757 #ifndef I40E_GLQF_L3_MAP
758 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
761 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
764 * Initialize registers for parsing packet type of QinQ
765 * This should be removed from code once proper
766 * configuration API is added to avoid configuration conflicts
767 * between ports of the same device.
769 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
770 I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
773 static inline void i40e_config_automask(struct i40e_pf *pf)
775 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
778 /* INTENA flag is not auto-cleared for interrupt */
779 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
780 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
781 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
783 /* If support multi-driver, PF will use INT0. */
784 if (!pf->support_multi_driver)
785 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
787 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
790 static inline void i40e_clear_automask(struct i40e_pf *pf)
792 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
795 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
796 val &= ~(I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
797 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK);
799 if (!pf->support_multi_driver)
800 val &= ~I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
802 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
805 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
808 * Add a ethertype filter to drop all flow control frames transmitted
812 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
814 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
815 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
816 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
817 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
820 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
821 I40E_FLOW_CONTROL_ETHERTYPE, flags,
822 pf->main_vsi_seid, 0,
826 "Failed to add filter to drop flow control frames from VSIs.");
830 floating_veb_list_handler(__rte_unused const char *key,
831 const char *floating_veb_value,
835 unsigned int count = 0;
838 bool *vf_floating_veb = opaque;
840 while (isblank(*floating_veb_value))
841 floating_veb_value++;
843 /* Reset floating VEB configuration for VFs */
844 for (idx = 0; idx < I40E_MAX_VF; idx++)
845 vf_floating_veb[idx] = false;
849 while (isblank(*floating_veb_value))
850 floating_veb_value++;
851 if (*floating_veb_value == '\0')
854 idx = strtoul(floating_veb_value, &end, 10);
855 if (errno || end == NULL)
859 while (isblank(*end))
863 } else if ((*end == ';') || (*end == '\0')) {
865 if (min == I40E_MAX_VF)
867 if (max >= I40E_MAX_VF)
868 max = I40E_MAX_VF - 1;
869 for (idx = min; idx <= max; idx++) {
870 vf_floating_veb[idx] = true;
877 floating_veb_value = end + 1;
878 } while (*end != '\0');
887 config_vf_floating_veb(struct rte_devargs *devargs,
888 uint16_t floating_veb,
889 bool *vf_floating_veb)
891 struct rte_kvargs *kvlist;
893 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
897 /* All the VFs attach to the floating VEB by default
898 * when the floating VEB is enabled.
900 for (i = 0; i < I40E_MAX_VF; i++)
901 vf_floating_veb[i] = true;
906 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
910 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
911 rte_kvargs_free(kvlist);
914 /* When the floating_veb_list parameter exists, all the VFs
915 * will attach to the legacy VEB firstly, then configure VFs
916 * to the floating VEB according to the floating_veb_list.
918 if (rte_kvargs_process(kvlist, floating_veb_list,
919 floating_veb_list_handler,
920 vf_floating_veb) < 0) {
921 rte_kvargs_free(kvlist);
924 rte_kvargs_free(kvlist);
928 i40e_check_floating_handler(__rte_unused const char *key,
930 __rte_unused void *opaque)
932 if (strcmp(value, "1"))
939 is_floating_veb_supported(struct rte_devargs *devargs)
941 struct rte_kvargs *kvlist;
942 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
947 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
951 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
952 rte_kvargs_free(kvlist);
955 /* Floating VEB is enabled when there's key-value:
956 * enable_floating_veb=1
958 if (rte_kvargs_process(kvlist, floating_veb_key,
959 i40e_check_floating_handler, NULL) < 0) {
960 rte_kvargs_free(kvlist);
963 rte_kvargs_free(kvlist);
969 config_floating_veb(struct rte_eth_dev *dev)
971 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
972 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
973 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
975 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
977 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
979 is_floating_veb_supported(pci_dev->device.devargs);
980 config_vf_floating_veb(pci_dev->device.devargs,
982 pf->floating_veb_list);
984 pf->floating_veb = false;
988 #define I40E_L2_TAGS_S_TAG_SHIFT 1
989 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
992 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
994 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
995 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
996 char ethertype_hash_name[RTE_HASH_NAMESIZE];
999 struct rte_hash_parameters ethertype_hash_params = {
1000 .name = ethertype_hash_name,
1001 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
1002 .key_len = sizeof(struct i40e_ethertype_filter_input),
1003 .hash_func = rte_hash_crc,
1004 .hash_func_init_val = 0,
1005 .socket_id = rte_socket_id(),
1008 /* Initialize ethertype filter rule list and hash */
1009 TAILQ_INIT(ðertype_rule->ethertype_list);
1010 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
1011 "ethertype_%s", dev->device->name);
1012 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
1013 if (!ethertype_rule->hash_table) {
1014 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
1017 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
1018 sizeof(struct i40e_ethertype_filter *) *
1019 I40E_MAX_ETHERTYPE_FILTER_NUM,
1021 if (!ethertype_rule->hash_map) {
1023 "Failed to allocate memory for ethertype hash map!");
1025 goto err_ethertype_hash_map_alloc;
1030 err_ethertype_hash_map_alloc:
1031 rte_hash_free(ethertype_rule->hash_table);
1037 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
1039 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1040 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
1041 char tunnel_hash_name[RTE_HASH_NAMESIZE];
1044 struct rte_hash_parameters tunnel_hash_params = {
1045 .name = tunnel_hash_name,
1046 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1047 .key_len = sizeof(struct i40e_tunnel_filter_input),
1048 .hash_func = rte_hash_crc,
1049 .hash_func_init_val = 0,
1050 .socket_id = rte_socket_id(),
1053 /* Initialize tunnel filter rule list and hash */
1054 TAILQ_INIT(&tunnel_rule->tunnel_list);
1055 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1056 "tunnel_%s", dev->device->name);
1057 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1058 if (!tunnel_rule->hash_table) {
1059 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1062 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1063 sizeof(struct i40e_tunnel_filter *) *
1064 I40E_MAX_TUNNEL_FILTER_NUM,
1066 if (!tunnel_rule->hash_map) {
1068 "Failed to allocate memory for tunnel hash map!");
1070 goto err_tunnel_hash_map_alloc;
1075 err_tunnel_hash_map_alloc:
1076 rte_hash_free(tunnel_rule->hash_table);
1082 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1084 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1085 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1086 struct i40e_fdir_info *fdir_info = &pf->fdir;
1087 char fdir_hash_name[RTE_HASH_NAMESIZE];
1088 uint32_t alloc = hw->func_caps.fd_filters_guaranteed;
1089 uint32_t best = hw->func_caps.fd_filters_best_effort;
1090 struct rte_bitmap *bmp = NULL;
1096 struct rte_hash_parameters fdir_hash_params = {
1097 .name = fdir_hash_name,
1098 .entries = I40E_MAX_FDIR_FILTER_NUM,
1099 .key_len = sizeof(struct i40e_fdir_input),
1100 .hash_func = rte_hash_crc,
1101 .hash_func_init_val = 0,
1102 .socket_id = rte_socket_id(),
1105 /* Initialize flow director filter rule list and hash */
1106 TAILQ_INIT(&fdir_info->fdir_list);
1107 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1108 "fdir_%s", dev->device->name);
1109 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1110 if (!fdir_info->hash_table) {
1111 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1115 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1116 sizeof(struct i40e_fdir_filter *) *
1117 I40E_MAX_FDIR_FILTER_NUM,
1119 if (!fdir_info->hash_map) {
1121 "Failed to allocate memory for fdir hash map!");
1123 goto err_fdir_hash_map_alloc;
1126 fdir_info->fdir_filter_array = rte_zmalloc("fdir_filter",
1127 sizeof(struct i40e_fdir_filter) *
1128 I40E_MAX_FDIR_FILTER_NUM,
1131 if (!fdir_info->fdir_filter_array) {
1133 "Failed to allocate memory for fdir filter array!");
1135 goto err_fdir_filter_array_alloc;
1138 fdir_info->fdir_space_size = alloc + best;
1139 fdir_info->fdir_actual_cnt = 0;
1140 fdir_info->fdir_guarantee_total_space = alloc;
1141 fdir_info->fdir_guarantee_free_space =
1142 fdir_info->fdir_guarantee_total_space;
1144 PMD_DRV_LOG(INFO, "FDIR guarantee space: %u, best_effort space %u.", alloc, best);
1146 fdir_info->fdir_flow_pool.pool =
1147 rte_zmalloc("i40e_fdir_entry",
1148 sizeof(struct i40e_fdir_entry) *
1149 fdir_info->fdir_space_size,
1152 if (!fdir_info->fdir_flow_pool.pool) {
1154 "Failed to allocate memory for bitmap flow!");
1156 goto err_fdir_bitmap_flow_alloc;
1159 for (i = 0; i < fdir_info->fdir_space_size; i++)
1160 fdir_info->fdir_flow_pool.pool[i].idx = i;
1163 rte_bitmap_get_memory_footprint(fdir_info->fdir_space_size);
1164 mem = rte_zmalloc("fdir_bmap", bmp_size, RTE_CACHE_LINE_SIZE);
1167 "Failed to allocate memory for fdir bitmap!");
1169 goto err_fdir_mem_alloc;
1171 bmp = rte_bitmap_init(fdir_info->fdir_space_size, mem, bmp_size);
1174 "Failed to initialization fdir bitmap!");
1176 goto err_fdir_bmp_alloc;
1178 for (i = 0; i < fdir_info->fdir_space_size; i++)
1179 rte_bitmap_set(bmp, i);
1181 fdir_info->fdir_flow_pool.bitmap = bmp;
1188 rte_free(fdir_info->fdir_flow_pool.pool);
1189 err_fdir_bitmap_flow_alloc:
1190 rte_free(fdir_info->fdir_filter_array);
1191 err_fdir_filter_array_alloc:
1192 rte_free(fdir_info->hash_map);
1193 err_fdir_hash_map_alloc:
1194 rte_hash_free(fdir_info->hash_table);
1200 i40e_init_customized_info(struct i40e_pf *pf)
1204 /* Initialize customized pctype */
1205 for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1206 pf->customized_pctype[i].index = i;
1207 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1208 pf->customized_pctype[i].valid = false;
1211 pf->gtp_support = false;
1212 pf->esp_support = false;
1216 i40e_init_filter_invalidation(struct i40e_pf *pf)
1218 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1219 struct i40e_fdir_info *fdir_info = &pf->fdir;
1220 uint32_t glqf_ctl_reg = 0;
1222 glqf_ctl_reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
1223 if (!pf->support_multi_driver) {
1224 fdir_info->fdir_invalprio = 1;
1225 glqf_ctl_reg |= I40E_GLQF_CTL_INVALPRIO_MASK;
1226 PMD_DRV_LOG(INFO, "FDIR INVALPRIO set to guaranteed first");
1227 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, glqf_ctl_reg);
1229 if (glqf_ctl_reg & I40E_GLQF_CTL_INVALPRIO_MASK) {
1230 fdir_info->fdir_invalprio = 1;
1231 PMD_DRV_LOG(INFO, "FDIR INVALPRIO is: guaranteed first");
1233 fdir_info->fdir_invalprio = 0;
1234 PMD_DRV_LOG(INFO, "FDIR INVALPRIO is: shared first");
1240 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1242 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1243 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1244 struct i40e_queue_regions *info = &pf->queue_region;
1247 for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1248 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1250 memset(info, 0, sizeof(struct i40e_queue_regions));
1254 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1259 unsigned long support_multi_driver;
1262 pf = (struct i40e_pf *)opaque;
1265 support_multi_driver = strtoul(value, &end, 10);
1266 if (errno != 0 || end == value || *end != 0) {
1267 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1271 if (support_multi_driver == 1 || support_multi_driver == 0)
1272 pf->support_multi_driver = (bool)support_multi_driver;
1274 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1275 "enable global configuration by default."
1276 ETH_I40E_SUPPORT_MULTI_DRIVER);
1281 i40e_support_multi_driver(struct rte_eth_dev *dev)
1283 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1284 struct rte_kvargs *kvlist;
1287 /* Enable global configuration by default */
1288 pf->support_multi_driver = false;
1290 if (!dev->device->devargs)
1293 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1297 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1298 if (!kvargs_count) {
1299 rte_kvargs_free(kvlist);
1303 if (kvargs_count > 1)
1304 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1305 "the first invalid or last valid one is used !",
1306 ETH_I40E_SUPPORT_MULTI_DRIVER);
1308 if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1309 i40e_parse_multi_drv_handler, pf) < 0) {
1310 rte_kvargs_free(kvlist);
1314 rte_kvargs_free(kvlist);
1319 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1320 uint32_t reg_addr, uint64_t reg_val,
1321 struct i40e_asq_cmd_details *cmd_details)
1323 uint64_t ori_reg_val;
1324 struct rte_eth_dev *dev;
1327 ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1328 if (ret != I40E_SUCCESS) {
1330 "Fail to debug read from 0x%08x",
1334 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1336 if (ori_reg_val != reg_val)
1337 PMD_DRV_LOG(WARNING,
1338 "i40e device %s changed global register [0x%08x]."
1339 " original: 0x%"PRIx64", after: 0x%"PRIx64,
1340 dev->device->name, reg_addr, ori_reg_val, reg_val);
1342 return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1346 read_vf_msg_config(__rte_unused const char *key,
1350 struct i40e_vf_msg_cfg *cfg = opaque;
1352 if (sscanf(value, "%u@%u:%u", &cfg->max_msg, &cfg->period,
1353 &cfg->ignore_second) != 3) {
1354 memset(cfg, 0, sizeof(*cfg));
1355 PMD_DRV_LOG(ERR, "format error! example: "
1356 "%s=60@120:180", ETH_I40E_VF_MSG_CFG);
1361 * If the message validation function been enabled, the 'period'
1362 * and 'ignore_second' must greater than 0.
1364 if (cfg->max_msg && (!cfg->period || !cfg->ignore_second)) {
1365 memset(cfg, 0, sizeof(*cfg));
1366 PMD_DRV_LOG(ERR, "%s error! the second and third"
1367 " number must be greater than 0!",
1368 ETH_I40E_VF_MSG_CFG);
1376 i40e_parse_vf_msg_config(struct rte_eth_dev *dev,
1377 struct i40e_vf_msg_cfg *msg_cfg)
1379 struct rte_kvargs *kvlist;
1383 memset(msg_cfg, 0, sizeof(*msg_cfg));
1385 if (!dev->device->devargs)
1388 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1392 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_VF_MSG_CFG);
1396 if (kvargs_count > 1) {
1397 PMD_DRV_LOG(ERR, "More than one argument \"%s\"!",
1398 ETH_I40E_VF_MSG_CFG);
1403 if (rte_kvargs_process(kvlist, ETH_I40E_VF_MSG_CFG,
1404 read_vf_msg_config, msg_cfg) < 0)
1408 rte_kvargs_free(kvlist);
1412 #define I40E_ALARM_INTERVAL 50000 /* us */
1415 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1417 struct rte_pci_device *pci_dev;
1418 struct rte_intr_handle *intr_handle;
1419 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1420 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1421 struct i40e_vsi *vsi;
1424 uint8_t aq_fail = 0;
1426 PMD_INIT_FUNC_TRACE();
1428 dev->dev_ops = &i40e_eth_dev_ops;
1429 dev->rx_queue_count = i40e_dev_rx_queue_count;
1430 dev->rx_descriptor_done = i40e_dev_rx_descriptor_done;
1431 dev->rx_descriptor_status = i40e_dev_rx_descriptor_status;
1432 dev->tx_descriptor_status = i40e_dev_tx_descriptor_status;
1433 dev->rx_pkt_burst = i40e_recv_pkts;
1434 dev->tx_pkt_burst = i40e_xmit_pkts;
1435 dev->tx_pkt_prepare = i40e_prep_pkts;
1437 /* for secondary processes, we don't initialise any further as primary
1438 * has already done this work. Only check we don't need a different
1440 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1441 i40e_set_rx_function(dev);
1442 i40e_set_tx_function(dev);
1445 i40e_set_default_ptype_table(dev);
1446 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1447 intr_handle = &pci_dev->intr_handle;
1449 rte_eth_copy_pci_info(dev, pci_dev);
1450 dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1452 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1453 pf->adapter->eth_dev = dev;
1454 pf->dev_data = dev->data;
1456 hw->back = I40E_PF_TO_ADAPTER(pf);
1457 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1460 "Hardware is not available, as address is NULL");
1464 hw->vendor_id = pci_dev->id.vendor_id;
1465 hw->device_id = pci_dev->id.device_id;
1466 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1467 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1468 hw->bus.device = pci_dev->addr.devid;
1469 hw->bus.func = pci_dev->addr.function;
1470 hw->adapter_stopped = 0;
1471 hw->adapter_closed = 0;
1473 /* Init switch device pointer */
1474 hw->switch_dev = NULL;
1477 * Switch Tag value should not be identical to either the First Tag
1478 * or Second Tag values. So set something other than common Ethertype
1479 * for internal switching.
1481 hw->switch_tag = 0xffff;
1483 val = I40E_READ_REG(hw, I40E_GL_FWSTS);
1484 if (val & I40E_GL_FWSTS_FWS1B_MASK) {
1485 PMD_INIT_LOG(ERR, "\nERROR: "
1486 "Firmware recovery mode detected. Limiting functionality.\n"
1487 "Refer to the Intel(R) Ethernet Adapters and Devices "
1488 "User Guide for details on firmware recovery mode.");
1492 i40e_parse_vf_msg_config(dev, &pf->vf_msg_cfg);
1493 /* Check if need to support multi-driver */
1494 i40e_support_multi_driver(dev);
1496 /* Make sure all is clean before doing PF reset */
1499 /* Reset here to make sure all is clean for each PF */
1500 ret = i40e_pf_reset(hw);
1502 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1506 /* Initialize the shared code (base driver) */
1507 ret = i40e_init_shared_code(hw);
1509 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1513 /* Initialize the parameters for adminq */
1514 i40e_init_adminq_parameter(hw);
1515 ret = i40e_init_adminq(hw);
1516 if (ret != I40E_SUCCESS) {
1517 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1520 /* Firmware of SFP x722 does not support 802.1ad frames ability */
1521 if (hw->device_id == I40E_DEV_ID_SFP_X722 ||
1522 hw->device_id == I40E_DEV_ID_SFP_I_X722)
1523 hw->flags &= ~I40E_HW_FLAG_802_1AD_CAPABLE;
1525 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1526 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1527 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1528 ((hw->nvm.version >> 12) & 0xf),
1529 ((hw->nvm.version >> 4) & 0xff),
1530 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1532 /* Initialize the hardware */
1535 i40e_config_automask(pf);
1537 i40e_set_default_pctype_table(dev);
1540 * To work around the NVM issue, initialize registers
1541 * for packet type of QinQ by software.
1542 * It should be removed once issues are fixed in NVM.
1544 if (!pf->support_multi_driver)
1545 i40e_GLQF_reg_init(hw);
1547 /* Initialize the input set for filters (hash and fd) to default value */
1548 i40e_filter_input_set_init(pf);
1550 /* initialise the L3_MAP register */
1551 if (!pf->support_multi_driver) {
1552 ret = i40e_aq_debug_write_global_register(hw,
1553 I40E_GLQF_L3_MAP(40),
1556 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1559 "Global register 0x%08x is changed with 0x28",
1560 I40E_GLQF_L3_MAP(40));
1563 /* Need the special FW version to support floating VEB */
1564 config_floating_veb(dev);
1565 /* Clear PXE mode */
1566 i40e_clear_pxe_mode(hw);
1567 i40e_dev_sync_phy_type(hw);
1570 * On X710, performance number is far from the expectation on recent
1571 * firmware versions. The fix for this issue may not be integrated in
1572 * the following firmware version. So the workaround in software driver
1573 * is needed. It needs to modify the initial values of 3 internal only
1574 * registers. Note that the workaround can be removed when it is fixed
1575 * in firmware in the future.
1577 i40e_configure_registers(hw);
1579 /* Get hw capabilities */
1580 ret = i40e_get_cap(hw);
1581 if (ret != I40E_SUCCESS) {
1582 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1583 goto err_get_capabilities;
1586 /* Initialize parameters for PF */
1587 ret = i40e_pf_parameter_init(dev);
1589 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1590 goto err_parameter_init;
1593 /* Initialize the queue management */
1594 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1596 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1597 goto err_qp_pool_init;
1599 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1600 hw->func_caps.num_msix_vectors - 1);
1602 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1603 goto err_msix_pool_init;
1606 /* Initialize lan hmc */
1607 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1608 hw->func_caps.num_rx_qp, 0, 0);
1609 if (ret != I40E_SUCCESS) {
1610 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1611 goto err_init_lan_hmc;
1614 /* Configure lan hmc */
1615 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1616 if (ret != I40E_SUCCESS) {
1617 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1618 goto err_configure_lan_hmc;
1621 /* Get and check the mac address */
1622 i40e_get_mac_addr(hw, hw->mac.addr);
1623 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1624 PMD_INIT_LOG(ERR, "mac address is not valid");
1626 goto err_get_mac_addr;
1628 /* Copy the permanent MAC address */
1629 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1630 (struct rte_ether_addr *)hw->mac.perm_addr);
1632 /* Disable flow control */
1633 hw->fc.requested_mode = I40E_FC_NONE;
1634 i40e_set_fc(hw, &aq_fail, TRUE);
1636 /* Set the global registers with default ether type value */
1637 if (!pf->support_multi_driver) {
1638 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1639 RTE_ETHER_TYPE_VLAN);
1640 if (ret != I40E_SUCCESS) {
1642 "Failed to set the default outer "
1644 goto err_setup_pf_switch;
1648 /* PF setup, which includes VSI setup */
1649 ret = i40e_pf_setup(pf);
1651 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1652 goto err_setup_pf_switch;
1657 /* Disable double vlan by default */
1658 i40e_vsi_config_double_vlan(vsi, FALSE);
1660 /* Disable S-TAG identification when floating_veb is disabled */
1661 if (!pf->floating_veb) {
1662 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1663 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1664 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1665 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1669 if (!vsi->max_macaddrs)
1670 len = RTE_ETHER_ADDR_LEN;
1672 len = RTE_ETHER_ADDR_LEN * vsi->max_macaddrs;
1674 /* Should be after VSI initialized */
1675 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1676 if (!dev->data->mac_addrs) {
1678 "Failed to allocated memory for storing mac address");
1681 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1682 &dev->data->mac_addrs[0]);
1684 /* Init dcb to sw mode by default */
1685 ret = i40e_dcb_init_configure(dev, TRUE);
1686 if (ret != I40E_SUCCESS) {
1687 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1688 pf->flags &= ~I40E_FLAG_DCB;
1690 /* Update HW struct after DCB configuration */
1693 /* initialize pf host driver to setup SRIOV resource if applicable */
1694 i40e_pf_host_init(dev);
1696 /* register callback func to eal lib */
1697 rte_intr_callback_register(intr_handle,
1698 i40e_dev_interrupt_handler, dev);
1700 /* configure and enable device interrupt */
1701 i40e_pf_config_irq0(hw, TRUE);
1702 i40e_pf_enable_irq0(hw);
1704 /* enable uio intr after callback register */
1705 rte_intr_enable(intr_handle);
1707 /* By default disable flexible payload in global configuration */
1708 if (!pf->support_multi_driver)
1709 i40e_flex_payload_reg_set_default(hw);
1712 * Add an ethertype filter to drop all flow control frames transmitted
1713 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1716 i40e_add_tx_flow_control_drop_filter(pf);
1718 /* Set the max frame size to 0x2600 by default,
1719 * in case other drivers changed the default value.
1721 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, false, 0, NULL);
1723 /* initialize mirror rule list */
1724 TAILQ_INIT(&pf->mirror_list);
1726 /* initialize RSS rule list */
1727 TAILQ_INIT(&pf->rss_config_list);
1729 /* initialize Traffic Manager configuration */
1730 i40e_tm_conf_init(dev);
1732 /* Initialize customized information */
1733 i40e_init_customized_info(pf);
1735 /* Initialize the filter invalidation configuration */
1736 i40e_init_filter_invalidation(pf);
1738 ret = i40e_init_ethtype_filter_list(dev);
1740 goto err_init_ethtype_filter_list;
1741 ret = i40e_init_tunnel_filter_list(dev);
1743 goto err_init_tunnel_filter_list;
1744 ret = i40e_init_fdir_filter_list(dev);
1746 goto err_init_fdir_filter_list;
1748 /* initialize queue region configuration */
1749 i40e_init_queue_region_conf(dev);
1751 /* reset all stats of the device, including pf and main vsi */
1752 i40e_dev_stats_reset(dev);
1756 err_init_fdir_filter_list:
1757 rte_free(pf->tunnel.hash_table);
1758 rte_free(pf->tunnel.hash_map);
1759 err_init_tunnel_filter_list:
1760 rte_free(pf->ethertype.hash_table);
1761 rte_free(pf->ethertype.hash_map);
1762 err_init_ethtype_filter_list:
1763 rte_free(dev->data->mac_addrs);
1764 dev->data->mac_addrs = NULL;
1766 i40e_vsi_release(pf->main_vsi);
1767 err_setup_pf_switch:
1769 err_configure_lan_hmc:
1770 (void)i40e_shutdown_lan_hmc(hw);
1772 i40e_res_pool_destroy(&pf->msix_pool);
1774 i40e_res_pool_destroy(&pf->qp_pool);
1777 err_get_capabilities:
1778 (void)i40e_shutdown_adminq(hw);
1784 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1786 struct i40e_ethertype_filter *p_ethertype;
1787 struct i40e_ethertype_rule *ethertype_rule;
1789 ethertype_rule = &pf->ethertype;
1790 /* Remove all ethertype filter rules and hash */
1791 if (ethertype_rule->hash_map)
1792 rte_free(ethertype_rule->hash_map);
1793 if (ethertype_rule->hash_table)
1794 rte_hash_free(ethertype_rule->hash_table);
1796 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1797 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1798 p_ethertype, rules);
1799 rte_free(p_ethertype);
1804 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1806 struct i40e_tunnel_filter *p_tunnel;
1807 struct i40e_tunnel_rule *tunnel_rule;
1809 tunnel_rule = &pf->tunnel;
1810 /* Remove all tunnel director rules and hash */
1811 if (tunnel_rule->hash_map)
1812 rte_free(tunnel_rule->hash_map);
1813 if (tunnel_rule->hash_table)
1814 rte_hash_free(tunnel_rule->hash_table);
1816 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1817 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1823 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1825 struct i40e_fdir_filter *p_fdir;
1826 struct i40e_fdir_info *fdir_info;
1828 fdir_info = &pf->fdir;
1830 /* Remove all flow director rules */
1831 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list)))
1832 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1836 i40e_fdir_memory_cleanup(struct i40e_pf *pf)
1838 struct i40e_fdir_info *fdir_info;
1840 fdir_info = &pf->fdir;
1842 /* flow director memory cleanup */
1843 if (fdir_info->hash_map)
1844 rte_free(fdir_info->hash_map);
1845 if (fdir_info->hash_table)
1846 rte_hash_free(fdir_info->hash_table);
1847 if (fdir_info->fdir_flow_pool.bitmap)
1848 rte_free(fdir_info->fdir_flow_pool.bitmap);
1849 if (fdir_info->fdir_flow_pool.pool)
1850 rte_free(fdir_info->fdir_flow_pool.pool);
1851 if (fdir_info->fdir_filter_array)
1852 rte_free(fdir_info->fdir_filter_array);
1855 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1858 * Disable by default flexible payload
1859 * for corresponding L2/L3/L4 layers.
1861 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1862 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1863 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1867 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1871 PMD_INIT_FUNC_TRACE();
1873 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1876 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1878 if (hw->adapter_closed == 0)
1879 i40e_dev_close(dev);
1885 i40e_dev_configure(struct rte_eth_dev *dev)
1887 struct i40e_adapter *ad =
1888 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1889 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1890 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1891 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1894 ret = i40e_dev_sync_phy_type(hw);
1898 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1899 * bulk allocation or vector Rx preconditions we will reset it.
1901 ad->rx_bulk_alloc_allowed = true;
1902 ad->rx_vec_allowed = true;
1903 ad->tx_simple_allowed = true;
1904 ad->tx_vec_allowed = true;
1906 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1907 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1909 /* Only legacy filter API needs the following fdir config. So when the
1910 * legacy filter API is deprecated, the following codes should also be
1913 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1914 ret = i40e_fdir_setup(pf);
1915 if (ret != I40E_SUCCESS) {
1916 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1919 ret = i40e_fdir_configure(dev);
1921 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1925 i40e_fdir_teardown(pf);
1927 ret = i40e_dev_init_vlan(dev);
1932 * General PMD driver call sequence are NIC init, configure,
1933 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1934 * will try to lookup the VSI that specific queue belongs to if VMDQ
1935 * applicable. So, VMDQ setting has to be done before
1936 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1937 * For RSS setting, it will try to calculate actual configured RX queue
1938 * number, which will be available after rx_queue_setup(). dev_start()
1939 * function is good to place RSS setup.
1941 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1942 ret = i40e_vmdq_setup(dev);
1947 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1948 ret = i40e_dcb_setup(dev);
1950 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1955 TAILQ_INIT(&pf->flow_list);
1960 /* need to release vmdq resource if exists */
1961 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1962 i40e_vsi_release(pf->vmdq[i].vsi);
1963 pf->vmdq[i].vsi = NULL;
1968 /* Need to release fdir resource if exists.
1969 * Only legacy filter API needs the following fdir config. So when the
1970 * legacy filter API is deprecated, the following code should also be
1973 i40e_fdir_teardown(pf);
1978 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1980 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1981 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1982 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1983 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1984 uint16_t msix_vect = vsi->msix_intr;
1987 for (i = 0; i < vsi->nb_qps; i++) {
1988 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1989 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1993 if (vsi->type != I40E_VSI_SRIOV) {
1994 if (!rte_intr_allow_others(intr_handle)) {
1995 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1996 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1998 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
2001 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
2002 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
2004 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
2009 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
2010 vsi->user_param + (msix_vect - 1);
2012 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
2013 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
2015 I40E_WRITE_FLUSH(hw);
2019 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
2020 int base_queue, int nb_queue,
2025 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2026 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2028 /* Bind all RX queues to allocated MSIX interrupt */
2029 for (i = 0; i < nb_queue; i++) {
2030 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2031 itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
2032 ((base_queue + i + 1) <<
2033 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
2034 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
2035 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
2037 if (i == nb_queue - 1)
2038 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
2039 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
2042 /* Write first RX queue to Link list register as the head element */
2043 if (vsi->type != I40E_VSI_SRIOV) {
2045 i40e_calc_itr_interval(1, pf->support_multi_driver);
2047 if (msix_vect == I40E_MISC_VEC_ID) {
2048 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
2050 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
2052 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
2054 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
2057 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
2059 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
2061 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2063 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
2070 if (msix_vect == I40E_MISC_VEC_ID) {
2072 I40E_VPINT_LNKLST0(vsi->user_param),
2074 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
2076 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
2078 /* num_msix_vectors_vf needs to minus irq0 */
2079 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
2080 vsi->user_param + (msix_vect - 1);
2082 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
2084 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
2086 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2090 I40E_WRITE_FLUSH(hw);
2094 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
2096 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2097 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2098 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2099 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2100 uint16_t msix_vect = vsi->msix_intr;
2101 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2102 uint16_t queue_idx = 0;
2106 for (i = 0; i < vsi->nb_qps; i++) {
2107 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
2108 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2111 /* VF bind interrupt */
2112 if (vsi->type == I40E_VSI_SRIOV) {
2113 if (vsi->nb_msix == 0) {
2114 PMD_DRV_LOG(ERR, "No msix resource");
2117 __vsi_queues_bind_intr(vsi, msix_vect,
2118 vsi->base_queue, vsi->nb_qps,
2123 /* PF & VMDq bind interrupt */
2124 if (rte_intr_dp_is_en(intr_handle)) {
2125 if (vsi->type == I40E_VSI_MAIN) {
2128 } else if (vsi->type == I40E_VSI_VMDQ2) {
2129 struct i40e_vsi *main_vsi =
2130 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2131 queue_idx = vsi->base_queue - main_vsi->nb_qps;
2136 for (i = 0; i < vsi->nb_used_qps; i++) {
2137 if (vsi->nb_msix == 0) {
2138 PMD_DRV_LOG(ERR, "No msix resource");
2140 } else if (nb_msix <= 1) {
2141 if (!rte_intr_allow_others(intr_handle))
2142 /* allow to share MISC_VEC_ID */
2143 msix_vect = I40E_MISC_VEC_ID;
2145 /* no enough msix_vect, map all to one */
2146 __vsi_queues_bind_intr(vsi, msix_vect,
2147 vsi->base_queue + i,
2148 vsi->nb_used_qps - i,
2150 for (; !!record && i < vsi->nb_used_qps; i++)
2151 intr_handle->intr_vec[queue_idx + i] =
2155 /* 1:1 queue/msix_vect mapping */
2156 __vsi_queues_bind_intr(vsi, msix_vect,
2157 vsi->base_queue + i, 1,
2160 intr_handle->intr_vec[queue_idx + i] = msix_vect;
2170 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2172 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2173 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2174 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2175 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2176 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2177 uint16_t msix_intr, i;
2179 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2180 for (i = 0; i < vsi->nb_msix; i++) {
2181 msix_intr = vsi->msix_intr + i;
2182 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2183 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2184 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2185 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2188 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2189 I40E_PFINT_DYN_CTL0_INTENA_MASK |
2190 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2191 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2193 I40E_WRITE_FLUSH(hw);
2197 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2199 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2200 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2201 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2202 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2203 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2204 uint16_t msix_intr, i;
2206 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2207 for (i = 0; i < vsi->nb_msix; i++) {
2208 msix_intr = vsi->msix_intr + i;
2209 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2210 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2213 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2214 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2216 I40E_WRITE_FLUSH(hw);
2219 static inline uint8_t
2220 i40e_parse_link_speeds(uint16_t link_speeds)
2222 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2224 if (link_speeds & ETH_LINK_SPEED_40G)
2225 link_speed |= I40E_LINK_SPEED_40GB;
2226 if (link_speeds & ETH_LINK_SPEED_25G)
2227 link_speed |= I40E_LINK_SPEED_25GB;
2228 if (link_speeds & ETH_LINK_SPEED_20G)
2229 link_speed |= I40E_LINK_SPEED_20GB;
2230 if (link_speeds & ETH_LINK_SPEED_10G)
2231 link_speed |= I40E_LINK_SPEED_10GB;
2232 if (link_speeds & ETH_LINK_SPEED_1G)
2233 link_speed |= I40E_LINK_SPEED_1GB;
2234 if (link_speeds & ETH_LINK_SPEED_100M)
2235 link_speed |= I40E_LINK_SPEED_100MB;
2241 i40e_phy_conf_link(struct i40e_hw *hw,
2243 uint8_t force_speed,
2246 enum i40e_status_code status;
2247 struct i40e_aq_get_phy_abilities_resp phy_ab;
2248 struct i40e_aq_set_phy_config phy_conf;
2249 enum i40e_aq_phy_type cnt;
2250 uint8_t avail_speed;
2251 uint32_t phy_type_mask = 0;
2253 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2254 I40E_AQ_PHY_FLAG_PAUSE_RX |
2255 I40E_AQ_PHY_FLAG_PAUSE_RX |
2256 I40E_AQ_PHY_FLAG_LOW_POWER;
2259 /* To get phy capabilities of available speeds. */
2260 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2263 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2267 avail_speed = phy_ab.link_speed;
2269 /* To get the current phy config. */
2270 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2273 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2278 /* If link needs to go up and it is in autoneg mode the speed is OK,
2279 * no need to set up again.
2281 if (is_up && phy_ab.phy_type != 0 &&
2282 abilities & I40E_AQ_PHY_AN_ENABLED &&
2283 phy_ab.link_speed != 0)
2284 return I40E_SUCCESS;
2286 memset(&phy_conf, 0, sizeof(phy_conf));
2288 /* bits 0-2 use the values from get_phy_abilities_resp */
2290 abilities |= phy_ab.abilities & mask;
2292 phy_conf.abilities = abilities;
2294 /* If link needs to go up, but the force speed is not supported,
2295 * Warn users and config the default available speeds.
2297 if (is_up && !(force_speed & avail_speed)) {
2298 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2299 phy_conf.link_speed = avail_speed;
2301 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2304 /* PHY type mask needs to include each type except PHY type extension */
2305 for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2306 phy_type_mask |= 1 << cnt;
2308 /* use get_phy_abilities_resp value for the rest */
2309 phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2310 phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2311 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2312 I40E_AQ_PHY_TYPE_EXT_25G_LR | I40E_AQ_PHY_TYPE_EXT_25G_AOC |
2313 I40E_AQ_PHY_TYPE_EXT_25G_ACC) : 0;
2314 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2315 phy_conf.eee_capability = phy_ab.eee_capability;
2316 phy_conf.eeer = phy_ab.eeer_val;
2317 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2319 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2320 phy_ab.abilities, phy_ab.link_speed);
2321 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
2322 phy_conf.abilities, phy_conf.link_speed);
2324 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2328 return I40E_SUCCESS;
2332 i40e_apply_link_speed(struct rte_eth_dev *dev)
2335 uint8_t abilities = 0;
2336 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2337 struct rte_eth_conf *conf = &dev->data->dev_conf;
2339 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2340 I40E_AQ_PHY_LINK_ENABLED;
2342 if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2343 conf->link_speeds = ETH_LINK_SPEED_40G |
2344 ETH_LINK_SPEED_25G |
2345 ETH_LINK_SPEED_20G |
2346 ETH_LINK_SPEED_10G |
2348 ETH_LINK_SPEED_100M;
2350 abilities |= I40E_AQ_PHY_AN_ENABLED;
2352 abilities &= ~I40E_AQ_PHY_AN_ENABLED;
2354 speed = i40e_parse_link_speeds(conf->link_speeds);
2356 return i40e_phy_conf_link(hw, abilities, speed, true);
2360 i40e_dev_start(struct rte_eth_dev *dev)
2362 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2363 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2364 struct i40e_vsi *main_vsi = pf->main_vsi;
2366 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2367 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2368 uint32_t intr_vector = 0;
2369 struct i40e_vsi *vsi;
2370 uint16_t nb_rxq, nb_txq;
2372 hw->adapter_stopped = 0;
2374 rte_intr_disable(intr_handle);
2376 if ((rte_intr_cap_multiple(intr_handle) ||
2377 !RTE_ETH_DEV_SRIOV(dev).active) &&
2378 dev->data->dev_conf.intr_conf.rxq != 0) {
2379 intr_vector = dev->data->nb_rx_queues;
2380 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2385 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2386 intr_handle->intr_vec =
2387 rte_zmalloc("intr_vec",
2388 dev->data->nb_rx_queues * sizeof(int),
2390 if (!intr_handle->intr_vec) {
2392 "Failed to allocate %d rx_queues intr_vec",
2393 dev->data->nb_rx_queues);
2398 /* Initialize VSI */
2399 ret = i40e_dev_rxtx_init(pf);
2400 if (ret != I40E_SUCCESS) {
2401 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2405 /* Map queues with MSIX interrupt */
2406 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2407 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2408 ret = i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2411 i40e_vsi_enable_queues_intr(main_vsi);
2413 /* Map VMDQ VSI queues with MSIX interrupt */
2414 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2415 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2416 ret = i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2417 I40E_ITR_INDEX_DEFAULT);
2420 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2423 /* Enable all queues which have been configured */
2424 for (nb_rxq = 0; nb_rxq < dev->data->nb_rx_queues; nb_rxq++) {
2425 ret = i40e_dev_rx_queue_start(dev, nb_rxq);
2430 for (nb_txq = 0; nb_txq < dev->data->nb_tx_queues; nb_txq++) {
2431 ret = i40e_dev_tx_queue_start(dev, nb_txq);
2436 /* Enable receiving broadcast packets */
2437 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2438 if (ret != I40E_SUCCESS)
2439 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2441 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2442 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2444 if (ret != I40E_SUCCESS)
2445 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2448 /* Enable the VLAN promiscuous mode. */
2450 for (i = 0; i < pf->vf_num; i++) {
2451 vsi = pf->vfs[i].vsi;
2452 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2457 /* Enable mac loopback mode */
2458 if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2459 dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2460 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2461 if (ret != I40E_SUCCESS) {
2462 PMD_DRV_LOG(ERR, "fail to set loopback link");
2467 /* Apply link configure */
2468 ret = i40e_apply_link_speed(dev);
2469 if (I40E_SUCCESS != ret) {
2470 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2474 if (!rte_intr_allow_others(intr_handle)) {
2475 rte_intr_callback_unregister(intr_handle,
2476 i40e_dev_interrupt_handler,
2478 /* configure and enable device interrupt */
2479 i40e_pf_config_irq0(hw, FALSE);
2480 i40e_pf_enable_irq0(hw);
2482 if (dev->data->dev_conf.intr_conf.lsc != 0)
2484 "lsc won't enable because of no intr multiplex");
2486 ret = i40e_aq_set_phy_int_mask(hw,
2487 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2488 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2489 I40E_AQ_EVENT_MEDIA_NA), NULL);
2490 if (ret != I40E_SUCCESS)
2491 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2493 /* Call get_link_info aq commond to enable/disable LSE */
2494 i40e_dev_link_update(dev, 0);
2497 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2498 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2499 i40e_dev_alarm_handler, dev);
2501 /* enable uio intr after callback register */
2502 rte_intr_enable(intr_handle);
2505 i40e_filter_restore(pf);
2507 if (pf->tm_conf.root && !pf->tm_conf.committed)
2508 PMD_DRV_LOG(WARNING,
2509 "please call hierarchy_commit() "
2510 "before starting the port");
2512 return I40E_SUCCESS;
2515 for (i = 0; i < nb_txq; i++)
2516 i40e_dev_tx_queue_stop(dev, i);
2518 for (i = 0; i < nb_rxq; i++)
2519 i40e_dev_rx_queue_stop(dev, i);
2525 i40e_dev_stop(struct rte_eth_dev *dev)
2527 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2528 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2529 struct i40e_vsi *main_vsi = pf->main_vsi;
2530 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2531 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2534 if (hw->adapter_stopped == 1)
2537 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2538 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2539 rte_intr_enable(intr_handle);
2542 /* Disable all queues */
2543 for (i = 0; i < dev->data->nb_tx_queues; i++)
2544 i40e_dev_tx_queue_stop(dev, i);
2546 for (i = 0; i < dev->data->nb_rx_queues; i++)
2547 i40e_dev_rx_queue_stop(dev, i);
2549 /* un-map queues with interrupt registers */
2550 i40e_vsi_disable_queues_intr(main_vsi);
2551 i40e_vsi_queues_unbind_intr(main_vsi);
2553 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2554 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2555 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2558 /* Clear all queues and release memory */
2559 i40e_dev_clear_queues(dev);
2562 i40e_dev_set_link_down(dev);
2564 if (!rte_intr_allow_others(intr_handle))
2565 /* resume to the default handler */
2566 rte_intr_callback_register(intr_handle,
2567 i40e_dev_interrupt_handler,
2570 /* Clean datapath event and queue/vec mapping */
2571 rte_intr_efd_disable(intr_handle);
2572 if (intr_handle->intr_vec) {
2573 rte_free(intr_handle->intr_vec);
2574 intr_handle->intr_vec = NULL;
2577 /* reset hierarchy commit */
2578 pf->tm_conf.committed = false;
2580 hw->adapter_stopped = 1;
2581 dev->data->dev_started = 0;
2583 pf->adapter->rss_reta_updated = 0;
2589 i40e_dev_close(struct rte_eth_dev *dev)
2591 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2592 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2593 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2594 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2595 struct i40e_mirror_rule *p_mirror;
2596 struct i40e_filter_control_settings settings;
2597 struct rte_flow *p_flow;
2601 uint8_t aq_fail = 0;
2604 PMD_INIT_FUNC_TRACE();
2605 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2608 ret = rte_eth_switch_domain_free(pf->switch_domain_id);
2610 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
2613 ret = i40e_dev_stop(dev);
2615 /* Remove all mirror rules */
2616 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2617 ret = i40e_aq_del_mirror_rule(hw,
2618 pf->main_vsi->veb->seid,
2619 p_mirror->rule_type,
2621 p_mirror->num_entries,
2624 PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2625 "status = %d, aq_err = %d.", ret,
2626 hw->aq.asq_last_status);
2628 /* remove mirror software resource anyway */
2629 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2631 pf->nb_mirror_rule--;
2634 i40e_dev_free_queues(dev);
2636 /* Disable interrupt */
2637 i40e_pf_disable_irq0(hw);
2638 rte_intr_disable(intr_handle);
2641 * Only legacy filter API needs the following fdir config. So when the
2642 * legacy filter API is deprecated, the following code should also be
2645 i40e_fdir_teardown(pf);
2647 /* shutdown and destroy the HMC */
2648 i40e_shutdown_lan_hmc(hw);
2650 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2651 i40e_vsi_release(pf->vmdq[i].vsi);
2652 pf->vmdq[i].vsi = NULL;
2657 /* release all the existing VSIs and VEBs */
2658 i40e_vsi_release(pf->main_vsi);
2660 /* shutdown the adminq */
2661 i40e_aq_queue_shutdown(hw, true);
2662 i40e_shutdown_adminq(hw);
2664 i40e_res_pool_destroy(&pf->qp_pool);
2665 i40e_res_pool_destroy(&pf->msix_pool);
2667 /* Disable flexible payload in global configuration */
2668 if (!pf->support_multi_driver)
2669 i40e_flex_payload_reg_set_default(hw);
2671 /* force a PF reset to clean anything leftover */
2672 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2673 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2674 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2675 I40E_WRITE_FLUSH(hw);
2677 /* Clear PXE mode */
2678 i40e_clear_pxe_mode(hw);
2680 /* Unconfigure filter control */
2681 memset(&settings, 0, sizeof(settings));
2682 ret = i40e_set_filter_control(hw, &settings);
2684 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
2687 /* Disable flow control */
2688 hw->fc.requested_mode = I40E_FC_NONE;
2689 i40e_set_fc(hw, &aq_fail, TRUE);
2691 /* uninitialize pf host driver */
2692 i40e_pf_host_uninit(dev);
2695 ret = rte_intr_callback_unregister(intr_handle,
2696 i40e_dev_interrupt_handler, dev);
2697 if (ret >= 0 || ret == -ENOENT) {
2699 } else if (ret != -EAGAIN) {
2701 "intr callback unregister failed: %d",
2704 i40e_msec_delay(500);
2705 } while (retries++ < 5);
2707 i40e_rm_ethtype_filter_list(pf);
2708 i40e_rm_tunnel_filter_list(pf);
2709 i40e_rm_fdir_filter_list(pf);
2711 /* Remove all flows */
2712 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
2713 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
2714 /* Do not free FDIR flows since they are static allocated */
2715 if (p_flow->filter_type != RTE_ETH_FILTER_FDIR)
2719 /* release the fdir static allocated memory */
2720 i40e_fdir_memory_cleanup(pf);
2722 /* Remove all Traffic Manager configuration */
2723 i40e_tm_conf_uninit(dev);
2725 i40e_clear_automask(pf);
2727 hw->adapter_closed = 1;
2732 * Reset PF device only to re-initialize resources in PMD layer
2735 i40e_dev_reset(struct rte_eth_dev *dev)
2739 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2740 * its VF to make them align with it. The detailed notification
2741 * mechanism is PMD specific. As to i40e PF, it is rather complex.
2742 * To avoid unexpected behavior in VF, currently reset of PF with
2743 * SR-IOV activation is not supported. It might be supported later.
2745 if (dev->data->sriov.active)
2748 ret = eth_i40e_dev_uninit(dev);
2752 ret = eth_i40e_dev_init(dev, NULL);
2758 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2760 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2761 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2762 struct i40e_vsi *vsi = pf->main_vsi;
2765 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2767 if (status != I40E_SUCCESS) {
2768 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2772 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2774 if (status != I40E_SUCCESS) {
2775 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2776 /* Rollback unicast promiscuous mode */
2777 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2786 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2788 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2789 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2790 struct i40e_vsi *vsi = pf->main_vsi;
2793 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2795 if (status != I40E_SUCCESS) {
2796 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2800 /* must remain in all_multicast mode */
2801 if (dev->data->all_multicast == 1)
2804 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2806 if (status != I40E_SUCCESS) {
2807 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2808 /* Rollback unicast promiscuous mode */
2809 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2818 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2820 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2821 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2822 struct i40e_vsi *vsi = pf->main_vsi;
2825 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2826 if (ret != I40E_SUCCESS) {
2827 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2835 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2837 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2838 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2839 struct i40e_vsi *vsi = pf->main_vsi;
2842 if (dev->data->promiscuous == 1)
2843 return 0; /* must remain in all_multicast mode */
2845 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2846 vsi->seid, FALSE, NULL);
2847 if (ret != I40E_SUCCESS) {
2848 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2856 * Set device link up.
2859 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2861 /* re-apply link speed setting */
2862 return i40e_apply_link_speed(dev);
2866 * Set device link down.
2869 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2871 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2872 uint8_t abilities = 0;
2873 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2875 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2876 return i40e_phy_conf_link(hw, abilities, speed, false);
2879 static __rte_always_inline void
2880 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2882 /* Link status registers and values*/
2883 #define I40E_PRTMAC_LINKSTA 0x001E2420
2884 #define I40E_REG_LINK_UP 0x40000080
2885 #define I40E_PRTMAC_MACC 0x001E24E0
2886 #define I40E_REG_MACC_25GB 0x00020000
2887 #define I40E_REG_SPEED_MASK 0x38000000
2888 #define I40E_REG_SPEED_0 0x00000000
2889 #define I40E_REG_SPEED_1 0x08000000
2890 #define I40E_REG_SPEED_2 0x10000000
2891 #define I40E_REG_SPEED_3 0x18000000
2892 #define I40E_REG_SPEED_4 0x20000000
2893 uint32_t link_speed;
2896 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2897 link_speed = reg_val & I40E_REG_SPEED_MASK;
2898 reg_val &= I40E_REG_LINK_UP;
2899 link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2901 if (unlikely(link->link_status == 0))
2904 /* Parse the link status */
2905 switch (link_speed) {
2906 case I40E_REG_SPEED_0:
2907 link->link_speed = ETH_SPEED_NUM_100M;
2909 case I40E_REG_SPEED_1:
2910 link->link_speed = ETH_SPEED_NUM_1G;
2912 case I40E_REG_SPEED_2:
2913 if (hw->mac.type == I40E_MAC_X722)
2914 link->link_speed = ETH_SPEED_NUM_2_5G;
2916 link->link_speed = ETH_SPEED_NUM_10G;
2918 case I40E_REG_SPEED_3:
2919 if (hw->mac.type == I40E_MAC_X722) {
2920 link->link_speed = ETH_SPEED_NUM_5G;
2922 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2924 if (reg_val & I40E_REG_MACC_25GB)
2925 link->link_speed = ETH_SPEED_NUM_25G;
2927 link->link_speed = ETH_SPEED_NUM_40G;
2930 case I40E_REG_SPEED_4:
2931 if (hw->mac.type == I40E_MAC_X722)
2932 link->link_speed = ETH_SPEED_NUM_10G;
2934 link->link_speed = ETH_SPEED_NUM_20G;
2937 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2942 static __rte_always_inline void
2943 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2944 bool enable_lse, int wait_to_complete)
2946 #define CHECK_INTERVAL 100 /* 100ms */
2947 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2948 uint32_t rep_cnt = MAX_REPEAT_TIME;
2949 struct i40e_link_status link_status;
2952 memset(&link_status, 0, sizeof(link_status));
2955 memset(&link_status, 0, sizeof(link_status));
2957 /* Get link status information from hardware */
2958 status = i40e_aq_get_link_info(hw, enable_lse,
2959 &link_status, NULL);
2960 if (unlikely(status != I40E_SUCCESS)) {
2961 link->link_speed = ETH_SPEED_NUM_NONE;
2962 link->link_duplex = ETH_LINK_FULL_DUPLEX;
2963 PMD_DRV_LOG(ERR, "Failed to get link info");
2967 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2968 if (!wait_to_complete || link->link_status)
2971 rte_delay_ms(CHECK_INTERVAL);
2972 } while (--rep_cnt);
2974 /* Parse the link status */
2975 switch (link_status.link_speed) {
2976 case I40E_LINK_SPEED_100MB:
2977 link->link_speed = ETH_SPEED_NUM_100M;
2979 case I40E_LINK_SPEED_1GB:
2980 link->link_speed = ETH_SPEED_NUM_1G;
2982 case I40E_LINK_SPEED_10GB:
2983 link->link_speed = ETH_SPEED_NUM_10G;
2985 case I40E_LINK_SPEED_20GB:
2986 link->link_speed = ETH_SPEED_NUM_20G;
2988 case I40E_LINK_SPEED_25GB:
2989 link->link_speed = ETH_SPEED_NUM_25G;
2991 case I40E_LINK_SPEED_40GB:
2992 link->link_speed = ETH_SPEED_NUM_40G;
2995 if (link->link_status)
2996 link->link_speed = ETH_SPEED_NUM_UNKNOWN;
2998 link->link_speed = ETH_SPEED_NUM_NONE;
3004 i40e_dev_link_update(struct rte_eth_dev *dev,
3005 int wait_to_complete)
3007 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3008 struct rte_eth_link link;
3009 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3012 memset(&link, 0, sizeof(link));
3014 /* i40e uses full duplex only */
3015 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3016 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
3017 ETH_LINK_SPEED_FIXED);
3019 if (!wait_to_complete && !enable_lse)
3020 update_link_reg(hw, &link);
3022 update_link_aq(hw, &link, enable_lse, wait_to_complete);
3025 rte_eth_linkstatus_get(hw->switch_dev, &link);
3027 ret = rte_eth_linkstatus_set(dev, &link);
3028 i40e_notify_all_vfs_link_status(dev);
3034 i40e_stat_update_48_in_64(struct i40e_hw *hw, uint32_t hireg,
3035 uint32_t loreg, bool offset_loaded, uint64_t *offset,
3036 uint64_t *stat, uint64_t *prev_stat)
3038 i40e_stat_update_48(hw, hireg, loreg, offset_loaded, offset, stat);
3039 /* enlarge the limitation when statistics counters overflowed */
3040 if (offset_loaded) {
3041 if (I40E_RXTX_BYTES_L_48_BIT(*prev_stat) > *stat)
3042 *stat += (uint64_t)1 << I40E_48_BIT_WIDTH;
3043 *stat += I40E_RXTX_BYTES_H_16_BIT(*prev_stat);
3048 /* Get all the statistics of a VSI */
3050 i40e_update_vsi_stats(struct i40e_vsi *vsi)
3052 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
3053 struct i40e_eth_stats *nes = &vsi->eth_stats;
3054 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3055 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
3057 i40e_stat_update_48_in_64(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
3058 vsi->offset_loaded, &oes->rx_bytes,
3059 &nes->rx_bytes, &vsi->prev_rx_bytes);
3060 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
3061 vsi->offset_loaded, &oes->rx_unicast,
3063 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
3064 vsi->offset_loaded, &oes->rx_multicast,
3065 &nes->rx_multicast);
3066 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
3067 vsi->offset_loaded, &oes->rx_broadcast,
3068 &nes->rx_broadcast);
3069 /* exclude CRC bytes */
3070 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
3071 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
3073 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
3074 &oes->rx_discards, &nes->rx_discards);
3075 /* GLV_REPC not supported */
3076 /* GLV_RMPC not supported */
3077 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
3078 &oes->rx_unknown_protocol,
3079 &nes->rx_unknown_protocol);
3080 i40e_stat_update_48_in_64(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
3081 vsi->offset_loaded, &oes->tx_bytes,
3082 &nes->tx_bytes, &vsi->prev_tx_bytes);
3083 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
3084 vsi->offset_loaded, &oes->tx_unicast,
3086 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
3087 vsi->offset_loaded, &oes->tx_multicast,
3088 &nes->tx_multicast);
3089 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
3090 vsi->offset_loaded, &oes->tx_broadcast,
3091 &nes->tx_broadcast);
3092 /* GLV_TDPC not supported */
3093 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
3094 &oes->tx_errors, &nes->tx_errors);
3095 vsi->offset_loaded = true;
3097 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
3099 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
3100 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
3101 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
3102 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
3103 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
3104 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3105 nes->rx_unknown_protocol);
3106 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
3107 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
3108 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
3109 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
3110 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
3111 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
3112 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
3117 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
3120 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3121 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
3123 /* Get rx/tx bytes of internal transfer packets */
3124 i40e_stat_update_48_in_64(hw, I40E_GLV_GORCH(hw->port),
3125 I40E_GLV_GORCL(hw->port),
3127 &pf->internal_stats_offset.rx_bytes,
3128 &pf->internal_stats.rx_bytes,
3129 &pf->internal_prev_rx_bytes);
3130 i40e_stat_update_48_in_64(hw, I40E_GLV_GOTCH(hw->port),
3131 I40E_GLV_GOTCL(hw->port),
3133 &pf->internal_stats_offset.tx_bytes,
3134 &pf->internal_stats.tx_bytes,
3135 &pf->internal_prev_tx_bytes);
3136 /* Get total internal rx packet count */
3137 i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
3138 I40E_GLV_UPRCL(hw->port),
3140 &pf->internal_stats_offset.rx_unicast,
3141 &pf->internal_stats.rx_unicast);
3142 i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
3143 I40E_GLV_MPRCL(hw->port),
3145 &pf->internal_stats_offset.rx_multicast,
3146 &pf->internal_stats.rx_multicast);
3147 i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
3148 I40E_GLV_BPRCL(hw->port),
3150 &pf->internal_stats_offset.rx_broadcast,
3151 &pf->internal_stats.rx_broadcast);
3152 /* Get total internal tx packet count */
3153 i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
3154 I40E_GLV_UPTCL(hw->port),
3156 &pf->internal_stats_offset.tx_unicast,
3157 &pf->internal_stats.tx_unicast);
3158 i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
3159 I40E_GLV_MPTCL(hw->port),
3161 &pf->internal_stats_offset.tx_multicast,
3162 &pf->internal_stats.tx_multicast);
3163 i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
3164 I40E_GLV_BPTCL(hw->port),
3166 &pf->internal_stats_offset.tx_broadcast,
3167 &pf->internal_stats.tx_broadcast);
3169 /* exclude CRC size */
3170 pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
3171 pf->internal_stats.rx_multicast +
3172 pf->internal_stats.rx_broadcast) * RTE_ETHER_CRC_LEN;
3174 /* Get statistics of struct i40e_eth_stats */
3175 i40e_stat_update_48_in_64(hw, I40E_GLPRT_GORCH(hw->port),
3176 I40E_GLPRT_GORCL(hw->port),
3177 pf->offset_loaded, &os->eth.rx_bytes,
3178 &ns->eth.rx_bytes, &pf->prev_rx_bytes);
3179 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
3180 I40E_GLPRT_UPRCL(hw->port),
3181 pf->offset_loaded, &os->eth.rx_unicast,
3182 &ns->eth.rx_unicast);
3183 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
3184 I40E_GLPRT_MPRCL(hw->port),
3185 pf->offset_loaded, &os->eth.rx_multicast,
3186 &ns->eth.rx_multicast);
3187 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
3188 I40E_GLPRT_BPRCL(hw->port),
3189 pf->offset_loaded, &os->eth.rx_broadcast,
3190 &ns->eth.rx_broadcast);
3191 /* Workaround: CRC size should not be included in byte statistics,
3192 * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
3195 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
3196 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
3198 /* exclude internal rx bytes
3199 * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
3200 * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
3202 * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
3204 if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
3205 ns->eth.rx_bytes = 0;
3207 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
3209 if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
3210 ns->eth.rx_unicast = 0;
3212 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
3214 if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
3215 ns->eth.rx_multicast = 0;
3217 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
3219 if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
3220 ns->eth.rx_broadcast = 0;
3222 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
3224 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
3225 pf->offset_loaded, &os->eth.rx_discards,
3226 &ns->eth.rx_discards);
3227 /* GLPRT_REPC not supported */
3228 /* GLPRT_RMPC not supported */
3229 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
3231 &os->eth.rx_unknown_protocol,
3232 &ns->eth.rx_unknown_protocol);
3233 i40e_stat_update_48_in_64(hw, I40E_GLPRT_GOTCH(hw->port),
3234 I40E_GLPRT_GOTCL(hw->port),
3235 pf->offset_loaded, &os->eth.tx_bytes,
3236 &ns->eth.tx_bytes, &pf->prev_tx_bytes);
3237 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
3238 I40E_GLPRT_UPTCL(hw->port),
3239 pf->offset_loaded, &os->eth.tx_unicast,
3240 &ns->eth.tx_unicast);
3241 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
3242 I40E_GLPRT_MPTCL(hw->port),
3243 pf->offset_loaded, &os->eth.tx_multicast,
3244 &ns->eth.tx_multicast);
3245 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
3246 I40E_GLPRT_BPTCL(hw->port),
3247 pf->offset_loaded, &os->eth.tx_broadcast,
3248 &ns->eth.tx_broadcast);
3249 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3250 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3252 /* exclude internal tx bytes
3253 * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
3254 * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
3256 * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
3258 if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
3259 ns->eth.tx_bytes = 0;
3261 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3263 if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3264 ns->eth.tx_unicast = 0;
3266 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3268 if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3269 ns->eth.tx_multicast = 0;
3271 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3273 if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3274 ns->eth.tx_broadcast = 0;
3276 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3278 /* GLPRT_TEPC not supported */
3280 /* additional port specific stats */
3281 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3282 pf->offset_loaded, &os->tx_dropped_link_down,
3283 &ns->tx_dropped_link_down);
3284 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3285 pf->offset_loaded, &os->crc_errors,
3287 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3288 pf->offset_loaded, &os->illegal_bytes,
3289 &ns->illegal_bytes);
3290 /* GLPRT_ERRBC not supported */
3291 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3292 pf->offset_loaded, &os->mac_local_faults,
3293 &ns->mac_local_faults);
3294 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3295 pf->offset_loaded, &os->mac_remote_faults,
3296 &ns->mac_remote_faults);
3297 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3298 pf->offset_loaded, &os->rx_length_errors,
3299 &ns->rx_length_errors);
3300 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3301 pf->offset_loaded, &os->link_xon_rx,
3303 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3304 pf->offset_loaded, &os->link_xoff_rx,
3306 for (i = 0; i < 8; i++) {
3307 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3309 &os->priority_xon_rx[i],
3310 &ns->priority_xon_rx[i]);
3311 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3313 &os->priority_xoff_rx[i],
3314 &ns->priority_xoff_rx[i]);
3316 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3317 pf->offset_loaded, &os->link_xon_tx,
3319 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3320 pf->offset_loaded, &os->link_xoff_tx,
3322 for (i = 0; i < 8; i++) {
3323 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3325 &os->priority_xon_tx[i],
3326 &ns->priority_xon_tx[i]);
3327 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3329 &os->priority_xoff_tx[i],
3330 &ns->priority_xoff_tx[i]);
3331 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3333 &os->priority_xon_2_xoff[i],
3334 &ns->priority_xon_2_xoff[i]);
3336 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3337 I40E_GLPRT_PRC64L(hw->port),
3338 pf->offset_loaded, &os->rx_size_64,
3340 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3341 I40E_GLPRT_PRC127L(hw->port),
3342 pf->offset_loaded, &os->rx_size_127,
3344 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3345 I40E_GLPRT_PRC255L(hw->port),
3346 pf->offset_loaded, &os->rx_size_255,
3348 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3349 I40E_GLPRT_PRC511L(hw->port),
3350 pf->offset_loaded, &os->rx_size_511,
3352 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3353 I40E_GLPRT_PRC1023L(hw->port),
3354 pf->offset_loaded, &os->rx_size_1023,
3356 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3357 I40E_GLPRT_PRC1522L(hw->port),
3358 pf->offset_loaded, &os->rx_size_1522,
3360 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3361 I40E_GLPRT_PRC9522L(hw->port),
3362 pf->offset_loaded, &os->rx_size_big,
3364 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3365 pf->offset_loaded, &os->rx_undersize,
3367 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3368 pf->offset_loaded, &os->rx_fragments,
3370 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3371 pf->offset_loaded, &os->rx_oversize,
3373 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3374 pf->offset_loaded, &os->rx_jabber,
3376 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3377 I40E_GLPRT_PTC64L(hw->port),
3378 pf->offset_loaded, &os->tx_size_64,
3380 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3381 I40E_GLPRT_PTC127L(hw->port),
3382 pf->offset_loaded, &os->tx_size_127,
3384 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3385 I40E_GLPRT_PTC255L(hw->port),
3386 pf->offset_loaded, &os->tx_size_255,
3388 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3389 I40E_GLPRT_PTC511L(hw->port),
3390 pf->offset_loaded, &os->tx_size_511,
3392 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3393 I40E_GLPRT_PTC1023L(hw->port),
3394 pf->offset_loaded, &os->tx_size_1023,
3396 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3397 I40E_GLPRT_PTC1522L(hw->port),
3398 pf->offset_loaded, &os->tx_size_1522,
3400 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3401 I40E_GLPRT_PTC9522L(hw->port),
3402 pf->offset_loaded, &os->tx_size_big,
3404 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3406 &os->fd_sb_match, &ns->fd_sb_match);
3407 /* GLPRT_MSPDC not supported */
3408 /* GLPRT_XEC not supported */
3410 pf->offset_loaded = true;
3413 i40e_update_vsi_stats(pf->main_vsi);
3416 /* Get all statistics of a port */
3418 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3420 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3421 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3422 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3423 struct i40e_vsi *vsi;
3426 /* call read registers - updates values, now write them to struct */
3427 i40e_read_stats_registers(pf, hw);
3429 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3430 pf->main_vsi->eth_stats.rx_multicast +
3431 pf->main_vsi->eth_stats.rx_broadcast -
3432 pf->main_vsi->eth_stats.rx_discards;
3433 stats->opackets = ns->eth.tx_unicast +
3434 ns->eth.tx_multicast +
3435 ns->eth.tx_broadcast;
3436 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes;
3437 stats->obytes = ns->eth.tx_bytes;
3438 stats->oerrors = ns->eth.tx_errors +
3439 pf->main_vsi->eth_stats.tx_errors;
3442 stats->imissed = ns->eth.rx_discards +
3443 pf->main_vsi->eth_stats.rx_discards;
3444 stats->ierrors = ns->crc_errors +
3445 ns->rx_length_errors + ns->rx_undersize +
3446 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3449 for (i = 0; i < pf->vf_num; i++) {
3450 vsi = pf->vfs[i].vsi;
3451 i40e_update_vsi_stats(vsi);
3453 stats->ipackets += (vsi->eth_stats.rx_unicast +
3454 vsi->eth_stats.rx_multicast +
3455 vsi->eth_stats.rx_broadcast -
3456 vsi->eth_stats.rx_discards);
3457 stats->ibytes += vsi->eth_stats.rx_bytes;
3458 stats->oerrors += vsi->eth_stats.tx_errors;
3459 stats->imissed += vsi->eth_stats.rx_discards;
3463 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3464 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
3465 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
3466 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
3467 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
3468 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
3469 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3470 ns->eth.rx_unknown_protocol);
3471 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
3472 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
3473 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
3474 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
3475 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
3476 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
3478 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
3479 ns->tx_dropped_link_down);
3480 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
3481 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
3483 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
3484 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
3485 ns->mac_local_faults);
3486 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
3487 ns->mac_remote_faults);
3488 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
3489 ns->rx_length_errors);
3490 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
3491 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
3492 for (i = 0; i < 8; i++) {
3493 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
3494 i, ns->priority_xon_rx[i]);
3495 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
3496 i, ns->priority_xoff_rx[i]);
3498 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
3499 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
3500 for (i = 0; i < 8; i++) {
3501 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
3502 i, ns->priority_xon_tx[i]);
3503 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
3504 i, ns->priority_xoff_tx[i]);
3505 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
3506 i, ns->priority_xon_2_xoff[i]);
3508 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
3509 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
3510 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
3511 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
3512 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
3513 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
3514 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
3515 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
3516 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
3517 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
3518 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
3519 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
3520 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
3521 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
3522 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
3523 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
3524 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
3525 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
3526 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3527 ns->mac_short_packet_dropped);
3528 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
3529 ns->checksum_error);
3530 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
3531 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3535 /* Reset the statistics */
3537 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3539 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3540 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3542 /* Mark PF and VSI stats to update the offset, aka "reset" */
3543 pf->offset_loaded = false;
3545 pf->main_vsi->offset_loaded = false;
3547 /* read the stats, reading current register values into offset */
3548 i40e_read_stats_registers(pf, hw);
3554 i40e_xstats_calc_num(void)
3556 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3557 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3558 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3561 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3562 struct rte_eth_xstat_name *xstats_names,
3563 __rte_unused unsigned limit)
3568 if (xstats_names == NULL)
3569 return i40e_xstats_calc_num();
3571 /* Note: limit checked in rte_eth_xstats_names() */
3573 /* Get stats from i40e_eth_stats struct */
3574 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3575 strlcpy(xstats_names[count].name,
3576 rte_i40e_stats_strings[i].name,
3577 sizeof(xstats_names[count].name));
3581 /* Get individiual stats from i40e_hw_port struct */
3582 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3583 strlcpy(xstats_names[count].name,
3584 rte_i40e_hw_port_strings[i].name,
3585 sizeof(xstats_names[count].name));
3589 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3590 for (prio = 0; prio < 8; prio++) {
3591 snprintf(xstats_names[count].name,
3592 sizeof(xstats_names[count].name),
3593 "rx_priority%u_%s", prio,
3594 rte_i40e_rxq_prio_strings[i].name);
3599 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3600 for (prio = 0; prio < 8; prio++) {
3601 snprintf(xstats_names[count].name,
3602 sizeof(xstats_names[count].name),
3603 "tx_priority%u_%s", prio,
3604 rte_i40e_txq_prio_strings[i].name);
3612 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3615 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3616 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3617 unsigned i, count, prio;
3618 struct i40e_hw_port_stats *hw_stats = &pf->stats;
3620 count = i40e_xstats_calc_num();
3624 i40e_read_stats_registers(pf, hw);
3631 /* Get stats from i40e_eth_stats struct */
3632 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3633 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3634 rte_i40e_stats_strings[i].offset);
3635 xstats[count].id = count;
3639 /* Get individiual stats from i40e_hw_port struct */
3640 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3641 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3642 rte_i40e_hw_port_strings[i].offset);
3643 xstats[count].id = count;
3647 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3648 for (prio = 0; prio < 8; prio++) {
3649 xstats[count].value =
3650 *(uint64_t *)(((char *)hw_stats) +
3651 rte_i40e_rxq_prio_strings[i].offset +
3652 (sizeof(uint64_t) * prio));
3653 xstats[count].id = count;
3658 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3659 for (prio = 0; prio < 8; prio++) {
3660 xstats[count].value =
3661 *(uint64_t *)(((char *)hw_stats) +
3662 rte_i40e_txq_prio_strings[i].offset +
3663 (sizeof(uint64_t) * prio));
3664 xstats[count].id = count;
3673 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3675 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3681 full_ver = hw->nvm.oem_ver;
3682 ver = (u8)(full_ver >> 24);
3683 build = (u16)((full_ver >> 8) & 0xffff);
3684 patch = (u8)(full_ver & 0xff);
3686 ret = snprintf(fw_version, fw_size,
3687 "%d.%d%d 0x%08x %d.%d.%d",
3688 ((hw->nvm.version >> 12) & 0xf),
3689 ((hw->nvm.version >> 4) & 0xff),
3690 (hw->nvm.version & 0xf), hw->nvm.eetrack,
3695 ret += 1; /* add the size of '\0' */
3696 if (fw_size < (size_t)ret)
3703 * When using NVM 6.01(for X710 XL710 XXV710)/3.33(for X722) or later,
3704 * the Rx data path does not hang if the FW LLDP is stopped.
3705 * return true if lldp need to stop
3706 * return false if we cannot disable the LLDP to avoid Rx data path blocking.
3709 i40e_need_stop_lldp(struct rte_eth_dev *dev)
3712 char ver_str[64] = {0};
3713 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3715 i40e_fw_version_get(dev, ver_str, 64);
3716 nvm_ver = atof(ver_str);
3717 if ((hw->mac.type == I40E_MAC_X722 ||
3718 hw->mac.type == I40E_MAC_X722_VF) &&
3719 ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(3.33 * 1000)))
3721 else if ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(6.01 * 1000))
3728 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3730 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3731 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3732 struct i40e_vsi *vsi = pf->main_vsi;
3733 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3735 dev_info->max_rx_queues = vsi->nb_qps;
3736 dev_info->max_tx_queues = vsi->nb_qps;
3737 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3738 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3739 dev_info->max_mac_addrs = vsi->max_macaddrs;
3740 dev_info->max_vfs = pci_dev->max_vfs;
3741 dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
3742 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3743 dev_info->rx_queue_offload_capa = 0;
3744 dev_info->rx_offload_capa =
3745 DEV_RX_OFFLOAD_VLAN_STRIP |
3746 DEV_RX_OFFLOAD_QINQ_STRIP |
3747 DEV_RX_OFFLOAD_IPV4_CKSUM |
3748 DEV_RX_OFFLOAD_UDP_CKSUM |
3749 DEV_RX_OFFLOAD_TCP_CKSUM |
3750 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3751 DEV_RX_OFFLOAD_KEEP_CRC |
3752 DEV_RX_OFFLOAD_SCATTER |
3753 DEV_RX_OFFLOAD_VLAN_EXTEND |
3754 DEV_RX_OFFLOAD_VLAN_FILTER |
3755 DEV_RX_OFFLOAD_JUMBO_FRAME |
3756 DEV_RX_OFFLOAD_RSS_HASH;
3758 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3759 dev_info->tx_offload_capa =
3760 DEV_TX_OFFLOAD_VLAN_INSERT |
3761 DEV_TX_OFFLOAD_QINQ_INSERT |
3762 DEV_TX_OFFLOAD_IPV4_CKSUM |
3763 DEV_TX_OFFLOAD_UDP_CKSUM |
3764 DEV_TX_OFFLOAD_TCP_CKSUM |
3765 DEV_TX_OFFLOAD_SCTP_CKSUM |
3766 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3767 DEV_TX_OFFLOAD_TCP_TSO |
3768 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3769 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3770 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3771 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3772 DEV_TX_OFFLOAD_MULTI_SEGS |
3773 dev_info->tx_queue_offload_capa;
3774 dev_info->dev_capa =
3775 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3776 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3778 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3780 dev_info->reta_size = pf->hash_lut_size;
3781 dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3783 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3785 .pthresh = I40E_DEFAULT_RX_PTHRESH,
3786 .hthresh = I40E_DEFAULT_RX_HTHRESH,
3787 .wthresh = I40E_DEFAULT_RX_WTHRESH,
3789 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3794 dev_info->default_txconf = (struct rte_eth_txconf) {
3796 .pthresh = I40E_DEFAULT_TX_PTHRESH,
3797 .hthresh = I40E_DEFAULT_TX_HTHRESH,
3798 .wthresh = I40E_DEFAULT_TX_WTHRESH,
3800 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3801 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3805 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3806 .nb_max = I40E_MAX_RING_DESC,
3807 .nb_min = I40E_MIN_RING_DESC,
3808 .nb_align = I40E_ALIGN_RING_DESC,
3811 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3812 .nb_max = I40E_MAX_RING_DESC,
3813 .nb_min = I40E_MIN_RING_DESC,
3814 .nb_align = I40E_ALIGN_RING_DESC,
3815 .nb_seg_max = I40E_TX_MAX_SEG,
3816 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3819 if (pf->flags & I40E_FLAG_VMDQ) {
3820 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3821 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3822 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3823 pf->max_nb_vmdq_vsi;
3824 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3825 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3826 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3829 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3831 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3832 dev_info->default_rxportconf.nb_queues = 2;
3833 dev_info->default_txportconf.nb_queues = 2;
3834 if (dev->data->nb_rx_queues == 1)
3835 dev_info->default_rxportconf.ring_size = 2048;
3837 dev_info->default_rxportconf.ring_size = 1024;
3838 if (dev->data->nb_tx_queues == 1)
3839 dev_info->default_txportconf.ring_size = 1024;
3841 dev_info->default_txportconf.ring_size = 512;
3843 } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3845 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3846 dev_info->default_rxportconf.nb_queues = 1;
3847 dev_info->default_txportconf.nb_queues = 1;
3848 dev_info->default_rxportconf.ring_size = 256;
3849 dev_info->default_txportconf.ring_size = 256;
3852 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3853 dev_info->default_rxportconf.nb_queues = 1;
3854 dev_info->default_txportconf.nb_queues = 1;
3855 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3856 dev_info->default_rxportconf.ring_size = 512;
3857 dev_info->default_txportconf.ring_size = 256;
3859 dev_info->default_rxportconf.ring_size = 256;
3860 dev_info->default_txportconf.ring_size = 256;
3863 dev_info->default_rxportconf.burst_size = 32;
3864 dev_info->default_txportconf.burst_size = 32;
3870 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3872 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3873 struct i40e_vsi *vsi = pf->main_vsi;
3874 PMD_INIT_FUNC_TRACE();
3877 return i40e_vsi_add_vlan(vsi, vlan_id);
3879 return i40e_vsi_delete_vlan(vsi, vlan_id);
3883 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3884 enum rte_vlan_type vlan_type,
3885 uint16_t tpid, int qinq)
3887 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3890 uint16_t reg_id = 3;
3894 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3898 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3900 if (ret != I40E_SUCCESS) {
3902 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3907 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3910 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3911 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3912 if (reg_r == reg_w) {
3913 PMD_DRV_LOG(DEBUG, "No need to write");
3917 ret = i40e_aq_debug_write_global_register(hw,
3918 I40E_GL_SWT_L2TAGCTRL(reg_id),
3920 if (ret != I40E_SUCCESS) {
3922 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3927 "Global register 0x%08x is changed with value 0x%08x",
3928 I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3934 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3935 enum rte_vlan_type vlan_type,
3938 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3939 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3940 int qinq = dev->data->dev_conf.rxmode.offloads &
3941 DEV_RX_OFFLOAD_VLAN_EXTEND;
3944 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3945 vlan_type != ETH_VLAN_TYPE_OUTER) ||
3946 (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3948 "Unsupported vlan type.");
3952 if (pf->support_multi_driver) {
3953 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3957 /* 802.1ad frames ability is added in NVM API 1.7*/
3958 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3960 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3961 hw->first_tag = rte_cpu_to_le_16(tpid);
3962 else if (vlan_type == ETH_VLAN_TYPE_INNER)
3963 hw->second_tag = rte_cpu_to_le_16(tpid);
3965 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3966 hw->second_tag = rte_cpu_to_le_16(tpid);
3968 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL);
3969 if (ret != I40E_SUCCESS) {
3971 "Set switch config failed aq_err: %d",
3972 hw->aq.asq_last_status);
3976 /* If NVM API < 1.7, keep the register setting */
3977 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3983 /* Configure outer vlan stripping on or off in QinQ mode */
3985 i40e_vsi_config_outer_vlan_stripping(struct i40e_vsi *vsi, bool on)
3987 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3988 int ret = I40E_SUCCESS;
3991 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
3992 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
3996 /* Configure for outer VLAN RX stripping */
3997 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
4000 reg |= I40E_VSI_TSR_QINQ_STRIP;
4002 reg &= ~I40E_VSI_TSR_QINQ_STRIP;
4004 ret = i40e_aq_debug_write_register(hw,
4005 I40E_VSI_TSR(vsi->vsi_id),
4008 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
4010 return I40E_ERR_CONFIG;
4017 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4019 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4020 struct i40e_vsi *vsi = pf->main_vsi;
4021 struct rte_eth_rxmode *rxmode;
4023 rxmode = &dev->data->dev_conf.rxmode;
4024 if (mask & ETH_VLAN_FILTER_MASK) {
4025 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4026 i40e_vsi_config_vlan_filter(vsi, TRUE);
4028 i40e_vsi_config_vlan_filter(vsi, FALSE);
4031 if (mask & ETH_VLAN_STRIP_MASK) {
4032 /* Enable or disable VLAN stripping */
4033 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
4034 i40e_vsi_config_vlan_stripping(vsi, TRUE);
4036 i40e_vsi_config_vlan_stripping(vsi, FALSE);
4039 if (mask & ETH_VLAN_EXTEND_MASK) {
4040 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
4041 i40e_vsi_config_double_vlan(vsi, TRUE);
4042 /* Set global registers with default ethertype. */
4043 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
4044 RTE_ETHER_TYPE_VLAN);
4045 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
4046 RTE_ETHER_TYPE_VLAN);
4049 i40e_vsi_config_double_vlan(vsi, FALSE);
4052 if (mask & ETH_QINQ_STRIP_MASK) {
4053 /* Enable or disable outer VLAN stripping */
4054 if (rxmode->offloads & DEV_RX_OFFLOAD_QINQ_STRIP)
4055 i40e_vsi_config_outer_vlan_stripping(vsi, TRUE);
4057 i40e_vsi_config_outer_vlan_stripping(vsi, FALSE);
4064 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
4065 __rte_unused uint16_t queue,
4066 __rte_unused int on)
4068 PMD_INIT_FUNC_TRACE();
4072 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
4074 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4075 struct i40e_vsi *vsi = pf->main_vsi;
4076 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
4077 struct i40e_vsi_vlan_pvid_info info;
4079 memset(&info, 0, sizeof(info));
4082 info.config.pvid = pvid;
4084 info.config.reject.tagged =
4085 data->dev_conf.txmode.hw_vlan_reject_tagged;
4086 info.config.reject.untagged =
4087 data->dev_conf.txmode.hw_vlan_reject_untagged;
4090 return i40e_vsi_vlan_pvid_set(vsi, &info);
4094 i40e_dev_led_on(struct rte_eth_dev *dev)
4096 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4097 uint32_t mode = i40e_led_get(hw);
4100 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
4106 i40e_dev_led_off(struct rte_eth_dev *dev)
4108 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4109 uint32_t mode = i40e_led_get(hw);
4112 i40e_led_set(hw, 0, false);
4118 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4120 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4121 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4123 fc_conf->pause_time = pf->fc_conf.pause_time;
4125 /* read out from register, in case they are modified by other port */
4126 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
4127 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
4128 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
4129 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
4131 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
4132 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
4134 /* Return current mode according to actual setting*/
4135 switch (hw->fc.current_mode) {
4137 fc_conf->mode = RTE_FC_FULL;
4139 case I40E_FC_TX_PAUSE:
4140 fc_conf->mode = RTE_FC_TX_PAUSE;
4142 case I40E_FC_RX_PAUSE:
4143 fc_conf->mode = RTE_FC_RX_PAUSE;
4147 fc_conf->mode = RTE_FC_NONE;
4154 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4156 uint32_t mflcn_reg, fctrl_reg, reg;
4157 uint32_t max_high_water;
4158 uint8_t i, aq_failure;
4162 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
4163 [RTE_FC_NONE] = I40E_FC_NONE,
4164 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
4165 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
4166 [RTE_FC_FULL] = I40E_FC_FULL
4169 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
4171 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
4172 if ((fc_conf->high_water > max_high_water) ||
4173 (fc_conf->high_water < fc_conf->low_water)) {
4175 "Invalid high/low water setup value in KB, High_water must be <= %d.",
4180 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4181 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4182 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
4184 pf->fc_conf.pause_time = fc_conf->pause_time;
4185 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
4186 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
4188 PMD_INIT_FUNC_TRACE();
4190 /* All the link flow control related enable/disable register
4191 * configuration is handle by the F/W
4193 err = i40e_set_fc(hw, &aq_failure, true);
4197 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
4198 /* Configure flow control refresh threshold,
4199 * the value for stat_tx_pause_refresh_timer[8]
4200 * is used for global pause operation.
4204 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
4205 pf->fc_conf.pause_time);
4207 /* configure the timer value included in transmitted pause
4209 * the value for stat_tx_pause_quanta[8] is used for global
4212 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
4213 pf->fc_conf.pause_time);
4215 fctrl_reg = I40E_READ_REG(hw,
4216 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
4218 if (fc_conf->mac_ctrl_frame_fwd != 0)
4219 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
4221 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
4223 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
4226 /* Configure pause time (2 TCs per register) */
4227 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
4228 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
4229 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
4231 /* Configure flow control refresh threshold value */
4232 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
4233 pf->fc_conf.pause_time / 2);
4235 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4237 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
4238 *depending on configuration
4240 if (fc_conf->mac_ctrl_frame_fwd != 0) {
4241 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
4242 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
4244 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
4245 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
4248 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
4251 if (!pf->support_multi_driver) {
4252 /* config water marker both based on the packets and bytes */
4253 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
4254 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4255 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4256 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
4257 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4258 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4259 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
4260 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4262 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
4263 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4267 "Water marker configuration is not supported.");
4270 I40E_WRITE_FLUSH(hw);
4276 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
4277 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
4279 PMD_INIT_FUNC_TRACE();
4284 /* Add a MAC address, and update filters */
4286 i40e_macaddr_add(struct rte_eth_dev *dev,
4287 struct rte_ether_addr *mac_addr,
4288 __rte_unused uint32_t index,
4291 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4292 struct i40e_mac_filter_info mac_filter;
4293 struct i40e_vsi *vsi;
4294 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
4297 /* If VMDQ not enabled or configured, return */
4298 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
4299 !pf->nb_cfg_vmdq_vsi)) {
4300 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
4301 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
4306 if (pool > pf->nb_cfg_vmdq_vsi) {
4307 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
4308 pool, pf->nb_cfg_vmdq_vsi);
4312 rte_memcpy(&mac_filter.mac_addr, mac_addr, RTE_ETHER_ADDR_LEN);
4313 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4314 mac_filter.filter_type = I40E_MACVLAN_PERFECT_MATCH;
4316 mac_filter.filter_type = I40E_MAC_PERFECT_MATCH;
4321 vsi = pf->vmdq[pool - 1].vsi;
4323 ret = i40e_vsi_add_mac(vsi, &mac_filter);
4324 if (ret != I40E_SUCCESS) {
4325 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4331 /* Remove a MAC address, and update filters */
4333 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4335 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4336 struct i40e_vsi *vsi;
4337 struct rte_eth_dev_data *data = dev->data;
4338 struct rte_ether_addr *macaddr;
4343 macaddr = &(data->mac_addrs[index]);
4345 pool_sel = dev->data->mac_pool_sel[index];
4347 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4348 if (pool_sel & (1ULL << i)) {
4352 /* No VMDQ pool enabled or configured */
4353 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4354 (i > pf->nb_cfg_vmdq_vsi)) {
4356 "No VMDQ pool enabled/configured");
4359 vsi = pf->vmdq[i - 1].vsi;
4361 ret = i40e_vsi_delete_mac(vsi, macaddr);
4364 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4372 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4374 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4375 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4382 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4383 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id,
4384 vsi->type != I40E_VSI_SRIOV,
4387 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4391 uint32_t *lut_dw = (uint32_t *)lut;
4392 uint16_t i, lut_size_dw = lut_size / 4;
4394 if (vsi->type == I40E_VSI_SRIOV) {
4395 for (i = 0; i <= lut_size_dw; i++) {
4396 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4397 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4400 for (i = 0; i < lut_size_dw; i++)
4401 lut_dw[i] = I40E_READ_REG(hw,
4410 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4418 pf = I40E_VSI_TO_PF(vsi);
4419 hw = I40E_VSI_TO_HW(vsi);
4421 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4422 enum i40e_status_code status;
4424 status = i40e_aq_set_rss_lut(hw, vsi->vsi_id,
4425 vsi->type != I40E_VSI_SRIOV,
4429 "Failed to update RSS lookup table, error status: %d",
4434 uint32_t *lut_dw = (uint32_t *)lut;
4435 uint16_t i, lut_size_dw = lut_size / 4;
4437 if (vsi->type == I40E_VSI_SRIOV) {
4438 for (i = 0; i < lut_size_dw; i++)
4441 I40E_VFQF_HLUT1(i, vsi->user_param),
4444 for (i = 0; i < lut_size_dw; i++)
4445 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4448 I40E_WRITE_FLUSH(hw);
4455 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4456 struct rte_eth_rss_reta_entry64 *reta_conf,
4459 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4460 uint16_t i, lut_size = pf->hash_lut_size;
4461 uint16_t idx, shift;
4465 if (reta_size != lut_size ||
4466 reta_size > ETH_RSS_RETA_SIZE_512) {
4468 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4469 reta_size, lut_size);
4473 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4475 PMD_DRV_LOG(ERR, "No memory can be allocated");
4478 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4481 for (i = 0; i < reta_size; i++) {
4482 idx = i / RTE_RETA_GROUP_SIZE;
4483 shift = i % RTE_RETA_GROUP_SIZE;
4484 if (reta_conf[idx].mask & (1ULL << shift))
4485 lut[i] = reta_conf[idx].reta[shift];
4487 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4489 pf->adapter->rss_reta_updated = 1;
4498 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4499 struct rte_eth_rss_reta_entry64 *reta_conf,
4502 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4503 uint16_t i, lut_size = pf->hash_lut_size;
4504 uint16_t idx, shift;
4508 if (reta_size != lut_size ||
4509 reta_size > ETH_RSS_RETA_SIZE_512) {
4511 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4512 reta_size, lut_size);
4516 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4518 PMD_DRV_LOG(ERR, "No memory can be allocated");
4522 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4525 for (i = 0; i < reta_size; i++) {
4526 idx = i / RTE_RETA_GROUP_SIZE;
4527 shift = i % RTE_RETA_GROUP_SIZE;
4528 if (reta_conf[idx].mask & (1ULL << shift))
4529 reta_conf[idx].reta[shift] = lut[i];
4539 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4540 * @hw: pointer to the HW structure
4541 * @mem: pointer to mem struct to fill out
4542 * @size: size of memory requested
4543 * @alignment: what to align the allocation to
4545 enum i40e_status_code
4546 i40e_allocate_dma_mem_d(__rte_unused struct i40e_hw *hw,
4547 struct i40e_dma_mem *mem,
4551 const struct rte_memzone *mz = NULL;
4552 char z_name[RTE_MEMZONE_NAMESIZE];
4555 return I40E_ERR_PARAM;
4557 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4558 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4559 RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4561 return I40E_ERR_NO_MEMORY;
4566 mem->zone = (const void *)mz;
4568 "memzone %s allocated with physical address: %"PRIu64,
4571 return I40E_SUCCESS;
4575 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4576 * @hw: pointer to the HW structure
4577 * @mem: ptr to mem struct to free
4579 enum i40e_status_code
4580 i40e_free_dma_mem_d(__rte_unused struct i40e_hw *hw,
4581 struct i40e_dma_mem *mem)
4584 return I40E_ERR_PARAM;
4587 "memzone %s to be freed with physical address: %"PRIu64,
4588 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4589 rte_memzone_free((const struct rte_memzone *)mem->zone);
4594 return I40E_SUCCESS;
4598 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4599 * @hw: pointer to the HW structure
4600 * @mem: pointer to mem struct to fill out
4601 * @size: size of memory requested
4603 enum i40e_status_code
4604 i40e_allocate_virt_mem_d(__rte_unused struct i40e_hw *hw,
4605 struct i40e_virt_mem *mem,
4609 return I40E_ERR_PARAM;
4612 mem->va = rte_zmalloc("i40e", size, 0);
4615 return I40E_SUCCESS;
4617 return I40E_ERR_NO_MEMORY;
4621 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4622 * @hw: pointer to the HW structure
4623 * @mem: pointer to mem struct to free
4625 enum i40e_status_code
4626 i40e_free_virt_mem_d(__rte_unused struct i40e_hw *hw,
4627 struct i40e_virt_mem *mem)
4630 return I40E_ERR_PARAM;
4635 return I40E_SUCCESS;
4639 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4641 rte_spinlock_init(&sp->spinlock);
4645 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4647 rte_spinlock_lock(&sp->spinlock);
4651 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4653 rte_spinlock_unlock(&sp->spinlock);
4657 i40e_destroy_spinlock_d(__rte_unused struct i40e_spinlock *sp)
4663 * Get the hardware capabilities, which will be parsed
4664 * and saved into struct i40e_hw.
4667 i40e_get_cap(struct i40e_hw *hw)
4669 struct i40e_aqc_list_capabilities_element_resp *buf;
4670 uint16_t len, size = 0;
4673 /* Calculate a huge enough buff for saving response data temporarily */
4674 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4675 I40E_MAX_CAP_ELE_NUM;
4676 buf = rte_zmalloc("i40e", len, 0);
4678 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4679 return I40E_ERR_NO_MEMORY;
4682 /* Get, parse the capabilities and save it to hw */
4683 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4684 i40e_aqc_opc_list_func_capabilities, NULL);
4685 if (ret != I40E_SUCCESS)
4686 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4688 /* Free the temporary buffer after being used */
4694 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4
4696 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4704 pf = (struct i40e_pf *)opaque;
4708 num = strtoul(value, &end, 0);
4709 if (errno != 0 || end == value || *end != 0) {
4710 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4711 "kept the value = %hu", value, pf->vf_nb_qp_max);
4715 if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4716 pf->vf_nb_qp_max = (uint16_t)num;
4718 /* here return 0 to make next valid same argument work */
4719 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4720 "power of 2 and equal or less than 16 !, Now it is "
4721 "kept the value = %hu", num, pf->vf_nb_qp_max);
4726 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4728 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4729 struct rte_kvargs *kvlist;
4732 /* set default queue number per VF as 4 */
4733 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4735 if (dev->device->devargs == NULL)
4738 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4742 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4743 if (!kvargs_count) {
4744 rte_kvargs_free(kvlist);
4748 if (kvargs_count > 1)
4749 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4750 "the first invalid or last valid one is used !",
4751 ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4753 rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4754 i40e_pf_parse_vf_queue_number_handler, pf);
4756 rte_kvargs_free(kvlist);
4762 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4764 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4765 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4766 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4767 uint16_t qp_count = 0, vsi_count = 0;
4769 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4770 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4774 i40e_pf_config_vf_rxq_number(dev);
4776 /* Add the parameter init for LFC */
4777 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4778 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4779 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4781 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4782 pf->max_num_vsi = hw->func_caps.num_vsis;
4783 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4784 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4786 /* FDir queue/VSI allocation */
4787 pf->fdir_qp_offset = 0;
4788 if (hw->func_caps.fd) {
4789 pf->flags |= I40E_FLAG_FDIR;
4790 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4792 pf->fdir_nb_qps = 0;
4794 qp_count += pf->fdir_nb_qps;
4797 /* LAN queue/VSI allocation */
4798 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4799 if (!hw->func_caps.rss) {
4802 pf->flags |= I40E_FLAG_RSS;
4803 if (hw->mac.type == I40E_MAC_X722)
4804 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4805 pf->lan_nb_qps = pf->lan_nb_qp_max;
4807 qp_count += pf->lan_nb_qps;
4810 /* VF queue/VSI allocation */
4811 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4812 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4813 pf->flags |= I40E_FLAG_SRIOV;
4814 pf->vf_nb_qps = pf->vf_nb_qp_max;
4815 pf->vf_num = pci_dev->max_vfs;
4817 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4818 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4823 qp_count += pf->vf_nb_qps * pf->vf_num;
4824 vsi_count += pf->vf_num;
4826 /* VMDq queue/VSI allocation */
4827 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4828 pf->vmdq_nb_qps = 0;
4829 pf->max_nb_vmdq_vsi = 0;
4830 if (hw->func_caps.vmdq) {
4831 if (qp_count < hw->func_caps.num_tx_qp &&
4832 vsi_count < hw->func_caps.num_vsis) {
4833 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4834 qp_count) / pf->vmdq_nb_qp_max;
4836 /* Limit the maximum number of VMDq vsi to the maximum
4837 * ethdev can support
4839 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4840 hw->func_caps.num_vsis - vsi_count);
4841 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4843 if (pf->max_nb_vmdq_vsi) {
4844 pf->flags |= I40E_FLAG_VMDQ;
4845 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4847 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4848 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4849 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4852 "No enough queues left for VMDq");
4855 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4858 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4859 vsi_count += pf->max_nb_vmdq_vsi;
4861 if (hw->func_caps.dcb)
4862 pf->flags |= I40E_FLAG_DCB;
4864 if (qp_count > hw->func_caps.num_tx_qp) {
4866 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4867 qp_count, hw->func_caps.num_tx_qp);
4870 if (vsi_count > hw->func_caps.num_vsis) {
4872 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4873 vsi_count, hw->func_caps.num_vsis);
4881 i40e_pf_get_switch_config(struct i40e_pf *pf)
4883 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4884 struct i40e_aqc_get_switch_config_resp *switch_config;
4885 struct i40e_aqc_switch_config_element_resp *element;
4886 uint16_t start_seid = 0, num_reported;
4889 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4890 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4891 if (!switch_config) {
4892 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4896 /* Get the switch configurations */
4897 ret = i40e_aq_get_switch_config(hw, switch_config,
4898 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4899 if (ret != I40E_SUCCESS) {
4900 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4903 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4904 if (num_reported != 1) { /* The number should be 1 */
4905 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4909 /* Parse the switch configuration elements */
4910 element = &(switch_config->element[0]);
4911 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4912 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4913 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4915 PMD_DRV_LOG(INFO, "Unknown element type");
4918 rte_free(switch_config);
4924 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4927 struct pool_entry *entry;
4929 if (pool == NULL || num == 0)
4932 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4933 if (entry == NULL) {
4934 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4938 /* queue heap initialize */
4939 pool->num_free = num;
4940 pool->num_alloc = 0;
4942 LIST_INIT(&pool->alloc_list);
4943 LIST_INIT(&pool->free_list);
4945 /* Initialize element */
4949 LIST_INSERT_HEAD(&pool->free_list, entry, next);
4954 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4956 struct pool_entry *entry, *next_entry;
4961 for (entry = LIST_FIRST(&pool->alloc_list);
4962 entry && (next_entry = LIST_NEXT(entry, next), 1);
4963 entry = next_entry) {
4964 LIST_REMOVE(entry, next);
4968 for (entry = LIST_FIRST(&pool->free_list);
4969 entry && (next_entry = LIST_NEXT(entry, next), 1);
4970 entry = next_entry) {
4971 LIST_REMOVE(entry, next);
4976 pool->num_alloc = 0;
4978 LIST_INIT(&pool->alloc_list);
4979 LIST_INIT(&pool->free_list);
4983 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4986 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4987 uint32_t pool_offset;
4992 PMD_DRV_LOG(ERR, "Invalid parameter");
4996 pool_offset = base - pool->base;
4997 /* Lookup in alloc list */
4998 LIST_FOREACH(entry, &pool->alloc_list, next) {
4999 if (entry->base == pool_offset) {
5000 valid_entry = entry;
5001 LIST_REMOVE(entry, next);
5006 /* Not find, return */
5007 if (valid_entry == NULL) {
5008 PMD_DRV_LOG(ERR, "Failed to find entry");
5013 * Found it, move it to free list and try to merge.
5014 * In order to make merge easier, always sort it by qbase.
5015 * Find adjacent prev and last entries.
5018 LIST_FOREACH(entry, &pool->free_list, next) {
5019 if (entry->base > valid_entry->base) {
5027 len = valid_entry->len;
5028 /* Try to merge with next one*/
5030 /* Merge with next one */
5031 if (valid_entry->base + len == next->base) {
5032 next->base = valid_entry->base;
5034 rte_free(valid_entry);
5041 /* Merge with previous one */
5042 if (prev->base + prev->len == valid_entry->base) {
5044 /* If it merge with next one, remove next node */
5046 LIST_REMOVE(valid_entry, next);
5047 rte_free(valid_entry);
5050 rte_free(valid_entry);
5057 /* Not find any entry to merge, insert */
5060 LIST_INSERT_AFTER(prev, valid_entry, next);
5061 else if (next != NULL)
5062 LIST_INSERT_BEFORE(next, valid_entry, next);
5063 else /* It's empty list, insert to head */
5064 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
5067 pool->num_free += len;
5068 pool->num_alloc -= len;
5074 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
5077 struct pool_entry *entry, *valid_entry;
5079 if (pool == NULL || num == 0) {
5080 PMD_DRV_LOG(ERR, "Invalid parameter");
5084 if (pool->num_free < num) {
5085 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
5086 num, pool->num_free);
5091 /* Lookup in free list and find most fit one */
5092 LIST_FOREACH(entry, &pool->free_list, next) {
5093 if (entry->len >= num) {
5095 if (entry->len == num) {
5096 valid_entry = entry;
5099 if (valid_entry == NULL || valid_entry->len > entry->len)
5100 valid_entry = entry;
5104 /* Not find one to satisfy the request, return */
5105 if (valid_entry == NULL) {
5106 PMD_DRV_LOG(ERR, "No valid entry found");
5110 * The entry have equal queue number as requested,
5111 * remove it from alloc_list.
5113 if (valid_entry->len == num) {
5114 LIST_REMOVE(valid_entry, next);
5117 * The entry have more numbers than requested,
5118 * create a new entry for alloc_list and minus its
5119 * queue base and number in free_list.
5121 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
5122 if (entry == NULL) {
5124 "Failed to allocate memory for resource pool");
5127 entry->base = valid_entry->base;
5129 valid_entry->base += num;
5130 valid_entry->len -= num;
5131 valid_entry = entry;
5134 /* Insert it into alloc list, not sorted */
5135 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
5137 pool->num_free -= valid_entry->len;
5138 pool->num_alloc += valid_entry->len;
5140 return valid_entry->base + pool->base;
5144 * bitmap_is_subset - Check whether src2 is subset of src1
5147 bitmap_is_subset(uint8_t src1, uint8_t src2)
5149 return !((src1 ^ src2) & src2);
5152 static enum i40e_status_code
5153 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5155 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5157 /* If DCB is not supported, only default TC is supported */
5158 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
5159 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
5160 return I40E_NOT_SUPPORTED;
5163 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
5165 "Enabled TC map 0x%x not applicable to HW support 0x%x",
5166 hw->func_caps.enabled_tcmap, enabled_tcmap);
5167 return I40E_NOT_SUPPORTED;
5169 return I40E_SUCCESS;
5173 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
5174 struct i40e_vsi_vlan_pvid_info *info)
5177 struct i40e_vsi_context ctxt;
5178 uint8_t vlan_flags = 0;
5181 if (vsi == NULL || info == NULL) {
5182 PMD_DRV_LOG(ERR, "invalid parameters");
5183 return I40E_ERR_PARAM;
5187 vsi->info.pvid = info->config.pvid;
5189 * If insert pvid is enabled, only tagged pkts are
5190 * allowed to be sent out.
5192 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
5193 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5196 if (info->config.reject.tagged == 0)
5197 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5199 if (info->config.reject.untagged == 0)
5200 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
5202 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
5203 I40E_AQ_VSI_PVLAN_MODE_MASK);
5204 vsi->info.port_vlan_flags |= vlan_flags;
5205 vsi->info.valid_sections =
5206 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5207 memset(&ctxt, 0, sizeof(ctxt));
5208 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5209 ctxt.seid = vsi->seid;
5211 hw = I40E_VSI_TO_HW(vsi);
5212 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5213 if (ret != I40E_SUCCESS)
5214 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5220 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5222 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5224 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
5226 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5227 if (ret != I40E_SUCCESS)
5231 PMD_DRV_LOG(ERR, "seid not valid");
5235 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
5236 tc_bw_data.tc_valid_bits = enabled_tcmap;
5237 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5238 tc_bw_data.tc_bw_credits[i] =
5239 (enabled_tcmap & (1 << i)) ? 1 : 0;
5241 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5242 if (ret != I40E_SUCCESS) {
5243 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5247 rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5248 sizeof(vsi->info.qs_handle));
5249 return I40E_SUCCESS;
5252 static enum i40e_status_code
5253 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5254 struct i40e_aqc_vsi_properties_data *info,
5255 uint8_t enabled_tcmap)
5257 enum i40e_status_code ret;
5258 int i, total_tc = 0;
5259 uint16_t qpnum_per_tc, bsf, qp_idx;
5261 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5262 if (ret != I40E_SUCCESS)
5265 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5266 if (enabled_tcmap & (1 << i))
5270 vsi->enabled_tc = enabled_tcmap;
5272 /* Number of queues per enabled TC */
5273 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5274 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5275 bsf = rte_bsf32(qpnum_per_tc);
5277 /* Adjust the queue number to actual queues that can be applied */
5278 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5279 vsi->nb_qps = qpnum_per_tc * total_tc;
5282 * Configure TC and queue mapping parameters, for enabled TC,
5283 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5284 * default queue will serve it.
5287 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5288 if (vsi->enabled_tc & (1 << i)) {
5289 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5290 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5291 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5292 qp_idx += qpnum_per_tc;
5294 info->tc_mapping[i] = 0;
5297 /* Associate queue number with VSI */
5298 if (vsi->type == I40E_VSI_SRIOV) {
5299 info->mapping_flags |=
5300 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5301 for (i = 0; i < vsi->nb_qps; i++)
5302 info->queue_mapping[i] =
5303 rte_cpu_to_le_16(vsi->base_queue + i);
5305 info->mapping_flags |=
5306 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5307 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5309 info->valid_sections |=
5310 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5312 return I40E_SUCCESS;
5316 i40e_veb_release(struct i40e_veb *veb)
5318 struct i40e_vsi *vsi;
5324 if (!TAILQ_EMPTY(&veb->head)) {
5325 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5328 /* associate_vsi field is NULL for floating VEB */
5329 if (veb->associate_vsi != NULL) {
5330 vsi = veb->associate_vsi;
5331 hw = I40E_VSI_TO_HW(vsi);
5333 vsi->uplink_seid = veb->uplink_seid;
5336 veb->associate_pf->main_vsi->floating_veb = NULL;
5337 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5340 i40e_aq_delete_element(hw, veb->seid, NULL);
5342 return I40E_SUCCESS;
5346 static struct i40e_veb *
5347 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5349 struct i40e_veb *veb;
5355 "veb setup failed, associated PF shouldn't null");
5358 hw = I40E_PF_TO_HW(pf);
5360 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5362 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5366 veb->associate_vsi = vsi;
5367 veb->associate_pf = pf;
5368 TAILQ_INIT(&veb->head);
5369 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5371 /* create floating veb if vsi is NULL */
5373 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5374 I40E_DEFAULT_TCMAP, false,
5375 &veb->seid, false, NULL);
5377 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5378 true, &veb->seid, false, NULL);
5381 if (ret != I40E_SUCCESS) {
5382 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5383 hw->aq.asq_last_status);
5386 veb->enabled_tc = I40E_DEFAULT_TCMAP;
5388 /* get statistics index */
5389 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5390 &veb->stats_idx, NULL, NULL, NULL);
5391 if (ret != I40E_SUCCESS) {
5392 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5393 hw->aq.asq_last_status);
5396 /* Get VEB bandwidth, to be implemented */
5397 /* Now associated vsi binding to the VEB, set uplink to this VEB */
5399 vsi->uplink_seid = veb->seid;
5408 i40e_vsi_release(struct i40e_vsi *vsi)
5412 struct i40e_vsi_list *vsi_list;
5415 struct i40e_mac_filter *f;
5416 uint16_t user_param;
5419 return I40E_SUCCESS;
5424 user_param = vsi->user_param;
5426 pf = I40E_VSI_TO_PF(vsi);
5427 hw = I40E_VSI_TO_HW(vsi);
5429 /* VSI has child to attach, release child first */
5431 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5432 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5435 i40e_veb_release(vsi->veb);
5438 if (vsi->floating_veb) {
5439 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5440 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5445 /* Remove all macvlan filters of the VSI */
5446 i40e_vsi_remove_all_macvlan_filter(vsi);
5447 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5450 if (vsi->type != I40E_VSI_MAIN &&
5451 ((vsi->type != I40E_VSI_SRIOV) ||
5452 !pf->floating_veb_list[user_param])) {
5453 /* Remove vsi from parent's sibling list */
5454 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5455 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5456 return I40E_ERR_PARAM;
5458 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5459 &vsi->sib_vsi_list, list);
5461 /* Remove all switch element of the VSI */
5462 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5463 if (ret != I40E_SUCCESS)
5464 PMD_DRV_LOG(ERR, "Failed to delete element");
5467 if ((vsi->type == I40E_VSI_SRIOV) &&
5468 pf->floating_veb_list[user_param]) {
5469 /* Remove vsi from parent's sibling list */
5470 if (vsi->parent_vsi == NULL ||
5471 vsi->parent_vsi->floating_veb == NULL) {
5472 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5473 return I40E_ERR_PARAM;
5475 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5476 &vsi->sib_vsi_list, list);
5478 /* Remove all switch element of the VSI */
5479 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5480 if (ret != I40E_SUCCESS)
5481 PMD_DRV_LOG(ERR, "Failed to delete element");
5484 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5486 if (vsi->type != I40E_VSI_SRIOV)
5487 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5490 return I40E_SUCCESS;
5494 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5496 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5497 struct i40e_aqc_remove_macvlan_element_data def_filter;
5498 struct i40e_mac_filter_info filter;
5501 if (vsi->type != I40E_VSI_MAIN)
5502 return I40E_ERR_CONFIG;
5503 memset(&def_filter, 0, sizeof(def_filter));
5504 rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5506 def_filter.vlan_tag = 0;
5507 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5508 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5509 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5510 if (ret != I40E_SUCCESS) {
5511 struct i40e_mac_filter *f;
5512 struct rte_ether_addr *mac;
5515 "Cannot remove the default macvlan filter");
5516 /* It needs to add the permanent mac into mac list */
5517 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5519 PMD_DRV_LOG(ERR, "failed to allocate memory");
5520 return I40E_ERR_NO_MEMORY;
5522 mac = &f->mac_info.mac_addr;
5523 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5525 f->mac_info.filter_type = I40E_MACVLAN_PERFECT_MATCH;
5526 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5531 rte_memcpy(&filter.mac_addr,
5532 (struct rte_ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5533 filter.filter_type = I40E_MACVLAN_PERFECT_MATCH;
5534 return i40e_vsi_add_mac(vsi, &filter);
5538 * i40e_vsi_get_bw_config - Query VSI BW Information
5539 * @vsi: the VSI to be queried
5541 * Returns 0 on success, negative value on failure
5543 static enum i40e_status_code
5544 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5546 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5547 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5548 struct i40e_hw *hw = &vsi->adapter->hw;
5553 memset(&bw_config, 0, sizeof(bw_config));
5554 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5555 if (ret != I40E_SUCCESS) {
5556 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5557 hw->aq.asq_last_status);
5561 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5562 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5563 &ets_sla_config, NULL);
5564 if (ret != I40E_SUCCESS) {
5566 "VSI failed to get TC bandwdith configuration %u",
5567 hw->aq.asq_last_status);
5571 /* store and print out BW info */
5572 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5573 vsi->bw_info.bw_max = bw_config.max_bw;
5574 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5575 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5576 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5577 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5579 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5580 vsi->bw_info.bw_ets_share_credits[i] =
5581 ets_sla_config.share_credits[i];
5582 vsi->bw_info.bw_ets_credits[i] =
5583 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5584 /* 4 bits per TC, 4th bit is reserved */
5585 vsi->bw_info.bw_ets_max[i] =
5586 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5587 RTE_LEN2MASK(3, uint8_t));
5588 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5589 vsi->bw_info.bw_ets_share_credits[i]);
5590 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5591 vsi->bw_info.bw_ets_credits[i]);
5592 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5593 vsi->bw_info.bw_ets_max[i]);
5596 return I40E_SUCCESS;
5599 /* i40e_enable_pf_lb
5600 * @pf: pointer to the pf structure
5602 * allow loopback on pf
5605 i40e_enable_pf_lb(struct i40e_pf *pf)
5607 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5608 struct i40e_vsi_context ctxt;
5611 /* Use the FW API if FW >= v5.0 */
5612 if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
5613 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5617 memset(&ctxt, 0, sizeof(ctxt));
5618 ctxt.seid = pf->main_vsi_seid;
5619 ctxt.pf_num = hw->pf_id;
5620 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5622 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5623 ret, hw->aq.asq_last_status);
5626 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5627 ctxt.info.valid_sections =
5628 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5629 ctxt.info.switch_id |=
5630 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5632 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5634 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5635 hw->aq.asq_last_status);
5640 i40e_vsi_setup(struct i40e_pf *pf,
5641 enum i40e_vsi_type type,
5642 struct i40e_vsi *uplink_vsi,
5643 uint16_t user_param)
5645 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5646 struct i40e_vsi *vsi;
5647 struct i40e_mac_filter_info filter;
5649 struct i40e_vsi_context ctxt;
5650 struct rte_ether_addr broadcast =
5651 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5653 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5654 uplink_vsi == NULL) {
5656 "VSI setup failed, VSI link shouldn't be NULL");
5660 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5662 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5667 * 1.type is not MAIN and uplink vsi is not NULL
5668 * If uplink vsi didn't setup VEB, create one first under veb field
5669 * 2.type is SRIOV and the uplink is NULL
5670 * If floating VEB is NULL, create one veb under floating veb field
5673 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5674 uplink_vsi->veb == NULL) {
5675 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5677 if (uplink_vsi->veb == NULL) {
5678 PMD_DRV_LOG(ERR, "VEB setup failed");
5681 /* set ALLOWLOOPBACk on pf, when veb is created */
5682 i40e_enable_pf_lb(pf);
5685 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5686 pf->main_vsi->floating_veb == NULL) {
5687 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5689 if (pf->main_vsi->floating_veb == NULL) {
5690 PMD_DRV_LOG(ERR, "VEB setup failed");
5695 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5697 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5700 TAILQ_INIT(&vsi->mac_list);
5702 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5703 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5704 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5705 vsi->user_param = user_param;
5706 vsi->vlan_anti_spoof_on = 0;
5707 vsi->vlan_filter_on = 0;
5708 /* Allocate queues */
5709 switch (vsi->type) {
5710 case I40E_VSI_MAIN :
5711 vsi->nb_qps = pf->lan_nb_qps;
5713 case I40E_VSI_SRIOV :
5714 vsi->nb_qps = pf->vf_nb_qps;
5716 case I40E_VSI_VMDQ2:
5717 vsi->nb_qps = pf->vmdq_nb_qps;
5720 vsi->nb_qps = pf->fdir_nb_qps;
5726 * The filter status descriptor is reported in rx queue 0,
5727 * while the tx queue for fdir filter programming has no
5728 * such constraints, can be non-zero queues.
5729 * To simplify it, choose FDIR vsi use queue 0 pair.
5730 * To make sure it will use queue 0 pair, queue allocation
5731 * need be done before this function is called
5733 if (type != I40E_VSI_FDIR) {
5734 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5736 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5740 vsi->base_queue = ret;
5742 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5744 /* VF has MSIX interrupt in VF range, don't allocate here */
5745 if (type == I40E_VSI_MAIN) {
5746 if (pf->support_multi_driver) {
5747 /* If support multi-driver, need to use INT0 instead of
5748 * allocating from msix pool. The Msix pool is init from
5749 * INT1, so it's OK just set msix_intr to 0 and nb_msix
5750 * to 1 without calling i40e_res_pool_alloc.
5755 ret = i40e_res_pool_alloc(&pf->msix_pool,
5756 RTE_MIN(vsi->nb_qps,
5757 RTE_MAX_RXTX_INTR_VEC_ID));
5760 "VSI MAIN %d get heap failed %d",
5762 goto fail_queue_alloc;
5764 vsi->msix_intr = ret;
5765 vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5766 RTE_MAX_RXTX_INTR_VEC_ID);
5768 } else if (type != I40E_VSI_SRIOV) {
5769 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5771 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5772 if (type != I40E_VSI_FDIR)
5773 goto fail_queue_alloc;
5777 vsi->msix_intr = ret;
5786 if (type == I40E_VSI_MAIN) {
5787 /* For main VSI, no need to add since it's default one */
5788 vsi->uplink_seid = pf->mac_seid;
5789 vsi->seid = pf->main_vsi_seid;
5790 /* Bind queues with specific MSIX interrupt */
5792 * Needs 2 interrupt at least, one for misc cause which will
5793 * enabled from OS side, Another for queues binding the
5794 * interrupt from device side only.
5797 /* Get default VSI parameters from hardware */
5798 memset(&ctxt, 0, sizeof(ctxt));
5799 ctxt.seid = vsi->seid;
5800 ctxt.pf_num = hw->pf_id;
5801 ctxt.uplink_seid = vsi->uplink_seid;
5803 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5804 if (ret != I40E_SUCCESS) {
5805 PMD_DRV_LOG(ERR, "Failed to get VSI params");
5806 goto fail_msix_alloc;
5808 rte_memcpy(&vsi->info, &ctxt.info,
5809 sizeof(struct i40e_aqc_vsi_properties_data));
5810 vsi->vsi_id = ctxt.vsi_number;
5811 vsi->info.valid_sections = 0;
5813 /* Configure tc, enabled TC0 only */
5814 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5816 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5817 goto fail_msix_alloc;
5820 /* TC, queue mapping */
5821 memset(&ctxt, 0, sizeof(ctxt));
5822 vsi->info.valid_sections |=
5823 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5824 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5825 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5826 rte_memcpy(&ctxt.info, &vsi->info,
5827 sizeof(struct i40e_aqc_vsi_properties_data));
5828 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5829 I40E_DEFAULT_TCMAP);
5830 if (ret != I40E_SUCCESS) {
5832 "Failed to configure TC queue mapping");
5833 goto fail_msix_alloc;
5835 ctxt.seid = vsi->seid;
5836 ctxt.pf_num = hw->pf_id;
5837 ctxt.uplink_seid = vsi->uplink_seid;
5840 /* Update VSI parameters */
5841 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5842 if (ret != I40E_SUCCESS) {
5843 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5844 goto fail_msix_alloc;
5847 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5848 sizeof(vsi->info.tc_mapping));
5849 rte_memcpy(&vsi->info.queue_mapping,
5850 &ctxt.info.queue_mapping,
5851 sizeof(vsi->info.queue_mapping));
5852 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5853 vsi->info.valid_sections = 0;
5855 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5859 * Updating default filter settings are necessary to prevent
5860 * reception of tagged packets.
5861 * Some old firmware configurations load a default macvlan
5862 * filter which accepts both tagged and untagged packets.
5863 * The updating is to use a normal filter instead if needed.
5864 * For NVM 4.2.2 or after, the updating is not needed anymore.
5865 * The firmware with correct configurations load the default
5866 * macvlan filter which is expected and cannot be removed.
5868 i40e_update_default_filter_setting(vsi);
5869 i40e_config_qinq(hw, vsi);
5870 } else if (type == I40E_VSI_SRIOV) {
5871 memset(&ctxt, 0, sizeof(ctxt));
5873 * For other VSI, the uplink_seid equals to uplink VSI's
5874 * uplink_seid since they share same VEB
5876 if (uplink_vsi == NULL)
5877 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5879 vsi->uplink_seid = uplink_vsi->uplink_seid;
5880 ctxt.pf_num = hw->pf_id;
5881 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5882 ctxt.uplink_seid = vsi->uplink_seid;
5883 ctxt.connection_type = 0x1;
5884 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5886 /* Use the VEB configuration if FW >= v5.0 */
5887 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
5888 /* Configure switch ID */
5889 ctxt.info.valid_sections |=
5890 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5891 ctxt.info.switch_id =
5892 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5895 /* Configure port/vlan */
5896 ctxt.info.valid_sections |=
5897 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5898 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5899 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5900 hw->func_caps.enabled_tcmap);
5901 if (ret != I40E_SUCCESS) {
5903 "Failed to configure TC queue mapping");
5904 goto fail_msix_alloc;
5907 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5908 ctxt.info.valid_sections |=
5909 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5911 * Since VSI is not created yet, only configure parameter,
5912 * will add vsi below.
5915 i40e_config_qinq(hw, vsi);
5916 } else if (type == I40E_VSI_VMDQ2) {
5917 memset(&ctxt, 0, sizeof(ctxt));
5919 * For other VSI, the uplink_seid equals to uplink VSI's
5920 * uplink_seid since they share same VEB
5922 vsi->uplink_seid = uplink_vsi->uplink_seid;
5923 ctxt.pf_num = hw->pf_id;
5925 ctxt.uplink_seid = vsi->uplink_seid;
5926 ctxt.connection_type = 0x1;
5927 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5929 ctxt.info.valid_sections |=
5930 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5931 /* user_param carries flag to enable loop back */
5933 ctxt.info.switch_id =
5934 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5935 ctxt.info.switch_id |=
5936 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5939 /* Configure port/vlan */
5940 ctxt.info.valid_sections |=
5941 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5942 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5943 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5944 I40E_DEFAULT_TCMAP);
5945 if (ret != I40E_SUCCESS) {
5947 "Failed to configure TC queue mapping");
5948 goto fail_msix_alloc;
5950 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5951 ctxt.info.valid_sections |=
5952 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5953 } else if (type == I40E_VSI_FDIR) {
5954 memset(&ctxt, 0, sizeof(ctxt));
5955 vsi->uplink_seid = uplink_vsi->uplink_seid;
5956 ctxt.pf_num = hw->pf_id;
5958 ctxt.uplink_seid = vsi->uplink_seid;
5959 ctxt.connection_type = 0x1; /* regular data port */
5960 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5961 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5962 I40E_DEFAULT_TCMAP);
5963 if (ret != I40E_SUCCESS) {
5965 "Failed to configure TC queue mapping.");
5966 goto fail_msix_alloc;
5968 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5969 ctxt.info.valid_sections |=
5970 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5972 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5973 goto fail_msix_alloc;
5976 if (vsi->type != I40E_VSI_MAIN) {
5977 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5978 if (ret != I40E_SUCCESS) {
5979 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5980 hw->aq.asq_last_status);
5981 goto fail_msix_alloc;
5983 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5984 vsi->info.valid_sections = 0;
5985 vsi->seid = ctxt.seid;
5986 vsi->vsi_id = ctxt.vsi_number;
5987 vsi->sib_vsi_list.vsi = vsi;
5988 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5989 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5990 &vsi->sib_vsi_list, list);
5992 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5993 &vsi->sib_vsi_list, list);
5997 /* MAC/VLAN configuration */
5998 rte_memcpy(&filter.mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
5999 filter.filter_type = I40E_MACVLAN_PERFECT_MATCH;
6001 ret = i40e_vsi_add_mac(vsi, &filter);
6002 if (ret != I40E_SUCCESS) {
6003 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
6004 goto fail_msix_alloc;
6007 /* Get VSI BW information */
6008 i40e_vsi_get_bw_config(vsi);
6011 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
6013 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
6019 /* Configure vlan filter on or off */
6021 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
6024 struct i40e_mac_filter *f;
6026 struct i40e_mac_filter_info *mac_filter;
6027 enum i40e_mac_filter_type desired_filter;
6028 int ret = I40E_SUCCESS;
6031 /* Filter to match MAC and VLAN */
6032 desired_filter = I40E_MACVLAN_PERFECT_MATCH;
6034 /* Filter to match only MAC */
6035 desired_filter = I40E_MAC_PERFECT_MATCH;
6040 mac_filter = rte_zmalloc("mac_filter_info_data",
6041 num * sizeof(*mac_filter), 0);
6042 if (mac_filter == NULL) {
6043 PMD_DRV_LOG(ERR, "failed to allocate memory");
6044 return I40E_ERR_NO_MEMORY;
6049 /* Remove all existing mac */
6050 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
6051 mac_filter[i] = f->mac_info;
6052 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
6054 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6055 on ? "enable" : "disable");
6061 /* Override with new filter */
6062 for (i = 0; i < num; i++) {
6063 mac_filter[i].filter_type = desired_filter;
6064 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
6066 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6067 on ? "enable" : "disable");
6073 rte_free(mac_filter);
6077 /* Configure vlan stripping on or off */
6079 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
6081 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6082 struct i40e_vsi_context ctxt;
6084 int ret = I40E_SUCCESS;
6086 /* Check if it has been already on or off */
6087 if (vsi->info.valid_sections &
6088 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
6090 if ((vsi->info.port_vlan_flags &
6091 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
6092 return 0; /* already on */
6094 if ((vsi->info.port_vlan_flags &
6095 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
6096 I40E_AQ_VSI_PVLAN_EMOD_MASK)
6097 return 0; /* already off */
6102 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
6104 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
6105 vsi->info.valid_sections =
6106 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
6107 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
6108 vsi->info.port_vlan_flags |= vlan_flags;
6109 ctxt.seid = vsi->seid;
6110 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
6111 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6113 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
6114 on ? "enable" : "disable");
6120 i40e_dev_init_vlan(struct rte_eth_dev *dev)
6122 struct rte_eth_dev_data *data = dev->data;
6126 /* Apply vlan offload setting */
6127 mask = ETH_VLAN_STRIP_MASK |
6128 ETH_QINQ_STRIP_MASK |
6129 ETH_VLAN_FILTER_MASK |
6130 ETH_VLAN_EXTEND_MASK;
6131 ret = i40e_vlan_offload_set(dev, mask);
6133 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
6137 /* Apply pvid setting */
6138 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
6139 data->dev_conf.txmode.hw_vlan_insert_pvid);
6141 PMD_DRV_LOG(INFO, "Failed to update VSI params");
6147 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
6149 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6151 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
6155 i40e_update_flow_control(struct i40e_hw *hw)
6157 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
6158 struct i40e_link_status link_status;
6159 uint32_t rxfc = 0, txfc = 0, reg;
6163 memset(&link_status, 0, sizeof(link_status));
6164 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
6165 if (ret != I40E_SUCCESS) {
6166 PMD_DRV_LOG(ERR, "Failed to get link status information");
6167 goto write_reg; /* Disable flow control */
6170 an_info = hw->phy.link_info.an_info;
6171 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
6172 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
6173 ret = I40E_ERR_NOT_READY;
6174 goto write_reg; /* Disable flow control */
6177 * If link auto negotiation is enabled, flow control needs to
6178 * be configured according to it
6180 switch (an_info & I40E_LINK_PAUSE_RXTX) {
6181 case I40E_LINK_PAUSE_RXTX:
6184 hw->fc.current_mode = I40E_FC_FULL;
6186 case I40E_AQ_LINK_PAUSE_RX:
6188 hw->fc.current_mode = I40E_FC_RX_PAUSE;
6190 case I40E_AQ_LINK_PAUSE_TX:
6192 hw->fc.current_mode = I40E_FC_TX_PAUSE;
6195 hw->fc.current_mode = I40E_FC_NONE;
6200 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
6201 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
6202 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
6203 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
6204 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
6205 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
6212 i40e_pf_setup(struct i40e_pf *pf)
6214 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6215 struct i40e_filter_control_settings settings;
6216 struct i40e_vsi *vsi;
6219 /* Clear all stats counters */
6220 pf->offset_loaded = FALSE;
6221 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
6222 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
6223 memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
6224 memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
6226 ret = i40e_pf_get_switch_config(pf);
6227 if (ret != I40E_SUCCESS) {
6228 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
6232 ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
6234 PMD_INIT_LOG(WARNING,
6235 "failed to allocate switch domain for device %d", ret);
6237 if (pf->flags & I40E_FLAG_FDIR) {
6238 /* make queue allocated first, let FDIR use queue pair 0*/
6239 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
6240 if (ret != I40E_FDIR_QUEUE_ID) {
6242 "queue allocation fails for FDIR: ret =%d",
6244 pf->flags &= ~I40E_FLAG_FDIR;
6247 /* main VSI setup */
6248 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6250 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6251 return I40E_ERR_NOT_READY;
6255 /* Configure filter control */
6256 memset(&settings, 0, sizeof(settings));
6257 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
6258 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6259 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
6260 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6262 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6263 hw->func_caps.rss_table_size);
6264 return I40E_ERR_PARAM;
6266 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6267 hw->func_caps.rss_table_size);
6268 pf->hash_lut_size = hw->func_caps.rss_table_size;
6270 /* Enable ethtype and macvlan filters */
6271 settings.enable_ethtype = TRUE;
6272 settings.enable_macvlan = TRUE;
6273 ret = i40e_set_filter_control(hw, &settings);
6275 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6278 /* Update flow control according to the auto negotiation */
6279 i40e_update_flow_control(hw);
6281 return I40E_SUCCESS;
6285 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6291 * Set or clear TX Queue Disable flags,
6292 * which is required by hardware.
6294 i40e_pre_tx_queue_cfg(hw, q_idx, on);
6295 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6297 /* Wait until the request is finished */
6298 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6299 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6300 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6301 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6302 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6308 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6309 return I40E_SUCCESS; /* already on, skip next steps */
6311 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6312 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6314 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6315 return I40E_SUCCESS; /* already off, skip next steps */
6316 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6318 /* Write the register */
6319 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6320 /* Check the result */
6321 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6322 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6323 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6325 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6326 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6329 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6330 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6334 /* Check if it is timeout */
6335 if (j >= I40E_CHK_Q_ENA_COUNT) {
6336 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6337 (on ? "enable" : "disable"), q_idx);
6338 return I40E_ERR_TIMEOUT;
6341 return I40E_SUCCESS;
6345 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6350 /* Wait until the request is finished */
6351 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6352 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6353 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6354 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6355 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6360 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6361 return I40E_SUCCESS; /* Already on, skip next steps */
6362 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6364 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6365 return I40E_SUCCESS; /* Already off, skip next steps */
6366 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6369 /* Write the register */
6370 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6371 /* Check the result */
6372 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6373 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6374 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6376 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6377 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6380 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6381 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6386 /* Check if it is timeout */
6387 if (j >= I40E_CHK_Q_ENA_COUNT) {
6388 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6389 (on ? "enable" : "disable"), q_idx);
6390 return I40E_ERR_TIMEOUT;
6393 return I40E_SUCCESS;
6396 /* Initialize VSI for TX */
6398 i40e_dev_tx_init(struct i40e_pf *pf)
6400 struct rte_eth_dev_data *data = pf->dev_data;
6402 uint32_t ret = I40E_SUCCESS;
6403 struct i40e_tx_queue *txq;
6405 for (i = 0; i < data->nb_tx_queues; i++) {
6406 txq = data->tx_queues[i];
6407 if (!txq || !txq->q_set)
6409 ret = i40e_tx_queue_init(txq);
6410 if (ret != I40E_SUCCESS)
6413 if (ret == I40E_SUCCESS)
6414 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6420 /* Initialize VSI for RX */
6422 i40e_dev_rx_init(struct i40e_pf *pf)
6424 struct rte_eth_dev_data *data = pf->dev_data;
6425 int ret = I40E_SUCCESS;
6427 struct i40e_rx_queue *rxq;
6429 i40e_pf_config_rss(pf);
6430 for (i = 0; i < data->nb_rx_queues; i++) {
6431 rxq = data->rx_queues[i];
6432 if (!rxq || !rxq->q_set)
6435 ret = i40e_rx_queue_init(rxq);
6436 if (ret != I40E_SUCCESS) {
6438 "Failed to do RX queue initialization");
6442 if (ret == I40E_SUCCESS)
6443 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6450 i40e_dev_rxtx_init(struct i40e_pf *pf)
6454 err = i40e_dev_tx_init(pf);
6456 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6459 err = i40e_dev_rx_init(pf);
6461 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6469 i40e_vmdq_setup(struct rte_eth_dev *dev)
6471 struct rte_eth_conf *conf = &dev->data->dev_conf;
6472 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6473 int i, err, conf_vsis, j, loop;
6474 struct i40e_vsi *vsi;
6475 struct i40e_vmdq_info *vmdq_info;
6476 struct rte_eth_vmdq_rx_conf *vmdq_conf;
6477 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6480 * Disable interrupt to avoid message from VF. Furthermore, it will
6481 * avoid race condition in VSI creation/destroy.
6483 i40e_pf_disable_irq0(hw);
6485 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6486 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6490 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6491 if (conf_vsis > pf->max_nb_vmdq_vsi) {
6492 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6493 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6494 pf->max_nb_vmdq_vsi);
6498 if (pf->vmdq != NULL) {
6499 PMD_INIT_LOG(INFO, "VMDQ already configured");
6503 pf->vmdq = rte_zmalloc("vmdq_info_struct",
6504 sizeof(*vmdq_info) * conf_vsis, 0);
6506 if (pf->vmdq == NULL) {
6507 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6511 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6513 /* Create VMDQ VSI */
6514 for (i = 0; i < conf_vsis; i++) {
6515 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6516 vmdq_conf->enable_loop_back);
6518 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6522 vmdq_info = &pf->vmdq[i];
6524 vmdq_info->vsi = vsi;
6526 pf->nb_cfg_vmdq_vsi = conf_vsis;
6528 /* Configure Vlan */
6529 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6530 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6531 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6532 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6533 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6534 vmdq_conf->pool_map[i].vlan_id, j);
6536 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6537 vmdq_conf->pool_map[i].vlan_id);
6539 PMD_INIT_LOG(ERR, "Failed to add vlan");
6547 i40e_pf_enable_irq0(hw);
6552 for (i = 0; i < conf_vsis; i++)
6553 if (pf->vmdq[i].vsi == NULL)
6556 i40e_vsi_release(pf->vmdq[i].vsi);
6560 i40e_pf_enable_irq0(hw);
6565 i40e_stat_update_32(struct i40e_hw *hw,
6573 new_data = (uint64_t)I40E_READ_REG(hw, reg);
6577 if (new_data >= *offset)
6578 *stat = (uint64_t)(new_data - *offset);
6580 *stat = (uint64_t)((new_data +
6581 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6585 i40e_stat_update_48(struct i40e_hw *hw,
6594 if (hw->device_id == I40E_DEV_ID_QEMU) {
6595 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6596 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6597 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6599 new_data = I40E_READ_REG64(hw, loreg);
6605 if (new_data >= *offset)
6606 *stat = new_data - *offset;
6608 *stat = (uint64_t)((new_data +
6609 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6611 *stat &= I40E_48_BIT_MASK;
6616 i40e_pf_disable_irq0(struct i40e_hw *hw)
6618 /* Disable all interrupt types */
6619 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6620 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6621 I40E_WRITE_FLUSH(hw);
6626 i40e_pf_enable_irq0(struct i40e_hw *hw)
6628 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6629 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6630 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6631 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6632 I40E_WRITE_FLUSH(hw);
6636 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6638 /* read pending request and disable first */
6639 i40e_pf_disable_irq0(hw);
6640 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6641 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6642 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6645 /* Link no queues with irq0 */
6646 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6647 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6651 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6653 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6654 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6657 uint32_t index, offset, val;
6662 * Try to find which VF trigger a reset, use absolute VF id to access
6663 * since the reg is global register.
6665 for (i = 0; i < pf->vf_num; i++) {
6666 abs_vf_id = hw->func_caps.vf_base_id + i;
6667 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6668 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6669 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6670 /* VFR event occurred */
6671 if (val & (0x1 << offset)) {
6674 /* Clear the event first */
6675 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6677 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6679 * Only notify a VF reset event occurred,
6680 * don't trigger another SW reset
6682 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6683 if (ret != I40E_SUCCESS)
6684 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6690 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6692 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6695 for (i = 0; i < pf->vf_num; i++)
6696 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6700 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6702 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6703 struct i40e_arq_event_info info;
6704 uint16_t pending, opcode;
6707 info.buf_len = I40E_AQ_BUF_SZ;
6708 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6709 if (!info.msg_buf) {
6710 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6716 ret = i40e_clean_arq_element(hw, &info, &pending);
6718 if (ret != I40E_SUCCESS) {
6720 "Failed to read msg from AdminQ, aq_err: %u",
6721 hw->aq.asq_last_status);
6724 opcode = rte_le_to_cpu_16(info.desc.opcode);
6727 case i40e_aqc_opc_send_msg_to_pf:
6728 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6729 i40e_pf_host_handle_vf_msg(dev,
6730 rte_le_to_cpu_16(info.desc.retval),
6731 rte_le_to_cpu_32(info.desc.cookie_high),
6732 rte_le_to_cpu_32(info.desc.cookie_low),
6736 case i40e_aqc_opc_get_link_status:
6737 ret = i40e_dev_link_update(dev, 0);
6739 rte_eth_dev_callback_process(dev,
6740 RTE_ETH_EVENT_INTR_LSC, NULL);
6743 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6748 rte_free(info.msg_buf);
6752 i40e_handle_mdd_event(struct rte_eth_dev *dev)
6754 #define I40E_MDD_CLEAR32 0xFFFFFFFF
6755 #define I40E_MDD_CLEAR16 0xFFFF
6756 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6757 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6758 bool mdd_detected = false;
6759 struct i40e_pf_vf *vf;
6763 /* find what triggered the MDD event */
6764 reg = I40E_READ_REG(hw, I40E_GL_MDET_TX);
6765 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
6766 uint8_t pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6767 I40E_GL_MDET_TX_PF_NUM_SHIFT;
6768 uint16_t vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
6769 I40E_GL_MDET_TX_VF_NUM_SHIFT;
6770 uint8_t event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
6771 I40E_GL_MDET_TX_EVENT_SHIFT;
6772 uint16_t queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6773 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6774 hw->func_caps.base_queue;
6775 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on TX "
6776 "queue %d PF number 0x%02x VF number 0x%02x device %s\n",
6777 event, queue, pf_num, vf_num, dev->data->name);
6778 I40E_WRITE_REG(hw, I40E_GL_MDET_TX, I40E_MDD_CLEAR32);
6779 mdd_detected = true;
6781 reg = I40E_READ_REG(hw, I40E_GL_MDET_RX);
6782 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
6783 uint8_t func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6784 I40E_GL_MDET_RX_FUNCTION_SHIFT;
6785 uint8_t event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
6786 I40E_GL_MDET_RX_EVENT_SHIFT;
6787 uint16_t queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6788 I40E_GL_MDET_RX_QUEUE_SHIFT) -
6789 hw->func_caps.base_queue;
6791 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on RX "
6792 "queue %d of function 0x%02x device %s\n",
6793 event, queue, func, dev->data->name);
6794 I40E_WRITE_REG(hw, I40E_GL_MDET_RX, I40E_MDD_CLEAR32);
6795 mdd_detected = true;
6799 reg = I40E_READ_REG(hw, I40E_PF_MDET_TX);
6800 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
6801 I40E_WRITE_REG(hw, I40E_PF_MDET_TX, I40E_MDD_CLEAR16);
6802 PMD_DRV_LOG(WARNING, "TX driver issue detected on PF\n");
6804 reg = I40E_READ_REG(hw, I40E_PF_MDET_RX);
6805 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
6806 I40E_WRITE_REG(hw, I40E_PF_MDET_RX,
6808 PMD_DRV_LOG(WARNING, "RX driver issue detected on PF\n");
6812 /* see if one of the VFs needs its hand slapped */
6813 for (i = 0; i < pf->vf_num && mdd_detected; i++) {
6815 reg = I40E_READ_REG(hw, I40E_VP_MDET_TX(i));
6816 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
6817 I40E_WRITE_REG(hw, I40E_VP_MDET_TX(i),
6819 vf->num_mdd_events++;
6820 PMD_DRV_LOG(WARNING, "TX driver issue detected on VF %d %-"
6822 i, vf->num_mdd_events);
6825 reg = I40E_READ_REG(hw, I40E_VP_MDET_RX(i));
6826 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
6827 I40E_WRITE_REG(hw, I40E_VP_MDET_RX(i),
6829 vf->num_mdd_events++;
6830 PMD_DRV_LOG(WARNING, "RX driver issue detected on VF %d %-"
6832 i, vf->num_mdd_events);
6838 * Interrupt handler triggered by NIC for handling
6839 * specific interrupt.
6842 * Pointer to interrupt handle.
6844 * The address of parameter (struct rte_eth_dev *) regsitered before.
6850 i40e_dev_interrupt_handler(void *param)
6852 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6853 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6856 /* Disable interrupt */
6857 i40e_pf_disable_irq0(hw);
6859 /* read out interrupt causes */
6860 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6862 /* No interrupt event indicated */
6863 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6864 PMD_DRV_LOG(INFO, "No interrupt event");
6867 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6868 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6869 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
6870 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6871 i40e_handle_mdd_event(dev);
6873 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6874 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6875 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6876 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6877 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6878 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6879 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6880 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6881 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6882 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6884 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6885 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6886 i40e_dev_handle_vfr_event(dev);
6888 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6889 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6890 i40e_dev_handle_aq_msg(dev);
6894 /* Enable interrupt */
6895 i40e_pf_enable_irq0(hw);
6899 i40e_dev_alarm_handler(void *param)
6901 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6902 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6905 /* Disable interrupt */
6906 i40e_pf_disable_irq0(hw);
6908 /* read out interrupt causes */
6909 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6911 /* No interrupt event indicated */
6912 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
6914 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6915 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6916 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
6917 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6918 i40e_handle_mdd_event(dev);
6920 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6921 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6922 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6923 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6924 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6925 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6926 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6927 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6928 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6929 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6931 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6932 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6933 i40e_dev_handle_vfr_event(dev);
6935 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6936 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6937 i40e_dev_handle_aq_msg(dev);
6941 /* Enable interrupt */
6942 i40e_pf_enable_irq0(hw);
6943 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
6944 i40e_dev_alarm_handler, dev);
6948 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6949 struct i40e_macvlan_filter *filter,
6952 int ele_num, ele_buff_size;
6953 int num, actual_num, i;
6955 int ret = I40E_SUCCESS;
6956 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6957 struct i40e_aqc_add_macvlan_element_data *req_list;
6959 if (filter == NULL || total == 0)
6960 return I40E_ERR_PARAM;
6961 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6962 ele_buff_size = hw->aq.asq_buf_size;
6964 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6965 if (req_list == NULL) {
6966 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6967 return I40E_ERR_NO_MEMORY;
6972 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6973 memset(req_list, 0, ele_buff_size);
6975 for (i = 0; i < actual_num; i++) {
6976 rte_memcpy(req_list[i].mac_addr,
6977 &filter[num + i].macaddr, ETH_ADDR_LEN);
6978 req_list[i].vlan_tag =
6979 rte_cpu_to_le_16(filter[num + i].vlan_id);
6981 switch (filter[num + i].filter_type) {
6982 case I40E_MAC_PERFECT_MATCH:
6983 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6984 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6986 case I40E_MACVLAN_PERFECT_MATCH:
6987 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6989 case I40E_MAC_HASH_MATCH:
6990 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6991 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6993 case I40E_MACVLAN_HASH_MATCH:
6994 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6997 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6998 ret = I40E_ERR_PARAM;
7002 req_list[i].queue_number = 0;
7004 req_list[i].flags = rte_cpu_to_le_16(flags);
7007 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
7009 if (ret != I40E_SUCCESS) {
7010 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
7014 } while (num < total);
7022 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
7023 struct i40e_macvlan_filter *filter,
7026 int ele_num, ele_buff_size;
7027 int num, actual_num, i;
7029 int ret = I40E_SUCCESS;
7030 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7031 struct i40e_aqc_remove_macvlan_element_data *req_list;
7033 if (filter == NULL || total == 0)
7034 return I40E_ERR_PARAM;
7036 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
7037 ele_buff_size = hw->aq.asq_buf_size;
7039 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
7040 if (req_list == NULL) {
7041 PMD_DRV_LOG(ERR, "Fail to allocate memory");
7042 return I40E_ERR_NO_MEMORY;
7047 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
7048 memset(req_list, 0, ele_buff_size);
7050 for (i = 0; i < actual_num; i++) {
7051 rte_memcpy(req_list[i].mac_addr,
7052 &filter[num + i].macaddr, ETH_ADDR_LEN);
7053 req_list[i].vlan_tag =
7054 rte_cpu_to_le_16(filter[num + i].vlan_id);
7056 switch (filter[num + i].filter_type) {
7057 case I40E_MAC_PERFECT_MATCH:
7058 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
7059 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7061 case I40E_MACVLAN_PERFECT_MATCH:
7062 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
7064 case I40E_MAC_HASH_MATCH:
7065 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
7066 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7068 case I40E_MACVLAN_HASH_MATCH:
7069 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
7072 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
7073 ret = I40E_ERR_PARAM;
7076 req_list[i].flags = rte_cpu_to_le_16(flags);
7079 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
7081 if (ret != I40E_SUCCESS) {
7082 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
7086 } while (num < total);
7093 /* Find out specific MAC filter */
7094 static struct i40e_mac_filter *
7095 i40e_find_mac_filter(struct i40e_vsi *vsi,
7096 struct rte_ether_addr *macaddr)
7098 struct i40e_mac_filter *f;
7100 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7101 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
7109 i40e_find_vlan_filter(struct i40e_vsi *vsi,
7112 uint32_t vid_idx, vid_bit;
7114 if (vlan_id > ETH_VLAN_ID_MAX)
7117 vid_idx = I40E_VFTA_IDX(vlan_id);
7118 vid_bit = I40E_VFTA_BIT(vlan_id);
7120 if (vsi->vfta[vid_idx] & vid_bit)
7127 i40e_store_vlan_filter(struct i40e_vsi *vsi,
7128 uint16_t vlan_id, bool on)
7130 uint32_t vid_idx, vid_bit;
7132 vid_idx = I40E_VFTA_IDX(vlan_id);
7133 vid_bit = I40E_VFTA_BIT(vlan_id);
7136 vsi->vfta[vid_idx] |= vid_bit;
7138 vsi->vfta[vid_idx] &= ~vid_bit;
7142 i40e_set_vlan_filter(struct i40e_vsi *vsi,
7143 uint16_t vlan_id, bool on)
7145 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7146 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
7149 if (vlan_id > ETH_VLAN_ID_MAX)
7152 i40e_store_vlan_filter(vsi, vlan_id, on);
7154 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
7157 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
7160 ret = i40e_aq_add_vlan(hw, vsi->seid,
7161 &vlan_data, 1, NULL);
7162 if (ret != I40E_SUCCESS)
7163 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
7165 ret = i40e_aq_remove_vlan(hw, vsi->seid,
7166 &vlan_data, 1, NULL);
7167 if (ret != I40E_SUCCESS)
7169 "Failed to remove vlan filter");
7174 * Find all vlan options for specific mac addr,
7175 * return with actual vlan found.
7178 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
7179 struct i40e_macvlan_filter *mv_f,
7180 int num, struct rte_ether_addr *addr)
7186 * Not to use i40e_find_vlan_filter to decrease the loop time,
7187 * although the code looks complex.
7189 if (num < vsi->vlan_num)
7190 return I40E_ERR_PARAM;
7193 for (j = 0; j < I40E_VFTA_SIZE; j++) {
7195 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
7196 if (vsi->vfta[j] & (1 << k)) {
7199 "vlan number doesn't match");
7200 return I40E_ERR_PARAM;
7202 rte_memcpy(&mv_f[i].macaddr,
7203 addr, ETH_ADDR_LEN);
7205 j * I40E_UINT32_BIT_SIZE + k;
7211 return I40E_SUCCESS;
7215 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
7216 struct i40e_macvlan_filter *mv_f,
7221 struct i40e_mac_filter *f;
7223 if (num < vsi->mac_num)
7224 return I40E_ERR_PARAM;
7226 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7228 PMD_DRV_LOG(ERR, "buffer number not match");
7229 return I40E_ERR_PARAM;
7231 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7233 mv_f[i].vlan_id = vlan;
7234 mv_f[i].filter_type = f->mac_info.filter_type;
7238 return I40E_SUCCESS;
7242 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
7245 struct i40e_mac_filter *f;
7246 struct i40e_macvlan_filter *mv_f;
7247 int ret = I40E_SUCCESS;
7249 if (vsi == NULL || vsi->mac_num == 0)
7250 return I40E_ERR_PARAM;
7252 /* Case that no vlan is set */
7253 if (vsi->vlan_num == 0)
7256 num = vsi->mac_num * vsi->vlan_num;
7258 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7260 PMD_DRV_LOG(ERR, "failed to allocate memory");
7261 return I40E_ERR_NO_MEMORY;
7265 if (vsi->vlan_num == 0) {
7266 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7267 rte_memcpy(&mv_f[i].macaddr,
7268 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7269 mv_f[i].filter_type = f->mac_info.filter_type;
7270 mv_f[i].vlan_id = 0;
7274 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7275 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7276 vsi->vlan_num, &f->mac_info.mac_addr);
7277 if (ret != I40E_SUCCESS)
7279 for (j = i; j < i + vsi->vlan_num; j++)
7280 mv_f[j].filter_type = f->mac_info.filter_type;
7285 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7293 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7295 struct i40e_macvlan_filter *mv_f;
7297 int ret = I40E_SUCCESS;
7299 if (!vsi || vlan > RTE_ETHER_MAX_VLAN_ID)
7300 return I40E_ERR_PARAM;
7302 /* If it's already set, just return */
7303 if (i40e_find_vlan_filter(vsi,vlan))
7304 return I40E_SUCCESS;
7306 mac_num = vsi->mac_num;
7309 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7310 return I40E_ERR_PARAM;
7313 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7316 PMD_DRV_LOG(ERR, "failed to allocate memory");
7317 return I40E_ERR_NO_MEMORY;
7320 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7322 if (ret != I40E_SUCCESS)
7325 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7327 if (ret != I40E_SUCCESS)
7330 i40e_set_vlan_filter(vsi, vlan, 1);
7340 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7342 struct i40e_macvlan_filter *mv_f;
7344 int ret = I40E_SUCCESS;
7347 * Vlan 0 is the generic filter for untagged packets
7348 * and can't be removed.
7350 if (!vsi || vlan == 0 || vlan > RTE_ETHER_MAX_VLAN_ID)
7351 return I40E_ERR_PARAM;
7353 /* If can't find it, just return */
7354 if (!i40e_find_vlan_filter(vsi, vlan))
7355 return I40E_ERR_PARAM;
7357 mac_num = vsi->mac_num;
7360 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7361 return I40E_ERR_PARAM;
7364 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7367 PMD_DRV_LOG(ERR, "failed to allocate memory");
7368 return I40E_ERR_NO_MEMORY;
7371 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7373 if (ret != I40E_SUCCESS)
7376 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7378 if (ret != I40E_SUCCESS)
7381 /* This is last vlan to remove, replace all mac filter with vlan 0 */
7382 if (vsi->vlan_num == 1) {
7383 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7384 if (ret != I40E_SUCCESS)
7387 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7388 if (ret != I40E_SUCCESS)
7392 i40e_set_vlan_filter(vsi, vlan, 0);
7402 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7404 struct i40e_mac_filter *f;
7405 struct i40e_macvlan_filter *mv_f;
7406 int i, vlan_num = 0;
7407 int ret = I40E_SUCCESS;
7409 /* If it's add and we've config it, return */
7410 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7412 return I40E_SUCCESS;
7413 if (mac_filter->filter_type == I40E_MACVLAN_PERFECT_MATCH ||
7414 mac_filter->filter_type == I40E_MACVLAN_HASH_MATCH) {
7417 * If vlan_num is 0, that's the first time to add mac,
7418 * set mask for vlan_id 0.
7420 if (vsi->vlan_num == 0) {
7421 i40e_set_vlan_filter(vsi, 0, 1);
7424 vlan_num = vsi->vlan_num;
7425 } else if (mac_filter->filter_type == I40E_MAC_PERFECT_MATCH ||
7426 mac_filter->filter_type == I40E_MAC_HASH_MATCH)
7429 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7431 PMD_DRV_LOG(ERR, "failed to allocate memory");
7432 return I40E_ERR_NO_MEMORY;
7435 for (i = 0; i < vlan_num; i++) {
7436 mv_f[i].filter_type = mac_filter->filter_type;
7437 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7441 if (mac_filter->filter_type == I40E_MACVLAN_PERFECT_MATCH ||
7442 mac_filter->filter_type == I40E_MACVLAN_HASH_MATCH) {
7443 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7444 &mac_filter->mac_addr);
7445 if (ret != I40E_SUCCESS)
7449 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7450 if (ret != I40E_SUCCESS)
7453 /* Add the mac addr into mac list */
7454 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7456 PMD_DRV_LOG(ERR, "failed to allocate memory");
7457 ret = I40E_ERR_NO_MEMORY;
7460 rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7462 f->mac_info.filter_type = mac_filter->filter_type;
7463 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7474 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr)
7476 struct i40e_mac_filter *f;
7477 struct i40e_macvlan_filter *mv_f;
7479 enum i40e_mac_filter_type filter_type;
7480 int ret = I40E_SUCCESS;
7482 /* Can't find it, return an error */
7483 f = i40e_find_mac_filter(vsi, addr);
7485 return I40E_ERR_PARAM;
7487 vlan_num = vsi->vlan_num;
7488 filter_type = f->mac_info.filter_type;
7489 if (filter_type == I40E_MACVLAN_PERFECT_MATCH ||
7490 filter_type == I40E_MACVLAN_HASH_MATCH) {
7491 if (vlan_num == 0) {
7492 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7493 return I40E_ERR_PARAM;
7495 } else if (filter_type == I40E_MAC_PERFECT_MATCH ||
7496 filter_type == I40E_MAC_HASH_MATCH)
7499 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7501 PMD_DRV_LOG(ERR, "failed to allocate memory");
7502 return I40E_ERR_NO_MEMORY;
7505 for (i = 0; i < vlan_num; i++) {
7506 mv_f[i].filter_type = filter_type;
7507 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7510 if (filter_type == I40E_MACVLAN_PERFECT_MATCH ||
7511 filter_type == I40E_MACVLAN_HASH_MATCH) {
7512 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7513 if (ret != I40E_SUCCESS)
7517 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7518 if (ret != I40E_SUCCESS)
7521 /* Remove the mac addr into mac list */
7522 TAILQ_REMOVE(&vsi->mac_list, f, next);
7532 /* Configure hash enable flags for RSS */
7534 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7542 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7543 if (flags & (1ULL << i))
7544 hena |= adapter->pctypes_tbl[i];
7550 /* Parse the hash enable flags */
7552 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7554 uint64_t rss_hf = 0;
7560 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7561 if (flags & adapter->pctypes_tbl[i])
7562 rss_hf |= (1ULL << i);
7569 i40e_pf_disable_rss(struct i40e_pf *pf)
7571 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7573 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7574 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7575 I40E_WRITE_FLUSH(hw);
7579 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7581 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7582 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7583 uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7584 I40E_VFQF_HKEY_MAX_INDEX :
7585 I40E_PFQF_HKEY_MAX_INDEX;
7587 if (!key || key_len == 0) {
7588 PMD_DRV_LOG(DEBUG, "No key to be configured");
7590 } else if (key_len != (key_idx + 1) *
7592 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7596 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7597 struct i40e_aqc_get_set_rss_key_data *key_dw =
7598 (struct i40e_aqc_get_set_rss_key_data *)key;
7599 enum i40e_status_code status =
7600 i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7604 "Failed to configure RSS key via AQ, error status: %d",
7609 uint32_t *hash_key = (uint32_t *)key;
7612 if (vsi->type == I40E_VSI_SRIOV) {
7613 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7616 I40E_VFQF_HKEY1(i, vsi->user_param),
7620 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7621 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7624 I40E_WRITE_FLUSH(hw);
7631 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7633 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7634 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7638 if (!key || !key_len)
7641 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7642 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7643 (struct i40e_aqc_get_set_rss_key_data *)key);
7645 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7649 uint32_t *key_dw = (uint32_t *)key;
7652 if (vsi->type == I40E_VSI_SRIOV) {
7653 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7654 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7655 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7657 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7660 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7661 reg = I40E_PFQF_HKEY(i);
7662 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7664 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7672 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7674 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7678 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7679 rss_conf->rss_key_len);
7683 hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7684 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7685 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7686 I40E_WRITE_FLUSH(hw);
7692 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7693 struct rte_eth_rss_conf *rss_conf)
7695 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7696 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7697 uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7700 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7701 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7703 if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7704 if (rss_hf != 0) /* Enable RSS */
7706 return 0; /* Nothing to do */
7709 if (rss_hf == 0) /* Disable RSS */
7712 return i40e_hw_rss_hash_set(pf, rss_conf);
7716 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7717 struct rte_eth_rss_conf *rss_conf)
7719 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7720 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7727 ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7728 &rss_conf->rss_key_len);
7732 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7733 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7734 rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7740 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7742 switch (filter_type) {
7743 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7744 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7746 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7747 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7749 case RTE_TUNNEL_FILTER_IMAC_TENID:
7750 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7752 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7753 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7755 case ETH_TUNNEL_FILTER_IMAC:
7756 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7758 case ETH_TUNNEL_FILTER_OIP:
7759 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7761 case ETH_TUNNEL_FILTER_IIP:
7762 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7765 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7772 /* Convert tunnel filter structure */
7774 i40e_tunnel_filter_convert(
7775 struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7776 struct i40e_tunnel_filter *tunnel_filter)
7778 rte_ether_addr_copy((struct rte_ether_addr *)
7779 &cld_filter->element.outer_mac,
7780 (struct rte_ether_addr *)&tunnel_filter->input.outer_mac);
7781 rte_ether_addr_copy((struct rte_ether_addr *)
7782 &cld_filter->element.inner_mac,
7783 (struct rte_ether_addr *)&tunnel_filter->input.inner_mac);
7784 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7785 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7786 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7787 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7788 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7790 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7791 tunnel_filter->input.flags = cld_filter->element.flags;
7792 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7793 tunnel_filter->queue = cld_filter->element.queue_number;
7794 rte_memcpy(tunnel_filter->input.general_fields,
7795 cld_filter->general_fields,
7796 sizeof(cld_filter->general_fields));
7801 /* Check if there exists the tunnel filter */
7802 struct i40e_tunnel_filter *
7803 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7804 const struct i40e_tunnel_filter_input *input)
7808 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7812 return tunnel_rule->hash_map[ret];
7815 /* Add a tunnel filter into the SW list */
7817 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7818 struct i40e_tunnel_filter *tunnel_filter)
7820 struct i40e_tunnel_rule *rule = &pf->tunnel;
7823 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7826 "Failed to insert tunnel filter to hash table %d!",
7830 rule->hash_map[ret] = tunnel_filter;
7832 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7837 /* Delete a tunnel filter from the SW list */
7839 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7840 struct i40e_tunnel_filter_input *input)
7842 struct i40e_tunnel_rule *rule = &pf->tunnel;
7843 struct i40e_tunnel_filter *tunnel_filter;
7846 ret = rte_hash_del_key(rule->hash_table, input);
7849 "Failed to delete tunnel filter to hash table %d!",
7853 tunnel_filter = rule->hash_map[ret];
7854 rule->hash_map[ret] = NULL;
7856 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7857 rte_free(tunnel_filter);
7862 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7863 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
7864 #define I40E_TR_GENEVE_KEY_MASK 0x8
7865 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
7866 #define I40E_TR_GRE_KEY_MASK 0x400
7867 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
7868 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
7869 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_PORT_TR_WORD0 0x49
7870 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_DIRECTION_WORD0 0x41
7871 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_INGRESS_WORD0 0x80
7872 #define I40E_DIRECTION_INGRESS_KEY 0x8000
7873 #define I40E_TR_L4_TYPE_TCP 0x2
7874 #define I40E_TR_L4_TYPE_UDP 0x4
7875 #define I40E_TR_L4_TYPE_SCTP 0x8
7878 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7880 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7881 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7882 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7883 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7884 enum i40e_status_code status = I40E_SUCCESS;
7886 if (pf->support_multi_driver) {
7887 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7888 return I40E_NOT_SUPPORTED;
7891 memset(&filter_replace, 0,
7892 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7893 memset(&filter_replace_buf, 0,
7894 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7896 /* create L1 filter */
7897 filter_replace.old_filter_type =
7898 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7899 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7900 filter_replace.tr_bit = 0;
7902 /* Prepare the buffer, 3 entries */
7903 filter_replace_buf.data[0] =
7904 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7905 filter_replace_buf.data[0] |=
7906 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7907 filter_replace_buf.data[2] = 0xFF;
7908 filter_replace_buf.data[3] = 0xFF;
7909 filter_replace_buf.data[4] =
7910 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7911 filter_replace_buf.data[4] |=
7912 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7913 filter_replace_buf.data[7] = 0xF0;
7914 filter_replace_buf.data[8]
7915 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7916 filter_replace_buf.data[8] |=
7917 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7918 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7919 I40E_TR_GENEVE_KEY_MASK |
7920 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7921 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7922 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7923 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7925 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7926 &filter_replace_buf);
7927 if (!status && (filter_replace.old_filter_type !=
7928 filter_replace.new_filter_type))
7929 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7930 " original: 0x%x, new: 0x%x",
7932 filter_replace.old_filter_type,
7933 filter_replace.new_filter_type);
7939 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7941 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7942 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7943 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7944 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7945 enum i40e_status_code status = I40E_SUCCESS;
7947 if (pf->support_multi_driver) {
7948 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7949 return I40E_NOT_SUPPORTED;
7953 memset(&filter_replace, 0,
7954 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7955 memset(&filter_replace_buf, 0,
7956 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7957 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7958 I40E_AQC_MIRROR_CLOUD_FILTER;
7959 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7960 filter_replace.new_filter_type =
7961 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7962 /* Prepare the buffer, 2 entries */
7963 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7964 filter_replace_buf.data[0] |=
7965 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7966 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7967 filter_replace_buf.data[4] |=
7968 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7969 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7970 &filter_replace_buf);
7973 if (filter_replace.old_filter_type !=
7974 filter_replace.new_filter_type)
7975 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7976 " original: 0x%x, new: 0x%x",
7978 filter_replace.old_filter_type,
7979 filter_replace.new_filter_type);
7982 memset(&filter_replace, 0,
7983 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7984 memset(&filter_replace_buf, 0,
7985 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7987 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7988 I40E_AQC_MIRROR_CLOUD_FILTER;
7989 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7990 filter_replace.new_filter_type =
7991 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7992 /* Prepare the buffer, 2 entries */
7993 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7994 filter_replace_buf.data[0] |=
7995 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7996 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7997 filter_replace_buf.data[4] |=
7998 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8000 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8001 &filter_replace_buf);
8002 if (!status && (filter_replace.old_filter_type !=
8003 filter_replace.new_filter_type))
8004 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8005 " original: 0x%x, new: 0x%x",
8007 filter_replace.old_filter_type,
8008 filter_replace.new_filter_type);
8013 static enum i40e_status_code
8014 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
8016 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8017 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8018 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8019 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8020 enum i40e_status_code status = I40E_SUCCESS;
8022 if (pf->support_multi_driver) {
8023 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8024 return I40E_NOT_SUPPORTED;
8028 memset(&filter_replace, 0,
8029 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8030 memset(&filter_replace_buf, 0,
8031 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8032 /* create L1 filter */
8033 filter_replace.old_filter_type =
8034 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
8035 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
8036 filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
8037 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8038 /* Prepare the buffer, 2 entries */
8039 filter_replace_buf.data[0] =
8040 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8041 filter_replace_buf.data[0] |=
8042 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8043 filter_replace_buf.data[2] = 0xFF;
8044 filter_replace_buf.data[3] = 0xFF;
8045 filter_replace_buf.data[4] =
8046 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8047 filter_replace_buf.data[4] |=
8048 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8049 filter_replace_buf.data[6] = 0xFF;
8050 filter_replace_buf.data[7] = 0xFF;
8051 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8052 &filter_replace_buf);
8055 if (filter_replace.old_filter_type !=
8056 filter_replace.new_filter_type)
8057 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8058 " original: 0x%x, new: 0x%x",
8060 filter_replace.old_filter_type,
8061 filter_replace.new_filter_type);
8064 memset(&filter_replace, 0,
8065 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8066 memset(&filter_replace_buf, 0,
8067 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8068 /* create L1 filter */
8069 filter_replace.old_filter_type =
8070 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8071 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
8072 filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
8073 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8074 /* Prepare the buffer, 2 entries */
8075 filter_replace_buf.data[0] =
8076 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8077 filter_replace_buf.data[0] |=
8078 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8079 filter_replace_buf.data[2] = 0xFF;
8080 filter_replace_buf.data[3] = 0xFF;
8081 filter_replace_buf.data[4] =
8082 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8083 filter_replace_buf.data[4] |=
8084 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8085 filter_replace_buf.data[6] = 0xFF;
8086 filter_replace_buf.data[7] = 0xFF;
8088 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8089 &filter_replace_buf);
8090 if (!status && (filter_replace.old_filter_type !=
8091 filter_replace.new_filter_type))
8092 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8093 " original: 0x%x, new: 0x%x",
8095 filter_replace.old_filter_type,
8096 filter_replace.new_filter_type);
8102 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
8104 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8105 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8106 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8107 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8108 enum i40e_status_code status = I40E_SUCCESS;
8110 if (pf->support_multi_driver) {
8111 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8112 return I40E_NOT_SUPPORTED;
8116 memset(&filter_replace, 0,
8117 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8118 memset(&filter_replace_buf, 0,
8119 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8120 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8121 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
8122 filter_replace.new_filter_type =
8123 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8124 /* Prepare the buffer, 2 entries */
8125 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
8126 filter_replace_buf.data[0] |=
8127 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8128 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8129 filter_replace_buf.data[4] |=
8130 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8131 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8132 &filter_replace_buf);
8135 if (filter_replace.old_filter_type !=
8136 filter_replace.new_filter_type)
8137 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8138 " original: 0x%x, new: 0x%x",
8140 filter_replace.old_filter_type,
8141 filter_replace.new_filter_type);
8144 memset(&filter_replace, 0,
8145 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8146 memset(&filter_replace_buf, 0,
8147 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8148 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8149 filter_replace.old_filter_type =
8150 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8151 filter_replace.new_filter_type =
8152 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8153 /* Prepare the buffer, 2 entries */
8154 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8155 filter_replace_buf.data[0] |=
8156 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8157 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8158 filter_replace_buf.data[4] |=
8159 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8161 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8162 &filter_replace_buf);
8163 if (!status && (filter_replace.old_filter_type !=
8164 filter_replace.new_filter_type))
8165 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8166 " original: 0x%x, new: 0x%x",
8168 filter_replace.old_filter_type,
8169 filter_replace.new_filter_type);
8174 static enum i40e_status_code
8175 i40e_replace_port_l1_filter(struct i40e_pf *pf,
8176 enum i40e_l4_port_type l4_port_type)
8178 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8179 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8180 enum i40e_status_code status = I40E_SUCCESS;
8181 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8182 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8184 if (pf->support_multi_driver) {
8185 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8186 return I40E_NOT_SUPPORTED;
8189 memset(&filter_replace, 0,
8190 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8191 memset(&filter_replace_buf, 0,
8192 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8194 /* create L1 filter */
8195 if (l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8196 filter_replace.old_filter_type =
8197 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8198 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
8199 filter_replace_buf.data[8] =
8200 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_SRC_PORT;
8202 filter_replace.old_filter_type =
8203 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
8204 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X10;
8205 filter_replace_buf.data[8] =
8206 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_DST_PORT;
8209 filter_replace.tr_bit = 0;
8210 /* Prepare the buffer, 3 entries */
8211 filter_replace_buf.data[0] =
8212 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_DIRECTION_WORD0;
8213 filter_replace_buf.data[0] |=
8214 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8215 filter_replace_buf.data[2] = 0x00;
8216 filter_replace_buf.data[3] =
8217 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_INGRESS_WORD0;
8218 filter_replace_buf.data[4] =
8219 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_PORT_TR_WORD0;
8220 filter_replace_buf.data[4] |=
8221 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8222 filter_replace_buf.data[5] = 0x00;
8223 filter_replace_buf.data[6] = I40E_TR_L4_TYPE_UDP |
8224 I40E_TR_L4_TYPE_TCP |
8225 I40E_TR_L4_TYPE_SCTP;
8226 filter_replace_buf.data[7] = 0x00;
8227 filter_replace_buf.data[8] |=
8228 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8229 filter_replace_buf.data[9] = 0x00;
8230 filter_replace_buf.data[10] = 0xFF;
8231 filter_replace_buf.data[11] = 0xFF;
8233 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8234 &filter_replace_buf);
8235 if (!status && filter_replace.old_filter_type !=
8236 filter_replace.new_filter_type)
8237 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8238 " original: 0x%x, new: 0x%x",
8240 filter_replace.old_filter_type,
8241 filter_replace.new_filter_type);
8246 static enum i40e_status_code
8247 i40e_replace_port_cloud_filter(struct i40e_pf *pf,
8248 enum i40e_l4_port_type l4_port_type)
8250 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8251 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8252 enum i40e_status_code status = I40E_SUCCESS;
8253 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8254 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8256 if (pf->support_multi_driver) {
8257 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8258 return I40E_NOT_SUPPORTED;
8261 memset(&filter_replace, 0,
8262 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8263 memset(&filter_replace_buf, 0,
8264 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8266 if (l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8267 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
8268 filter_replace.new_filter_type =
8269 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8270 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X11;
8272 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
8273 filter_replace.new_filter_type =
8274 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8275 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
8278 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8279 filter_replace.tr_bit = 0;
8280 /* Prepare the buffer, 2 entries */
8281 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8282 filter_replace_buf.data[0] |=
8283 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8284 filter_replace_buf.data[4] |=
8285 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8286 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8287 &filter_replace_buf);
8289 if (!status && filter_replace.old_filter_type !=
8290 filter_replace.new_filter_type)
8291 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8292 " original: 0x%x, new: 0x%x",
8294 filter_replace.old_filter_type,
8295 filter_replace.new_filter_type);
8301 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8302 struct i40e_tunnel_filter_conf *tunnel_filter,
8306 uint32_t ipv4_addr, ipv4_addr_le;
8307 uint8_t i, tun_type = 0;
8308 /* internal variable to convert ipv6 byte order */
8309 uint32_t convert_ipv6[4];
8311 struct i40e_pf_vf *vf = NULL;
8312 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8313 struct i40e_vsi *vsi;
8314 struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8315 struct i40e_aqc_cloud_filters_element_bb *pfilter;
8316 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8317 struct i40e_tunnel_filter *tunnel, *node;
8318 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8320 bool big_buffer = 0;
8322 cld_filter = rte_zmalloc("tunnel_filter",
8323 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8326 if (cld_filter == NULL) {
8327 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8330 pfilter = cld_filter;
8332 rte_ether_addr_copy(&tunnel_filter->outer_mac,
8333 (struct rte_ether_addr *)&pfilter->element.outer_mac);
8334 rte_ether_addr_copy(&tunnel_filter->inner_mac,
8335 (struct rte_ether_addr *)&pfilter->element.inner_mac);
8337 pfilter->element.inner_vlan =
8338 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8339 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8340 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8341 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8342 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8343 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8345 sizeof(pfilter->element.ipaddr.v4.data));
8347 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8348 for (i = 0; i < 4; i++) {
8350 rte_cpu_to_le_32(rte_be_to_cpu_32(
8351 tunnel_filter->ip_addr.ipv6_addr[i]));
8353 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8355 sizeof(pfilter->element.ipaddr.v6.data));
8358 /* check tunneled type */
8359 switch (tunnel_filter->tunnel_type) {
8360 case I40E_TUNNEL_TYPE_VXLAN:
8361 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8363 case I40E_TUNNEL_TYPE_NVGRE:
8364 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8366 case I40E_TUNNEL_TYPE_IP_IN_GRE:
8367 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8369 case I40E_TUNNEL_TYPE_MPLSoUDP:
8370 if (!pf->mpls_replace_flag) {
8371 i40e_replace_mpls_l1_filter(pf);
8372 i40e_replace_mpls_cloud_filter(pf);
8373 pf->mpls_replace_flag = 1;
8375 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8376 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8378 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8379 (teid_le & 0xF) << 12;
8380 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8383 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8385 case I40E_TUNNEL_TYPE_MPLSoGRE:
8386 if (!pf->mpls_replace_flag) {
8387 i40e_replace_mpls_l1_filter(pf);
8388 i40e_replace_mpls_cloud_filter(pf);
8389 pf->mpls_replace_flag = 1;
8391 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8392 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8394 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8395 (teid_le & 0xF) << 12;
8396 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8399 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8401 case I40E_TUNNEL_TYPE_GTPC:
8402 if (!pf->gtp_replace_flag) {
8403 i40e_replace_gtp_l1_filter(pf);
8404 i40e_replace_gtp_cloud_filter(pf);
8405 pf->gtp_replace_flag = 1;
8407 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8408 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8409 (teid_le >> 16) & 0xFFFF;
8410 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8412 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8416 case I40E_TUNNEL_TYPE_GTPU:
8417 if (!pf->gtp_replace_flag) {
8418 i40e_replace_gtp_l1_filter(pf);
8419 i40e_replace_gtp_cloud_filter(pf);
8420 pf->gtp_replace_flag = 1;
8422 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8423 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8424 (teid_le >> 16) & 0xFFFF;
8425 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8427 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8431 case I40E_TUNNEL_TYPE_QINQ:
8432 if (!pf->qinq_replace_flag) {
8433 ret = i40e_cloud_filter_qinq_create(pf);
8436 "QinQ tunnel filter already created.");
8437 pf->qinq_replace_flag = 1;
8439 /* Add in the General fields the values of
8440 * the Outer and Inner VLAN
8441 * Big Buffer should be set, see changes in
8442 * i40e_aq_add_cloud_filters
8444 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8445 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8448 case I40E_CLOUD_TYPE_UDP:
8449 case I40E_CLOUD_TYPE_TCP:
8450 case I40E_CLOUD_TYPE_SCTP:
8451 if (tunnel_filter->l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8452 if (!pf->sport_replace_flag) {
8453 i40e_replace_port_l1_filter(pf,
8454 tunnel_filter->l4_port_type);
8455 i40e_replace_port_cloud_filter(pf,
8456 tunnel_filter->l4_port_type);
8457 pf->sport_replace_flag = 1;
8459 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8460 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8461 I40E_DIRECTION_INGRESS_KEY;
8463 if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP)
8464 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8465 I40E_TR_L4_TYPE_UDP;
8466 else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP)
8467 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8468 I40E_TR_L4_TYPE_TCP;
8470 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8471 I40E_TR_L4_TYPE_SCTP;
8473 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8474 (teid_le >> 16) & 0xFFFF;
8477 if (!pf->dport_replace_flag) {
8478 i40e_replace_port_l1_filter(pf,
8479 tunnel_filter->l4_port_type);
8480 i40e_replace_port_cloud_filter(pf,
8481 tunnel_filter->l4_port_type);
8482 pf->dport_replace_flag = 1;
8484 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8485 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0] =
8486 I40E_DIRECTION_INGRESS_KEY;
8488 if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP)
8489 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8490 I40E_TR_L4_TYPE_UDP;
8491 else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP)
8492 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8493 I40E_TR_L4_TYPE_TCP;
8495 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8496 I40E_TR_L4_TYPE_SCTP;
8498 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2] =
8499 (teid_le >> 16) & 0xFFFF;
8505 /* Other tunnel types is not supported. */
8506 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8507 rte_free(cld_filter);
8511 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8512 pfilter->element.flags =
8513 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8514 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8515 pfilter->element.flags =
8516 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8517 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8518 pfilter->element.flags =
8519 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8520 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8521 pfilter->element.flags =
8522 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8523 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8524 pfilter->element.flags |=
8525 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8526 else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP ||
8527 tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP ||
8528 tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_SCTP) {
8529 if (tunnel_filter->l4_port_type == I40E_L4_PORT_TYPE_SRC)
8530 pfilter->element.flags |=
8531 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8533 pfilter->element.flags |=
8534 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8536 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8537 &pfilter->element.flags);
8539 rte_free(cld_filter);
8544 pfilter->element.flags |= rte_cpu_to_le_16(
8545 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8546 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8547 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8548 pfilter->element.queue_number =
8549 rte_cpu_to_le_16(tunnel_filter->queue_id);
8551 if (!tunnel_filter->is_to_vf)
8554 if (tunnel_filter->vf_id >= pf->vf_num) {
8555 PMD_DRV_LOG(ERR, "Invalid argument.");
8556 rte_free(cld_filter);
8559 vf = &pf->vfs[tunnel_filter->vf_id];
8563 /* Check if there is the filter in SW list */
8564 memset(&check_filter, 0, sizeof(check_filter));
8565 i40e_tunnel_filter_convert(cld_filter, &check_filter);
8566 check_filter.is_to_vf = tunnel_filter->is_to_vf;
8567 check_filter.vf_id = tunnel_filter->vf_id;
8568 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8570 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8571 rte_free(cld_filter);
8575 if (!add && !node) {
8576 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8577 rte_free(cld_filter);
8583 ret = i40e_aq_add_cloud_filters_bb(hw,
8584 vsi->seid, cld_filter, 1);
8586 ret = i40e_aq_add_cloud_filters(hw,
8587 vsi->seid, &cld_filter->element, 1);
8589 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8590 rte_free(cld_filter);
8593 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8594 if (tunnel == NULL) {
8595 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8596 rte_free(cld_filter);
8600 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8601 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8606 ret = i40e_aq_rem_cloud_filters_bb(
8607 hw, vsi->seid, cld_filter, 1);
8609 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8610 &cld_filter->element, 1);
8612 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8613 rte_free(cld_filter);
8616 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8619 rte_free(cld_filter);
8624 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8628 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8629 if (pf->vxlan_ports[i] == port)
8637 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port, int udp_type)
8640 uint8_t filter_idx = 0;
8641 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8643 idx = i40e_get_vxlan_port_idx(pf, port);
8645 /* Check if port already exists */
8647 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8651 /* Now check if there is space to add the new port */
8652 idx = i40e_get_vxlan_port_idx(pf, 0);
8655 "Maximum number of UDP ports reached, not adding port %d",
8660 ret = i40e_aq_add_udp_tunnel(hw, port, udp_type,
8663 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8667 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8670 /* New port: add it and mark its index in the bitmap */
8671 pf->vxlan_ports[idx] = port;
8672 pf->vxlan_bitmap |= (1 << idx);
8674 if (!(pf->flags & I40E_FLAG_VXLAN))
8675 pf->flags |= I40E_FLAG_VXLAN;
8681 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8684 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8686 if (!(pf->flags & I40E_FLAG_VXLAN)) {
8687 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8691 idx = i40e_get_vxlan_port_idx(pf, port);
8694 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8698 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8699 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8703 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8706 pf->vxlan_ports[idx] = 0;
8707 pf->vxlan_bitmap &= ~(1 << idx);
8709 if (!pf->vxlan_bitmap)
8710 pf->flags &= ~I40E_FLAG_VXLAN;
8715 /* Add UDP tunneling port */
8717 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8718 struct rte_eth_udp_tunnel *udp_tunnel)
8721 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8723 if (udp_tunnel == NULL)
8726 switch (udp_tunnel->prot_type) {
8727 case RTE_TUNNEL_TYPE_VXLAN:
8728 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8729 I40E_AQC_TUNNEL_TYPE_VXLAN);
8731 case RTE_TUNNEL_TYPE_VXLAN_GPE:
8732 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8733 I40E_AQC_TUNNEL_TYPE_VXLAN_GPE);
8735 case RTE_TUNNEL_TYPE_GENEVE:
8736 case RTE_TUNNEL_TYPE_TEREDO:
8737 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8742 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8750 /* Remove UDP tunneling port */
8752 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8753 struct rte_eth_udp_tunnel *udp_tunnel)
8756 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8758 if (udp_tunnel == NULL)
8761 switch (udp_tunnel->prot_type) {
8762 case RTE_TUNNEL_TYPE_VXLAN:
8763 case RTE_TUNNEL_TYPE_VXLAN_GPE:
8764 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8766 case RTE_TUNNEL_TYPE_GENEVE:
8767 case RTE_TUNNEL_TYPE_TEREDO:
8768 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8772 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8780 /* Calculate the maximum number of contiguous PF queues that are configured */
8782 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8784 struct rte_eth_dev_data *data = pf->dev_data;
8786 struct i40e_rx_queue *rxq;
8789 for (i = 0; i < pf->lan_nb_qps; i++) {
8790 rxq = data->rx_queues[i];
8791 if (rxq && rxq->q_set)
8800 /* Reset the global configure of hash function and input sets */
8802 i40e_pf_global_rss_reset(struct i40e_pf *pf)
8804 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8805 uint32_t reg, reg_val;
8808 /* Reset global RSS function sets */
8809 reg_val = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8810 if (!(reg_val & I40E_GLQF_CTL_HTOEP_MASK)) {
8811 reg_val |= I40E_GLQF_CTL_HTOEP_MASK;
8812 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg_val);
8815 for (i = 0; i <= I40E_FILTER_PCTYPE_L2_PAYLOAD; i++) {
8819 if (hw->mac.type == I40E_MAC_X722)
8820 pctype = i40e_read_rx_ctl(hw, I40E_GLQF_FD_PCTYPES(i));
8824 /* Reset pctype insets */
8825 inset = i40e_get_default_input_set(i);
8827 pf->hash_input_set[pctype] = inset;
8828 inset = i40e_translate_input_set_reg(hw->mac.type,
8831 reg = I40E_GLQF_HASH_INSET(0, pctype);
8832 i40e_check_write_global_reg(hw, reg, (uint32_t)inset);
8833 reg = I40E_GLQF_HASH_INSET(1, pctype);
8834 i40e_check_write_global_reg(hw, reg,
8835 (uint32_t)(inset >> 32));
8837 /* Clear unused mask registers of the pctype */
8838 for (j = 0; j < I40E_INSET_MASK_NUM_REG; j++) {
8839 reg = I40E_GLQF_HASH_MSK(j, pctype);
8840 i40e_check_write_global_reg(hw, reg, 0);
8844 /* Reset pctype symmetric sets */
8845 reg = I40E_GLQF_HSYM(pctype);
8846 reg_val = i40e_read_rx_ctl(hw, reg);
8847 if (reg_val & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8848 reg_val &= ~I40E_GLQF_HSYM_SYMH_ENA_MASK;
8849 i40e_write_global_rx_ctl(hw, reg, reg_val);
8852 I40E_WRITE_FLUSH(hw);
8856 i40e_pf_reset_rss_reta(struct i40e_pf *pf)
8858 struct i40e_hw *hw = &pf->adapter->hw;
8859 uint8_t lut[ETH_RSS_RETA_SIZE_512];
8863 /* If both VMDQ and RSS enabled, not all of PF queues are
8864 * configured. It's necessary to calculate the actual PF
8865 * queues that are configured.
8867 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8868 num = i40e_pf_calc_configured_queues_num(pf);
8870 num = pf->dev_data->nb_rx_queues;
8872 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8876 for (i = 0; i < hw->func_caps.rss_table_size; i++)
8877 lut[i] = (uint8_t)(i % (uint32_t)num);
8879 return i40e_set_rss_lut(pf->main_vsi, lut, (uint16_t)i);
8883 i40e_pf_reset_rss_key(struct i40e_pf *pf)
8885 const uint8_t key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8890 rss_key = pf->dev_data->dev_conf.rx_adv_conf.rss_conf.rss_key;
8892 pf->dev_data->dev_conf.rx_adv_conf.rss_conf.rss_key_len < key_len) {
8893 static uint32_t rss_key_default[] = {0x6b793944,
8894 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8895 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8896 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8898 rss_key = (uint8_t *)rss_key_default;
8901 return i40e_set_rss_key(pf->main_vsi, rss_key, key_len);
8905 i40e_pf_rss_reset(struct i40e_pf *pf)
8907 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8911 pf->hash_filter_enabled = 0;
8912 i40e_pf_disable_rss(pf);
8913 i40e_set_symmetric_hash_enable_per_port(hw, 0);
8915 if (!pf->support_multi_driver)
8916 i40e_pf_global_rss_reset(pf);
8918 /* Reset RETA table */
8919 if (pf->adapter->rss_reta_updated == 0) {
8920 ret = i40e_pf_reset_rss_reta(pf);
8925 return i40e_pf_reset_rss_key(pf);
8930 i40e_pf_config_rss(struct i40e_pf *pf)
8933 enum rte_eth_rx_mq_mode mq_mode;
8934 uint64_t rss_hf, hena;
8937 ret = i40e_pf_rss_reset(pf);
8939 PMD_DRV_LOG(ERR, "Reset RSS failed, RSS has been disabled");
8943 rss_hf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf.rss_hf;
8944 mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8945 if (!(rss_hf & pf->adapter->flow_types_mask) ||
8946 !(mq_mode & ETH_MQ_RX_RSS_FLAG))
8949 hw = I40E_PF_TO_HW(pf);
8950 hena = i40e_config_hena(pf->adapter, rss_hf);
8951 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
8952 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
8953 I40E_WRITE_FLUSH(hw);
8958 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8959 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
8961 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8963 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8967 if (pf->support_multi_driver) {
8968 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8972 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8973 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8976 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8977 } else if (len == 4) {
8978 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8980 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8985 ret = i40e_aq_debug_write_global_register(hw,
8986 I40E_GL_PRS_FVBM(2),
8990 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8991 "with value 0x%08x",
8992 I40E_GL_PRS_FVBM(2), reg);
8996 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8997 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
9002 /* Set the symmetric hash enable configurations per port */
9004 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
9006 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
9009 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)
9012 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
9014 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK))
9017 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
9019 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
9020 I40E_WRITE_FLUSH(hw);
9024 * Valid input sets for hash and flow director filters per PCTYPE
9027 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
9028 enum rte_filter_type filter)
9032 static const uint64_t valid_hash_inset_table[] = {
9033 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9034 I40E_INSET_DMAC | I40E_INSET_SMAC |
9035 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9036 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
9037 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
9038 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9039 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9040 I40E_INSET_FLEX_PAYLOAD,
9041 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9042 I40E_INSET_DMAC | I40E_INSET_SMAC |
9043 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9044 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9045 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9046 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9047 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9048 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9049 I40E_INSET_FLEX_PAYLOAD,
9050 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9051 I40E_INSET_DMAC | I40E_INSET_SMAC |
9052 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9053 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9054 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9055 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9056 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9057 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9058 I40E_INSET_FLEX_PAYLOAD,
9059 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9060 I40E_INSET_DMAC | I40E_INSET_SMAC |
9061 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9062 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9063 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9064 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9065 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9066 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9067 I40E_INSET_FLEX_PAYLOAD,
9068 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9069 I40E_INSET_DMAC | I40E_INSET_SMAC |
9070 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9071 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9072 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9073 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9074 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9075 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9076 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9077 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9078 I40E_INSET_DMAC | I40E_INSET_SMAC |
9079 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9080 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9081 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9082 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9083 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9084 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9085 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9086 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9087 I40E_INSET_DMAC | I40E_INSET_SMAC |
9088 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9089 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9090 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9091 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9092 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9093 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9094 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
9095 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9096 I40E_INSET_DMAC | I40E_INSET_SMAC |
9097 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9098 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9099 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9100 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9101 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9102 I40E_INSET_FLEX_PAYLOAD,
9103 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9104 I40E_INSET_DMAC | I40E_INSET_SMAC |
9105 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9106 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9107 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9108 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
9109 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
9110 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
9111 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9112 I40E_INSET_DMAC | I40E_INSET_SMAC |
9113 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9114 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9115 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9116 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9117 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9118 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
9119 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9120 I40E_INSET_DMAC | I40E_INSET_SMAC |
9121 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9122 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9123 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9124 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9125 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9126 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9127 I40E_INSET_FLEX_PAYLOAD,
9128 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9129 I40E_INSET_DMAC | I40E_INSET_SMAC |
9130 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9131 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9132 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9133 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9134 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9135 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9136 I40E_INSET_FLEX_PAYLOAD,
9137 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9138 I40E_INSET_DMAC | I40E_INSET_SMAC |
9139 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9140 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9141 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9142 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9143 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9144 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9145 I40E_INSET_FLEX_PAYLOAD,
9146 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9147 I40E_INSET_DMAC | I40E_INSET_SMAC |
9148 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9149 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9150 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9151 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9152 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9153 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9154 I40E_INSET_FLEX_PAYLOAD,
9155 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9156 I40E_INSET_DMAC | I40E_INSET_SMAC |
9157 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9158 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9159 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9160 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9161 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9162 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9163 I40E_INSET_FLEX_PAYLOAD,
9164 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9165 I40E_INSET_DMAC | I40E_INSET_SMAC |
9166 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9167 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9168 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9169 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9170 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9171 I40E_INSET_FLEX_PAYLOAD,
9172 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9173 I40E_INSET_DMAC | I40E_INSET_SMAC |
9174 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9175 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9176 I40E_INSET_FLEX_PAYLOAD,
9180 * Flow director supports only fields defined in
9181 * union rte_eth_fdir_flow.
9183 static const uint64_t valid_fdir_inset_table[] = {
9184 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9185 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9186 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9187 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9188 I40E_INSET_IPV4_TTL,
9189 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9190 I40E_INSET_DMAC | I40E_INSET_SMAC |
9191 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9192 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9193 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9194 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9195 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9196 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9197 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9198 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9199 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9200 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9201 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9202 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9203 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9204 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9205 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9206 I40E_INSET_DMAC | I40E_INSET_SMAC |
9207 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9208 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9209 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9210 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9211 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9212 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9213 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9214 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9215 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9216 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9217 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9218 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9219 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9220 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9222 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9223 I40E_INSET_DMAC | I40E_INSET_SMAC |
9224 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9225 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9226 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9227 I40E_INSET_IPV4_TTL,
9228 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9229 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9230 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9231 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9232 I40E_INSET_IPV6_HOP_LIMIT,
9233 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9234 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9235 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9236 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9237 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9238 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9239 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9240 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9241 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9242 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9243 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9244 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9245 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9246 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9247 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9248 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9249 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9250 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9251 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9252 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9253 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9254 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9255 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9256 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9257 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9258 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9259 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9260 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9261 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9262 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9264 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9265 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9266 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9267 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9268 I40E_INSET_IPV6_HOP_LIMIT,
9269 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9270 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9271 I40E_INSET_LAST_ETHER_TYPE,
9274 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9276 if (filter == RTE_ETH_FILTER_HASH)
9277 valid = valid_hash_inset_table[pctype];
9279 valid = valid_fdir_inset_table[pctype];
9285 * Validate if the input set is allowed for a specific PCTYPE
9288 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9289 enum rte_filter_type filter, uint64_t inset)
9293 valid = i40e_get_valid_input_set(pctype, filter);
9294 if (inset & (~valid))
9300 /* default input set fields combination per pctype */
9302 i40e_get_default_input_set(uint16_t pctype)
9304 static const uint64_t default_inset_table[] = {
9305 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9306 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9307 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9308 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9309 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9310 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9311 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9312 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9313 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9314 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9315 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9316 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9317 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9318 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9319 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9320 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9321 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9322 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9323 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9324 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9326 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9327 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9328 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9329 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9330 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9331 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9332 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9333 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9334 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9335 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9336 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9337 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9338 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9339 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9340 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9341 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9342 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9343 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9344 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9345 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9346 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9347 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9349 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9350 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9351 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9352 I40E_INSET_LAST_ETHER_TYPE,
9355 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9358 return default_inset_table[pctype];
9362 * Translate the input set from bit masks to register aware bit masks
9366 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9376 static const struct inset_map inset_map_common[] = {
9377 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9378 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9379 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9380 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9381 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9382 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9383 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9384 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9385 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9386 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9387 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9388 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9389 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9390 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9391 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9392 {I40E_INSET_TUNNEL_DMAC,
9393 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9394 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9395 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9396 {I40E_INSET_TUNNEL_SRC_PORT,
9397 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9398 {I40E_INSET_TUNNEL_DST_PORT,
9399 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9400 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9401 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9402 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9403 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9404 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9405 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9406 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9407 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9408 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9411 /* some different registers map in x722*/
9412 static const struct inset_map inset_map_diff_x722[] = {
9413 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9414 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9415 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9416 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9419 static const struct inset_map inset_map_diff_not_x722[] = {
9420 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9421 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9422 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9423 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9429 /* Translate input set to register aware inset */
9430 if (type == I40E_MAC_X722) {
9431 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9432 if (input & inset_map_diff_x722[i].inset)
9433 val |= inset_map_diff_x722[i].inset_reg;
9436 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9437 if (input & inset_map_diff_not_x722[i].inset)
9438 val |= inset_map_diff_not_x722[i].inset_reg;
9442 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9443 if (input & inset_map_common[i].inset)
9444 val |= inset_map_common[i].inset_reg;
9451 i40e_get_inset_field_offset(struct i40e_hw *hw, uint32_t pit_reg_start,
9452 uint32_t pit_reg_count, uint32_t hdr_off)
9454 const uint32_t pit_reg_end = pit_reg_start + pit_reg_count;
9455 uint32_t field_off = I40E_FDIR_FIELD_OFFSET(hdr_off);
9456 uint32_t i, reg_val, src_off, count;
9458 for (i = pit_reg_start; i < pit_reg_end; i++) {
9459 reg_val = i40e_read_rx_ctl(hw, I40E_GLQF_PIT(i));
9461 src_off = I40E_GLQF_PIT_SOURCE_OFF_GET(reg_val);
9462 count = I40E_GLQF_PIT_FSIZE_GET(reg_val);
9464 if (src_off <= field_off && (src_off + count) > field_off)
9468 if (i >= pit_reg_end) {
9470 "Hardware GLQF_PIT configuration does not support this field mask");
9474 return I40E_GLQF_PIT_DEST_OFF_GET(reg_val) + field_off - src_off;
9478 i40e_generate_inset_mask_reg(struct i40e_hw *hw, uint64_t inset,
9479 uint32_t *mask, uint8_t nb_elem)
9481 static const uint64_t mask_inset[] = {
9482 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL,
9483 I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT };
9485 static const struct {
9489 } inset_mask_offset_map[] = {
9490 { I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK,
9491 offsetof(struct rte_ipv4_hdr, type_of_service) },
9493 { I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK,
9494 offsetof(struct rte_ipv4_hdr, next_proto_id) },
9496 { I40E_INSET_IPV4_TTL, I40E_INSET_IPV4_TTL_MASK,
9497 offsetof(struct rte_ipv4_hdr, time_to_live) },
9499 { I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK,
9500 offsetof(struct rte_ipv6_hdr, vtc_flow) },
9502 { I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK,
9503 offsetof(struct rte_ipv6_hdr, proto) },
9505 { I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK,
9506 offsetof(struct rte_ipv6_hdr, hop_limits) },
9516 for (i = 0; i < RTE_DIM(mask_inset); i++) {
9517 /* Clear the inset bit, if no MASK is required,
9518 * for example proto + ttl
9520 if ((mask_inset[i] & inset) == mask_inset[i]) {
9521 inset &= ~mask_inset[i];
9527 for (i = 0; i < RTE_DIM(inset_mask_offset_map); i++) {
9528 uint32_t pit_start, pit_count;
9531 if (!(inset_mask_offset_map[i].inset & inset))
9534 if (inset_mask_offset_map[i].inset &
9535 (I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9536 I40E_INSET_IPV4_TTL)) {
9537 pit_start = I40E_GLQF_PIT_IPV4_START;
9538 pit_count = I40E_GLQF_PIT_IPV4_COUNT;
9540 pit_start = I40E_GLQF_PIT_IPV6_START;
9541 pit_count = I40E_GLQF_PIT_IPV6_COUNT;
9544 offset = i40e_get_inset_field_offset(hw, pit_start, pit_count,
9545 inset_mask_offset_map[i].offset);
9550 if (idx >= nb_elem) {
9552 "Configuration of inset mask out of range %u",
9557 mask[idx] = I40E_GLQF_PIT_BUILD((uint32_t)offset,
9558 inset_mask_offset_map[i].mask);
9566 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9568 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9570 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9572 i40e_write_rx_ctl(hw, addr, val);
9573 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9574 (uint32_t)i40e_read_rx_ctl(hw, addr));
9578 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9580 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9581 struct rte_eth_dev *dev;
9583 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
9585 i40e_write_rx_ctl(hw, addr, val);
9586 PMD_DRV_LOG(WARNING,
9587 "i40e device %s changed global register [0x%08x]."
9588 " original: 0x%08x, new: 0x%08x",
9589 dev->device->name, addr, reg,
9590 (uint32_t)i40e_read_rx_ctl(hw, addr));
9595 i40e_filter_input_set_init(struct i40e_pf *pf)
9597 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9598 enum i40e_filter_pctype pctype;
9599 uint64_t input_set, inset_reg;
9600 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9604 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9605 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9606 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9608 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9611 input_set = i40e_get_default_input_set(pctype);
9613 num = i40e_generate_inset_mask_reg(hw, input_set, mask_reg,
9614 I40E_INSET_MASK_NUM_REG);
9617 if (pf->support_multi_driver && num > 0) {
9618 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9621 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9624 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9625 (uint32_t)(inset_reg & UINT32_MAX));
9626 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9627 (uint32_t)((inset_reg >>
9628 I40E_32_BIT_WIDTH) & UINT32_MAX));
9629 if (!pf->support_multi_driver) {
9630 i40e_check_write_global_reg(hw,
9631 I40E_GLQF_HASH_INSET(0, pctype),
9632 (uint32_t)(inset_reg & UINT32_MAX));
9633 i40e_check_write_global_reg(hw,
9634 I40E_GLQF_HASH_INSET(1, pctype),
9635 (uint32_t)((inset_reg >>
9636 I40E_32_BIT_WIDTH) & UINT32_MAX));
9638 for (i = 0; i < num; i++) {
9639 i40e_check_write_global_reg(hw,
9640 I40E_GLQF_FD_MSK(i, pctype),
9642 i40e_check_write_global_reg(hw,
9643 I40E_GLQF_HASH_MSK(i, pctype),
9646 /*clear unused mask registers of the pctype */
9647 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9648 i40e_check_write_global_reg(hw,
9649 I40E_GLQF_FD_MSK(i, pctype),
9651 i40e_check_write_global_reg(hw,
9652 I40E_GLQF_HASH_MSK(i, pctype),
9656 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9658 I40E_WRITE_FLUSH(hw);
9660 /* store the default input set */
9661 if (!pf->support_multi_driver)
9662 pf->hash_input_set[pctype] = input_set;
9663 pf->fdir.input_set[pctype] = input_set;
9668 i40e_set_hash_inset(struct i40e_hw *hw, uint64_t input_set,
9669 uint32_t pctype, bool add)
9671 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9672 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9673 uint64_t inset_reg = 0;
9676 if (pf->support_multi_driver) {
9678 "Modify input set is not permitted when multi-driver enabled.");
9682 /* For X722, get translated pctype in fd pctype register */
9683 if (hw->mac.type == I40E_MAC_X722)
9684 pctype = i40e_read_rx_ctl(hw, I40E_GLQF_FD_PCTYPES(pctype));
9687 /* get inset value in register */
9688 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9689 inset_reg <<= I40E_32_BIT_WIDTH;
9690 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9691 input_set |= pf->hash_input_set[pctype];
9693 num = i40e_generate_inset_mask_reg(hw, input_set, mask_reg,
9694 I40E_INSET_MASK_NUM_REG);
9698 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9700 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9701 (uint32_t)(inset_reg & UINT32_MAX));
9702 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9703 (uint32_t)((inset_reg >>
9704 I40E_32_BIT_WIDTH) & UINT32_MAX));
9706 for (i = 0; i < num; i++)
9707 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9709 /*clear unused mask registers of the pctype */
9710 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9711 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9713 I40E_WRITE_FLUSH(hw);
9715 pf->hash_input_set[pctype] = input_set;
9719 /* Convert ethertype filter structure */
9721 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9722 struct i40e_ethertype_filter *filter)
9724 rte_memcpy(&filter->input.mac_addr, &input->mac_addr,
9725 RTE_ETHER_ADDR_LEN);
9726 filter->input.ether_type = input->ether_type;
9727 filter->flags = input->flags;
9728 filter->queue = input->queue;
9733 /* Check if there exists the ehtertype filter */
9734 struct i40e_ethertype_filter *
9735 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9736 const struct i40e_ethertype_filter_input *input)
9740 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9744 return ethertype_rule->hash_map[ret];
9747 /* Add ethertype filter in SW list */
9749 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9750 struct i40e_ethertype_filter *filter)
9752 struct i40e_ethertype_rule *rule = &pf->ethertype;
9755 ret = rte_hash_add_key(rule->hash_table, &filter->input);
9758 "Failed to insert ethertype filter"
9759 " to hash table %d!",
9763 rule->hash_map[ret] = filter;
9765 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9770 /* Delete ethertype filter in SW list */
9772 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9773 struct i40e_ethertype_filter_input *input)
9775 struct i40e_ethertype_rule *rule = &pf->ethertype;
9776 struct i40e_ethertype_filter *filter;
9779 ret = rte_hash_del_key(rule->hash_table, input);
9782 "Failed to delete ethertype filter"
9783 " to hash table %d!",
9787 filter = rule->hash_map[ret];
9788 rule->hash_map[ret] = NULL;
9790 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9797 * Configure ethertype filter, which can director packet by filtering
9798 * with mac address and ether_type or only ether_type
9801 i40e_ethertype_filter_set(struct i40e_pf *pf,
9802 struct rte_eth_ethertype_filter *filter,
9805 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9806 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9807 struct i40e_ethertype_filter *ethertype_filter, *node;
9808 struct i40e_ethertype_filter check_filter;
9809 struct i40e_control_filter_stats stats;
9813 if (filter->queue >= pf->dev_data->nb_rx_queues) {
9814 PMD_DRV_LOG(ERR, "Invalid queue ID");
9817 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
9818 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
9820 "unsupported ether_type(0x%04x) in control packet filter.",
9821 filter->ether_type);
9824 if (filter->ether_type == RTE_ETHER_TYPE_VLAN)
9825 PMD_DRV_LOG(WARNING,
9826 "filter vlan ether_type in first tag is not supported.");
9828 /* Check if there is the filter in SW list */
9829 memset(&check_filter, 0, sizeof(check_filter));
9830 i40e_ethertype_filter_convert(filter, &check_filter);
9831 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9832 &check_filter.input);
9834 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9838 if (!add && !node) {
9839 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9843 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9844 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9845 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9846 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9847 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9849 memset(&stats, 0, sizeof(stats));
9850 ret = i40e_aq_add_rem_control_packet_filter(hw,
9851 filter->mac_addr.addr_bytes,
9852 filter->ether_type, flags,
9854 filter->queue, add, &stats, NULL);
9857 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9858 ret, stats.mac_etype_used, stats.etype_used,
9859 stats.mac_etype_free, stats.etype_free);
9863 /* Add or delete a filter in SW list */
9865 ethertype_filter = rte_zmalloc("ethertype_filter",
9866 sizeof(*ethertype_filter), 0);
9867 if (ethertype_filter == NULL) {
9868 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
9872 rte_memcpy(ethertype_filter, &check_filter,
9873 sizeof(check_filter));
9874 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9876 rte_free(ethertype_filter);
9878 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9885 i40e_dev_flow_ops_get(struct rte_eth_dev *dev,
9886 const struct rte_flow_ops **ops)
9891 *ops = &i40e_flow_ops;
9896 * Check and enable Extended Tag.
9897 * Enabling Extended Tag is important for 40G performance.
9900 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9902 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9906 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9909 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9913 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9914 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9919 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9922 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9926 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9927 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9930 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9931 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9934 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9941 * As some registers wouldn't be reset unless a global hardware reset,
9942 * hardware initialization is needed to put those registers into an
9943 * expected initial state.
9946 i40e_hw_init(struct rte_eth_dev *dev)
9948 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9950 i40e_enable_extended_tag(dev);
9952 /* clear the PF Queue Filter control register */
9953 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9955 /* Disable symmetric hash per port */
9956 i40e_set_symmetric_hash_enable_per_port(hw, 0);
9960 * For X722 it is possible to have multiple pctypes mapped to the same flowtype
9961 * however this function will return only one highest pctype index,
9962 * which is not quite correct. This is known problem of i40e driver
9963 * and needs to be fixed later.
9965 enum i40e_filter_pctype
9966 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
9969 uint64_t pctype_mask;
9971 if (flow_type < I40E_FLOW_TYPE_MAX) {
9972 pctype_mask = adapter->pctypes_tbl[flow_type];
9973 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
9974 if (pctype_mask & (1ULL << i))
9975 return (enum i40e_filter_pctype)i;
9978 return I40E_FILTER_PCTYPE_INVALID;
9982 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
9983 enum i40e_filter_pctype pctype)
9986 uint64_t pctype_mask = 1ULL << pctype;
9988 for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
9990 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
9994 return RTE_ETH_FLOW_UNKNOWN;
9998 * On X710, performance number is far from the expectation on recent firmware
9999 * versions; on XL710, performance number is also far from the expectation on
10000 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10001 * mode is enabled and port MAC address is equal to the packet destination MAC
10002 * address. The fix for this issue may not be integrated in the following
10003 * firmware version. So the workaround in software driver is needed. It needs
10004 * to modify the initial values of 3 internal only registers for both X710 and
10005 * XL710. Note that the values for X710 or XL710 could be different, and the
10006 * workaround can be removed when it is fixed in firmware in the future.
10009 /* For both X710 and XL710 */
10010 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1 0x10000200
10011 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x203F0200
10012 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
10014 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10015 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
10018 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10019 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10022 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
10024 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
10025 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
10028 * GL_SWR_PM_UP_THR:
10029 * The value is not impacted from the link speed, its value is set according
10030 * to the total number of ports for a better pipe-monitor configuration.
10033 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10035 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10036 .device_id = (dev), \
10037 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10039 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10040 .device_id = (dev), \
10041 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10043 static const struct {
10044 uint16_t device_id;
10046 } swr_pm_table[] = {
10047 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10048 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10049 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10050 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10051 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_X722) },
10053 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10054 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10055 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10056 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10057 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10058 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10059 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10063 if (value == NULL) {
10064 PMD_DRV_LOG(ERR, "value is NULL");
10068 for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10069 if (hw->device_id == swr_pm_table[i].device_id) {
10070 *value = swr_pm_table[i].val;
10072 PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10074 hw->device_id, *value);
10083 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10085 enum i40e_status_code status;
10086 struct i40e_aq_get_phy_abilities_resp phy_ab;
10087 int ret = -ENOTSUP;
10090 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10094 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10097 rte_delay_us(100000);
10099 status = i40e_aq_get_phy_capabilities(hw, false,
10100 true, &phy_ab, NULL);
10108 i40e_configure_registers(struct i40e_hw *hw)
10114 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10115 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10116 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10122 for (i = 0; i < RTE_DIM(reg_table); i++) {
10123 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10124 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10126 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10127 else /* For X710/XL710/XXV710 */
10128 if (hw->aq.fw_maj_ver < 6)
10130 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10133 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10136 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10137 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10139 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10140 else /* For X710/XL710/XXV710 */
10142 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10145 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10148 if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10149 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10150 "GL_SWR_PM_UP_THR value fixup",
10155 reg_table[i].val = cfg_val;
10158 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10161 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10162 reg_table[i].addr);
10165 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10166 reg_table[i].addr, reg);
10167 if (reg == reg_table[i].val)
10170 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10171 reg_table[i].val, NULL);
10174 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10175 reg_table[i].val, reg_table[i].addr);
10178 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10179 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10183 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
10184 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
10185 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10187 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10192 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10193 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10197 /* Configure for double VLAN RX stripping */
10198 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10199 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10200 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10201 ret = i40e_aq_debug_write_register(hw,
10202 I40E_VSI_TSR(vsi->vsi_id),
10205 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10207 return I40E_ERR_CONFIG;
10211 /* Configure for double VLAN TX insertion */
10212 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10213 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10214 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10215 ret = i40e_aq_debug_write_register(hw,
10216 I40E_VSI_L2TAGSTXVALID(
10217 vsi->vsi_id), reg, NULL);
10220 "Failed to update VSI_L2TAGSTXVALID[%d]",
10222 return I40E_ERR_CONFIG;
10230 * i40e_aq_add_mirror_rule
10231 * @hw: pointer to the hardware structure
10232 * @seid: VEB seid to add mirror rule to
10233 * @dst_id: destination vsi seid
10234 * @entries: Buffer which contains the entities to be mirrored
10235 * @count: number of entities contained in the buffer
10236 * @rule_id:the rule_id of the rule to be added
10238 * Add a mirror rule for a given veb.
10241 static enum i40e_status_code
10242 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10243 uint16_t seid, uint16_t dst_id,
10244 uint16_t rule_type, uint16_t *entries,
10245 uint16_t count, uint16_t *rule_id)
10247 struct i40e_aq_desc desc;
10248 struct i40e_aqc_add_delete_mirror_rule cmd;
10249 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10250 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10253 enum i40e_status_code status;
10255 i40e_fill_default_direct_cmd_desc(&desc,
10256 i40e_aqc_opc_add_mirror_rule);
10257 memset(&cmd, 0, sizeof(cmd));
10259 buff_len = sizeof(uint16_t) * count;
10260 desc.datalen = rte_cpu_to_le_16(buff_len);
10262 desc.flags |= rte_cpu_to_le_16(
10263 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10264 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10265 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10266 cmd.num_entries = rte_cpu_to_le_16(count);
10267 cmd.seid = rte_cpu_to_le_16(seid);
10268 cmd.destination = rte_cpu_to_le_16(dst_id);
10270 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10271 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10273 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10274 hw->aq.asq_last_status, resp->rule_id,
10275 resp->mirror_rules_used, resp->mirror_rules_free);
10276 *rule_id = rte_le_to_cpu_16(resp->rule_id);
10282 * i40e_aq_del_mirror_rule
10283 * @hw: pointer to the hardware structure
10284 * @seid: VEB seid to add mirror rule to
10285 * @entries: Buffer which contains the entities to be mirrored
10286 * @count: number of entities contained in the buffer
10287 * @rule_id:the rule_id of the rule to be delete
10289 * Delete a mirror rule for a given veb.
10292 static enum i40e_status_code
10293 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10294 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10295 uint16_t count, uint16_t rule_id)
10297 struct i40e_aq_desc desc;
10298 struct i40e_aqc_add_delete_mirror_rule cmd;
10299 uint16_t buff_len = 0;
10300 enum i40e_status_code status;
10303 i40e_fill_default_direct_cmd_desc(&desc,
10304 i40e_aqc_opc_delete_mirror_rule);
10305 memset(&cmd, 0, sizeof(cmd));
10306 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10307 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10309 cmd.num_entries = count;
10310 buff_len = sizeof(uint16_t) * count;
10311 desc.datalen = rte_cpu_to_le_16(buff_len);
10312 buff = (void *)entries;
10314 /* rule id is filled in destination field for deleting mirror rule */
10315 cmd.destination = rte_cpu_to_le_16(rule_id);
10317 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10318 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10319 cmd.seid = rte_cpu_to_le_16(seid);
10321 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10322 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10328 * i40e_mirror_rule_set
10329 * @dev: pointer to the hardware structure
10330 * @mirror_conf: mirror rule info
10331 * @sw_id: mirror rule's sw_id
10332 * @on: enable/disable
10334 * set a mirror rule.
10338 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10339 struct rte_eth_mirror_conf *mirror_conf,
10340 uint8_t sw_id, uint8_t on)
10342 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10343 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10344 struct i40e_mirror_rule *it, *mirr_rule = NULL;
10345 struct i40e_mirror_rule *parent = NULL;
10346 uint16_t seid, dst_seid, rule_id;
10350 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10352 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10354 "mirror rule can not be configured without veb or vfs.");
10357 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10358 PMD_DRV_LOG(ERR, "mirror table is full.");
10361 if (mirror_conf->dst_pool > pf->vf_num) {
10362 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10363 mirror_conf->dst_pool);
10367 seid = pf->main_vsi->veb->seid;
10369 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10370 if (sw_id <= it->index) {
10376 if (mirr_rule && sw_id == mirr_rule->index) {
10378 PMD_DRV_LOG(ERR, "mirror rule exists.");
10381 ret = i40e_aq_del_mirror_rule(hw, seid,
10382 mirr_rule->rule_type,
10383 mirr_rule->entries,
10384 mirr_rule->num_entries, mirr_rule->id);
10387 "failed to remove mirror rule: ret = %d, aq_err = %d.",
10388 ret, hw->aq.asq_last_status);
10391 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10392 rte_free(mirr_rule);
10393 pf->nb_mirror_rule--;
10397 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10401 mirr_rule = rte_zmalloc("i40e_mirror_rule",
10402 sizeof(struct i40e_mirror_rule) , 0);
10404 PMD_DRV_LOG(ERR, "failed to allocate memory");
10405 return I40E_ERR_NO_MEMORY;
10407 switch (mirror_conf->rule_type) {
10408 case ETH_MIRROR_VLAN:
10409 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10410 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10411 mirr_rule->entries[j] =
10412 mirror_conf->vlan.vlan_id[i];
10417 PMD_DRV_LOG(ERR, "vlan is not specified.");
10418 rte_free(mirr_rule);
10421 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10423 case ETH_MIRROR_VIRTUAL_POOL_UP:
10424 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10425 /* check if the specified pool bit is out of range */
10426 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10427 PMD_DRV_LOG(ERR, "pool mask is out of range.");
10428 rte_free(mirr_rule);
10431 for (i = 0, j = 0; i < pf->vf_num; i++) {
10432 if (mirror_conf->pool_mask & (1ULL << i)) {
10433 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10437 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10438 /* add pf vsi to entries */
10439 mirr_rule->entries[j] = pf->main_vsi_seid;
10443 PMD_DRV_LOG(ERR, "pool is not specified.");
10444 rte_free(mirr_rule);
10447 /* egress and ingress in aq commands means from switch but not port */
10448 mirr_rule->rule_type =
10449 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10450 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10451 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10453 case ETH_MIRROR_UPLINK_PORT:
10454 /* egress and ingress in aq commands means from switch but not port*/
10455 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10457 case ETH_MIRROR_DOWNLINK_PORT:
10458 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10461 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10462 mirror_conf->rule_type);
10463 rte_free(mirr_rule);
10467 /* If the dst_pool is equal to vf_num, consider it as PF */
10468 if (mirror_conf->dst_pool == pf->vf_num)
10469 dst_seid = pf->main_vsi_seid;
10471 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10473 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10474 mirr_rule->rule_type, mirr_rule->entries,
10478 "failed to add mirror rule: ret = %d, aq_err = %d.",
10479 ret, hw->aq.asq_last_status);
10480 rte_free(mirr_rule);
10484 mirr_rule->index = sw_id;
10485 mirr_rule->num_entries = j;
10486 mirr_rule->id = rule_id;
10487 mirr_rule->dst_vsi_seid = dst_seid;
10490 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10492 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10494 pf->nb_mirror_rule++;
10499 * i40e_mirror_rule_reset
10500 * @dev: pointer to the device
10501 * @sw_id: mirror rule's sw_id
10503 * reset a mirror rule.
10507 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10509 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10510 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10511 struct i40e_mirror_rule *it, *mirr_rule = NULL;
10515 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10517 seid = pf->main_vsi->veb->seid;
10519 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10520 if (sw_id == it->index) {
10526 ret = i40e_aq_del_mirror_rule(hw, seid,
10527 mirr_rule->rule_type,
10528 mirr_rule->entries,
10529 mirr_rule->num_entries, mirr_rule->id);
10532 "failed to remove mirror rule: status = %d, aq_err = %d.",
10533 ret, hw->aq.asq_last_status);
10536 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10537 rte_free(mirr_rule);
10538 pf->nb_mirror_rule--;
10540 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10547 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10549 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10550 uint64_t systim_cycles;
10552 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10553 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10556 return systim_cycles;
10560 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10562 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10563 uint64_t rx_tstamp;
10565 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10566 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10573 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10575 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10576 uint64_t tx_tstamp;
10578 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10579 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10586 i40e_start_timecounters(struct rte_eth_dev *dev)
10588 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10589 struct i40e_adapter *adapter = dev->data->dev_private;
10590 struct rte_eth_link link;
10591 uint32_t tsync_inc_l;
10592 uint32_t tsync_inc_h;
10594 /* Get current link speed. */
10595 i40e_dev_link_update(dev, 1);
10596 rte_eth_linkstatus_get(dev, &link);
10598 switch (link.link_speed) {
10599 case ETH_SPEED_NUM_40G:
10600 case ETH_SPEED_NUM_25G:
10601 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10602 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10604 case ETH_SPEED_NUM_10G:
10605 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10606 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10608 case ETH_SPEED_NUM_1G:
10609 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10610 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10617 /* Set the timesync increment value. */
10618 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10619 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10621 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10622 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10623 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10625 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10626 adapter->systime_tc.cc_shift = 0;
10627 adapter->systime_tc.nsec_mask = 0;
10629 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10630 adapter->rx_tstamp_tc.cc_shift = 0;
10631 adapter->rx_tstamp_tc.nsec_mask = 0;
10633 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10634 adapter->tx_tstamp_tc.cc_shift = 0;
10635 adapter->tx_tstamp_tc.nsec_mask = 0;
10639 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10641 struct i40e_adapter *adapter = dev->data->dev_private;
10643 adapter->systime_tc.nsec += delta;
10644 adapter->rx_tstamp_tc.nsec += delta;
10645 adapter->tx_tstamp_tc.nsec += delta;
10651 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10654 struct i40e_adapter *adapter = dev->data->dev_private;
10656 ns = rte_timespec_to_ns(ts);
10658 /* Set the timecounters to a new value. */
10659 adapter->systime_tc.nsec = ns;
10660 adapter->rx_tstamp_tc.nsec = ns;
10661 adapter->tx_tstamp_tc.nsec = ns;
10667 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10669 uint64_t ns, systime_cycles;
10670 struct i40e_adapter *adapter = dev->data->dev_private;
10672 systime_cycles = i40e_read_systime_cyclecounter(dev);
10673 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10674 *ts = rte_ns_to_timespec(ns);
10680 i40e_timesync_enable(struct rte_eth_dev *dev)
10682 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10683 uint32_t tsync_ctl_l;
10684 uint32_t tsync_ctl_h;
10686 /* Stop the timesync system time. */
10687 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10688 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10689 /* Reset the timesync system time value. */
10690 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10691 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10693 i40e_start_timecounters(dev);
10695 /* Clear timesync registers. */
10696 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10697 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10698 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10699 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10700 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10701 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10703 /* Enable timestamping of PTP packets. */
10704 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10705 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10707 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10708 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10709 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10711 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10712 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10718 i40e_timesync_disable(struct rte_eth_dev *dev)
10720 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10721 uint32_t tsync_ctl_l;
10722 uint32_t tsync_ctl_h;
10724 /* Disable timestamping of transmitted PTP packets. */
10725 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10726 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10728 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10729 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10731 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10732 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10734 /* Reset the timesync increment value. */
10735 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10736 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10742 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10743 struct timespec *timestamp, uint32_t flags)
10745 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10746 struct i40e_adapter *adapter = dev->data->dev_private;
10747 uint32_t sync_status;
10748 uint32_t index = flags & 0x03;
10749 uint64_t rx_tstamp_cycles;
10752 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10753 if ((sync_status & (1 << index)) == 0)
10756 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10757 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10758 *timestamp = rte_ns_to_timespec(ns);
10764 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10765 struct timespec *timestamp)
10767 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10768 struct i40e_adapter *adapter = dev->data->dev_private;
10769 uint32_t sync_status;
10770 uint64_t tx_tstamp_cycles;
10773 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10774 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10777 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10778 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10779 *timestamp = rte_ns_to_timespec(ns);
10785 * i40e_parse_dcb_configure - parse dcb configure from user
10786 * @dev: the device being configured
10787 * @dcb_cfg: pointer of the result of parse
10788 * @*tc_map: bit map of enabled traffic classes
10790 * Returns 0 on success, negative value on failure
10793 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10794 struct i40e_dcbx_config *dcb_cfg,
10797 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10798 uint8_t i, tc_bw, bw_lf;
10800 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10802 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10803 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10804 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10808 /* assume each tc has the same bw */
10809 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10810 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10811 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10812 /* to ensure the sum of tcbw is equal to 100 */
10813 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10814 for (i = 0; i < bw_lf; i++)
10815 dcb_cfg->etscfg.tcbwtable[i]++;
10817 /* assume each tc has the same Transmission Selection Algorithm */
10818 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10819 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10821 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10822 dcb_cfg->etscfg.prioritytable[i] =
10823 dcb_rx_conf->dcb_tc[i];
10825 /* FW needs one App to configure HW */
10826 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10827 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10828 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10829 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10831 if (dcb_rx_conf->nb_tcs == 0)
10832 *tc_map = 1; /* tc0 only */
10834 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10836 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10837 dcb_cfg->pfc.willing = 0;
10838 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10839 dcb_cfg->pfc.pfcenable = *tc_map;
10845 static enum i40e_status_code
10846 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10847 struct i40e_aqc_vsi_properties_data *info,
10848 uint8_t enabled_tcmap)
10850 enum i40e_status_code ret;
10851 int i, total_tc = 0;
10852 uint16_t qpnum_per_tc, bsf, qp_idx;
10853 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10854 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10855 uint16_t used_queues;
10857 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10858 if (ret != I40E_SUCCESS)
10861 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10862 if (enabled_tcmap & (1 << i))
10867 vsi->enabled_tc = enabled_tcmap;
10869 /* different VSI has different queues assigned */
10870 if (vsi->type == I40E_VSI_MAIN)
10871 used_queues = dev_data->nb_rx_queues -
10872 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10873 else if (vsi->type == I40E_VSI_VMDQ2)
10874 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10876 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10877 return I40E_ERR_NO_AVAILABLE_VSI;
10880 qpnum_per_tc = used_queues / total_tc;
10881 /* Number of queues per enabled TC */
10882 if (qpnum_per_tc == 0) {
10883 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10884 return I40E_ERR_INVALID_QP_ID;
10886 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10887 I40E_MAX_Q_PER_TC);
10888 bsf = rte_bsf32(qpnum_per_tc);
10891 * Configure TC and queue mapping parameters, for enabled TC,
10892 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10893 * default queue will serve it.
10896 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10897 if (vsi->enabled_tc & (1 << i)) {
10898 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10899 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10900 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10901 qp_idx += qpnum_per_tc;
10903 info->tc_mapping[i] = 0;
10906 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10907 if (vsi->type == I40E_VSI_SRIOV) {
10908 info->mapping_flags |=
10909 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10910 for (i = 0; i < vsi->nb_qps; i++)
10911 info->queue_mapping[i] =
10912 rte_cpu_to_le_16(vsi->base_queue + i);
10914 info->mapping_flags |=
10915 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10916 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10918 info->valid_sections |=
10919 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10921 return I40E_SUCCESS;
10925 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10926 * @veb: VEB to be configured
10927 * @tc_map: enabled TC bitmap
10929 * Returns 0 on success, negative value on failure
10931 static enum i40e_status_code
10932 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10934 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10935 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10936 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10937 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10938 enum i40e_status_code ret = I40E_SUCCESS;
10942 /* Check if enabled_tc is same as existing or new TCs */
10943 if (veb->enabled_tc == tc_map)
10946 /* configure tc bandwidth */
10947 memset(&veb_bw, 0, sizeof(veb_bw));
10948 veb_bw.tc_valid_bits = tc_map;
10949 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10950 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10951 if (tc_map & BIT_ULL(i))
10952 veb_bw.tc_bw_share_credits[i] = 1;
10954 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10958 "AQ command Config switch_comp BW allocation per TC failed = %d",
10959 hw->aq.asq_last_status);
10963 memset(&ets_query, 0, sizeof(ets_query));
10964 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10966 if (ret != I40E_SUCCESS) {
10968 "Failed to get switch_comp ETS configuration %u",
10969 hw->aq.asq_last_status);
10972 memset(&bw_query, 0, sizeof(bw_query));
10973 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10975 if (ret != I40E_SUCCESS) {
10977 "Failed to get switch_comp bandwidth configuration %u",
10978 hw->aq.asq_last_status);
10982 /* store and print out BW info */
10983 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10984 veb->bw_info.bw_max = ets_query.tc_bw_max;
10985 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10986 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10987 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10988 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10989 I40E_16_BIT_WIDTH);
10990 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10991 veb->bw_info.bw_ets_share_credits[i] =
10992 bw_query.tc_bw_share_credits[i];
10993 veb->bw_info.bw_ets_credits[i] =
10994 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10995 /* 4 bits per TC, 4th bit is reserved */
10996 veb->bw_info.bw_ets_max[i] =
10997 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10998 RTE_LEN2MASK(3, uint8_t));
10999 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
11000 veb->bw_info.bw_ets_share_credits[i]);
11001 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11002 veb->bw_info.bw_ets_credits[i]);
11003 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11004 veb->bw_info.bw_ets_max[i]);
11007 veb->enabled_tc = tc_map;
11014 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11015 * @vsi: VSI to be configured
11016 * @tc_map: enabled TC bitmap
11018 * Returns 0 on success, negative value on failure
11020 static enum i40e_status_code
11021 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11023 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11024 struct i40e_vsi_context ctxt;
11025 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11026 enum i40e_status_code ret = I40E_SUCCESS;
11029 /* Check if enabled_tc is same as existing or new TCs */
11030 if (vsi->enabled_tc == tc_map)
11033 /* configure tc bandwidth */
11034 memset(&bw_data, 0, sizeof(bw_data));
11035 bw_data.tc_valid_bits = tc_map;
11036 /* Enable ETS TCs with equal BW Share for now across all VSIs */
11037 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11038 if (tc_map & BIT_ULL(i))
11039 bw_data.tc_bw_credits[i] = 1;
11041 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11044 "AQ command Config VSI BW allocation per TC failed = %d",
11045 hw->aq.asq_last_status);
11048 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11049 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11051 /* Update Queue Pairs Mapping for currently enabled UPs */
11052 ctxt.seid = vsi->seid;
11053 ctxt.pf_num = hw->pf_id;
11055 ctxt.uplink_seid = vsi->uplink_seid;
11056 ctxt.info = vsi->info;
11058 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11062 /* Update the VSI after updating the VSI queue-mapping information */
11063 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11065 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11066 hw->aq.asq_last_status);
11069 /* update the local VSI info with updated queue map */
11070 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11071 sizeof(vsi->info.tc_mapping));
11072 rte_memcpy(&vsi->info.queue_mapping,
11073 &ctxt.info.queue_mapping,
11074 sizeof(vsi->info.queue_mapping));
11075 vsi->info.mapping_flags = ctxt.info.mapping_flags;
11076 vsi->info.valid_sections = 0;
11078 /* query and update current VSI BW information */
11079 ret = i40e_vsi_get_bw_config(vsi);
11082 "Failed updating vsi bw info, err %s aq_err %s",
11083 i40e_stat_str(hw, ret),
11084 i40e_aq_str(hw, hw->aq.asq_last_status));
11088 vsi->enabled_tc = tc_map;
11095 * i40e_dcb_hw_configure - program the dcb setting to hw
11096 * @pf: pf the configuration is taken on
11097 * @new_cfg: new configuration
11098 * @tc_map: enabled TC bitmap
11100 * Returns 0 on success, negative value on failure
11102 static enum i40e_status_code
11103 i40e_dcb_hw_configure(struct i40e_pf *pf,
11104 struct i40e_dcbx_config *new_cfg,
11107 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11108 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11109 struct i40e_vsi *main_vsi = pf->main_vsi;
11110 struct i40e_vsi_list *vsi_list;
11111 enum i40e_status_code ret;
11115 /* Use the FW API if FW > v4.4*/
11116 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11117 (hw->aq.fw_maj_ver >= 5))) {
11119 "FW < v4.4, can not use FW LLDP API to configure DCB");
11120 return I40E_ERR_FIRMWARE_API_VERSION;
11123 /* Check if need reconfiguration */
11124 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11125 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11126 return I40E_SUCCESS;
11129 /* Copy the new config to the current config */
11130 *old_cfg = *new_cfg;
11131 old_cfg->etsrec = old_cfg->etscfg;
11132 ret = i40e_set_dcb_config(hw);
11134 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11135 i40e_stat_str(hw, ret),
11136 i40e_aq_str(hw, hw->aq.asq_last_status));
11139 /* set receive Arbiter to RR mode and ETS scheme by default */
11140 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11141 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11142 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
11143 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11144 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11145 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11146 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11147 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11148 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11149 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11150 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11151 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11152 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11154 /* get local mib to check whether it is configured correctly */
11156 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11157 /* Get Local DCB Config */
11158 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11159 &hw->local_dcbx_config);
11161 /* if Veb is created, need to update TC of it at first */
11162 if (main_vsi->veb) {
11163 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11165 PMD_INIT_LOG(WARNING,
11166 "Failed configuring TC for VEB seid=%d",
11167 main_vsi->veb->seid);
11169 /* Update each VSI */
11170 i40e_vsi_config_tc(main_vsi, tc_map);
11171 if (main_vsi->veb) {
11172 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11173 /* Beside main VSI and VMDQ VSIs, only enable default
11174 * TC for other VSIs
11176 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11177 ret = i40e_vsi_config_tc(vsi_list->vsi,
11180 ret = i40e_vsi_config_tc(vsi_list->vsi,
11181 I40E_DEFAULT_TCMAP);
11183 PMD_INIT_LOG(WARNING,
11184 "Failed configuring TC for VSI seid=%d",
11185 vsi_list->vsi->seid);
11189 return I40E_SUCCESS;
11193 * i40e_dcb_init_configure - initial dcb config
11194 * @dev: device being configured
11195 * @sw_dcb: indicate whether dcb is sw configured or hw offload
11197 * Returns 0 on success, negative value on failure
11200 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11202 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11203 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11206 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11207 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11211 /* DCB initialization:
11212 * Update DCB configuration from the Firmware and configure
11213 * LLDP MIB change event.
11215 if (sw_dcb == TRUE) {
11216 /* Stopping lldp is necessary for DPDK, but it will cause
11217 * DCB init failed. For i40e_init_dcb(), the prerequisite
11218 * for successful initialization of DCB is that LLDP is
11219 * enabled. So it is needed to start lldp before DCB init
11220 * and stop it after initialization.
11222 ret = i40e_aq_start_lldp(hw, true, NULL);
11223 if (ret != I40E_SUCCESS)
11224 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11226 ret = i40e_init_dcb(hw, true);
11227 /* If lldp agent is stopped, the return value from
11228 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11229 * adminq status. Otherwise, it should return success.
11231 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11232 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11233 memset(&hw->local_dcbx_config, 0,
11234 sizeof(struct i40e_dcbx_config));
11235 /* set dcb default configuration */
11236 hw->local_dcbx_config.etscfg.willing = 0;
11237 hw->local_dcbx_config.etscfg.maxtcs = 0;
11238 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11239 hw->local_dcbx_config.etscfg.tsatable[0] =
11241 /* all UPs mapping to TC0 */
11242 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11243 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11244 hw->local_dcbx_config.etsrec =
11245 hw->local_dcbx_config.etscfg;
11246 hw->local_dcbx_config.pfc.willing = 0;
11247 hw->local_dcbx_config.pfc.pfccap =
11248 I40E_MAX_TRAFFIC_CLASS;
11249 /* FW needs one App to configure HW */
11250 hw->local_dcbx_config.numapps = 1;
11251 hw->local_dcbx_config.app[0].selector =
11252 I40E_APP_SEL_ETHTYPE;
11253 hw->local_dcbx_config.app[0].priority = 3;
11254 hw->local_dcbx_config.app[0].protocolid =
11255 I40E_APP_PROTOID_FCOE;
11256 ret = i40e_set_dcb_config(hw);
11259 "default dcb config fails. err = %d, aq_err = %d.",
11260 ret, hw->aq.asq_last_status);
11265 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11266 ret, hw->aq.asq_last_status);
11270 if (i40e_need_stop_lldp(dev)) {
11271 ret = i40e_aq_stop_lldp(hw, true, true, NULL);
11272 if (ret != I40E_SUCCESS)
11273 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
11276 ret = i40e_aq_start_lldp(hw, true, NULL);
11277 if (ret != I40E_SUCCESS)
11278 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11280 ret = i40e_init_dcb(hw, true);
11282 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11284 "HW doesn't support DCBX offload.");
11289 "DCBX configuration failed, err = %d, aq_err = %d.",
11290 ret, hw->aq.asq_last_status);
11298 * i40e_dcb_setup - setup dcb related config
11299 * @dev: device being configured
11301 * Returns 0 on success, negative value on failure
11304 i40e_dcb_setup(struct rte_eth_dev *dev)
11306 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11307 struct i40e_dcbx_config dcb_cfg;
11308 uint8_t tc_map = 0;
11311 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11312 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11316 if (pf->vf_num != 0)
11317 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11319 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11321 PMD_INIT_LOG(ERR, "invalid dcb config");
11324 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11326 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11334 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11335 struct rte_eth_dcb_info *dcb_info)
11337 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11338 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11339 struct i40e_vsi *vsi = pf->main_vsi;
11340 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11341 uint16_t bsf, tc_mapping;
11344 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11345 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11347 dcb_info->nb_tcs = 1;
11348 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11349 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11350 for (i = 0; i < dcb_info->nb_tcs; i++)
11351 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11353 /* get queue mapping if vmdq is disabled */
11354 if (!pf->nb_cfg_vmdq_vsi) {
11355 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11356 if (!(vsi->enabled_tc & (1 << i)))
11358 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11359 dcb_info->tc_queue.tc_rxq[j][i].base =
11360 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11361 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11362 dcb_info->tc_queue.tc_txq[j][i].base =
11363 dcb_info->tc_queue.tc_rxq[j][i].base;
11364 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11365 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11366 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11367 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11368 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11373 /* get queue mapping if vmdq is enabled */
11375 vsi = pf->vmdq[j].vsi;
11376 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11377 if (!(vsi->enabled_tc & (1 << i)))
11379 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11380 dcb_info->tc_queue.tc_rxq[j][i].base =
11381 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11382 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11383 dcb_info->tc_queue.tc_txq[j][i].base =
11384 dcb_info->tc_queue.tc_rxq[j][i].base;
11385 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11386 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11387 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11388 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11389 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11392 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11397 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11399 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11400 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11401 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11402 uint16_t msix_intr;
11404 msix_intr = intr_handle->intr_vec[queue_id];
11405 if (msix_intr == I40E_MISC_VEC_ID)
11406 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11407 I40E_PFINT_DYN_CTL0_INTENA_MASK |
11408 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11409 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11412 I40E_PFINT_DYN_CTLN(msix_intr -
11413 I40E_RX_VEC_START),
11414 I40E_PFINT_DYN_CTLN_INTENA_MASK |
11415 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11416 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11418 I40E_WRITE_FLUSH(hw);
11419 rte_intr_ack(&pci_dev->intr_handle);
11425 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11427 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11428 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11429 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11430 uint16_t msix_intr;
11432 msix_intr = intr_handle->intr_vec[queue_id];
11433 if (msix_intr == I40E_MISC_VEC_ID)
11434 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11435 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11438 I40E_PFINT_DYN_CTLN(msix_intr -
11439 I40E_RX_VEC_START),
11440 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11441 I40E_WRITE_FLUSH(hw);
11447 * This function is used to check if the register is valid.
11448 * Below is the valid registers list for X722 only:
11452 * 0x208e00--0x209000
11453 * 0x20be00--0x20c000
11454 * 0x263c00--0x264000
11455 * 0x265c00--0x266000
11457 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset)
11459 if ((type != I40E_MAC_X722) &&
11460 ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) ||
11461 (reg_offset >= 0x38700 && reg_offset <= 0x38a00) ||
11462 (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) ||
11463 (reg_offset >= 0x208e00 && reg_offset <= 0x209000) ||
11464 (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) ||
11465 (reg_offset >= 0x263c00 && reg_offset <= 0x264000) ||
11466 (reg_offset >= 0x265c00 && reg_offset <= 0x266000)))
11472 static int i40e_get_regs(struct rte_eth_dev *dev,
11473 struct rte_dev_reg_info *regs)
11475 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11476 uint32_t *ptr_data = regs->data;
11477 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11478 const struct i40e_reg_info *reg_info;
11480 if (ptr_data == NULL) {
11481 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11482 regs->width = sizeof(uint32_t);
11486 /* The first few registers have to be read using AQ operations */
11488 while (i40e_regs_adminq[reg_idx].name) {
11489 reg_info = &i40e_regs_adminq[reg_idx++];
11490 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11492 arr_idx2 <= reg_info->count2;
11494 reg_offset = arr_idx * reg_info->stride1 +
11495 arr_idx2 * reg_info->stride2;
11496 reg_offset += reg_info->base_addr;
11497 ptr_data[reg_offset >> 2] =
11498 i40e_read_rx_ctl(hw, reg_offset);
11502 /* The remaining registers can be read using primitives */
11504 while (i40e_regs_others[reg_idx].name) {
11505 reg_info = &i40e_regs_others[reg_idx++];
11506 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11508 arr_idx2 <= reg_info->count2;
11510 reg_offset = arr_idx * reg_info->stride1 +
11511 arr_idx2 * reg_info->stride2;
11512 reg_offset += reg_info->base_addr;
11513 if (!i40e_valid_regs(hw->mac.type, reg_offset))
11514 ptr_data[reg_offset >> 2] = 0;
11516 ptr_data[reg_offset >> 2] =
11517 I40E_READ_REG(hw, reg_offset);
11524 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11526 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11528 /* Convert word count to byte count */
11529 return hw->nvm.sr_size << 1;
11532 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11533 struct rte_dev_eeprom_info *eeprom)
11535 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11536 uint16_t *data = eeprom->data;
11537 uint16_t offset, length, cnt_words;
11540 offset = eeprom->offset >> 1;
11541 length = eeprom->length >> 1;
11542 cnt_words = length;
11544 if (offset > hw->nvm.sr_size ||
11545 offset + length > hw->nvm.sr_size) {
11546 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11550 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11552 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11553 if (ret_code != I40E_SUCCESS || cnt_words != length) {
11554 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11561 static int i40e_get_module_info(struct rte_eth_dev *dev,
11562 struct rte_eth_dev_module_info *modinfo)
11564 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11565 uint32_t sff8472_comp = 0;
11566 uint32_t sff8472_swap = 0;
11567 uint32_t sff8636_rev = 0;
11568 i40e_status status;
11571 /* Check if firmware supports reading module EEPROM. */
11572 if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
11574 "Module EEPROM memory read not supported. "
11575 "Please update the NVM image.\n");
11579 status = i40e_update_link_info(hw);
11583 if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
11585 "Cannot read module EEPROM memory. "
11586 "No module connected.\n");
11590 type = hw->phy.link_info.module_type[0];
11593 case I40E_MODULE_TYPE_SFP:
11594 status = i40e_aq_get_phy_register(hw,
11595 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11596 I40E_I2C_EEPROM_DEV_ADDR, 1,
11597 I40E_MODULE_SFF_8472_COMP,
11598 &sff8472_comp, NULL);
11602 status = i40e_aq_get_phy_register(hw,
11603 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11604 I40E_I2C_EEPROM_DEV_ADDR, 1,
11605 I40E_MODULE_SFF_8472_SWAP,
11606 &sff8472_swap, NULL);
11610 /* Check if the module requires address swap to access
11611 * the other EEPROM memory page.
11613 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
11614 PMD_DRV_LOG(WARNING,
11615 "Module address swap to access "
11616 "page 0xA2 is not supported.\n");
11617 modinfo->type = RTE_ETH_MODULE_SFF_8079;
11618 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11619 } else if (sff8472_comp == 0x00) {
11620 /* Module is not SFF-8472 compliant */
11621 modinfo->type = RTE_ETH_MODULE_SFF_8079;
11622 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11624 modinfo->type = RTE_ETH_MODULE_SFF_8472;
11625 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
11628 case I40E_MODULE_TYPE_QSFP_PLUS:
11629 /* Read from memory page 0. */
11630 status = i40e_aq_get_phy_register(hw,
11631 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11633 I40E_MODULE_REVISION_ADDR,
11634 &sff8636_rev, NULL);
11637 /* Determine revision compliance byte */
11638 if (sff8636_rev > 0x02) {
11639 /* Module is SFF-8636 compliant */
11640 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11641 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11643 modinfo->type = RTE_ETH_MODULE_SFF_8436;
11644 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11647 case I40E_MODULE_TYPE_QSFP28:
11648 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11649 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11652 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
11658 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
11659 struct rte_dev_eeprom_info *info)
11661 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11662 bool is_sfp = false;
11663 i40e_status status;
11665 uint32_t value = 0;
11668 if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
11672 for (i = 0; i < info->length; i++) {
11673 u32 offset = i + info->offset;
11674 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
11676 /* Check if we need to access the other memory page */
11678 if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
11679 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
11680 addr = I40E_I2C_EEPROM_DEV_ADDR2;
11683 while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
11684 /* Compute memory page number and offset. */
11685 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
11689 status = i40e_aq_get_phy_register(hw,
11690 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11691 addr, 1, offset, &value, NULL);
11694 data[i] = (uint8_t)value;
11699 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11700 struct rte_ether_addr *mac_addr)
11702 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11703 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11704 struct i40e_vsi *vsi = pf->main_vsi;
11705 struct i40e_mac_filter_info mac_filter;
11706 struct i40e_mac_filter *f;
11709 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
11710 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11714 TAILQ_FOREACH(f, &vsi->mac_list, next) {
11715 if (rte_is_same_ether_addr(&pf->dev_addr,
11716 &f->mac_info.mac_addr))
11721 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11725 mac_filter = f->mac_info;
11726 ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11727 if (ret != I40E_SUCCESS) {
11728 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11731 memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11732 ret = i40e_vsi_add_mac(vsi, &mac_filter);
11733 if (ret != I40E_SUCCESS) {
11734 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11737 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11739 ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11740 mac_addr->addr_bytes, NULL);
11741 if (ret != I40E_SUCCESS) {
11742 PMD_DRV_LOG(ERR, "Failed to change mac");
11750 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
11752 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11753 struct rte_eth_dev_data *dev_data = pf->dev_data;
11754 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
11757 /* check if mtu is within the allowed range */
11758 if (mtu < RTE_ETHER_MIN_MTU || frame_size > I40E_FRAME_SIZE_MAX)
11761 /* mtu setting is forbidden if port is start */
11762 if (dev_data->dev_started) {
11763 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
11764 dev_data->port_id);
11768 if (frame_size > I40E_ETH_MAX_LEN)
11769 dev_data->dev_conf.rxmode.offloads |=
11770 DEV_RX_OFFLOAD_JUMBO_FRAME;
11772 dev_data->dev_conf.rxmode.offloads &=
11773 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
11775 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
11780 /* Restore ethertype filter */
11782 i40e_ethertype_filter_restore(struct i40e_pf *pf)
11784 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11785 struct i40e_ethertype_filter_list
11786 *ethertype_list = &pf->ethertype.ethertype_list;
11787 struct i40e_ethertype_filter *f;
11788 struct i40e_control_filter_stats stats;
11791 TAILQ_FOREACH(f, ethertype_list, rules) {
11793 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
11794 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
11795 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
11796 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
11797 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
11799 memset(&stats, 0, sizeof(stats));
11800 i40e_aq_add_rem_control_packet_filter(hw,
11801 f->input.mac_addr.addr_bytes,
11802 f->input.ether_type,
11803 flags, pf->main_vsi->seid,
11804 f->queue, 1, &stats, NULL);
11806 PMD_DRV_LOG(INFO, "Ethertype filter:"
11807 " mac_etype_used = %u, etype_used = %u,"
11808 " mac_etype_free = %u, etype_free = %u",
11809 stats.mac_etype_used, stats.etype_used,
11810 stats.mac_etype_free, stats.etype_free);
11813 /* Restore tunnel filter */
11815 i40e_tunnel_filter_restore(struct i40e_pf *pf)
11817 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11818 struct i40e_vsi *vsi;
11819 struct i40e_pf_vf *vf;
11820 struct i40e_tunnel_filter_list
11821 *tunnel_list = &pf->tunnel.tunnel_list;
11822 struct i40e_tunnel_filter *f;
11823 struct i40e_aqc_cloud_filters_element_bb cld_filter;
11824 bool big_buffer = 0;
11826 TAILQ_FOREACH(f, tunnel_list, rules) {
11828 vsi = pf->main_vsi;
11830 vf = &pf->vfs[f->vf_id];
11833 memset(&cld_filter, 0, sizeof(cld_filter));
11834 rte_ether_addr_copy((struct rte_ether_addr *)
11835 &f->input.outer_mac,
11836 (struct rte_ether_addr *)&cld_filter.element.outer_mac);
11837 rte_ether_addr_copy((struct rte_ether_addr *)
11838 &f->input.inner_mac,
11839 (struct rte_ether_addr *)&cld_filter.element.inner_mac);
11840 cld_filter.element.inner_vlan = f->input.inner_vlan;
11841 cld_filter.element.flags = f->input.flags;
11842 cld_filter.element.tenant_id = f->input.tenant_id;
11843 cld_filter.element.queue_number = f->queue;
11844 rte_memcpy(cld_filter.general_fields,
11845 f->input.general_fields,
11846 sizeof(f->input.general_fields));
11848 if (((f->input.flags &
11849 I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
11850 I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
11852 I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
11853 I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
11855 I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
11856 I40E_AQC_ADD_CLOUD_FILTER_0X10))
11860 i40e_aq_add_cloud_filters_bb(hw,
11861 vsi->seid, &cld_filter, 1);
11863 i40e_aq_add_cloud_filters(hw, vsi->seid,
11864 &cld_filter.element, 1);
11869 i40e_filter_restore(struct i40e_pf *pf)
11871 i40e_ethertype_filter_restore(pf);
11872 i40e_tunnel_filter_restore(pf);
11873 i40e_fdir_filter_restore(pf);
11874 (void)i40e_hash_filter_restore(pf);
11878 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
11880 if (strcmp(dev->device->driver->name, drv->driver.name))
11887 is_i40e_supported(struct rte_eth_dev *dev)
11889 return is_device_supported(dev, &rte_i40e_pmd);
11892 struct i40e_customized_pctype*
11893 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
11897 for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
11898 if (pf->customized_pctype[i].index == index)
11899 return &pf->customized_pctype[i];
11905 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
11906 uint32_t pkg_size, uint32_t proto_num,
11907 struct rte_pmd_i40e_proto_info *proto,
11908 enum rte_pmd_i40e_package_op op)
11910 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11911 uint32_t pctype_num;
11912 struct rte_pmd_i40e_ptype_info *pctype;
11913 uint32_t buff_size;
11914 struct i40e_customized_pctype *new_pctype = NULL;
11916 uint8_t pctype_value;
11921 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11922 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11923 PMD_DRV_LOG(ERR, "Unsupported operation.");
11927 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11928 (uint8_t *)&pctype_num, sizeof(pctype_num),
11929 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
11931 PMD_DRV_LOG(ERR, "Failed to get pctype number");
11935 PMD_DRV_LOG(INFO, "No new pctype added");
11939 buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
11940 pctype = rte_zmalloc("new_pctype", buff_size, 0);
11942 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11945 /* get information about new pctype list */
11946 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11947 (uint8_t *)pctype, buff_size,
11948 RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
11950 PMD_DRV_LOG(ERR, "Failed to get pctype list");
11955 /* Update customized pctype. */
11956 for (i = 0; i < pctype_num; i++) {
11957 pctype_value = pctype[i].ptype_id;
11958 memset(name, 0, sizeof(name));
11959 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11960 proto_id = pctype[i].protocols[j];
11961 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11963 for (n = 0; n < proto_num; n++) {
11964 if (proto[n].proto_id != proto_id)
11966 strlcat(name, proto[n].name, sizeof(name));
11967 strlcat(name, "_", sizeof(name));
11971 name[strlen(name) - 1] = '\0';
11972 PMD_DRV_LOG(INFO, "name = %s\n", name);
11973 if (!strcmp(name, "GTPC"))
11975 i40e_find_customized_pctype(pf,
11976 I40E_CUSTOMIZED_GTPC);
11977 else if (!strcmp(name, "GTPU_IPV4"))
11979 i40e_find_customized_pctype(pf,
11980 I40E_CUSTOMIZED_GTPU_IPV4);
11981 else if (!strcmp(name, "GTPU_IPV6"))
11983 i40e_find_customized_pctype(pf,
11984 I40E_CUSTOMIZED_GTPU_IPV6);
11985 else if (!strcmp(name, "GTPU"))
11987 i40e_find_customized_pctype(pf,
11988 I40E_CUSTOMIZED_GTPU);
11989 else if (!strcmp(name, "IPV4_L2TPV3"))
11991 i40e_find_customized_pctype(pf,
11992 I40E_CUSTOMIZED_IPV4_L2TPV3);
11993 else if (!strcmp(name, "IPV6_L2TPV3"))
11995 i40e_find_customized_pctype(pf,
11996 I40E_CUSTOMIZED_IPV6_L2TPV3);
11997 else if (!strcmp(name, "IPV4_ESP"))
11999 i40e_find_customized_pctype(pf,
12000 I40E_CUSTOMIZED_ESP_IPV4);
12001 else if (!strcmp(name, "IPV6_ESP"))
12003 i40e_find_customized_pctype(pf,
12004 I40E_CUSTOMIZED_ESP_IPV6);
12005 else if (!strcmp(name, "IPV4_UDP_ESP"))
12007 i40e_find_customized_pctype(pf,
12008 I40E_CUSTOMIZED_ESP_IPV4_UDP);
12009 else if (!strcmp(name, "IPV6_UDP_ESP"))
12011 i40e_find_customized_pctype(pf,
12012 I40E_CUSTOMIZED_ESP_IPV6_UDP);
12013 else if (!strcmp(name, "IPV4_AH"))
12015 i40e_find_customized_pctype(pf,
12016 I40E_CUSTOMIZED_AH_IPV4);
12017 else if (!strcmp(name, "IPV6_AH"))
12019 i40e_find_customized_pctype(pf,
12020 I40E_CUSTOMIZED_AH_IPV6);
12022 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12023 new_pctype->pctype = pctype_value;
12024 new_pctype->valid = true;
12026 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
12027 new_pctype->valid = false;
12037 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
12038 uint32_t pkg_size, uint32_t proto_num,
12039 struct rte_pmd_i40e_proto_info *proto,
12040 enum rte_pmd_i40e_package_op op)
12042 struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
12043 uint16_t port_id = dev->data->port_id;
12044 uint32_t ptype_num;
12045 struct rte_pmd_i40e_ptype_info *ptype;
12046 uint32_t buff_size;
12048 char name[RTE_PMD_I40E_DDP_NAME_SIZE];
12053 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12054 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12055 PMD_DRV_LOG(ERR, "Unsupported operation.");
12059 if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
12060 rte_pmd_i40e_ptype_mapping_reset(port_id);
12064 /* get information about new ptype num */
12065 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12066 (uint8_t *)&ptype_num, sizeof(ptype_num),
12067 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12069 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12073 PMD_DRV_LOG(INFO, "No new ptype added");
12077 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12078 ptype = rte_zmalloc("new_ptype", buff_size, 0);
12080 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12084 /* get information about new ptype list */
12085 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12086 (uint8_t *)ptype, buff_size,
12087 RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12089 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12094 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12095 ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12096 if (!ptype_mapping) {
12097 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12102 /* Update ptype mapping table. */
12103 for (i = 0; i < ptype_num; i++) {
12104 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12105 ptype_mapping[i].sw_ptype = 0;
12107 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12108 proto_id = ptype[i].protocols[j];
12109 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12111 for (n = 0; n < proto_num; n++) {
12112 if (proto[n].proto_id != proto_id)
12114 memset(name, 0, sizeof(name));
12115 strcpy(name, proto[n].name);
12116 PMD_DRV_LOG(INFO, "name = %s\n", name);
12117 if (!strncasecmp(name, "PPPOE", 5))
12118 ptype_mapping[i].sw_ptype |=
12119 RTE_PTYPE_L2_ETHER_PPPOE;
12120 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12122 ptype_mapping[i].sw_ptype |=
12123 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12124 ptype_mapping[i].sw_ptype |=
12126 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12128 ptype_mapping[i].sw_ptype |=
12129 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12130 ptype_mapping[i].sw_ptype |=
12131 RTE_PTYPE_INNER_L4_FRAG;
12132 } else if (!strncasecmp(name, "OIPV4", 5)) {
12133 ptype_mapping[i].sw_ptype |=
12134 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12136 } else if (!strncasecmp(name, "IPV4", 4) &&
12138 ptype_mapping[i].sw_ptype |=
12139 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12140 else if (!strncasecmp(name, "IPV4", 4) &&
12142 ptype_mapping[i].sw_ptype |=
12143 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12144 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12146 ptype_mapping[i].sw_ptype |=
12147 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12148 ptype_mapping[i].sw_ptype |=
12150 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12152 ptype_mapping[i].sw_ptype |=
12153 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12154 ptype_mapping[i].sw_ptype |=
12155 RTE_PTYPE_INNER_L4_FRAG;
12156 } else if (!strncasecmp(name, "OIPV6", 5)) {
12157 ptype_mapping[i].sw_ptype |=
12158 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12160 } else if (!strncasecmp(name, "IPV6", 4) &&
12162 ptype_mapping[i].sw_ptype |=
12163 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12164 else if (!strncasecmp(name, "IPV6", 4) &&
12166 ptype_mapping[i].sw_ptype |=
12167 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12168 else if (!strncasecmp(name, "UDP", 3) &&
12170 ptype_mapping[i].sw_ptype |=
12172 else if (!strncasecmp(name, "UDP", 3) &&
12174 ptype_mapping[i].sw_ptype |=
12175 RTE_PTYPE_INNER_L4_UDP;
12176 else if (!strncasecmp(name, "TCP", 3) &&
12178 ptype_mapping[i].sw_ptype |=
12180 else if (!strncasecmp(name, "TCP", 3) &&
12182 ptype_mapping[i].sw_ptype |=
12183 RTE_PTYPE_INNER_L4_TCP;
12184 else if (!strncasecmp(name, "SCTP", 4) &&
12186 ptype_mapping[i].sw_ptype |=
12188 else if (!strncasecmp(name, "SCTP", 4) &&
12190 ptype_mapping[i].sw_ptype |=
12191 RTE_PTYPE_INNER_L4_SCTP;
12192 else if ((!strncasecmp(name, "ICMP", 4) ||
12193 !strncasecmp(name, "ICMPV6", 6)) &&
12195 ptype_mapping[i].sw_ptype |=
12197 else if ((!strncasecmp(name, "ICMP", 4) ||
12198 !strncasecmp(name, "ICMPV6", 6)) &&
12200 ptype_mapping[i].sw_ptype |=
12201 RTE_PTYPE_INNER_L4_ICMP;
12202 else if (!strncasecmp(name, "GTPC", 4)) {
12203 ptype_mapping[i].sw_ptype |=
12204 RTE_PTYPE_TUNNEL_GTPC;
12206 } else if (!strncasecmp(name, "GTPU", 4)) {
12207 ptype_mapping[i].sw_ptype |=
12208 RTE_PTYPE_TUNNEL_GTPU;
12210 } else if (!strncasecmp(name, "ESP", 3)) {
12211 ptype_mapping[i].sw_ptype |=
12212 RTE_PTYPE_TUNNEL_ESP;
12214 } else if (!strncasecmp(name, "GRENAT", 6)) {
12215 ptype_mapping[i].sw_ptype |=
12216 RTE_PTYPE_TUNNEL_GRENAT;
12218 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12219 !strncasecmp(name, "L2TPV2", 6) ||
12220 !strncasecmp(name, "L2TPV3", 6)) {
12221 ptype_mapping[i].sw_ptype |=
12222 RTE_PTYPE_TUNNEL_L2TP;
12231 ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12234 PMD_DRV_LOG(ERR, "Failed to update ptype mapping table.");
12236 rte_free(ptype_mapping);
12242 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12243 uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12245 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12246 uint32_t proto_num;
12247 struct rte_pmd_i40e_proto_info *proto;
12248 uint32_t buff_size;
12252 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12253 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12254 PMD_DRV_LOG(ERR, "Unsupported operation.");
12258 /* get information about protocol number */
12259 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12260 (uint8_t *)&proto_num, sizeof(proto_num),
12261 RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12263 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12267 PMD_DRV_LOG(INFO, "No new protocol added");
12271 buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12272 proto = rte_zmalloc("new_proto", buff_size, 0);
12274 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12278 /* get information about protocol list */
12279 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12280 (uint8_t *)proto, buff_size,
12281 RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12283 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12288 /* Check if GTP is supported. */
12289 for (i = 0; i < proto_num; i++) {
12290 if (!strncmp(proto[i].name, "GTP", 3)) {
12291 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12292 pf->gtp_support = true;
12294 pf->gtp_support = false;
12299 /* Check if ESP is supported. */
12300 for (i = 0; i < proto_num; i++) {
12301 if (!strncmp(proto[i].name, "ESP", 3)) {
12302 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12303 pf->esp_support = true;
12305 pf->esp_support = false;
12310 /* Update customized pctype info */
12311 ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12312 proto_num, proto, op);
12314 PMD_DRV_LOG(INFO, "No pctype is updated.");
12316 /* Update customized ptype info */
12317 ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12318 proto_num, proto, op);
12320 PMD_DRV_LOG(INFO, "No ptype is updated.");
12325 /* Create a QinQ cloud filter
12327 * The Fortville NIC has limited resources for tunnel filters,
12328 * so we can only reuse existing filters.
12330 * In step 1 we define which Field Vector fields can be used for
12332 * As we do not have the inner tag defined as a field,
12333 * we have to define it first, by reusing one of L1 entries.
12335 * In step 2 we are replacing one of existing filter types with
12336 * a new one for QinQ.
12337 * As we reusing L1 and replacing L2, some of the default filter
12338 * types will disappear,which depends on L1 and L2 entries we reuse.
12340 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12342 * 1. Create L1 filter of outer vlan (12b) which will be in use
12343 * later when we define the cloud filter.
12344 * a. Valid_flags.replace_cloud = 0
12345 * b. Old_filter = 10 (Stag_Inner_Vlan)
12346 * c. New_filter = 0x10
12347 * d. TR bit = 0xff (optional, not used here)
12348 * e. Buffer – 2 entries:
12349 * i. Byte 0 = 8 (outer vlan FV index).
12351 * Byte 2-3 = 0x0fff
12352 * ii. Byte 0 = 37 (inner vlan FV index).
12354 * Byte 2-3 = 0x0fff
12357 * 2. Create cloud filter using two L1 filters entries: stag and
12358 * new filter(outer vlan+ inner vlan)
12359 * a. Valid_flags.replace_cloud = 1
12360 * b. Old_filter = 1 (instead of outer IP)
12361 * c. New_filter = 0x10
12362 * d. Buffer – 2 entries:
12363 * i. Byte 0 = 0x80 | 7 (valid | Stag).
12364 * Byte 1-3 = 0 (rsv)
12365 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12366 * Byte 9-11 = 0 (rsv)
12369 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12371 int ret = -ENOTSUP;
12372 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
12373 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
12374 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12375 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
12377 if (pf->support_multi_driver) {
12378 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12383 memset(&filter_replace, 0,
12384 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12385 memset(&filter_replace_buf, 0,
12386 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12388 /* create L1 filter */
12389 filter_replace.old_filter_type =
12390 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12391 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12392 filter_replace.tr_bit = 0;
12394 /* Prepare the buffer, 2 entries */
12395 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12396 filter_replace_buf.data[0] |=
12397 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12398 /* Field Vector 12b mask */
12399 filter_replace_buf.data[2] = 0xff;
12400 filter_replace_buf.data[3] = 0x0f;
12401 filter_replace_buf.data[4] =
12402 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12403 filter_replace_buf.data[4] |=
12404 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12405 /* Field Vector 12b mask */
12406 filter_replace_buf.data[6] = 0xff;
12407 filter_replace_buf.data[7] = 0x0f;
12408 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12409 &filter_replace_buf);
12410 if (ret != I40E_SUCCESS)
12413 if (filter_replace.old_filter_type !=
12414 filter_replace.new_filter_type)
12415 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
12416 " original: 0x%x, new: 0x%x",
12418 filter_replace.old_filter_type,
12419 filter_replace.new_filter_type);
12421 /* Apply the second L2 cloud filter */
12422 memset(&filter_replace, 0,
12423 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12424 memset(&filter_replace_buf, 0,
12425 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12427 /* create L2 filter, input for L2 filter will be L1 filter */
12428 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12429 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12430 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12432 /* Prepare the buffer, 2 entries */
12433 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12434 filter_replace_buf.data[0] |=
12435 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12436 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12437 filter_replace_buf.data[4] |=
12438 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12439 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12440 &filter_replace_buf);
12441 if (!ret && (filter_replace.old_filter_type !=
12442 filter_replace.new_filter_type))
12443 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
12444 " original: 0x%x, new: 0x%x",
12446 filter_replace.old_filter_type,
12447 filter_replace.new_filter_type);
12452 RTE_LOG_REGISTER_SUFFIX(i40e_logtype_init, init, NOTICE);
12453 RTE_LOG_REGISTER_SUFFIX(i40e_logtype_driver, driver, NOTICE);
12454 #ifdef RTE_ETHDEV_DEBUG_RX
12455 RTE_LOG_REGISTER_SUFFIX(i40e_logtype_rx, rx, DEBUG);
12457 #ifdef RTE_ETHDEV_DEBUG_TX
12458 RTE_LOG_REGISTER_SUFFIX(i40e_logtype_tx, tx, DEBUG);
12461 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12462 ETH_I40E_FLOATING_VEB_ARG "=1"
12463 ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
12464 ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12465 ETH_I40E_SUPPORT_MULTI_DRIVER "=1");