4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
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34 #include <sys/queue.h>
44 #include <rte_string_fns.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memzone.h>
49 #include <rte_malloc.h>
50 #include <rte_memcpy.h>
51 #include <rte_alarm.h>
53 #include <rte_eth_ctrl.h>
55 #include "i40e_logs.h"
56 #include "base/i40e_prototype.h"
57 #include "base/i40e_adminq_cmd.h"
58 #include "base/i40e_type.h"
59 #include "base/i40e_register.h"
60 #include "base/i40e_dcb.h"
61 #include "i40e_ethdev.h"
62 #include "i40e_rxtx.h"
65 /* Maximun number of MAC addresses */
66 #define I40E_NUM_MACADDR_MAX 64
67 #define I40E_CLEAR_PXE_WAIT_MS 200
69 /* Maximun number of capability elements */
70 #define I40E_MAX_CAP_ELE_NUM 128
72 /* Wait count and inteval */
73 #define I40E_CHK_Q_ENA_COUNT 1000
74 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
76 /* Maximun number of VSI */
77 #define I40E_MAX_NUM_VSIS (384UL)
79 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
81 /* Flow control default timer */
82 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
84 /* Flow control default high water */
85 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
87 /* Flow control default low water */
88 #define I40E_DEFAULT_LOW_WATER (0x1A40/1024)
90 /* Flow control enable fwd bit */
91 #define I40E_PRTMAC_FWD_CTRL 0x00000001
93 /* Receive Packet Buffer size */
94 #define I40E_RXPBSIZE (968 * 1024)
97 #define I40E_KILOSHIFT 10
99 /* Receive Average Packet Size in Byte*/
100 #define I40E_PACKET_AVERAGE_SIZE 128
102 /* Mask of PF interrupt causes */
103 #define I40E_PFINT_ICR0_ENA_MASK ( \
104 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
105 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
106 I40E_PFINT_ICR0_ENA_GRST_MASK | \
107 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
108 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
109 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
110 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
111 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
112 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
113 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
115 #define I40E_FLOW_TYPES ( \
116 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
117 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
118 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
119 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
120 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
121 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
122 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
123 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
124 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
125 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
126 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
128 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
129 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
130 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
131 #define I40E_PRTTSYN_TSYNENA 0x80000000
132 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
134 #define I40E_MAX_PERCENT 100
135 #define I40E_DEFAULT_DCB_APP_NUM 1
136 #define I40E_DEFAULT_DCB_APP_PRIO 3
138 #define I40E_PRTQF_FD_INSET(_i, _j) (0x00250000 + ((_i) * 64 + (_j) * 32))
139 #define I40E_GLQF_FD_MSK(_i, _j) (0x00267200 + ((_i) * 4 + (_j) * 8))
140 #define I40E_GLQF_FD_MSK_FIELD 0x0000FFFF
141 #define I40E_GLQF_HASH_INSET(_i, _j) (0x00267600 + ((_i) * 4 + (_j) * 8))
142 #define I40E_GLQF_HASH_MSK(_i, _j) (0x00267A00 + ((_i) * 4 + (_j) * 8))
143 #define I40E_GLQF_HASH_MSK_FIELD 0x0000FFFF
145 #define I40E_INSET_NONE 0x00000000000000000ULL
148 #define I40E_INSET_DMAC 0x0000000000000001ULL
149 #define I40E_INSET_SMAC 0x0000000000000002ULL
150 #define I40E_INSET_VLAN_OUTER 0x0000000000000004ULL
151 #define I40E_INSET_VLAN_INNER 0x0000000000000008ULL
152 #define I40E_INSET_VLAN_TUNNEL 0x0000000000000010ULL
155 #define I40E_INSET_IPV4_SRC 0x0000000000000100ULL
156 #define I40E_INSET_IPV4_DST 0x0000000000000200ULL
157 #define I40E_INSET_IPV6_SRC 0x0000000000000400ULL
158 #define I40E_INSET_IPV6_DST 0x0000000000000800ULL
159 #define I40E_INSET_SRC_PORT 0x0000000000001000ULL
160 #define I40E_INSET_DST_PORT 0x0000000000002000ULL
161 #define I40E_INSET_SCTP_VT 0x0000000000004000ULL
163 /* bit 16 ~ bit 31 */
164 #define I40E_INSET_IPV4_TOS 0x0000000000010000ULL
165 #define I40E_INSET_IPV4_PROTO 0x0000000000020000ULL
166 #define I40E_INSET_IPV4_TTL 0x0000000000040000ULL
167 #define I40E_INSET_IPV6_TC 0x0000000000080000ULL
168 #define I40E_INSET_IPV6_FLOW 0x0000000000100000ULL
169 #define I40E_INSET_IPV6_NEXT_HDR 0x0000000000200000ULL
170 #define I40E_INSET_IPV6_HOP_LIMIT 0x0000000000400000ULL
171 #define I40E_INSET_TCP_FLAGS 0x0000000000800000ULL
173 /* bit 32 ~ bit 47, tunnel fields */
174 #define I40E_INSET_TUNNEL_IPV4_DST 0x0000000100000000ULL
175 #define I40E_INSET_TUNNEL_IPV6_DST 0x0000000200000000ULL
176 #define I40E_INSET_TUNNEL_DMAC 0x0000000400000000ULL
177 #define I40E_INSET_TUNNEL_SRC_PORT 0x0000000800000000ULL
178 #define I40E_INSET_TUNNEL_DST_PORT 0x0000001000000000ULL
179 #define I40E_INSET_TUNNEL_ID 0x0000002000000000ULL
181 /* bit 48 ~ bit 55 */
182 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
184 /* bit 56 ~ bit 63, Flex Payload */
185 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
186 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
187 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
188 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
189 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
190 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
191 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
192 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
193 #define I40E_INSET_FLEX_PAYLOAD \
194 (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
195 I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W3 | \
196 I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
197 I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
200 * Below are values for writing un-exposed registers suggested
203 /* Destination MAC address */
204 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
205 /* Source MAC address */
206 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
207 /* VLAN tag in the outer L2 header */
208 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000000800000ULL
209 /* VLAN tag in the inner L2 header */
210 #define I40E_REG_INSET_L2_INNER_VLAN 0x0000000001000000ULL
211 /* Source IPv4 address */
212 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
213 /* Destination IPv4 address */
214 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
215 /* IPv4 Type of Service (TOS) */
216 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
218 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
219 /* Source IPv6 address */
220 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
221 /* Destination IPv6 address */
222 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
223 /* IPv6 Traffic Class (TC) */
224 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
225 /* IPv6 Next Header */
226 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
228 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
229 /* Destination L4 port */
230 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
231 /* SCTP verification tag */
232 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
233 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
234 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
235 /* Source port of tunneling UDP */
236 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
237 /* Destination port of tunneling UDP */
238 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
239 /* UDP Tunneling ID, NVGRE/GRE key */
240 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
241 /* Last ether type */
242 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
243 /* Tunneling outer destination IPv4 address */
244 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
245 /* Tunneling outer destination IPv6 address */
246 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
247 /* 1st word of flex payload */
248 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
249 /* 2nd word of flex payload */
250 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
251 /* 3rd word of flex payload */
252 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
253 /* 4th word of flex payload */
254 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
255 /* 5th word of flex payload */
256 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
257 /* 6th word of flex payload */
258 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
259 /* 7th word of flex payload */
260 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
261 /* 8th word of flex payload */
262 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
264 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
266 #define I40E_TRANSLATE_INSET 0
267 #define I40E_TRANSLATE_REG 1
269 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
270 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
271 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
272 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
274 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
275 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
276 static int i40e_dev_configure(struct rte_eth_dev *dev);
277 static int i40e_dev_start(struct rte_eth_dev *dev);
278 static void i40e_dev_stop(struct rte_eth_dev *dev);
279 static void i40e_dev_close(struct rte_eth_dev *dev);
280 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
281 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
282 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
283 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
284 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
285 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
286 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
287 struct rte_eth_stats *stats);
288 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
289 struct rte_eth_xstats *xstats, unsigned n);
290 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
291 static void i40e_dev_xstats_reset(struct rte_eth_dev *dev);
292 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
296 static void i40e_dev_info_get(struct rte_eth_dev *dev,
297 struct rte_eth_dev_info *dev_info);
298 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
301 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
302 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
303 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
306 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
307 static int i40e_dev_led_on(struct rte_eth_dev *dev);
308 static int i40e_dev_led_off(struct rte_eth_dev *dev);
309 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
310 struct rte_eth_fc_conf *fc_conf);
311 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
312 struct rte_eth_fc_conf *fc_conf);
313 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
314 struct rte_eth_pfc_conf *pfc_conf);
315 static void i40e_macaddr_add(struct rte_eth_dev *dev,
316 struct ether_addr *mac_addr,
319 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
320 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
321 struct rte_eth_rss_reta_entry64 *reta_conf,
323 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
324 struct rte_eth_rss_reta_entry64 *reta_conf,
327 static int i40e_get_cap(struct i40e_hw *hw);
328 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
329 static int i40e_pf_setup(struct i40e_pf *pf);
330 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
331 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
332 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
333 static int i40e_dcb_setup(struct rte_eth_dev *dev);
334 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
335 bool offset_loaded, uint64_t *offset, uint64_t *stat);
336 static void i40e_stat_update_48(struct i40e_hw *hw,
342 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
343 static void i40e_dev_interrupt_handler(
344 __rte_unused struct rte_intr_handle *handle, void *param);
345 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
346 uint32_t base, uint32_t num);
347 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
348 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
350 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
352 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
353 static int i40e_veb_release(struct i40e_veb *veb);
354 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
355 struct i40e_vsi *vsi);
356 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
357 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
358 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
359 struct i40e_macvlan_filter *mv_f,
361 struct ether_addr *addr);
362 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
363 struct i40e_macvlan_filter *mv_f,
366 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
367 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
368 struct rte_eth_rss_conf *rss_conf);
369 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
370 struct rte_eth_rss_conf *rss_conf);
371 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
372 struct rte_eth_udp_tunnel *udp_tunnel);
373 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
374 struct rte_eth_udp_tunnel *udp_tunnel);
375 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
376 struct rte_eth_ethertype_filter *filter,
378 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
379 enum rte_filter_op filter_op,
381 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
382 enum rte_filter_type filter_type,
383 enum rte_filter_op filter_op,
385 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
386 struct rte_eth_dcb_info *dcb_info);
387 static void i40e_configure_registers(struct i40e_hw *hw);
388 static void i40e_hw_init(struct i40e_hw *hw);
389 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
390 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
391 struct rte_eth_mirror_conf *mirror_conf,
392 uint8_t sw_id, uint8_t on);
393 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
395 static int i40e_timesync_enable(struct rte_eth_dev *dev);
396 static int i40e_timesync_disable(struct rte_eth_dev *dev);
397 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
398 struct timespec *timestamp,
400 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
401 struct timespec *timestamp);
402 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
403 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
405 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
408 static const struct rte_pci_id pci_id_i40e_map[] = {
409 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
410 #include "rte_pci_dev_ids.h"
411 { .vendor_id = 0, /* sentinel */ },
414 static const struct eth_dev_ops i40e_eth_dev_ops = {
415 .dev_configure = i40e_dev_configure,
416 .dev_start = i40e_dev_start,
417 .dev_stop = i40e_dev_stop,
418 .dev_close = i40e_dev_close,
419 .promiscuous_enable = i40e_dev_promiscuous_enable,
420 .promiscuous_disable = i40e_dev_promiscuous_disable,
421 .allmulticast_enable = i40e_dev_allmulticast_enable,
422 .allmulticast_disable = i40e_dev_allmulticast_disable,
423 .dev_set_link_up = i40e_dev_set_link_up,
424 .dev_set_link_down = i40e_dev_set_link_down,
425 .link_update = i40e_dev_link_update,
426 .stats_get = i40e_dev_stats_get,
427 .xstats_get = i40e_dev_xstats_get,
428 .stats_reset = i40e_dev_stats_reset,
429 .xstats_reset = i40e_dev_xstats_reset,
430 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
431 .dev_infos_get = i40e_dev_info_get,
432 .vlan_filter_set = i40e_vlan_filter_set,
433 .vlan_tpid_set = i40e_vlan_tpid_set,
434 .vlan_offload_set = i40e_vlan_offload_set,
435 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
436 .vlan_pvid_set = i40e_vlan_pvid_set,
437 .rx_queue_start = i40e_dev_rx_queue_start,
438 .rx_queue_stop = i40e_dev_rx_queue_stop,
439 .tx_queue_start = i40e_dev_tx_queue_start,
440 .tx_queue_stop = i40e_dev_tx_queue_stop,
441 .rx_queue_setup = i40e_dev_rx_queue_setup,
442 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
443 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
444 .rx_queue_release = i40e_dev_rx_queue_release,
445 .rx_queue_count = i40e_dev_rx_queue_count,
446 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
447 .tx_queue_setup = i40e_dev_tx_queue_setup,
448 .tx_queue_release = i40e_dev_tx_queue_release,
449 .dev_led_on = i40e_dev_led_on,
450 .dev_led_off = i40e_dev_led_off,
451 .flow_ctrl_get = i40e_flow_ctrl_get,
452 .flow_ctrl_set = i40e_flow_ctrl_set,
453 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
454 .mac_addr_add = i40e_macaddr_add,
455 .mac_addr_remove = i40e_macaddr_remove,
456 .reta_update = i40e_dev_rss_reta_update,
457 .reta_query = i40e_dev_rss_reta_query,
458 .rss_hash_update = i40e_dev_rss_hash_update,
459 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
460 .udp_tunnel_add = i40e_dev_udp_tunnel_add,
461 .udp_tunnel_del = i40e_dev_udp_tunnel_del,
462 .filter_ctrl = i40e_dev_filter_ctrl,
463 .rxq_info_get = i40e_rxq_info_get,
464 .txq_info_get = i40e_txq_info_get,
465 .mirror_rule_set = i40e_mirror_rule_set,
466 .mirror_rule_reset = i40e_mirror_rule_reset,
467 .timesync_enable = i40e_timesync_enable,
468 .timesync_disable = i40e_timesync_disable,
469 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
470 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
471 .get_dcb_info = i40e_dev_get_dcb_info,
474 /* store statistics names and its offset in stats structure */
475 struct rte_i40e_xstats_name_off {
476 char name[RTE_ETH_XSTATS_NAME_SIZE];
480 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
481 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
482 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
483 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
484 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
485 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
486 rx_unknown_protocol)},
487 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
488 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
489 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
490 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
493 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
494 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
495 tx_dropped_link_down)},
496 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
497 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
499 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
500 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
502 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
504 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
506 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
507 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
508 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
509 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
510 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
511 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
513 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
515 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
517 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
519 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
521 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
523 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
525 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
527 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
528 mac_short_packet_dropped)},
529 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
531 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
532 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
533 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
535 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
537 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
539 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
541 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
543 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
545 {"rx_flow_director_atr_match_packets",
546 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
547 {"rx_flow_director_sb_match_packets",
548 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
549 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
551 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
553 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
555 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
559 /* Q Stats: 5 stats are exposed for each queue, implemented in xstats_get() */
560 #define I40E_NB_HW_PORT_Q_STATS (8 * 5)
562 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
563 sizeof(rte_i40e_stats_strings[0]))
564 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
565 sizeof(rte_i40e_hw_port_strings[0]))
566 #define I40E_NB_XSTATS (I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS + \
567 I40E_NB_HW_PORT_Q_STATS)
569 static struct eth_driver rte_i40e_pmd = {
571 .name = "rte_i40e_pmd",
572 .id_table = pci_id_i40e_map,
573 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
574 RTE_PCI_DRV_DETACHABLE,
576 .eth_dev_init = eth_i40e_dev_init,
577 .eth_dev_uninit = eth_i40e_dev_uninit,
578 .dev_private_size = sizeof(struct i40e_adapter),
582 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
583 struct rte_eth_link *link)
585 struct rte_eth_link *dst = link;
586 struct rte_eth_link *src = &(dev->data->dev_link);
588 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
589 *(uint64_t *)src) == 0)
596 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
597 struct rte_eth_link *link)
599 struct rte_eth_link *dst = &(dev->data->dev_link);
600 struct rte_eth_link *src = link;
602 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
603 *(uint64_t *)src) == 0)
610 * Driver initialization routine.
611 * Invoked once at EAL init time.
612 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
615 rte_i40e_pmd_init(const char *name __rte_unused,
616 const char *params __rte_unused)
618 PMD_INIT_FUNC_TRACE();
619 rte_eth_driver_register(&rte_i40e_pmd);
624 static struct rte_driver rte_i40e_driver = {
626 .init = rte_i40e_pmd_init,
629 PMD_REGISTER_DRIVER(rte_i40e_driver);
632 * Initialize registers for flexible payload, which should be set by NVM.
633 * This should be removed from code once it is fixed in NVM.
635 #ifndef I40E_GLQF_ORT
636 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
638 #ifndef I40E_GLQF_PIT
639 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
642 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
644 I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
645 I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
646 I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
647 I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
648 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
649 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
650 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
651 I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
652 I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
653 I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
655 /* GLQF_PIT Registers */
656 I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
657 I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
660 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
663 * Add a ethertype filter to drop all flow control frames transmitted
667 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
669 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
670 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
671 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
672 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
675 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
676 I40E_FLOW_CONTROL_ETHERTYPE, flags,
677 pf->main_vsi_seid, 0,
680 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
681 " frames from VSIs.");
685 eth_i40e_dev_init(struct rte_eth_dev *dev)
687 struct rte_pci_device *pci_dev;
688 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
689 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
690 struct i40e_vsi *vsi;
695 PMD_INIT_FUNC_TRACE();
697 dev->dev_ops = &i40e_eth_dev_ops;
698 dev->rx_pkt_burst = i40e_recv_pkts;
699 dev->tx_pkt_burst = i40e_xmit_pkts;
701 /* for secondary processes, we don't initialise any further as primary
702 * has already done this work. Only check we don't need a different
704 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
705 i40e_set_rx_function(dev);
706 i40e_set_tx_function(dev);
709 pci_dev = dev->pci_dev;
711 rte_eth_copy_pci_info(dev, pci_dev);
713 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
714 pf->adapter->eth_dev = dev;
715 pf->dev_data = dev->data;
717 hw->back = I40E_PF_TO_ADAPTER(pf);
718 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
720 PMD_INIT_LOG(ERR, "Hardware is not available, "
721 "as address is NULL");
725 hw->vendor_id = pci_dev->id.vendor_id;
726 hw->device_id = pci_dev->id.device_id;
727 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
728 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
729 hw->bus.device = pci_dev->addr.devid;
730 hw->bus.func = pci_dev->addr.function;
731 hw->adapter_stopped = 0;
733 /* Make sure all is clean before doing PF reset */
736 /* Initialize the hardware */
739 /* Reset here to make sure all is clean for each PF */
740 ret = i40e_pf_reset(hw);
742 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
746 /* Initialize the shared code (base driver) */
747 ret = i40e_init_shared_code(hw);
749 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
754 * To work around the NVM issue,initialize registers
755 * for flexible payload by software.
756 * It should be removed once issues are fixed in NVM.
758 i40e_flex_payload_reg_init(hw);
760 /* Initialize the parameters for adminq */
761 i40e_init_adminq_parameter(hw);
762 ret = i40e_init_adminq(hw);
763 if (ret != I40E_SUCCESS) {
764 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
767 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
768 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
769 hw->aq.api_maj_ver, hw->aq.api_min_ver,
770 ((hw->nvm.version >> 12) & 0xf),
771 ((hw->nvm.version >> 4) & 0xff),
772 (hw->nvm.version & 0xf), hw->nvm.eetrack);
775 i40e_clear_pxe_mode(hw);
778 * On X710, performance number is far from the expectation on recent
779 * firmware versions. The fix for this issue may not be integrated in
780 * the following firmware version. So the workaround in software driver
781 * is needed. It needs to modify the initial values of 3 internal only
782 * registers. Note that the workaround can be removed when it is fixed
783 * in firmware in the future.
785 i40e_configure_registers(hw);
787 /* Get hw capabilities */
788 ret = i40e_get_cap(hw);
789 if (ret != I40E_SUCCESS) {
790 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
791 goto err_get_capabilities;
794 /* Initialize parameters for PF */
795 ret = i40e_pf_parameter_init(dev);
797 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
798 goto err_parameter_init;
801 /* Initialize the queue management */
802 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
804 PMD_INIT_LOG(ERR, "Failed to init queue pool");
805 goto err_qp_pool_init;
807 ret = i40e_res_pool_init(&pf->msix_pool, 1,
808 hw->func_caps.num_msix_vectors - 1);
810 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
811 goto err_msix_pool_init;
814 /* Initialize lan hmc */
815 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
816 hw->func_caps.num_rx_qp, 0, 0);
817 if (ret != I40E_SUCCESS) {
818 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
819 goto err_init_lan_hmc;
822 /* Configure lan hmc */
823 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
824 if (ret != I40E_SUCCESS) {
825 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
826 goto err_configure_lan_hmc;
829 /* Get and check the mac address */
830 i40e_get_mac_addr(hw, hw->mac.addr);
831 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
832 PMD_INIT_LOG(ERR, "mac address is not valid");
834 goto err_get_mac_addr;
836 /* Copy the permanent MAC address */
837 ether_addr_copy((struct ether_addr *) hw->mac.addr,
838 (struct ether_addr *) hw->mac.perm_addr);
840 /* Disable flow control */
841 hw->fc.requested_mode = I40E_FC_NONE;
842 i40e_set_fc(hw, &aq_fail, TRUE);
844 /* PF setup, which includes VSI setup */
845 ret = i40e_pf_setup(pf);
847 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
848 goto err_setup_pf_switch;
853 /* Disable double vlan by default */
854 i40e_vsi_config_double_vlan(vsi, FALSE);
856 if (!vsi->max_macaddrs)
857 len = ETHER_ADDR_LEN;
859 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
861 /* Should be after VSI initialized */
862 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
863 if (!dev->data->mac_addrs) {
864 PMD_INIT_LOG(ERR, "Failed to allocated memory "
865 "for storing mac address");
868 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
869 &dev->data->mac_addrs[0]);
871 /* initialize pf host driver to setup SRIOV resource if applicable */
872 i40e_pf_host_init(dev);
874 /* register callback func to eal lib */
875 rte_intr_callback_register(&(pci_dev->intr_handle),
876 i40e_dev_interrupt_handler, (void *)dev);
878 /* configure and enable device interrupt */
879 i40e_pf_config_irq0(hw, TRUE);
880 i40e_pf_enable_irq0(hw);
882 /* enable uio intr after callback register */
883 rte_intr_enable(&(pci_dev->intr_handle));
885 * Add an ethertype filter to drop all flow control frames transmitted
886 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
889 i40e_add_tx_flow_control_drop_filter(pf);
891 /* initialize mirror rule list */
892 TAILQ_INIT(&pf->mirror_list);
894 /* Init dcb to sw mode by default */
895 ret = i40e_dcb_init_configure(dev, TRUE);
896 if (ret != I40E_SUCCESS) {
897 PMD_INIT_LOG(INFO, "Failed to init dcb.");
898 pf->flags &= ~I40E_FLAG_DCB;
904 i40e_vsi_release(pf->main_vsi);
907 err_configure_lan_hmc:
908 (void)i40e_shutdown_lan_hmc(hw);
910 i40e_res_pool_destroy(&pf->msix_pool);
912 i40e_res_pool_destroy(&pf->qp_pool);
915 err_get_capabilities:
916 (void)i40e_shutdown_adminq(hw);
922 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
924 struct rte_pci_device *pci_dev;
926 struct i40e_filter_control_settings settings;
930 PMD_INIT_FUNC_TRACE();
932 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
935 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
936 pci_dev = dev->pci_dev;
938 if (hw->adapter_stopped == 0)
942 dev->rx_pkt_burst = NULL;
943 dev->tx_pkt_burst = NULL;
946 ret = i40e_aq_stop_lldp(hw, true, NULL);
947 if (ret != I40E_SUCCESS) /* Its failure can be ignored */
948 PMD_INIT_LOG(INFO, "Failed to stop lldp");
951 i40e_clear_pxe_mode(hw);
953 /* Unconfigure filter control */
954 memset(&settings, 0, sizeof(settings));
955 ret = i40e_set_filter_control(hw, &settings);
957 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
960 /* Disable flow control */
961 hw->fc.requested_mode = I40E_FC_NONE;
962 i40e_set_fc(hw, &aq_fail, TRUE);
964 /* uninitialize pf host driver */
965 i40e_pf_host_uninit(dev);
967 rte_free(dev->data->mac_addrs);
968 dev->data->mac_addrs = NULL;
970 /* disable uio intr before callback unregister */
971 rte_intr_disable(&(pci_dev->intr_handle));
973 /* register callback func to eal lib */
974 rte_intr_callback_unregister(&(pci_dev->intr_handle),
975 i40e_dev_interrupt_handler, (void *)dev);
981 i40e_dev_configure(struct rte_eth_dev *dev)
983 struct i40e_adapter *ad =
984 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
985 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
986 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
989 /* Initialize to TRUE. If any of Rx queues doesn't meet the
990 * bulk allocation or vector Rx preconditions we will reset it.
992 ad->rx_bulk_alloc_allowed = true;
993 ad->rx_vec_allowed = true;
994 ad->tx_simple_allowed = true;
995 ad->tx_vec_allowed = true;
997 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
998 ret = i40e_fdir_setup(pf);
999 if (ret != I40E_SUCCESS) {
1000 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1003 ret = i40e_fdir_configure(dev);
1005 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1009 i40e_fdir_teardown(pf);
1011 ret = i40e_dev_init_vlan(dev);
1016 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1017 * RSS setting have different requirements.
1018 * General PMD driver call sequence are NIC init, configure,
1019 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1020 * will try to lookup the VSI that specific queue belongs to if VMDQ
1021 * applicable. So, VMDQ setting has to be done before
1022 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1023 * For RSS setting, it will try to calculate actual configured RX queue
1024 * number, which will be available after rx_queue_setup(). dev_start()
1025 * function is good to place RSS setup.
1027 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1028 ret = i40e_vmdq_setup(dev);
1033 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1034 ret = i40e_dcb_setup(dev);
1036 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1044 /* need to release vmdq resource if exists */
1045 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1046 i40e_vsi_release(pf->vmdq[i].vsi);
1047 pf->vmdq[i].vsi = NULL;
1052 /* need to release fdir resource if exists */
1053 i40e_fdir_teardown(pf);
1058 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1060 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1061 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1062 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1063 uint16_t msix_vect = vsi->msix_intr;
1066 for (i = 0; i < vsi->nb_qps; i++) {
1067 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1068 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1072 if (vsi->type != I40E_VSI_SRIOV) {
1073 if (!rte_intr_allow_others(intr_handle)) {
1074 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1075 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1077 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1080 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1081 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1083 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1088 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1089 vsi->user_param + (msix_vect - 1);
1091 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1092 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1094 I40E_WRITE_FLUSH(hw);
1098 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1099 int base_queue, int nb_queue)
1103 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1105 /* Bind all RX queues to allocated MSIX interrupt */
1106 for (i = 0; i < nb_queue; i++) {
1107 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1108 I40E_QINT_RQCTL_ITR_INDX_MASK |
1109 ((base_queue + i + 1) <<
1110 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1111 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1112 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1114 if (i == nb_queue - 1)
1115 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1116 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1119 /* Write first RX queue to Link list register as the head element */
1120 if (vsi->type != I40E_VSI_SRIOV) {
1122 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1124 if (msix_vect == I40E_MISC_VEC_ID) {
1125 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1127 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1129 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1131 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1134 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1136 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1138 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1140 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1147 if (msix_vect == I40E_MISC_VEC_ID) {
1149 I40E_VPINT_LNKLST0(vsi->user_param),
1151 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1153 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1155 /* num_msix_vectors_vf needs to minus irq0 */
1156 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1157 vsi->user_param + (msix_vect - 1);
1159 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1161 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1163 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1167 I40E_WRITE_FLUSH(hw);
1171 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1173 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1174 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1175 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1176 uint16_t msix_vect = vsi->msix_intr;
1177 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1178 uint16_t queue_idx = 0;
1183 for (i = 0; i < vsi->nb_qps; i++) {
1184 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1185 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1188 /* INTENA flag is not auto-cleared for interrupt */
1189 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1190 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1191 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1192 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1193 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1195 /* VF bind interrupt */
1196 if (vsi->type == I40E_VSI_SRIOV) {
1197 __vsi_queues_bind_intr(vsi, msix_vect,
1198 vsi->base_queue, vsi->nb_qps);
1202 /* PF & VMDq bind interrupt */
1203 if (rte_intr_dp_is_en(intr_handle)) {
1204 if (vsi->type == I40E_VSI_MAIN) {
1207 } else if (vsi->type == I40E_VSI_VMDQ2) {
1208 struct i40e_vsi *main_vsi =
1209 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1210 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1215 for (i = 0; i < vsi->nb_used_qps; i++) {
1217 if (!rte_intr_allow_others(intr_handle))
1218 /* allow to share MISC_VEC_ID */
1219 msix_vect = I40E_MISC_VEC_ID;
1221 /* no enough msix_vect, map all to one */
1222 __vsi_queues_bind_intr(vsi, msix_vect,
1223 vsi->base_queue + i,
1224 vsi->nb_used_qps - i);
1225 for (; !!record && i < vsi->nb_used_qps; i++)
1226 intr_handle->intr_vec[queue_idx + i] =
1230 /* 1:1 queue/msix_vect mapping */
1231 __vsi_queues_bind_intr(vsi, msix_vect,
1232 vsi->base_queue + i, 1);
1234 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1242 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1244 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1245 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1246 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1247 uint16_t interval = i40e_calc_itr_interval(\
1248 RTE_LIBRTE_I40E_ITR_INTERVAL);
1249 uint16_t msix_intr, i;
1251 if (rte_intr_allow_others(intr_handle))
1252 for (i = 0; i < vsi->nb_msix; i++) {
1253 msix_intr = vsi->msix_intr + i;
1254 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1255 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1256 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1257 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1259 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1262 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1263 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1264 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1265 (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1267 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1269 I40E_WRITE_FLUSH(hw);
1273 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1275 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1276 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1277 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1278 uint16_t msix_intr, i;
1280 if (rte_intr_allow_others(intr_handle))
1281 for (i = 0; i < vsi->nb_msix; i++) {
1282 msix_intr = vsi->msix_intr + i;
1283 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1287 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1289 I40E_WRITE_FLUSH(hw);
1292 static inline uint8_t
1293 i40e_parse_link_speed(uint16_t eth_link_speed)
1295 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1297 switch (eth_link_speed) {
1298 case ETH_LINK_SPEED_40G:
1299 link_speed = I40E_LINK_SPEED_40GB;
1301 case ETH_LINK_SPEED_20G:
1302 link_speed = I40E_LINK_SPEED_20GB;
1304 case ETH_LINK_SPEED_10G:
1305 link_speed = I40E_LINK_SPEED_10GB;
1307 case ETH_LINK_SPEED_1000:
1308 link_speed = I40E_LINK_SPEED_1GB;
1310 case ETH_LINK_SPEED_100:
1311 link_speed = I40E_LINK_SPEED_100MB;
1319 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
1321 enum i40e_status_code status;
1322 struct i40e_aq_get_phy_abilities_resp phy_ab;
1323 struct i40e_aq_set_phy_config phy_conf;
1324 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1325 I40E_AQ_PHY_FLAG_PAUSE_RX |
1326 I40E_AQ_PHY_FLAG_LOW_POWER;
1327 const uint8_t advt = I40E_LINK_SPEED_40GB |
1328 I40E_LINK_SPEED_10GB |
1329 I40E_LINK_SPEED_1GB |
1330 I40E_LINK_SPEED_100MB;
1333 /* Skip it on 40G interfaces, as a workaround for the link issue */
1334 if (i40e_is_40G_device(hw->device_id))
1335 return I40E_SUCCESS;
1337 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1342 memset(&phy_conf, 0, sizeof(phy_conf));
1344 /* bits 0-2 use the values from get_phy_abilities_resp */
1346 abilities |= phy_ab.abilities & mask;
1348 /* update ablities and speed */
1349 if (abilities & I40E_AQ_PHY_AN_ENABLED)
1350 phy_conf.link_speed = advt;
1352 phy_conf.link_speed = force_speed;
1354 phy_conf.abilities = abilities;
1356 /* use get_phy_abilities_resp value for the rest */
1357 phy_conf.phy_type = phy_ab.phy_type;
1358 phy_conf.eee_capability = phy_ab.eee_capability;
1359 phy_conf.eeer = phy_ab.eeer_val;
1360 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1362 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1363 phy_ab.abilities, phy_ab.link_speed);
1364 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
1365 phy_conf.abilities, phy_conf.link_speed);
1367 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1371 return I40E_SUCCESS;
1375 i40e_apply_link_speed(struct rte_eth_dev *dev)
1378 uint8_t abilities = 0;
1379 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1380 struct rte_eth_conf *conf = &dev->data->dev_conf;
1382 speed = i40e_parse_link_speed(conf->link_speed);
1383 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1384 if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
1385 abilities |= I40E_AQ_PHY_AN_ENABLED;
1387 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1389 return i40e_phy_conf_link(hw, abilities, speed);
1393 i40e_dev_start(struct rte_eth_dev *dev)
1395 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1396 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1397 struct i40e_vsi *main_vsi = pf->main_vsi;
1399 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1400 uint32_t intr_vector = 0;
1402 hw->adapter_stopped = 0;
1404 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1405 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1406 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1407 dev->data->dev_conf.link_duplex,
1408 dev->data->port_id);
1412 rte_intr_disable(intr_handle);
1414 if ((rte_intr_cap_multiple(intr_handle) ||
1415 !RTE_ETH_DEV_SRIOV(dev).active) &&
1416 dev->data->dev_conf.intr_conf.rxq != 0) {
1417 intr_vector = dev->data->nb_rx_queues;
1418 if (rte_intr_efd_enable(intr_handle, intr_vector))
1422 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1423 intr_handle->intr_vec =
1424 rte_zmalloc("intr_vec",
1425 dev->data->nb_rx_queues * sizeof(int),
1427 if (!intr_handle->intr_vec) {
1428 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1429 " intr_vec\n", dev->data->nb_rx_queues);
1434 /* Initialize VSI */
1435 ret = i40e_dev_rxtx_init(pf);
1436 if (ret != I40E_SUCCESS) {
1437 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1441 /* Map queues with MSIX interrupt */
1442 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1443 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1444 i40e_vsi_queues_bind_intr(main_vsi);
1445 i40e_vsi_enable_queues_intr(main_vsi);
1447 /* Map VMDQ VSI queues with MSIX interrupt */
1448 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1449 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1450 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1451 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1454 /* enable FDIR MSIX interrupt */
1455 if (pf->fdir.fdir_vsi) {
1456 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1457 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1460 /* Enable all queues which have been configured */
1461 ret = i40e_dev_switch_queues(pf, TRUE);
1462 if (ret != I40E_SUCCESS) {
1463 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1467 /* Enable receiving broadcast packets */
1468 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1469 if (ret != I40E_SUCCESS)
1470 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1472 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1473 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1475 if (ret != I40E_SUCCESS)
1476 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1479 /* Apply link configure */
1480 ret = i40e_apply_link_speed(dev);
1481 if (I40E_SUCCESS != ret) {
1482 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1486 if (!rte_intr_allow_others(intr_handle)) {
1487 rte_intr_callback_unregister(intr_handle,
1488 i40e_dev_interrupt_handler,
1490 /* configure and enable device interrupt */
1491 i40e_pf_config_irq0(hw, FALSE);
1492 i40e_pf_enable_irq0(hw);
1494 if (dev->data->dev_conf.intr_conf.lsc != 0)
1495 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1496 " no intr multiplex\n");
1499 /* enable uio intr after callback register */
1500 rte_intr_enable(intr_handle);
1502 return I40E_SUCCESS;
1505 i40e_dev_switch_queues(pf, FALSE);
1506 i40e_dev_clear_queues(dev);
1512 i40e_dev_stop(struct rte_eth_dev *dev)
1514 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1515 struct i40e_vsi *main_vsi = pf->main_vsi;
1516 struct i40e_mirror_rule *p_mirror;
1517 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1520 /* Disable all queues */
1521 i40e_dev_switch_queues(pf, FALSE);
1523 /* un-map queues with interrupt registers */
1524 i40e_vsi_disable_queues_intr(main_vsi);
1525 i40e_vsi_queues_unbind_intr(main_vsi);
1527 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1528 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1529 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1532 if (pf->fdir.fdir_vsi) {
1533 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1534 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1536 /* Clear all queues and release memory */
1537 i40e_dev_clear_queues(dev);
1540 i40e_dev_set_link_down(dev);
1542 /* Remove all mirror rules */
1543 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1544 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1547 pf->nb_mirror_rule = 0;
1549 if (!rte_intr_allow_others(intr_handle))
1550 /* resume to the default handler */
1551 rte_intr_callback_register(intr_handle,
1552 i40e_dev_interrupt_handler,
1555 /* Clean datapath event and queue/vec mapping */
1556 rte_intr_efd_disable(intr_handle);
1557 if (intr_handle->intr_vec) {
1558 rte_free(intr_handle->intr_vec);
1559 intr_handle->intr_vec = NULL;
1564 i40e_dev_close(struct rte_eth_dev *dev)
1566 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1567 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1571 PMD_INIT_FUNC_TRACE();
1574 hw->adapter_stopped = 1;
1575 i40e_dev_free_queues(dev);
1577 /* Disable interrupt */
1578 i40e_pf_disable_irq0(hw);
1579 rte_intr_disable(&(dev->pci_dev->intr_handle));
1581 /* shutdown and destroy the HMC */
1582 i40e_shutdown_lan_hmc(hw);
1584 /* release all the existing VSIs and VEBs */
1585 i40e_fdir_teardown(pf);
1586 i40e_vsi_release(pf->main_vsi);
1588 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1589 i40e_vsi_release(pf->vmdq[i].vsi);
1590 pf->vmdq[i].vsi = NULL;
1596 /* shutdown the adminq */
1597 i40e_aq_queue_shutdown(hw, true);
1598 i40e_shutdown_adminq(hw);
1600 i40e_res_pool_destroy(&pf->qp_pool);
1601 i40e_res_pool_destroy(&pf->msix_pool);
1603 /* force a PF reset to clean anything leftover */
1604 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1605 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1606 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1607 I40E_WRITE_FLUSH(hw);
1611 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1613 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1614 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1615 struct i40e_vsi *vsi = pf->main_vsi;
1618 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1620 if (status != I40E_SUCCESS)
1621 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1623 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1625 if (status != I40E_SUCCESS)
1626 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1631 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1633 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1634 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1635 struct i40e_vsi *vsi = pf->main_vsi;
1638 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1640 if (status != I40E_SUCCESS)
1641 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1643 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1645 if (status != I40E_SUCCESS)
1646 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1650 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1652 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1653 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1654 struct i40e_vsi *vsi = pf->main_vsi;
1657 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1658 if (ret != I40E_SUCCESS)
1659 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1663 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1665 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1666 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1667 struct i40e_vsi *vsi = pf->main_vsi;
1670 if (dev->data->promiscuous == 1)
1671 return; /* must remain in all_multicast mode */
1673 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1674 vsi->seid, FALSE, NULL);
1675 if (ret != I40E_SUCCESS)
1676 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1680 * Set device link up.
1683 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1685 /* re-apply link speed setting */
1686 return i40e_apply_link_speed(dev);
1690 * Set device link down.
1693 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1695 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1696 uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1697 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1699 return i40e_phy_conf_link(hw, abilities, speed);
1703 i40e_dev_link_update(struct rte_eth_dev *dev,
1704 int wait_to_complete)
1706 #define CHECK_INTERVAL 100 /* 100ms */
1707 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
1708 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1709 struct i40e_link_status link_status;
1710 struct rte_eth_link link, old;
1712 unsigned rep_cnt = MAX_REPEAT_TIME;
1714 memset(&link, 0, sizeof(link));
1715 memset(&old, 0, sizeof(old));
1716 memset(&link_status, 0, sizeof(link_status));
1717 rte_i40e_dev_atomic_read_link_status(dev, &old);
1720 /* Get link status information from hardware */
1721 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1722 if (status != I40E_SUCCESS) {
1723 link.link_speed = ETH_LINK_SPEED_100;
1724 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1725 PMD_DRV_LOG(ERR, "Failed to get link info");
1729 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1730 if (!wait_to_complete)
1733 rte_delay_ms(CHECK_INTERVAL);
1734 } while (!link.link_status && rep_cnt--);
1736 if (!link.link_status)
1739 /* i40e uses full duplex only */
1740 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1742 /* Parse the link status */
1743 switch (link_status.link_speed) {
1744 case I40E_LINK_SPEED_100MB:
1745 link.link_speed = ETH_LINK_SPEED_100;
1747 case I40E_LINK_SPEED_1GB:
1748 link.link_speed = ETH_LINK_SPEED_1000;
1750 case I40E_LINK_SPEED_10GB:
1751 link.link_speed = ETH_LINK_SPEED_10G;
1753 case I40E_LINK_SPEED_20GB:
1754 link.link_speed = ETH_LINK_SPEED_20G;
1756 case I40E_LINK_SPEED_40GB:
1757 link.link_speed = ETH_LINK_SPEED_40G;
1760 link.link_speed = ETH_LINK_SPEED_100;
1765 rte_i40e_dev_atomic_write_link_status(dev, &link);
1766 if (link.link_status == old.link_status)
1772 /* Get all the statistics of a VSI */
1774 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1776 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1777 struct i40e_eth_stats *nes = &vsi->eth_stats;
1778 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1779 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1781 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1782 vsi->offset_loaded, &oes->rx_bytes,
1784 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1785 vsi->offset_loaded, &oes->rx_unicast,
1787 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1788 vsi->offset_loaded, &oes->rx_multicast,
1789 &nes->rx_multicast);
1790 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1791 vsi->offset_loaded, &oes->rx_broadcast,
1792 &nes->rx_broadcast);
1793 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1794 &oes->rx_discards, &nes->rx_discards);
1795 /* GLV_REPC not supported */
1796 /* GLV_RMPC not supported */
1797 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1798 &oes->rx_unknown_protocol,
1799 &nes->rx_unknown_protocol);
1800 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1801 vsi->offset_loaded, &oes->tx_bytes,
1803 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1804 vsi->offset_loaded, &oes->tx_unicast,
1806 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1807 vsi->offset_loaded, &oes->tx_multicast,
1808 &nes->tx_multicast);
1809 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1810 vsi->offset_loaded, &oes->tx_broadcast,
1811 &nes->tx_broadcast);
1812 /* GLV_TDPC not supported */
1813 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1814 &oes->tx_errors, &nes->tx_errors);
1815 vsi->offset_loaded = true;
1817 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1819 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
1820 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
1821 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
1822 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
1823 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
1824 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1825 nes->rx_unknown_protocol);
1826 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
1827 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
1828 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
1829 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
1830 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
1831 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
1832 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1837 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
1840 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1841 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1842 /* Get statistics of struct i40e_eth_stats */
1843 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1844 I40E_GLPRT_GORCL(hw->port),
1845 pf->offset_loaded, &os->eth.rx_bytes,
1847 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1848 I40E_GLPRT_UPRCL(hw->port),
1849 pf->offset_loaded, &os->eth.rx_unicast,
1850 &ns->eth.rx_unicast);
1851 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1852 I40E_GLPRT_MPRCL(hw->port),
1853 pf->offset_loaded, &os->eth.rx_multicast,
1854 &ns->eth.rx_multicast);
1855 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1856 I40E_GLPRT_BPRCL(hw->port),
1857 pf->offset_loaded, &os->eth.rx_broadcast,
1858 &ns->eth.rx_broadcast);
1859 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1860 pf->offset_loaded, &os->eth.rx_discards,
1861 &ns->eth.rx_discards);
1862 /* GLPRT_REPC not supported */
1863 /* GLPRT_RMPC not supported */
1864 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1866 &os->eth.rx_unknown_protocol,
1867 &ns->eth.rx_unknown_protocol);
1868 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1869 I40E_GLPRT_GOTCL(hw->port),
1870 pf->offset_loaded, &os->eth.tx_bytes,
1872 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1873 I40E_GLPRT_UPTCL(hw->port),
1874 pf->offset_loaded, &os->eth.tx_unicast,
1875 &ns->eth.tx_unicast);
1876 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1877 I40E_GLPRT_MPTCL(hw->port),
1878 pf->offset_loaded, &os->eth.tx_multicast,
1879 &ns->eth.tx_multicast);
1880 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1881 I40E_GLPRT_BPTCL(hw->port),
1882 pf->offset_loaded, &os->eth.tx_broadcast,
1883 &ns->eth.tx_broadcast);
1884 /* GLPRT_TEPC not supported */
1886 /* additional port specific stats */
1887 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1888 pf->offset_loaded, &os->tx_dropped_link_down,
1889 &ns->tx_dropped_link_down);
1890 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1891 pf->offset_loaded, &os->crc_errors,
1893 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1894 pf->offset_loaded, &os->illegal_bytes,
1895 &ns->illegal_bytes);
1896 /* GLPRT_ERRBC not supported */
1897 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1898 pf->offset_loaded, &os->mac_local_faults,
1899 &ns->mac_local_faults);
1900 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1901 pf->offset_loaded, &os->mac_remote_faults,
1902 &ns->mac_remote_faults);
1903 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1904 pf->offset_loaded, &os->rx_length_errors,
1905 &ns->rx_length_errors);
1906 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1907 pf->offset_loaded, &os->link_xon_rx,
1909 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1910 pf->offset_loaded, &os->link_xoff_rx,
1912 for (i = 0; i < 8; i++) {
1913 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1915 &os->priority_xon_rx[i],
1916 &ns->priority_xon_rx[i]);
1917 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1919 &os->priority_xoff_rx[i],
1920 &ns->priority_xoff_rx[i]);
1922 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1923 pf->offset_loaded, &os->link_xon_tx,
1925 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1926 pf->offset_loaded, &os->link_xoff_tx,
1928 for (i = 0; i < 8; i++) {
1929 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1931 &os->priority_xon_tx[i],
1932 &ns->priority_xon_tx[i]);
1933 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1935 &os->priority_xoff_tx[i],
1936 &ns->priority_xoff_tx[i]);
1937 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1939 &os->priority_xon_2_xoff[i],
1940 &ns->priority_xon_2_xoff[i]);
1942 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1943 I40E_GLPRT_PRC64L(hw->port),
1944 pf->offset_loaded, &os->rx_size_64,
1946 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1947 I40E_GLPRT_PRC127L(hw->port),
1948 pf->offset_loaded, &os->rx_size_127,
1950 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1951 I40E_GLPRT_PRC255L(hw->port),
1952 pf->offset_loaded, &os->rx_size_255,
1954 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1955 I40E_GLPRT_PRC511L(hw->port),
1956 pf->offset_loaded, &os->rx_size_511,
1958 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1959 I40E_GLPRT_PRC1023L(hw->port),
1960 pf->offset_loaded, &os->rx_size_1023,
1962 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1963 I40E_GLPRT_PRC1522L(hw->port),
1964 pf->offset_loaded, &os->rx_size_1522,
1966 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1967 I40E_GLPRT_PRC9522L(hw->port),
1968 pf->offset_loaded, &os->rx_size_big,
1970 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1971 pf->offset_loaded, &os->rx_undersize,
1973 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1974 pf->offset_loaded, &os->rx_fragments,
1976 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1977 pf->offset_loaded, &os->rx_oversize,
1979 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1980 pf->offset_loaded, &os->rx_jabber,
1982 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1983 I40E_GLPRT_PTC64L(hw->port),
1984 pf->offset_loaded, &os->tx_size_64,
1986 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1987 I40E_GLPRT_PTC127L(hw->port),
1988 pf->offset_loaded, &os->tx_size_127,
1990 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1991 I40E_GLPRT_PTC255L(hw->port),
1992 pf->offset_loaded, &os->tx_size_255,
1994 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1995 I40E_GLPRT_PTC511L(hw->port),
1996 pf->offset_loaded, &os->tx_size_511,
1998 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1999 I40E_GLPRT_PTC1023L(hw->port),
2000 pf->offset_loaded, &os->tx_size_1023,
2002 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2003 I40E_GLPRT_PTC1522L(hw->port),
2004 pf->offset_loaded, &os->tx_size_1522,
2006 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2007 I40E_GLPRT_PTC9522L(hw->port),
2008 pf->offset_loaded, &os->tx_size_big,
2010 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2012 &os->fd_sb_match, &ns->fd_sb_match);
2013 /* GLPRT_MSPDC not supported */
2014 /* GLPRT_XEC not supported */
2016 pf->offset_loaded = true;
2019 i40e_update_vsi_stats(pf->main_vsi);
2022 /* Get all statistics of a port */
2024 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2026 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2027 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2028 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2031 /* call read registers - updates values, now write them to struct */
2032 i40e_read_stats_registers(pf, hw);
2034 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2035 pf->main_vsi->eth_stats.rx_multicast +
2036 pf->main_vsi->eth_stats.rx_broadcast -
2037 pf->main_vsi->eth_stats.rx_discards;
2038 stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2039 pf->main_vsi->eth_stats.tx_multicast +
2040 pf->main_vsi->eth_stats.tx_broadcast;
2041 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes;
2042 stats->obytes = pf->main_vsi->eth_stats.tx_bytes;
2043 stats->oerrors = ns->eth.tx_errors +
2044 pf->main_vsi->eth_stats.tx_errors;
2045 stats->imcasts = pf->main_vsi->eth_stats.rx_multicast;
2046 stats->fdirmatch = ns->fd_sb_match;
2049 stats->ibadcrc = ns->crc_errors;
2050 stats->ibadlen = ns->rx_length_errors + ns->rx_undersize +
2051 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2052 stats->imissed = ns->eth.rx_discards +
2053 pf->main_vsi->eth_stats.rx_discards;
2054 stats->ierrors = stats->ibadcrc + stats->ibadlen + stats->imissed;
2056 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2057 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
2058 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
2059 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
2060 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
2061 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
2062 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2063 ns->eth.rx_unknown_protocol);
2064 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
2065 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
2066 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
2067 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
2068 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
2069 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
2071 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
2072 ns->tx_dropped_link_down);
2073 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
2074 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
2076 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
2077 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
2078 ns->mac_local_faults);
2079 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
2080 ns->mac_remote_faults);
2081 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
2082 ns->rx_length_errors);
2083 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
2084 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
2085 for (i = 0; i < 8; i++) {
2086 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
2087 i, ns->priority_xon_rx[i]);
2088 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
2089 i, ns->priority_xoff_rx[i]);
2091 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
2092 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
2093 for (i = 0; i < 8; i++) {
2094 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
2095 i, ns->priority_xon_tx[i]);
2096 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
2097 i, ns->priority_xoff_tx[i]);
2098 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
2099 i, ns->priority_xon_2_xoff[i]);
2101 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
2102 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
2103 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
2104 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
2105 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
2106 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
2107 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
2108 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
2109 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
2110 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
2111 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
2112 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
2113 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
2114 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
2115 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
2116 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
2117 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
2118 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
2119 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2120 ns->mac_short_packet_dropped);
2121 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
2122 ns->checksum_error);
2123 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
2124 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2128 i40e_dev_xstats_reset(struct rte_eth_dev *dev)
2130 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2131 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2132 struct i40e_hw_port_stats *hw_stats = &pf->stats;
2134 /* The hw registers are cleared on read */
2135 pf->offset_loaded = false;
2136 i40e_read_stats_registers(pf, hw);
2138 /* reset software counters */
2139 memset(hw_stats, 0, sizeof(*hw_stats));
2143 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2146 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2147 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2148 unsigned i, count = 0;
2149 struct i40e_hw_port_stats *hw_stats = &pf->stats;
2151 if (n < I40E_NB_XSTATS)
2152 return I40E_NB_XSTATS;
2154 i40e_read_stats_registers(pf, hw);
2160 /* Get stats from i40e_eth_stats struct */
2161 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2162 snprintf(xstats[count].name, sizeof(xstats[count].name),
2163 "%s", rte_i40e_stats_strings[i].name);
2164 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2165 rte_i40e_stats_strings[i].offset);
2169 /* Get individiual stats from i40e_hw_port struct */
2170 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2171 snprintf(xstats[count].name, sizeof(xstats[count].name),
2172 "%s", rte_i40e_hw_port_strings[i].name);
2173 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2174 rte_i40e_hw_port_strings[i].offset);
2178 /* Get per-queue stats from i40e_hw_port struct */
2179 for (i = 0; i < 8; i++) {
2180 snprintf(xstats[count].name, sizeof(xstats[count].name),
2181 "rx_q%u_xon_priority_packets", i);
2182 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2183 offsetof(struct i40e_hw_port_stats,
2184 priority_xon_rx[i]));
2187 snprintf(xstats[count].name, sizeof(xstats[count].name),
2188 "rx_q%u_xoff_priority_packets", i);
2189 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2190 offsetof(struct i40e_hw_port_stats,
2191 priority_xoff_rx[i]));
2194 snprintf(xstats[count].name, sizeof(xstats[count].name),
2195 "tx_q%u_xon_priority_packets", i);
2196 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2197 offsetof(struct i40e_hw_port_stats,
2198 priority_xon_tx[i]));
2201 snprintf(xstats[count].name, sizeof(xstats[count].name),
2202 "tx_q%u_xoff_priority_packets", i);
2203 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2204 offsetof(struct i40e_hw_port_stats,
2205 priority_xoff_tx[i]));
2208 snprintf(xstats[count].name, sizeof(xstats[count].name),
2209 "xx_q%u_xon_to_xoff_priority_packets", i);
2210 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2211 offsetof(struct i40e_hw_port_stats,
2212 priority_xon_2_xoff[i]));
2216 return I40E_NB_XSTATS;
2219 /* Reset the statistics */
2221 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2223 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2225 /* It results in reloading the start point of each counter */
2226 pf->offset_loaded = false;
2230 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2231 __rte_unused uint16_t queue_id,
2232 __rte_unused uint8_t stat_idx,
2233 __rte_unused uint8_t is_rx)
2235 PMD_INIT_FUNC_TRACE();
2241 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2243 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2244 struct i40e_vsi *vsi = pf->main_vsi;
2246 dev_info->max_rx_queues = vsi->nb_qps;
2247 dev_info->max_tx_queues = vsi->nb_qps;
2248 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2249 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2250 dev_info->max_mac_addrs = vsi->max_macaddrs;
2251 dev_info->max_vfs = dev->pci_dev->max_vfs;
2252 dev_info->rx_offload_capa =
2253 DEV_RX_OFFLOAD_VLAN_STRIP |
2254 DEV_RX_OFFLOAD_QINQ_STRIP |
2255 DEV_RX_OFFLOAD_IPV4_CKSUM |
2256 DEV_RX_OFFLOAD_UDP_CKSUM |
2257 DEV_RX_OFFLOAD_TCP_CKSUM;
2258 dev_info->tx_offload_capa =
2259 DEV_TX_OFFLOAD_VLAN_INSERT |
2260 DEV_TX_OFFLOAD_QINQ_INSERT |
2261 DEV_TX_OFFLOAD_IPV4_CKSUM |
2262 DEV_TX_OFFLOAD_UDP_CKSUM |
2263 DEV_TX_OFFLOAD_TCP_CKSUM |
2264 DEV_TX_OFFLOAD_SCTP_CKSUM |
2265 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2266 DEV_TX_OFFLOAD_TCP_TSO;
2267 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2269 dev_info->reta_size = pf->hash_lut_size;
2270 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2272 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2274 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2275 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2276 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2278 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2282 dev_info->default_txconf = (struct rte_eth_txconf) {
2284 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2285 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2286 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2288 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2289 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2290 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2291 ETH_TXQ_FLAGS_NOOFFLOADS,
2294 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2295 .nb_max = I40E_MAX_RING_DESC,
2296 .nb_min = I40E_MIN_RING_DESC,
2297 .nb_align = I40E_ALIGN_RING_DESC,
2300 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2301 .nb_max = I40E_MAX_RING_DESC,
2302 .nb_min = I40E_MIN_RING_DESC,
2303 .nb_align = I40E_ALIGN_RING_DESC,
2306 if (pf->flags & I40E_FLAG_VMDQ) {
2307 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2308 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2309 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2310 pf->max_nb_vmdq_vsi;
2311 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2312 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2313 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2318 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2320 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2321 struct i40e_vsi *vsi = pf->main_vsi;
2322 PMD_INIT_FUNC_TRACE();
2325 return i40e_vsi_add_vlan(vsi, vlan_id);
2327 return i40e_vsi_delete_vlan(vsi, vlan_id);
2331 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
2332 __rte_unused uint16_t tpid)
2334 PMD_INIT_FUNC_TRACE();
2338 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2340 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2341 struct i40e_vsi *vsi = pf->main_vsi;
2343 if (mask & ETH_VLAN_STRIP_MASK) {
2344 /* Enable or disable VLAN stripping */
2345 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2346 i40e_vsi_config_vlan_stripping(vsi, TRUE);
2348 i40e_vsi_config_vlan_stripping(vsi, FALSE);
2351 if (mask & ETH_VLAN_EXTEND_MASK) {
2352 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2353 i40e_vsi_config_double_vlan(vsi, TRUE);
2355 i40e_vsi_config_double_vlan(vsi, FALSE);
2360 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2361 __rte_unused uint16_t queue,
2362 __rte_unused int on)
2364 PMD_INIT_FUNC_TRACE();
2368 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2370 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2371 struct i40e_vsi *vsi = pf->main_vsi;
2372 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2373 struct i40e_vsi_vlan_pvid_info info;
2375 memset(&info, 0, sizeof(info));
2378 info.config.pvid = pvid;
2380 info.config.reject.tagged =
2381 data->dev_conf.txmode.hw_vlan_reject_tagged;
2382 info.config.reject.untagged =
2383 data->dev_conf.txmode.hw_vlan_reject_untagged;
2386 return i40e_vsi_vlan_pvid_set(vsi, &info);
2390 i40e_dev_led_on(struct rte_eth_dev *dev)
2392 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2393 uint32_t mode = i40e_led_get(hw);
2396 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2402 i40e_dev_led_off(struct rte_eth_dev *dev)
2404 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2405 uint32_t mode = i40e_led_get(hw);
2408 i40e_led_set(hw, 0, false);
2414 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2416 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2417 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2419 fc_conf->pause_time = pf->fc_conf.pause_time;
2420 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2421 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2423 /* Return current mode according to actual setting*/
2424 switch (hw->fc.current_mode) {
2426 fc_conf->mode = RTE_FC_FULL;
2428 case I40E_FC_TX_PAUSE:
2429 fc_conf->mode = RTE_FC_TX_PAUSE;
2431 case I40E_FC_RX_PAUSE:
2432 fc_conf->mode = RTE_FC_RX_PAUSE;
2436 fc_conf->mode = RTE_FC_NONE;
2443 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2445 uint32_t mflcn_reg, fctrl_reg, reg;
2446 uint32_t max_high_water;
2447 uint8_t i, aq_failure;
2451 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2452 [RTE_FC_NONE] = I40E_FC_NONE,
2453 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2454 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2455 [RTE_FC_FULL] = I40E_FC_FULL
2458 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2460 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2461 if ((fc_conf->high_water > max_high_water) ||
2462 (fc_conf->high_water < fc_conf->low_water)) {
2463 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2464 "High_water must <= %d.", max_high_water);
2468 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2469 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2470 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2472 pf->fc_conf.pause_time = fc_conf->pause_time;
2473 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2474 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2476 PMD_INIT_FUNC_TRACE();
2478 /* All the link flow control related enable/disable register
2479 * configuration is handle by the F/W
2481 err = i40e_set_fc(hw, &aq_failure, true);
2485 if (i40e_is_40G_device(hw->device_id)) {
2486 /* Configure flow control refresh threshold,
2487 * the value for stat_tx_pause_refresh_timer[8]
2488 * is used for global pause operation.
2492 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2493 pf->fc_conf.pause_time);
2495 /* configure the timer value included in transmitted pause
2497 * the value for stat_tx_pause_quanta[8] is used for global
2500 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2501 pf->fc_conf.pause_time);
2503 fctrl_reg = I40E_READ_REG(hw,
2504 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2506 if (fc_conf->mac_ctrl_frame_fwd != 0)
2507 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2509 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2511 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2514 /* Configure pause time (2 TCs per register) */
2515 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2516 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2517 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2519 /* Configure flow control refresh threshold value */
2520 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2521 pf->fc_conf.pause_time / 2);
2523 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2525 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2526 *depending on configuration
2528 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2529 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2530 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2532 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2533 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2536 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2539 /* config the water marker both based on the packets and bytes */
2540 I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2541 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2542 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2543 I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2544 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2545 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2546 I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2547 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2549 I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2550 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2553 I40E_WRITE_FLUSH(hw);
2559 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2560 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2562 PMD_INIT_FUNC_TRACE();
2567 /* Add a MAC address, and update filters */
2569 i40e_macaddr_add(struct rte_eth_dev *dev,
2570 struct ether_addr *mac_addr,
2571 __rte_unused uint32_t index,
2574 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2575 struct i40e_mac_filter_info mac_filter;
2576 struct i40e_vsi *vsi;
2579 /* If VMDQ not enabled or configured, return */
2580 if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
2581 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2582 pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
2587 if (pool > pf->nb_cfg_vmdq_vsi) {
2588 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2589 pool, pf->nb_cfg_vmdq_vsi);
2593 (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2594 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2599 vsi = pf->vmdq[pool - 1].vsi;
2601 ret = i40e_vsi_add_mac(vsi, &mac_filter);
2602 if (ret != I40E_SUCCESS) {
2603 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2608 /* Remove a MAC address, and update filters */
2610 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2612 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2613 struct i40e_vsi *vsi;
2614 struct rte_eth_dev_data *data = dev->data;
2615 struct ether_addr *macaddr;
2620 macaddr = &(data->mac_addrs[index]);
2622 pool_sel = dev->data->mac_pool_sel[index];
2624 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
2625 if (pool_sel & (1ULL << i)) {
2629 /* No VMDQ pool enabled or configured */
2630 if (!(pf->flags | I40E_FLAG_VMDQ) ||
2631 (i > pf->nb_cfg_vmdq_vsi)) {
2632 PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
2636 vsi = pf->vmdq[i - 1].vsi;
2638 ret = i40e_vsi_delete_mac(vsi, macaddr);
2641 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
2648 /* Set perfect match or hash match of MAC and VLAN for a VF */
2650 i40e_vf_mac_filter_set(struct i40e_pf *pf,
2651 struct rte_eth_mac_filter *filter,
2655 struct i40e_mac_filter_info mac_filter;
2656 struct ether_addr old_mac;
2657 struct ether_addr *new_mac;
2658 struct i40e_pf_vf *vf = NULL;
2663 PMD_DRV_LOG(ERR, "Invalid PF argument.");
2666 hw = I40E_PF_TO_HW(pf);
2668 if (filter == NULL) {
2669 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
2673 new_mac = &filter->mac_addr;
2675 if (is_zero_ether_addr(new_mac)) {
2676 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
2680 vf_id = filter->dst_id;
2682 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
2683 PMD_DRV_LOG(ERR, "Invalid argument.");
2686 vf = &pf->vfs[vf_id];
2688 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
2689 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
2694 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
2695 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
2697 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
2700 mac_filter.filter_type = filter->filter_type;
2701 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
2702 if (ret != I40E_SUCCESS) {
2703 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
2706 ether_addr_copy(new_mac, &pf->dev_addr);
2708 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
2710 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
2711 if (ret != I40E_SUCCESS) {
2712 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
2716 /* Clear device address as it has been removed */
2717 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
2718 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
2724 /* MAC filter handle */
2726 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
2729 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2730 struct rte_eth_mac_filter *filter;
2731 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2732 int ret = I40E_NOT_SUPPORTED;
2734 filter = (struct rte_eth_mac_filter *)(arg);
2736 switch (filter_op) {
2737 case RTE_ETH_FILTER_NOP:
2740 case RTE_ETH_FILTER_ADD:
2741 i40e_pf_disable_irq0(hw);
2743 ret = i40e_vf_mac_filter_set(pf, filter, 1);
2744 i40e_pf_enable_irq0(hw);
2746 case RTE_ETH_FILTER_DELETE:
2747 i40e_pf_disable_irq0(hw);
2749 ret = i40e_vf_mac_filter_set(pf, filter, 0);
2750 i40e_pf_enable_irq0(hw);
2753 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2754 ret = I40E_ERR_PARAM;
2762 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2764 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2765 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2771 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2772 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
2775 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2779 uint32_t *lut_dw = (uint32_t *)lut;
2780 uint16_t i, lut_size_dw = lut_size / 4;
2782 for (i = 0; i < lut_size_dw; i++)
2783 lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
2790 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2792 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2793 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2799 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2800 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
2803 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2807 uint32_t *lut_dw = (uint32_t *)lut;
2808 uint16_t i, lut_size_dw = lut_size / 4;
2810 for (i = 0; i < lut_size_dw; i++)
2811 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
2812 I40E_WRITE_FLUSH(hw);
2819 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
2820 struct rte_eth_rss_reta_entry64 *reta_conf,
2823 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2824 uint16_t i, lut_size = pf->hash_lut_size;
2825 uint16_t idx, shift;
2829 if (reta_size != lut_size ||
2830 reta_size > ETH_RSS_RETA_SIZE_512) {
2831 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2832 "(%d) doesn't match the number hardware can supported "
2833 "(%d)\n", reta_size, lut_size);
2837 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2839 PMD_DRV_LOG(ERR, "No memory can be allocated");
2842 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2845 for (i = 0; i < reta_size; i++) {
2846 idx = i / RTE_RETA_GROUP_SIZE;
2847 shift = i % RTE_RETA_GROUP_SIZE;
2848 if (reta_conf[idx].mask & (1ULL << shift))
2849 lut[i] = reta_conf[idx].reta[shift];
2851 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
2860 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
2861 struct rte_eth_rss_reta_entry64 *reta_conf,
2864 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2865 uint16_t i, lut_size = pf->hash_lut_size;
2866 uint16_t idx, shift;
2870 if (reta_size != lut_size ||
2871 reta_size > ETH_RSS_RETA_SIZE_512) {
2872 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2873 "(%d) doesn't match the number hardware can supported "
2874 "(%d)\n", reta_size, lut_size);
2878 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2880 PMD_DRV_LOG(ERR, "No memory can be allocated");
2884 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2887 for (i = 0; i < reta_size; i++) {
2888 idx = i / RTE_RETA_GROUP_SIZE;
2889 shift = i % RTE_RETA_GROUP_SIZE;
2890 if (reta_conf[idx].mask & (1ULL << shift))
2891 reta_conf[idx].reta[shift] = lut[i];
2901 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
2902 * @hw: pointer to the HW structure
2903 * @mem: pointer to mem struct to fill out
2904 * @size: size of memory requested
2905 * @alignment: what to align the allocation to
2907 enum i40e_status_code
2908 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2909 struct i40e_dma_mem *mem,
2913 static uint64_t id = 0;
2914 const struct rte_memzone *mz = NULL;
2915 char z_name[RTE_MEMZONE_NAMESIZE];
2918 return I40E_ERR_PARAM;
2921 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
2922 #ifdef RTE_LIBRTE_XEN_DOM0
2923 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
2924 alignment, RTE_PGSIZE_2M);
2926 mz = rte_memzone_reserve_aligned(z_name, size, SOCKET_ID_ANY, 0,
2930 return I40E_ERR_NO_MEMORY;
2935 #ifdef RTE_LIBRTE_XEN_DOM0
2936 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
2938 mem->pa = mz->phys_addr;
2941 return I40E_SUCCESS;
2945 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
2946 * @hw: pointer to the HW structure
2947 * @mem: ptr to mem struct to free
2949 enum i40e_status_code
2950 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2951 struct i40e_dma_mem *mem)
2953 if (!mem || !mem->va)
2954 return I40E_ERR_PARAM;
2959 return I40E_SUCCESS;
2963 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
2964 * @hw: pointer to the HW structure
2965 * @mem: pointer to mem struct to fill out
2966 * @size: size of memory requested
2968 enum i40e_status_code
2969 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2970 struct i40e_virt_mem *mem,
2974 return I40E_ERR_PARAM;
2977 mem->va = rte_zmalloc("i40e", size, 0);
2980 return I40E_SUCCESS;
2982 return I40E_ERR_NO_MEMORY;
2986 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
2987 * @hw: pointer to the HW structure
2988 * @mem: pointer to mem struct to free
2990 enum i40e_status_code
2991 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2992 struct i40e_virt_mem *mem)
2995 return I40E_ERR_PARAM;
3000 return I40E_SUCCESS;
3004 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3006 rte_spinlock_init(&sp->spinlock);
3010 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3012 rte_spinlock_lock(&sp->spinlock);
3016 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3018 rte_spinlock_unlock(&sp->spinlock);
3022 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3028 * Get the hardware capabilities, which will be parsed
3029 * and saved into struct i40e_hw.
3032 i40e_get_cap(struct i40e_hw *hw)
3034 struct i40e_aqc_list_capabilities_element_resp *buf;
3035 uint16_t len, size = 0;
3038 /* Calculate a huge enough buff for saving response data temporarily */
3039 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3040 I40E_MAX_CAP_ELE_NUM;
3041 buf = rte_zmalloc("i40e", len, 0);
3043 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3044 return I40E_ERR_NO_MEMORY;
3047 /* Get, parse the capabilities and save it to hw */
3048 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3049 i40e_aqc_opc_list_func_capabilities, NULL);
3050 if (ret != I40E_SUCCESS)
3051 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3053 /* Free the temporary buffer after being used */
3060 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3062 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3063 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3064 uint16_t qp_count = 0, vsi_count = 0;
3066 if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3067 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3070 /* Add the parameter init for LFC */
3071 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3072 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3073 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3075 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3076 pf->max_num_vsi = hw->func_caps.num_vsis;
3077 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3078 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3079 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3081 /* FDir queue/VSI allocation */
3082 pf->fdir_qp_offset = 0;
3083 if (hw->func_caps.fd) {
3084 pf->flags |= I40E_FLAG_FDIR;
3085 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3087 pf->fdir_nb_qps = 0;
3089 qp_count += pf->fdir_nb_qps;
3092 /* LAN queue/VSI allocation */
3093 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3094 if (!hw->func_caps.rss) {
3097 pf->flags |= I40E_FLAG_RSS;
3098 if (hw->mac.type == I40E_MAC_X722)
3099 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3100 pf->lan_nb_qps = pf->lan_nb_qp_max;
3102 qp_count += pf->lan_nb_qps;
3105 /* VF queue/VSI allocation */
3106 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3107 if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3108 pf->flags |= I40E_FLAG_SRIOV;
3109 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3110 pf->vf_num = dev->pci_dev->max_vfs;
3111 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3112 "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3113 pf->vf_nb_qps * pf->vf_num);
3118 qp_count += pf->vf_nb_qps * pf->vf_num;
3119 vsi_count += pf->vf_num;
3121 /* VMDq queue/VSI allocation */
3122 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3123 if (hw->func_caps.vmdq) {
3124 pf->flags |= I40E_FLAG_VMDQ;
3125 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3126 pf->max_nb_vmdq_vsi = 1;
3127 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues per VMDQ VSI, "
3128 "in total %u queues", pf->max_nb_vmdq_vsi,
3130 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
3132 pf->vmdq_nb_qps = 0;
3133 pf->max_nb_vmdq_vsi = 0;
3135 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3136 vsi_count += pf->max_nb_vmdq_vsi;
3138 if (hw->func_caps.dcb)
3139 pf->flags |= I40E_FLAG_DCB;
3141 if (qp_count > hw->func_caps.num_tx_qp) {
3142 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3143 "the hardware maximum %u", qp_count,
3144 hw->func_caps.num_tx_qp);
3147 if (vsi_count > hw->func_caps.num_vsis) {
3148 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3149 "the hardware maximum %u", vsi_count,
3150 hw->func_caps.num_vsis);
3158 i40e_pf_get_switch_config(struct i40e_pf *pf)
3160 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3161 struct i40e_aqc_get_switch_config_resp *switch_config;
3162 struct i40e_aqc_switch_config_element_resp *element;
3163 uint16_t start_seid = 0, num_reported;
3166 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3167 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3168 if (!switch_config) {
3169 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3173 /* Get the switch configurations */
3174 ret = i40e_aq_get_switch_config(hw, switch_config,
3175 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3176 if (ret != I40E_SUCCESS) {
3177 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3180 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3181 if (num_reported != 1) { /* The number should be 1 */
3182 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3186 /* Parse the switch configuration elements */
3187 element = &(switch_config->element[0]);
3188 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3189 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3190 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3192 PMD_DRV_LOG(INFO, "Unknown element type");
3195 rte_free(switch_config);
3201 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3204 struct pool_entry *entry;
3206 if (pool == NULL || num == 0)
3209 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3210 if (entry == NULL) {
3211 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3215 /* queue heap initialize */
3216 pool->num_free = num;
3217 pool->num_alloc = 0;
3219 LIST_INIT(&pool->alloc_list);
3220 LIST_INIT(&pool->free_list);
3222 /* Initialize element */
3226 LIST_INSERT_HEAD(&pool->free_list, entry, next);
3231 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3233 struct pool_entry *entry;
3238 LIST_FOREACH(entry, &pool->alloc_list, next) {
3239 LIST_REMOVE(entry, next);
3243 LIST_FOREACH(entry, &pool->free_list, next) {
3244 LIST_REMOVE(entry, next);
3249 pool->num_alloc = 0;
3251 LIST_INIT(&pool->alloc_list);
3252 LIST_INIT(&pool->free_list);
3256 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3259 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3260 uint32_t pool_offset;
3264 PMD_DRV_LOG(ERR, "Invalid parameter");
3268 pool_offset = base - pool->base;
3269 /* Lookup in alloc list */
3270 LIST_FOREACH(entry, &pool->alloc_list, next) {
3271 if (entry->base == pool_offset) {
3272 valid_entry = entry;
3273 LIST_REMOVE(entry, next);
3278 /* Not find, return */
3279 if (valid_entry == NULL) {
3280 PMD_DRV_LOG(ERR, "Failed to find entry");
3285 * Found it, move it to free list and try to merge.
3286 * In order to make merge easier, always sort it by qbase.
3287 * Find adjacent prev and last entries.
3290 LIST_FOREACH(entry, &pool->free_list, next) {
3291 if (entry->base > valid_entry->base) {
3299 /* Try to merge with next one*/
3301 /* Merge with next one */
3302 if (valid_entry->base + valid_entry->len == next->base) {
3303 next->base = valid_entry->base;
3304 next->len += valid_entry->len;
3305 rte_free(valid_entry);
3312 /* Merge with previous one */
3313 if (prev->base + prev->len == valid_entry->base) {
3314 prev->len += valid_entry->len;
3315 /* If it merge with next one, remove next node */
3317 LIST_REMOVE(valid_entry, next);
3318 rte_free(valid_entry);
3320 rte_free(valid_entry);
3326 /* Not find any entry to merge, insert */
3329 LIST_INSERT_AFTER(prev, valid_entry, next);
3330 else if (next != NULL)
3331 LIST_INSERT_BEFORE(next, valid_entry, next);
3332 else /* It's empty list, insert to head */
3333 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3336 pool->num_free += valid_entry->len;
3337 pool->num_alloc -= valid_entry->len;
3343 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3346 struct pool_entry *entry, *valid_entry;
3348 if (pool == NULL || num == 0) {
3349 PMD_DRV_LOG(ERR, "Invalid parameter");
3353 if (pool->num_free < num) {
3354 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3355 num, pool->num_free);
3360 /* Lookup in free list and find most fit one */
3361 LIST_FOREACH(entry, &pool->free_list, next) {
3362 if (entry->len >= num) {
3364 if (entry->len == num) {
3365 valid_entry = entry;
3368 if (valid_entry == NULL || valid_entry->len > entry->len)
3369 valid_entry = entry;
3373 /* Not find one to satisfy the request, return */
3374 if (valid_entry == NULL) {
3375 PMD_DRV_LOG(ERR, "No valid entry found");
3379 * The entry have equal queue number as requested,
3380 * remove it from alloc_list.
3382 if (valid_entry->len == num) {
3383 LIST_REMOVE(valid_entry, next);
3386 * The entry have more numbers than requested,
3387 * create a new entry for alloc_list and minus its
3388 * queue base and number in free_list.
3390 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3391 if (entry == NULL) {
3392 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3396 entry->base = valid_entry->base;
3398 valid_entry->base += num;
3399 valid_entry->len -= num;
3400 valid_entry = entry;
3403 /* Insert it into alloc list, not sorted */
3404 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3406 pool->num_free -= valid_entry->len;
3407 pool->num_alloc += valid_entry->len;
3409 return (valid_entry->base + pool->base);
3413 * bitmap_is_subset - Check whether src2 is subset of src1
3416 bitmap_is_subset(uint8_t src1, uint8_t src2)
3418 return !((src1 ^ src2) & src2);
3422 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3424 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3426 /* If DCB is not supported, only default TC is supported */
3427 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3428 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3432 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3433 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3434 "HW support 0x%x", hw->func_caps.enabled_tcmap,
3438 return I40E_SUCCESS;
3442 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3443 struct i40e_vsi_vlan_pvid_info *info)
3446 struct i40e_vsi_context ctxt;
3447 uint8_t vlan_flags = 0;
3450 if (vsi == NULL || info == NULL) {
3451 PMD_DRV_LOG(ERR, "invalid parameters");
3452 return I40E_ERR_PARAM;
3456 vsi->info.pvid = info->config.pvid;
3458 * If insert pvid is enabled, only tagged pkts are
3459 * allowed to be sent out.
3461 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3462 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3465 if (info->config.reject.tagged == 0)
3466 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3468 if (info->config.reject.untagged == 0)
3469 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3471 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3472 I40E_AQ_VSI_PVLAN_MODE_MASK);
3473 vsi->info.port_vlan_flags |= vlan_flags;
3474 vsi->info.valid_sections =
3475 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3476 memset(&ctxt, 0, sizeof(ctxt));
3477 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3478 ctxt.seid = vsi->seid;
3480 hw = I40E_VSI_TO_HW(vsi);
3481 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3482 if (ret != I40E_SUCCESS)
3483 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3489 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3491 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3493 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3495 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3496 if (ret != I40E_SUCCESS)
3500 PMD_DRV_LOG(ERR, "seid not valid");
3504 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3505 tc_bw_data.tc_valid_bits = enabled_tcmap;
3506 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3507 tc_bw_data.tc_bw_credits[i] =
3508 (enabled_tcmap & (1 << i)) ? 1 : 0;
3510 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3511 if (ret != I40E_SUCCESS) {
3512 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3516 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3517 sizeof(vsi->info.qs_handle));
3518 return I40E_SUCCESS;
3522 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3523 struct i40e_aqc_vsi_properties_data *info,
3524 uint8_t enabled_tcmap)
3526 int ret, i, total_tc = 0;
3527 uint16_t qpnum_per_tc, bsf, qp_idx;
3529 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3530 if (ret != I40E_SUCCESS)
3533 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3534 if (enabled_tcmap & (1 << i))
3536 vsi->enabled_tc = enabled_tcmap;
3538 /* Number of queues per enabled TC */
3539 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3540 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3541 bsf = rte_bsf32(qpnum_per_tc);
3543 /* Adjust the queue number to actual queues that can be applied */
3544 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3545 vsi->nb_qps = qpnum_per_tc * total_tc;
3548 * Configure TC and queue mapping parameters, for enabled TC,
3549 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3550 * default queue will serve it.
3553 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3554 if (vsi->enabled_tc & (1 << i)) {
3555 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3556 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3557 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
3558 qp_idx += qpnum_per_tc;
3560 info->tc_mapping[i] = 0;
3563 /* Associate queue number with VSI */
3564 if (vsi->type == I40E_VSI_SRIOV) {
3565 info->mapping_flags |=
3566 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
3567 for (i = 0; i < vsi->nb_qps; i++)
3568 info->queue_mapping[i] =
3569 rte_cpu_to_le_16(vsi->base_queue + i);
3571 info->mapping_flags |=
3572 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3573 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3575 info->valid_sections |=
3576 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
3578 return I40E_SUCCESS;
3582 i40e_veb_release(struct i40e_veb *veb)
3584 struct i40e_vsi *vsi;
3587 if (veb == NULL || veb->associate_vsi == NULL)
3590 if (!TAILQ_EMPTY(&veb->head)) {
3591 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
3595 vsi = veb->associate_vsi;
3596 hw = I40E_VSI_TO_HW(vsi);
3598 vsi->uplink_seid = veb->uplink_seid;
3599 i40e_aq_delete_element(hw, veb->seid, NULL);
3602 return I40E_SUCCESS;
3606 static struct i40e_veb *
3607 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
3609 struct i40e_veb *veb;
3613 if (NULL == pf || vsi == NULL) {
3614 PMD_DRV_LOG(ERR, "veb setup failed, "
3615 "associated VSI shouldn't null");
3618 hw = I40E_PF_TO_HW(pf);
3620 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
3622 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
3626 veb->associate_vsi = vsi;
3627 TAILQ_INIT(&veb->head);
3628 veb->uplink_seid = vsi->uplink_seid;
3630 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
3631 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
3633 if (ret != I40E_SUCCESS) {
3634 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
3635 hw->aq.asq_last_status);
3639 /* get statistics index */
3640 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
3641 &veb->stats_idx, NULL, NULL, NULL);
3642 if (ret != I40E_SUCCESS) {
3643 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
3644 hw->aq.asq_last_status);
3648 /* Get VEB bandwidth, to be implemented */
3649 /* Now associated vsi binding to the VEB, set uplink to this VEB */
3650 vsi->uplink_seid = veb->seid;
3659 i40e_vsi_release(struct i40e_vsi *vsi)
3663 struct i40e_vsi_list *vsi_list;
3665 struct i40e_mac_filter *f;
3668 return I40E_SUCCESS;
3670 pf = I40E_VSI_TO_PF(vsi);
3671 hw = I40E_VSI_TO_HW(vsi);
3673 /* VSI has child to attach, release child first */
3675 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
3676 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
3678 TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
3680 i40e_veb_release(vsi->veb);
3683 /* Remove all macvlan filters of the VSI */
3684 i40e_vsi_remove_all_macvlan_filter(vsi);
3685 TAILQ_FOREACH(f, &vsi->mac_list, next)
3688 if (vsi->type != I40E_VSI_MAIN) {
3689 /* Remove vsi from parent's sibling list */
3690 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
3691 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
3692 return I40E_ERR_PARAM;
3694 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
3695 &vsi->sib_vsi_list, list);
3697 /* Remove all switch element of the VSI */
3698 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
3699 if (ret != I40E_SUCCESS)
3700 PMD_DRV_LOG(ERR, "Failed to delete element");
3702 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
3704 if (vsi->type != I40E_VSI_SRIOV)
3705 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
3708 return I40E_SUCCESS;
3712 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
3714 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3715 struct i40e_aqc_remove_macvlan_element_data def_filter;
3716 struct i40e_mac_filter_info filter;
3719 if (vsi->type != I40E_VSI_MAIN)
3720 return I40E_ERR_CONFIG;
3721 memset(&def_filter, 0, sizeof(def_filter));
3722 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
3724 def_filter.vlan_tag = 0;
3725 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
3726 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
3727 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
3728 if (ret != I40E_SUCCESS) {
3729 struct i40e_mac_filter *f;
3730 struct ether_addr *mac;
3732 PMD_DRV_LOG(WARNING, "Cannot remove the default "
3734 /* It needs to add the permanent mac into mac list */
3735 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3737 PMD_DRV_LOG(ERR, "failed to allocate memory");
3738 return I40E_ERR_NO_MEMORY;
3740 mac = &f->mac_info.mac_addr;
3741 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
3743 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3744 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3749 (void)rte_memcpy(&filter.mac_addr,
3750 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
3751 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3752 return i40e_vsi_add_mac(vsi, &filter);
3756 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
3758 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
3759 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
3760 struct i40e_hw *hw = &vsi->adapter->hw;
3764 memset(&bw_config, 0, sizeof(bw_config));
3765 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3766 if (ret != I40E_SUCCESS) {
3767 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
3768 hw->aq.asq_last_status);
3772 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
3773 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
3774 &ets_sla_config, NULL);
3775 if (ret != I40E_SUCCESS) {
3776 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
3777 "configuration %u", hw->aq.asq_last_status);
3781 /* Not store the info yet, just print out */
3782 PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
3783 PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
3784 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3785 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
3786 ets_sla_config.share_credits[i]);
3787 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
3788 rte_le_to_cpu_16(ets_sla_config.credits[i]));
3789 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
3790 rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
3799 i40e_vsi_setup(struct i40e_pf *pf,
3800 enum i40e_vsi_type type,
3801 struct i40e_vsi *uplink_vsi,
3802 uint16_t user_param)
3804 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3805 struct i40e_vsi *vsi;
3806 struct i40e_mac_filter_info filter;
3808 struct i40e_vsi_context ctxt;
3809 struct ether_addr broadcast =
3810 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
3812 if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
3813 PMD_DRV_LOG(ERR, "VSI setup failed, "
3814 "VSI link shouldn't be NULL");
3818 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
3819 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
3820 "uplink VSI should be NULL");
3824 /* If uplink vsi didn't setup VEB, create one first */
3825 if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
3826 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
3828 if (NULL == uplink_vsi->veb) {
3829 PMD_DRV_LOG(ERR, "VEB setup failed");
3834 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
3836 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
3839 TAILQ_INIT(&vsi->mac_list);
3841 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
3842 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
3843 vsi->parent_vsi = uplink_vsi;
3844 vsi->user_param = user_param;
3845 /* Allocate queues */
3846 switch (vsi->type) {
3847 case I40E_VSI_MAIN :
3848 vsi->nb_qps = pf->lan_nb_qps;
3850 case I40E_VSI_SRIOV :
3851 vsi->nb_qps = pf->vf_nb_qps;
3853 case I40E_VSI_VMDQ2:
3854 vsi->nb_qps = pf->vmdq_nb_qps;
3857 vsi->nb_qps = pf->fdir_nb_qps;
3863 * The filter status descriptor is reported in rx queue 0,
3864 * while the tx queue for fdir filter programming has no
3865 * such constraints, can be non-zero queues.
3866 * To simplify it, choose FDIR vsi use queue 0 pair.
3867 * To make sure it will use queue 0 pair, queue allocation
3868 * need be done before this function is called
3870 if (type != I40E_VSI_FDIR) {
3871 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
3873 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
3877 vsi->base_queue = ret;
3879 vsi->base_queue = I40E_FDIR_QUEUE_ID;
3881 /* VF has MSIX interrupt in VF range, don't allocate here */
3882 if (type == I40E_VSI_MAIN) {
3883 ret = i40e_res_pool_alloc(&pf->msix_pool,
3884 RTE_MIN(vsi->nb_qps,
3885 RTE_MAX_RXTX_INTR_VEC_ID));
3887 PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
3889 goto fail_queue_alloc;
3891 vsi->msix_intr = ret;
3892 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
3893 } else if (type != I40E_VSI_SRIOV) {
3894 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
3896 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
3897 goto fail_queue_alloc;
3899 vsi->msix_intr = ret;
3907 if (type == I40E_VSI_MAIN) {
3908 /* For main VSI, no need to add since it's default one */
3909 vsi->uplink_seid = pf->mac_seid;
3910 vsi->seid = pf->main_vsi_seid;
3911 /* Bind queues with specific MSIX interrupt */
3913 * Needs 2 interrupt at least, one for misc cause which will
3914 * enabled from OS side, Another for queues binding the
3915 * interrupt from device side only.
3918 /* Get default VSI parameters from hardware */
3919 memset(&ctxt, 0, sizeof(ctxt));
3920 ctxt.seid = vsi->seid;
3921 ctxt.pf_num = hw->pf_id;
3922 ctxt.uplink_seid = vsi->uplink_seid;
3924 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
3925 if (ret != I40E_SUCCESS) {
3926 PMD_DRV_LOG(ERR, "Failed to get VSI params");
3927 goto fail_msix_alloc;
3929 (void)rte_memcpy(&vsi->info, &ctxt.info,
3930 sizeof(struct i40e_aqc_vsi_properties_data));
3931 vsi->vsi_id = ctxt.vsi_number;
3932 vsi->info.valid_sections = 0;
3934 /* Configure tc, enabled TC0 only */
3935 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
3937 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
3938 goto fail_msix_alloc;
3941 /* TC, queue mapping */
3942 memset(&ctxt, 0, sizeof(ctxt));
3943 vsi->info.valid_sections |=
3944 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3945 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
3946 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3947 (void)rte_memcpy(&ctxt.info, &vsi->info,
3948 sizeof(struct i40e_aqc_vsi_properties_data));
3949 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3950 I40E_DEFAULT_TCMAP);
3951 if (ret != I40E_SUCCESS) {
3952 PMD_DRV_LOG(ERR, "Failed to configure "
3953 "TC queue mapping");
3954 goto fail_msix_alloc;
3956 ctxt.seid = vsi->seid;
3957 ctxt.pf_num = hw->pf_id;
3958 ctxt.uplink_seid = vsi->uplink_seid;
3961 /* Update VSI parameters */
3962 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3963 if (ret != I40E_SUCCESS) {
3964 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3965 goto fail_msix_alloc;
3968 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
3969 sizeof(vsi->info.tc_mapping));
3970 (void)rte_memcpy(&vsi->info.queue_mapping,
3971 &ctxt.info.queue_mapping,
3972 sizeof(vsi->info.queue_mapping));
3973 vsi->info.mapping_flags = ctxt.info.mapping_flags;
3974 vsi->info.valid_sections = 0;
3976 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
3980 * Updating default filter settings are necessary to prevent
3981 * reception of tagged packets.
3982 * Some old firmware configurations load a default macvlan
3983 * filter which accepts both tagged and untagged packets.
3984 * The updating is to use a normal filter instead if needed.
3985 * For NVM 4.2.2 or after, the updating is not needed anymore.
3986 * The firmware with correct configurations load the default
3987 * macvlan filter which is expected and cannot be removed.
3989 i40e_update_default_filter_setting(vsi);
3990 i40e_config_qinq(hw, vsi);
3991 } else if (type == I40E_VSI_SRIOV) {
3992 memset(&ctxt, 0, sizeof(ctxt));
3994 * For other VSI, the uplink_seid equals to uplink VSI's
3995 * uplink_seid since they share same VEB
3997 vsi->uplink_seid = uplink_vsi->uplink_seid;
3998 ctxt.pf_num = hw->pf_id;
3999 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4000 ctxt.uplink_seid = vsi->uplink_seid;
4001 ctxt.connection_type = 0x1;
4002 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4005 * Do not configure switch ID to enable VEB switch by
4006 * I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB. Because in Fortville,
4007 * if the source mac address of packet sent from VF is not
4008 * listed in the VEB's mac table, the VEB will switch the
4009 * packet back to the VF. Need to enable it when HW issue
4013 /* Configure port/vlan */
4014 ctxt.info.valid_sections |=
4015 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4016 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4017 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4018 I40E_DEFAULT_TCMAP);
4019 if (ret != I40E_SUCCESS) {
4020 PMD_DRV_LOG(ERR, "Failed to configure "
4021 "TC queue mapping");
4022 goto fail_msix_alloc;
4024 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4025 ctxt.info.valid_sections |=
4026 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4028 * Since VSI is not created yet, only configure parameter,
4029 * will add vsi below.
4032 i40e_config_qinq(hw, vsi);
4033 } else if (type == I40E_VSI_VMDQ2) {
4034 memset(&ctxt, 0, sizeof(ctxt));
4036 * For other VSI, the uplink_seid equals to uplink VSI's
4037 * uplink_seid since they share same VEB
4039 vsi->uplink_seid = uplink_vsi->uplink_seid;
4040 ctxt.pf_num = hw->pf_id;
4042 ctxt.uplink_seid = vsi->uplink_seid;
4043 ctxt.connection_type = 0x1;
4044 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4046 ctxt.info.valid_sections |=
4047 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4048 /* user_param carries flag to enable loop back */
4050 ctxt.info.switch_id =
4051 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4052 ctxt.info.switch_id |=
4053 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4056 /* Configure port/vlan */
4057 ctxt.info.valid_sections |=
4058 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4059 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4060 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4061 I40E_DEFAULT_TCMAP);
4062 if (ret != I40E_SUCCESS) {
4063 PMD_DRV_LOG(ERR, "Failed to configure "
4064 "TC queue mapping");
4065 goto fail_msix_alloc;
4067 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4068 ctxt.info.valid_sections |=
4069 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4070 } else if (type == I40E_VSI_FDIR) {
4071 memset(&ctxt, 0, sizeof(ctxt));
4072 vsi->uplink_seid = uplink_vsi->uplink_seid;
4073 ctxt.pf_num = hw->pf_id;
4075 ctxt.uplink_seid = vsi->uplink_seid;
4076 ctxt.connection_type = 0x1; /* regular data port */
4077 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4078 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4079 I40E_DEFAULT_TCMAP);
4080 if (ret != I40E_SUCCESS) {
4081 PMD_DRV_LOG(ERR, "Failed to configure "
4082 "TC queue mapping.");
4083 goto fail_msix_alloc;
4085 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4086 ctxt.info.valid_sections |=
4087 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4089 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4090 goto fail_msix_alloc;
4093 if (vsi->type != I40E_VSI_MAIN) {
4094 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4095 if (ret != I40E_SUCCESS) {
4096 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4097 hw->aq.asq_last_status);
4098 goto fail_msix_alloc;
4100 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4101 vsi->info.valid_sections = 0;
4102 vsi->seid = ctxt.seid;
4103 vsi->vsi_id = ctxt.vsi_number;
4104 vsi->sib_vsi_list.vsi = vsi;
4105 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4106 &vsi->sib_vsi_list, list);
4109 /* MAC/VLAN configuration */
4110 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4111 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4113 ret = i40e_vsi_add_mac(vsi, &filter);
4114 if (ret != I40E_SUCCESS) {
4115 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4116 goto fail_msix_alloc;
4119 /* Get VSI BW information */
4120 i40e_vsi_dump_bw_config(vsi);
4123 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4125 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4131 /* Configure vlan stripping on or off */
4133 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4135 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4136 struct i40e_vsi_context ctxt;
4138 int ret = I40E_SUCCESS;
4140 /* Check if it has been already on or off */
4141 if (vsi->info.valid_sections &
4142 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4144 if ((vsi->info.port_vlan_flags &
4145 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4146 return 0; /* already on */
4148 if ((vsi->info.port_vlan_flags &
4149 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4150 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4151 return 0; /* already off */
4156 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4158 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4159 vsi->info.valid_sections =
4160 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4161 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4162 vsi->info.port_vlan_flags |= vlan_flags;
4163 ctxt.seid = vsi->seid;
4164 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4165 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4167 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4168 on ? "enable" : "disable");
4174 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4176 struct rte_eth_dev_data *data = dev->data;
4179 /* Apply vlan offload setting */
4180 i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
4182 /* Apply double-vlan setting, not implemented yet */
4184 /* Apply pvid setting */
4185 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4186 data->dev_conf.txmode.hw_vlan_insert_pvid);
4188 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4194 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4196 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4198 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4202 i40e_update_flow_control(struct i40e_hw *hw)
4204 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4205 struct i40e_link_status link_status;
4206 uint32_t rxfc = 0, txfc = 0, reg;
4210 memset(&link_status, 0, sizeof(link_status));
4211 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4212 if (ret != I40E_SUCCESS) {
4213 PMD_DRV_LOG(ERR, "Failed to get link status information");
4214 goto write_reg; /* Disable flow control */
4217 an_info = hw->phy.link_info.an_info;
4218 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4219 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4220 ret = I40E_ERR_NOT_READY;
4221 goto write_reg; /* Disable flow control */
4224 * If link auto negotiation is enabled, flow control needs to
4225 * be configured according to it
4227 switch (an_info & I40E_LINK_PAUSE_RXTX) {
4228 case I40E_LINK_PAUSE_RXTX:
4231 hw->fc.current_mode = I40E_FC_FULL;
4233 case I40E_AQ_LINK_PAUSE_RX:
4235 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4237 case I40E_AQ_LINK_PAUSE_TX:
4239 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4242 hw->fc.current_mode = I40E_FC_NONE;
4247 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4248 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4249 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4250 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4251 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4252 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4259 i40e_pf_setup(struct i40e_pf *pf)
4261 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4262 struct i40e_filter_control_settings settings;
4263 struct i40e_vsi *vsi;
4266 /* Clear all stats counters */
4267 pf->offset_loaded = FALSE;
4268 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4269 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4271 ret = i40e_pf_get_switch_config(pf);
4272 if (ret != I40E_SUCCESS) {
4273 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4276 if (pf->flags & I40E_FLAG_FDIR) {
4277 /* make queue allocated first, let FDIR use queue pair 0*/
4278 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4279 if (ret != I40E_FDIR_QUEUE_ID) {
4280 PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4282 pf->flags &= ~I40E_FLAG_FDIR;
4285 /* main VSI setup */
4286 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4288 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4289 return I40E_ERR_NOT_READY;
4293 /* Configure filter control */
4294 memset(&settings, 0, sizeof(settings));
4295 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4296 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4297 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4298 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4300 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4301 hw->func_caps.rss_table_size);
4302 return I40E_ERR_PARAM;
4304 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4305 "size: %u\n", hw->func_caps.rss_table_size);
4306 pf->hash_lut_size = hw->func_caps.rss_table_size;
4308 /* Enable ethtype and macvlan filters */
4309 settings.enable_ethtype = TRUE;
4310 settings.enable_macvlan = TRUE;
4311 ret = i40e_set_filter_control(hw, &settings);
4313 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4316 /* Update flow control according to the auto negotiation */
4317 i40e_update_flow_control(hw);
4319 return I40E_SUCCESS;
4323 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4329 * Set or clear TX Queue Disable flags,
4330 * which is required by hardware.
4332 i40e_pre_tx_queue_cfg(hw, q_idx, on);
4333 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4335 /* Wait until the request is finished */
4336 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4337 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4338 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4339 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4340 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4346 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4347 return I40E_SUCCESS; /* already on, skip next steps */
4349 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4350 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4352 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4353 return I40E_SUCCESS; /* already off, skip next steps */
4354 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4356 /* Write the register */
4357 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4358 /* Check the result */
4359 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4360 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4361 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4363 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4364 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
4367 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4368 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4372 /* Check if it is timeout */
4373 if (j >= I40E_CHK_Q_ENA_COUNT) {
4374 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
4375 (on ? "enable" : "disable"), q_idx);
4376 return I40E_ERR_TIMEOUT;
4379 return I40E_SUCCESS;
4382 /* Swith on or off the tx queues */
4384 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
4386 struct rte_eth_dev_data *dev_data = pf->dev_data;
4387 struct i40e_tx_queue *txq;
4388 struct rte_eth_dev *dev = pf->adapter->eth_dev;
4392 for (i = 0; i < dev_data->nb_tx_queues; i++) {
4393 txq = dev_data->tx_queues[i];
4394 /* Don't operate the queue if not configured or
4395 * if starting only per queue */
4396 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
4399 ret = i40e_dev_tx_queue_start(dev, i);
4401 ret = i40e_dev_tx_queue_stop(dev, i);
4402 if ( ret != I40E_SUCCESS)
4406 return I40E_SUCCESS;
4410 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4415 /* Wait until the request is finished */
4416 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4417 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4418 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4419 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4420 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
4425 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
4426 return I40E_SUCCESS; /* Already on, skip next steps */
4427 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
4429 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4430 return I40E_SUCCESS; /* Already off, skip next steps */
4431 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
4434 /* Write the register */
4435 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
4436 /* Check the result */
4437 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4438 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4439 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4441 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4442 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
4445 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4446 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4451 /* Check if it is timeout */
4452 if (j >= I40E_CHK_Q_ENA_COUNT) {
4453 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
4454 (on ? "enable" : "disable"), q_idx);
4455 return I40E_ERR_TIMEOUT;
4458 return I40E_SUCCESS;
4460 /* Switch on or off the rx queues */
4462 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
4464 struct rte_eth_dev_data *dev_data = pf->dev_data;
4465 struct i40e_rx_queue *rxq;
4466 struct rte_eth_dev *dev = pf->adapter->eth_dev;
4470 for (i = 0; i < dev_data->nb_rx_queues; i++) {
4471 rxq = dev_data->rx_queues[i];
4472 /* Don't operate the queue if not configured or
4473 * if starting only per queue */
4474 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
4477 ret = i40e_dev_rx_queue_start(dev, i);
4479 ret = i40e_dev_rx_queue_stop(dev, i);
4480 if (ret != I40E_SUCCESS)
4484 return I40E_SUCCESS;
4487 /* Switch on or off all the rx/tx queues */
4489 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
4494 /* enable rx queues before enabling tx queues */
4495 ret = i40e_dev_switch_rx_queues(pf, on);
4497 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
4500 ret = i40e_dev_switch_tx_queues(pf, on);
4502 /* Stop tx queues before stopping rx queues */
4503 ret = i40e_dev_switch_tx_queues(pf, on);
4505 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
4508 ret = i40e_dev_switch_rx_queues(pf, on);
4514 /* Initialize VSI for TX */
4516 i40e_dev_tx_init(struct i40e_pf *pf)
4518 struct rte_eth_dev_data *data = pf->dev_data;
4520 uint32_t ret = I40E_SUCCESS;
4521 struct i40e_tx_queue *txq;
4523 for (i = 0; i < data->nb_tx_queues; i++) {
4524 txq = data->tx_queues[i];
4525 if (!txq || !txq->q_set)
4527 ret = i40e_tx_queue_init(txq);
4528 if (ret != I40E_SUCCESS)
4531 if (ret == I40E_SUCCESS)
4532 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
4538 /* Initialize VSI for RX */
4540 i40e_dev_rx_init(struct i40e_pf *pf)
4542 struct rte_eth_dev_data *data = pf->dev_data;
4543 int ret = I40E_SUCCESS;
4545 struct i40e_rx_queue *rxq;
4547 i40e_pf_config_mq_rx(pf);
4548 for (i = 0; i < data->nb_rx_queues; i++) {
4549 rxq = data->rx_queues[i];
4550 if (!rxq || !rxq->q_set)
4553 ret = i40e_rx_queue_init(rxq);
4554 if (ret != I40E_SUCCESS) {
4555 PMD_DRV_LOG(ERR, "Failed to do RX queue "
4560 if (ret == I40E_SUCCESS)
4561 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
4568 i40e_dev_rxtx_init(struct i40e_pf *pf)
4572 err = i40e_dev_tx_init(pf);
4574 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
4577 err = i40e_dev_rx_init(pf);
4579 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
4587 i40e_vmdq_setup(struct rte_eth_dev *dev)
4589 struct rte_eth_conf *conf = &dev->data->dev_conf;
4590 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4591 int i, err, conf_vsis, j, loop;
4592 struct i40e_vsi *vsi;
4593 struct i40e_vmdq_info *vmdq_info;
4594 struct rte_eth_vmdq_rx_conf *vmdq_conf;
4595 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4598 * Disable interrupt to avoid message from VF. Furthermore, it will
4599 * avoid race condition in VSI creation/destroy.
4601 i40e_pf_disable_irq0(hw);
4603 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
4604 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
4608 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
4609 if (conf_vsis > pf->max_nb_vmdq_vsi) {
4610 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
4611 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
4612 pf->max_nb_vmdq_vsi);
4616 if (pf->vmdq != NULL) {
4617 PMD_INIT_LOG(INFO, "VMDQ already configured");
4621 pf->vmdq = rte_zmalloc("vmdq_info_struct",
4622 sizeof(*vmdq_info) * conf_vsis, 0);
4624 if (pf->vmdq == NULL) {
4625 PMD_INIT_LOG(ERR, "Failed to allocate memory");
4629 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
4631 /* Create VMDQ VSI */
4632 for (i = 0; i < conf_vsis; i++) {
4633 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
4634 vmdq_conf->enable_loop_back);
4636 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
4640 vmdq_info = &pf->vmdq[i];
4642 vmdq_info->vsi = vsi;
4644 pf->nb_cfg_vmdq_vsi = conf_vsis;
4646 /* Configure Vlan */
4647 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
4648 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
4649 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
4650 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
4651 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
4652 vmdq_conf->pool_map[i].vlan_id, j);
4654 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
4655 vmdq_conf->pool_map[i].vlan_id);
4657 PMD_INIT_LOG(ERR, "Failed to add vlan");
4665 i40e_pf_enable_irq0(hw);
4670 for (i = 0; i < conf_vsis; i++)
4671 if (pf->vmdq[i].vsi == NULL)
4674 i40e_vsi_release(pf->vmdq[i].vsi);
4678 i40e_pf_enable_irq0(hw);
4683 i40e_stat_update_32(struct i40e_hw *hw,
4691 new_data = (uint64_t)I40E_READ_REG(hw, reg);
4695 if (new_data >= *offset)
4696 *stat = (uint64_t)(new_data - *offset);
4698 *stat = (uint64_t)((new_data +
4699 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
4703 i40e_stat_update_48(struct i40e_hw *hw,
4712 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
4713 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
4714 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
4719 if (new_data >= *offset)
4720 *stat = new_data - *offset;
4722 *stat = (uint64_t)((new_data +
4723 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
4725 *stat &= I40E_48_BIT_MASK;
4730 i40e_pf_disable_irq0(struct i40e_hw *hw)
4732 /* Disable all interrupt types */
4733 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
4734 I40E_WRITE_FLUSH(hw);
4739 i40e_pf_enable_irq0(struct i40e_hw *hw)
4741 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
4742 I40E_PFINT_DYN_CTL0_INTENA_MASK |
4743 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
4744 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
4745 I40E_WRITE_FLUSH(hw);
4749 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
4751 /* read pending request and disable first */
4752 i40e_pf_disable_irq0(hw);
4753 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
4754 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
4755 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
4758 /* Link no queues with irq0 */
4759 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
4760 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
4764 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
4766 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4767 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4770 uint32_t index, offset, val;
4775 * Try to find which VF trigger a reset, use absolute VF id to access
4776 * since the reg is global register.
4778 for (i = 0; i < pf->vf_num; i++) {
4779 abs_vf_id = hw->func_caps.vf_base_id + i;
4780 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
4781 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
4782 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
4783 /* VFR event occured */
4784 if (val & (0x1 << offset)) {
4787 /* Clear the event first */
4788 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
4790 PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
4792 * Only notify a VF reset event occured,
4793 * don't trigger another SW reset
4795 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
4796 if (ret != I40E_SUCCESS)
4797 PMD_DRV_LOG(ERR, "Failed to do VF reset");
4803 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
4805 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4806 struct i40e_arq_event_info info;
4807 uint16_t pending, opcode;
4810 info.buf_len = I40E_AQ_BUF_SZ;
4811 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
4812 if (!info.msg_buf) {
4813 PMD_DRV_LOG(ERR, "Failed to allocate mem");
4819 ret = i40e_clean_arq_element(hw, &info, &pending);
4821 if (ret != I40E_SUCCESS) {
4822 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
4823 "aq_err: %u", hw->aq.asq_last_status);
4826 opcode = rte_le_to_cpu_16(info.desc.opcode);
4829 case i40e_aqc_opc_send_msg_to_pf:
4830 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
4831 i40e_pf_host_handle_vf_msg(dev,
4832 rte_le_to_cpu_16(info.desc.retval),
4833 rte_le_to_cpu_32(info.desc.cookie_high),
4834 rte_le_to_cpu_32(info.desc.cookie_low),
4839 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
4844 rte_free(info.msg_buf);
4848 * Interrupt handler is registered as the alarm callback for handling LSC
4849 * interrupt in a definite of time, in order to wait the NIC into a stable
4850 * state. Currently it waits 1 sec in i40e for the link up interrupt, and
4851 * no need for link down interrupt.
4854 i40e_dev_interrupt_delayed_handler(void *param)
4856 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4857 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4860 /* read interrupt causes again */
4861 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4863 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4864 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4865 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
4866 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4867 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
4868 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4869 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
4870 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4871 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
4872 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4873 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
4875 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4876 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
4877 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4878 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
4879 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4881 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4882 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
4883 i40e_dev_handle_vfr_event(dev);
4885 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4886 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
4887 i40e_dev_handle_aq_msg(dev);
4890 /* handle the link up interrupt in an alarm callback */
4891 i40e_dev_link_update(dev, 0);
4892 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
4894 i40e_pf_enable_irq0(hw);
4895 rte_intr_enable(&(dev->pci_dev->intr_handle));
4899 * Interrupt handler triggered by NIC for handling
4900 * specific interrupt.
4903 * Pointer to interrupt handle.
4905 * The address of parameter (struct rte_eth_dev *) regsitered before.
4911 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
4914 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4915 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4918 /* Disable interrupt */
4919 i40e_pf_disable_irq0(hw);
4921 /* read out interrupt causes */
4922 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4924 /* No interrupt event indicated */
4925 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
4926 PMD_DRV_LOG(INFO, "No interrupt event");
4929 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4930 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4931 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
4932 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4933 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
4934 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4935 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
4936 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4937 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
4938 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4939 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
4940 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4941 PMD_DRV_LOG(ERR, "ICR0: HMC error");
4942 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4943 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
4944 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4946 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4947 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
4948 i40e_dev_handle_vfr_event(dev);
4950 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4951 PMD_DRV_LOG(INFO, "ICR0: adminq event");
4952 i40e_dev_handle_aq_msg(dev);
4955 /* Link Status Change interrupt */
4956 if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
4957 #define I40E_US_PER_SECOND 1000000
4958 struct rte_eth_link link;
4960 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
4961 memset(&link, 0, sizeof(link));
4962 rte_i40e_dev_atomic_read_link_status(dev, &link);
4963 i40e_dev_link_update(dev, 0);
4966 * For link up interrupt, it needs to wait 1 second to let the
4967 * hardware be a stable state. Otherwise several consecutive
4968 * interrupts can be observed.
4969 * For link down interrupt, no need to wait.
4971 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
4972 i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
4975 _rte_eth_dev_callback_process(dev,
4976 RTE_ETH_EVENT_INTR_LSC);
4980 /* Enable interrupt */
4981 i40e_pf_enable_irq0(hw);
4982 rte_intr_enable(&(dev->pci_dev->intr_handle));
4986 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
4987 struct i40e_macvlan_filter *filter,
4990 int ele_num, ele_buff_size;
4991 int num, actual_num, i;
4993 int ret = I40E_SUCCESS;
4994 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4995 struct i40e_aqc_add_macvlan_element_data *req_list;
4997 if (filter == NULL || total == 0)
4998 return I40E_ERR_PARAM;
4999 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5000 ele_buff_size = hw->aq.asq_buf_size;
5002 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5003 if (req_list == NULL) {
5004 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5005 return I40E_ERR_NO_MEMORY;
5010 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5011 memset(req_list, 0, ele_buff_size);
5013 for (i = 0; i < actual_num; i++) {
5014 (void)rte_memcpy(req_list[i].mac_addr,
5015 &filter[num + i].macaddr, ETH_ADDR_LEN);
5016 req_list[i].vlan_tag =
5017 rte_cpu_to_le_16(filter[num + i].vlan_id);
5019 switch (filter[num + i].filter_type) {
5020 case RTE_MAC_PERFECT_MATCH:
5021 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5022 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5024 case RTE_MACVLAN_PERFECT_MATCH:
5025 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5027 case RTE_MAC_HASH_MATCH:
5028 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5029 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5031 case RTE_MACVLAN_HASH_MATCH:
5032 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5035 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5036 ret = I40E_ERR_PARAM;
5040 req_list[i].queue_number = 0;
5042 req_list[i].flags = rte_cpu_to_le_16(flags);
5045 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5047 if (ret != I40E_SUCCESS) {
5048 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5052 } while (num < total);
5060 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5061 struct i40e_macvlan_filter *filter,
5064 int ele_num, ele_buff_size;
5065 int num, actual_num, i;
5067 int ret = I40E_SUCCESS;
5068 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5069 struct i40e_aqc_remove_macvlan_element_data *req_list;
5071 if (filter == NULL || total == 0)
5072 return I40E_ERR_PARAM;
5074 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5075 ele_buff_size = hw->aq.asq_buf_size;
5077 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5078 if (req_list == NULL) {
5079 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5080 return I40E_ERR_NO_MEMORY;
5085 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5086 memset(req_list, 0, ele_buff_size);
5088 for (i = 0; i < actual_num; i++) {
5089 (void)rte_memcpy(req_list[i].mac_addr,
5090 &filter[num + i].macaddr, ETH_ADDR_LEN);
5091 req_list[i].vlan_tag =
5092 rte_cpu_to_le_16(filter[num + i].vlan_id);
5094 switch (filter[num + i].filter_type) {
5095 case RTE_MAC_PERFECT_MATCH:
5096 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5097 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5099 case RTE_MACVLAN_PERFECT_MATCH:
5100 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5102 case RTE_MAC_HASH_MATCH:
5103 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5104 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5106 case RTE_MACVLAN_HASH_MATCH:
5107 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5110 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5111 ret = I40E_ERR_PARAM;
5114 req_list[i].flags = rte_cpu_to_le_16(flags);
5117 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5119 if (ret != I40E_SUCCESS) {
5120 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5124 } while (num < total);
5131 /* Find out specific MAC filter */
5132 static struct i40e_mac_filter *
5133 i40e_find_mac_filter(struct i40e_vsi *vsi,
5134 struct ether_addr *macaddr)
5136 struct i40e_mac_filter *f;
5138 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5139 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5147 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5150 uint32_t vid_idx, vid_bit;
5152 if (vlan_id > ETH_VLAN_ID_MAX)
5155 vid_idx = I40E_VFTA_IDX(vlan_id);
5156 vid_bit = I40E_VFTA_BIT(vlan_id);
5158 if (vsi->vfta[vid_idx] & vid_bit)
5165 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5166 uint16_t vlan_id, bool on)
5168 uint32_t vid_idx, vid_bit;
5170 if (vlan_id > ETH_VLAN_ID_MAX)
5173 vid_idx = I40E_VFTA_IDX(vlan_id);
5174 vid_bit = I40E_VFTA_BIT(vlan_id);
5177 vsi->vfta[vid_idx] |= vid_bit;
5179 vsi->vfta[vid_idx] &= ~vid_bit;
5183 * Find all vlan options for specific mac addr,
5184 * return with actual vlan found.
5187 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5188 struct i40e_macvlan_filter *mv_f,
5189 int num, struct ether_addr *addr)
5195 * Not to use i40e_find_vlan_filter to decrease the loop time,
5196 * although the code looks complex.
5198 if (num < vsi->vlan_num)
5199 return I40E_ERR_PARAM;
5202 for (j = 0; j < I40E_VFTA_SIZE; j++) {
5204 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5205 if (vsi->vfta[j] & (1 << k)) {
5207 PMD_DRV_LOG(ERR, "vlan number "
5209 return I40E_ERR_PARAM;
5211 (void)rte_memcpy(&mv_f[i].macaddr,
5212 addr, ETH_ADDR_LEN);
5214 j * I40E_UINT32_BIT_SIZE + k;
5220 return I40E_SUCCESS;
5224 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5225 struct i40e_macvlan_filter *mv_f,
5230 struct i40e_mac_filter *f;
5232 if (num < vsi->mac_num)
5233 return I40E_ERR_PARAM;
5235 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5237 PMD_DRV_LOG(ERR, "buffer number not match");
5238 return I40E_ERR_PARAM;
5240 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5242 mv_f[i].vlan_id = vlan;
5243 mv_f[i].filter_type = f->mac_info.filter_type;
5247 return I40E_SUCCESS;
5251 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5254 struct i40e_mac_filter *f;
5255 struct i40e_macvlan_filter *mv_f;
5256 int ret = I40E_SUCCESS;
5258 if (vsi == NULL || vsi->mac_num == 0)
5259 return I40E_ERR_PARAM;
5261 /* Case that no vlan is set */
5262 if (vsi->vlan_num == 0)
5265 num = vsi->mac_num * vsi->vlan_num;
5267 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5269 PMD_DRV_LOG(ERR, "failed to allocate memory");
5270 return I40E_ERR_NO_MEMORY;
5274 if (vsi->vlan_num == 0) {
5275 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5276 (void)rte_memcpy(&mv_f[i].macaddr,
5277 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5278 mv_f[i].vlan_id = 0;
5282 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5283 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5284 vsi->vlan_num, &f->mac_info.mac_addr);
5285 if (ret != I40E_SUCCESS)
5291 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5299 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5301 struct i40e_macvlan_filter *mv_f;
5303 int ret = I40E_SUCCESS;
5305 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5306 return I40E_ERR_PARAM;
5308 /* If it's already set, just return */
5309 if (i40e_find_vlan_filter(vsi,vlan))
5310 return I40E_SUCCESS;
5312 mac_num = vsi->mac_num;
5315 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5316 return I40E_ERR_PARAM;
5319 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5322 PMD_DRV_LOG(ERR, "failed to allocate memory");
5323 return I40E_ERR_NO_MEMORY;
5326 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5328 if (ret != I40E_SUCCESS)
5331 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5333 if (ret != I40E_SUCCESS)
5336 i40e_set_vlan_filter(vsi, vlan, 1);
5346 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5348 struct i40e_macvlan_filter *mv_f;
5350 int ret = I40E_SUCCESS;
5353 * Vlan 0 is the generic filter for untagged packets
5354 * and can't be removed.
5356 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5357 return I40E_ERR_PARAM;
5359 /* If can't find it, just return */
5360 if (!i40e_find_vlan_filter(vsi, vlan))
5361 return I40E_ERR_PARAM;
5363 mac_num = vsi->mac_num;
5366 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5367 return I40E_ERR_PARAM;
5370 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5373 PMD_DRV_LOG(ERR, "failed to allocate memory");
5374 return I40E_ERR_NO_MEMORY;
5377 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5379 if (ret != I40E_SUCCESS)
5382 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5384 if (ret != I40E_SUCCESS)
5387 /* This is last vlan to remove, replace all mac filter with vlan 0 */
5388 if (vsi->vlan_num == 1) {
5389 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5390 if (ret != I40E_SUCCESS)
5393 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5394 if (ret != I40E_SUCCESS)
5398 i40e_set_vlan_filter(vsi, vlan, 0);
5408 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
5410 struct i40e_mac_filter *f;
5411 struct i40e_macvlan_filter *mv_f;
5412 int i, vlan_num = 0;
5413 int ret = I40E_SUCCESS;
5415 /* If it's add and we've config it, return */
5416 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
5418 return I40E_SUCCESS;
5419 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
5420 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
5423 * If vlan_num is 0, that's the first time to add mac,
5424 * set mask for vlan_id 0.
5426 if (vsi->vlan_num == 0) {
5427 i40e_set_vlan_filter(vsi, 0, 1);
5430 vlan_num = vsi->vlan_num;
5431 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
5432 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
5435 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5437 PMD_DRV_LOG(ERR, "failed to allocate memory");
5438 return I40E_ERR_NO_MEMORY;
5441 for (i = 0; i < vlan_num; i++) {
5442 mv_f[i].filter_type = mac_filter->filter_type;
5443 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
5447 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5448 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
5449 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
5450 &mac_filter->mac_addr);
5451 if (ret != I40E_SUCCESS)
5455 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
5456 if (ret != I40E_SUCCESS)
5459 /* Add the mac addr into mac list */
5460 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5462 PMD_DRV_LOG(ERR, "failed to allocate memory");
5463 ret = I40E_ERR_NO_MEMORY;
5466 (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
5468 f->mac_info.filter_type = mac_filter->filter_type;
5469 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5480 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
5482 struct i40e_mac_filter *f;
5483 struct i40e_macvlan_filter *mv_f;
5485 enum rte_mac_filter_type filter_type;
5486 int ret = I40E_SUCCESS;
5488 /* Can't find it, return an error */
5489 f = i40e_find_mac_filter(vsi, addr);
5491 return I40E_ERR_PARAM;
5493 vlan_num = vsi->vlan_num;
5494 filter_type = f->mac_info.filter_type;
5495 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5496 filter_type == RTE_MACVLAN_HASH_MATCH) {
5497 if (vlan_num == 0) {
5498 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
5499 return I40E_ERR_PARAM;
5501 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
5502 filter_type == RTE_MAC_HASH_MATCH)
5505 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5507 PMD_DRV_LOG(ERR, "failed to allocate memory");
5508 return I40E_ERR_NO_MEMORY;
5511 for (i = 0; i < vlan_num; i++) {
5512 mv_f[i].filter_type = filter_type;
5513 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5516 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5517 filter_type == RTE_MACVLAN_HASH_MATCH) {
5518 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
5519 if (ret != I40E_SUCCESS)
5523 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
5524 if (ret != I40E_SUCCESS)
5527 /* Remove the mac addr into mac list */
5528 TAILQ_REMOVE(&vsi->mac_list, f, next);
5538 /* Configure hash enable flags for RSS */
5540 i40e_config_hena(uint64_t flags)
5547 if (flags & ETH_RSS_FRAG_IPV4)
5548 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
5549 if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
5550 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
5551 if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
5552 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
5553 if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
5554 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
5555 if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
5556 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
5557 if (flags & ETH_RSS_FRAG_IPV6)
5558 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
5559 if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
5560 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
5561 if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
5562 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
5563 if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
5564 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
5565 if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
5566 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
5567 if (flags & ETH_RSS_L2_PAYLOAD)
5568 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
5573 /* Parse the hash enable flags */
5575 i40e_parse_hena(uint64_t flags)
5577 uint64_t rss_hf = 0;
5581 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
5582 rss_hf |= ETH_RSS_FRAG_IPV4;
5583 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
5584 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
5585 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
5586 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
5587 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
5588 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
5589 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
5590 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
5591 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
5592 rss_hf |= ETH_RSS_FRAG_IPV6;
5593 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
5594 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
5595 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
5596 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
5597 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
5598 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
5599 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
5600 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
5601 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
5602 rss_hf |= ETH_RSS_L2_PAYLOAD;
5609 i40e_pf_disable_rss(struct i40e_pf *pf)
5611 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5614 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5615 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5616 hena &= ~I40E_RSS_HENA_ALL;
5617 I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5618 I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5619 I40E_WRITE_FLUSH(hw);
5623 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
5625 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5626 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5629 if (!key || key_len != ((I40E_PFQF_HKEY_MAX_INDEX + 1) *
5633 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5634 struct i40e_aqc_get_set_rss_key_data *key_dw =
5635 (struct i40e_aqc_get_set_rss_key_data *)key;
5637 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
5639 PMD_INIT_LOG(ERR, "Failed to configure RSS key "
5642 uint32_t *hash_key = (uint32_t *)key;
5645 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5646 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
5647 I40E_WRITE_FLUSH(hw);
5654 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
5656 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5657 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5660 if (!key || !key_len)
5663 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5664 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
5665 (struct i40e_aqc_get_set_rss_key_data *)key);
5667 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
5671 uint32_t *key_dw = (uint32_t *)key;
5674 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5675 key_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
5677 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
5683 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
5685 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5690 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
5691 rss_conf->rss_key_len);
5695 rss_hf = rss_conf->rss_hf;
5696 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5697 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5698 hena &= ~I40E_RSS_HENA_ALL;
5699 hena |= i40e_config_hena(rss_hf);
5700 I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5701 I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5702 I40E_WRITE_FLUSH(hw);
5708 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
5709 struct rte_eth_rss_conf *rss_conf)
5711 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5712 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5713 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
5716 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5717 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5718 if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
5719 if (rss_hf != 0) /* Enable RSS */
5721 return 0; /* Nothing to do */
5724 if (rss_hf == 0) /* Disable RSS */
5727 return i40e_hw_rss_hash_set(pf, rss_conf);
5731 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
5732 struct rte_eth_rss_conf *rss_conf)
5734 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5735 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5738 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
5739 &rss_conf->rss_key_len);
5741 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5742 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5743 rss_conf->rss_hf = i40e_parse_hena(hena);
5749 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
5751 switch (filter_type) {
5752 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
5753 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
5755 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
5756 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
5758 case RTE_TUNNEL_FILTER_IMAC_TENID:
5759 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
5761 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
5762 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
5764 case ETH_TUNNEL_FILTER_IMAC:
5765 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
5768 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
5776 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
5777 struct rte_eth_tunnel_filter_conf *tunnel_filter,
5781 uint8_t tun_type = 0;
5783 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5784 struct i40e_vsi *vsi = pf->main_vsi;
5785 struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter;
5786 struct i40e_aqc_add_remove_cloud_filters_element_data *pfilter;
5788 cld_filter = rte_zmalloc("tunnel_filter",
5789 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
5792 if (NULL == cld_filter) {
5793 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
5796 pfilter = cld_filter;
5798 (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
5799 sizeof(struct ether_addr));
5800 (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
5801 sizeof(struct ether_addr));
5803 pfilter->inner_vlan = tunnel_filter->inner_vlan;
5804 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
5805 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
5806 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
5807 &tunnel_filter->ip_addr,
5808 sizeof(pfilter->ipaddr.v4.data));
5810 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
5811 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
5812 &tunnel_filter->ip_addr,
5813 sizeof(pfilter->ipaddr.v6.data));
5816 /* check tunneled type */
5817 switch (tunnel_filter->tunnel_type) {
5818 case RTE_TUNNEL_TYPE_VXLAN:
5819 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
5821 case RTE_TUNNEL_TYPE_NVGRE:
5822 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
5825 /* Other tunnel types is not supported. */
5826 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
5827 rte_free(cld_filter);
5831 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
5834 rte_free(cld_filter);
5838 pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
5839 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
5840 pfilter->tenant_id = tunnel_filter->tenant_id;
5841 pfilter->queue_number = tunnel_filter->queue_id;
5844 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
5846 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
5849 rte_free(cld_filter);
5854 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
5858 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5859 if (pf->vxlan_ports[i] == port)
5867 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
5871 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5873 idx = i40e_get_vxlan_port_idx(pf, port);
5875 /* Check if port already exists */
5877 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
5881 /* Now check if there is space to add the new port */
5882 idx = i40e_get_vxlan_port_idx(pf, 0);
5884 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
5885 "not adding port %d", port);
5889 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
5892 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
5896 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
5899 /* New port: add it and mark its index in the bitmap */
5900 pf->vxlan_ports[idx] = port;
5901 pf->vxlan_bitmap |= (1 << idx);
5903 if (!(pf->flags & I40E_FLAG_VXLAN))
5904 pf->flags |= I40E_FLAG_VXLAN;
5910 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
5913 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5915 if (!(pf->flags & I40E_FLAG_VXLAN)) {
5916 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
5920 idx = i40e_get_vxlan_port_idx(pf, port);
5923 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
5927 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
5928 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
5932 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
5935 pf->vxlan_ports[idx] = 0;
5936 pf->vxlan_bitmap &= ~(1 << idx);
5938 if (!pf->vxlan_bitmap)
5939 pf->flags &= ~I40E_FLAG_VXLAN;
5944 /* Add UDP tunneling port */
5946 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
5947 struct rte_eth_udp_tunnel *udp_tunnel)
5950 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5952 if (udp_tunnel == NULL)
5955 switch (udp_tunnel->prot_type) {
5956 case RTE_TUNNEL_TYPE_VXLAN:
5957 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
5960 case RTE_TUNNEL_TYPE_GENEVE:
5961 case RTE_TUNNEL_TYPE_TEREDO:
5962 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
5967 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5975 /* Remove UDP tunneling port */
5977 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
5978 struct rte_eth_udp_tunnel *udp_tunnel)
5981 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5983 if (udp_tunnel == NULL)
5986 switch (udp_tunnel->prot_type) {
5987 case RTE_TUNNEL_TYPE_VXLAN:
5988 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
5990 case RTE_TUNNEL_TYPE_GENEVE:
5991 case RTE_TUNNEL_TYPE_TEREDO:
5992 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
5996 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6004 /* Calculate the maximum number of contiguous PF queues that are configured */
6006 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6008 struct rte_eth_dev_data *data = pf->dev_data;
6010 struct i40e_rx_queue *rxq;
6013 for (i = 0; i < pf->lan_nb_qps; i++) {
6014 rxq = data->rx_queues[i];
6015 if (rxq && rxq->q_set)
6026 i40e_pf_config_rss(struct i40e_pf *pf)
6028 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6029 struct rte_eth_rss_conf rss_conf;
6030 uint32_t i, lut = 0;
6034 * If both VMDQ and RSS enabled, not all of PF queues are configured.
6035 * It's necessary to calulate the actual PF queues that are configured.
6037 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6038 num = i40e_pf_calc_configured_queues_num(pf);
6040 num = pf->dev_data->nb_rx_queues;
6042 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6043 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6047 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6051 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6054 lut = (lut << 8) | (j & ((0x1 <<
6055 hw->func_caps.rss_table_entry_width) - 1));
6057 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6060 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6061 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6062 i40e_pf_disable_rss(pf);
6065 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6066 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6067 /* Random default keys */
6068 static uint32_t rss_key_default[] = {0x6b793944,
6069 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6070 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6071 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6073 rss_conf.rss_key = (uint8_t *)rss_key_default;
6074 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6078 return i40e_hw_rss_hash_set(pf, &rss_conf);
6082 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6083 struct rte_eth_tunnel_filter_conf *filter)
6085 if (pf == NULL || filter == NULL) {
6086 PMD_DRV_LOG(ERR, "Invalid parameter");
6090 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6091 PMD_DRV_LOG(ERR, "Invalid queue ID");
6095 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6096 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6100 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6101 (is_zero_ether_addr(filter->outer_mac))) {
6102 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6106 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6107 (is_zero_ether_addr(filter->inner_mac))) {
6108 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6115 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6116 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
6118 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6123 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6124 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6127 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6128 } else if (len == 4) {
6129 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6131 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6136 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6143 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6144 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6150 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6157 switch (cfg->cfg_type) {
6158 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6159 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6162 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6170 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6171 enum rte_filter_op filter_op,
6174 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6175 int ret = I40E_ERR_PARAM;
6177 switch (filter_op) {
6178 case RTE_ETH_FILTER_SET:
6179 ret = i40e_dev_global_config_set(hw,
6180 (struct rte_eth_global_cfg *)arg);
6183 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6191 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6192 enum rte_filter_op filter_op,
6195 struct rte_eth_tunnel_filter_conf *filter;
6196 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6197 int ret = I40E_SUCCESS;
6199 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6201 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6202 return I40E_ERR_PARAM;
6204 switch (filter_op) {
6205 case RTE_ETH_FILTER_NOP:
6206 if (!(pf->flags & I40E_FLAG_VXLAN))
6207 ret = I40E_NOT_SUPPORTED;
6209 case RTE_ETH_FILTER_ADD:
6210 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6212 case RTE_ETH_FILTER_DELETE:
6213 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6216 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6217 ret = I40E_ERR_PARAM;
6225 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6228 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6231 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6232 ret = i40e_pf_config_rss(pf);
6234 i40e_pf_disable_rss(pf);
6239 /* Get the symmetric hash enable configurations per port */
6241 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6243 uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
6245 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6248 /* Set the symmetric hash enable configurations per port */
6250 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6252 uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
6255 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6256 PMD_DRV_LOG(INFO, "Symmetric hash has already "
6260 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6262 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6263 PMD_DRV_LOG(INFO, "Symmetric hash has already "
6267 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6269 I40E_WRITE_REG(hw, I40E_PRTQF_CTL_0, reg);
6270 I40E_WRITE_FLUSH(hw);
6274 * Get global configurations of hash function type and symmetric hash enable
6275 * per flow type (pctype). Note that global configuration means it affects all
6276 * the ports on the same NIC.
6279 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6280 struct rte_eth_hash_global_conf *g_cfg)
6282 uint32_t reg, mask = I40E_FLOW_TYPES;
6284 enum i40e_filter_pctype pctype;
6286 memset(g_cfg, 0, sizeof(*g_cfg));
6287 reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
6288 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6289 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6291 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6292 PMD_DRV_LOG(DEBUG, "Hash function is %s",
6293 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6295 for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6296 if (!(mask & (1UL << i)))
6298 mask &= ~(1UL << i);
6299 /* Bit set indicats the coresponding flow type is supported */
6300 g_cfg->valid_bit_mask[0] |= (1UL << i);
6301 pctype = i40e_flowtype_to_pctype(i);
6302 reg = I40E_READ_REG(hw, I40E_GLQF_HSYM(pctype));
6303 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6304 g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6311 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6314 uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6316 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
6317 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
6318 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
6319 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
6325 * As i40e supports less than 32 flow types, only first 32 bits need to
6328 mask0 = g_cfg->valid_bit_mask[0];
6329 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
6331 /* Check if any unsupported flow type configured */
6332 if ((mask0 | i40e_mask) ^ i40e_mask)
6335 if (g_cfg->valid_bit_mask[i])
6343 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
6349 * Set global configurations of hash function type and symmetric hash enable
6350 * per flow type (pctype). Note any modifying global configuration will affect
6351 * all the ports on the same NIC.
6354 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
6355 struct rte_eth_hash_global_conf *g_cfg)
6360 uint32_t mask0 = g_cfg->valid_bit_mask[0];
6361 enum i40e_filter_pctype pctype;
6363 /* Check the input parameters */
6364 ret = i40e_hash_global_config_check(g_cfg);
6368 for (i = 0; mask0 && i < UINT32_BIT; i++) {
6369 if (!(mask0 & (1UL << i)))
6371 mask0 &= ~(1UL << i);
6372 pctype = i40e_flowtype_to_pctype(i);
6373 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
6374 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
6375 I40E_WRITE_REG(hw, I40E_GLQF_HSYM(pctype), reg);
6378 reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
6379 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
6381 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
6382 PMD_DRV_LOG(DEBUG, "Hash function already set to "
6386 reg |= I40E_GLQF_CTL_HTOEP_MASK;
6387 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
6389 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
6390 PMD_DRV_LOG(DEBUG, "Hash function already set to "
6394 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
6396 /* Use the default, and keep it as it is */
6399 I40E_WRITE_REG(hw, I40E_GLQF_CTL, reg);
6402 I40E_WRITE_FLUSH(hw);
6408 * Valid input sets for hash and flow director filters per PCTYPE
6411 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
6412 enum rte_filter_type filter)
6416 static const uint64_t valid_hash_inset_table[] = {
6417 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6418 I40E_INSET_DMAC | I40E_INSET_SMAC |
6419 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6420 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
6421 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
6422 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6423 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6424 I40E_INSET_FLEX_PAYLOAD,
6425 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6426 I40E_INSET_DMAC | I40E_INSET_SMAC |
6427 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6428 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6429 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6430 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6431 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6432 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6433 I40E_INSET_FLEX_PAYLOAD,
6434 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6435 I40E_INSET_DMAC | I40E_INSET_SMAC |
6436 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6437 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6438 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6439 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6440 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6441 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6442 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
6443 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6444 I40E_INSET_DMAC | I40E_INSET_SMAC |
6445 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6446 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6447 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6448 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6449 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6450 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6451 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6452 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6453 I40E_INSET_DMAC | I40E_INSET_SMAC |
6454 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6455 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6456 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6457 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6458 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6459 I40E_INSET_FLEX_PAYLOAD,
6460 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6461 I40E_INSET_DMAC | I40E_INSET_SMAC |
6462 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6463 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6464 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6465 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
6466 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
6467 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
6468 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6469 I40E_INSET_DMAC | I40E_INSET_SMAC |
6470 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6471 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6472 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6473 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6474 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6475 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
6476 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6477 I40E_INSET_DMAC | I40E_INSET_SMAC |
6478 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6479 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6480 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6481 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6482 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6483 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
6484 I40E_INSET_FLEX_PAYLOAD,
6485 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6486 I40E_INSET_DMAC | I40E_INSET_SMAC |
6487 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6488 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6489 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6490 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6491 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6492 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
6493 I40E_INSET_FLEX_PAYLOAD,
6494 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6495 I40E_INSET_DMAC | I40E_INSET_SMAC |
6496 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6497 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6498 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6499 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6500 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
6501 I40E_INSET_FLEX_PAYLOAD,
6502 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6503 I40E_INSET_DMAC | I40E_INSET_SMAC |
6504 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6505 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
6506 I40E_INSET_FLEX_PAYLOAD,
6510 * Flow director supports only fields defined in
6511 * union rte_eth_fdir_flow.
6513 static const uint64_t valid_fdir_inset_table[] = {
6514 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6515 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6516 I40E_INSET_FLEX_PAYLOAD,
6517 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6518 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6519 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6520 I40E_INSET_FLEX_PAYLOAD,
6521 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6522 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6523 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6524 I40E_INSET_FLEX_PAYLOAD,
6525 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6526 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6527 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6528 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6529 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6530 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6531 I40E_INSET_FLEX_PAYLOAD,
6532 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6533 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6534 I40E_INSET_FLEX_PAYLOAD,
6535 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6536 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6537 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6538 I40E_INSET_FLEX_PAYLOAD,
6539 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6540 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6541 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6542 I40E_INSET_FLEX_PAYLOAD,
6543 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6544 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6545 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6546 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6547 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6548 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6549 I40E_INSET_FLEX_PAYLOAD,
6550 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6551 I40E_INSET_LAST_ETHER_TYPE | I40E_INSET_FLEX_PAYLOAD,
6554 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6556 if (filter == RTE_ETH_FILTER_HASH)
6557 valid = valid_hash_inset_table[pctype];
6559 valid = valid_fdir_inset_table[pctype];
6565 * Validate if the input set is allowed for a specific PCTYPE
6568 i40e_validate_input_set(enum i40e_filter_pctype pctype,
6569 enum rte_filter_type filter, uint64_t inset)
6573 valid = i40e_get_valid_input_set(pctype, filter);
6574 if (inset & (~valid))
6580 /* default input set fields combination per pctype */
6582 i40e_get_default_input_set(uint16_t pctype)
6584 static const uint64_t default_inset_table[] = {
6585 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6586 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6587 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6588 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6589 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6590 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6591 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6592 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6593 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6594 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6595 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6597 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6598 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6599 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6600 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6601 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6602 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6603 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6604 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6605 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6606 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6607 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6608 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6609 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6611 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6612 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6613 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6614 I40E_INSET_LAST_ETHER_TYPE,
6617 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6620 return default_inset_table[pctype];
6624 * Parse the input set from index to logical bit masks
6627 i40e_parse_input_set(uint64_t *inset,
6628 enum i40e_filter_pctype pctype,
6629 enum rte_eth_input_set_field *field,
6635 static const struct {
6636 enum rte_eth_input_set_field field;
6638 } inset_convert_table[] = {
6639 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
6640 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
6641 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
6642 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
6643 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
6644 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
6645 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
6646 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
6647 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
6648 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
6649 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
6650 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
6651 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
6652 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
6653 I40E_INSET_IPV6_NEXT_HDR},
6654 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
6655 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
6656 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
6657 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
6658 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
6659 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
6660 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
6661 I40E_INSET_SCTP_VT},
6662 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
6663 I40E_INSET_TUNNEL_DMAC},
6664 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
6665 I40E_INSET_VLAN_TUNNEL},
6666 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
6667 I40E_INSET_TUNNEL_ID},
6668 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
6669 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
6670 I40E_INSET_FLEX_PAYLOAD_W1},
6671 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
6672 I40E_INSET_FLEX_PAYLOAD_W2},
6673 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
6674 I40E_INSET_FLEX_PAYLOAD_W3},
6675 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
6676 I40E_INSET_FLEX_PAYLOAD_W4},
6677 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
6678 I40E_INSET_FLEX_PAYLOAD_W5},
6679 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
6680 I40E_INSET_FLEX_PAYLOAD_W6},
6681 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
6682 I40E_INSET_FLEX_PAYLOAD_W7},
6683 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
6684 I40E_INSET_FLEX_PAYLOAD_W8},
6687 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
6690 /* Only one item allowed for default or all */
6692 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
6693 *inset = i40e_get_default_input_set(pctype);
6695 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
6696 *inset = I40E_INSET_NONE;
6701 for (i = 0, *inset = 0; i < size; i++) {
6702 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
6703 if (field[i] == inset_convert_table[j].field) {
6704 *inset |= inset_convert_table[j].inset;
6709 /* It contains unsupported input set, return immediately */
6710 if (j == RTE_DIM(inset_convert_table))
6718 * Translate the input set from bit masks to register aware bit masks
6722 i40e_translate_input_set_reg(uint64_t input)
6727 static const struct {
6731 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
6732 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
6733 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
6734 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
6735 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
6736 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
6737 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
6738 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
6739 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
6740 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
6741 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
6742 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
6743 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
6744 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
6745 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
6746 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
6747 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
6748 {I40E_INSET_TUNNEL_DMAC,
6749 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
6750 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
6751 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
6752 {I40E_INSET_TUNNEL_SRC_PORT,
6753 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
6754 {I40E_INSET_TUNNEL_DST_PORT,
6755 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
6756 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
6757 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
6758 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
6759 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
6760 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
6761 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
6762 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
6763 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
6764 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
6770 /* Translate input set to register aware inset */
6771 for (i = 0; i < RTE_DIM(inset_map); i++) {
6772 if (input & inset_map[i].inset)
6773 val |= inset_map[i].inset_reg;
6780 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
6784 static const struct {
6787 } inset_mask_map[] = {
6788 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
6789 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
6790 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
6791 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
6794 if (!inset || !mask || !nb_elem)
6797 if (!inset && nb_elem >= I40E_INSET_MASK_NUM_REG) {
6798 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++)
6800 return I40E_INSET_MASK_NUM_REG;
6803 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
6806 if (inset & inset_mask_map[i].inset) {
6807 mask[idx] = inset_mask_map[i].mask;
6816 i40e_get_reg_inset(struct i40e_hw *hw, enum rte_filter_type filter,
6817 enum i40e_filter_pctype pctype)
6821 if (filter == RTE_ETH_FILTER_HASH) {
6822 reg = I40E_READ_REG(hw, I40E_GLQF_HASH_INSET(1, pctype));
6823 reg <<= I40E_32_BIT_WIDTH;
6824 reg |= I40E_READ_REG(hw, I40E_GLQF_HASH_INSET(0, pctype));
6825 } else if (filter == RTE_ETH_FILTER_FDIR) {
6826 reg = I40E_READ_REG(hw, I40E_PRTQF_FD_INSET(pctype, 1));
6827 reg <<= I40E_32_BIT_WIDTH;
6828 reg |= I40E_READ_REG(hw, I40E_PRTQF_FD_INSET(pctype, 0));
6835 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
6837 uint32_t reg = I40E_READ_REG(hw, addr);
6839 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
6841 I40E_WRITE_REG(hw, addr, val);
6842 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
6843 (uint32_t)I40E_READ_REG(hw, addr));
6847 i40e_set_hash_inset_mask(struct i40e_hw *hw,
6848 enum i40e_filter_pctype pctype,
6849 enum rte_filter_input_set_op op,
6856 if (!mask_reg || num > RTE_ETH_INPUT_SET_SELECT)
6859 if (op == RTE_ETH_INPUT_SET_SELECT) {
6860 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6861 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
6865 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
6868 } else if (op == RTE_ETH_INPUT_SET_ADD) {
6869 uint8_t j, count = 0;
6871 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6872 reg = I40E_READ_REG(hw, I40E_GLQF_HASH_MSK(i, pctype));
6873 if (reg & I40E_GLQF_HASH_MSK_FIELD)
6876 if (count + num > I40E_INSET_MASK_NUM_REG)
6879 for (i = count, j = 0; i < I40E_INSET_MASK_NUM_REG; i++, j++)
6880 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
6888 i40e_set_fd_inset_mask(struct i40e_hw *hw,
6889 enum i40e_filter_pctype pctype,
6890 enum rte_filter_input_set_op op,
6897 if (!mask_reg || num > RTE_ETH_INPUT_SET_SELECT)
6900 if (op == RTE_ETH_INPUT_SET_SELECT) {
6901 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6902 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
6906 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
6909 } else if (op == RTE_ETH_INPUT_SET_ADD) {
6910 uint8_t j, count = 0;
6912 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6913 reg = I40E_READ_REG(hw, I40E_GLQF_FD_MSK(i, pctype));
6914 if (reg & I40E_GLQF_FD_MSK_FIELD)
6917 if (count + num > I40E_INSET_MASK_NUM_REG)
6920 for (i = count, j = 0; i < I40E_INSET_MASK_NUM_REG; i++, j++)
6921 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
6929 i40e_filter_inset_select(struct i40e_hw *hw,
6930 struct rte_eth_input_set_conf *conf,
6931 enum rte_filter_type filter)
6933 enum i40e_filter_pctype pctype;
6934 uint64_t inset_reg = 0, input_set;
6935 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG];
6940 PMD_DRV_LOG(ERR, "Invalid pointer");
6944 pctype = i40e_flowtype_to_pctype(conf->flow_type);
6945 if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
6946 PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
6950 if (filter != RTE_ETH_FILTER_HASH && filter != RTE_ETH_FILTER_FDIR) {
6951 PMD_DRV_LOG(ERR, "Not supported filter type (%u)", filter);
6955 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
6958 PMD_DRV_LOG(ERR, "Failed to parse input set");
6961 if (i40e_validate_input_set(pctype, filter, input_set) != 0) {
6962 PMD_DRV_LOG(ERR, "Invalid input set");
6966 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
6967 inset_reg |= i40e_get_reg_inset(hw, filter, pctype);
6968 } else if (conf->op != RTE_ETH_INPUT_SET_SELECT) {
6969 PMD_DRV_LOG(ERR, "Unsupported input set operation");
6972 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
6973 I40E_INSET_MASK_NUM_REG);
6974 inset_reg |= i40e_translate_input_set_reg(input_set);
6976 if (filter == RTE_ETH_FILTER_HASH) {
6977 ret = i40e_set_hash_inset_mask(hw, pctype, conf->op, mask_reg,
6982 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
6983 (uint32_t)(inset_reg & UINT32_MAX));
6984 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
6985 (uint32_t)((inset_reg >>
6986 I40E_32_BIT_WIDTH) & UINT32_MAX));
6987 } else if (filter == RTE_ETH_FILTER_FDIR) {
6988 ret = i40e_set_fd_inset_mask(hw, pctype, conf->op, mask_reg,
6993 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
6994 (uint32_t)(inset_reg & UINT32_MAX));
6995 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
6996 (uint32_t)((inset_reg >>
6997 I40E_32_BIT_WIDTH) & UINT32_MAX));
6999 PMD_DRV_LOG(ERR, "Not supported filter type (%u)", filter);
7002 I40E_WRITE_FLUSH(hw);
7008 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7013 PMD_DRV_LOG(ERR, "Invalid pointer");
7017 switch (info->info_type) {
7018 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7019 i40e_get_symmetric_hash_enable_per_port(hw,
7020 &(info->info.enable));
7022 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7023 ret = i40e_get_hash_filter_global_config(hw,
7024 &(info->info.global_conf));
7027 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7037 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7042 PMD_DRV_LOG(ERR, "Invalid pointer");
7046 switch (info->info_type) {
7047 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7048 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7050 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7051 ret = i40e_set_hash_filter_global_config(hw,
7052 &(info->info.global_conf));
7054 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7055 ret = i40e_filter_inset_select(hw,
7056 &(info->info.input_set_conf),
7057 RTE_ETH_FILTER_HASH);
7061 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7070 /* Operations for hash function */
7072 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7073 enum rte_filter_op filter_op,
7076 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7079 switch (filter_op) {
7080 case RTE_ETH_FILTER_NOP:
7082 case RTE_ETH_FILTER_GET:
7083 ret = i40e_hash_filter_get(hw,
7084 (struct rte_eth_hash_filter_info *)arg);
7086 case RTE_ETH_FILTER_SET:
7087 ret = i40e_hash_filter_set(hw,
7088 (struct rte_eth_hash_filter_info *)arg);
7091 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
7101 * Configure ethertype filter, which can director packet by filtering
7102 * with mac address and ether_type or only ether_type
7105 i40e_ethertype_filter_set(struct i40e_pf *pf,
7106 struct rte_eth_ethertype_filter *filter,
7109 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7110 struct i40e_control_filter_stats stats;
7114 if (filter->queue >= pf->dev_data->nb_rx_queues) {
7115 PMD_DRV_LOG(ERR, "Invalid queue ID");
7118 if (filter->ether_type == ETHER_TYPE_IPv4 ||
7119 filter->ether_type == ETHER_TYPE_IPv6) {
7120 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
7121 " control packet filter.", filter->ether_type);
7124 if (filter->ether_type == ETHER_TYPE_VLAN)
7125 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
7128 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
7129 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
7130 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
7131 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
7132 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
7134 memset(&stats, 0, sizeof(stats));
7135 ret = i40e_aq_add_rem_control_packet_filter(hw,
7136 filter->mac_addr.addr_bytes,
7137 filter->ether_type, flags,
7139 filter->queue, add, &stats, NULL);
7141 PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
7142 " mac_etype_used = %u, etype_used = %u,"
7143 " mac_etype_free = %u, etype_free = %u\n",
7144 ret, stats.mac_etype_used, stats.etype_used,
7145 stats.mac_etype_free, stats.etype_free);
7152 * Handle operations for ethertype filter.
7155 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
7156 enum rte_filter_op filter_op,
7159 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7162 if (filter_op == RTE_ETH_FILTER_NOP)
7166 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
7171 switch (filter_op) {
7172 case RTE_ETH_FILTER_ADD:
7173 ret = i40e_ethertype_filter_set(pf,
7174 (struct rte_eth_ethertype_filter *)arg,
7177 case RTE_ETH_FILTER_DELETE:
7178 ret = i40e_ethertype_filter_set(pf,
7179 (struct rte_eth_ethertype_filter *)arg,
7183 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
7191 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
7192 enum rte_filter_type filter_type,
7193 enum rte_filter_op filter_op,
7201 switch (filter_type) {
7202 case RTE_ETH_FILTER_NONE:
7203 /* For global configuration */
7204 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
7206 case RTE_ETH_FILTER_HASH:
7207 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
7209 case RTE_ETH_FILTER_MACVLAN:
7210 ret = i40e_mac_filter_handle(dev, filter_op, arg);
7212 case RTE_ETH_FILTER_ETHERTYPE:
7213 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
7215 case RTE_ETH_FILTER_TUNNEL:
7216 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
7218 case RTE_ETH_FILTER_FDIR:
7219 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
7222 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7232 * As some registers wouldn't be reset unless a global hardware reset,
7233 * hardware initialization is needed to put those registers into an
7234 * expected initial state.
7237 i40e_hw_init(struct i40e_hw *hw)
7239 /* clear the PF Queue Filter control register */
7240 I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0);
7242 /* Disable symmetric hash per port */
7243 i40e_set_symmetric_hash_enable_per_port(hw, 0);
7246 enum i40e_filter_pctype
7247 i40e_flowtype_to_pctype(uint16_t flow_type)
7249 static const enum i40e_filter_pctype pctype_table[] = {
7250 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
7251 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
7252 I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
7253 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
7254 I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
7255 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
7256 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
7257 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
7258 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
7259 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
7260 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
7261 I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
7262 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
7263 I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
7264 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
7265 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
7266 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
7267 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
7268 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
7271 return pctype_table[flow_type];
7275 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
7277 static const uint16_t flowtype_table[] = {
7278 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
7279 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7280 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
7281 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7282 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
7283 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7284 RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
7285 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7286 RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
7287 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
7288 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7289 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
7290 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7291 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
7292 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7293 RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
7294 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7295 RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
7296 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
7299 return flowtype_table[pctype];
7303 * On X710, performance number is far from the expectation on recent firmware
7304 * versions; on XL710, performance number is also far from the expectation on
7305 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
7306 * mode is enabled and port MAC address is equal to the packet destination MAC
7307 * address. The fix for this issue may not be integrated in the following
7308 * firmware version. So the workaround in software driver is needed. It needs
7309 * to modify the initial values of 3 internal only registers for both X710 and
7310 * XL710. Note that the values for X710 or XL710 could be different, and the
7311 * workaround can be removed when it is fixed in firmware in the future.
7314 /* For both X710 and XL710 */
7315 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
7316 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
7318 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
7319 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
7322 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
7324 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
7325 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
7328 i40e_configure_registers(struct i40e_hw *hw)
7334 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
7335 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
7336 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
7342 for (i = 0; i < RTE_DIM(reg_table); i++) {
7343 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
7344 if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
7346 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
7349 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
7352 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
7355 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
7359 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
7360 reg_table[i].addr, reg);
7361 if (reg == reg_table[i].val)
7364 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
7365 reg_table[i].val, NULL);
7367 PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
7368 "address of 0x%"PRIx32, reg_table[i].val,
7372 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
7373 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
7377 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
7378 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
7379 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
7380 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
7382 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
7387 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
7388 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
7392 /* Configure for double VLAN RX stripping */
7393 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
7394 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
7395 reg |= I40E_VSI_TSR_QINQ_CONFIG;
7396 ret = i40e_aq_debug_write_register(hw,
7397 I40E_VSI_TSR(vsi->vsi_id),
7400 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
7402 return I40E_ERR_CONFIG;
7406 /* Configure for double VLAN TX insertion */
7407 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
7408 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
7409 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
7410 ret = i40e_aq_debug_write_register(hw,
7411 I40E_VSI_L2TAGSTXVALID(
7412 vsi->vsi_id), reg, NULL);
7414 PMD_DRV_LOG(ERR, "Failed to update "
7415 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
7416 return I40E_ERR_CONFIG;
7424 * i40e_aq_add_mirror_rule
7425 * @hw: pointer to the hardware structure
7426 * @seid: VEB seid to add mirror rule to
7427 * @dst_id: destination vsi seid
7428 * @entries: Buffer which contains the entities to be mirrored
7429 * @count: number of entities contained in the buffer
7430 * @rule_id:the rule_id of the rule to be added
7432 * Add a mirror rule for a given veb.
7435 static enum i40e_status_code
7436 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
7437 uint16_t seid, uint16_t dst_id,
7438 uint16_t rule_type, uint16_t *entries,
7439 uint16_t count, uint16_t *rule_id)
7441 struct i40e_aq_desc desc;
7442 struct i40e_aqc_add_delete_mirror_rule cmd;
7443 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
7444 (struct i40e_aqc_add_delete_mirror_rule_completion *)
7447 enum i40e_status_code status;
7449 i40e_fill_default_direct_cmd_desc(&desc,
7450 i40e_aqc_opc_add_mirror_rule);
7451 memset(&cmd, 0, sizeof(cmd));
7453 buff_len = sizeof(uint16_t) * count;
7454 desc.datalen = rte_cpu_to_le_16(buff_len);
7456 desc.flags |= rte_cpu_to_le_16(
7457 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
7458 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7459 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7460 cmd.num_entries = rte_cpu_to_le_16(count);
7461 cmd.seid = rte_cpu_to_le_16(seid);
7462 cmd.destination = rte_cpu_to_le_16(dst_id);
7464 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7465 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
7466 PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
7468 " mirror_rules_used = %u, mirror_rules_free = %u,",
7469 hw->aq.asq_last_status, resp->rule_id,
7470 resp->mirror_rules_used, resp->mirror_rules_free);
7471 *rule_id = rte_le_to_cpu_16(resp->rule_id);
7477 * i40e_aq_del_mirror_rule
7478 * @hw: pointer to the hardware structure
7479 * @seid: VEB seid to add mirror rule to
7480 * @entries: Buffer which contains the entities to be mirrored
7481 * @count: number of entities contained in the buffer
7482 * @rule_id:the rule_id of the rule to be delete
7484 * Delete a mirror rule for a given veb.
7487 static enum i40e_status_code
7488 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
7489 uint16_t seid, uint16_t rule_type, uint16_t *entries,
7490 uint16_t count, uint16_t rule_id)
7492 struct i40e_aq_desc desc;
7493 struct i40e_aqc_add_delete_mirror_rule cmd;
7494 uint16_t buff_len = 0;
7495 enum i40e_status_code status;
7498 i40e_fill_default_direct_cmd_desc(&desc,
7499 i40e_aqc_opc_delete_mirror_rule);
7500 memset(&cmd, 0, sizeof(cmd));
7501 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
7502 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
7504 cmd.num_entries = count;
7505 buff_len = sizeof(uint16_t) * count;
7506 desc.datalen = rte_cpu_to_le_16(buff_len);
7507 buff = (void *)entries;
7509 /* rule id is filled in destination field for deleting mirror rule */
7510 cmd.destination = rte_cpu_to_le_16(rule_id);
7512 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7513 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7514 cmd.seid = rte_cpu_to_le_16(seid);
7516 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7517 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
7523 * i40e_mirror_rule_set
7524 * @dev: pointer to the hardware structure
7525 * @mirror_conf: mirror rule info
7526 * @sw_id: mirror rule's sw_id
7527 * @on: enable/disable
7529 * set a mirror rule.
7533 i40e_mirror_rule_set(struct rte_eth_dev *dev,
7534 struct rte_eth_mirror_conf *mirror_conf,
7535 uint8_t sw_id, uint8_t on)
7537 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7538 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7539 struct i40e_mirror_rule *it, *mirr_rule = NULL;
7540 struct i40e_mirror_rule *parent = NULL;
7541 uint16_t seid, dst_seid, rule_id;
7545 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
7547 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
7548 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
7549 " without veb or vfs.");
7552 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
7553 PMD_DRV_LOG(ERR, "mirror table is full.");
7556 if (mirror_conf->dst_pool > pf->vf_num) {
7557 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
7558 mirror_conf->dst_pool);
7562 seid = pf->main_vsi->veb->seid;
7564 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
7565 if (sw_id <= it->index) {
7571 if (mirr_rule && sw_id == mirr_rule->index) {
7573 PMD_DRV_LOG(ERR, "mirror rule exists.");
7576 ret = i40e_aq_del_mirror_rule(hw, seid,
7577 mirr_rule->rule_type,
7579 mirr_rule->num_entries, mirr_rule->id);
7581 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
7582 " ret = %d, aq_err = %d.",
7583 ret, hw->aq.asq_last_status);
7586 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
7587 rte_free(mirr_rule);
7588 pf->nb_mirror_rule--;
7592 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
7596 mirr_rule = rte_zmalloc("i40e_mirror_rule",
7597 sizeof(struct i40e_mirror_rule) , 0);
7599 PMD_DRV_LOG(ERR, "failed to allocate memory");
7600 return I40E_ERR_NO_MEMORY;
7602 switch (mirror_conf->rule_type) {
7603 case ETH_MIRROR_VLAN:
7604 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
7605 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
7606 mirr_rule->entries[j] =
7607 mirror_conf->vlan.vlan_id[i];
7612 PMD_DRV_LOG(ERR, "vlan is not specified.");
7613 rte_free(mirr_rule);
7616 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
7618 case ETH_MIRROR_VIRTUAL_POOL_UP:
7619 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
7620 /* check if the specified pool bit is out of range */
7621 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
7622 PMD_DRV_LOG(ERR, "pool mask is out of range.");
7623 rte_free(mirr_rule);
7626 for (i = 0, j = 0; i < pf->vf_num; i++) {
7627 if (mirror_conf->pool_mask & (1ULL << i)) {
7628 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
7632 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
7633 /* add pf vsi to entries */
7634 mirr_rule->entries[j] = pf->main_vsi_seid;
7638 PMD_DRV_LOG(ERR, "pool is not specified.");
7639 rte_free(mirr_rule);
7642 /* egress and ingress in aq commands means from switch but not port */
7643 mirr_rule->rule_type =
7644 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
7645 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
7646 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
7648 case ETH_MIRROR_UPLINK_PORT:
7649 /* egress and ingress in aq commands means from switch but not port*/
7650 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
7652 case ETH_MIRROR_DOWNLINK_PORT:
7653 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
7656 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
7657 mirror_conf->rule_type);
7658 rte_free(mirr_rule);
7662 /* If the dst_pool is equal to vf_num, consider it as PF */
7663 if (mirror_conf->dst_pool == pf->vf_num)
7664 dst_seid = pf->main_vsi_seid;
7666 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
7668 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
7669 mirr_rule->rule_type, mirr_rule->entries,
7672 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
7673 " ret = %d, aq_err = %d.",
7674 ret, hw->aq.asq_last_status);
7675 rte_free(mirr_rule);
7679 mirr_rule->index = sw_id;
7680 mirr_rule->num_entries = j;
7681 mirr_rule->id = rule_id;
7682 mirr_rule->dst_vsi_seid = dst_seid;
7685 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
7687 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
7689 pf->nb_mirror_rule++;
7694 * i40e_mirror_rule_reset
7695 * @dev: pointer to the device
7696 * @sw_id: mirror rule's sw_id
7698 * reset a mirror rule.
7702 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
7704 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7705 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7706 struct i40e_mirror_rule *it, *mirr_rule = NULL;
7710 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
7712 seid = pf->main_vsi->veb->seid;
7714 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
7715 if (sw_id == it->index) {
7721 ret = i40e_aq_del_mirror_rule(hw, seid,
7722 mirr_rule->rule_type,
7724 mirr_rule->num_entries, mirr_rule->id);
7726 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
7727 " status = %d, aq_err = %d.",
7728 ret, hw->aq.asq_last_status);
7731 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
7732 rte_free(mirr_rule);
7733 pf->nb_mirror_rule--;
7735 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
7742 i40e_timesync_enable(struct rte_eth_dev *dev)
7744 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7745 struct rte_eth_link *link = &dev->data->dev_link;
7746 uint32_t tsync_ctl_l;
7747 uint32_t tsync_ctl_h;
7748 uint32_t tsync_inc_l;
7749 uint32_t tsync_inc_h;
7751 switch (link->link_speed) {
7752 case ETH_LINK_SPEED_40G:
7753 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
7754 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
7756 case ETH_LINK_SPEED_10G:
7757 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
7758 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
7760 case ETH_LINK_SPEED_1000:
7761 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
7762 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
7769 /* Clear timesync registers. */
7770 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
7771 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
7772 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(0));
7773 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(1));
7774 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(2));
7775 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(3));
7776 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
7778 /* Set the timesync increment value. */
7779 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
7780 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
7782 /* Enable timestamping of PTP packets. */
7783 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
7784 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
7786 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
7787 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
7788 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
7790 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
7791 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
7797 i40e_timesync_disable(struct rte_eth_dev *dev)
7799 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7800 uint32_t tsync_ctl_l;
7801 uint32_t tsync_ctl_h;
7803 /* Disable timestamping of transmitted PTP packets. */
7804 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
7805 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
7807 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
7808 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
7810 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
7811 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
7813 /* Set the timesync increment value. */
7814 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
7815 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
7821 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7822 struct timespec *timestamp, uint32_t flags)
7824 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7825 uint32_t sync_status;
7828 uint32_t index = flags & 0x03;
7830 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
7831 if ((sync_status & (1 << index)) == 0)
7834 rx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
7835 rx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index));
7837 timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
7838 timestamp->tv_nsec = 0;
7844 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7845 struct timespec *timestamp)
7847 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7848 uint32_t sync_status;
7852 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
7853 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
7856 tx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
7857 tx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
7859 timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
7860 timestamp->tv_nsec = 0;
7866 * i40e_parse_dcb_configure - parse dcb configure from user
7867 * @dev: the device being configured
7868 * @dcb_cfg: pointer of the result of parse
7869 * @*tc_map: bit map of enabled traffic classes
7871 * Returns 0 on success, negative value on failure
7874 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
7875 struct i40e_dcbx_config *dcb_cfg,
7878 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
7879 uint8_t i, tc_bw, bw_lf;
7881 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
7883 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7884 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
7885 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
7889 /* assume each tc has the same bw */
7890 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
7891 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
7892 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
7893 /* to ensure the sum of tcbw is equal to 100 */
7894 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
7895 for (i = 0; i < bw_lf; i++)
7896 dcb_cfg->etscfg.tcbwtable[i]++;
7898 /* assume each tc has the same Transmission Selection Algorithm */
7899 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
7900 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
7902 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
7903 dcb_cfg->etscfg.prioritytable[i] =
7904 dcb_rx_conf->dcb_tc[i];
7906 /* FW needs one App to configure HW */
7907 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
7908 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
7909 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
7910 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
7912 if (dcb_rx_conf->nb_tcs == 0)
7913 *tc_map = 1; /* tc0 only */
7915 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
7917 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
7918 dcb_cfg->pfc.willing = 0;
7919 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
7920 dcb_cfg->pfc.pfcenable = *tc_map;
7926 * i40e_vsi_get_bw_info - Query VSI BW Information
7927 * @vsi: the VSI being queried
7929 * Returns 0 on success, negative value on failure
7932 i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
7934 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
7935 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
7936 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7940 /* Get the VSI level BW configuration */
7941 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
7944 "couldn't get PF vsi bw config, err %s aq_err %s\n",
7945 i40e_stat_str(hw, ret),
7946 i40e_aq_str(hw, hw->aq.asq_last_status));
7950 /* Get the VSI level BW configuration per TC */
7951 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
7955 "couldn't get PF vsi ets bw config, err %s aq_err %s\n",
7956 i40e_stat_str(hw, ret),
7957 i40e_aq_str(hw, hw->aq.asq_last_status));
7961 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
7962 PMD_INIT_LOG(WARNING,
7963 "Enabled TCs mismatch from querying VSI BW info"
7964 " 0x%08x 0x%08x\n", bw_config.tc_valid_bits,
7965 bw_ets_config.tc_valid_bits);
7966 /* Still continuing */
7969 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
7970 vsi->bw_info.bw_max_quanta = bw_config.max_bw;
7971 tc_bw_max = rte_le_to_cpu_16(bw_ets_config.tc_bw_max[0]) |
7972 (rte_le_to_cpu_16(bw_ets_config.tc_bw_max[1]) << 16);
7973 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
7974 vsi->bw_info.bw_ets_share_credits[i] =
7975 bw_ets_config.share_credits[i];
7976 vsi->bw_info.bw_ets_limit_credits[i] =
7977 rte_le_to_cpu_16(bw_ets_config.credits[i]);
7978 /* 3 bits out of 4 for each TC */
7979 vsi->bw_info.bw_ets_max_quanta[i] =
7980 (uint8_t)((tc_bw_max >> (i * 4)) & 0x7);
7982 "%s: vsi seid = %d, TC = %d, qset = 0x%x\n",
7983 __func__, vsi->seid, i, bw_config.qs_handles[i]);
7990 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
7991 struct i40e_aqc_vsi_properties_data *info,
7992 uint8_t enabled_tcmap)
7994 int ret, i, total_tc = 0;
7995 uint16_t qpnum_per_tc, bsf, qp_idx;
7996 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
7998 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
7999 if (ret != I40E_SUCCESS)
8002 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8003 if (enabled_tcmap & (1 << i))
8008 vsi->enabled_tc = enabled_tcmap;
8010 qpnum_per_tc = dev_data->nb_rx_queues / total_tc;
8011 /* Number of queues per enabled TC */
8012 if (qpnum_per_tc == 0) {
8013 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
8014 return I40E_ERR_INVALID_QP_ID;
8016 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
8018 bsf = rte_bsf32(qpnum_per_tc);
8021 * Configure TC and queue mapping parameters, for enabled TC,
8022 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
8023 * default queue will serve it.
8026 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8027 if (vsi->enabled_tc & (1 << i)) {
8028 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
8029 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
8030 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
8031 qp_idx += qpnum_per_tc;
8033 info->tc_mapping[i] = 0;
8036 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
8037 if (vsi->type == I40E_VSI_SRIOV) {
8038 info->mapping_flags |=
8039 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
8040 for (i = 0; i < vsi->nb_qps; i++)
8041 info->queue_mapping[i] =
8042 rte_cpu_to_le_16(vsi->base_queue + i);
8044 info->mapping_flags |=
8045 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
8046 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
8048 info->valid_sections |=
8049 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
8051 return I40E_SUCCESS;
8055 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
8056 * @vsi: VSI to be configured
8057 * @tc_map: enabled TC bitmap
8059 * Returns 0 on success, negative value on failure
8062 i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 tc_map)
8064 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
8065 struct i40e_vsi_context ctxt;
8066 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
8070 /* Check if enabled_tc is same as existing or new TCs */
8071 if (vsi->enabled_tc == tc_map)
8074 /* configure tc bandwidth */
8075 memset(&bw_data, 0, sizeof(bw_data));
8076 bw_data.tc_valid_bits = tc_map;
8077 /* Enable ETS TCs with equal BW Share for now across all VSIs */
8078 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8079 if (tc_map & BIT_ULL(i))
8080 bw_data.tc_bw_credits[i] = 1;
8082 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
8084 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
8085 " per TC failed = %d",
8086 hw->aq.asq_last_status);
8089 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
8090 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
8092 /* Update Queue Pairs Mapping for currently enabled UPs */
8093 ctxt.seid = vsi->seid;
8094 ctxt.pf_num = hw->pf_id;
8096 ctxt.uplink_seid = vsi->uplink_seid;
8097 ctxt.info = vsi->info;
8099 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
8103 /* Update the VSI after updating the VSI queue-mapping information */
8104 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8106 PMD_INIT_LOG(ERR, "Failed to configure "
8107 "TC queue mapping = %d",
8108 hw->aq.asq_last_status);
8111 /* update the local VSI info with updated queue map */
8112 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
8113 sizeof(vsi->info.tc_mapping));
8114 (void)rte_memcpy(&vsi->info.queue_mapping,
8115 &ctxt.info.queue_mapping,
8116 sizeof(vsi->info.queue_mapping));
8117 vsi->info.mapping_flags = ctxt.info.mapping_flags;
8118 vsi->info.valid_sections = 0;
8120 /* Update current VSI BW information */
8121 ret = i40e_vsi_get_bw_info(vsi);
8124 "Failed updating vsi bw info, err %s aq_err %s",
8125 i40e_stat_str(hw, ret),
8126 i40e_aq_str(hw, hw->aq.asq_last_status));
8130 vsi->enabled_tc = tc_map;
8137 * i40e_dcb_hw_configure - program the dcb setting to hw
8138 * @pf: pf the configuration is taken on
8139 * @new_cfg: new configuration
8140 * @tc_map: enabled TC bitmap
8142 * Returns 0 on success, negative value on failure
8144 static enum i40e_status_code
8145 i40e_dcb_hw_configure(struct i40e_pf *pf,
8146 struct i40e_dcbx_config *new_cfg,
8149 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8150 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
8151 struct i40e_vsi *main_vsi = pf->main_vsi;
8152 struct i40e_vsi_list *vsi_list;
8156 /* Use the FW API if FW > v4.4*/
8157 if (!((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4))) {
8158 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
8159 " to configure DCB");
8160 return I40E_ERR_FIRMWARE_API_VERSION;
8163 /* Check if need reconfiguration */
8164 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
8165 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
8166 return I40E_SUCCESS;
8169 /* Copy the new config to the current config */
8170 *old_cfg = *new_cfg;
8171 old_cfg->etsrec = old_cfg->etscfg;
8172 ret = i40e_set_dcb_config(hw);
8175 "Set DCB Config failed, err %s aq_err %s\n",
8176 i40e_stat_str(hw, ret),
8177 i40e_aq_str(hw, hw->aq.asq_last_status));
8180 /* set receive Arbiter to RR mode and ETS scheme by default */
8181 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
8182 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
8183 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
8184 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
8185 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
8186 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
8187 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
8188 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
8189 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
8190 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
8191 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
8192 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
8193 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
8195 /* get local mib to check whether it is configured correctly */
8197 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
8198 /* Get Local DCB Config */
8199 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
8200 &hw->local_dcbx_config);
8202 /* Update each VSI */
8203 i40e_vsi_config_tc(main_vsi, tc_map);
8204 if (main_vsi->veb) {
8205 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
8206 /* Beside main VSI, only enable default
8209 ret = i40e_vsi_config_tc(vsi_list->vsi,
8210 I40E_DEFAULT_TCMAP);
8212 PMD_INIT_LOG(WARNING,
8213 "Failed configuring TC for VSI seid=%d\n",
8214 vsi_list->vsi->seid);
8218 return I40E_SUCCESS;
8222 * i40e_dcb_init_configure - initial dcb config
8223 * @dev: device being configured
8224 * @sw_dcb: indicate whether dcb is sw configured or hw offload
8226 * Returns 0 on success, negative value on failure
8229 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
8231 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8232 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8235 if ((pf->flags & I40E_FLAG_DCB) == 0) {
8236 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8240 /* DCB initialization:
8241 * Update DCB configuration from the Firmware and configure
8242 * LLDP MIB change event.
8244 if (sw_dcb == TRUE) {
8245 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
8246 if (ret != I40E_SUCCESS)
8247 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
8249 ret = i40e_init_dcb(hw);
8250 /* if sw_dcb, lldp agent is stopped, the return from
8251 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
8254 if (ret != I40E_SUCCESS &&
8255 hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
8256 memset(&hw->local_dcbx_config, 0,
8257 sizeof(struct i40e_dcbx_config));
8258 /* set dcb default configuration */
8259 hw->local_dcbx_config.etscfg.willing = 0;
8260 hw->local_dcbx_config.etscfg.maxtcs = 0;
8261 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
8262 hw->local_dcbx_config.etscfg.tsatable[0] =
8264 hw->local_dcbx_config.etsrec =
8265 hw->local_dcbx_config.etscfg;
8266 hw->local_dcbx_config.pfc.willing = 0;
8267 hw->local_dcbx_config.pfc.pfccap =
8268 I40E_MAX_TRAFFIC_CLASS;
8269 /* FW needs one App to configure HW */
8270 hw->local_dcbx_config.numapps = 1;
8271 hw->local_dcbx_config.app[0].selector =
8272 I40E_APP_SEL_ETHTYPE;
8273 hw->local_dcbx_config.app[0].priority = 3;
8274 hw->local_dcbx_config.app[0].protocolid =
8275 I40E_APP_PROTOID_FCOE;
8276 ret = i40e_set_dcb_config(hw);
8278 PMD_INIT_LOG(ERR, "default dcb config fails."
8279 " err = %d, aq_err = %d.", ret,
8280 hw->aq.asq_last_status);
8284 PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8285 " aq_err = %d.", ret,
8286 hw->aq.asq_last_status);
8290 ret = i40e_aq_start_lldp(hw, NULL);
8291 if (ret != I40E_SUCCESS)
8292 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
8294 ret = i40e_init_dcb(hw);
8296 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
8297 PMD_INIT_LOG(ERR, "HW doesn't support"
8302 PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8303 " aq_err = %d.", ret,
8304 hw->aq.asq_last_status);
8312 * i40e_dcb_setup - setup dcb related config
8313 * @dev: device being configured
8315 * Returns 0 on success, negative value on failure
8318 i40e_dcb_setup(struct rte_eth_dev *dev)
8320 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8321 struct i40e_dcbx_config dcb_cfg;
8325 if ((pf->flags & I40E_FLAG_DCB) == 0) {
8326 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8330 if (pf->vf_num != 0 ||
8331 (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG))
8332 PMD_INIT_LOG(DEBUG, " DCB only works on main vsi.");
8334 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
8336 PMD_INIT_LOG(ERR, "invalid dcb config");
8339 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
8341 PMD_INIT_LOG(ERR, "dcb sw configure fails");
8349 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
8350 struct rte_eth_dcb_info *dcb_info)
8352 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8353 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8354 struct i40e_vsi *vsi = pf->main_vsi;
8355 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
8356 uint16_t bsf, tc_mapping;
8359 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
8360 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
8362 dcb_info->nb_tcs = 1;
8363 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8364 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
8365 for (i = 0; i < dcb_info->nb_tcs; i++)
8366 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
8368 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8369 if (vsi->enabled_tc & (1 << i)) {
8370 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
8371 /* only main vsi support multi TCs */
8372 dcb_info->tc_queue.tc_rxq[0][i].base =
8373 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
8374 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
8375 dcb_info->tc_queue.tc_txq[0][i].base =
8376 dcb_info->tc_queue.tc_rxq[0][i].base;
8377 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
8378 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
8379 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 1 << bsf;
8380 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
8381 dcb_info->tc_queue.tc_rxq[0][i].nb_queue;
8389 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
8391 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
8392 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8394 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
8397 msix_intr = intr_handle->intr_vec[queue_id];
8398 if (msix_intr == I40E_MISC_VEC_ID)
8399 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
8400 I40E_PFINT_DYN_CTLN_INTENA_MASK |
8401 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
8402 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
8404 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
8407 I40E_PFINT_DYN_CTLN(msix_intr -
8409 I40E_PFINT_DYN_CTLN_INTENA_MASK |
8410 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
8411 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
8413 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
8415 I40E_WRITE_FLUSH(hw);
8416 rte_intr_enable(&dev->pci_dev->intr_handle);
8422 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
8424 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
8425 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8428 msix_intr = intr_handle->intr_vec[queue_id];
8429 if (msix_intr == I40E_MISC_VEC_ID)
8430 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
8433 I40E_PFINT_DYN_CTLN(msix_intr -
8436 I40E_WRITE_FLUSH(hw);