drivers/net/i40e/i40e_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10 #include <stdarg.h>
  11 #include <inttypes.h>
  12 #include <assert.h>
  13
  14 #include <rte_common.h>
  15 #include <rte_eal.h>
  16 #include <rte_string_fns.h>
  17 #include <rte_pci.h>
  18 #include <rte_bus_pci.h>
  19 #include <rte_ether.h>
  20 #include <ethdev_driver.h>
  21 #include <ethdev_pci.h>
  22 #include <rte_memzone.h>
  23 #include <rte_malloc.h>
  24 #include <rte_memcpy.h>
  25 #include <rte_alarm.h>
  26 #include <rte_dev.h>
  27 #include <rte_tailq.h>
  28 #include <rte_hash_crc.h>
  29 #include <rte_bitmap.h>
  30 #include <rte_os_shim.h>
  31
  32 #include "i40e_logs.h"
  33 #include "base/i40e_prototype.h"
  34 #include "base/i40e_adminq_cmd.h"
  35 #include "base/i40e_type.h"
  36 #include "base/i40e_register.h"
  37 #include "base/i40e_dcb.h"
  38 #include "i40e_ethdev.h"
  39 #include "i40e_rxtx.h"
  40 #include "i40e_pf.h"
  41 #include "i40e_regs.h"
  42 #include "rte_pmd_i40e.h"
  43 #include "i40e_hash.h"
  44
  45 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  46 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  47 #define ETH_I40E_SUPPORT_MULTI_DRIVER   "support-multi-driver"
  48 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG   "queue-num-per-vf"
  49 #define ETH_I40E_VF_MSG_CFG             "vf_msg_cfg"
  50
  51 #define I40E_CLEAR_PXE_WAIT_MS     200
  52 #define I40E_VSI_TSR_QINQ_STRIP         0x4010
  53 #define I40E_VSI_TSR(_i)        (0x00050800 + ((_i) * 4))
  54
  55 /* Maximun number of capability elements */
  56 #define I40E_MAX_CAP_ELE_NUM       128
  57
  58 /* Wait count and interval */
  59 #define I40E_CHK_Q_ENA_COUNT       1000
  60 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  61
  62 /* Maximun number of VSI */
  63 #define I40E_MAX_NUM_VSIS          (384UL)
  64
  65 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  66
  67 /* Flow control default timer */
  68 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  69
  70 /* Flow control enable fwd bit */
  71 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  72
  73 /* Receive Packet Buffer size */
  74 #define I40E_RXPBSIZE (968 * 1024)
  75
  76 /* Kilobytes shift */
  77 #define I40E_KILOSHIFT 10
  78
  79 /* Flow control default high water */
  80 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
  81
  82 /* Flow control default low water */
  83 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
  84
  85 /* Receive Average Packet Size in Byte*/
  86 #define I40E_PACKET_AVERAGE_SIZE 128
  87
  88 /* Mask of PF interrupt causes */
  89 #define I40E_PFINT_ICR0_ENA_MASK ( \
  90                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  91                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  92                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  93                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  94                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  95                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  96                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  97                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  98                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  99
 100 #define I40E_FLOW_TYPES ( \
 101         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 102         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 103         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 104         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 105         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 106         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 107         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 108         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 109         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 110         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 111         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 112
 113 /* Additional timesync values. */
 114 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 115 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 116 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 117 #define I40E_PRTTSYN_TSYNENA     0x80000000
 118 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 119 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 120
 121 /**
 122  * Below are values for writing un-exposed registers suggested
 123  * by silicon experts
 124  */
 125 /* Destination MAC address */
 126 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 127 /* Source MAC address */
 128 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 129 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 130 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 131 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 132 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 133 /* Single VLAN tag in the inner L2 header */
 134 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 135 /* Source IPv4 address */
 136 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 137 /* Destination IPv4 address */
 138 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 139 /* Source IPv4 address for X722 */
 140 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 141 /* Destination IPv4 address for X722 */
 142 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 143 /* IPv4 Protocol for X722 */
 144 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 145 /* IPv4 Time to Live for X722 */
 146 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 147 /* IPv4 Type of Service (TOS) */
 148 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 149 /* IPv4 Protocol */
 150 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 151 /* IPv4 Time to Live */
 152 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 153 /* Source IPv6 address */
 154 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 155 /* Destination IPv6 address */
 156 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 157 /* IPv6 Traffic Class (TC) */
 158 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 159 /* IPv6 Next Header */
 160 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 161 /* IPv6 Hop Limit */
 162 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 163 /* Source L4 port */
 164 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 165 /* Destination L4 port */
 166 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 167 /* SCTP verification tag */
 168 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 169 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 170 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 171 /* Source port of tunneling UDP */
 172 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 173 /* Destination port of tunneling UDP */
 174 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 175 /* UDP Tunneling ID, NVGRE/GRE key */
 176 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 177 /* Last ether type */
 178 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 179 /* Tunneling outer destination IPv4 address */
 180 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 181 /* Tunneling outer destination IPv6 address */
 182 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 183 /* 1st word of flex payload */
 184 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 185 /* 2nd word of flex payload */
 186 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 187 /* 3rd word of flex payload */
 188 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 189 /* 4th word of flex payload */
 190 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 191 /* 5th word of flex payload */
 192 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 193 /* 6th word of flex payload */
 194 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 195 /* 7th word of flex payload */
 196 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 197 /* 8th word of flex payload */
 198 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 199 /* all 8 words flex payload */
 200 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 201 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 202
 203 #define I40E_TRANSLATE_INSET 0
 204 #define I40E_TRANSLATE_REG   1
 205
 206 #define I40E_INSET_IPV4_TOS_MASK        0x0000FF00UL
 207 #define I40E_INSET_IPV4_TTL_MASK        0x000000FFUL
 208 #define I40E_INSET_IPV4_PROTO_MASK      0x0000FF00UL
 209 #define I40E_INSET_IPV6_TC_MASK         0x0000F00FUL
 210 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x0000FF00UL
 211 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000000FFUL
 212
 213 /* PCI offset for querying capability */
 214 #define PCI_DEV_CAP_REG            0xA4
 215 /* PCI offset for enabling/disabling Extended Tag */
 216 #define PCI_DEV_CTRL_REG           0xA8
 217 /* Bit mask of Extended Tag capability */
 218 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 219 /* Bit shift of Extended Tag enable/disable */
 220 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 221 /* Bit mask of Extended Tag enable/disable */
 222 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 223
 224 #define I40E_GLQF_PIT_IPV4_START        2
 225 #define I40E_GLQF_PIT_IPV4_COUNT        2
 226 #define I40E_GLQF_PIT_IPV6_START        4
 227 #define I40E_GLQF_PIT_IPV6_COUNT        2
 228
 229 #define I40E_GLQF_PIT_SOURCE_OFF_GET(a) \
 230                                 (((a) & I40E_GLQF_PIT_SOURCE_OFF_MASK) >> \
 231                                  I40E_GLQF_PIT_SOURCE_OFF_SHIFT)
 232
 233 #define I40E_GLQF_PIT_DEST_OFF_GET(a) \
 234                                 (((a) & I40E_GLQF_PIT_DEST_OFF_MASK) >> \
 235                                  I40E_GLQF_PIT_DEST_OFF_SHIFT)
 236
 237 #define I40E_GLQF_PIT_FSIZE_GET(a)      (((a) & I40E_GLQF_PIT_FSIZE_MASK) >> \
 238                                          I40E_GLQF_PIT_FSIZE_SHIFT)
 239
 240 #define I40E_GLQF_PIT_BUILD(off, mask)  (((off) << 16) | (mask))
 241 #define I40E_FDIR_FIELD_OFFSET(a)       ((a) >> 1)
 242
 243 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 244 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 245 static int i40e_dev_configure(struct rte_eth_dev *dev);
 246 static int i40e_dev_start(struct rte_eth_dev *dev);
 247 static int i40e_dev_stop(struct rte_eth_dev *dev);
 248 static int i40e_dev_close(struct rte_eth_dev *dev);
 249 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 250 static int i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 251 static int i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 252 static int i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 253 static int i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 254 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 255 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 256 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 257                                struct rte_eth_stats *stats);
 258 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 259                                struct rte_eth_xstat *xstats, unsigned n);
 260 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 261                                      struct rte_eth_xstat_name *xstats_names,
 262                                      unsigned limit);
 263 static int i40e_dev_stats_reset(struct rte_eth_dev *dev);
 264 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 265                                 char *fw_version, size_t fw_size);
 266 static int i40e_dev_info_get(struct rte_eth_dev *dev,
 267                              struct rte_eth_dev_info *dev_info);
 268 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 269                                 uint16_t vlan_id,
 270                                 int on);
 271 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 272                               enum rte_vlan_type vlan_type,
 273                               uint16_t tpid);
 274 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 275 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 276                                       uint16_t queue,
 277                                       int on);
 278 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 279 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 280 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 281 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 282                               struct rte_eth_fc_conf *fc_conf);
 283 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 284                               struct rte_eth_fc_conf *fc_conf);
 285 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 286                                        struct rte_eth_pfc_conf *pfc_conf);
 287 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 288                             struct rte_ether_addr *mac_addr,
 289                             uint32_t index,
 290                             uint32_t pool);
 291 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 292 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 293                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 294                                     uint16_t reta_size);
 295 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 296                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 297                                    uint16_t reta_size);
 298
 299 static int i40e_get_cap(struct i40e_hw *hw);
 300 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 301 static int i40e_pf_setup(struct i40e_pf *pf);
 302 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 303 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 304 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 305 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 306                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 307 static void i40e_stat_update_48(struct i40e_hw *hw,
 308                                uint32_t hireg,
 309                                uint32_t loreg,
 310                                bool offset_loaded,
 311                                uint64_t *offset,
 312                                uint64_t *stat);
 313 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 314 static void i40e_dev_interrupt_handler(void *param);
 315 static void i40e_dev_alarm_handler(void *param);
 316 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 317                                 uint32_t base, uint32_t num);
 318 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 319 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 320                         uint32_t base);
 321 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 322                         uint16_t num);
 323 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 324 static int i40e_veb_release(struct i40e_veb *veb);
 325 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 326                                                 struct i40e_vsi *vsi);
 327 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 328 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 329                                              struct i40e_macvlan_filter *mv_f,
 330                                              int num,
 331                                              uint16_t vlan);
 332 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 333 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 334                                     struct rte_eth_rss_conf *rss_conf);
 335 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 336                                       struct rte_eth_rss_conf *rss_conf);
 337 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 338                                         struct rte_eth_udp_tunnel *udp_tunnel);
 339 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 340                                         struct rte_eth_udp_tunnel *udp_tunnel);
 341 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 342 static int i40e_dev_flow_ops_get(struct rte_eth_dev *dev,
 343                                  const struct rte_flow_ops **ops);
 344 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 345                                   struct rte_eth_dcb_info *dcb_info);
 346 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 347 static void i40e_configure_registers(struct i40e_hw *hw);
 348 static void i40e_hw_init(struct rte_eth_dev *dev);
 349 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 350 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 351                                                      uint16_t seid,
 352                                                      uint16_t rule_type,
 353                                                      uint16_t *entries,
 354                                                      uint16_t count,
 355                                                      uint16_t rule_id);
 356 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 357                         struct rte_eth_mirror_conf *mirror_conf,
 358                         uint8_t sw_id, uint8_t on);
 359 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 360
 361 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 362 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 363 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 364                                            struct timespec *timestamp,
 365                                            uint32_t flags);
 366 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 367                                            struct timespec *timestamp);
 368 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 369
 370 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 371
 372 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 373                                    struct timespec *timestamp);
 374 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 375                                     const struct timespec *timestamp);
 376
 377 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 378                                          uint16_t queue_id);
 379 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 380                                           uint16_t queue_id);
 381
 382 static int i40e_get_regs(struct rte_eth_dev *dev,
 383                          struct rte_dev_reg_info *regs);
 384
 385 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 386
 387 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 388                            struct rte_dev_eeprom_info *eeprom);
 389
 390 static int i40e_get_module_info(struct rte_eth_dev *dev,
 391                                 struct rte_eth_dev_module_info *modinfo);
 392 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
 393                                   struct rte_dev_eeprom_info *info);
 394
 395 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 396                                       struct rte_ether_addr *mac_addr);
 397
 398 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 399
 400 static int i40e_ethertype_filter_convert(
 401         const struct rte_eth_ethertype_filter *input,
 402         struct i40e_ethertype_filter *filter);
 403 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 404                                    struct i40e_ethertype_filter *filter);
 405
 406 static int i40e_tunnel_filter_convert(
 407         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
 408         struct i40e_tunnel_filter *tunnel_filter);
 409 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 410                                 struct i40e_tunnel_filter *tunnel_filter);
 411 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 412
 413 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 414 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 415 static void i40e_filter_restore(struct i40e_pf *pf);
 416 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 417
 418 static const char *const valid_keys[] = {
 419         ETH_I40E_FLOATING_VEB_ARG,
 420         ETH_I40E_FLOATING_VEB_LIST_ARG,
 421         ETH_I40E_SUPPORT_MULTI_DRIVER,
 422         ETH_I40E_QUEUE_NUM_PER_VF_ARG,
 423         ETH_I40E_VF_MSG_CFG,
 424         NULL};
 425
 426 static const struct rte_pci_id pci_id_i40e_map[] = {
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 438         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 439         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 440         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 441         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 442         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 443         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 444         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 445         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 446         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 447         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X710_N3000) },
 448         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_XXV710_N3000) },
 449         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_BC) },
 450         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_5G_BASE_T_BC) },
 451         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_B) },
 452         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_SFP) },
 453         { .vendor_id = 0, /* sentinel */ },
 454 };
 455
 456 static const struct eth_dev_ops i40e_eth_dev_ops = {
 457         .dev_configure                = i40e_dev_configure,
 458         .dev_start                    = i40e_dev_start,
 459         .dev_stop                     = i40e_dev_stop,
 460         .dev_close                    = i40e_dev_close,
 461         .dev_reset                    = i40e_dev_reset,
 462         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 463         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 464         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 465         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 466         .dev_set_link_up              = i40e_dev_set_link_up,
 467         .dev_set_link_down            = i40e_dev_set_link_down,
 468         .link_update                  = i40e_dev_link_update,
 469         .stats_get                    = i40e_dev_stats_get,
 470         .xstats_get                   = i40e_dev_xstats_get,
 471         .xstats_get_names             = i40e_dev_xstats_get_names,
 472         .stats_reset                  = i40e_dev_stats_reset,
 473         .xstats_reset                 = i40e_dev_stats_reset,
 474         .fw_version_get               = i40e_fw_version_get,
 475         .dev_infos_get                = i40e_dev_info_get,
 476         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 477         .vlan_filter_set              = i40e_vlan_filter_set,
 478         .vlan_tpid_set                = i40e_vlan_tpid_set,
 479         .vlan_offload_set             = i40e_vlan_offload_set,
 480         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 481         .vlan_pvid_set                = i40e_vlan_pvid_set,
 482         .rx_queue_start               = i40e_dev_rx_queue_start,
 483         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 484         .tx_queue_start               = i40e_dev_tx_queue_start,
 485         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 486         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 487         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 488         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 489         .rx_queue_release             = i40e_dev_rx_queue_release,
 490         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 491         .tx_queue_release             = i40e_dev_tx_queue_release,
 492         .dev_led_on                   = i40e_dev_led_on,
 493         .dev_led_off                  = i40e_dev_led_off,
 494         .flow_ctrl_get                = i40e_flow_ctrl_get,
 495         .flow_ctrl_set                = i40e_flow_ctrl_set,
 496         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 497         .mac_addr_add                 = i40e_macaddr_add,
 498         .mac_addr_remove              = i40e_macaddr_remove,
 499         .reta_update                  = i40e_dev_rss_reta_update,
 500         .reta_query                   = i40e_dev_rss_reta_query,
 501         .rss_hash_update              = i40e_dev_rss_hash_update,
 502         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 503         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 504         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 505         .flow_ops_get                 = i40e_dev_flow_ops_get,
 506         .rxq_info_get                 = i40e_rxq_info_get,
 507         .txq_info_get                 = i40e_txq_info_get,
 508         .rx_burst_mode_get            = i40e_rx_burst_mode_get,
 509         .tx_burst_mode_get            = i40e_tx_burst_mode_get,
 510         .mirror_rule_set              = i40e_mirror_rule_set,
 511         .mirror_rule_reset            = i40e_mirror_rule_reset,
 512         .timesync_enable              = i40e_timesync_enable,
 513         .timesync_disable             = i40e_timesync_disable,
 514         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 515         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 516         .get_dcb_info                 = i40e_dev_get_dcb_info,
 517         .timesync_adjust_time         = i40e_timesync_adjust_time,
 518         .timesync_read_time           = i40e_timesync_read_time,
 519         .timesync_write_time          = i40e_timesync_write_time,
 520         .get_reg                      = i40e_get_regs,
 521         .get_eeprom_length            = i40e_get_eeprom_length,
 522         .get_eeprom                   = i40e_get_eeprom,
 523         .get_module_info              = i40e_get_module_info,
 524         .get_module_eeprom            = i40e_get_module_eeprom,
 525         .mac_addr_set                 = i40e_set_default_mac_addr,
 526         .mtu_set                      = i40e_dev_mtu_set,
 527         .tm_ops_get                   = i40e_tm_ops_get,
 528         .tx_done_cleanup              = i40e_tx_done_cleanup,
 529         .get_monitor_addr             = i40e_get_monitor_addr,
 530 };
 531
 532 /* store statistics names and its offset in stats structure */
 533 struct rte_i40e_xstats_name_off {
 534         char name[RTE_ETH_XSTATS_NAME_SIZE];
 535         unsigned offset;
 536 };
 537
 538 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 539         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 540         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 541         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 542         {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
 543         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 544                 rx_unknown_protocol)},
 545         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 546         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 547         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 548         {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
 549 };
 550
 551 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 552                 sizeof(rte_i40e_stats_strings[0]))
 553
 554 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 555         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 556                 tx_dropped_link_down)},
 557         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 558         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 559                 illegal_bytes)},
 560         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 561         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 562                 mac_local_faults)},
 563         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 564                 mac_remote_faults)},
 565         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 566                 rx_length_errors)},
 567         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 568         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 569         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 570         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 571         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 572         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 573                 rx_size_127)},
 574         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 575                 rx_size_255)},
 576         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 577                 rx_size_511)},
 578         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 579                 rx_size_1023)},
 580         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 581                 rx_size_1522)},
 582         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 583                 rx_size_big)},
 584         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 585                 rx_undersize)},
 586         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 587                 rx_oversize)},
 588         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 589                 mac_short_packet_dropped)},
 590         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 591                 rx_fragments)},
 592         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 593         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 594         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 595                 tx_size_127)},
 596         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 597                 tx_size_255)},
 598         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 599                 tx_size_511)},
 600         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 601                 tx_size_1023)},
 602         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 603                 tx_size_1522)},
 604         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 605                 tx_size_big)},
 606         {"rx_flow_director_atr_match_packets",
 607                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 608         {"rx_flow_director_sb_match_packets",
 609                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 610         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 611                 tx_lpi_status)},
 612         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 613                 rx_lpi_status)},
 614         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 615                 tx_lpi_count)},
 616         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 617                 rx_lpi_count)},
 618 };
 619
 620 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 621                 sizeof(rte_i40e_hw_port_strings[0]))
 622
 623 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 624         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 625                 priority_xon_rx)},
 626         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 627                 priority_xoff_rx)},
 628 };
 629
 630 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 631                 sizeof(rte_i40e_rxq_prio_strings[0]))
 632
 633 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 634         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 635                 priority_xon_tx)},
 636         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 637                 priority_xoff_tx)},
 638         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 639                 priority_xon_2_xoff)},
 640 };
 641
 642 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 643                 sizeof(rte_i40e_txq_prio_strings[0]))
 644
 645 static int
 646 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 647         struct rte_pci_device *pci_dev)
 648 {
 649         char name[RTE_ETH_NAME_MAX_LEN];
 650         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
 651         int i, retval;
 652
 653         if (pci_dev->device.devargs) {
 654                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
 655                                 &eth_da);
 656                 if (retval)
 657                         return retval;
 658         }
 659
 660         if (eth_da.nb_representor_ports > 0 &&
 661             eth_da.type != RTE_ETH_REPRESENTOR_VF) {
 662                 PMD_DRV_LOG(ERR, "unsupported representor type: %s\n",
 663                             pci_dev->device.devargs->args);
 664                 return -ENOTSUP;
 665         }
 666
 667         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
 668                 sizeof(struct i40e_adapter),
 669                 eth_dev_pci_specific_init, pci_dev,
 670                 eth_i40e_dev_init, NULL);
 671
 672         if (retval || eth_da.nb_representor_ports < 1)
 673                 return retval;
 674
 675         /* probe VF representor ports */
 676         struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
 677                 pci_dev->device.name);
 678
 679         if (pf_ethdev == NULL)
 680                 return -ENODEV;
 681
 682         for (i = 0; i < eth_da.nb_representor_ports; i++) {
 683                 struct i40e_vf_representor representor = {
 684                         .vf_id = eth_da.representor_ports[i],
 685                         .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
 686                                 pf_ethdev->data->dev_private)->switch_domain_id,
 687                         .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
 688                                 pf_ethdev->data->dev_private)
 689                 };
 690
 691                 /* representor port net_bdf_port */
 692                 snprintf(name, sizeof(name), "net_%s_representor_%d",
 693                         pci_dev->device.name, eth_da.representor_ports[i]);
 694
 695                 retval = rte_eth_dev_create(&pci_dev->device, name,
 696                         sizeof(struct i40e_vf_representor), NULL, NULL,
 697                         i40e_vf_representor_init, &representor);
 698
 699                 if (retval)
 700                         PMD_DRV_LOG(ERR, "failed to create i40e vf "
 701                                 "representor %s.", name);
 702         }
 703
 704         return 0;
 705 }
 706
 707 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 708 {
 709         struct rte_eth_dev *ethdev;
 710
 711         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 712         if (!ethdev)
 713                 return 0;
 714
 715         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
 716                 return rte_eth_dev_pci_generic_remove(pci_dev,
 717                                         i40e_vf_representor_uninit);
 718         else
 719                 return rte_eth_dev_pci_generic_remove(pci_dev,
 720                                                 eth_i40e_dev_uninit);
 721 }
 722
 723 static struct rte_pci_driver rte_i40e_pmd = {
 724         .id_table = pci_id_i40e_map,
 725         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 726         .probe = eth_i40e_pci_probe,
 727         .remove = eth_i40e_pci_remove,
 728 };
 729
 730 static inline void
 731 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
 732                          uint32_t reg_val)
 733 {
 734         uint32_t ori_reg_val;
 735         struct rte_eth_dev *dev;
 736
 737         ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
 738         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
 739         i40e_write_rx_ctl(hw, reg_addr, reg_val);
 740         if (ori_reg_val != reg_val)
 741                 PMD_DRV_LOG(WARNING,
 742                             "i40e device %s changed global register [0x%08x]."
 743                             " original: 0x%08x, new: 0x%08x",
 744                             dev->device->name, reg_addr, ori_reg_val, reg_val);
 745 }
 746
 747 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 748 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 749 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 750
 751 #ifndef I40E_GLQF_ORT
 752 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 753 #endif
 754 #ifndef I40E_GLQF_PIT
 755 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 756 #endif
 757 #ifndef I40E_GLQF_L3_MAP
 758 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 759 #endif
 760
 761 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 762 {
 763         /*
 764          * Initialize registers for parsing packet type of QinQ
 765          * This should be removed from code once proper
 766          * configuration API is added to avoid configuration conflicts
 767          * between ports of the same device.
 768          */
 769         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 770         I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 771 }
 772
 773 static inline void i40e_config_automask(struct i40e_pf *pf)
 774 {
 775         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 776         uint32_t val;
 777
 778         /* INTENA flag is not auto-cleared for interrupt */
 779         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
 780         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
 781                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
 782
 783         /* If support multi-driver, PF will use INT0. */
 784         if (!pf->support_multi_driver)
 785                 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
 786
 787         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
 788 }
 789
 790 static inline void i40e_clear_automask(struct i40e_pf *pf)
 791 {
 792         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 793         uint32_t val;
 794
 795         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
 796         val &= ~(I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
 797                  I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK);
 798
 799         if (!pf->support_multi_driver)
 800                 val &= ~I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
 801
 802         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
 803 }
 804
 805 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 806
 807 /*
 808  * Add a ethertype filter to drop all flow control frames transmitted
 809  * from VSIs.
 810 */
 811 static void
 812 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 813 {
 814         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 815         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 816                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 817                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 818         int ret;
 819
 820         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 821                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 822                                 pf->main_vsi_seid, 0,
 823                                 TRUE, NULL, NULL);
 824         if (ret)
 825                 PMD_INIT_LOG(ERR,
 826                         "Failed to add filter to drop flow control frames from VSIs.");
 827 }
 828
 829 static int
 830 floating_veb_list_handler(__rte_unused const char *key,
 831                           const char *floating_veb_value,
 832                           void *opaque)
 833 {
 834         int idx = 0;
 835         unsigned int count = 0;
 836         char *end = NULL;
 837         int min, max;
 838         bool *vf_floating_veb = opaque;
 839
 840         while (isblank(*floating_veb_value))
 841                 floating_veb_value++;
 842
 843         /* Reset floating VEB configuration for VFs */
 844         for (idx = 0; idx < I40E_MAX_VF; idx++)
 845                 vf_floating_veb[idx] = false;
 846
 847         min = I40E_MAX_VF;
 848         do {
 849                 while (isblank(*floating_veb_value))
 850                         floating_veb_value++;
 851                 if (*floating_veb_value == '\0')
 852                         return -1;
 853                 errno = 0;
 854                 idx = strtoul(floating_veb_value, &end, 10);
 855                 if (errno || end == NULL)
 856                         return -1;
 857                 if (idx < 0)
 858                         return -1;
 859                 while (isblank(*end))
 860                         end++;
 861                 if (*end == '-') {
 862                         min = idx;
 863                 } else if ((*end == ';') || (*end == '\0')) {
 864                         max = idx;
 865                         if (min == I40E_MAX_VF)
 866                                 min = idx;
 867                         if (max >= I40E_MAX_VF)
 868                                 max = I40E_MAX_VF - 1;
 869                         for (idx = min; idx <= max; idx++) {
 870                                 vf_floating_veb[idx] = true;
 871                                 count++;
 872                         }
 873                         min = I40E_MAX_VF;
 874                 } else {
 875                         return -1;
 876                 }
 877                 floating_veb_value = end + 1;
 878         } while (*end != '\0');
 879
 880         if (count == 0)
 881                 return -1;
 882
 883         return 0;
 884 }
 885
 886 static void
 887 config_vf_floating_veb(struct rte_devargs *devargs,
 888                        uint16_t floating_veb,
 889                        bool *vf_floating_veb)
 890 {
 891         struct rte_kvargs *kvlist;
 892         int i;
 893         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 894
 895         if (!floating_veb)
 896                 return;
 897         /* All the VFs attach to the floating VEB by default
 898          * when the floating VEB is enabled.
 899          */
 900         for (i = 0; i < I40E_MAX_VF; i++)
 901                 vf_floating_veb[i] = true;
 902
 903         if (devargs == NULL)
 904                 return;
 905
 906         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 907         if (kvlist == NULL)
 908                 return;
 909
 910         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 911                 rte_kvargs_free(kvlist);
 912                 return;
 913         }
 914         /* When the floating_veb_list parameter exists, all the VFs
 915          * will attach to the legacy VEB firstly, then configure VFs
 916          * to the floating VEB according to the floating_veb_list.
 917          */
 918         if (rte_kvargs_process(kvlist, floating_veb_list,
 919                                floating_veb_list_handler,
 920                                vf_floating_veb) < 0) {
 921                 rte_kvargs_free(kvlist);
 922                 return;
 923         }
 924         rte_kvargs_free(kvlist);
 925 }
 926
 927 static int
 928 i40e_check_floating_handler(__rte_unused const char *key,
 929                             const char *value,
 930                             __rte_unused void *opaque)
 931 {
 932         if (strcmp(value, "1"))
 933                 return -1;
 934
 935         return 0;
 936 }
 937
 938 static int
 939 is_floating_veb_supported(struct rte_devargs *devargs)
 940 {
 941         struct rte_kvargs *kvlist;
 942         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 943
 944         if (devargs == NULL)
 945                 return 0;
 946
 947         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 948         if (kvlist == NULL)
 949                 return 0;
 950
 951         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 952                 rte_kvargs_free(kvlist);
 953                 return 0;
 954         }
 955         /* Floating VEB is enabled when there's key-value:
 956          * enable_floating_veb=1
 957          */
 958         if (rte_kvargs_process(kvlist, floating_veb_key,
 959                                i40e_check_floating_handler, NULL) < 0) {
 960                 rte_kvargs_free(kvlist);
 961                 return 0;
 962         }
 963         rte_kvargs_free(kvlist);
 964
 965         return 1;
 966 }
 967
 968 static void
 969 config_floating_veb(struct rte_eth_dev *dev)
 970 {
 971         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 972         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 973         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 974
 975         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 976
 977         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 978                 pf->floating_veb =
 979                         is_floating_veb_supported(pci_dev->device.devargs);
 980                 config_vf_floating_veb(pci_dev->device.devargs,
 981                                        pf->floating_veb,
 982                                        pf->floating_veb_list);
 983         } else {
 984                 pf->floating_veb = false;
 985         }
 986 }
 987
 988 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 989 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 990
 991 static int
 992 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 993 {
 994         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 995         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 996         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 997         int ret;
 998
 999         struct rte_hash_parameters ethertype_hash_params = {
1000                 .name = ethertype_hash_name,
1001                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
1002                 .key_len = sizeof(struct i40e_ethertype_filter_input),
1003                 .hash_func = rte_hash_crc,
1004                 .hash_func_init_val = 0,
1005                 .socket_id = rte_socket_id(),
1006         };
1007
1008         /* Initialize ethertype filter rule list and hash */
1009         TAILQ_INIT(&ethertype_rule->ethertype_list);
1010         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
1011                  "ethertype_%s", dev->device->name);
1012         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
1013         if (!ethertype_rule->hash_table) {
1014                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
1015                 return -EINVAL;
1016         }
1017         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
1018                                        sizeof(struct i40e_ethertype_filter *) *
1019                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
1020                                        0);
1021         if (!ethertype_rule->hash_map) {
1022                 PMD_INIT_LOG(ERR,
1023                              "Failed to allocate memory for ethertype hash map!");
1024                 ret = -ENOMEM;
1025                 goto err_ethertype_hash_map_alloc;
1026         }
1027
1028         return 0;
1029
1030 err_ethertype_hash_map_alloc:
1031         rte_hash_free(ethertype_rule->hash_table);
1032
1033         return ret;
1034 }
1035
1036 static int
1037 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
1038 {
1039         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1040         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
1041         char tunnel_hash_name[RTE_HASH_NAMESIZE];
1042         int ret;
1043
1044         struct rte_hash_parameters tunnel_hash_params = {
1045                 .name = tunnel_hash_name,
1046                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1047                 .key_len = sizeof(struct i40e_tunnel_filter_input),
1048                 .hash_func = rte_hash_crc,
1049                 .hash_func_init_val = 0,
1050                 .socket_id = rte_socket_id(),
1051         };
1052
1053         /* Initialize tunnel filter rule list and hash */
1054         TAILQ_INIT(&tunnel_rule->tunnel_list);
1055         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1056                  "tunnel_%s", dev->device->name);
1057         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1058         if (!tunnel_rule->hash_table) {
1059                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1060                 return -EINVAL;
1061         }
1062         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1063                                     sizeof(struct i40e_tunnel_filter *) *
1064                                     I40E_MAX_TUNNEL_FILTER_NUM,
1065                                     0);
1066         if (!tunnel_rule->hash_map) {
1067                 PMD_INIT_LOG(ERR,
1068                              "Failed to allocate memory for tunnel hash map!");
1069                 ret = -ENOMEM;
1070                 goto err_tunnel_hash_map_alloc;
1071         }
1072
1073         return 0;
1074
1075 err_tunnel_hash_map_alloc:
1076         rte_hash_free(tunnel_rule->hash_table);
1077
1078         return ret;
1079 }
1080
1081 static int
1082 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1083 {
1084         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1085         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1086         struct i40e_fdir_info *fdir_info = &pf->fdir;
1087         char fdir_hash_name[RTE_HASH_NAMESIZE];
1088         uint32_t alloc = hw->func_caps.fd_filters_guaranteed;
1089         uint32_t best = hw->func_caps.fd_filters_best_effort;
1090         enum i40e_filter_pctype pctype;
1091         struct rte_bitmap *bmp = NULL;
1092         uint32_t bmp_size;
1093         void *mem = NULL;
1094         uint32_t i = 0;
1095         int ret;
1096
1097         struct rte_hash_parameters fdir_hash_params = {
1098                 .name = fdir_hash_name,
1099                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1100                 .key_len = sizeof(struct i40e_fdir_input),
1101                 .hash_func = rte_hash_crc,
1102                 .hash_func_init_val = 0,
1103                 .socket_id = rte_socket_id(),
1104         };
1105
1106         /* Initialize flow director filter rule list and hash */
1107         TAILQ_INIT(&fdir_info->fdir_list);
1108         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1109                  "fdir_%s", dev->device->name);
1110         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1111         if (!fdir_info->hash_table) {
1112                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1113                 return -EINVAL;
1114         }
1115
1116         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1117                                           sizeof(struct i40e_fdir_filter *) *
1118                                           I40E_MAX_FDIR_FILTER_NUM,
1119                                           0);
1120         if (!fdir_info->hash_map) {
1121                 PMD_INIT_LOG(ERR,
1122                              "Failed to allocate memory for fdir hash map!");
1123                 ret = -ENOMEM;
1124                 goto err_fdir_hash_map_alloc;
1125         }
1126
1127         fdir_info->fdir_filter_array = rte_zmalloc("fdir_filter",
1128                         sizeof(struct i40e_fdir_filter) *
1129                         I40E_MAX_FDIR_FILTER_NUM,
1130                         0);
1131
1132         if (!fdir_info->fdir_filter_array) {
1133                 PMD_INIT_LOG(ERR,
1134                              "Failed to allocate memory for fdir filter array!");
1135                 ret = -ENOMEM;
1136                 goto err_fdir_filter_array_alloc;
1137         }
1138
1139         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
1140              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++)
1141                 pf->fdir.flow_count[pctype] = 0;
1142
1143         fdir_info->fdir_space_size = alloc + best;
1144         fdir_info->fdir_actual_cnt = 0;
1145         fdir_info->fdir_guarantee_total_space = alloc;
1146         fdir_info->fdir_guarantee_free_space =
1147                 fdir_info->fdir_guarantee_total_space;
1148
1149         PMD_DRV_LOG(INFO, "FDIR guarantee space: %u, best_effort space %u.", alloc, best);
1150
1151         fdir_info->fdir_flow_pool.pool =
1152                         rte_zmalloc("i40e_fdir_entry",
1153                                 sizeof(struct i40e_fdir_entry) *
1154                                 fdir_info->fdir_space_size,
1155                                 0);
1156
1157         if (!fdir_info->fdir_flow_pool.pool) {
1158                 PMD_INIT_LOG(ERR,
1159                              "Failed to allocate memory for bitmap flow!");
1160                 ret = -ENOMEM;
1161                 goto err_fdir_bitmap_flow_alloc;
1162         }
1163
1164         for (i = 0; i < fdir_info->fdir_space_size; i++)
1165                 fdir_info->fdir_flow_pool.pool[i].idx = i;
1166
1167         bmp_size =
1168                 rte_bitmap_get_memory_footprint(fdir_info->fdir_space_size);
1169         mem = rte_zmalloc("fdir_bmap", bmp_size, RTE_CACHE_LINE_SIZE);
1170         if (mem == NULL) {
1171                 PMD_INIT_LOG(ERR,
1172                              "Failed to allocate memory for fdir bitmap!");
1173                 ret = -ENOMEM;
1174                 goto err_fdir_mem_alloc;
1175         }
1176         bmp = rte_bitmap_init(fdir_info->fdir_space_size, mem, bmp_size);
1177         if (bmp == NULL) {
1178                 PMD_INIT_LOG(ERR,
1179                              "Failed to initialization fdir bitmap!");
1180                 ret = -ENOMEM;
1181                 goto err_fdir_bmp_alloc;
1182         }
1183         for (i = 0; i < fdir_info->fdir_space_size; i++)
1184                 rte_bitmap_set(bmp, i);
1185
1186         fdir_info->fdir_flow_pool.bitmap = bmp;
1187
1188         return 0;
1189
1190 err_fdir_bmp_alloc:
1191         rte_free(mem);
1192 err_fdir_mem_alloc:
1193         rte_free(fdir_info->fdir_flow_pool.pool);
1194 err_fdir_bitmap_flow_alloc:
1195         rte_free(fdir_info->fdir_filter_array);
1196 err_fdir_filter_array_alloc:
1197         rte_free(fdir_info->hash_map);
1198 err_fdir_hash_map_alloc:
1199         rte_hash_free(fdir_info->hash_table);
1200
1201         return ret;
1202 }
1203
1204 static void
1205 i40e_init_customized_info(struct i40e_pf *pf)
1206 {
1207         int i;
1208
1209         /* Initialize customized pctype */
1210         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1211                 pf->customized_pctype[i].index = i;
1212                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1213                 pf->customized_pctype[i].valid = false;
1214         }
1215
1216         pf->gtp_support = false;
1217         pf->esp_support = false;
1218 }
1219
1220 static void
1221 i40e_init_filter_invalidation(struct i40e_pf *pf)
1222 {
1223         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1224         struct i40e_fdir_info *fdir_info = &pf->fdir;
1225         uint32_t glqf_ctl_reg = 0;
1226
1227         glqf_ctl_reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
1228         if (!pf->support_multi_driver) {
1229                 fdir_info->fdir_invalprio = 1;
1230                 glqf_ctl_reg |= I40E_GLQF_CTL_INVALPRIO_MASK;
1231                 PMD_DRV_LOG(INFO, "FDIR INVALPRIO set to guaranteed first");
1232                 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, glqf_ctl_reg);
1233         } else {
1234                 if (glqf_ctl_reg & I40E_GLQF_CTL_INVALPRIO_MASK) {
1235                         fdir_info->fdir_invalprio = 1;
1236                         PMD_DRV_LOG(INFO, "FDIR INVALPRIO is: guaranteed first");
1237                 } else {
1238                         fdir_info->fdir_invalprio = 0;
1239                         PMD_DRV_LOG(INFO, "FDIR INVALPRIO is: shared first");
1240                 }
1241         }
1242 }
1243
1244 void
1245 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1246 {
1247         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1248         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1249         struct i40e_queue_regions *info = &pf->queue_region;
1250         uint16_t i;
1251
1252         for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1253                 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1254
1255         memset(info, 0, sizeof(struct i40e_queue_regions));
1256 }
1257
1258 static int
1259 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1260                                const char *value,
1261                                void *opaque)
1262 {
1263         struct i40e_pf *pf;
1264         unsigned long support_multi_driver;
1265         char *end;
1266
1267         pf = (struct i40e_pf *)opaque;
1268
1269         errno = 0;
1270         support_multi_driver = strtoul(value, &end, 10);
1271         if (errno != 0 || end == value || *end != 0) {
1272                 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1273                 return -(EINVAL);
1274         }
1275
1276         if (support_multi_driver == 1 || support_multi_driver == 0)
1277                 pf->support_multi_driver = (bool)support_multi_driver;
1278         else
1279                 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1280                             "enable global configuration by default."
1281                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1282         return 0;
1283 }
1284
1285 static int
1286 i40e_support_multi_driver(struct rte_eth_dev *dev)
1287 {
1288         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1289         struct rte_kvargs *kvlist;
1290         int kvargs_count;
1291
1292         /* Enable global configuration by default */
1293         pf->support_multi_driver = false;
1294
1295         if (!dev->device->devargs)
1296                 return 0;
1297
1298         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1299         if (!kvlist)
1300                 return -EINVAL;
1301
1302         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1303         if (!kvargs_count) {
1304                 rte_kvargs_free(kvlist);
1305                 return 0;
1306         }
1307
1308         if (kvargs_count > 1)
1309                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1310                             "the first invalid or last valid one is used !",
1311                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1312
1313         if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1314                                i40e_parse_multi_drv_handler, pf) < 0) {
1315                 rte_kvargs_free(kvlist);
1316                 return -EINVAL;
1317         }
1318
1319         rte_kvargs_free(kvlist);
1320         return 0;
1321 }
1322
1323 static int
1324 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1325                                     uint32_t reg_addr, uint64_t reg_val,
1326                                     struct i40e_asq_cmd_details *cmd_details)
1327 {
1328         uint64_t ori_reg_val;
1329         struct rte_eth_dev *dev;
1330         int ret;
1331
1332         ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1333         if (ret != I40E_SUCCESS) {
1334                 PMD_DRV_LOG(ERR,
1335                             "Fail to debug read from 0x%08x",
1336                             reg_addr);
1337                 return -EIO;
1338         }
1339         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1340
1341         if (ori_reg_val != reg_val)
1342                 PMD_DRV_LOG(WARNING,
1343                             "i40e device %s changed global register [0x%08x]."
1344                             " original: 0x%"PRIx64", after: 0x%"PRIx64,
1345                             dev->device->name, reg_addr, ori_reg_val, reg_val);
1346
1347         return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1348 }
1349
1350 static int
1351 read_vf_msg_config(__rte_unused const char *key,
1352                                const char *value,
1353                                void *opaque)
1354 {
1355         struct i40e_vf_msg_cfg *cfg = opaque;
1356
1357         if (sscanf(value, "%u@%u:%u", &cfg->max_msg, &cfg->period,
1358                         &cfg->ignore_second) != 3) {
1359                 memset(cfg, 0, sizeof(*cfg));
1360                 PMD_DRV_LOG(ERR, "format error! example: "
1361                                 "%s=60@120:180", ETH_I40E_VF_MSG_CFG);
1362                 return -EINVAL;
1363         }
1364
1365         /*
1366          * If the message validation function been enabled, the 'period'
1367          * and 'ignore_second' must greater than 0.
1368          */
1369         if (cfg->max_msg && (!cfg->period || !cfg->ignore_second)) {
1370                 memset(cfg, 0, sizeof(*cfg));
1371                 PMD_DRV_LOG(ERR, "%s error! the second and third"
1372                                 " number must be greater than 0!",
1373                                 ETH_I40E_VF_MSG_CFG);
1374                 return -EINVAL;
1375         }
1376
1377         return 0;
1378 }
1379
1380 static int
1381 i40e_parse_vf_msg_config(struct rte_eth_dev *dev,
1382                 struct i40e_vf_msg_cfg *msg_cfg)
1383 {
1384         struct rte_kvargs *kvlist;
1385         int kvargs_count;
1386         int ret = 0;
1387
1388         memset(msg_cfg, 0, sizeof(*msg_cfg));
1389
1390         if (!dev->device->devargs)
1391                 return ret;
1392
1393         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1394         if (!kvlist)
1395                 return -EINVAL;
1396
1397         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_VF_MSG_CFG);
1398         if (!kvargs_count)
1399                 goto free_end;
1400
1401         if (kvargs_count > 1) {
1402                 PMD_DRV_LOG(ERR, "More than one argument \"%s\"!",
1403                                 ETH_I40E_VF_MSG_CFG);
1404                 ret = -EINVAL;
1405                 goto free_end;
1406         }
1407
1408         if (rte_kvargs_process(kvlist, ETH_I40E_VF_MSG_CFG,
1409                         read_vf_msg_config, msg_cfg) < 0)
1410                 ret = -EINVAL;
1411
1412 free_end:
1413         rte_kvargs_free(kvlist);
1414         return ret;
1415 }
1416
1417 #define I40E_ALARM_INTERVAL 50000 /* us */
1418
1419 static int
1420 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1421 {
1422         struct rte_pci_device *pci_dev;
1423         struct rte_intr_handle *intr_handle;
1424         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1425         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1426         struct i40e_vsi *vsi;
1427         int ret;
1428         uint32_t len, val;
1429         uint8_t aq_fail = 0;
1430
1431         PMD_INIT_FUNC_TRACE();
1432
1433         dev->dev_ops = &i40e_eth_dev_ops;
1434         dev->rx_queue_count = i40e_dev_rx_queue_count;
1435         dev->rx_descriptor_done = i40e_dev_rx_descriptor_done;
1436         dev->rx_descriptor_status = i40e_dev_rx_descriptor_status;
1437         dev->tx_descriptor_status = i40e_dev_tx_descriptor_status;
1438         dev->rx_pkt_burst = i40e_recv_pkts;
1439         dev->tx_pkt_burst = i40e_xmit_pkts;
1440         dev->tx_pkt_prepare = i40e_prep_pkts;
1441
1442         /* for secondary processes, we don't initialise any further as primary
1443          * has already done this work. Only check we don't need a different
1444          * RX function */
1445         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1446                 i40e_set_rx_function(dev);
1447                 i40e_set_tx_function(dev);
1448                 return 0;
1449         }
1450         i40e_set_default_ptype_table(dev);
1451         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1452         intr_handle = &pci_dev->intr_handle;
1453
1454         rte_eth_copy_pci_info(dev, pci_dev);
1455         dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1456
1457         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1458         pf->adapter->eth_dev = dev;
1459         pf->dev_data = dev->data;
1460
1461         hw->back = I40E_PF_TO_ADAPTER(pf);
1462         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1463         if (!hw->hw_addr) {
1464                 PMD_INIT_LOG(ERR,
1465                         "Hardware is not available, as address is NULL");
1466                 return -ENODEV;
1467         }
1468
1469         hw->vendor_id = pci_dev->id.vendor_id;
1470         hw->device_id = pci_dev->id.device_id;
1471         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1472         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1473         hw->bus.device = pci_dev->addr.devid;
1474         hw->bus.func = pci_dev->addr.function;
1475         hw->adapter_stopped = 0;
1476         hw->adapter_closed = 0;
1477
1478         /* Init switch device pointer */
1479         hw->switch_dev = NULL;
1480
1481         /*
1482          * Switch Tag value should not be identical to either the First Tag
1483          * or Second Tag values. So set something other than common Ethertype
1484          * for internal switching.
1485          */
1486         hw->switch_tag = 0xffff;
1487
1488         val = I40E_READ_REG(hw, I40E_GL_FWSTS);
1489         if (val & I40E_GL_FWSTS_FWS1B_MASK) {
1490                 PMD_INIT_LOG(ERR, "\nERROR: "
1491                         "Firmware recovery mode detected. Limiting functionality.\n"
1492                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1493                         "User Guide for details on firmware recovery mode.");
1494                 return -EIO;
1495         }
1496
1497         i40e_parse_vf_msg_config(dev, &pf->vf_msg_cfg);
1498         /* Check if need to support multi-driver */
1499         i40e_support_multi_driver(dev);
1500
1501         /* Make sure all is clean before doing PF reset */
1502         i40e_clear_hw(hw);
1503
1504         /* Reset here to make sure all is clean for each PF */
1505         ret = i40e_pf_reset(hw);
1506         if (ret) {
1507                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1508                 return ret;
1509         }
1510
1511         /* Initialize the shared code (base driver) */
1512         ret = i40e_init_shared_code(hw);
1513         if (ret) {
1514                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1515                 return ret;
1516         }
1517
1518         /* Initialize the parameters for adminq */
1519         i40e_init_adminq_parameter(hw);
1520         ret = i40e_init_adminq(hw);
1521         if (ret != I40E_SUCCESS) {
1522                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1523                 return -EIO;
1524         }
1525         /* Firmware of SFP x722 does not support 802.1ad frames ability */
1526         if (hw->device_id == I40E_DEV_ID_SFP_X722 ||
1527                 hw->device_id == I40E_DEV_ID_SFP_I_X722)
1528                 hw->flags &= ~I40E_HW_FLAG_802_1AD_CAPABLE;
1529
1530         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1531                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1532                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1533                      ((hw->nvm.version >> 12) & 0xf),
1534                      ((hw->nvm.version >> 4) & 0xff),
1535                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1536
1537         /* Initialize the hardware */
1538         i40e_hw_init(dev);
1539
1540         i40e_config_automask(pf);
1541
1542         i40e_set_default_pctype_table(dev);
1543
1544         /*
1545          * To work around the NVM issue, initialize registers
1546          * for packet type of QinQ by software.
1547          * It should be removed once issues are fixed in NVM.
1548          */
1549         if (!pf->support_multi_driver)
1550                 i40e_GLQF_reg_init(hw);
1551
1552         /* Initialize the input set for filters (hash and fd) to default value */
1553         i40e_filter_input_set_init(pf);
1554
1555         /* initialise the L3_MAP register */
1556         if (!pf->support_multi_driver) {
1557                 ret = i40e_aq_debug_write_global_register(hw,
1558                                                    I40E_GLQF_L3_MAP(40),
1559                                                    0x00000028,  NULL);
1560                 if (ret)
1561                         PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1562                                      ret);
1563                 PMD_INIT_LOG(DEBUG,
1564                              "Global register 0x%08x is changed with 0x28",
1565                              I40E_GLQF_L3_MAP(40));
1566         }
1567
1568         /* Need the special FW version to support floating VEB */
1569         config_floating_veb(dev);
1570         /* Clear PXE mode */
1571         i40e_clear_pxe_mode(hw);
1572         i40e_dev_sync_phy_type(hw);
1573
1574         /*
1575          * On X710, performance number is far from the expectation on recent
1576          * firmware versions. The fix for this issue may not be integrated in
1577          * the following firmware version. So the workaround in software driver
1578          * is needed. It needs to modify the initial values of 3 internal only
1579          * registers. Note that the workaround can be removed when it is fixed
1580          * in firmware in the future.
1581          */
1582         i40e_configure_registers(hw);
1583
1584         /* Get hw capabilities */
1585         ret = i40e_get_cap(hw);
1586         if (ret != I40E_SUCCESS) {
1587                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1588                 goto err_get_capabilities;
1589         }
1590
1591         /* Initialize parameters for PF */
1592         ret = i40e_pf_parameter_init(dev);
1593         if (ret != 0) {
1594                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1595                 goto err_parameter_init;
1596         }
1597
1598         /* Initialize the queue management */
1599         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1600         if (ret < 0) {
1601                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1602                 goto err_qp_pool_init;
1603         }
1604         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1605                                 hw->func_caps.num_msix_vectors - 1);
1606         if (ret < 0) {
1607                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1608                 goto err_msix_pool_init;
1609         }
1610
1611         /* Initialize lan hmc */
1612         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1613                                 hw->func_caps.num_rx_qp, 0, 0);
1614         if (ret != I40E_SUCCESS) {
1615                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1616                 goto err_init_lan_hmc;
1617         }
1618
1619         /* Configure lan hmc */
1620         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1621         if (ret != I40E_SUCCESS) {
1622                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1623                 goto err_configure_lan_hmc;
1624         }
1625
1626         /* Get and check the mac address */
1627         i40e_get_mac_addr(hw, hw->mac.addr);
1628         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1629                 PMD_INIT_LOG(ERR, "mac address is not valid");
1630                 ret = -EIO;
1631                 goto err_get_mac_addr;
1632         }
1633         /* Copy the permanent MAC address */
1634         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1635                         (struct rte_ether_addr *)hw->mac.perm_addr);
1636
1637         /* Disable flow control */
1638         hw->fc.requested_mode = I40E_FC_NONE;
1639         i40e_set_fc(hw, &aq_fail, TRUE);
1640
1641         /* Set the global registers with default ether type value */
1642         if (!pf->support_multi_driver) {
1643                 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1644                                          RTE_ETHER_TYPE_VLAN);
1645                 if (ret != I40E_SUCCESS) {
1646                         PMD_INIT_LOG(ERR,
1647                                      "Failed to set the default outer "
1648                                      "VLAN ether type");
1649                         goto err_setup_pf_switch;
1650                 }
1651         }
1652
1653         /* PF setup, which includes VSI setup */
1654         ret = i40e_pf_setup(pf);
1655         if (ret) {
1656                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1657                 goto err_setup_pf_switch;
1658         }
1659
1660         vsi = pf->main_vsi;
1661
1662         /* Disable double vlan by default */
1663         i40e_vsi_config_double_vlan(vsi, FALSE);
1664
1665         /* Disable S-TAG identification when floating_veb is disabled */
1666         if (!pf->floating_veb) {
1667                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1668                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1669                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1670                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1671                 }
1672         }
1673
1674         if (!vsi->max_macaddrs)
1675                 len = RTE_ETHER_ADDR_LEN;
1676         else
1677                 len = RTE_ETHER_ADDR_LEN * vsi->max_macaddrs;
1678
1679         /* Should be after VSI initialized */
1680         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1681         if (!dev->data->mac_addrs) {
1682                 PMD_INIT_LOG(ERR,
1683                         "Failed to allocated memory for storing mac address");
1684                 goto err_mac_alloc;
1685         }
1686         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1687                                         &dev->data->mac_addrs[0]);
1688
1689         /* Init dcb to sw mode by default */
1690         ret = i40e_dcb_init_configure(dev, TRUE);
1691         if (ret != I40E_SUCCESS) {
1692                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1693                 pf->flags &= ~I40E_FLAG_DCB;
1694         }
1695         /* Update HW struct after DCB configuration */
1696         i40e_get_cap(hw);
1697
1698         /* initialize pf host driver to setup SRIOV resource if applicable */
1699         i40e_pf_host_init(dev);
1700
1701         /* register callback func to eal lib */
1702         rte_intr_callback_register(intr_handle,
1703                                    i40e_dev_interrupt_handler, dev);
1704
1705         /* configure and enable device interrupt */
1706         i40e_pf_config_irq0(hw, TRUE);
1707         i40e_pf_enable_irq0(hw);
1708
1709         /* enable uio intr after callback register */
1710         rte_intr_enable(intr_handle);
1711
1712         /* By default disable flexible payload in global configuration */
1713         if (!pf->support_multi_driver)
1714                 i40e_flex_payload_reg_set_default(hw);
1715
1716         /*
1717          * Add an ethertype filter to drop all flow control frames transmitted
1718          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1719          * frames to wire.
1720          */
1721         i40e_add_tx_flow_control_drop_filter(pf);
1722
1723         /* Set the max frame size to 0x2600 by default,
1724          * in case other drivers changed the default value.
1725          */
1726         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, false, 0, NULL);
1727
1728         /* initialize mirror rule list */
1729         TAILQ_INIT(&pf->mirror_list);
1730
1731         /* initialize RSS rule list */
1732         TAILQ_INIT(&pf->rss_config_list);
1733
1734         /* initialize Traffic Manager configuration */
1735         i40e_tm_conf_init(dev);
1736
1737         /* Initialize customized information */
1738         i40e_init_customized_info(pf);
1739
1740         /* Initialize the filter invalidation configuration */
1741         i40e_init_filter_invalidation(pf);
1742
1743         ret = i40e_init_ethtype_filter_list(dev);
1744         if (ret < 0)
1745                 goto err_init_ethtype_filter_list;
1746         ret = i40e_init_tunnel_filter_list(dev);
1747         if (ret < 0)
1748                 goto err_init_tunnel_filter_list;
1749         ret = i40e_init_fdir_filter_list(dev);
1750         if (ret < 0)
1751                 goto err_init_fdir_filter_list;
1752
1753         /* initialize queue region configuration */
1754         i40e_init_queue_region_conf(dev);
1755
1756         /* reset all stats of the device, including pf and main vsi */
1757         i40e_dev_stats_reset(dev);
1758
1759         return 0;
1760
1761 err_init_fdir_filter_list:
1762         rte_free(pf->tunnel.hash_table);
1763         rte_free(pf->tunnel.hash_map);
1764 err_init_tunnel_filter_list:
1765         rte_free(pf->ethertype.hash_table);
1766         rte_free(pf->ethertype.hash_map);
1767 err_init_ethtype_filter_list:
1768         rte_free(dev->data->mac_addrs);
1769         dev->data->mac_addrs = NULL;
1770 err_mac_alloc:
1771         i40e_vsi_release(pf->main_vsi);
1772 err_setup_pf_switch:
1773 err_get_mac_addr:
1774 err_configure_lan_hmc:
1775         (void)i40e_shutdown_lan_hmc(hw);
1776 err_init_lan_hmc:
1777         i40e_res_pool_destroy(&pf->msix_pool);
1778 err_msix_pool_init:
1779         i40e_res_pool_destroy(&pf->qp_pool);
1780 err_qp_pool_init:
1781 err_parameter_init:
1782 err_get_capabilities:
1783         (void)i40e_shutdown_adminq(hw);
1784
1785         return ret;
1786 }
1787
1788 static void
1789 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1790 {
1791         struct i40e_ethertype_filter *p_ethertype;
1792         struct i40e_ethertype_rule *ethertype_rule;
1793
1794         ethertype_rule = &pf->ethertype;
1795         /* Remove all ethertype filter rules and hash */
1796         if (ethertype_rule->hash_map)
1797                 rte_free(ethertype_rule->hash_map);
1798         if (ethertype_rule->hash_table)
1799                 rte_hash_free(ethertype_rule->hash_table);
1800
1801         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1802                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1803                              p_ethertype, rules);
1804                 rte_free(p_ethertype);
1805         }
1806 }
1807
1808 static void
1809 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1810 {
1811         struct i40e_tunnel_filter *p_tunnel;
1812         struct i40e_tunnel_rule *tunnel_rule;
1813
1814         tunnel_rule = &pf->tunnel;
1815         /* Remove all tunnel director rules and hash */
1816         if (tunnel_rule->hash_map)
1817                 rte_free(tunnel_rule->hash_map);
1818         if (tunnel_rule->hash_table)
1819                 rte_hash_free(tunnel_rule->hash_table);
1820
1821         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1822                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1823                 rte_free(p_tunnel);
1824         }
1825 }
1826
1827 static void
1828 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1829 {
1830         struct i40e_fdir_filter *p_fdir;
1831         struct i40e_fdir_info *fdir_info;
1832
1833         fdir_info = &pf->fdir;
1834
1835         /* Remove all flow director rules */
1836         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list)))
1837                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1838 }
1839
1840 static void
1841 i40e_fdir_memory_cleanup(struct i40e_pf *pf)
1842 {
1843         struct i40e_fdir_info *fdir_info;
1844
1845         fdir_info = &pf->fdir;
1846
1847         /* flow director memory cleanup */
1848         if (fdir_info->hash_map)
1849                 rte_free(fdir_info->hash_map);
1850         if (fdir_info->hash_table)
1851                 rte_hash_free(fdir_info->hash_table);
1852         if (fdir_info->fdir_flow_pool.bitmap)
1853                 rte_free(fdir_info->fdir_flow_pool.bitmap);
1854         if (fdir_info->fdir_flow_pool.pool)
1855                 rte_free(fdir_info->fdir_flow_pool.pool);
1856         if (fdir_info->fdir_filter_array)
1857                 rte_free(fdir_info->fdir_filter_array);
1858 }
1859
1860 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1861 {
1862         /*
1863          * Disable by default flexible payload
1864          * for corresponding L2/L3/L4 layers.
1865          */
1866         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1867         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1868         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1869 }
1870
1871 static int
1872 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1873 {
1874         struct i40e_hw *hw;
1875
1876         PMD_INIT_FUNC_TRACE();
1877
1878         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1879                 return 0;
1880
1881         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1882
1883         if (hw->adapter_closed == 0)
1884                 i40e_dev_close(dev);
1885
1886         return 0;
1887 }
1888
1889 static int
1890 i40e_dev_configure(struct rte_eth_dev *dev)
1891 {
1892         struct i40e_adapter *ad =
1893                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1894         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1895         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1896         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1897         int i, ret;
1898
1899         ret = i40e_dev_sync_phy_type(hw);
1900         if (ret)
1901                 return ret;
1902
1903         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1904          * bulk allocation or vector Rx preconditions we will reset it.
1905          */
1906         ad->rx_bulk_alloc_allowed = true;
1907         ad->rx_vec_allowed = true;
1908         ad->tx_simple_allowed = true;
1909         ad->tx_vec_allowed = true;
1910
1911         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1912                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1913
1914         /* Only legacy filter API needs the following fdir config. So when the
1915          * legacy filter API is deprecated, the following codes should also be
1916          * removed.
1917          */
1918         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1919                 ret = i40e_fdir_setup(pf);
1920                 if (ret != I40E_SUCCESS) {
1921                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1922                         return -ENOTSUP;
1923                 }
1924                 ret = i40e_fdir_configure(dev);
1925                 if (ret < 0) {
1926                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1927                         goto err;
1928                 }
1929         } else
1930                 i40e_fdir_teardown(pf);
1931
1932         ret = i40e_dev_init_vlan(dev);
1933         if (ret < 0)
1934                 goto err;
1935
1936         /* VMDQ setup.
1937          *  General PMD driver call sequence are NIC init, configure,
1938          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1939          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1940          *  applicable. So, VMDQ setting has to be done before
1941          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1942          *  For RSS setting, it will try to calculate actual configured RX queue
1943          *  number, which will be available after rx_queue_setup(). dev_start()
1944          *  function is good to place RSS setup.
1945          */
1946         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1947                 ret = i40e_vmdq_setup(dev);
1948                 if (ret)
1949                         goto err;
1950         }
1951
1952         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1953                 ret = i40e_dcb_setup(dev);
1954                 if (ret) {
1955                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1956                         goto err_dcb;
1957                 }
1958         }
1959
1960         TAILQ_INIT(&pf->flow_list);
1961
1962         return 0;
1963
1964 err_dcb:
1965         /* need to release vmdq resource if exists */
1966         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1967                 i40e_vsi_release(pf->vmdq[i].vsi);
1968                 pf->vmdq[i].vsi = NULL;
1969         }
1970         rte_free(pf->vmdq);
1971         pf->vmdq = NULL;
1972 err:
1973         /* Need to release fdir resource if exists.
1974          * Only legacy filter API needs the following fdir config. So when the
1975          * legacy filter API is deprecated, the following code should also be
1976          * removed.
1977          */
1978         i40e_fdir_teardown(pf);
1979         return ret;
1980 }
1981
1982 void
1983 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1984 {
1985         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1986         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1987         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1988         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1989         uint16_t msix_vect = vsi->msix_intr;
1990         uint16_t i;
1991
1992         for (i = 0; i < vsi->nb_qps; i++) {
1993                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1994                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1995                 rte_wmb();
1996         }
1997
1998         if (vsi->type != I40E_VSI_SRIOV) {
1999                 if (!rte_intr_allow_others(intr_handle)) {
2000                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
2001                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
2002                         I40E_WRITE_REG(hw,
2003                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
2004                                        0);
2005                 } else {
2006                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
2007                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
2008                         I40E_WRITE_REG(hw,
2009                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
2010                                                        msix_vect - 1), 0);
2011                 }
2012         } else {
2013                 uint32_t reg;
2014                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
2015                         vsi->user_param + (msix_vect - 1);
2016
2017                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
2018                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
2019         }
2020         I40E_WRITE_FLUSH(hw);
2021 }
2022
2023 static void
2024 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
2025                        int base_queue, int nb_queue,
2026                        uint16_t itr_idx)
2027 {
2028         int i;
2029         uint32_t val;
2030         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2031         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2032
2033         /* Bind all RX queues to allocated MSIX interrupt */
2034         for (i = 0; i < nb_queue; i++) {
2035                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2036                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
2037                         ((base_queue + i + 1) <<
2038                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
2039                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
2040                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
2041
2042                 if (i == nb_queue - 1)
2043                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
2044                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
2045         }
2046
2047         /* Write first RX queue to Link list register as the head element */
2048         if (vsi->type != I40E_VSI_SRIOV) {
2049                 uint16_t interval =
2050                         i40e_calc_itr_interval(1, pf->support_multi_driver);
2051
2052                 if (msix_vect == I40E_MISC_VEC_ID) {
2053                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
2054                                        (base_queue <<
2055                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
2056                                        (0x0 <<
2057                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
2058                         I40E_WRITE_REG(hw,
2059                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
2060                                        interval);
2061                 } else {
2062                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
2063                                        (base_queue <<
2064                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
2065                                        (0x0 <<
2066                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2067                         I40E_WRITE_REG(hw,
2068                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
2069                                                        msix_vect - 1),
2070                                        interval);
2071                 }
2072         } else {
2073                 uint32_t reg;
2074
2075                 if (msix_vect == I40E_MISC_VEC_ID) {
2076                         I40E_WRITE_REG(hw,
2077                                        I40E_VPINT_LNKLST0(vsi->user_param),
2078                                        (base_queue <<
2079                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
2080                                        (0x0 <<
2081                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
2082                 } else {
2083                         /* num_msix_vectors_vf needs to minus irq0 */
2084                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
2085                                 vsi->user_param + (msix_vect - 1);
2086
2087                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
2088                                        (base_queue <<
2089                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
2090                                        (0x0 <<
2091                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2092                 }
2093         }
2094
2095         I40E_WRITE_FLUSH(hw);
2096 }
2097
2098 int
2099 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
2100 {
2101         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2102         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2103         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2104         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2105         uint16_t msix_vect = vsi->msix_intr;
2106         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2107         uint16_t queue_idx = 0;
2108         int record = 0;
2109         int i;
2110
2111         for (i = 0; i < vsi->nb_qps; i++) {
2112                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
2113                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2114         }
2115
2116         /* VF bind interrupt */
2117         if (vsi->type == I40E_VSI_SRIOV) {
2118                 if (vsi->nb_msix == 0) {
2119                         PMD_DRV_LOG(ERR, "No msix resource");
2120                         return -EINVAL;
2121                 }
2122                 __vsi_queues_bind_intr(vsi, msix_vect,
2123                                        vsi->base_queue, vsi->nb_qps,
2124                                        itr_idx);
2125                 return 0;
2126         }
2127
2128         /* PF & VMDq bind interrupt */
2129         if (rte_intr_dp_is_en(intr_handle)) {
2130                 if (vsi->type == I40E_VSI_MAIN) {
2131                         queue_idx = 0;
2132                         record = 1;
2133                 } else if (vsi->type == I40E_VSI_VMDQ2) {
2134                         struct i40e_vsi *main_vsi =
2135                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2136                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
2137                         record = 1;
2138                 }
2139         }
2140
2141         for (i = 0; i < vsi->nb_used_qps; i++) {
2142                 if (vsi->nb_msix == 0) {
2143                         PMD_DRV_LOG(ERR, "No msix resource");
2144                         return -EINVAL;
2145                 } else if (nb_msix <= 1) {
2146                         if (!rte_intr_allow_others(intr_handle))
2147                                 /* allow to share MISC_VEC_ID */
2148                                 msix_vect = I40E_MISC_VEC_ID;
2149
2150                         /* no enough msix_vect, map all to one */
2151                         __vsi_queues_bind_intr(vsi, msix_vect,
2152                                                vsi->base_queue + i,
2153                                                vsi->nb_used_qps - i,
2154                                                itr_idx);
2155                         for (; !!record && i < vsi->nb_used_qps; i++)
2156                                 intr_handle->intr_vec[queue_idx + i] =
2157                                         msix_vect;
2158                         break;
2159                 }
2160                 /* 1:1 queue/msix_vect mapping */
2161                 __vsi_queues_bind_intr(vsi, msix_vect,
2162                                        vsi->base_queue + i, 1,
2163                                        itr_idx);
2164                 if (!!record)
2165                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
2166
2167                 msix_vect++;
2168                 nb_msix--;
2169         }
2170
2171         return 0;
2172 }
2173
2174 void
2175 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2176 {
2177         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2178         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2179         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2180         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2181         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2182         uint16_t msix_intr, i;
2183
2184         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2185                 for (i = 0; i < vsi->nb_msix; i++) {
2186                         msix_intr = vsi->msix_intr + i;
2187                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2188                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2189                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2190                                 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2191                 }
2192         else
2193                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2194                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
2195                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2196                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2197
2198         I40E_WRITE_FLUSH(hw);
2199 }
2200
2201 void
2202 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2203 {
2204         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2205         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2206         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2207         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2208         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2209         uint16_t msix_intr, i;
2210
2211         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2212                 for (i = 0; i < vsi->nb_msix; i++) {
2213                         msix_intr = vsi->msix_intr + i;
2214                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2215                                        I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2216                 }
2217         else
2218                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2219                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2220
2221         I40E_WRITE_FLUSH(hw);
2222 }
2223
2224 static inline uint8_t
2225 i40e_parse_link_speeds(uint16_t link_speeds)
2226 {
2227         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2228
2229         if (link_speeds & ETH_LINK_SPEED_40G)
2230                 link_speed |= I40E_LINK_SPEED_40GB;
2231         if (link_speeds & ETH_LINK_SPEED_25G)
2232                 link_speed |= I40E_LINK_SPEED_25GB;
2233         if (link_speeds & ETH_LINK_SPEED_20G)
2234                 link_speed |= I40E_LINK_SPEED_20GB;
2235         if (link_speeds & ETH_LINK_SPEED_10G)
2236                 link_speed |= I40E_LINK_SPEED_10GB;
2237         if (link_speeds & ETH_LINK_SPEED_1G)
2238                 link_speed |= I40E_LINK_SPEED_1GB;
2239         if (link_speeds & ETH_LINK_SPEED_100M)
2240                 link_speed |= I40E_LINK_SPEED_100MB;
2241
2242         return link_speed;
2243 }
2244
2245 static int
2246 i40e_phy_conf_link(struct i40e_hw *hw,
2247                    uint8_t abilities,
2248                    uint8_t force_speed,
2249                    bool is_up)
2250 {
2251         enum i40e_status_code status;
2252         struct i40e_aq_get_phy_abilities_resp phy_ab;
2253         struct i40e_aq_set_phy_config phy_conf;
2254         enum i40e_aq_phy_type cnt;
2255         uint8_t avail_speed;
2256         uint32_t phy_type_mask = 0;
2257
2258         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2259                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2260                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2261                         I40E_AQ_PHY_FLAG_LOW_POWER;
2262         int ret = -ENOTSUP;
2263
2264         /* To get phy capabilities of available speeds. */
2265         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2266                                               NULL);
2267         if (status) {
2268                 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2269                                 status);
2270                 return ret;
2271         }
2272         avail_speed = phy_ab.link_speed;
2273
2274         /* To get the current phy config. */
2275         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2276                                               NULL);
2277         if (status) {
2278                 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2279                                 status);
2280                 return ret;
2281         }
2282
2283         /* If link needs to go up and it is in autoneg mode the speed is OK,
2284          * no need to set up again.
2285          */
2286         if (is_up && phy_ab.phy_type != 0 &&
2287                      abilities & I40E_AQ_PHY_AN_ENABLED &&
2288                      phy_ab.link_speed != 0)
2289                 return I40E_SUCCESS;
2290
2291         memset(&phy_conf, 0, sizeof(phy_conf));
2292
2293         /* bits 0-2 use the values from get_phy_abilities_resp */
2294         abilities &= ~mask;
2295         abilities |= phy_ab.abilities & mask;
2296
2297         phy_conf.abilities = abilities;
2298
2299         /* If link needs to go up, but the force speed is not supported,
2300          * Warn users and config the default available speeds.
2301          */
2302         if (is_up && !(force_speed & avail_speed)) {
2303                 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2304                 phy_conf.link_speed = avail_speed;
2305         } else {
2306                 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2307         }
2308
2309         /* PHY type mask needs to include each type except PHY type extension */
2310         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2311                 phy_type_mask |= 1 << cnt;
2312
2313         /* use get_phy_abilities_resp value for the rest */
2314         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2315         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2316                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2317                 I40E_AQ_PHY_TYPE_EXT_25G_LR | I40E_AQ_PHY_TYPE_EXT_25G_AOC |
2318                 I40E_AQ_PHY_TYPE_EXT_25G_ACC) : 0;
2319         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2320         phy_conf.eee_capability = phy_ab.eee_capability;
2321         phy_conf.eeer = phy_ab.eeer_val;
2322         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2323
2324         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2325                     phy_ab.abilities, phy_ab.link_speed);
2326         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
2327                     phy_conf.abilities, phy_conf.link_speed);
2328
2329         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2330         if (status)
2331                 return ret;
2332
2333         return I40E_SUCCESS;
2334 }
2335
2336 static int
2337 i40e_apply_link_speed(struct rte_eth_dev *dev)
2338 {
2339         uint8_t speed;
2340         uint8_t abilities = 0;
2341         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2342         struct rte_eth_conf *conf = &dev->data->dev_conf;
2343
2344         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2345                      I40E_AQ_PHY_LINK_ENABLED;
2346
2347         if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2348                 conf->link_speeds = ETH_LINK_SPEED_40G |
2349                                     ETH_LINK_SPEED_25G |
2350                                     ETH_LINK_SPEED_20G |
2351                                     ETH_LINK_SPEED_10G |
2352                                     ETH_LINK_SPEED_1G |
2353                                     ETH_LINK_SPEED_100M;
2354
2355                 abilities |= I40E_AQ_PHY_AN_ENABLED;
2356         } else {
2357                 abilities &= ~I40E_AQ_PHY_AN_ENABLED;
2358         }
2359         speed = i40e_parse_link_speeds(conf->link_speeds);
2360
2361         return i40e_phy_conf_link(hw, abilities, speed, true);
2362 }
2363
2364 static int
2365 i40e_dev_start(struct rte_eth_dev *dev)
2366 {
2367         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2368         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2369         struct i40e_vsi *main_vsi = pf->main_vsi;
2370         int ret, i;
2371         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2372         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2373         uint32_t intr_vector = 0;
2374         struct i40e_vsi *vsi;
2375         uint16_t nb_rxq, nb_txq;
2376
2377         hw->adapter_stopped = 0;
2378
2379         rte_intr_disable(intr_handle);
2380
2381         if ((rte_intr_cap_multiple(intr_handle) ||
2382              !RTE_ETH_DEV_SRIOV(dev).active) &&
2383             dev->data->dev_conf.intr_conf.rxq != 0) {
2384                 intr_vector = dev->data->nb_rx_queues;
2385                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2386                 if (ret)
2387                         return ret;
2388         }
2389
2390         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2391                 intr_handle->intr_vec =
2392                         rte_zmalloc("intr_vec",
2393                                     dev->data->nb_rx_queues * sizeof(int),
2394                                     0);
2395                 if (!intr_handle->intr_vec) {
2396                         PMD_INIT_LOG(ERR,
2397                                 "Failed to allocate %d rx_queues intr_vec",
2398                                 dev->data->nb_rx_queues);
2399                         return -ENOMEM;
2400                 }
2401         }
2402
2403         /* Initialize VSI */
2404         ret = i40e_dev_rxtx_init(pf);
2405         if (ret != I40E_SUCCESS) {
2406                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2407                 return ret;
2408         }
2409
2410         /* Map queues with MSIX interrupt */
2411         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2412                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2413         ret = i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2414         if (ret < 0)
2415                 return ret;
2416         i40e_vsi_enable_queues_intr(main_vsi);
2417
2418         /* Map VMDQ VSI queues with MSIX interrupt */
2419         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2420                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2421                 ret = i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2422                                                 I40E_ITR_INDEX_DEFAULT);
2423                 if (ret < 0)
2424                         return ret;
2425                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2426         }
2427
2428         /* Enable all queues which have been configured */
2429         for (nb_rxq = 0; nb_rxq < dev->data->nb_rx_queues; nb_rxq++) {
2430                 ret = i40e_dev_rx_queue_start(dev, nb_rxq);
2431                 if (ret)
2432                         goto rx_err;
2433         }
2434
2435         for (nb_txq = 0; nb_txq < dev->data->nb_tx_queues; nb_txq++) {
2436                 ret = i40e_dev_tx_queue_start(dev, nb_txq);
2437                 if (ret)
2438                         goto tx_err;
2439         }
2440
2441         /* Enable receiving broadcast packets */
2442         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2443         if (ret != I40E_SUCCESS)
2444                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2445
2446         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2447                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2448                                                 true, NULL);
2449                 if (ret != I40E_SUCCESS)
2450                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2451         }
2452
2453         /* Enable the VLAN promiscuous mode. */
2454         if (pf->vfs) {
2455                 for (i = 0; i < pf->vf_num; i++) {
2456                         vsi = pf->vfs[i].vsi;
2457                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2458                                                      true, NULL);
2459                 }
2460         }
2461
2462         /* Enable mac loopback mode */
2463         if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2464             dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2465                 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2466                 if (ret != I40E_SUCCESS) {
2467                         PMD_DRV_LOG(ERR, "fail to set loopback link");
2468                         goto tx_err;
2469                 }
2470         }
2471
2472         /* Apply link configure */
2473         ret = i40e_apply_link_speed(dev);
2474         if (I40E_SUCCESS != ret) {
2475                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2476                 goto tx_err;
2477         }
2478
2479         if (!rte_intr_allow_others(intr_handle)) {
2480                 rte_intr_callback_unregister(intr_handle,
2481                                              i40e_dev_interrupt_handler,
2482                                              (void *)dev);
2483                 /* configure and enable device interrupt */
2484                 i40e_pf_config_irq0(hw, FALSE);
2485                 i40e_pf_enable_irq0(hw);
2486
2487                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2488                         PMD_INIT_LOG(INFO,
2489                                 "lsc won't enable because of no intr multiplex");
2490         } else {
2491                 ret = i40e_aq_set_phy_int_mask(hw,
2492                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2493                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2494                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2495                 if (ret != I40E_SUCCESS)
2496                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2497
2498                 /* Call get_link_info aq commond to enable/disable LSE */
2499                 i40e_dev_link_update(dev, 0);
2500         }
2501
2502         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2503                 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2504                                   i40e_dev_alarm_handler, dev);
2505         } else {
2506                 /* enable uio intr after callback register */
2507                 rte_intr_enable(intr_handle);
2508         }
2509
2510         i40e_filter_restore(pf);
2511
2512         if (pf->tm_conf.root && !pf->tm_conf.committed)
2513                 PMD_DRV_LOG(WARNING,
2514                             "please call hierarchy_commit() "
2515                             "before starting the port");
2516
2517         return I40E_SUCCESS;
2518
2519 tx_err:
2520         for (i = 0; i < nb_txq; i++)
2521                 i40e_dev_tx_queue_stop(dev, i);
2522 rx_err:
2523         for (i = 0; i < nb_rxq; i++)
2524                 i40e_dev_rx_queue_stop(dev, i);
2525
2526         return ret;
2527 }
2528
2529 static int
2530 i40e_dev_stop(struct rte_eth_dev *dev)
2531 {
2532         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2533         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2534         struct i40e_vsi *main_vsi = pf->main_vsi;
2535         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2536         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2537         int i;
2538
2539         if (hw->adapter_stopped == 1)
2540                 return 0;
2541
2542         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2543                 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2544                 rte_intr_enable(intr_handle);
2545         }
2546
2547         /* Disable all queues */
2548         for (i = 0; i < dev->data->nb_tx_queues; i++)
2549                 i40e_dev_tx_queue_stop(dev, i);
2550
2551         for (i = 0; i < dev->data->nb_rx_queues; i++)
2552                 i40e_dev_rx_queue_stop(dev, i);
2553
2554         /* un-map queues with interrupt registers */
2555         i40e_vsi_disable_queues_intr(main_vsi);
2556         i40e_vsi_queues_unbind_intr(main_vsi);
2557
2558         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2559                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2560                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2561         }
2562
2563         /* Clear all queues and release memory */
2564         i40e_dev_clear_queues(dev);
2565
2566         /* Set link down */
2567         i40e_dev_set_link_down(dev);
2568
2569         if (!rte_intr_allow_others(intr_handle))
2570                 /* resume to the default handler */
2571                 rte_intr_callback_register(intr_handle,
2572                                            i40e_dev_interrupt_handler,
2573                                            (void *)dev);
2574
2575         /* Clean datapath event and queue/vec mapping */
2576         rte_intr_efd_disable(intr_handle);
2577         if (intr_handle->intr_vec) {
2578                 rte_free(intr_handle->intr_vec);
2579                 intr_handle->intr_vec = NULL;
2580         }
2581
2582         /* reset hierarchy commit */
2583         pf->tm_conf.committed = false;
2584
2585         hw->adapter_stopped = 1;
2586         dev->data->dev_started = 0;
2587
2588         pf->adapter->rss_reta_updated = 0;
2589
2590         return 0;
2591 }
2592
2593 static int
2594 i40e_dev_close(struct rte_eth_dev *dev)
2595 {
2596         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2597         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2598         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2599         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2600         struct i40e_mirror_rule *p_mirror;
2601         struct i40e_filter_control_settings settings;
2602         struct rte_flow *p_flow;
2603         uint32_t reg;
2604         int i;
2605         int ret;
2606         uint8_t aq_fail = 0;
2607         int retries = 0;
2608
2609         PMD_INIT_FUNC_TRACE();
2610         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2611                 return 0;
2612
2613         ret = rte_eth_switch_domain_free(pf->switch_domain_id);
2614         if (ret)
2615                 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
2616
2617
2618         ret = i40e_dev_stop(dev);
2619
2620         /* Remove all mirror rules */
2621         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2622                 ret = i40e_aq_del_mirror_rule(hw,
2623                                               pf->main_vsi->veb->seid,
2624                                               p_mirror->rule_type,
2625                                               p_mirror->entries,
2626                                               p_mirror->num_entries,
2627                                               p_mirror->id);
2628                 if (ret < 0)
2629                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2630                                     "status = %d, aq_err = %d.", ret,
2631                                     hw->aq.asq_last_status);
2632
2633                 /* remove mirror software resource anyway */
2634                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2635                 rte_free(p_mirror);
2636                 pf->nb_mirror_rule--;
2637         }
2638
2639         i40e_dev_free_queues(dev);
2640
2641         /* Disable interrupt */
2642         i40e_pf_disable_irq0(hw);
2643         rte_intr_disable(intr_handle);
2644
2645         /*
2646          * Only legacy filter API needs the following fdir config. So when the
2647          * legacy filter API is deprecated, the following code should also be
2648          * removed.
2649          */
2650         i40e_fdir_teardown(pf);
2651
2652         /* shutdown and destroy the HMC */
2653         i40e_shutdown_lan_hmc(hw);
2654
2655         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2656                 i40e_vsi_release(pf->vmdq[i].vsi);
2657                 pf->vmdq[i].vsi = NULL;
2658         }
2659         rte_free(pf->vmdq);
2660         pf->vmdq = NULL;
2661
2662         /* release all the existing VSIs and VEBs */
2663         i40e_vsi_release(pf->main_vsi);
2664
2665         /* shutdown the adminq */
2666         i40e_aq_queue_shutdown(hw, true);
2667         i40e_shutdown_adminq(hw);
2668
2669         i40e_res_pool_destroy(&pf->qp_pool);
2670         i40e_res_pool_destroy(&pf->msix_pool);
2671
2672         /* Disable flexible payload in global configuration */
2673         if (!pf->support_multi_driver)
2674                 i40e_flex_payload_reg_set_default(hw);
2675
2676         /* force a PF reset to clean anything leftover */
2677         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2678         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2679                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2680         I40E_WRITE_FLUSH(hw);
2681
2682         /* Clear PXE mode */
2683         i40e_clear_pxe_mode(hw);
2684
2685         /* Unconfigure filter control */
2686         memset(&settings, 0, sizeof(settings));
2687         ret = i40e_set_filter_control(hw, &settings);
2688         if (ret)
2689                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
2690                                         ret);
2691
2692         /* Disable flow control */
2693         hw->fc.requested_mode = I40E_FC_NONE;
2694         i40e_set_fc(hw, &aq_fail, TRUE);
2695
2696         /* uninitialize pf host driver */
2697         i40e_pf_host_uninit(dev);
2698
2699         do {
2700                 ret = rte_intr_callback_unregister(intr_handle,
2701                                 i40e_dev_interrupt_handler, dev);
2702                 if (ret >= 0 || ret == -ENOENT) {
2703                         break;
2704                 } else if (ret != -EAGAIN) {
2705                         PMD_INIT_LOG(ERR,
2706                                  "intr callback unregister failed: %d",
2707                                  ret);
2708                 }
2709                 i40e_msec_delay(500);
2710         } while (retries++ < 5);
2711
2712         i40e_rm_ethtype_filter_list(pf);
2713         i40e_rm_tunnel_filter_list(pf);
2714         i40e_rm_fdir_filter_list(pf);
2715
2716         /* Remove all flows */
2717         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
2718                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
2719                 /* Do not free FDIR flows since they are static allocated */
2720                 if (p_flow->filter_type != RTE_ETH_FILTER_FDIR)
2721                         rte_free(p_flow);
2722         }
2723
2724         /* release the fdir static allocated memory */
2725         i40e_fdir_memory_cleanup(pf);
2726
2727         /* Remove all Traffic Manager configuration */
2728         i40e_tm_conf_uninit(dev);
2729
2730         i40e_clear_automask(pf);
2731
2732         hw->adapter_closed = 1;
2733         return ret;
2734 }
2735
2736 /*
2737  * Reset PF device only to re-initialize resources in PMD layer
2738  */
2739 static int
2740 i40e_dev_reset(struct rte_eth_dev *dev)
2741 {
2742         int ret;
2743
2744         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2745          * its VF to make them align with it. The detailed notification
2746          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2747          * To avoid unexpected behavior in VF, currently reset of PF with
2748          * SR-IOV activation is not supported. It might be supported later.
2749          */
2750         if (dev->data->sriov.active)
2751                 return -ENOTSUP;
2752
2753         ret = eth_i40e_dev_uninit(dev);
2754         if (ret)
2755                 return ret;
2756
2757         ret = eth_i40e_dev_init(dev, NULL);
2758
2759         return ret;
2760 }
2761
2762 static int
2763 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2764 {
2765         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2766         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2767         struct i40e_vsi *vsi = pf->main_vsi;
2768         int status;
2769
2770         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2771                                                      true, NULL, true);
2772         if (status != I40E_SUCCESS) {
2773                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2774                 return -EAGAIN;
2775         }
2776
2777         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2778                                                         TRUE, NULL);
2779         if (status != I40E_SUCCESS) {
2780                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2781                 /* Rollback unicast promiscuous mode */
2782                 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2783                                                     false, NULL, true);
2784                 return -EAGAIN;
2785         }
2786
2787         return 0;
2788 }
2789
2790 static int
2791 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2792 {
2793         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2794         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2795         struct i40e_vsi *vsi = pf->main_vsi;
2796         int status;
2797
2798         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2799                                                      false, NULL, true);
2800         if (status != I40E_SUCCESS) {
2801                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2802                 return -EAGAIN;
2803         }
2804
2805         /* must remain in all_multicast mode */
2806         if (dev->data->all_multicast == 1)
2807                 return 0;
2808
2809         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2810                                                         false, NULL);
2811         if (status != I40E_SUCCESS) {
2812                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2813                 /* Rollback unicast promiscuous mode */
2814                 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2815                                                     true, NULL, true);
2816                 return -EAGAIN;
2817         }
2818
2819         return 0;
2820 }
2821
2822 static int
2823 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2824 {
2825         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2826         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2827         struct i40e_vsi *vsi = pf->main_vsi;
2828         int ret;
2829
2830         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2831         if (ret != I40E_SUCCESS) {
2832                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2833                 return -EAGAIN;
2834         }
2835
2836         return 0;
2837 }
2838
2839 static int
2840 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2841 {
2842         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2843         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2844         struct i40e_vsi *vsi = pf->main_vsi;
2845         int ret;
2846
2847         if (dev->data->promiscuous == 1)
2848                 return 0; /* must remain in all_multicast mode */
2849
2850         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2851                                 vsi->seid, FALSE, NULL);
2852         if (ret != I40E_SUCCESS) {
2853                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2854                 return -EAGAIN;
2855         }
2856
2857         return 0;
2858 }
2859
2860 /*
2861  * Set device link up.
2862  */
2863 static int
2864 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2865 {
2866         /* re-apply link speed setting */
2867         return i40e_apply_link_speed(dev);
2868 }
2869
2870 /*
2871  * Set device link down.
2872  */
2873 static int
2874 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2875 {
2876         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2877         uint8_t abilities = 0;
2878         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2879
2880         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2881         return i40e_phy_conf_link(hw, abilities, speed, false);
2882 }
2883
2884 static __rte_always_inline void
2885 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2886 {
2887 /* Link status registers and values*/
2888 #define I40E_PRTMAC_LINKSTA             0x001E2420
2889 #define I40E_REG_LINK_UP                0x40000080
2890 #define I40E_PRTMAC_MACC                0x001E24E0
2891 #define I40E_REG_MACC_25GB              0x00020000
2892 #define I40E_REG_SPEED_MASK             0x38000000
2893 #define I40E_REG_SPEED_0                0x00000000
2894 #define I40E_REG_SPEED_1                0x08000000
2895 #define I40E_REG_SPEED_2                0x10000000
2896 #define I40E_REG_SPEED_3                0x18000000
2897 #define I40E_REG_SPEED_4                0x20000000
2898         uint32_t link_speed;
2899         uint32_t reg_val;
2900
2901         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2902         link_speed = reg_val & I40E_REG_SPEED_MASK;
2903         reg_val &= I40E_REG_LINK_UP;
2904         link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2905
2906         if (unlikely(link->link_status == 0))
2907                 return;
2908
2909         /* Parse the link status */
2910         switch (link_speed) {
2911         case I40E_REG_SPEED_0:
2912                 link->link_speed = ETH_SPEED_NUM_100M;
2913                 break;
2914         case I40E_REG_SPEED_1:
2915                 link->link_speed = ETH_SPEED_NUM_1G;
2916                 break;
2917         case I40E_REG_SPEED_2:
2918                 if (hw->mac.type == I40E_MAC_X722)
2919                         link->link_speed = ETH_SPEED_NUM_2_5G;
2920                 else
2921                         link->link_speed = ETH_SPEED_NUM_10G;
2922                 break;
2923         case I40E_REG_SPEED_3:
2924                 if (hw->mac.type == I40E_MAC_X722) {
2925                         link->link_speed = ETH_SPEED_NUM_5G;
2926                 } else {
2927                         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2928
2929                         if (reg_val & I40E_REG_MACC_25GB)
2930                                 link->link_speed = ETH_SPEED_NUM_25G;
2931                         else
2932                                 link->link_speed = ETH_SPEED_NUM_40G;
2933                 }
2934                 break;
2935         case I40E_REG_SPEED_4:
2936                 if (hw->mac.type == I40E_MAC_X722)
2937                         link->link_speed = ETH_SPEED_NUM_10G;
2938                 else
2939                         link->link_speed = ETH_SPEED_NUM_20G;
2940                 break;
2941         default:
2942                 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2943                 break;
2944         }
2945 }
2946
2947 static __rte_always_inline void
2948 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2949         bool enable_lse, int wait_to_complete)
2950 {
2951 #define CHECK_INTERVAL             100  /* 100ms */
2952 #define MAX_REPEAT_TIME            10  /* 1s (10 * 100ms) in total */
2953         uint32_t rep_cnt = MAX_REPEAT_TIME;
2954         struct i40e_link_status link_status;
2955         int status;
2956
2957         memset(&link_status, 0, sizeof(link_status));
2958
2959         do {
2960                 memset(&link_status, 0, sizeof(link_status));
2961
2962                 /* Get link status information from hardware */
2963                 status = i40e_aq_get_link_info(hw, enable_lse,
2964                                                 &link_status, NULL);
2965                 if (unlikely(status != I40E_SUCCESS)) {
2966                         link->link_speed = ETH_SPEED_NUM_NONE;
2967                         link->link_duplex = ETH_LINK_FULL_DUPLEX;
2968                         PMD_DRV_LOG(ERR, "Failed to get link info");
2969                         return;
2970                 }
2971
2972                 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2973                 if (!wait_to_complete || link->link_status)
2974                         break;
2975
2976                 rte_delay_ms(CHECK_INTERVAL);
2977         } while (--rep_cnt);
2978
2979         /* Parse the link status */
2980         switch (link_status.link_speed) {
2981         case I40E_LINK_SPEED_100MB:
2982                 link->link_speed = ETH_SPEED_NUM_100M;
2983                 break;
2984         case I40E_LINK_SPEED_1GB:
2985                 link->link_speed = ETH_SPEED_NUM_1G;
2986                 break;
2987         case I40E_LINK_SPEED_10GB:
2988                 link->link_speed = ETH_SPEED_NUM_10G;
2989                 break;
2990         case I40E_LINK_SPEED_20GB:
2991                 link->link_speed = ETH_SPEED_NUM_20G;
2992                 break;
2993         case I40E_LINK_SPEED_25GB:
2994                 link->link_speed = ETH_SPEED_NUM_25G;
2995                 break;
2996         case I40E_LINK_SPEED_40GB:
2997                 link->link_speed = ETH_SPEED_NUM_40G;
2998                 break;
2999         default:
3000                 if (link->link_status)
3001                         link->link_speed = ETH_SPEED_NUM_UNKNOWN;
3002                 else
3003                         link->link_speed = ETH_SPEED_NUM_NONE;
3004                 break;
3005         }
3006 }
3007
3008 int
3009 i40e_dev_link_update(struct rte_eth_dev *dev,
3010                      int wait_to_complete)
3011 {
3012         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3013         struct rte_eth_link link;
3014         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3015         int ret;
3016
3017         memset(&link, 0, sizeof(link));
3018
3019         /* i40e uses full duplex only */
3020         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3021         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
3022                         ETH_LINK_SPEED_FIXED);
3023
3024         if (!wait_to_complete && !enable_lse)
3025                 update_link_reg(hw, &link);
3026         else
3027                 update_link_aq(hw, &link, enable_lse, wait_to_complete);
3028
3029         if (hw->switch_dev)
3030                 rte_eth_linkstatus_get(hw->switch_dev, &link);
3031
3032         ret = rte_eth_linkstatus_set(dev, &link);
3033         i40e_notify_all_vfs_link_status(dev);
3034
3035         return ret;
3036 }
3037
3038 static void
3039 i40e_stat_update_48_in_64(struct i40e_hw *hw, uint32_t hireg,
3040                           uint32_t loreg, bool offset_loaded, uint64_t *offset,
3041                           uint64_t *stat, uint64_t *prev_stat)
3042 {
3043         i40e_stat_update_48(hw, hireg, loreg, offset_loaded, offset, stat);
3044         /* enlarge the limitation when statistics counters overflowed */
3045         if (offset_loaded) {
3046                 if (I40E_RXTX_BYTES_L_48_BIT(*prev_stat) > *stat)
3047                         *stat += (uint64_t)1 << I40E_48_BIT_WIDTH;
3048                 *stat += I40E_RXTX_BYTES_H_16_BIT(*prev_stat);
3049         }
3050         *prev_stat = *stat;
3051 }
3052
3053 /* Get all the statistics of a VSI */
3054 void
3055 i40e_update_vsi_stats(struct i40e_vsi *vsi)
3056 {
3057         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
3058         struct i40e_eth_stats *nes = &vsi->eth_stats;
3059         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3060         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
3061
3062         i40e_stat_update_48_in_64(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
3063                                   vsi->offset_loaded, &oes->rx_bytes,
3064                                   &nes->rx_bytes, &vsi->prev_rx_bytes);
3065         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
3066                             vsi->offset_loaded, &oes->rx_unicast,
3067                             &nes->rx_unicast);
3068         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
3069                             vsi->offset_loaded, &oes->rx_multicast,
3070                             &nes->rx_multicast);
3071         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
3072                             vsi->offset_loaded, &oes->rx_broadcast,
3073                             &nes->rx_broadcast);
3074         /* exclude CRC bytes */
3075         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
3076                 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
3077
3078         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
3079                             &oes->rx_discards, &nes->rx_discards);
3080         /* GLV_REPC not supported */
3081         /* GLV_RMPC not supported */
3082         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
3083                             &oes->rx_unknown_protocol,
3084                             &nes->rx_unknown_protocol);
3085         i40e_stat_update_48_in_64(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
3086                                   vsi->offset_loaded, &oes->tx_bytes,
3087                                   &nes->tx_bytes, &vsi->prev_tx_bytes);
3088         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
3089                             vsi->offset_loaded, &oes->tx_unicast,
3090                             &nes->tx_unicast);
3091         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
3092                             vsi->offset_loaded, &oes->tx_multicast,
3093                             &nes->tx_multicast);
3094         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
3095                             vsi->offset_loaded,  &oes->tx_broadcast,
3096                             &nes->tx_broadcast);
3097         /* GLV_TDPC not supported */
3098         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
3099                             &oes->tx_errors, &nes->tx_errors);
3100         vsi->offset_loaded = true;
3101
3102         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
3103                     vsi->vsi_id);
3104         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
3105         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
3106         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
3107         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
3108         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
3109         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3110                     nes->rx_unknown_protocol);
3111         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
3112         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
3113         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
3114         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
3115         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
3116         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
3117         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
3118                     vsi->vsi_id);
3119 }
3120
3121 static void
3122 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
3123 {
3124         unsigned int i;
3125         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3126         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
3127
3128         /* Get rx/tx bytes of internal transfer packets */
3129         i40e_stat_update_48_in_64(hw, I40E_GLV_GORCH(hw->port),
3130                                   I40E_GLV_GORCL(hw->port),
3131                                   pf->offset_loaded,
3132                                   &pf->internal_stats_offset.rx_bytes,
3133                                   &pf->internal_stats.rx_bytes,
3134                                   &pf->internal_prev_rx_bytes);
3135         i40e_stat_update_48_in_64(hw, I40E_GLV_GOTCH(hw->port),
3136                                   I40E_GLV_GOTCL(hw->port),
3137                                   pf->offset_loaded,
3138                                   &pf->internal_stats_offset.tx_bytes,
3139                                   &pf->internal_stats.tx_bytes,
3140                                   &pf->internal_prev_tx_bytes);
3141         /* Get total internal rx packet count */
3142         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
3143                             I40E_GLV_UPRCL(hw->port),
3144                             pf->offset_loaded,
3145                             &pf->internal_stats_offset.rx_unicast,
3146                             &pf->internal_stats.rx_unicast);
3147         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
3148                             I40E_GLV_MPRCL(hw->port),
3149                             pf->offset_loaded,
3150                             &pf->internal_stats_offset.rx_multicast,
3151                             &pf->internal_stats.rx_multicast);
3152         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
3153                             I40E_GLV_BPRCL(hw->port),
3154                             pf->offset_loaded,
3155                             &pf->internal_stats_offset.rx_broadcast,
3156                             &pf->internal_stats.rx_broadcast);
3157         /* Get total internal tx packet count */
3158         i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
3159                             I40E_GLV_UPTCL(hw->port),
3160                             pf->offset_loaded,
3161                             &pf->internal_stats_offset.tx_unicast,
3162                             &pf->internal_stats.tx_unicast);
3163         i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
3164                             I40E_GLV_MPTCL(hw->port),
3165                             pf->offset_loaded,
3166                             &pf->internal_stats_offset.tx_multicast,
3167                             &pf->internal_stats.tx_multicast);
3168         i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
3169                             I40E_GLV_BPTCL(hw->port),
3170                             pf->offset_loaded,
3171                             &pf->internal_stats_offset.tx_broadcast,
3172                             &pf->internal_stats.tx_broadcast);
3173
3174         /* exclude CRC size */
3175         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
3176                 pf->internal_stats.rx_multicast +
3177                 pf->internal_stats.rx_broadcast) * RTE_ETHER_CRC_LEN;
3178
3179         /* Get statistics of struct i40e_eth_stats */
3180         i40e_stat_update_48_in_64(hw, I40E_GLPRT_GORCH(hw->port),
3181                                   I40E_GLPRT_GORCL(hw->port),
3182                                   pf->offset_loaded, &os->eth.rx_bytes,
3183                                   &ns->eth.rx_bytes, &pf->prev_rx_bytes);
3184         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
3185                             I40E_GLPRT_UPRCL(hw->port),
3186                             pf->offset_loaded, &os->eth.rx_unicast,
3187                             &ns->eth.rx_unicast);
3188         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
3189                             I40E_GLPRT_MPRCL(hw->port),
3190                             pf->offset_loaded, &os->eth.rx_multicast,
3191                             &ns->eth.rx_multicast);
3192         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
3193                             I40E_GLPRT_BPRCL(hw->port),
3194                             pf->offset_loaded, &os->eth.rx_broadcast,
3195                             &ns->eth.rx_broadcast);
3196         /* Workaround: CRC size should not be included in byte statistics,
3197          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
3198          * packet.
3199          */
3200         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
3201                 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
3202
3203         /* exclude internal rx bytes
3204          * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
3205          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
3206          * value.
3207          * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
3208          */
3209         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
3210                 ns->eth.rx_bytes = 0;
3211         else
3212                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
3213
3214         if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
3215                 ns->eth.rx_unicast = 0;
3216         else
3217                 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
3218
3219         if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
3220                 ns->eth.rx_multicast = 0;
3221         else
3222                 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
3223
3224         if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
3225                 ns->eth.rx_broadcast = 0;
3226         else
3227                 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
3228
3229         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
3230                             pf->offset_loaded, &os->eth.rx_discards,
3231                             &ns->eth.rx_discards);
3232         /* GLPRT_REPC not supported */
3233         /* GLPRT_RMPC not supported */
3234         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
3235                             pf->offset_loaded,
3236                             &os->eth.rx_unknown_protocol,
3237                             &ns->eth.rx_unknown_protocol);
3238         i40e_stat_update_48_in_64(hw, I40E_GLPRT_GOTCH(hw->port),
3239                                   I40E_GLPRT_GOTCL(hw->port),
3240                                   pf->offset_loaded, &os->eth.tx_bytes,
3241                                   &ns->eth.tx_bytes, &pf->prev_tx_bytes);
3242         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
3243                             I40E_GLPRT_UPTCL(hw->port),
3244                             pf->offset_loaded, &os->eth.tx_unicast,
3245                             &ns->eth.tx_unicast);
3246         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
3247                             I40E_GLPRT_MPTCL(hw->port),
3248                             pf->offset_loaded, &os->eth.tx_multicast,
3249                             &ns->eth.tx_multicast);
3250         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
3251                             I40E_GLPRT_BPTCL(hw->port),
3252                             pf->offset_loaded, &os->eth.tx_broadcast,
3253                             &ns->eth.tx_broadcast);
3254         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3255                 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3256
3257         /* exclude internal tx bytes
3258          * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
3259          * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
3260          * value.
3261          * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
3262          */
3263         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
3264                 ns->eth.tx_bytes = 0;
3265         else
3266                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3267
3268         if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3269                 ns->eth.tx_unicast = 0;
3270         else
3271                 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3272
3273         if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3274                 ns->eth.tx_multicast = 0;
3275         else
3276                 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3277
3278         if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3279                 ns->eth.tx_broadcast = 0;
3280         else
3281                 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3282
3283         /* GLPRT_TEPC not supported */
3284
3285         /* additional port specific stats */
3286         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3287                             pf->offset_loaded, &os->tx_dropped_link_down,
3288                             &ns->tx_dropped_link_down);
3289         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3290                             pf->offset_loaded, &os->crc_errors,
3291                             &ns->crc_errors);
3292         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3293                             pf->offset_loaded, &os->illegal_bytes,
3294                             &ns->illegal_bytes);
3295         /* GLPRT_ERRBC not supported */
3296         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3297                             pf->offset_loaded, &os->mac_local_faults,
3298                             &ns->mac_local_faults);
3299         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3300                             pf->offset_loaded, &os->mac_remote_faults,
3301                             &ns->mac_remote_faults);
3302         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3303                             pf->offset_loaded, &os->rx_length_errors,
3304                             &ns->rx_length_errors);
3305         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3306                             pf->offset_loaded, &os->link_xon_rx,
3307                             &ns->link_xon_rx);
3308         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3309                             pf->offset_loaded, &os->link_xoff_rx,
3310                             &ns->link_xoff_rx);
3311         for (i = 0; i < 8; i++) {
3312                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3313                                     pf->offset_loaded,
3314                                     &os->priority_xon_rx[i],
3315                                     &ns->priority_xon_rx[i]);
3316                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3317                                     pf->offset_loaded,
3318                                     &os->priority_xoff_rx[i],
3319                                     &ns->priority_xoff_rx[i]);
3320         }
3321         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3322                             pf->offset_loaded, &os->link_xon_tx,
3323                             &ns->link_xon_tx);
3324         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3325                             pf->offset_loaded, &os->link_xoff_tx,
3326                             &ns->link_xoff_tx);
3327         for (i = 0; i < 8; i++) {
3328                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3329                                     pf->offset_loaded,
3330                                     &os->priority_xon_tx[i],
3331                                     &ns->priority_xon_tx[i]);
3332                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3333                                     pf->offset_loaded,
3334                                     &os->priority_xoff_tx[i],
3335                                     &ns->priority_xoff_tx[i]);
3336                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3337                                     pf->offset_loaded,
3338                                     &os->priority_xon_2_xoff[i],
3339                                     &ns->priority_xon_2_xoff[i]);
3340         }
3341         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3342                             I40E_GLPRT_PRC64L(hw->port),
3343                             pf->offset_loaded, &os->rx_size_64,
3344                             &ns->rx_size_64);
3345         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3346                             I40E_GLPRT_PRC127L(hw->port),
3347                             pf->offset_loaded, &os->rx_size_127,
3348                             &ns->rx_size_127);
3349         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3350                             I40E_GLPRT_PRC255L(hw->port),
3351                             pf->offset_loaded, &os->rx_size_255,
3352                             &ns->rx_size_255);
3353         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3354                             I40E_GLPRT_PRC511L(hw->port),
3355                             pf->offset_loaded, &os->rx_size_511,
3356                             &ns->rx_size_511);
3357         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3358                             I40E_GLPRT_PRC1023L(hw->port),
3359                             pf->offset_loaded, &os->rx_size_1023,
3360                             &ns->rx_size_1023);
3361         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3362                             I40E_GLPRT_PRC1522L(hw->port),
3363                             pf->offset_loaded, &os->rx_size_1522,
3364                             &ns->rx_size_1522);
3365         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3366                             I40E_GLPRT_PRC9522L(hw->port),
3367                             pf->offset_loaded, &os->rx_size_big,
3368                             &ns->rx_size_big);
3369         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3370                             pf->offset_loaded, &os->rx_undersize,
3371                             &ns->rx_undersize);
3372         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3373                             pf->offset_loaded, &os->rx_fragments,
3374                             &ns->rx_fragments);
3375         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3376                             pf->offset_loaded, &os->rx_oversize,
3377                             &ns->rx_oversize);
3378         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3379                             pf->offset_loaded, &os->rx_jabber,
3380                             &ns->rx_jabber);
3381         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3382                             I40E_GLPRT_PTC64L(hw->port),
3383                             pf->offset_loaded, &os->tx_size_64,
3384                             &ns->tx_size_64);
3385         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3386                             I40E_GLPRT_PTC127L(hw->port),
3387                             pf->offset_loaded, &os->tx_size_127,
3388                             &ns->tx_size_127);
3389         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3390                             I40E_GLPRT_PTC255L(hw->port),
3391                             pf->offset_loaded, &os->tx_size_255,
3392                             &ns->tx_size_255);
3393         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3394                             I40E_GLPRT_PTC511L(hw->port),
3395                             pf->offset_loaded, &os->tx_size_511,
3396                             &ns->tx_size_511);
3397         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3398                             I40E_GLPRT_PTC1023L(hw->port),
3399                             pf->offset_loaded, &os->tx_size_1023,
3400                             &ns->tx_size_1023);
3401         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3402                             I40E_GLPRT_PTC1522L(hw->port),
3403                             pf->offset_loaded, &os->tx_size_1522,
3404                             &ns->tx_size_1522);
3405         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3406                             I40E_GLPRT_PTC9522L(hw->port),
3407                             pf->offset_loaded, &os->tx_size_big,
3408                             &ns->tx_size_big);
3409         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3410                            pf->offset_loaded,
3411                            &os->fd_sb_match, &ns->fd_sb_match);
3412         /* GLPRT_MSPDC not supported */
3413         /* GLPRT_XEC not supported */
3414
3415         pf->offset_loaded = true;
3416
3417         if (pf->main_vsi)
3418                 i40e_update_vsi_stats(pf->main_vsi);
3419 }
3420
3421 /* Get all statistics of a port */
3422 static int
3423 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3424 {
3425         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3426         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3427         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3428         struct i40e_vsi *vsi;
3429         unsigned i;
3430
3431         /* call read registers - updates values, now write them to struct */
3432         i40e_read_stats_registers(pf, hw);
3433
3434         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3435                         pf->main_vsi->eth_stats.rx_multicast +
3436                         pf->main_vsi->eth_stats.rx_broadcast -
3437                         pf->main_vsi->eth_stats.rx_discards;
3438         stats->opackets = ns->eth.tx_unicast +
3439                         ns->eth.tx_multicast +
3440                         ns->eth.tx_broadcast;
3441         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
3442         stats->obytes   = ns->eth.tx_bytes;
3443         stats->oerrors  = ns->eth.tx_errors +
3444                         pf->main_vsi->eth_stats.tx_errors;
3445
3446         /* Rx Errors */
3447         stats->imissed  = ns->eth.rx_discards +
3448                         pf->main_vsi->eth_stats.rx_discards;
3449         stats->ierrors  = ns->crc_errors +
3450                         ns->rx_length_errors + ns->rx_undersize +
3451                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3452
3453         if (pf->vfs) {
3454                 for (i = 0; i < pf->vf_num; i++) {
3455                         vsi = pf->vfs[i].vsi;
3456                         i40e_update_vsi_stats(vsi);
3457
3458                         stats->ipackets += (vsi->eth_stats.rx_unicast +
3459                                         vsi->eth_stats.rx_multicast +
3460                                         vsi->eth_stats.rx_broadcast -
3461                                         vsi->eth_stats.rx_discards);
3462                         stats->ibytes   += vsi->eth_stats.rx_bytes;
3463                         stats->oerrors  += vsi->eth_stats.tx_errors;
3464                         stats->imissed  += vsi->eth_stats.rx_discards;
3465                 }
3466         }
3467
3468         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3469         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
3470         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
3471         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
3472         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
3473         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
3474         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3475                     ns->eth.rx_unknown_protocol);
3476         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
3477         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
3478         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
3479         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
3480         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
3481         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
3482
3483         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
3484                     ns->tx_dropped_link_down);
3485         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
3486         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
3487                     ns->illegal_bytes);
3488         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
3489         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
3490                     ns->mac_local_faults);
3491         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
3492                     ns->mac_remote_faults);
3493         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
3494                     ns->rx_length_errors);
3495         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
3496         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
3497         for (i = 0; i < 8; i++) {
3498                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
3499                                 i, ns->priority_xon_rx[i]);
3500                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
3501                                 i, ns->priority_xoff_rx[i]);
3502         }
3503         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
3504         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
3505         for (i = 0; i < 8; i++) {
3506                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
3507                                 i, ns->priority_xon_tx[i]);
3508                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
3509                                 i, ns->priority_xoff_tx[i]);
3510                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
3511                                 i, ns->priority_xon_2_xoff[i]);
3512         }
3513         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
3514         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
3515         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
3516         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
3517         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
3518         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
3519         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
3520         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
3521         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
3522         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
3523         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
3524         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
3525         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
3526         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
3527         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
3528         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
3529         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
3530         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
3531         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3532                         ns->mac_short_packet_dropped);
3533         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
3534                     ns->checksum_error);
3535         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
3536         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3537         return 0;
3538 }
3539
3540 /* Reset the statistics */
3541 static int
3542 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3543 {
3544         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3545         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3546
3547         /* Mark PF and VSI stats to update the offset, aka "reset" */
3548         pf->offset_loaded = false;
3549         if (pf->main_vsi)
3550                 pf->main_vsi->offset_loaded = false;
3551
3552         /* read the stats, reading current register values into offset */
3553         i40e_read_stats_registers(pf, hw);
3554
3555         return 0;
3556 }
3557
3558 static uint32_t
3559 i40e_xstats_calc_num(void)
3560 {
3561         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3562                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3563                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3564 }
3565
3566 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3567                                      struct rte_eth_xstat_name *xstats_names,
3568                                      __rte_unused unsigned limit)
3569 {
3570         unsigned count = 0;
3571         unsigned i, prio;
3572
3573         if (xstats_names == NULL)
3574                 return i40e_xstats_calc_num();
3575
3576         /* Note: limit checked in rte_eth_xstats_names() */
3577
3578         /* Get stats from i40e_eth_stats struct */
3579         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3580                 strlcpy(xstats_names[count].name,
3581                         rte_i40e_stats_strings[i].name,
3582                         sizeof(xstats_names[count].name));
3583                 count++;
3584         }
3585
3586         /* Get individiual stats from i40e_hw_port struct */
3587         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3588                 strlcpy(xstats_names[count].name,
3589                         rte_i40e_hw_port_strings[i].name,
3590                         sizeof(xstats_names[count].name));
3591                 count++;
3592         }
3593
3594         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3595                 for (prio = 0; prio < 8; prio++) {
3596                         snprintf(xstats_names[count].name,
3597                                  sizeof(xstats_names[count].name),
3598                                  "rx_priority%u_%s", prio,
3599                                  rte_i40e_rxq_prio_strings[i].name);
3600                         count++;
3601                 }
3602         }
3603
3604         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3605                 for (prio = 0; prio < 8; prio++) {
3606                         snprintf(xstats_names[count].name,
3607                                  sizeof(xstats_names[count].name),
3608                                  "tx_priority%u_%s", prio,
3609                                  rte_i40e_txq_prio_strings[i].name);
3610                         count++;
3611                 }
3612         }
3613         return count;
3614 }
3615
3616 static int
3617 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3618                     unsigned n)
3619 {
3620         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3621         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3622         unsigned i, count, prio;
3623         struct i40e_hw_port_stats *hw_stats = &pf->stats;
3624
3625         count = i40e_xstats_calc_num();
3626         if (n < count)
3627                 return count;
3628
3629         i40e_read_stats_registers(pf, hw);
3630
3631         if (xstats == NULL)
3632                 return 0;
3633
3634         count = 0;
3635
3636         /* Get stats from i40e_eth_stats struct */
3637         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3638                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3639                         rte_i40e_stats_strings[i].offset);
3640                 xstats[count].id = count;
3641                 count++;
3642         }
3643
3644         /* Get individiual stats from i40e_hw_port struct */
3645         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3646                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3647                         rte_i40e_hw_port_strings[i].offset);
3648                 xstats[count].id = count;
3649                 count++;
3650         }
3651
3652         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3653                 for (prio = 0; prio < 8; prio++) {
3654                         xstats[count].value =
3655                                 *(uint64_t *)(((char *)hw_stats) +
3656                                 rte_i40e_rxq_prio_strings[i].offset +
3657                                 (sizeof(uint64_t) * prio));
3658                         xstats[count].id = count;
3659                         count++;
3660                 }
3661         }
3662
3663         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3664                 for (prio = 0; prio < 8; prio++) {
3665                         xstats[count].value =
3666                                 *(uint64_t *)(((char *)hw_stats) +
3667                                 rte_i40e_txq_prio_strings[i].offset +
3668                                 (sizeof(uint64_t) * prio));
3669                         xstats[count].id = count;
3670                         count++;
3671                 }
3672         }
3673
3674         return count;
3675 }
3676
3677 static int
3678 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3679 {
3680         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3681         u32 full_ver;
3682         u8 ver, patch;
3683         u16 build;
3684         int ret;
3685
3686         full_ver = hw->nvm.oem_ver;
3687         ver = (u8)(full_ver >> 24);
3688         build = (u16)((full_ver >> 8) & 0xffff);
3689         patch = (u8)(full_ver & 0xff);
3690
3691         ret = snprintf(fw_version, fw_size,
3692                  "%d.%d%d 0x%08x %d.%d.%d",
3693                  ((hw->nvm.version >> 12) & 0xf),
3694                  ((hw->nvm.version >> 4) & 0xff),
3695                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
3696                  ver, build, patch);
3697         if (ret < 0)
3698                 return -EINVAL;
3699
3700         ret += 1; /* add the size of '\0' */
3701         if (fw_size < (size_t)ret)
3702                 return ret;
3703         else
3704                 return 0;
3705 }
3706
3707 /*
3708  * When using NVM 6.01(for X710 XL710 XXV710)/3.33(for X722) or later,
3709  * the Rx data path does not hang if the FW LLDP is stopped.
3710  * return true if lldp need to stop
3711  * return false if we cannot disable the LLDP to avoid Rx data path blocking.
3712  */
3713 static bool
3714 i40e_need_stop_lldp(struct rte_eth_dev *dev)
3715 {
3716         double nvm_ver;
3717         char ver_str[64] = {0};
3718         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3719
3720         i40e_fw_version_get(dev, ver_str, 64);
3721         nvm_ver = atof(ver_str);
3722         if ((hw->mac.type == I40E_MAC_X722 ||
3723              hw->mac.type == I40E_MAC_X722_VF) &&
3724              ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(3.33 * 1000)))
3725                 return true;
3726         else if ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(6.01 * 1000))
3727                 return true;
3728
3729         return false;
3730 }
3731
3732 static int
3733 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3734 {
3735         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3736         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3737         struct i40e_vsi *vsi = pf->main_vsi;
3738         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3739
3740         dev_info->max_rx_queues = vsi->nb_qps;
3741         dev_info->max_tx_queues = vsi->nb_qps;
3742         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3743         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3744         dev_info->max_mac_addrs = vsi->max_macaddrs;
3745         dev_info->max_vfs = pci_dev->max_vfs;
3746         dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
3747         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3748         dev_info->rx_queue_offload_capa = 0;
3749         dev_info->rx_offload_capa =
3750                 DEV_RX_OFFLOAD_VLAN_STRIP |
3751                 DEV_RX_OFFLOAD_QINQ_STRIP |
3752                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3753                 DEV_RX_OFFLOAD_UDP_CKSUM |
3754                 DEV_RX_OFFLOAD_TCP_CKSUM |
3755                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3756                 DEV_RX_OFFLOAD_KEEP_CRC |
3757                 DEV_RX_OFFLOAD_SCATTER |
3758                 DEV_RX_OFFLOAD_VLAN_EXTEND |
3759                 DEV_RX_OFFLOAD_VLAN_FILTER |
3760                 DEV_RX_OFFLOAD_JUMBO_FRAME |
3761                 DEV_RX_OFFLOAD_RSS_HASH;
3762
3763         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3764         dev_info->tx_offload_capa =
3765                 DEV_TX_OFFLOAD_VLAN_INSERT |
3766                 DEV_TX_OFFLOAD_QINQ_INSERT |
3767                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3768                 DEV_TX_OFFLOAD_UDP_CKSUM |
3769                 DEV_TX_OFFLOAD_TCP_CKSUM |
3770                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3771                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3772                 DEV_TX_OFFLOAD_TCP_TSO |
3773                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3774                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3775                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3776                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3777                 DEV_TX_OFFLOAD_MULTI_SEGS |
3778                 dev_info->tx_queue_offload_capa;
3779         dev_info->dev_capa =
3780                 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3781                 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3782
3783         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3784                                                 sizeof(uint32_t);
3785         dev_info->reta_size = pf->hash_lut_size;
3786         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3787
3788         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3789                 .rx_thresh = {
3790                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3791                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3792                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3793                 },
3794                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3795                 .rx_drop_en = 0,
3796                 .offloads = 0,
3797         };
3798
3799         dev_info->default_txconf = (struct rte_eth_txconf) {
3800                 .tx_thresh = {
3801                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3802                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3803                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3804                 },
3805                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3806                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3807                 .offloads = 0,
3808         };
3809
3810         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3811                 .nb_max = I40E_MAX_RING_DESC,
3812                 .nb_min = I40E_MIN_RING_DESC,
3813                 .nb_align = I40E_ALIGN_RING_DESC,
3814         };
3815
3816         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3817                 .nb_max = I40E_MAX_RING_DESC,
3818                 .nb_min = I40E_MIN_RING_DESC,
3819                 .nb_align = I40E_ALIGN_RING_DESC,
3820                 .nb_seg_max = I40E_TX_MAX_SEG,
3821                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3822         };
3823
3824         if (pf->flags & I40E_FLAG_VMDQ) {
3825                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3826                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3827                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3828                                                 pf->max_nb_vmdq_vsi;
3829                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3830                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3831                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3832         }
3833
3834         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3835                 /* For XL710 */
3836                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3837                 dev_info->default_rxportconf.nb_queues = 2;
3838                 dev_info->default_txportconf.nb_queues = 2;
3839                 if (dev->data->nb_rx_queues == 1)
3840                         dev_info->default_rxportconf.ring_size = 2048;
3841                 else
3842                         dev_info->default_rxportconf.ring_size = 1024;
3843                 if (dev->data->nb_tx_queues == 1)
3844                         dev_info->default_txportconf.ring_size = 1024;
3845                 else
3846                         dev_info->default_txportconf.ring_size = 512;
3847
3848         } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3849                 /* For XXV710 */
3850                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3851                 dev_info->default_rxportconf.nb_queues = 1;
3852                 dev_info->default_txportconf.nb_queues = 1;
3853                 dev_info->default_rxportconf.ring_size = 256;
3854                 dev_info->default_txportconf.ring_size = 256;
3855         } else {
3856                 /* For X710 */
3857                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3858                 dev_info->default_rxportconf.nb_queues = 1;
3859                 dev_info->default_txportconf.nb_queues = 1;
3860                 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3861                         dev_info->default_rxportconf.ring_size = 512;
3862                         dev_info->default_txportconf.ring_size = 256;
3863                 } else {
3864                         dev_info->default_rxportconf.ring_size = 256;
3865                         dev_info->default_txportconf.ring_size = 256;
3866                 }
3867         }
3868         dev_info->default_rxportconf.burst_size = 32;
3869         dev_info->default_txportconf.burst_size = 32;
3870
3871         return 0;
3872 }
3873
3874 static int
3875 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3876 {
3877         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3878         struct i40e_vsi *vsi = pf->main_vsi;
3879         PMD_INIT_FUNC_TRACE();
3880
3881         if (on)
3882                 return i40e_vsi_add_vlan(vsi, vlan_id);
3883         else
3884                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3885 }
3886
3887 static int
3888 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3889                                 enum rte_vlan_type vlan_type,
3890                                 uint16_t tpid, int qinq)
3891 {
3892         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3893         uint64_t reg_r = 0;
3894         uint64_t reg_w = 0;
3895         uint16_t reg_id = 3;
3896         int ret;
3897
3898         if (qinq) {
3899                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3900                         reg_id = 2;
3901         }
3902
3903         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3904                                           &reg_r, NULL);
3905         if (ret != I40E_SUCCESS) {
3906                 PMD_DRV_LOG(ERR,
3907                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3908                            reg_id);
3909                 return -EIO;
3910         }
3911         PMD_DRV_LOG(DEBUG,
3912                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3913                     reg_id, reg_r);
3914
3915         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3916         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3917         if (reg_r == reg_w) {
3918                 PMD_DRV_LOG(DEBUG, "No need to write");
3919                 return 0;
3920         }
3921
3922         ret = i40e_aq_debug_write_global_register(hw,
3923                                            I40E_GL_SWT_L2TAGCTRL(reg_id),
3924                                            reg_w, NULL);
3925         if (ret != I40E_SUCCESS) {
3926                 PMD_DRV_LOG(ERR,
3927                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3928                             reg_id);
3929                 return -EIO;
3930         }
3931         PMD_DRV_LOG(DEBUG,
3932                     "Global register 0x%08x is changed with value 0x%08x",
3933                     I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3934
3935         return 0;
3936 }
3937
3938 static int
3939 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3940                    enum rte_vlan_type vlan_type,
3941                    uint16_t tpid)
3942 {
3943         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3944         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3945         int qinq = dev->data->dev_conf.rxmode.offloads &
3946                    DEV_RX_OFFLOAD_VLAN_EXTEND;
3947         int ret = 0;
3948
3949         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3950              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3951             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3952                 PMD_DRV_LOG(ERR,
3953                             "Unsupported vlan type.");
3954                 return -EINVAL;
3955         }
3956
3957         if (pf->support_multi_driver) {
3958                 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3959                 return -ENOTSUP;
3960         }
3961
3962         /* 802.1ad frames ability is added in NVM API 1.7*/
3963         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3964                 if (qinq) {
3965                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3966                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3967                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3968                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3969                 } else {
3970                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3971                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3972                 }
3973                 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL);
3974                 if (ret != I40E_SUCCESS) {
3975                         PMD_DRV_LOG(ERR,
3976                                     "Set switch config failed aq_err: %d",
3977                                     hw->aq.asq_last_status);
3978                         ret = -EIO;
3979                 }
3980         } else
3981                 /* If NVM API < 1.7, keep the register setting */
3982                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3983                                                       tpid, qinq);
3984
3985         return ret;
3986 }
3987
3988 /* Configure outer vlan stripping on or off in QinQ mode */
3989 static int
3990 i40e_vsi_config_outer_vlan_stripping(struct i40e_vsi *vsi, bool on)
3991 {
3992         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3993         int ret = I40E_SUCCESS;
3994         uint32_t reg;
3995
3996         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
3997                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
3998                 return -EINVAL;
3999         }
4000
4001         /* Configure for outer VLAN RX stripping */
4002         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
4003
4004         if (on)
4005                 reg |= I40E_VSI_TSR_QINQ_STRIP;
4006         else
4007                 reg &= ~I40E_VSI_TSR_QINQ_STRIP;
4008
4009         ret = i40e_aq_debug_write_register(hw,
4010                                                    I40E_VSI_TSR(vsi->vsi_id),
4011                                                    reg, NULL);
4012         if (ret < 0) {
4013                 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
4014                                     vsi->vsi_id);
4015                 return I40E_ERR_CONFIG;
4016         }
4017
4018         return ret;
4019 }
4020
4021 static int
4022 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4023 {
4024         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4025         struct i40e_vsi *vsi = pf->main_vsi;
4026         struct rte_eth_rxmode *rxmode;
4027
4028         rxmode = &dev->data->dev_conf.rxmode;
4029         if (mask & ETH_VLAN_FILTER_MASK) {
4030                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4031                         i40e_vsi_config_vlan_filter(vsi, TRUE);
4032                 else
4033                         i40e_vsi_config_vlan_filter(vsi, FALSE);
4034         }
4035
4036         if (mask & ETH_VLAN_STRIP_MASK) {
4037                 /* Enable or disable VLAN stripping */
4038                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
4039                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
4040                 else
4041                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
4042         }
4043
4044         if (mask & ETH_VLAN_EXTEND_MASK) {
4045                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
4046                         i40e_vsi_config_double_vlan(vsi, TRUE);
4047                         /* Set global registers with default ethertype. */
4048                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
4049                                            RTE_ETHER_TYPE_VLAN);
4050                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
4051                                            RTE_ETHER_TYPE_VLAN);
4052                 }
4053                 else
4054                         i40e_vsi_config_double_vlan(vsi, FALSE);
4055         }
4056
4057         if (mask & ETH_QINQ_STRIP_MASK) {
4058                 /* Enable or disable outer VLAN stripping */
4059                 if (rxmode->offloads & DEV_RX_OFFLOAD_QINQ_STRIP)
4060                         i40e_vsi_config_outer_vlan_stripping(vsi, TRUE);
4061                 else
4062                         i40e_vsi_config_outer_vlan_stripping(vsi, FALSE);
4063         }
4064
4065         return 0;
4066 }
4067
4068 static void
4069 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
4070                           __rte_unused uint16_t queue,
4071                           __rte_unused int on)
4072 {
4073         PMD_INIT_FUNC_TRACE();
4074 }
4075
4076 static int
4077 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
4078 {
4079         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4080         struct i40e_vsi *vsi = pf->main_vsi;
4081         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
4082         struct i40e_vsi_vlan_pvid_info info;
4083
4084         memset(&info, 0, sizeof(info));
4085         info.on = on;
4086         if (info.on)
4087                 info.config.pvid = pvid;
4088         else {
4089                 info.config.reject.tagged =
4090                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
4091                 info.config.reject.untagged =
4092                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
4093         }
4094
4095         return i40e_vsi_vlan_pvid_set(vsi, &info);
4096 }
4097
4098 static int
4099 i40e_dev_led_on(struct rte_eth_dev *dev)
4100 {
4101         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4102         uint32_t mode = i40e_led_get(hw);
4103
4104         if (mode == 0)
4105                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
4106
4107         return 0;
4108 }
4109
4110 static int
4111 i40e_dev_led_off(struct rte_eth_dev *dev)
4112 {
4113         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4114         uint32_t mode = i40e_led_get(hw);
4115
4116         if (mode != 0)
4117                 i40e_led_set(hw, 0, false);
4118
4119         return 0;
4120 }
4121
4122 static int
4123 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4124 {
4125         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4126         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4127
4128         fc_conf->pause_time = pf->fc_conf.pause_time;
4129
4130         /* read out from register, in case they are modified by other port */
4131         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
4132                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
4133         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
4134                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
4135
4136         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
4137         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
4138
4139          /* Return current mode according to actual setting*/
4140         switch (hw->fc.current_mode) {
4141         case I40E_FC_FULL:
4142                 fc_conf->mode = RTE_FC_FULL;
4143                 break;
4144         case I40E_FC_TX_PAUSE:
4145                 fc_conf->mode = RTE_FC_TX_PAUSE;
4146                 break;
4147         case I40E_FC_RX_PAUSE:
4148                 fc_conf->mode = RTE_FC_RX_PAUSE;
4149                 break;
4150         case I40E_FC_NONE:
4151         default:
4152                 fc_conf->mode = RTE_FC_NONE;
4153         };
4154
4155         return 0;
4156 }
4157
4158 static int
4159 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4160 {
4161         uint32_t mflcn_reg, fctrl_reg, reg;
4162         uint32_t max_high_water;
4163         uint8_t i, aq_failure;
4164         int err;
4165         struct i40e_hw *hw;
4166         struct i40e_pf *pf;
4167         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
4168                 [RTE_FC_NONE] = I40E_FC_NONE,
4169                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
4170                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
4171                 [RTE_FC_FULL] = I40E_FC_FULL
4172         };
4173
4174         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
4175
4176         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
4177         if ((fc_conf->high_water > max_high_water) ||
4178                         (fc_conf->high_water < fc_conf->low_water)) {
4179                 PMD_INIT_LOG(ERR,
4180                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
4181                         max_high_water);
4182                 return -EINVAL;
4183         }
4184
4185         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4186         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4187         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
4188
4189         pf->fc_conf.pause_time = fc_conf->pause_time;
4190         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
4191         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
4192
4193         PMD_INIT_FUNC_TRACE();
4194
4195         /* All the link flow control related enable/disable register
4196          * configuration is handle by the F/W
4197          */
4198         err = i40e_set_fc(hw, &aq_failure, true);
4199         if (err < 0)
4200                 return -ENOSYS;
4201
4202         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
4203                 /* Configure flow control refresh threshold,
4204                  * the value for stat_tx_pause_refresh_timer[8]
4205                  * is used for global pause operation.
4206                  */
4207
4208                 I40E_WRITE_REG(hw,
4209                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
4210                                pf->fc_conf.pause_time);
4211
4212                 /* configure the timer value included in transmitted pause
4213                  * frame,
4214                  * the value for stat_tx_pause_quanta[8] is used for global
4215                  * pause operation
4216                  */
4217                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
4218                                pf->fc_conf.pause_time);
4219
4220                 fctrl_reg = I40E_READ_REG(hw,
4221                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
4222
4223                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4224                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
4225                 else
4226                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
4227
4228                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
4229                                fctrl_reg);
4230         } else {
4231                 /* Configure pause time (2 TCs per register) */
4232                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
4233                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
4234                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
4235
4236                 /* Configure flow control refresh threshold value */
4237                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
4238                                pf->fc_conf.pause_time / 2);
4239
4240                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4241
4242                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
4243                  *depending on configuration
4244                  */
4245                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
4246                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
4247                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
4248                 } else {
4249                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
4250                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
4251                 }
4252
4253                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
4254         }
4255
4256         if (!pf->support_multi_driver) {
4257                 /* config water marker both based on the packets and bytes */
4258                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
4259                                  (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4260                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4261                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
4262                                   (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4263                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4264                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
4265                                   pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4266                                   << I40E_KILOSHIFT);
4267                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
4268                                    pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4269                                    << I40E_KILOSHIFT);
4270         } else {
4271                 PMD_DRV_LOG(ERR,
4272                             "Water marker configuration is not supported.");
4273         }
4274
4275         I40E_WRITE_FLUSH(hw);
4276
4277         return 0;
4278 }
4279
4280 static int
4281 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
4282                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
4283 {
4284         PMD_INIT_FUNC_TRACE();
4285
4286         return -ENOSYS;
4287 }
4288
4289 /* Add a MAC address, and update filters */
4290 static int
4291 i40e_macaddr_add(struct rte_eth_dev *dev,
4292                  struct rte_ether_addr *mac_addr,
4293                  __rte_unused uint32_t index,
4294                  uint32_t pool)
4295 {
4296         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4297         struct i40e_mac_filter_info mac_filter;
4298         struct i40e_vsi *vsi;
4299         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
4300         int ret;
4301
4302         /* If VMDQ not enabled or configured, return */
4303         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
4304                           !pf->nb_cfg_vmdq_vsi)) {
4305                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
4306                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
4307                         pool);
4308                 return -ENOTSUP;
4309         }
4310
4311         if (pool > pf->nb_cfg_vmdq_vsi) {
4312                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
4313                                 pool, pf->nb_cfg_vmdq_vsi);
4314                 return -EINVAL;
4315         }
4316
4317         rte_memcpy(&mac_filter.mac_addr, mac_addr, RTE_ETHER_ADDR_LEN);
4318         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4319                 mac_filter.filter_type = I40E_MACVLAN_PERFECT_MATCH;
4320         else
4321                 mac_filter.filter_type = I40E_MAC_PERFECT_MATCH;
4322
4323         if (pool == 0)
4324                 vsi = pf->main_vsi;
4325         else
4326                 vsi = pf->vmdq[pool - 1].vsi;
4327
4328         ret = i40e_vsi_add_mac(vsi, &mac_filter);
4329         if (ret != I40E_SUCCESS) {
4330                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4331                 return -ENODEV;
4332         }
4333         return 0;
4334 }
4335
4336 /* Remove a MAC address, and update filters */
4337 static void
4338 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4339 {
4340         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4341         struct i40e_vsi *vsi;
4342         struct rte_eth_dev_data *data = dev->data;
4343         struct rte_ether_addr *macaddr;
4344         int ret;
4345         uint32_t i;
4346         uint64_t pool_sel;
4347
4348         macaddr = &(data->mac_addrs[index]);
4349
4350         pool_sel = dev->data->mac_pool_sel[index];
4351
4352         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4353                 if (pool_sel & (1ULL << i)) {
4354                         if (i == 0)
4355                                 vsi = pf->main_vsi;
4356                         else {
4357                                 /* No VMDQ pool enabled or configured */
4358                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4359                                         (i > pf->nb_cfg_vmdq_vsi)) {
4360                                         PMD_DRV_LOG(ERR,
4361                                                 "No VMDQ pool enabled/configured");
4362                                         return;
4363                                 }
4364                                 vsi = pf->vmdq[i - 1].vsi;
4365                         }
4366                         ret = i40e_vsi_delete_mac(vsi, macaddr);
4367
4368                         if (ret) {
4369                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4370                                 return;
4371                         }
4372                 }
4373         }
4374 }
4375
4376 static int
4377 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4378 {
4379         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4380         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4381         uint32_t reg;
4382         int ret;
4383
4384         if (!lut)
4385                 return -EINVAL;
4386
4387         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4388                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id,
4389                                           vsi->type != I40E_VSI_SRIOV,
4390                                           lut, lut_size);
4391                 if (ret) {
4392                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4393                         return ret;
4394                 }
4395         } else {
4396                 uint32_t *lut_dw = (uint32_t *)lut;
4397                 uint16_t i, lut_size_dw = lut_size / 4;
4398
4399                 if (vsi->type == I40E_VSI_SRIOV) {
4400                         for (i = 0; i <= lut_size_dw; i++) {
4401                                 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4402                                 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4403                         }
4404                 } else {
4405                         for (i = 0; i < lut_size_dw; i++)
4406                                 lut_dw[i] = I40E_READ_REG(hw,
4407                                                           I40E_PFQF_HLUT(i));
4408                 }
4409         }
4410
4411         return 0;
4412 }
4413
4414 int
4415 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4416 {
4417         struct i40e_pf *pf;
4418         struct i40e_hw *hw;
4419
4420         if (!vsi || !lut)
4421                 return -EINVAL;
4422
4423         pf = I40E_VSI_TO_PF(vsi);
4424         hw = I40E_VSI_TO_HW(vsi);
4425
4426         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4427                 enum i40e_status_code status;
4428
4429                 status = i40e_aq_set_rss_lut(hw, vsi->vsi_id,
4430                                              vsi->type != I40E_VSI_SRIOV,
4431                                              lut, lut_size);
4432                 if (status) {
4433                         PMD_DRV_LOG(ERR,
4434                                     "Failed to update RSS lookup table, error status: %d",
4435                                     status);
4436                         return -EIO;
4437                 }
4438         } else {
4439                 uint32_t *lut_dw = (uint32_t *)lut;
4440                 uint16_t i, lut_size_dw = lut_size / 4;
4441
4442                 if (vsi->type == I40E_VSI_SRIOV) {
4443                         for (i = 0; i < lut_size_dw; i++)
4444                                 I40E_WRITE_REG(
4445                                         hw,
4446                                         I40E_VFQF_HLUT1(i, vsi->user_param),
4447                                         lut_dw[i]);
4448                 } else {
4449                         for (i = 0; i < lut_size_dw; i++)
4450                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4451                                                lut_dw[i]);
4452                 }
4453                 I40E_WRITE_FLUSH(hw);
4454         }
4455
4456         return 0;
4457 }
4458
4459 static int
4460 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4461                          struct rte_eth_rss_reta_entry64 *reta_conf,
4462                          uint16_t reta_size)
4463 {
4464         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4465         uint16_t i, lut_size = pf->hash_lut_size;
4466         uint16_t idx, shift;
4467         uint8_t *lut;
4468         int ret;
4469
4470         if (reta_size != lut_size ||
4471                 reta_size > ETH_RSS_RETA_SIZE_512) {
4472                 PMD_DRV_LOG(ERR,
4473                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4474                         reta_size, lut_size);
4475                 return -EINVAL;
4476         }
4477
4478         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4479         if (!lut) {
4480                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4481                 return -ENOMEM;
4482         }
4483         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4484         if (ret)
4485                 goto out;
4486         for (i = 0; i < reta_size; i++) {
4487                 idx = i / RTE_RETA_GROUP_SIZE;
4488                 shift = i % RTE_RETA_GROUP_SIZE;
4489                 if (reta_conf[idx].mask & (1ULL << shift))
4490                         lut[i] = reta_conf[idx].reta[shift];
4491         }
4492         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4493
4494         pf->adapter->rss_reta_updated = 1;
4495
4496 out:
4497         rte_free(lut);
4498
4499         return ret;
4500 }
4501
4502 static int
4503 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4504                         struct rte_eth_rss_reta_entry64 *reta_conf,
4505                         uint16_t reta_size)
4506 {
4507         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4508         uint16_t i, lut_size = pf->hash_lut_size;
4509         uint16_t idx, shift;
4510         uint8_t *lut;
4511         int ret;
4512
4513         if (reta_size != lut_size ||
4514                 reta_size > ETH_RSS_RETA_SIZE_512) {
4515                 PMD_DRV_LOG(ERR,
4516                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4517                         reta_size, lut_size);
4518                 return -EINVAL;
4519         }
4520
4521         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4522         if (!lut) {
4523                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4524                 return -ENOMEM;
4525         }
4526
4527         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4528         if (ret)
4529                 goto out;
4530         for (i = 0; i < reta_size; i++) {
4531                 idx = i / RTE_RETA_GROUP_SIZE;
4532                 shift = i % RTE_RETA_GROUP_SIZE;
4533                 if (reta_conf[idx].mask & (1ULL << shift))
4534                         reta_conf[idx].reta[shift] = lut[i];
4535         }
4536
4537 out:
4538         rte_free(lut);
4539
4540         return ret;
4541 }
4542
4543 /**
4544  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4545  * @hw:   pointer to the HW structure
4546  * @mem:  pointer to mem struct to fill out
4547  * @size: size of memory requested
4548  * @alignment: what to align the allocation to
4549  **/
4550 enum i40e_status_code
4551 i40e_allocate_dma_mem_d(__rte_unused struct i40e_hw *hw,
4552                         struct i40e_dma_mem *mem,
4553                         u64 size,
4554                         u32 alignment)
4555 {
4556         const struct rte_memzone *mz = NULL;
4557         char z_name[RTE_MEMZONE_NAMESIZE];
4558
4559         if (!mem)
4560                 return I40E_ERR_PARAM;
4561
4562         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4563         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4564                         RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4565         if (!mz)
4566                 return I40E_ERR_NO_MEMORY;
4567
4568         mem->size = size;
4569         mem->va = mz->addr;
4570         mem->pa = mz->iova;
4571         mem->zone = (const void *)mz;
4572         PMD_DRV_LOG(DEBUG,
4573                 "memzone %s allocated with physical address: %"PRIu64,
4574                 mz->name, mem->pa);
4575
4576         return I40E_SUCCESS;
4577 }
4578
4579 /**
4580  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4581  * @hw:   pointer to the HW structure
4582  * @mem:  ptr to mem struct to free
4583  **/
4584 enum i40e_status_code
4585 i40e_free_dma_mem_d(__rte_unused struct i40e_hw *hw,
4586                     struct i40e_dma_mem *mem)
4587 {
4588         if (!mem)
4589                 return I40E_ERR_PARAM;
4590
4591         PMD_DRV_LOG(DEBUG,
4592                 "memzone %s to be freed with physical address: %"PRIu64,
4593                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4594         rte_memzone_free((const struct rte_memzone *)mem->zone);
4595         mem->zone = NULL;
4596         mem->va = NULL;
4597         mem->pa = (u64)0;
4598
4599         return I40E_SUCCESS;
4600 }
4601
4602 /**
4603  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4604  * @hw:   pointer to the HW structure
4605  * @mem:  pointer to mem struct to fill out
4606  * @size: size of memory requested
4607  **/
4608 enum i40e_status_code
4609 i40e_allocate_virt_mem_d(__rte_unused struct i40e_hw *hw,
4610                          struct i40e_virt_mem *mem,
4611                          u32 size)
4612 {
4613         if (!mem)
4614                 return I40E_ERR_PARAM;
4615
4616         mem->size = size;
4617         mem->va = rte_zmalloc("i40e", size, 0);
4618
4619         if (mem->va)
4620                 return I40E_SUCCESS;
4621         else
4622                 return I40E_ERR_NO_MEMORY;
4623 }
4624
4625 /**
4626  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4627  * @hw:   pointer to the HW structure
4628  * @mem:  pointer to mem struct to free
4629  **/
4630 enum i40e_status_code
4631 i40e_free_virt_mem_d(__rte_unused struct i40e_hw *hw,
4632                      struct i40e_virt_mem *mem)
4633 {
4634         if (!mem)
4635                 return I40E_ERR_PARAM;
4636
4637         rte_free(mem->va);
4638         mem->va = NULL;
4639
4640         return I40E_SUCCESS;
4641 }
4642
4643 void
4644 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4645 {
4646         rte_spinlock_init(&sp->spinlock);
4647 }
4648
4649 void
4650 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4651 {
4652         rte_spinlock_lock(&sp->spinlock);
4653 }
4654
4655 void
4656 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4657 {
4658         rte_spinlock_unlock(&sp->spinlock);
4659 }
4660
4661 void
4662 i40e_destroy_spinlock_d(__rte_unused struct i40e_spinlock *sp)
4663 {
4664         return;
4665 }
4666
4667 /**
4668  * Get the hardware capabilities, which will be parsed
4669  * and saved into struct i40e_hw.
4670  */
4671 static int
4672 i40e_get_cap(struct i40e_hw *hw)
4673 {
4674         struct i40e_aqc_list_capabilities_element_resp *buf;
4675         uint16_t len, size = 0;
4676         int ret;
4677
4678         /* Calculate a huge enough buff for saving response data temporarily */
4679         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4680                                                 I40E_MAX_CAP_ELE_NUM;
4681         buf = rte_zmalloc("i40e", len, 0);
4682         if (!buf) {
4683                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4684                 return I40E_ERR_NO_MEMORY;
4685         }
4686
4687         /* Get, parse the capabilities and save it to hw */
4688         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4689                         i40e_aqc_opc_list_func_capabilities, NULL);
4690         if (ret != I40E_SUCCESS)
4691                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4692
4693         /* Free the temporary buffer after being used */
4694         rte_free(buf);
4695
4696         return ret;
4697 }
4698
4699 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF        4
4700
4701 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4702                 const char *value,
4703                 void *opaque)
4704 {
4705         struct i40e_pf *pf;
4706         unsigned long num;
4707         char *end;
4708
4709         pf = (struct i40e_pf *)opaque;
4710         RTE_SET_USED(key);
4711
4712         errno = 0;
4713         num = strtoul(value, &end, 0);
4714         if (errno != 0 || end == value || *end != 0) {
4715                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4716                             "kept the value = %hu", value, pf->vf_nb_qp_max);
4717                 return -(EINVAL);
4718         }
4719
4720         if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4721                 pf->vf_nb_qp_max = (uint16_t)num;
4722         else
4723                 /* here return 0 to make next valid same argument work */
4724                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4725                             "power of 2 and equal or less than 16 !, Now it is "
4726                             "kept the value = %hu", num, pf->vf_nb_qp_max);
4727
4728         return 0;
4729 }
4730
4731 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4732 {
4733         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4734         struct rte_kvargs *kvlist;
4735         int kvargs_count;
4736
4737         /* set default queue number per VF as 4 */
4738         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4739
4740         if (dev->device->devargs == NULL)
4741                 return 0;
4742
4743         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4744         if (kvlist == NULL)
4745                 return -(EINVAL);
4746
4747         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4748         if (!kvargs_count) {
4749                 rte_kvargs_free(kvlist);
4750                 return 0;
4751         }
4752
4753         if (kvargs_count > 1)
4754                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4755                             "the first invalid or last valid one is used !",
4756                             ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4757
4758         rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4759                            i40e_pf_parse_vf_queue_number_handler, pf);
4760
4761         rte_kvargs_free(kvlist);
4762
4763         return 0;
4764 }
4765
4766 static int
4767 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4768 {
4769         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4770         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4771         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4772         uint16_t qp_count = 0, vsi_count = 0;
4773
4774         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4775                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4776                 return -EINVAL;
4777         }
4778
4779         i40e_pf_config_vf_rxq_number(dev);
4780
4781         /* Add the parameter init for LFC */
4782         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4783         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4784         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4785
4786         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4787         pf->max_num_vsi = hw->func_caps.num_vsis;
4788         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4789         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4790
4791         /* FDir queue/VSI allocation */
4792         pf->fdir_qp_offset = 0;
4793         if (hw->func_caps.fd) {
4794                 pf->flags |= I40E_FLAG_FDIR;
4795                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4796         } else {
4797                 pf->fdir_nb_qps = 0;
4798         }
4799         qp_count += pf->fdir_nb_qps;
4800         vsi_count += 1;
4801
4802         /* LAN queue/VSI allocation */
4803         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4804         if (!hw->func_caps.rss) {
4805                 pf->lan_nb_qps = 1;
4806         } else {
4807                 pf->flags |= I40E_FLAG_RSS;
4808                 if (hw->mac.type == I40E_MAC_X722)
4809                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4810                 pf->lan_nb_qps = pf->lan_nb_qp_max;
4811         }
4812         qp_count += pf->lan_nb_qps;
4813         vsi_count += 1;
4814
4815         /* VF queue/VSI allocation */
4816         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4817         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4818                 pf->flags |= I40E_FLAG_SRIOV;
4819                 pf->vf_nb_qps = pf->vf_nb_qp_max;
4820                 pf->vf_num = pci_dev->max_vfs;
4821                 PMD_DRV_LOG(DEBUG,
4822                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4823                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4824         } else {
4825                 pf->vf_nb_qps = 0;
4826                 pf->vf_num = 0;
4827         }
4828         qp_count += pf->vf_nb_qps * pf->vf_num;
4829         vsi_count += pf->vf_num;
4830
4831         /* VMDq queue/VSI allocation */
4832         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4833         pf->vmdq_nb_qps = 0;
4834         pf->max_nb_vmdq_vsi = 0;
4835         if (hw->func_caps.vmdq) {
4836                 if (qp_count < hw->func_caps.num_tx_qp &&
4837                         vsi_count < hw->func_caps.num_vsis) {
4838                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4839                                 qp_count) / pf->vmdq_nb_qp_max;
4840
4841                         /* Limit the maximum number of VMDq vsi to the maximum
4842                          * ethdev can support
4843                          */
4844                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4845                                 hw->func_caps.num_vsis - vsi_count);
4846                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4847                                 ETH_64_POOLS);
4848                         if (pf->max_nb_vmdq_vsi) {
4849                                 pf->flags |= I40E_FLAG_VMDQ;
4850                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4851                                 PMD_DRV_LOG(DEBUG,
4852                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4853                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4854                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4855                         } else {
4856                                 PMD_DRV_LOG(INFO,
4857                                         "No enough queues left for VMDq");
4858                         }
4859                 } else {
4860                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4861                 }
4862         }
4863         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4864         vsi_count += pf->max_nb_vmdq_vsi;
4865
4866         if (hw->func_caps.dcb)
4867                 pf->flags |= I40E_FLAG_DCB;
4868
4869         if (qp_count > hw->func_caps.num_tx_qp) {
4870                 PMD_DRV_LOG(ERR,
4871                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4872                         qp_count, hw->func_caps.num_tx_qp);
4873                 return -EINVAL;
4874         }
4875         if (vsi_count > hw->func_caps.num_vsis) {
4876                 PMD_DRV_LOG(ERR,
4877                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4878                         vsi_count, hw->func_caps.num_vsis);
4879                 return -EINVAL;
4880         }
4881
4882         return 0;
4883 }
4884
4885 static int
4886 i40e_pf_get_switch_config(struct i40e_pf *pf)
4887 {
4888         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4889         struct i40e_aqc_get_switch_config_resp *switch_config;
4890         struct i40e_aqc_switch_config_element_resp *element;
4891         uint16_t start_seid = 0, num_reported;
4892         int ret;
4893
4894         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4895                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4896         if (!switch_config) {
4897                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4898                 return -ENOMEM;
4899         }
4900
4901         /* Get the switch configurations */
4902         ret = i40e_aq_get_switch_config(hw, switch_config,
4903                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4904         if (ret != I40E_SUCCESS) {
4905                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4906                 goto fail;
4907         }
4908         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4909         if (num_reported != 1) { /* The number should be 1 */
4910                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4911                 goto fail;
4912         }
4913
4914         /* Parse the switch configuration elements */
4915         element = &(switch_config->element[0]);
4916         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4917                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4918                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4919         } else
4920                 PMD_DRV_LOG(INFO, "Unknown element type");
4921
4922 fail:
4923         rte_free(switch_config);
4924
4925         return ret;
4926 }
4927
4928 static int
4929 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4930                         uint32_t num)
4931 {
4932         struct pool_entry *entry;
4933
4934         if (pool == NULL || num == 0)
4935                 return -EINVAL;
4936
4937         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4938         if (entry == NULL) {
4939                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4940                 return -ENOMEM;
4941         }
4942
4943         /* queue heap initialize */
4944         pool->num_free = num;
4945         pool->num_alloc = 0;
4946         pool->base = base;
4947         LIST_INIT(&pool->alloc_list);
4948         LIST_INIT(&pool->free_list);
4949
4950         /* Initialize element  */
4951         entry->base = 0;
4952         entry->len = num;
4953
4954         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4955         return 0;
4956 }
4957
4958 static void
4959 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4960 {
4961         struct pool_entry *entry, *next_entry;
4962
4963         if (pool == NULL)
4964                 return;
4965
4966         for (entry = LIST_FIRST(&pool->alloc_list);
4967                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4968                         entry = next_entry) {
4969                 LIST_REMOVE(entry, next);
4970                 rte_free(entry);
4971         }
4972
4973         for (entry = LIST_FIRST(&pool->free_list);
4974                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4975                         entry = next_entry) {
4976                 LIST_REMOVE(entry, next);
4977                 rte_free(entry);
4978         }
4979
4980         pool->num_free = 0;
4981         pool->num_alloc = 0;
4982         pool->base = 0;
4983         LIST_INIT(&pool->alloc_list);
4984         LIST_INIT(&pool->free_list);
4985 }
4986
4987 static int
4988 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4989                        uint32_t base)
4990 {
4991         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4992         uint32_t pool_offset;
4993         uint16_t len;
4994         int insert;
4995
4996         if (pool == NULL) {
4997                 PMD_DRV_LOG(ERR, "Invalid parameter");
4998                 return -EINVAL;
4999         }
5000
5001         pool_offset = base - pool->base;
5002         /* Lookup in alloc list */
5003         LIST_FOREACH(entry, &pool->alloc_list, next) {
5004                 if (entry->base == pool_offset) {
5005                         valid_entry = entry;
5006                         LIST_REMOVE(entry, next);
5007                         break;
5008                 }
5009         }
5010
5011         /* Not find, return */
5012         if (valid_entry == NULL) {
5013                 PMD_DRV_LOG(ERR, "Failed to find entry");
5014                 return -EINVAL;
5015         }
5016
5017         /**
5018          * Found it, move it to free list  and try to merge.
5019          * In order to make merge easier, always sort it by qbase.
5020          * Find adjacent prev and last entries.
5021          */
5022         prev = next = NULL;
5023         LIST_FOREACH(entry, &pool->free_list, next) {
5024                 if (entry->base > valid_entry->base) {
5025                         next = entry;
5026                         break;
5027                 }
5028                 prev = entry;
5029         }
5030
5031         insert = 0;
5032         len = valid_entry->len;
5033         /* Try to merge with next one*/
5034         if (next != NULL) {
5035                 /* Merge with next one */
5036                 if (valid_entry->base + len == next->base) {
5037                         next->base = valid_entry->base;
5038                         next->len += len;
5039                         rte_free(valid_entry);
5040                         valid_entry = next;
5041                         insert = 1;
5042                 }
5043         }
5044
5045         if (prev != NULL) {
5046                 /* Merge with previous one */
5047                 if (prev->base + prev->len == valid_entry->base) {
5048                         prev->len += len;
5049                         /* If it merge with next one, remove next node */
5050                         if (insert == 1) {
5051                                 LIST_REMOVE(valid_entry, next);
5052                                 rte_free(valid_entry);
5053                                 valid_entry = NULL;
5054                         } else {
5055                                 rte_free(valid_entry);
5056                                 valid_entry = NULL;
5057                                 insert = 1;
5058                         }
5059                 }
5060         }
5061
5062         /* Not find any entry to merge, insert */
5063         if (insert == 0) {
5064                 if (prev != NULL)
5065                         LIST_INSERT_AFTER(prev, valid_entry, next);
5066                 else if (next != NULL)
5067                         LIST_INSERT_BEFORE(next, valid_entry, next);
5068                 else /* It's empty list, insert to head */
5069                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
5070         }
5071
5072         pool->num_free += len;
5073         pool->num_alloc -= len;
5074
5075         return 0;
5076 }
5077
5078 static int
5079 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
5080                        uint16_t num)
5081 {
5082         struct pool_entry *entry, *valid_entry;
5083
5084         if (pool == NULL || num == 0) {
5085                 PMD_DRV_LOG(ERR, "Invalid parameter");
5086                 return -EINVAL;
5087         }
5088
5089         if (pool->num_free < num) {
5090                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
5091                             num, pool->num_free);
5092                 return -ENOMEM;
5093         }
5094
5095         valid_entry = NULL;
5096         /* Lookup  in free list and find most fit one */
5097         LIST_FOREACH(entry, &pool->free_list, next) {
5098                 if (entry->len >= num) {
5099                         /* Find best one */
5100                         if (entry->len == num) {
5101                                 valid_entry = entry;
5102                                 break;
5103                         }
5104                         if (valid_entry == NULL || valid_entry->len > entry->len)
5105                                 valid_entry = entry;
5106                 }
5107         }
5108
5109         /* Not find one to satisfy the request, return */
5110         if (valid_entry == NULL) {
5111                 PMD_DRV_LOG(ERR, "No valid entry found");
5112                 return -ENOMEM;
5113         }
5114         /**
5115          * The entry have equal queue number as requested,
5116          * remove it from alloc_list.
5117          */
5118         if (valid_entry->len == num) {
5119                 LIST_REMOVE(valid_entry, next);
5120         } else {
5121                 /**
5122                  * The entry have more numbers than requested,
5123                  * create a new entry for alloc_list and minus its
5124                  * queue base and number in free_list.
5125                  */
5126                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
5127                 if (entry == NULL) {
5128                         PMD_DRV_LOG(ERR,
5129                                 "Failed to allocate memory for resource pool");
5130                         return -ENOMEM;
5131                 }
5132                 entry->base = valid_entry->base;
5133                 entry->len = num;
5134                 valid_entry->base += num;
5135                 valid_entry->len -= num;
5136                 valid_entry = entry;
5137         }
5138
5139         /* Insert it into alloc list, not sorted */
5140         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
5141
5142         pool->num_free -= valid_entry->len;
5143         pool->num_alloc += valid_entry->len;
5144
5145         return valid_entry->base + pool->base;
5146 }
5147
5148 /**
5149  * bitmap_is_subset - Check whether src2 is subset of src1
5150  **/
5151 static inline int
5152 bitmap_is_subset(uint8_t src1, uint8_t src2)
5153 {
5154         return !((src1 ^ src2) & src2);
5155 }
5156
5157 static enum i40e_status_code
5158 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5159 {
5160         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5161
5162         /* If DCB is not supported, only default TC is supported */
5163         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
5164                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
5165                 return I40E_NOT_SUPPORTED;
5166         }
5167
5168         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
5169                 PMD_DRV_LOG(ERR,
5170                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
5171                         hw->func_caps.enabled_tcmap, enabled_tcmap);
5172                 return I40E_NOT_SUPPORTED;
5173         }
5174         return I40E_SUCCESS;
5175 }
5176
5177 int
5178 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
5179                                 struct i40e_vsi_vlan_pvid_info *info)
5180 {
5181         struct i40e_hw *hw;
5182         struct i40e_vsi_context ctxt;
5183         uint8_t vlan_flags = 0;
5184         int ret;
5185
5186         if (vsi == NULL || info == NULL) {
5187                 PMD_DRV_LOG(ERR, "invalid parameters");
5188                 return I40E_ERR_PARAM;
5189         }
5190
5191         if (info->on) {
5192                 vsi->info.pvid = info->config.pvid;
5193                 /**
5194                  * If insert pvid is enabled, only tagged pkts are
5195                  * allowed to be sent out.
5196                  */
5197                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
5198                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5199         } else {
5200                 vsi->info.pvid = 0;
5201                 if (info->config.reject.tagged == 0)
5202                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5203
5204                 if (info->config.reject.untagged == 0)
5205                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
5206         }
5207         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
5208                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
5209         vsi->info.port_vlan_flags |= vlan_flags;
5210         vsi->info.valid_sections =
5211                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5212         memset(&ctxt, 0, sizeof(ctxt));
5213         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5214         ctxt.seid = vsi->seid;
5215
5216         hw = I40E_VSI_TO_HW(vsi);
5217         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5218         if (ret != I40E_SUCCESS)
5219                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5220
5221         return ret;
5222 }
5223
5224 static int
5225 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5226 {
5227         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5228         int i, ret;
5229         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
5230
5231         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5232         if (ret != I40E_SUCCESS)
5233                 return ret;
5234
5235         if (!vsi->seid) {
5236                 PMD_DRV_LOG(ERR, "seid not valid");
5237                 return -EINVAL;
5238         }
5239
5240         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
5241         tc_bw_data.tc_valid_bits = enabled_tcmap;
5242         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5243                 tc_bw_data.tc_bw_credits[i] =
5244                         (enabled_tcmap & (1 << i)) ? 1 : 0;
5245
5246         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5247         if (ret != I40E_SUCCESS) {
5248                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5249                 return ret;
5250         }
5251
5252         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5253                                         sizeof(vsi->info.qs_handle));
5254         return I40E_SUCCESS;
5255 }
5256
5257 static enum i40e_status_code
5258 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5259                                  struct i40e_aqc_vsi_properties_data *info,
5260                                  uint8_t enabled_tcmap)
5261 {
5262         enum i40e_status_code ret;
5263         int i, total_tc = 0;
5264         uint16_t qpnum_per_tc, bsf, qp_idx;
5265
5266         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5267         if (ret != I40E_SUCCESS)
5268                 return ret;
5269
5270         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5271                 if (enabled_tcmap & (1 << i))
5272                         total_tc++;
5273         if (total_tc == 0)
5274                 total_tc = 1;
5275         vsi->enabled_tc = enabled_tcmap;
5276
5277         /* Number of queues per enabled TC */
5278         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5279         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5280         bsf = rte_bsf32(qpnum_per_tc);
5281
5282         /* Adjust the queue number to actual queues that can be applied */
5283         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5284                 vsi->nb_qps = qpnum_per_tc * total_tc;
5285
5286         /**
5287          * Configure TC and queue mapping parameters, for enabled TC,
5288          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5289          * default queue will serve it.
5290          */
5291         qp_idx = 0;
5292         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5293                 if (vsi->enabled_tc & (1 << i)) {
5294                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5295                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5296                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5297                         qp_idx += qpnum_per_tc;
5298                 } else
5299                         info->tc_mapping[i] = 0;
5300         }
5301
5302         /* Associate queue number with VSI */
5303         if (vsi->type == I40E_VSI_SRIOV) {
5304                 info->mapping_flags |=
5305                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5306                 for (i = 0; i < vsi->nb_qps; i++)
5307                         info->queue_mapping[i] =
5308                                 rte_cpu_to_le_16(vsi->base_queue + i);
5309         } else {
5310                 info->mapping_flags |=
5311                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5312                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5313         }
5314         info->valid_sections |=
5315                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5316
5317         return I40E_SUCCESS;
5318 }
5319
5320 static int
5321 i40e_veb_release(struct i40e_veb *veb)
5322 {
5323         struct i40e_vsi *vsi;
5324         struct i40e_hw *hw;
5325
5326         if (veb == NULL)
5327                 return -EINVAL;
5328
5329         if (!TAILQ_EMPTY(&veb->head)) {
5330                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5331                 return -EACCES;
5332         }
5333         /* associate_vsi field is NULL for floating VEB */
5334         if (veb->associate_vsi != NULL) {
5335                 vsi = veb->associate_vsi;
5336                 hw = I40E_VSI_TO_HW(vsi);
5337
5338                 vsi->uplink_seid = veb->uplink_seid;
5339                 vsi->veb = NULL;
5340         } else {
5341                 veb->associate_pf->main_vsi->floating_veb = NULL;
5342                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5343         }
5344
5345         i40e_aq_delete_element(hw, veb->seid, NULL);
5346         rte_free(veb);
5347         return I40E_SUCCESS;
5348 }
5349
5350 /* Setup a veb */
5351 static struct i40e_veb *
5352 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5353 {
5354         struct i40e_veb *veb;
5355         int ret;
5356         struct i40e_hw *hw;
5357
5358         if (pf == NULL) {
5359                 PMD_DRV_LOG(ERR,
5360                             "veb setup failed, associated PF shouldn't null");
5361                 return NULL;
5362         }
5363         hw = I40E_PF_TO_HW(pf);
5364
5365         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5366         if (!veb) {
5367                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5368                 goto fail;
5369         }
5370
5371         veb->associate_vsi = vsi;
5372         veb->associate_pf = pf;
5373         TAILQ_INIT(&veb->head);
5374         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5375
5376         /* create floating veb if vsi is NULL */
5377         if (vsi != NULL) {
5378                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5379                                       I40E_DEFAULT_TCMAP, false,
5380                                       &veb->seid, false, NULL);
5381         } else {
5382                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5383                                       true, &veb->seid, false, NULL);
5384         }
5385
5386         if (ret != I40E_SUCCESS) {
5387                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5388                             hw->aq.asq_last_status);
5389                 goto fail;
5390         }
5391         veb->enabled_tc = I40E_DEFAULT_TCMAP;
5392
5393         /* get statistics index */
5394         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5395                                 &veb->stats_idx, NULL, NULL, NULL);
5396         if (ret != I40E_SUCCESS) {
5397                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5398                             hw->aq.asq_last_status);
5399                 goto fail;
5400         }
5401         /* Get VEB bandwidth, to be implemented */
5402         /* Now associated vsi binding to the VEB, set uplink to this VEB */
5403         if (vsi)
5404                 vsi->uplink_seid = veb->seid;
5405
5406         return veb;
5407 fail:
5408         rte_free(veb);
5409         return NULL;
5410 }
5411
5412 int
5413 i40e_vsi_release(struct i40e_vsi *vsi)
5414 {
5415         struct i40e_pf *pf;
5416         struct i40e_hw *hw;
5417         struct i40e_vsi_list *vsi_list;
5418         void *temp;
5419         int ret;
5420         struct i40e_mac_filter *f;
5421         uint16_t user_param;
5422
5423         if (!vsi)
5424                 return I40E_SUCCESS;
5425
5426         if (!vsi->adapter)
5427                 return -EFAULT;
5428
5429         user_param = vsi->user_param;
5430
5431         pf = I40E_VSI_TO_PF(vsi);
5432         hw = I40E_VSI_TO_HW(vsi);
5433
5434         /* VSI has child to attach, release child first */
5435         if (vsi->veb) {
5436                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5437                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5438                                 return -1;
5439                 }
5440                 i40e_veb_release(vsi->veb);
5441         }
5442
5443         if (vsi->floating_veb) {
5444                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5445                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5446                                 return -1;
5447                 }
5448         }
5449
5450         /* Remove all macvlan filters of the VSI */
5451         i40e_vsi_remove_all_macvlan_filter(vsi);
5452         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5453                 rte_free(f);
5454
5455         if (vsi->type != I40E_VSI_MAIN &&
5456             ((vsi->type != I40E_VSI_SRIOV) ||
5457             !pf->floating_veb_list[user_param])) {
5458                 /* Remove vsi from parent's sibling list */
5459                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5460                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5461                         return I40E_ERR_PARAM;
5462                 }
5463                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5464                                 &vsi->sib_vsi_list, list);
5465
5466                 /* Remove all switch element of the VSI */
5467                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5468                 if (ret != I40E_SUCCESS)
5469                         PMD_DRV_LOG(ERR, "Failed to delete element");
5470         }
5471
5472         if ((vsi->type == I40E_VSI_SRIOV) &&
5473             pf->floating_veb_list[user_param]) {
5474                 /* Remove vsi from parent's sibling list */
5475                 if (vsi->parent_vsi == NULL ||
5476                     vsi->parent_vsi->floating_veb == NULL) {
5477                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5478                         return I40E_ERR_PARAM;
5479                 }
5480                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5481                              &vsi->sib_vsi_list, list);
5482
5483                 /* Remove all switch element of the VSI */
5484                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5485                 if (ret != I40E_SUCCESS)
5486                         PMD_DRV_LOG(ERR, "Failed to delete element");
5487         }
5488
5489         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5490
5491         if (vsi->type != I40E_VSI_SRIOV)
5492                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5493         rte_free(vsi);
5494
5495         return I40E_SUCCESS;
5496 }
5497
5498 static int
5499 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5500 {
5501         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5502         struct i40e_aqc_remove_macvlan_element_data def_filter;
5503         struct i40e_mac_filter_info filter;
5504         int ret;
5505
5506         if (vsi->type != I40E_VSI_MAIN)
5507                 return I40E_ERR_CONFIG;
5508         memset(&def_filter, 0, sizeof(def_filter));
5509         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5510                                         ETH_ADDR_LEN);
5511         def_filter.vlan_tag = 0;
5512         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5513                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5514         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5515         if (ret != I40E_SUCCESS) {
5516                 struct i40e_mac_filter *f;
5517                 struct rte_ether_addr *mac;
5518
5519                 PMD_DRV_LOG(DEBUG,
5520                             "Cannot remove the default macvlan filter");
5521                 /* It needs to add the permanent mac into mac list */
5522                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5523                 if (f == NULL) {
5524                         PMD_DRV_LOG(ERR, "failed to allocate memory");
5525                         return I40E_ERR_NO_MEMORY;
5526                 }
5527                 mac = &f->mac_info.mac_addr;
5528                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5529                                 ETH_ADDR_LEN);
5530                 f->mac_info.filter_type = I40E_MACVLAN_PERFECT_MATCH;
5531                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5532                 vsi->mac_num++;
5533
5534                 return ret;
5535         }
5536         rte_memcpy(&filter.mac_addr,
5537                 (struct rte_ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5538         filter.filter_type = I40E_MACVLAN_PERFECT_MATCH;
5539         return i40e_vsi_add_mac(vsi, &filter);
5540 }
5541
5542 /*
5543  * i40e_vsi_get_bw_config - Query VSI BW Information
5544  * @vsi: the VSI to be queried
5545  *
5546  * Returns 0 on success, negative value on failure
5547  */
5548 static enum i40e_status_code
5549 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5550 {
5551         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5552         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5553         struct i40e_hw *hw = &vsi->adapter->hw;
5554         i40e_status ret;
5555         int i;
5556         uint32_t bw_max;
5557
5558         memset(&bw_config, 0, sizeof(bw_config));
5559         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5560         if (ret != I40E_SUCCESS) {
5561                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5562                             hw->aq.asq_last_status);
5563                 return ret;
5564         }
5565
5566         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5567         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5568                                         &ets_sla_config, NULL);
5569         if (ret != I40E_SUCCESS) {
5570                 PMD_DRV_LOG(ERR,
5571                         "VSI failed to get TC bandwdith configuration %u",
5572                         hw->aq.asq_last_status);
5573                 return ret;
5574         }
5575
5576         /* store and print out BW info */
5577         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5578         vsi->bw_info.bw_max = bw_config.max_bw;
5579         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5580         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5581         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5582                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5583                      I40E_16_BIT_WIDTH);
5584         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5585                 vsi->bw_info.bw_ets_share_credits[i] =
5586                                 ets_sla_config.share_credits[i];
5587                 vsi->bw_info.bw_ets_credits[i] =
5588                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5589                 /* 4 bits per TC, 4th bit is reserved */
5590                 vsi->bw_info.bw_ets_max[i] =
5591                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5592                                   RTE_LEN2MASK(3, uint8_t));
5593                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5594                             vsi->bw_info.bw_ets_share_credits[i]);
5595                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5596                             vsi->bw_info.bw_ets_credits[i]);
5597                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5598                             vsi->bw_info.bw_ets_max[i]);
5599         }
5600
5601         return I40E_SUCCESS;
5602 }
5603
5604 /* i40e_enable_pf_lb
5605  * @pf: pointer to the pf structure
5606  *
5607  * allow loopback on pf
5608  */
5609 static inline void
5610 i40e_enable_pf_lb(struct i40e_pf *pf)
5611 {
5612         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5613         struct i40e_vsi_context ctxt;
5614         int ret;
5615
5616         /* Use the FW API if FW >= v5.0 */
5617         if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
5618                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5619                 return;
5620         }
5621
5622         memset(&ctxt, 0, sizeof(ctxt));
5623         ctxt.seid = pf->main_vsi_seid;
5624         ctxt.pf_num = hw->pf_id;
5625         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5626         if (ret) {
5627                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5628                             ret, hw->aq.asq_last_status);
5629                 return;
5630         }
5631         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5632         ctxt.info.valid_sections =
5633                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5634         ctxt.info.switch_id |=
5635                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5636
5637         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5638         if (ret)
5639                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5640                             hw->aq.asq_last_status);
5641 }
5642
5643 /* Setup a VSI */
5644 struct i40e_vsi *
5645 i40e_vsi_setup(struct i40e_pf *pf,
5646                enum i40e_vsi_type type,
5647                struct i40e_vsi *uplink_vsi,
5648                uint16_t user_param)
5649 {
5650         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5651         struct i40e_vsi *vsi;
5652         struct i40e_mac_filter_info filter;
5653         int ret;
5654         struct i40e_vsi_context ctxt;
5655         struct rte_ether_addr broadcast =
5656                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5657
5658         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5659             uplink_vsi == NULL) {
5660                 PMD_DRV_LOG(ERR,
5661                         "VSI setup failed, VSI link shouldn't be NULL");
5662                 return NULL;
5663         }
5664
5665         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5666                 PMD_DRV_LOG(ERR,
5667                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5668                 return NULL;
5669         }
5670
5671         /* two situations
5672          * 1.type is not MAIN and uplink vsi is not NULL
5673          * If uplink vsi didn't setup VEB, create one first under veb field
5674          * 2.type is SRIOV and the uplink is NULL
5675          * If floating VEB is NULL, create one veb under floating veb field
5676          */
5677
5678         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5679             uplink_vsi->veb == NULL) {
5680                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5681
5682                 if (uplink_vsi->veb == NULL) {
5683                         PMD_DRV_LOG(ERR, "VEB setup failed");
5684                         return NULL;
5685                 }
5686                 /* set ALLOWLOOPBACk on pf, when veb is created */
5687                 i40e_enable_pf_lb(pf);
5688         }
5689
5690         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5691             pf->main_vsi->floating_veb == NULL) {
5692                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5693
5694                 if (pf->main_vsi->floating_veb == NULL) {
5695                         PMD_DRV_LOG(ERR, "VEB setup failed");
5696                         return NULL;
5697                 }
5698         }
5699
5700         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5701         if (!vsi) {
5702                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5703                 return NULL;
5704         }
5705         TAILQ_INIT(&vsi->mac_list);
5706         vsi->type = type;
5707         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5708         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5709         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5710         vsi->user_param = user_param;
5711         vsi->vlan_anti_spoof_on = 0;
5712         vsi->vlan_filter_on = 0;
5713         /* Allocate queues */
5714         switch (vsi->type) {
5715         case I40E_VSI_MAIN  :
5716                 vsi->nb_qps = pf->lan_nb_qps;
5717                 break;
5718         case I40E_VSI_SRIOV :
5719                 vsi->nb_qps = pf->vf_nb_qps;
5720                 break;
5721         case I40E_VSI_VMDQ2:
5722                 vsi->nb_qps = pf->vmdq_nb_qps;
5723                 break;
5724         case I40E_VSI_FDIR:
5725                 vsi->nb_qps = pf->fdir_nb_qps;
5726                 break;
5727         default:
5728                 goto fail_mem;
5729         }
5730         /*
5731          * The filter status descriptor is reported in rx queue 0,
5732          * while the tx queue for fdir filter programming has no
5733          * such constraints, can be non-zero queues.
5734          * To simplify it, choose FDIR vsi use queue 0 pair.
5735          * To make sure it will use queue 0 pair, queue allocation
5736          * need be done before this function is called
5737          */
5738         if (type != I40E_VSI_FDIR) {
5739                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5740                         if (ret < 0) {
5741                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5742                                                 vsi->seid, ret);
5743                                 goto fail_mem;
5744                         }
5745                         vsi->base_queue = ret;
5746         } else
5747                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5748
5749         /* VF has MSIX interrupt in VF range, don't allocate here */
5750         if (type == I40E_VSI_MAIN) {
5751                 if (pf->support_multi_driver) {
5752                         /* If support multi-driver, need to use INT0 instead of
5753                          * allocating from msix pool. The Msix pool is init from
5754                          * INT1, so it's OK just set msix_intr to 0 and nb_msix
5755                          * to 1 without calling i40e_res_pool_alloc.
5756                          */
5757                         vsi->msix_intr = 0;
5758                         vsi->nb_msix = 1;
5759                 } else {
5760                         ret = i40e_res_pool_alloc(&pf->msix_pool,
5761                                                   RTE_MIN(vsi->nb_qps,
5762                                                      RTE_MAX_RXTX_INTR_VEC_ID));
5763                         if (ret < 0) {
5764                                 PMD_DRV_LOG(ERR,
5765                                             "VSI MAIN %d get heap failed %d",
5766                                             vsi->seid, ret);
5767                                 goto fail_queue_alloc;
5768                         }
5769                         vsi->msix_intr = ret;
5770                         vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5771                                                RTE_MAX_RXTX_INTR_VEC_ID);
5772                 }
5773         } else if (type != I40E_VSI_SRIOV) {
5774                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5775                 if (ret < 0) {
5776                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5777                         if (type != I40E_VSI_FDIR)
5778                                 goto fail_queue_alloc;
5779                         vsi->msix_intr = 0;
5780                         vsi->nb_msix = 0;
5781                 } else {
5782                         vsi->msix_intr = ret;
5783                         vsi->nb_msix = 1;
5784                 }
5785         } else {
5786                 vsi->msix_intr = 0;
5787                 vsi->nb_msix = 0;
5788         }
5789
5790         /* Add VSI */
5791         if (type == I40E_VSI_MAIN) {
5792                 /* For main VSI, no need to add since it's default one */
5793                 vsi->uplink_seid = pf->mac_seid;
5794                 vsi->seid = pf->main_vsi_seid;
5795                 /* Bind queues with specific MSIX interrupt */
5796                 /**
5797                  * Needs 2 interrupt at least, one for misc cause which will
5798                  * enabled from OS side, Another for queues binding the
5799                  * interrupt from device side only.
5800                  */
5801
5802                 /* Get default VSI parameters from hardware */
5803                 memset(&ctxt, 0, sizeof(ctxt));
5804                 ctxt.seid = vsi->seid;
5805                 ctxt.pf_num = hw->pf_id;
5806                 ctxt.uplink_seid = vsi->uplink_seid;
5807                 ctxt.vf_num = 0;
5808                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5809                 if (ret != I40E_SUCCESS) {
5810                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
5811                         goto fail_msix_alloc;
5812                 }
5813                 rte_memcpy(&vsi->info, &ctxt.info,
5814                         sizeof(struct i40e_aqc_vsi_properties_data));
5815                 vsi->vsi_id = ctxt.vsi_number;
5816                 vsi->info.valid_sections = 0;
5817
5818                 /* Configure tc, enabled TC0 only */
5819                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5820                         I40E_SUCCESS) {
5821                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5822                         goto fail_msix_alloc;
5823                 }
5824
5825                 /* TC, queue mapping */
5826                 memset(&ctxt, 0, sizeof(ctxt));
5827                 vsi->info.valid_sections |=
5828                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5829                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5830                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5831                 rte_memcpy(&ctxt.info, &vsi->info,
5832                         sizeof(struct i40e_aqc_vsi_properties_data));
5833                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5834                                                 I40E_DEFAULT_TCMAP);
5835                 if (ret != I40E_SUCCESS) {
5836                         PMD_DRV_LOG(ERR,
5837                                 "Failed to configure TC queue mapping");
5838                         goto fail_msix_alloc;
5839                 }
5840                 ctxt.seid = vsi->seid;
5841                 ctxt.pf_num = hw->pf_id;
5842                 ctxt.uplink_seid = vsi->uplink_seid;
5843                 ctxt.vf_num = 0;
5844
5845                 /* Update VSI parameters */
5846                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5847                 if (ret != I40E_SUCCESS) {
5848                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5849                         goto fail_msix_alloc;
5850                 }
5851
5852                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5853                                                 sizeof(vsi->info.tc_mapping));
5854                 rte_memcpy(&vsi->info.queue_mapping,
5855                                 &ctxt.info.queue_mapping,
5856                         sizeof(vsi->info.queue_mapping));
5857                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5858                 vsi->info.valid_sections = 0;
5859
5860                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5861                                 ETH_ADDR_LEN);
5862
5863                 /**
5864                  * Updating default filter settings are necessary to prevent
5865                  * reception of tagged packets.
5866                  * Some old firmware configurations load a default macvlan
5867                  * filter which accepts both tagged and untagged packets.
5868                  * The updating is to use a normal filter instead if needed.
5869                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5870                  * The firmware with correct configurations load the default
5871                  * macvlan filter which is expected and cannot be removed.
5872                  */
5873                 i40e_update_default_filter_setting(vsi);
5874                 i40e_config_qinq(hw, vsi);
5875         } else if (type == I40E_VSI_SRIOV) {
5876                 memset(&ctxt, 0, sizeof(ctxt));
5877                 /**
5878                  * For other VSI, the uplink_seid equals to uplink VSI's
5879                  * uplink_seid since they share same VEB
5880                  */
5881                 if (uplink_vsi == NULL)
5882                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5883                 else
5884                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5885                 ctxt.pf_num = hw->pf_id;
5886                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5887                 ctxt.uplink_seid = vsi->uplink_seid;
5888                 ctxt.connection_type = 0x1;
5889                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5890
5891                 /* Use the VEB configuration if FW >= v5.0 */
5892                 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
5893                         /* Configure switch ID */
5894                         ctxt.info.valid_sections |=
5895                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5896                         ctxt.info.switch_id =
5897                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5898                 }
5899
5900                 /* Configure port/vlan */
5901                 ctxt.info.valid_sections |=
5902                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5903                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5904                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5905                                                 hw->func_caps.enabled_tcmap);
5906                 if (ret != I40E_SUCCESS) {
5907                         PMD_DRV_LOG(ERR,
5908                                 "Failed to configure TC queue mapping");
5909                         goto fail_msix_alloc;
5910                 }
5911
5912                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5913                 ctxt.info.valid_sections |=
5914                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5915                 /**
5916                  * Since VSI is not created yet, only configure parameter,
5917                  * will add vsi below.
5918                  */
5919
5920                 i40e_config_qinq(hw, vsi);
5921         } else if (type == I40E_VSI_VMDQ2) {
5922                 memset(&ctxt, 0, sizeof(ctxt));
5923                 /*
5924                  * For other VSI, the uplink_seid equals to uplink VSI's
5925                  * uplink_seid since they share same VEB
5926                  */
5927                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5928                 ctxt.pf_num = hw->pf_id;
5929                 ctxt.vf_num = 0;
5930                 ctxt.uplink_seid = vsi->uplink_seid;
5931                 ctxt.connection_type = 0x1;
5932                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5933
5934                 ctxt.info.valid_sections |=
5935                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5936                 /* user_param carries flag to enable loop back */
5937                 if (user_param) {
5938                         ctxt.info.switch_id =
5939                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5940                         ctxt.info.switch_id |=
5941                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5942                 }
5943
5944                 /* Configure port/vlan */
5945                 ctxt.info.valid_sections |=
5946                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5947                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5948                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5949                                                 I40E_DEFAULT_TCMAP);
5950                 if (ret != I40E_SUCCESS) {
5951                         PMD_DRV_LOG(ERR,
5952                                 "Failed to configure TC queue mapping");
5953                         goto fail_msix_alloc;
5954                 }
5955                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5956                 ctxt.info.valid_sections |=
5957                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5958         } else if (type == I40E_VSI_FDIR) {
5959                 memset(&ctxt, 0, sizeof(ctxt));
5960                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5961                 ctxt.pf_num = hw->pf_id;
5962                 ctxt.vf_num = 0;
5963                 ctxt.uplink_seid = vsi->uplink_seid;
5964                 ctxt.connection_type = 0x1;     /* regular data port */
5965                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5966                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5967                                                 I40E_DEFAULT_TCMAP);
5968                 if (ret != I40E_SUCCESS) {
5969                         PMD_DRV_LOG(ERR,
5970                                 "Failed to configure TC queue mapping.");
5971                         goto fail_msix_alloc;
5972                 }
5973                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5974                 ctxt.info.valid_sections |=
5975                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5976         } else {
5977                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5978                 goto fail_msix_alloc;
5979         }
5980
5981         if (vsi->type != I40E_VSI_MAIN) {
5982                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5983                 if (ret != I40E_SUCCESS) {
5984                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5985                                     hw->aq.asq_last_status);
5986                         goto fail_msix_alloc;
5987                 }
5988                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5989                 vsi->info.valid_sections = 0;
5990                 vsi->seid = ctxt.seid;
5991                 vsi->vsi_id = ctxt.vsi_number;
5992                 vsi->sib_vsi_list.vsi = vsi;
5993                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5994                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5995                                           &vsi->sib_vsi_list, list);
5996                 } else {
5997                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5998                                           &vsi->sib_vsi_list, list);
5999                 }
6000         }
6001
6002         /* MAC/VLAN configuration */
6003         rte_memcpy(&filter.mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
6004         filter.filter_type = I40E_MACVLAN_PERFECT_MATCH;
6005
6006         ret = i40e_vsi_add_mac(vsi, &filter);
6007         if (ret != I40E_SUCCESS) {
6008                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
6009                 goto fail_msix_alloc;
6010         }
6011
6012         /* Get VSI BW information */
6013         i40e_vsi_get_bw_config(vsi);
6014         return vsi;
6015 fail_msix_alloc:
6016         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
6017 fail_queue_alloc:
6018         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
6019 fail_mem:
6020         rte_free(vsi);
6021         return NULL;
6022 }
6023
6024 /* Configure vlan filter on or off */
6025 int
6026 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
6027 {
6028         int i, num;
6029         struct i40e_mac_filter *f;
6030         void *temp;
6031         struct i40e_mac_filter_info *mac_filter;
6032         enum i40e_mac_filter_type desired_filter;
6033         int ret = I40E_SUCCESS;
6034
6035         if (on) {
6036                 /* Filter to match MAC and VLAN */
6037                 desired_filter = I40E_MACVLAN_PERFECT_MATCH;
6038         } else {
6039                 /* Filter to match only MAC */
6040                 desired_filter = I40E_MAC_PERFECT_MATCH;
6041         }
6042
6043         num = vsi->mac_num;
6044
6045         mac_filter = rte_zmalloc("mac_filter_info_data",
6046                                  num * sizeof(*mac_filter), 0);
6047         if (mac_filter == NULL) {
6048                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6049                 return I40E_ERR_NO_MEMORY;
6050         }
6051
6052         i = 0;
6053
6054         /* Remove all existing mac */
6055         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
6056                 mac_filter[i] = f->mac_info;
6057                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
6058                 if (ret) {
6059                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6060                                     on ? "enable" : "disable");
6061                         goto DONE;
6062                 }
6063                 i++;
6064         }
6065
6066         /* Override with new filter */
6067         for (i = 0; i < num; i++) {
6068                 mac_filter[i].filter_type = desired_filter;
6069                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
6070                 if (ret) {
6071                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6072                                     on ? "enable" : "disable");
6073                         goto DONE;
6074                 }
6075         }
6076
6077 DONE:
6078         rte_free(mac_filter);
6079         return ret;
6080 }
6081
6082 /* Configure vlan stripping on or off */
6083 int
6084 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
6085 {
6086         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6087         struct i40e_vsi_context ctxt;
6088         uint8_t vlan_flags;
6089         int ret = I40E_SUCCESS;
6090
6091         /* Check if it has been already on or off */
6092         if (vsi->info.valid_sections &
6093                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
6094                 if (on) {
6095                         if ((vsi->info.port_vlan_flags &
6096                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
6097                                 return 0; /* already on */
6098                 } else {
6099                         if ((vsi->info.port_vlan_flags &
6100                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
6101                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
6102                                 return 0; /* already off */
6103                 }
6104         }
6105
6106         if (on)
6107                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
6108         else
6109                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
6110         vsi->info.valid_sections =
6111                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
6112         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
6113         vsi->info.port_vlan_flags |= vlan_flags;
6114         ctxt.seid = vsi->seid;
6115         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
6116         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6117         if (ret)
6118                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
6119                             on ? "enable" : "disable");
6120
6121         return ret;
6122 }
6123
6124 static int
6125 i40e_dev_init_vlan(struct rte_eth_dev *dev)
6126 {
6127         struct rte_eth_dev_data *data = dev->data;
6128         int ret;
6129         int mask = 0;
6130
6131         /* Apply vlan offload setting */
6132         mask = ETH_VLAN_STRIP_MASK |
6133                ETH_QINQ_STRIP_MASK |
6134                ETH_VLAN_FILTER_MASK |
6135                ETH_VLAN_EXTEND_MASK;
6136         ret = i40e_vlan_offload_set(dev, mask);
6137         if (ret) {
6138                 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
6139                 return ret;
6140         }
6141
6142         /* Apply pvid setting */
6143         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
6144                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
6145         if (ret)
6146                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
6147
6148         return ret;
6149 }
6150
6151 static int
6152 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
6153 {
6154         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6155
6156         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
6157 }
6158
6159 static int
6160 i40e_update_flow_control(struct i40e_hw *hw)
6161 {
6162 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
6163         struct i40e_link_status link_status;
6164         uint32_t rxfc = 0, txfc = 0, reg;
6165         uint8_t an_info;
6166         int ret;
6167
6168         memset(&link_status, 0, sizeof(link_status));
6169         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
6170         if (ret != I40E_SUCCESS) {
6171                 PMD_DRV_LOG(ERR, "Failed to get link status information");
6172                 goto write_reg; /* Disable flow control */
6173         }
6174
6175         an_info = hw->phy.link_info.an_info;
6176         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
6177                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
6178                 ret = I40E_ERR_NOT_READY;
6179                 goto write_reg; /* Disable flow control */
6180         }
6181         /**
6182          * If link auto negotiation is enabled, flow control needs to
6183          * be configured according to it
6184          */
6185         switch (an_info & I40E_LINK_PAUSE_RXTX) {
6186         case I40E_LINK_PAUSE_RXTX:
6187                 rxfc = 1;
6188                 txfc = 1;
6189                 hw->fc.current_mode = I40E_FC_FULL;
6190                 break;
6191         case I40E_AQ_LINK_PAUSE_RX:
6192                 rxfc = 1;
6193                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
6194                 break;
6195         case I40E_AQ_LINK_PAUSE_TX:
6196                 txfc = 1;
6197                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
6198                 break;
6199         default:
6200                 hw->fc.current_mode = I40E_FC_NONE;
6201                 break;
6202         }
6203
6204 write_reg:
6205         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
6206                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
6207         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
6208         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
6209         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
6210         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
6211
6212         return ret;
6213 }
6214
6215 /* PF setup */
6216 static int
6217 i40e_pf_setup(struct i40e_pf *pf)
6218 {
6219         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6220         struct i40e_filter_control_settings settings;
6221         struct i40e_vsi *vsi;
6222         int ret;
6223
6224         /* Clear all stats counters */
6225         pf->offset_loaded = FALSE;
6226         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
6227         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
6228         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
6229         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
6230
6231         ret = i40e_pf_get_switch_config(pf);
6232         if (ret != I40E_SUCCESS) {
6233                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
6234                 return ret;
6235         }
6236
6237         ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
6238         if (ret)
6239                 PMD_INIT_LOG(WARNING,
6240                         "failed to allocate switch domain for device %d", ret);
6241
6242         if (pf->flags & I40E_FLAG_FDIR) {
6243                 /* make queue allocated first, let FDIR use queue pair 0*/
6244                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
6245                 if (ret != I40E_FDIR_QUEUE_ID) {
6246                         PMD_DRV_LOG(ERR,
6247                                 "queue allocation fails for FDIR: ret =%d",
6248                                 ret);
6249                         pf->flags &= ~I40E_FLAG_FDIR;
6250                 }
6251         }
6252         /*  main VSI setup */
6253         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6254         if (!vsi) {
6255                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6256                 return I40E_ERR_NOT_READY;
6257         }
6258         pf->main_vsi = vsi;
6259
6260         /* Configure filter control */
6261         memset(&settings, 0, sizeof(settings));
6262         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
6263                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6264         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
6265                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6266         else {
6267                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6268                         hw->func_caps.rss_table_size);
6269                 return I40E_ERR_PARAM;
6270         }
6271         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6272                 hw->func_caps.rss_table_size);
6273         pf->hash_lut_size = hw->func_caps.rss_table_size;
6274
6275         /* Enable ethtype and macvlan filters */
6276         settings.enable_ethtype = TRUE;
6277         settings.enable_macvlan = TRUE;
6278         ret = i40e_set_filter_control(hw, &settings);
6279         if (ret)
6280                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6281                                                                 ret);
6282
6283         /* Update flow control according to the auto negotiation */
6284         i40e_update_flow_control(hw);
6285
6286         return I40E_SUCCESS;
6287 }
6288
6289 int
6290 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6291 {
6292         uint32_t reg;
6293         uint16_t j;
6294
6295         /**
6296          * Set or clear TX Queue Disable flags,
6297          * which is required by hardware.
6298          */
6299         i40e_pre_tx_queue_cfg(hw, q_idx, on);
6300         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6301
6302         /* Wait until the request is finished */
6303         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6304                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6305                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6306                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6307                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6308                                                         & 0x1))) {
6309                         break;
6310                 }
6311         }
6312         if (on) {
6313                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6314                         return I40E_SUCCESS; /* already on, skip next steps */
6315
6316                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6317                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6318         } else {
6319                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6320                         return I40E_SUCCESS; /* already off, skip next steps */
6321                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6322         }
6323         /* Write the register */
6324         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6325         /* Check the result */
6326         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6327                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6328                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6329                 if (on) {
6330                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6331                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6332                                 break;
6333                 } else {
6334                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6335                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6336                                 break;
6337                 }
6338         }
6339         /* Check if it is timeout */
6340         if (j >= I40E_CHK_Q_ENA_COUNT) {
6341                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6342                             (on ? "enable" : "disable"), q_idx);
6343                 return I40E_ERR_TIMEOUT;
6344         }
6345
6346         return I40E_SUCCESS;
6347 }
6348
6349 int
6350 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6351 {
6352         uint32_t reg;
6353         uint16_t j;
6354
6355         /* Wait until the request is finished */
6356         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6357                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6358                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6359                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6360                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6361                         break;
6362         }
6363
6364         if (on) {
6365                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6366                         return I40E_SUCCESS; /* Already on, skip next steps */
6367                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6368         } else {
6369                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6370                         return I40E_SUCCESS; /* Already off, skip next steps */
6371                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6372         }
6373
6374         /* Write the register */
6375         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6376         /* Check the result */
6377         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6378                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6379                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6380                 if (on) {
6381                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6382                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6383                                 break;
6384                 } else {
6385                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6386                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6387                                 break;
6388                 }
6389         }
6390
6391         /* Check if it is timeout */
6392         if (j >= I40E_CHK_Q_ENA_COUNT) {
6393                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6394                             (on ? "enable" : "disable"), q_idx);
6395                 return I40E_ERR_TIMEOUT;
6396         }
6397
6398         return I40E_SUCCESS;
6399 }
6400
6401 /* Initialize VSI for TX */
6402 static int
6403 i40e_dev_tx_init(struct i40e_pf *pf)
6404 {
6405         struct rte_eth_dev_data *data = pf->dev_data;
6406         uint16_t i;
6407         uint32_t ret = I40E_SUCCESS;
6408         struct i40e_tx_queue *txq;
6409
6410         for (i = 0; i < data->nb_tx_queues; i++) {
6411                 txq = data->tx_queues[i];
6412                 if (!txq || !txq->q_set)
6413                         continue;
6414                 ret = i40e_tx_queue_init(txq);
6415                 if (ret != I40E_SUCCESS)
6416                         break;
6417         }
6418         if (ret == I40E_SUCCESS)
6419                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6420                                      ->eth_dev);
6421
6422         return ret;
6423 }
6424
6425 /* Initialize VSI for RX */
6426 static int
6427 i40e_dev_rx_init(struct i40e_pf *pf)
6428 {
6429         struct rte_eth_dev_data *data = pf->dev_data;
6430         int ret = I40E_SUCCESS;
6431         uint16_t i;
6432         struct i40e_rx_queue *rxq;
6433
6434         i40e_pf_config_rss(pf);
6435         for (i = 0; i < data->nb_rx_queues; i++) {
6436                 rxq = data->rx_queues[i];
6437                 if (!rxq || !rxq->q_set)
6438                         continue;
6439
6440                 ret = i40e_rx_queue_init(rxq);
6441                 if (ret != I40E_SUCCESS) {
6442                         PMD_DRV_LOG(ERR,
6443                                 "Failed to do RX queue initialization");
6444                         break;
6445                 }
6446         }
6447         if (ret == I40E_SUCCESS)
6448                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6449                                      ->eth_dev);
6450
6451         return ret;
6452 }
6453
6454 static int
6455 i40e_dev_rxtx_init(struct i40e_pf *pf)
6456 {
6457         int err;
6458
6459         err = i40e_dev_tx_init(pf);
6460         if (err) {
6461                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6462                 return err;
6463         }
6464         err = i40e_dev_rx_init(pf);
6465         if (err) {
6466                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6467                 return err;
6468         }
6469
6470         return err;
6471 }
6472
6473 static int
6474 i40e_vmdq_setup(struct rte_eth_dev *dev)
6475 {
6476         struct rte_eth_conf *conf = &dev->data->dev_conf;
6477         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6478         int i, err, conf_vsis, j, loop;
6479         struct i40e_vsi *vsi;
6480         struct i40e_vmdq_info *vmdq_info;
6481         struct rte_eth_vmdq_rx_conf *vmdq_conf;
6482         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6483
6484         /*
6485          * Disable interrupt to avoid message from VF. Furthermore, it will
6486          * avoid race condition in VSI creation/destroy.
6487          */
6488         i40e_pf_disable_irq0(hw);
6489
6490         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6491                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6492                 return -ENOTSUP;
6493         }
6494
6495         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6496         if (conf_vsis > pf->max_nb_vmdq_vsi) {
6497                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6498                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6499                         pf->max_nb_vmdq_vsi);
6500                 return -ENOTSUP;
6501         }
6502
6503         if (pf->vmdq != NULL) {
6504                 PMD_INIT_LOG(INFO, "VMDQ already configured");
6505                 return 0;
6506         }
6507
6508         pf->vmdq = rte_zmalloc("vmdq_info_struct",
6509                                 sizeof(*vmdq_info) * conf_vsis, 0);
6510
6511         if (pf->vmdq == NULL) {
6512                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6513                 return -ENOMEM;
6514         }
6515
6516         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6517
6518         /* Create VMDQ VSI */
6519         for (i = 0; i < conf_vsis; i++) {
6520                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6521                                 vmdq_conf->enable_loop_back);
6522                 if (vsi == NULL) {
6523                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6524                         err = -1;
6525                         goto err_vsi_setup;
6526                 }
6527                 vmdq_info = &pf->vmdq[i];
6528                 vmdq_info->pf = pf;
6529                 vmdq_info->vsi = vsi;
6530         }
6531         pf->nb_cfg_vmdq_vsi = conf_vsis;
6532
6533         /* Configure Vlan */
6534         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6535         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6536                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6537                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6538                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6539                                         vmdq_conf->pool_map[i].vlan_id, j);
6540
6541                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6542                                                 vmdq_conf->pool_map[i].vlan_id);
6543                                 if (err) {
6544                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
6545                                         err = -1;
6546                                         goto err_vsi_setup;
6547                                 }
6548                         }
6549                 }
6550         }
6551
6552         i40e_pf_enable_irq0(hw);
6553
6554         return 0;
6555
6556 err_vsi_setup:
6557         for (i = 0; i < conf_vsis; i++)
6558                 if (pf->vmdq[i].vsi == NULL)
6559                         break;
6560                 else
6561                         i40e_vsi_release(pf->vmdq[i].vsi);
6562
6563         rte_free(pf->vmdq);
6564         pf->vmdq = NULL;
6565         i40e_pf_enable_irq0(hw);
6566         return err;
6567 }
6568
6569 static void
6570 i40e_stat_update_32(struct i40e_hw *hw,
6571                    uint32_t reg,
6572                    bool offset_loaded,
6573                    uint64_t *offset,
6574                    uint64_t *stat)
6575 {
6576         uint64_t new_data;
6577
6578         new_data = (uint64_t)I40E_READ_REG(hw, reg);
6579         if (!offset_loaded)
6580                 *offset = new_data;
6581
6582         if (new_data >= *offset)
6583                 *stat = (uint64_t)(new_data - *offset);
6584         else
6585                 *stat = (uint64_t)((new_data +
6586                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6587 }
6588
6589 static void
6590 i40e_stat_update_48(struct i40e_hw *hw,
6591                    uint32_t hireg,
6592                    uint32_t loreg,
6593                    bool offset_loaded,
6594                    uint64_t *offset,
6595                    uint64_t *stat)
6596 {
6597         uint64_t new_data;
6598
6599         if (hw->device_id == I40E_DEV_ID_QEMU) {
6600                 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6601                 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6602                                 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6603         } else {
6604                 new_data = I40E_READ_REG64(hw, loreg);
6605         }
6606
6607         if (!offset_loaded)
6608                 *offset = new_data;
6609
6610         if (new_data >= *offset)
6611                 *stat = new_data - *offset;
6612         else
6613                 *stat = (uint64_t)((new_data +
6614                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6615
6616         *stat &= I40E_48_BIT_MASK;
6617 }
6618
6619 /* Disable IRQ0 */
6620 void
6621 i40e_pf_disable_irq0(struct i40e_hw *hw)
6622 {
6623         /* Disable all interrupt types */
6624         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6625                        I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6626         I40E_WRITE_FLUSH(hw);
6627 }
6628
6629 /* Enable IRQ0 */
6630 void
6631 i40e_pf_enable_irq0(struct i40e_hw *hw)
6632 {
6633         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6634                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6635                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6636                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6637         I40E_WRITE_FLUSH(hw);
6638 }
6639
6640 static void
6641 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6642 {
6643         /* read pending request and disable first */
6644         i40e_pf_disable_irq0(hw);
6645         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6646         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6647                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6648
6649         if (no_queue)
6650                 /* Link no queues with irq0 */
6651                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6652                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6653 }
6654
6655 static void
6656 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6657 {
6658         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6659         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6660         int i;
6661         uint16_t abs_vf_id;
6662         uint32_t index, offset, val;
6663
6664         if (!pf->vfs)
6665                 return;
6666         /**
6667          * Try to find which VF trigger a reset, use absolute VF id to access
6668          * since the reg is global register.
6669          */
6670         for (i = 0; i < pf->vf_num; i++) {
6671                 abs_vf_id = hw->func_caps.vf_base_id + i;
6672                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6673                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6674                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6675                 /* VFR event occurred */
6676                 if (val & (0x1 << offset)) {
6677                         int ret;
6678
6679                         /* Clear the event first */
6680                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6681                                                         (0x1 << offset));
6682                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6683                         /**
6684                          * Only notify a VF reset event occurred,
6685                          * don't trigger another SW reset
6686                          */
6687                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6688                         if (ret != I40E_SUCCESS)
6689                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6690                 }
6691         }
6692 }
6693
6694 static void
6695 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6696 {
6697         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6698         int i;
6699
6700         for (i = 0; i < pf->vf_num; i++)
6701                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6702 }
6703
6704 static void
6705 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6706 {
6707         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6708         struct i40e_arq_event_info info;
6709         uint16_t pending, opcode;
6710         int ret;
6711
6712         info.buf_len = I40E_AQ_BUF_SZ;
6713         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6714         if (!info.msg_buf) {
6715                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6716                 return;
6717         }
6718
6719         pending = 1;
6720         while (pending) {
6721                 ret = i40e_clean_arq_element(hw, &info, &pending);
6722
6723                 if (ret != I40E_SUCCESS) {
6724                         PMD_DRV_LOG(INFO,
6725                                 "Failed to read msg from AdminQ, aq_err: %u",
6726                                 hw->aq.asq_last_status);
6727                         break;
6728                 }
6729                 opcode = rte_le_to_cpu_16(info.desc.opcode);
6730
6731                 switch (opcode) {
6732                 case i40e_aqc_opc_send_msg_to_pf:
6733                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6734                         i40e_pf_host_handle_vf_msg(dev,
6735                                         rte_le_to_cpu_16(info.desc.retval),
6736                                         rte_le_to_cpu_32(info.desc.cookie_high),
6737                                         rte_le_to_cpu_32(info.desc.cookie_low),
6738                                         info.msg_buf,
6739                                         info.msg_len);
6740                         break;
6741                 case i40e_aqc_opc_get_link_status:
6742                         ret = i40e_dev_link_update(dev, 0);
6743                         if (!ret)
6744                                 rte_eth_dev_callback_process(dev,
6745                                         RTE_ETH_EVENT_INTR_LSC, NULL);
6746                         break;
6747                 default:
6748                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6749                                     opcode);
6750                         break;
6751                 }
6752         }
6753         rte_free(info.msg_buf);
6754 }
6755
6756 static void
6757 i40e_handle_mdd_event(struct rte_eth_dev *dev)
6758 {
6759 #define I40E_MDD_CLEAR32 0xFFFFFFFF
6760 #define I40E_MDD_CLEAR16 0xFFFF
6761         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6762         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6763         bool mdd_detected = false;
6764         struct i40e_pf_vf *vf;
6765         uint32_t reg;
6766         int i;
6767
6768         /* find what triggered the MDD event */
6769         reg = I40E_READ_REG(hw, I40E_GL_MDET_TX);
6770         if (reg & I40E_GL_MDET_TX_VALID_MASK) {
6771                 uint8_t pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6772                                 I40E_GL_MDET_TX_PF_NUM_SHIFT;
6773                 uint16_t vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
6774                                 I40E_GL_MDET_TX_VF_NUM_SHIFT;
6775                 uint8_t event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
6776                                 I40E_GL_MDET_TX_EVENT_SHIFT;
6777                 uint16_t queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6778                                 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6779                                         hw->func_caps.base_queue;
6780                 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on TX "
6781                         "queue %d PF number 0x%02x VF number 0x%02x device %s\n",
6782                                 event, queue, pf_num, vf_num, dev->data->name);
6783                 I40E_WRITE_REG(hw, I40E_GL_MDET_TX, I40E_MDD_CLEAR32);
6784                 mdd_detected = true;
6785         }
6786         reg = I40E_READ_REG(hw, I40E_GL_MDET_RX);
6787         if (reg & I40E_GL_MDET_RX_VALID_MASK) {
6788                 uint8_t func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6789                                 I40E_GL_MDET_RX_FUNCTION_SHIFT;
6790                 uint8_t event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
6791                                 I40E_GL_MDET_RX_EVENT_SHIFT;
6792                 uint16_t queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6793                                 I40E_GL_MDET_RX_QUEUE_SHIFT) -
6794                                         hw->func_caps.base_queue;
6795
6796                 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on RX "
6797                                 "queue %d of function 0x%02x device %s\n",
6798                                         event, queue, func, dev->data->name);
6799                 I40E_WRITE_REG(hw, I40E_GL_MDET_RX, I40E_MDD_CLEAR32);
6800                 mdd_detected = true;
6801         }
6802
6803         if (mdd_detected) {
6804                 reg = I40E_READ_REG(hw, I40E_PF_MDET_TX);
6805                 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
6806                         I40E_WRITE_REG(hw, I40E_PF_MDET_TX, I40E_MDD_CLEAR16);
6807                         PMD_DRV_LOG(WARNING, "TX driver issue detected on PF\n");
6808                 }
6809                 reg = I40E_READ_REG(hw, I40E_PF_MDET_RX);
6810                 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
6811                         I40E_WRITE_REG(hw, I40E_PF_MDET_RX,
6812                                         I40E_MDD_CLEAR16);
6813                         PMD_DRV_LOG(WARNING, "RX driver issue detected on PF\n");
6814                 }
6815         }
6816
6817         /* see if one of the VFs needs its hand slapped */
6818         for (i = 0; i < pf->vf_num && mdd_detected; i++) {
6819                 vf = &pf->vfs[i];
6820                 reg = I40E_READ_REG(hw, I40E_VP_MDET_TX(i));
6821                 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
6822                         I40E_WRITE_REG(hw, I40E_VP_MDET_TX(i),
6823                                         I40E_MDD_CLEAR16);
6824                         vf->num_mdd_events++;
6825                         PMD_DRV_LOG(WARNING, "TX driver issue detected on VF %d %-"
6826                                         PRIu64 "times\n",
6827                                         i, vf->num_mdd_events);
6828                 }
6829
6830                 reg = I40E_READ_REG(hw, I40E_VP_MDET_RX(i));
6831                 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
6832                         I40E_WRITE_REG(hw, I40E_VP_MDET_RX(i),
6833                                         I40E_MDD_CLEAR16);
6834                         vf->num_mdd_events++;
6835                         PMD_DRV_LOG(WARNING, "RX driver issue detected on VF %d %-"
6836                                         PRIu64 "times\n",
6837                                         i, vf->num_mdd_events);
6838                 }
6839         }
6840 }
6841
6842 /**
6843  * Interrupt handler triggered by NIC  for handling
6844  * specific interrupt.
6845  *
6846  * @param handle
6847  *  Pointer to interrupt handle.
6848  * @param param
6849  *  The address of parameter (struct rte_eth_dev *) regsitered before.
6850  *
6851  * @return
6852  *  void
6853  */
6854 static void
6855 i40e_dev_interrupt_handler(void *param)
6856 {
6857         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6858         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6859         uint32_t icr0;
6860
6861         /* Disable interrupt */
6862         i40e_pf_disable_irq0(hw);
6863
6864         /* read out interrupt causes */
6865         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6866
6867         /* No interrupt event indicated */
6868         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6869                 PMD_DRV_LOG(INFO, "No interrupt event");
6870                 goto done;
6871         }
6872         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6873                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6874         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
6875                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6876                 i40e_handle_mdd_event(dev);
6877         }
6878         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6879                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6880         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6881                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6882         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6883                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6884         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6885                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6886         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6887                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6888
6889         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6890                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6891                 i40e_dev_handle_vfr_event(dev);
6892         }
6893         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6894                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6895                 i40e_dev_handle_aq_msg(dev);
6896         }
6897
6898 done:
6899         /* Enable interrupt */
6900         i40e_pf_enable_irq0(hw);
6901 }
6902
6903 static void
6904 i40e_dev_alarm_handler(void *param)
6905 {
6906         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6907         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6908         uint32_t icr0;
6909
6910         /* Disable interrupt */
6911         i40e_pf_disable_irq0(hw);
6912
6913         /* read out interrupt causes */
6914         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6915
6916         /* No interrupt event indicated */
6917         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
6918                 goto done;
6919         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6920                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6921         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
6922                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6923                 i40e_handle_mdd_event(dev);
6924         }
6925         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6926                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6927         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6928                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6929         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6930                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6931         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6932                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6933         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6934                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6935
6936         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6937                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6938                 i40e_dev_handle_vfr_event(dev);
6939         }
6940         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6941                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6942                 i40e_dev_handle_aq_msg(dev);
6943         }
6944
6945 done:
6946         /* Enable interrupt */
6947         i40e_pf_enable_irq0(hw);
6948         rte_eal_alarm_set(I40E_ALARM_INTERVAL,
6949                           i40e_dev_alarm_handler, dev);
6950 }
6951
6952 int
6953 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6954                          struct i40e_macvlan_filter *filter,
6955                          int total)
6956 {
6957         int ele_num, ele_buff_size;
6958         int num, actual_num, i;
6959         uint16_t flags;
6960         int ret = I40E_SUCCESS;
6961         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6962         struct i40e_aqc_add_macvlan_element_data *req_list;
6963
6964         if (filter == NULL  || total == 0)
6965                 return I40E_ERR_PARAM;
6966         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6967         ele_buff_size = hw->aq.asq_buf_size;
6968
6969         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6970         if (req_list == NULL) {
6971                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6972                 return I40E_ERR_NO_MEMORY;
6973         }
6974
6975         num = 0;
6976         do {
6977                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6978                 memset(req_list, 0, ele_buff_size);
6979
6980                 for (i = 0; i < actual_num; i++) {
6981                         rte_memcpy(req_list[i].mac_addr,
6982                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6983                         req_list[i].vlan_tag =
6984                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6985
6986                         switch (filter[num + i].filter_type) {
6987                         case I40E_MAC_PERFECT_MATCH:
6988                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6989                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6990                                 break;
6991                         case I40E_MACVLAN_PERFECT_MATCH:
6992                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6993                                 break;
6994                         case I40E_MAC_HASH_MATCH:
6995                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6996                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6997                                 break;
6998                         case I40E_MACVLAN_HASH_MATCH:
6999                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
7000                                 break;
7001                         default:
7002                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
7003                                 ret = I40E_ERR_PARAM;
7004                                 goto DONE;
7005                         }
7006
7007                         req_list[i].queue_number = 0;
7008
7009                         req_list[i].flags = rte_cpu_to_le_16(flags);
7010                 }
7011
7012                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
7013                                                 actual_num, NULL);
7014                 if (ret != I40E_SUCCESS) {
7015                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
7016                         goto DONE;
7017                 }
7018                 num += actual_num;
7019         } while (num < total);
7020
7021 DONE:
7022         rte_free(req_list);
7023         return ret;
7024 }
7025
7026 int
7027 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
7028                             struct i40e_macvlan_filter *filter,
7029                             int total)
7030 {
7031         int ele_num, ele_buff_size;
7032         int num, actual_num, i;
7033         uint16_t flags;
7034         int ret = I40E_SUCCESS;
7035         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7036         struct i40e_aqc_remove_macvlan_element_data *req_list;
7037
7038         if (filter == NULL  || total == 0)
7039                 return I40E_ERR_PARAM;
7040
7041         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
7042         ele_buff_size = hw->aq.asq_buf_size;
7043
7044         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
7045         if (req_list == NULL) {
7046                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
7047                 return I40E_ERR_NO_MEMORY;
7048         }
7049
7050         num = 0;
7051         do {
7052                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
7053                 memset(req_list, 0, ele_buff_size);
7054
7055                 for (i = 0; i < actual_num; i++) {
7056                         rte_memcpy(req_list[i].mac_addr,
7057                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
7058                         req_list[i].vlan_tag =
7059                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
7060
7061                         switch (filter[num + i].filter_type) {
7062                         case I40E_MAC_PERFECT_MATCH:
7063                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
7064                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7065                                 break;
7066                         case I40E_MACVLAN_PERFECT_MATCH:
7067                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
7068                                 break;
7069                         case I40E_MAC_HASH_MATCH:
7070                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
7071                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7072                                 break;
7073                         case I40E_MACVLAN_HASH_MATCH:
7074                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
7075                                 break;
7076                         default:
7077                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
7078                                 ret = I40E_ERR_PARAM;
7079                                 goto DONE;
7080                         }
7081                         req_list[i].flags = rte_cpu_to_le_16(flags);
7082                 }
7083
7084                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
7085                                                 actual_num, NULL);
7086                 if (ret != I40E_SUCCESS) {
7087                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
7088                         goto DONE;
7089                 }
7090                 num += actual_num;
7091         } while (num < total);
7092
7093 DONE:
7094         rte_free(req_list);
7095         return ret;
7096 }
7097
7098 /* Find out specific MAC filter */
7099 static struct i40e_mac_filter *
7100 i40e_find_mac_filter(struct i40e_vsi *vsi,
7101                          struct rte_ether_addr *macaddr)
7102 {
7103         struct i40e_mac_filter *f;
7104
7105         TAILQ_FOREACH(f, &vsi->mac_list, next) {
7106                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
7107                         return f;
7108         }
7109
7110         return NULL;
7111 }
7112
7113 static bool
7114 i40e_find_vlan_filter(struct i40e_vsi *vsi,
7115                          uint16_t vlan_id)
7116 {
7117         uint32_t vid_idx, vid_bit;
7118
7119         if (vlan_id > ETH_VLAN_ID_MAX)
7120                 return 0;
7121
7122         vid_idx = I40E_VFTA_IDX(vlan_id);
7123         vid_bit = I40E_VFTA_BIT(vlan_id);
7124
7125         if (vsi->vfta[vid_idx] & vid_bit)
7126                 return 1;
7127         else
7128                 return 0;
7129 }
7130
7131 static void
7132 i40e_store_vlan_filter(struct i40e_vsi *vsi,
7133                        uint16_t vlan_id, bool on)
7134 {
7135         uint32_t vid_idx, vid_bit;
7136
7137         vid_idx = I40E_VFTA_IDX(vlan_id);
7138         vid_bit = I40E_VFTA_BIT(vlan_id);
7139
7140         if (on)
7141                 vsi->vfta[vid_idx] |= vid_bit;
7142         else
7143                 vsi->vfta[vid_idx] &= ~vid_bit;
7144 }
7145
7146 void
7147 i40e_set_vlan_filter(struct i40e_vsi *vsi,
7148                      uint16_t vlan_id, bool on)
7149 {
7150         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7151         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
7152         int ret;
7153
7154         if (vlan_id > ETH_VLAN_ID_MAX)
7155                 return;
7156
7157         i40e_store_vlan_filter(vsi, vlan_id, on);
7158
7159         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
7160                 return;
7161
7162         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
7163
7164         if (on) {
7165                 ret = i40e_aq_add_vlan(hw, vsi->seid,
7166                                        &vlan_data, 1, NULL);
7167                 if (ret != I40E_SUCCESS)
7168                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
7169         } else {
7170                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
7171                                           &vlan_data, 1, NULL);
7172                 if (ret != I40E_SUCCESS)
7173                         PMD_DRV_LOG(ERR,
7174                                     "Failed to remove vlan filter");
7175         }
7176 }
7177
7178 /**
7179  * Find all vlan options for specific mac addr,
7180  * return with actual vlan found.
7181  */
7182 int
7183 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
7184                            struct i40e_macvlan_filter *mv_f,
7185                            int num, struct rte_ether_addr *addr)
7186 {
7187         int i;
7188         uint32_t j, k;
7189
7190         /**
7191          * Not to use i40e_find_vlan_filter to decrease the loop time,
7192          * although the code looks complex.
7193           */
7194         if (num < vsi->vlan_num)
7195                 return I40E_ERR_PARAM;
7196
7197         i = 0;
7198         for (j = 0; j < I40E_VFTA_SIZE; j++) {
7199                 if (vsi->vfta[j]) {
7200                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
7201                                 if (vsi->vfta[j] & (1 << k)) {
7202                                         if (i > num - 1) {
7203                                                 PMD_DRV_LOG(ERR,
7204                                                         "vlan number doesn't match");
7205                                                 return I40E_ERR_PARAM;
7206                                         }
7207                                         rte_memcpy(&mv_f[i].macaddr,
7208                                                         addr, ETH_ADDR_LEN);
7209                                         mv_f[i].vlan_id =
7210                                                 j * I40E_UINT32_BIT_SIZE + k;
7211                                         i++;
7212                                 }
7213                         }
7214                 }
7215         }
7216         return I40E_SUCCESS;
7217 }
7218
7219 static inline int
7220 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
7221                            struct i40e_macvlan_filter *mv_f,
7222                            int num,
7223                            uint16_t vlan)
7224 {
7225         int i = 0;
7226         struct i40e_mac_filter *f;
7227
7228         if (num < vsi->mac_num)
7229                 return I40E_ERR_PARAM;
7230
7231         TAILQ_FOREACH(f, &vsi->mac_list, next) {
7232                 if (i > num - 1) {
7233                         PMD_DRV_LOG(ERR, "buffer number not match");
7234                         return I40E_ERR_PARAM;
7235                 }
7236                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7237                                 ETH_ADDR_LEN);
7238                 mv_f[i].vlan_id = vlan;
7239                 mv_f[i].filter_type = f->mac_info.filter_type;
7240                 i++;
7241         }
7242
7243         return I40E_SUCCESS;
7244 }
7245
7246 static int
7247 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
7248 {
7249         int i, j, num;
7250         struct i40e_mac_filter *f;
7251         struct i40e_macvlan_filter *mv_f;
7252         int ret = I40E_SUCCESS;
7253
7254         if (vsi == NULL || vsi->mac_num == 0)
7255                 return I40E_ERR_PARAM;
7256
7257         /* Case that no vlan is set */
7258         if (vsi->vlan_num == 0)
7259                 num = vsi->mac_num;
7260         else
7261                 num = vsi->mac_num * vsi->vlan_num;
7262
7263         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7264         if (mv_f == NULL) {
7265                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7266                 return I40E_ERR_NO_MEMORY;
7267         }
7268
7269         i = 0;
7270         if (vsi->vlan_num == 0) {
7271                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7272                         rte_memcpy(&mv_f[i].macaddr,
7273                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7274                         mv_f[i].filter_type = f->mac_info.filter_type;
7275                         mv_f[i].vlan_id = 0;
7276                         i++;
7277                 }
7278         } else {
7279                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7280                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7281                                         vsi->vlan_num, &f->mac_info.mac_addr);
7282                         if (ret != I40E_SUCCESS)
7283                                 goto DONE;
7284                         for (j = i; j < i + vsi->vlan_num; j++)
7285                                 mv_f[j].filter_type = f->mac_info.filter_type;
7286                         i += vsi->vlan_num;
7287                 }
7288         }
7289
7290         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7291 DONE:
7292         rte_free(mv_f);
7293
7294         return ret;
7295 }
7296
7297 int
7298 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7299 {
7300         struct i40e_macvlan_filter *mv_f;
7301         int mac_num;
7302         int ret = I40E_SUCCESS;
7303
7304         if (!vsi || vlan > RTE_ETHER_MAX_VLAN_ID)
7305                 return I40E_ERR_PARAM;
7306
7307         /* If it's already set, just return */
7308         if (i40e_find_vlan_filter(vsi,vlan))
7309                 return I40E_SUCCESS;
7310
7311         mac_num = vsi->mac_num;
7312
7313         if (mac_num == 0) {
7314                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7315                 return I40E_ERR_PARAM;
7316         }
7317
7318         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7319
7320         if (mv_f == NULL) {
7321                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7322                 return I40E_ERR_NO_MEMORY;
7323         }
7324
7325         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7326
7327         if (ret != I40E_SUCCESS)
7328                 goto DONE;
7329
7330         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7331
7332         if (ret != I40E_SUCCESS)
7333                 goto DONE;
7334
7335         i40e_set_vlan_filter(vsi, vlan, 1);
7336
7337         vsi->vlan_num++;
7338         ret = I40E_SUCCESS;
7339 DONE:
7340         rte_free(mv_f);
7341         return ret;
7342 }
7343
7344 int
7345 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7346 {
7347         struct i40e_macvlan_filter *mv_f;
7348         int mac_num;
7349         int ret = I40E_SUCCESS;
7350
7351         /**
7352          * Vlan 0 is the generic filter for untagged packets
7353          * and can't be removed.
7354          */
7355         if (!vsi || vlan == 0 || vlan > RTE_ETHER_MAX_VLAN_ID)
7356                 return I40E_ERR_PARAM;
7357
7358         /* If can't find it, just return */
7359         if (!i40e_find_vlan_filter(vsi, vlan))
7360                 return I40E_ERR_PARAM;
7361
7362         mac_num = vsi->mac_num;
7363
7364         if (mac_num == 0) {
7365                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7366                 return I40E_ERR_PARAM;
7367         }
7368
7369         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7370
7371         if (mv_f == NULL) {
7372                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7373                 return I40E_ERR_NO_MEMORY;
7374         }
7375
7376         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7377
7378         if (ret != I40E_SUCCESS)
7379                 goto DONE;
7380
7381         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7382
7383         if (ret != I40E_SUCCESS)
7384                 goto DONE;
7385
7386         /* This is last vlan to remove, replace all mac filter with vlan 0 */
7387         if (vsi->vlan_num == 1) {
7388                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7389                 if (ret != I40E_SUCCESS)
7390                         goto DONE;
7391
7392                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7393                 if (ret != I40E_SUCCESS)
7394                         goto DONE;
7395         }
7396
7397         i40e_set_vlan_filter(vsi, vlan, 0);
7398
7399         vsi->vlan_num--;
7400         ret = I40E_SUCCESS;
7401 DONE:
7402         rte_free(mv_f);
7403         return ret;
7404 }
7405
7406 int
7407 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7408 {
7409         struct i40e_mac_filter *f;
7410         struct i40e_macvlan_filter *mv_f;
7411         int i, vlan_num = 0;
7412         int ret = I40E_SUCCESS;
7413
7414         /* If it's add and we've config it, return */
7415         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7416         if (f != NULL)
7417                 return I40E_SUCCESS;
7418         if (mac_filter->filter_type == I40E_MACVLAN_PERFECT_MATCH ||
7419                 mac_filter->filter_type == I40E_MACVLAN_HASH_MATCH) {
7420
7421                 /**
7422                  * If vlan_num is 0, that's the first time to add mac,
7423                  * set mask for vlan_id 0.
7424                  */
7425                 if (vsi->vlan_num == 0) {
7426                         i40e_set_vlan_filter(vsi, 0, 1);
7427                         vsi->vlan_num = 1;
7428                 }
7429                 vlan_num = vsi->vlan_num;
7430         } else if (mac_filter->filter_type == I40E_MAC_PERFECT_MATCH ||
7431                         mac_filter->filter_type == I40E_MAC_HASH_MATCH)
7432                 vlan_num = 1;
7433
7434         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7435         if (mv_f == NULL) {
7436                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7437                 return I40E_ERR_NO_MEMORY;
7438         }
7439
7440         for (i = 0; i < vlan_num; i++) {
7441                 mv_f[i].filter_type = mac_filter->filter_type;
7442                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7443                                 ETH_ADDR_LEN);
7444         }
7445
7446         if (mac_filter->filter_type == I40E_MACVLAN_PERFECT_MATCH ||
7447                 mac_filter->filter_type == I40E_MACVLAN_HASH_MATCH) {
7448                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7449                                         &mac_filter->mac_addr);
7450                 if (ret != I40E_SUCCESS)
7451                         goto DONE;
7452         }
7453
7454         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7455         if (ret != I40E_SUCCESS)
7456                 goto DONE;
7457
7458         /* Add the mac addr into mac list */
7459         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7460         if (f == NULL) {
7461                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7462                 ret = I40E_ERR_NO_MEMORY;
7463                 goto DONE;
7464         }
7465         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7466                         ETH_ADDR_LEN);
7467         f->mac_info.filter_type = mac_filter->filter_type;
7468         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7469         vsi->mac_num++;
7470
7471         ret = I40E_SUCCESS;
7472 DONE:
7473         rte_free(mv_f);
7474
7475         return ret;
7476 }
7477
7478 int
7479 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr)
7480 {
7481         struct i40e_mac_filter *f;
7482         struct i40e_macvlan_filter *mv_f;
7483         int i, vlan_num;
7484         enum i40e_mac_filter_type filter_type;
7485         int ret = I40E_SUCCESS;
7486
7487         /* Can't find it, return an error */
7488         f = i40e_find_mac_filter(vsi, addr);
7489         if (f == NULL)
7490                 return I40E_ERR_PARAM;
7491
7492         vlan_num = vsi->vlan_num;
7493         filter_type = f->mac_info.filter_type;
7494         if (filter_type == I40E_MACVLAN_PERFECT_MATCH ||
7495                 filter_type == I40E_MACVLAN_HASH_MATCH) {
7496                 if (vlan_num == 0) {
7497                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7498                         return I40E_ERR_PARAM;
7499                 }
7500         } else if (filter_type == I40E_MAC_PERFECT_MATCH ||
7501                         filter_type == I40E_MAC_HASH_MATCH)
7502                 vlan_num = 1;
7503
7504         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7505         if (mv_f == NULL) {
7506                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7507                 return I40E_ERR_NO_MEMORY;
7508         }
7509
7510         for (i = 0; i < vlan_num; i++) {
7511                 mv_f[i].filter_type = filter_type;
7512                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7513                                 ETH_ADDR_LEN);
7514         }
7515         if (filter_type == I40E_MACVLAN_PERFECT_MATCH ||
7516                         filter_type == I40E_MACVLAN_HASH_MATCH) {
7517                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7518                 if (ret != I40E_SUCCESS)
7519                         goto DONE;
7520         }
7521
7522         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7523         if (ret != I40E_SUCCESS)
7524                 goto DONE;
7525
7526         /* Remove the mac addr into mac list */
7527         TAILQ_REMOVE(&vsi->mac_list, f, next);
7528         rte_free(f);
7529         vsi->mac_num--;
7530
7531         ret = I40E_SUCCESS;
7532 DONE:
7533         rte_free(mv_f);
7534         return ret;
7535 }
7536
7537 /* Configure hash enable flags for RSS */
7538 uint64_t
7539 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7540 {
7541         uint64_t hena = 0;
7542         int i;
7543
7544         if (!flags)
7545                 return hena;
7546
7547         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7548                 if (flags & (1ULL << i))
7549                         hena |= adapter->pctypes_tbl[i];
7550         }
7551
7552         return hena;
7553 }
7554
7555 /* Parse the hash enable flags */
7556 uint64_t
7557 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7558 {
7559         uint64_t rss_hf = 0;
7560
7561         if (!flags)
7562                 return rss_hf;
7563         int i;
7564
7565         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7566                 if (flags & adapter->pctypes_tbl[i])
7567                         rss_hf |= (1ULL << i);
7568         }
7569         return rss_hf;
7570 }
7571
7572 /* Disable RSS */
7573 void
7574 i40e_pf_disable_rss(struct i40e_pf *pf)
7575 {
7576         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7577
7578         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7579         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7580         I40E_WRITE_FLUSH(hw);
7581 }
7582
7583 int
7584 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7585 {
7586         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7587         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7588         uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7589                            I40E_VFQF_HKEY_MAX_INDEX :
7590                            I40E_PFQF_HKEY_MAX_INDEX;
7591
7592         if (!key || key_len == 0) {
7593                 PMD_DRV_LOG(DEBUG, "No key to be configured");
7594                 return 0;
7595         } else if (key_len != (key_idx + 1) *
7596                 sizeof(uint32_t)) {
7597                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7598                 return -EINVAL;
7599         }
7600
7601         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7602                 struct i40e_aqc_get_set_rss_key_data *key_dw =
7603                                 (struct i40e_aqc_get_set_rss_key_data *)key;
7604                 enum i40e_status_code status =
7605                                 i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7606
7607                 if (status) {
7608                         PMD_DRV_LOG(ERR,
7609                                     "Failed to configure RSS key via AQ, error status: %d",
7610                                     status);
7611                         return -EIO;
7612                 }
7613         } else {
7614                 uint32_t *hash_key = (uint32_t *)key;
7615                 uint16_t i;
7616
7617                 if (vsi->type == I40E_VSI_SRIOV) {
7618                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7619                                 I40E_WRITE_REG(
7620                                         hw,
7621                                         I40E_VFQF_HKEY1(i, vsi->user_param),
7622                                         hash_key[i]);
7623
7624                 } else {
7625                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7626                                 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7627                                                hash_key[i]);
7628                 }
7629                 I40E_WRITE_FLUSH(hw);
7630         }
7631
7632         return 0;
7633 }
7634
7635 static int
7636 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7637 {
7638         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7639         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7640         uint32_t reg;
7641         int ret;
7642
7643         if (!key || !key_len)
7644                 return 0;
7645
7646         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7647                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7648                         (struct i40e_aqc_get_set_rss_key_data *)key);
7649                 if (ret) {
7650                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7651                         return ret;
7652                 }
7653         } else {
7654                 uint32_t *key_dw = (uint32_t *)key;
7655                 uint16_t i;
7656
7657                 if (vsi->type == I40E_VSI_SRIOV) {
7658                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7659                                 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7660                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7661                         }
7662                         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7663                                    sizeof(uint32_t);
7664                 } else {
7665                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7666                                 reg = I40E_PFQF_HKEY(i);
7667                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7668                         }
7669                         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7670                                    sizeof(uint32_t);
7671                 }
7672         }
7673         return 0;
7674 }
7675
7676 static int
7677 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7678 {
7679         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7680         uint64_t hena;
7681         int ret;
7682
7683         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7684                                rss_conf->rss_key_len);
7685         if (ret)
7686                 return ret;
7687
7688         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7689         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7690         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7691         I40E_WRITE_FLUSH(hw);
7692
7693         return 0;
7694 }
7695
7696 static int
7697 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7698                          struct rte_eth_rss_conf *rss_conf)
7699 {
7700         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7701         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7702         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7703         uint64_t hena;
7704
7705         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7706         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7707
7708         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7709                 if (rss_hf != 0) /* Enable RSS */
7710                         return -EINVAL;
7711                 return 0; /* Nothing to do */
7712         }
7713         /* RSS enabled */
7714         if (rss_hf == 0) /* Disable RSS */
7715                 return -EINVAL;
7716
7717         return i40e_hw_rss_hash_set(pf, rss_conf);
7718 }
7719
7720 static int
7721 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7722                            struct rte_eth_rss_conf *rss_conf)
7723 {
7724         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7725         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7726         uint64_t hena;
7727         int ret;
7728
7729         if (!rss_conf)
7730                 return -EINVAL;
7731
7732         ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7733                          &rss_conf->rss_key_len);
7734         if (ret)
7735                 return ret;
7736
7737         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7738         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7739         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7740
7741         return 0;
7742 }
7743
7744 static int
7745 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7746 {
7747         switch (filter_type) {
7748         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7749                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7750                 break;
7751         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7752                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7753                 break;
7754         case RTE_TUNNEL_FILTER_IMAC_TENID:
7755                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7756                 break;
7757         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7758                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7759                 break;
7760         case ETH_TUNNEL_FILTER_IMAC:
7761                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7762                 break;
7763         case ETH_TUNNEL_FILTER_OIP:
7764                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7765                 break;
7766         case ETH_TUNNEL_FILTER_IIP:
7767                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7768                 break;
7769         default:
7770                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7771                 return -EINVAL;
7772         }
7773
7774         return 0;
7775 }
7776
7777 /* Convert tunnel filter structure */
7778 static int
7779 i40e_tunnel_filter_convert(
7780         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7781         struct i40e_tunnel_filter *tunnel_filter)
7782 {
7783         rte_ether_addr_copy((struct rte_ether_addr *)
7784                         &cld_filter->element.outer_mac,
7785                 (struct rte_ether_addr *)&tunnel_filter->input.outer_mac);
7786         rte_ether_addr_copy((struct rte_ether_addr *)
7787                         &cld_filter->element.inner_mac,
7788                 (struct rte_ether_addr *)&tunnel_filter->input.inner_mac);
7789         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7790         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7791              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7792             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7793                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7794         else
7795                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7796         tunnel_filter->input.flags = cld_filter->element.flags;
7797         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7798         tunnel_filter->queue = cld_filter->element.queue_number;
7799         rte_memcpy(tunnel_filter->input.general_fields,
7800                    cld_filter->general_fields,
7801                    sizeof(cld_filter->general_fields));
7802
7803         return 0;
7804 }
7805
7806 /* Check if there exists the tunnel filter */
7807 struct i40e_tunnel_filter *
7808 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7809                              const struct i40e_tunnel_filter_input *input)
7810 {
7811         int ret;
7812
7813         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7814         if (ret < 0)
7815                 return NULL;
7816
7817         return tunnel_rule->hash_map[ret];
7818 }
7819
7820 /* Add a tunnel filter into the SW list */
7821 static int
7822 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7823                              struct i40e_tunnel_filter *tunnel_filter)
7824 {
7825         struct i40e_tunnel_rule *rule = &pf->tunnel;
7826         int ret;
7827
7828         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7829         if (ret < 0) {
7830                 PMD_DRV_LOG(ERR,
7831                             "Failed to insert tunnel filter to hash table %d!",
7832                             ret);
7833                 return ret;
7834         }
7835         rule->hash_map[ret] = tunnel_filter;
7836
7837         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7838
7839         return 0;
7840 }
7841
7842 /* Delete a tunnel filter from the SW list */
7843 int
7844 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7845                           struct i40e_tunnel_filter_input *input)
7846 {
7847         struct i40e_tunnel_rule *rule = &pf->tunnel;
7848         struct i40e_tunnel_filter *tunnel_filter;
7849         int ret;
7850
7851         ret = rte_hash_del_key(rule->hash_table, input);
7852         if (ret < 0) {
7853                 PMD_DRV_LOG(ERR,
7854                             "Failed to delete tunnel filter to hash table %d!",
7855                             ret);
7856                 return ret;
7857         }
7858         tunnel_filter = rule->hash_map[ret];
7859         rule->hash_map[ret] = NULL;
7860
7861         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7862         rte_free(tunnel_filter);
7863
7864         return 0;
7865 }
7866
7867 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7868 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7869 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7870 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7871 #define I40E_TR_GRE_KEY_MASK                    0x400
7872 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7873 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7874 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_PORT_TR_WORD0 0x49
7875 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_DIRECTION_WORD0 0x41
7876 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_INGRESS_WORD0 0x80
7877 #define I40E_DIRECTION_INGRESS_KEY              0x8000
7878 #define I40E_TR_L4_TYPE_TCP                     0x2
7879 #define I40E_TR_L4_TYPE_UDP                     0x4
7880 #define I40E_TR_L4_TYPE_SCTP                    0x8
7881
7882 static enum
7883 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7884 {
7885         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7886         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7887         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7888         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7889         enum i40e_status_code status = I40E_SUCCESS;
7890
7891         if (pf->support_multi_driver) {
7892                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7893                 return I40E_NOT_SUPPORTED;
7894         }
7895
7896         memset(&filter_replace, 0,
7897                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7898         memset(&filter_replace_buf, 0,
7899                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7900
7901         /* create L1 filter */
7902         filter_replace.old_filter_type =
7903                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7904         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7905         filter_replace.tr_bit = 0;
7906
7907         /* Prepare the buffer, 3 entries */
7908         filter_replace_buf.data[0] =
7909                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7910         filter_replace_buf.data[0] |=
7911                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7912         filter_replace_buf.data[2] = 0xFF;
7913         filter_replace_buf.data[3] = 0xFF;
7914         filter_replace_buf.data[4] =
7915                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7916         filter_replace_buf.data[4] |=
7917                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7918         filter_replace_buf.data[7] = 0xF0;
7919         filter_replace_buf.data[8]
7920                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7921         filter_replace_buf.data[8] |=
7922                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7923         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7924                 I40E_TR_GENEVE_KEY_MASK |
7925                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7926         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7927                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7928                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7929
7930         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7931                                                &filter_replace_buf);
7932         if (!status && (filter_replace.old_filter_type !=
7933                         filter_replace.new_filter_type))
7934                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7935                             " original: 0x%x, new: 0x%x",
7936                             dev->device->name,
7937                             filter_replace.old_filter_type,
7938                             filter_replace.new_filter_type);
7939
7940         return status;
7941 }
7942
7943 static enum
7944 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7945 {
7946         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7947         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7948         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7949         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7950         enum i40e_status_code status = I40E_SUCCESS;
7951
7952         if (pf->support_multi_driver) {
7953                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7954                 return I40E_NOT_SUPPORTED;
7955         }
7956
7957         /* For MPLSoUDP */
7958         memset(&filter_replace, 0,
7959                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7960         memset(&filter_replace_buf, 0,
7961                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7962         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7963                 I40E_AQC_MIRROR_CLOUD_FILTER;
7964         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7965         filter_replace.new_filter_type =
7966                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7967         /* Prepare the buffer, 2 entries */
7968         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7969         filter_replace_buf.data[0] |=
7970                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7971         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7972         filter_replace_buf.data[4] |=
7973                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7974         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7975                                                &filter_replace_buf);
7976         if (status < 0)
7977                 return status;
7978         if (filter_replace.old_filter_type !=
7979             filter_replace.new_filter_type)
7980                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7981                             " original: 0x%x, new: 0x%x",
7982                             dev->device->name,
7983                             filter_replace.old_filter_type,
7984                             filter_replace.new_filter_type);
7985
7986         /* For MPLSoGRE */
7987         memset(&filter_replace, 0,
7988                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7989         memset(&filter_replace_buf, 0,
7990                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7991
7992         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7993                 I40E_AQC_MIRROR_CLOUD_FILTER;
7994         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7995         filter_replace.new_filter_type =
7996                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7997         /* Prepare the buffer, 2 entries */
7998         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7999         filter_replace_buf.data[0] |=
8000                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8001         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8002         filter_replace_buf.data[4] |=
8003                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8004
8005         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8006                                                &filter_replace_buf);
8007         if (!status && (filter_replace.old_filter_type !=
8008                         filter_replace.new_filter_type))
8009                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8010                             " original: 0x%x, new: 0x%x",
8011                             dev->device->name,
8012                             filter_replace.old_filter_type,
8013                             filter_replace.new_filter_type);
8014
8015         return status;
8016 }
8017
8018 static enum i40e_status_code
8019 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
8020 {
8021         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8022         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8023         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8024         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8025         enum i40e_status_code status = I40E_SUCCESS;
8026
8027         if (pf->support_multi_driver) {
8028                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8029                 return I40E_NOT_SUPPORTED;
8030         }
8031
8032         /* For GTP-C */
8033         memset(&filter_replace, 0,
8034                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8035         memset(&filter_replace_buf, 0,
8036                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8037         /* create L1 filter */
8038         filter_replace.old_filter_type =
8039                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
8040         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
8041         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
8042                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8043         /* Prepare the buffer, 2 entries */
8044         filter_replace_buf.data[0] =
8045                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8046         filter_replace_buf.data[0] |=
8047                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8048         filter_replace_buf.data[2] = 0xFF;
8049         filter_replace_buf.data[3] = 0xFF;
8050         filter_replace_buf.data[4] =
8051                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8052         filter_replace_buf.data[4] |=
8053                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8054         filter_replace_buf.data[6] = 0xFF;
8055         filter_replace_buf.data[7] = 0xFF;
8056         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8057                                                &filter_replace_buf);
8058         if (status < 0)
8059                 return status;
8060         if (filter_replace.old_filter_type !=
8061             filter_replace.new_filter_type)
8062                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8063                             " original: 0x%x, new: 0x%x",
8064                             dev->device->name,
8065                             filter_replace.old_filter_type,
8066                             filter_replace.new_filter_type);
8067
8068         /* for GTP-U */
8069         memset(&filter_replace, 0,
8070                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8071         memset(&filter_replace_buf, 0,
8072                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8073         /* create L1 filter */
8074         filter_replace.old_filter_type =
8075                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8076         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
8077         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
8078                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8079         /* Prepare the buffer, 2 entries */
8080         filter_replace_buf.data[0] =
8081                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8082         filter_replace_buf.data[0] |=
8083                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8084         filter_replace_buf.data[2] = 0xFF;
8085         filter_replace_buf.data[3] = 0xFF;
8086         filter_replace_buf.data[4] =
8087                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8088         filter_replace_buf.data[4] |=
8089                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8090         filter_replace_buf.data[6] = 0xFF;
8091         filter_replace_buf.data[7] = 0xFF;
8092
8093         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8094                                                &filter_replace_buf);
8095         if (!status && (filter_replace.old_filter_type !=
8096                         filter_replace.new_filter_type))
8097                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8098                             " original: 0x%x, new: 0x%x",
8099                             dev->device->name,
8100                             filter_replace.old_filter_type,
8101                             filter_replace.new_filter_type);
8102
8103         return status;
8104 }
8105
8106 static enum
8107 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
8108 {
8109         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8110         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8111         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8112         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8113         enum i40e_status_code status = I40E_SUCCESS;
8114
8115         if (pf->support_multi_driver) {
8116                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8117                 return I40E_NOT_SUPPORTED;
8118         }
8119
8120         /* for GTP-C */
8121         memset(&filter_replace, 0,
8122                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8123         memset(&filter_replace_buf, 0,
8124                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8125         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8126         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
8127         filter_replace.new_filter_type =
8128                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8129         /* Prepare the buffer, 2 entries */
8130         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
8131         filter_replace_buf.data[0] |=
8132                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8133         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8134         filter_replace_buf.data[4] |=
8135                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8136         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8137                                                &filter_replace_buf);
8138         if (status < 0)
8139                 return status;
8140         if (filter_replace.old_filter_type !=
8141             filter_replace.new_filter_type)
8142                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8143                             " original: 0x%x, new: 0x%x",
8144                             dev->device->name,
8145                             filter_replace.old_filter_type,
8146                             filter_replace.new_filter_type);
8147
8148         /* for GTP-U */
8149         memset(&filter_replace, 0,
8150                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8151         memset(&filter_replace_buf, 0,
8152                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8153         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8154         filter_replace.old_filter_type =
8155                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8156         filter_replace.new_filter_type =
8157                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8158         /* Prepare the buffer, 2 entries */
8159         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8160         filter_replace_buf.data[0] |=
8161                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8162         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8163         filter_replace_buf.data[4] |=
8164                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8165
8166         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8167                                                &filter_replace_buf);
8168         if (!status && (filter_replace.old_filter_type !=
8169                         filter_replace.new_filter_type))
8170                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8171                             " original: 0x%x, new: 0x%x",
8172                             dev->device->name,
8173                             filter_replace.old_filter_type,
8174                             filter_replace.new_filter_type);
8175
8176         return status;
8177 }
8178
8179 static enum i40e_status_code
8180 i40e_replace_port_l1_filter(struct i40e_pf *pf,
8181                             enum i40e_l4_port_type l4_port_type)
8182 {
8183         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8184         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8185         enum i40e_status_code status = I40E_SUCCESS;
8186         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8187         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8188
8189         if (pf->support_multi_driver) {
8190                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8191                 return I40E_NOT_SUPPORTED;
8192         }
8193
8194         memset(&filter_replace, 0,
8195                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8196         memset(&filter_replace_buf, 0,
8197                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8198
8199         /* create L1 filter */
8200         if (l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8201                 filter_replace.old_filter_type =
8202                         I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8203                 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
8204                 filter_replace_buf.data[8] =
8205                         I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_SRC_PORT;
8206         } else {
8207                 filter_replace.old_filter_type =
8208                         I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
8209                 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X10;
8210                 filter_replace_buf.data[8] =
8211                         I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_DST_PORT;
8212         }
8213
8214         filter_replace.tr_bit = 0;
8215         /* Prepare the buffer, 3 entries */
8216         filter_replace_buf.data[0] =
8217                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_DIRECTION_WORD0;
8218         filter_replace_buf.data[0] |=
8219                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8220         filter_replace_buf.data[2] = 0x00;
8221         filter_replace_buf.data[3] =
8222                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_INGRESS_WORD0;
8223         filter_replace_buf.data[4] =
8224                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_PORT_TR_WORD0;
8225         filter_replace_buf.data[4] |=
8226                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8227         filter_replace_buf.data[5] = 0x00;
8228         filter_replace_buf.data[6] = I40E_TR_L4_TYPE_UDP |
8229                 I40E_TR_L4_TYPE_TCP |
8230                 I40E_TR_L4_TYPE_SCTP;
8231         filter_replace_buf.data[7] = 0x00;
8232         filter_replace_buf.data[8] |=
8233                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8234         filter_replace_buf.data[9] = 0x00;
8235         filter_replace_buf.data[10] = 0xFF;
8236         filter_replace_buf.data[11] = 0xFF;
8237
8238         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8239                                                &filter_replace_buf);
8240         if (!status && filter_replace.old_filter_type !=
8241             filter_replace.new_filter_type)
8242                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8243                             " original: 0x%x, new: 0x%x",
8244                             dev->device->name,
8245                             filter_replace.old_filter_type,
8246                             filter_replace.new_filter_type);
8247
8248         return status;
8249 }
8250
8251 static enum i40e_status_code
8252 i40e_replace_port_cloud_filter(struct i40e_pf *pf,
8253                                enum i40e_l4_port_type l4_port_type)
8254 {
8255         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8256         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8257         enum i40e_status_code status = I40E_SUCCESS;
8258         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8259         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8260
8261         if (pf->support_multi_driver) {
8262                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8263                 return I40E_NOT_SUPPORTED;
8264         }
8265
8266         memset(&filter_replace, 0,
8267                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8268         memset(&filter_replace_buf, 0,
8269                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8270
8271         if (l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8272                 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
8273                 filter_replace.new_filter_type =
8274                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8275                 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X11;
8276         } else {
8277                 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
8278                 filter_replace.new_filter_type =
8279                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
8280                 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
8281         }
8282
8283         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8284         filter_replace.tr_bit = 0;
8285         /* Prepare the buffer, 2 entries */
8286         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8287         filter_replace_buf.data[0] |=
8288                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8289         filter_replace_buf.data[4] |=
8290                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8291         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8292                                                &filter_replace_buf);
8293
8294         if (!status && filter_replace.old_filter_type !=
8295             filter_replace.new_filter_type)
8296                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8297                             " original: 0x%x, new: 0x%x",
8298                             dev->device->name,
8299                             filter_replace.old_filter_type,
8300                             filter_replace.new_filter_type);
8301
8302         return status;
8303 }
8304
8305 int
8306 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8307                       struct i40e_tunnel_filter_conf *tunnel_filter,
8308                       uint8_t add)
8309 {
8310         uint16_t ip_type;
8311         uint32_t ipv4_addr, ipv4_addr_le;
8312         uint8_t i, tun_type = 0;
8313         /* internal variable to convert ipv6 byte order */
8314         uint32_t convert_ipv6[4];
8315         int val, ret = 0;
8316         struct i40e_pf_vf *vf = NULL;
8317         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8318         struct i40e_vsi *vsi;
8319         struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8320         struct i40e_aqc_cloud_filters_element_bb *pfilter;
8321         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8322         struct i40e_tunnel_filter *tunnel, *node;
8323         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8324         uint32_t teid_le;
8325         bool big_buffer = 0;
8326
8327         cld_filter = rte_zmalloc("tunnel_filter",
8328                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8329                          0);
8330
8331         if (cld_filter == NULL) {
8332                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8333                 return -ENOMEM;
8334         }
8335         pfilter = cld_filter;
8336
8337         rte_ether_addr_copy(&tunnel_filter->outer_mac,
8338                         (struct rte_ether_addr *)&pfilter->element.outer_mac);
8339         rte_ether_addr_copy(&tunnel_filter->inner_mac,
8340                         (struct rte_ether_addr *)&pfilter->element.inner_mac);
8341
8342         pfilter->element.inner_vlan =
8343                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8344         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8345                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8346                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8347                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8348                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8349                                 &ipv4_addr_le,
8350                                 sizeof(pfilter->element.ipaddr.v4.data));
8351         } else {
8352                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8353                 for (i = 0; i < 4; i++) {
8354                         convert_ipv6[i] =
8355                         rte_cpu_to_le_32(rte_be_to_cpu_32(
8356                                          tunnel_filter->ip_addr.ipv6_addr[i]));
8357                 }
8358                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8359                            &convert_ipv6,
8360                            sizeof(pfilter->element.ipaddr.v6.data));
8361         }
8362
8363         /* check tunneled type */
8364         switch (tunnel_filter->tunnel_type) {
8365         case I40E_TUNNEL_TYPE_VXLAN:
8366                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8367                 break;
8368         case I40E_TUNNEL_TYPE_NVGRE:
8369                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8370                 break;
8371         case I40E_TUNNEL_TYPE_IP_IN_GRE:
8372                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8373                 break;
8374         case I40E_TUNNEL_TYPE_MPLSoUDP:
8375                 if (!pf->mpls_replace_flag) {
8376                         i40e_replace_mpls_l1_filter(pf);
8377                         i40e_replace_mpls_cloud_filter(pf);
8378                         pf->mpls_replace_flag = 1;
8379                 }
8380                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8381                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8382                         teid_le >> 4;
8383                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8384                         (teid_le & 0xF) << 12;
8385                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8386                         0x40;
8387                 big_buffer = 1;
8388                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8389                 break;
8390         case I40E_TUNNEL_TYPE_MPLSoGRE:
8391                 if (!pf->mpls_replace_flag) {
8392                         i40e_replace_mpls_l1_filter(pf);
8393                         i40e_replace_mpls_cloud_filter(pf);
8394                         pf->mpls_replace_flag = 1;
8395                 }
8396                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8397                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8398                         teid_le >> 4;
8399                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8400                         (teid_le & 0xF) << 12;
8401                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8402                         0x0;
8403                 big_buffer = 1;
8404                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8405                 break;
8406         case I40E_TUNNEL_TYPE_GTPC:
8407                 if (!pf->gtp_replace_flag) {
8408                         i40e_replace_gtp_l1_filter(pf);
8409                         i40e_replace_gtp_cloud_filter(pf);
8410                         pf->gtp_replace_flag = 1;
8411                 }
8412                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8413                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8414                         (teid_le >> 16) & 0xFFFF;
8415                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8416                         teid_le & 0xFFFF;
8417                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8418                         0x0;
8419                 big_buffer = 1;
8420                 break;
8421         case I40E_TUNNEL_TYPE_GTPU:
8422                 if (!pf->gtp_replace_flag) {
8423                         i40e_replace_gtp_l1_filter(pf);
8424                         i40e_replace_gtp_cloud_filter(pf);
8425                         pf->gtp_replace_flag = 1;
8426                 }
8427                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8428                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8429                         (teid_le >> 16) & 0xFFFF;
8430                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8431                         teid_le & 0xFFFF;
8432                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8433                         0x0;
8434                 big_buffer = 1;
8435                 break;
8436         case I40E_TUNNEL_TYPE_QINQ:
8437                 if (!pf->qinq_replace_flag) {
8438                         ret = i40e_cloud_filter_qinq_create(pf);
8439                         if (ret < 0)
8440                                 PMD_DRV_LOG(DEBUG,
8441                                             "QinQ tunnel filter already created.");
8442                         pf->qinq_replace_flag = 1;
8443                 }
8444                 /*      Add in the General fields the values of
8445                  *      the Outer and Inner VLAN
8446                  *      Big Buffer should be set, see changes in
8447                  *      i40e_aq_add_cloud_filters
8448                  */
8449                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8450                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8451                 big_buffer = 1;
8452                 break;
8453         case I40E_CLOUD_TYPE_UDP:
8454         case I40E_CLOUD_TYPE_TCP:
8455         case I40E_CLOUD_TYPE_SCTP:
8456                 if (tunnel_filter->l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8457                         if (!pf->sport_replace_flag) {
8458                                 i40e_replace_port_l1_filter(pf,
8459                                                 tunnel_filter->l4_port_type);
8460                                 i40e_replace_port_cloud_filter(pf,
8461                                                 tunnel_filter->l4_port_type);
8462                                 pf->sport_replace_flag = 1;
8463                         }
8464                         teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8465                         pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8466                                 I40E_DIRECTION_INGRESS_KEY;
8467
8468                         if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP)
8469                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8470                                         I40E_TR_L4_TYPE_UDP;
8471                         else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP)
8472                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8473                                         I40E_TR_L4_TYPE_TCP;
8474                         else
8475                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8476                                         I40E_TR_L4_TYPE_SCTP;
8477
8478                         pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8479                                 (teid_le >> 16) & 0xFFFF;
8480                         big_buffer = 1;
8481                 } else {
8482                         if (!pf->dport_replace_flag) {
8483                                 i40e_replace_port_l1_filter(pf,
8484                                                 tunnel_filter->l4_port_type);
8485                                 i40e_replace_port_cloud_filter(pf,
8486                                                 tunnel_filter->l4_port_type);
8487                                 pf->dport_replace_flag = 1;
8488                         }
8489                         teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8490                         pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0] =
8491                                 I40E_DIRECTION_INGRESS_KEY;
8492
8493                         if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP)
8494                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8495                                         I40E_TR_L4_TYPE_UDP;
8496                         else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP)
8497                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8498                                         I40E_TR_L4_TYPE_TCP;
8499                         else
8500                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8501                                         I40E_TR_L4_TYPE_SCTP;
8502
8503                         pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2] =
8504                                 (teid_le >> 16) & 0xFFFF;
8505                         big_buffer = 1;
8506                 }
8507
8508                 break;
8509         default:
8510                 /* Other tunnel types is not supported. */
8511                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8512                 rte_free(cld_filter);
8513                 return -EINVAL;
8514         }
8515
8516         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8517                 pfilter->element.flags =
8518                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8519         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8520                 pfilter->element.flags =
8521                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8522         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8523                 pfilter->element.flags =
8524                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8525         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8526                 pfilter->element.flags =
8527                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8528         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8529                 pfilter->element.flags |=
8530                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
8531         else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP ||
8532                  tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP ||
8533                  tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_SCTP) {
8534                 if (tunnel_filter->l4_port_type == I40E_L4_PORT_TYPE_SRC)
8535                         pfilter->element.flags |=
8536                                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8537                 else
8538                         pfilter->element.flags |=
8539                                 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8540         } else {
8541                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8542                                                 &pfilter->element.flags);
8543                 if (val < 0) {
8544                         rte_free(cld_filter);
8545                         return -EINVAL;
8546                 }
8547         }
8548
8549         pfilter->element.flags |= rte_cpu_to_le_16(
8550                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8551                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8552         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8553         pfilter->element.queue_number =
8554                 rte_cpu_to_le_16(tunnel_filter->queue_id);
8555
8556         if (!tunnel_filter->is_to_vf)
8557                 vsi = pf->main_vsi;
8558         else {
8559                 if (tunnel_filter->vf_id >= pf->vf_num) {
8560                         PMD_DRV_LOG(ERR, "Invalid argument.");
8561                         rte_free(cld_filter);
8562                         return -EINVAL;
8563                 }
8564                 vf = &pf->vfs[tunnel_filter->vf_id];
8565                 vsi = vf->vsi;
8566         }
8567
8568         /* Check if there is the filter in SW list */
8569         memset(&check_filter, 0, sizeof(check_filter));
8570         i40e_tunnel_filter_convert(cld_filter, &check_filter);
8571         check_filter.is_to_vf = tunnel_filter->is_to_vf;
8572         check_filter.vf_id = tunnel_filter->vf_id;
8573         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8574         if (add && node) {
8575                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8576                 rte_free(cld_filter);
8577                 return -EINVAL;
8578         }
8579
8580         if (!add && !node) {
8581                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8582                 rte_free(cld_filter);
8583                 return -EINVAL;
8584         }
8585
8586         if (add) {
8587                 if (big_buffer)
8588                         ret = i40e_aq_add_cloud_filters_bb(hw,
8589                                                    vsi->seid, cld_filter, 1);
8590                 else
8591                         ret = i40e_aq_add_cloud_filters(hw,
8592                                         vsi->seid, &cld_filter->element, 1);
8593                 if (ret < 0) {
8594                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8595                         rte_free(cld_filter);
8596                         return -ENOTSUP;
8597                 }
8598                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8599                 if (tunnel == NULL) {
8600                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8601                         rte_free(cld_filter);
8602                         return -ENOMEM;
8603                 }
8604
8605                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8606                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8607                 if (ret < 0)
8608                         rte_free(tunnel);
8609         } else {
8610                 if (big_buffer)
8611                         ret = i40e_aq_rem_cloud_filters_bb(
8612                                 hw, vsi->seid, cld_filter, 1);
8613                 else
8614                         ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8615                                                 &cld_filter->element, 1);
8616                 if (ret < 0) {
8617                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8618                         rte_free(cld_filter);
8619                         return -ENOTSUP;
8620                 }
8621                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8622         }
8623
8624         rte_free(cld_filter);
8625         return ret;
8626 }
8627
8628 static int
8629 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8630 {
8631         uint8_t i;
8632
8633         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8634                 if (pf->vxlan_ports[i] == port)
8635                         return i;
8636         }
8637
8638         return -1;
8639 }
8640
8641 static int
8642 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port, int udp_type)
8643 {
8644         int  idx, ret;
8645         uint8_t filter_idx = 0;
8646         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8647
8648         idx = i40e_get_vxlan_port_idx(pf, port);
8649
8650         /* Check if port already exists */
8651         if (idx >= 0) {
8652                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8653                 return -EINVAL;
8654         }
8655
8656         /* Now check if there is space to add the new port */
8657         idx = i40e_get_vxlan_port_idx(pf, 0);
8658         if (idx < 0) {
8659                 PMD_DRV_LOG(ERR,
8660                         "Maximum number of UDP ports reached, not adding port %d",
8661                         port);
8662                 return -ENOSPC;
8663         }
8664
8665         ret =  i40e_aq_add_udp_tunnel(hw, port, udp_type,
8666                                         &filter_idx, NULL);
8667         if (ret < 0) {
8668                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8669                 return -1;
8670         }
8671
8672         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8673                          port,  filter_idx);
8674
8675         /* New port: add it and mark its index in the bitmap */
8676         pf->vxlan_ports[idx] = port;
8677         pf->vxlan_bitmap |= (1 << idx);
8678
8679         if (!(pf->flags & I40E_FLAG_VXLAN))
8680                 pf->flags |= I40E_FLAG_VXLAN;
8681
8682         return 0;
8683 }
8684
8685 static int
8686 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8687 {
8688         int idx;
8689         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8690
8691         if (!(pf->flags & I40E_FLAG_VXLAN)) {
8692                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8693                 return -EINVAL;
8694         }
8695
8696         idx = i40e_get_vxlan_port_idx(pf, port);
8697
8698         if (idx < 0) {
8699                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8700                 return -EINVAL;
8701         }
8702
8703         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8704                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8705                 return -1;
8706         }
8707
8708         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8709                         port, idx);
8710
8711         pf->vxlan_ports[idx] = 0;
8712         pf->vxlan_bitmap &= ~(1 << idx);
8713
8714         if (!pf->vxlan_bitmap)
8715                 pf->flags &= ~I40E_FLAG_VXLAN;
8716
8717         return 0;
8718 }
8719
8720 /* Add UDP tunneling port */
8721 static int
8722 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8723                              struct rte_eth_udp_tunnel *udp_tunnel)
8724 {
8725         int ret = 0;
8726         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8727
8728         if (udp_tunnel == NULL)
8729                 return -EINVAL;
8730
8731         switch (udp_tunnel->prot_type) {
8732         case RTE_TUNNEL_TYPE_VXLAN:
8733                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8734                                           I40E_AQC_TUNNEL_TYPE_VXLAN);
8735                 break;
8736         case RTE_TUNNEL_TYPE_VXLAN_GPE:
8737                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8738                                           I40E_AQC_TUNNEL_TYPE_VXLAN_GPE);
8739                 break;
8740         case RTE_TUNNEL_TYPE_GENEVE:
8741         case RTE_TUNNEL_TYPE_TEREDO:
8742                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8743                 ret = -1;
8744                 break;
8745
8746         default:
8747                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8748                 ret = -1;
8749                 break;
8750         }
8751
8752         return ret;
8753 }
8754
8755 /* Remove UDP tunneling port */
8756 static int
8757 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8758                              struct rte_eth_udp_tunnel *udp_tunnel)
8759 {
8760         int ret = 0;
8761         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8762
8763         if (udp_tunnel == NULL)
8764                 return -EINVAL;
8765
8766         switch (udp_tunnel->prot_type) {
8767         case RTE_TUNNEL_TYPE_VXLAN:
8768         case RTE_TUNNEL_TYPE_VXLAN_GPE:
8769                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8770                 break;
8771         case RTE_TUNNEL_TYPE_GENEVE:
8772         case RTE_TUNNEL_TYPE_TEREDO:
8773                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8774                 ret = -1;
8775                 break;
8776         default:
8777                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8778                 ret = -1;
8779                 break;
8780         }
8781
8782         return ret;
8783 }
8784
8785 /* Calculate the maximum number of contiguous PF queues that are configured */
8786 int
8787 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8788 {
8789         struct rte_eth_dev_data *data = pf->dev_data;
8790         int i, num;
8791         struct i40e_rx_queue *rxq;
8792
8793         num = 0;
8794         for (i = 0; i < pf->lan_nb_qps; i++) {
8795                 rxq = data->rx_queues[i];
8796                 if (rxq && rxq->q_set)
8797                         num++;
8798                 else
8799                         break;
8800         }
8801
8802         return num;
8803 }
8804
8805 /* Reset the global configure of hash function and input sets */
8806 static void
8807 i40e_pf_global_rss_reset(struct i40e_pf *pf)
8808 {
8809         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8810         uint32_t reg, reg_val;
8811         int i;
8812
8813         /* Reset global RSS function sets */
8814         reg_val = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8815         if (!(reg_val & I40E_GLQF_CTL_HTOEP_MASK)) {
8816                 reg_val |= I40E_GLQF_CTL_HTOEP_MASK;
8817                 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg_val);
8818         }
8819
8820         for (i = 0; i <= I40E_FILTER_PCTYPE_L2_PAYLOAD; i++) {
8821                 uint64_t inset;
8822                 int j, pctype;
8823
8824                 if (hw->mac.type == I40E_MAC_X722)
8825                         pctype = i40e_read_rx_ctl(hw, I40E_GLQF_FD_PCTYPES(i));
8826                 else
8827                         pctype = i;
8828
8829                 /* Reset pctype insets */
8830                 inset = i40e_get_default_input_set(i);
8831                 if (inset) {
8832                         pf->hash_input_set[pctype] = inset;
8833                         inset = i40e_translate_input_set_reg(hw->mac.type,
8834                                                              inset);
8835
8836                         reg = I40E_GLQF_HASH_INSET(0, pctype);
8837                         i40e_check_write_global_reg(hw, reg, (uint32_t)inset);
8838                         reg = I40E_GLQF_HASH_INSET(1, pctype);
8839                         i40e_check_write_global_reg(hw, reg,
8840                                                     (uint32_t)(inset >> 32));
8841
8842                         /* Clear unused mask registers of the pctype */
8843                         for (j = 0; j < I40E_INSET_MASK_NUM_REG; j++) {
8844                                 reg = I40E_GLQF_HASH_MSK(j, pctype);
8845                                 i40e_check_write_global_reg(hw, reg, 0);
8846                         }
8847                 }
8848
8849                 /* Reset pctype symmetric sets */
8850                 reg = I40E_GLQF_HSYM(pctype);
8851                 reg_val = i40e_read_rx_ctl(hw, reg);
8852                 if (reg_val & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8853                         reg_val &= ~I40E_GLQF_HSYM_SYMH_ENA_MASK;
8854                         i40e_write_global_rx_ctl(hw, reg, reg_val);
8855                 }
8856         }
8857         I40E_WRITE_FLUSH(hw);
8858 }
8859
8860 int
8861 i40e_pf_reset_rss_reta(struct i40e_pf *pf)
8862 {
8863         struct i40e_hw *hw = &pf->adapter->hw;
8864         uint8_t lut[ETH_RSS_RETA_SIZE_512];
8865         uint32_t i;
8866         int num;
8867
8868         /* If both VMDQ and RSS enabled, not all of PF queues are
8869          * configured. It's necessary to calculate the actual PF
8870          * queues that are configured.
8871          */
8872         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8873                 num = i40e_pf_calc_configured_queues_num(pf);
8874         else
8875                 num = pf->dev_data->nb_rx_queues;
8876
8877         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8878         if (num <= 0)
8879                 return 0;
8880
8881         for (i = 0; i < hw->func_caps.rss_table_size; i++)
8882                 lut[i] = (uint8_t)(i % (uint32_t)num);
8883
8884         return i40e_set_rss_lut(pf->main_vsi, lut, (uint16_t)i);
8885 }
8886
8887 int
8888 i40e_pf_reset_rss_key(struct i40e_pf *pf)
8889 {
8890         const uint8_t key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8891                         sizeof(uint32_t);
8892         uint8_t *rss_key;
8893
8894         /* Reset key */
8895         rss_key = pf->dev_data->dev_conf.rx_adv_conf.rss_conf.rss_key;
8896         if (!rss_key ||
8897             pf->dev_data->dev_conf.rx_adv_conf.rss_conf.rss_key_len < key_len) {
8898                 static uint32_t rss_key_default[] = {0x6b793944,
8899                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8900                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8901                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8902
8903                 rss_key = (uint8_t *)rss_key_default;
8904         }
8905
8906         return i40e_set_rss_key(pf->main_vsi, rss_key, key_len);
8907 }
8908
8909 static int
8910 i40e_pf_rss_reset(struct i40e_pf *pf)
8911 {
8912         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8913
8914         int ret;
8915
8916         pf->hash_filter_enabled = 0;
8917         i40e_pf_disable_rss(pf);
8918         i40e_set_symmetric_hash_enable_per_port(hw, 0);
8919
8920         if (!pf->support_multi_driver)
8921                 i40e_pf_global_rss_reset(pf);
8922
8923         /* Reset RETA table */
8924         if (pf->adapter->rss_reta_updated == 0) {
8925                 ret = i40e_pf_reset_rss_reta(pf);
8926                 if (ret)
8927                         return ret;
8928         }
8929
8930         return i40e_pf_reset_rss_key(pf);
8931 }
8932
8933 /* Configure RSS */
8934 int
8935 i40e_pf_config_rss(struct i40e_pf *pf)
8936 {
8937         struct i40e_hw *hw;
8938         enum rte_eth_rx_mq_mode mq_mode;
8939         uint64_t rss_hf, hena;
8940         int ret;
8941
8942         ret = i40e_pf_rss_reset(pf);
8943         if (ret) {
8944                 PMD_DRV_LOG(ERR, "Reset RSS failed, RSS has been disabled");
8945                 return ret;
8946         }
8947
8948         rss_hf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf.rss_hf;
8949         mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8950         if (!(rss_hf & pf->adapter->flow_types_mask) ||
8951             !(mq_mode & ETH_MQ_RX_RSS_FLAG))
8952                 return 0;
8953
8954         hw = I40E_PF_TO_HW(pf);
8955         hena = i40e_config_hena(pf->adapter, rss_hf);
8956         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
8957         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
8958         I40E_WRITE_FLUSH(hw);
8959
8960         return 0;
8961 }
8962
8963 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8964 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
8965 int
8966 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8967 {
8968         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8969         uint32_t val, reg;
8970         int ret = -EINVAL;
8971
8972         if (pf->support_multi_driver) {
8973                 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8974                 return -ENOTSUP;
8975         }
8976
8977         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8978         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8979
8980         if (len == 3) {
8981                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8982         } else if (len == 4) {
8983                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8984         } else {
8985                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8986                 return ret;
8987         }
8988
8989         if (reg != val) {
8990                 ret = i40e_aq_debug_write_global_register(hw,
8991                                                    I40E_GL_PRS_FVBM(2),
8992                                                    reg, NULL);
8993                 if (ret != 0)
8994                         return ret;
8995                 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8996                             "with value 0x%08x",
8997                             I40E_GL_PRS_FVBM(2), reg);
8998         } else {
8999                 ret = 0;
9000         }
9001         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
9002                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
9003
9004         return ret;
9005 }
9006
9007 /* Set the symmetric hash enable configurations per port */
9008 void
9009 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
9010 {
9011         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
9012
9013         if (enable > 0) {
9014                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)
9015                         return;
9016
9017                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
9018         } else {
9019                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK))
9020                         return;
9021
9022                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
9023         }
9024         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
9025         I40E_WRITE_FLUSH(hw);
9026 }
9027
9028 /**
9029  * Valid input sets for hash and flow director filters per PCTYPE
9030  */
9031 static uint64_t
9032 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
9033                 enum rte_filter_type filter)
9034 {
9035         uint64_t valid;
9036
9037         static const uint64_t valid_hash_inset_table[] = {
9038                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9039                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9040                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9041                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
9042                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
9043                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9044                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9045                         I40E_INSET_FLEX_PAYLOAD,
9046                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9047                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9048                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9049                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9050                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9051                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9052                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9053                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9054                         I40E_INSET_FLEX_PAYLOAD,
9055                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9056                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9057                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9058                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9059                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9060                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9061                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9062                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9063                         I40E_INSET_FLEX_PAYLOAD,
9064                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9065                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9066                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9067                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9068                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9069                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9070                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9071                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9072                         I40E_INSET_FLEX_PAYLOAD,
9073                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9074                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9075                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9076                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9077                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9078                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9079                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9080                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9081                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9082                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9083                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9084                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9085                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9086                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9087                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9088                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9089                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9090                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9091                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9092                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9093                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9094                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9095                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9096                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9097                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9098                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9099                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
9100                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9101                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9102                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9103                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9104                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9105                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9106                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9107                         I40E_INSET_FLEX_PAYLOAD,
9108                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9109                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9110                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9111                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9112                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9113                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
9114                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
9115                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
9116                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9117                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9118                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9119                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9120                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9121                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9122                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9123                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
9124                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9125                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9126                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9127                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9128                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9129                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9130                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9131                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9132                         I40E_INSET_FLEX_PAYLOAD,
9133                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9134                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9135                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9136                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9137                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9138                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9139                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9140                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9141                         I40E_INSET_FLEX_PAYLOAD,
9142                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9143                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9144                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9145                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9146                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9147                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9148                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9149                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9150                         I40E_INSET_FLEX_PAYLOAD,
9151                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9152                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9153                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9154                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9155                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9156                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9157                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9158                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9159                         I40E_INSET_FLEX_PAYLOAD,
9160                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9161                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9162                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9163                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9164                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9165                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9166                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9167                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9168                         I40E_INSET_FLEX_PAYLOAD,
9169                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9170                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9171                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9172                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9173                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9174                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9175                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9176                         I40E_INSET_FLEX_PAYLOAD,
9177                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9178                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9179                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9180                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9181                         I40E_INSET_FLEX_PAYLOAD,
9182         };
9183
9184         /**
9185          * Flow director supports only fields defined in
9186          * union rte_eth_fdir_flow.
9187          */
9188         static const uint64_t valid_fdir_inset_table[] = {
9189                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9190                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9191                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9192                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9193                 I40E_INSET_IPV4_TTL,
9194                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9195                 I40E_INSET_DMAC | I40E_INSET_SMAC |
9196                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9197                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9198                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9199                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9200                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9201                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9202                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9203                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9204                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9205                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9206                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9207                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9208                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9209                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9210                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9211                 I40E_INSET_DMAC | I40E_INSET_SMAC |
9212                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9213                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9214                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9215                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9216                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9217                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9218                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9219                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9220                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9221                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9222                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9223                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9224                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9225                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9226                 I40E_INSET_SCTP_VT,
9227                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9228                 I40E_INSET_DMAC | I40E_INSET_SMAC |
9229                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9230                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9231                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9232                 I40E_INSET_IPV4_TTL,
9233                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9234                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9235                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9236                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9237                 I40E_INSET_IPV6_HOP_LIMIT,
9238                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9239                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9240                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9241                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9242                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9243                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9244                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9245                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9246                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9247                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9248                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9249                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9250                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9251                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9252                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9253                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9254                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9255                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9256                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9257                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9258                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9259                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9260                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9261                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9262                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9263                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9264                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9265                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9266                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9267                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9268                 I40E_INSET_SCTP_VT,
9269                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9270                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9271                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9272                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9273                 I40E_INSET_IPV6_HOP_LIMIT,
9274                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9275                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9276                 I40E_INSET_LAST_ETHER_TYPE,
9277         };
9278
9279         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9280                 return 0;
9281         if (filter == RTE_ETH_FILTER_HASH)
9282                 valid = valid_hash_inset_table[pctype];
9283         else
9284                 valid = valid_fdir_inset_table[pctype];
9285
9286         return valid;
9287 }
9288
9289 /**
9290  * Validate if the input set is allowed for a specific PCTYPE
9291  */
9292 int
9293 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9294                 enum rte_filter_type filter, uint64_t inset)
9295 {
9296         uint64_t valid;
9297
9298         valid = i40e_get_valid_input_set(pctype, filter);
9299         if (inset & (~valid))
9300                 return -EINVAL;
9301
9302         return 0;
9303 }
9304
9305 /* default input set fields combination per pctype */
9306 uint64_t
9307 i40e_get_default_input_set(uint16_t pctype)
9308 {
9309         static const uint64_t default_inset_table[] = {
9310                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9311                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9312                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9313                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9314                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9315                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9316                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9317                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9318                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9319                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9320                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9321                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9322                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9323                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9324                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9325                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9326                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9327                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9328                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9329                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9330                         I40E_INSET_SCTP_VT,
9331                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9332                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9333                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9334                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9335                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9336                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9337                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9338                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9339                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9340                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9341                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9342                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9343                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9344                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9345                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9346                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9347                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9348                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9349                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9350                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9351                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9352                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9353                         I40E_INSET_SCTP_VT,
9354                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9355                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9356                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9357                         I40E_INSET_LAST_ETHER_TYPE,
9358         };
9359
9360         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9361                 return 0;
9362
9363         return default_inset_table[pctype];
9364 }
9365
9366 /**
9367  * Translate the input set from bit masks to register aware bit masks
9368  * and vice versa
9369  */
9370 uint64_t
9371 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9372 {
9373         uint64_t val = 0;
9374         uint16_t i;
9375
9376         struct inset_map {
9377                 uint64_t inset;
9378                 uint64_t inset_reg;
9379         };
9380
9381         static const struct inset_map inset_map_common[] = {
9382                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9383                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9384                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9385                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9386                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9387                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9388                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9389                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9390                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9391                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9392                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9393                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9394                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9395                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9396                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9397                 {I40E_INSET_TUNNEL_DMAC,
9398                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9399                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9400                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9401                 {I40E_INSET_TUNNEL_SRC_PORT,
9402                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9403                 {I40E_INSET_TUNNEL_DST_PORT,
9404                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9405                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9406                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9407                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9408                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9409                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9410                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9411                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9412                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9413                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9414         };
9415
9416     /* some different registers map in x722*/
9417         static const struct inset_map inset_map_diff_x722[] = {
9418                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9419                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9420                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9421                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9422         };
9423
9424         static const struct inset_map inset_map_diff_not_x722[] = {
9425                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9426                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9427                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9428                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9429         };
9430
9431         if (input == 0)
9432                 return val;
9433
9434         /* Translate input set to register aware inset */
9435         if (type == I40E_MAC_X722) {
9436                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9437                         if (input & inset_map_diff_x722[i].inset)
9438                                 val |= inset_map_diff_x722[i].inset_reg;
9439                 }
9440         } else {
9441                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9442                         if (input & inset_map_diff_not_x722[i].inset)
9443                                 val |= inset_map_diff_not_x722[i].inset_reg;
9444                 }
9445         }
9446
9447         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9448                 if (input & inset_map_common[i].inset)
9449                         val |= inset_map_common[i].inset_reg;
9450         }
9451
9452         return val;
9453 }
9454
9455 static int
9456 i40e_get_inset_field_offset(struct i40e_hw *hw, uint32_t pit_reg_start,
9457                             uint32_t pit_reg_count, uint32_t hdr_off)
9458 {
9459         const uint32_t pit_reg_end = pit_reg_start + pit_reg_count;
9460         uint32_t field_off = I40E_FDIR_FIELD_OFFSET(hdr_off);
9461         uint32_t i, reg_val, src_off, count;
9462
9463         for (i = pit_reg_start; i < pit_reg_end; i++) {
9464                 reg_val = i40e_read_rx_ctl(hw, I40E_GLQF_PIT(i));
9465
9466                 src_off = I40E_GLQF_PIT_SOURCE_OFF_GET(reg_val);
9467                 count = I40E_GLQF_PIT_FSIZE_GET(reg_val);
9468
9469                 if (src_off <= field_off && (src_off + count) > field_off)
9470                         break;
9471         }
9472
9473         if (i >= pit_reg_end) {
9474                 PMD_DRV_LOG(ERR,
9475                             "Hardware GLQF_PIT configuration does not support this field mask");
9476                 return -1;
9477         }
9478
9479         return I40E_GLQF_PIT_DEST_OFF_GET(reg_val) + field_off - src_off;
9480 }
9481
9482 int
9483 i40e_generate_inset_mask_reg(struct i40e_hw *hw, uint64_t inset,
9484                              uint32_t *mask, uint8_t nb_elem)
9485 {
9486         static const uint64_t mask_inset[] = {
9487                 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL,
9488                 I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT };
9489
9490         static const struct {
9491                 uint64_t inset;
9492                 uint32_t mask;
9493                 uint32_t offset;
9494         } inset_mask_offset_map[] = {
9495                 { I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK,
9496                   offsetof(struct rte_ipv4_hdr, type_of_service) },
9497
9498                 { I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK,
9499                   offsetof(struct rte_ipv4_hdr, next_proto_id) },
9500
9501                 { I40E_INSET_IPV4_TTL, I40E_INSET_IPV4_TTL_MASK,
9502                   offsetof(struct rte_ipv4_hdr, time_to_live) },
9503
9504                 { I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK,
9505                   offsetof(struct rte_ipv6_hdr, vtc_flow) },
9506
9507                 { I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK,
9508                   offsetof(struct rte_ipv6_hdr, proto) },
9509
9510                 { I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK,
9511                   offsetof(struct rte_ipv6_hdr, hop_limits) },
9512         };
9513
9514         uint32_t i;
9515         int idx = 0;
9516
9517         assert(mask);
9518         if (!inset)
9519                 return 0;
9520
9521         for (i = 0; i < RTE_DIM(mask_inset); i++) {
9522                 /* Clear the inset bit, if no MASK is required,
9523                  * for example proto + ttl
9524                  */
9525                 if ((mask_inset[i] & inset) == mask_inset[i]) {
9526                         inset &= ~mask_inset[i];
9527                         if (!inset)
9528                                 return 0;
9529                 }
9530         }
9531
9532         for (i = 0; i < RTE_DIM(inset_mask_offset_map); i++) {
9533                 uint32_t pit_start, pit_count;
9534                 int offset;
9535
9536                 if (!(inset_mask_offset_map[i].inset & inset))
9537                         continue;
9538
9539                 if (inset_mask_offset_map[i].inset &
9540                     (I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9541                      I40E_INSET_IPV4_TTL)) {
9542                         pit_start = I40E_GLQF_PIT_IPV4_START;
9543                         pit_count = I40E_GLQF_PIT_IPV4_COUNT;
9544                 } else {
9545                         pit_start = I40E_GLQF_PIT_IPV6_START;
9546                         pit_count = I40E_GLQF_PIT_IPV6_COUNT;
9547                 }
9548
9549                 offset = i40e_get_inset_field_offset(hw, pit_start, pit_count,
9550                                 inset_mask_offset_map[i].offset);
9551
9552                 if (offset < 0)
9553                         return -EINVAL;
9554
9555                 if (idx >= nb_elem) {
9556                         PMD_DRV_LOG(ERR,
9557                                     "Configuration of inset mask out of range %u",
9558                                     nb_elem);
9559                         return -ERANGE;
9560                 }
9561
9562                 mask[idx] = I40E_GLQF_PIT_BUILD((uint32_t)offset,
9563                                                 inset_mask_offset_map[i].mask);
9564                 idx++;
9565         }
9566
9567         return idx;
9568 }
9569
9570 void
9571 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9572 {
9573         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9574
9575         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9576         if (reg != val)
9577                 i40e_write_rx_ctl(hw, addr, val);
9578         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9579                     (uint32_t)i40e_read_rx_ctl(hw, addr));
9580 }
9581
9582 void
9583 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9584 {
9585         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9586         struct rte_eth_dev *dev;
9587
9588         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
9589         if (reg != val) {
9590                 i40e_write_rx_ctl(hw, addr, val);
9591                 PMD_DRV_LOG(WARNING,
9592                             "i40e device %s changed global register [0x%08x]."
9593                             " original: 0x%08x, new: 0x%08x",
9594                             dev->device->name, addr, reg,
9595                             (uint32_t)i40e_read_rx_ctl(hw, addr));
9596         }
9597 }
9598
9599 static void
9600 i40e_filter_input_set_init(struct i40e_pf *pf)
9601 {
9602         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9603         enum i40e_filter_pctype pctype;
9604         uint64_t input_set, inset_reg;
9605         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9606         int num, i;
9607         uint16_t flow_type;
9608
9609         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9610              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9611                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9612
9613                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9614                         continue;
9615
9616                 input_set = i40e_get_default_input_set(pctype);
9617
9618                 num = i40e_generate_inset_mask_reg(hw, input_set, mask_reg,
9619                                                    I40E_INSET_MASK_NUM_REG);
9620                 if (num < 0)
9621                         return;
9622                 if (pf->support_multi_driver && num > 0) {
9623                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9624                         return;
9625                 }
9626                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9627                                         input_set);
9628
9629                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9630                                       (uint32_t)(inset_reg & UINT32_MAX));
9631                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9632                                      (uint32_t)((inset_reg >>
9633                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
9634                 if (!pf->support_multi_driver) {
9635                         i40e_check_write_global_reg(hw,
9636                                             I40E_GLQF_HASH_INSET(0, pctype),
9637                                             (uint32_t)(inset_reg & UINT32_MAX));
9638                         i40e_check_write_global_reg(hw,
9639                                              I40E_GLQF_HASH_INSET(1, pctype),
9640                                              (uint32_t)((inset_reg >>
9641                                               I40E_32_BIT_WIDTH) & UINT32_MAX));
9642
9643                         for (i = 0; i < num; i++) {
9644                                 i40e_check_write_global_reg(hw,
9645                                                     I40E_GLQF_FD_MSK(i, pctype),
9646                                                     mask_reg[i]);
9647                                 i40e_check_write_global_reg(hw,
9648                                                   I40E_GLQF_HASH_MSK(i, pctype),
9649                                                   mask_reg[i]);
9650                         }
9651                         /*clear unused mask registers of the pctype */
9652                         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9653                                 i40e_check_write_global_reg(hw,
9654                                                     I40E_GLQF_FD_MSK(i, pctype),
9655                                                     0);
9656                                 i40e_check_write_global_reg(hw,
9657                                                   I40E_GLQF_HASH_MSK(i, pctype),
9658                                                   0);
9659                         }
9660                 } else {
9661                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9662                 }
9663                 I40E_WRITE_FLUSH(hw);
9664
9665                 /* store the default input set */
9666                 if (!pf->support_multi_driver)
9667                         pf->hash_input_set[pctype] = input_set;
9668                 pf->fdir.input_set[pctype] = input_set;
9669         }
9670 }
9671
9672 int
9673 i40e_set_hash_inset(struct i40e_hw *hw, uint64_t input_set,
9674                     uint32_t pctype, bool add)
9675 {
9676         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9677         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9678         uint64_t inset_reg = 0;
9679         int num, i;
9680
9681         if (pf->support_multi_driver) {
9682                 PMD_DRV_LOG(ERR,
9683                             "Modify input set is not permitted when multi-driver enabled.");
9684                 return -EPERM;
9685         }
9686
9687         /* For X722, get translated pctype in fd pctype register */
9688         if (hw->mac.type == I40E_MAC_X722)
9689                 pctype = i40e_read_rx_ctl(hw, I40E_GLQF_FD_PCTYPES(pctype));
9690
9691         if (add) {
9692                 /* get inset value in register */
9693                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9694                 inset_reg <<= I40E_32_BIT_WIDTH;
9695                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9696                 input_set |= pf->hash_input_set[pctype];
9697         }
9698         num = i40e_generate_inset_mask_reg(hw, input_set, mask_reg,
9699                                            I40E_INSET_MASK_NUM_REG);
9700         if (num < 0)
9701                 return -EINVAL;
9702
9703         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9704
9705         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9706                                     (uint32_t)(inset_reg & UINT32_MAX));
9707         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9708                                     (uint32_t)((inset_reg >>
9709                                     I40E_32_BIT_WIDTH) & UINT32_MAX));
9710
9711         for (i = 0; i < num; i++)
9712                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9713                                             mask_reg[i]);
9714         /*clear unused mask registers of the pctype */
9715         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9716                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9717                                             0);
9718         I40E_WRITE_FLUSH(hw);
9719
9720         pf->hash_input_set[pctype] = input_set;
9721         return 0;
9722 }
9723
9724 /* Convert ethertype filter structure */
9725 static int
9726 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9727                               struct i40e_ethertype_filter *filter)
9728 {
9729         rte_memcpy(&filter->input.mac_addr, &input->mac_addr,
9730                 RTE_ETHER_ADDR_LEN);
9731         filter->input.ether_type = input->ether_type;
9732         filter->flags = input->flags;
9733         filter->queue = input->queue;
9734
9735         return 0;
9736 }
9737
9738 /* Check if there exists the ehtertype filter */
9739 struct i40e_ethertype_filter *
9740 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9741                                 const struct i40e_ethertype_filter_input *input)
9742 {
9743         int ret;
9744
9745         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9746         if (ret < 0)
9747                 return NULL;
9748
9749         return ethertype_rule->hash_map[ret];
9750 }
9751
9752 /* Add ethertype filter in SW list */
9753 static int
9754 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9755                                 struct i40e_ethertype_filter *filter)
9756 {
9757         struct i40e_ethertype_rule *rule = &pf->ethertype;
9758         int ret;
9759
9760         ret = rte_hash_add_key(rule->hash_table, &filter->input);
9761         if (ret < 0) {
9762                 PMD_DRV_LOG(ERR,
9763                             "Failed to insert ethertype filter"
9764                             " to hash table %d!",
9765                             ret);
9766                 return ret;
9767         }
9768         rule->hash_map[ret] = filter;
9769
9770         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9771
9772         return 0;
9773 }
9774
9775 /* Delete ethertype filter in SW list */
9776 int
9777 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9778                              struct i40e_ethertype_filter_input *input)
9779 {
9780         struct i40e_ethertype_rule *rule = &pf->ethertype;
9781         struct i40e_ethertype_filter *filter;
9782         int ret;
9783
9784         ret = rte_hash_del_key(rule->hash_table, input);
9785         if (ret < 0) {
9786                 PMD_DRV_LOG(ERR,
9787                             "Failed to delete ethertype filter"
9788                             " to hash table %d!",
9789                             ret);
9790                 return ret;
9791         }
9792         filter = rule->hash_map[ret];
9793         rule->hash_map[ret] = NULL;
9794
9795         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9796         rte_free(filter);
9797
9798         return 0;
9799 }
9800
9801 /*
9802  * Configure ethertype filter, which can director packet by filtering
9803  * with mac address and ether_type or only ether_type
9804  */
9805 int
9806 i40e_ethertype_filter_set(struct i40e_pf *pf,
9807                         struct rte_eth_ethertype_filter *filter,
9808                         bool add)
9809 {
9810         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9811         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9812         struct i40e_ethertype_filter *ethertype_filter, *node;
9813         struct i40e_ethertype_filter check_filter;
9814         struct i40e_control_filter_stats stats;
9815         uint16_t flags = 0;
9816         int ret;
9817
9818         if (filter->queue >= pf->dev_data->nb_rx_queues) {
9819                 PMD_DRV_LOG(ERR, "Invalid queue ID");
9820                 return -EINVAL;
9821         }
9822         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
9823                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
9824                 PMD_DRV_LOG(ERR,
9825                         "unsupported ether_type(0x%04x) in control packet filter.",
9826                         filter->ether_type);
9827                 return -EINVAL;
9828         }
9829         if (filter->ether_type == RTE_ETHER_TYPE_VLAN)
9830                 PMD_DRV_LOG(WARNING,
9831                         "filter vlan ether_type in first tag is not supported.");
9832
9833         /* Check if there is the filter in SW list */
9834         memset(&check_filter, 0, sizeof(check_filter));
9835         i40e_ethertype_filter_convert(filter, &check_filter);
9836         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9837                                                &check_filter.input);
9838         if (add && node) {
9839                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9840                 return -EINVAL;
9841         }
9842
9843         if (!add && !node) {
9844                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9845                 return -EINVAL;
9846         }
9847
9848         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9849                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9850         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9851                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9852         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9853
9854         memset(&stats, 0, sizeof(stats));
9855         ret = i40e_aq_add_rem_control_packet_filter(hw,
9856                         filter->mac_addr.addr_bytes,
9857                         filter->ether_type, flags,
9858                         pf->main_vsi->seid,
9859                         filter->queue, add, &stats, NULL);
9860
9861         PMD_DRV_LOG(INFO,
9862                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9863                 ret, stats.mac_etype_used, stats.etype_used,
9864                 stats.mac_etype_free, stats.etype_free);
9865         if (ret < 0)
9866                 return -ENOSYS;
9867
9868         /* Add or delete a filter in SW list */
9869         if (add) {
9870                 ethertype_filter = rte_zmalloc("ethertype_filter",
9871                                        sizeof(*ethertype_filter), 0);
9872                 if (ethertype_filter == NULL) {
9873                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
9874                         return -ENOMEM;
9875                 }
9876
9877                 rte_memcpy(ethertype_filter, &check_filter,
9878                            sizeof(check_filter));
9879                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9880                 if (ret < 0)
9881                         rte_free(ethertype_filter);
9882         } else {
9883                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9884         }
9885
9886         return ret;
9887 }
9888
9889 static int
9890 i40e_dev_flow_ops_get(struct rte_eth_dev *dev,
9891                       const struct rte_flow_ops **ops)
9892 {
9893         if (dev == NULL)
9894                 return -EINVAL;
9895
9896         *ops = &i40e_flow_ops;
9897         return 0;
9898 }
9899
9900 /*
9901  * Check and enable Extended Tag.
9902  * Enabling Extended Tag is important for 40G performance.
9903  */
9904 static void
9905 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9906 {
9907         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9908         uint32_t buf = 0;
9909         int ret;
9910
9911         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9912                                       PCI_DEV_CAP_REG);
9913         if (ret < 0) {
9914                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9915                             PCI_DEV_CAP_REG);
9916                 return;
9917         }
9918         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9919                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9920                 return;
9921         }
9922
9923         buf = 0;
9924         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9925                                       PCI_DEV_CTRL_REG);
9926         if (ret < 0) {
9927                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9928                             PCI_DEV_CTRL_REG);
9929                 return;
9930         }
9931         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9932                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9933                 return;
9934         }
9935         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9936         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9937                                        PCI_DEV_CTRL_REG);
9938         if (ret < 0) {
9939                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9940                             PCI_DEV_CTRL_REG);
9941                 return;
9942         }
9943 }
9944
9945 /*
9946  * As some registers wouldn't be reset unless a global hardware reset,
9947  * hardware initialization is needed to put those registers into an
9948  * expected initial state.
9949  */
9950 static void
9951 i40e_hw_init(struct rte_eth_dev *dev)
9952 {
9953         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9954
9955         i40e_enable_extended_tag(dev);
9956
9957         /* clear the PF Queue Filter control register */
9958         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9959
9960         /* Disable symmetric hash per port */
9961         i40e_set_symmetric_hash_enable_per_port(hw, 0);
9962 }
9963
9964 /*
9965  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
9966  * however this function will return only one highest pctype index,
9967  * which is not quite correct. This is known problem of i40e driver
9968  * and needs to be fixed later.
9969  */
9970 enum i40e_filter_pctype
9971 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
9972 {
9973         int i;
9974         uint64_t pctype_mask;
9975
9976         if (flow_type < I40E_FLOW_TYPE_MAX) {
9977                 pctype_mask = adapter->pctypes_tbl[flow_type];
9978                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
9979                         if (pctype_mask & (1ULL << i))
9980                                 return (enum i40e_filter_pctype)i;
9981                 }
9982         }
9983         return I40E_FILTER_PCTYPE_INVALID;
9984 }
9985
9986 uint16_t
9987 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
9988                         enum i40e_filter_pctype pctype)
9989 {
9990         uint16_t flowtype;
9991         uint64_t pctype_mask = 1ULL << pctype;
9992
9993         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
9994              flowtype++) {
9995                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
9996                         return flowtype;
9997         }
9998
9999         return RTE_ETH_FLOW_UNKNOWN;
10000 }
10001
10002 /*
10003  * On X710, performance number is far from the expectation on recent firmware
10004  * versions; on XL710, performance number is also far from the expectation on
10005  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10006  * mode is enabled and port MAC address is equal to the packet destination MAC
10007  * address. The fix for this issue may not be integrated in the following
10008  * firmware version. So the workaround in software driver is needed. It needs
10009  * to modify the initial values of 3 internal only registers for both X710 and
10010  * XL710. Note that the values for X710 or XL710 could be different, and the
10011  * workaround can be removed when it is fixed in firmware in the future.
10012  */
10013
10014 /* For both X710 and XL710 */
10015 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
10016 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
10017 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
10018
10019 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10020 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
10021
10022 /* For X722 */
10023 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10024 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10025
10026 /* For X710 */
10027 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
10028 /* For XL710 */
10029 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
10030 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
10031
10032 /*
10033  * GL_SWR_PM_UP_THR:
10034  * The value is not impacted from the link speed, its value is set according
10035  * to the total number of ports for a better pipe-monitor configuration.
10036  */
10037 static bool
10038 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10039 {
10040 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10041                 .device_id = (dev),   \
10042                 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10043
10044 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10045                 .device_id = (dev),   \
10046                 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10047
10048         static const struct {
10049                 uint16_t device_id;
10050                 uint32_t val;
10051         } swr_pm_table[] = {
10052                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10053                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10054                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10055                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10056                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_X722) },
10057
10058                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10059                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10060                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10061                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10062                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10063                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10064                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10065         };
10066         uint32_t i;
10067
10068         if (value == NULL) {
10069                 PMD_DRV_LOG(ERR, "value is NULL");
10070                 return false;
10071         }
10072
10073         for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10074                 if (hw->device_id == swr_pm_table[i].device_id) {
10075                         *value = swr_pm_table[i].val;
10076
10077                         PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10078                                     "value - 0x%08x",
10079                                     hw->device_id, *value);
10080                         return true;
10081                 }
10082         }
10083
10084         return false;
10085 }
10086
10087 static int
10088 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10089 {
10090         enum i40e_status_code status;
10091         struct i40e_aq_get_phy_abilities_resp phy_ab;
10092         int ret = -ENOTSUP;
10093         int retries = 0;
10094
10095         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10096                                               NULL);
10097
10098         while (status) {
10099                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10100                         status);
10101                 retries++;
10102                 rte_delay_us(100000);
10103                 if  (retries < 5)
10104                         status = i40e_aq_get_phy_capabilities(hw, false,
10105                                         true, &phy_ab, NULL);
10106                 else
10107                         return ret;
10108         }
10109         return 0;
10110 }
10111
10112 static void
10113 i40e_configure_registers(struct i40e_hw *hw)
10114 {
10115         static struct {
10116                 uint32_t addr;
10117                 uint64_t val;
10118         } reg_table[] = {
10119                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10120                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10121                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10122         };
10123         uint64_t reg;
10124         uint32_t i;
10125         int ret;
10126
10127         for (i = 0; i < RTE_DIM(reg_table); i++) {
10128                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10129                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10130                                 reg_table[i].val =
10131                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10132                         else /* For X710/XL710/XXV710 */
10133                                 if (hw->aq.fw_maj_ver < 6)
10134                                         reg_table[i].val =
10135                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10136                                 else
10137                                         reg_table[i].val =
10138                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10139                 }
10140
10141                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10142                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10143                                 reg_table[i].val =
10144                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10145                         else /* For X710/XL710/XXV710 */
10146                                 reg_table[i].val =
10147                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10148                 }
10149
10150                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10151                         uint32_t cfg_val;
10152
10153                         if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10154                                 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10155                                             "GL_SWR_PM_UP_THR value fixup",
10156                                             hw->device_id);
10157                                 continue;
10158                         }
10159
10160                         reg_table[i].val = cfg_val;
10161                 }
10162
10163                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10164                                                         &reg, NULL);
10165                 if (ret < 0) {
10166                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10167                                                         reg_table[i].addr);
10168                         break;
10169                 }
10170                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10171                                                 reg_table[i].addr, reg);
10172                 if (reg == reg_table[i].val)
10173                         continue;
10174
10175                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10176                                                 reg_table[i].val, NULL);
10177                 if (ret < 0) {
10178                         PMD_DRV_LOG(ERR,
10179                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10180                                 reg_table[i].val, reg_table[i].addr);
10181                         break;
10182                 }
10183                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10184                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10185         }
10186 }
10187
10188 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
10189 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
10190 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10191 static int
10192 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10193 {
10194         uint32_t reg;
10195         int ret;
10196
10197         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10198                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10199                 return -EINVAL;
10200         }
10201
10202         /* Configure for double VLAN RX stripping */
10203         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10204         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10205                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10206                 ret = i40e_aq_debug_write_register(hw,
10207                                                    I40E_VSI_TSR(vsi->vsi_id),
10208                                                    reg, NULL);
10209                 if (ret < 0) {
10210                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10211                                     vsi->vsi_id);
10212                         return I40E_ERR_CONFIG;
10213                 }
10214         }
10215
10216         /* Configure for double VLAN TX insertion */
10217         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10218         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10219                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10220                 ret = i40e_aq_debug_write_register(hw,
10221                                                    I40E_VSI_L2TAGSTXVALID(
10222                                                    vsi->vsi_id), reg, NULL);
10223                 if (ret < 0) {
10224                         PMD_DRV_LOG(ERR,
10225                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
10226                                 vsi->vsi_id);
10227                         return I40E_ERR_CONFIG;
10228                 }
10229         }
10230
10231         return 0;
10232 }
10233
10234 /**
10235  * i40e_aq_add_mirror_rule
10236  * @hw: pointer to the hardware structure
10237  * @seid: VEB seid to add mirror rule to
10238  * @dst_id: destination vsi seid
10239  * @entries: Buffer which contains the entities to be mirrored
10240  * @count: number of entities contained in the buffer
10241  * @rule_id:the rule_id of the rule to be added
10242  *
10243  * Add a mirror rule for a given veb.
10244  *
10245  **/
10246 static enum i40e_status_code
10247 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10248                         uint16_t seid, uint16_t dst_id,
10249                         uint16_t rule_type, uint16_t *entries,
10250                         uint16_t count, uint16_t *rule_id)
10251 {
10252         struct i40e_aq_desc desc;
10253         struct i40e_aqc_add_delete_mirror_rule cmd;
10254         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10255                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10256                 &desc.params.raw;
10257         uint16_t buff_len;
10258         enum i40e_status_code status;
10259
10260         i40e_fill_default_direct_cmd_desc(&desc,
10261                                           i40e_aqc_opc_add_mirror_rule);
10262         memset(&cmd, 0, sizeof(cmd));
10263
10264         buff_len = sizeof(uint16_t) * count;
10265         desc.datalen = rte_cpu_to_le_16(buff_len);
10266         if (buff_len > 0)
10267                 desc.flags |= rte_cpu_to_le_16(
10268                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10269         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10270                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10271         cmd.num_entries = rte_cpu_to_le_16(count);
10272         cmd.seid = rte_cpu_to_le_16(seid);
10273         cmd.destination = rte_cpu_to_le_16(dst_id);
10274
10275         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10276         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10277         PMD_DRV_LOG(INFO,
10278                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10279                 hw->aq.asq_last_status, resp->rule_id,
10280                 resp->mirror_rules_used, resp->mirror_rules_free);
10281         *rule_id = rte_le_to_cpu_16(resp->rule_id);
10282
10283         return status;
10284 }
10285
10286 /**
10287  * i40e_aq_del_mirror_rule
10288  * @hw: pointer to the hardware structure
10289  * @seid: VEB seid to add mirror rule to
10290  * @entries: Buffer which contains the entities to be mirrored
10291  * @count: number of entities contained in the buffer
10292  * @rule_id:the rule_id of the rule to be delete
10293  *
10294  * Delete a mirror rule for a given veb.
10295  *
10296  **/
10297 static enum i40e_status_code
10298 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10299                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10300                 uint16_t count, uint16_t rule_id)
10301 {
10302         struct i40e_aq_desc desc;
10303         struct i40e_aqc_add_delete_mirror_rule cmd;
10304         uint16_t buff_len = 0;
10305         enum i40e_status_code status;
10306         void *buff = NULL;
10307
10308         i40e_fill_default_direct_cmd_desc(&desc,
10309                                           i40e_aqc_opc_delete_mirror_rule);
10310         memset(&cmd, 0, sizeof(cmd));
10311         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10312                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10313                                                           I40E_AQ_FLAG_RD));
10314                 cmd.num_entries = count;
10315                 buff_len = sizeof(uint16_t) * count;
10316                 desc.datalen = rte_cpu_to_le_16(buff_len);
10317                 buff = (void *)entries;
10318         } else
10319                 /* rule id is filled in destination field for deleting mirror rule */
10320                 cmd.destination = rte_cpu_to_le_16(rule_id);
10321
10322         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10323                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10324         cmd.seid = rte_cpu_to_le_16(seid);
10325
10326         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10327         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10328
10329         return status;
10330 }
10331
10332 /**
10333  * i40e_mirror_rule_set
10334  * @dev: pointer to the hardware structure
10335  * @mirror_conf: mirror rule info
10336  * @sw_id: mirror rule's sw_id
10337  * @on: enable/disable
10338  *
10339  * set a mirror rule.
10340  *
10341  **/
10342 static int
10343 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10344                         struct rte_eth_mirror_conf *mirror_conf,
10345                         uint8_t sw_id, uint8_t on)
10346 {
10347         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10348         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10349         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10350         struct i40e_mirror_rule *parent = NULL;
10351         uint16_t seid, dst_seid, rule_id;
10352         uint16_t i, j = 0;
10353         int ret;
10354
10355         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10356
10357         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10358                 PMD_DRV_LOG(ERR,
10359                         "mirror rule can not be configured without veb or vfs.");
10360                 return -ENOSYS;
10361         }
10362         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10363                 PMD_DRV_LOG(ERR, "mirror table is full.");
10364                 return -ENOSPC;
10365         }
10366         if (mirror_conf->dst_pool > pf->vf_num) {
10367                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10368                                  mirror_conf->dst_pool);
10369                 return -EINVAL;
10370         }
10371
10372         seid = pf->main_vsi->veb->seid;
10373
10374         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10375                 if (sw_id <= it->index) {
10376                         mirr_rule = it;
10377                         break;
10378                 }
10379                 parent = it;
10380         }
10381         if (mirr_rule && sw_id == mirr_rule->index) {
10382                 if (on) {
10383                         PMD_DRV_LOG(ERR, "mirror rule exists.");
10384                         return -EEXIST;
10385                 } else {
10386                         ret = i40e_aq_del_mirror_rule(hw, seid,
10387                                         mirr_rule->rule_type,
10388                                         mirr_rule->entries,
10389                                         mirr_rule->num_entries, mirr_rule->id);
10390                         if (ret < 0) {
10391                                 PMD_DRV_LOG(ERR,
10392                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
10393                                         ret, hw->aq.asq_last_status);
10394                                 return -ENOSYS;
10395                         }
10396                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10397                         rte_free(mirr_rule);
10398                         pf->nb_mirror_rule--;
10399                         return 0;
10400                 }
10401         } else if (!on) {
10402                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10403                 return -ENOENT;
10404         }
10405
10406         mirr_rule = rte_zmalloc("i40e_mirror_rule",
10407                                 sizeof(struct i40e_mirror_rule) , 0);
10408         if (!mirr_rule) {
10409                 PMD_DRV_LOG(ERR, "failed to allocate memory");
10410                 return I40E_ERR_NO_MEMORY;
10411         }
10412         switch (mirror_conf->rule_type) {
10413         case ETH_MIRROR_VLAN:
10414                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10415                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10416                                 mirr_rule->entries[j] =
10417                                         mirror_conf->vlan.vlan_id[i];
10418                                 j++;
10419                         }
10420                 }
10421                 if (j == 0) {
10422                         PMD_DRV_LOG(ERR, "vlan is not specified.");
10423                         rte_free(mirr_rule);
10424                         return -EINVAL;
10425                 }
10426                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10427                 break;
10428         case ETH_MIRROR_VIRTUAL_POOL_UP:
10429         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10430                 /* check if the specified pool bit is out of range */
10431                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10432                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
10433                         rte_free(mirr_rule);
10434                         return -EINVAL;
10435                 }
10436                 for (i = 0, j = 0; i < pf->vf_num; i++) {
10437                         if (mirror_conf->pool_mask & (1ULL << i)) {
10438                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10439                                 j++;
10440                         }
10441                 }
10442                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10443                         /* add pf vsi to entries */
10444                         mirr_rule->entries[j] = pf->main_vsi_seid;
10445                         j++;
10446                 }
10447                 if (j == 0) {
10448                         PMD_DRV_LOG(ERR, "pool is not specified.");
10449                         rte_free(mirr_rule);
10450                         return -EINVAL;
10451                 }
10452                 /* egress and ingress in aq commands means from switch but not port */
10453                 mirr_rule->rule_type =
10454                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10455                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10456                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10457                 break;
10458         case ETH_MIRROR_UPLINK_PORT:
10459                 /* egress and ingress in aq commands means from switch but not port*/
10460                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10461                 break;
10462         case ETH_MIRROR_DOWNLINK_PORT:
10463                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10464                 break;
10465         default:
10466                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10467                         mirror_conf->rule_type);
10468                 rte_free(mirr_rule);
10469                 return -EINVAL;
10470         }
10471
10472         /* If the dst_pool is equal to vf_num, consider it as PF */
10473         if (mirror_conf->dst_pool == pf->vf_num)
10474                 dst_seid = pf->main_vsi_seid;
10475         else
10476                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10477
10478         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10479                                       mirr_rule->rule_type, mirr_rule->entries,
10480                                       j, &rule_id);
10481         if (ret < 0) {
10482                 PMD_DRV_LOG(ERR,
10483                         "failed to add mirror rule: ret = %d, aq_err = %d.",
10484                         ret, hw->aq.asq_last_status);
10485                 rte_free(mirr_rule);
10486                 return -ENOSYS;
10487         }
10488
10489         mirr_rule->index = sw_id;
10490         mirr_rule->num_entries = j;
10491         mirr_rule->id = rule_id;
10492         mirr_rule->dst_vsi_seid = dst_seid;
10493
10494         if (parent)
10495                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10496         else
10497                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10498
10499         pf->nb_mirror_rule++;
10500         return 0;
10501 }
10502
10503 /**
10504  * i40e_mirror_rule_reset
10505  * @dev: pointer to the device
10506  * @sw_id: mirror rule's sw_id
10507  *
10508  * reset a mirror rule.
10509  *
10510  **/
10511 static int
10512 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10513 {
10514         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10515         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10516         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10517         uint16_t seid;
10518         int ret;
10519
10520         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10521
10522         seid = pf->main_vsi->veb->seid;
10523
10524         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10525                 if (sw_id == it->index) {
10526                         mirr_rule = it;
10527                         break;
10528                 }
10529         }
10530         if (mirr_rule) {
10531                 ret = i40e_aq_del_mirror_rule(hw, seid,
10532                                 mirr_rule->rule_type,
10533                                 mirr_rule->entries,
10534                                 mirr_rule->num_entries, mirr_rule->id);
10535                 if (ret < 0) {
10536                         PMD_DRV_LOG(ERR,
10537                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
10538                                 ret, hw->aq.asq_last_status);
10539                         return -ENOSYS;
10540                 }
10541                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10542                 rte_free(mirr_rule);
10543                 pf->nb_mirror_rule--;
10544         } else {
10545                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10546                 return -ENOENT;
10547         }
10548         return 0;
10549 }
10550
10551 static uint64_t
10552 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10553 {
10554         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10555         uint64_t systim_cycles;
10556
10557         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10558         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10559                         << 32;
10560
10561         return systim_cycles;
10562 }
10563
10564 static uint64_t
10565 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10566 {
10567         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10568         uint64_t rx_tstamp;
10569
10570         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10571         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10572                         << 32;
10573
10574         return rx_tstamp;
10575 }
10576
10577 static uint64_t
10578 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10579 {
10580         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10581         uint64_t tx_tstamp;
10582
10583         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10584         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10585                         << 32;
10586
10587         return tx_tstamp;
10588 }
10589
10590 static void
10591 i40e_start_timecounters(struct rte_eth_dev *dev)
10592 {
10593         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10594         struct i40e_adapter *adapter = dev->data->dev_private;
10595         struct rte_eth_link link;
10596         uint32_t tsync_inc_l;
10597         uint32_t tsync_inc_h;
10598
10599         /* Get current link speed. */
10600         i40e_dev_link_update(dev, 1);
10601         rte_eth_linkstatus_get(dev, &link);
10602
10603         switch (link.link_speed) {
10604         case ETH_SPEED_NUM_40G:
10605         case ETH_SPEED_NUM_25G:
10606                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10607                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10608                 break;
10609         case ETH_SPEED_NUM_10G:
10610                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10611                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10612                 break;
10613         case ETH_SPEED_NUM_1G:
10614                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10615                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10616                 break;
10617         default:
10618                 tsync_inc_l = 0x0;
10619                 tsync_inc_h = 0x0;
10620         }
10621
10622         /* Set the timesync increment value. */
10623         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10624         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10625
10626         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10627         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10628         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10629
10630         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10631         adapter->systime_tc.cc_shift = 0;
10632         adapter->systime_tc.nsec_mask = 0;
10633
10634         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10635         adapter->rx_tstamp_tc.cc_shift = 0;
10636         adapter->rx_tstamp_tc.nsec_mask = 0;
10637
10638         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10639         adapter->tx_tstamp_tc.cc_shift = 0;
10640         adapter->tx_tstamp_tc.nsec_mask = 0;
10641 }
10642
10643 static int
10644 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10645 {
10646         struct i40e_adapter *adapter = dev->data->dev_private;
10647
10648         adapter->systime_tc.nsec += delta;
10649         adapter->rx_tstamp_tc.nsec += delta;
10650         adapter->tx_tstamp_tc.nsec += delta;
10651
10652         return 0;
10653 }
10654
10655 static int
10656 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10657 {
10658         uint64_t ns;
10659         struct i40e_adapter *adapter = dev->data->dev_private;
10660
10661         ns = rte_timespec_to_ns(ts);
10662
10663         /* Set the timecounters to a new value. */
10664         adapter->systime_tc.nsec = ns;
10665         adapter->rx_tstamp_tc.nsec = ns;
10666         adapter->tx_tstamp_tc.nsec = ns;
10667
10668         return 0;
10669 }
10670
10671 static int
10672 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10673 {
10674         uint64_t ns, systime_cycles;
10675         struct i40e_adapter *adapter = dev->data->dev_private;
10676
10677         systime_cycles = i40e_read_systime_cyclecounter(dev);
10678         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10679         *ts = rte_ns_to_timespec(ns);
10680
10681         return 0;
10682 }
10683
10684 static int
10685 i40e_timesync_enable(struct rte_eth_dev *dev)
10686 {
10687         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10688         uint32_t tsync_ctl_l;
10689         uint32_t tsync_ctl_h;
10690
10691         /* Stop the timesync system time. */
10692         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10693         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10694         /* Reset the timesync system time value. */
10695         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10696         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10697
10698         i40e_start_timecounters(dev);
10699
10700         /* Clear timesync registers. */
10701         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10702         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10703         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10704         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10705         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10706         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10707
10708         /* Enable timestamping of PTP packets. */
10709         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10710         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10711
10712         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10713         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10714         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10715
10716         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10717         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10718
10719         return 0;
10720 }
10721
10722 static int
10723 i40e_timesync_disable(struct rte_eth_dev *dev)
10724 {
10725         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10726         uint32_t tsync_ctl_l;
10727         uint32_t tsync_ctl_h;
10728
10729         /* Disable timestamping of transmitted PTP packets. */
10730         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10731         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10732
10733         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10734         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10735
10736         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10737         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10738
10739         /* Reset the timesync increment value. */
10740         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10741         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10742
10743         return 0;
10744 }
10745
10746 static int
10747 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10748                                 struct timespec *timestamp, uint32_t flags)
10749 {
10750         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10751         struct i40e_adapter *adapter = dev->data->dev_private;
10752         uint32_t sync_status;
10753         uint32_t index = flags & 0x03;
10754         uint64_t rx_tstamp_cycles;
10755         uint64_t ns;
10756
10757         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10758         if ((sync_status & (1 << index)) == 0)
10759                 return -EINVAL;
10760
10761         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10762         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10763         *timestamp = rte_ns_to_timespec(ns);
10764
10765         return 0;
10766 }
10767
10768 static int
10769 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10770                                 struct timespec *timestamp)
10771 {
10772         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10773         struct i40e_adapter *adapter = dev->data->dev_private;
10774         uint32_t sync_status;
10775         uint64_t tx_tstamp_cycles;
10776         uint64_t ns;
10777
10778         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10779         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10780                 return -EINVAL;
10781
10782         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10783         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10784         *timestamp = rte_ns_to_timespec(ns);
10785
10786         return 0;
10787 }
10788
10789 /*
10790  * i40e_parse_dcb_configure - parse dcb configure from user
10791  * @dev: the device being configured
10792  * @dcb_cfg: pointer of the result of parse
10793  * @*tc_map: bit map of enabled traffic classes
10794  *
10795  * Returns 0 on success, negative value on failure
10796  */
10797 static int
10798 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10799                          struct i40e_dcbx_config *dcb_cfg,
10800                          uint8_t *tc_map)
10801 {
10802         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10803         uint8_t i, tc_bw, bw_lf;
10804
10805         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10806
10807         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10808         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10809                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10810                 return -EINVAL;
10811         }
10812
10813         /* assume each tc has the same bw */
10814         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10815         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10816                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10817         /* to ensure the sum of tcbw is equal to 100 */
10818         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10819         for (i = 0; i < bw_lf; i++)
10820                 dcb_cfg->etscfg.tcbwtable[i]++;
10821
10822         /* assume each tc has the same Transmission Selection Algorithm */
10823         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10824                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10825
10826         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10827                 dcb_cfg->etscfg.prioritytable[i] =
10828                                 dcb_rx_conf->dcb_tc[i];
10829
10830         /* FW needs one App to configure HW */
10831         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10832         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10833         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10834         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10835
10836         if (dcb_rx_conf->nb_tcs == 0)
10837                 *tc_map = 1; /* tc0 only */
10838         else
10839                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10840
10841         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10842                 dcb_cfg->pfc.willing = 0;
10843                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10844                 dcb_cfg->pfc.pfcenable = *tc_map;
10845         }
10846         return 0;
10847 }
10848
10849
10850 static enum i40e_status_code
10851 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10852                               struct i40e_aqc_vsi_properties_data *info,
10853                               uint8_t enabled_tcmap)
10854 {
10855         enum i40e_status_code ret;
10856         int i, total_tc = 0;
10857         uint16_t qpnum_per_tc, bsf, qp_idx;
10858         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10859         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10860         uint16_t used_queues;
10861
10862         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10863         if (ret != I40E_SUCCESS)
10864                 return ret;
10865
10866         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10867                 if (enabled_tcmap & (1 << i))
10868                         total_tc++;
10869         }
10870         if (total_tc == 0)
10871                 total_tc = 1;
10872         vsi->enabled_tc = enabled_tcmap;
10873
10874         /* different VSI has different queues assigned */
10875         if (vsi->type == I40E_VSI_MAIN)
10876                 used_queues = dev_data->nb_rx_queues -
10877                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10878         else if (vsi->type == I40E_VSI_VMDQ2)
10879                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10880         else {
10881                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10882                 return I40E_ERR_NO_AVAILABLE_VSI;
10883         }
10884
10885         qpnum_per_tc = used_queues / total_tc;
10886         /* Number of queues per enabled TC */
10887         if (qpnum_per_tc == 0) {
10888                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10889                 return I40E_ERR_INVALID_QP_ID;
10890         }
10891         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10892                                 I40E_MAX_Q_PER_TC);
10893         bsf = rte_bsf32(qpnum_per_tc);
10894
10895         /**
10896          * Configure TC and queue mapping parameters, for enabled TC,
10897          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10898          * default queue will serve it.
10899          */
10900         qp_idx = 0;
10901         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10902                 if (vsi->enabled_tc & (1 << i)) {
10903                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10904                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10905                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10906                         qp_idx += qpnum_per_tc;
10907                 } else
10908                         info->tc_mapping[i] = 0;
10909         }
10910
10911         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10912         if (vsi->type == I40E_VSI_SRIOV) {
10913                 info->mapping_flags |=
10914                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10915                 for (i = 0; i < vsi->nb_qps; i++)
10916                         info->queue_mapping[i] =
10917                                 rte_cpu_to_le_16(vsi->base_queue + i);
10918         } else {
10919                 info->mapping_flags |=
10920                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10921                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10922         }
10923         info->valid_sections |=
10924                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10925
10926         return I40E_SUCCESS;
10927 }
10928
10929 /*
10930  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10931  * @veb: VEB to be configured
10932  * @tc_map: enabled TC bitmap
10933  *
10934  * Returns 0 on success, negative value on failure
10935  */
10936 static enum i40e_status_code
10937 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10938 {
10939         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10940         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10941         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10942         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10943         enum i40e_status_code ret = I40E_SUCCESS;
10944         int i;
10945         uint32_t bw_max;
10946
10947         /* Check if enabled_tc is same as existing or new TCs */
10948         if (veb->enabled_tc == tc_map)
10949                 return ret;
10950
10951         /* configure tc bandwidth */
10952         memset(&veb_bw, 0, sizeof(veb_bw));
10953         veb_bw.tc_valid_bits = tc_map;
10954         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10955         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10956                 if (tc_map & BIT_ULL(i))
10957                         veb_bw.tc_bw_share_credits[i] = 1;
10958         }
10959         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10960                                                    &veb_bw, NULL);
10961         if (ret) {
10962                 PMD_INIT_LOG(ERR,
10963                         "AQ command Config switch_comp BW allocation per TC failed = %d",
10964                         hw->aq.asq_last_status);
10965                 return ret;
10966         }
10967
10968         memset(&ets_query, 0, sizeof(ets_query));
10969         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10970                                                    &ets_query, NULL);
10971         if (ret != I40E_SUCCESS) {
10972                 PMD_DRV_LOG(ERR,
10973                         "Failed to get switch_comp ETS configuration %u",
10974                         hw->aq.asq_last_status);
10975                 return ret;
10976         }
10977         memset(&bw_query, 0, sizeof(bw_query));
10978         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10979                                                   &bw_query, NULL);
10980         if (ret != I40E_SUCCESS) {
10981                 PMD_DRV_LOG(ERR,
10982                         "Failed to get switch_comp bandwidth configuration %u",
10983                         hw->aq.asq_last_status);
10984                 return ret;
10985         }
10986
10987         /* store and print out BW info */
10988         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10989         veb->bw_info.bw_max = ets_query.tc_bw_max;
10990         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10991         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10992         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10993                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10994                      I40E_16_BIT_WIDTH);
10995         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10996                 veb->bw_info.bw_ets_share_credits[i] =
10997                                 bw_query.tc_bw_share_credits[i];
10998                 veb->bw_info.bw_ets_credits[i] =
10999                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
11000                 /* 4 bits per TC, 4th bit is reserved */
11001                 veb->bw_info.bw_ets_max[i] =
11002                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
11003                                   RTE_LEN2MASK(3, uint8_t));
11004                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
11005                             veb->bw_info.bw_ets_share_credits[i]);
11006                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11007                             veb->bw_info.bw_ets_credits[i]);
11008                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11009                             veb->bw_info.bw_ets_max[i]);
11010         }
11011
11012         veb->enabled_tc = tc_map;
11013
11014         return ret;
11015 }
11016
11017
11018 /*
11019  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11020  * @vsi: VSI to be configured
11021  * @tc_map: enabled TC bitmap
11022  *
11023  * Returns 0 on success, negative value on failure
11024  */
11025 static enum i40e_status_code
11026 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11027 {
11028         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11029         struct i40e_vsi_context ctxt;
11030         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11031         enum i40e_status_code ret = I40E_SUCCESS;
11032         int i;
11033
11034         /* Check if enabled_tc is same as existing or new TCs */
11035         if (vsi->enabled_tc == tc_map)
11036                 return ret;
11037
11038         /* configure tc bandwidth */
11039         memset(&bw_data, 0, sizeof(bw_data));
11040         bw_data.tc_valid_bits = tc_map;
11041         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11042         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11043                 if (tc_map & BIT_ULL(i))
11044                         bw_data.tc_bw_credits[i] = 1;
11045         }
11046         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11047         if (ret) {
11048                 PMD_INIT_LOG(ERR,
11049                         "AQ command Config VSI BW allocation per TC failed = %d",
11050                         hw->aq.asq_last_status);
11051                 goto out;
11052         }
11053         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11054                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11055
11056         /* Update Queue Pairs Mapping for currently enabled UPs */
11057         ctxt.seid = vsi->seid;
11058         ctxt.pf_num = hw->pf_id;
11059         ctxt.vf_num = 0;
11060         ctxt.uplink_seid = vsi->uplink_seid;
11061         ctxt.info = vsi->info;
11062         i40e_get_cap(hw);
11063         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11064         if (ret)
11065                 goto out;
11066
11067         /* Update the VSI after updating the VSI queue-mapping information */
11068         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11069         if (ret) {
11070                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11071                         hw->aq.asq_last_status);
11072                 goto out;
11073         }
11074         /* update the local VSI info with updated queue map */
11075         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11076                                         sizeof(vsi->info.tc_mapping));
11077         rte_memcpy(&vsi->info.queue_mapping,
11078                         &ctxt.info.queue_mapping,
11079                 sizeof(vsi->info.queue_mapping));
11080         vsi->info.mapping_flags = ctxt.info.mapping_flags;
11081         vsi->info.valid_sections = 0;
11082
11083         /* query and update current VSI BW information */
11084         ret = i40e_vsi_get_bw_config(vsi);
11085         if (ret) {
11086                 PMD_INIT_LOG(ERR,
11087                          "Failed updating vsi bw info, err %s aq_err %s",
11088                          i40e_stat_str(hw, ret),
11089                          i40e_aq_str(hw, hw->aq.asq_last_status));
11090                 goto out;
11091         }
11092
11093         vsi->enabled_tc = tc_map;
11094
11095 out:
11096         return ret;
11097 }
11098
11099 /*
11100  * i40e_dcb_hw_configure - program the dcb setting to hw
11101  * @pf: pf the configuration is taken on
11102  * @new_cfg: new configuration
11103  * @tc_map: enabled TC bitmap
11104  *
11105  * Returns 0 on success, negative value on failure
11106  */
11107 static enum i40e_status_code
11108 i40e_dcb_hw_configure(struct i40e_pf *pf,
11109                       struct i40e_dcbx_config *new_cfg,
11110                       uint8_t tc_map)
11111 {
11112         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11113         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11114         struct i40e_vsi *main_vsi = pf->main_vsi;
11115         struct i40e_vsi_list *vsi_list;
11116         enum i40e_status_code ret;
11117         int i;
11118         uint32_t val;
11119
11120         /* Use the FW API if FW > v4.4*/
11121         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11122               (hw->aq.fw_maj_ver >= 5))) {
11123                 PMD_INIT_LOG(ERR,
11124                         "FW < v4.4, can not use FW LLDP API to configure DCB");
11125                 return I40E_ERR_FIRMWARE_API_VERSION;
11126         }
11127
11128         /* Check if need reconfiguration */
11129         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11130                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11131                 return I40E_SUCCESS;
11132         }
11133
11134         /* Copy the new config to the current config */
11135         *old_cfg = *new_cfg;
11136         old_cfg->etsrec = old_cfg->etscfg;
11137         ret = i40e_set_dcb_config(hw);
11138         if (ret) {
11139                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11140                          i40e_stat_str(hw, ret),
11141                          i40e_aq_str(hw, hw->aq.asq_last_status));
11142                 return ret;
11143         }
11144         /* set receive Arbiter to RR mode and ETS scheme by default */
11145         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11146                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11147                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
11148                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11149                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11150                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11151                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11152                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11153                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11154                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11155                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11156                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11157                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11158         }
11159         /* get local mib to check whether it is configured correctly */
11160         /* IEEE mode */
11161         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11162         /* Get Local DCB Config */
11163         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11164                                      &hw->local_dcbx_config);
11165
11166         /* if Veb is created, need to update TC of it at first */
11167         if (main_vsi->veb) {
11168                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11169                 if (ret)
11170                         PMD_INIT_LOG(WARNING,
11171                                  "Failed configuring TC for VEB seid=%d",
11172                                  main_vsi->veb->seid);
11173         }
11174         /* Update each VSI */
11175         i40e_vsi_config_tc(main_vsi, tc_map);
11176         if (main_vsi->veb) {
11177                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11178                         /* Beside main VSI and VMDQ VSIs, only enable default
11179                          * TC for other VSIs
11180                          */
11181                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11182                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11183                                                          tc_map);
11184                         else
11185                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11186                                                          I40E_DEFAULT_TCMAP);
11187                         if (ret)
11188                                 PMD_INIT_LOG(WARNING,
11189                                         "Failed configuring TC for VSI seid=%d",
11190                                         vsi_list->vsi->seid);
11191                         /* continue */
11192                 }
11193         }
11194         return I40E_SUCCESS;
11195 }
11196
11197 /*
11198  * i40e_dcb_init_configure - initial dcb config
11199  * @dev: device being configured
11200  * @sw_dcb: indicate whether dcb is sw configured or hw offload
11201  *
11202  * Returns 0 on success, negative value on failure
11203  */
11204 int
11205 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11206 {
11207         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11208         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11209         int i, ret = 0;
11210
11211         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11212                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11213                 return -ENOTSUP;
11214         }
11215
11216         /* DCB initialization:
11217          * Update DCB configuration from the Firmware and configure
11218          * LLDP MIB change event.
11219          */
11220         if (sw_dcb == TRUE) {
11221                 /* Stopping lldp is necessary for DPDK, but it will cause
11222                  * DCB init failed. For i40e_init_dcb(), the prerequisite
11223                  * for successful initialization of DCB is that LLDP is
11224                  * enabled. So it is needed to start lldp before DCB init
11225                  * and stop it after initialization.
11226                  */
11227                 ret = i40e_aq_start_lldp(hw, true, NULL);
11228                 if (ret != I40E_SUCCESS)
11229                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11230
11231                 ret = i40e_init_dcb(hw, true);
11232                 /* If lldp agent is stopped, the return value from
11233                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11234                  * adminq status. Otherwise, it should return success.
11235                  */
11236                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11237                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11238                         memset(&hw->local_dcbx_config, 0,
11239                                 sizeof(struct i40e_dcbx_config));
11240                         /* set dcb default configuration */
11241                         hw->local_dcbx_config.etscfg.willing = 0;
11242                         hw->local_dcbx_config.etscfg.maxtcs = 0;
11243                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11244                         hw->local_dcbx_config.etscfg.tsatable[0] =
11245                                                 I40E_IEEE_TSA_ETS;
11246                         /* all UPs mapping to TC0 */
11247                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11248                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11249                         hw->local_dcbx_config.etsrec =
11250                                 hw->local_dcbx_config.etscfg;
11251                         hw->local_dcbx_config.pfc.willing = 0;
11252                         hw->local_dcbx_config.pfc.pfccap =
11253                                                 I40E_MAX_TRAFFIC_CLASS;
11254                         /* FW needs one App to configure HW */
11255                         hw->local_dcbx_config.numapps = 1;
11256                         hw->local_dcbx_config.app[0].selector =
11257                                                 I40E_APP_SEL_ETHTYPE;
11258                         hw->local_dcbx_config.app[0].priority = 3;
11259                         hw->local_dcbx_config.app[0].protocolid =
11260                                                 I40E_APP_PROTOID_FCOE;
11261                         ret = i40e_set_dcb_config(hw);
11262                         if (ret) {
11263                                 PMD_INIT_LOG(ERR,
11264                                         "default dcb config fails. err = %d, aq_err = %d.",
11265                                         ret, hw->aq.asq_last_status);
11266                                 return -ENOSYS;
11267                         }
11268                 } else {
11269                         PMD_INIT_LOG(ERR,
11270                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11271                                 ret, hw->aq.asq_last_status);
11272                         return -ENOTSUP;
11273                 }
11274
11275                 if (i40e_need_stop_lldp(dev)) {
11276                         ret = i40e_aq_stop_lldp(hw, true, true, NULL);
11277                         if (ret != I40E_SUCCESS)
11278                                 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
11279                 }
11280         } else {
11281                 ret = i40e_aq_start_lldp(hw, true, NULL);
11282                 if (ret != I40E_SUCCESS)
11283                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11284
11285                 ret = i40e_init_dcb(hw, true);
11286                 if (!ret) {
11287                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11288                                 PMD_INIT_LOG(ERR,
11289                                         "HW doesn't support DCBX offload.");
11290                                 return -ENOTSUP;
11291                         }
11292                 } else {
11293                         PMD_INIT_LOG(ERR,
11294                                 "DCBX configuration failed, err = %d, aq_err = %d.",
11295                                 ret, hw->aq.asq_last_status);
11296                         return -ENOTSUP;
11297                 }
11298         }
11299         return 0;
11300 }
11301
11302 /*
11303  * i40e_dcb_setup - setup dcb related config
11304  * @dev: device being configured
11305  *
11306  * Returns 0 on success, negative value on failure
11307  */
11308 static int
11309 i40e_dcb_setup(struct rte_eth_dev *dev)
11310 {
11311         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11312         struct i40e_dcbx_config dcb_cfg;
11313         uint8_t tc_map = 0;
11314         int ret = 0;
11315
11316         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11317                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11318                 return -ENOTSUP;
11319         }
11320
11321         if (pf->vf_num != 0)
11322                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11323
11324         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11325         if (ret) {
11326                 PMD_INIT_LOG(ERR, "invalid dcb config");
11327                 return -EINVAL;
11328         }
11329         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11330         if (ret) {
11331                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11332                 return -ENOSYS;
11333         }
11334
11335         return 0;
11336 }
11337
11338 static int
11339 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11340                       struct rte_eth_dcb_info *dcb_info)
11341 {
11342         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11343         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11344         struct i40e_vsi *vsi = pf->main_vsi;
11345         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11346         uint16_t bsf, tc_mapping;
11347         int i, j = 0;
11348
11349         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11350                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11351         else
11352                 dcb_info->nb_tcs = 1;
11353         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11354                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11355         for (i = 0; i < dcb_info->nb_tcs; i++)
11356                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11357
11358         /* get queue mapping if vmdq is disabled */
11359         if (!pf->nb_cfg_vmdq_vsi) {
11360                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11361                         if (!(vsi->enabled_tc & (1 << i)))
11362                                 continue;
11363                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11364                         dcb_info->tc_queue.tc_rxq[j][i].base =
11365                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11366                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11367                         dcb_info->tc_queue.tc_txq[j][i].base =
11368                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11369                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11370                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11371                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11372                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11373                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11374                 }
11375                 return 0;
11376         }
11377
11378         /* get queue mapping if vmdq is enabled */
11379         do {
11380                 vsi = pf->vmdq[j].vsi;
11381                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11382                         if (!(vsi->enabled_tc & (1 << i)))
11383                                 continue;
11384                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11385                         dcb_info->tc_queue.tc_rxq[j][i].base =
11386                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11387                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11388                         dcb_info->tc_queue.tc_txq[j][i].base =
11389                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11390                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11391                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11392                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11393                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11394                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11395                 }
11396                 j++;
11397         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11398         return 0;
11399 }
11400
11401 static int
11402 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11403 {
11404         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11405         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11406         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11407         uint16_t msix_intr;
11408
11409         msix_intr = intr_handle->intr_vec[queue_id];
11410         if (msix_intr == I40E_MISC_VEC_ID)
11411                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11412                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
11413                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11414                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11415         else
11416                 I40E_WRITE_REG(hw,
11417                                I40E_PFINT_DYN_CTLN(msix_intr -
11418                                                    I40E_RX_VEC_START),
11419                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
11420                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11421                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11422
11423         I40E_WRITE_FLUSH(hw);
11424         rte_intr_ack(&pci_dev->intr_handle);
11425
11426         return 0;
11427 }
11428
11429 static int
11430 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11431 {
11432         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11433         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11434         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11435         uint16_t msix_intr;
11436
11437         msix_intr = intr_handle->intr_vec[queue_id];
11438         if (msix_intr == I40E_MISC_VEC_ID)
11439                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11440                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11441         else
11442                 I40E_WRITE_REG(hw,
11443                                I40E_PFINT_DYN_CTLN(msix_intr -
11444                                                    I40E_RX_VEC_START),
11445                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11446         I40E_WRITE_FLUSH(hw);
11447
11448         return 0;
11449 }
11450
11451 /**
11452  * This function is used to check if the register is valid.
11453  * Below is the valid registers list for X722 only:
11454  * 0x2b800--0x2bb00
11455  * 0x38700--0x38a00
11456  * 0x3d800--0x3db00
11457  * 0x208e00--0x209000
11458  * 0x20be00--0x20c000
11459  * 0x263c00--0x264000
11460  * 0x265c00--0x266000
11461  */
11462 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset)
11463 {
11464         if ((type != I40E_MAC_X722) &&
11465             ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) ||
11466              (reg_offset >= 0x38700 && reg_offset <= 0x38a00) ||
11467              (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) ||
11468              (reg_offset >= 0x208e00 && reg_offset <= 0x209000) ||
11469              (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) ||
11470              (reg_offset >= 0x263c00 && reg_offset <= 0x264000) ||
11471              (reg_offset >= 0x265c00 && reg_offset <= 0x266000)))
11472                 return 0;
11473         else
11474                 return 1;
11475 }
11476
11477 static int i40e_get_regs(struct rte_eth_dev *dev,
11478                          struct rte_dev_reg_info *regs)
11479 {
11480         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11481         uint32_t *ptr_data = regs->data;
11482         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11483         const struct i40e_reg_info *reg_info;
11484
11485         if (ptr_data == NULL) {
11486                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11487                 regs->width = sizeof(uint32_t);
11488                 return 0;
11489         }
11490
11491         /* The first few registers have to be read using AQ operations */
11492         reg_idx = 0;
11493         while (i40e_regs_adminq[reg_idx].name) {
11494                 reg_info = &i40e_regs_adminq[reg_idx++];
11495                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11496                         for (arr_idx2 = 0;
11497                                         arr_idx2 <= reg_info->count2;
11498                                         arr_idx2++) {
11499                                 reg_offset = arr_idx * reg_info->stride1 +
11500                                         arr_idx2 * reg_info->stride2;
11501                                 reg_offset += reg_info->base_addr;
11502                                 ptr_data[reg_offset >> 2] =
11503                                         i40e_read_rx_ctl(hw, reg_offset);
11504                         }
11505         }
11506
11507         /* The remaining registers can be read using primitives */
11508         reg_idx = 0;
11509         while (i40e_regs_others[reg_idx].name) {
11510                 reg_info = &i40e_regs_others[reg_idx++];
11511                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11512                         for (arr_idx2 = 0;
11513                                         arr_idx2 <= reg_info->count2;
11514                                         arr_idx2++) {
11515                                 reg_offset = arr_idx * reg_info->stride1 +
11516                                         arr_idx2 * reg_info->stride2;
11517                                 reg_offset += reg_info->base_addr;
11518                                 if (!i40e_valid_regs(hw->mac.type, reg_offset))
11519                                         ptr_data[reg_offset >> 2] = 0;
11520                                 else
11521                                         ptr_data[reg_offset >> 2] =
11522                                                 I40E_READ_REG(hw, reg_offset);
11523                         }
11524         }
11525
11526         return 0;
11527 }
11528
11529 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11530 {
11531         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11532
11533         /* Convert word count to byte count */
11534         return hw->nvm.sr_size << 1;
11535 }
11536
11537 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11538                            struct rte_dev_eeprom_info *eeprom)
11539 {
11540         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11541         uint16_t *data = eeprom->data;
11542         uint16_t offset, length, cnt_words;
11543         int ret_code;
11544
11545         offset = eeprom->offset >> 1;
11546         length = eeprom->length >> 1;
11547         cnt_words = length;
11548
11549         if (offset > hw->nvm.sr_size ||
11550                 offset + length > hw->nvm.sr_size) {
11551                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11552                 return -EINVAL;
11553         }
11554
11555         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11556
11557         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11558         if (ret_code != I40E_SUCCESS || cnt_words != length) {
11559                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11560                 return -EIO;
11561         }
11562
11563         return 0;
11564 }
11565
11566 static int i40e_get_module_info(struct rte_eth_dev *dev,
11567                                 struct rte_eth_dev_module_info *modinfo)
11568 {
11569         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11570         uint32_t sff8472_comp = 0;
11571         uint32_t sff8472_swap = 0;
11572         uint32_t sff8636_rev = 0;
11573         i40e_status status;
11574         uint32_t type = 0;
11575
11576         /* Check if firmware supports reading module EEPROM. */
11577         if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
11578                 PMD_DRV_LOG(ERR,
11579                             "Module EEPROM memory read not supported. "
11580                             "Please update the NVM image.\n");
11581                 return -EINVAL;
11582         }
11583
11584         status = i40e_update_link_info(hw);
11585         if (status)
11586                 return -EIO;
11587
11588         if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
11589                 PMD_DRV_LOG(ERR,
11590                             "Cannot read module EEPROM memory. "
11591                             "No module connected.\n");
11592                 return -EINVAL;
11593         }
11594
11595         type = hw->phy.link_info.module_type[0];
11596
11597         switch (type) {
11598         case I40E_MODULE_TYPE_SFP:
11599                 status = i40e_aq_get_phy_register(hw,
11600                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11601                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
11602                                 I40E_MODULE_SFF_8472_COMP,
11603                                 &sff8472_comp, NULL);
11604                 if (status)
11605                         return -EIO;
11606
11607                 status = i40e_aq_get_phy_register(hw,
11608                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11609                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
11610                                 I40E_MODULE_SFF_8472_SWAP,
11611                                 &sff8472_swap, NULL);
11612                 if (status)
11613                         return -EIO;
11614
11615                 /* Check if the module requires address swap to access
11616                  * the other EEPROM memory page.
11617                  */
11618                 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
11619                         PMD_DRV_LOG(WARNING,
11620                                     "Module address swap to access "
11621                                     "page 0xA2 is not supported.\n");
11622                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
11623                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11624                 } else if (sff8472_comp == 0x00) {
11625                         /* Module is not SFF-8472 compliant */
11626                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
11627                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11628                 } else {
11629                         modinfo->type = RTE_ETH_MODULE_SFF_8472;
11630                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
11631                 }
11632                 break;
11633         case I40E_MODULE_TYPE_QSFP_PLUS:
11634                 /* Read from memory page 0. */
11635                 status = i40e_aq_get_phy_register(hw,
11636                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11637                                 0, 1,
11638                                 I40E_MODULE_REVISION_ADDR,
11639                                 &sff8636_rev, NULL);
11640                 if (status)
11641                         return -EIO;
11642                 /* Determine revision compliance byte */
11643                 if (sff8636_rev > 0x02) {
11644                         /* Module is SFF-8636 compliant */
11645                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
11646                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11647                 } else {
11648                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
11649                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11650                 }
11651                 break;
11652         case I40E_MODULE_TYPE_QSFP28:
11653                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11654                 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11655                 break;
11656         default:
11657                 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
11658                 return -EINVAL;
11659         }
11660         return 0;
11661 }
11662
11663 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
11664                                   struct rte_dev_eeprom_info *info)
11665 {
11666         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11667         bool is_sfp = false;
11668         i40e_status status;
11669         uint8_t *data;
11670         uint32_t value = 0;
11671         uint32_t i;
11672
11673         if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
11674                 is_sfp = true;
11675
11676         data = info->data;
11677         for (i = 0; i < info->length; i++) {
11678                 u32 offset = i + info->offset;
11679                 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
11680
11681                 /* Check if we need to access the other memory page */
11682                 if (is_sfp) {
11683                         if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
11684                                 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
11685                                 addr = I40E_I2C_EEPROM_DEV_ADDR2;
11686                         }
11687                 } else {
11688                         while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
11689                                 /* Compute memory page number and offset. */
11690                                 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
11691                                 addr++;
11692                         }
11693                 }
11694                 status = i40e_aq_get_phy_register(hw,
11695                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11696                                 addr, 1, offset, &value, NULL);
11697                 if (status)
11698                         return -EIO;
11699                 data[i] = (uint8_t)value;
11700         }
11701         return 0;
11702 }
11703
11704 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11705                                      struct rte_ether_addr *mac_addr)
11706 {
11707         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11708         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11709         struct i40e_vsi *vsi = pf->main_vsi;
11710         struct i40e_mac_filter_info mac_filter;
11711         struct i40e_mac_filter *f;
11712         int ret;
11713
11714         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
11715                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11716                 return -EINVAL;
11717         }
11718
11719         TAILQ_FOREACH(f, &vsi->mac_list, next) {
11720                 if (rte_is_same_ether_addr(&pf->dev_addr,
11721                                                 &f->mac_info.mac_addr))
11722                         break;
11723         }
11724
11725         if (f == NULL) {
11726                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11727                 return -EIO;
11728         }
11729
11730         mac_filter = f->mac_info;
11731         ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11732         if (ret != I40E_SUCCESS) {
11733                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11734                 return -EIO;
11735         }
11736         memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11737         ret = i40e_vsi_add_mac(vsi, &mac_filter);
11738         if (ret != I40E_SUCCESS) {
11739                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11740                 return -EIO;
11741         }
11742         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11743
11744         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11745                                         mac_addr->addr_bytes, NULL);
11746         if (ret != I40E_SUCCESS) {
11747                 PMD_DRV_LOG(ERR, "Failed to change mac");
11748                 return -EIO;
11749         }
11750
11751         return 0;
11752 }
11753
11754 static int
11755 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
11756 {
11757         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11758         struct rte_eth_dev_data *dev_data = pf->dev_data;
11759         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
11760         int ret = 0;
11761
11762         /* check if mtu is within the allowed range */
11763         if (mtu < RTE_ETHER_MIN_MTU || frame_size > I40E_FRAME_SIZE_MAX)
11764                 return -EINVAL;
11765
11766         /* mtu setting is forbidden if port is start */
11767         if (dev_data->dev_started) {
11768                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
11769                             dev_data->port_id);
11770                 return -EBUSY;
11771         }
11772
11773         if (frame_size > I40E_ETH_MAX_LEN)
11774                 dev_data->dev_conf.rxmode.offloads |=
11775                         DEV_RX_OFFLOAD_JUMBO_FRAME;
11776         else
11777                 dev_data->dev_conf.rxmode.offloads &=
11778                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
11779
11780         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
11781
11782         return ret;
11783 }
11784
11785 /* Restore ethertype filter */
11786 static void
11787 i40e_ethertype_filter_restore(struct i40e_pf *pf)
11788 {
11789         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11790         struct i40e_ethertype_filter_list
11791                 *ethertype_list = &pf->ethertype.ethertype_list;
11792         struct i40e_ethertype_filter *f;
11793         struct i40e_control_filter_stats stats;
11794         uint16_t flags;
11795
11796         TAILQ_FOREACH(f, ethertype_list, rules) {
11797                 flags = 0;
11798                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
11799                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
11800                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
11801                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
11802                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
11803
11804                 memset(&stats, 0, sizeof(stats));
11805                 i40e_aq_add_rem_control_packet_filter(hw,
11806                                             f->input.mac_addr.addr_bytes,
11807                                             f->input.ether_type,
11808                                             flags, pf->main_vsi->seid,
11809                                             f->queue, 1, &stats, NULL);
11810         }
11811         PMD_DRV_LOG(INFO, "Ethertype filter:"
11812                     " mac_etype_used = %u, etype_used = %u,"
11813                     " mac_etype_free = %u, etype_free = %u",
11814                     stats.mac_etype_used, stats.etype_used,
11815                     stats.mac_etype_free, stats.etype_free);
11816 }
11817
11818 /* Restore tunnel filter */
11819 static void
11820 i40e_tunnel_filter_restore(struct i40e_pf *pf)
11821 {
11822         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11823         struct i40e_vsi *vsi;
11824         struct i40e_pf_vf *vf;
11825         struct i40e_tunnel_filter_list
11826                 *tunnel_list = &pf->tunnel.tunnel_list;
11827         struct i40e_tunnel_filter *f;
11828         struct i40e_aqc_cloud_filters_element_bb cld_filter;
11829         bool big_buffer = 0;
11830
11831         TAILQ_FOREACH(f, tunnel_list, rules) {
11832                 if (!f->is_to_vf)
11833                         vsi = pf->main_vsi;
11834                 else {
11835                         vf = &pf->vfs[f->vf_id];
11836                         vsi = vf->vsi;
11837                 }
11838                 memset(&cld_filter, 0, sizeof(cld_filter));
11839                 rte_ether_addr_copy((struct rte_ether_addr *)
11840                                 &f->input.outer_mac,
11841                         (struct rte_ether_addr *)&cld_filter.element.outer_mac);
11842                 rte_ether_addr_copy((struct rte_ether_addr *)
11843                                 &f->input.inner_mac,
11844                         (struct rte_ether_addr *)&cld_filter.element.inner_mac);
11845                 cld_filter.element.inner_vlan = f->input.inner_vlan;
11846                 cld_filter.element.flags = f->input.flags;
11847                 cld_filter.element.tenant_id = f->input.tenant_id;
11848                 cld_filter.element.queue_number = f->queue;
11849                 rte_memcpy(cld_filter.general_fields,
11850                            f->input.general_fields,
11851                            sizeof(f->input.general_fields));
11852
11853                 if (((f->input.flags &
11854                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
11855                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
11856                     ((f->input.flags &
11857                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
11858                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
11859                     ((f->input.flags &
11860                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
11861                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
11862                         big_buffer = 1;
11863
11864                 if (big_buffer)
11865                         i40e_aq_add_cloud_filters_bb(hw,
11866                                         vsi->seid, &cld_filter, 1);
11867                 else
11868                         i40e_aq_add_cloud_filters(hw, vsi->seid,
11869                                                   &cld_filter.element, 1);
11870         }
11871 }
11872
11873 static void
11874 i40e_filter_restore(struct i40e_pf *pf)
11875 {
11876         i40e_ethertype_filter_restore(pf);
11877         i40e_tunnel_filter_restore(pf);
11878         i40e_fdir_filter_restore(pf);
11879         (void)i40e_hash_filter_restore(pf);
11880 }
11881
11882 bool
11883 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
11884 {
11885         if (strcmp(dev->device->driver->name, drv->driver.name))
11886                 return false;
11887
11888         return true;
11889 }
11890
11891 bool
11892 is_i40e_supported(struct rte_eth_dev *dev)
11893 {
11894         return is_device_supported(dev, &rte_i40e_pmd);
11895 }
11896
11897 struct i40e_customized_pctype*
11898 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
11899 {
11900         int i;
11901
11902         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
11903                 if (pf->customized_pctype[i].index == index)
11904                         return &pf->customized_pctype[i];
11905         }
11906         return NULL;
11907 }
11908
11909 static int
11910 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
11911                               uint32_t pkg_size, uint32_t proto_num,
11912                               struct rte_pmd_i40e_proto_info *proto,
11913                               enum rte_pmd_i40e_package_op op)
11914 {
11915         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11916         uint32_t pctype_num;
11917         struct rte_pmd_i40e_ptype_info *pctype;
11918         uint32_t buff_size;
11919         struct i40e_customized_pctype *new_pctype = NULL;
11920         uint8_t proto_id;
11921         uint8_t pctype_value;
11922         char name[64];
11923         uint32_t i, j, n;
11924         int ret;
11925
11926         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11927             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11928                 PMD_DRV_LOG(ERR, "Unsupported operation.");
11929                 return -1;
11930         }
11931
11932         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11933                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
11934                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
11935         if (ret) {
11936                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
11937                 return -1;
11938         }
11939         if (!pctype_num) {
11940                 PMD_DRV_LOG(INFO, "No new pctype added");
11941                 return -1;
11942         }
11943
11944         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
11945         pctype = rte_zmalloc("new_pctype", buff_size, 0);
11946         if (!pctype) {
11947                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11948                 return -1;
11949         }
11950         /* get information about new pctype list */
11951         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11952                                         (uint8_t *)pctype, buff_size,
11953                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
11954         if (ret) {
11955                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
11956                 rte_free(pctype);
11957                 return -1;
11958         }
11959
11960         /* Update customized pctype. */
11961         for (i = 0; i < pctype_num; i++) {
11962                 pctype_value = pctype[i].ptype_id;
11963                 memset(name, 0, sizeof(name));
11964                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11965                         proto_id = pctype[i].protocols[j];
11966                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11967                                 continue;
11968                         for (n = 0; n < proto_num; n++) {
11969                                 if (proto[n].proto_id != proto_id)
11970                                         continue;
11971                                 strlcat(name, proto[n].name, sizeof(name));
11972                                 strlcat(name, "_", sizeof(name));
11973                                 break;
11974                         }
11975                 }
11976                 name[strlen(name) - 1] = '\0';
11977                 PMD_DRV_LOG(INFO, "name = %s\n", name);
11978                 if (!strcmp(name, "GTPC"))
11979                         new_pctype =
11980                                 i40e_find_customized_pctype(pf,
11981                                                       I40E_CUSTOMIZED_GTPC);
11982                 else if (!strcmp(name, "GTPU_IPV4"))
11983                         new_pctype =
11984                                 i40e_find_customized_pctype(pf,
11985                                                    I40E_CUSTOMIZED_GTPU_IPV4);
11986                 else if (!strcmp(name, "GTPU_IPV6"))
11987                         new_pctype =
11988                                 i40e_find_customized_pctype(pf,
11989                                                    I40E_CUSTOMIZED_GTPU_IPV6);
11990                 else if (!strcmp(name, "GTPU"))
11991                         new_pctype =
11992                                 i40e_find_customized_pctype(pf,
11993                                                       I40E_CUSTOMIZED_GTPU);
11994                 else if (!strcmp(name, "IPV4_L2TPV3"))
11995                         new_pctype =
11996                                 i40e_find_customized_pctype(pf,
11997                                                 I40E_CUSTOMIZED_IPV4_L2TPV3);
11998                 else if (!strcmp(name, "IPV6_L2TPV3"))
11999                         new_pctype =
12000                                 i40e_find_customized_pctype(pf,
12001                                                 I40E_CUSTOMIZED_IPV6_L2TPV3);
12002                 else if (!strcmp(name, "IPV4_ESP"))
12003                         new_pctype =
12004                                 i40e_find_customized_pctype(pf,
12005                                                 I40E_CUSTOMIZED_ESP_IPV4);
12006                 else if (!strcmp(name, "IPV6_ESP"))
12007                         new_pctype =
12008                                 i40e_find_customized_pctype(pf,
12009                                                 I40E_CUSTOMIZED_ESP_IPV6);
12010                 else if (!strcmp(name, "IPV4_UDP_ESP"))
12011                         new_pctype =
12012                                 i40e_find_customized_pctype(pf,
12013                                                 I40E_CUSTOMIZED_ESP_IPV4_UDP);
12014                 else if (!strcmp(name, "IPV6_UDP_ESP"))
12015                         new_pctype =
12016                                 i40e_find_customized_pctype(pf,
12017                                                 I40E_CUSTOMIZED_ESP_IPV6_UDP);
12018                 else if (!strcmp(name, "IPV4_AH"))
12019                         new_pctype =
12020                                 i40e_find_customized_pctype(pf,
12021                                                 I40E_CUSTOMIZED_AH_IPV4);
12022                 else if (!strcmp(name, "IPV6_AH"))
12023                         new_pctype =
12024                                 i40e_find_customized_pctype(pf,
12025                                                 I40E_CUSTOMIZED_AH_IPV6);
12026                 if (new_pctype) {
12027                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12028                                 new_pctype->pctype = pctype_value;
12029                                 new_pctype->valid = true;
12030                         } else {
12031                                 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
12032                                 new_pctype->valid = false;
12033                         }
12034                 }
12035         }
12036
12037         rte_free(pctype);
12038         return 0;
12039 }
12040
12041 static int
12042 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
12043                              uint32_t pkg_size, uint32_t proto_num,
12044                              struct rte_pmd_i40e_proto_info *proto,
12045                              enum rte_pmd_i40e_package_op op)
12046 {
12047         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
12048         uint16_t port_id = dev->data->port_id;
12049         uint32_t ptype_num;
12050         struct rte_pmd_i40e_ptype_info *ptype;
12051         uint32_t buff_size;
12052         uint8_t proto_id;
12053         char name[RTE_PMD_I40E_DDP_NAME_SIZE];
12054         uint32_t i, j, n;
12055         bool in_tunnel;
12056         int ret;
12057
12058         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12059             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12060                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12061                 return -1;
12062         }
12063
12064         if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
12065                 rte_pmd_i40e_ptype_mapping_reset(port_id);
12066                 return 0;
12067         }
12068
12069         /* get information about new ptype num */
12070         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12071                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
12072                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12073         if (ret) {
12074                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12075                 return ret;
12076         }
12077         if (!ptype_num) {
12078                 PMD_DRV_LOG(INFO, "No new ptype added");
12079                 return -1;
12080         }
12081
12082         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12083         ptype = rte_zmalloc("new_ptype", buff_size, 0);
12084         if (!ptype) {
12085                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12086                 return -1;
12087         }
12088
12089         /* get information about new ptype list */
12090         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12091                                         (uint8_t *)ptype, buff_size,
12092                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12093         if (ret) {
12094                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12095                 rte_free(ptype);
12096                 return ret;
12097         }
12098
12099         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12100         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12101         if (!ptype_mapping) {
12102                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12103                 rte_free(ptype);
12104                 return -1;
12105         }
12106
12107         /* Update ptype mapping table. */
12108         for (i = 0; i < ptype_num; i++) {
12109                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12110                 ptype_mapping[i].sw_ptype = 0;
12111                 in_tunnel = false;
12112                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12113                         proto_id = ptype[i].protocols[j];
12114                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12115                                 continue;
12116                         for (n = 0; n < proto_num; n++) {
12117                                 if (proto[n].proto_id != proto_id)
12118                                         continue;
12119                                 memset(name, 0, sizeof(name));
12120                                 strcpy(name, proto[n].name);
12121                                 PMD_DRV_LOG(INFO, "name = %s\n", name);
12122                                 if (!strncasecmp(name, "PPPOE", 5))
12123                                         ptype_mapping[i].sw_ptype |=
12124                                                 RTE_PTYPE_L2_ETHER_PPPOE;
12125                                 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12126                                          !in_tunnel) {
12127                                         ptype_mapping[i].sw_ptype |=
12128                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12129                                         ptype_mapping[i].sw_ptype |=
12130                                                 RTE_PTYPE_L4_FRAG;
12131                                 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12132                                            in_tunnel) {
12133                                         ptype_mapping[i].sw_ptype |=
12134                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12135                                         ptype_mapping[i].sw_ptype |=
12136                                                 RTE_PTYPE_INNER_L4_FRAG;
12137                                 } else if (!strncasecmp(name, "OIPV4", 5)) {
12138                                         ptype_mapping[i].sw_ptype |=
12139                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12140                                         in_tunnel = true;
12141                                 } else if (!strncasecmp(name, "IPV4", 4) &&
12142                                            !in_tunnel)
12143                                         ptype_mapping[i].sw_ptype |=
12144                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12145                                 else if (!strncasecmp(name, "IPV4", 4) &&
12146                                          in_tunnel)
12147                                         ptype_mapping[i].sw_ptype |=
12148                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12149                                 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12150                                          !in_tunnel) {
12151                                         ptype_mapping[i].sw_ptype |=
12152                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12153                                         ptype_mapping[i].sw_ptype |=
12154                                                 RTE_PTYPE_L4_FRAG;
12155                                 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12156                                            in_tunnel) {
12157                                         ptype_mapping[i].sw_ptype |=
12158                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12159                                         ptype_mapping[i].sw_ptype |=
12160                                                 RTE_PTYPE_INNER_L4_FRAG;
12161                                 } else if (!strncasecmp(name, "OIPV6", 5)) {
12162                                         ptype_mapping[i].sw_ptype |=
12163                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12164                                         in_tunnel = true;
12165                                 } else if (!strncasecmp(name, "IPV6", 4) &&
12166                                            !in_tunnel)
12167                                         ptype_mapping[i].sw_ptype |=
12168                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12169                                 else if (!strncasecmp(name, "IPV6", 4) &&
12170                                          in_tunnel)
12171                                         ptype_mapping[i].sw_ptype |=
12172                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12173                                 else if (!strncasecmp(name, "UDP", 3) &&
12174                                          !in_tunnel)
12175                                         ptype_mapping[i].sw_ptype |=
12176                                                 RTE_PTYPE_L4_UDP;
12177                                 else if (!strncasecmp(name, "UDP", 3) &&
12178                                          in_tunnel)
12179                                         ptype_mapping[i].sw_ptype |=
12180                                                 RTE_PTYPE_INNER_L4_UDP;
12181                                 else if (!strncasecmp(name, "TCP", 3) &&
12182                                          !in_tunnel)
12183                                         ptype_mapping[i].sw_ptype |=
12184                                                 RTE_PTYPE_L4_TCP;
12185                                 else if (!strncasecmp(name, "TCP", 3) &&
12186                                          in_tunnel)
12187                                         ptype_mapping[i].sw_ptype |=
12188                                                 RTE_PTYPE_INNER_L4_TCP;
12189                                 else if (!strncasecmp(name, "SCTP", 4) &&
12190                                          !in_tunnel)
12191                                         ptype_mapping[i].sw_ptype |=
12192                                                 RTE_PTYPE_L4_SCTP;
12193                                 else if (!strncasecmp(name, "SCTP", 4) &&
12194                                          in_tunnel)
12195                                         ptype_mapping[i].sw_ptype |=
12196                                                 RTE_PTYPE_INNER_L4_SCTP;
12197                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12198                                           !strncasecmp(name, "ICMPV6", 6)) &&
12199                                          !in_tunnel)
12200                                         ptype_mapping[i].sw_ptype |=
12201                                                 RTE_PTYPE_L4_ICMP;
12202                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12203                                           !strncasecmp(name, "ICMPV6", 6)) &&
12204                                          in_tunnel)
12205                                         ptype_mapping[i].sw_ptype |=
12206                                                 RTE_PTYPE_INNER_L4_ICMP;
12207                                 else if (!strncasecmp(name, "GTPC", 4)) {
12208                                         ptype_mapping[i].sw_ptype |=
12209                                                 RTE_PTYPE_TUNNEL_GTPC;
12210                                         in_tunnel = true;
12211                                 } else if (!strncasecmp(name, "GTPU", 4)) {
12212                                         ptype_mapping[i].sw_ptype |=
12213                                                 RTE_PTYPE_TUNNEL_GTPU;
12214                                         in_tunnel = true;
12215                                 } else if (!strncasecmp(name, "ESP", 3)) {
12216                                         ptype_mapping[i].sw_ptype |=
12217                                                 RTE_PTYPE_TUNNEL_ESP;
12218                                         in_tunnel = true;
12219                                 } else if (!strncasecmp(name, "GRENAT", 6)) {
12220                                         ptype_mapping[i].sw_ptype |=
12221                                                 RTE_PTYPE_TUNNEL_GRENAT;
12222                                         in_tunnel = true;
12223                                 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12224                                            !strncasecmp(name, "L2TPV2", 6) ||
12225                                            !strncasecmp(name, "L2TPV3", 6)) {
12226                                         ptype_mapping[i].sw_ptype |=
12227                                                 RTE_PTYPE_TUNNEL_L2TP;
12228                                         in_tunnel = true;
12229                                 }
12230
12231                                 break;
12232                         }
12233                 }
12234         }
12235
12236         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12237                                                 ptype_num, 0);
12238         if (ret)
12239                 PMD_DRV_LOG(ERR, "Failed to update ptype mapping table.");
12240
12241         rte_free(ptype_mapping);
12242         rte_free(ptype);
12243         return ret;
12244 }
12245
12246 void
12247 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12248                             uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12249 {
12250         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12251         uint32_t proto_num;
12252         struct rte_pmd_i40e_proto_info *proto;
12253         uint32_t buff_size;
12254         uint32_t i;
12255         int ret;
12256
12257         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12258             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12259                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12260                 return;
12261         }
12262
12263         /* get information about protocol number */
12264         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12265                                        (uint8_t *)&proto_num, sizeof(proto_num),
12266                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12267         if (ret) {
12268                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12269                 return;
12270         }
12271         if (!proto_num) {
12272                 PMD_DRV_LOG(INFO, "No new protocol added");
12273                 return;
12274         }
12275
12276         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12277         proto = rte_zmalloc("new_proto", buff_size, 0);
12278         if (!proto) {
12279                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12280                 return;
12281         }
12282
12283         /* get information about protocol list */
12284         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12285                                         (uint8_t *)proto, buff_size,
12286                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12287         if (ret) {
12288                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12289                 rte_free(proto);
12290                 return;
12291         }
12292
12293         /* Check if GTP is supported. */
12294         for (i = 0; i < proto_num; i++) {
12295                 if (!strncmp(proto[i].name, "GTP", 3)) {
12296                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12297                                 pf->gtp_support = true;
12298                         else
12299                                 pf->gtp_support = false;
12300                         break;
12301                 }
12302         }
12303
12304         /* Check if ESP is supported. */
12305         for (i = 0; i < proto_num; i++) {
12306                 if (!strncmp(proto[i].name, "ESP", 3)) {
12307                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12308                                 pf->esp_support = true;
12309                         else
12310                                 pf->esp_support = false;
12311                         break;
12312                 }
12313         }
12314
12315         /* Update customized pctype info */
12316         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12317                                             proto_num, proto, op);
12318         if (ret)
12319                 PMD_DRV_LOG(INFO, "No pctype is updated.");
12320
12321         /* Update customized ptype info */
12322         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12323                                            proto_num, proto, op);
12324         if (ret)
12325                 PMD_DRV_LOG(INFO, "No ptype is updated.");
12326
12327         rte_free(proto);
12328 }
12329
12330 /* Create a QinQ cloud filter
12331  *
12332  * The Fortville NIC has limited resources for tunnel filters,
12333  * so we can only reuse existing filters.
12334  *
12335  * In step 1 we define which Field Vector fields can be used for
12336  * filter types.
12337  * As we do not have the inner tag defined as a field,
12338  * we have to define it first, by reusing one of L1 entries.
12339  *
12340  * In step 2 we are replacing one of existing filter types with
12341  * a new one for QinQ.
12342  * As we reusing L1 and replacing L2, some of the default filter
12343  * types will disappear,which depends on L1 and L2 entries we reuse.
12344  *
12345  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12346  *
12347  * 1.   Create L1 filter of outer vlan (12b) which will be in use
12348  *              later when we define the cloud filter.
12349  *      a.      Valid_flags.replace_cloud = 0
12350  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
12351  *      c.      New_filter = 0x10
12352  *      d.      TR bit = 0xff (optional, not used here)
12353  *      e.      Buffer – 2 entries:
12354  *              i.      Byte 0 = 8 (outer vlan FV index).
12355  *                      Byte 1 = 0 (rsv)
12356  *                      Byte 2-3 = 0x0fff
12357  *              ii.     Byte 0 = 37 (inner vlan FV index).
12358  *                      Byte 1 =0 (rsv)
12359  *                      Byte 2-3 = 0x0fff
12360  *
12361  * Step 2:
12362  * 2.   Create cloud filter using two L1 filters entries: stag and
12363  *              new filter(outer vlan+ inner vlan)
12364  *      a.      Valid_flags.replace_cloud = 1
12365  *      b.      Old_filter = 1 (instead of outer IP)
12366  *      c.      New_filter = 0x10
12367  *      d.      Buffer – 2 entries:
12368  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
12369  *                      Byte 1-3 = 0 (rsv)
12370  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12371  *                      Byte 9-11 = 0 (rsv)
12372  */
12373 static int
12374 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12375 {
12376         int ret = -ENOTSUP;
12377         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
12378         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
12379         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12380         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
12381
12382         if (pf->support_multi_driver) {
12383                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12384                 return ret;
12385         }
12386
12387         /* Init */
12388         memset(&filter_replace, 0,
12389                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12390         memset(&filter_replace_buf, 0,
12391                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12392
12393         /* create L1 filter */
12394         filter_replace.old_filter_type =
12395                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12396         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12397         filter_replace.tr_bit = 0;
12398
12399         /* Prepare the buffer, 2 entries */
12400         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12401         filter_replace_buf.data[0] |=
12402                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12403         /* Field Vector 12b mask */
12404         filter_replace_buf.data[2] = 0xff;
12405         filter_replace_buf.data[3] = 0x0f;
12406         filter_replace_buf.data[4] =
12407                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12408         filter_replace_buf.data[4] |=
12409                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12410         /* Field Vector 12b mask */
12411         filter_replace_buf.data[6] = 0xff;
12412         filter_replace_buf.data[7] = 0x0f;
12413         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12414                         &filter_replace_buf);
12415         if (ret != I40E_SUCCESS)
12416                 return ret;
12417
12418         if (filter_replace.old_filter_type !=
12419             filter_replace.new_filter_type)
12420                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
12421                             " original: 0x%x, new: 0x%x",
12422                             dev->device->name,
12423                             filter_replace.old_filter_type,
12424                             filter_replace.new_filter_type);
12425
12426         /* Apply the second L2 cloud filter */
12427         memset(&filter_replace, 0,
12428                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12429         memset(&filter_replace_buf, 0,
12430                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12431
12432         /* create L2 filter, input for L2 filter will be L1 filter  */
12433         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12434         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12435         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12436
12437         /* Prepare the buffer, 2 entries */
12438         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12439         filter_replace_buf.data[0] |=
12440                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12441         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12442         filter_replace_buf.data[4] |=
12443                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12444         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12445                         &filter_replace_buf);
12446         if (!ret && (filter_replace.old_filter_type !=
12447                      filter_replace.new_filter_type))
12448                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
12449                             " original: 0x%x, new: 0x%x",
12450                             dev->device->name,
12451                             filter_replace.old_filter_type,
12452                             filter_replace.new_filter_type);
12453
12454         return ret;
12455 }
12456
12457 RTE_LOG_REGISTER_SUFFIX(i40e_logtype_init, init, NOTICE);
12458 RTE_LOG_REGISTER_SUFFIX(i40e_logtype_driver, driver, NOTICE);
12459 #ifdef RTE_ETHDEV_DEBUG_RX
12460 RTE_LOG_REGISTER_SUFFIX(i40e_logtype_rx, rx, DEBUG);
12461 #endif
12462 #ifdef RTE_ETHDEV_DEBUG_TX
12463 RTE_LOG_REGISTER_SUFFIX(i40e_logtype_tx, tx, DEBUG);
12464 #endif
12465
12466 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12467                               ETH_I40E_FLOATING_VEB_ARG "=1"
12468                               ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
12469                               ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12470                               ETH_I40E_SUPPORT_MULTI_DRIVER "=1");