4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
43 #include <rte_string_fns.h>
45 #include <rte_ether.h>
46 #include <rte_ethdev.h>
47 #include <rte_memzone.h>
48 #include <rte_malloc.h>
49 #include <rte_memcpy.h>
50 #include <rte_alarm.h>
52 #include <rte_eth_ctrl.h>
54 #include "i40e_logs.h"
55 #include "base/i40e_prototype.h"
56 #include "base/i40e_adminq_cmd.h"
57 #include "base/i40e_type.h"
58 #include "base/i40e_register.h"
59 #include "base/i40e_dcb.h"
60 #include "i40e_ethdev.h"
61 #include "i40e_rxtx.h"
64 /* Maximun number of MAC addresses */
65 #define I40E_NUM_MACADDR_MAX 64
66 #define I40E_CLEAR_PXE_WAIT_MS 200
68 /* Maximun number of capability elements */
69 #define I40E_MAX_CAP_ELE_NUM 128
71 /* Wait count and inteval */
72 #define I40E_CHK_Q_ENA_COUNT 1000
73 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
75 /* Maximun number of VSI */
76 #define I40E_MAX_NUM_VSIS (384UL)
78 /* Default queue interrupt throttling time in microseconds */
79 #define I40E_ITR_INDEX_DEFAULT 0
80 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
81 #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */
83 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
85 /* Flow control default timer */
86 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
88 /* Flow control default high water */
89 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
91 /* Flow control default low water */
92 #define I40E_DEFAULT_LOW_WATER (0x1A40/1024)
94 /* Flow control enable fwd bit */
95 #define I40E_PRTMAC_FWD_CTRL 0x00000001
97 /* Receive Packet Buffer size */
98 #define I40E_RXPBSIZE (968 * 1024)
100 /* Kilobytes shift */
101 #define I40E_KILOSHIFT 10
103 /* Receive Average Packet Size in Byte*/
104 #define I40E_PACKET_AVERAGE_SIZE 128
106 /* Mask of PF interrupt causes */
107 #define I40E_PFINT_ICR0_ENA_MASK ( \
108 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
109 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
110 I40E_PFINT_ICR0_ENA_GRST_MASK | \
111 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
112 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
113 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
114 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
115 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
116 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
117 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
119 #define I40E_FLOW_TYPES ( \
120 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
121 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
122 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
123 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
124 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
125 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
126 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
127 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
128 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
129 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
130 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
132 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
133 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
134 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
135 #define I40E_PRTTSYN_TSYNENA 0x80000000
136 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
138 #define I40E_MAX_PERCENT 100
139 #define I40E_DEFAULT_DCB_APP_NUM 1
140 #define I40E_DEFAULT_DCB_APP_PRIO 3
142 #define I40E_PRTQF_FD_INSET(_i, _j) (0x00250000 + ((_i) * 64 + (_j) * 32))
143 #define I40E_GLQF_FD_MSK(_i, _j) (0x00267200 + ((_i) * 4 + (_j) * 8))
144 #define I40E_GLQF_FD_MSK_FIELD 0x0000FFFF
145 #define I40E_GLQF_HASH_INSET(_i, _j) (0x00267600 + ((_i) * 4 + (_j) * 8))
146 #define I40E_GLQF_HASH_MSK(_i, _j) (0x00267A00 + ((_i) * 4 + (_j) * 8))
147 #define I40E_GLQF_HASH_MSK_FIELD 0x0000FFFF
149 #define I40E_INSET_NONE 0x00000000000000000ULL
152 #define I40E_INSET_DMAC 0x0000000000000001ULL
153 #define I40E_INSET_SMAC 0x0000000000000002ULL
154 #define I40E_INSET_VLAN_OUTER 0x0000000000000004ULL
155 #define I40E_INSET_VLAN_INNER 0x0000000000000008ULL
156 #define I40E_INSET_VLAN_TUNNEL 0x0000000000000010ULL
159 #define I40E_INSET_IPV4_SRC 0x0000000000000100ULL
160 #define I40E_INSET_IPV4_DST 0x0000000000000200ULL
161 #define I40E_INSET_IPV6_SRC 0x0000000000000400ULL
162 #define I40E_INSET_IPV6_DST 0x0000000000000800ULL
163 #define I40E_INSET_SRC_PORT 0x0000000000001000ULL
164 #define I40E_INSET_DST_PORT 0x0000000000002000ULL
165 #define I40E_INSET_SCTP_VT 0x0000000000004000ULL
167 /* bit 16 ~ bit 31 */
168 #define I40E_INSET_IPV4_TOS 0x0000000000010000ULL
169 #define I40E_INSET_IPV4_PROTO 0x0000000000020000ULL
170 #define I40E_INSET_IPV4_TTL 0x0000000000040000ULL
171 #define I40E_INSET_IPV6_TC 0x0000000000080000ULL
172 #define I40E_INSET_IPV6_FLOW 0x0000000000100000ULL
173 #define I40E_INSET_IPV6_NEXT_HDR 0x0000000000200000ULL
174 #define I40E_INSET_IPV6_HOP_LIMIT 0x0000000000400000ULL
175 #define I40E_INSET_TCP_FLAGS 0x0000000000800000ULL
177 /* bit 32 ~ bit 47, tunnel fields */
178 #define I40E_INSET_TUNNEL_IPV4_DST 0x0000000100000000ULL
179 #define I40E_INSET_TUNNEL_IPV6_DST 0x0000000200000000ULL
180 #define I40E_INSET_TUNNEL_DMAC 0x0000000400000000ULL
181 #define I40E_INSET_TUNNEL_SRC_PORT 0x0000000800000000ULL
182 #define I40E_INSET_TUNNEL_DST_PORT 0x0000001000000000ULL
183 #define I40E_INSET_TUNNEL_ID 0x0000002000000000ULL
185 /* bit 48 ~ bit 55 */
186 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
188 /* bit 56 ~ bit 63, Flex Payload */
189 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
190 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
191 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
192 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
193 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
194 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
195 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
196 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
197 #define I40E_INSET_FLEX_PAYLOAD \
198 (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
199 I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W3 | \
200 I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
201 I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
204 * Below are values for writing un-exposed registers suggested
207 /* Destination MAC address */
208 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
209 /* Source MAC address */
210 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
211 /* VLAN tag in the outer L2 header */
212 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000000800000ULL
213 /* VLAN tag in the inner L2 header */
214 #define I40E_REG_INSET_L2_INNER_VLAN 0x0000000001000000ULL
215 /* Source IPv4 address */
216 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
217 /* Destination IPv4 address */
218 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
219 /* IPv4 Type of Service (TOS) */
220 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
222 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
223 /* Source IPv6 address */
224 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
225 /* Destination IPv6 address */
226 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
227 /* IPv6 Traffic Class (TC) */
228 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
229 /* IPv6 Next Header */
230 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
232 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
233 /* Destination L4 port */
234 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
235 /* SCTP verification tag */
236 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
237 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
238 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
239 /* Source port of tunneling UDP */
240 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
241 /* Destination port of tunneling UDP */
242 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
243 /* UDP Tunneling ID, NVGRE/GRE key */
244 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
245 /* Last ether type */
246 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
247 /* Tunneling outer destination IPv4 address */
248 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
249 /* Tunneling outer destination IPv6 address */
250 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
251 /* 1st word of flex payload */
252 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
253 /* 2nd word of flex payload */
254 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
255 /* 3rd word of flex payload */
256 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
257 /* 4th word of flex payload */
258 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
259 /* 5th word of flex payload */
260 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
261 /* 6th word of flex payload */
262 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
263 /* 7th word of flex payload */
264 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
265 /* 8th word of flex payload */
266 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
268 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
270 #define I40E_TRANSLATE_INSET 0
271 #define I40E_TRANSLATE_REG 1
273 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
274 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
275 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
276 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
278 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
279 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
280 static int i40e_dev_configure(struct rte_eth_dev *dev);
281 static int i40e_dev_start(struct rte_eth_dev *dev);
282 static void i40e_dev_stop(struct rte_eth_dev *dev);
283 static void i40e_dev_close(struct rte_eth_dev *dev);
284 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
285 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
286 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
287 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
288 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
289 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
290 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
291 struct rte_eth_stats *stats);
292 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
293 struct rte_eth_xstats *xstats, unsigned n);
294 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
295 static void i40e_dev_xstats_reset(struct rte_eth_dev *dev);
296 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
300 static void i40e_dev_info_get(struct rte_eth_dev *dev,
301 struct rte_eth_dev_info *dev_info);
302 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
305 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
306 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
307 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
310 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
311 static int i40e_dev_led_on(struct rte_eth_dev *dev);
312 static int i40e_dev_led_off(struct rte_eth_dev *dev);
313 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
314 struct rte_eth_fc_conf *fc_conf);
315 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
316 struct rte_eth_fc_conf *fc_conf);
317 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
318 struct rte_eth_pfc_conf *pfc_conf);
319 static void i40e_macaddr_add(struct rte_eth_dev *dev,
320 struct ether_addr *mac_addr,
323 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
324 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
325 struct rte_eth_rss_reta_entry64 *reta_conf,
327 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
328 struct rte_eth_rss_reta_entry64 *reta_conf,
331 static int i40e_get_cap(struct i40e_hw *hw);
332 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
333 static int i40e_pf_setup(struct i40e_pf *pf);
334 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
335 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
336 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
337 static int i40e_dcb_setup(struct rte_eth_dev *dev);
338 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
339 bool offset_loaded, uint64_t *offset, uint64_t *stat);
340 static void i40e_stat_update_48(struct i40e_hw *hw,
346 static void i40e_pf_config_irq0(struct i40e_hw *hw);
347 static void i40e_dev_interrupt_handler(
348 __rte_unused struct rte_intr_handle *handle, void *param);
349 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
350 uint32_t base, uint32_t num);
351 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
352 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
354 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
356 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
357 static int i40e_veb_release(struct i40e_veb *veb);
358 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
359 struct i40e_vsi *vsi);
360 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
361 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
362 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
363 struct i40e_macvlan_filter *mv_f,
365 struct ether_addr *addr);
366 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
367 struct i40e_macvlan_filter *mv_f,
370 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
371 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
372 struct rte_eth_rss_conf *rss_conf);
373 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
374 struct rte_eth_rss_conf *rss_conf);
375 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
376 struct rte_eth_udp_tunnel *udp_tunnel);
377 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
378 struct rte_eth_udp_tunnel *udp_tunnel);
379 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
380 struct rte_eth_ethertype_filter *filter,
382 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
383 enum rte_filter_op filter_op,
385 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
386 enum rte_filter_type filter_type,
387 enum rte_filter_op filter_op,
389 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
390 struct rte_eth_dcb_info *dcb_info);
391 static void i40e_configure_registers(struct i40e_hw *hw);
392 static void i40e_hw_init(struct i40e_hw *hw);
393 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
394 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
395 struct rte_eth_mirror_conf *mirror_conf,
396 uint8_t sw_id, uint8_t on);
397 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
399 static int i40e_timesync_enable(struct rte_eth_dev *dev);
400 static int i40e_timesync_disable(struct rte_eth_dev *dev);
401 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
402 struct timespec *timestamp,
404 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
405 struct timespec *timestamp);
406 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
409 static const struct rte_pci_id pci_id_i40e_map[] = {
410 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
411 #include "rte_pci_dev_ids.h"
412 { .vendor_id = 0, /* sentinel */ },
415 static const struct eth_dev_ops i40e_eth_dev_ops = {
416 .dev_configure = i40e_dev_configure,
417 .dev_start = i40e_dev_start,
418 .dev_stop = i40e_dev_stop,
419 .dev_close = i40e_dev_close,
420 .promiscuous_enable = i40e_dev_promiscuous_enable,
421 .promiscuous_disable = i40e_dev_promiscuous_disable,
422 .allmulticast_enable = i40e_dev_allmulticast_enable,
423 .allmulticast_disable = i40e_dev_allmulticast_disable,
424 .dev_set_link_up = i40e_dev_set_link_up,
425 .dev_set_link_down = i40e_dev_set_link_down,
426 .link_update = i40e_dev_link_update,
427 .stats_get = i40e_dev_stats_get,
428 .xstats_get = i40e_dev_xstats_get,
429 .stats_reset = i40e_dev_stats_reset,
430 .xstats_reset = i40e_dev_xstats_reset,
431 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
432 .dev_infos_get = i40e_dev_info_get,
433 .vlan_filter_set = i40e_vlan_filter_set,
434 .vlan_tpid_set = i40e_vlan_tpid_set,
435 .vlan_offload_set = i40e_vlan_offload_set,
436 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
437 .vlan_pvid_set = i40e_vlan_pvid_set,
438 .rx_queue_start = i40e_dev_rx_queue_start,
439 .rx_queue_stop = i40e_dev_rx_queue_stop,
440 .tx_queue_start = i40e_dev_tx_queue_start,
441 .tx_queue_stop = i40e_dev_tx_queue_stop,
442 .rx_queue_setup = i40e_dev_rx_queue_setup,
443 .rx_queue_release = i40e_dev_rx_queue_release,
444 .rx_queue_count = i40e_dev_rx_queue_count,
445 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
446 .tx_queue_setup = i40e_dev_tx_queue_setup,
447 .tx_queue_release = i40e_dev_tx_queue_release,
448 .dev_led_on = i40e_dev_led_on,
449 .dev_led_off = i40e_dev_led_off,
450 .flow_ctrl_get = i40e_flow_ctrl_get,
451 .flow_ctrl_set = i40e_flow_ctrl_set,
452 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
453 .mac_addr_add = i40e_macaddr_add,
454 .mac_addr_remove = i40e_macaddr_remove,
455 .reta_update = i40e_dev_rss_reta_update,
456 .reta_query = i40e_dev_rss_reta_query,
457 .rss_hash_update = i40e_dev_rss_hash_update,
458 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
459 .udp_tunnel_add = i40e_dev_udp_tunnel_add,
460 .udp_tunnel_del = i40e_dev_udp_tunnel_del,
461 .filter_ctrl = i40e_dev_filter_ctrl,
462 .rxq_info_get = i40e_rxq_info_get,
463 .txq_info_get = i40e_txq_info_get,
464 .mirror_rule_set = i40e_mirror_rule_set,
465 .mirror_rule_reset = i40e_mirror_rule_reset,
466 .timesync_enable = i40e_timesync_enable,
467 .timesync_disable = i40e_timesync_disable,
468 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
469 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
470 .get_dcb_info = i40e_dev_get_dcb_info,
473 /* store statistics names and its offset in stats structure */
474 struct rte_i40e_xstats_name_off {
475 char name[RTE_ETH_XSTATS_NAME_SIZE];
479 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
480 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
481 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
482 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
483 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
484 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
485 rx_unknown_protocol)},
486 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
487 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
488 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
489 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
492 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
493 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
494 tx_dropped_link_down)},
495 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
496 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
498 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
499 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
501 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
503 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
505 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
506 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
507 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
508 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
509 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
510 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
512 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
514 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
516 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
518 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
520 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
522 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
524 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
526 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
527 mac_short_packet_dropped)},
528 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
530 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
531 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
532 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
534 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
536 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
538 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
540 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
542 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
544 {"rx_flow_director_atr_match_packets",
545 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
546 {"rx_flow_director_sb_match_packets",
547 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
548 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
550 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
552 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
554 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
558 /* Q Stats: 5 stats are exposed for each queue, implemented in xstats_get() */
559 #define I40E_NB_HW_PORT_Q_STATS (8 * 5)
561 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
562 sizeof(rte_i40e_stats_strings[0]))
563 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
564 sizeof(rte_i40e_hw_port_strings[0]))
565 #define I40E_NB_XSTATS (I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS + \
566 I40E_NB_HW_PORT_Q_STATS)
568 static struct eth_driver rte_i40e_pmd = {
570 .name = "rte_i40e_pmd",
571 .id_table = pci_id_i40e_map,
572 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
573 RTE_PCI_DRV_DETACHABLE,
575 .eth_dev_init = eth_i40e_dev_init,
576 .eth_dev_uninit = eth_i40e_dev_uninit,
577 .dev_private_size = sizeof(struct i40e_adapter),
581 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
582 struct rte_eth_link *link)
584 struct rte_eth_link *dst = link;
585 struct rte_eth_link *src = &(dev->data->dev_link);
587 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
588 *(uint64_t *)src) == 0)
595 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
596 struct rte_eth_link *link)
598 struct rte_eth_link *dst = &(dev->data->dev_link);
599 struct rte_eth_link *src = link;
601 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
602 *(uint64_t *)src) == 0)
609 * Driver initialization routine.
610 * Invoked once at EAL init time.
611 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
614 rte_i40e_pmd_init(const char *name __rte_unused,
615 const char *params __rte_unused)
617 PMD_INIT_FUNC_TRACE();
618 rte_eth_driver_register(&rte_i40e_pmd);
623 static struct rte_driver rte_i40e_driver = {
625 .init = rte_i40e_pmd_init,
628 PMD_REGISTER_DRIVER(rte_i40e_driver);
631 * Initialize registers for flexible payload, which should be set by NVM.
632 * This should be removed from code once it is fixed in NVM.
634 #ifndef I40E_GLQF_ORT
635 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
637 #ifndef I40E_GLQF_PIT
638 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
641 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
643 I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
644 I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
645 I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
646 I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
647 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
648 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
649 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
650 I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
651 I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
652 I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
654 /* GLQF_PIT Registers */
655 I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
656 I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
659 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
662 * Add a ethertype filter to drop all flow control frames transmitted
666 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
668 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
669 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
670 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
671 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
674 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
675 I40E_FLOW_CONTROL_ETHERTYPE, flags,
676 pf->main_vsi_seid, 0,
679 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
680 " frames from VSIs.");
684 eth_i40e_dev_init(struct rte_eth_dev *dev)
686 struct rte_pci_device *pci_dev;
687 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
688 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
689 struct i40e_vsi *vsi;
694 PMD_INIT_FUNC_TRACE();
696 dev->dev_ops = &i40e_eth_dev_ops;
697 dev->rx_pkt_burst = i40e_recv_pkts;
698 dev->tx_pkt_burst = i40e_xmit_pkts;
700 /* for secondary processes, we don't initialise any further as primary
701 * has already done this work. Only check we don't need a different
703 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
704 i40e_set_rx_function(dev);
705 i40e_set_tx_function(dev);
708 pci_dev = dev->pci_dev;
710 rte_eth_copy_pci_info(dev, pci_dev);
712 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
713 pf->adapter->eth_dev = dev;
714 pf->dev_data = dev->data;
716 hw->back = I40E_PF_TO_ADAPTER(pf);
717 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
719 PMD_INIT_LOG(ERR, "Hardware is not available, "
720 "as address is NULL");
724 hw->vendor_id = pci_dev->id.vendor_id;
725 hw->device_id = pci_dev->id.device_id;
726 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
727 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
728 hw->bus.device = pci_dev->addr.devid;
729 hw->bus.func = pci_dev->addr.function;
730 hw->adapter_stopped = 0;
732 /* Make sure all is clean before doing PF reset */
735 /* Initialize the hardware */
738 /* Reset here to make sure all is clean for each PF */
739 ret = i40e_pf_reset(hw);
741 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
745 /* Initialize the shared code (base driver) */
746 ret = i40e_init_shared_code(hw);
748 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
753 * To work around the NVM issue,initialize registers
754 * for flexible payload by software.
755 * It should be removed once issues are fixed in NVM.
757 i40e_flex_payload_reg_init(hw);
759 /* Initialize the parameters for adminq */
760 i40e_init_adminq_parameter(hw);
761 ret = i40e_init_adminq(hw);
762 if (ret != I40E_SUCCESS) {
763 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
766 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
767 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
768 hw->aq.api_maj_ver, hw->aq.api_min_ver,
769 ((hw->nvm.version >> 12) & 0xf),
770 ((hw->nvm.version >> 4) & 0xff),
771 (hw->nvm.version & 0xf), hw->nvm.eetrack);
774 i40e_clear_pxe_mode(hw);
777 * On X710, performance number is far from the expectation on recent
778 * firmware versions. The fix for this issue may not be integrated in
779 * the following firmware version. So the workaround in software driver
780 * is needed. It needs to modify the initial values of 3 internal only
781 * registers. Note that the workaround can be removed when it is fixed
782 * in firmware in the future.
784 i40e_configure_registers(hw);
786 /* Get hw capabilities */
787 ret = i40e_get_cap(hw);
788 if (ret != I40E_SUCCESS) {
789 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
790 goto err_get_capabilities;
793 /* Initialize parameters for PF */
794 ret = i40e_pf_parameter_init(dev);
796 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
797 goto err_parameter_init;
800 /* Initialize the queue management */
801 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
803 PMD_INIT_LOG(ERR, "Failed to init queue pool");
804 goto err_qp_pool_init;
806 ret = i40e_res_pool_init(&pf->msix_pool, 1,
807 hw->func_caps.num_msix_vectors - 1);
809 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
810 goto err_msix_pool_init;
813 /* Initialize lan hmc */
814 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
815 hw->func_caps.num_rx_qp, 0, 0);
816 if (ret != I40E_SUCCESS) {
817 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
818 goto err_init_lan_hmc;
821 /* Configure lan hmc */
822 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
823 if (ret != I40E_SUCCESS) {
824 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
825 goto err_configure_lan_hmc;
828 /* Get and check the mac address */
829 i40e_get_mac_addr(hw, hw->mac.addr);
830 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
831 PMD_INIT_LOG(ERR, "mac address is not valid");
833 goto err_get_mac_addr;
835 /* Copy the permanent MAC address */
836 ether_addr_copy((struct ether_addr *) hw->mac.addr,
837 (struct ether_addr *) hw->mac.perm_addr);
839 /* Disable flow control */
840 hw->fc.requested_mode = I40E_FC_NONE;
841 i40e_set_fc(hw, &aq_fail, TRUE);
843 /* PF setup, which includes VSI setup */
844 ret = i40e_pf_setup(pf);
846 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
847 goto err_setup_pf_switch;
852 /* Disable double vlan by default */
853 i40e_vsi_config_double_vlan(vsi, FALSE);
855 if (!vsi->max_macaddrs)
856 len = ETHER_ADDR_LEN;
858 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
860 /* Should be after VSI initialized */
861 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
862 if (!dev->data->mac_addrs) {
863 PMD_INIT_LOG(ERR, "Failed to allocated memory "
864 "for storing mac address");
867 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
868 &dev->data->mac_addrs[0]);
870 /* initialize pf host driver to setup SRIOV resource if applicable */
871 i40e_pf_host_init(dev);
873 /* register callback func to eal lib */
874 rte_intr_callback_register(&(pci_dev->intr_handle),
875 i40e_dev_interrupt_handler, (void *)dev);
877 /* configure and enable device interrupt */
878 i40e_pf_config_irq0(hw);
879 i40e_pf_enable_irq0(hw);
881 /* enable uio intr after callback register */
882 rte_intr_enable(&(pci_dev->intr_handle));
884 * Add an ethertype filter to drop all flow control frames transmitted
885 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
888 i40e_add_tx_flow_control_drop_filter(pf);
890 /* initialize mirror rule list */
891 TAILQ_INIT(&pf->mirror_list);
893 /* Init dcb to sw mode by default */
894 ret = i40e_dcb_init_configure(dev, TRUE);
895 if (ret != I40E_SUCCESS) {
896 PMD_INIT_LOG(INFO, "Failed to init dcb.");
897 pf->flags &= ~I40E_FLAG_DCB;
903 i40e_vsi_release(pf->main_vsi);
906 err_configure_lan_hmc:
907 (void)i40e_shutdown_lan_hmc(hw);
909 i40e_res_pool_destroy(&pf->msix_pool);
911 i40e_res_pool_destroy(&pf->qp_pool);
914 err_get_capabilities:
915 (void)i40e_shutdown_adminq(hw);
921 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
923 struct rte_pci_device *pci_dev;
925 struct i40e_filter_control_settings settings;
929 PMD_INIT_FUNC_TRACE();
931 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
934 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
935 pci_dev = dev->pci_dev;
937 if (hw->adapter_stopped == 0)
941 dev->rx_pkt_burst = NULL;
942 dev->tx_pkt_burst = NULL;
945 ret = i40e_aq_stop_lldp(hw, true, NULL);
946 if (ret != I40E_SUCCESS) /* Its failure can be ignored */
947 PMD_INIT_LOG(INFO, "Failed to stop lldp");
950 i40e_clear_pxe_mode(hw);
952 /* Unconfigure filter control */
953 memset(&settings, 0, sizeof(settings));
954 ret = i40e_set_filter_control(hw, &settings);
956 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
959 /* Disable flow control */
960 hw->fc.requested_mode = I40E_FC_NONE;
961 i40e_set_fc(hw, &aq_fail, TRUE);
963 /* uninitialize pf host driver */
964 i40e_pf_host_uninit(dev);
966 rte_free(dev->data->mac_addrs);
967 dev->data->mac_addrs = NULL;
969 /* disable uio intr before callback unregister */
970 rte_intr_disable(&(pci_dev->intr_handle));
972 /* register callback func to eal lib */
973 rte_intr_callback_unregister(&(pci_dev->intr_handle),
974 i40e_dev_interrupt_handler, (void *)dev);
980 i40e_dev_configure(struct rte_eth_dev *dev)
982 struct i40e_adapter *ad =
983 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
984 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
985 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
988 /* Initialize to TRUE. If any of Rx queues doesn't meet the
989 * bulk allocation or vector Rx preconditions we will reset it.
991 ad->rx_bulk_alloc_allowed = true;
992 ad->rx_vec_allowed = true;
993 ad->tx_simple_allowed = true;
994 ad->tx_vec_allowed = true;
996 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
997 ret = i40e_fdir_setup(pf);
998 if (ret != I40E_SUCCESS) {
999 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1002 ret = i40e_fdir_configure(dev);
1004 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1008 i40e_fdir_teardown(pf);
1010 ret = i40e_dev_init_vlan(dev);
1015 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1016 * RSS setting have different requirements.
1017 * General PMD driver call sequence are NIC init, configure,
1018 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1019 * will try to lookup the VSI that specific queue belongs to if VMDQ
1020 * applicable. So, VMDQ setting has to be done before
1021 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1022 * For RSS setting, it will try to calculate actual configured RX queue
1023 * number, which will be available after rx_queue_setup(). dev_start()
1024 * function is good to place RSS setup.
1026 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1027 ret = i40e_vmdq_setup(dev);
1032 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1033 ret = i40e_dcb_setup(dev);
1035 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1043 /* need to release vmdq resource if exists */
1044 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1045 i40e_vsi_release(pf->vmdq[i].vsi);
1046 pf->vmdq[i].vsi = NULL;
1051 /* need to release fdir resource if exists */
1052 i40e_fdir_teardown(pf);
1057 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1059 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1060 uint16_t msix_vect = vsi->msix_intr;
1063 for (i = 0; i < vsi->nb_qps; i++) {
1064 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1065 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1069 if (vsi->type != I40E_VSI_SRIOV) {
1070 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
1071 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1075 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1076 vsi->user_param + (msix_vect - 1);
1078 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
1080 I40E_WRITE_FLUSH(hw);
1083 static inline uint16_t
1084 i40e_calc_itr_interval(int16_t interval)
1086 if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
1087 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
1089 /* Convert to hardware count, as writing each 1 represents 2 us */
1090 return (interval/2);
1094 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1097 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1098 uint16_t msix_vect = vsi->msix_intr;
1101 for (i = 0; i < vsi->nb_qps; i++)
1102 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1104 /* Bind all RX queues to allocated MSIX interrupt */
1105 for (i = 0; i < vsi->nb_qps; i++) {
1106 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1107 I40E_QINT_RQCTL_ITR_INDX_MASK |
1108 ((vsi->base_queue + i + 1) <<
1109 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1110 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1111 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1113 if (i == vsi->nb_qps - 1)
1114 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1115 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
1118 /* Write first RX queue to Link list register as the head element */
1119 if (vsi->type != I40E_VSI_SRIOV) {
1121 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1123 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1125 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1126 (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1128 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1129 msix_vect - 1), interval);
1131 #ifndef I40E_GLINT_CTL
1132 #define I40E_GLINT_CTL 0x0003F800
1133 #define I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK 0x4
1135 /* Disable auto-mask on enabling of all none-zero interrupt */
1136 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
1137 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
1141 /* num_msix_vectors_vf needs to minus irq0 */
1142 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1143 vsi->user_param + (msix_vect - 1);
1145 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), (vsi->base_queue <<
1146 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1147 (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1150 I40E_WRITE_FLUSH(hw);
1154 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1156 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1157 uint16_t interval = i40e_calc_itr_interval(\
1158 RTE_LIBRTE_I40E_ITR_INTERVAL);
1160 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
1161 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1162 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1163 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1164 (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1168 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1170 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1172 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
1175 static inline uint8_t
1176 i40e_parse_link_speed(uint16_t eth_link_speed)
1178 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1180 switch (eth_link_speed) {
1181 case ETH_LINK_SPEED_40G:
1182 link_speed = I40E_LINK_SPEED_40GB;
1184 case ETH_LINK_SPEED_20G:
1185 link_speed = I40E_LINK_SPEED_20GB;
1187 case ETH_LINK_SPEED_10G:
1188 link_speed = I40E_LINK_SPEED_10GB;
1190 case ETH_LINK_SPEED_1000:
1191 link_speed = I40E_LINK_SPEED_1GB;
1193 case ETH_LINK_SPEED_100:
1194 link_speed = I40E_LINK_SPEED_100MB;
1202 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
1204 enum i40e_status_code status;
1205 struct i40e_aq_get_phy_abilities_resp phy_ab;
1206 struct i40e_aq_set_phy_config phy_conf;
1207 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1208 I40E_AQ_PHY_FLAG_PAUSE_RX |
1209 I40E_AQ_PHY_FLAG_LOW_POWER;
1210 const uint8_t advt = I40E_LINK_SPEED_40GB |
1211 I40E_LINK_SPEED_10GB |
1212 I40E_LINK_SPEED_1GB |
1213 I40E_LINK_SPEED_100MB;
1216 /* Skip it on 40G interfaces, as a workaround for the link issue */
1217 if (i40e_is_40G_device(hw->device_id))
1218 return I40E_SUCCESS;
1220 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1225 memset(&phy_conf, 0, sizeof(phy_conf));
1227 /* bits 0-2 use the values from get_phy_abilities_resp */
1229 abilities |= phy_ab.abilities & mask;
1231 /* update ablities and speed */
1232 if (abilities & I40E_AQ_PHY_AN_ENABLED)
1233 phy_conf.link_speed = advt;
1235 phy_conf.link_speed = force_speed;
1237 phy_conf.abilities = abilities;
1239 /* use get_phy_abilities_resp value for the rest */
1240 phy_conf.phy_type = phy_ab.phy_type;
1241 phy_conf.eee_capability = phy_ab.eee_capability;
1242 phy_conf.eeer = phy_ab.eeer_val;
1243 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1245 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1246 phy_ab.abilities, phy_ab.link_speed);
1247 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
1248 phy_conf.abilities, phy_conf.link_speed);
1250 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1254 return I40E_SUCCESS;
1258 i40e_apply_link_speed(struct rte_eth_dev *dev)
1261 uint8_t abilities = 0;
1262 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1263 struct rte_eth_conf *conf = &dev->data->dev_conf;
1265 speed = i40e_parse_link_speed(conf->link_speed);
1266 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1267 if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
1268 abilities |= I40E_AQ_PHY_AN_ENABLED;
1270 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1272 return i40e_phy_conf_link(hw, abilities, speed);
1276 i40e_dev_start(struct rte_eth_dev *dev)
1278 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1279 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1280 struct i40e_vsi *main_vsi = pf->main_vsi;
1283 hw->adapter_stopped = 0;
1285 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1286 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1287 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1288 dev->data->dev_conf.link_duplex,
1289 dev->data->port_id);
1293 /* Initialize VSI */
1294 ret = i40e_dev_rxtx_init(pf);
1295 if (ret != I40E_SUCCESS) {
1296 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1300 /* Map queues with MSIX interrupt */
1301 i40e_vsi_queues_bind_intr(main_vsi);
1302 i40e_vsi_enable_queues_intr(main_vsi);
1304 /* Map VMDQ VSI queues with MSIX interrupt */
1305 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1306 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1307 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1310 /* enable FDIR MSIX interrupt */
1311 if (pf->fdir.fdir_vsi) {
1312 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1313 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1316 /* Enable all queues which have been configured */
1317 ret = i40e_dev_switch_queues(pf, TRUE);
1318 if (ret != I40E_SUCCESS) {
1319 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1323 /* Enable receiving broadcast packets */
1324 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1325 if (ret != I40E_SUCCESS)
1326 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1328 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1329 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1331 if (ret != I40E_SUCCESS)
1332 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1335 /* Apply link configure */
1336 ret = i40e_apply_link_speed(dev);
1337 if (I40E_SUCCESS != ret) {
1338 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1342 return I40E_SUCCESS;
1345 i40e_dev_switch_queues(pf, FALSE);
1346 i40e_dev_clear_queues(dev);
1352 i40e_dev_stop(struct rte_eth_dev *dev)
1354 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1355 struct i40e_vsi *main_vsi = pf->main_vsi;
1356 struct i40e_mirror_rule *p_mirror;
1359 /* Disable all queues */
1360 i40e_dev_switch_queues(pf, FALSE);
1362 /* un-map queues with interrupt registers */
1363 i40e_vsi_disable_queues_intr(main_vsi);
1364 i40e_vsi_queues_unbind_intr(main_vsi);
1366 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1367 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1368 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1371 if (pf->fdir.fdir_vsi) {
1372 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1373 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1375 /* Clear all queues and release memory */
1376 i40e_dev_clear_queues(dev);
1379 i40e_dev_set_link_down(dev);
1381 /* Remove all mirror rules */
1382 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1383 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1386 pf->nb_mirror_rule = 0;
1391 i40e_dev_close(struct rte_eth_dev *dev)
1393 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1394 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1398 PMD_INIT_FUNC_TRACE();
1401 hw->adapter_stopped = 1;
1402 i40e_dev_free_queues(dev);
1404 /* Disable interrupt */
1405 i40e_pf_disable_irq0(hw);
1406 rte_intr_disable(&(dev->pci_dev->intr_handle));
1408 /* shutdown and destroy the HMC */
1409 i40e_shutdown_lan_hmc(hw);
1411 /* release all the existing VSIs and VEBs */
1412 i40e_fdir_teardown(pf);
1413 i40e_vsi_release(pf->main_vsi);
1415 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1416 i40e_vsi_release(pf->vmdq[i].vsi);
1417 pf->vmdq[i].vsi = NULL;
1423 /* shutdown the adminq */
1424 i40e_aq_queue_shutdown(hw, true);
1425 i40e_shutdown_adminq(hw);
1427 i40e_res_pool_destroy(&pf->qp_pool);
1428 i40e_res_pool_destroy(&pf->msix_pool);
1430 /* force a PF reset to clean anything leftover */
1431 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1432 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1433 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1434 I40E_WRITE_FLUSH(hw);
1438 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1440 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1441 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1442 struct i40e_vsi *vsi = pf->main_vsi;
1445 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1447 if (status != I40E_SUCCESS)
1448 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1450 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1452 if (status != I40E_SUCCESS)
1453 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1458 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1460 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1461 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1462 struct i40e_vsi *vsi = pf->main_vsi;
1465 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1467 if (status != I40E_SUCCESS)
1468 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1470 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1472 if (status != I40E_SUCCESS)
1473 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1477 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1479 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1480 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1481 struct i40e_vsi *vsi = pf->main_vsi;
1484 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1485 if (ret != I40E_SUCCESS)
1486 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1490 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1492 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1493 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1494 struct i40e_vsi *vsi = pf->main_vsi;
1497 if (dev->data->promiscuous == 1)
1498 return; /* must remain in all_multicast mode */
1500 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1501 vsi->seid, FALSE, NULL);
1502 if (ret != I40E_SUCCESS)
1503 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1507 * Set device link up.
1510 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1512 /* re-apply link speed setting */
1513 return i40e_apply_link_speed(dev);
1517 * Set device link down.
1520 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1522 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1523 uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1524 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1526 return i40e_phy_conf_link(hw, abilities, speed);
1530 i40e_dev_link_update(struct rte_eth_dev *dev,
1531 int wait_to_complete)
1533 #define CHECK_INTERVAL 100 /* 100ms */
1534 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
1535 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1536 struct i40e_link_status link_status;
1537 struct rte_eth_link link, old;
1539 unsigned rep_cnt = MAX_REPEAT_TIME;
1541 memset(&link, 0, sizeof(link));
1542 memset(&old, 0, sizeof(old));
1543 memset(&link_status, 0, sizeof(link_status));
1544 rte_i40e_dev_atomic_read_link_status(dev, &old);
1547 /* Get link status information from hardware */
1548 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1549 if (status != I40E_SUCCESS) {
1550 link.link_speed = ETH_LINK_SPEED_100;
1551 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1552 PMD_DRV_LOG(ERR, "Failed to get link info");
1556 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1557 if (!wait_to_complete)
1560 rte_delay_ms(CHECK_INTERVAL);
1561 } while (!link.link_status && rep_cnt--);
1563 if (!link.link_status)
1566 /* i40e uses full duplex only */
1567 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1569 /* Parse the link status */
1570 switch (link_status.link_speed) {
1571 case I40E_LINK_SPEED_100MB:
1572 link.link_speed = ETH_LINK_SPEED_100;
1574 case I40E_LINK_SPEED_1GB:
1575 link.link_speed = ETH_LINK_SPEED_1000;
1577 case I40E_LINK_SPEED_10GB:
1578 link.link_speed = ETH_LINK_SPEED_10G;
1580 case I40E_LINK_SPEED_20GB:
1581 link.link_speed = ETH_LINK_SPEED_20G;
1583 case I40E_LINK_SPEED_40GB:
1584 link.link_speed = ETH_LINK_SPEED_40G;
1587 link.link_speed = ETH_LINK_SPEED_100;
1592 rte_i40e_dev_atomic_write_link_status(dev, &link);
1593 if (link.link_status == old.link_status)
1599 /* Get all the statistics of a VSI */
1601 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1603 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1604 struct i40e_eth_stats *nes = &vsi->eth_stats;
1605 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1606 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1608 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1609 vsi->offset_loaded, &oes->rx_bytes,
1611 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1612 vsi->offset_loaded, &oes->rx_unicast,
1614 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1615 vsi->offset_loaded, &oes->rx_multicast,
1616 &nes->rx_multicast);
1617 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1618 vsi->offset_loaded, &oes->rx_broadcast,
1619 &nes->rx_broadcast);
1620 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1621 &oes->rx_discards, &nes->rx_discards);
1622 /* GLV_REPC not supported */
1623 /* GLV_RMPC not supported */
1624 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1625 &oes->rx_unknown_protocol,
1626 &nes->rx_unknown_protocol);
1627 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1628 vsi->offset_loaded, &oes->tx_bytes,
1630 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1631 vsi->offset_loaded, &oes->tx_unicast,
1633 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1634 vsi->offset_loaded, &oes->tx_multicast,
1635 &nes->tx_multicast);
1636 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1637 vsi->offset_loaded, &oes->tx_broadcast,
1638 &nes->tx_broadcast);
1639 /* GLV_TDPC not supported */
1640 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1641 &oes->tx_errors, &nes->tx_errors);
1642 vsi->offset_loaded = true;
1644 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1646 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
1647 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
1648 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
1649 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
1650 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
1651 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1652 nes->rx_unknown_protocol);
1653 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
1654 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
1655 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
1656 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
1657 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
1658 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
1659 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1664 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
1667 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1668 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1669 /* Get statistics of struct i40e_eth_stats */
1670 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1671 I40E_GLPRT_GORCL(hw->port),
1672 pf->offset_loaded, &os->eth.rx_bytes,
1674 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1675 I40E_GLPRT_UPRCL(hw->port),
1676 pf->offset_loaded, &os->eth.rx_unicast,
1677 &ns->eth.rx_unicast);
1678 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1679 I40E_GLPRT_MPRCL(hw->port),
1680 pf->offset_loaded, &os->eth.rx_multicast,
1681 &ns->eth.rx_multicast);
1682 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1683 I40E_GLPRT_BPRCL(hw->port),
1684 pf->offset_loaded, &os->eth.rx_broadcast,
1685 &ns->eth.rx_broadcast);
1686 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1687 pf->offset_loaded, &os->eth.rx_discards,
1688 &ns->eth.rx_discards);
1689 /* GLPRT_REPC not supported */
1690 /* GLPRT_RMPC not supported */
1691 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1693 &os->eth.rx_unknown_protocol,
1694 &ns->eth.rx_unknown_protocol);
1695 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1696 I40E_GLPRT_GOTCL(hw->port),
1697 pf->offset_loaded, &os->eth.tx_bytes,
1699 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1700 I40E_GLPRT_UPTCL(hw->port),
1701 pf->offset_loaded, &os->eth.tx_unicast,
1702 &ns->eth.tx_unicast);
1703 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1704 I40E_GLPRT_MPTCL(hw->port),
1705 pf->offset_loaded, &os->eth.tx_multicast,
1706 &ns->eth.tx_multicast);
1707 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1708 I40E_GLPRT_BPTCL(hw->port),
1709 pf->offset_loaded, &os->eth.tx_broadcast,
1710 &ns->eth.tx_broadcast);
1711 /* GLPRT_TEPC not supported */
1713 /* additional port specific stats */
1714 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1715 pf->offset_loaded, &os->tx_dropped_link_down,
1716 &ns->tx_dropped_link_down);
1717 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1718 pf->offset_loaded, &os->crc_errors,
1720 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1721 pf->offset_loaded, &os->illegal_bytes,
1722 &ns->illegal_bytes);
1723 /* GLPRT_ERRBC not supported */
1724 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1725 pf->offset_loaded, &os->mac_local_faults,
1726 &ns->mac_local_faults);
1727 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1728 pf->offset_loaded, &os->mac_remote_faults,
1729 &ns->mac_remote_faults);
1730 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1731 pf->offset_loaded, &os->rx_length_errors,
1732 &ns->rx_length_errors);
1733 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1734 pf->offset_loaded, &os->link_xon_rx,
1736 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1737 pf->offset_loaded, &os->link_xoff_rx,
1739 for (i = 0; i < 8; i++) {
1740 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1742 &os->priority_xon_rx[i],
1743 &ns->priority_xon_rx[i]);
1744 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1746 &os->priority_xoff_rx[i],
1747 &ns->priority_xoff_rx[i]);
1749 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1750 pf->offset_loaded, &os->link_xon_tx,
1752 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1753 pf->offset_loaded, &os->link_xoff_tx,
1755 for (i = 0; i < 8; i++) {
1756 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1758 &os->priority_xon_tx[i],
1759 &ns->priority_xon_tx[i]);
1760 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1762 &os->priority_xoff_tx[i],
1763 &ns->priority_xoff_tx[i]);
1764 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1766 &os->priority_xon_2_xoff[i],
1767 &ns->priority_xon_2_xoff[i]);
1769 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1770 I40E_GLPRT_PRC64L(hw->port),
1771 pf->offset_loaded, &os->rx_size_64,
1773 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1774 I40E_GLPRT_PRC127L(hw->port),
1775 pf->offset_loaded, &os->rx_size_127,
1777 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1778 I40E_GLPRT_PRC255L(hw->port),
1779 pf->offset_loaded, &os->rx_size_255,
1781 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1782 I40E_GLPRT_PRC511L(hw->port),
1783 pf->offset_loaded, &os->rx_size_511,
1785 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1786 I40E_GLPRT_PRC1023L(hw->port),
1787 pf->offset_loaded, &os->rx_size_1023,
1789 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1790 I40E_GLPRT_PRC1522L(hw->port),
1791 pf->offset_loaded, &os->rx_size_1522,
1793 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1794 I40E_GLPRT_PRC9522L(hw->port),
1795 pf->offset_loaded, &os->rx_size_big,
1797 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1798 pf->offset_loaded, &os->rx_undersize,
1800 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1801 pf->offset_loaded, &os->rx_fragments,
1803 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1804 pf->offset_loaded, &os->rx_oversize,
1806 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1807 pf->offset_loaded, &os->rx_jabber,
1809 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1810 I40E_GLPRT_PTC64L(hw->port),
1811 pf->offset_loaded, &os->tx_size_64,
1813 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1814 I40E_GLPRT_PTC127L(hw->port),
1815 pf->offset_loaded, &os->tx_size_127,
1817 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1818 I40E_GLPRT_PTC255L(hw->port),
1819 pf->offset_loaded, &os->tx_size_255,
1821 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1822 I40E_GLPRT_PTC511L(hw->port),
1823 pf->offset_loaded, &os->tx_size_511,
1825 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1826 I40E_GLPRT_PTC1023L(hw->port),
1827 pf->offset_loaded, &os->tx_size_1023,
1829 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1830 I40E_GLPRT_PTC1522L(hw->port),
1831 pf->offset_loaded, &os->tx_size_1522,
1833 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1834 I40E_GLPRT_PTC9522L(hw->port),
1835 pf->offset_loaded, &os->tx_size_big,
1837 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
1839 &os->fd_sb_match, &ns->fd_sb_match);
1840 /* GLPRT_MSPDC not supported */
1841 /* GLPRT_XEC not supported */
1843 pf->offset_loaded = true;
1846 i40e_update_vsi_stats(pf->main_vsi);
1849 /* Get all statistics of a port */
1851 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1853 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1854 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1855 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1858 /* call read registers - updates values, now write them to struct */
1859 i40e_read_stats_registers(pf, hw);
1861 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
1862 pf->main_vsi->eth_stats.rx_multicast +
1863 pf->main_vsi->eth_stats.rx_broadcast -
1864 pf->main_vsi->eth_stats.rx_discards;
1865 stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
1866 pf->main_vsi->eth_stats.tx_multicast +
1867 pf->main_vsi->eth_stats.tx_broadcast;
1868 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes;
1869 stats->obytes = pf->main_vsi->eth_stats.tx_bytes;
1870 stats->oerrors = ns->eth.tx_errors +
1871 pf->main_vsi->eth_stats.tx_errors;
1872 stats->imcasts = pf->main_vsi->eth_stats.rx_multicast;
1873 stats->fdirmatch = ns->fd_sb_match;
1876 stats->ibadcrc = ns->crc_errors;
1877 stats->ibadlen = ns->rx_length_errors + ns->rx_undersize +
1878 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
1879 stats->imissed = ns->eth.rx_discards +
1880 pf->main_vsi->eth_stats.rx_discards;
1881 stats->ierrors = stats->ibadcrc + stats->ibadlen + stats->imissed;
1883 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
1884 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
1885 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
1886 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
1887 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
1888 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
1889 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1890 ns->eth.rx_unknown_protocol);
1891 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
1892 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
1893 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
1894 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
1895 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
1896 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
1898 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
1899 ns->tx_dropped_link_down);
1900 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
1901 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
1903 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
1904 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
1905 ns->mac_local_faults);
1906 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
1907 ns->mac_remote_faults);
1908 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
1909 ns->rx_length_errors);
1910 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
1911 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
1912 for (i = 0; i < 8; i++) {
1913 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
1914 i, ns->priority_xon_rx[i]);
1915 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
1916 i, ns->priority_xoff_rx[i]);
1918 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
1919 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
1920 for (i = 0; i < 8; i++) {
1921 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
1922 i, ns->priority_xon_tx[i]);
1923 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
1924 i, ns->priority_xoff_tx[i]);
1925 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
1926 i, ns->priority_xon_2_xoff[i]);
1928 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
1929 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
1930 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
1931 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
1932 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
1933 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
1934 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
1935 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
1936 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
1937 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
1938 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
1939 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
1940 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
1941 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
1942 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
1943 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
1944 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
1945 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
1946 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
1947 ns->mac_short_packet_dropped);
1948 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
1949 ns->checksum_error);
1950 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
1951 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
1955 i40e_dev_xstats_reset(struct rte_eth_dev *dev)
1957 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1958 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1959 struct i40e_hw_port_stats *hw_stats = &pf->stats;
1961 /* The hw registers are cleared on read */
1962 pf->offset_loaded = false;
1963 i40e_read_stats_registers(pf, hw);
1965 /* reset software counters */
1966 memset(hw_stats, 0, sizeof(*hw_stats));
1970 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
1973 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1974 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1975 unsigned i, count = 0;
1976 struct i40e_hw_port_stats *hw_stats = &pf->stats;
1978 if (n < I40E_NB_XSTATS)
1979 return I40E_NB_XSTATS;
1981 i40e_read_stats_registers(pf, hw);
1987 /* Get stats from i40e_eth_stats struct */
1988 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
1989 snprintf(xstats[count].name, sizeof(xstats[count].name),
1990 "%s", rte_i40e_stats_strings[i].name);
1991 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
1992 rte_i40e_stats_strings[i].offset);
1996 /* Get individiual stats from i40e_hw_port struct */
1997 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
1998 snprintf(xstats[count].name, sizeof(xstats[count].name),
1999 "%s", rte_i40e_hw_port_strings[i].name);
2000 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2001 rte_i40e_hw_port_strings[i].offset);
2005 /* Get per-queue stats from i40e_hw_port struct */
2006 for (i = 0; i < 8; i++) {
2007 snprintf(xstats[count].name, sizeof(xstats[count].name),
2008 "rx_q%u_xon_priority_packets", i);
2009 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2010 offsetof(struct i40e_hw_port_stats,
2011 priority_xon_rx[i]));
2014 snprintf(xstats[count].name, sizeof(xstats[count].name),
2015 "rx_q%u_xoff_priority_packets", i);
2016 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2017 offsetof(struct i40e_hw_port_stats,
2018 priority_xoff_rx[i]));
2021 snprintf(xstats[count].name, sizeof(xstats[count].name),
2022 "tx_q%u_xon_priority_packets", i);
2023 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2024 offsetof(struct i40e_hw_port_stats,
2025 priority_xon_tx[i]));
2028 snprintf(xstats[count].name, sizeof(xstats[count].name),
2029 "tx_q%u_xoff_priority_packets", i);
2030 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2031 offsetof(struct i40e_hw_port_stats,
2032 priority_xoff_tx[i]));
2035 snprintf(xstats[count].name, sizeof(xstats[count].name),
2036 "xx_q%u_xon_to_xoff_priority_packets", i);
2037 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2038 offsetof(struct i40e_hw_port_stats,
2039 priority_xon_2_xoff[i]));
2043 return I40E_NB_XSTATS;
2046 /* Reset the statistics */
2048 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2050 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2052 /* It results in reloading the start point of each counter */
2053 pf->offset_loaded = false;
2057 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2058 __rte_unused uint16_t queue_id,
2059 __rte_unused uint8_t stat_idx,
2060 __rte_unused uint8_t is_rx)
2062 PMD_INIT_FUNC_TRACE();
2068 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2070 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2071 struct i40e_vsi *vsi = pf->main_vsi;
2073 dev_info->max_rx_queues = vsi->nb_qps;
2074 dev_info->max_tx_queues = vsi->nb_qps;
2075 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2076 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2077 dev_info->max_mac_addrs = vsi->max_macaddrs;
2078 dev_info->max_vfs = dev->pci_dev->max_vfs;
2079 dev_info->rx_offload_capa =
2080 DEV_RX_OFFLOAD_VLAN_STRIP |
2081 DEV_RX_OFFLOAD_QINQ_STRIP |
2082 DEV_RX_OFFLOAD_IPV4_CKSUM |
2083 DEV_RX_OFFLOAD_UDP_CKSUM |
2084 DEV_RX_OFFLOAD_TCP_CKSUM;
2085 dev_info->tx_offload_capa =
2086 DEV_TX_OFFLOAD_VLAN_INSERT |
2087 DEV_TX_OFFLOAD_QINQ_INSERT |
2088 DEV_TX_OFFLOAD_IPV4_CKSUM |
2089 DEV_TX_OFFLOAD_UDP_CKSUM |
2090 DEV_TX_OFFLOAD_TCP_CKSUM |
2091 DEV_TX_OFFLOAD_SCTP_CKSUM |
2092 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2093 DEV_TX_OFFLOAD_TCP_TSO;
2094 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2096 dev_info->reta_size = pf->hash_lut_size;
2097 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2099 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2101 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2102 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2103 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2105 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2109 dev_info->default_txconf = (struct rte_eth_txconf) {
2111 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2112 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2113 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2115 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2116 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2117 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2118 ETH_TXQ_FLAGS_NOOFFLOADS,
2121 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2122 .nb_max = I40E_MAX_RING_DESC,
2123 .nb_min = I40E_MIN_RING_DESC,
2124 .nb_align = I40E_ALIGN_RING_DESC,
2127 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2128 .nb_max = I40E_MAX_RING_DESC,
2129 .nb_min = I40E_MIN_RING_DESC,
2130 .nb_align = I40E_ALIGN_RING_DESC,
2133 if (pf->flags & I40E_FLAG_VMDQ) {
2134 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2135 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2136 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2137 pf->max_nb_vmdq_vsi;
2138 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2139 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2140 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2145 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2147 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2148 struct i40e_vsi *vsi = pf->main_vsi;
2149 PMD_INIT_FUNC_TRACE();
2152 return i40e_vsi_add_vlan(vsi, vlan_id);
2154 return i40e_vsi_delete_vlan(vsi, vlan_id);
2158 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
2159 __rte_unused uint16_t tpid)
2161 PMD_INIT_FUNC_TRACE();
2165 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2167 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2168 struct i40e_vsi *vsi = pf->main_vsi;
2170 if (mask & ETH_VLAN_STRIP_MASK) {
2171 /* Enable or disable VLAN stripping */
2172 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2173 i40e_vsi_config_vlan_stripping(vsi, TRUE);
2175 i40e_vsi_config_vlan_stripping(vsi, FALSE);
2178 if (mask & ETH_VLAN_EXTEND_MASK) {
2179 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2180 i40e_vsi_config_double_vlan(vsi, TRUE);
2182 i40e_vsi_config_double_vlan(vsi, FALSE);
2187 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2188 __rte_unused uint16_t queue,
2189 __rte_unused int on)
2191 PMD_INIT_FUNC_TRACE();
2195 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2197 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2198 struct i40e_vsi *vsi = pf->main_vsi;
2199 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2200 struct i40e_vsi_vlan_pvid_info info;
2202 memset(&info, 0, sizeof(info));
2205 info.config.pvid = pvid;
2207 info.config.reject.tagged =
2208 data->dev_conf.txmode.hw_vlan_reject_tagged;
2209 info.config.reject.untagged =
2210 data->dev_conf.txmode.hw_vlan_reject_untagged;
2213 return i40e_vsi_vlan_pvid_set(vsi, &info);
2217 i40e_dev_led_on(struct rte_eth_dev *dev)
2219 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2220 uint32_t mode = i40e_led_get(hw);
2223 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2229 i40e_dev_led_off(struct rte_eth_dev *dev)
2231 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2232 uint32_t mode = i40e_led_get(hw);
2235 i40e_led_set(hw, 0, false);
2241 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2243 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2244 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2246 fc_conf->pause_time = pf->fc_conf.pause_time;
2247 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2248 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2250 /* Return current mode according to actual setting*/
2251 switch (hw->fc.current_mode) {
2253 fc_conf->mode = RTE_FC_FULL;
2255 case I40E_FC_TX_PAUSE:
2256 fc_conf->mode = RTE_FC_TX_PAUSE;
2258 case I40E_FC_RX_PAUSE:
2259 fc_conf->mode = RTE_FC_RX_PAUSE;
2263 fc_conf->mode = RTE_FC_NONE;
2270 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2272 uint32_t mflcn_reg, fctrl_reg, reg;
2273 uint32_t max_high_water;
2274 uint8_t i, aq_failure;
2278 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2279 [RTE_FC_NONE] = I40E_FC_NONE,
2280 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2281 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2282 [RTE_FC_FULL] = I40E_FC_FULL
2285 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2287 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2288 if ((fc_conf->high_water > max_high_water) ||
2289 (fc_conf->high_water < fc_conf->low_water)) {
2290 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2291 "High_water must <= %d.", max_high_water);
2295 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2296 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2297 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2299 pf->fc_conf.pause_time = fc_conf->pause_time;
2300 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2301 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2303 PMD_INIT_FUNC_TRACE();
2305 /* All the link flow control related enable/disable register
2306 * configuration is handle by the F/W
2308 err = i40e_set_fc(hw, &aq_failure, true);
2312 if (i40e_is_40G_device(hw->device_id)) {
2313 /* Configure flow control refresh threshold,
2314 * the value for stat_tx_pause_refresh_timer[8]
2315 * is used for global pause operation.
2319 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2320 pf->fc_conf.pause_time);
2322 /* configure the timer value included in transmitted pause
2324 * the value for stat_tx_pause_quanta[8] is used for global
2327 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2328 pf->fc_conf.pause_time);
2330 fctrl_reg = I40E_READ_REG(hw,
2331 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2333 if (fc_conf->mac_ctrl_frame_fwd != 0)
2334 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2336 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2338 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2341 /* Configure pause time (2 TCs per register) */
2342 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2343 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2344 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2346 /* Configure flow control refresh threshold value */
2347 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2348 pf->fc_conf.pause_time / 2);
2350 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2352 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2353 *depending on configuration
2355 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2356 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2357 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2359 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2360 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2363 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2366 /* config the water marker both based on the packets and bytes */
2367 I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2368 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2369 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2370 I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2371 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2372 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2373 I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2374 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2376 I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2377 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2380 I40E_WRITE_FLUSH(hw);
2386 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2387 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2389 PMD_INIT_FUNC_TRACE();
2394 /* Add a MAC address, and update filters */
2396 i40e_macaddr_add(struct rte_eth_dev *dev,
2397 struct ether_addr *mac_addr,
2398 __rte_unused uint32_t index,
2401 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2402 struct i40e_mac_filter_info mac_filter;
2403 struct i40e_vsi *vsi;
2406 /* If VMDQ not enabled or configured, return */
2407 if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
2408 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2409 pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
2414 if (pool > pf->nb_cfg_vmdq_vsi) {
2415 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2416 pool, pf->nb_cfg_vmdq_vsi);
2420 (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2421 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2426 vsi = pf->vmdq[pool - 1].vsi;
2428 ret = i40e_vsi_add_mac(vsi, &mac_filter);
2429 if (ret != I40E_SUCCESS) {
2430 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2435 /* Remove a MAC address, and update filters */
2437 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2439 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2440 struct i40e_vsi *vsi;
2441 struct rte_eth_dev_data *data = dev->data;
2442 struct ether_addr *macaddr;
2447 macaddr = &(data->mac_addrs[index]);
2449 pool_sel = dev->data->mac_pool_sel[index];
2451 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
2452 if (pool_sel & (1ULL << i)) {
2456 /* No VMDQ pool enabled or configured */
2457 if (!(pf->flags | I40E_FLAG_VMDQ) ||
2458 (i > pf->nb_cfg_vmdq_vsi)) {
2459 PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
2463 vsi = pf->vmdq[i - 1].vsi;
2465 ret = i40e_vsi_delete_mac(vsi, macaddr);
2468 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
2475 /* Set perfect match or hash match of MAC and VLAN for a VF */
2477 i40e_vf_mac_filter_set(struct i40e_pf *pf,
2478 struct rte_eth_mac_filter *filter,
2482 struct i40e_mac_filter_info mac_filter;
2483 struct ether_addr old_mac;
2484 struct ether_addr *new_mac;
2485 struct i40e_pf_vf *vf = NULL;
2490 PMD_DRV_LOG(ERR, "Invalid PF argument.");
2493 hw = I40E_PF_TO_HW(pf);
2495 if (filter == NULL) {
2496 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
2500 new_mac = &filter->mac_addr;
2502 if (is_zero_ether_addr(new_mac)) {
2503 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
2507 vf_id = filter->dst_id;
2509 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
2510 PMD_DRV_LOG(ERR, "Invalid argument.");
2513 vf = &pf->vfs[vf_id];
2515 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
2516 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
2521 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
2522 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
2524 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
2527 mac_filter.filter_type = filter->filter_type;
2528 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
2529 if (ret != I40E_SUCCESS) {
2530 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
2533 ether_addr_copy(new_mac, &pf->dev_addr);
2535 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
2537 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
2538 if (ret != I40E_SUCCESS) {
2539 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
2543 /* Clear device address as it has been removed */
2544 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
2545 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
2551 /* MAC filter handle */
2553 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
2556 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2557 struct rte_eth_mac_filter *filter;
2558 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2559 int ret = I40E_NOT_SUPPORTED;
2561 filter = (struct rte_eth_mac_filter *)(arg);
2563 switch (filter_op) {
2564 case RTE_ETH_FILTER_NOP:
2567 case RTE_ETH_FILTER_ADD:
2568 i40e_pf_disable_irq0(hw);
2570 ret = i40e_vf_mac_filter_set(pf, filter, 1);
2571 i40e_pf_enable_irq0(hw);
2573 case RTE_ETH_FILTER_DELETE:
2574 i40e_pf_disable_irq0(hw);
2576 ret = i40e_vf_mac_filter_set(pf, filter, 0);
2577 i40e_pf_enable_irq0(hw);
2580 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2581 ret = I40E_ERR_PARAM;
2589 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2591 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2592 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2598 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2599 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
2602 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2606 uint32_t *lut_dw = (uint32_t *)lut;
2607 uint16_t i, lut_size_dw = lut_size / 4;
2609 for (i = 0; i < lut_size_dw; i++)
2610 lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
2617 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2619 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2620 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2626 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2627 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
2630 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2634 uint32_t *lut_dw = (uint32_t *)lut;
2635 uint16_t i, lut_size_dw = lut_size / 4;
2637 for (i = 0; i < lut_size_dw; i++)
2638 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
2639 I40E_WRITE_FLUSH(hw);
2646 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
2647 struct rte_eth_rss_reta_entry64 *reta_conf,
2650 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2651 uint16_t i, lut_size = pf->hash_lut_size;
2652 uint16_t idx, shift;
2656 if (reta_size != lut_size ||
2657 reta_size > ETH_RSS_RETA_SIZE_512) {
2658 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2659 "(%d) doesn't match the number hardware can supported "
2660 "(%d)\n", reta_size, lut_size);
2664 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2666 PMD_DRV_LOG(ERR, "No memory can be allocated");
2669 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2672 for (i = 0; i < reta_size; i++) {
2673 idx = i / RTE_RETA_GROUP_SIZE;
2674 shift = i % RTE_RETA_GROUP_SIZE;
2675 if (reta_conf[idx].mask & (1ULL << shift))
2676 lut[i] = reta_conf[idx].reta[shift];
2678 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
2687 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
2688 struct rte_eth_rss_reta_entry64 *reta_conf,
2691 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2692 uint16_t i, lut_size = pf->hash_lut_size;
2693 uint16_t idx, shift;
2697 if (reta_size != lut_size ||
2698 reta_size > ETH_RSS_RETA_SIZE_512) {
2699 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2700 "(%d) doesn't match the number hardware can supported "
2701 "(%d)\n", reta_size, lut_size);
2705 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2707 PMD_DRV_LOG(ERR, "No memory can be allocated");
2711 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2714 for (i = 0; i < reta_size; i++) {
2715 idx = i / RTE_RETA_GROUP_SIZE;
2716 shift = i % RTE_RETA_GROUP_SIZE;
2717 if (reta_conf[idx].mask & (1ULL << shift))
2718 reta_conf[idx].reta[shift] = lut[i];
2728 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
2729 * @hw: pointer to the HW structure
2730 * @mem: pointer to mem struct to fill out
2731 * @size: size of memory requested
2732 * @alignment: what to align the allocation to
2734 enum i40e_status_code
2735 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2736 struct i40e_dma_mem *mem,
2740 static uint64_t id = 0;
2741 const struct rte_memzone *mz = NULL;
2742 char z_name[RTE_MEMZONE_NAMESIZE];
2745 return I40E_ERR_PARAM;
2748 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
2749 #ifdef RTE_LIBRTE_XEN_DOM0
2750 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
2751 alignment, RTE_PGSIZE_2M);
2753 mz = rte_memzone_reserve_aligned(z_name, size, SOCKET_ID_ANY, 0,
2757 return I40E_ERR_NO_MEMORY;
2762 #ifdef RTE_LIBRTE_XEN_DOM0
2763 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
2765 mem->pa = mz->phys_addr;
2768 return I40E_SUCCESS;
2772 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
2773 * @hw: pointer to the HW structure
2774 * @mem: ptr to mem struct to free
2776 enum i40e_status_code
2777 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2778 struct i40e_dma_mem *mem)
2780 if (!mem || !mem->va)
2781 return I40E_ERR_PARAM;
2786 return I40E_SUCCESS;
2790 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
2791 * @hw: pointer to the HW structure
2792 * @mem: pointer to mem struct to fill out
2793 * @size: size of memory requested
2795 enum i40e_status_code
2796 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2797 struct i40e_virt_mem *mem,
2801 return I40E_ERR_PARAM;
2804 mem->va = rte_zmalloc("i40e", size, 0);
2807 return I40E_SUCCESS;
2809 return I40E_ERR_NO_MEMORY;
2813 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
2814 * @hw: pointer to the HW structure
2815 * @mem: pointer to mem struct to free
2817 enum i40e_status_code
2818 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2819 struct i40e_virt_mem *mem)
2822 return I40E_ERR_PARAM;
2827 return I40E_SUCCESS;
2831 i40e_init_spinlock_d(struct i40e_spinlock *sp)
2833 rte_spinlock_init(&sp->spinlock);
2837 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
2839 rte_spinlock_lock(&sp->spinlock);
2843 i40e_release_spinlock_d(struct i40e_spinlock *sp)
2845 rte_spinlock_unlock(&sp->spinlock);
2849 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
2855 * Get the hardware capabilities, which will be parsed
2856 * and saved into struct i40e_hw.
2859 i40e_get_cap(struct i40e_hw *hw)
2861 struct i40e_aqc_list_capabilities_element_resp *buf;
2862 uint16_t len, size = 0;
2865 /* Calculate a huge enough buff for saving response data temporarily */
2866 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
2867 I40E_MAX_CAP_ELE_NUM;
2868 buf = rte_zmalloc("i40e", len, 0);
2870 PMD_DRV_LOG(ERR, "Failed to allocate memory");
2871 return I40E_ERR_NO_MEMORY;
2874 /* Get, parse the capabilities and save it to hw */
2875 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
2876 i40e_aqc_opc_list_func_capabilities, NULL);
2877 if (ret != I40E_SUCCESS)
2878 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
2880 /* Free the temporary buffer after being used */
2887 i40e_pf_parameter_init(struct rte_eth_dev *dev)
2889 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2890 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2891 uint16_t qp_count = 0, vsi_count = 0;
2893 if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
2894 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
2897 /* Add the parameter init for LFC */
2898 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
2899 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
2900 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
2902 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
2903 pf->max_num_vsi = hw->func_caps.num_vsis;
2904 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
2905 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2906 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
2908 /* FDir queue/VSI allocation */
2909 pf->fdir_qp_offset = 0;
2910 if (hw->func_caps.fd) {
2911 pf->flags |= I40E_FLAG_FDIR;
2912 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
2914 pf->fdir_nb_qps = 0;
2916 qp_count += pf->fdir_nb_qps;
2919 /* LAN queue/VSI allocation */
2920 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
2921 if (!hw->func_caps.rss) {
2924 pf->flags |= I40E_FLAG_RSS;
2925 if (hw->mac.type == I40E_MAC_X722)
2926 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
2927 pf->lan_nb_qps = pf->lan_nb_qp_max;
2929 qp_count += pf->lan_nb_qps;
2932 /* VF queue/VSI allocation */
2933 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
2934 if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
2935 pf->flags |= I40E_FLAG_SRIOV;
2936 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
2937 pf->vf_num = dev->pci_dev->max_vfs;
2938 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
2939 "in total %u queues", pf->vf_num, pf->vf_nb_qps,
2940 pf->vf_nb_qps * pf->vf_num);
2945 qp_count += pf->vf_nb_qps * pf->vf_num;
2946 vsi_count += pf->vf_num;
2948 /* VMDq queue/VSI allocation */
2949 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
2950 if (hw->func_caps.vmdq) {
2951 pf->flags |= I40E_FLAG_VMDQ;
2952 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
2953 pf->max_nb_vmdq_vsi = 1;
2954 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues per VMDQ VSI, "
2955 "in total %u queues", pf->max_nb_vmdq_vsi,
2957 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
2959 pf->vmdq_nb_qps = 0;
2960 pf->max_nb_vmdq_vsi = 0;
2962 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
2963 vsi_count += pf->max_nb_vmdq_vsi;
2965 if (hw->func_caps.dcb)
2966 pf->flags |= I40E_FLAG_DCB;
2968 if (qp_count > hw->func_caps.num_tx_qp) {
2969 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
2970 "the hardware maximum %u", qp_count,
2971 hw->func_caps.num_tx_qp);
2974 if (vsi_count > hw->func_caps.num_vsis) {
2975 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
2976 "the hardware maximum %u", vsi_count,
2977 hw->func_caps.num_vsis);
2985 i40e_pf_get_switch_config(struct i40e_pf *pf)
2987 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2988 struct i40e_aqc_get_switch_config_resp *switch_config;
2989 struct i40e_aqc_switch_config_element_resp *element;
2990 uint16_t start_seid = 0, num_reported;
2993 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
2994 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
2995 if (!switch_config) {
2996 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3000 /* Get the switch configurations */
3001 ret = i40e_aq_get_switch_config(hw, switch_config,
3002 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3003 if (ret != I40E_SUCCESS) {
3004 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3007 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3008 if (num_reported != 1) { /* The number should be 1 */
3009 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3013 /* Parse the switch configuration elements */
3014 element = &(switch_config->element[0]);
3015 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3016 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3017 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3019 PMD_DRV_LOG(INFO, "Unknown element type");
3022 rte_free(switch_config);
3028 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3031 struct pool_entry *entry;
3033 if (pool == NULL || num == 0)
3036 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3037 if (entry == NULL) {
3038 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3042 /* queue heap initialize */
3043 pool->num_free = num;
3044 pool->num_alloc = 0;
3046 LIST_INIT(&pool->alloc_list);
3047 LIST_INIT(&pool->free_list);
3049 /* Initialize element */
3053 LIST_INSERT_HEAD(&pool->free_list, entry, next);
3058 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3060 struct pool_entry *entry;
3065 LIST_FOREACH(entry, &pool->alloc_list, next) {
3066 LIST_REMOVE(entry, next);
3070 LIST_FOREACH(entry, &pool->free_list, next) {
3071 LIST_REMOVE(entry, next);
3076 pool->num_alloc = 0;
3078 LIST_INIT(&pool->alloc_list);
3079 LIST_INIT(&pool->free_list);
3083 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3086 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3087 uint32_t pool_offset;
3091 PMD_DRV_LOG(ERR, "Invalid parameter");
3095 pool_offset = base - pool->base;
3096 /* Lookup in alloc list */
3097 LIST_FOREACH(entry, &pool->alloc_list, next) {
3098 if (entry->base == pool_offset) {
3099 valid_entry = entry;
3100 LIST_REMOVE(entry, next);
3105 /* Not find, return */
3106 if (valid_entry == NULL) {
3107 PMD_DRV_LOG(ERR, "Failed to find entry");
3112 * Found it, move it to free list and try to merge.
3113 * In order to make merge easier, always sort it by qbase.
3114 * Find adjacent prev and last entries.
3117 LIST_FOREACH(entry, &pool->free_list, next) {
3118 if (entry->base > valid_entry->base) {
3126 /* Try to merge with next one*/
3128 /* Merge with next one */
3129 if (valid_entry->base + valid_entry->len == next->base) {
3130 next->base = valid_entry->base;
3131 next->len += valid_entry->len;
3132 rte_free(valid_entry);
3139 /* Merge with previous one */
3140 if (prev->base + prev->len == valid_entry->base) {
3141 prev->len += valid_entry->len;
3142 /* If it merge with next one, remove next node */
3144 LIST_REMOVE(valid_entry, next);
3145 rte_free(valid_entry);
3147 rte_free(valid_entry);
3153 /* Not find any entry to merge, insert */
3156 LIST_INSERT_AFTER(prev, valid_entry, next);
3157 else if (next != NULL)
3158 LIST_INSERT_BEFORE(next, valid_entry, next);
3159 else /* It's empty list, insert to head */
3160 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3163 pool->num_free += valid_entry->len;
3164 pool->num_alloc -= valid_entry->len;
3170 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3173 struct pool_entry *entry, *valid_entry;
3175 if (pool == NULL || num == 0) {
3176 PMD_DRV_LOG(ERR, "Invalid parameter");
3180 if (pool->num_free < num) {
3181 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3182 num, pool->num_free);
3187 /* Lookup in free list and find most fit one */
3188 LIST_FOREACH(entry, &pool->free_list, next) {
3189 if (entry->len >= num) {
3191 if (entry->len == num) {
3192 valid_entry = entry;
3195 if (valid_entry == NULL || valid_entry->len > entry->len)
3196 valid_entry = entry;
3200 /* Not find one to satisfy the request, return */
3201 if (valid_entry == NULL) {
3202 PMD_DRV_LOG(ERR, "No valid entry found");
3206 * The entry have equal queue number as requested,
3207 * remove it from alloc_list.
3209 if (valid_entry->len == num) {
3210 LIST_REMOVE(valid_entry, next);
3213 * The entry have more numbers than requested,
3214 * create a new entry for alloc_list and minus its
3215 * queue base and number in free_list.
3217 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3218 if (entry == NULL) {
3219 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3223 entry->base = valid_entry->base;
3225 valid_entry->base += num;
3226 valid_entry->len -= num;
3227 valid_entry = entry;
3230 /* Insert it into alloc list, not sorted */
3231 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3233 pool->num_free -= valid_entry->len;
3234 pool->num_alloc += valid_entry->len;
3236 return (valid_entry->base + pool->base);
3240 * bitmap_is_subset - Check whether src2 is subset of src1
3243 bitmap_is_subset(uint8_t src1, uint8_t src2)
3245 return !((src1 ^ src2) & src2);
3249 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3251 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3253 /* If DCB is not supported, only default TC is supported */
3254 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3255 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3259 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3260 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3261 "HW support 0x%x", hw->func_caps.enabled_tcmap,
3265 return I40E_SUCCESS;
3269 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3270 struct i40e_vsi_vlan_pvid_info *info)
3273 struct i40e_vsi_context ctxt;
3274 uint8_t vlan_flags = 0;
3277 if (vsi == NULL || info == NULL) {
3278 PMD_DRV_LOG(ERR, "invalid parameters");
3279 return I40E_ERR_PARAM;
3283 vsi->info.pvid = info->config.pvid;
3285 * If insert pvid is enabled, only tagged pkts are
3286 * allowed to be sent out.
3288 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3289 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3292 if (info->config.reject.tagged == 0)
3293 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3295 if (info->config.reject.untagged == 0)
3296 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3298 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3299 I40E_AQ_VSI_PVLAN_MODE_MASK);
3300 vsi->info.port_vlan_flags |= vlan_flags;
3301 vsi->info.valid_sections =
3302 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3303 memset(&ctxt, 0, sizeof(ctxt));
3304 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3305 ctxt.seid = vsi->seid;
3307 hw = I40E_VSI_TO_HW(vsi);
3308 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3309 if (ret != I40E_SUCCESS)
3310 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3316 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3318 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3320 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3322 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3323 if (ret != I40E_SUCCESS)
3327 PMD_DRV_LOG(ERR, "seid not valid");
3331 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3332 tc_bw_data.tc_valid_bits = enabled_tcmap;
3333 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3334 tc_bw_data.tc_bw_credits[i] =
3335 (enabled_tcmap & (1 << i)) ? 1 : 0;
3337 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3338 if (ret != I40E_SUCCESS) {
3339 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3343 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3344 sizeof(vsi->info.qs_handle));
3345 return I40E_SUCCESS;
3349 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3350 struct i40e_aqc_vsi_properties_data *info,
3351 uint8_t enabled_tcmap)
3353 int ret, i, total_tc = 0;
3354 uint16_t qpnum_per_tc, bsf, qp_idx;
3356 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3357 if (ret != I40E_SUCCESS)
3360 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3361 if (enabled_tcmap & (1 << i))
3363 vsi->enabled_tc = enabled_tcmap;
3365 /* Number of queues per enabled TC */
3366 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3367 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3368 bsf = rte_bsf32(qpnum_per_tc);
3370 /* Adjust the queue number to actual queues that can be applied */
3371 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3372 vsi->nb_qps = qpnum_per_tc * total_tc;
3375 * Configure TC and queue mapping parameters, for enabled TC,
3376 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3377 * default queue will serve it.
3380 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3381 if (vsi->enabled_tc & (1 << i)) {
3382 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3383 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3384 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
3385 qp_idx += qpnum_per_tc;
3387 info->tc_mapping[i] = 0;
3390 /* Associate queue number with VSI */
3391 if (vsi->type == I40E_VSI_SRIOV) {
3392 info->mapping_flags |=
3393 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
3394 for (i = 0; i < vsi->nb_qps; i++)
3395 info->queue_mapping[i] =
3396 rte_cpu_to_le_16(vsi->base_queue + i);
3398 info->mapping_flags |=
3399 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3400 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3402 info->valid_sections |=
3403 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
3405 return I40E_SUCCESS;
3409 i40e_veb_release(struct i40e_veb *veb)
3411 struct i40e_vsi *vsi;
3414 if (veb == NULL || veb->associate_vsi == NULL)
3417 if (!TAILQ_EMPTY(&veb->head)) {
3418 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
3422 vsi = veb->associate_vsi;
3423 hw = I40E_VSI_TO_HW(vsi);
3425 vsi->uplink_seid = veb->uplink_seid;
3426 i40e_aq_delete_element(hw, veb->seid, NULL);
3429 return I40E_SUCCESS;
3433 static struct i40e_veb *
3434 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
3436 struct i40e_veb *veb;
3440 if (NULL == pf || vsi == NULL) {
3441 PMD_DRV_LOG(ERR, "veb setup failed, "
3442 "associated VSI shouldn't null");
3445 hw = I40E_PF_TO_HW(pf);
3447 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
3449 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
3453 veb->associate_vsi = vsi;
3454 TAILQ_INIT(&veb->head);
3455 veb->uplink_seid = vsi->uplink_seid;
3457 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
3458 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
3460 if (ret != I40E_SUCCESS) {
3461 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
3462 hw->aq.asq_last_status);
3466 /* get statistics index */
3467 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
3468 &veb->stats_idx, NULL, NULL, NULL);
3469 if (ret != I40E_SUCCESS) {
3470 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
3471 hw->aq.asq_last_status);
3475 /* Get VEB bandwidth, to be implemented */
3476 /* Now associated vsi binding to the VEB, set uplink to this VEB */
3477 vsi->uplink_seid = veb->seid;
3486 i40e_vsi_release(struct i40e_vsi *vsi)
3490 struct i40e_vsi_list *vsi_list;
3492 struct i40e_mac_filter *f;
3495 return I40E_SUCCESS;
3497 pf = I40E_VSI_TO_PF(vsi);
3498 hw = I40E_VSI_TO_HW(vsi);
3500 /* VSI has child to attach, release child first */
3502 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
3503 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
3505 TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
3507 i40e_veb_release(vsi->veb);
3510 /* Remove all macvlan filters of the VSI */
3511 i40e_vsi_remove_all_macvlan_filter(vsi);
3512 TAILQ_FOREACH(f, &vsi->mac_list, next)
3515 if (vsi->type != I40E_VSI_MAIN) {
3516 /* Remove vsi from parent's sibling list */
3517 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
3518 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
3519 return I40E_ERR_PARAM;
3521 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
3522 &vsi->sib_vsi_list, list);
3524 /* Remove all switch element of the VSI */
3525 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
3526 if (ret != I40E_SUCCESS)
3527 PMD_DRV_LOG(ERR, "Failed to delete element");
3529 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
3531 if (vsi->type != I40E_VSI_SRIOV)
3532 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
3535 return I40E_SUCCESS;
3539 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
3541 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3542 struct i40e_aqc_remove_macvlan_element_data def_filter;
3543 struct i40e_mac_filter_info filter;
3546 if (vsi->type != I40E_VSI_MAIN)
3547 return I40E_ERR_CONFIG;
3548 memset(&def_filter, 0, sizeof(def_filter));
3549 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
3551 def_filter.vlan_tag = 0;
3552 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
3553 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
3554 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
3555 if (ret != I40E_SUCCESS) {
3556 struct i40e_mac_filter *f;
3557 struct ether_addr *mac;
3559 PMD_DRV_LOG(WARNING, "Cannot remove the default "
3561 /* It needs to add the permanent mac into mac list */
3562 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3564 PMD_DRV_LOG(ERR, "failed to allocate memory");
3565 return I40E_ERR_NO_MEMORY;
3567 mac = &f->mac_info.mac_addr;
3568 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
3570 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3571 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3576 (void)rte_memcpy(&filter.mac_addr,
3577 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
3578 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3579 return i40e_vsi_add_mac(vsi, &filter);
3583 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
3585 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
3586 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
3587 struct i40e_hw *hw = &vsi->adapter->hw;
3591 memset(&bw_config, 0, sizeof(bw_config));
3592 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3593 if (ret != I40E_SUCCESS) {
3594 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
3595 hw->aq.asq_last_status);
3599 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
3600 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
3601 &ets_sla_config, NULL);
3602 if (ret != I40E_SUCCESS) {
3603 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
3604 "configuration %u", hw->aq.asq_last_status);
3608 /* Not store the info yet, just print out */
3609 PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
3610 PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
3611 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3612 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
3613 ets_sla_config.share_credits[i]);
3614 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
3615 rte_le_to_cpu_16(ets_sla_config.credits[i]));
3616 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
3617 rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
3626 i40e_vsi_setup(struct i40e_pf *pf,
3627 enum i40e_vsi_type type,
3628 struct i40e_vsi *uplink_vsi,
3629 uint16_t user_param)
3631 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3632 struct i40e_vsi *vsi;
3633 struct i40e_mac_filter_info filter;
3635 struct i40e_vsi_context ctxt;
3636 struct ether_addr broadcast =
3637 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
3639 if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
3640 PMD_DRV_LOG(ERR, "VSI setup failed, "
3641 "VSI link shouldn't be NULL");
3645 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
3646 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
3647 "uplink VSI should be NULL");
3651 /* If uplink vsi didn't setup VEB, create one first */
3652 if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
3653 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
3655 if (NULL == uplink_vsi->veb) {
3656 PMD_DRV_LOG(ERR, "VEB setup failed");
3661 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
3663 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
3666 TAILQ_INIT(&vsi->mac_list);
3668 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
3669 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
3670 vsi->parent_vsi = uplink_vsi;
3671 vsi->user_param = user_param;
3672 /* Allocate queues */
3673 switch (vsi->type) {
3674 case I40E_VSI_MAIN :
3675 vsi->nb_qps = pf->lan_nb_qps;
3677 case I40E_VSI_SRIOV :
3678 vsi->nb_qps = pf->vf_nb_qps;
3680 case I40E_VSI_VMDQ2:
3681 vsi->nb_qps = pf->vmdq_nb_qps;
3684 vsi->nb_qps = pf->fdir_nb_qps;
3690 * The filter status descriptor is reported in rx queue 0,
3691 * while the tx queue for fdir filter programming has no
3692 * such constraints, can be non-zero queues.
3693 * To simplify it, choose FDIR vsi use queue 0 pair.
3694 * To make sure it will use queue 0 pair, queue allocation
3695 * need be done before this function is called
3697 if (type != I40E_VSI_FDIR) {
3698 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
3700 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
3704 vsi->base_queue = ret;
3706 vsi->base_queue = I40E_FDIR_QUEUE_ID;
3708 /* VF has MSIX interrupt in VF range, don't allocate here */
3709 if (type != I40E_VSI_SRIOV) {
3710 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
3712 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
3713 goto fail_queue_alloc;
3715 vsi->msix_intr = ret;
3719 if (type == I40E_VSI_MAIN) {
3720 /* For main VSI, no need to add since it's default one */
3721 vsi->uplink_seid = pf->mac_seid;
3722 vsi->seid = pf->main_vsi_seid;
3723 /* Bind queues with specific MSIX interrupt */
3725 * Needs 2 interrupt at least, one for misc cause which will
3726 * enabled from OS side, Another for queues binding the
3727 * interrupt from device side only.
3730 /* Get default VSI parameters from hardware */
3731 memset(&ctxt, 0, sizeof(ctxt));
3732 ctxt.seid = vsi->seid;
3733 ctxt.pf_num = hw->pf_id;
3734 ctxt.uplink_seid = vsi->uplink_seid;
3736 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
3737 if (ret != I40E_SUCCESS) {
3738 PMD_DRV_LOG(ERR, "Failed to get VSI params");
3739 goto fail_msix_alloc;
3741 (void)rte_memcpy(&vsi->info, &ctxt.info,
3742 sizeof(struct i40e_aqc_vsi_properties_data));
3743 vsi->vsi_id = ctxt.vsi_number;
3744 vsi->info.valid_sections = 0;
3746 /* Configure tc, enabled TC0 only */
3747 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
3749 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
3750 goto fail_msix_alloc;
3753 /* TC, queue mapping */
3754 memset(&ctxt, 0, sizeof(ctxt));
3755 vsi->info.valid_sections |=
3756 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3757 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
3758 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3759 (void)rte_memcpy(&ctxt.info, &vsi->info,
3760 sizeof(struct i40e_aqc_vsi_properties_data));
3761 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3762 I40E_DEFAULT_TCMAP);
3763 if (ret != I40E_SUCCESS) {
3764 PMD_DRV_LOG(ERR, "Failed to configure "
3765 "TC queue mapping");
3766 goto fail_msix_alloc;
3768 ctxt.seid = vsi->seid;
3769 ctxt.pf_num = hw->pf_id;
3770 ctxt.uplink_seid = vsi->uplink_seid;
3773 /* Update VSI parameters */
3774 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3775 if (ret != I40E_SUCCESS) {
3776 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3777 goto fail_msix_alloc;
3780 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
3781 sizeof(vsi->info.tc_mapping));
3782 (void)rte_memcpy(&vsi->info.queue_mapping,
3783 &ctxt.info.queue_mapping,
3784 sizeof(vsi->info.queue_mapping));
3785 vsi->info.mapping_flags = ctxt.info.mapping_flags;
3786 vsi->info.valid_sections = 0;
3788 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
3792 * Updating default filter settings are necessary to prevent
3793 * reception of tagged packets.
3794 * Some old firmware configurations load a default macvlan
3795 * filter which accepts both tagged and untagged packets.
3796 * The updating is to use a normal filter instead if needed.
3797 * For NVM 4.2.2 or after, the updating is not needed anymore.
3798 * The firmware with correct configurations load the default
3799 * macvlan filter which is expected and cannot be removed.
3801 i40e_update_default_filter_setting(vsi);
3802 i40e_config_qinq(hw, vsi);
3803 } else if (type == I40E_VSI_SRIOV) {
3804 memset(&ctxt, 0, sizeof(ctxt));
3806 * For other VSI, the uplink_seid equals to uplink VSI's
3807 * uplink_seid since they share same VEB
3809 vsi->uplink_seid = uplink_vsi->uplink_seid;
3810 ctxt.pf_num = hw->pf_id;
3811 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
3812 ctxt.uplink_seid = vsi->uplink_seid;
3813 ctxt.connection_type = 0x1;
3814 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
3817 * Do not configure switch ID to enable VEB switch by
3818 * I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB. Because in Fortville,
3819 * if the source mac address of packet sent from VF is not
3820 * listed in the VEB's mac table, the VEB will switch the
3821 * packet back to the VF. Need to enable it when HW issue
3825 /* Configure port/vlan */
3826 ctxt.info.valid_sections |=
3827 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3828 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3829 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3830 I40E_DEFAULT_TCMAP);
3831 if (ret != I40E_SUCCESS) {
3832 PMD_DRV_LOG(ERR, "Failed to configure "
3833 "TC queue mapping");
3834 goto fail_msix_alloc;
3836 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3837 ctxt.info.valid_sections |=
3838 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3840 * Since VSI is not created yet, only configure parameter,
3841 * will add vsi below.
3844 i40e_config_qinq(hw, vsi);
3845 } else if (type == I40E_VSI_VMDQ2) {
3846 memset(&ctxt, 0, sizeof(ctxt));
3848 * For other VSI, the uplink_seid equals to uplink VSI's
3849 * uplink_seid since they share same VEB
3851 vsi->uplink_seid = uplink_vsi->uplink_seid;
3852 ctxt.pf_num = hw->pf_id;
3854 ctxt.uplink_seid = vsi->uplink_seid;
3855 ctxt.connection_type = 0x1;
3856 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
3858 ctxt.info.valid_sections |=
3859 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3860 /* user_param carries flag to enable loop back */
3862 ctxt.info.switch_id =
3863 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
3864 ctxt.info.switch_id |=
3865 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3868 /* Configure port/vlan */
3869 ctxt.info.valid_sections |=
3870 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3871 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3872 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3873 I40E_DEFAULT_TCMAP);
3874 if (ret != I40E_SUCCESS) {
3875 PMD_DRV_LOG(ERR, "Failed to configure "
3876 "TC queue mapping");
3877 goto fail_msix_alloc;
3879 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3880 ctxt.info.valid_sections |=
3881 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3882 } else if (type == I40E_VSI_FDIR) {
3883 memset(&ctxt, 0, sizeof(ctxt));
3884 vsi->uplink_seid = uplink_vsi->uplink_seid;
3885 ctxt.pf_num = hw->pf_id;
3887 ctxt.uplink_seid = vsi->uplink_seid;
3888 ctxt.connection_type = 0x1; /* regular data port */
3889 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
3890 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3891 I40E_DEFAULT_TCMAP);
3892 if (ret != I40E_SUCCESS) {
3893 PMD_DRV_LOG(ERR, "Failed to configure "
3894 "TC queue mapping.");
3895 goto fail_msix_alloc;
3897 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3898 ctxt.info.valid_sections |=
3899 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3901 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
3902 goto fail_msix_alloc;
3905 if (vsi->type != I40E_VSI_MAIN) {
3906 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
3907 if (ret != I40E_SUCCESS) {
3908 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
3909 hw->aq.asq_last_status);
3910 goto fail_msix_alloc;
3912 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
3913 vsi->info.valid_sections = 0;
3914 vsi->seid = ctxt.seid;
3915 vsi->vsi_id = ctxt.vsi_number;
3916 vsi->sib_vsi_list.vsi = vsi;
3917 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
3918 &vsi->sib_vsi_list, list);
3921 /* MAC/VLAN configuration */
3922 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
3923 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3925 ret = i40e_vsi_add_mac(vsi, &filter);
3926 if (ret != I40E_SUCCESS) {
3927 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3928 goto fail_msix_alloc;
3931 /* Get VSI BW information */
3932 i40e_vsi_dump_bw_config(vsi);
3935 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
3937 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
3943 /* Configure vlan stripping on or off */
3945 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
3947 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3948 struct i40e_vsi_context ctxt;
3950 int ret = I40E_SUCCESS;
3952 /* Check if it has been already on or off */
3953 if (vsi->info.valid_sections &
3954 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
3956 if ((vsi->info.port_vlan_flags &
3957 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
3958 return 0; /* already on */
3960 if ((vsi->info.port_vlan_flags &
3961 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
3962 I40E_AQ_VSI_PVLAN_EMOD_MASK)
3963 return 0; /* already off */
3968 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3970 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
3971 vsi->info.valid_sections =
3972 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3973 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
3974 vsi->info.port_vlan_flags |= vlan_flags;
3975 ctxt.seid = vsi->seid;
3976 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3977 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3979 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3980 on ? "enable" : "disable");
3986 i40e_dev_init_vlan(struct rte_eth_dev *dev)
3988 struct rte_eth_dev_data *data = dev->data;
3991 /* Apply vlan offload setting */
3992 i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
3994 /* Apply double-vlan setting, not implemented yet */
3996 /* Apply pvid setting */
3997 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
3998 data->dev_conf.txmode.hw_vlan_insert_pvid);
4000 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4006 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4008 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4010 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4014 i40e_update_flow_control(struct i40e_hw *hw)
4016 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4017 struct i40e_link_status link_status;
4018 uint32_t rxfc = 0, txfc = 0, reg;
4022 memset(&link_status, 0, sizeof(link_status));
4023 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4024 if (ret != I40E_SUCCESS) {
4025 PMD_DRV_LOG(ERR, "Failed to get link status information");
4026 goto write_reg; /* Disable flow control */
4029 an_info = hw->phy.link_info.an_info;
4030 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4031 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4032 ret = I40E_ERR_NOT_READY;
4033 goto write_reg; /* Disable flow control */
4036 * If link auto negotiation is enabled, flow control needs to
4037 * be configured according to it
4039 switch (an_info & I40E_LINK_PAUSE_RXTX) {
4040 case I40E_LINK_PAUSE_RXTX:
4043 hw->fc.current_mode = I40E_FC_FULL;
4045 case I40E_AQ_LINK_PAUSE_RX:
4047 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4049 case I40E_AQ_LINK_PAUSE_TX:
4051 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4054 hw->fc.current_mode = I40E_FC_NONE;
4059 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4060 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4061 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4062 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4063 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4064 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4071 i40e_pf_setup(struct i40e_pf *pf)
4073 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4074 struct i40e_filter_control_settings settings;
4075 struct i40e_vsi *vsi;
4078 /* Clear all stats counters */
4079 pf->offset_loaded = FALSE;
4080 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4081 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4083 ret = i40e_pf_get_switch_config(pf);
4084 if (ret != I40E_SUCCESS) {
4085 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4088 if (pf->flags & I40E_FLAG_FDIR) {
4089 /* make queue allocated first, let FDIR use queue pair 0*/
4090 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4091 if (ret != I40E_FDIR_QUEUE_ID) {
4092 PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4094 pf->flags &= ~I40E_FLAG_FDIR;
4097 /* main VSI setup */
4098 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4100 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4101 return I40E_ERR_NOT_READY;
4105 /* Configure filter control */
4106 memset(&settings, 0, sizeof(settings));
4107 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4108 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4109 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4110 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4112 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4113 hw->func_caps.rss_table_size);
4114 return I40E_ERR_PARAM;
4116 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4117 "size: %u\n", hw->func_caps.rss_table_size);
4118 pf->hash_lut_size = hw->func_caps.rss_table_size;
4120 /* Enable ethtype and macvlan filters */
4121 settings.enable_ethtype = TRUE;
4122 settings.enable_macvlan = TRUE;
4123 ret = i40e_set_filter_control(hw, &settings);
4125 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4128 /* Update flow control according to the auto negotiation */
4129 i40e_update_flow_control(hw);
4131 return I40E_SUCCESS;
4135 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4141 * Set or clear TX Queue Disable flags,
4142 * which is required by hardware.
4144 i40e_pre_tx_queue_cfg(hw, q_idx, on);
4145 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4147 /* Wait until the request is finished */
4148 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4149 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4150 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4151 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4152 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4158 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4159 return I40E_SUCCESS; /* already on, skip next steps */
4161 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4162 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4164 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4165 return I40E_SUCCESS; /* already off, skip next steps */
4166 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4168 /* Write the register */
4169 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4170 /* Check the result */
4171 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4172 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4173 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4175 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4176 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
4179 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4180 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4184 /* Check if it is timeout */
4185 if (j >= I40E_CHK_Q_ENA_COUNT) {
4186 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
4187 (on ? "enable" : "disable"), q_idx);
4188 return I40E_ERR_TIMEOUT;
4191 return I40E_SUCCESS;
4194 /* Swith on or off the tx queues */
4196 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
4198 struct rte_eth_dev_data *dev_data = pf->dev_data;
4199 struct i40e_tx_queue *txq;
4200 struct rte_eth_dev *dev = pf->adapter->eth_dev;
4204 for (i = 0; i < dev_data->nb_tx_queues; i++) {
4205 txq = dev_data->tx_queues[i];
4206 /* Don't operate the queue if not configured or
4207 * if starting only per queue */
4208 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
4211 ret = i40e_dev_tx_queue_start(dev, i);
4213 ret = i40e_dev_tx_queue_stop(dev, i);
4214 if ( ret != I40E_SUCCESS)
4218 return I40E_SUCCESS;
4222 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4227 /* Wait until the request is finished */
4228 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4229 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4230 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4231 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4232 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
4237 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
4238 return I40E_SUCCESS; /* Already on, skip next steps */
4239 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
4241 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4242 return I40E_SUCCESS; /* Already off, skip next steps */
4243 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
4246 /* Write the register */
4247 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
4248 /* Check the result */
4249 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4250 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4251 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4253 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4254 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
4257 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4258 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4263 /* Check if it is timeout */
4264 if (j >= I40E_CHK_Q_ENA_COUNT) {
4265 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
4266 (on ? "enable" : "disable"), q_idx);
4267 return I40E_ERR_TIMEOUT;
4270 return I40E_SUCCESS;
4272 /* Switch on or off the rx queues */
4274 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
4276 struct rte_eth_dev_data *dev_data = pf->dev_data;
4277 struct i40e_rx_queue *rxq;
4278 struct rte_eth_dev *dev = pf->adapter->eth_dev;
4282 for (i = 0; i < dev_data->nb_rx_queues; i++) {
4283 rxq = dev_data->rx_queues[i];
4284 /* Don't operate the queue if not configured or
4285 * if starting only per queue */
4286 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
4289 ret = i40e_dev_rx_queue_start(dev, i);
4291 ret = i40e_dev_rx_queue_stop(dev, i);
4292 if (ret != I40E_SUCCESS)
4296 return I40E_SUCCESS;
4299 /* Switch on or off all the rx/tx queues */
4301 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
4306 /* enable rx queues before enabling tx queues */
4307 ret = i40e_dev_switch_rx_queues(pf, on);
4309 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
4312 ret = i40e_dev_switch_tx_queues(pf, on);
4314 /* Stop tx queues before stopping rx queues */
4315 ret = i40e_dev_switch_tx_queues(pf, on);
4317 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
4320 ret = i40e_dev_switch_rx_queues(pf, on);
4326 /* Initialize VSI for TX */
4328 i40e_dev_tx_init(struct i40e_pf *pf)
4330 struct rte_eth_dev_data *data = pf->dev_data;
4332 uint32_t ret = I40E_SUCCESS;
4333 struct i40e_tx_queue *txq;
4335 for (i = 0; i < data->nb_tx_queues; i++) {
4336 txq = data->tx_queues[i];
4337 if (!txq || !txq->q_set)
4339 ret = i40e_tx_queue_init(txq);
4340 if (ret != I40E_SUCCESS)
4343 if (ret == I40E_SUCCESS)
4344 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
4350 /* Initialize VSI for RX */
4352 i40e_dev_rx_init(struct i40e_pf *pf)
4354 struct rte_eth_dev_data *data = pf->dev_data;
4355 int ret = I40E_SUCCESS;
4357 struct i40e_rx_queue *rxq;
4359 i40e_pf_config_mq_rx(pf);
4360 for (i = 0; i < data->nb_rx_queues; i++) {
4361 rxq = data->rx_queues[i];
4362 if (!rxq || !rxq->q_set)
4365 ret = i40e_rx_queue_init(rxq);
4366 if (ret != I40E_SUCCESS) {
4367 PMD_DRV_LOG(ERR, "Failed to do RX queue "
4372 if (ret == I40E_SUCCESS)
4373 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
4380 i40e_dev_rxtx_init(struct i40e_pf *pf)
4384 err = i40e_dev_tx_init(pf);
4386 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
4389 err = i40e_dev_rx_init(pf);
4391 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
4399 i40e_vmdq_setup(struct rte_eth_dev *dev)
4401 struct rte_eth_conf *conf = &dev->data->dev_conf;
4402 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4403 int i, err, conf_vsis, j, loop;
4404 struct i40e_vsi *vsi;
4405 struct i40e_vmdq_info *vmdq_info;
4406 struct rte_eth_vmdq_rx_conf *vmdq_conf;
4407 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4410 * Disable interrupt to avoid message from VF. Furthermore, it will
4411 * avoid race condition in VSI creation/destroy.
4413 i40e_pf_disable_irq0(hw);
4415 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
4416 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
4420 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
4421 if (conf_vsis > pf->max_nb_vmdq_vsi) {
4422 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
4423 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
4424 pf->max_nb_vmdq_vsi);
4428 if (pf->vmdq != NULL) {
4429 PMD_INIT_LOG(INFO, "VMDQ already configured");
4433 pf->vmdq = rte_zmalloc("vmdq_info_struct",
4434 sizeof(*vmdq_info) * conf_vsis, 0);
4436 if (pf->vmdq == NULL) {
4437 PMD_INIT_LOG(ERR, "Failed to allocate memory");
4441 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
4443 /* Create VMDQ VSI */
4444 for (i = 0; i < conf_vsis; i++) {
4445 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
4446 vmdq_conf->enable_loop_back);
4448 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
4452 vmdq_info = &pf->vmdq[i];
4454 vmdq_info->vsi = vsi;
4456 pf->nb_cfg_vmdq_vsi = conf_vsis;
4458 /* Configure Vlan */
4459 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
4460 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
4461 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
4462 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
4463 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
4464 vmdq_conf->pool_map[i].vlan_id, j);
4466 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
4467 vmdq_conf->pool_map[i].vlan_id);
4469 PMD_INIT_LOG(ERR, "Failed to add vlan");
4477 i40e_pf_enable_irq0(hw);
4482 for (i = 0; i < conf_vsis; i++)
4483 if (pf->vmdq[i].vsi == NULL)
4486 i40e_vsi_release(pf->vmdq[i].vsi);
4490 i40e_pf_enable_irq0(hw);
4495 i40e_stat_update_32(struct i40e_hw *hw,
4503 new_data = (uint64_t)I40E_READ_REG(hw, reg);
4507 if (new_data >= *offset)
4508 *stat = (uint64_t)(new_data - *offset);
4510 *stat = (uint64_t)((new_data +
4511 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
4515 i40e_stat_update_48(struct i40e_hw *hw,
4524 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
4525 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
4526 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
4531 if (new_data >= *offset)
4532 *stat = new_data - *offset;
4534 *stat = (uint64_t)((new_data +
4535 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
4537 *stat &= I40E_48_BIT_MASK;
4542 i40e_pf_disable_irq0(struct i40e_hw *hw)
4544 /* Disable all interrupt types */
4545 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
4546 I40E_WRITE_FLUSH(hw);
4551 i40e_pf_enable_irq0(struct i40e_hw *hw)
4553 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
4554 I40E_PFINT_DYN_CTL0_INTENA_MASK |
4555 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
4556 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
4557 I40E_WRITE_FLUSH(hw);
4561 i40e_pf_config_irq0(struct i40e_hw *hw)
4563 /* read pending request and disable first */
4564 i40e_pf_disable_irq0(hw);
4565 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
4566 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
4567 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
4569 /* Link no queues with irq0 */
4570 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
4571 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
4575 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
4577 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4578 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4581 uint32_t index, offset, val;
4586 * Try to find which VF trigger a reset, use absolute VF id to access
4587 * since the reg is global register.
4589 for (i = 0; i < pf->vf_num; i++) {
4590 abs_vf_id = hw->func_caps.vf_base_id + i;
4591 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
4592 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
4593 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
4594 /* VFR event occured */
4595 if (val & (0x1 << offset)) {
4598 /* Clear the event first */
4599 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
4601 PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
4603 * Only notify a VF reset event occured,
4604 * don't trigger another SW reset
4606 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
4607 if (ret != I40E_SUCCESS)
4608 PMD_DRV_LOG(ERR, "Failed to do VF reset");
4614 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
4616 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4617 struct i40e_arq_event_info info;
4618 uint16_t pending, opcode;
4621 info.buf_len = I40E_AQ_BUF_SZ;
4622 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
4623 if (!info.msg_buf) {
4624 PMD_DRV_LOG(ERR, "Failed to allocate mem");
4630 ret = i40e_clean_arq_element(hw, &info, &pending);
4632 if (ret != I40E_SUCCESS) {
4633 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
4634 "aq_err: %u", hw->aq.asq_last_status);
4637 opcode = rte_le_to_cpu_16(info.desc.opcode);
4640 case i40e_aqc_opc_send_msg_to_pf:
4641 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
4642 i40e_pf_host_handle_vf_msg(dev,
4643 rte_le_to_cpu_16(info.desc.retval),
4644 rte_le_to_cpu_32(info.desc.cookie_high),
4645 rte_le_to_cpu_32(info.desc.cookie_low),
4650 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
4655 rte_free(info.msg_buf);
4659 * Interrupt handler is registered as the alarm callback for handling LSC
4660 * interrupt in a definite of time, in order to wait the NIC into a stable
4661 * state. Currently it waits 1 sec in i40e for the link up interrupt, and
4662 * no need for link down interrupt.
4665 i40e_dev_interrupt_delayed_handler(void *param)
4667 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4668 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4671 /* read interrupt causes again */
4672 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4674 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4675 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4676 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
4677 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4678 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
4679 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4680 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
4681 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4682 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
4683 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4684 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
4686 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4687 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
4688 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4689 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
4690 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4692 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4693 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
4694 i40e_dev_handle_vfr_event(dev);
4696 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4697 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
4698 i40e_dev_handle_aq_msg(dev);
4701 /* handle the link up interrupt in an alarm callback */
4702 i40e_dev_link_update(dev, 0);
4703 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
4705 i40e_pf_enable_irq0(hw);
4706 rte_intr_enable(&(dev->pci_dev->intr_handle));
4710 * Interrupt handler triggered by NIC for handling
4711 * specific interrupt.
4714 * Pointer to interrupt handle.
4716 * The address of parameter (struct rte_eth_dev *) regsitered before.
4722 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
4725 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4726 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4729 /* Disable interrupt */
4730 i40e_pf_disable_irq0(hw);
4732 /* read out interrupt causes */
4733 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4735 /* No interrupt event indicated */
4736 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
4737 PMD_DRV_LOG(INFO, "No interrupt event");
4740 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4741 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4742 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
4743 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4744 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
4745 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4746 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
4747 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4748 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
4749 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4750 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
4751 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4752 PMD_DRV_LOG(ERR, "ICR0: HMC error");
4753 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4754 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
4755 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4757 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4758 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
4759 i40e_dev_handle_vfr_event(dev);
4761 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4762 PMD_DRV_LOG(INFO, "ICR0: adminq event");
4763 i40e_dev_handle_aq_msg(dev);
4766 /* Link Status Change interrupt */
4767 if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
4768 #define I40E_US_PER_SECOND 1000000
4769 struct rte_eth_link link;
4771 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
4772 memset(&link, 0, sizeof(link));
4773 rte_i40e_dev_atomic_read_link_status(dev, &link);
4774 i40e_dev_link_update(dev, 0);
4777 * For link up interrupt, it needs to wait 1 second to let the
4778 * hardware be a stable state. Otherwise several consecutive
4779 * interrupts can be observed.
4780 * For link down interrupt, no need to wait.
4782 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
4783 i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
4786 _rte_eth_dev_callback_process(dev,
4787 RTE_ETH_EVENT_INTR_LSC);
4791 /* Enable interrupt */
4792 i40e_pf_enable_irq0(hw);
4793 rte_intr_enable(&(dev->pci_dev->intr_handle));
4797 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
4798 struct i40e_macvlan_filter *filter,
4801 int ele_num, ele_buff_size;
4802 int num, actual_num, i;
4804 int ret = I40E_SUCCESS;
4805 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4806 struct i40e_aqc_add_macvlan_element_data *req_list;
4808 if (filter == NULL || total == 0)
4809 return I40E_ERR_PARAM;
4810 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4811 ele_buff_size = hw->aq.asq_buf_size;
4813 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
4814 if (req_list == NULL) {
4815 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4816 return I40E_ERR_NO_MEMORY;
4821 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4822 memset(req_list, 0, ele_buff_size);
4824 for (i = 0; i < actual_num; i++) {
4825 (void)rte_memcpy(req_list[i].mac_addr,
4826 &filter[num + i].macaddr, ETH_ADDR_LEN);
4827 req_list[i].vlan_tag =
4828 rte_cpu_to_le_16(filter[num + i].vlan_id);
4830 switch (filter[num + i].filter_type) {
4831 case RTE_MAC_PERFECT_MATCH:
4832 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
4833 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4835 case RTE_MACVLAN_PERFECT_MATCH:
4836 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
4838 case RTE_MAC_HASH_MATCH:
4839 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
4840 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4842 case RTE_MACVLAN_HASH_MATCH:
4843 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
4846 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
4847 ret = I40E_ERR_PARAM;
4851 req_list[i].queue_number = 0;
4853 req_list[i].flags = rte_cpu_to_le_16(flags);
4856 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
4858 if (ret != I40E_SUCCESS) {
4859 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
4863 } while (num < total);
4871 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
4872 struct i40e_macvlan_filter *filter,
4875 int ele_num, ele_buff_size;
4876 int num, actual_num, i;
4878 int ret = I40E_SUCCESS;
4879 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4880 struct i40e_aqc_remove_macvlan_element_data *req_list;
4882 if (filter == NULL || total == 0)
4883 return I40E_ERR_PARAM;
4885 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4886 ele_buff_size = hw->aq.asq_buf_size;
4888 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
4889 if (req_list == NULL) {
4890 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4891 return I40E_ERR_NO_MEMORY;
4896 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4897 memset(req_list, 0, ele_buff_size);
4899 for (i = 0; i < actual_num; i++) {
4900 (void)rte_memcpy(req_list[i].mac_addr,
4901 &filter[num + i].macaddr, ETH_ADDR_LEN);
4902 req_list[i].vlan_tag =
4903 rte_cpu_to_le_16(filter[num + i].vlan_id);
4905 switch (filter[num + i].filter_type) {
4906 case RTE_MAC_PERFECT_MATCH:
4907 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4908 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4910 case RTE_MACVLAN_PERFECT_MATCH:
4911 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
4913 case RTE_MAC_HASH_MATCH:
4914 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
4915 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4917 case RTE_MACVLAN_HASH_MATCH:
4918 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
4921 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
4922 ret = I40E_ERR_PARAM;
4925 req_list[i].flags = rte_cpu_to_le_16(flags);
4928 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
4930 if (ret != I40E_SUCCESS) {
4931 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
4935 } while (num < total);
4942 /* Find out specific MAC filter */
4943 static struct i40e_mac_filter *
4944 i40e_find_mac_filter(struct i40e_vsi *vsi,
4945 struct ether_addr *macaddr)
4947 struct i40e_mac_filter *f;
4949 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4950 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
4958 i40e_find_vlan_filter(struct i40e_vsi *vsi,
4961 uint32_t vid_idx, vid_bit;
4963 if (vlan_id > ETH_VLAN_ID_MAX)
4966 vid_idx = I40E_VFTA_IDX(vlan_id);
4967 vid_bit = I40E_VFTA_BIT(vlan_id);
4969 if (vsi->vfta[vid_idx] & vid_bit)
4976 i40e_set_vlan_filter(struct i40e_vsi *vsi,
4977 uint16_t vlan_id, bool on)
4979 uint32_t vid_idx, vid_bit;
4981 if (vlan_id > ETH_VLAN_ID_MAX)
4984 vid_idx = I40E_VFTA_IDX(vlan_id);
4985 vid_bit = I40E_VFTA_BIT(vlan_id);
4988 vsi->vfta[vid_idx] |= vid_bit;
4990 vsi->vfta[vid_idx] &= ~vid_bit;
4994 * Find all vlan options for specific mac addr,
4995 * return with actual vlan found.
4998 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
4999 struct i40e_macvlan_filter *mv_f,
5000 int num, struct ether_addr *addr)
5006 * Not to use i40e_find_vlan_filter to decrease the loop time,
5007 * although the code looks complex.
5009 if (num < vsi->vlan_num)
5010 return I40E_ERR_PARAM;
5013 for (j = 0; j < I40E_VFTA_SIZE; j++) {
5015 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5016 if (vsi->vfta[j] & (1 << k)) {
5018 PMD_DRV_LOG(ERR, "vlan number "
5020 return I40E_ERR_PARAM;
5022 (void)rte_memcpy(&mv_f[i].macaddr,
5023 addr, ETH_ADDR_LEN);
5025 j * I40E_UINT32_BIT_SIZE + k;
5031 return I40E_SUCCESS;
5035 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5036 struct i40e_macvlan_filter *mv_f,
5041 struct i40e_mac_filter *f;
5043 if (num < vsi->mac_num)
5044 return I40E_ERR_PARAM;
5046 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5048 PMD_DRV_LOG(ERR, "buffer number not match");
5049 return I40E_ERR_PARAM;
5051 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5053 mv_f[i].vlan_id = vlan;
5054 mv_f[i].filter_type = f->mac_info.filter_type;
5058 return I40E_SUCCESS;
5062 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5065 struct i40e_mac_filter *f;
5066 struct i40e_macvlan_filter *mv_f;
5067 int ret = I40E_SUCCESS;
5069 if (vsi == NULL || vsi->mac_num == 0)
5070 return I40E_ERR_PARAM;
5072 /* Case that no vlan is set */
5073 if (vsi->vlan_num == 0)
5076 num = vsi->mac_num * vsi->vlan_num;
5078 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5080 PMD_DRV_LOG(ERR, "failed to allocate memory");
5081 return I40E_ERR_NO_MEMORY;
5085 if (vsi->vlan_num == 0) {
5086 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5087 (void)rte_memcpy(&mv_f[i].macaddr,
5088 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5089 mv_f[i].vlan_id = 0;
5093 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5094 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5095 vsi->vlan_num, &f->mac_info.mac_addr);
5096 if (ret != I40E_SUCCESS)
5102 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5110 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5112 struct i40e_macvlan_filter *mv_f;
5114 int ret = I40E_SUCCESS;
5116 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5117 return I40E_ERR_PARAM;
5119 /* If it's already set, just return */
5120 if (i40e_find_vlan_filter(vsi,vlan))
5121 return I40E_SUCCESS;
5123 mac_num = vsi->mac_num;
5126 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5127 return I40E_ERR_PARAM;
5130 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5133 PMD_DRV_LOG(ERR, "failed to allocate memory");
5134 return I40E_ERR_NO_MEMORY;
5137 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5139 if (ret != I40E_SUCCESS)
5142 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5144 if (ret != I40E_SUCCESS)
5147 i40e_set_vlan_filter(vsi, vlan, 1);
5157 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5159 struct i40e_macvlan_filter *mv_f;
5161 int ret = I40E_SUCCESS;
5164 * Vlan 0 is the generic filter for untagged packets
5165 * and can't be removed.
5167 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5168 return I40E_ERR_PARAM;
5170 /* If can't find it, just return */
5171 if (!i40e_find_vlan_filter(vsi, vlan))
5172 return I40E_ERR_PARAM;
5174 mac_num = vsi->mac_num;
5177 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5178 return I40E_ERR_PARAM;
5181 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5184 PMD_DRV_LOG(ERR, "failed to allocate memory");
5185 return I40E_ERR_NO_MEMORY;
5188 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5190 if (ret != I40E_SUCCESS)
5193 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5195 if (ret != I40E_SUCCESS)
5198 /* This is last vlan to remove, replace all mac filter with vlan 0 */
5199 if (vsi->vlan_num == 1) {
5200 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5201 if (ret != I40E_SUCCESS)
5204 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5205 if (ret != I40E_SUCCESS)
5209 i40e_set_vlan_filter(vsi, vlan, 0);
5219 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
5221 struct i40e_mac_filter *f;
5222 struct i40e_macvlan_filter *mv_f;
5223 int i, vlan_num = 0;
5224 int ret = I40E_SUCCESS;
5226 /* If it's add and we've config it, return */
5227 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
5229 return I40E_SUCCESS;
5230 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
5231 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
5234 * If vlan_num is 0, that's the first time to add mac,
5235 * set mask for vlan_id 0.
5237 if (vsi->vlan_num == 0) {
5238 i40e_set_vlan_filter(vsi, 0, 1);
5241 vlan_num = vsi->vlan_num;
5242 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
5243 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
5246 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5248 PMD_DRV_LOG(ERR, "failed to allocate memory");
5249 return I40E_ERR_NO_MEMORY;
5252 for (i = 0; i < vlan_num; i++) {
5253 mv_f[i].filter_type = mac_filter->filter_type;
5254 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
5258 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5259 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
5260 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
5261 &mac_filter->mac_addr);
5262 if (ret != I40E_SUCCESS)
5266 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
5267 if (ret != I40E_SUCCESS)
5270 /* Add the mac addr into mac list */
5271 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5273 PMD_DRV_LOG(ERR, "failed to allocate memory");
5274 ret = I40E_ERR_NO_MEMORY;
5277 (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
5279 f->mac_info.filter_type = mac_filter->filter_type;
5280 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5291 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
5293 struct i40e_mac_filter *f;
5294 struct i40e_macvlan_filter *mv_f;
5296 enum rte_mac_filter_type filter_type;
5297 int ret = I40E_SUCCESS;
5299 /* Can't find it, return an error */
5300 f = i40e_find_mac_filter(vsi, addr);
5302 return I40E_ERR_PARAM;
5304 vlan_num = vsi->vlan_num;
5305 filter_type = f->mac_info.filter_type;
5306 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5307 filter_type == RTE_MACVLAN_HASH_MATCH) {
5308 if (vlan_num == 0) {
5309 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
5310 return I40E_ERR_PARAM;
5312 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
5313 filter_type == RTE_MAC_HASH_MATCH)
5316 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5318 PMD_DRV_LOG(ERR, "failed to allocate memory");
5319 return I40E_ERR_NO_MEMORY;
5322 for (i = 0; i < vlan_num; i++) {
5323 mv_f[i].filter_type = filter_type;
5324 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5327 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5328 filter_type == RTE_MACVLAN_HASH_MATCH) {
5329 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
5330 if (ret != I40E_SUCCESS)
5334 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
5335 if (ret != I40E_SUCCESS)
5338 /* Remove the mac addr into mac list */
5339 TAILQ_REMOVE(&vsi->mac_list, f, next);
5349 /* Configure hash enable flags for RSS */
5351 i40e_config_hena(uint64_t flags)
5358 if (flags & ETH_RSS_FRAG_IPV4)
5359 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
5360 if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
5361 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
5362 if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
5363 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
5364 if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
5365 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
5366 if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
5367 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
5368 if (flags & ETH_RSS_FRAG_IPV6)
5369 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
5370 if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
5371 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
5372 if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
5373 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
5374 if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
5375 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
5376 if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
5377 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
5378 if (flags & ETH_RSS_L2_PAYLOAD)
5379 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
5384 /* Parse the hash enable flags */
5386 i40e_parse_hena(uint64_t flags)
5388 uint64_t rss_hf = 0;
5392 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
5393 rss_hf |= ETH_RSS_FRAG_IPV4;
5394 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
5395 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
5396 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
5397 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
5398 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
5399 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
5400 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
5401 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
5402 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
5403 rss_hf |= ETH_RSS_FRAG_IPV6;
5404 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
5405 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
5406 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
5407 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
5408 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
5409 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
5410 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
5411 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
5412 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
5413 rss_hf |= ETH_RSS_L2_PAYLOAD;
5420 i40e_pf_disable_rss(struct i40e_pf *pf)
5422 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5425 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5426 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5427 hena &= ~I40E_RSS_HENA_ALL;
5428 I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5429 I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5430 I40E_WRITE_FLUSH(hw);
5434 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
5436 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5437 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5440 if (!key || key_len != ((I40E_PFQF_HKEY_MAX_INDEX + 1) *
5444 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5445 struct i40e_aqc_get_set_rss_key_data *key_dw =
5446 (struct i40e_aqc_get_set_rss_key_data *)key;
5448 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
5450 PMD_INIT_LOG(ERR, "Failed to configure RSS key "
5453 uint32_t *hash_key = (uint32_t *)key;
5456 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5457 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
5458 I40E_WRITE_FLUSH(hw);
5465 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
5467 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5468 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5471 if (!key || !key_len)
5474 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5475 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
5476 (struct i40e_aqc_get_set_rss_key_data *)key);
5478 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
5482 uint32_t *key_dw = (uint32_t *)key;
5485 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5486 key_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
5488 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
5494 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
5496 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5501 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
5502 rss_conf->rss_key_len);
5506 rss_hf = rss_conf->rss_hf;
5507 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5508 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5509 hena &= ~I40E_RSS_HENA_ALL;
5510 hena |= i40e_config_hena(rss_hf);
5511 I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5512 I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5513 I40E_WRITE_FLUSH(hw);
5519 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
5520 struct rte_eth_rss_conf *rss_conf)
5522 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5523 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5524 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
5527 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5528 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5529 if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
5530 if (rss_hf != 0) /* Enable RSS */
5532 return 0; /* Nothing to do */
5535 if (rss_hf == 0) /* Disable RSS */
5538 return i40e_hw_rss_hash_set(pf, rss_conf);
5542 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
5543 struct rte_eth_rss_conf *rss_conf)
5545 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5546 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5549 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
5550 &rss_conf->rss_key_len);
5552 hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5553 hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5554 rss_conf->rss_hf = i40e_parse_hena(hena);
5560 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
5562 switch (filter_type) {
5563 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
5564 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
5566 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
5567 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
5569 case RTE_TUNNEL_FILTER_IMAC_TENID:
5570 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
5572 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
5573 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
5575 case ETH_TUNNEL_FILTER_IMAC:
5576 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
5579 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
5587 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
5588 struct rte_eth_tunnel_filter_conf *tunnel_filter,
5592 uint8_t tun_type = 0;
5594 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5595 struct i40e_vsi *vsi = pf->main_vsi;
5596 struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter;
5597 struct i40e_aqc_add_remove_cloud_filters_element_data *pfilter;
5599 cld_filter = rte_zmalloc("tunnel_filter",
5600 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
5603 if (NULL == cld_filter) {
5604 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
5607 pfilter = cld_filter;
5609 (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
5610 sizeof(struct ether_addr));
5611 (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
5612 sizeof(struct ether_addr));
5614 pfilter->inner_vlan = tunnel_filter->inner_vlan;
5615 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
5616 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
5617 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
5618 &tunnel_filter->ip_addr,
5619 sizeof(pfilter->ipaddr.v4.data));
5621 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
5622 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
5623 &tunnel_filter->ip_addr,
5624 sizeof(pfilter->ipaddr.v6.data));
5627 /* check tunneled type */
5628 switch (tunnel_filter->tunnel_type) {
5629 case RTE_TUNNEL_TYPE_VXLAN:
5630 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
5632 case RTE_TUNNEL_TYPE_NVGRE:
5633 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
5636 /* Other tunnel types is not supported. */
5637 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
5638 rte_free(cld_filter);
5642 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
5645 rte_free(cld_filter);
5649 pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
5650 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
5651 pfilter->tenant_id = tunnel_filter->tenant_id;
5652 pfilter->queue_number = tunnel_filter->queue_id;
5655 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
5657 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
5660 rte_free(cld_filter);
5665 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
5669 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5670 if (pf->vxlan_ports[i] == port)
5678 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
5682 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5684 idx = i40e_get_vxlan_port_idx(pf, port);
5686 /* Check if port already exists */
5688 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
5692 /* Now check if there is space to add the new port */
5693 idx = i40e_get_vxlan_port_idx(pf, 0);
5695 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
5696 "not adding port %d", port);
5700 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
5703 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
5707 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
5710 /* New port: add it and mark its index in the bitmap */
5711 pf->vxlan_ports[idx] = port;
5712 pf->vxlan_bitmap |= (1 << idx);
5714 if (!(pf->flags & I40E_FLAG_VXLAN))
5715 pf->flags |= I40E_FLAG_VXLAN;
5721 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
5724 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5726 if (!(pf->flags & I40E_FLAG_VXLAN)) {
5727 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
5731 idx = i40e_get_vxlan_port_idx(pf, port);
5734 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
5738 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
5739 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
5743 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
5746 pf->vxlan_ports[idx] = 0;
5747 pf->vxlan_bitmap &= ~(1 << idx);
5749 if (!pf->vxlan_bitmap)
5750 pf->flags &= ~I40E_FLAG_VXLAN;
5755 /* Add UDP tunneling port */
5757 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
5758 struct rte_eth_udp_tunnel *udp_tunnel)
5761 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5763 if (udp_tunnel == NULL)
5766 switch (udp_tunnel->prot_type) {
5767 case RTE_TUNNEL_TYPE_VXLAN:
5768 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
5771 case RTE_TUNNEL_TYPE_GENEVE:
5772 case RTE_TUNNEL_TYPE_TEREDO:
5773 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
5778 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5786 /* Remove UDP tunneling port */
5788 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
5789 struct rte_eth_udp_tunnel *udp_tunnel)
5792 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5794 if (udp_tunnel == NULL)
5797 switch (udp_tunnel->prot_type) {
5798 case RTE_TUNNEL_TYPE_VXLAN:
5799 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
5801 case RTE_TUNNEL_TYPE_GENEVE:
5802 case RTE_TUNNEL_TYPE_TEREDO:
5803 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
5807 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5815 /* Calculate the maximum number of contiguous PF queues that are configured */
5817 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
5819 struct rte_eth_dev_data *data = pf->dev_data;
5821 struct i40e_rx_queue *rxq;
5824 for (i = 0; i < pf->lan_nb_qps; i++) {
5825 rxq = data->rx_queues[i];
5826 if (rxq && rxq->q_set)
5837 i40e_pf_config_rss(struct i40e_pf *pf)
5839 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5840 struct rte_eth_rss_conf rss_conf;
5841 uint32_t i, lut = 0;
5845 * If both VMDQ and RSS enabled, not all of PF queues are configured.
5846 * It's necessary to calulate the actual PF queues that are configured.
5848 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
5849 num = i40e_pf_calc_configured_queues_num(pf);
5851 num = pf->dev_data->nb_rx_queues;
5853 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
5854 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
5858 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
5862 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
5865 lut = (lut << 8) | (j & ((0x1 <<
5866 hw->func_caps.rss_table_entry_width) - 1));
5868 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
5871 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
5872 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
5873 i40e_pf_disable_rss(pf);
5876 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
5877 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
5878 /* Random default keys */
5879 static uint32_t rss_key_default[] = {0x6b793944,
5880 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
5881 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
5882 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
5884 rss_conf.rss_key = (uint8_t *)rss_key_default;
5885 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5889 return i40e_hw_rss_hash_set(pf, &rss_conf);
5893 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
5894 struct rte_eth_tunnel_filter_conf *filter)
5896 if (pf == NULL || filter == NULL) {
5897 PMD_DRV_LOG(ERR, "Invalid parameter");
5901 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
5902 PMD_DRV_LOG(ERR, "Invalid queue ID");
5906 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
5907 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
5911 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
5912 (is_zero_ether_addr(filter->outer_mac))) {
5913 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
5917 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
5918 (is_zero_ether_addr(filter->inner_mac))) {
5919 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
5926 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
5927 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
5929 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
5934 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
5935 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
5938 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
5939 } else if (len == 4) {
5940 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
5942 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
5947 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
5954 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
5955 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
5961 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
5968 switch (cfg->cfg_type) {
5969 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
5970 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
5973 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
5981 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
5982 enum rte_filter_op filter_op,
5985 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5986 int ret = I40E_ERR_PARAM;
5988 switch (filter_op) {
5989 case RTE_ETH_FILTER_SET:
5990 ret = i40e_dev_global_config_set(hw,
5991 (struct rte_eth_global_cfg *)arg);
5994 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6002 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6003 enum rte_filter_op filter_op,
6006 struct rte_eth_tunnel_filter_conf *filter;
6007 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6008 int ret = I40E_SUCCESS;
6010 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6012 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6013 return I40E_ERR_PARAM;
6015 switch (filter_op) {
6016 case RTE_ETH_FILTER_NOP:
6017 if (!(pf->flags & I40E_FLAG_VXLAN))
6018 ret = I40E_NOT_SUPPORTED;
6020 case RTE_ETH_FILTER_ADD:
6021 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6023 case RTE_ETH_FILTER_DELETE:
6024 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6027 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6028 ret = I40E_ERR_PARAM;
6036 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6039 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6042 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6043 ret = i40e_pf_config_rss(pf);
6045 i40e_pf_disable_rss(pf);
6050 /* Get the symmetric hash enable configurations per port */
6052 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6054 uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
6056 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6059 /* Set the symmetric hash enable configurations per port */
6061 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6063 uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
6066 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6067 PMD_DRV_LOG(INFO, "Symmetric hash has already "
6071 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6073 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6074 PMD_DRV_LOG(INFO, "Symmetric hash has already "
6078 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6080 I40E_WRITE_REG(hw, I40E_PRTQF_CTL_0, reg);
6081 I40E_WRITE_FLUSH(hw);
6085 * Get global configurations of hash function type and symmetric hash enable
6086 * per flow type (pctype). Note that global configuration means it affects all
6087 * the ports on the same NIC.
6090 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6091 struct rte_eth_hash_global_conf *g_cfg)
6093 uint32_t reg, mask = I40E_FLOW_TYPES;
6095 enum i40e_filter_pctype pctype;
6097 memset(g_cfg, 0, sizeof(*g_cfg));
6098 reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
6099 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6100 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6102 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6103 PMD_DRV_LOG(DEBUG, "Hash function is %s",
6104 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6106 for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6107 if (!(mask & (1UL << i)))
6109 mask &= ~(1UL << i);
6110 /* Bit set indicats the coresponding flow type is supported */
6111 g_cfg->valid_bit_mask[0] |= (1UL << i);
6112 pctype = i40e_flowtype_to_pctype(i);
6113 reg = I40E_READ_REG(hw, I40E_GLQF_HSYM(pctype));
6114 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6115 g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6122 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6125 uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6127 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
6128 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
6129 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
6130 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
6136 * As i40e supports less than 32 flow types, only first 32 bits need to
6139 mask0 = g_cfg->valid_bit_mask[0];
6140 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
6142 /* Check if any unsupported flow type configured */
6143 if ((mask0 | i40e_mask) ^ i40e_mask)
6146 if (g_cfg->valid_bit_mask[i])
6154 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
6160 * Set global configurations of hash function type and symmetric hash enable
6161 * per flow type (pctype). Note any modifying global configuration will affect
6162 * all the ports on the same NIC.
6165 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
6166 struct rte_eth_hash_global_conf *g_cfg)
6171 uint32_t mask0 = g_cfg->valid_bit_mask[0];
6172 enum i40e_filter_pctype pctype;
6174 /* Check the input parameters */
6175 ret = i40e_hash_global_config_check(g_cfg);
6179 for (i = 0; mask0 && i < UINT32_BIT; i++) {
6180 if (!(mask0 & (1UL << i)))
6182 mask0 &= ~(1UL << i);
6183 pctype = i40e_flowtype_to_pctype(i);
6184 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
6185 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
6186 I40E_WRITE_REG(hw, I40E_GLQF_HSYM(pctype), reg);
6189 reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
6190 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
6192 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
6193 PMD_DRV_LOG(DEBUG, "Hash function already set to "
6197 reg |= I40E_GLQF_CTL_HTOEP_MASK;
6198 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
6200 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
6201 PMD_DRV_LOG(DEBUG, "Hash function already set to "
6205 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
6207 /* Use the default, and keep it as it is */
6210 I40E_WRITE_REG(hw, I40E_GLQF_CTL, reg);
6213 I40E_WRITE_FLUSH(hw);
6219 * Valid input sets for hash and flow director filters per PCTYPE
6222 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
6223 enum rte_filter_type filter)
6227 static const uint64_t valid_hash_inset_table[] = {
6228 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6229 I40E_INSET_DMAC | I40E_INSET_SMAC |
6230 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6231 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
6232 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
6233 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6234 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6235 I40E_INSET_FLEX_PAYLOAD,
6236 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6237 I40E_INSET_DMAC | I40E_INSET_SMAC |
6238 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6239 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6240 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6241 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6242 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6243 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6244 I40E_INSET_FLEX_PAYLOAD,
6245 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6246 I40E_INSET_DMAC | I40E_INSET_SMAC |
6247 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6248 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6249 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6250 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6251 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6252 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6253 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
6254 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6255 I40E_INSET_DMAC | I40E_INSET_SMAC |
6256 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6257 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6258 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6259 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6260 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6261 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6262 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6263 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6264 I40E_INSET_DMAC | I40E_INSET_SMAC |
6265 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6266 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6267 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6268 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6269 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6270 I40E_INSET_FLEX_PAYLOAD,
6271 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6272 I40E_INSET_DMAC | I40E_INSET_SMAC |
6273 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6274 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6275 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6276 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
6277 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
6278 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
6279 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6280 I40E_INSET_DMAC | I40E_INSET_SMAC |
6281 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6282 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6283 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6284 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6285 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6286 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
6287 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6288 I40E_INSET_DMAC | I40E_INSET_SMAC |
6289 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6290 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6291 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6292 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6293 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6294 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
6295 I40E_INSET_FLEX_PAYLOAD,
6296 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6297 I40E_INSET_DMAC | I40E_INSET_SMAC |
6298 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6299 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6300 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6301 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6302 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6303 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
6304 I40E_INSET_FLEX_PAYLOAD,
6305 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6306 I40E_INSET_DMAC | I40E_INSET_SMAC |
6307 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6308 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6309 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6310 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6311 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
6312 I40E_INSET_FLEX_PAYLOAD,
6313 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6314 I40E_INSET_DMAC | I40E_INSET_SMAC |
6315 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6316 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
6317 I40E_INSET_FLEX_PAYLOAD,
6321 * Flow director supports only fields defined in
6322 * union rte_eth_fdir_flow.
6324 static const uint64_t valid_fdir_inset_table[] = {
6325 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6326 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6327 I40E_INSET_FLEX_PAYLOAD,
6328 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6329 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6330 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6331 I40E_INSET_FLEX_PAYLOAD,
6332 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6333 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6334 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6335 I40E_INSET_FLEX_PAYLOAD,
6336 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6337 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6338 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6339 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6340 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6341 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6342 I40E_INSET_FLEX_PAYLOAD,
6343 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6344 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6345 I40E_INSET_FLEX_PAYLOAD,
6346 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6347 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6348 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6349 I40E_INSET_FLEX_PAYLOAD,
6350 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6351 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6352 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6353 I40E_INSET_FLEX_PAYLOAD,
6354 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6355 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6356 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6357 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6358 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6359 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6360 I40E_INSET_FLEX_PAYLOAD,
6361 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6362 I40E_INSET_LAST_ETHER_TYPE | I40E_INSET_FLEX_PAYLOAD,
6365 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6367 if (filter == RTE_ETH_FILTER_HASH)
6368 valid = valid_hash_inset_table[pctype];
6370 valid = valid_fdir_inset_table[pctype];
6376 * Validate if the input set is allowed for a specific PCTYPE
6379 i40e_validate_input_set(enum i40e_filter_pctype pctype,
6380 enum rte_filter_type filter, uint64_t inset)
6384 valid = i40e_get_valid_input_set(pctype, filter);
6385 if (inset & (~valid))
6391 /* default input set fields combination per pctype */
6393 i40e_get_default_input_set(uint16_t pctype)
6395 static const uint64_t default_inset_table[] = {
6396 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6397 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6398 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6399 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6400 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6401 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6402 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6403 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6404 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6405 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6406 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6408 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6409 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6410 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6411 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6412 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6413 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6414 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6415 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6416 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6417 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6418 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6419 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6420 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6422 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6423 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6424 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6425 I40E_INSET_LAST_ETHER_TYPE,
6428 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6431 return default_inset_table[pctype];
6435 * Parse the input set from index to logical bit masks
6438 i40e_parse_input_set(uint64_t *inset,
6439 enum i40e_filter_pctype pctype,
6440 enum rte_eth_input_set_field *field,
6446 static const struct {
6447 enum rte_eth_input_set_field field;
6449 } inset_convert_table[] = {
6450 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
6451 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
6452 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
6453 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
6454 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
6455 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
6456 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
6457 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
6458 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
6459 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
6460 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
6461 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
6462 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
6463 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
6464 I40E_INSET_IPV6_NEXT_HDR},
6465 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
6466 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
6467 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
6468 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
6469 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
6470 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
6471 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
6472 I40E_INSET_SCTP_VT},
6473 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
6474 I40E_INSET_TUNNEL_DMAC},
6475 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
6476 I40E_INSET_VLAN_TUNNEL},
6477 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
6478 I40E_INSET_TUNNEL_ID},
6479 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
6480 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
6481 I40E_INSET_FLEX_PAYLOAD_W1},
6482 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
6483 I40E_INSET_FLEX_PAYLOAD_W2},
6484 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
6485 I40E_INSET_FLEX_PAYLOAD_W3},
6486 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
6487 I40E_INSET_FLEX_PAYLOAD_W4},
6488 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
6489 I40E_INSET_FLEX_PAYLOAD_W5},
6490 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
6491 I40E_INSET_FLEX_PAYLOAD_W6},
6492 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
6493 I40E_INSET_FLEX_PAYLOAD_W7},
6494 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
6495 I40E_INSET_FLEX_PAYLOAD_W8},
6498 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
6501 /* Only one item allowed for default or all */
6503 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
6504 *inset = i40e_get_default_input_set(pctype);
6506 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
6507 *inset = I40E_INSET_NONE;
6512 for (i = 0, *inset = 0; i < size; i++) {
6513 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
6514 if (field[i] == inset_convert_table[j].field) {
6515 *inset |= inset_convert_table[j].inset;
6520 /* It contains unsupported input set, return immediately */
6521 if (j == RTE_DIM(inset_convert_table))
6529 * Translate the input set from bit masks to register aware bit masks
6533 i40e_translate_input_set_reg(uint64_t input)
6538 static const struct {
6542 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
6543 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
6544 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
6545 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
6546 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
6547 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
6548 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
6549 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
6550 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
6551 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
6552 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
6553 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
6554 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
6555 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
6556 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
6557 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
6558 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
6559 {I40E_INSET_TUNNEL_DMAC,
6560 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
6561 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
6562 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
6563 {I40E_INSET_TUNNEL_SRC_PORT,
6564 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
6565 {I40E_INSET_TUNNEL_DST_PORT,
6566 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
6567 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
6568 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
6569 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
6570 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
6571 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
6572 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
6573 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
6574 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
6575 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
6581 /* Translate input set to register aware inset */
6582 for (i = 0; i < RTE_DIM(inset_map); i++) {
6583 if (input & inset_map[i].inset)
6584 val |= inset_map[i].inset_reg;
6591 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
6595 static const struct {
6598 } inset_mask_map[] = {
6599 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
6600 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
6601 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
6602 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
6605 if (!inset || !mask || !nb_elem)
6608 if (!inset && nb_elem >= I40E_INSET_MASK_NUM_REG) {
6609 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++)
6611 return I40E_INSET_MASK_NUM_REG;
6614 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
6617 if (inset & inset_mask_map[i].inset) {
6618 mask[idx] = inset_mask_map[i].mask;
6627 i40e_get_reg_inset(struct i40e_hw *hw, enum rte_filter_type filter,
6628 enum i40e_filter_pctype pctype)
6632 if (filter == RTE_ETH_FILTER_HASH) {
6633 reg = I40E_READ_REG(hw, I40E_GLQF_HASH_INSET(1, pctype));
6634 reg <<= I40E_32_BIT_WIDTH;
6635 reg |= I40E_READ_REG(hw, I40E_GLQF_HASH_INSET(0, pctype));
6636 } else if (filter == RTE_ETH_FILTER_FDIR) {
6637 reg = I40E_READ_REG(hw, I40E_PRTQF_FD_INSET(pctype, 1));
6638 reg <<= I40E_32_BIT_WIDTH;
6639 reg |= I40E_READ_REG(hw, I40E_PRTQF_FD_INSET(pctype, 0));
6646 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
6648 uint32_t reg = I40E_READ_REG(hw, addr);
6650 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
6652 I40E_WRITE_REG(hw, addr, val);
6653 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
6654 (uint32_t)I40E_READ_REG(hw, addr));
6658 i40e_set_hash_inset_mask(struct i40e_hw *hw,
6659 enum i40e_filter_pctype pctype,
6660 enum rte_filter_input_set_op op,
6667 if (!mask_reg || num > RTE_ETH_INPUT_SET_SELECT)
6670 if (op == RTE_ETH_INPUT_SET_SELECT) {
6671 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6672 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
6676 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
6679 } else if (op == RTE_ETH_INPUT_SET_ADD) {
6680 uint8_t j, count = 0;
6682 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6683 reg = I40E_READ_REG(hw, I40E_GLQF_HASH_MSK(i, pctype));
6684 if (reg & I40E_GLQF_HASH_MSK_FIELD)
6687 if (count + num > I40E_INSET_MASK_NUM_REG)
6690 for (i = count, j = 0; i < I40E_INSET_MASK_NUM_REG; i++, j++)
6691 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
6699 i40e_set_fd_inset_mask(struct i40e_hw *hw,
6700 enum i40e_filter_pctype pctype,
6701 enum rte_filter_input_set_op op,
6708 if (!mask_reg || num > RTE_ETH_INPUT_SET_SELECT)
6711 if (op == RTE_ETH_INPUT_SET_SELECT) {
6712 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6713 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
6717 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
6720 } else if (op == RTE_ETH_INPUT_SET_ADD) {
6721 uint8_t j, count = 0;
6723 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
6724 reg = I40E_READ_REG(hw, I40E_GLQF_FD_MSK(i, pctype));
6725 if (reg & I40E_GLQF_FD_MSK_FIELD)
6728 if (count + num > I40E_INSET_MASK_NUM_REG)
6731 for (i = count, j = 0; i < I40E_INSET_MASK_NUM_REG; i++, j++)
6732 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
6740 i40e_filter_inset_select(struct i40e_hw *hw,
6741 struct rte_eth_input_set_conf *conf,
6742 enum rte_filter_type filter)
6744 enum i40e_filter_pctype pctype;
6745 uint64_t inset_reg = 0, input_set;
6746 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG];
6751 PMD_DRV_LOG(ERR, "Invalid pointer");
6755 pctype = i40e_flowtype_to_pctype(conf->flow_type);
6756 if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
6757 PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
6761 if (filter != RTE_ETH_FILTER_HASH && filter != RTE_ETH_FILTER_FDIR) {
6762 PMD_DRV_LOG(ERR, "Not supported filter type (%u)", filter);
6766 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
6769 PMD_DRV_LOG(ERR, "Failed to parse input set");
6772 if (i40e_validate_input_set(pctype, filter, input_set) != 0) {
6773 PMD_DRV_LOG(ERR, "Invalid input set");
6777 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
6778 inset_reg |= i40e_get_reg_inset(hw, filter, pctype);
6779 } else if (conf->op != RTE_ETH_INPUT_SET_SELECT) {
6780 PMD_DRV_LOG(ERR, "Unsupported input set operation");
6783 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
6784 I40E_INSET_MASK_NUM_REG);
6785 inset_reg |= i40e_translate_input_set_reg(input_set);
6787 if (filter == RTE_ETH_FILTER_HASH) {
6788 ret = i40e_set_hash_inset_mask(hw, pctype, conf->op, mask_reg,
6793 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
6794 (uint32_t)(inset_reg & UINT32_MAX));
6795 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
6796 (uint32_t)((inset_reg >>
6797 I40E_32_BIT_WIDTH) & UINT32_MAX));
6798 } else if (filter == RTE_ETH_FILTER_FDIR) {
6799 ret = i40e_set_fd_inset_mask(hw, pctype, conf->op, mask_reg,
6804 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
6805 (uint32_t)(inset_reg & UINT32_MAX));
6806 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
6807 (uint32_t)((inset_reg >>
6808 I40E_32_BIT_WIDTH) & UINT32_MAX));
6810 PMD_DRV_LOG(ERR, "Not supported filter type (%u)", filter);
6813 I40E_WRITE_FLUSH(hw);
6819 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
6824 PMD_DRV_LOG(ERR, "Invalid pointer");
6828 switch (info->info_type) {
6829 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
6830 i40e_get_symmetric_hash_enable_per_port(hw,
6831 &(info->info.enable));
6833 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
6834 ret = i40e_get_hash_filter_global_config(hw,
6835 &(info->info.global_conf));
6838 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
6848 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
6853 PMD_DRV_LOG(ERR, "Invalid pointer");
6857 switch (info->info_type) {
6858 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
6859 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
6861 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
6862 ret = i40e_set_hash_filter_global_config(hw,
6863 &(info->info.global_conf));
6865 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
6866 ret = i40e_filter_inset_select(hw,
6867 &(info->info.input_set_conf),
6868 RTE_ETH_FILTER_HASH);
6872 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
6881 /* Operations for hash function */
6883 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
6884 enum rte_filter_op filter_op,
6887 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6890 switch (filter_op) {
6891 case RTE_ETH_FILTER_NOP:
6893 case RTE_ETH_FILTER_GET:
6894 ret = i40e_hash_filter_get(hw,
6895 (struct rte_eth_hash_filter_info *)arg);
6897 case RTE_ETH_FILTER_SET:
6898 ret = i40e_hash_filter_set(hw,
6899 (struct rte_eth_hash_filter_info *)arg);
6902 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
6912 * Configure ethertype filter, which can director packet by filtering
6913 * with mac address and ether_type or only ether_type
6916 i40e_ethertype_filter_set(struct i40e_pf *pf,
6917 struct rte_eth_ethertype_filter *filter,
6920 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6921 struct i40e_control_filter_stats stats;
6925 if (filter->queue >= pf->dev_data->nb_rx_queues) {
6926 PMD_DRV_LOG(ERR, "Invalid queue ID");
6929 if (filter->ether_type == ETHER_TYPE_IPv4 ||
6930 filter->ether_type == ETHER_TYPE_IPv6) {
6931 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
6932 " control packet filter.", filter->ether_type);
6935 if (filter->ether_type == ETHER_TYPE_VLAN)
6936 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
6939 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
6940 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
6941 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
6942 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
6943 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
6945 memset(&stats, 0, sizeof(stats));
6946 ret = i40e_aq_add_rem_control_packet_filter(hw,
6947 filter->mac_addr.addr_bytes,
6948 filter->ether_type, flags,
6950 filter->queue, add, &stats, NULL);
6952 PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
6953 " mac_etype_used = %u, etype_used = %u,"
6954 " mac_etype_free = %u, etype_free = %u\n",
6955 ret, stats.mac_etype_used, stats.etype_used,
6956 stats.mac_etype_free, stats.etype_free);
6963 * Handle operations for ethertype filter.
6966 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
6967 enum rte_filter_op filter_op,
6970 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6973 if (filter_op == RTE_ETH_FILTER_NOP)
6977 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
6982 switch (filter_op) {
6983 case RTE_ETH_FILTER_ADD:
6984 ret = i40e_ethertype_filter_set(pf,
6985 (struct rte_eth_ethertype_filter *)arg,
6988 case RTE_ETH_FILTER_DELETE:
6989 ret = i40e_ethertype_filter_set(pf,
6990 (struct rte_eth_ethertype_filter *)arg,
6994 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
7002 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
7003 enum rte_filter_type filter_type,
7004 enum rte_filter_op filter_op,
7012 switch (filter_type) {
7013 case RTE_ETH_FILTER_NONE:
7014 /* For global configuration */
7015 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
7017 case RTE_ETH_FILTER_HASH:
7018 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
7020 case RTE_ETH_FILTER_MACVLAN:
7021 ret = i40e_mac_filter_handle(dev, filter_op, arg);
7023 case RTE_ETH_FILTER_ETHERTYPE:
7024 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
7026 case RTE_ETH_FILTER_TUNNEL:
7027 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
7029 case RTE_ETH_FILTER_FDIR:
7030 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
7033 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7043 * As some registers wouldn't be reset unless a global hardware reset,
7044 * hardware initialization is needed to put those registers into an
7045 * expected initial state.
7048 i40e_hw_init(struct i40e_hw *hw)
7050 /* clear the PF Queue Filter control register */
7051 I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0);
7053 /* Disable symmetric hash per port */
7054 i40e_set_symmetric_hash_enable_per_port(hw, 0);
7057 enum i40e_filter_pctype
7058 i40e_flowtype_to_pctype(uint16_t flow_type)
7060 static const enum i40e_filter_pctype pctype_table[] = {
7061 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
7062 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
7063 I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
7064 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
7065 I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
7066 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
7067 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
7068 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
7069 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
7070 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
7071 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
7072 I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
7073 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
7074 I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
7075 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
7076 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
7077 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
7078 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
7079 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
7082 return pctype_table[flow_type];
7086 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
7088 static const uint16_t flowtype_table[] = {
7089 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
7090 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7091 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
7092 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7093 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
7094 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7095 RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
7096 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7097 RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
7098 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
7099 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7100 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
7101 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7102 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
7103 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7104 RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
7105 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7106 RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
7107 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
7110 return flowtype_table[pctype];
7114 * On X710, performance number is far from the expectation on recent firmware
7115 * versions; on XL710, performance number is also far from the expectation on
7116 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
7117 * mode is enabled and port MAC address is equal to the packet destination MAC
7118 * address. The fix for this issue may not be integrated in the following
7119 * firmware version. So the workaround in software driver is needed. It needs
7120 * to modify the initial values of 3 internal only registers for both X710 and
7121 * XL710. Note that the values for X710 or XL710 could be different, and the
7122 * workaround can be removed when it is fixed in firmware in the future.
7125 /* For both X710 and XL710 */
7126 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
7127 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
7129 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
7130 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
7133 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
7135 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
7136 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
7139 i40e_configure_registers(struct i40e_hw *hw)
7145 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
7146 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
7147 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
7153 for (i = 0; i < RTE_DIM(reg_table); i++) {
7154 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
7155 if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
7157 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
7160 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
7163 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
7166 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
7170 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
7171 reg_table[i].addr, reg);
7172 if (reg == reg_table[i].val)
7175 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
7176 reg_table[i].val, NULL);
7178 PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
7179 "address of 0x%"PRIx32, reg_table[i].val,
7183 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
7184 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
7188 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
7189 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
7190 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
7191 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
7193 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
7198 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
7199 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
7203 /* Configure for double VLAN RX stripping */
7204 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
7205 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
7206 reg |= I40E_VSI_TSR_QINQ_CONFIG;
7207 ret = i40e_aq_debug_write_register(hw,
7208 I40E_VSI_TSR(vsi->vsi_id),
7211 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
7213 return I40E_ERR_CONFIG;
7217 /* Configure for double VLAN TX insertion */
7218 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
7219 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
7220 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
7221 ret = i40e_aq_debug_write_register(hw,
7222 I40E_VSI_L2TAGSTXVALID(
7223 vsi->vsi_id), reg, NULL);
7225 PMD_DRV_LOG(ERR, "Failed to update "
7226 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
7227 return I40E_ERR_CONFIG;
7235 * i40e_aq_add_mirror_rule
7236 * @hw: pointer to the hardware structure
7237 * @seid: VEB seid to add mirror rule to
7238 * @dst_id: destination vsi seid
7239 * @entries: Buffer which contains the entities to be mirrored
7240 * @count: number of entities contained in the buffer
7241 * @rule_id:the rule_id of the rule to be added
7243 * Add a mirror rule for a given veb.
7246 static enum i40e_status_code
7247 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
7248 uint16_t seid, uint16_t dst_id,
7249 uint16_t rule_type, uint16_t *entries,
7250 uint16_t count, uint16_t *rule_id)
7252 struct i40e_aq_desc desc;
7253 struct i40e_aqc_add_delete_mirror_rule cmd;
7254 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
7255 (struct i40e_aqc_add_delete_mirror_rule_completion *)
7258 enum i40e_status_code status;
7260 i40e_fill_default_direct_cmd_desc(&desc,
7261 i40e_aqc_opc_add_mirror_rule);
7262 memset(&cmd, 0, sizeof(cmd));
7264 buff_len = sizeof(uint16_t) * count;
7265 desc.datalen = rte_cpu_to_le_16(buff_len);
7267 desc.flags |= rte_cpu_to_le_16(
7268 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
7269 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7270 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7271 cmd.num_entries = rte_cpu_to_le_16(count);
7272 cmd.seid = rte_cpu_to_le_16(seid);
7273 cmd.destination = rte_cpu_to_le_16(dst_id);
7275 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7276 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
7277 PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
7279 " mirror_rules_used = %u, mirror_rules_free = %u,",
7280 hw->aq.asq_last_status, resp->rule_id,
7281 resp->mirror_rules_used, resp->mirror_rules_free);
7282 *rule_id = rte_le_to_cpu_16(resp->rule_id);
7288 * i40e_aq_del_mirror_rule
7289 * @hw: pointer to the hardware structure
7290 * @seid: VEB seid to add mirror rule to
7291 * @entries: Buffer which contains the entities to be mirrored
7292 * @count: number of entities contained in the buffer
7293 * @rule_id:the rule_id of the rule to be delete
7295 * Delete a mirror rule for a given veb.
7298 static enum i40e_status_code
7299 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
7300 uint16_t seid, uint16_t rule_type, uint16_t *entries,
7301 uint16_t count, uint16_t rule_id)
7303 struct i40e_aq_desc desc;
7304 struct i40e_aqc_add_delete_mirror_rule cmd;
7305 uint16_t buff_len = 0;
7306 enum i40e_status_code status;
7309 i40e_fill_default_direct_cmd_desc(&desc,
7310 i40e_aqc_opc_delete_mirror_rule);
7311 memset(&cmd, 0, sizeof(cmd));
7312 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
7313 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
7315 cmd.num_entries = count;
7316 buff_len = sizeof(uint16_t) * count;
7317 desc.datalen = rte_cpu_to_le_16(buff_len);
7318 buff = (void *)entries;
7320 /* rule id is filled in destination field for deleting mirror rule */
7321 cmd.destination = rte_cpu_to_le_16(rule_id);
7323 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7324 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7325 cmd.seid = rte_cpu_to_le_16(seid);
7327 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7328 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
7334 * i40e_mirror_rule_set
7335 * @dev: pointer to the hardware structure
7336 * @mirror_conf: mirror rule info
7337 * @sw_id: mirror rule's sw_id
7338 * @on: enable/disable
7340 * set a mirror rule.
7344 i40e_mirror_rule_set(struct rte_eth_dev *dev,
7345 struct rte_eth_mirror_conf *mirror_conf,
7346 uint8_t sw_id, uint8_t on)
7348 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7349 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7350 struct i40e_mirror_rule *it, *mirr_rule = NULL;
7351 struct i40e_mirror_rule *parent = NULL;
7352 uint16_t seid, dst_seid, rule_id;
7356 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
7358 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
7359 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
7360 " without veb or vfs.");
7363 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
7364 PMD_DRV_LOG(ERR, "mirror table is full.");
7367 if (mirror_conf->dst_pool > pf->vf_num) {
7368 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
7369 mirror_conf->dst_pool);
7373 seid = pf->main_vsi->veb->seid;
7375 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
7376 if (sw_id <= it->index) {
7382 if (mirr_rule && sw_id == mirr_rule->index) {
7384 PMD_DRV_LOG(ERR, "mirror rule exists.");
7387 ret = i40e_aq_del_mirror_rule(hw, seid,
7388 mirr_rule->rule_type,
7390 mirr_rule->num_entries, mirr_rule->id);
7392 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
7393 " ret = %d, aq_err = %d.",
7394 ret, hw->aq.asq_last_status);
7397 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
7398 rte_free(mirr_rule);
7399 pf->nb_mirror_rule--;
7403 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
7407 mirr_rule = rte_zmalloc("i40e_mirror_rule",
7408 sizeof(struct i40e_mirror_rule) , 0);
7410 PMD_DRV_LOG(ERR, "failed to allocate memory");
7411 return I40E_ERR_NO_MEMORY;
7413 switch (mirror_conf->rule_type) {
7414 case ETH_MIRROR_VLAN:
7415 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
7416 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
7417 mirr_rule->entries[j] =
7418 mirror_conf->vlan.vlan_id[i];
7423 PMD_DRV_LOG(ERR, "vlan is not specified.");
7424 rte_free(mirr_rule);
7427 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
7429 case ETH_MIRROR_VIRTUAL_POOL_UP:
7430 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
7431 /* check if the specified pool bit is out of range */
7432 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
7433 PMD_DRV_LOG(ERR, "pool mask is out of range.");
7434 rte_free(mirr_rule);
7437 for (i = 0, j = 0; i < pf->vf_num; i++) {
7438 if (mirror_conf->pool_mask & (1ULL << i)) {
7439 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
7443 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
7444 /* add pf vsi to entries */
7445 mirr_rule->entries[j] = pf->main_vsi_seid;
7449 PMD_DRV_LOG(ERR, "pool is not specified.");
7450 rte_free(mirr_rule);
7453 /* egress and ingress in aq commands means from switch but not port */
7454 mirr_rule->rule_type =
7455 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
7456 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
7457 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
7459 case ETH_MIRROR_UPLINK_PORT:
7460 /* egress and ingress in aq commands means from switch but not port*/
7461 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
7463 case ETH_MIRROR_DOWNLINK_PORT:
7464 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
7467 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
7468 mirror_conf->rule_type);
7469 rte_free(mirr_rule);
7473 /* If the dst_pool is equal to vf_num, consider it as PF */
7474 if (mirror_conf->dst_pool == pf->vf_num)
7475 dst_seid = pf->main_vsi_seid;
7477 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
7479 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
7480 mirr_rule->rule_type, mirr_rule->entries,
7483 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
7484 " ret = %d, aq_err = %d.",
7485 ret, hw->aq.asq_last_status);
7486 rte_free(mirr_rule);
7490 mirr_rule->index = sw_id;
7491 mirr_rule->num_entries = j;
7492 mirr_rule->id = rule_id;
7493 mirr_rule->dst_vsi_seid = dst_seid;
7496 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
7498 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
7500 pf->nb_mirror_rule++;
7505 * i40e_mirror_rule_reset
7506 * @dev: pointer to the device
7507 * @sw_id: mirror rule's sw_id
7509 * reset a mirror rule.
7513 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
7515 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7516 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7517 struct i40e_mirror_rule *it, *mirr_rule = NULL;
7521 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
7523 seid = pf->main_vsi->veb->seid;
7525 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
7526 if (sw_id == it->index) {
7532 ret = i40e_aq_del_mirror_rule(hw, seid,
7533 mirr_rule->rule_type,
7535 mirr_rule->num_entries, mirr_rule->id);
7537 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
7538 " status = %d, aq_err = %d.",
7539 ret, hw->aq.asq_last_status);
7542 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
7543 rte_free(mirr_rule);
7544 pf->nb_mirror_rule--;
7546 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
7553 i40e_timesync_enable(struct rte_eth_dev *dev)
7555 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7556 struct rte_eth_link *link = &dev->data->dev_link;
7557 uint32_t tsync_ctl_l;
7558 uint32_t tsync_ctl_h;
7559 uint32_t tsync_inc_l;
7560 uint32_t tsync_inc_h;
7562 switch (link->link_speed) {
7563 case ETH_LINK_SPEED_40G:
7564 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
7565 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
7567 case ETH_LINK_SPEED_10G:
7568 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
7569 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
7571 case ETH_LINK_SPEED_1000:
7572 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
7573 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
7580 /* Clear timesync registers. */
7581 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
7582 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
7583 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(0));
7584 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(1));
7585 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(2));
7586 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(3));
7587 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
7589 /* Set the timesync increment value. */
7590 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
7591 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
7593 /* Enable timestamping of PTP packets. */
7594 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
7595 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
7597 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
7598 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
7599 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
7601 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
7602 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
7608 i40e_timesync_disable(struct rte_eth_dev *dev)
7610 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7611 uint32_t tsync_ctl_l;
7612 uint32_t tsync_ctl_h;
7614 /* Disable timestamping of transmitted PTP packets. */
7615 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
7616 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
7618 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
7619 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
7621 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
7622 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
7624 /* Set the timesync increment value. */
7625 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
7626 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
7632 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
7633 struct timespec *timestamp, uint32_t flags)
7635 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7636 uint32_t sync_status;
7639 uint32_t index = flags & 0x03;
7641 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
7642 if ((sync_status & (1 << index)) == 0)
7645 rx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
7646 rx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index));
7648 timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
7649 timestamp->tv_nsec = 0;
7655 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
7656 struct timespec *timestamp)
7658 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7659 uint32_t sync_status;
7663 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
7664 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
7667 tx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
7668 tx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
7670 timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
7671 timestamp->tv_nsec = 0;
7677 * i40e_parse_dcb_configure - parse dcb configure from user
7678 * @dev: the device being configured
7679 * @dcb_cfg: pointer of the result of parse
7680 * @*tc_map: bit map of enabled traffic classes
7682 * Returns 0 on success, negative value on failure
7685 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
7686 struct i40e_dcbx_config *dcb_cfg,
7689 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
7690 uint8_t i, tc_bw, bw_lf;
7692 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
7694 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
7695 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
7696 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
7700 /* assume each tc has the same bw */
7701 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
7702 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
7703 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
7704 /* to ensure the sum of tcbw is equal to 100 */
7705 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
7706 for (i = 0; i < bw_lf; i++)
7707 dcb_cfg->etscfg.tcbwtable[i]++;
7709 /* assume each tc has the same Transmission Selection Algorithm */
7710 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
7711 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
7713 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
7714 dcb_cfg->etscfg.prioritytable[i] =
7715 dcb_rx_conf->dcb_tc[i];
7717 /* FW needs one App to configure HW */
7718 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
7719 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
7720 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
7721 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
7723 if (dcb_rx_conf->nb_tcs == 0)
7724 *tc_map = 1; /* tc0 only */
7726 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
7728 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
7729 dcb_cfg->pfc.willing = 0;
7730 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
7731 dcb_cfg->pfc.pfcenable = *tc_map;
7737 * i40e_vsi_get_bw_info - Query VSI BW Information
7738 * @vsi: the VSI being queried
7740 * Returns 0 on success, negative value on failure
7743 i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
7745 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
7746 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
7747 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7751 /* Get the VSI level BW configuration */
7752 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
7755 "couldn't get PF vsi bw config, err %s aq_err %s\n",
7756 i40e_stat_str(hw, ret),
7757 i40e_aq_str(hw, hw->aq.asq_last_status));
7761 /* Get the VSI level BW configuration per TC */
7762 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
7766 "couldn't get PF vsi ets bw config, err %s aq_err %s\n",
7767 i40e_stat_str(hw, ret),
7768 i40e_aq_str(hw, hw->aq.asq_last_status));
7772 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
7773 PMD_INIT_LOG(WARNING,
7774 "Enabled TCs mismatch from querying VSI BW info"
7775 " 0x%08x 0x%08x\n", bw_config.tc_valid_bits,
7776 bw_ets_config.tc_valid_bits);
7777 /* Still continuing */
7780 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
7781 vsi->bw_info.bw_max_quanta = bw_config.max_bw;
7782 tc_bw_max = rte_le_to_cpu_16(bw_ets_config.tc_bw_max[0]) |
7783 (rte_le_to_cpu_16(bw_ets_config.tc_bw_max[1]) << 16);
7784 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
7785 vsi->bw_info.bw_ets_share_credits[i] =
7786 bw_ets_config.share_credits[i];
7787 vsi->bw_info.bw_ets_limit_credits[i] =
7788 rte_le_to_cpu_16(bw_ets_config.credits[i]);
7789 /* 3 bits out of 4 for each TC */
7790 vsi->bw_info.bw_ets_max_quanta[i] =
7791 (uint8_t)((tc_bw_max >> (i * 4)) & 0x7);
7793 "%s: vsi seid = %d, TC = %d, qset = 0x%x\n",
7794 __func__, vsi->seid, i, bw_config.qs_handles[i]);
7801 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
7802 struct i40e_aqc_vsi_properties_data *info,
7803 uint8_t enabled_tcmap)
7805 int ret, i, total_tc = 0;
7806 uint16_t qpnum_per_tc, bsf, qp_idx;
7807 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
7809 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
7810 if (ret != I40E_SUCCESS)
7813 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
7814 if (enabled_tcmap & (1 << i))
7819 vsi->enabled_tc = enabled_tcmap;
7821 qpnum_per_tc = dev_data->nb_rx_queues / total_tc;
7822 /* Number of queues per enabled TC */
7823 if (qpnum_per_tc == 0) {
7824 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
7825 return I40E_ERR_INVALID_QP_ID;
7827 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
7829 bsf = rte_bsf32(qpnum_per_tc);
7832 * Configure TC and queue mapping parameters, for enabled TC,
7833 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
7834 * default queue will serve it.
7837 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
7838 if (vsi->enabled_tc & (1 << i)) {
7839 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
7840 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
7841 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
7842 qp_idx += qpnum_per_tc;
7844 info->tc_mapping[i] = 0;
7847 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
7848 if (vsi->type == I40E_VSI_SRIOV) {
7849 info->mapping_flags |=
7850 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
7851 for (i = 0; i < vsi->nb_qps; i++)
7852 info->queue_mapping[i] =
7853 rte_cpu_to_le_16(vsi->base_queue + i);
7855 info->mapping_flags |=
7856 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
7857 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
7859 info->valid_sections |=
7860 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
7862 return I40E_SUCCESS;
7866 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
7867 * @vsi: VSI to be configured
7868 * @tc_map: enabled TC bitmap
7870 * Returns 0 on success, negative value on failure
7873 i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 tc_map)
7875 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
7876 struct i40e_vsi_context ctxt;
7877 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7881 /* Check if enabled_tc is same as existing or new TCs */
7882 if (vsi->enabled_tc == tc_map)
7885 /* configure tc bandwidth */
7886 memset(&bw_data, 0, sizeof(bw_data));
7887 bw_data.tc_valid_bits = tc_map;
7888 /* Enable ETS TCs with equal BW Share for now across all VSIs */
7889 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
7890 if (tc_map & BIT_ULL(i))
7891 bw_data.tc_bw_credits[i] = 1;
7893 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
7895 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
7896 " per TC failed = %d",
7897 hw->aq.asq_last_status);
7900 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
7901 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
7903 /* Update Queue Pairs Mapping for currently enabled UPs */
7904 ctxt.seid = vsi->seid;
7905 ctxt.pf_num = hw->pf_id;
7907 ctxt.uplink_seid = vsi->uplink_seid;
7908 ctxt.info = vsi->info;
7910 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
7914 /* Update the VSI after updating the VSI queue-mapping information */
7915 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
7917 PMD_INIT_LOG(ERR, "Failed to configure "
7918 "TC queue mapping = %d",
7919 hw->aq.asq_last_status);
7922 /* update the local VSI info with updated queue map */
7923 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
7924 sizeof(vsi->info.tc_mapping));
7925 (void)rte_memcpy(&vsi->info.queue_mapping,
7926 &ctxt.info.queue_mapping,
7927 sizeof(vsi->info.queue_mapping));
7928 vsi->info.mapping_flags = ctxt.info.mapping_flags;
7929 vsi->info.valid_sections = 0;
7931 /* Update current VSI BW information */
7932 ret = i40e_vsi_get_bw_info(vsi);
7935 "Failed updating vsi bw info, err %s aq_err %s",
7936 i40e_stat_str(hw, ret),
7937 i40e_aq_str(hw, hw->aq.asq_last_status));
7941 vsi->enabled_tc = tc_map;
7948 * i40e_dcb_hw_configure - program the dcb setting to hw
7949 * @pf: pf the configuration is taken on
7950 * @new_cfg: new configuration
7951 * @tc_map: enabled TC bitmap
7953 * Returns 0 on success, negative value on failure
7955 static enum i40e_status_code
7956 i40e_dcb_hw_configure(struct i40e_pf *pf,
7957 struct i40e_dcbx_config *new_cfg,
7960 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7961 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
7962 struct i40e_vsi *main_vsi = pf->main_vsi;
7963 struct i40e_vsi_list *vsi_list;
7967 /* Use the FW API if FW > v4.4*/
7968 if (!((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4))) {
7969 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
7970 " to configure DCB");
7971 return I40E_ERR_FIRMWARE_API_VERSION;
7974 /* Check if need reconfiguration */
7975 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
7976 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
7977 return I40E_SUCCESS;
7980 /* Copy the new config to the current config */
7981 *old_cfg = *new_cfg;
7982 old_cfg->etsrec = old_cfg->etscfg;
7983 ret = i40e_set_dcb_config(hw);
7986 "Set DCB Config failed, err %s aq_err %s\n",
7987 i40e_stat_str(hw, ret),
7988 i40e_aq_str(hw, hw->aq.asq_last_status));
7991 /* set receive Arbiter to RR mode and ETS scheme by default */
7992 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
7993 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
7994 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
7995 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
7996 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
7997 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
7998 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
7999 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
8000 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
8001 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
8002 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
8003 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
8004 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
8006 /* get local mib to check whether it is configured correctly */
8008 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
8009 /* Get Local DCB Config */
8010 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
8011 &hw->local_dcbx_config);
8013 /* Update each VSI */
8014 i40e_vsi_config_tc(main_vsi, tc_map);
8015 if (main_vsi->veb) {
8016 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
8017 /* Beside main VSI, only enable default
8020 ret = i40e_vsi_config_tc(vsi_list->vsi,
8021 I40E_DEFAULT_TCMAP);
8023 PMD_INIT_LOG(WARNING,
8024 "Failed configuring TC for VSI seid=%d\n",
8025 vsi_list->vsi->seid);
8029 return I40E_SUCCESS;
8033 * i40e_dcb_init_configure - initial dcb config
8034 * @dev: device being configured
8035 * @sw_dcb: indicate whether dcb is sw configured or hw offload
8037 * Returns 0 on success, negative value on failure
8040 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
8042 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8043 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8046 if ((pf->flags & I40E_FLAG_DCB) == 0) {
8047 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8051 /* DCB initialization:
8052 * Update DCB configuration from the Firmware and configure
8053 * LLDP MIB change event.
8055 if (sw_dcb == TRUE) {
8056 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
8057 if (ret != I40E_SUCCESS)
8058 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
8060 ret = i40e_init_dcb(hw);
8061 /* if sw_dcb, lldp agent is stopped, the return from
8062 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
8065 if (ret != I40E_SUCCESS &&
8066 hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
8067 memset(&hw->local_dcbx_config, 0,
8068 sizeof(struct i40e_dcbx_config));
8069 /* set dcb default configuration */
8070 hw->local_dcbx_config.etscfg.willing = 0;
8071 hw->local_dcbx_config.etscfg.maxtcs = 0;
8072 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
8073 hw->local_dcbx_config.etscfg.tsatable[0] =
8075 hw->local_dcbx_config.etsrec =
8076 hw->local_dcbx_config.etscfg;
8077 hw->local_dcbx_config.pfc.willing = 0;
8078 hw->local_dcbx_config.pfc.pfccap =
8079 I40E_MAX_TRAFFIC_CLASS;
8080 /* FW needs one App to configure HW */
8081 hw->local_dcbx_config.numapps = 1;
8082 hw->local_dcbx_config.app[0].selector =
8083 I40E_APP_SEL_ETHTYPE;
8084 hw->local_dcbx_config.app[0].priority = 3;
8085 hw->local_dcbx_config.app[0].protocolid =
8086 I40E_APP_PROTOID_FCOE;
8087 ret = i40e_set_dcb_config(hw);
8089 PMD_INIT_LOG(ERR, "default dcb config fails."
8090 " err = %d, aq_err = %d.", ret,
8091 hw->aq.asq_last_status);
8095 PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8096 " aq_err = %d.", ret,
8097 hw->aq.asq_last_status);
8101 ret = i40e_aq_start_lldp(hw, NULL);
8102 if (ret != I40E_SUCCESS)
8103 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
8105 ret = i40e_init_dcb(hw);
8107 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
8108 PMD_INIT_LOG(ERR, "HW doesn't support"
8113 PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8114 " aq_err = %d.", ret,
8115 hw->aq.asq_last_status);
8123 * i40e_dcb_setup - setup dcb related config
8124 * @dev: device being configured
8126 * Returns 0 on success, negative value on failure
8129 i40e_dcb_setup(struct rte_eth_dev *dev)
8131 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8132 struct i40e_dcbx_config dcb_cfg;
8136 if ((pf->flags & I40E_FLAG_DCB) == 0) {
8137 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8141 if (pf->vf_num != 0 ||
8142 (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG))
8143 PMD_INIT_LOG(DEBUG, " DCB only works on main vsi.");
8145 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
8147 PMD_INIT_LOG(ERR, "invalid dcb config");
8150 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
8152 PMD_INIT_LOG(ERR, "dcb sw configure fails");
8159 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
8160 struct rte_eth_dcb_info *dcb_info)
8162 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8163 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8164 struct i40e_vsi *vsi = pf->main_vsi;
8165 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
8166 uint16_t bsf, tc_mapping;
8169 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
8170 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
8172 dcb_info->nb_tcs = 1;
8173 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8174 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
8175 for (i = 0; i < dcb_info->nb_tcs; i++)
8176 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
8178 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8179 if (vsi->enabled_tc & (1 << i)) {
8180 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
8181 /* only main vsi support multi TCs */
8182 dcb_info->tc_queue.tc_rxq[0][i].base =
8183 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
8184 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
8185 dcb_info->tc_queue.tc_txq[0][i].base =
8186 dcb_info->tc_queue.tc_rxq[0][i].base;
8187 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
8188 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
8189 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 1 << bsf;
8190 dcb_info->tc_queue.tc_txq[0][i].nb_queue =
8191 dcb_info->tc_queue.tc_rxq[0][i].nb_queue;