1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
14 #include <rte_common.h>
16 #include <rte_string_fns.h>
18 #include <rte_bus_pci.h>
19 #include <rte_ether.h>
20 #include <rte_ethdev_driver.h>
21 #include <rte_ethdev_pci.h>
22 #include <rte_memzone.h>
23 #include <rte_malloc.h>
24 #include <rte_memcpy.h>
25 #include <rte_alarm.h>
27 #include <rte_tailq.h>
28 #include <rte_hash_crc.h>
29 #include <rte_bitmap.h>
31 #include "i40e_logs.h"
32 #include "base/i40e_prototype.h"
33 #include "base/i40e_adminq_cmd.h"
34 #include "base/i40e_type.h"
35 #include "base/i40e_register.h"
36 #include "base/i40e_dcb.h"
37 #include "i40e_ethdev.h"
38 #include "i40e_rxtx.h"
40 #include "i40e_regs.h"
41 #include "rte_pmd_i40e.h"
43 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
44 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
45 #define ETH_I40E_SUPPORT_MULTI_DRIVER "support-multi-driver"
46 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG "queue-num-per-vf"
47 #define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec"
48 #define ETH_I40E_VF_MSG_CFG "vf_msg_cfg"
50 #define I40E_CLEAR_PXE_WAIT_MS 200
51 #define I40E_VSI_TSR_QINQ_STRIP 0x4010
52 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
54 /* Maximun number of capability elements */
55 #define I40E_MAX_CAP_ELE_NUM 128
57 /* Wait count and interval */
58 #define I40E_CHK_Q_ENA_COUNT 1000
59 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
61 /* Maximun number of VSI */
62 #define I40E_MAX_NUM_VSIS (384UL)
64 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
66 /* Flow control default timer */
67 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
69 /* Flow control enable fwd bit */
70 #define I40E_PRTMAC_FWD_CTRL 0x00000001
72 /* Receive Packet Buffer size */
73 #define I40E_RXPBSIZE (968 * 1024)
76 #define I40E_KILOSHIFT 10
78 /* Flow control default high water */
79 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
81 /* Flow control default low water */
82 #define I40E_DEFAULT_LOW_WATER (0xF2000 >> I40E_KILOSHIFT)
84 /* Receive Average Packet Size in Byte*/
85 #define I40E_PACKET_AVERAGE_SIZE 128
87 /* Mask of PF interrupt causes */
88 #define I40E_PFINT_ICR0_ENA_MASK ( \
89 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
90 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
91 I40E_PFINT_ICR0_ENA_GRST_MASK | \
92 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
93 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
94 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
95 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
96 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
97 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
99 #define I40E_FLOW_TYPES ( \
100 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
101 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
102 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
103 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
104 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
105 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
106 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
107 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
108 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
109 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
110 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
112 /* Additional timesync values. */
113 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
114 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
115 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
116 #define I40E_PRTTSYN_TSYNENA 0x80000000
117 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
118 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
121 * Below are values for writing un-exposed registers suggested
124 /* Destination MAC address */
125 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
126 /* Source MAC address */
127 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
128 /* Outer (S-Tag) VLAN tag in the outer L2 header */
129 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
130 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
131 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
132 /* Single VLAN tag in the inner L2 header */
133 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
134 /* Source IPv4 address */
135 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
136 /* Destination IPv4 address */
137 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
138 /* Source IPv4 address for X722 */
139 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
140 /* Destination IPv4 address for X722 */
141 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
142 /* IPv4 Protocol for X722 */
143 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
144 /* IPv4 Time to Live for X722 */
145 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
146 /* IPv4 Type of Service (TOS) */
147 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
149 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
150 /* IPv4 Time to Live */
151 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
152 /* Source IPv6 address */
153 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
154 /* Destination IPv6 address */
155 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
156 /* IPv6 Traffic Class (TC) */
157 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
158 /* IPv6 Next Header */
159 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
161 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
163 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
164 /* Destination L4 port */
165 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
166 /* SCTP verification tag */
167 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
168 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
169 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
170 /* Source port of tunneling UDP */
171 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
172 /* Destination port of tunneling UDP */
173 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
174 /* UDP Tunneling ID, NVGRE/GRE key */
175 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
176 /* Last ether type */
177 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
178 /* Tunneling outer destination IPv4 address */
179 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
180 /* Tunneling outer destination IPv6 address */
181 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
182 /* 1st word of flex payload */
183 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
184 /* 2nd word of flex payload */
185 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
186 /* 3rd word of flex payload */
187 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
188 /* 4th word of flex payload */
189 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
190 /* 5th word of flex payload */
191 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
192 /* 6th word of flex payload */
193 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
194 /* 7th word of flex payload */
195 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
196 /* 8th word of flex payload */
197 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
198 /* all 8 words flex payload */
199 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
200 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
202 #define I40E_TRANSLATE_INSET 0
203 #define I40E_TRANSLATE_REG 1
205 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
206 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
207 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
208 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
209 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
210 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
212 /* PCI offset for querying capability */
213 #define PCI_DEV_CAP_REG 0xA4
214 /* PCI offset for enabling/disabling Extended Tag */
215 #define PCI_DEV_CTRL_REG 0xA8
216 /* Bit mask of Extended Tag capability */
217 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
218 /* Bit shift of Extended Tag enable/disable */
219 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
220 /* Bit mask of Extended Tag enable/disable */
221 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
223 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
224 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
225 static int i40e_dev_configure(struct rte_eth_dev *dev);
226 static int i40e_dev_start(struct rte_eth_dev *dev);
227 static int i40e_dev_stop(struct rte_eth_dev *dev);
228 static int i40e_dev_close(struct rte_eth_dev *dev);
229 static int i40e_dev_reset(struct rte_eth_dev *dev);
230 static int i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
231 static int i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
232 static int i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
233 static int i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
234 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
235 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
236 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
237 struct rte_eth_stats *stats);
238 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
239 struct rte_eth_xstat *xstats, unsigned n);
240 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
241 struct rte_eth_xstat_name *xstats_names,
243 static int i40e_dev_stats_reset(struct rte_eth_dev *dev);
244 static int i40e_fw_version_get(struct rte_eth_dev *dev,
245 char *fw_version, size_t fw_size);
246 static int i40e_dev_info_get(struct rte_eth_dev *dev,
247 struct rte_eth_dev_info *dev_info);
248 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
251 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
252 enum rte_vlan_type vlan_type,
254 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
255 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
258 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
259 static int i40e_dev_led_on(struct rte_eth_dev *dev);
260 static int i40e_dev_led_off(struct rte_eth_dev *dev);
261 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
262 struct rte_eth_fc_conf *fc_conf);
263 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
264 struct rte_eth_fc_conf *fc_conf);
265 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
266 struct rte_eth_pfc_conf *pfc_conf);
267 static int i40e_macaddr_add(struct rte_eth_dev *dev,
268 struct rte_ether_addr *mac_addr,
271 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
272 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
273 struct rte_eth_rss_reta_entry64 *reta_conf,
275 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
276 struct rte_eth_rss_reta_entry64 *reta_conf,
279 static int i40e_get_cap(struct i40e_hw *hw);
280 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
281 static int i40e_pf_setup(struct i40e_pf *pf);
282 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
283 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
284 static int i40e_dcb_setup(struct rte_eth_dev *dev);
285 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
286 bool offset_loaded, uint64_t *offset, uint64_t *stat);
287 static void i40e_stat_update_48(struct i40e_hw *hw,
293 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
294 static void i40e_dev_interrupt_handler(void *param);
295 static void i40e_dev_alarm_handler(void *param);
296 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
297 uint32_t base, uint32_t num);
298 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
299 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
301 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
303 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
304 static int i40e_veb_release(struct i40e_veb *veb);
305 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
306 struct i40e_vsi *vsi);
307 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
308 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
309 struct i40e_macvlan_filter *mv_f,
312 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
313 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
314 struct rte_eth_rss_conf *rss_conf);
315 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
316 struct rte_eth_rss_conf *rss_conf);
317 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
318 struct rte_eth_udp_tunnel *udp_tunnel);
319 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
320 struct rte_eth_udp_tunnel *udp_tunnel);
321 static void i40e_filter_input_set_init(struct i40e_pf *pf);
322 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
323 enum rte_filter_op filter_op,
325 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
326 enum rte_filter_type filter_type,
327 enum rte_filter_op filter_op,
329 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
330 struct rte_eth_dcb_info *dcb_info);
331 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
332 static void i40e_configure_registers(struct i40e_hw *hw);
333 static void i40e_hw_init(struct rte_eth_dev *dev);
334 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
335 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
341 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
342 struct rte_eth_mirror_conf *mirror_conf,
343 uint8_t sw_id, uint8_t on);
344 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
346 static int i40e_timesync_enable(struct rte_eth_dev *dev);
347 static int i40e_timesync_disable(struct rte_eth_dev *dev);
348 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
349 struct timespec *timestamp,
351 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
352 struct timespec *timestamp);
353 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
355 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
357 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
358 struct timespec *timestamp);
359 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
360 const struct timespec *timestamp);
362 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
364 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
367 static int i40e_get_regs(struct rte_eth_dev *dev,
368 struct rte_dev_reg_info *regs);
370 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
372 static int i40e_get_eeprom(struct rte_eth_dev *dev,
373 struct rte_dev_eeprom_info *eeprom);
375 static int i40e_get_module_info(struct rte_eth_dev *dev,
376 struct rte_eth_dev_module_info *modinfo);
377 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
378 struct rte_dev_eeprom_info *info);
380 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
381 struct rte_ether_addr *mac_addr);
383 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
385 static int i40e_ethertype_filter_convert(
386 const struct rte_eth_ethertype_filter *input,
387 struct i40e_ethertype_filter *filter);
388 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
389 struct i40e_ethertype_filter *filter);
391 static int i40e_tunnel_filter_convert(
392 struct i40e_aqc_cloud_filters_element_bb *cld_filter,
393 struct i40e_tunnel_filter *tunnel_filter);
394 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
395 struct i40e_tunnel_filter *tunnel_filter);
396 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
398 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
399 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
400 static void i40e_filter_restore(struct i40e_pf *pf);
401 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
402 static int i40e_pf_config_rss(struct i40e_pf *pf);
404 static const char *const valid_keys[] = {
405 ETH_I40E_FLOATING_VEB_ARG,
406 ETH_I40E_FLOATING_VEB_LIST_ARG,
407 ETH_I40E_SUPPORT_MULTI_DRIVER,
408 ETH_I40E_QUEUE_NUM_PER_VF_ARG,
409 ETH_I40E_USE_LATEST_VEC,
413 static const struct rte_pci_id pci_id_i40e_map[] = {
414 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
415 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
416 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
417 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
418 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
419 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
420 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
421 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
422 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
423 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
424 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
425 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
426 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
427 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
428 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
429 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
430 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
431 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
432 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X710_N3000) },
435 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_XXV710_N3000) },
436 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_BC) },
437 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_5G_BASE_T_BC) },
438 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_B) },
439 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_SFP) },
440 { .vendor_id = 0, /* sentinel */ },
443 static const struct eth_dev_ops i40e_eth_dev_ops = {
444 .dev_configure = i40e_dev_configure,
445 .dev_start = i40e_dev_start,
446 .dev_stop = i40e_dev_stop,
447 .dev_close = i40e_dev_close,
448 .dev_reset = i40e_dev_reset,
449 .promiscuous_enable = i40e_dev_promiscuous_enable,
450 .promiscuous_disable = i40e_dev_promiscuous_disable,
451 .allmulticast_enable = i40e_dev_allmulticast_enable,
452 .allmulticast_disable = i40e_dev_allmulticast_disable,
453 .dev_set_link_up = i40e_dev_set_link_up,
454 .dev_set_link_down = i40e_dev_set_link_down,
455 .link_update = i40e_dev_link_update,
456 .stats_get = i40e_dev_stats_get,
457 .xstats_get = i40e_dev_xstats_get,
458 .xstats_get_names = i40e_dev_xstats_get_names,
459 .stats_reset = i40e_dev_stats_reset,
460 .xstats_reset = i40e_dev_stats_reset,
461 .fw_version_get = i40e_fw_version_get,
462 .dev_infos_get = i40e_dev_info_get,
463 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
464 .vlan_filter_set = i40e_vlan_filter_set,
465 .vlan_tpid_set = i40e_vlan_tpid_set,
466 .vlan_offload_set = i40e_vlan_offload_set,
467 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
468 .vlan_pvid_set = i40e_vlan_pvid_set,
469 .rx_queue_start = i40e_dev_rx_queue_start,
470 .rx_queue_stop = i40e_dev_rx_queue_stop,
471 .tx_queue_start = i40e_dev_tx_queue_start,
472 .tx_queue_stop = i40e_dev_tx_queue_stop,
473 .rx_queue_setup = i40e_dev_rx_queue_setup,
474 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
475 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
476 .rx_queue_release = i40e_dev_rx_queue_release,
477 .tx_queue_setup = i40e_dev_tx_queue_setup,
478 .tx_queue_release = i40e_dev_tx_queue_release,
479 .dev_led_on = i40e_dev_led_on,
480 .dev_led_off = i40e_dev_led_off,
481 .flow_ctrl_get = i40e_flow_ctrl_get,
482 .flow_ctrl_set = i40e_flow_ctrl_set,
483 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
484 .mac_addr_add = i40e_macaddr_add,
485 .mac_addr_remove = i40e_macaddr_remove,
486 .reta_update = i40e_dev_rss_reta_update,
487 .reta_query = i40e_dev_rss_reta_query,
488 .rss_hash_update = i40e_dev_rss_hash_update,
489 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
490 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
491 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
492 .filter_ctrl = i40e_dev_filter_ctrl,
493 .rxq_info_get = i40e_rxq_info_get,
494 .txq_info_get = i40e_txq_info_get,
495 .rx_burst_mode_get = i40e_rx_burst_mode_get,
496 .tx_burst_mode_get = i40e_tx_burst_mode_get,
497 .mirror_rule_set = i40e_mirror_rule_set,
498 .mirror_rule_reset = i40e_mirror_rule_reset,
499 .timesync_enable = i40e_timesync_enable,
500 .timesync_disable = i40e_timesync_disable,
501 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
502 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
503 .get_dcb_info = i40e_dev_get_dcb_info,
504 .timesync_adjust_time = i40e_timesync_adjust_time,
505 .timesync_read_time = i40e_timesync_read_time,
506 .timesync_write_time = i40e_timesync_write_time,
507 .get_reg = i40e_get_regs,
508 .get_eeprom_length = i40e_get_eeprom_length,
509 .get_eeprom = i40e_get_eeprom,
510 .get_module_info = i40e_get_module_info,
511 .get_module_eeprom = i40e_get_module_eeprom,
512 .mac_addr_set = i40e_set_default_mac_addr,
513 .mtu_set = i40e_dev_mtu_set,
514 .tm_ops_get = i40e_tm_ops_get,
515 .tx_done_cleanup = i40e_tx_done_cleanup,
518 /* store statistics names and its offset in stats structure */
519 struct rte_i40e_xstats_name_off {
520 char name[RTE_ETH_XSTATS_NAME_SIZE];
524 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
525 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
526 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
527 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
528 {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
529 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
530 rx_unknown_protocol)},
531 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
532 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
533 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
534 {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
537 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
538 sizeof(rte_i40e_stats_strings[0]))
540 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
541 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
542 tx_dropped_link_down)},
543 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
544 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
546 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
547 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
549 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
551 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
553 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
554 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
555 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
556 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
557 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
558 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
560 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
562 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
564 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
566 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
568 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
570 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
572 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
574 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
575 mac_short_packet_dropped)},
576 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
578 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
579 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
580 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
582 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
584 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
586 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
588 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
590 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
592 {"rx_flow_director_atr_match_packets",
593 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
594 {"rx_flow_director_sb_match_packets",
595 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
596 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
598 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
600 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
602 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
606 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
607 sizeof(rte_i40e_hw_port_strings[0]))
609 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
610 {"xon_packets", offsetof(struct i40e_hw_port_stats,
612 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
616 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
617 sizeof(rte_i40e_rxq_prio_strings[0]))
619 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
620 {"xon_packets", offsetof(struct i40e_hw_port_stats,
622 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
624 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
625 priority_xon_2_xoff)},
628 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
629 sizeof(rte_i40e_txq_prio_strings[0]))
632 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
633 struct rte_pci_device *pci_dev)
635 char name[RTE_ETH_NAME_MAX_LEN];
636 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
639 if (pci_dev->device.devargs) {
640 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
646 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
647 sizeof(struct i40e_adapter),
648 eth_dev_pci_specific_init, pci_dev,
649 eth_i40e_dev_init, NULL);
651 if (retval || eth_da.nb_representor_ports < 1)
654 /* probe VF representor ports */
655 struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
656 pci_dev->device.name);
658 if (pf_ethdev == NULL)
661 for (i = 0; i < eth_da.nb_representor_ports; i++) {
662 struct i40e_vf_representor representor = {
663 .vf_id = eth_da.representor_ports[i],
664 .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
665 pf_ethdev->data->dev_private)->switch_domain_id,
666 .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
667 pf_ethdev->data->dev_private)
670 /* representor port net_bdf_port */
671 snprintf(name, sizeof(name), "net_%s_representor_%d",
672 pci_dev->device.name, eth_da.representor_ports[i]);
674 retval = rte_eth_dev_create(&pci_dev->device, name,
675 sizeof(struct i40e_vf_representor), NULL, NULL,
676 i40e_vf_representor_init, &representor);
679 PMD_DRV_LOG(ERR, "failed to create i40e vf "
680 "representor %s.", name);
686 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
688 struct rte_eth_dev *ethdev;
690 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
694 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
695 return rte_eth_dev_pci_generic_remove(pci_dev,
696 i40e_vf_representor_uninit);
698 return rte_eth_dev_pci_generic_remove(pci_dev,
699 eth_i40e_dev_uninit);
702 static struct rte_pci_driver rte_i40e_pmd = {
703 .id_table = pci_id_i40e_map,
704 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
705 .probe = eth_i40e_pci_probe,
706 .remove = eth_i40e_pci_remove,
710 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
713 uint32_t ori_reg_val;
714 struct rte_eth_dev *dev;
716 ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
717 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
718 i40e_write_rx_ctl(hw, reg_addr, reg_val);
719 if (ori_reg_val != reg_val)
721 "i40e device %s changed global register [0x%08x]."
722 " original: 0x%08x, new: 0x%08x",
723 dev->device->name, reg_addr, ori_reg_val, reg_val);
726 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
727 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
728 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
730 #ifndef I40E_GLQF_ORT
731 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
733 #ifndef I40E_GLQF_PIT
734 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
736 #ifndef I40E_GLQF_L3_MAP
737 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
740 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
743 * Initialize registers for parsing packet type of QinQ
744 * This should be removed from code once proper
745 * configuration API is added to avoid configuration conflicts
746 * between ports of the same device.
748 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
749 I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
752 static inline void i40e_config_automask(struct i40e_pf *pf)
754 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
757 /* INTENA flag is not auto-cleared for interrupt */
758 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
759 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
760 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
762 /* If support multi-driver, PF will use INT0. */
763 if (!pf->support_multi_driver)
764 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
766 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
769 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
772 * Add a ethertype filter to drop all flow control frames transmitted
776 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
778 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
779 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
780 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
781 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
784 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
785 I40E_FLOW_CONTROL_ETHERTYPE, flags,
786 pf->main_vsi_seid, 0,
790 "Failed to add filter to drop flow control frames from VSIs.");
794 floating_veb_list_handler(__rte_unused const char *key,
795 const char *floating_veb_value,
799 unsigned int count = 0;
802 bool *vf_floating_veb = opaque;
804 while (isblank(*floating_veb_value))
805 floating_veb_value++;
807 /* Reset floating VEB configuration for VFs */
808 for (idx = 0; idx < I40E_MAX_VF; idx++)
809 vf_floating_veb[idx] = false;
813 while (isblank(*floating_veb_value))
814 floating_veb_value++;
815 if (*floating_veb_value == '\0')
818 idx = strtoul(floating_veb_value, &end, 10);
819 if (errno || end == NULL)
821 while (isblank(*end))
825 } else if ((*end == ';') || (*end == '\0')) {
827 if (min == I40E_MAX_VF)
829 if (max >= I40E_MAX_VF)
830 max = I40E_MAX_VF - 1;
831 for (idx = min; idx <= max; idx++) {
832 vf_floating_veb[idx] = true;
839 floating_veb_value = end + 1;
840 } while (*end != '\0');
849 config_vf_floating_veb(struct rte_devargs *devargs,
850 uint16_t floating_veb,
851 bool *vf_floating_veb)
853 struct rte_kvargs *kvlist;
855 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
859 /* All the VFs attach to the floating VEB by default
860 * when the floating VEB is enabled.
862 for (i = 0; i < I40E_MAX_VF; i++)
863 vf_floating_veb[i] = true;
868 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
872 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
873 rte_kvargs_free(kvlist);
876 /* When the floating_veb_list parameter exists, all the VFs
877 * will attach to the legacy VEB firstly, then configure VFs
878 * to the floating VEB according to the floating_veb_list.
880 if (rte_kvargs_process(kvlist, floating_veb_list,
881 floating_veb_list_handler,
882 vf_floating_veb) < 0) {
883 rte_kvargs_free(kvlist);
886 rte_kvargs_free(kvlist);
890 i40e_check_floating_handler(__rte_unused const char *key,
892 __rte_unused void *opaque)
894 if (strcmp(value, "1"))
901 is_floating_veb_supported(struct rte_devargs *devargs)
903 struct rte_kvargs *kvlist;
904 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
909 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
913 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
914 rte_kvargs_free(kvlist);
917 /* Floating VEB is enabled when there's key-value:
918 * enable_floating_veb=1
920 if (rte_kvargs_process(kvlist, floating_veb_key,
921 i40e_check_floating_handler, NULL) < 0) {
922 rte_kvargs_free(kvlist);
925 rte_kvargs_free(kvlist);
931 config_floating_veb(struct rte_eth_dev *dev)
933 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
934 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
935 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
937 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
939 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
941 is_floating_veb_supported(pci_dev->device.devargs);
942 config_vf_floating_veb(pci_dev->device.devargs,
944 pf->floating_veb_list);
946 pf->floating_veb = false;
950 #define I40E_L2_TAGS_S_TAG_SHIFT 1
951 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
954 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
956 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
957 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
958 char ethertype_hash_name[RTE_HASH_NAMESIZE];
961 struct rte_hash_parameters ethertype_hash_params = {
962 .name = ethertype_hash_name,
963 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
964 .key_len = sizeof(struct i40e_ethertype_filter_input),
965 .hash_func = rte_hash_crc,
966 .hash_func_init_val = 0,
967 .socket_id = rte_socket_id(),
970 /* Initialize ethertype filter rule list and hash */
971 TAILQ_INIT(ðertype_rule->ethertype_list);
972 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
973 "ethertype_%s", dev->device->name);
974 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
975 if (!ethertype_rule->hash_table) {
976 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
979 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
980 sizeof(struct i40e_ethertype_filter *) *
981 I40E_MAX_ETHERTYPE_FILTER_NUM,
983 if (!ethertype_rule->hash_map) {
985 "Failed to allocate memory for ethertype hash map!");
987 goto err_ethertype_hash_map_alloc;
992 err_ethertype_hash_map_alloc:
993 rte_hash_free(ethertype_rule->hash_table);
999 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
1001 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1002 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
1003 char tunnel_hash_name[RTE_HASH_NAMESIZE];
1006 struct rte_hash_parameters tunnel_hash_params = {
1007 .name = tunnel_hash_name,
1008 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1009 .key_len = sizeof(struct i40e_tunnel_filter_input),
1010 .hash_func = rte_hash_crc,
1011 .hash_func_init_val = 0,
1012 .socket_id = rte_socket_id(),
1015 /* Initialize tunnel filter rule list and hash */
1016 TAILQ_INIT(&tunnel_rule->tunnel_list);
1017 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1018 "tunnel_%s", dev->device->name);
1019 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1020 if (!tunnel_rule->hash_table) {
1021 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1024 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1025 sizeof(struct i40e_tunnel_filter *) *
1026 I40E_MAX_TUNNEL_FILTER_NUM,
1028 if (!tunnel_rule->hash_map) {
1030 "Failed to allocate memory for tunnel hash map!");
1032 goto err_tunnel_hash_map_alloc;
1037 err_tunnel_hash_map_alloc:
1038 rte_hash_free(tunnel_rule->hash_table);
1044 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1046 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1047 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1048 struct i40e_fdir_info *fdir_info = &pf->fdir;
1049 char fdir_hash_name[RTE_HASH_NAMESIZE];
1050 uint32_t alloc = hw->func_caps.fd_filters_guaranteed;
1051 uint32_t best = hw->func_caps.fd_filters_best_effort;
1052 struct rte_bitmap *bmp = NULL;
1058 struct rte_hash_parameters fdir_hash_params = {
1059 .name = fdir_hash_name,
1060 .entries = I40E_MAX_FDIR_FILTER_NUM,
1061 .key_len = sizeof(struct i40e_fdir_input),
1062 .hash_func = rte_hash_crc,
1063 .hash_func_init_val = 0,
1064 .socket_id = rte_socket_id(),
1067 /* Initialize flow director filter rule list and hash */
1068 TAILQ_INIT(&fdir_info->fdir_list);
1069 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1070 "fdir_%s", dev->device->name);
1071 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1072 if (!fdir_info->hash_table) {
1073 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1077 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1078 sizeof(struct i40e_fdir_filter *) *
1079 I40E_MAX_FDIR_FILTER_NUM,
1081 if (!fdir_info->hash_map) {
1083 "Failed to allocate memory for fdir hash map!");
1085 goto err_fdir_hash_map_alloc;
1088 fdir_info->fdir_filter_array = rte_zmalloc("fdir_filter",
1089 sizeof(struct i40e_fdir_filter) *
1090 I40E_MAX_FDIR_FILTER_NUM,
1093 if (!fdir_info->fdir_filter_array) {
1095 "Failed to allocate memory for fdir filter array!");
1097 goto err_fdir_filter_array_alloc;
1100 fdir_info->fdir_space_size = alloc + best;
1101 fdir_info->fdir_actual_cnt = 0;
1102 fdir_info->fdir_guarantee_total_space = alloc;
1103 fdir_info->fdir_guarantee_free_space =
1104 fdir_info->fdir_guarantee_total_space;
1106 PMD_DRV_LOG(INFO, "FDIR guarantee space: %u, best_effort space %u.", alloc, best);
1108 fdir_info->fdir_flow_pool.pool =
1109 rte_zmalloc("i40e_fdir_entry",
1110 sizeof(struct i40e_fdir_entry) *
1111 fdir_info->fdir_space_size,
1114 if (!fdir_info->fdir_flow_pool.pool) {
1116 "Failed to allocate memory for bitmap flow!");
1118 goto err_fdir_bitmap_flow_alloc;
1121 for (i = 0; i < fdir_info->fdir_space_size; i++)
1122 fdir_info->fdir_flow_pool.pool[i].idx = i;
1125 rte_bitmap_get_memory_footprint(fdir_info->fdir_space_size);
1126 mem = rte_zmalloc("fdir_bmap", bmp_size, RTE_CACHE_LINE_SIZE);
1129 "Failed to allocate memory for fdir bitmap!");
1131 goto err_fdir_mem_alloc;
1133 bmp = rte_bitmap_init(fdir_info->fdir_space_size, mem, bmp_size);
1136 "Failed to initialization fdir bitmap!");
1138 goto err_fdir_bmp_alloc;
1140 for (i = 0; i < fdir_info->fdir_space_size; i++)
1141 rte_bitmap_set(bmp, i);
1143 fdir_info->fdir_flow_pool.bitmap = bmp;
1150 rte_free(fdir_info->fdir_flow_pool.pool);
1151 err_fdir_bitmap_flow_alloc:
1152 rte_free(fdir_info->fdir_filter_array);
1153 err_fdir_filter_array_alloc:
1154 rte_free(fdir_info->hash_map);
1155 err_fdir_hash_map_alloc:
1156 rte_hash_free(fdir_info->hash_table);
1162 i40e_init_customized_info(struct i40e_pf *pf)
1166 /* Initialize customized pctype */
1167 for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1168 pf->customized_pctype[i].index = i;
1169 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1170 pf->customized_pctype[i].valid = false;
1173 pf->gtp_support = false;
1174 pf->esp_support = false;
1178 i40e_init_filter_invalidation(struct i40e_pf *pf)
1180 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1181 struct i40e_fdir_info *fdir_info = &pf->fdir;
1182 uint32_t glqf_ctl_reg = 0;
1184 glqf_ctl_reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
1185 if (!pf->support_multi_driver) {
1186 fdir_info->fdir_invalprio = 1;
1187 glqf_ctl_reg |= I40E_GLQF_CTL_INVALPRIO_MASK;
1188 PMD_DRV_LOG(INFO, "FDIR INVALPRIO set to guaranteed first");
1189 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, glqf_ctl_reg);
1191 if (glqf_ctl_reg & I40E_GLQF_CTL_INVALPRIO_MASK) {
1192 fdir_info->fdir_invalprio = 1;
1193 PMD_DRV_LOG(INFO, "FDIR INVALPRIO is: guaranteed first");
1195 fdir_info->fdir_invalprio = 0;
1196 PMD_DRV_LOG(INFO, "FDIR INVALPRIO is: shared first");
1202 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1204 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1205 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1206 struct i40e_queue_regions *info = &pf->queue_region;
1209 for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1210 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1212 memset(info, 0, sizeof(struct i40e_queue_regions));
1216 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1221 unsigned long support_multi_driver;
1224 pf = (struct i40e_pf *)opaque;
1227 support_multi_driver = strtoul(value, &end, 10);
1228 if (errno != 0 || end == value || *end != 0) {
1229 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1233 if (support_multi_driver == 1 || support_multi_driver == 0)
1234 pf->support_multi_driver = (bool)support_multi_driver;
1236 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1237 "enable global configuration by default."
1238 ETH_I40E_SUPPORT_MULTI_DRIVER);
1243 i40e_support_multi_driver(struct rte_eth_dev *dev)
1245 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1246 struct rte_kvargs *kvlist;
1249 /* Enable global configuration by default */
1250 pf->support_multi_driver = false;
1252 if (!dev->device->devargs)
1255 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1259 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1260 if (!kvargs_count) {
1261 rte_kvargs_free(kvlist);
1265 if (kvargs_count > 1)
1266 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1267 "the first invalid or last valid one is used !",
1268 ETH_I40E_SUPPORT_MULTI_DRIVER);
1270 if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1271 i40e_parse_multi_drv_handler, pf) < 0) {
1272 rte_kvargs_free(kvlist);
1276 rte_kvargs_free(kvlist);
1281 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1282 uint32_t reg_addr, uint64_t reg_val,
1283 struct i40e_asq_cmd_details *cmd_details)
1285 uint64_t ori_reg_val;
1286 struct rte_eth_dev *dev;
1289 ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1290 if (ret != I40E_SUCCESS) {
1292 "Fail to debug read from 0x%08x",
1296 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1298 if (ori_reg_val != reg_val)
1299 PMD_DRV_LOG(WARNING,
1300 "i40e device %s changed global register [0x%08x]."
1301 " original: 0x%"PRIx64", after: 0x%"PRIx64,
1302 dev->device->name, reg_addr, ori_reg_val, reg_val);
1304 return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1308 i40e_parse_latest_vec_handler(__rte_unused const char *key,
1312 struct i40e_adapter *ad = opaque;
1315 use_latest_vec = atoi(value);
1317 if (use_latest_vec != 0 && use_latest_vec != 1)
1318 PMD_DRV_LOG(WARNING, "Value should be 0 or 1, set it as 1!");
1320 ad->use_latest_vec = (uint8_t)use_latest_vec;
1326 i40e_use_latest_vec(struct rte_eth_dev *dev)
1328 struct i40e_adapter *ad =
1329 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1330 struct rte_kvargs *kvlist;
1333 ad->use_latest_vec = false;
1335 if (!dev->device->devargs)
1338 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1342 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_USE_LATEST_VEC);
1343 if (!kvargs_count) {
1344 rte_kvargs_free(kvlist);
1348 if (kvargs_count > 1)
1349 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1350 "the first invalid or last valid one is used !",
1351 ETH_I40E_USE_LATEST_VEC);
1353 if (rte_kvargs_process(kvlist, ETH_I40E_USE_LATEST_VEC,
1354 i40e_parse_latest_vec_handler, ad) < 0) {
1355 rte_kvargs_free(kvlist);
1359 rte_kvargs_free(kvlist);
1364 read_vf_msg_config(__rte_unused const char *key,
1368 struct i40e_vf_msg_cfg *cfg = opaque;
1370 if (sscanf(value, "%u@%u:%u", &cfg->max_msg, &cfg->period,
1371 &cfg->ignore_second) != 3) {
1372 memset(cfg, 0, sizeof(*cfg));
1373 PMD_DRV_LOG(ERR, "format error! example: "
1374 "%s=60@120:180", ETH_I40E_VF_MSG_CFG);
1379 * If the message validation function been enabled, the 'period'
1380 * and 'ignore_second' must greater than 0.
1382 if (cfg->max_msg && (!cfg->period || !cfg->ignore_second)) {
1383 memset(cfg, 0, sizeof(*cfg));
1384 PMD_DRV_LOG(ERR, "%s error! the second and third"
1385 " number must be greater than 0!",
1386 ETH_I40E_VF_MSG_CFG);
1394 i40e_parse_vf_msg_config(struct rte_eth_dev *dev,
1395 struct i40e_vf_msg_cfg *msg_cfg)
1397 struct rte_kvargs *kvlist;
1401 memset(msg_cfg, 0, sizeof(*msg_cfg));
1403 if (!dev->device->devargs)
1406 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1410 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_VF_MSG_CFG);
1414 if (kvargs_count > 1) {
1415 PMD_DRV_LOG(ERR, "More than one argument \"%s\"!",
1416 ETH_I40E_VF_MSG_CFG);
1421 if (rte_kvargs_process(kvlist, ETH_I40E_VF_MSG_CFG,
1422 read_vf_msg_config, msg_cfg) < 0)
1426 rte_kvargs_free(kvlist);
1430 #define I40E_ALARM_INTERVAL 50000 /* us */
1433 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1435 struct rte_pci_device *pci_dev;
1436 struct rte_intr_handle *intr_handle;
1437 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1438 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1439 struct i40e_vsi *vsi;
1442 uint8_t aq_fail = 0;
1444 PMD_INIT_FUNC_TRACE();
1446 dev->dev_ops = &i40e_eth_dev_ops;
1447 dev->rx_queue_count = i40e_dev_rx_queue_count;
1448 dev->rx_descriptor_done = i40e_dev_rx_descriptor_done;
1449 dev->rx_descriptor_status = i40e_dev_rx_descriptor_status;
1450 dev->tx_descriptor_status = i40e_dev_tx_descriptor_status;
1451 dev->rx_pkt_burst = i40e_recv_pkts;
1452 dev->tx_pkt_burst = i40e_xmit_pkts;
1453 dev->tx_pkt_prepare = i40e_prep_pkts;
1455 /* for secondary processes, we don't initialise any further as primary
1456 * has already done this work. Only check we don't need a different
1458 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1459 i40e_set_rx_function(dev);
1460 i40e_set_tx_function(dev);
1463 i40e_set_default_ptype_table(dev);
1464 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1465 intr_handle = &pci_dev->intr_handle;
1467 rte_eth_copy_pci_info(dev, pci_dev);
1468 dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1470 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1471 pf->adapter->eth_dev = dev;
1472 pf->dev_data = dev->data;
1474 hw->back = I40E_PF_TO_ADAPTER(pf);
1475 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1478 "Hardware is not available, as address is NULL");
1482 hw->vendor_id = pci_dev->id.vendor_id;
1483 hw->device_id = pci_dev->id.device_id;
1484 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1485 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1486 hw->bus.device = pci_dev->addr.devid;
1487 hw->bus.func = pci_dev->addr.function;
1488 hw->adapter_stopped = 0;
1489 hw->adapter_closed = 0;
1491 /* Init switch device pointer */
1492 hw->switch_dev = NULL;
1495 * Switch Tag value should not be identical to either the First Tag
1496 * or Second Tag values. So set something other than common Ethertype
1497 * for internal switching.
1499 hw->switch_tag = 0xffff;
1501 val = I40E_READ_REG(hw, I40E_GL_FWSTS);
1502 if (val & I40E_GL_FWSTS_FWS1B_MASK) {
1503 PMD_INIT_LOG(ERR, "\nERROR: "
1504 "Firmware recovery mode detected. Limiting functionality.\n"
1505 "Refer to the Intel(R) Ethernet Adapters and Devices "
1506 "User Guide for details on firmware recovery mode.");
1510 i40e_parse_vf_msg_config(dev, &pf->vf_msg_cfg);
1511 /* Check if need to support multi-driver */
1512 i40e_support_multi_driver(dev);
1513 /* Check if users want the latest supported vec path */
1514 i40e_use_latest_vec(dev);
1516 /* Make sure all is clean before doing PF reset */
1519 /* Reset here to make sure all is clean for each PF */
1520 ret = i40e_pf_reset(hw);
1522 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1526 /* Initialize the shared code (base driver) */
1527 ret = i40e_init_shared_code(hw);
1529 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1533 /* Initialize the parameters for adminq */
1534 i40e_init_adminq_parameter(hw);
1535 ret = i40e_init_adminq(hw);
1536 if (ret != I40E_SUCCESS) {
1537 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1540 /* Firmware of SFP x722 does not support adminq option */
1541 if (hw->device_id == I40E_DEV_ID_SFP_X722)
1542 hw->flags &= ~I40E_HW_FLAG_802_1AD_CAPABLE;
1544 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1545 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1546 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1547 ((hw->nvm.version >> 12) & 0xf),
1548 ((hw->nvm.version >> 4) & 0xff),
1549 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1551 /* Initialize the hardware */
1554 i40e_config_automask(pf);
1556 i40e_set_default_pctype_table(dev);
1559 * To work around the NVM issue, initialize registers
1560 * for packet type of QinQ by software.
1561 * It should be removed once issues are fixed in NVM.
1563 if (!pf->support_multi_driver)
1564 i40e_GLQF_reg_init(hw);
1566 /* Initialize the input set for filters (hash and fd) to default value */
1567 i40e_filter_input_set_init(pf);
1569 /* initialise the L3_MAP register */
1570 if (!pf->support_multi_driver) {
1571 ret = i40e_aq_debug_write_global_register(hw,
1572 I40E_GLQF_L3_MAP(40),
1575 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1578 "Global register 0x%08x is changed with 0x28",
1579 I40E_GLQF_L3_MAP(40));
1582 /* Need the special FW version to support floating VEB */
1583 config_floating_veb(dev);
1584 /* Clear PXE mode */
1585 i40e_clear_pxe_mode(hw);
1586 i40e_dev_sync_phy_type(hw);
1589 * On X710, performance number is far from the expectation on recent
1590 * firmware versions. The fix for this issue may not be integrated in
1591 * the following firmware version. So the workaround in software driver
1592 * is needed. It needs to modify the initial values of 3 internal only
1593 * registers. Note that the workaround can be removed when it is fixed
1594 * in firmware in the future.
1596 i40e_configure_registers(hw);
1598 /* Get hw capabilities */
1599 ret = i40e_get_cap(hw);
1600 if (ret != I40E_SUCCESS) {
1601 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1602 goto err_get_capabilities;
1605 /* Initialize parameters for PF */
1606 ret = i40e_pf_parameter_init(dev);
1608 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1609 goto err_parameter_init;
1612 /* Initialize the queue management */
1613 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1615 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1616 goto err_qp_pool_init;
1618 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1619 hw->func_caps.num_msix_vectors - 1);
1621 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1622 goto err_msix_pool_init;
1625 /* Initialize lan hmc */
1626 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1627 hw->func_caps.num_rx_qp, 0, 0);
1628 if (ret != I40E_SUCCESS) {
1629 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1630 goto err_init_lan_hmc;
1633 /* Configure lan hmc */
1634 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1635 if (ret != I40E_SUCCESS) {
1636 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1637 goto err_configure_lan_hmc;
1640 /* Get and check the mac address */
1641 i40e_get_mac_addr(hw, hw->mac.addr);
1642 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1643 PMD_INIT_LOG(ERR, "mac address is not valid");
1645 goto err_get_mac_addr;
1647 /* Copy the permanent MAC address */
1648 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1649 (struct rte_ether_addr *)hw->mac.perm_addr);
1651 /* Disable flow control */
1652 hw->fc.requested_mode = I40E_FC_NONE;
1653 i40e_set_fc(hw, &aq_fail, TRUE);
1655 /* Set the global registers with default ether type value */
1656 if (!pf->support_multi_driver) {
1657 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1658 RTE_ETHER_TYPE_VLAN);
1659 if (ret != I40E_SUCCESS) {
1661 "Failed to set the default outer "
1663 goto err_setup_pf_switch;
1667 /* PF setup, which includes VSI setup */
1668 ret = i40e_pf_setup(pf);
1670 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1671 goto err_setup_pf_switch;
1676 /* Disable double vlan by default */
1677 i40e_vsi_config_double_vlan(vsi, FALSE);
1679 /* Disable S-TAG identification when floating_veb is disabled */
1680 if (!pf->floating_veb) {
1681 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1682 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1683 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1684 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1688 if (!vsi->max_macaddrs)
1689 len = RTE_ETHER_ADDR_LEN;
1691 len = RTE_ETHER_ADDR_LEN * vsi->max_macaddrs;
1693 /* Should be after VSI initialized */
1694 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1695 if (!dev->data->mac_addrs) {
1697 "Failed to allocated memory for storing mac address");
1700 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1701 &dev->data->mac_addrs[0]);
1703 /* Init dcb to sw mode by default */
1704 ret = i40e_dcb_init_configure(dev, TRUE);
1705 if (ret != I40E_SUCCESS) {
1706 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1707 pf->flags &= ~I40E_FLAG_DCB;
1709 /* Update HW struct after DCB configuration */
1712 /* initialize pf host driver to setup SRIOV resource if applicable */
1713 i40e_pf_host_init(dev);
1715 /* register callback func to eal lib */
1716 rte_intr_callback_register(intr_handle,
1717 i40e_dev_interrupt_handler, dev);
1719 /* configure and enable device interrupt */
1720 i40e_pf_config_irq0(hw, TRUE);
1721 i40e_pf_enable_irq0(hw);
1723 /* enable uio intr after callback register */
1724 rte_intr_enable(intr_handle);
1726 /* By default disable flexible payload in global configuration */
1727 if (!pf->support_multi_driver)
1728 i40e_flex_payload_reg_set_default(hw);
1731 * Add an ethertype filter to drop all flow control frames transmitted
1732 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1735 i40e_add_tx_flow_control_drop_filter(pf);
1737 /* Set the max frame size to 0x2600 by default,
1738 * in case other drivers changed the default value.
1740 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, false, 0, NULL);
1742 /* initialize mirror rule list */
1743 TAILQ_INIT(&pf->mirror_list);
1745 /* initialize RSS rule list */
1746 TAILQ_INIT(&pf->rss_config_list);
1748 /* initialize Traffic Manager configuration */
1749 i40e_tm_conf_init(dev);
1751 /* Initialize customized information */
1752 i40e_init_customized_info(pf);
1754 /* Initialize the filter invalidation configuration */
1755 i40e_init_filter_invalidation(pf);
1757 ret = i40e_init_ethtype_filter_list(dev);
1759 goto err_init_ethtype_filter_list;
1760 ret = i40e_init_tunnel_filter_list(dev);
1762 goto err_init_tunnel_filter_list;
1763 ret = i40e_init_fdir_filter_list(dev);
1765 goto err_init_fdir_filter_list;
1767 /* initialize queue region configuration */
1768 i40e_init_queue_region_conf(dev);
1770 /* initialize RSS configuration from rte_flow */
1771 memset(&pf->rss_info, 0,
1772 sizeof(struct i40e_rte_flow_rss_conf));
1774 /* reset all stats of the device, including pf and main vsi */
1775 i40e_dev_stats_reset(dev);
1779 err_init_fdir_filter_list:
1780 rte_free(pf->tunnel.hash_table);
1781 rte_free(pf->tunnel.hash_map);
1782 err_init_tunnel_filter_list:
1783 rte_free(pf->ethertype.hash_table);
1784 rte_free(pf->ethertype.hash_map);
1785 err_init_ethtype_filter_list:
1786 rte_free(dev->data->mac_addrs);
1787 dev->data->mac_addrs = NULL;
1789 i40e_vsi_release(pf->main_vsi);
1790 err_setup_pf_switch:
1792 err_configure_lan_hmc:
1793 (void)i40e_shutdown_lan_hmc(hw);
1795 i40e_res_pool_destroy(&pf->msix_pool);
1797 i40e_res_pool_destroy(&pf->qp_pool);
1800 err_get_capabilities:
1801 (void)i40e_shutdown_adminq(hw);
1807 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1809 struct i40e_ethertype_filter *p_ethertype;
1810 struct i40e_ethertype_rule *ethertype_rule;
1812 ethertype_rule = &pf->ethertype;
1813 /* Remove all ethertype filter rules and hash */
1814 if (ethertype_rule->hash_map)
1815 rte_free(ethertype_rule->hash_map);
1816 if (ethertype_rule->hash_table)
1817 rte_hash_free(ethertype_rule->hash_table);
1819 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1820 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1821 p_ethertype, rules);
1822 rte_free(p_ethertype);
1827 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1829 struct i40e_tunnel_filter *p_tunnel;
1830 struct i40e_tunnel_rule *tunnel_rule;
1832 tunnel_rule = &pf->tunnel;
1833 /* Remove all tunnel director rules and hash */
1834 if (tunnel_rule->hash_map)
1835 rte_free(tunnel_rule->hash_map);
1836 if (tunnel_rule->hash_table)
1837 rte_hash_free(tunnel_rule->hash_table);
1839 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1840 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1846 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1848 struct i40e_fdir_filter *p_fdir;
1849 struct i40e_fdir_info *fdir_info;
1851 fdir_info = &pf->fdir;
1853 /* Remove all flow director rules */
1854 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list)))
1855 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1859 i40e_fdir_memory_cleanup(struct i40e_pf *pf)
1861 struct i40e_fdir_info *fdir_info;
1863 fdir_info = &pf->fdir;
1865 /* flow director memory cleanup */
1866 if (fdir_info->hash_map)
1867 rte_free(fdir_info->hash_map);
1868 if (fdir_info->hash_table)
1869 rte_hash_free(fdir_info->hash_table);
1870 if (fdir_info->fdir_flow_pool.bitmap)
1871 rte_free(fdir_info->fdir_flow_pool.bitmap);
1872 if (fdir_info->fdir_flow_pool.pool)
1873 rte_free(fdir_info->fdir_flow_pool.pool);
1874 if (fdir_info->fdir_filter_array)
1875 rte_free(fdir_info->fdir_filter_array);
1878 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1881 * Disable by default flexible payload
1882 * for corresponding L2/L3/L4 layers.
1884 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1885 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1886 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1890 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1894 PMD_INIT_FUNC_TRACE();
1896 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1899 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1901 if (hw->adapter_closed == 0)
1902 i40e_dev_close(dev);
1908 i40e_dev_configure(struct rte_eth_dev *dev)
1910 struct i40e_adapter *ad =
1911 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1912 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1913 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1914 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1917 ret = i40e_dev_sync_phy_type(hw);
1921 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1922 * bulk allocation or vector Rx preconditions we will reset it.
1924 ad->rx_bulk_alloc_allowed = true;
1925 ad->rx_vec_allowed = true;
1926 ad->tx_simple_allowed = true;
1927 ad->tx_vec_allowed = true;
1929 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1930 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1932 /* Only legacy filter API needs the following fdir config. So when the
1933 * legacy filter API is deprecated, the following codes should also be
1936 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1937 ret = i40e_fdir_setup(pf);
1938 if (ret != I40E_SUCCESS) {
1939 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1942 ret = i40e_fdir_configure(dev);
1944 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1948 i40e_fdir_teardown(pf);
1950 ret = i40e_dev_init_vlan(dev);
1955 * General PMD driver call sequence are NIC init, configure,
1956 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1957 * will try to lookup the VSI that specific queue belongs to if VMDQ
1958 * applicable. So, VMDQ setting has to be done before
1959 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1960 * For RSS setting, it will try to calculate actual configured RX queue
1961 * number, which will be available after rx_queue_setup(). dev_start()
1962 * function is good to place RSS setup.
1964 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1965 ret = i40e_vmdq_setup(dev);
1970 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1971 ret = i40e_dcb_setup(dev);
1973 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1978 TAILQ_INIT(&pf->flow_list);
1983 /* need to release vmdq resource if exists */
1984 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1985 i40e_vsi_release(pf->vmdq[i].vsi);
1986 pf->vmdq[i].vsi = NULL;
1991 /* Need to release fdir resource if exists.
1992 * Only legacy filter API needs the following fdir config. So when the
1993 * legacy filter API is deprecated, the following code should also be
1996 i40e_fdir_teardown(pf);
2001 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
2003 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2004 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2005 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2006 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2007 uint16_t msix_vect = vsi->msix_intr;
2010 for (i = 0; i < vsi->nb_qps; i++) {
2011 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
2012 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2016 if (vsi->type != I40E_VSI_SRIOV) {
2017 if (!rte_intr_allow_others(intr_handle)) {
2018 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
2019 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
2021 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
2024 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
2025 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
2027 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
2032 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
2033 vsi->user_param + (msix_vect - 1);
2035 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
2036 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
2038 I40E_WRITE_FLUSH(hw);
2042 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
2043 int base_queue, int nb_queue,
2048 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2049 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2051 /* Bind all RX queues to allocated MSIX interrupt */
2052 for (i = 0; i < nb_queue; i++) {
2053 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2054 itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
2055 ((base_queue + i + 1) <<
2056 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
2057 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
2058 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
2060 if (i == nb_queue - 1)
2061 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
2062 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
2065 /* Write first RX queue to Link list register as the head element */
2066 if (vsi->type != I40E_VSI_SRIOV) {
2068 i40e_calc_itr_interval(1, pf->support_multi_driver);
2070 if (msix_vect == I40E_MISC_VEC_ID) {
2071 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
2073 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
2075 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
2077 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
2080 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
2082 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
2084 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2086 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
2093 if (msix_vect == I40E_MISC_VEC_ID) {
2095 I40E_VPINT_LNKLST0(vsi->user_param),
2097 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
2099 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
2101 /* num_msix_vectors_vf needs to minus irq0 */
2102 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
2103 vsi->user_param + (msix_vect - 1);
2105 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
2107 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
2109 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2113 I40E_WRITE_FLUSH(hw);
2117 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
2119 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2120 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2121 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2122 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2123 uint16_t msix_vect = vsi->msix_intr;
2124 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2125 uint16_t queue_idx = 0;
2129 for (i = 0; i < vsi->nb_qps; i++) {
2130 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
2131 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2134 /* VF bind interrupt */
2135 if (vsi->type == I40E_VSI_SRIOV) {
2136 if (vsi->nb_msix == 0) {
2137 PMD_DRV_LOG(ERR, "No msix resource");
2140 __vsi_queues_bind_intr(vsi, msix_vect,
2141 vsi->base_queue, vsi->nb_qps,
2146 /* PF & VMDq bind interrupt */
2147 if (rte_intr_dp_is_en(intr_handle)) {
2148 if (vsi->type == I40E_VSI_MAIN) {
2151 } else if (vsi->type == I40E_VSI_VMDQ2) {
2152 struct i40e_vsi *main_vsi =
2153 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2154 queue_idx = vsi->base_queue - main_vsi->nb_qps;
2159 for (i = 0; i < vsi->nb_used_qps; i++) {
2160 if (vsi->nb_msix == 0) {
2161 PMD_DRV_LOG(ERR, "No msix resource");
2163 } else if (nb_msix <= 1) {
2164 if (!rte_intr_allow_others(intr_handle))
2165 /* allow to share MISC_VEC_ID */
2166 msix_vect = I40E_MISC_VEC_ID;
2168 /* no enough msix_vect, map all to one */
2169 __vsi_queues_bind_intr(vsi, msix_vect,
2170 vsi->base_queue + i,
2171 vsi->nb_used_qps - i,
2173 for (; !!record && i < vsi->nb_used_qps; i++)
2174 intr_handle->intr_vec[queue_idx + i] =
2178 /* 1:1 queue/msix_vect mapping */
2179 __vsi_queues_bind_intr(vsi, msix_vect,
2180 vsi->base_queue + i, 1,
2183 intr_handle->intr_vec[queue_idx + i] = msix_vect;
2193 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2195 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2196 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2197 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2198 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2199 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2200 uint16_t msix_intr, i;
2202 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2203 for (i = 0; i < vsi->nb_msix; i++) {
2204 msix_intr = vsi->msix_intr + i;
2205 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2206 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2207 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2208 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2211 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2212 I40E_PFINT_DYN_CTL0_INTENA_MASK |
2213 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2214 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2216 I40E_WRITE_FLUSH(hw);
2220 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2222 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2223 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2224 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2225 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2226 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2227 uint16_t msix_intr, i;
2229 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2230 for (i = 0; i < vsi->nb_msix; i++) {
2231 msix_intr = vsi->msix_intr + i;
2232 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2233 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2236 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2237 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2239 I40E_WRITE_FLUSH(hw);
2242 static inline uint8_t
2243 i40e_parse_link_speeds(uint16_t link_speeds)
2245 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2247 if (link_speeds & ETH_LINK_SPEED_40G)
2248 link_speed |= I40E_LINK_SPEED_40GB;
2249 if (link_speeds & ETH_LINK_SPEED_25G)
2250 link_speed |= I40E_LINK_SPEED_25GB;
2251 if (link_speeds & ETH_LINK_SPEED_20G)
2252 link_speed |= I40E_LINK_SPEED_20GB;
2253 if (link_speeds & ETH_LINK_SPEED_10G)
2254 link_speed |= I40E_LINK_SPEED_10GB;
2255 if (link_speeds & ETH_LINK_SPEED_1G)
2256 link_speed |= I40E_LINK_SPEED_1GB;
2257 if (link_speeds & ETH_LINK_SPEED_100M)
2258 link_speed |= I40E_LINK_SPEED_100MB;
2264 i40e_phy_conf_link(struct i40e_hw *hw,
2266 uint8_t force_speed,
2269 enum i40e_status_code status;
2270 struct i40e_aq_get_phy_abilities_resp phy_ab;
2271 struct i40e_aq_set_phy_config phy_conf;
2272 enum i40e_aq_phy_type cnt;
2273 uint8_t avail_speed;
2274 uint32_t phy_type_mask = 0;
2276 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2277 I40E_AQ_PHY_FLAG_PAUSE_RX |
2278 I40E_AQ_PHY_FLAG_PAUSE_RX |
2279 I40E_AQ_PHY_FLAG_LOW_POWER;
2282 /* To get phy capabilities of available speeds. */
2283 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2286 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2290 avail_speed = phy_ab.link_speed;
2292 /* To get the current phy config. */
2293 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2296 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2301 /* If link needs to go up and it is in autoneg mode the speed is OK,
2302 * no need to set up again.
2304 if (is_up && phy_ab.phy_type != 0 &&
2305 abilities & I40E_AQ_PHY_AN_ENABLED &&
2306 phy_ab.link_speed != 0)
2307 return I40E_SUCCESS;
2309 memset(&phy_conf, 0, sizeof(phy_conf));
2311 /* bits 0-2 use the values from get_phy_abilities_resp */
2313 abilities |= phy_ab.abilities & mask;
2315 phy_conf.abilities = abilities;
2317 /* If link needs to go up, but the force speed is not supported,
2318 * Warn users and config the default available speeds.
2320 if (is_up && !(force_speed & avail_speed)) {
2321 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2322 phy_conf.link_speed = avail_speed;
2324 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2327 /* PHY type mask needs to include each type except PHY type extension */
2328 for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2329 phy_type_mask |= 1 << cnt;
2331 /* use get_phy_abilities_resp value for the rest */
2332 phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2333 phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2334 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2335 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2336 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2337 phy_conf.eee_capability = phy_ab.eee_capability;
2338 phy_conf.eeer = phy_ab.eeer_val;
2339 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2341 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2342 phy_ab.abilities, phy_ab.link_speed);
2343 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
2344 phy_conf.abilities, phy_conf.link_speed);
2346 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2350 return I40E_SUCCESS;
2354 i40e_apply_link_speed(struct rte_eth_dev *dev)
2357 uint8_t abilities = 0;
2358 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2359 struct rte_eth_conf *conf = &dev->data->dev_conf;
2361 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2362 I40E_AQ_PHY_LINK_ENABLED;
2364 if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2365 conf->link_speeds = ETH_LINK_SPEED_40G |
2366 ETH_LINK_SPEED_25G |
2367 ETH_LINK_SPEED_20G |
2368 ETH_LINK_SPEED_10G |
2370 ETH_LINK_SPEED_100M;
2372 abilities |= I40E_AQ_PHY_AN_ENABLED;
2374 abilities &= ~I40E_AQ_PHY_AN_ENABLED;
2376 speed = i40e_parse_link_speeds(conf->link_speeds);
2378 return i40e_phy_conf_link(hw, abilities, speed, true);
2382 i40e_dev_start(struct rte_eth_dev *dev)
2384 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2385 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2386 struct i40e_vsi *main_vsi = pf->main_vsi;
2388 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2389 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2390 uint32_t intr_vector = 0;
2391 struct i40e_vsi *vsi;
2392 uint16_t nb_rxq, nb_txq;
2394 hw->adapter_stopped = 0;
2396 rte_intr_disable(intr_handle);
2398 if ((rte_intr_cap_multiple(intr_handle) ||
2399 !RTE_ETH_DEV_SRIOV(dev).active) &&
2400 dev->data->dev_conf.intr_conf.rxq != 0) {
2401 intr_vector = dev->data->nb_rx_queues;
2402 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2407 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2408 intr_handle->intr_vec =
2409 rte_zmalloc("intr_vec",
2410 dev->data->nb_rx_queues * sizeof(int),
2412 if (!intr_handle->intr_vec) {
2414 "Failed to allocate %d rx_queues intr_vec",
2415 dev->data->nb_rx_queues);
2420 /* Initialize VSI */
2421 ret = i40e_dev_rxtx_init(pf);
2422 if (ret != I40E_SUCCESS) {
2423 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2427 /* Map queues with MSIX interrupt */
2428 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2429 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2430 ret = i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2433 i40e_vsi_enable_queues_intr(main_vsi);
2435 /* Map VMDQ VSI queues with MSIX interrupt */
2436 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2437 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2438 ret = i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2439 I40E_ITR_INDEX_DEFAULT);
2442 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2445 /* Enable all queues which have been configured */
2446 for (nb_rxq = 0; nb_rxq < dev->data->nb_rx_queues; nb_rxq++) {
2447 ret = i40e_dev_rx_queue_start(dev, nb_rxq);
2452 for (nb_txq = 0; nb_txq < dev->data->nb_tx_queues; nb_txq++) {
2453 ret = i40e_dev_tx_queue_start(dev, nb_txq);
2458 /* Enable receiving broadcast packets */
2459 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2460 if (ret != I40E_SUCCESS)
2461 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2463 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2464 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2466 if (ret != I40E_SUCCESS)
2467 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2470 /* Enable the VLAN promiscuous mode. */
2472 for (i = 0; i < pf->vf_num; i++) {
2473 vsi = pf->vfs[i].vsi;
2474 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2479 /* Enable mac loopback mode */
2480 if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2481 dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2482 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2483 if (ret != I40E_SUCCESS) {
2484 PMD_DRV_LOG(ERR, "fail to set loopback link");
2489 /* Apply link configure */
2490 ret = i40e_apply_link_speed(dev);
2491 if (I40E_SUCCESS != ret) {
2492 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2496 if (!rte_intr_allow_others(intr_handle)) {
2497 rte_intr_callback_unregister(intr_handle,
2498 i40e_dev_interrupt_handler,
2500 /* configure and enable device interrupt */
2501 i40e_pf_config_irq0(hw, FALSE);
2502 i40e_pf_enable_irq0(hw);
2504 if (dev->data->dev_conf.intr_conf.lsc != 0)
2506 "lsc won't enable because of no intr multiplex");
2508 ret = i40e_aq_set_phy_int_mask(hw,
2509 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2510 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2511 I40E_AQ_EVENT_MEDIA_NA), NULL);
2512 if (ret != I40E_SUCCESS)
2513 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2515 /* Call get_link_info aq commond to enable/disable LSE */
2516 i40e_dev_link_update(dev, 0);
2519 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2520 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2521 i40e_dev_alarm_handler, dev);
2523 /* enable uio intr after callback register */
2524 rte_intr_enable(intr_handle);
2527 i40e_filter_restore(pf);
2529 if (pf->tm_conf.root && !pf->tm_conf.committed)
2530 PMD_DRV_LOG(WARNING,
2531 "please call hierarchy_commit() "
2532 "before starting the port");
2534 return I40E_SUCCESS;
2537 for (i = 0; i < nb_txq; i++)
2538 i40e_dev_tx_queue_stop(dev, i);
2540 for (i = 0; i < nb_rxq; i++)
2541 i40e_dev_rx_queue_stop(dev, i);
2547 i40e_dev_stop(struct rte_eth_dev *dev)
2549 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2550 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2551 struct i40e_vsi *main_vsi = pf->main_vsi;
2552 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2553 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2556 if (hw->adapter_stopped == 1)
2559 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2560 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2561 rte_intr_enable(intr_handle);
2564 /* Disable all queues */
2565 for (i = 0; i < dev->data->nb_tx_queues; i++)
2566 i40e_dev_tx_queue_stop(dev, i);
2568 for (i = 0; i < dev->data->nb_rx_queues; i++)
2569 i40e_dev_rx_queue_stop(dev, i);
2571 /* un-map queues with interrupt registers */
2572 i40e_vsi_disable_queues_intr(main_vsi);
2573 i40e_vsi_queues_unbind_intr(main_vsi);
2575 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2576 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2577 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2580 /* Clear all queues and release memory */
2581 i40e_dev_clear_queues(dev);
2584 i40e_dev_set_link_down(dev);
2586 if (!rte_intr_allow_others(intr_handle))
2587 /* resume to the default handler */
2588 rte_intr_callback_register(intr_handle,
2589 i40e_dev_interrupt_handler,
2592 /* Clean datapath event and queue/vec mapping */
2593 rte_intr_efd_disable(intr_handle);
2594 if (intr_handle->intr_vec) {
2595 rte_free(intr_handle->intr_vec);
2596 intr_handle->intr_vec = NULL;
2599 /* reset hierarchy commit */
2600 pf->tm_conf.committed = false;
2602 hw->adapter_stopped = 1;
2603 dev->data->dev_started = 0;
2605 pf->adapter->rss_reta_updated = 0;
2611 i40e_dev_close(struct rte_eth_dev *dev)
2613 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2614 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2615 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2616 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2617 struct i40e_mirror_rule *p_mirror;
2618 struct i40e_filter_control_settings settings;
2619 struct rte_flow *p_flow;
2623 uint8_t aq_fail = 0;
2626 PMD_INIT_FUNC_TRACE();
2627 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2630 ret = rte_eth_switch_domain_free(pf->switch_domain_id);
2632 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
2635 ret = i40e_dev_stop(dev);
2637 /* Remove all mirror rules */
2638 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2639 ret = i40e_aq_del_mirror_rule(hw,
2640 pf->main_vsi->veb->seid,
2641 p_mirror->rule_type,
2643 p_mirror->num_entries,
2646 PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2647 "status = %d, aq_err = %d.", ret,
2648 hw->aq.asq_last_status);
2650 /* remove mirror software resource anyway */
2651 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2653 pf->nb_mirror_rule--;
2656 i40e_dev_free_queues(dev);
2658 /* Disable interrupt */
2659 i40e_pf_disable_irq0(hw);
2660 rte_intr_disable(intr_handle);
2663 * Only legacy filter API needs the following fdir config. So when the
2664 * legacy filter API is deprecated, the following code should also be
2667 i40e_fdir_teardown(pf);
2669 /* shutdown and destroy the HMC */
2670 i40e_shutdown_lan_hmc(hw);
2672 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2673 i40e_vsi_release(pf->vmdq[i].vsi);
2674 pf->vmdq[i].vsi = NULL;
2679 /* release all the existing VSIs and VEBs */
2680 i40e_vsi_release(pf->main_vsi);
2682 /* shutdown the adminq */
2683 i40e_aq_queue_shutdown(hw, true);
2684 i40e_shutdown_adminq(hw);
2686 i40e_res_pool_destroy(&pf->qp_pool);
2687 i40e_res_pool_destroy(&pf->msix_pool);
2689 /* Disable flexible payload in global configuration */
2690 if (!pf->support_multi_driver)
2691 i40e_flex_payload_reg_set_default(hw);
2693 /* force a PF reset to clean anything leftover */
2694 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2695 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2696 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2697 I40E_WRITE_FLUSH(hw);
2699 /* Clear PXE mode */
2700 i40e_clear_pxe_mode(hw);
2702 /* Unconfigure filter control */
2703 memset(&settings, 0, sizeof(settings));
2704 ret = i40e_set_filter_control(hw, &settings);
2706 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
2709 /* Disable flow control */
2710 hw->fc.requested_mode = I40E_FC_NONE;
2711 i40e_set_fc(hw, &aq_fail, TRUE);
2713 /* uninitialize pf host driver */
2714 i40e_pf_host_uninit(dev);
2717 ret = rte_intr_callback_unregister(intr_handle,
2718 i40e_dev_interrupt_handler, dev);
2719 if (ret >= 0 || ret == -ENOENT) {
2721 } else if (ret != -EAGAIN) {
2723 "intr callback unregister failed: %d",
2726 i40e_msec_delay(500);
2727 } while (retries++ < 5);
2729 i40e_rm_ethtype_filter_list(pf);
2730 i40e_rm_tunnel_filter_list(pf);
2731 i40e_rm_fdir_filter_list(pf);
2733 /* Remove all flows */
2734 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
2735 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
2736 /* Do not free FDIR flows since they are static allocated */
2737 if (p_flow->filter_type != RTE_ETH_FILTER_FDIR)
2741 /* release the fdir static allocated memory */
2742 i40e_fdir_memory_cleanup(pf);
2744 /* Remove all Traffic Manager configuration */
2745 i40e_tm_conf_uninit(dev);
2747 hw->adapter_closed = 1;
2752 * Reset PF device only to re-initialize resources in PMD layer
2755 i40e_dev_reset(struct rte_eth_dev *dev)
2759 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2760 * its VF to make them align with it. The detailed notification
2761 * mechanism is PMD specific. As to i40e PF, it is rather complex.
2762 * To avoid unexpected behavior in VF, currently reset of PF with
2763 * SR-IOV activation is not supported. It might be supported later.
2765 if (dev->data->sriov.active)
2768 ret = eth_i40e_dev_uninit(dev);
2772 ret = eth_i40e_dev_init(dev, NULL);
2778 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2780 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2781 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2782 struct i40e_vsi *vsi = pf->main_vsi;
2785 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2787 if (status != I40E_SUCCESS) {
2788 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2792 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2794 if (status != I40E_SUCCESS) {
2795 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2796 /* Rollback unicast promiscuous mode */
2797 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2806 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2808 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2809 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2810 struct i40e_vsi *vsi = pf->main_vsi;
2813 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2815 if (status != I40E_SUCCESS) {
2816 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2820 /* must remain in all_multicast mode */
2821 if (dev->data->all_multicast == 1)
2824 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2826 if (status != I40E_SUCCESS) {
2827 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2828 /* Rollback unicast promiscuous mode */
2829 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2838 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2840 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2841 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2842 struct i40e_vsi *vsi = pf->main_vsi;
2845 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2846 if (ret != I40E_SUCCESS) {
2847 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2855 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2857 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2858 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2859 struct i40e_vsi *vsi = pf->main_vsi;
2862 if (dev->data->promiscuous == 1)
2863 return 0; /* must remain in all_multicast mode */
2865 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2866 vsi->seid, FALSE, NULL);
2867 if (ret != I40E_SUCCESS) {
2868 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2876 * Set device link up.
2879 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2881 /* re-apply link speed setting */
2882 return i40e_apply_link_speed(dev);
2886 * Set device link down.
2889 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2891 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2892 uint8_t abilities = 0;
2893 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2895 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2896 return i40e_phy_conf_link(hw, abilities, speed, false);
2899 static __rte_always_inline void
2900 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2902 /* Link status registers and values*/
2903 #define I40E_PRTMAC_LINKSTA 0x001E2420
2904 #define I40E_REG_LINK_UP 0x40000080
2905 #define I40E_PRTMAC_MACC 0x001E24E0
2906 #define I40E_REG_MACC_25GB 0x00020000
2907 #define I40E_REG_SPEED_MASK 0x38000000
2908 #define I40E_REG_SPEED_0 0x00000000
2909 #define I40E_REG_SPEED_1 0x08000000
2910 #define I40E_REG_SPEED_2 0x10000000
2911 #define I40E_REG_SPEED_3 0x18000000
2912 #define I40E_REG_SPEED_4 0x20000000
2913 uint32_t link_speed;
2916 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2917 link_speed = reg_val & I40E_REG_SPEED_MASK;
2918 reg_val &= I40E_REG_LINK_UP;
2919 link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2921 if (unlikely(link->link_status == 0))
2924 /* Parse the link status */
2925 switch (link_speed) {
2926 case I40E_REG_SPEED_0:
2927 link->link_speed = ETH_SPEED_NUM_100M;
2929 case I40E_REG_SPEED_1:
2930 link->link_speed = ETH_SPEED_NUM_1G;
2932 case I40E_REG_SPEED_2:
2933 if (hw->mac.type == I40E_MAC_X722)
2934 link->link_speed = ETH_SPEED_NUM_2_5G;
2936 link->link_speed = ETH_SPEED_NUM_10G;
2938 case I40E_REG_SPEED_3:
2939 if (hw->mac.type == I40E_MAC_X722) {
2940 link->link_speed = ETH_SPEED_NUM_5G;
2942 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2944 if (reg_val & I40E_REG_MACC_25GB)
2945 link->link_speed = ETH_SPEED_NUM_25G;
2947 link->link_speed = ETH_SPEED_NUM_40G;
2950 case I40E_REG_SPEED_4:
2951 if (hw->mac.type == I40E_MAC_X722)
2952 link->link_speed = ETH_SPEED_NUM_10G;
2954 link->link_speed = ETH_SPEED_NUM_20G;
2957 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2962 static __rte_always_inline void
2963 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2964 bool enable_lse, int wait_to_complete)
2966 #define CHECK_INTERVAL 100 /* 100ms */
2967 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2968 uint32_t rep_cnt = MAX_REPEAT_TIME;
2969 struct i40e_link_status link_status;
2972 memset(&link_status, 0, sizeof(link_status));
2975 memset(&link_status, 0, sizeof(link_status));
2977 /* Get link status information from hardware */
2978 status = i40e_aq_get_link_info(hw, enable_lse,
2979 &link_status, NULL);
2980 if (unlikely(status != I40E_SUCCESS)) {
2981 link->link_speed = ETH_SPEED_NUM_NONE;
2982 link->link_duplex = ETH_LINK_FULL_DUPLEX;
2983 PMD_DRV_LOG(ERR, "Failed to get link info");
2987 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2988 if (!wait_to_complete || link->link_status)
2991 rte_delay_ms(CHECK_INTERVAL);
2992 } while (--rep_cnt);
2994 /* Parse the link status */
2995 switch (link_status.link_speed) {
2996 case I40E_LINK_SPEED_100MB:
2997 link->link_speed = ETH_SPEED_NUM_100M;
2999 case I40E_LINK_SPEED_1GB:
3000 link->link_speed = ETH_SPEED_NUM_1G;
3002 case I40E_LINK_SPEED_10GB:
3003 link->link_speed = ETH_SPEED_NUM_10G;
3005 case I40E_LINK_SPEED_20GB:
3006 link->link_speed = ETH_SPEED_NUM_20G;
3008 case I40E_LINK_SPEED_25GB:
3009 link->link_speed = ETH_SPEED_NUM_25G;
3011 case I40E_LINK_SPEED_40GB:
3012 link->link_speed = ETH_SPEED_NUM_40G;
3015 if (link->link_status)
3016 link->link_speed = ETH_SPEED_NUM_UNKNOWN;
3018 link->link_speed = ETH_SPEED_NUM_NONE;
3024 i40e_dev_link_update(struct rte_eth_dev *dev,
3025 int wait_to_complete)
3027 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3028 struct rte_eth_link link;
3029 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3032 memset(&link, 0, sizeof(link));
3034 /* i40e uses full duplex only */
3035 link.link_duplex = ETH_LINK_FULL_DUPLEX;
3036 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
3037 ETH_LINK_SPEED_FIXED);
3039 if (!wait_to_complete && !enable_lse)
3040 update_link_reg(hw, &link);
3042 update_link_aq(hw, &link, enable_lse, wait_to_complete);
3045 rte_eth_linkstatus_get(hw->switch_dev, &link);
3047 ret = rte_eth_linkstatus_set(dev, &link);
3048 i40e_notify_all_vfs_link_status(dev);
3054 i40e_stat_update_48_in_64(struct i40e_hw *hw, uint32_t hireg,
3055 uint32_t loreg, bool offset_loaded, uint64_t *offset,
3056 uint64_t *stat, uint64_t *prev_stat)
3058 i40e_stat_update_48(hw, hireg, loreg, offset_loaded, offset, stat);
3059 /* enlarge the limitation when statistics counters overflowed */
3060 if (offset_loaded) {
3061 if (I40E_RXTX_BYTES_L_48_BIT(*prev_stat) > *stat)
3062 *stat += (uint64_t)1 << I40E_48_BIT_WIDTH;
3063 *stat += I40E_RXTX_BYTES_H_16_BIT(*prev_stat);
3068 /* Get all the statistics of a VSI */
3070 i40e_update_vsi_stats(struct i40e_vsi *vsi)
3072 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
3073 struct i40e_eth_stats *nes = &vsi->eth_stats;
3074 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3075 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
3077 i40e_stat_update_48_in_64(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
3078 vsi->offset_loaded, &oes->rx_bytes,
3079 &nes->rx_bytes, &vsi->prev_rx_bytes);
3080 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
3081 vsi->offset_loaded, &oes->rx_unicast,
3083 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
3084 vsi->offset_loaded, &oes->rx_multicast,
3085 &nes->rx_multicast);
3086 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
3087 vsi->offset_loaded, &oes->rx_broadcast,
3088 &nes->rx_broadcast);
3089 /* exclude CRC bytes */
3090 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
3091 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
3093 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
3094 &oes->rx_discards, &nes->rx_discards);
3095 /* GLV_REPC not supported */
3096 /* GLV_RMPC not supported */
3097 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
3098 &oes->rx_unknown_protocol,
3099 &nes->rx_unknown_protocol);
3100 i40e_stat_update_48_in_64(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
3101 vsi->offset_loaded, &oes->tx_bytes,
3102 &nes->tx_bytes, &vsi->prev_tx_bytes);
3103 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
3104 vsi->offset_loaded, &oes->tx_unicast,
3106 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
3107 vsi->offset_loaded, &oes->tx_multicast,
3108 &nes->tx_multicast);
3109 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
3110 vsi->offset_loaded, &oes->tx_broadcast,
3111 &nes->tx_broadcast);
3112 /* GLV_TDPC not supported */
3113 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
3114 &oes->tx_errors, &nes->tx_errors);
3115 vsi->offset_loaded = true;
3117 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
3119 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
3120 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
3121 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
3122 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
3123 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
3124 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3125 nes->rx_unknown_protocol);
3126 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
3127 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
3128 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
3129 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
3130 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
3131 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
3132 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
3137 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
3140 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3141 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
3143 /* Get rx/tx bytes of internal transfer packets */
3144 i40e_stat_update_48_in_64(hw, I40E_GLV_GORCH(hw->port),
3145 I40E_GLV_GORCL(hw->port),
3147 &pf->internal_stats_offset.rx_bytes,
3148 &pf->internal_stats.rx_bytes,
3149 &pf->internal_prev_rx_bytes);
3150 i40e_stat_update_48_in_64(hw, I40E_GLV_GOTCH(hw->port),
3151 I40E_GLV_GOTCL(hw->port),
3153 &pf->internal_stats_offset.tx_bytes,
3154 &pf->internal_stats.tx_bytes,
3155 &pf->internal_prev_tx_bytes);
3156 /* Get total internal rx packet count */
3157 i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
3158 I40E_GLV_UPRCL(hw->port),
3160 &pf->internal_stats_offset.rx_unicast,
3161 &pf->internal_stats.rx_unicast);
3162 i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
3163 I40E_GLV_MPRCL(hw->port),
3165 &pf->internal_stats_offset.rx_multicast,
3166 &pf->internal_stats.rx_multicast);
3167 i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
3168 I40E_GLV_BPRCL(hw->port),
3170 &pf->internal_stats_offset.rx_broadcast,
3171 &pf->internal_stats.rx_broadcast);
3172 /* Get total internal tx packet count */
3173 i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
3174 I40E_GLV_UPTCL(hw->port),
3176 &pf->internal_stats_offset.tx_unicast,
3177 &pf->internal_stats.tx_unicast);
3178 i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
3179 I40E_GLV_MPTCL(hw->port),
3181 &pf->internal_stats_offset.tx_multicast,
3182 &pf->internal_stats.tx_multicast);
3183 i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
3184 I40E_GLV_BPTCL(hw->port),
3186 &pf->internal_stats_offset.tx_broadcast,
3187 &pf->internal_stats.tx_broadcast);
3189 /* exclude CRC size */
3190 pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
3191 pf->internal_stats.rx_multicast +
3192 pf->internal_stats.rx_broadcast) * RTE_ETHER_CRC_LEN;
3194 /* Get statistics of struct i40e_eth_stats */
3195 i40e_stat_update_48_in_64(hw, I40E_GLPRT_GORCH(hw->port),
3196 I40E_GLPRT_GORCL(hw->port),
3197 pf->offset_loaded, &os->eth.rx_bytes,
3198 &ns->eth.rx_bytes, &pf->prev_rx_bytes);
3199 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
3200 I40E_GLPRT_UPRCL(hw->port),
3201 pf->offset_loaded, &os->eth.rx_unicast,
3202 &ns->eth.rx_unicast);
3203 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
3204 I40E_GLPRT_MPRCL(hw->port),
3205 pf->offset_loaded, &os->eth.rx_multicast,
3206 &ns->eth.rx_multicast);
3207 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
3208 I40E_GLPRT_BPRCL(hw->port),
3209 pf->offset_loaded, &os->eth.rx_broadcast,
3210 &ns->eth.rx_broadcast);
3211 /* Workaround: CRC size should not be included in byte statistics,
3212 * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
3215 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
3216 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
3218 /* exclude internal rx bytes
3219 * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
3220 * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
3222 * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
3224 if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
3225 ns->eth.rx_bytes = 0;
3227 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
3229 if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
3230 ns->eth.rx_unicast = 0;
3232 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
3234 if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
3235 ns->eth.rx_multicast = 0;
3237 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
3239 if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
3240 ns->eth.rx_broadcast = 0;
3242 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
3244 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
3245 pf->offset_loaded, &os->eth.rx_discards,
3246 &ns->eth.rx_discards);
3247 /* GLPRT_REPC not supported */
3248 /* GLPRT_RMPC not supported */
3249 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
3251 &os->eth.rx_unknown_protocol,
3252 &ns->eth.rx_unknown_protocol);
3253 i40e_stat_update_48_in_64(hw, I40E_GLPRT_GOTCH(hw->port),
3254 I40E_GLPRT_GOTCL(hw->port),
3255 pf->offset_loaded, &os->eth.tx_bytes,
3256 &ns->eth.tx_bytes, &pf->prev_tx_bytes);
3257 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
3258 I40E_GLPRT_UPTCL(hw->port),
3259 pf->offset_loaded, &os->eth.tx_unicast,
3260 &ns->eth.tx_unicast);
3261 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
3262 I40E_GLPRT_MPTCL(hw->port),
3263 pf->offset_loaded, &os->eth.tx_multicast,
3264 &ns->eth.tx_multicast);
3265 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
3266 I40E_GLPRT_BPTCL(hw->port),
3267 pf->offset_loaded, &os->eth.tx_broadcast,
3268 &ns->eth.tx_broadcast);
3269 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3270 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3272 /* exclude internal tx bytes
3273 * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
3274 * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
3276 * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
3278 if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
3279 ns->eth.tx_bytes = 0;
3281 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3283 if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3284 ns->eth.tx_unicast = 0;
3286 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3288 if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3289 ns->eth.tx_multicast = 0;
3291 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3293 if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3294 ns->eth.tx_broadcast = 0;
3296 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3298 /* GLPRT_TEPC not supported */
3300 /* additional port specific stats */
3301 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3302 pf->offset_loaded, &os->tx_dropped_link_down,
3303 &ns->tx_dropped_link_down);
3304 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3305 pf->offset_loaded, &os->crc_errors,
3307 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3308 pf->offset_loaded, &os->illegal_bytes,
3309 &ns->illegal_bytes);
3310 /* GLPRT_ERRBC not supported */
3311 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3312 pf->offset_loaded, &os->mac_local_faults,
3313 &ns->mac_local_faults);
3314 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3315 pf->offset_loaded, &os->mac_remote_faults,
3316 &ns->mac_remote_faults);
3317 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3318 pf->offset_loaded, &os->rx_length_errors,
3319 &ns->rx_length_errors);
3320 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3321 pf->offset_loaded, &os->link_xon_rx,
3323 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3324 pf->offset_loaded, &os->link_xoff_rx,
3326 for (i = 0; i < 8; i++) {
3327 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3329 &os->priority_xon_rx[i],
3330 &ns->priority_xon_rx[i]);
3331 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3333 &os->priority_xoff_rx[i],
3334 &ns->priority_xoff_rx[i]);
3336 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3337 pf->offset_loaded, &os->link_xon_tx,
3339 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3340 pf->offset_loaded, &os->link_xoff_tx,
3342 for (i = 0; i < 8; i++) {
3343 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3345 &os->priority_xon_tx[i],
3346 &ns->priority_xon_tx[i]);
3347 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3349 &os->priority_xoff_tx[i],
3350 &ns->priority_xoff_tx[i]);
3351 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3353 &os->priority_xon_2_xoff[i],
3354 &ns->priority_xon_2_xoff[i]);
3356 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3357 I40E_GLPRT_PRC64L(hw->port),
3358 pf->offset_loaded, &os->rx_size_64,
3360 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3361 I40E_GLPRT_PRC127L(hw->port),
3362 pf->offset_loaded, &os->rx_size_127,
3364 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3365 I40E_GLPRT_PRC255L(hw->port),
3366 pf->offset_loaded, &os->rx_size_255,
3368 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3369 I40E_GLPRT_PRC511L(hw->port),
3370 pf->offset_loaded, &os->rx_size_511,
3372 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3373 I40E_GLPRT_PRC1023L(hw->port),
3374 pf->offset_loaded, &os->rx_size_1023,
3376 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3377 I40E_GLPRT_PRC1522L(hw->port),
3378 pf->offset_loaded, &os->rx_size_1522,
3380 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3381 I40E_GLPRT_PRC9522L(hw->port),
3382 pf->offset_loaded, &os->rx_size_big,
3384 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3385 pf->offset_loaded, &os->rx_undersize,
3387 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3388 pf->offset_loaded, &os->rx_fragments,
3390 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3391 pf->offset_loaded, &os->rx_oversize,
3393 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3394 pf->offset_loaded, &os->rx_jabber,
3396 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3397 I40E_GLPRT_PTC64L(hw->port),
3398 pf->offset_loaded, &os->tx_size_64,
3400 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3401 I40E_GLPRT_PTC127L(hw->port),
3402 pf->offset_loaded, &os->tx_size_127,
3404 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3405 I40E_GLPRT_PTC255L(hw->port),
3406 pf->offset_loaded, &os->tx_size_255,
3408 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3409 I40E_GLPRT_PTC511L(hw->port),
3410 pf->offset_loaded, &os->tx_size_511,
3412 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3413 I40E_GLPRT_PTC1023L(hw->port),
3414 pf->offset_loaded, &os->tx_size_1023,
3416 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3417 I40E_GLPRT_PTC1522L(hw->port),
3418 pf->offset_loaded, &os->tx_size_1522,
3420 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3421 I40E_GLPRT_PTC9522L(hw->port),
3422 pf->offset_loaded, &os->tx_size_big,
3424 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3426 &os->fd_sb_match, &ns->fd_sb_match);
3427 /* GLPRT_MSPDC not supported */
3428 /* GLPRT_XEC not supported */
3430 pf->offset_loaded = true;
3433 i40e_update_vsi_stats(pf->main_vsi);
3436 /* Get all statistics of a port */
3438 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3440 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3441 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3442 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3443 struct i40e_vsi *vsi;
3446 /* call read registers - updates values, now write them to struct */
3447 i40e_read_stats_registers(pf, hw);
3449 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3450 pf->main_vsi->eth_stats.rx_multicast +
3451 pf->main_vsi->eth_stats.rx_broadcast -
3452 pf->main_vsi->eth_stats.rx_discards;
3453 stats->opackets = ns->eth.tx_unicast +
3454 ns->eth.tx_multicast +
3455 ns->eth.tx_broadcast;
3456 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes;
3457 stats->obytes = ns->eth.tx_bytes;
3458 stats->oerrors = ns->eth.tx_errors +
3459 pf->main_vsi->eth_stats.tx_errors;
3462 stats->imissed = ns->eth.rx_discards +
3463 pf->main_vsi->eth_stats.rx_discards;
3464 stats->ierrors = ns->crc_errors +
3465 ns->rx_length_errors + ns->rx_undersize +
3466 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3469 for (i = 0; i < pf->vf_num; i++) {
3470 vsi = pf->vfs[i].vsi;
3471 i40e_update_vsi_stats(vsi);
3473 stats->ipackets += (vsi->eth_stats.rx_unicast +
3474 vsi->eth_stats.rx_multicast +
3475 vsi->eth_stats.rx_broadcast -
3476 vsi->eth_stats.rx_discards);
3477 stats->ibytes += vsi->eth_stats.rx_bytes;
3478 stats->oerrors += vsi->eth_stats.tx_errors;
3479 stats->imissed += vsi->eth_stats.rx_discards;
3483 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3484 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
3485 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
3486 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
3487 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
3488 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
3489 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3490 ns->eth.rx_unknown_protocol);
3491 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
3492 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
3493 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
3494 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
3495 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
3496 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
3498 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
3499 ns->tx_dropped_link_down);
3500 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
3501 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
3503 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
3504 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
3505 ns->mac_local_faults);
3506 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
3507 ns->mac_remote_faults);
3508 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
3509 ns->rx_length_errors);
3510 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
3511 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
3512 for (i = 0; i < 8; i++) {
3513 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
3514 i, ns->priority_xon_rx[i]);
3515 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
3516 i, ns->priority_xoff_rx[i]);
3518 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
3519 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
3520 for (i = 0; i < 8; i++) {
3521 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
3522 i, ns->priority_xon_tx[i]);
3523 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
3524 i, ns->priority_xoff_tx[i]);
3525 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
3526 i, ns->priority_xon_2_xoff[i]);
3528 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
3529 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
3530 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
3531 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
3532 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
3533 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
3534 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
3535 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
3536 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
3537 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
3538 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
3539 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
3540 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
3541 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
3542 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
3543 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
3544 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
3545 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
3546 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3547 ns->mac_short_packet_dropped);
3548 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
3549 ns->checksum_error);
3550 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
3551 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3555 /* Reset the statistics */
3557 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3559 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3560 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3562 /* Mark PF and VSI stats to update the offset, aka "reset" */
3563 pf->offset_loaded = false;
3565 pf->main_vsi->offset_loaded = false;
3567 /* read the stats, reading current register values into offset */
3568 i40e_read_stats_registers(pf, hw);
3574 i40e_xstats_calc_num(void)
3576 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3577 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3578 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3581 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3582 struct rte_eth_xstat_name *xstats_names,
3583 __rte_unused unsigned limit)
3588 if (xstats_names == NULL)
3589 return i40e_xstats_calc_num();
3591 /* Note: limit checked in rte_eth_xstats_names() */
3593 /* Get stats from i40e_eth_stats struct */
3594 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3595 strlcpy(xstats_names[count].name,
3596 rte_i40e_stats_strings[i].name,
3597 sizeof(xstats_names[count].name));
3601 /* Get individiual stats from i40e_hw_port struct */
3602 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3603 strlcpy(xstats_names[count].name,
3604 rte_i40e_hw_port_strings[i].name,
3605 sizeof(xstats_names[count].name));
3609 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3610 for (prio = 0; prio < 8; prio++) {
3611 snprintf(xstats_names[count].name,
3612 sizeof(xstats_names[count].name),
3613 "rx_priority%u_%s", prio,
3614 rte_i40e_rxq_prio_strings[i].name);
3619 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3620 for (prio = 0; prio < 8; prio++) {
3621 snprintf(xstats_names[count].name,
3622 sizeof(xstats_names[count].name),
3623 "tx_priority%u_%s", prio,
3624 rte_i40e_txq_prio_strings[i].name);
3632 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3635 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3636 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3637 unsigned i, count, prio;
3638 struct i40e_hw_port_stats *hw_stats = &pf->stats;
3640 count = i40e_xstats_calc_num();
3644 i40e_read_stats_registers(pf, hw);
3651 /* Get stats from i40e_eth_stats struct */
3652 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3653 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3654 rte_i40e_stats_strings[i].offset);
3655 xstats[count].id = count;
3659 /* Get individiual stats from i40e_hw_port struct */
3660 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3661 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3662 rte_i40e_hw_port_strings[i].offset);
3663 xstats[count].id = count;
3667 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3668 for (prio = 0; prio < 8; prio++) {
3669 xstats[count].value =
3670 *(uint64_t *)(((char *)hw_stats) +
3671 rte_i40e_rxq_prio_strings[i].offset +
3672 (sizeof(uint64_t) * prio));
3673 xstats[count].id = count;
3678 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3679 for (prio = 0; prio < 8; prio++) {
3680 xstats[count].value =
3681 *(uint64_t *)(((char *)hw_stats) +
3682 rte_i40e_txq_prio_strings[i].offset +
3683 (sizeof(uint64_t) * prio));
3684 xstats[count].id = count;
3693 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3695 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3701 full_ver = hw->nvm.oem_ver;
3702 ver = (u8)(full_ver >> 24);
3703 build = (u16)((full_ver >> 8) & 0xffff);
3704 patch = (u8)(full_ver & 0xff);
3706 ret = snprintf(fw_version, fw_size,
3707 "%d.%d%d 0x%08x %d.%d.%d",
3708 ((hw->nvm.version >> 12) & 0xf),
3709 ((hw->nvm.version >> 4) & 0xff),
3710 (hw->nvm.version & 0xf), hw->nvm.eetrack,
3713 ret += 1; /* add the size of '\0' */
3714 if (fw_size < (u32)ret)
3721 * When using NVM 6.01(for X710 XL710 XXV710)/3.33(for X722) or later,
3722 * the Rx data path does not hang if the FW LLDP is stopped.
3723 * return true if lldp need to stop
3724 * return false if we cannot disable the LLDP to avoid Rx data path blocking.
3727 i40e_need_stop_lldp(struct rte_eth_dev *dev)
3730 char ver_str[64] = {0};
3731 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3733 i40e_fw_version_get(dev, ver_str, 64);
3734 nvm_ver = atof(ver_str);
3735 if ((hw->mac.type == I40E_MAC_X722 ||
3736 hw->mac.type == I40E_MAC_X722_VF) &&
3737 ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(3.33 * 1000)))
3739 else if ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(6.01 * 1000))
3746 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3748 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3749 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3750 struct i40e_vsi *vsi = pf->main_vsi;
3751 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3753 dev_info->max_rx_queues = vsi->nb_qps;
3754 dev_info->max_tx_queues = vsi->nb_qps;
3755 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3756 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3757 dev_info->max_mac_addrs = vsi->max_macaddrs;
3758 dev_info->max_vfs = pci_dev->max_vfs;
3759 dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
3760 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3761 dev_info->rx_queue_offload_capa = 0;
3762 dev_info->rx_offload_capa =
3763 DEV_RX_OFFLOAD_VLAN_STRIP |
3764 DEV_RX_OFFLOAD_QINQ_STRIP |
3765 DEV_RX_OFFLOAD_IPV4_CKSUM |
3766 DEV_RX_OFFLOAD_UDP_CKSUM |
3767 DEV_RX_OFFLOAD_TCP_CKSUM |
3768 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3769 DEV_RX_OFFLOAD_KEEP_CRC |
3770 DEV_RX_OFFLOAD_SCATTER |
3771 DEV_RX_OFFLOAD_VLAN_EXTEND |
3772 DEV_RX_OFFLOAD_VLAN_FILTER |
3773 DEV_RX_OFFLOAD_JUMBO_FRAME |
3774 DEV_RX_OFFLOAD_RSS_HASH;
3776 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3777 dev_info->tx_offload_capa =
3778 DEV_TX_OFFLOAD_VLAN_INSERT |
3779 DEV_TX_OFFLOAD_QINQ_INSERT |
3780 DEV_TX_OFFLOAD_IPV4_CKSUM |
3781 DEV_TX_OFFLOAD_UDP_CKSUM |
3782 DEV_TX_OFFLOAD_TCP_CKSUM |
3783 DEV_TX_OFFLOAD_SCTP_CKSUM |
3784 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3785 DEV_TX_OFFLOAD_TCP_TSO |
3786 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3787 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3788 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3789 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3790 DEV_TX_OFFLOAD_MULTI_SEGS |
3791 dev_info->tx_queue_offload_capa;
3792 dev_info->dev_capa =
3793 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3794 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3796 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3798 dev_info->reta_size = pf->hash_lut_size;
3799 dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3801 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3803 .pthresh = I40E_DEFAULT_RX_PTHRESH,
3804 .hthresh = I40E_DEFAULT_RX_HTHRESH,
3805 .wthresh = I40E_DEFAULT_RX_WTHRESH,
3807 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3812 dev_info->default_txconf = (struct rte_eth_txconf) {
3814 .pthresh = I40E_DEFAULT_TX_PTHRESH,
3815 .hthresh = I40E_DEFAULT_TX_HTHRESH,
3816 .wthresh = I40E_DEFAULT_TX_WTHRESH,
3818 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3819 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3823 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3824 .nb_max = I40E_MAX_RING_DESC,
3825 .nb_min = I40E_MIN_RING_DESC,
3826 .nb_align = I40E_ALIGN_RING_DESC,
3829 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3830 .nb_max = I40E_MAX_RING_DESC,
3831 .nb_min = I40E_MIN_RING_DESC,
3832 .nb_align = I40E_ALIGN_RING_DESC,
3833 .nb_seg_max = I40E_TX_MAX_SEG,
3834 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3837 if (pf->flags & I40E_FLAG_VMDQ) {
3838 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3839 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3840 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3841 pf->max_nb_vmdq_vsi;
3842 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3843 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3844 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3847 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3849 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3850 dev_info->default_rxportconf.nb_queues = 2;
3851 dev_info->default_txportconf.nb_queues = 2;
3852 if (dev->data->nb_rx_queues == 1)
3853 dev_info->default_rxportconf.ring_size = 2048;
3855 dev_info->default_rxportconf.ring_size = 1024;
3856 if (dev->data->nb_tx_queues == 1)
3857 dev_info->default_txportconf.ring_size = 1024;
3859 dev_info->default_txportconf.ring_size = 512;
3861 } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3863 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3864 dev_info->default_rxportconf.nb_queues = 1;
3865 dev_info->default_txportconf.nb_queues = 1;
3866 dev_info->default_rxportconf.ring_size = 256;
3867 dev_info->default_txportconf.ring_size = 256;
3870 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3871 dev_info->default_rxportconf.nb_queues = 1;
3872 dev_info->default_txportconf.nb_queues = 1;
3873 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3874 dev_info->default_rxportconf.ring_size = 512;
3875 dev_info->default_txportconf.ring_size = 256;
3877 dev_info->default_rxportconf.ring_size = 256;
3878 dev_info->default_txportconf.ring_size = 256;
3881 dev_info->default_rxportconf.burst_size = 32;
3882 dev_info->default_txportconf.burst_size = 32;
3888 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3890 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3891 struct i40e_vsi *vsi = pf->main_vsi;
3892 PMD_INIT_FUNC_TRACE();
3895 return i40e_vsi_add_vlan(vsi, vlan_id);
3897 return i40e_vsi_delete_vlan(vsi, vlan_id);
3901 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3902 enum rte_vlan_type vlan_type,
3903 uint16_t tpid, int qinq)
3905 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3908 uint16_t reg_id = 3;
3912 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3916 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3918 if (ret != I40E_SUCCESS) {
3920 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3925 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3928 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3929 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3930 if (reg_r == reg_w) {
3931 PMD_DRV_LOG(DEBUG, "No need to write");
3935 ret = i40e_aq_debug_write_global_register(hw,
3936 I40E_GL_SWT_L2TAGCTRL(reg_id),
3938 if (ret != I40E_SUCCESS) {
3940 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3945 "Global register 0x%08x is changed with value 0x%08x",
3946 I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3952 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3953 enum rte_vlan_type vlan_type,
3956 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3957 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3958 int qinq = dev->data->dev_conf.rxmode.offloads &
3959 DEV_RX_OFFLOAD_VLAN_EXTEND;
3962 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3963 vlan_type != ETH_VLAN_TYPE_OUTER) ||
3964 (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3966 "Unsupported vlan type.");
3970 if (pf->support_multi_driver) {
3971 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3975 /* 802.1ad frames ability is added in NVM API 1.7*/
3976 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3978 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3979 hw->first_tag = rte_cpu_to_le_16(tpid);
3980 else if (vlan_type == ETH_VLAN_TYPE_INNER)
3981 hw->second_tag = rte_cpu_to_le_16(tpid);
3983 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3984 hw->second_tag = rte_cpu_to_le_16(tpid);
3986 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL);
3987 if (ret != I40E_SUCCESS) {
3989 "Set switch config failed aq_err: %d",
3990 hw->aq.asq_last_status);
3994 /* If NVM API < 1.7, keep the register setting */
3995 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
4001 /* Configure outer vlan stripping on or off in QinQ mode */
4003 i40e_vsi_config_outer_vlan_stripping(struct i40e_vsi *vsi, bool on)
4005 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4006 int ret = I40E_SUCCESS;
4009 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
4010 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
4014 /* Configure for outer VLAN RX stripping */
4015 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
4018 reg |= I40E_VSI_TSR_QINQ_STRIP;
4020 reg &= ~I40E_VSI_TSR_QINQ_STRIP;
4022 ret = i40e_aq_debug_write_register(hw,
4023 I40E_VSI_TSR(vsi->vsi_id),
4026 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
4028 return I40E_ERR_CONFIG;
4035 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4037 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4038 struct i40e_vsi *vsi = pf->main_vsi;
4039 struct rte_eth_rxmode *rxmode;
4041 rxmode = &dev->data->dev_conf.rxmode;
4042 if (mask & ETH_VLAN_FILTER_MASK) {
4043 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4044 i40e_vsi_config_vlan_filter(vsi, TRUE);
4046 i40e_vsi_config_vlan_filter(vsi, FALSE);
4049 if (mask & ETH_VLAN_STRIP_MASK) {
4050 /* Enable or disable VLAN stripping */
4051 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
4052 i40e_vsi_config_vlan_stripping(vsi, TRUE);
4054 i40e_vsi_config_vlan_stripping(vsi, FALSE);
4057 if (mask & ETH_VLAN_EXTEND_MASK) {
4058 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
4059 i40e_vsi_config_double_vlan(vsi, TRUE);
4060 /* Set global registers with default ethertype. */
4061 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
4062 RTE_ETHER_TYPE_VLAN);
4063 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
4064 RTE_ETHER_TYPE_VLAN);
4067 i40e_vsi_config_double_vlan(vsi, FALSE);
4070 if (mask & ETH_QINQ_STRIP_MASK) {
4071 /* Enable or disable outer VLAN stripping */
4072 if (rxmode->offloads & DEV_RX_OFFLOAD_QINQ_STRIP)
4073 i40e_vsi_config_outer_vlan_stripping(vsi, TRUE);
4075 i40e_vsi_config_outer_vlan_stripping(vsi, FALSE);
4082 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
4083 __rte_unused uint16_t queue,
4084 __rte_unused int on)
4086 PMD_INIT_FUNC_TRACE();
4090 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
4092 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4093 struct i40e_vsi *vsi = pf->main_vsi;
4094 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
4095 struct i40e_vsi_vlan_pvid_info info;
4097 memset(&info, 0, sizeof(info));
4100 info.config.pvid = pvid;
4102 info.config.reject.tagged =
4103 data->dev_conf.txmode.hw_vlan_reject_tagged;
4104 info.config.reject.untagged =
4105 data->dev_conf.txmode.hw_vlan_reject_untagged;
4108 return i40e_vsi_vlan_pvid_set(vsi, &info);
4112 i40e_dev_led_on(struct rte_eth_dev *dev)
4114 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4115 uint32_t mode = i40e_led_get(hw);
4118 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
4124 i40e_dev_led_off(struct rte_eth_dev *dev)
4126 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4127 uint32_t mode = i40e_led_get(hw);
4130 i40e_led_set(hw, 0, false);
4136 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4138 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4139 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4141 fc_conf->pause_time = pf->fc_conf.pause_time;
4143 /* read out from register, in case they are modified by other port */
4144 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
4145 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
4146 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
4147 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
4149 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
4150 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
4152 /* Return current mode according to actual setting*/
4153 switch (hw->fc.current_mode) {
4155 fc_conf->mode = RTE_FC_FULL;
4157 case I40E_FC_TX_PAUSE:
4158 fc_conf->mode = RTE_FC_TX_PAUSE;
4160 case I40E_FC_RX_PAUSE:
4161 fc_conf->mode = RTE_FC_RX_PAUSE;
4165 fc_conf->mode = RTE_FC_NONE;
4172 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4174 uint32_t mflcn_reg, fctrl_reg, reg;
4175 uint32_t max_high_water;
4176 uint8_t i, aq_failure;
4180 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
4181 [RTE_FC_NONE] = I40E_FC_NONE,
4182 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
4183 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
4184 [RTE_FC_FULL] = I40E_FC_FULL
4187 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
4189 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
4190 if ((fc_conf->high_water > max_high_water) ||
4191 (fc_conf->high_water < fc_conf->low_water)) {
4193 "Invalid high/low water setup value in KB, High_water must be <= %d.",
4198 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4199 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4200 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
4202 pf->fc_conf.pause_time = fc_conf->pause_time;
4203 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
4204 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
4206 PMD_INIT_FUNC_TRACE();
4208 /* All the link flow control related enable/disable register
4209 * configuration is handle by the F/W
4211 err = i40e_set_fc(hw, &aq_failure, true);
4215 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
4216 /* Configure flow control refresh threshold,
4217 * the value for stat_tx_pause_refresh_timer[8]
4218 * is used for global pause operation.
4222 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
4223 pf->fc_conf.pause_time);
4225 /* configure the timer value included in transmitted pause
4227 * the value for stat_tx_pause_quanta[8] is used for global
4230 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
4231 pf->fc_conf.pause_time);
4233 fctrl_reg = I40E_READ_REG(hw,
4234 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
4236 if (fc_conf->mac_ctrl_frame_fwd != 0)
4237 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
4239 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
4241 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
4244 /* Configure pause time (2 TCs per register) */
4245 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
4246 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
4247 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
4249 /* Configure flow control refresh threshold value */
4250 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
4251 pf->fc_conf.pause_time / 2);
4253 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4255 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
4256 *depending on configuration
4258 if (fc_conf->mac_ctrl_frame_fwd != 0) {
4259 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
4260 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
4262 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
4263 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
4266 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
4269 if (!pf->support_multi_driver) {
4270 /* config water marker both based on the packets and bytes */
4271 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
4272 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4273 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4274 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
4275 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4276 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4277 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
4278 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4280 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
4281 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4285 "Water marker configuration is not supported.");
4288 I40E_WRITE_FLUSH(hw);
4294 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
4295 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
4297 PMD_INIT_FUNC_TRACE();
4302 /* Add a MAC address, and update filters */
4304 i40e_macaddr_add(struct rte_eth_dev *dev,
4305 struct rte_ether_addr *mac_addr,
4306 __rte_unused uint32_t index,
4309 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4310 struct i40e_mac_filter_info mac_filter;
4311 struct i40e_vsi *vsi;
4312 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
4315 /* If VMDQ not enabled or configured, return */
4316 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
4317 !pf->nb_cfg_vmdq_vsi)) {
4318 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
4319 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
4324 if (pool > pf->nb_cfg_vmdq_vsi) {
4325 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
4326 pool, pf->nb_cfg_vmdq_vsi);
4330 rte_memcpy(&mac_filter.mac_addr, mac_addr, RTE_ETHER_ADDR_LEN);
4331 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4332 mac_filter.filter_type = I40E_MACVLAN_PERFECT_MATCH;
4334 mac_filter.filter_type = I40E_MAC_PERFECT_MATCH;
4339 vsi = pf->vmdq[pool - 1].vsi;
4341 ret = i40e_vsi_add_mac(vsi, &mac_filter);
4342 if (ret != I40E_SUCCESS) {
4343 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4349 /* Remove a MAC address, and update filters */
4351 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4353 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4354 struct i40e_vsi *vsi;
4355 struct rte_eth_dev_data *data = dev->data;
4356 struct rte_ether_addr *macaddr;
4361 macaddr = &(data->mac_addrs[index]);
4363 pool_sel = dev->data->mac_pool_sel[index];
4365 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4366 if (pool_sel & (1ULL << i)) {
4370 /* No VMDQ pool enabled or configured */
4371 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4372 (i > pf->nb_cfg_vmdq_vsi)) {
4374 "No VMDQ pool enabled/configured");
4377 vsi = pf->vmdq[i - 1].vsi;
4379 ret = i40e_vsi_delete_mac(vsi, macaddr);
4382 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4390 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4392 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4393 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4400 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4401 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id,
4402 vsi->type != I40E_VSI_SRIOV,
4405 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4409 uint32_t *lut_dw = (uint32_t *)lut;
4410 uint16_t i, lut_size_dw = lut_size / 4;
4412 if (vsi->type == I40E_VSI_SRIOV) {
4413 for (i = 0; i <= lut_size_dw; i++) {
4414 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4415 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4418 for (i = 0; i < lut_size_dw; i++)
4419 lut_dw[i] = I40E_READ_REG(hw,
4428 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4437 pf = I40E_VSI_TO_PF(vsi);
4438 hw = I40E_VSI_TO_HW(vsi);
4440 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4441 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id,
4442 vsi->type != I40E_VSI_SRIOV,
4445 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4449 uint32_t *lut_dw = (uint32_t *)lut;
4450 uint16_t i, lut_size_dw = lut_size / 4;
4452 if (vsi->type == I40E_VSI_SRIOV) {
4453 for (i = 0; i < lut_size_dw; i++)
4456 I40E_VFQF_HLUT1(i, vsi->user_param),
4459 for (i = 0; i < lut_size_dw; i++)
4460 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4463 I40E_WRITE_FLUSH(hw);
4470 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4471 struct rte_eth_rss_reta_entry64 *reta_conf,
4474 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4475 uint16_t i, lut_size = pf->hash_lut_size;
4476 uint16_t idx, shift;
4480 if (reta_size != lut_size ||
4481 reta_size > ETH_RSS_RETA_SIZE_512) {
4483 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4484 reta_size, lut_size);
4488 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4490 PMD_DRV_LOG(ERR, "No memory can be allocated");
4493 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4496 for (i = 0; i < reta_size; i++) {
4497 idx = i / RTE_RETA_GROUP_SIZE;
4498 shift = i % RTE_RETA_GROUP_SIZE;
4499 if (reta_conf[idx].mask & (1ULL << shift))
4500 lut[i] = reta_conf[idx].reta[shift];
4502 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4504 pf->adapter->rss_reta_updated = 1;
4513 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4514 struct rte_eth_rss_reta_entry64 *reta_conf,
4517 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4518 uint16_t i, lut_size = pf->hash_lut_size;
4519 uint16_t idx, shift;
4523 if (reta_size != lut_size ||
4524 reta_size > ETH_RSS_RETA_SIZE_512) {
4526 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4527 reta_size, lut_size);
4531 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4533 PMD_DRV_LOG(ERR, "No memory can be allocated");
4537 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4540 for (i = 0; i < reta_size; i++) {
4541 idx = i / RTE_RETA_GROUP_SIZE;
4542 shift = i % RTE_RETA_GROUP_SIZE;
4543 if (reta_conf[idx].mask & (1ULL << shift))
4544 reta_conf[idx].reta[shift] = lut[i];
4554 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4555 * @hw: pointer to the HW structure
4556 * @mem: pointer to mem struct to fill out
4557 * @size: size of memory requested
4558 * @alignment: what to align the allocation to
4560 enum i40e_status_code
4561 i40e_allocate_dma_mem_d(__rte_unused struct i40e_hw *hw,
4562 struct i40e_dma_mem *mem,
4566 const struct rte_memzone *mz = NULL;
4567 char z_name[RTE_MEMZONE_NAMESIZE];
4570 return I40E_ERR_PARAM;
4572 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4573 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4574 RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4576 return I40E_ERR_NO_MEMORY;
4581 mem->zone = (const void *)mz;
4583 "memzone %s allocated with physical address: %"PRIu64,
4586 return I40E_SUCCESS;
4590 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4591 * @hw: pointer to the HW structure
4592 * @mem: ptr to mem struct to free
4594 enum i40e_status_code
4595 i40e_free_dma_mem_d(__rte_unused struct i40e_hw *hw,
4596 struct i40e_dma_mem *mem)
4599 return I40E_ERR_PARAM;
4602 "memzone %s to be freed with physical address: %"PRIu64,
4603 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4604 rte_memzone_free((const struct rte_memzone *)mem->zone);
4609 return I40E_SUCCESS;
4613 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4614 * @hw: pointer to the HW structure
4615 * @mem: pointer to mem struct to fill out
4616 * @size: size of memory requested
4618 enum i40e_status_code
4619 i40e_allocate_virt_mem_d(__rte_unused struct i40e_hw *hw,
4620 struct i40e_virt_mem *mem,
4624 return I40E_ERR_PARAM;
4627 mem->va = rte_zmalloc("i40e", size, 0);
4630 return I40E_SUCCESS;
4632 return I40E_ERR_NO_MEMORY;
4636 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4637 * @hw: pointer to the HW structure
4638 * @mem: pointer to mem struct to free
4640 enum i40e_status_code
4641 i40e_free_virt_mem_d(__rte_unused struct i40e_hw *hw,
4642 struct i40e_virt_mem *mem)
4645 return I40E_ERR_PARAM;
4650 return I40E_SUCCESS;
4654 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4656 rte_spinlock_init(&sp->spinlock);
4660 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4662 rte_spinlock_lock(&sp->spinlock);
4666 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4668 rte_spinlock_unlock(&sp->spinlock);
4672 i40e_destroy_spinlock_d(__rte_unused struct i40e_spinlock *sp)
4678 * Get the hardware capabilities, which will be parsed
4679 * and saved into struct i40e_hw.
4682 i40e_get_cap(struct i40e_hw *hw)
4684 struct i40e_aqc_list_capabilities_element_resp *buf;
4685 uint16_t len, size = 0;
4688 /* Calculate a huge enough buff for saving response data temporarily */
4689 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4690 I40E_MAX_CAP_ELE_NUM;
4691 buf = rte_zmalloc("i40e", len, 0);
4693 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4694 return I40E_ERR_NO_MEMORY;
4697 /* Get, parse the capabilities and save it to hw */
4698 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4699 i40e_aqc_opc_list_func_capabilities, NULL);
4700 if (ret != I40E_SUCCESS)
4701 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4703 /* Free the temporary buffer after being used */
4709 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4
4711 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4719 pf = (struct i40e_pf *)opaque;
4723 num = strtoul(value, &end, 0);
4724 if (errno != 0 || end == value || *end != 0) {
4725 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4726 "kept the value = %hu", value, pf->vf_nb_qp_max);
4730 if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4731 pf->vf_nb_qp_max = (uint16_t)num;
4733 /* here return 0 to make next valid same argument work */
4734 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4735 "power of 2 and equal or less than 16 !, Now it is "
4736 "kept the value = %hu", num, pf->vf_nb_qp_max);
4741 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4743 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4744 struct rte_kvargs *kvlist;
4747 /* set default queue number per VF as 4 */
4748 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4750 if (dev->device->devargs == NULL)
4753 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4757 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4758 if (!kvargs_count) {
4759 rte_kvargs_free(kvlist);
4763 if (kvargs_count > 1)
4764 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4765 "the first invalid or last valid one is used !",
4766 ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4768 rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4769 i40e_pf_parse_vf_queue_number_handler, pf);
4771 rte_kvargs_free(kvlist);
4777 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4779 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4780 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4781 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4782 uint16_t qp_count = 0, vsi_count = 0;
4784 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4785 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4789 i40e_pf_config_vf_rxq_number(dev);
4791 /* Add the parameter init for LFC */
4792 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4793 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4794 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4796 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4797 pf->max_num_vsi = hw->func_caps.num_vsis;
4798 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4799 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4801 /* FDir queue/VSI allocation */
4802 pf->fdir_qp_offset = 0;
4803 if (hw->func_caps.fd) {
4804 pf->flags |= I40E_FLAG_FDIR;
4805 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4807 pf->fdir_nb_qps = 0;
4809 qp_count += pf->fdir_nb_qps;
4812 /* LAN queue/VSI allocation */
4813 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4814 if (!hw->func_caps.rss) {
4817 pf->flags |= I40E_FLAG_RSS;
4818 if (hw->mac.type == I40E_MAC_X722)
4819 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4820 pf->lan_nb_qps = pf->lan_nb_qp_max;
4822 qp_count += pf->lan_nb_qps;
4825 /* VF queue/VSI allocation */
4826 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4827 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4828 pf->flags |= I40E_FLAG_SRIOV;
4829 pf->vf_nb_qps = pf->vf_nb_qp_max;
4830 pf->vf_num = pci_dev->max_vfs;
4832 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4833 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4838 qp_count += pf->vf_nb_qps * pf->vf_num;
4839 vsi_count += pf->vf_num;
4841 /* VMDq queue/VSI allocation */
4842 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4843 pf->vmdq_nb_qps = 0;
4844 pf->max_nb_vmdq_vsi = 0;
4845 if (hw->func_caps.vmdq) {
4846 if (qp_count < hw->func_caps.num_tx_qp &&
4847 vsi_count < hw->func_caps.num_vsis) {
4848 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4849 qp_count) / pf->vmdq_nb_qp_max;
4851 /* Limit the maximum number of VMDq vsi to the maximum
4852 * ethdev can support
4854 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4855 hw->func_caps.num_vsis - vsi_count);
4856 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4858 if (pf->max_nb_vmdq_vsi) {
4859 pf->flags |= I40E_FLAG_VMDQ;
4860 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4862 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4863 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4864 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4867 "No enough queues left for VMDq");
4870 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4873 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4874 vsi_count += pf->max_nb_vmdq_vsi;
4876 if (hw->func_caps.dcb)
4877 pf->flags |= I40E_FLAG_DCB;
4879 if (qp_count > hw->func_caps.num_tx_qp) {
4881 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4882 qp_count, hw->func_caps.num_tx_qp);
4885 if (vsi_count > hw->func_caps.num_vsis) {
4887 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4888 vsi_count, hw->func_caps.num_vsis);
4896 i40e_pf_get_switch_config(struct i40e_pf *pf)
4898 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4899 struct i40e_aqc_get_switch_config_resp *switch_config;
4900 struct i40e_aqc_switch_config_element_resp *element;
4901 uint16_t start_seid = 0, num_reported;
4904 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4905 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4906 if (!switch_config) {
4907 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4911 /* Get the switch configurations */
4912 ret = i40e_aq_get_switch_config(hw, switch_config,
4913 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4914 if (ret != I40E_SUCCESS) {
4915 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4918 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4919 if (num_reported != 1) { /* The number should be 1 */
4920 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4924 /* Parse the switch configuration elements */
4925 element = &(switch_config->element[0]);
4926 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4927 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4928 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4930 PMD_DRV_LOG(INFO, "Unknown element type");
4933 rte_free(switch_config);
4939 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4942 struct pool_entry *entry;
4944 if (pool == NULL || num == 0)
4947 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4948 if (entry == NULL) {
4949 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4953 /* queue heap initialize */
4954 pool->num_free = num;
4955 pool->num_alloc = 0;
4957 LIST_INIT(&pool->alloc_list);
4958 LIST_INIT(&pool->free_list);
4960 /* Initialize element */
4964 LIST_INSERT_HEAD(&pool->free_list, entry, next);
4969 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4971 struct pool_entry *entry, *next_entry;
4976 for (entry = LIST_FIRST(&pool->alloc_list);
4977 entry && (next_entry = LIST_NEXT(entry, next), 1);
4978 entry = next_entry) {
4979 LIST_REMOVE(entry, next);
4983 for (entry = LIST_FIRST(&pool->free_list);
4984 entry && (next_entry = LIST_NEXT(entry, next), 1);
4985 entry = next_entry) {
4986 LIST_REMOVE(entry, next);
4991 pool->num_alloc = 0;
4993 LIST_INIT(&pool->alloc_list);
4994 LIST_INIT(&pool->free_list);
4998 i40e_res_pool_free(struct i40e_res_pool_info *pool,
5001 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
5002 uint32_t pool_offset;
5007 PMD_DRV_LOG(ERR, "Invalid parameter");
5011 pool_offset = base - pool->base;
5012 /* Lookup in alloc list */
5013 LIST_FOREACH(entry, &pool->alloc_list, next) {
5014 if (entry->base == pool_offset) {
5015 valid_entry = entry;
5016 LIST_REMOVE(entry, next);
5021 /* Not find, return */
5022 if (valid_entry == NULL) {
5023 PMD_DRV_LOG(ERR, "Failed to find entry");
5028 * Found it, move it to free list and try to merge.
5029 * In order to make merge easier, always sort it by qbase.
5030 * Find adjacent prev and last entries.
5033 LIST_FOREACH(entry, &pool->free_list, next) {
5034 if (entry->base > valid_entry->base) {
5042 len = valid_entry->len;
5043 /* Try to merge with next one*/
5045 /* Merge with next one */
5046 if (valid_entry->base + len == next->base) {
5047 next->base = valid_entry->base;
5049 rte_free(valid_entry);
5056 /* Merge with previous one */
5057 if (prev->base + prev->len == valid_entry->base) {
5059 /* If it merge with next one, remove next node */
5061 LIST_REMOVE(valid_entry, next);
5062 rte_free(valid_entry);
5065 rte_free(valid_entry);
5072 /* Not find any entry to merge, insert */
5075 LIST_INSERT_AFTER(prev, valid_entry, next);
5076 else if (next != NULL)
5077 LIST_INSERT_BEFORE(next, valid_entry, next);
5078 else /* It's empty list, insert to head */
5079 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
5082 pool->num_free += len;
5083 pool->num_alloc -= len;
5089 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
5092 struct pool_entry *entry, *valid_entry;
5094 if (pool == NULL || num == 0) {
5095 PMD_DRV_LOG(ERR, "Invalid parameter");
5099 if (pool->num_free < num) {
5100 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
5101 num, pool->num_free);
5106 /* Lookup in free list and find most fit one */
5107 LIST_FOREACH(entry, &pool->free_list, next) {
5108 if (entry->len >= num) {
5110 if (entry->len == num) {
5111 valid_entry = entry;
5114 if (valid_entry == NULL || valid_entry->len > entry->len)
5115 valid_entry = entry;
5119 /* Not find one to satisfy the request, return */
5120 if (valid_entry == NULL) {
5121 PMD_DRV_LOG(ERR, "No valid entry found");
5125 * The entry have equal queue number as requested,
5126 * remove it from alloc_list.
5128 if (valid_entry->len == num) {
5129 LIST_REMOVE(valid_entry, next);
5132 * The entry have more numbers than requested,
5133 * create a new entry for alloc_list and minus its
5134 * queue base and number in free_list.
5136 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
5137 if (entry == NULL) {
5139 "Failed to allocate memory for resource pool");
5142 entry->base = valid_entry->base;
5144 valid_entry->base += num;
5145 valid_entry->len -= num;
5146 valid_entry = entry;
5149 /* Insert it into alloc list, not sorted */
5150 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
5152 pool->num_free -= valid_entry->len;
5153 pool->num_alloc += valid_entry->len;
5155 return valid_entry->base + pool->base;
5159 * bitmap_is_subset - Check whether src2 is subset of src1
5162 bitmap_is_subset(uint8_t src1, uint8_t src2)
5164 return !((src1 ^ src2) & src2);
5167 static enum i40e_status_code
5168 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5170 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5172 /* If DCB is not supported, only default TC is supported */
5173 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
5174 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
5175 return I40E_NOT_SUPPORTED;
5178 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
5180 "Enabled TC map 0x%x not applicable to HW support 0x%x",
5181 hw->func_caps.enabled_tcmap, enabled_tcmap);
5182 return I40E_NOT_SUPPORTED;
5184 return I40E_SUCCESS;
5188 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
5189 struct i40e_vsi_vlan_pvid_info *info)
5192 struct i40e_vsi_context ctxt;
5193 uint8_t vlan_flags = 0;
5196 if (vsi == NULL || info == NULL) {
5197 PMD_DRV_LOG(ERR, "invalid parameters");
5198 return I40E_ERR_PARAM;
5202 vsi->info.pvid = info->config.pvid;
5204 * If insert pvid is enabled, only tagged pkts are
5205 * allowed to be sent out.
5207 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
5208 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5211 if (info->config.reject.tagged == 0)
5212 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5214 if (info->config.reject.untagged == 0)
5215 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
5217 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
5218 I40E_AQ_VSI_PVLAN_MODE_MASK);
5219 vsi->info.port_vlan_flags |= vlan_flags;
5220 vsi->info.valid_sections =
5221 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5222 memset(&ctxt, 0, sizeof(ctxt));
5223 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5224 ctxt.seid = vsi->seid;
5226 hw = I40E_VSI_TO_HW(vsi);
5227 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5228 if (ret != I40E_SUCCESS)
5229 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5235 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5237 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5239 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
5241 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5242 if (ret != I40E_SUCCESS)
5246 PMD_DRV_LOG(ERR, "seid not valid");
5250 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
5251 tc_bw_data.tc_valid_bits = enabled_tcmap;
5252 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5253 tc_bw_data.tc_bw_credits[i] =
5254 (enabled_tcmap & (1 << i)) ? 1 : 0;
5256 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5257 if (ret != I40E_SUCCESS) {
5258 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5262 rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5263 sizeof(vsi->info.qs_handle));
5264 return I40E_SUCCESS;
5267 static enum i40e_status_code
5268 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5269 struct i40e_aqc_vsi_properties_data *info,
5270 uint8_t enabled_tcmap)
5272 enum i40e_status_code ret;
5273 int i, total_tc = 0;
5274 uint16_t qpnum_per_tc, bsf, qp_idx;
5276 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5277 if (ret != I40E_SUCCESS)
5280 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5281 if (enabled_tcmap & (1 << i))
5285 vsi->enabled_tc = enabled_tcmap;
5287 /* Number of queues per enabled TC */
5288 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5289 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5290 bsf = rte_bsf32(qpnum_per_tc);
5292 /* Adjust the queue number to actual queues that can be applied */
5293 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5294 vsi->nb_qps = qpnum_per_tc * total_tc;
5297 * Configure TC and queue mapping parameters, for enabled TC,
5298 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5299 * default queue will serve it.
5302 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5303 if (vsi->enabled_tc & (1 << i)) {
5304 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5305 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5306 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5307 qp_idx += qpnum_per_tc;
5309 info->tc_mapping[i] = 0;
5312 /* Associate queue number with VSI */
5313 if (vsi->type == I40E_VSI_SRIOV) {
5314 info->mapping_flags |=
5315 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5316 for (i = 0; i < vsi->nb_qps; i++)
5317 info->queue_mapping[i] =
5318 rte_cpu_to_le_16(vsi->base_queue + i);
5320 info->mapping_flags |=
5321 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5322 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5324 info->valid_sections |=
5325 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5327 return I40E_SUCCESS;
5331 i40e_veb_release(struct i40e_veb *veb)
5333 struct i40e_vsi *vsi;
5339 if (!TAILQ_EMPTY(&veb->head)) {
5340 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5343 /* associate_vsi field is NULL for floating VEB */
5344 if (veb->associate_vsi != NULL) {
5345 vsi = veb->associate_vsi;
5346 hw = I40E_VSI_TO_HW(vsi);
5348 vsi->uplink_seid = veb->uplink_seid;
5351 veb->associate_pf->main_vsi->floating_veb = NULL;
5352 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5355 i40e_aq_delete_element(hw, veb->seid, NULL);
5357 return I40E_SUCCESS;
5361 static struct i40e_veb *
5362 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5364 struct i40e_veb *veb;
5370 "veb setup failed, associated PF shouldn't null");
5373 hw = I40E_PF_TO_HW(pf);
5375 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5377 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5381 veb->associate_vsi = vsi;
5382 veb->associate_pf = pf;
5383 TAILQ_INIT(&veb->head);
5384 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5386 /* create floating veb if vsi is NULL */
5388 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5389 I40E_DEFAULT_TCMAP, false,
5390 &veb->seid, false, NULL);
5392 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5393 true, &veb->seid, false, NULL);
5396 if (ret != I40E_SUCCESS) {
5397 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5398 hw->aq.asq_last_status);
5401 veb->enabled_tc = I40E_DEFAULT_TCMAP;
5403 /* get statistics index */
5404 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5405 &veb->stats_idx, NULL, NULL, NULL);
5406 if (ret != I40E_SUCCESS) {
5407 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5408 hw->aq.asq_last_status);
5411 /* Get VEB bandwidth, to be implemented */
5412 /* Now associated vsi binding to the VEB, set uplink to this VEB */
5414 vsi->uplink_seid = veb->seid;
5423 i40e_vsi_release(struct i40e_vsi *vsi)
5427 struct i40e_vsi_list *vsi_list;
5430 struct i40e_mac_filter *f;
5431 uint16_t user_param;
5434 return I40E_SUCCESS;
5439 user_param = vsi->user_param;
5441 pf = I40E_VSI_TO_PF(vsi);
5442 hw = I40E_VSI_TO_HW(vsi);
5444 /* VSI has child to attach, release child first */
5446 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5447 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5450 i40e_veb_release(vsi->veb);
5453 if (vsi->floating_veb) {
5454 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5455 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5460 /* Remove all macvlan filters of the VSI */
5461 i40e_vsi_remove_all_macvlan_filter(vsi);
5462 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5465 if (vsi->type != I40E_VSI_MAIN &&
5466 ((vsi->type != I40E_VSI_SRIOV) ||
5467 !pf->floating_veb_list[user_param])) {
5468 /* Remove vsi from parent's sibling list */
5469 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5470 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5471 return I40E_ERR_PARAM;
5473 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5474 &vsi->sib_vsi_list, list);
5476 /* Remove all switch element of the VSI */
5477 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5478 if (ret != I40E_SUCCESS)
5479 PMD_DRV_LOG(ERR, "Failed to delete element");
5482 if ((vsi->type == I40E_VSI_SRIOV) &&
5483 pf->floating_veb_list[user_param]) {
5484 /* Remove vsi from parent's sibling list */
5485 if (vsi->parent_vsi == NULL ||
5486 vsi->parent_vsi->floating_veb == NULL) {
5487 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5488 return I40E_ERR_PARAM;
5490 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5491 &vsi->sib_vsi_list, list);
5493 /* Remove all switch element of the VSI */
5494 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5495 if (ret != I40E_SUCCESS)
5496 PMD_DRV_LOG(ERR, "Failed to delete element");
5499 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5501 if (vsi->type != I40E_VSI_SRIOV)
5502 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5505 return I40E_SUCCESS;
5509 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5511 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5512 struct i40e_aqc_remove_macvlan_element_data def_filter;
5513 struct i40e_mac_filter_info filter;
5516 if (vsi->type != I40E_VSI_MAIN)
5517 return I40E_ERR_CONFIG;
5518 memset(&def_filter, 0, sizeof(def_filter));
5519 rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5521 def_filter.vlan_tag = 0;
5522 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5523 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5524 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5525 if (ret != I40E_SUCCESS) {
5526 struct i40e_mac_filter *f;
5527 struct rte_ether_addr *mac;
5530 "Cannot remove the default macvlan filter");
5531 /* It needs to add the permanent mac into mac list */
5532 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5534 PMD_DRV_LOG(ERR, "failed to allocate memory");
5535 return I40E_ERR_NO_MEMORY;
5537 mac = &f->mac_info.mac_addr;
5538 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5540 f->mac_info.filter_type = I40E_MACVLAN_PERFECT_MATCH;
5541 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5546 rte_memcpy(&filter.mac_addr,
5547 (struct rte_ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5548 filter.filter_type = I40E_MACVLAN_PERFECT_MATCH;
5549 return i40e_vsi_add_mac(vsi, &filter);
5553 * i40e_vsi_get_bw_config - Query VSI BW Information
5554 * @vsi: the VSI to be queried
5556 * Returns 0 on success, negative value on failure
5558 static enum i40e_status_code
5559 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5561 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5562 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5563 struct i40e_hw *hw = &vsi->adapter->hw;
5568 memset(&bw_config, 0, sizeof(bw_config));
5569 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5570 if (ret != I40E_SUCCESS) {
5571 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5572 hw->aq.asq_last_status);
5576 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5577 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5578 &ets_sla_config, NULL);
5579 if (ret != I40E_SUCCESS) {
5581 "VSI failed to get TC bandwdith configuration %u",
5582 hw->aq.asq_last_status);
5586 /* store and print out BW info */
5587 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5588 vsi->bw_info.bw_max = bw_config.max_bw;
5589 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5590 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5591 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5592 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5594 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5595 vsi->bw_info.bw_ets_share_credits[i] =
5596 ets_sla_config.share_credits[i];
5597 vsi->bw_info.bw_ets_credits[i] =
5598 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5599 /* 4 bits per TC, 4th bit is reserved */
5600 vsi->bw_info.bw_ets_max[i] =
5601 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5602 RTE_LEN2MASK(3, uint8_t));
5603 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5604 vsi->bw_info.bw_ets_share_credits[i]);
5605 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5606 vsi->bw_info.bw_ets_credits[i]);
5607 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5608 vsi->bw_info.bw_ets_max[i]);
5611 return I40E_SUCCESS;
5614 /* i40e_enable_pf_lb
5615 * @pf: pointer to the pf structure
5617 * allow loopback on pf
5620 i40e_enable_pf_lb(struct i40e_pf *pf)
5622 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5623 struct i40e_vsi_context ctxt;
5626 /* Use the FW API if FW >= v5.0 */
5627 if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
5628 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5632 memset(&ctxt, 0, sizeof(ctxt));
5633 ctxt.seid = pf->main_vsi_seid;
5634 ctxt.pf_num = hw->pf_id;
5635 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5637 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5638 ret, hw->aq.asq_last_status);
5641 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5642 ctxt.info.valid_sections =
5643 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5644 ctxt.info.switch_id |=
5645 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5647 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5649 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5650 hw->aq.asq_last_status);
5655 i40e_vsi_setup(struct i40e_pf *pf,
5656 enum i40e_vsi_type type,
5657 struct i40e_vsi *uplink_vsi,
5658 uint16_t user_param)
5660 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5661 struct i40e_vsi *vsi;
5662 struct i40e_mac_filter_info filter;
5664 struct i40e_vsi_context ctxt;
5665 struct rte_ether_addr broadcast =
5666 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5668 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5669 uplink_vsi == NULL) {
5671 "VSI setup failed, VSI link shouldn't be NULL");
5675 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5677 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5682 * 1.type is not MAIN and uplink vsi is not NULL
5683 * If uplink vsi didn't setup VEB, create one first under veb field
5684 * 2.type is SRIOV and the uplink is NULL
5685 * If floating VEB is NULL, create one veb under floating veb field
5688 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5689 uplink_vsi->veb == NULL) {
5690 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5692 if (uplink_vsi->veb == NULL) {
5693 PMD_DRV_LOG(ERR, "VEB setup failed");
5696 /* set ALLOWLOOPBACk on pf, when veb is created */
5697 i40e_enable_pf_lb(pf);
5700 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5701 pf->main_vsi->floating_veb == NULL) {
5702 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5704 if (pf->main_vsi->floating_veb == NULL) {
5705 PMD_DRV_LOG(ERR, "VEB setup failed");
5710 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5712 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5715 TAILQ_INIT(&vsi->mac_list);
5717 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5718 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5719 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5720 vsi->user_param = user_param;
5721 vsi->vlan_anti_spoof_on = 0;
5722 vsi->vlan_filter_on = 0;
5723 /* Allocate queues */
5724 switch (vsi->type) {
5725 case I40E_VSI_MAIN :
5726 vsi->nb_qps = pf->lan_nb_qps;
5728 case I40E_VSI_SRIOV :
5729 vsi->nb_qps = pf->vf_nb_qps;
5731 case I40E_VSI_VMDQ2:
5732 vsi->nb_qps = pf->vmdq_nb_qps;
5735 vsi->nb_qps = pf->fdir_nb_qps;
5741 * The filter status descriptor is reported in rx queue 0,
5742 * while the tx queue for fdir filter programming has no
5743 * such constraints, can be non-zero queues.
5744 * To simplify it, choose FDIR vsi use queue 0 pair.
5745 * To make sure it will use queue 0 pair, queue allocation
5746 * need be done before this function is called
5748 if (type != I40E_VSI_FDIR) {
5749 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5751 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5755 vsi->base_queue = ret;
5757 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5759 /* VF has MSIX interrupt in VF range, don't allocate here */
5760 if (type == I40E_VSI_MAIN) {
5761 if (pf->support_multi_driver) {
5762 /* If support multi-driver, need to use INT0 instead of
5763 * allocating from msix pool. The Msix pool is init from
5764 * INT1, so it's OK just set msix_intr to 0 and nb_msix
5765 * to 1 without calling i40e_res_pool_alloc.
5770 ret = i40e_res_pool_alloc(&pf->msix_pool,
5771 RTE_MIN(vsi->nb_qps,
5772 RTE_MAX_RXTX_INTR_VEC_ID));
5775 "VSI MAIN %d get heap failed %d",
5777 goto fail_queue_alloc;
5779 vsi->msix_intr = ret;
5780 vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5781 RTE_MAX_RXTX_INTR_VEC_ID);
5783 } else if (type != I40E_VSI_SRIOV) {
5784 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5786 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5787 if (type != I40E_VSI_FDIR)
5788 goto fail_queue_alloc;
5792 vsi->msix_intr = ret;
5801 if (type == I40E_VSI_MAIN) {
5802 /* For main VSI, no need to add since it's default one */
5803 vsi->uplink_seid = pf->mac_seid;
5804 vsi->seid = pf->main_vsi_seid;
5805 /* Bind queues with specific MSIX interrupt */
5807 * Needs 2 interrupt at least, one for misc cause which will
5808 * enabled from OS side, Another for queues binding the
5809 * interrupt from device side only.
5812 /* Get default VSI parameters from hardware */
5813 memset(&ctxt, 0, sizeof(ctxt));
5814 ctxt.seid = vsi->seid;
5815 ctxt.pf_num = hw->pf_id;
5816 ctxt.uplink_seid = vsi->uplink_seid;
5818 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5819 if (ret != I40E_SUCCESS) {
5820 PMD_DRV_LOG(ERR, "Failed to get VSI params");
5821 goto fail_msix_alloc;
5823 rte_memcpy(&vsi->info, &ctxt.info,
5824 sizeof(struct i40e_aqc_vsi_properties_data));
5825 vsi->vsi_id = ctxt.vsi_number;
5826 vsi->info.valid_sections = 0;
5828 /* Configure tc, enabled TC0 only */
5829 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5831 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5832 goto fail_msix_alloc;
5835 /* TC, queue mapping */
5836 memset(&ctxt, 0, sizeof(ctxt));
5837 vsi->info.valid_sections |=
5838 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5839 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5840 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5841 rte_memcpy(&ctxt.info, &vsi->info,
5842 sizeof(struct i40e_aqc_vsi_properties_data));
5843 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5844 I40E_DEFAULT_TCMAP);
5845 if (ret != I40E_SUCCESS) {
5847 "Failed to configure TC queue mapping");
5848 goto fail_msix_alloc;
5850 ctxt.seid = vsi->seid;
5851 ctxt.pf_num = hw->pf_id;
5852 ctxt.uplink_seid = vsi->uplink_seid;
5855 /* Update VSI parameters */
5856 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5857 if (ret != I40E_SUCCESS) {
5858 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5859 goto fail_msix_alloc;
5862 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5863 sizeof(vsi->info.tc_mapping));
5864 rte_memcpy(&vsi->info.queue_mapping,
5865 &ctxt.info.queue_mapping,
5866 sizeof(vsi->info.queue_mapping));
5867 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5868 vsi->info.valid_sections = 0;
5870 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5874 * Updating default filter settings are necessary to prevent
5875 * reception of tagged packets.
5876 * Some old firmware configurations load a default macvlan
5877 * filter which accepts both tagged and untagged packets.
5878 * The updating is to use a normal filter instead if needed.
5879 * For NVM 4.2.2 or after, the updating is not needed anymore.
5880 * The firmware with correct configurations load the default
5881 * macvlan filter which is expected and cannot be removed.
5883 i40e_update_default_filter_setting(vsi);
5884 i40e_config_qinq(hw, vsi);
5885 } else if (type == I40E_VSI_SRIOV) {
5886 memset(&ctxt, 0, sizeof(ctxt));
5888 * For other VSI, the uplink_seid equals to uplink VSI's
5889 * uplink_seid since they share same VEB
5891 if (uplink_vsi == NULL)
5892 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5894 vsi->uplink_seid = uplink_vsi->uplink_seid;
5895 ctxt.pf_num = hw->pf_id;
5896 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5897 ctxt.uplink_seid = vsi->uplink_seid;
5898 ctxt.connection_type = 0x1;
5899 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5901 /* Use the VEB configuration if FW >= v5.0 */
5902 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
5903 /* Configure switch ID */
5904 ctxt.info.valid_sections |=
5905 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5906 ctxt.info.switch_id =
5907 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5910 /* Configure port/vlan */
5911 ctxt.info.valid_sections |=
5912 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5913 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5914 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5915 hw->func_caps.enabled_tcmap);
5916 if (ret != I40E_SUCCESS) {
5918 "Failed to configure TC queue mapping");
5919 goto fail_msix_alloc;
5922 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5923 ctxt.info.valid_sections |=
5924 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5926 * Since VSI is not created yet, only configure parameter,
5927 * will add vsi below.
5930 i40e_config_qinq(hw, vsi);
5931 } else if (type == I40E_VSI_VMDQ2) {
5932 memset(&ctxt, 0, sizeof(ctxt));
5934 * For other VSI, the uplink_seid equals to uplink VSI's
5935 * uplink_seid since they share same VEB
5937 vsi->uplink_seid = uplink_vsi->uplink_seid;
5938 ctxt.pf_num = hw->pf_id;
5940 ctxt.uplink_seid = vsi->uplink_seid;
5941 ctxt.connection_type = 0x1;
5942 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5944 ctxt.info.valid_sections |=
5945 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5946 /* user_param carries flag to enable loop back */
5948 ctxt.info.switch_id =
5949 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5950 ctxt.info.switch_id |=
5951 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5954 /* Configure port/vlan */
5955 ctxt.info.valid_sections |=
5956 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5957 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5958 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5959 I40E_DEFAULT_TCMAP);
5960 if (ret != I40E_SUCCESS) {
5962 "Failed to configure TC queue mapping");
5963 goto fail_msix_alloc;
5965 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5966 ctxt.info.valid_sections |=
5967 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5968 } else if (type == I40E_VSI_FDIR) {
5969 memset(&ctxt, 0, sizeof(ctxt));
5970 vsi->uplink_seid = uplink_vsi->uplink_seid;
5971 ctxt.pf_num = hw->pf_id;
5973 ctxt.uplink_seid = vsi->uplink_seid;
5974 ctxt.connection_type = 0x1; /* regular data port */
5975 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5976 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5977 I40E_DEFAULT_TCMAP);
5978 if (ret != I40E_SUCCESS) {
5980 "Failed to configure TC queue mapping.");
5981 goto fail_msix_alloc;
5983 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5984 ctxt.info.valid_sections |=
5985 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5987 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5988 goto fail_msix_alloc;
5991 if (vsi->type != I40E_VSI_MAIN) {
5992 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5993 if (ret != I40E_SUCCESS) {
5994 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5995 hw->aq.asq_last_status);
5996 goto fail_msix_alloc;
5998 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5999 vsi->info.valid_sections = 0;
6000 vsi->seid = ctxt.seid;
6001 vsi->vsi_id = ctxt.vsi_number;
6002 vsi->sib_vsi_list.vsi = vsi;
6003 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
6004 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
6005 &vsi->sib_vsi_list, list);
6007 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
6008 &vsi->sib_vsi_list, list);
6012 /* MAC/VLAN configuration */
6013 rte_memcpy(&filter.mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
6014 filter.filter_type = I40E_MACVLAN_PERFECT_MATCH;
6016 ret = i40e_vsi_add_mac(vsi, &filter);
6017 if (ret != I40E_SUCCESS) {
6018 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
6019 goto fail_msix_alloc;
6022 /* Get VSI BW information */
6023 i40e_vsi_get_bw_config(vsi);
6026 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
6028 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
6034 /* Configure vlan filter on or off */
6036 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
6039 struct i40e_mac_filter *f;
6041 struct i40e_mac_filter_info *mac_filter;
6042 enum i40e_mac_filter_type desired_filter;
6043 int ret = I40E_SUCCESS;
6046 /* Filter to match MAC and VLAN */
6047 desired_filter = I40E_MACVLAN_PERFECT_MATCH;
6049 /* Filter to match only MAC */
6050 desired_filter = I40E_MAC_PERFECT_MATCH;
6055 mac_filter = rte_zmalloc("mac_filter_info_data",
6056 num * sizeof(*mac_filter), 0);
6057 if (mac_filter == NULL) {
6058 PMD_DRV_LOG(ERR, "failed to allocate memory");
6059 return I40E_ERR_NO_MEMORY;
6064 /* Remove all existing mac */
6065 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
6066 mac_filter[i] = f->mac_info;
6067 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
6069 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6070 on ? "enable" : "disable");
6076 /* Override with new filter */
6077 for (i = 0; i < num; i++) {
6078 mac_filter[i].filter_type = desired_filter;
6079 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
6081 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6082 on ? "enable" : "disable");
6088 rte_free(mac_filter);
6092 /* Configure vlan stripping on or off */
6094 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
6096 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6097 struct i40e_vsi_context ctxt;
6099 int ret = I40E_SUCCESS;
6101 /* Check if it has been already on or off */
6102 if (vsi->info.valid_sections &
6103 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
6105 if ((vsi->info.port_vlan_flags &
6106 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
6107 return 0; /* already on */
6109 if ((vsi->info.port_vlan_flags &
6110 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
6111 I40E_AQ_VSI_PVLAN_EMOD_MASK)
6112 return 0; /* already off */
6117 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
6119 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
6120 vsi->info.valid_sections =
6121 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
6122 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
6123 vsi->info.port_vlan_flags |= vlan_flags;
6124 ctxt.seid = vsi->seid;
6125 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
6126 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6128 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
6129 on ? "enable" : "disable");
6135 i40e_dev_init_vlan(struct rte_eth_dev *dev)
6137 struct rte_eth_dev_data *data = dev->data;
6141 /* Apply vlan offload setting */
6142 mask = ETH_VLAN_STRIP_MASK |
6143 ETH_QINQ_STRIP_MASK |
6144 ETH_VLAN_FILTER_MASK |
6145 ETH_VLAN_EXTEND_MASK;
6146 ret = i40e_vlan_offload_set(dev, mask);
6148 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
6152 /* Apply pvid setting */
6153 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
6154 data->dev_conf.txmode.hw_vlan_insert_pvid);
6156 PMD_DRV_LOG(INFO, "Failed to update VSI params");
6162 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
6164 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6166 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
6170 i40e_update_flow_control(struct i40e_hw *hw)
6172 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
6173 struct i40e_link_status link_status;
6174 uint32_t rxfc = 0, txfc = 0, reg;
6178 memset(&link_status, 0, sizeof(link_status));
6179 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
6180 if (ret != I40E_SUCCESS) {
6181 PMD_DRV_LOG(ERR, "Failed to get link status information");
6182 goto write_reg; /* Disable flow control */
6185 an_info = hw->phy.link_info.an_info;
6186 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
6187 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
6188 ret = I40E_ERR_NOT_READY;
6189 goto write_reg; /* Disable flow control */
6192 * If link auto negotiation is enabled, flow control needs to
6193 * be configured according to it
6195 switch (an_info & I40E_LINK_PAUSE_RXTX) {
6196 case I40E_LINK_PAUSE_RXTX:
6199 hw->fc.current_mode = I40E_FC_FULL;
6201 case I40E_AQ_LINK_PAUSE_RX:
6203 hw->fc.current_mode = I40E_FC_RX_PAUSE;
6205 case I40E_AQ_LINK_PAUSE_TX:
6207 hw->fc.current_mode = I40E_FC_TX_PAUSE;
6210 hw->fc.current_mode = I40E_FC_NONE;
6215 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
6216 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
6217 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
6218 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
6219 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
6220 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
6227 i40e_pf_setup(struct i40e_pf *pf)
6229 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6230 struct i40e_filter_control_settings settings;
6231 struct i40e_vsi *vsi;
6234 /* Clear all stats counters */
6235 pf->offset_loaded = FALSE;
6236 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
6237 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
6238 memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
6239 memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
6241 ret = i40e_pf_get_switch_config(pf);
6242 if (ret != I40E_SUCCESS) {
6243 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
6247 ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
6249 PMD_INIT_LOG(WARNING,
6250 "failed to allocate switch domain for device %d", ret);
6252 if (pf->flags & I40E_FLAG_FDIR) {
6253 /* make queue allocated first, let FDIR use queue pair 0*/
6254 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
6255 if (ret != I40E_FDIR_QUEUE_ID) {
6257 "queue allocation fails for FDIR: ret =%d",
6259 pf->flags &= ~I40E_FLAG_FDIR;
6262 /* main VSI setup */
6263 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6265 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6266 return I40E_ERR_NOT_READY;
6270 /* Configure filter control */
6271 memset(&settings, 0, sizeof(settings));
6272 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
6273 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6274 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
6275 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6277 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6278 hw->func_caps.rss_table_size);
6279 return I40E_ERR_PARAM;
6281 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6282 hw->func_caps.rss_table_size);
6283 pf->hash_lut_size = hw->func_caps.rss_table_size;
6285 /* Enable ethtype and macvlan filters */
6286 settings.enable_ethtype = TRUE;
6287 settings.enable_macvlan = TRUE;
6288 ret = i40e_set_filter_control(hw, &settings);
6290 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6293 /* Update flow control according to the auto negotiation */
6294 i40e_update_flow_control(hw);
6296 return I40E_SUCCESS;
6300 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6306 * Set or clear TX Queue Disable flags,
6307 * which is required by hardware.
6309 i40e_pre_tx_queue_cfg(hw, q_idx, on);
6310 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6312 /* Wait until the request is finished */
6313 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6314 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6315 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6316 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6317 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6323 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6324 return I40E_SUCCESS; /* already on, skip next steps */
6326 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6327 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6329 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6330 return I40E_SUCCESS; /* already off, skip next steps */
6331 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6333 /* Write the register */
6334 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6335 /* Check the result */
6336 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6337 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6338 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6340 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6341 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6344 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6345 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6349 /* Check if it is timeout */
6350 if (j >= I40E_CHK_Q_ENA_COUNT) {
6351 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6352 (on ? "enable" : "disable"), q_idx);
6353 return I40E_ERR_TIMEOUT;
6356 return I40E_SUCCESS;
6360 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6365 /* Wait until the request is finished */
6366 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6367 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6368 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6369 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6370 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6375 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6376 return I40E_SUCCESS; /* Already on, skip next steps */
6377 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6379 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6380 return I40E_SUCCESS; /* Already off, skip next steps */
6381 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6384 /* Write the register */
6385 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6386 /* Check the result */
6387 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6388 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6389 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6391 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6392 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6395 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6396 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6401 /* Check if it is timeout */
6402 if (j >= I40E_CHK_Q_ENA_COUNT) {
6403 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6404 (on ? "enable" : "disable"), q_idx);
6405 return I40E_ERR_TIMEOUT;
6408 return I40E_SUCCESS;
6411 /* Initialize VSI for TX */
6413 i40e_dev_tx_init(struct i40e_pf *pf)
6415 struct rte_eth_dev_data *data = pf->dev_data;
6417 uint32_t ret = I40E_SUCCESS;
6418 struct i40e_tx_queue *txq;
6420 for (i = 0; i < data->nb_tx_queues; i++) {
6421 txq = data->tx_queues[i];
6422 if (!txq || !txq->q_set)
6424 ret = i40e_tx_queue_init(txq);
6425 if (ret != I40E_SUCCESS)
6428 if (ret == I40E_SUCCESS)
6429 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6435 /* Initialize VSI for RX */
6437 i40e_dev_rx_init(struct i40e_pf *pf)
6439 struct rte_eth_dev_data *data = pf->dev_data;
6440 int ret = I40E_SUCCESS;
6442 struct i40e_rx_queue *rxq;
6444 i40e_pf_config_rss(pf);
6445 for (i = 0; i < data->nb_rx_queues; i++) {
6446 rxq = data->rx_queues[i];
6447 if (!rxq || !rxq->q_set)
6450 ret = i40e_rx_queue_init(rxq);
6451 if (ret != I40E_SUCCESS) {
6453 "Failed to do RX queue initialization");
6457 if (ret == I40E_SUCCESS)
6458 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6465 i40e_dev_rxtx_init(struct i40e_pf *pf)
6469 err = i40e_dev_tx_init(pf);
6471 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6474 err = i40e_dev_rx_init(pf);
6476 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6484 i40e_vmdq_setup(struct rte_eth_dev *dev)
6486 struct rte_eth_conf *conf = &dev->data->dev_conf;
6487 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6488 int i, err, conf_vsis, j, loop;
6489 struct i40e_vsi *vsi;
6490 struct i40e_vmdq_info *vmdq_info;
6491 struct rte_eth_vmdq_rx_conf *vmdq_conf;
6492 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6495 * Disable interrupt to avoid message from VF. Furthermore, it will
6496 * avoid race condition in VSI creation/destroy.
6498 i40e_pf_disable_irq0(hw);
6500 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6501 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6505 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6506 if (conf_vsis > pf->max_nb_vmdq_vsi) {
6507 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6508 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6509 pf->max_nb_vmdq_vsi);
6513 if (pf->vmdq != NULL) {
6514 PMD_INIT_LOG(INFO, "VMDQ already configured");
6518 pf->vmdq = rte_zmalloc("vmdq_info_struct",
6519 sizeof(*vmdq_info) * conf_vsis, 0);
6521 if (pf->vmdq == NULL) {
6522 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6526 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6528 /* Create VMDQ VSI */
6529 for (i = 0; i < conf_vsis; i++) {
6530 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6531 vmdq_conf->enable_loop_back);
6533 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6537 vmdq_info = &pf->vmdq[i];
6539 vmdq_info->vsi = vsi;
6541 pf->nb_cfg_vmdq_vsi = conf_vsis;
6543 /* Configure Vlan */
6544 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6545 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6546 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6547 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6548 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6549 vmdq_conf->pool_map[i].vlan_id, j);
6551 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6552 vmdq_conf->pool_map[i].vlan_id);
6554 PMD_INIT_LOG(ERR, "Failed to add vlan");
6562 i40e_pf_enable_irq0(hw);
6567 for (i = 0; i < conf_vsis; i++)
6568 if (pf->vmdq[i].vsi == NULL)
6571 i40e_vsi_release(pf->vmdq[i].vsi);
6575 i40e_pf_enable_irq0(hw);
6580 i40e_stat_update_32(struct i40e_hw *hw,
6588 new_data = (uint64_t)I40E_READ_REG(hw, reg);
6592 if (new_data >= *offset)
6593 *stat = (uint64_t)(new_data - *offset);
6595 *stat = (uint64_t)((new_data +
6596 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6600 i40e_stat_update_48(struct i40e_hw *hw,
6609 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6610 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6611 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6616 if (new_data >= *offset)
6617 *stat = new_data - *offset;
6619 *stat = (uint64_t)((new_data +
6620 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6622 *stat &= I40E_48_BIT_MASK;
6627 i40e_pf_disable_irq0(struct i40e_hw *hw)
6629 /* Disable all interrupt types */
6630 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6631 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6632 I40E_WRITE_FLUSH(hw);
6637 i40e_pf_enable_irq0(struct i40e_hw *hw)
6639 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6640 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6641 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6642 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6643 I40E_WRITE_FLUSH(hw);
6647 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6649 /* read pending request and disable first */
6650 i40e_pf_disable_irq0(hw);
6651 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6652 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6653 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6656 /* Link no queues with irq0 */
6657 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6658 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6662 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6664 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6665 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6668 uint32_t index, offset, val;
6673 * Try to find which VF trigger a reset, use absolute VF id to access
6674 * since the reg is global register.
6676 for (i = 0; i < pf->vf_num; i++) {
6677 abs_vf_id = hw->func_caps.vf_base_id + i;
6678 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6679 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6680 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6681 /* VFR event occurred */
6682 if (val & (0x1 << offset)) {
6685 /* Clear the event first */
6686 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6688 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6690 * Only notify a VF reset event occurred,
6691 * don't trigger another SW reset
6693 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6694 if (ret != I40E_SUCCESS)
6695 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6701 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6703 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6706 for (i = 0; i < pf->vf_num; i++)
6707 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6711 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6713 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6714 struct i40e_arq_event_info info;
6715 uint16_t pending, opcode;
6718 info.buf_len = I40E_AQ_BUF_SZ;
6719 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6720 if (!info.msg_buf) {
6721 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6727 ret = i40e_clean_arq_element(hw, &info, &pending);
6729 if (ret != I40E_SUCCESS) {
6731 "Failed to read msg from AdminQ, aq_err: %u",
6732 hw->aq.asq_last_status);
6735 opcode = rte_le_to_cpu_16(info.desc.opcode);
6738 case i40e_aqc_opc_send_msg_to_pf:
6739 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6740 i40e_pf_host_handle_vf_msg(dev,
6741 rte_le_to_cpu_16(info.desc.retval),
6742 rte_le_to_cpu_32(info.desc.cookie_high),
6743 rte_le_to_cpu_32(info.desc.cookie_low),
6747 case i40e_aqc_opc_get_link_status:
6748 ret = i40e_dev_link_update(dev, 0);
6750 rte_eth_dev_callback_process(dev,
6751 RTE_ETH_EVENT_INTR_LSC, NULL);
6754 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6759 rte_free(info.msg_buf);
6763 i40e_handle_mdd_event(struct rte_eth_dev *dev)
6765 #define I40E_MDD_CLEAR32 0xFFFFFFFF
6766 #define I40E_MDD_CLEAR16 0xFFFF
6767 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6768 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6769 bool mdd_detected = false;
6770 struct i40e_pf_vf *vf;
6774 /* find what triggered the MDD event */
6775 reg = I40E_READ_REG(hw, I40E_GL_MDET_TX);
6776 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
6777 uint8_t pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6778 I40E_GL_MDET_TX_PF_NUM_SHIFT;
6779 uint16_t vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
6780 I40E_GL_MDET_TX_VF_NUM_SHIFT;
6781 uint8_t event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
6782 I40E_GL_MDET_TX_EVENT_SHIFT;
6783 uint16_t queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6784 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6785 hw->func_caps.base_queue;
6786 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on TX "
6787 "queue %d PF number 0x%02x VF number 0x%02x device %s\n",
6788 event, queue, pf_num, vf_num, dev->data->name);
6789 I40E_WRITE_REG(hw, I40E_GL_MDET_TX, I40E_MDD_CLEAR32);
6790 mdd_detected = true;
6792 reg = I40E_READ_REG(hw, I40E_GL_MDET_RX);
6793 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
6794 uint8_t func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6795 I40E_GL_MDET_RX_FUNCTION_SHIFT;
6796 uint8_t event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
6797 I40E_GL_MDET_RX_EVENT_SHIFT;
6798 uint16_t queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6799 I40E_GL_MDET_RX_QUEUE_SHIFT) -
6800 hw->func_caps.base_queue;
6802 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on RX "
6803 "queue %d of function 0x%02x device %s\n",
6804 event, queue, func, dev->data->name);
6805 I40E_WRITE_REG(hw, I40E_GL_MDET_RX, I40E_MDD_CLEAR32);
6806 mdd_detected = true;
6810 reg = I40E_READ_REG(hw, I40E_PF_MDET_TX);
6811 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
6812 I40E_WRITE_REG(hw, I40E_PF_MDET_TX, I40E_MDD_CLEAR16);
6813 PMD_DRV_LOG(WARNING, "TX driver issue detected on PF\n");
6815 reg = I40E_READ_REG(hw, I40E_PF_MDET_RX);
6816 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
6817 I40E_WRITE_REG(hw, I40E_PF_MDET_RX,
6819 PMD_DRV_LOG(WARNING, "RX driver issue detected on PF\n");
6823 /* see if one of the VFs needs its hand slapped */
6824 for (i = 0; i < pf->vf_num && mdd_detected; i++) {
6826 reg = I40E_READ_REG(hw, I40E_VP_MDET_TX(i));
6827 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
6828 I40E_WRITE_REG(hw, I40E_VP_MDET_TX(i),
6830 vf->num_mdd_events++;
6831 PMD_DRV_LOG(WARNING, "TX driver issue detected on VF %d %-"
6833 i, vf->num_mdd_events);
6836 reg = I40E_READ_REG(hw, I40E_VP_MDET_RX(i));
6837 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
6838 I40E_WRITE_REG(hw, I40E_VP_MDET_RX(i),
6840 vf->num_mdd_events++;
6841 PMD_DRV_LOG(WARNING, "RX driver issue detected on VF %d %-"
6843 i, vf->num_mdd_events);
6849 * Interrupt handler triggered by NIC for handling
6850 * specific interrupt.
6853 * Pointer to interrupt handle.
6855 * The address of parameter (struct rte_eth_dev *) regsitered before.
6861 i40e_dev_interrupt_handler(void *param)
6863 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6864 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6867 /* Disable interrupt */
6868 i40e_pf_disable_irq0(hw);
6870 /* read out interrupt causes */
6871 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6873 /* No interrupt event indicated */
6874 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6875 PMD_DRV_LOG(INFO, "No interrupt event");
6878 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6879 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6880 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
6881 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6882 i40e_handle_mdd_event(dev);
6884 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6885 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6886 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6887 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6888 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6889 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6890 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6891 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6892 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6893 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6895 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6896 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6897 i40e_dev_handle_vfr_event(dev);
6899 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6900 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6901 i40e_dev_handle_aq_msg(dev);
6905 /* Enable interrupt */
6906 i40e_pf_enable_irq0(hw);
6910 i40e_dev_alarm_handler(void *param)
6912 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6913 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6916 /* Disable interrupt */
6917 i40e_pf_disable_irq0(hw);
6919 /* read out interrupt causes */
6920 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6922 /* No interrupt event indicated */
6923 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
6925 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6926 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6927 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
6928 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6929 i40e_handle_mdd_event(dev);
6931 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6932 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6933 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6934 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6935 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6936 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6937 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6938 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6939 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6940 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6942 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6943 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6944 i40e_dev_handle_vfr_event(dev);
6946 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6947 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6948 i40e_dev_handle_aq_msg(dev);
6952 /* Enable interrupt */
6953 i40e_pf_enable_irq0(hw);
6954 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
6955 i40e_dev_alarm_handler, dev);
6959 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6960 struct i40e_macvlan_filter *filter,
6963 int ele_num, ele_buff_size;
6964 int num, actual_num, i;
6966 int ret = I40E_SUCCESS;
6967 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6968 struct i40e_aqc_add_macvlan_element_data *req_list;
6970 if (filter == NULL || total == 0)
6971 return I40E_ERR_PARAM;
6972 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6973 ele_buff_size = hw->aq.asq_buf_size;
6975 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6976 if (req_list == NULL) {
6977 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6978 return I40E_ERR_NO_MEMORY;
6983 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6984 memset(req_list, 0, ele_buff_size);
6986 for (i = 0; i < actual_num; i++) {
6987 rte_memcpy(req_list[i].mac_addr,
6988 &filter[num + i].macaddr, ETH_ADDR_LEN);
6989 req_list[i].vlan_tag =
6990 rte_cpu_to_le_16(filter[num + i].vlan_id);
6992 switch (filter[num + i].filter_type) {
6993 case I40E_MAC_PERFECT_MATCH:
6994 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6995 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6997 case I40E_MACVLAN_PERFECT_MATCH:
6998 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
7000 case I40E_MAC_HASH_MATCH:
7001 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
7002 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
7004 case I40E_MACVLAN_HASH_MATCH:
7005 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
7008 PMD_DRV_LOG(ERR, "Invalid MAC match type");
7009 ret = I40E_ERR_PARAM;
7013 req_list[i].queue_number = 0;
7015 req_list[i].flags = rte_cpu_to_le_16(flags);
7018 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
7020 if (ret != I40E_SUCCESS) {
7021 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
7025 } while (num < total);
7033 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
7034 struct i40e_macvlan_filter *filter,
7037 int ele_num, ele_buff_size;
7038 int num, actual_num, i;
7040 int ret = I40E_SUCCESS;
7041 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7042 struct i40e_aqc_remove_macvlan_element_data *req_list;
7044 if (filter == NULL || total == 0)
7045 return I40E_ERR_PARAM;
7047 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
7048 ele_buff_size = hw->aq.asq_buf_size;
7050 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
7051 if (req_list == NULL) {
7052 PMD_DRV_LOG(ERR, "Fail to allocate memory");
7053 return I40E_ERR_NO_MEMORY;
7058 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
7059 memset(req_list, 0, ele_buff_size);
7061 for (i = 0; i < actual_num; i++) {
7062 rte_memcpy(req_list[i].mac_addr,
7063 &filter[num + i].macaddr, ETH_ADDR_LEN);
7064 req_list[i].vlan_tag =
7065 rte_cpu_to_le_16(filter[num + i].vlan_id);
7067 switch (filter[num + i].filter_type) {
7068 case I40E_MAC_PERFECT_MATCH:
7069 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
7070 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7072 case I40E_MACVLAN_PERFECT_MATCH:
7073 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
7075 case I40E_MAC_HASH_MATCH:
7076 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
7077 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7079 case I40E_MACVLAN_HASH_MATCH:
7080 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
7083 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
7084 ret = I40E_ERR_PARAM;
7087 req_list[i].flags = rte_cpu_to_le_16(flags);
7090 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
7092 if (ret != I40E_SUCCESS) {
7093 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
7097 } while (num < total);
7104 /* Find out specific MAC filter */
7105 static struct i40e_mac_filter *
7106 i40e_find_mac_filter(struct i40e_vsi *vsi,
7107 struct rte_ether_addr *macaddr)
7109 struct i40e_mac_filter *f;
7111 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7112 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
7120 i40e_find_vlan_filter(struct i40e_vsi *vsi,
7123 uint32_t vid_idx, vid_bit;
7125 if (vlan_id > ETH_VLAN_ID_MAX)
7128 vid_idx = I40E_VFTA_IDX(vlan_id);
7129 vid_bit = I40E_VFTA_BIT(vlan_id);
7131 if (vsi->vfta[vid_idx] & vid_bit)
7138 i40e_store_vlan_filter(struct i40e_vsi *vsi,
7139 uint16_t vlan_id, bool on)
7141 uint32_t vid_idx, vid_bit;
7143 vid_idx = I40E_VFTA_IDX(vlan_id);
7144 vid_bit = I40E_VFTA_BIT(vlan_id);
7147 vsi->vfta[vid_idx] |= vid_bit;
7149 vsi->vfta[vid_idx] &= ~vid_bit;
7153 i40e_set_vlan_filter(struct i40e_vsi *vsi,
7154 uint16_t vlan_id, bool on)
7156 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7157 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
7160 if (vlan_id > ETH_VLAN_ID_MAX)
7163 i40e_store_vlan_filter(vsi, vlan_id, on);
7165 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
7168 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
7171 ret = i40e_aq_add_vlan(hw, vsi->seid,
7172 &vlan_data, 1, NULL);
7173 if (ret != I40E_SUCCESS)
7174 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
7176 ret = i40e_aq_remove_vlan(hw, vsi->seid,
7177 &vlan_data, 1, NULL);
7178 if (ret != I40E_SUCCESS)
7180 "Failed to remove vlan filter");
7185 * Find all vlan options for specific mac addr,
7186 * return with actual vlan found.
7189 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
7190 struct i40e_macvlan_filter *mv_f,
7191 int num, struct rte_ether_addr *addr)
7197 * Not to use i40e_find_vlan_filter to decrease the loop time,
7198 * although the code looks complex.
7200 if (num < vsi->vlan_num)
7201 return I40E_ERR_PARAM;
7204 for (j = 0; j < I40E_VFTA_SIZE; j++) {
7206 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
7207 if (vsi->vfta[j] & (1 << k)) {
7210 "vlan number doesn't match");
7211 return I40E_ERR_PARAM;
7213 rte_memcpy(&mv_f[i].macaddr,
7214 addr, ETH_ADDR_LEN);
7216 j * I40E_UINT32_BIT_SIZE + k;
7222 return I40E_SUCCESS;
7226 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
7227 struct i40e_macvlan_filter *mv_f,
7232 struct i40e_mac_filter *f;
7234 if (num < vsi->mac_num)
7235 return I40E_ERR_PARAM;
7237 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7239 PMD_DRV_LOG(ERR, "buffer number not match");
7240 return I40E_ERR_PARAM;
7242 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7244 mv_f[i].vlan_id = vlan;
7245 mv_f[i].filter_type = f->mac_info.filter_type;
7249 return I40E_SUCCESS;
7253 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
7256 struct i40e_mac_filter *f;
7257 struct i40e_macvlan_filter *mv_f;
7258 int ret = I40E_SUCCESS;
7260 if (vsi == NULL || vsi->mac_num == 0)
7261 return I40E_ERR_PARAM;
7263 /* Case that no vlan is set */
7264 if (vsi->vlan_num == 0)
7267 num = vsi->mac_num * vsi->vlan_num;
7269 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7271 PMD_DRV_LOG(ERR, "failed to allocate memory");
7272 return I40E_ERR_NO_MEMORY;
7276 if (vsi->vlan_num == 0) {
7277 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7278 rte_memcpy(&mv_f[i].macaddr,
7279 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7280 mv_f[i].filter_type = f->mac_info.filter_type;
7281 mv_f[i].vlan_id = 0;
7285 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7286 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7287 vsi->vlan_num, &f->mac_info.mac_addr);
7288 if (ret != I40E_SUCCESS)
7290 for (j = i; j < i + vsi->vlan_num; j++)
7291 mv_f[j].filter_type = f->mac_info.filter_type;
7296 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7304 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7306 struct i40e_macvlan_filter *mv_f;
7308 int ret = I40E_SUCCESS;
7310 if (!vsi || vlan > RTE_ETHER_MAX_VLAN_ID)
7311 return I40E_ERR_PARAM;
7313 /* If it's already set, just return */
7314 if (i40e_find_vlan_filter(vsi,vlan))
7315 return I40E_SUCCESS;
7317 mac_num = vsi->mac_num;
7320 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7321 return I40E_ERR_PARAM;
7324 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7327 PMD_DRV_LOG(ERR, "failed to allocate memory");
7328 return I40E_ERR_NO_MEMORY;
7331 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7333 if (ret != I40E_SUCCESS)
7336 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7338 if (ret != I40E_SUCCESS)
7341 i40e_set_vlan_filter(vsi, vlan, 1);
7351 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7353 struct i40e_macvlan_filter *mv_f;
7355 int ret = I40E_SUCCESS;
7358 * Vlan 0 is the generic filter for untagged packets
7359 * and can't be removed.
7361 if (!vsi || vlan == 0 || vlan > RTE_ETHER_MAX_VLAN_ID)
7362 return I40E_ERR_PARAM;
7364 /* If can't find it, just return */
7365 if (!i40e_find_vlan_filter(vsi, vlan))
7366 return I40E_ERR_PARAM;
7368 mac_num = vsi->mac_num;
7371 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7372 return I40E_ERR_PARAM;
7375 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7378 PMD_DRV_LOG(ERR, "failed to allocate memory");
7379 return I40E_ERR_NO_MEMORY;
7382 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7384 if (ret != I40E_SUCCESS)
7387 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7389 if (ret != I40E_SUCCESS)
7392 /* This is last vlan to remove, replace all mac filter with vlan 0 */
7393 if (vsi->vlan_num == 1) {
7394 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7395 if (ret != I40E_SUCCESS)
7398 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7399 if (ret != I40E_SUCCESS)
7403 i40e_set_vlan_filter(vsi, vlan, 0);
7413 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7415 struct i40e_mac_filter *f;
7416 struct i40e_macvlan_filter *mv_f;
7417 int i, vlan_num = 0;
7418 int ret = I40E_SUCCESS;
7420 /* If it's add and we've config it, return */
7421 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7423 return I40E_SUCCESS;
7424 if (mac_filter->filter_type == I40E_MACVLAN_PERFECT_MATCH ||
7425 mac_filter->filter_type == I40E_MACVLAN_HASH_MATCH) {
7428 * If vlan_num is 0, that's the first time to add mac,
7429 * set mask for vlan_id 0.
7431 if (vsi->vlan_num == 0) {
7432 i40e_set_vlan_filter(vsi, 0, 1);
7435 vlan_num = vsi->vlan_num;
7436 } else if (mac_filter->filter_type == I40E_MAC_PERFECT_MATCH ||
7437 mac_filter->filter_type == I40E_MAC_HASH_MATCH)
7440 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7442 PMD_DRV_LOG(ERR, "failed to allocate memory");
7443 return I40E_ERR_NO_MEMORY;
7446 for (i = 0; i < vlan_num; i++) {
7447 mv_f[i].filter_type = mac_filter->filter_type;
7448 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7452 if (mac_filter->filter_type == I40E_MACVLAN_PERFECT_MATCH ||
7453 mac_filter->filter_type == I40E_MACVLAN_HASH_MATCH) {
7454 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7455 &mac_filter->mac_addr);
7456 if (ret != I40E_SUCCESS)
7460 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7461 if (ret != I40E_SUCCESS)
7464 /* Add the mac addr into mac list */
7465 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7467 PMD_DRV_LOG(ERR, "failed to allocate memory");
7468 ret = I40E_ERR_NO_MEMORY;
7471 rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7473 f->mac_info.filter_type = mac_filter->filter_type;
7474 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7485 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr)
7487 struct i40e_mac_filter *f;
7488 struct i40e_macvlan_filter *mv_f;
7490 enum i40e_mac_filter_type filter_type;
7491 int ret = I40E_SUCCESS;
7493 /* Can't find it, return an error */
7494 f = i40e_find_mac_filter(vsi, addr);
7496 return I40E_ERR_PARAM;
7498 vlan_num = vsi->vlan_num;
7499 filter_type = f->mac_info.filter_type;
7500 if (filter_type == I40E_MACVLAN_PERFECT_MATCH ||
7501 filter_type == I40E_MACVLAN_HASH_MATCH) {
7502 if (vlan_num == 0) {
7503 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7504 return I40E_ERR_PARAM;
7506 } else if (filter_type == I40E_MAC_PERFECT_MATCH ||
7507 filter_type == I40E_MAC_HASH_MATCH)
7510 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7512 PMD_DRV_LOG(ERR, "failed to allocate memory");
7513 return I40E_ERR_NO_MEMORY;
7516 for (i = 0; i < vlan_num; i++) {
7517 mv_f[i].filter_type = filter_type;
7518 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7521 if (filter_type == I40E_MACVLAN_PERFECT_MATCH ||
7522 filter_type == I40E_MACVLAN_HASH_MATCH) {
7523 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7524 if (ret != I40E_SUCCESS)
7528 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7529 if (ret != I40E_SUCCESS)
7532 /* Remove the mac addr into mac list */
7533 TAILQ_REMOVE(&vsi->mac_list, f, next);
7543 /* Configure hash enable flags for RSS */
7545 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7553 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7554 if (flags & (1ULL << i))
7555 hena |= adapter->pctypes_tbl[i];
7561 /* Parse the hash enable flags */
7563 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7565 uint64_t rss_hf = 0;
7571 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7572 if (flags & adapter->pctypes_tbl[i])
7573 rss_hf |= (1ULL << i);
7580 i40e_pf_disable_rss(struct i40e_pf *pf)
7582 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7584 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7585 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7586 I40E_WRITE_FLUSH(hw);
7590 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7592 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7593 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7594 uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7595 I40E_VFQF_HKEY_MAX_INDEX :
7596 I40E_PFQF_HKEY_MAX_INDEX;
7599 if (!key || key_len == 0) {
7600 PMD_DRV_LOG(DEBUG, "No key to be configured");
7602 } else if (key_len != (key_idx + 1) *
7604 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7608 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7609 struct i40e_aqc_get_set_rss_key_data *key_dw =
7610 (struct i40e_aqc_get_set_rss_key_data *)key;
7612 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7614 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7616 uint32_t *hash_key = (uint32_t *)key;
7619 if (vsi->type == I40E_VSI_SRIOV) {
7620 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7623 I40E_VFQF_HKEY1(i, vsi->user_param),
7627 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7628 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7631 I40E_WRITE_FLUSH(hw);
7638 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7640 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7641 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7645 if (!key || !key_len)
7648 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7649 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7650 (struct i40e_aqc_get_set_rss_key_data *)key);
7652 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7656 uint32_t *key_dw = (uint32_t *)key;
7659 if (vsi->type == I40E_VSI_SRIOV) {
7660 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7661 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7662 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7664 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7667 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7668 reg = I40E_PFQF_HKEY(i);
7669 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7671 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7679 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7681 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7685 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7686 rss_conf->rss_key_len);
7690 hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7691 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7692 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7693 I40E_WRITE_FLUSH(hw);
7699 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7700 struct rte_eth_rss_conf *rss_conf)
7702 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7703 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7704 uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7707 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7708 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7710 if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7711 if (rss_hf != 0) /* Enable RSS */
7713 return 0; /* Nothing to do */
7716 if (rss_hf == 0) /* Disable RSS */
7719 return i40e_hw_rss_hash_set(pf, rss_conf);
7723 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7724 struct rte_eth_rss_conf *rss_conf)
7726 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7727 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7734 ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7735 &rss_conf->rss_key_len);
7739 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7740 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7741 rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7747 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7749 switch (filter_type) {
7750 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7751 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7753 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7754 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7756 case RTE_TUNNEL_FILTER_IMAC_TENID:
7757 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7759 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7760 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7762 case ETH_TUNNEL_FILTER_IMAC:
7763 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7765 case ETH_TUNNEL_FILTER_OIP:
7766 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7768 case ETH_TUNNEL_FILTER_IIP:
7769 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7772 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7779 /* Convert tunnel filter structure */
7781 i40e_tunnel_filter_convert(
7782 struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7783 struct i40e_tunnel_filter *tunnel_filter)
7785 rte_ether_addr_copy((struct rte_ether_addr *)
7786 &cld_filter->element.outer_mac,
7787 (struct rte_ether_addr *)&tunnel_filter->input.outer_mac);
7788 rte_ether_addr_copy((struct rte_ether_addr *)
7789 &cld_filter->element.inner_mac,
7790 (struct rte_ether_addr *)&tunnel_filter->input.inner_mac);
7791 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7792 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7793 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7794 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7795 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7797 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7798 tunnel_filter->input.flags = cld_filter->element.flags;
7799 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7800 tunnel_filter->queue = cld_filter->element.queue_number;
7801 rte_memcpy(tunnel_filter->input.general_fields,
7802 cld_filter->general_fields,
7803 sizeof(cld_filter->general_fields));
7808 /* Check if there exists the tunnel filter */
7809 struct i40e_tunnel_filter *
7810 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7811 const struct i40e_tunnel_filter_input *input)
7815 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7819 return tunnel_rule->hash_map[ret];
7822 /* Add a tunnel filter into the SW list */
7824 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7825 struct i40e_tunnel_filter *tunnel_filter)
7827 struct i40e_tunnel_rule *rule = &pf->tunnel;
7830 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7833 "Failed to insert tunnel filter to hash table %d!",
7837 rule->hash_map[ret] = tunnel_filter;
7839 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7844 /* Delete a tunnel filter from the SW list */
7846 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7847 struct i40e_tunnel_filter_input *input)
7849 struct i40e_tunnel_rule *rule = &pf->tunnel;
7850 struct i40e_tunnel_filter *tunnel_filter;
7853 ret = rte_hash_del_key(rule->hash_table, input);
7856 "Failed to delete tunnel filter to hash table %d!",
7860 tunnel_filter = rule->hash_map[ret];
7861 rule->hash_map[ret] = NULL;
7863 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7864 rte_free(tunnel_filter);
7870 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7871 struct rte_eth_tunnel_filter_conf *tunnel_filter,
7875 uint32_t ipv4_addr, ipv4_addr_le;
7876 uint8_t i, tun_type = 0;
7877 /* internal varialbe to convert ipv6 byte order */
7878 uint32_t convert_ipv6[4];
7880 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7881 struct i40e_vsi *vsi = pf->main_vsi;
7882 struct i40e_aqc_cloud_filters_element_bb *cld_filter;
7883 struct i40e_aqc_cloud_filters_element_bb *pfilter;
7884 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7885 struct i40e_tunnel_filter *tunnel, *node;
7886 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7888 cld_filter = rte_zmalloc("tunnel_filter",
7889 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7892 if (NULL == cld_filter) {
7893 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7896 pfilter = cld_filter;
7898 rte_ether_addr_copy(&tunnel_filter->outer_mac,
7899 (struct rte_ether_addr *)&pfilter->element.outer_mac);
7900 rte_ether_addr_copy(&tunnel_filter->inner_mac,
7901 (struct rte_ether_addr *)&pfilter->element.inner_mac);
7903 pfilter->element.inner_vlan =
7904 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7905 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7906 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7907 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7908 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7909 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7911 sizeof(pfilter->element.ipaddr.v4.data));
7913 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7914 for (i = 0; i < 4; i++) {
7916 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7918 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7920 sizeof(pfilter->element.ipaddr.v6.data));
7923 /* check tunneled type */
7924 switch (tunnel_filter->tunnel_type) {
7925 case RTE_TUNNEL_TYPE_VXLAN:
7926 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7928 case RTE_TUNNEL_TYPE_NVGRE:
7929 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7931 case RTE_TUNNEL_TYPE_IP_IN_GRE:
7932 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7934 case RTE_TUNNEL_TYPE_VXLAN_GPE:
7935 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE;
7938 /* Other tunnel types is not supported. */
7939 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7940 rte_free(cld_filter);
7944 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7945 &pfilter->element.flags);
7947 rte_free(cld_filter);
7951 pfilter->element.flags |= rte_cpu_to_le_16(
7952 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7953 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7954 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7955 pfilter->element.queue_number =
7956 rte_cpu_to_le_16(tunnel_filter->queue_id);
7958 /* Check if there is the filter in SW list */
7959 memset(&check_filter, 0, sizeof(check_filter));
7960 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7961 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7963 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7964 rte_free(cld_filter);
7968 if (!add && !node) {
7969 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7970 rte_free(cld_filter);
7975 ret = i40e_aq_add_cloud_filters(hw,
7976 vsi->seid, &cld_filter->element, 1);
7978 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7979 rte_free(cld_filter);
7982 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7983 if (tunnel == NULL) {
7984 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7985 rte_free(cld_filter);
7989 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7990 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7994 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
7995 &cld_filter->element, 1);
7997 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7998 rte_free(cld_filter);
8001 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8004 rte_free(cld_filter);
8008 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
8009 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
8010 #define I40E_TR_GENEVE_KEY_MASK 0x8
8011 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
8012 #define I40E_TR_GRE_KEY_MASK 0x400
8013 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
8014 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
8015 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_PORT_TR_WORD0 0x49
8016 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_DIRECTION_WORD0 0x41
8017 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_INGRESS_WORD0 0x80
8018 #define I40E_DIRECTION_INGRESS_KEY 0x8000
8019 #define I40E_TR_L4_TYPE_TCP 0x2
8020 #define I40E_TR_L4_TYPE_UDP 0x4
8021 #define I40E_TR_L4_TYPE_SCTP 0x8
8024 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
8026 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8027 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8028 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8029 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8030 enum i40e_status_code status = I40E_SUCCESS;
8032 if (pf->support_multi_driver) {
8033 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8034 return I40E_NOT_SUPPORTED;
8037 memset(&filter_replace, 0,
8038 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8039 memset(&filter_replace_buf, 0,
8040 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8042 /* create L1 filter */
8043 filter_replace.old_filter_type =
8044 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
8045 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
8046 filter_replace.tr_bit = 0;
8048 /* Prepare the buffer, 3 entries */
8049 filter_replace_buf.data[0] =
8050 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8051 filter_replace_buf.data[0] |=
8052 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8053 filter_replace_buf.data[2] = 0xFF;
8054 filter_replace_buf.data[3] = 0xFF;
8055 filter_replace_buf.data[4] =
8056 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8057 filter_replace_buf.data[4] |=
8058 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8059 filter_replace_buf.data[7] = 0xF0;
8060 filter_replace_buf.data[8]
8061 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
8062 filter_replace_buf.data[8] |=
8063 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8064 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
8065 I40E_TR_GENEVE_KEY_MASK |
8066 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
8067 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
8068 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
8069 I40E_TR_GRE_NO_KEY_MASK) >> 8;
8071 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8072 &filter_replace_buf);
8073 if (!status && (filter_replace.old_filter_type !=
8074 filter_replace.new_filter_type))
8075 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8076 " original: 0x%x, new: 0x%x",
8078 filter_replace.old_filter_type,
8079 filter_replace.new_filter_type);
8085 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
8087 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8088 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8089 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8090 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8091 enum i40e_status_code status = I40E_SUCCESS;
8093 if (pf->support_multi_driver) {
8094 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8095 return I40E_NOT_SUPPORTED;
8099 memset(&filter_replace, 0,
8100 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8101 memset(&filter_replace_buf, 0,
8102 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8103 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
8104 I40E_AQC_MIRROR_CLOUD_FILTER;
8105 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
8106 filter_replace.new_filter_type =
8107 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8108 /* Prepare the buffer, 2 entries */
8109 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8110 filter_replace_buf.data[0] |=
8111 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8112 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8113 filter_replace_buf.data[4] |=
8114 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8115 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8116 &filter_replace_buf);
8119 if (filter_replace.old_filter_type !=
8120 filter_replace.new_filter_type)
8121 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8122 " original: 0x%x, new: 0x%x",
8124 filter_replace.old_filter_type,
8125 filter_replace.new_filter_type);
8128 memset(&filter_replace, 0,
8129 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8130 memset(&filter_replace_buf, 0,
8131 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8133 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
8134 I40E_AQC_MIRROR_CLOUD_FILTER;
8135 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
8136 filter_replace.new_filter_type =
8137 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8138 /* Prepare the buffer, 2 entries */
8139 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8140 filter_replace_buf.data[0] |=
8141 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8142 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8143 filter_replace_buf.data[4] |=
8144 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8146 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8147 &filter_replace_buf);
8148 if (!status && (filter_replace.old_filter_type !=
8149 filter_replace.new_filter_type))
8150 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8151 " original: 0x%x, new: 0x%x",
8153 filter_replace.old_filter_type,
8154 filter_replace.new_filter_type);
8159 static enum i40e_status_code
8160 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
8162 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8163 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8164 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8165 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8166 enum i40e_status_code status = I40E_SUCCESS;
8168 if (pf->support_multi_driver) {
8169 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8170 return I40E_NOT_SUPPORTED;
8174 memset(&filter_replace, 0,
8175 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8176 memset(&filter_replace_buf, 0,
8177 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8178 /* create L1 filter */
8179 filter_replace.old_filter_type =
8180 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
8181 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
8182 filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
8183 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8184 /* Prepare the buffer, 2 entries */
8185 filter_replace_buf.data[0] =
8186 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8187 filter_replace_buf.data[0] |=
8188 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8189 filter_replace_buf.data[2] = 0xFF;
8190 filter_replace_buf.data[3] = 0xFF;
8191 filter_replace_buf.data[4] =
8192 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8193 filter_replace_buf.data[4] |=
8194 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8195 filter_replace_buf.data[6] = 0xFF;
8196 filter_replace_buf.data[7] = 0xFF;
8197 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8198 &filter_replace_buf);
8201 if (filter_replace.old_filter_type !=
8202 filter_replace.new_filter_type)
8203 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8204 " original: 0x%x, new: 0x%x",
8206 filter_replace.old_filter_type,
8207 filter_replace.new_filter_type);
8210 memset(&filter_replace, 0,
8211 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8212 memset(&filter_replace_buf, 0,
8213 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8214 /* create L1 filter */
8215 filter_replace.old_filter_type =
8216 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8217 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
8218 filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
8219 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8220 /* Prepare the buffer, 2 entries */
8221 filter_replace_buf.data[0] =
8222 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8223 filter_replace_buf.data[0] |=
8224 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8225 filter_replace_buf.data[2] = 0xFF;
8226 filter_replace_buf.data[3] = 0xFF;
8227 filter_replace_buf.data[4] =
8228 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8229 filter_replace_buf.data[4] |=
8230 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8231 filter_replace_buf.data[6] = 0xFF;
8232 filter_replace_buf.data[7] = 0xFF;
8234 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8235 &filter_replace_buf);
8236 if (!status && (filter_replace.old_filter_type !=
8237 filter_replace.new_filter_type))
8238 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8239 " original: 0x%x, new: 0x%x",
8241 filter_replace.old_filter_type,
8242 filter_replace.new_filter_type);
8248 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
8250 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8251 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8252 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8253 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8254 enum i40e_status_code status = I40E_SUCCESS;
8256 if (pf->support_multi_driver) {
8257 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8258 return I40E_NOT_SUPPORTED;
8262 memset(&filter_replace, 0,
8263 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8264 memset(&filter_replace_buf, 0,
8265 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8266 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8267 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
8268 filter_replace.new_filter_type =
8269 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8270 /* Prepare the buffer, 2 entries */
8271 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
8272 filter_replace_buf.data[0] |=
8273 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8274 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8275 filter_replace_buf.data[4] |=
8276 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8277 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8278 &filter_replace_buf);
8281 if (filter_replace.old_filter_type !=
8282 filter_replace.new_filter_type)
8283 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8284 " original: 0x%x, new: 0x%x",
8286 filter_replace.old_filter_type,
8287 filter_replace.new_filter_type);
8290 memset(&filter_replace, 0,
8291 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8292 memset(&filter_replace_buf, 0,
8293 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8294 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8295 filter_replace.old_filter_type =
8296 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8297 filter_replace.new_filter_type =
8298 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8299 /* Prepare the buffer, 2 entries */
8300 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8301 filter_replace_buf.data[0] |=
8302 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8303 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8304 filter_replace_buf.data[4] |=
8305 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8307 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8308 &filter_replace_buf);
8309 if (!status && (filter_replace.old_filter_type !=
8310 filter_replace.new_filter_type))
8311 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8312 " original: 0x%x, new: 0x%x",
8314 filter_replace.old_filter_type,
8315 filter_replace.new_filter_type);
8320 static enum i40e_status_code
8321 i40e_replace_port_l1_filter(struct i40e_pf *pf,
8322 enum i40e_l4_port_type l4_port_type)
8324 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8325 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8326 enum i40e_status_code status = I40E_SUCCESS;
8327 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8328 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8330 if (pf->support_multi_driver) {
8331 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8332 return I40E_NOT_SUPPORTED;
8335 memset(&filter_replace, 0,
8336 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8337 memset(&filter_replace_buf, 0,
8338 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8340 /* create L1 filter */
8341 if (l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8342 filter_replace.old_filter_type =
8343 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8344 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
8345 filter_replace_buf.data[8] =
8346 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_SRC_PORT;
8348 filter_replace.old_filter_type =
8349 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
8350 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X10;
8351 filter_replace_buf.data[8] =
8352 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_DST_PORT;
8355 filter_replace.tr_bit = 0;
8356 /* Prepare the buffer, 3 entries */
8357 filter_replace_buf.data[0] =
8358 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_DIRECTION_WORD0;
8359 filter_replace_buf.data[0] |=
8360 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8361 filter_replace_buf.data[2] = 0x00;
8362 filter_replace_buf.data[3] =
8363 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_INGRESS_WORD0;
8364 filter_replace_buf.data[4] =
8365 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_PORT_TR_WORD0;
8366 filter_replace_buf.data[4] |=
8367 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8368 filter_replace_buf.data[5] = 0x00;
8369 filter_replace_buf.data[6] = I40E_TR_L4_TYPE_UDP |
8370 I40E_TR_L4_TYPE_TCP |
8371 I40E_TR_L4_TYPE_SCTP;
8372 filter_replace_buf.data[7] = 0x00;
8373 filter_replace_buf.data[8] |=
8374 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8375 filter_replace_buf.data[9] = 0x00;
8376 filter_replace_buf.data[10] = 0xFF;
8377 filter_replace_buf.data[11] = 0xFF;
8379 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8380 &filter_replace_buf);
8381 if (!status && filter_replace.old_filter_type !=
8382 filter_replace.new_filter_type)
8383 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8384 " original: 0x%x, new: 0x%x",
8386 filter_replace.old_filter_type,
8387 filter_replace.new_filter_type);
8392 static enum i40e_status_code
8393 i40e_replace_port_cloud_filter(struct i40e_pf *pf,
8394 enum i40e_l4_port_type l4_port_type)
8396 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8397 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8398 enum i40e_status_code status = I40E_SUCCESS;
8399 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8400 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8402 if (pf->support_multi_driver) {
8403 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8404 return I40E_NOT_SUPPORTED;
8407 memset(&filter_replace, 0,
8408 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8409 memset(&filter_replace_buf, 0,
8410 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8412 if (l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8413 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
8414 filter_replace.new_filter_type =
8415 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8416 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X11;
8418 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
8419 filter_replace.new_filter_type =
8420 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8421 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
8424 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8425 filter_replace.tr_bit = 0;
8426 /* Prepare the buffer, 2 entries */
8427 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8428 filter_replace_buf.data[0] |=
8429 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8430 filter_replace_buf.data[4] |=
8431 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8432 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8433 &filter_replace_buf);
8435 if (!status && filter_replace.old_filter_type !=
8436 filter_replace.new_filter_type)
8437 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8438 " original: 0x%x, new: 0x%x",
8440 filter_replace.old_filter_type,
8441 filter_replace.new_filter_type);
8447 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8448 struct i40e_tunnel_filter_conf *tunnel_filter,
8452 uint32_t ipv4_addr, ipv4_addr_le;
8453 uint8_t i, tun_type = 0;
8454 /* internal variable to convert ipv6 byte order */
8455 uint32_t convert_ipv6[4];
8457 struct i40e_pf_vf *vf = NULL;
8458 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8459 struct i40e_vsi *vsi;
8460 struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8461 struct i40e_aqc_cloud_filters_element_bb *pfilter;
8462 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8463 struct i40e_tunnel_filter *tunnel, *node;
8464 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8466 bool big_buffer = 0;
8468 cld_filter = rte_zmalloc("tunnel_filter",
8469 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8472 if (cld_filter == NULL) {
8473 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8476 pfilter = cld_filter;
8478 rte_ether_addr_copy(&tunnel_filter->outer_mac,
8479 (struct rte_ether_addr *)&pfilter->element.outer_mac);
8480 rte_ether_addr_copy(&tunnel_filter->inner_mac,
8481 (struct rte_ether_addr *)&pfilter->element.inner_mac);
8483 pfilter->element.inner_vlan =
8484 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8485 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8486 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8487 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8488 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8489 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8491 sizeof(pfilter->element.ipaddr.v4.data));
8493 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8494 for (i = 0; i < 4; i++) {
8496 rte_cpu_to_le_32(rte_be_to_cpu_32(
8497 tunnel_filter->ip_addr.ipv6_addr[i]));
8499 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8501 sizeof(pfilter->element.ipaddr.v6.data));
8504 /* check tunneled type */
8505 switch (tunnel_filter->tunnel_type) {
8506 case I40E_TUNNEL_TYPE_VXLAN:
8507 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8509 case I40E_TUNNEL_TYPE_NVGRE:
8510 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8512 case I40E_TUNNEL_TYPE_IP_IN_GRE:
8513 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8515 case I40E_TUNNEL_TYPE_MPLSoUDP:
8516 if (!pf->mpls_replace_flag) {
8517 i40e_replace_mpls_l1_filter(pf);
8518 i40e_replace_mpls_cloud_filter(pf);
8519 pf->mpls_replace_flag = 1;
8521 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8522 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8524 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8525 (teid_le & 0xF) << 12;
8526 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8529 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8531 case I40E_TUNNEL_TYPE_MPLSoGRE:
8532 if (!pf->mpls_replace_flag) {
8533 i40e_replace_mpls_l1_filter(pf);
8534 i40e_replace_mpls_cloud_filter(pf);
8535 pf->mpls_replace_flag = 1;
8537 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8538 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8540 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8541 (teid_le & 0xF) << 12;
8542 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8545 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8547 case I40E_TUNNEL_TYPE_GTPC:
8548 if (!pf->gtp_replace_flag) {
8549 i40e_replace_gtp_l1_filter(pf);
8550 i40e_replace_gtp_cloud_filter(pf);
8551 pf->gtp_replace_flag = 1;
8553 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8554 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8555 (teid_le >> 16) & 0xFFFF;
8556 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8558 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8562 case I40E_TUNNEL_TYPE_GTPU:
8563 if (!pf->gtp_replace_flag) {
8564 i40e_replace_gtp_l1_filter(pf);
8565 i40e_replace_gtp_cloud_filter(pf);
8566 pf->gtp_replace_flag = 1;
8568 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8569 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8570 (teid_le >> 16) & 0xFFFF;
8571 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8573 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8577 case I40E_TUNNEL_TYPE_QINQ:
8578 if (!pf->qinq_replace_flag) {
8579 ret = i40e_cloud_filter_qinq_create(pf);
8582 "QinQ tunnel filter already created.");
8583 pf->qinq_replace_flag = 1;
8585 /* Add in the General fields the values of
8586 * the Outer and Inner VLAN
8587 * Big Buffer should be set, see changes in
8588 * i40e_aq_add_cloud_filters
8590 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8591 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8594 case I40E_CLOUD_TYPE_UDP:
8595 case I40E_CLOUD_TYPE_TCP:
8596 case I40E_CLOUD_TYPE_SCTP:
8597 if (tunnel_filter->l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8598 if (!pf->sport_replace_flag) {
8599 i40e_replace_port_l1_filter(pf,
8600 tunnel_filter->l4_port_type);
8601 i40e_replace_port_cloud_filter(pf,
8602 tunnel_filter->l4_port_type);
8603 pf->sport_replace_flag = 1;
8605 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8606 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8607 I40E_DIRECTION_INGRESS_KEY;
8609 if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP)
8610 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8611 I40E_TR_L4_TYPE_UDP;
8612 else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP)
8613 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8614 I40E_TR_L4_TYPE_TCP;
8616 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8617 I40E_TR_L4_TYPE_SCTP;
8619 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8620 (teid_le >> 16) & 0xFFFF;
8623 if (!pf->dport_replace_flag) {
8624 i40e_replace_port_l1_filter(pf,
8625 tunnel_filter->l4_port_type);
8626 i40e_replace_port_cloud_filter(pf,
8627 tunnel_filter->l4_port_type);
8628 pf->dport_replace_flag = 1;
8630 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8631 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0] =
8632 I40E_DIRECTION_INGRESS_KEY;
8634 if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP)
8635 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8636 I40E_TR_L4_TYPE_UDP;
8637 else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP)
8638 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8639 I40E_TR_L4_TYPE_TCP;
8641 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8642 I40E_TR_L4_TYPE_SCTP;
8644 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2] =
8645 (teid_le >> 16) & 0xFFFF;
8651 /* Other tunnel types is not supported. */
8652 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8653 rte_free(cld_filter);
8657 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8658 pfilter->element.flags =
8659 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8660 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8661 pfilter->element.flags =
8662 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8663 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8664 pfilter->element.flags =
8665 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8666 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8667 pfilter->element.flags =
8668 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8669 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8670 pfilter->element.flags |=
8671 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8672 else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP ||
8673 tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP ||
8674 tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_SCTP) {
8675 if (tunnel_filter->l4_port_type == I40E_L4_PORT_TYPE_SRC)
8676 pfilter->element.flags |=
8677 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8679 pfilter->element.flags |=
8680 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8682 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8683 &pfilter->element.flags);
8685 rte_free(cld_filter);
8690 pfilter->element.flags |= rte_cpu_to_le_16(
8691 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8692 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8693 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8694 pfilter->element.queue_number =
8695 rte_cpu_to_le_16(tunnel_filter->queue_id);
8697 if (!tunnel_filter->is_to_vf)
8700 if (tunnel_filter->vf_id >= pf->vf_num) {
8701 PMD_DRV_LOG(ERR, "Invalid argument.");
8702 rte_free(cld_filter);
8705 vf = &pf->vfs[tunnel_filter->vf_id];
8709 /* Check if there is the filter in SW list */
8710 memset(&check_filter, 0, sizeof(check_filter));
8711 i40e_tunnel_filter_convert(cld_filter, &check_filter);
8712 check_filter.is_to_vf = tunnel_filter->is_to_vf;
8713 check_filter.vf_id = tunnel_filter->vf_id;
8714 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8716 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8717 rte_free(cld_filter);
8721 if (!add && !node) {
8722 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8723 rte_free(cld_filter);
8729 ret = i40e_aq_add_cloud_filters_bb(hw,
8730 vsi->seid, cld_filter, 1);
8732 ret = i40e_aq_add_cloud_filters(hw,
8733 vsi->seid, &cld_filter->element, 1);
8735 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8736 rte_free(cld_filter);
8739 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8740 if (tunnel == NULL) {
8741 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8742 rte_free(cld_filter);
8746 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8747 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8752 ret = i40e_aq_rem_cloud_filters_bb(
8753 hw, vsi->seid, cld_filter, 1);
8755 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8756 &cld_filter->element, 1);
8758 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8759 rte_free(cld_filter);
8762 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8765 rte_free(cld_filter);
8770 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8774 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8775 if (pf->vxlan_ports[i] == port)
8783 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port, int udp_type)
8786 uint8_t filter_idx = 0;
8787 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8789 idx = i40e_get_vxlan_port_idx(pf, port);
8791 /* Check if port already exists */
8793 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8797 /* Now check if there is space to add the new port */
8798 idx = i40e_get_vxlan_port_idx(pf, 0);
8801 "Maximum number of UDP ports reached, not adding port %d",
8806 ret = i40e_aq_add_udp_tunnel(hw, port, udp_type,
8809 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8813 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8816 /* New port: add it and mark its index in the bitmap */
8817 pf->vxlan_ports[idx] = port;
8818 pf->vxlan_bitmap |= (1 << idx);
8820 if (!(pf->flags & I40E_FLAG_VXLAN))
8821 pf->flags |= I40E_FLAG_VXLAN;
8827 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8830 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8832 if (!(pf->flags & I40E_FLAG_VXLAN)) {
8833 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8837 idx = i40e_get_vxlan_port_idx(pf, port);
8840 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8844 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8845 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8849 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8852 pf->vxlan_ports[idx] = 0;
8853 pf->vxlan_bitmap &= ~(1 << idx);
8855 if (!pf->vxlan_bitmap)
8856 pf->flags &= ~I40E_FLAG_VXLAN;
8861 /* Add UDP tunneling port */
8863 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8864 struct rte_eth_udp_tunnel *udp_tunnel)
8867 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8869 if (udp_tunnel == NULL)
8872 switch (udp_tunnel->prot_type) {
8873 case RTE_TUNNEL_TYPE_VXLAN:
8874 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8875 I40E_AQC_TUNNEL_TYPE_VXLAN);
8877 case RTE_TUNNEL_TYPE_VXLAN_GPE:
8878 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8879 I40E_AQC_TUNNEL_TYPE_VXLAN_GPE);
8881 case RTE_TUNNEL_TYPE_GENEVE:
8882 case RTE_TUNNEL_TYPE_TEREDO:
8883 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8888 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8896 /* Remove UDP tunneling port */
8898 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8899 struct rte_eth_udp_tunnel *udp_tunnel)
8902 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8904 if (udp_tunnel == NULL)
8907 switch (udp_tunnel->prot_type) {
8908 case RTE_TUNNEL_TYPE_VXLAN:
8909 case RTE_TUNNEL_TYPE_VXLAN_GPE:
8910 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8912 case RTE_TUNNEL_TYPE_GENEVE:
8913 case RTE_TUNNEL_TYPE_TEREDO:
8914 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8918 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8926 /* Calculate the maximum number of contiguous PF queues that are configured */
8928 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8930 struct rte_eth_dev_data *data = pf->dev_data;
8932 struct i40e_rx_queue *rxq;
8935 for (i = 0; i < pf->lan_nb_qps; i++) {
8936 rxq = data->rx_queues[i];
8937 if (rxq && rxq->q_set)
8948 i40e_pf_config_rss(struct i40e_pf *pf)
8950 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8951 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8952 struct rte_eth_rss_conf rss_conf;
8953 uint32_t i, lut = 0;
8957 * If both VMDQ and RSS enabled, not all of PF queues are configured.
8958 * It's necessary to calculate the actual PF queues that are configured.
8960 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8961 num = i40e_pf_calc_configured_queues_num(pf);
8963 num = pf->dev_data->nb_rx_queues;
8965 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8966 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8971 "No PF queues are configured to enable RSS for port %u",
8972 pf->dev_data->port_id);
8976 if (pf->adapter->rss_reta_updated == 0) {
8977 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8980 lut = (lut << 8) | (j & ((0x1 <<
8981 hw->func_caps.rss_table_entry_width) - 1));
8983 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2),
8988 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8989 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0 ||
8990 !(mq_mode & ETH_MQ_RX_RSS_FLAG)) {
8991 i40e_pf_disable_rss(pf);
8994 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8995 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8996 /* Random default keys */
8997 static uint32_t rss_key_default[] = {0x6b793944,
8998 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8999 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
9000 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
9002 rss_conf.rss_key = (uint8_t *)rss_key_default;
9003 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
9007 return i40e_hw_rss_hash_set(pf, &rss_conf);
9011 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
9012 struct rte_eth_tunnel_filter_conf *filter)
9014 if (pf == NULL || filter == NULL) {
9015 PMD_DRV_LOG(ERR, "Invalid parameter");
9019 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
9020 PMD_DRV_LOG(ERR, "Invalid queue ID");
9024 if (filter->inner_vlan > RTE_ETHER_MAX_VLAN_ID) {
9025 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
9029 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
9030 (rte_is_zero_ether_addr(&filter->outer_mac))) {
9031 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
9035 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
9036 (rte_is_zero_ether_addr(&filter->inner_mac))) {
9037 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
9044 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
9045 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
9047 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
9049 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9053 if (pf->support_multi_driver) {
9054 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
9058 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
9059 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
9062 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
9063 } else if (len == 4) {
9064 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
9066 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
9071 ret = i40e_aq_debug_write_global_register(hw,
9072 I40E_GL_PRS_FVBM(2),
9076 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
9077 "with value 0x%08x",
9078 I40E_GL_PRS_FVBM(2), reg);
9082 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
9083 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
9089 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
9096 switch (cfg->cfg_type) {
9097 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
9098 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
9101 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
9109 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
9110 enum rte_filter_op filter_op,
9113 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9114 int ret = I40E_ERR_PARAM;
9116 switch (filter_op) {
9117 case RTE_ETH_FILTER_SET:
9118 ret = i40e_dev_global_config_set(hw,
9119 (struct rte_eth_global_cfg *)arg);
9122 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
9130 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
9131 enum rte_filter_op filter_op,
9134 struct rte_eth_tunnel_filter_conf *filter;
9135 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9136 int ret = I40E_SUCCESS;
9138 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
9140 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
9141 return I40E_ERR_PARAM;
9143 switch (filter_op) {
9144 case RTE_ETH_FILTER_NOP:
9145 if (!(pf->flags & I40E_FLAG_VXLAN))
9146 ret = I40E_NOT_SUPPORTED;
9148 case RTE_ETH_FILTER_ADD:
9149 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
9151 case RTE_ETH_FILTER_DELETE:
9152 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
9155 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
9156 ret = I40E_ERR_PARAM;
9163 /* Get the symmetric hash enable configurations per port */
9165 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
9167 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
9169 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
9172 /* Set the symmetric hash enable configurations per port */
9174 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
9176 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
9179 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
9181 "Symmetric hash has already been enabled");
9184 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
9186 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
9188 "Symmetric hash has already been disabled");
9191 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
9193 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
9194 I40E_WRITE_FLUSH(hw);
9198 * Get global configurations of hash function type and symmetric hash enable
9199 * per flow type (pctype). Note that global configuration means it affects all
9200 * the ports on the same NIC.
9203 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
9204 struct rte_eth_hash_global_conf *g_cfg)
9206 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
9210 memset(g_cfg, 0, sizeof(*g_cfg));
9211 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
9212 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
9213 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
9215 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
9216 PMD_DRV_LOG(DEBUG, "Hash function is %s",
9217 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
9220 * As i40e supports less than 64 flow types, only first 64 bits need to
9223 for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
9224 g_cfg->valid_bit_mask[i] = 0ULL;
9225 g_cfg->sym_hash_enable_mask[i] = 0ULL;
9228 g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
9230 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
9231 if (!adapter->pctypes_tbl[i])
9233 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
9234 j < I40E_FILTER_PCTYPE_MAX; j++) {
9235 if (adapter->pctypes_tbl[i] & (1ULL << j)) {
9236 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
9237 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
9238 g_cfg->sym_hash_enable_mask[0] |=
9249 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
9250 const struct rte_eth_hash_global_conf *g_cfg)
9253 uint64_t mask0, i40e_mask = adapter->flow_types_mask;
9255 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
9256 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
9257 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
9258 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
9264 * As i40e supports less than 64 flow types, only first 64 bits need to
9267 mask0 = g_cfg->valid_bit_mask[0];
9268 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
9270 /* Check if any unsupported flow type configured */
9271 if ((mask0 | i40e_mask) ^ i40e_mask)
9274 if (g_cfg->valid_bit_mask[i])
9282 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
9288 * Set global configurations of hash function type and symmetric hash enable
9289 * per flow type (pctype). Note any modifying global configuration will affect
9290 * all the ports on the same NIC.
9293 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
9294 struct rte_eth_hash_global_conf *g_cfg)
9296 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
9297 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9301 uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
9303 if (pf->support_multi_driver) {
9304 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
9308 /* Check the input parameters */
9309 ret = i40e_hash_global_config_check(adapter, g_cfg);
9314 * As i40e supports less than 64 flow types, only first 64 bits need to
9317 for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
9318 if (mask0 & (1UL << i)) {
9319 reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
9320 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
9322 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
9323 j < I40E_FILTER_PCTYPE_MAX; j++) {
9324 if (adapter->pctypes_tbl[i] & (1ULL << j))
9325 i40e_write_global_rx_ctl(hw,
9332 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
9333 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
9335 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
9337 "Hash function already set to Toeplitz");
9340 reg |= I40E_GLQF_CTL_HTOEP_MASK;
9341 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
9343 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
9345 "Hash function already set to Simple XOR");
9348 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
9350 /* Use the default, and keep it as it is */
9353 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
9356 I40E_WRITE_FLUSH(hw);
9362 * Valid input sets for hash and flow director filters per PCTYPE
9365 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
9366 enum rte_filter_type filter)
9370 static const uint64_t valid_hash_inset_table[] = {
9371 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9372 I40E_INSET_DMAC | I40E_INSET_SMAC |
9373 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9374 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
9375 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
9376 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9377 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9378 I40E_INSET_FLEX_PAYLOAD,
9379 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9380 I40E_INSET_DMAC | I40E_INSET_SMAC |
9381 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9382 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9383 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9384 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9385 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9386 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9387 I40E_INSET_FLEX_PAYLOAD,
9388 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9389 I40E_INSET_DMAC | I40E_INSET_SMAC |
9390 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9391 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9392 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9393 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9394 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9395 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9396 I40E_INSET_FLEX_PAYLOAD,
9397 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9398 I40E_INSET_DMAC | I40E_INSET_SMAC |
9399 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9400 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9401 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9402 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9403 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9404 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9405 I40E_INSET_FLEX_PAYLOAD,
9406 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9407 I40E_INSET_DMAC | I40E_INSET_SMAC |
9408 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9409 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9410 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9411 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9412 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9413 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9414 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9415 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9416 I40E_INSET_DMAC | I40E_INSET_SMAC |
9417 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9418 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9419 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9420 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9421 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9422 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9423 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9424 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9425 I40E_INSET_DMAC | I40E_INSET_SMAC |
9426 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9427 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9428 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9429 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9430 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9431 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9432 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
9433 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9434 I40E_INSET_DMAC | I40E_INSET_SMAC |
9435 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9436 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9437 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9438 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9439 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9440 I40E_INSET_FLEX_PAYLOAD,
9441 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9442 I40E_INSET_DMAC | I40E_INSET_SMAC |
9443 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9444 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9445 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9446 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
9447 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
9448 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
9449 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9450 I40E_INSET_DMAC | I40E_INSET_SMAC |
9451 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9452 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9453 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9454 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9455 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9456 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
9457 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9458 I40E_INSET_DMAC | I40E_INSET_SMAC |
9459 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9460 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9461 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9462 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9463 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9464 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9465 I40E_INSET_FLEX_PAYLOAD,
9466 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9467 I40E_INSET_DMAC | I40E_INSET_SMAC |
9468 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9469 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9470 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9471 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9472 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9473 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9474 I40E_INSET_FLEX_PAYLOAD,
9475 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9476 I40E_INSET_DMAC | I40E_INSET_SMAC |
9477 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9478 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9479 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9480 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9481 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9482 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9483 I40E_INSET_FLEX_PAYLOAD,
9484 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9485 I40E_INSET_DMAC | I40E_INSET_SMAC |
9486 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9487 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9488 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9489 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9490 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9491 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9492 I40E_INSET_FLEX_PAYLOAD,
9493 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9494 I40E_INSET_DMAC | I40E_INSET_SMAC |
9495 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9496 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9497 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9498 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9499 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9500 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9501 I40E_INSET_FLEX_PAYLOAD,
9502 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9503 I40E_INSET_DMAC | I40E_INSET_SMAC |
9504 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9505 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9506 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9507 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9508 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9509 I40E_INSET_FLEX_PAYLOAD,
9510 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9511 I40E_INSET_DMAC | I40E_INSET_SMAC |
9512 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9513 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9514 I40E_INSET_FLEX_PAYLOAD,
9518 * Flow director supports only fields defined in
9519 * union rte_eth_fdir_flow.
9521 static const uint64_t valid_fdir_inset_table[] = {
9522 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9523 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9524 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9525 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9526 I40E_INSET_IPV4_TTL,
9527 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9528 I40E_INSET_DMAC | I40E_INSET_SMAC |
9529 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9530 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9531 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9532 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9533 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9534 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9535 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9536 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9537 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9538 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9539 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9540 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9541 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9542 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9543 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9544 I40E_INSET_DMAC | I40E_INSET_SMAC |
9545 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9546 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9547 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9548 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9549 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9550 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9551 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9552 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9553 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9554 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9555 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9556 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9557 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9558 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9560 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9561 I40E_INSET_DMAC | I40E_INSET_SMAC |
9562 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9563 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9564 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9565 I40E_INSET_IPV4_TTL,
9566 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9567 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9568 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9569 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9570 I40E_INSET_IPV6_HOP_LIMIT,
9571 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9572 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9573 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9574 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9575 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9576 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9577 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9578 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9579 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9580 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9581 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9582 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9583 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9584 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9585 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9586 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9587 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9588 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9589 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9590 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9591 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9592 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9593 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9594 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9595 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9596 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9597 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9598 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9599 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9600 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9602 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9603 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9604 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9605 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9606 I40E_INSET_IPV6_HOP_LIMIT,
9607 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9608 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9609 I40E_INSET_LAST_ETHER_TYPE,
9612 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9614 if (filter == RTE_ETH_FILTER_HASH)
9615 valid = valid_hash_inset_table[pctype];
9617 valid = valid_fdir_inset_table[pctype];
9623 * Validate if the input set is allowed for a specific PCTYPE
9626 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9627 enum rte_filter_type filter, uint64_t inset)
9631 valid = i40e_get_valid_input_set(pctype, filter);
9632 if (inset & (~valid))
9638 /* default input set fields combination per pctype */
9640 i40e_get_default_input_set(uint16_t pctype)
9642 static const uint64_t default_inset_table[] = {
9643 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9644 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9645 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9646 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9647 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9648 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9649 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9650 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9651 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9652 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9653 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9654 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9655 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9656 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9657 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9658 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9659 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9660 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9661 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9662 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9664 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9665 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9666 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9667 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9668 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9669 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9670 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9671 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9672 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9673 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9674 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9675 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9676 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9677 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9678 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9679 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9680 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9681 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9682 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9683 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9684 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9685 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9687 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9688 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9689 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9690 I40E_INSET_LAST_ETHER_TYPE,
9693 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9696 return default_inset_table[pctype];
9700 * Parse the input set from index to logical bit masks
9703 i40e_parse_input_set(uint64_t *inset,
9704 enum i40e_filter_pctype pctype,
9705 enum rte_eth_input_set_field *field,
9711 static const struct {
9712 enum rte_eth_input_set_field field;
9714 } inset_convert_table[] = {
9715 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9716 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9717 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9718 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9719 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9720 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9721 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9722 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9723 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9724 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9725 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9726 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9727 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9728 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9729 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9730 I40E_INSET_IPV6_NEXT_HDR},
9731 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9732 I40E_INSET_IPV6_HOP_LIMIT},
9733 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9734 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9735 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9736 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9737 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9738 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9739 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9740 I40E_INSET_SCTP_VT},
9741 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9742 I40E_INSET_TUNNEL_DMAC},
9743 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9744 I40E_INSET_VLAN_TUNNEL},
9745 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9746 I40E_INSET_TUNNEL_ID},
9747 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9748 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9749 I40E_INSET_FLEX_PAYLOAD_W1},
9750 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9751 I40E_INSET_FLEX_PAYLOAD_W2},
9752 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9753 I40E_INSET_FLEX_PAYLOAD_W3},
9754 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9755 I40E_INSET_FLEX_PAYLOAD_W4},
9756 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9757 I40E_INSET_FLEX_PAYLOAD_W5},
9758 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9759 I40E_INSET_FLEX_PAYLOAD_W6},
9760 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9761 I40E_INSET_FLEX_PAYLOAD_W7},
9762 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9763 I40E_INSET_FLEX_PAYLOAD_W8},
9766 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9769 /* Only one item allowed for default or all */
9771 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9772 *inset = i40e_get_default_input_set(pctype);
9774 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9775 *inset = I40E_INSET_NONE;
9780 for (i = 0, *inset = 0; i < size; i++) {
9781 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9782 if (field[i] == inset_convert_table[j].field) {
9783 *inset |= inset_convert_table[j].inset;
9788 /* It contains unsupported input set, return immediately */
9789 if (j == RTE_DIM(inset_convert_table))
9797 * Translate the input set from bit masks to register aware bit masks
9801 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9811 static const struct inset_map inset_map_common[] = {
9812 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9813 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9814 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9815 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9816 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9817 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9818 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9819 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9820 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9821 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9822 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9823 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9824 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9825 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9826 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9827 {I40E_INSET_TUNNEL_DMAC,
9828 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9829 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9830 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9831 {I40E_INSET_TUNNEL_SRC_PORT,
9832 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9833 {I40E_INSET_TUNNEL_DST_PORT,
9834 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9835 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9836 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9837 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9838 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9839 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9840 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9841 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9842 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9843 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9846 /* some different registers map in x722*/
9847 static const struct inset_map inset_map_diff_x722[] = {
9848 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9849 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9850 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9851 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9854 static const struct inset_map inset_map_diff_not_x722[] = {
9855 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9856 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9857 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9858 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9864 /* Translate input set to register aware inset */
9865 if (type == I40E_MAC_X722) {
9866 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9867 if (input & inset_map_diff_x722[i].inset)
9868 val |= inset_map_diff_x722[i].inset_reg;
9871 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9872 if (input & inset_map_diff_not_x722[i].inset)
9873 val |= inset_map_diff_not_x722[i].inset_reg;
9877 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9878 if (input & inset_map_common[i].inset)
9879 val |= inset_map_common[i].inset_reg;
9886 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9889 uint64_t inset_need_mask = inset;
9891 static const struct {
9894 } inset_mask_map[] = {
9895 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9896 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9897 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9898 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9899 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9900 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9901 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9902 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9905 if (!inset || !mask || !nb_elem)
9908 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9909 /* Clear the inset bit, if no MASK is required,
9910 * for example proto + ttl
9912 if ((inset & inset_mask_map[i].inset) ==
9913 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9914 inset_need_mask &= ~inset_mask_map[i].inset;
9915 if (!inset_need_mask)
9918 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9919 if ((inset_need_mask & inset_mask_map[i].inset) ==
9920 inset_mask_map[i].inset) {
9921 if (idx >= nb_elem) {
9922 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9925 mask[idx] = inset_mask_map[i].mask;
9934 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9936 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9938 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9940 i40e_write_rx_ctl(hw, addr, val);
9941 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9942 (uint32_t)i40e_read_rx_ctl(hw, addr));
9946 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9948 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9949 struct rte_eth_dev *dev;
9951 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
9953 i40e_write_rx_ctl(hw, addr, val);
9954 PMD_DRV_LOG(WARNING,
9955 "i40e device %s changed global register [0x%08x]."
9956 " original: 0x%08x, new: 0x%08x",
9957 dev->device->name, addr, reg,
9958 (uint32_t)i40e_read_rx_ctl(hw, addr));
9963 i40e_filter_input_set_init(struct i40e_pf *pf)
9965 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9966 enum i40e_filter_pctype pctype;
9967 uint64_t input_set, inset_reg;
9968 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9972 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9973 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9974 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9976 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9979 input_set = i40e_get_default_input_set(pctype);
9981 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9982 I40E_INSET_MASK_NUM_REG);
9985 if (pf->support_multi_driver && num > 0) {
9986 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9989 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9992 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9993 (uint32_t)(inset_reg & UINT32_MAX));
9994 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9995 (uint32_t)((inset_reg >>
9996 I40E_32_BIT_WIDTH) & UINT32_MAX));
9997 if (!pf->support_multi_driver) {
9998 i40e_check_write_global_reg(hw,
9999 I40E_GLQF_HASH_INSET(0, pctype),
10000 (uint32_t)(inset_reg & UINT32_MAX));
10001 i40e_check_write_global_reg(hw,
10002 I40E_GLQF_HASH_INSET(1, pctype),
10003 (uint32_t)((inset_reg >>
10004 I40E_32_BIT_WIDTH) & UINT32_MAX));
10006 for (i = 0; i < num; i++) {
10007 i40e_check_write_global_reg(hw,
10008 I40E_GLQF_FD_MSK(i, pctype),
10010 i40e_check_write_global_reg(hw,
10011 I40E_GLQF_HASH_MSK(i, pctype),
10014 /*clear unused mask registers of the pctype */
10015 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
10016 i40e_check_write_global_reg(hw,
10017 I40E_GLQF_FD_MSK(i, pctype),
10019 i40e_check_write_global_reg(hw,
10020 I40E_GLQF_HASH_MSK(i, pctype),
10024 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
10026 I40E_WRITE_FLUSH(hw);
10028 /* store the default input set */
10029 if (!pf->support_multi_driver)
10030 pf->hash_input_set[pctype] = input_set;
10031 pf->fdir.input_set[pctype] = input_set;
10036 i40e_hash_filter_inset_select(struct i40e_hw *hw,
10037 struct rte_eth_input_set_conf *conf)
10039 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
10040 enum i40e_filter_pctype pctype;
10041 uint64_t input_set, inset_reg = 0;
10042 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
10046 PMD_DRV_LOG(ERR, "Invalid pointer");
10049 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
10050 conf->op != RTE_ETH_INPUT_SET_ADD) {
10051 PMD_DRV_LOG(ERR, "Unsupported input set operation");
10055 if (pf->support_multi_driver) {
10056 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
10060 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
10061 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
10062 PMD_DRV_LOG(ERR, "invalid flow_type input.");
10066 if (hw->mac.type == I40E_MAC_X722) {
10067 /* get translated pctype value in fd pctype register */
10068 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
10069 I40E_GLQF_FD_PCTYPES((int)pctype));
10072 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
10075 PMD_DRV_LOG(ERR, "Failed to parse input set");
10079 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
10080 /* get inset value in register */
10081 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
10082 inset_reg <<= I40E_32_BIT_WIDTH;
10083 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
10084 input_set |= pf->hash_input_set[pctype];
10086 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
10087 I40E_INSET_MASK_NUM_REG);
10091 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
10093 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
10094 (uint32_t)(inset_reg & UINT32_MAX));
10095 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
10096 (uint32_t)((inset_reg >>
10097 I40E_32_BIT_WIDTH) & UINT32_MAX));
10099 for (i = 0; i < num; i++)
10100 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
10102 /*clear unused mask registers of the pctype */
10103 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
10104 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
10106 I40E_WRITE_FLUSH(hw);
10108 pf->hash_input_set[pctype] = input_set;
10113 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
10114 struct rte_eth_input_set_conf *conf)
10116 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10117 enum i40e_filter_pctype pctype;
10118 uint64_t input_set, inset_reg = 0;
10119 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
10122 if (!hw || !conf) {
10123 PMD_DRV_LOG(ERR, "Invalid pointer");
10126 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
10127 conf->op != RTE_ETH_INPUT_SET_ADD) {
10128 PMD_DRV_LOG(ERR, "Unsupported input set operation");
10132 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
10134 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
10135 PMD_DRV_LOG(ERR, "invalid flow_type input.");
10139 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
10142 PMD_DRV_LOG(ERR, "Failed to parse input set");
10146 /* get inset value in register */
10147 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
10148 inset_reg <<= I40E_32_BIT_WIDTH;
10149 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
10151 /* Can not change the inset reg for flex payload for fdir,
10152 * it is done by writing I40E_PRTQF_FD_FLXINSET
10153 * in i40e_set_flex_mask_on_pctype.
10155 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
10156 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
10158 input_set |= pf->fdir.input_set[pctype];
10159 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
10160 I40E_INSET_MASK_NUM_REG);
10163 if (pf->support_multi_driver && num > 0) {
10164 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
10168 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
10170 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
10171 (uint32_t)(inset_reg & UINT32_MAX));
10172 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
10173 (uint32_t)((inset_reg >>
10174 I40E_32_BIT_WIDTH) & UINT32_MAX));
10176 if (!pf->support_multi_driver) {
10177 for (i = 0; i < num; i++)
10178 i40e_check_write_global_reg(hw,
10179 I40E_GLQF_FD_MSK(i, pctype),
10181 /*clear unused mask registers of the pctype */
10182 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
10183 i40e_check_write_global_reg(hw,
10184 I40E_GLQF_FD_MSK(i, pctype),
10187 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
10189 I40E_WRITE_FLUSH(hw);
10191 pf->fdir.input_set[pctype] = input_set;
10196 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
10200 if (!hw || !info) {
10201 PMD_DRV_LOG(ERR, "Invalid pointer");
10205 switch (info->info_type) {
10206 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
10207 i40e_get_symmetric_hash_enable_per_port(hw,
10208 &(info->info.enable));
10210 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
10211 ret = i40e_get_hash_filter_global_config(hw,
10212 &(info->info.global_conf));
10215 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
10225 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
10229 if (!hw || !info) {
10230 PMD_DRV_LOG(ERR, "Invalid pointer");
10234 switch (info->info_type) {
10235 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
10236 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
10238 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
10239 ret = i40e_set_hash_filter_global_config(hw,
10240 &(info->info.global_conf));
10242 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
10243 ret = i40e_hash_filter_inset_select(hw,
10244 &(info->info.input_set_conf));
10248 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
10257 /* Operations for hash function */
10259 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
10260 enum rte_filter_op filter_op,
10263 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10266 switch (filter_op) {
10267 case RTE_ETH_FILTER_NOP:
10269 case RTE_ETH_FILTER_GET:
10270 ret = i40e_hash_filter_get(hw,
10271 (struct rte_eth_hash_filter_info *)arg);
10273 case RTE_ETH_FILTER_SET:
10274 ret = i40e_hash_filter_set(hw,
10275 (struct rte_eth_hash_filter_info *)arg);
10278 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
10287 /* Convert ethertype filter structure */
10289 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
10290 struct i40e_ethertype_filter *filter)
10292 rte_memcpy(&filter->input.mac_addr, &input->mac_addr,
10293 RTE_ETHER_ADDR_LEN);
10294 filter->input.ether_type = input->ether_type;
10295 filter->flags = input->flags;
10296 filter->queue = input->queue;
10301 /* Check if there exists the ehtertype filter */
10302 struct i40e_ethertype_filter *
10303 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
10304 const struct i40e_ethertype_filter_input *input)
10308 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
10312 return ethertype_rule->hash_map[ret];
10315 /* Add ethertype filter in SW list */
10317 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
10318 struct i40e_ethertype_filter *filter)
10320 struct i40e_ethertype_rule *rule = &pf->ethertype;
10323 ret = rte_hash_add_key(rule->hash_table, &filter->input);
10326 "Failed to insert ethertype filter"
10327 " to hash table %d!",
10331 rule->hash_map[ret] = filter;
10333 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
10338 /* Delete ethertype filter in SW list */
10340 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
10341 struct i40e_ethertype_filter_input *input)
10343 struct i40e_ethertype_rule *rule = &pf->ethertype;
10344 struct i40e_ethertype_filter *filter;
10347 ret = rte_hash_del_key(rule->hash_table, input);
10350 "Failed to delete ethertype filter"
10351 " to hash table %d!",
10355 filter = rule->hash_map[ret];
10356 rule->hash_map[ret] = NULL;
10358 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
10365 * Configure ethertype filter, which can director packet by filtering
10366 * with mac address and ether_type or only ether_type
10369 i40e_ethertype_filter_set(struct i40e_pf *pf,
10370 struct rte_eth_ethertype_filter *filter,
10373 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10374 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
10375 struct i40e_ethertype_filter *ethertype_filter, *node;
10376 struct i40e_ethertype_filter check_filter;
10377 struct i40e_control_filter_stats stats;
10378 uint16_t flags = 0;
10381 if (filter->queue >= pf->dev_data->nb_rx_queues) {
10382 PMD_DRV_LOG(ERR, "Invalid queue ID");
10385 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
10386 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
10388 "unsupported ether_type(0x%04x) in control packet filter.",
10389 filter->ether_type);
10392 if (filter->ether_type == RTE_ETHER_TYPE_VLAN)
10393 PMD_DRV_LOG(WARNING,
10394 "filter vlan ether_type in first tag is not supported.");
10396 /* Check if there is the filter in SW list */
10397 memset(&check_filter, 0, sizeof(check_filter));
10398 i40e_ethertype_filter_convert(filter, &check_filter);
10399 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
10400 &check_filter.input);
10402 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
10406 if (!add && !node) {
10407 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
10411 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
10412 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10413 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
10414 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10415 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10417 memset(&stats, 0, sizeof(stats));
10418 ret = i40e_aq_add_rem_control_packet_filter(hw,
10419 filter->mac_addr.addr_bytes,
10420 filter->ether_type, flags,
10421 pf->main_vsi->seid,
10422 filter->queue, add, &stats, NULL);
10425 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
10426 ret, stats.mac_etype_used, stats.etype_used,
10427 stats.mac_etype_free, stats.etype_free);
10431 /* Add or delete a filter in SW list */
10433 ethertype_filter = rte_zmalloc("ethertype_filter",
10434 sizeof(*ethertype_filter), 0);
10435 if (ethertype_filter == NULL) {
10436 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
10440 rte_memcpy(ethertype_filter, &check_filter,
10441 sizeof(check_filter));
10442 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
10444 rte_free(ethertype_filter);
10446 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
10453 * Handle operations for ethertype filter.
10456 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
10457 enum rte_filter_op filter_op,
10460 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10463 if (filter_op == RTE_ETH_FILTER_NOP)
10467 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
10472 switch (filter_op) {
10473 case RTE_ETH_FILTER_ADD:
10474 ret = i40e_ethertype_filter_set(pf,
10475 (struct rte_eth_ethertype_filter *)arg,
10478 case RTE_ETH_FILTER_DELETE:
10479 ret = i40e_ethertype_filter_set(pf,
10480 (struct rte_eth_ethertype_filter *)arg,
10484 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
10492 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
10493 enum rte_filter_type filter_type,
10494 enum rte_filter_op filter_op,
10502 switch (filter_type) {
10503 case RTE_ETH_FILTER_NONE:
10504 /* For global configuration */
10505 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
10507 case RTE_ETH_FILTER_HASH:
10508 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
10510 case RTE_ETH_FILTER_ETHERTYPE:
10511 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
10513 case RTE_ETH_FILTER_TUNNEL:
10514 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
10516 case RTE_ETH_FILTER_FDIR:
10517 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
10519 case RTE_ETH_FILTER_GENERIC:
10520 if (filter_op != RTE_ETH_FILTER_GET)
10522 *(const void **)arg = &i40e_flow_ops;
10525 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
10535 * Check and enable Extended Tag.
10536 * Enabling Extended Tag is important for 40G performance.
10539 i40e_enable_extended_tag(struct rte_eth_dev *dev)
10541 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10545 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10548 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10552 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
10553 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
10558 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10561 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10565 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
10566 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
10569 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
10570 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
10573 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
10580 * As some registers wouldn't be reset unless a global hardware reset,
10581 * hardware initialization is needed to put those registers into an
10582 * expected initial state.
10585 i40e_hw_init(struct rte_eth_dev *dev)
10587 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10589 i40e_enable_extended_tag(dev);
10591 /* clear the PF Queue Filter control register */
10592 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
10594 /* Disable symmetric hash per port */
10595 i40e_set_symmetric_hash_enable_per_port(hw, 0);
10599 * For X722 it is possible to have multiple pctypes mapped to the same flowtype
10600 * however this function will return only one highest pctype index,
10601 * which is not quite correct. This is known problem of i40e driver
10602 * and needs to be fixed later.
10604 enum i40e_filter_pctype
10605 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
10608 uint64_t pctype_mask;
10610 if (flow_type < I40E_FLOW_TYPE_MAX) {
10611 pctype_mask = adapter->pctypes_tbl[flow_type];
10612 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
10613 if (pctype_mask & (1ULL << i))
10614 return (enum i40e_filter_pctype)i;
10617 return I40E_FILTER_PCTYPE_INVALID;
10621 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
10622 enum i40e_filter_pctype pctype)
10625 uint64_t pctype_mask = 1ULL << pctype;
10627 for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
10629 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
10633 return RTE_ETH_FLOW_UNKNOWN;
10637 * On X710, performance number is far from the expectation on recent firmware
10638 * versions; on XL710, performance number is also far from the expectation on
10639 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10640 * mode is enabled and port MAC address is equal to the packet destination MAC
10641 * address. The fix for this issue may not be integrated in the following
10642 * firmware version. So the workaround in software driver is needed. It needs
10643 * to modify the initial values of 3 internal only registers for both X710 and
10644 * XL710. Note that the values for X710 or XL710 could be different, and the
10645 * workaround can be removed when it is fixed in firmware in the future.
10648 /* For both X710 and XL710 */
10649 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1 0x10000200
10650 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x203F0200
10651 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
10653 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10654 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
10657 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10658 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10661 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
10663 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
10664 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
10667 * GL_SWR_PM_UP_THR:
10668 * The value is not impacted from the link speed, its value is set according
10669 * to the total number of ports for a better pipe-monitor configuration.
10672 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10674 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10675 .device_id = (dev), \
10676 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10678 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10679 .device_id = (dev), \
10680 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10682 static const struct {
10683 uint16_t device_id;
10685 } swr_pm_table[] = {
10686 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10687 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10688 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10689 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10690 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_X722) },
10692 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10693 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10694 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10695 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10696 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10697 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10698 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10702 if (value == NULL) {
10703 PMD_DRV_LOG(ERR, "value is NULL");
10707 for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10708 if (hw->device_id == swr_pm_table[i].device_id) {
10709 *value = swr_pm_table[i].val;
10711 PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10713 hw->device_id, *value);
10722 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10724 enum i40e_status_code status;
10725 struct i40e_aq_get_phy_abilities_resp phy_ab;
10726 int ret = -ENOTSUP;
10729 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10733 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10736 rte_delay_us(100000);
10738 status = i40e_aq_get_phy_capabilities(hw, false,
10739 true, &phy_ab, NULL);
10747 i40e_configure_registers(struct i40e_hw *hw)
10753 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10754 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10755 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10761 for (i = 0; i < RTE_DIM(reg_table); i++) {
10762 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10763 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10765 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10766 else /* For X710/XL710/XXV710 */
10767 if (hw->aq.fw_maj_ver < 6)
10769 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10772 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10775 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10776 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10778 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10779 else /* For X710/XL710/XXV710 */
10781 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10784 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10787 if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10788 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10789 "GL_SWR_PM_UP_THR value fixup",
10794 reg_table[i].val = cfg_val;
10797 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10800 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10801 reg_table[i].addr);
10804 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10805 reg_table[i].addr, reg);
10806 if (reg == reg_table[i].val)
10809 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10810 reg_table[i].val, NULL);
10813 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10814 reg_table[i].val, reg_table[i].addr);
10817 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10818 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10822 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
10823 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
10824 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10826 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10831 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10832 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10836 /* Configure for double VLAN RX stripping */
10837 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10838 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10839 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10840 ret = i40e_aq_debug_write_register(hw,
10841 I40E_VSI_TSR(vsi->vsi_id),
10844 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10846 return I40E_ERR_CONFIG;
10850 /* Configure for double VLAN TX insertion */
10851 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10852 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10853 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10854 ret = i40e_aq_debug_write_register(hw,
10855 I40E_VSI_L2TAGSTXVALID(
10856 vsi->vsi_id), reg, NULL);
10859 "Failed to update VSI_L2TAGSTXVALID[%d]",
10861 return I40E_ERR_CONFIG;
10869 * i40e_aq_add_mirror_rule
10870 * @hw: pointer to the hardware structure
10871 * @seid: VEB seid to add mirror rule to
10872 * @dst_id: destination vsi seid
10873 * @entries: Buffer which contains the entities to be mirrored
10874 * @count: number of entities contained in the buffer
10875 * @rule_id:the rule_id of the rule to be added
10877 * Add a mirror rule for a given veb.
10880 static enum i40e_status_code
10881 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10882 uint16_t seid, uint16_t dst_id,
10883 uint16_t rule_type, uint16_t *entries,
10884 uint16_t count, uint16_t *rule_id)
10886 struct i40e_aq_desc desc;
10887 struct i40e_aqc_add_delete_mirror_rule cmd;
10888 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10889 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10892 enum i40e_status_code status;
10894 i40e_fill_default_direct_cmd_desc(&desc,
10895 i40e_aqc_opc_add_mirror_rule);
10896 memset(&cmd, 0, sizeof(cmd));
10898 buff_len = sizeof(uint16_t) * count;
10899 desc.datalen = rte_cpu_to_le_16(buff_len);
10901 desc.flags |= rte_cpu_to_le_16(
10902 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10903 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10904 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10905 cmd.num_entries = rte_cpu_to_le_16(count);
10906 cmd.seid = rte_cpu_to_le_16(seid);
10907 cmd.destination = rte_cpu_to_le_16(dst_id);
10909 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10910 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10912 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10913 hw->aq.asq_last_status, resp->rule_id,
10914 resp->mirror_rules_used, resp->mirror_rules_free);
10915 *rule_id = rte_le_to_cpu_16(resp->rule_id);
10921 * i40e_aq_del_mirror_rule
10922 * @hw: pointer to the hardware structure
10923 * @seid: VEB seid to add mirror rule to
10924 * @entries: Buffer which contains the entities to be mirrored
10925 * @count: number of entities contained in the buffer
10926 * @rule_id:the rule_id of the rule to be delete
10928 * Delete a mirror rule for a given veb.
10931 static enum i40e_status_code
10932 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10933 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10934 uint16_t count, uint16_t rule_id)
10936 struct i40e_aq_desc desc;
10937 struct i40e_aqc_add_delete_mirror_rule cmd;
10938 uint16_t buff_len = 0;
10939 enum i40e_status_code status;
10942 i40e_fill_default_direct_cmd_desc(&desc,
10943 i40e_aqc_opc_delete_mirror_rule);
10944 memset(&cmd, 0, sizeof(cmd));
10945 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10946 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10948 cmd.num_entries = count;
10949 buff_len = sizeof(uint16_t) * count;
10950 desc.datalen = rte_cpu_to_le_16(buff_len);
10951 buff = (void *)entries;
10953 /* rule id is filled in destination field for deleting mirror rule */
10954 cmd.destination = rte_cpu_to_le_16(rule_id);
10956 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10957 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10958 cmd.seid = rte_cpu_to_le_16(seid);
10960 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10961 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10967 * i40e_mirror_rule_set
10968 * @dev: pointer to the hardware structure
10969 * @mirror_conf: mirror rule info
10970 * @sw_id: mirror rule's sw_id
10971 * @on: enable/disable
10973 * set a mirror rule.
10977 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10978 struct rte_eth_mirror_conf *mirror_conf,
10979 uint8_t sw_id, uint8_t on)
10981 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10982 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10983 struct i40e_mirror_rule *it, *mirr_rule = NULL;
10984 struct i40e_mirror_rule *parent = NULL;
10985 uint16_t seid, dst_seid, rule_id;
10989 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10991 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10993 "mirror rule can not be configured without veb or vfs.");
10996 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10997 PMD_DRV_LOG(ERR, "mirror table is full.");
11000 if (mirror_conf->dst_pool > pf->vf_num) {
11001 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
11002 mirror_conf->dst_pool);
11006 seid = pf->main_vsi->veb->seid;
11008 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
11009 if (sw_id <= it->index) {
11015 if (mirr_rule && sw_id == mirr_rule->index) {
11017 PMD_DRV_LOG(ERR, "mirror rule exists.");
11020 ret = i40e_aq_del_mirror_rule(hw, seid,
11021 mirr_rule->rule_type,
11022 mirr_rule->entries,
11023 mirr_rule->num_entries, mirr_rule->id);
11026 "failed to remove mirror rule: ret = %d, aq_err = %d.",
11027 ret, hw->aq.asq_last_status);
11030 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
11031 rte_free(mirr_rule);
11032 pf->nb_mirror_rule--;
11036 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
11040 mirr_rule = rte_zmalloc("i40e_mirror_rule",
11041 sizeof(struct i40e_mirror_rule) , 0);
11043 PMD_DRV_LOG(ERR, "failed to allocate memory");
11044 return I40E_ERR_NO_MEMORY;
11046 switch (mirror_conf->rule_type) {
11047 case ETH_MIRROR_VLAN:
11048 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
11049 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
11050 mirr_rule->entries[j] =
11051 mirror_conf->vlan.vlan_id[i];
11056 PMD_DRV_LOG(ERR, "vlan is not specified.");
11057 rte_free(mirr_rule);
11060 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
11062 case ETH_MIRROR_VIRTUAL_POOL_UP:
11063 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
11064 /* check if the specified pool bit is out of range */
11065 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
11066 PMD_DRV_LOG(ERR, "pool mask is out of range.");
11067 rte_free(mirr_rule);
11070 for (i = 0, j = 0; i < pf->vf_num; i++) {
11071 if (mirror_conf->pool_mask & (1ULL << i)) {
11072 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
11076 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
11077 /* add pf vsi to entries */
11078 mirr_rule->entries[j] = pf->main_vsi_seid;
11082 PMD_DRV_LOG(ERR, "pool is not specified.");
11083 rte_free(mirr_rule);
11086 /* egress and ingress in aq commands means from switch but not port */
11087 mirr_rule->rule_type =
11088 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
11089 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
11090 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
11092 case ETH_MIRROR_UPLINK_PORT:
11093 /* egress and ingress in aq commands means from switch but not port*/
11094 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
11096 case ETH_MIRROR_DOWNLINK_PORT:
11097 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
11100 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
11101 mirror_conf->rule_type);
11102 rte_free(mirr_rule);
11106 /* If the dst_pool is equal to vf_num, consider it as PF */
11107 if (mirror_conf->dst_pool == pf->vf_num)
11108 dst_seid = pf->main_vsi_seid;
11110 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
11112 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
11113 mirr_rule->rule_type, mirr_rule->entries,
11117 "failed to add mirror rule: ret = %d, aq_err = %d.",
11118 ret, hw->aq.asq_last_status);
11119 rte_free(mirr_rule);
11123 mirr_rule->index = sw_id;
11124 mirr_rule->num_entries = j;
11125 mirr_rule->id = rule_id;
11126 mirr_rule->dst_vsi_seid = dst_seid;
11129 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
11131 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
11133 pf->nb_mirror_rule++;
11138 * i40e_mirror_rule_reset
11139 * @dev: pointer to the device
11140 * @sw_id: mirror rule's sw_id
11142 * reset a mirror rule.
11146 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
11148 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11149 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11150 struct i40e_mirror_rule *it, *mirr_rule = NULL;
11154 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
11156 seid = pf->main_vsi->veb->seid;
11158 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
11159 if (sw_id == it->index) {
11165 ret = i40e_aq_del_mirror_rule(hw, seid,
11166 mirr_rule->rule_type,
11167 mirr_rule->entries,
11168 mirr_rule->num_entries, mirr_rule->id);
11171 "failed to remove mirror rule: status = %d, aq_err = %d.",
11172 ret, hw->aq.asq_last_status);
11175 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
11176 rte_free(mirr_rule);
11177 pf->nb_mirror_rule--;
11179 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
11186 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
11188 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11189 uint64_t systim_cycles;
11191 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
11192 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
11195 return systim_cycles;
11199 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
11201 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11202 uint64_t rx_tstamp;
11204 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
11205 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
11212 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
11214 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11215 uint64_t tx_tstamp;
11217 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
11218 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
11225 i40e_start_timecounters(struct rte_eth_dev *dev)
11227 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11228 struct i40e_adapter *adapter = dev->data->dev_private;
11229 struct rte_eth_link link;
11230 uint32_t tsync_inc_l;
11231 uint32_t tsync_inc_h;
11233 /* Get current link speed. */
11234 i40e_dev_link_update(dev, 1);
11235 rte_eth_linkstatus_get(dev, &link);
11237 switch (link.link_speed) {
11238 case ETH_SPEED_NUM_40G:
11239 case ETH_SPEED_NUM_25G:
11240 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
11241 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
11243 case ETH_SPEED_NUM_10G:
11244 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
11245 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
11247 case ETH_SPEED_NUM_1G:
11248 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
11249 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
11256 /* Set the timesync increment value. */
11257 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
11258 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
11260 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
11261 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
11262 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
11264 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
11265 adapter->systime_tc.cc_shift = 0;
11266 adapter->systime_tc.nsec_mask = 0;
11268 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
11269 adapter->rx_tstamp_tc.cc_shift = 0;
11270 adapter->rx_tstamp_tc.nsec_mask = 0;
11272 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
11273 adapter->tx_tstamp_tc.cc_shift = 0;
11274 adapter->tx_tstamp_tc.nsec_mask = 0;
11278 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
11280 struct i40e_adapter *adapter = dev->data->dev_private;
11282 adapter->systime_tc.nsec += delta;
11283 adapter->rx_tstamp_tc.nsec += delta;
11284 adapter->tx_tstamp_tc.nsec += delta;
11290 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
11293 struct i40e_adapter *adapter = dev->data->dev_private;
11295 ns = rte_timespec_to_ns(ts);
11297 /* Set the timecounters to a new value. */
11298 adapter->systime_tc.nsec = ns;
11299 adapter->rx_tstamp_tc.nsec = ns;
11300 adapter->tx_tstamp_tc.nsec = ns;
11306 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
11308 uint64_t ns, systime_cycles;
11309 struct i40e_adapter *adapter = dev->data->dev_private;
11311 systime_cycles = i40e_read_systime_cyclecounter(dev);
11312 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
11313 *ts = rte_ns_to_timespec(ns);
11319 i40e_timesync_enable(struct rte_eth_dev *dev)
11321 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11322 uint32_t tsync_ctl_l;
11323 uint32_t tsync_ctl_h;
11325 /* Stop the timesync system time. */
11326 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
11327 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11328 /* Reset the timesync system time value. */
11329 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
11330 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
11332 i40e_start_timecounters(dev);
11334 /* Clear timesync registers. */
11335 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11336 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
11337 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
11338 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
11339 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
11340 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
11342 /* Enable timestamping of PTP packets. */
11343 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
11344 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
11346 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
11347 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
11348 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
11350 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
11351 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
11357 i40e_timesync_disable(struct rte_eth_dev *dev)
11359 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11360 uint32_t tsync_ctl_l;
11361 uint32_t tsync_ctl_h;
11363 /* Disable timestamping of transmitted PTP packets. */
11364 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
11365 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
11367 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
11368 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
11370 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
11371 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
11373 /* Reset the timesync increment value. */
11374 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
11375 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11381 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
11382 struct timespec *timestamp, uint32_t flags)
11384 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11385 struct i40e_adapter *adapter = dev->data->dev_private;
11386 uint32_t sync_status;
11387 uint32_t index = flags & 0x03;
11388 uint64_t rx_tstamp_cycles;
11391 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
11392 if ((sync_status & (1 << index)) == 0)
11395 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
11396 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
11397 *timestamp = rte_ns_to_timespec(ns);
11403 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
11404 struct timespec *timestamp)
11406 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11407 struct i40e_adapter *adapter = dev->data->dev_private;
11408 uint32_t sync_status;
11409 uint64_t tx_tstamp_cycles;
11412 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11413 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
11416 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
11417 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
11418 *timestamp = rte_ns_to_timespec(ns);
11424 * i40e_parse_dcb_configure - parse dcb configure from user
11425 * @dev: the device being configured
11426 * @dcb_cfg: pointer of the result of parse
11427 * @*tc_map: bit map of enabled traffic classes
11429 * Returns 0 on success, negative value on failure
11432 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
11433 struct i40e_dcbx_config *dcb_cfg,
11436 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
11437 uint8_t i, tc_bw, bw_lf;
11439 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
11441 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
11442 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
11443 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
11447 /* assume each tc has the same bw */
11448 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
11449 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11450 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
11451 /* to ensure the sum of tcbw is equal to 100 */
11452 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
11453 for (i = 0; i < bw_lf; i++)
11454 dcb_cfg->etscfg.tcbwtable[i]++;
11456 /* assume each tc has the same Transmission Selection Algorithm */
11457 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11458 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
11460 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11461 dcb_cfg->etscfg.prioritytable[i] =
11462 dcb_rx_conf->dcb_tc[i];
11464 /* FW needs one App to configure HW */
11465 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
11466 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
11467 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
11468 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
11470 if (dcb_rx_conf->nb_tcs == 0)
11471 *tc_map = 1; /* tc0 only */
11473 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
11475 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
11476 dcb_cfg->pfc.willing = 0;
11477 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
11478 dcb_cfg->pfc.pfcenable = *tc_map;
11484 static enum i40e_status_code
11485 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
11486 struct i40e_aqc_vsi_properties_data *info,
11487 uint8_t enabled_tcmap)
11489 enum i40e_status_code ret;
11490 int i, total_tc = 0;
11491 uint16_t qpnum_per_tc, bsf, qp_idx;
11492 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
11493 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
11494 uint16_t used_queues;
11496 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
11497 if (ret != I40E_SUCCESS)
11500 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11501 if (enabled_tcmap & (1 << i))
11506 vsi->enabled_tc = enabled_tcmap;
11508 /* different VSI has different queues assigned */
11509 if (vsi->type == I40E_VSI_MAIN)
11510 used_queues = dev_data->nb_rx_queues -
11511 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11512 else if (vsi->type == I40E_VSI_VMDQ2)
11513 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11515 PMD_INIT_LOG(ERR, "unsupported VSI type.");
11516 return I40E_ERR_NO_AVAILABLE_VSI;
11519 qpnum_per_tc = used_queues / total_tc;
11520 /* Number of queues per enabled TC */
11521 if (qpnum_per_tc == 0) {
11522 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
11523 return I40E_ERR_INVALID_QP_ID;
11525 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
11526 I40E_MAX_Q_PER_TC);
11527 bsf = rte_bsf32(qpnum_per_tc);
11530 * Configure TC and queue mapping parameters, for enabled TC,
11531 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
11532 * default queue will serve it.
11535 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11536 if (vsi->enabled_tc & (1 << i)) {
11537 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
11538 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
11539 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
11540 qp_idx += qpnum_per_tc;
11542 info->tc_mapping[i] = 0;
11545 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
11546 if (vsi->type == I40E_VSI_SRIOV) {
11547 info->mapping_flags |=
11548 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
11549 for (i = 0; i < vsi->nb_qps; i++)
11550 info->queue_mapping[i] =
11551 rte_cpu_to_le_16(vsi->base_queue + i);
11553 info->mapping_flags |=
11554 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
11555 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
11557 info->valid_sections |=
11558 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
11560 return I40E_SUCCESS;
11564 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
11565 * @veb: VEB to be configured
11566 * @tc_map: enabled TC bitmap
11568 * Returns 0 on success, negative value on failure
11570 static enum i40e_status_code
11571 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
11573 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
11574 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
11575 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
11576 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
11577 enum i40e_status_code ret = I40E_SUCCESS;
11581 /* Check if enabled_tc is same as existing or new TCs */
11582 if (veb->enabled_tc == tc_map)
11585 /* configure tc bandwidth */
11586 memset(&veb_bw, 0, sizeof(veb_bw));
11587 veb_bw.tc_valid_bits = tc_map;
11588 /* Enable ETS TCs with equal BW Share for now across all VSIs */
11589 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11590 if (tc_map & BIT_ULL(i))
11591 veb_bw.tc_bw_share_credits[i] = 1;
11593 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
11597 "AQ command Config switch_comp BW allocation per TC failed = %d",
11598 hw->aq.asq_last_status);
11602 memset(&ets_query, 0, sizeof(ets_query));
11603 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
11605 if (ret != I40E_SUCCESS) {
11607 "Failed to get switch_comp ETS configuration %u",
11608 hw->aq.asq_last_status);
11611 memset(&bw_query, 0, sizeof(bw_query));
11612 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
11614 if (ret != I40E_SUCCESS) {
11616 "Failed to get switch_comp bandwidth configuration %u",
11617 hw->aq.asq_last_status);
11621 /* store and print out BW info */
11622 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
11623 veb->bw_info.bw_max = ets_query.tc_bw_max;
11624 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
11625 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
11626 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
11627 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
11628 I40E_16_BIT_WIDTH);
11629 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11630 veb->bw_info.bw_ets_share_credits[i] =
11631 bw_query.tc_bw_share_credits[i];
11632 veb->bw_info.bw_ets_credits[i] =
11633 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
11634 /* 4 bits per TC, 4th bit is reserved */
11635 veb->bw_info.bw_ets_max[i] =
11636 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
11637 RTE_LEN2MASK(3, uint8_t));
11638 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
11639 veb->bw_info.bw_ets_share_credits[i]);
11640 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11641 veb->bw_info.bw_ets_credits[i]);
11642 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11643 veb->bw_info.bw_ets_max[i]);
11646 veb->enabled_tc = tc_map;
11653 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11654 * @vsi: VSI to be configured
11655 * @tc_map: enabled TC bitmap
11657 * Returns 0 on success, negative value on failure
11659 static enum i40e_status_code
11660 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11662 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11663 struct i40e_vsi_context ctxt;
11664 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11665 enum i40e_status_code ret = I40E_SUCCESS;
11668 /* Check if enabled_tc is same as existing or new TCs */
11669 if (vsi->enabled_tc == tc_map)
11672 /* configure tc bandwidth */
11673 memset(&bw_data, 0, sizeof(bw_data));
11674 bw_data.tc_valid_bits = tc_map;
11675 /* Enable ETS TCs with equal BW Share for now across all VSIs */
11676 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11677 if (tc_map & BIT_ULL(i))
11678 bw_data.tc_bw_credits[i] = 1;
11680 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11683 "AQ command Config VSI BW allocation per TC failed = %d",
11684 hw->aq.asq_last_status);
11687 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11688 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11690 /* Update Queue Pairs Mapping for currently enabled UPs */
11691 ctxt.seid = vsi->seid;
11692 ctxt.pf_num = hw->pf_id;
11694 ctxt.uplink_seid = vsi->uplink_seid;
11695 ctxt.info = vsi->info;
11697 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11701 /* Update the VSI after updating the VSI queue-mapping information */
11702 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11704 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11705 hw->aq.asq_last_status);
11708 /* update the local VSI info with updated queue map */
11709 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11710 sizeof(vsi->info.tc_mapping));
11711 rte_memcpy(&vsi->info.queue_mapping,
11712 &ctxt.info.queue_mapping,
11713 sizeof(vsi->info.queue_mapping));
11714 vsi->info.mapping_flags = ctxt.info.mapping_flags;
11715 vsi->info.valid_sections = 0;
11717 /* query and update current VSI BW information */
11718 ret = i40e_vsi_get_bw_config(vsi);
11721 "Failed updating vsi bw info, err %s aq_err %s",
11722 i40e_stat_str(hw, ret),
11723 i40e_aq_str(hw, hw->aq.asq_last_status));
11727 vsi->enabled_tc = tc_map;
11734 * i40e_dcb_hw_configure - program the dcb setting to hw
11735 * @pf: pf the configuration is taken on
11736 * @new_cfg: new configuration
11737 * @tc_map: enabled TC bitmap
11739 * Returns 0 on success, negative value on failure
11741 static enum i40e_status_code
11742 i40e_dcb_hw_configure(struct i40e_pf *pf,
11743 struct i40e_dcbx_config *new_cfg,
11746 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11747 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11748 struct i40e_vsi *main_vsi = pf->main_vsi;
11749 struct i40e_vsi_list *vsi_list;
11750 enum i40e_status_code ret;
11754 /* Use the FW API if FW > v4.4*/
11755 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11756 (hw->aq.fw_maj_ver >= 5))) {
11758 "FW < v4.4, can not use FW LLDP API to configure DCB");
11759 return I40E_ERR_FIRMWARE_API_VERSION;
11762 /* Check if need reconfiguration */
11763 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11764 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11765 return I40E_SUCCESS;
11768 /* Copy the new config to the current config */
11769 *old_cfg = *new_cfg;
11770 old_cfg->etsrec = old_cfg->etscfg;
11771 ret = i40e_set_dcb_config(hw);
11773 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11774 i40e_stat_str(hw, ret),
11775 i40e_aq_str(hw, hw->aq.asq_last_status));
11778 /* set receive Arbiter to RR mode and ETS scheme by default */
11779 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11780 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11781 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
11782 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11783 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11784 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11785 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11786 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11787 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11788 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11789 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11790 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11791 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11793 /* get local mib to check whether it is configured correctly */
11795 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11796 /* Get Local DCB Config */
11797 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11798 &hw->local_dcbx_config);
11800 /* if Veb is created, need to update TC of it at first */
11801 if (main_vsi->veb) {
11802 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11804 PMD_INIT_LOG(WARNING,
11805 "Failed configuring TC for VEB seid=%d",
11806 main_vsi->veb->seid);
11808 /* Update each VSI */
11809 i40e_vsi_config_tc(main_vsi, tc_map);
11810 if (main_vsi->veb) {
11811 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11812 /* Beside main VSI and VMDQ VSIs, only enable default
11813 * TC for other VSIs
11815 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11816 ret = i40e_vsi_config_tc(vsi_list->vsi,
11819 ret = i40e_vsi_config_tc(vsi_list->vsi,
11820 I40E_DEFAULT_TCMAP);
11822 PMD_INIT_LOG(WARNING,
11823 "Failed configuring TC for VSI seid=%d",
11824 vsi_list->vsi->seid);
11828 return I40E_SUCCESS;
11832 * i40e_dcb_init_configure - initial dcb config
11833 * @dev: device being configured
11834 * @sw_dcb: indicate whether dcb is sw configured or hw offload
11836 * Returns 0 on success, negative value on failure
11839 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11841 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11842 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11845 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11846 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11850 /* DCB initialization:
11851 * Update DCB configuration from the Firmware and configure
11852 * LLDP MIB change event.
11854 if (sw_dcb == TRUE) {
11855 /* Stopping lldp is necessary for DPDK, but it will cause
11856 * DCB init failed. For i40e_init_dcb(), the prerequisite
11857 * for successful initialization of DCB is that LLDP is
11858 * enabled. So it is needed to start lldp before DCB init
11859 * and stop it after initialization.
11861 ret = i40e_aq_start_lldp(hw, true, NULL);
11862 if (ret != I40E_SUCCESS)
11863 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11865 ret = i40e_init_dcb(hw, true);
11866 /* If lldp agent is stopped, the return value from
11867 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11868 * adminq status. Otherwise, it should return success.
11870 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11871 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11872 memset(&hw->local_dcbx_config, 0,
11873 sizeof(struct i40e_dcbx_config));
11874 /* set dcb default configuration */
11875 hw->local_dcbx_config.etscfg.willing = 0;
11876 hw->local_dcbx_config.etscfg.maxtcs = 0;
11877 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11878 hw->local_dcbx_config.etscfg.tsatable[0] =
11880 /* all UPs mapping to TC0 */
11881 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11882 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11883 hw->local_dcbx_config.etsrec =
11884 hw->local_dcbx_config.etscfg;
11885 hw->local_dcbx_config.pfc.willing = 0;
11886 hw->local_dcbx_config.pfc.pfccap =
11887 I40E_MAX_TRAFFIC_CLASS;
11888 /* FW needs one App to configure HW */
11889 hw->local_dcbx_config.numapps = 1;
11890 hw->local_dcbx_config.app[0].selector =
11891 I40E_APP_SEL_ETHTYPE;
11892 hw->local_dcbx_config.app[0].priority = 3;
11893 hw->local_dcbx_config.app[0].protocolid =
11894 I40E_APP_PROTOID_FCOE;
11895 ret = i40e_set_dcb_config(hw);
11898 "default dcb config fails. err = %d, aq_err = %d.",
11899 ret, hw->aq.asq_last_status);
11904 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11905 ret, hw->aq.asq_last_status);
11909 if (i40e_need_stop_lldp(dev)) {
11910 ret = i40e_aq_stop_lldp(hw, true, true, NULL);
11911 if (ret != I40E_SUCCESS)
11912 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
11915 ret = i40e_aq_start_lldp(hw, true, NULL);
11916 if (ret != I40E_SUCCESS)
11917 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11919 ret = i40e_init_dcb(hw, true);
11921 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11923 "HW doesn't support DCBX offload.");
11928 "DCBX configuration failed, err = %d, aq_err = %d.",
11929 ret, hw->aq.asq_last_status);
11937 * i40e_dcb_setup - setup dcb related config
11938 * @dev: device being configured
11940 * Returns 0 on success, negative value on failure
11943 i40e_dcb_setup(struct rte_eth_dev *dev)
11945 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11946 struct i40e_dcbx_config dcb_cfg;
11947 uint8_t tc_map = 0;
11950 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11951 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11955 if (pf->vf_num != 0)
11956 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11958 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11960 PMD_INIT_LOG(ERR, "invalid dcb config");
11963 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11965 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11973 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11974 struct rte_eth_dcb_info *dcb_info)
11976 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11977 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11978 struct i40e_vsi *vsi = pf->main_vsi;
11979 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11980 uint16_t bsf, tc_mapping;
11983 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11984 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11986 dcb_info->nb_tcs = 1;
11987 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11988 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11989 for (i = 0; i < dcb_info->nb_tcs; i++)
11990 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11992 /* get queue mapping if vmdq is disabled */
11993 if (!pf->nb_cfg_vmdq_vsi) {
11994 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11995 if (!(vsi->enabled_tc & (1 << i)))
11997 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11998 dcb_info->tc_queue.tc_rxq[j][i].base =
11999 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
12000 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
12001 dcb_info->tc_queue.tc_txq[j][i].base =
12002 dcb_info->tc_queue.tc_rxq[j][i].base;
12003 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
12004 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
12005 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
12006 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
12007 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
12012 /* get queue mapping if vmdq is enabled */
12014 vsi = pf->vmdq[j].vsi;
12015 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
12016 if (!(vsi->enabled_tc & (1 << i)))
12018 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
12019 dcb_info->tc_queue.tc_rxq[j][i].base =
12020 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
12021 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
12022 dcb_info->tc_queue.tc_txq[j][i].base =
12023 dcb_info->tc_queue.tc_rxq[j][i].base;
12024 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
12025 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
12026 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
12027 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
12028 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
12031 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
12036 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
12038 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
12039 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
12040 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12041 uint16_t msix_intr;
12043 msix_intr = intr_handle->intr_vec[queue_id];
12044 if (msix_intr == I40E_MISC_VEC_ID)
12045 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
12046 I40E_PFINT_DYN_CTL0_INTENA_MASK |
12047 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
12048 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
12051 I40E_PFINT_DYN_CTLN(msix_intr -
12052 I40E_RX_VEC_START),
12053 I40E_PFINT_DYN_CTLN_INTENA_MASK |
12054 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
12055 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
12057 I40E_WRITE_FLUSH(hw);
12058 rte_intr_ack(&pci_dev->intr_handle);
12064 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
12066 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
12067 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
12068 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12069 uint16_t msix_intr;
12071 msix_intr = intr_handle->intr_vec[queue_id];
12072 if (msix_intr == I40E_MISC_VEC_ID)
12073 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
12074 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
12077 I40E_PFINT_DYN_CTLN(msix_intr -
12078 I40E_RX_VEC_START),
12079 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
12080 I40E_WRITE_FLUSH(hw);
12086 * This function is used to check if the register is valid.
12087 * Below is the valid registers list for X722 only:
12091 * 0x208e00--0x209000
12092 * 0x20be00--0x20c000
12093 * 0x263c00--0x264000
12094 * 0x265c00--0x266000
12096 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset)
12098 if ((type != I40E_MAC_X722) &&
12099 ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) ||
12100 (reg_offset >= 0x38700 && reg_offset <= 0x38a00) ||
12101 (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) ||
12102 (reg_offset >= 0x208e00 && reg_offset <= 0x209000) ||
12103 (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) ||
12104 (reg_offset >= 0x263c00 && reg_offset <= 0x264000) ||
12105 (reg_offset >= 0x265c00 && reg_offset <= 0x266000)))
12111 static int i40e_get_regs(struct rte_eth_dev *dev,
12112 struct rte_dev_reg_info *regs)
12114 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12115 uint32_t *ptr_data = regs->data;
12116 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
12117 const struct i40e_reg_info *reg_info;
12119 if (ptr_data == NULL) {
12120 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
12121 regs->width = sizeof(uint32_t);
12125 /* The first few registers have to be read using AQ operations */
12127 while (i40e_regs_adminq[reg_idx].name) {
12128 reg_info = &i40e_regs_adminq[reg_idx++];
12129 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
12131 arr_idx2 <= reg_info->count2;
12133 reg_offset = arr_idx * reg_info->stride1 +
12134 arr_idx2 * reg_info->stride2;
12135 reg_offset += reg_info->base_addr;
12136 ptr_data[reg_offset >> 2] =
12137 i40e_read_rx_ctl(hw, reg_offset);
12141 /* The remaining registers can be read using primitives */
12143 while (i40e_regs_others[reg_idx].name) {
12144 reg_info = &i40e_regs_others[reg_idx++];
12145 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
12147 arr_idx2 <= reg_info->count2;
12149 reg_offset = arr_idx * reg_info->stride1 +
12150 arr_idx2 * reg_info->stride2;
12151 reg_offset += reg_info->base_addr;
12152 if (!i40e_valid_regs(hw->mac.type, reg_offset))
12153 ptr_data[reg_offset >> 2] = 0;
12155 ptr_data[reg_offset >> 2] =
12156 I40E_READ_REG(hw, reg_offset);
12163 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
12165 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12167 /* Convert word count to byte count */
12168 return hw->nvm.sr_size << 1;
12171 static int i40e_get_eeprom(struct rte_eth_dev *dev,
12172 struct rte_dev_eeprom_info *eeprom)
12174 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12175 uint16_t *data = eeprom->data;
12176 uint16_t offset, length, cnt_words;
12179 offset = eeprom->offset >> 1;
12180 length = eeprom->length >> 1;
12181 cnt_words = length;
12183 if (offset > hw->nvm.sr_size ||
12184 offset + length > hw->nvm.sr_size) {
12185 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
12189 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
12191 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
12192 if (ret_code != I40E_SUCCESS || cnt_words != length) {
12193 PMD_DRV_LOG(ERR, "EEPROM read failed.");
12200 static int i40e_get_module_info(struct rte_eth_dev *dev,
12201 struct rte_eth_dev_module_info *modinfo)
12203 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12204 uint32_t sff8472_comp = 0;
12205 uint32_t sff8472_swap = 0;
12206 uint32_t sff8636_rev = 0;
12207 i40e_status status;
12210 /* Check if firmware supports reading module EEPROM. */
12211 if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
12213 "Module EEPROM memory read not supported. "
12214 "Please update the NVM image.\n");
12218 status = i40e_update_link_info(hw);
12222 if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
12224 "Cannot read module EEPROM memory. "
12225 "No module connected.\n");
12229 type = hw->phy.link_info.module_type[0];
12232 case I40E_MODULE_TYPE_SFP:
12233 status = i40e_aq_get_phy_register(hw,
12234 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12235 I40E_I2C_EEPROM_DEV_ADDR, 1,
12236 I40E_MODULE_SFF_8472_COMP,
12237 &sff8472_comp, NULL);
12241 status = i40e_aq_get_phy_register(hw,
12242 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12243 I40E_I2C_EEPROM_DEV_ADDR, 1,
12244 I40E_MODULE_SFF_8472_SWAP,
12245 &sff8472_swap, NULL);
12249 /* Check if the module requires address swap to access
12250 * the other EEPROM memory page.
12252 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
12253 PMD_DRV_LOG(WARNING,
12254 "Module address swap to access "
12255 "page 0xA2 is not supported.\n");
12256 modinfo->type = RTE_ETH_MODULE_SFF_8079;
12257 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
12258 } else if (sff8472_comp == 0x00) {
12259 /* Module is not SFF-8472 compliant */
12260 modinfo->type = RTE_ETH_MODULE_SFF_8079;
12261 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
12263 modinfo->type = RTE_ETH_MODULE_SFF_8472;
12264 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
12267 case I40E_MODULE_TYPE_QSFP_PLUS:
12268 /* Read from memory page 0. */
12269 status = i40e_aq_get_phy_register(hw,
12270 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12272 I40E_MODULE_REVISION_ADDR,
12273 &sff8636_rev, NULL);
12276 /* Determine revision compliance byte */
12277 if (sff8636_rev > 0x02) {
12278 /* Module is SFF-8636 compliant */
12279 modinfo->type = RTE_ETH_MODULE_SFF_8636;
12280 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12282 modinfo->type = RTE_ETH_MODULE_SFF_8436;
12283 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12286 case I40E_MODULE_TYPE_QSFP28:
12287 modinfo->type = RTE_ETH_MODULE_SFF_8636;
12288 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12291 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
12297 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
12298 struct rte_dev_eeprom_info *info)
12300 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12301 bool is_sfp = false;
12302 i40e_status status;
12304 uint32_t value = 0;
12307 if (!info || !info->length || !info->data)
12310 if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
12314 for (i = 0; i < info->length; i++) {
12315 u32 offset = i + info->offset;
12316 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
12318 /* Check if we need to access the other memory page */
12320 if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
12321 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
12322 addr = I40E_I2C_EEPROM_DEV_ADDR2;
12325 while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
12326 /* Compute memory page number and offset. */
12327 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
12331 status = i40e_aq_get_phy_register(hw,
12332 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12333 addr, 1, offset, &value, NULL);
12336 data[i] = (uint8_t)value;
12341 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
12342 struct rte_ether_addr *mac_addr)
12344 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12345 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12346 struct i40e_vsi *vsi = pf->main_vsi;
12347 struct i40e_mac_filter_info mac_filter;
12348 struct i40e_mac_filter *f;
12351 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
12352 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
12356 TAILQ_FOREACH(f, &vsi->mac_list, next) {
12357 if (rte_is_same_ether_addr(&pf->dev_addr,
12358 &f->mac_info.mac_addr))
12363 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
12367 mac_filter = f->mac_info;
12368 ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
12369 if (ret != I40E_SUCCESS) {
12370 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
12373 memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
12374 ret = i40e_vsi_add_mac(vsi, &mac_filter);
12375 if (ret != I40E_SUCCESS) {
12376 PMD_DRV_LOG(ERR, "Failed to add mac filter");
12379 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
12381 ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
12382 mac_addr->addr_bytes, NULL);
12383 if (ret != I40E_SUCCESS) {
12384 PMD_DRV_LOG(ERR, "Failed to change mac");
12392 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
12394 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12395 struct rte_eth_dev_data *dev_data = pf->dev_data;
12396 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
12399 /* check if mtu is within the allowed range */
12400 if (mtu < RTE_ETHER_MIN_MTU || frame_size > I40E_FRAME_SIZE_MAX)
12403 /* mtu setting is forbidden if port is start */
12404 if (dev_data->dev_started) {
12405 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
12406 dev_data->port_id);
12410 if (frame_size > RTE_ETHER_MAX_LEN)
12411 dev_data->dev_conf.rxmode.offloads |=
12412 DEV_RX_OFFLOAD_JUMBO_FRAME;
12414 dev_data->dev_conf.rxmode.offloads &=
12415 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
12417 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
12422 /* Restore ethertype filter */
12424 i40e_ethertype_filter_restore(struct i40e_pf *pf)
12426 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12427 struct i40e_ethertype_filter_list
12428 *ethertype_list = &pf->ethertype.ethertype_list;
12429 struct i40e_ethertype_filter *f;
12430 struct i40e_control_filter_stats stats;
12433 TAILQ_FOREACH(f, ethertype_list, rules) {
12435 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
12436 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
12437 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
12438 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
12439 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
12441 memset(&stats, 0, sizeof(stats));
12442 i40e_aq_add_rem_control_packet_filter(hw,
12443 f->input.mac_addr.addr_bytes,
12444 f->input.ether_type,
12445 flags, pf->main_vsi->seid,
12446 f->queue, 1, &stats, NULL);
12448 PMD_DRV_LOG(INFO, "Ethertype filter:"
12449 " mac_etype_used = %u, etype_used = %u,"
12450 " mac_etype_free = %u, etype_free = %u",
12451 stats.mac_etype_used, stats.etype_used,
12452 stats.mac_etype_free, stats.etype_free);
12455 /* Restore tunnel filter */
12457 i40e_tunnel_filter_restore(struct i40e_pf *pf)
12459 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12460 struct i40e_vsi *vsi;
12461 struct i40e_pf_vf *vf;
12462 struct i40e_tunnel_filter_list
12463 *tunnel_list = &pf->tunnel.tunnel_list;
12464 struct i40e_tunnel_filter *f;
12465 struct i40e_aqc_cloud_filters_element_bb cld_filter;
12466 bool big_buffer = 0;
12468 TAILQ_FOREACH(f, tunnel_list, rules) {
12470 vsi = pf->main_vsi;
12472 vf = &pf->vfs[f->vf_id];
12475 memset(&cld_filter, 0, sizeof(cld_filter));
12476 rte_ether_addr_copy((struct rte_ether_addr *)
12477 &f->input.outer_mac,
12478 (struct rte_ether_addr *)&cld_filter.element.outer_mac);
12479 rte_ether_addr_copy((struct rte_ether_addr *)
12480 &f->input.inner_mac,
12481 (struct rte_ether_addr *)&cld_filter.element.inner_mac);
12482 cld_filter.element.inner_vlan = f->input.inner_vlan;
12483 cld_filter.element.flags = f->input.flags;
12484 cld_filter.element.tenant_id = f->input.tenant_id;
12485 cld_filter.element.queue_number = f->queue;
12486 rte_memcpy(cld_filter.general_fields,
12487 f->input.general_fields,
12488 sizeof(f->input.general_fields));
12490 if (((f->input.flags &
12491 I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
12492 I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
12494 I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
12495 I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
12497 I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
12498 I40E_AQC_ADD_CLOUD_FILTER_0X10))
12502 i40e_aq_add_cloud_filters_bb(hw,
12503 vsi->seid, &cld_filter, 1);
12505 i40e_aq_add_cloud_filters(hw, vsi->seid,
12506 &cld_filter.element, 1);
12510 /* Restore RSS filter */
12512 i40e_rss_filter_restore(struct i40e_pf *pf)
12514 struct i40e_rss_conf_list *list = &pf->rss_config_list;
12515 struct i40e_rss_filter *filter;
12517 TAILQ_FOREACH(filter, list, next) {
12518 i40e_config_rss_filter(pf, &filter->rss_filter_info, TRUE);
12523 i40e_filter_restore(struct i40e_pf *pf)
12525 i40e_ethertype_filter_restore(pf);
12526 i40e_tunnel_filter_restore(pf);
12527 i40e_fdir_filter_restore(pf);
12528 i40e_rss_filter_restore(pf);
12532 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
12534 if (strcmp(dev->device->driver->name, drv->driver.name))
12541 is_i40e_supported(struct rte_eth_dev *dev)
12543 return is_device_supported(dev, &rte_i40e_pmd);
12546 struct i40e_customized_pctype*
12547 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
12551 for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
12552 if (pf->customized_pctype[i].index == index)
12553 return &pf->customized_pctype[i];
12559 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
12560 uint32_t pkg_size, uint32_t proto_num,
12561 struct rte_pmd_i40e_proto_info *proto,
12562 enum rte_pmd_i40e_package_op op)
12564 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12565 uint32_t pctype_num;
12566 struct rte_pmd_i40e_ptype_info *pctype;
12567 uint32_t buff_size;
12568 struct i40e_customized_pctype *new_pctype = NULL;
12570 uint8_t pctype_value;
12575 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12576 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12577 PMD_DRV_LOG(ERR, "Unsupported operation.");
12581 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12582 (uint8_t *)&pctype_num, sizeof(pctype_num),
12583 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
12585 PMD_DRV_LOG(ERR, "Failed to get pctype number");
12589 PMD_DRV_LOG(INFO, "No new pctype added");
12593 buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
12594 pctype = rte_zmalloc("new_pctype", buff_size, 0);
12596 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12599 /* get information about new pctype list */
12600 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12601 (uint8_t *)pctype, buff_size,
12602 RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
12604 PMD_DRV_LOG(ERR, "Failed to get pctype list");
12609 /* Update customized pctype. */
12610 for (i = 0; i < pctype_num; i++) {
12611 pctype_value = pctype[i].ptype_id;
12612 memset(name, 0, sizeof(name));
12613 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12614 proto_id = pctype[i].protocols[j];
12615 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12617 for (n = 0; n < proto_num; n++) {
12618 if (proto[n].proto_id != proto_id)
12620 strlcat(name, proto[n].name, sizeof(name));
12621 strlcat(name, "_", sizeof(name));
12625 name[strlen(name) - 1] = '\0';
12626 PMD_DRV_LOG(INFO, "name = %s\n", name);
12627 if (!strcmp(name, "GTPC"))
12629 i40e_find_customized_pctype(pf,
12630 I40E_CUSTOMIZED_GTPC);
12631 else if (!strcmp(name, "GTPU_IPV4"))
12633 i40e_find_customized_pctype(pf,
12634 I40E_CUSTOMIZED_GTPU_IPV4);
12635 else if (!strcmp(name, "GTPU_IPV6"))
12637 i40e_find_customized_pctype(pf,
12638 I40E_CUSTOMIZED_GTPU_IPV6);
12639 else if (!strcmp(name, "GTPU"))
12641 i40e_find_customized_pctype(pf,
12642 I40E_CUSTOMIZED_GTPU);
12643 else if (!strcmp(name, "IPV4_L2TPV3"))
12645 i40e_find_customized_pctype(pf,
12646 I40E_CUSTOMIZED_IPV4_L2TPV3);
12647 else if (!strcmp(name, "IPV6_L2TPV3"))
12649 i40e_find_customized_pctype(pf,
12650 I40E_CUSTOMIZED_IPV6_L2TPV3);
12651 else if (!strcmp(name, "IPV4_ESP"))
12653 i40e_find_customized_pctype(pf,
12654 I40E_CUSTOMIZED_ESP_IPV4);
12655 else if (!strcmp(name, "IPV6_ESP"))
12657 i40e_find_customized_pctype(pf,
12658 I40E_CUSTOMIZED_ESP_IPV6);
12659 else if (!strcmp(name, "IPV4_UDP_ESP"))
12661 i40e_find_customized_pctype(pf,
12662 I40E_CUSTOMIZED_ESP_IPV4_UDP);
12663 else if (!strcmp(name, "IPV6_UDP_ESP"))
12665 i40e_find_customized_pctype(pf,
12666 I40E_CUSTOMIZED_ESP_IPV6_UDP);
12667 else if (!strcmp(name, "IPV4_AH"))
12669 i40e_find_customized_pctype(pf,
12670 I40E_CUSTOMIZED_AH_IPV4);
12671 else if (!strcmp(name, "IPV6_AH"))
12673 i40e_find_customized_pctype(pf,
12674 I40E_CUSTOMIZED_AH_IPV6);
12676 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12677 new_pctype->pctype = pctype_value;
12678 new_pctype->valid = true;
12680 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
12681 new_pctype->valid = false;
12691 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
12692 uint32_t pkg_size, uint32_t proto_num,
12693 struct rte_pmd_i40e_proto_info *proto,
12694 enum rte_pmd_i40e_package_op op)
12696 struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
12697 uint16_t port_id = dev->data->port_id;
12698 uint32_t ptype_num;
12699 struct rte_pmd_i40e_ptype_info *ptype;
12700 uint32_t buff_size;
12702 char name[RTE_PMD_I40E_DDP_NAME_SIZE];
12707 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12708 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12709 PMD_DRV_LOG(ERR, "Unsupported operation.");
12713 if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
12714 rte_pmd_i40e_ptype_mapping_reset(port_id);
12718 /* get information about new ptype num */
12719 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12720 (uint8_t *)&ptype_num, sizeof(ptype_num),
12721 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12723 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12727 PMD_DRV_LOG(INFO, "No new ptype added");
12731 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12732 ptype = rte_zmalloc("new_ptype", buff_size, 0);
12734 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12738 /* get information about new ptype list */
12739 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12740 (uint8_t *)ptype, buff_size,
12741 RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12743 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12748 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12749 ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12750 if (!ptype_mapping) {
12751 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12756 /* Update ptype mapping table. */
12757 for (i = 0; i < ptype_num; i++) {
12758 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12759 ptype_mapping[i].sw_ptype = 0;
12761 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12762 proto_id = ptype[i].protocols[j];
12763 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12765 for (n = 0; n < proto_num; n++) {
12766 if (proto[n].proto_id != proto_id)
12768 memset(name, 0, sizeof(name));
12769 strcpy(name, proto[n].name);
12770 PMD_DRV_LOG(INFO, "name = %s\n", name);
12771 if (!strncasecmp(name, "PPPOE", 5))
12772 ptype_mapping[i].sw_ptype |=
12773 RTE_PTYPE_L2_ETHER_PPPOE;
12774 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12776 ptype_mapping[i].sw_ptype |=
12777 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12778 ptype_mapping[i].sw_ptype |=
12780 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12782 ptype_mapping[i].sw_ptype |=
12783 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12784 ptype_mapping[i].sw_ptype |=
12785 RTE_PTYPE_INNER_L4_FRAG;
12786 } else if (!strncasecmp(name, "OIPV4", 5)) {
12787 ptype_mapping[i].sw_ptype |=
12788 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12790 } else if (!strncasecmp(name, "IPV4", 4) &&
12792 ptype_mapping[i].sw_ptype |=
12793 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12794 else if (!strncasecmp(name, "IPV4", 4) &&
12796 ptype_mapping[i].sw_ptype |=
12797 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12798 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12800 ptype_mapping[i].sw_ptype |=
12801 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12802 ptype_mapping[i].sw_ptype |=
12804 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12806 ptype_mapping[i].sw_ptype |=
12807 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12808 ptype_mapping[i].sw_ptype |=
12809 RTE_PTYPE_INNER_L4_FRAG;
12810 } else if (!strncasecmp(name, "OIPV6", 5)) {
12811 ptype_mapping[i].sw_ptype |=
12812 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12814 } else if (!strncasecmp(name, "IPV6", 4) &&
12816 ptype_mapping[i].sw_ptype |=
12817 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12818 else if (!strncasecmp(name, "IPV6", 4) &&
12820 ptype_mapping[i].sw_ptype |=
12821 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12822 else if (!strncasecmp(name, "UDP", 3) &&
12824 ptype_mapping[i].sw_ptype |=
12826 else if (!strncasecmp(name, "UDP", 3) &&
12828 ptype_mapping[i].sw_ptype |=
12829 RTE_PTYPE_INNER_L4_UDP;
12830 else if (!strncasecmp(name, "TCP", 3) &&
12832 ptype_mapping[i].sw_ptype |=
12834 else if (!strncasecmp(name, "TCP", 3) &&
12836 ptype_mapping[i].sw_ptype |=
12837 RTE_PTYPE_INNER_L4_TCP;
12838 else if (!strncasecmp(name, "SCTP", 4) &&
12840 ptype_mapping[i].sw_ptype |=
12842 else if (!strncasecmp(name, "SCTP", 4) &&
12844 ptype_mapping[i].sw_ptype |=
12845 RTE_PTYPE_INNER_L4_SCTP;
12846 else if ((!strncasecmp(name, "ICMP", 4) ||
12847 !strncasecmp(name, "ICMPV6", 6)) &&
12849 ptype_mapping[i].sw_ptype |=
12851 else if ((!strncasecmp(name, "ICMP", 4) ||
12852 !strncasecmp(name, "ICMPV6", 6)) &&
12854 ptype_mapping[i].sw_ptype |=
12855 RTE_PTYPE_INNER_L4_ICMP;
12856 else if (!strncasecmp(name, "GTPC", 4)) {
12857 ptype_mapping[i].sw_ptype |=
12858 RTE_PTYPE_TUNNEL_GTPC;
12860 } else if (!strncasecmp(name, "GTPU", 4)) {
12861 ptype_mapping[i].sw_ptype |=
12862 RTE_PTYPE_TUNNEL_GTPU;
12864 } else if (!strncasecmp(name, "ESP", 3)) {
12865 ptype_mapping[i].sw_ptype |=
12866 RTE_PTYPE_TUNNEL_ESP;
12868 } else if (!strncasecmp(name, "GRENAT", 6)) {
12869 ptype_mapping[i].sw_ptype |=
12870 RTE_PTYPE_TUNNEL_GRENAT;
12872 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12873 !strncasecmp(name, "L2TPV2", 6) ||
12874 !strncasecmp(name, "L2TPV3", 6)) {
12875 ptype_mapping[i].sw_ptype |=
12876 RTE_PTYPE_TUNNEL_L2TP;
12885 ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12888 PMD_DRV_LOG(ERR, "Failed to update ptype mapping table.");
12890 rte_free(ptype_mapping);
12896 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12897 uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12899 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12900 uint32_t proto_num;
12901 struct rte_pmd_i40e_proto_info *proto;
12902 uint32_t buff_size;
12906 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12907 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12908 PMD_DRV_LOG(ERR, "Unsupported operation.");
12912 /* get information about protocol number */
12913 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12914 (uint8_t *)&proto_num, sizeof(proto_num),
12915 RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12917 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12921 PMD_DRV_LOG(INFO, "No new protocol added");
12925 buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12926 proto = rte_zmalloc("new_proto", buff_size, 0);
12928 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12932 /* get information about protocol list */
12933 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12934 (uint8_t *)proto, buff_size,
12935 RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12937 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12942 /* Check if GTP is supported. */
12943 for (i = 0; i < proto_num; i++) {
12944 if (!strncmp(proto[i].name, "GTP", 3)) {
12945 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12946 pf->gtp_support = true;
12948 pf->gtp_support = false;
12953 /* Check if ESP is supported. */
12954 for (i = 0; i < proto_num; i++) {
12955 if (!strncmp(proto[i].name, "ESP", 3)) {
12956 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12957 pf->esp_support = true;
12959 pf->esp_support = false;
12964 /* Update customized pctype info */
12965 ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12966 proto_num, proto, op);
12968 PMD_DRV_LOG(INFO, "No pctype is updated.");
12970 /* Update customized ptype info */
12971 ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12972 proto_num, proto, op);
12974 PMD_DRV_LOG(INFO, "No ptype is updated.");
12979 /* Create a QinQ cloud filter
12981 * The Fortville NIC has limited resources for tunnel filters,
12982 * so we can only reuse existing filters.
12984 * In step 1 we define which Field Vector fields can be used for
12986 * As we do not have the inner tag defined as a field,
12987 * we have to define it first, by reusing one of L1 entries.
12989 * In step 2 we are replacing one of existing filter types with
12990 * a new one for QinQ.
12991 * As we reusing L1 and replacing L2, some of the default filter
12992 * types will disappear,which depends on L1 and L2 entries we reuse.
12994 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12996 * 1. Create L1 filter of outer vlan (12b) which will be in use
12997 * later when we define the cloud filter.
12998 * a. Valid_flags.replace_cloud = 0
12999 * b. Old_filter = 10 (Stag_Inner_Vlan)
13000 * c. New_filter = 0x10
13001 * d. TR bit = 0xff (optional, not used here)
13002 * e. Buffer – 2 entries:
13003 * i. Byte 0 = 8 (outer vlan FV index).
13005 * Byte 2-3 = 0x0fff
13006 * ii. Byte 0 = 37 (inner vlan FV index).
13008 * Byte 2-3 = 0x0fff
13011 * 2. Create cloud filter using two L1 filters entries: stag and
13012 * new filter(outer vlan+ inner vlan)
13013 * a. Valid_flags.replace_cloud = 1
13014 * b. Old_filter = 1 (instead of outer IP)
13015 * c. New_filter = 0x10
13016 * d. Buffer – 2 entries:
13017 * i. Byte 0 = 0x80 | 7 (valid | Stag).
13018 * Byte 1-3 = 0 (rsv)
13019 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
13020 * Byte 9-11 = 0 (rsv)
13023 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
13025 int ret = -ENOTSUP;
13026 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
13027 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
13028 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13029 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
13031 if (pf->support_multi_driver) {
13032 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
13037 memset(&filter_replace, 0,
13038 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
13039 memset(&filter_replace_buf, 0,
13040 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
13042 /* create L1 filter */
13043 filter_replace.old_filter_type =
13044 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
13045 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
13046 filter_replace.tr_bit = 0;
13048 /* Prepare the buffer, 2 entries */
13049 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
13050 filter_replace_buf.data[0] |=
13051 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13052 /* Field Vector 12b mask */
13053 filter_replace_buf.data[2] = 0xff;
13054 filter_replace_buf.data[3] = 0x0f;
13055 filter_replace_buf.data[4] =
13056 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
13057 filter_replace_buf.data[4] |=
13058 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13059 /* Field Vector 12b mask */
13060 filter_replace_buf.data[6] = 0xff;
13061 filter_replace_buf.data[7] = 0x0f;
13062 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
13063 &filter_replace_buf);
13064 if (ret != I40E_SUCCESS)
13067 if (filter_replace.old_filter_type !=
13068 filter_replace.new_filter_type)
13069 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
13070 " original: 0x%x, new: 0x%x",
13072 filter_replace.old_filter_type,
13073 filter_replace.new_filter_type);
13075 /* Apply the second L2 cloud filter */
13076 memset(&filter_replace, 0,
13077 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
13078 memset(&filter_replace_buf, 0,
13079 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
13081 /* create L2 filter, input for L2 filter will be L1 filter */
13082 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
13083 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
13084 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
13086 /* Prepare the buffer, 2 entries */
13087 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
13088 filter_replace_buf.data[0] |=
13089 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13090 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
13091 filter_replace_buf.data[4] |=
13092 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13093 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
13094 &filter_replace_buf);
13095 if (!ret && (filter_replace.old_filter_type !=
13096 filter_replace.new_filter_type))
13097 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
13098 " original: 0x%x, new: 0x%x",
13100 filter_replace.old_filter_type,
13101 filter_replace.new_filter_type);
13107 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
13108 const struct rte_flow_action_rss *in)
13110 if (in->key_len > RTE_DIM(out->key) ||
13111 in->queue_num > RTE_DIM(out->queue))
13113 if (!in->key && in->key_len)
13115 out->conf = (struct rte_flow_action_rss){
13117 .level = in->level,
13118 .types = in->types,
13119 .key_len = in->key_len,
13120 .queue_num = in->queue_num,
13121 .queue = memcpy(out->queue, in->queue,
13122 sizeof(*in->queue) * in->queue_num),
13125 out->conf.key = memcpy(out->key, in->key, in->key_len);
13129 /* Write HENA register to enable hash */
13131 i40e_rss_hash_set(struct i40e_pf *pf, struct i40e_rte_flow_rss_conf *rss_conf)
13133 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13134 uint8_t *key = (void *)(uintptr_t)rss_conf->conf.key;
13138 ret = i40e_set_rss_key(pf->main_vsi, key,
13139 rss_conf->conf.key_len);
13143 hena = i40e_config_hena(pf->adapter, rss_conf->conf.types);
13144 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
13145 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
13146 I40E_WRITE_FLUSH(hw);
13151 /* Configure hash input set */
13153 i40e_rss_conf_hash_inset(struct i40e_pf *pf, uint64_t types)
13155 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13156 struct rte_eth_input_set_conf conf;
13161 static const struct {
13163 enum rte_eth_input_set_field field;
13164 } inset_match_table[] = {
13165 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L3_SRC_ONLY,
13166 RTE_ETH_INPUT_SET_L3_SRC_IP4},
13167 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L3_DST_ONLY,
13168 RTE_ETH_INPUT_SET_L3_DST_IP4},
13169 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L4_SRC_ONLY,
13170 RTE_ETH_INPUT_SET_UNKNOWN},
13171 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L4_DST_ONLY,
13172 RTE_ETH_INPUT_SET_UNKNOWN},
13174 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L3_SRC_ONLY,
13175 RTE_ETH_INPUT_SET_L3_SRC_IP4},
13176 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L3_DST_ONLY,
13177 RTE_ETH_INPUT_SET_L3_DST_IP4},
13178 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L4_SRC_ONLY,
13179 RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT},
13180 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L4_DST_ONLY,
13181 RTE_ETH_INPUT_SET_L4_TCP_DST_PORT},
13183 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L3_SRC_ONLY,
13184 RTE_ETH_INPUT_SET_L3_SRC_IP4},
13185 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L3_DST_ONLY,
13186 RTE_ETH_INPUT_SET_L3_DST_IP4},
13187 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L4_SRC_ONLY,
13188 RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT},
13189 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L4_DST_ONLY,
13190 RTE_ETH_INPUT_SET_L4_UDP_DST_PORT},
13192 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L3_SRC_ONLY,
13193 RTE_ETH_INPUT_SET_L3_SRC_IP4},
13194 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L3_DST_ONLY,
13195 RTE_ETH_INPUT_SET_L3_DST_IP4},
13196 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L4_SRC_ONLY,
13197 RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT},
13198 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L4_DST_ONLY,
13199 RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT},
13201 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L3_SRC_ONLY,
13202 RTE_ETH_INPUT_SET_L3_SRC_IP4},
13203 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L3_DST_ONLY,
13204 RTE_ETH_INPUT_SET_L3_DST_IP4},
13205 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L4_SRC_ONLY,
13206 RTE_ETH_INPUT_SET_UNKNOWN},
13207 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L4_DST_ONLY,
13208 RTE_ETH_INPUT_SET_UNKNOWN},
13210 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L3_SRC_ONLY,
13211 RTE_ETH_INPUT_SET_L3_SRC_IP6},
13212 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L3_DST_ONLY,
13213 RTE_ETH_INPUT_SET_L3_DST_IP6},
13214 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L4_SRC_ONLY,
13215 RTE_ETH_INPUT_SET_UNKNOWN},
13216 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L4_DST_ONLY,
13217 RTE_ETH_INPUT_SET_UNKNOWN},
13219 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L3_SRC_ONLY,
13220 RTE_ETH_INPUT_SET_L3_SRC_IP6},
13221 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L3_DST_ONLY,
13222 RTE_ETH_INPUT_SET_L3_DST_IP6},
13223 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L4_SRC_ONLY,
13224 RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT},
13225 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L4_DST_ONLY,
13226 RTE_ETH_INPUT_SET_L4_TCP_DST_PORT},
13228 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L3_SRC_ONLY,
13229 RTE_ETH_INPUT_SET_L3_SRC_IP6},
13230 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L3_DST_ONLY,
13231 RTE_ETH_INPUT_SET_L3_DST_IP6},
13232 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L4_SRC_ONLY,
13233 RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT},
13234 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L4_DST_ONLY,
13235 RTE_ETH_INPUT_SET_L4_UDP_DST_PORT},
13237 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L3_SRC_ONLY,
13238 RTE_ETH_INPUT_SET_L3_SRC_IP6},
13239 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L3_DST_ONLY,
13240 RTE_ETH_INPUT_SET_L3_DST_IP6},
13241 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L4_SRC_ONLY,
13242 RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT},
13243 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L4_DST_ONLY,
13244 RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT},
13246 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L3_SRC_ONLY,
13247 RTE_ETH_INPUT_SET_L3_SRC_IP6},
13248 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L3_DST_ONLY,
13249 RTE_ETH_INPUT_SET_L3_DST_IP6},
13250 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L4_SRC_ONLY,
13251 RTE_ETH_INPUT_SET_UNKNOWN},
13252 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L4_DST_ONLY,
13253 RTE_ETH_INPUT_SET_UNKNOWN},
13256 mask0 = types & pf->adapter->flow_types_mask;
13257 conf.op = RTE_ETH_INPUT_SET_SELECT;
13258 conf.inset_size = 0;
13259 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < RTE_ETH_FLOW_MAX; i++) {
13260 if (mask0 & (1ULL << i)) {
13261 conf.flow_type = i;
13266 for (j = 0; j < RTE_DIM(inset_match_table); j++) {
13267 if ((types & inset_match_table[j].type) ==
13268 inset_match_table[j].type) {
13269 if (inset_match_table[j].field ==
13270 RTE_ETH_INPUT_SET_UNKNOWN)
13273 conf.field[conf.inset_size] =
13274 inset_match_table[j].field;
13279 if (conf.inset_size) {
13280 ret = i40e_hash_filter_inset_select(hw, &conf);
13288 /* Look up the conflicted rule then mark it as invalid */
13290 i40e_rss_mark_invalid_rule(struct i40e_pf *pf,
13291 struct i40e_rte_flow_rss_conf *conf)
13293 struct i40e_rss_filter *rss_item;
13294 uint64_t rss_inset;
13296 /* Clear input set bits before comparing the pctype */
13297 rss_inset = ~(ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY |
13298 ETH_RSS_L4_SRC_ONLY | ETH_RSS_L4_DST_ONLY);
13300 /* Look up the conflicted rule then mark it as invalid */
13301 TAILQ_FOREACH(rss_item, &pf->rss_config_list, next) {
13302 if (!rss_item->rss_filter_info.valid)
13305 if (conf->conf.queue_num &&
13306 rss_item->rss_filter_info.conf.queue_num)
13307 rss_item->rss_filter_info.valid = false;
13309 if (conf->conf.types &&
13310 (rss_item->rss_filter_info.conf.types &
13312 (conf->conf.types & rss_inset))
13313 rss_item->rss_filter_info.valid = false;
13315 if (conf->conf.func ==
13316 RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
13317 rss_item->rss_filter_info.conf.func ==
13318 RTE_ETH_HASH_FUNCTION_SIMPLE_XOR)
13319 rss_item->rss_filter_info.valid = false;
13323 /* Configure RSS hash function */
13325 i40e_rss_config_hash_function(struct i40e_pf *pf,
13326 struct i40e_rte_flow_rss_conf *conf)
13328 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13333 if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
13334 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
13335 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
13336 PMD_DRV_LOG(DEBUG, "Hash function already set to Simple XOR");
13337 I40E_WRITE_FLUSH(hw);
13338 i40e_rss_mark_invalid_rule(pf, conf);
13342 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
13344 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
13345 I40E_WRITE_FLUSH(hw);
13346 i40e_rss_mark_invalid_rule(pf, conf);
13347 } else if (conf->conf.func ==
13348 RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ) {
13349 mask0 = conf->conf.types & pf->adapter->flow_types_mask;
13351 i40e_set_symmetric_hash_enable_per_port(hw, 1);
13352 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
13353 if (mask0 & (1UL << i))
13357 if (i == UINT64_BIT)
13360 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
13361 j < I40E_FILTER_PCTYPE_MAX; j++) {
13362 if (pf->adapter->pctypes_tbl[i] & (1ULL << j))
13363 i40e_write_global_rx_ctl(hw,
13365 I40E_GLQF_HSYM_SYMH_ENA_MASK);
13372 /* Enable RSS according to the configuration */
13374 i40e_rss_enable_hash(struct i40e_pf *pf,
13375 struct i40e_rte_flow_rss_conf *conf)
13377 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13378 struct i40e_rte_flow_rss_conf rss_conf;
13380 if (!(conf->conf.types & pf->adapter->flow_types_mask))
13383 memset(&rss_conf, 0, sizeof(rss_conf));
13384 rte_memcpy(&rss_conf, conf, sizeof(rss_conf));
13386 /* Configure hash input set */
13387 if (i40e_rss_conf_hash_inset(pf, conf->conf.types))
13390 if (rss_conf.conf.key == NULL || rss_conf.conf.key_len <
13391 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
13392 /* Random default keys */
13393 static uint32_t rss_key_default[] = {0x6b793944,
13394 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
13395 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
13396 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
13398 rss_conf.conf.key = (uint8_t *)rss_key_default;
13399 rss_conf.conf.key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
13402 "No valid RSS key config for i40e, using default\n");
13405 rss_conf.conf.types |= rss_info->conf.types;
13406 i40e_rss_hash_set(pf, &rss_conf);
13408 if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ)
13409 i40e_rss_config_hash_function(pf, conf);
13411 i40e_rss_mark_invalid_rule(pf, conf);
13416 /* Configure RSS queue region */
13418 i40e_rss_config_queue_region(struct i40e_pf *pf,
13419 struct i40e_rte_flow_rss_conf *conf)
13421 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13426 /* If both VMDQ and RSS enabled, not all of PF queues are configured.
13427 * It's necessary to calculate the actual PF queues that are configured.
13429 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
13430 num = i40e_pf_calc_configured_queues_num(pf);
13432 num = pf->dev_data->nb_rx_queues;
13434 num = RTE_MIN(num, conf->conf.queue_num);
13435 PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
13440 "No PF queues are configured to enable RSS for port %u",
13441 pf->dev_data->port_id);
13445 /* Fill in redirection table */
13446 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
13449 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
13450 hw->func_caps.rss_table_entry_width) - 1));
13452 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
13455 i40e_rss_mark_invalid_rule(pf, conf);
13460 /* Configure RSS hash function to default */
13462 i40e_rss_clear_hash_function(struct i40e_pf *pf,
13463 struct i40e_rte_flow_rss_conf *conf)
13465 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13470 if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
13471 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
13472 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
13474 "Hash function already set to Toeplitz");
13475 I40E_WRITE_FLUSH(hw);
13479 reg |= I40E_GLQF_CTL_HTOEP_MASK;
13481 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
13482 I40E_WRITE_FLUSH(hw);
13483 } else if (conf->conf.func ==
13484 RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ) {
13485 mask0 = conf->conf.types & pf->adapter->flow_types_mask;
13487 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
13488 if (mask0 & (1UL << i))
13492 if (i == UINT64_BIT)
13495 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
13496 j < I40E_FILTER_PCTYPE_MAX; j++) {
13497 if (pf->adapter->pctypes_tbl[i] & (1ULL << j))
13498 i40e_write_global_rx_ctl(hw,
13507 /* Disable RSS hash and configure default input set */
13509 i40e_rss_disable_hash(struct i40e_pf *pf,
13510 struct i40e_rte_flow_rss_conf *conf)
13512 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13513 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13514 struct i40e_rte_flow_rss_conf rss_conf;
13517 memset(&rss_conf, 0, sizeof(rss_conf));
13518 rte_memcpy(&rss_conf, conf, sizeof(rss_conf));
13520 /* Disable RSS hash */
13521 rss_conf.conf.types = rss_info->conf.types & ~(conf->conf.types);
13522 i40e_rss_hash_set(pf, &rss_conf);
13524 for (i = RTE_ETH_FLOW_IPV4; i <= RTE_ETH_FLOW_L2_PAYLOAD; i++) {
13525 if (!(pf->adapter->flow_types_mask & (1ULL << i)) ||
13526 !(conf->conf.types & (1ULL << i)))
13529 /* Configure default input set */
13530 struct rte_eth_input_set_conf input_conf = {
13531 .op = RTE_ETH_INPUT_SET_SELECT,
13535 input_conf.field[0] = RTE_ETH_INPUT_SET_DEFAULT;
13536 i40e_hash_filter_inset_select(hw, &input_conf);
13539 rss_info->conf.types = rss_conf.conf.types;
13541 i40e_rss_clear_hash_function(pf, conf);
13546 /* Configure RSS queue region to default */
13548 i40e_rss_clear_queue_region(struct i40e_pf *pf)
13550 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13551 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13552 uint16_t queue[I40E_MAX_Q_PER_TC];
13553 uint32_t num_rxq, i;
13557 num_rxq = RTE_MIN(pf->dev_data->nb_rx_queues, I40E_MAX_Q_PER_TC);
13559 for (j = 0; j < num_rxq; j++)
13562 /* If both VMDQ and RSS enabled, not all of PF queues are configured.
13563 * It's necessary to calculate the actual PF queues that are configured.
13565 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
13566 num = i40e_pf_calc_configured_queues_num(pf);
13568 num = pf->dev_data->nb_rx_queues;
13570 num = RTE_MIN(num, num_rxq);
13571 PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
13576 "No PF queues are configured to enable RSS for port %u",
13577 pf->dev_data->port_id);
13581 /* Fill in redirection table */
13582 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
13585 lut = (lut << 8) | (queue[j] & ((0x1 <<
13586 hw->func_caps.rss_table_entry_width) - 1));
13588 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
13591 rss_info->conf.queue_num = 0;
13592 memset(&rss_info->conf.queue, 0, sizeof(uint16_t));
13598 i40e_config_rss_filter(struct i40e_pf *pf,
13599 struct i40e_rte_flow_rss_conf *conf, bool add)
13601 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13602 struct rte_flow_action_rss update_conf = rss_info->conf;
13606 if (conf->conf.queue_num) {
13607 /* Configure RSS queue region */
13608 ret = i40e_rss_config_queue_region(pf, conf);
13612 update_conf.queue_num = conf->conf.queue_num;
13613 update_conf.queue = conf->conf.queue;
13614 } else if (conf->conf.func ==
13615 RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
13616 /* Configure hash function */
13617 ret = i40e_rss_config_hash_function(pf, conf);
13621 update_conf.func = conf->conf.func;
13623 /* Configure hash enable and input set */
13624 ret = i40e_rss_enable_hash(pf, conf);
13628 update_conf.types |= conf->conf.types;
13629 update_conf.key = conf->conf.key;
13630 update_conf.key_len = conf->conf.key_len;
13633 /* Update RSS info in pf */
13634 if (i40e_rss_conf_init(rss_info, &update_conf))
13640 if (conf->conf.queue_num)
13641 i40e_rss_clear_queue_region(pf);
13642 else if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR)
13643 i40e_rss_clear_hash_function(pf, conf);
13645 i40e_rss_disable_hash(pf, conf);
13651 RTE_LOG_REGISTER(i40e_logtype_init, pmd.net.i40e.init, NOTICE);
13652 RTE_LOG_REGISTER(i40e_logtype_driver, pmd.net.i40e.driver, NOTICE);
13653 #ifdef RTE_LIBRTE_I40E_DEBUG_RX
13654 RTE_LOG_REGISTER(i40e_logtype_rx, pmd.net.i40e.rx, DEBUG);
13656 #ifdef RTE_LIBRTE_I40E_DEBUG_TX
13657 RTE_LOG_REGISTER(i40e_logtype_tx, pmd.net.i40e.tx, DEBUG);
13659 #ifdef RTE_LIBRTE_I40E_DEBUG_TX_FREE
13660 RTE_LOG_REGISTER(i40e_logtype_tx_free, pmd.net.i40e.tx_free, DEBUG);
13663 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
13664 ETH_I40E_FLOATING_VEB_ARG "=1"
13665 ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
13666 ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
13667 ETH_I40E_SUPPORT_MULTI_DRIVER "=1"
13668 ETH_I40E_USE_LATEST_VEC "=0|1");