4 * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
44 #include <rte_string_fns.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_memzone.h>
49 #include <rte_malloc.h>
50 #include <rte_memcpy.h>
51 #include <rte_alarm.h>
53 #include <rte_eth_ctrl.h>
55 #include "i40e_logs.h"
56 #include "base/i40e_prototype.h"
57 #include "base/i40e_adminq_cmd.h"
58 #include "base/i40e_type.h"
59 #include "base/i40e_register.h"
60 #include "base/i40e_dcb.h"
61 #include "i40e_ethdev.h"
62 #include "i40e_rxtx.h"
65 /* Maximun number of MAC addresses */
66 #define I40E_NUM_MACADDR_MAX 64
67 #define I40E_CLEAR_PXE_WAIT_MS 200
69 /* Maximun number of capability elements */
70 #define I40E_MAX_CAP_ELE_NUM 128
72 /* Wait count and inteval */
73 #define I40E_CHK_Q_ENA_COUNT 1000
74 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
76 /* Maximun number of VSI */
77 #define I40E_MAX_NUM_VSIS (384UL)
79 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
81 /* Flow control default timer */
82 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
84 /* Flow control default high water */
85 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
87 /* Flow control default low water */
88 #define I40E_DEFAULT_LOW_WATER (0x1A40/1024)
90 /* Flow control enable fwd bit */
91 #define I40E_PRTMAC_FWD_CTRL 0x00000001
93 /* Receive Packet Buffer size */
94 #define I40E_RXPBSIZE (968 * 1024)
97 #define I40E_KILOSHIFT 10
99 /* Receive Average Packet Size in Byte*/
100 #define I40E_PACKET_AVERAGE_SIZE 128
102 /* Mask of PF interrupt causes */
103 #define I40E_PFINT_ICR0_ENA_MASK ( \
104 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
105 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
106 I40E_PFINT_ICR0_ENA_GRST_MASK | \
107 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
108 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
109 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
110 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
111 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
112 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
113 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
115 #define I40E_FLOW_TYPES ( \
116 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
117 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
118 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
119 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
120 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
121 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
122 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
123 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
124 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
125 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
126 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
128 /* Additional timesync values. */
129 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
130 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
131 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
132 #define I40E_PRTTSYN_TSYNENA 0x80000000
133 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
134 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
136 #define I40E_MAX_PERCENT 100
137 #define I40E_DEFAULT_DCB_APP_NUM 1
138 #define I40E_DEFAULT_DCB_APP_PRIO 3
140 #define I40E_INSET_NONE 0x00000000000000000ULL
143 #define I40E_INSET_DMAC 0x0000000000000001ULL
144 #define I40E_INSET_SMAC 0x0000000000000002ULL
145 #define I40E_INSET_VLAN_OUTER 0x0000000000000004ULL
146 #define I40E_INSET_VLAN_INNER 0x0000000000000008ULL
147 #define I40E_INSET_VLAN_TUNNEL 0x0000000000000010ULL
150 #define I40E_INSET_IPV4_SRC 0x0000000000000100ULL
151 #define I40E_INSET_IPV4_DST 0x0000000000000200ULL
152 #define I40E_INSET_IPV6_SRC 0x0000000000000400ULL
153 #define I40E_INSET_IPV6_DST 0x0000000000000800ULL
154 #define I40E_INSET_SRC_PORT 0x0000000000001000ULL
155 #define I40E_INSET_DST_PORT 0x0000000000002000ULL
156 #define I40E_INSET_SCTP_VT 0x0000000000004000ULL
158 /* bit 16 ~ bit 31 */
159 #define I40E_INSET_IPV4_TOS 0x0000000000010000ULL
160 #define I40E_INSET_IPV4_PROTO 0x0000000000020000ULL
161 #define I40E_INSET_IPV4_TTL 0x0000000000040000ULL
162 #define I40E_INSET_IPV6_TC 0x0000000000080000ULL
163 #define I40E_INSET_IPV6_FLOW 0x0000000000100000ULL
164 #define I40E_INSET_IPV6_NEXT_HDR 0x0000000000200000ULL
165 #define I40E_INSET_IPV6_HOP_LIMIT 0x0000000000400000ULL
166 #define I40E_INSET_TCP_FLAGS 0x0000000000800000ULL
168 /* bit 32 ~ bit 47, tunnel fields */
169 #define I40E_INSET_TUNNEL_IPV4_DST 0x0000000100000000ULL
170 #define I40E_INSET_TUNNEL_IPV6_DST 0x0000000200000000ULL
171 #define I40E_INSET_TUNNEL_DMAC 0x0000000400000000ULL
172 #define I40E_INSET_TUNNEL_SRC_PORT 0x0000000800000000ULL
173 #define I40E_INSET_TUNNEL_DST_PORT 0x0000001000000000ULL
174 #define I40E_INSET_TUNNEL_ID 0x0000002000000000ULL
176 /* bit 48 ~ bit 55 */
177 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
179 /* bit 56 ~ bit 63, Flex Payload */
180 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
181 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
182 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
183 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
184 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
185 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
186 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
187 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
188 #define I40E_INSET_FLEX_PAYLOAD \
189 (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
190 I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
191 I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
192 I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
195 * Below are values for writing un-exposed registers suggested
198 /* Destination MAC address */
199 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
200 /* Source MAC address */
201 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
202 /* VLAN tag in the outer L2 header */
203 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0080000000000000ULL
204 /* VLAN tag in the inner L2 header */
205 #define I40E_REG_INSET_L2_INNER_VLAN 0x0100000000000000ULL
206 /* Source IPv4 address */
207 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
208 /* Destination IPv4 address */
209 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
210 /* IPv4 Type of Service (TOS) */
211 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
213 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
214 /* Source IPv6 address */
215 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
216 /* Destination IPv6 address */
217 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
218 /* IPv6 Traffic Class (TC) */
219 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
220 /* IPv6 Next Header */
221 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
223 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
224 /* Destination L4 port */
225 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
226 /* SCTP verification tag */
227 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
228 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
229 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
230 /* Source port of tunneling UDP */
231 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
232 /* Destination port of tunneling UDP */
233 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
234 /* UDP Tunneling ID, NVGRE/GRE key */
235 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
236 /* Last ether type */
237 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
238 /* Tunneling outer destination IPv4 address */
239 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
240 /* Tunneling outer destination IPv6 address */
241 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
242 /* 1st word of flex payload */
243 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
244 /* 2nd word of flex payload */
245 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
246 /* 3rd word of flex payload */
247 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
248 /* 4th word of flex payload */
249 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
250 /* 5th word of flex payload */
251 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
252 /* 6th word of flex payload */
253 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
254 /* 7th word of flex payload */
255 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
256 /* 8th word of flex payload */
257 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
259 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
261 #define I40E_TRANSLATE_INSET 0
262 #define I40E_TRANSLATE_REG 1
264 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
265 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
266 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
267 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
269 #define I40E_GL_SWT_L2TAGCTRL(_i) (0x001C0A70 + ((_i) * 4))
270 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
271 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK \
272 I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
274 /* PCI offset for querying capability */
275 #define PCI_DEV_CAP_REG 0xA4
276 /* PCI offset for enabling/disabling Extended Tag */
277 #define PCI_DEV_CTRL_REG 0xA8
278 /* Bit mask of Extended Tag capability */
279 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
280 /* Bit shift of Extended Tag enable/disable */
281 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
282 /* Bit mask of Extended Tag enable/disable */
283 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
285 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
286 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
287 static int i40e_dev_configure(struct rte_eth_dev *dev);
288 static int i40e_dev_start(struct rte_eth_dev *dev);
289 static void i40e_dev_stop(struct rte_eth_dev *dev);
290 static void i40e_dev_close(struct rte_eth_dev *dev);
291 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
292 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
293 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
294 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
295 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
296 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
297 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
298 struct rte_eth_stats *stats);
299 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
300 struct rte_eth_xstats *xstats, unsigned n);
301 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
302 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
306 static void i40e_dev_info_get(struct rte_eth_dev *dev,
307 struct rte_eth_dev_info *dev_info);
308 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
311 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
312 enum rte_vlan_type vlan_type,
314 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
315 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
318 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
319 static int i40e_dev_led_on(struct rte_eth_dev *dev);
320 static int i40e_dev_led_off(struct rte_eth_dev *dev);
321 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
322 struct rte_eth_fc_conf *fc_conf);
323 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
324 struct rte_eth_fc_conf *fc_conf);
325 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
326 struct rte_eth_pfc_conf *pfc_conf);
327 static void i40e_macaddr_add(struct rte_eth_dev *dev,
328 struct ether_addr *mac_addr,
331 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
332 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
333 struct rte_eth_rss_reta_entry64 *reta_conf,
335 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
336 struct rte_eth_rss_reta_entry64 *reta_conf,
339 static int i40e_get_cap(struct i40e_hw *hw);
340 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
341 static int i40e_pf_setup(struct i40e_pf *pf);
342 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
343 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
344 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
345 static int i40e_dcb_setup(struct rte_eth_dev *dev);
346 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
347 bool offset_loaded, uint64_t *offset, uint64_t *stat);
348 static void i40e_stat_update_48(struct i40e_hw *hw,
354 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
355 static void i40e_dev_interrupt_handler(
356 __rte_unused struct rte_intr_handle *handle, void *param);
357 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
358 uint32_t base, uint32_t num);
359 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
360 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
362 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
364 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
365 static int i40e_veb_release(struct i40e_veb *veb);
366 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
367 struct i40e_vsi *vsi);
368 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
369 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
370 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
371 struct i40e_macvlan_filter *mv_f,
373 struct ether_addr *addr);
374 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
375 struct i40e_macvlan_filter *mv_f,
378 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
379 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
380 struct rte_eth_rss_conf *rss_conf);
381 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
382 struct rte_eth_rss_conf *rss_conf);
383 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
384 struct rte_eth_udp_tunnel *udp_tunnel);
385 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
386 struct rte_eth_udp_tunnel *udp_tunnel);
387 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
388 struct rte_eth_ethertype_filter *filter,
390 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
391 enum rte_filter_op filter_op,
393 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
394 enum rte_filter_type filter_type,
395 enum rte_filter_op filter_op,
397 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
398 struct rte_eth_dcb_info *dcb_info);
399 static void i40e_configure_registers(struct i40e_hw *hw);
400 static void i40e_hw_init(struct rte_eth_dev *dev);
401 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
402 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
403 struct rte_eth_mirror_conf *mirror_conf,
404 uint8_t sw_id, uint8_t on);
405 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
407 static int i40e_timesync_enable(struct rte_eth_dev *dev);
408 static int i40e_timesync_disable(struct rte_eth_dev *dev);
409 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
410 struct timespec *timestamp,
412 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
413 struct timespec *timestamp);
414 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
416 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
418 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
419 struct timespec *timestamp);
420 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
421 const struct timespec *timestamp);
423 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
425 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
429 static const struct rte_pci_id pci_id_i40e_map[] = {
430 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
431 #include "rte_pci_dev_ids.h"
432 { .vendor_id = 0, /* sentinel */ },
435 static const struct eth_dev_ops i40e_eth_dev_ops = {
436 .dev_configure = i40e_dev_configure,
437 .dev_start = i40e_dev_start,
438 .dev_stop = i40e_dev_stop,
439 .dev_close = i40e_dev_close,
440 .promiscuous_enable = i40e_dev_promiscuous_enable,
441 .promiscuous_disable = i40e_dev_promiscuous_disable,
442 .allmulticast_enable = i40e_dev_allmulticast_enable,
443 .allmulticast_disable = i40e_dev_allmulticast_disable,
444 .dev_set_link_up = i40e_dev_set_link_up,
445 .dev_set_link_down = i40e_dev_set_link_down,
446 .link_update = i40e_dev_link_update,
447 .stats_get = i40e_dev_stats_get,
448 .xstats_get = i40e_dev_xstats_get,
449 .stats_reset = i40e_dev_stats_reset,
450 .xstats_reset = i40e_dev_stats_reset,
451 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
452 .dev_infos_get = i40e_dev_info_get,
453 .vlan_filter_set = i40e_vlan_filter_set,
454 .vlan_tpid_set = i40e_vlan_tpid_set,
455 .vlan_offload_set = i40e_vlan_offload_set,
456 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
457 .vlan_pvid_set = i40e_vlan_pvid_set,
458 .rx_queue_start = i40e_dev_rx_queue_start,
459 .rx_queue_stop = i40e_dev_rx_queue_stop,
460 .tx_queue_start = i40e_dev_tx_queue_start,
461 .tx_queue_stop = i40e_dev_tx_queue_stop,
462 .rx_queue_setup = i40e_dev_rx_queue_setup,
463 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
464 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
465 .rx_queue_release = i40e_dev_rx_queue_release,
466 .rx_queue_count = i40e_dev_rx_queue_count,
467 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
468 .tx_queue_setup = i40e_dev_tx_queue_setup,
469 .tx_queue_release = i40e_dev_tx_queue_release,
470 .dev_led_on = i40e_dev_led_on,
471 .dev_led_off = i40e_dev_led_off,
472 .flow_ctrl_get = i40e_flow_ctrl_get,
473 .flow_ctrl_set = i40e_flow_ctrl_set,
474 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
475 .mac_addr_add = i40e_macaddr_add,
476 .mac_addr_remove = i40e_macaddr_remove,
477 .reta_update = i40e_dev_rss_reta_update,
478 .reta_query = i40e_dev_rss_reta_query,
479 .rss_hash_update = i40e_dev_rss_hash_update,
480 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
481 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
482 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
483 .filter_ctrl = i40e_dev_filter_ctrl,
484 .rxq_info_get = i40e_rxq_info_get,
485 .txq_info_get = i40e_txq_info_get,
486 .mirror_rule_set = i40e_mirror_rule_set,
487 .mirror_rule_reset = i40e_mirror_rule_reset,
488 .timesync_enable = i40e_timesync_enable,
489 .timesync_disable = i40e_timesync_disable,
490 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
491 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
492 .get_dcb_info = i40e_dev_get_dcb_info,
493 .timesync_adjust_time = i40e_timesync_adjust_time,
494 .timesync_read_time = i40e_timesync_read_time,
495 .timesync_write_time = i40e_timesync_write_time,
498 /* store statistics names and its offset in stats structure */
499 struct rte_i40e_xstats_name_off {
500 char name[RTE_ETH_XSTATS_NAME_SIZE];
504 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
505 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
506 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
507 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
508 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
509 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
510 rx_unknown_protocol)},
511 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
512 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
513 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
514 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
517 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
518 sizeof(rte_i40e_stats_strings[0]))
520 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
521 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
522 tx_dropped_link_down)},
523 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
524 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
526 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
527 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
529 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
531 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
533 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
534 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
535 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
536 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
537 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
538 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
540 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
542 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
544 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
546 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
548 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
550 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
552 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
554 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
555 mac_short_packet_dropped)},
556 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
558 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
559 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
560 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
562 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
564 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
566 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
568 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
570 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
572 {"rx_flow_director_atr_match_packets",
573 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
574 {"rx_flow_director_sb_match_packets",
575 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
576 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
578 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
580 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
582 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
586 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
587 sizeof(rte_i40e_hw_port_strings[0]))
589 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
590 {"xon_packets", offsetof(struct i40e_hw_port_stats,
592 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
596 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
597 sizeof(rte_i40e_rxq_prio_strings[0]))
599 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
600 {"xon_packets", offsetof(struct i40e_hw_port_stats,
602 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
604 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
605 priority_xon_2_xoff)},
608 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
609 sizeof(rte_i40e_txq_prio_strings[0]))
611 static struct eth_driver rte_i40e_pmd = {
613 .name = "rte_i40e_pmd",
614 .id_table = pci_id_i40e_map,
615 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
616 RTE_PCI_DRV_DETACHABLE,
618 .eth_dev_init = eth_i40e_dev_init,
619 .eth_dev_uninit = eth_i40e_dev_uninit,
620 .dev_private_size = sizeof(struct i40e_adapter),
624 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
625 struct rte_eth_link *link)
627 struct rte_eth_link *dst = link;
628 struct rte_eth_link *src = &(dev->data->dev_link);
630 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
631 *(uint64_t *)src) == 0)
638 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
639 struct rte_eth_link *link)
641 struct rte_eth_link *dst = &(dev->data->dev_link);
642 struct rte_eth_link *src = link;
644 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
645 *(uint64_t *)src) == 0)
652 * Driver initialization routine.
653 * Invoked once at EAL init time.
654 * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
657 rte_i40e_pmd_init(const char *name __rte_unused,
658 const char *params __rte_unused)
660 PMD_INIT_FUNC_TRACE();
661 rte_eth_driver_register(&rte_i40e_pmd);
666 static struct rte_driver rte_i40e_driver = {
668 .init = rte_i40e_pmd_init,
671 PMD_REGISTER_DRIVER(rte_i40e_driver);
674 * Initialize registers for flexible payload, which should be set by NVM.
675 * This should be removed from code once it is fixed in NVM.
677 #ifndef I40E_GLQF_ORT
678 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
680 #ifndef I40E_GLQF_PIT
681 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
684 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
686 I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
687 I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
688 I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
689 I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
690 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
691 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
692 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
693 I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
694 I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
695 I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
697 /* GLQF_PIT Registers */
698 I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
699 I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
702 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
705 * Add a ethertype filter to drop all flow control frames transmitted
709 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
711 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
712 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
713 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
714 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
717 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
718 I40E_FLOW_CONTROL_ETHERTYPE, flags,
719 pf->main_vsi_seid, 0,
722 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
723 " frames from VSIs.");
727 eth_i40e_dev_init(struct rte_eth_dev *dev)
729 struct rte_pci_device *pci_dev;
730 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
731 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
732 struct i40e_vsi *vsi;
737 PMD_INIT_FUNC_TRACE();
739 dev->dev_ops = &i40e_eth_dev_ops;
740 dev->rx_pkt_burst = i40e_recv_pkts;
741 dev->tx_pkt_burst = i40e_xmit_pkts;
743 /* for secondary processes, we don't initialise any further as primary
744 * has already done this work. Only check we don't need a different
746 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
747 i40e_set_rx_function(dev);
748 i40e_set_tx_function(dev);
751 pci_dev = dev->pci_dev;
753 rte_eth_copy_pci_info(dev, pci_dev);
755 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
756 pf->adapter->eth_dev = dev;
757 pf->dev_data = dev->data;
759 hw->back = I40E_PF_TO_ADAPTER(pf);
760 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
762 PMD_INIT_LOG(ERR, "Hardware is not available, "
763 "as address is NULL");
767 hw->vendor_id = pci_dev->id.vendor_id;
768 hw->device_id = pci_dev->id.device_id;
769 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
770 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
771 hw->bus.device = pci_dev->addr.devid;
772 hw->bus.func = pci_dev->addr.function;
773 hw->adapter_stopped = 0;
775 /* Make sure all is clean before doing PF reset */
778 /* Initialize the hardware */
781 /* Reset here to make sure all is clean for each PF */
782 ret = i40e_pf_reset(hw);
784 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
788 /* Initialize the shared code (base driver) */
789 ret = i40e_init_shared_code(hw);
791 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
796 * To work around the NVM issue,initialize registers
797 * for flexible payload by software.
798 * It should be removed once issues are fixed in NVM.
800 i40e_flex_payload_reg_init(hw);
802 /* Initialize the parameters for adminq */
803 i40e_init_adminq_parameter(hw);
804 ret = i40e_init_adminq(hw);
805 if (ret != I40E_SUCCESS) {
806 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
809 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
810 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
811 hw->aq.api_maj_ver, hw->aq.api_min_ver,
812 ((hw->nvm.version >> 12) & 0xf),
813 ((hw->nvm.version >> 4) & 0xff),
814 (hw->nvm.version & 0xf), hw->nvm.eetrack);
817 i40e_clear_pxe_mode(hw);
820 * On X710, performance number is far from the expectation on recent
821 * firmware versions. The fix for this issue may not be integrated in
822 * the following firmware version. So the workaround in software driver
823 * is needed. It needs to modify the initial values of 3 internal only
824 * registers. Note that the workaround can be removed when it is fixed
825 * in firmware in the future.
827 i40e_configure_registers(hw);
829 /* Get hw capabilities */
830 ret = i40e_get_cap(hw);
831 if (ret != I40E_SUCCESS) {
832 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
833 goto err_get_capabilities;
836 /* Initialize parameters for PF */
837 ret = i40e_pf_parameter_init(dev);
839 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
840 goto err_parameter_init;
843 /* Initialize the queue management */
844 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
846 PMD_INIT_LOG(ERR, "Failed to init queue pool");
847 goto err_qp_pool_init;
849 ret = i40e_res_pool_init(&pf->msix_pool, 1,
850 hw->func_caps.num_msix_vectors - 1);
852 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
853 goto err_msix_pool_init;
856 /* Initialize lan hmc */
857 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
858 hw->func_caps.num_rx_qp, 0, 0);
859 if (ret != I40E_SUCCESS) {
860 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
861 goto err_init_lan_hmc;
864 /* Configure lan hmc */
865 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
866 if (ret != I40E_SUCCESS) {
867 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
868 goto err_configure_lan_hmc;
871 /* Get and check the mac address */
872 i40e_get_mac_addr(hw, hw->mac.addr);
873 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
874 PMD_INIT_LOG(ERR, "mac address is not valid");
876 goto err_get_mac_addr;
878 /* Copy the permanent MAC address */
879 ether_addr_copy((struct ether_addr *) hw->mac.addr,
880 (struct ether_addr *) hw->mac.perm_addr);
882 /* Disable flow control */
883 hw->fc.requested_mode = I40E_FC_NONE;
884 i40e_set_fc(hw, &aq_fail, TRUE);
886 /* Set the global registers with default ether type value */
887 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
888 if (ret != I40E_SUCCESS) {
889 PMD_INIT_LOG(ERR, "Failed to set the default outer "
891 goto err_setup_pf_switch;
893 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER, ETHER_TYPE_VLAN);
894 if (ret != I40E_SUCCESS) {
895 PMD_INIT_LOG(ERR, "Failed to set the default outer "
897 goto err_setup_pf_switch;
900 /* PF setup, which includes VSI setup */
901 ret = i40e_pf_setup(pf);
903 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
904 goto err_setup_pf_switch;
909 /* Disable double vlan by default */
910 i40e_vsi_config_double_vlan(vsi, FALSE);
912 if (!vsi->max_macaddrs)
913 len = ETHER_ADDR_LEN;
915 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
917 /* Should be after VSI initialized */
918 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
919 if (!dev->data->mac_addrs) {
920 PMD_INIT_LOG(ERR, "Failed to allocated memory "
921 "for storing mac address");
924 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
925 &dev->data->mac_addrs[0]);
927 /* initialize pf host driver to setup SRIOV resource if applicable */
928 i40e_pf_host_init(dev);
930 /* register callback func to eal lib */
931 rte_intr_callback_register(&(pci_dev->intr_handle),
932 i40e_dev_interrupt_handler, (void *)dev);
934 /* configure and enable device interrupt */
935 i40e_pf_config_irq0(hw, TRUE);
936 i40e_pf_enable_irq0(hw);
938 /* enable uio intr after callback register */
939 rte_intr_enable(&(pci_dev->intr_handle));
941 * Add an ethertype filter to drop all flow control frames transmitted
942 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
945 i40e_add_tx_flow_control_drop_filter(pf);
947 /* Set the max frame size to 0x2600 by default,
948 * in case other drivers changed the default value.
950 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
952 /* initialize mirror rule list */
953 TAILQ_INIT(&pf->mirror_list);
955 /* Init dcb to sw mode by default */
956 ret = i40e_dcb_init_configure(dev, TRUE);
957 if (ret != I40E_SUCCESS) {
958 PMD_INIT_LOG(INFO, "Failed to init dcb.");
959 pf->flags &= ~I40E_FLAG_DCB;
965 i40e_vsi_release(pf->main_vsi);
968 err_configure_lan_hmc:
969 (void)i40e_shutdown_lan_hmc(hw);
971 i40e_res_pool_destroy(&pf->msix_pool);
973 i40e_res_pool_destroy(&pf->qp_pool);
976 err_get_capabilities:
977 (void)i40e_shutdown_adminq(hw);
983 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
985 struct rte_pci_device *pci_dev;
987 struct i40e_filter_control_settings settings;
991 PMD_INIT_FUNC_TRACE();
993 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
996 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
997 pci_dev = dev->pci_dev;
999 if (hw->adapter_stopped == 0)
1000 i40e_dev_close(dev);
1002 dev->dev_ops = NULL;
1003 dev->rx_pkt_burst = NULL;
1004 dev->tx_pkt_burst = NULL;
1007 ret = i40e_aq_stop_lldp(hw, true, NULL);
1008 if (ret != I40E_SUCCESS) /* Its failure can be ignored */
1009 PMD_INIT_LOG(INFO, "Failed to stop lldp");
1011 /* Clear PXE mode */
1012 i40e_clear_pxe_mode(hw);
1014 /* Unconfigure filter control */
1015 memset(&settings, 0, sizeof(settings));
1016 ret = i40e_set_filter_control(hw, &settings);
1018 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1021 /* Disable flow control */
1022 hw->fc.requested_mode = I40E_FC_NONE;
1023 i40e_set_fc(hw, &aq_fail, TRUE);
1025 /* uninitialize pf host driver */
1026 i40e_pf_host_uninit(dev);
1028 rte_free(dev->data->mac_addrs);
1029 dev->data->mac_addrs = NULL;
1031 /* disable uio intr before callback unregister */
1032 rte_intr_disable(&(pci_dev->intr_handle));
1034 /* register callback func to eal lib */
1035 rte_intr_callback_unregister(&(pci_dev->intr_handle),
1036 i40e_dev_interrupt_handler, (void *)dev);
1042 i40e_dev_configure(struct rte_eth_dev *dev)
1044 struct i40e_adapter *ad =
1045 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1046 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1047 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1050 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1051 * bulk allocation or vector Rx preconditions we will reset it.
1053 ad->rx_bulk_alloc_allowed = true;
1054 ad->rx_vec_allowed = true;
1055 ad->tx_simple_allowed = true;
1056 ad->tx_vec_allowed = true;
1058 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1059 ret = i40e_fdir_setup(pf);
1060 if (ret != I40E_SUCCESS) {
1061 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1064 ret = i40e_fdir_configure(dev);
1066 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1070 i40e_fdir_teardown(pf);
1072 ret = i40e_dev_init_vlan(dev);
1077 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1078 * RSS setting have different requirements.
1079 * General PMD driver call sequence are NIC init, configure,
1080 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1081 * will try to lookup the VSI that specific queue belongs to if VMDQ
1082 * applicable. So, VMDQ setting has to be done before
1083 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1084 * For RSS setting, it will try to calculate actual configured RX queue
1085 * number, which will be available after rx_queue_setup(). dev_start()
1086 * function is good to place RSS setup.
1088 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1089 ret = i40e_vmdq_setup(dev);
1094 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1095 ret = i40e_dcb_setup(dev);
1097 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1105 /* need to release vmdq resource if exists */
1106 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1107 i40e_vsi_release(pf->vmdq[i].vsi);
1108 pf->vmdq[i].vsi = NULL;
1113 /* need to release fdir resource if exists */
1114 i40e_fdir_teardown(pf);
1119 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1121 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1122 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1123 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1124 uint16_t msix_vect = vsi->msix_intr;
1127 for (i = 0; i < vsi->nb_qps; i++) {
1128 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1129 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1133 if (vsi->type != I40E_VSI_SRIOV) {
1134 if (!rte_intr_allow_others(intr_handle)) {
1135 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1136 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1138 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1141 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1142 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1144 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1149 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1150 vsi->user_param + (msix_vect - 1);
1152 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1153 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1155 I40E_WRITE_FLUSH(hw);
1159 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1160 int base_queue, int nb_queue)
1164 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1166 /* Bind all RX queues to allocated MSIX interrupt */
1167 for (i = 0; i < nb_queue; i++) {
1168 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1169 I40E_QINT_RQCTL_ITR_INDX_MASK |
1170 ((base_queue + i + 1) <<
1171 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1172 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1173 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1175 if (i == nb_queue - 1)
1176 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1177 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1180 /* Write first RX queue to Link list register as the head element */
1181 if (vsi->type != I40E_VSI_SRIOV) {
1183 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1185 if (msix_vect == I40E_MISC_VEC_ID) {
1186 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1188 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1190 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1192 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1195 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1197 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1199 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1201 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1208 if (msix_vect == I40E_MISC_VEC_ID) {
1210 I40E_VPINT_LNKLST0(vsi->user_param),
1212 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1214 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1216 /* num_msix_vectors_vf needs to minus irq0 */
1217 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1218 vsi->user_param + (msix_vect - 1);
1220 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1222 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1224 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1228 I40E_WRITE_FLUSH(hw);
1232 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1234 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1235 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1236 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1237 uint16_t msix_vect = vsi->msix_intr;
1238 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1239 uint16_t queue_idx = 0;
1244 for (i = 0; i < vsi->nb_qps; i++) {
1245 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1246 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1249 /* INTENA flag is not auto-cleared for interrupt */
1250 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1251 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1252 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1253 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1254 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1256 /* VF bind interrupt */
1257 if (vsi->type == I40E_VSI_SRIOV) {
1258 __vsi_queues_bind_intr(vsi, msix_vect,
1259 vsi->base_queue, vsi->nb_qps);
1263 /* PF & VMDq bind interrupt */
1264 if (rte_intr_dp_is_en(intr_handle)) {
1265 if (vsi->type == I40E_VSI_MAIN) {
1268 } else if (vsi->type == I40E_VSI_VMDQ2) {
1269 struct i40e_vsi *main_vsi =
1270 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1271 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1276 for (i = 0; i < vsi->nb_used_qps; i++) {
1278 if (!rte_intr_allow_others(intr_handle))
1279 /* allow to share MISC_VEC_ID */
1280 msix_vect = I40E_MISC_VEC_ID;
1282 /* no enough msix_vect, map all to one */
1283 __vsi_queues_bind_intr(vsi, msix_vect,
1284 vsi->base_queue + i,
1285 vsi->nb_used_qps - i);
1286 for (; !!record && i < vsi->nb_used_qps; i++)
1287 intr_handle->intr_vec[queue_idx + i] =
1291 /* 1:1 queue/msix_vect mapping */
1292 __vsi_queues_bind_intr(vsi, msix_vect,
1293 vsi->base_queue + i, 1);
1295 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1303 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1305 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1306 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1307 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1308 uint16_t interval = i40e_calc_itr_interval(\
1309 RTE_LIBRTE_I40E_ITR_INTERVAL);
1310 uint16_t msix_intr, i;
1312 if (rte_intr_allow_others(intr_handle))
1313 for (i = 0; i < vsi->nb_msix; i++) {
1314 msix_intr = vsi->msix_intr + i;
1315 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1316 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1317 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1318 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1320 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1323 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1324 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1325 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1326 (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1328 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1330 I40E_WRITE_FLUSH(hw);
1334 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1336 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1337 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1338 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1339 uint16_t msix_intr, i;
1341 if (rte_intr_allow_others(intr_handle))
1342 for (i = 0; i < vsi->nb_msix; i++) {
1343 msix_intr = vsi->msix_intr + i;
1344 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1348 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1350 I40E_WRITE_FLUSH(hw);
1353 static inline uint8_t
1354 i40e_parse_link_speed(uint16_t eth_link_speed)
1356 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1358 switch (eth_link_speed) {
1359 case ETH_LINK_SPEED_40G:
1360 link_speed = I40E_LINK_SPEED_40GB;
1362 case ETH_LINK_SPEED_20G:
1363 link_speed = I40E_LINK_SPEED_20GB;
1365 case ETH_LINK_SPEED_10G:
1366 link_speed = I40E_LINK_SPEED_10GB;
1368 case ETH_LINK_SPEED_1000:
1369 link_speed = I40E_LINK_SPEED_1GB;
1371 case ETH_LINK_SPEED_100:
1372 link_speed = I40E_LINK_SPEED_100MB;
1380 i40e_phy_conf_link(__rte_unused struct i40e_hw *hw,
1381 __rte_unused uint8_t abilities,
1382 __rte_unused uint8_t force_speed)
1384 /* Skip any phy config on both 10G and 40G interfaces, as a workaround
1385 * for the link control limitation of that all link control should be
1386 * handled by firmware. It should follow up if link control will be
1387 * opened to software driver in future firmware versions.
1389 return I40E_SUCCESS;
1393 i40e_apply_link_speed(struct rte_eth_dev *dev)
1396 uint8_t abilities = 0;
1397 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1398 struct rte_eth_conf *conf = &dev->data->dev_conf;
1400 speed = i40e_parse_link_speed(conf->link_speed);
1401 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1402 if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
1403 abilities |= I40E_AQ_PHY_AN_ENABLED;
1405 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1407 return i40e_phy_conf_link(hw, abilities, speed);
1411 i40e_dev_start(struct rte_eth_dev *dev)
1413 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1414 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1415 struct i40e_vsi *main_vsi = pf->main_vsi;
1417 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1418 uint32_t intr_vector = 0;
1420 hw->adapter_stopped = 0;
1422 if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1423 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1424 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1425 dev->data->dev_conf.link_duplex,
1426 dev->data->port_id);
1430 rte_intr_disable(intr_handle);
1432 if ((rte_intr_cap_multiple(intr_handle) ||
1433 !RTE_ETH_DEV_SRIOV(dev).active) &&
1434 dev->data->dev_conf.intr_conf.rxq != 0) {
1435 intr_vector = dev->data->nb_rx_queues;
1436 if (rte_intr_efd_enable(intr_handle, intr_vector))
1440 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1441 intr_handle->intr_vec =
1442 rte_zmalloc("intr_vec",
1443 dev->data->nb_rx_queues * sizeof(int),
1445 if (!intr_handle->intr_vec) {
1446 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1447 " intr_vec\n", dev->data->nb_rx_queues);
1452 /* Initialize VSI */
1453 ret = i40e_dev_rxtx_init(pf);
1454 if (ret != I40E_SUCCESS) {
1455 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1459 /* Map queues with MSIX interrupt */
1460 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1461 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1462 i40e_vsi_queues_bind_intr(main_vsi);
1463 i40e_vsi_enable_queues_intr(main_vsi);
1465 /* Map VMDQ VSI queues with MSIX interrupt */
1466 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1467 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1468 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1469 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1472 /* enable FDIR MSIX interrupt */
1473 if (pf->fdir.fdir_vsi) {
1474 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1475 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1478 /* Enable all queues which have been configured */
1479 ret = i40e_dev_switch_queues(pf, TRUE);
1480 if (ret != I40E_SUCCESS) {
1481 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1485 /* Enable receiving broadcast packets */
1486 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1487 if (ret != I40E_SUCCESS)
1488 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1490 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1491 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1493 if (ret != I40E_SUCCESS)
1494 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1497 /* Apply link configure */
1498 ret = i40e_apply_link_speed(dev);
1499 if (I40E_SUCCESS != ret) {
1500 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1504 if (!rte_intr_allow_others(intr_handle)) {
1505 rte_intr_callback_unregister(intr_handle,
1506 i40e_dev_interrupt_handler,
1508 /* configure and enable device interrupt */
1509 i40e_pf_config_irq0(hw, FALSE);
1510 i40e_pf_enable_irq0(hw);
1512 if (dev->data->dev_conf.intr_conf.lsc != 0)
1513 PMD_INIT_LOG(INFO, "lsc won't enable because of"
1514 " no intr multiplex\n");
1517 /* enable uio intr after callback register */
1518 rte_intr_enable(intr_handle);
1520 return I40E_SUCCESS;
1523 i40e_dev_switch_queues(pf, FALSE);
1524 i40e_dev_clear_queues(dev);
1530 i40e_dev_stop(struct rte_eth_dev *dev)
1532 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1533 struct i40e_vsi *main_vsi = pf->main_vsi;
1534 struct i40e_mirror_rule *p_mirror;
1535 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1538 /* Disable all queues */
1539 i40e_dev_switch_queues(pf, FALSE);
1541 /* un-map queues with interrupt registers */
1542 i40e_vsi_disable_queues_intr(main_vsi);
1543 i40e_vsi_queues_unbind_intr(main_vsi);
1545 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1546 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1547 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1550 if (pf->fdir.fdir_vsi) {
1551 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1552 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1554 /* Clear all queues and release memory */
1555 i40e_dev_clear_queues(dev);
1558 i40e_dev_set_link_down(dev);
1560 /* Remove all mirror rules */
1561 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1562 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1565 pf->nb_mirror_rule = 0;
1567 if (!rte_intr_allow_others(intr_handle))
1568 /* resume to the default handler */
1569 rte_intr_callback_register(intr_handle,
1570 i40e_dev_interrupt_handler,
1573 /* Clean datapath event and queue/vec mapping */
1574 rte_intr_efd_disable(intr_handle);
1575 if (intr_handle->intr_vec) {
1576 rte_free(intr_handle->intr_vec);
1577 intr_handle->intr_vec = NULL;
1582 i40e_dev_close(struct rte_eth_dev *dev)
1584 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1585 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1589 PMD_INIT_FUNC_TRACE();
1592 hw->adapter_stopped = 1;
1593 i40e_dev_free_queues(dev);
1595 /* Disable interrupt */
1596 i40e_pf_disable_irq0(hw);
1597 rte_intr_disable(&(dev->pci_dev->intr_handle));
1599 /* shutdown and destroy the HMC */
1600 i40e_shutdown_lan_hmc(hw);
1602 /* release all the existing VSIs and VEBs */
1603 i40e_fdir_teardown(pf);
1604 i40e_vsi_release(pf->main_vsi);
1606 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1607 i40e_vsi_release(pf->vmdq[i].vsi);
1608 pf->vmdq[i].vsi = NULL;
1614 /* shutdown the adminq */
1615 i40e_aq_queue_shutdown(hw, true);
1616 i40e_shutdown_adminq(hw);
1618 i40e_res_pool_destroy(&pf->qp_pool);
1619 i40e_res_pool_destroy(&pf->msix_pool);
1621 /* force a PF reset to clean anything leftover */
1622 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1623 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1624 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1625 I40E_WRITE_FLUSH(hw);
1629 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1631 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1632 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1633 struct i40e_vsi *vsi = pf->main_vsi;
1636 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1638 if (status != I40E_SUCCESS)
1639 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1641 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1643 if (status != I40E_SUCCESS)
1644 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1649 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1651 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1652 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1653 struct i40e_vsi *vsi = pf->main_vsi;
1656 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1658 if (status != I40E_SUCCESS)
1659 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1661 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1663 if (status != I40E_SUCCESS)
1664 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1668 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1670 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1671 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1672 struct i40e_vsi *vsi = pf->main_vsi;
1675 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1676 if (ret != I40E_SUCCESS)
1677 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1681 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1683 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1684 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1685 struct i40e_vsi *vsi = pf->main_vsi;
1688 if (dev->data->promiscuous == 1)
1689 return; /* must remain in all_multicast mode */
1691 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1692 vsi->seid, FALSE, NULL);
1693 if (ret != I40E_SUCCESS)
1694 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1698 * Set device link up.
1701 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1703 /* re-apply link speed setting */
1704 return i40e_apply_link_speed(dev);
1708 * Set device link down.
1711 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1713 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1714 uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1715 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1717 return i40e_phy_conf_link(hw, abilities, speed);
1721 i40e_dev_link_update(struct rte_eth_dev *dev,
1722 int wait_to_complete)
1724 #define CHECK_INTERVAL 100 /* 100ms */
1725 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
1726 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1727 struct i40e_link_status link_status;
1728 struct rte_eth_link link, old;
1730 unsigned rep_cnt = MAX_REPEAT_TIME;
1732 memset(&link, 0, sizeof(link));
1733 memset(&old, 0, sizeof(old));
1734 memset(&link_status, 0, sizeof(link_status));
1735 rte_i40e_dev_atomic_read_link_status(dev, &old);
1738 /* Get link status information from hardware */
1739 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1740 if (status != I40E_SUCCESS) {
1741 link.link_speed = ETH_LINK_SPEED_100;
1742 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1743 PMD_DRV_LOG(ERR, "Failed to get link info");
1747 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1748 if (!wait_to_complete)
1751 rte_delay_ms(CHECK_INTERVAL);
1752 } while (!link.link_status && rep_cnt--);
1754 if (!link.link_status)
1757 /* i40e uses full duplex only */
1758 link.link_duplex = ETH_LINK_FULL_DUPLEX;
1760 /* Parse the link status */
1761 switch (link_status.link_speed) {
1762 case I40E_LINK_SPEED_100MB:
1763 link.link_speed = ETH_LINK_SPEED_100;
1765 case I40E_LINK_SPEED_1GB:
1766 link.link_speed = ETH_LINK_SPEED_1000;
1768 case I40E_LINK_SPEED_10GB:
1769 link.link_speed = ETH_LINK_SPEED_10G;
1771 case I40E_LINK_SPEED_20GB:
1772 link.link_speed = ETH_LINK_SPEED_20G;
1774 case I40E_LINK_SPEED_40GB:
1775 link.link_speed = ETH_LINK_SPEED_40G;
1778 link.link_speed = ETH_LINK_SPEED_100;
1783 rte_i40e_dev_atomic_write_link_status(dev, &link);
1784 if (link.link_status == old.link_status)
1790 /* Get all the statistics of a VSI */
1792 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1794 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1795 struct i40e_eth_stats *nes = &vsi->eth_stats;
1796 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1797 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1799 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1800 vsi->offset_loaded, &oes->rx_bytes,
1802 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1803 vsi->offset_loaded, &oes->rx_unicast,
1805 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1806 vsi->offset_loaded, &oes->rx_multicast,
1807 &nes->rx_multicast);
1808 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1809 vsi->offset_loaded, &oes->rx_broadcast,
1810 &nes->rx_broadcast);
1811 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1812 &oes->rx_discards, &nes->rx_discards);
1813 /* GLV_REPC not supported */
1814 /* GLV_RMPC not supported */
1815 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1816 &oes->rx_unknown_protocol,
1817 &nes->rx_unknown_protocol);
1818 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1819 vsi->offset_loaded, &oes->tx_bytes,
1821 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1822 vsi->offset_loaded, &oes->tx_unicast,
1824 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1825 vsi->offset_loaded, &oes->tx_multicast,
1826 &nes->tx_multicast);
1827 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1828 vsi->offset_loaded, &oes->tx_broadcast,
1829 &nes->tx_broadcast);
1830 /* GLV_TDPC not supported */
1831 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1832 &oes->tx_errors, &nes->tx_errors);
1833 vsi->offset_loaded = true;
1835 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1837 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
1838 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
1839 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
1840 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
1841 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
1842 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1843 nes->rx_unknown_protocol);
1844 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
1845 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
1846 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
1847 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
1848 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
1849 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
1850 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1855 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
1858 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1859 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1861 /* Get statistics of struct i40e_eth_stats */
1862 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1863 I40E_GLPRT_GORCL(hw->port),
1864 pf->offset_loaded, &os->eth.rx_bytes,
1866 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1867 I40E_GLPRT_UPRCL(hw->port),
1868 pf->offset_loaded, &os->eth.rx_unicast,
1869 &ns->eth.rx_unicast);
1870 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1871 I40E_GLPRT_MPRCL(hw->port),
1872 pf->offset_loaded, &os->eth.rx_multicast,
1873 &ns->eth.rx_multicast);
1874 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1875 I40E_GLPRT_BPRCL(hw->port),
1876 pf->offset_loaded, &os->eth.rx_broadcast,
1877 &ns->eth.rx_broadcast);
1878 /* Workaround: CRC size should not be included in byte statistics,
1879 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
1881 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
1882 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
1884 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1885 pf->offset_loaded, &os->eth.rx_discards,
1886 &ns->eth.rx_discards);
1887 /* GLPRT_REPC not supported */
1888 /* GLPRT_RMPC not supported */
1889 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1891 &os->eth.rx_unknown_protocol,
1892 &ns->eth.rx_unknown_protocol);
1893 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1894 I40E_GLPRT_GOTCL(hw->port),
1895 pf->offset_loaded, &os->eth.tx_bytes,
1897 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1898 I40E_GLPRT_UPTCL(hw->port),
1899 pf->offset_loaded, &os->eth.tx_unicast,
1900 &ns->eth.tx_unicast);
1901 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1902 I40E_GLPRT_MPTCL(hw->port),
1903 pf->offset_loaded, &os->eth.tx_multicast,
1904 &ns->eth.tx_multicast);
1905 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1906 I40E_GLPRT_BPTCL(hw->port),
1907 pf->offset_loaded, &os->eth.tx_broadcast,
1908 &ns->eth.tx_broadcast);
1909 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
1910 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
1911 /* GLPRT_TEPC not supported */
1913 /* additional port specific stats */
1914 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1915 pf->offset_loaded, &os->tx_dropped_link_down,
1916 &ns->tx_dropped_link_down);
1917 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1918 pf->offset_loaded, &os->crc_errors,
1920 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1921 pf->offset_loaded, &os->illegal_bytes,
1922 &ns->illegal_bytes);
1923 /* GLPRT_ERRBC not supported */
1924 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1925 pf->offset_loaded, &os->mac_local_faults,
1926 &ns->mac_local_faults);
1927 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1928 pf->offset_loaded, &os->mac_remote_faults,
1929 &ns->mac_remote_faults);
1930 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1931 pf->offset_loaded, &os->rx_length_errors,
1932 &ns->rx_length_errors);
1933 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1934 pf->offset_loaded, &os->link_xon_rx,
1936 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1937 pf->offset_loaded, &os->link_xoff_rx,
1939 for (i = 0; i < 8; i++) {
1940 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1942 &os->priority_xon_rx[i],
1943 &ns->priority_xon_rx[i]);
1944 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1946 &os->priority_xoff_rx[i],
1947 &ns->priority_xoff_rx[i]);
1949 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1950 pf->offset_loaded, &os->link_xon_tx,
1952 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1953 pf->offset_loaded, &os->link_xoff_tx,
1955 for (i = 0; i < 8; i++) {
1956 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1958 &os->priority_xon_tx[i],
1959 &ns->priority_xon_tx[i]);
1960 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1962 &os->priority_xoff_tx[i],
1963 &ns->priority_xoff_tx[i]);
1964 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1966 &os->priority_xon_2_xoff[i],
1967 &ns->priority_xon_2_xoff[i]);
1969 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1970 I40E_GLPRT_PRC64L(hw->port),
1971 pf->offset_loaded, &os->rx_size_64,
1973 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1974 I40E_GLPRT_PRC127L(hw->port),
1975 pf->offset_loaded, &os->rx_size_127,
1977 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1978 I40E_GLPRT_PRC255L(hw->port),
1979 pf->offset_loaded, &os->rx_size_255,
1981 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1982 I40E_GLPRT_PRC511L(hw->port),
1983 pf->offset_loaded, &os->rx_size_511,
1985 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1986 I40E_GLPRT_PRC1023L(hw->port),
1987 pf->offset_loaded, &os->rx_size_1023,
1989 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1990 I40E_GLPRT_PRC1522L(hw->port),
1991 pf->offset_loaded, &os->rx_size_1522,
1993 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1994 I40E_GLPRT_PRC9522L(hw->port),
1995 pf->offset_loaded, &os->rx_size_big,
1997 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1998 pf->offset_loaded, &os->rx_undersize,
2000 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2001 pf->offset_loaded, &os->rx_fragments,
2003 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2004 pf->offset_loaded, &os->rx_oversize,
2006 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2007 pf->offset_loaded, &os->rx_jabber,
2009 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2010 I40E_GLPRT_PTC64L(hw->port),
2011 pf->offset_loaded, &os->tx_size_64,
2013 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2014 I40E_GLPRT_PTC127L(hw->port),
2015 pf->offset_loaded, &os->tx_size_127,
2017 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2018 I40E_GLPRT_PTC255L(hw->port),
2019 pf->offset_loaded, &os->tx_size_255,
2021 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2022 I40E_GLPRT_PTC511L(hw->port),
2023 pf->offset_loaded, &os->tx_size_511,
2025 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2026 I40E_GLPRT_PTC1023L(hw->port),
2027 pf->offset_loaded, &os->tx_size_1023,
2029 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2030 I40E_GLPRT_PTC1522L(hw->port),
2031 pf->offset_loaded, &os->tx_size_1522,
2033 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2034 I40E_GLPRT_PTC9522L(hw->port),
2035 pf->offset_loaded, &os->tx_size_big,
2037 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2039 &os->fd_sb_match, &ns->fd_sb_match);
2040 /* GLPRT_MSPDC not supported */
2041 /* GLPRT_XEC not supported */
2043 pf->offset_loaded = true;
2046 i40e_update_vsi_stats(pf->main_vsi);
2049 /* Get all statistics of a port */
2051 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2053 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2054 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2055 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2058 /* call read registers - updates values, now write them to struct */
2059 i40e_read_stats_registers(pf, hw);
2061 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2062 pf->main_vsi->eth_stats.rx_multicast +
2063 pf->main_vsi->eth_stats.rx_broadcast -
2064 pf->main_vsi->eth_stats.rx_discards;
2065 stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2066 pf->main_vsi->eth_stats.tx_multicast +
2067 pf->main_vsi->eth_stats.tx_broadcast;
2068 stats->ibytes = ns->eth.rx_bytes;
2069 stats->obytes = ns->eth.tx_bytes;
2070 stats->oerrors = ns->eth.tx_errors +
2071 pf->main_vsi->eth_stats.tx_errors;
2072 stats->imcasts = pf->main_vsi->eth_stats.rx_multicast;
2075 stats->imissed = ns->eth.rx_discards +
2076 pf->main_vsi->eth_stats.rx_discards;
2077 stats->ierrors = ns->crc_errors +
2078 ns->rx_length_errors + ns->rx_undersize +
2079 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber +
2082 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2083 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
2084 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
2085 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
2086 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
2087 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
2088 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2089 ns->eth.rx_unknown_protocol);
2090 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
2091 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
2092 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
2093 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
2094 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
2095 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
2097 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
2098 ns->tx_dropped_link_down);
2099 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
2100 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
2102 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
2103 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
2104 ns->mac_local_faults);
2105 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
2106 ns->mac_remote_faults);
2107 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
2108 ns->rx_length_errors);
2109 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
2110 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
2111 for (i = 0; i < 8; i++) {
2112 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
2113 i, ns->priority_xon_rx[i]);
2114 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
2115 i, ns->priority_xoff_rx[i]);
2117 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
2118 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
2119 for (i = 0; i < 8; i++) {
2120 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
2121 i, ns->priority_xon_tx[i]);
2122 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
2123 i, ns->priority_xoff_tx[i]);
2124 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
2125 i, ns->priority_xon_2_xoff[i]);
2127 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
2128 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
2129 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
2130 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
2131 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
2132 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
2133 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
2134 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
2135 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
2136 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
2137 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
2138 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
2139 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
2140 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
2141 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
2142 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
2143 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
2144 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
2145 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2146 ns->mac_short_packet_dropped);
2147 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
2148 ns->checksum_error);
2149 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
2150 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2153 /* Reset the statistics */
2155 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2157 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2158 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2160 /* Mark PF and VSI stats to update the offset, aka "reset" */
2161 pf->offset_loaded = false;
2163 pf->main_vsi->offset_loaded = false;
2165 /* read the stats, reading current register values into offset */
2166 i40e_read_stats_registers(pf, hw);
2170 i40e_xstats_calc_num(void)
2172 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2173 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2174 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2178 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstats *xstats,
2181 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2182 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2183 unsigned i, count, prio;
2184 struct i40e_hw_port_stats *hw_stats = &pf->stats;
2186 count = i40e_xstats_calc_num();
2190 i40e_read_stats_registers(pf, hw);
2197 /* Get stats from i40e_eth_stats struct */
2198 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2199 snprintf(xstats[count].name, sizeof(xstats[count].name),
2200 "%s", rte_i40e_stats_strings[i].name);
2201 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2202 rte_i40e_stats_strings[i].offset);
2206 /* Get individiual stats from i40e_hw_port struct */
2207 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2208 snprintf(xstats[count].name, sizeof(xstats[count].name),
2209 "%s", rte_i40e_hw_port_strings[i].name);
2210 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2211 rte_i40e_hw_port_strings[i].offset);
2215 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2216 for (prio = 0; prio < 8; prio++) {
2217 snprintf(xstats[count].name,
2218 sizeof(xstats[count].name),
2219 "rx_priority%u_%s", prio,
2220 rte_i40e_rxq_prio_strings[i].name);
2221 xstats[count].value =
2222 *(uint64_t *)(((char *)hw_stats) +
2223 rte_i40e_rxq_prio_strings[i].offset +
2224 (sizeof(uint64_t) * prio));
2229 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2230 for (prio = 0; prio < 8; prio++) {
2231 snprintf(xstats[count].name,
2232 sizeof(xstats[count].name),
2233 "tx_priority%u_%s", prio,
2234 rte_i40e_txq_prio_strings[i].name);
2235 xstats[count].value =
2236 *(uint64_t *)(((char *)hw_stats) +
2237 rte_i40e_txq_prio_strings[i].offset +
2238 (sizeof(uint64_t) * prio));
2247 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2248 __rte_unused uint16_t queue_id,
2249 __rte_unused uint8_t stat_idx,
2250 __rte_unused uint8_t is_rx)
2252 PMD_INIT_FUNC_TRACE();
2258 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2260 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2261 struct i40e_vsi *vsi = pf->main_vsi;
2263 dev_info->max_rx_queues = vsi->nb_qps;
2264 dev_info->max_tx_queues = vsi->nb_qps;
2265 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2266 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2267 dev_info->max_mac_addrs = vsi->max_macaddrs;
2268 dev_info->max_vfs = dev->pci_dev->max_vfs;
2269 dev_info->rx_offload_capa =
2270 DEV_RX_OFFLOAD_VLAN_STRIP |
2271 DEV_RX_OFFLOAD_QINQ_STRIP |
2272 DEV_RX_OFFLOAD_IPV4_CKSUM |
2273 DEV_RX_OFFLOAD_UDP_CKSUM |
2274 DEV_RX_OFFLOAD_TCP_CKSUM;
2275 dev_info->tx_offload_capa =
2276 DEV_TX_OFFLOAD_VLAN_INSERT |
2277 DEV_TX_OFFLOAD_QINQ_INSERT |
2278 DEV_TX_OFFLOAD_IPV4_CKSUM |
2279 DEV_TX_OFFLOAD_UDP_CKSUM |
2280 DEV_TX_OFFLOAD_TCP_CKSUM |
2281 DEV_TX_OFFLOAD_SCTP_CKSUM |
2282 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2283 DEV_TX_OFFLOAD_TCP_TSO;
2284 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2286 dev_info->reta_size = pf->hash_lut_size;
2287 dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2289 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2291 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2292 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2293 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2295 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2299 dev_info->default_txconf = (struct rte_eth_txconf) {
2301 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2302 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2303 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2305 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2306 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2307 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2308 ETH_TXQ_FLAGS_NOOFFLOADS,
2311 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2312 .nb_max = I40E_MAX_RING_DESC,
2313 .nb_min = I40E_MIN_RING_DESC,
2314 .nb_align = I40E_ALIGN_RING_DESC,
2317 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2318 .nb_max = I40E_MAX_RING_DESC,
2319 .nb_min = I40E_MIN_RING_DESC,
2320 .nb_align = I40E_ALIGN_RING_DESC,
2323 if (pf->flags & I40E_FLAG_VMDQ) {
2324 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2325 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2326 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2327 pf->max_nb_vmdq_vsi;
2328 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2329 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2330 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2335 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2337 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2338 struct i40e_vsi *vsi = pf->main_vsi;
2339 PMD_INIT_FUNC_TRACE();
2342 return i40e_vsi_add_vlan(vsi, vlan_id);
2344 return i40e_vsi_delete_vlan(vsi, vlan_id);
2348 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2349 enum rte_vlan_type vlan_type,
2352 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2353 uint64_t reg_r = 0, reg_w = 0;
2354 uint16_t reg_id = 0;
2357 switch (vlan_type) {
2358 case ETH_VLAN_TYPE_OUTER:
2361 case ETH_VLAN_TYPE_INNER:
2366 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2369 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2371 if (ret != I40E_SUCCESS) {
2372 PMD_DRV_LOG(ERR, "Fail to debug read from "
2373 "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2377 PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2378 "0x%08"PRIx64"", reg_id, reg_r);
2380 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2381 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2382 if (reg_r == reg_w) {
2384 PMD_DRV_LOG(DEBUG, "No need to write");
2388 ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2390 if (ret != I40E_SUCCESS) {
2392 PMD_DRV_LOG(ERR, "Fail to debug write to "
2393 "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2396 PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2397 "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2403 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2405 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2406 struct i40e_vsi *vsi = pf->main_vsi;
2408 if (mask & ETH_VLAN_FILTER_MASK) {
2409 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2410 i40e_vsi_config_vlan_filter(vsi, TRUE);
2412 i40e_vsi_config_vlan_filter(vsi, FALSE);
2415 if (mask & ETH_VLAN_STRIP_MASK) {
2416 /* Enable or disable VLAN stripping */
2417 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2418 i40e_vsi_config_vlan_stripping(vsi, TRUE);
2420 i40e_vsi_config_vlan_stripping(vsi, FALSE);
2423 if (mask & ETH_VLAN_EXTEND_MASK) {
2424 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
2425 i40e_vsi_config_double_vlan(vsi, TRUE);
2427 i40e_vsi_config_double_vlan(vsi, FALSE);
2432 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2433 __rte_unused uint16_t queue,
2434 __rte_unused int on)
2436 PMD_INIT_FUNC_TRACE();
2440 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2442 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2443 struct i40e_vsi *vsi = pf->main_vsi;
2444 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2445 struct i40e_vsi_vlan_pvid_info info;
2447 memset(&info, 0, sizeof(info));
2450 info.config.pvid = pvid;
2452 info.config.reject.tagged =
2453 data->dev_conf.txmode.hw_vlan_reject_tagged;
2454 info.config.reject.untagged =
2455 data->dev_conf.txmode.hw_vlan_reject_untagged;
2458 return i40e_vsi_vlan_pvid_set(vsi, &info);
2462 i40e_dev_led_on(struct rte_eth_dev *dev)
2464 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2465 uint32_t mode = i40e_led_get(hw);
2468 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2474 i40e_dev_led_off(struct rte_eth_dev *dev)
2476 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2477 uint32_t mode = i40e_led_get(hw);
2480 i40e_led_set(hw, 0, false);
2486 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2488 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2489 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2491 fc_conf->pause_time = pf->fc_conf.pause_time;
2492 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2493 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2495 /* Return current mode according to actual setting*/
2496 switch (hw->fc.current_mode) {
2498 fc_conf->mode = RTE_FC_FULL;
2500 case I40E_FC_TX_PAUSE:
2501 fc_conf->mode = RTE_FC_TX_PAUSE;
2503 case I40E_FC_RX_PAUSE:
2504 fc_conf->mode = RTE_FC_RX_PAUSE;
2508 fc_conf->mode = RTE_FC_NONE;
2515 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2517 uint32_t mflcn_reg, fctrl_reg, reg;
2518 uint32_t max_high_water;
2519 uint8_t i, aq_failure;
2523 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2524 [RTE_FC_NONE] = I40E_FC_NONE,
2525 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2526 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2527 [RTE_FC_FULL] = I40E_FC_FULL
2530 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2532 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2533 if ((fc_conf->high_water > max_high_water) ||
2534 (fc_conf->high_water < fc_conf->low_water)) {
2535 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2536 "High_water must <= %d.", max_high_water);
2540 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2541 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2542 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2544 pf->fc_conf.pause_time = fc_conf->pause_time;
2545 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2546 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2548 PMD_INIT_FUNC_TRACE();
2550 /* All the link flow control related enable/disable register
2551 * configuration is handle by the F/W
2553 err = i40e_set_fc(hw, &aq_failure, true);
2557 if (i40e_is_40G_device(hw->device_id)) {
2558 /* Configure flow control refresh threshold,
2559 * the value for stat_tx_pause_refresh_timer[8]
2560 * is used for global pause operation.
2564 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2565 pf->fc_conf.pause_time);
2567 /* configure the timer value included in transmitted pause
2569 * the value for stat_tx_pause_quanta[8] is used for global
2572 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2573 pf->fc_conf.pause_time);
2575 fctrl_reg = I40E_READ_REG(hw,
2576 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2578 if (fc_conf->mac_ctrl_frame_fwd != 0)
2579 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2581 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2583 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2586 /* Configure pause time (2 TCs per register) */
2587 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2588 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2589 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2591 /* Configure flow control refresh threshold value */
2592 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2593 pf->fc_conf.pause_time / 2);
2595 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2597 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2598 *depending on configuration
2600 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2601 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2602 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2604 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2605 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2608 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2611 /* config the water marker both based on the packets and bytes */
2612 I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2613 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2614 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2615 I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2616 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2617 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2618 I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2619 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2621 I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2622 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2625 I40E_WRITE_FLUSH(hw);
2631 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2632 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2634 PMD_INIT_FUNC_TRACE();
2639 /* Add a MAC address, and update filters */
2641 i40e_macaddr_add(struct rte_eth_dev *dev,
2642 struct ether_addr *mac_addr,
2643 __rte_unused uint32_t index,
2646 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2647 struct i40e_mac_filter_info mac_filter;
2648 struct i40e_vsi *vsi;
2651 /* If VMDQ not enabled or configured, return */
2652 if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
2653 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2654 pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
2659 if (pool > pf->nb_cfg_vmdq_vsi) {
2660 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2661 pool, pf->nb_cfg_vmdq_vsi);
2665 (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2666 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2667 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2669 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
2674 vsi = pf->vmdq[pool - 1].vsi;
2676 ret = i40e_vsi_add_mac(vsi, &mac_filter);
2677 if (ret != I40E_SUCCESS) {
2678 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2683 /* Remove a MAC address, and update filters */
2685 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2687 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2688 struct i40e_vsi *vsi;
2689 struct rte_eth_dev_data *data = dev->data;
2690 struct ether_addr *macaddr;
2695 macaddr = &(data->mac_addrs[index]);
2697 pool_sel = dev->data->mac_pool_sel[index];
2699 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
2700 if (pool_sel & (1ULL << i)) {
2704 /* No VMDQ pool enabled or configured */
2705 if (!(pf->flags | I40E_FLAG_VMDQ) ||
2706 (i > pf->nb_cfg_vmdq_vsi)) {
2707 PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
2711 vsi = pf->vmdq[i - 1].vsi;
2713 ret = i40e_vsi_delete_mac(vsi, macaddr);
2716 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
2723 /* Set perfect match or hash match of MAC and VLAN for a VF */
2725 i40e_vf_mac_filter_set(struct i40e_pf *pf,
2726 struct rte_eth_mac_filter *filter,
2730 struct i40e_mac_filter_info mac_filter;
2731 struct ether_addr old_mac;
2732 struct ether_addr *new_mac;
2733 struct i40e_pf_vf *vf = NULL;
2738 PMD_DRV_LOG(ERR, "Invalid PF argument.");
2741 hw = I40E_PF_TO_HW(pf);
2743 if (filter == NULL) {
2744 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
2748 new_mac = &filter->mac_addr;
2750 if (is_zero_ether_addr(new_mac)) {
2751 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
2755 vf_id = filter->dst_id;
2757 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
2758 PMD_DRV_LOG(ERR, "Invalid argument.");
2761 vf = &pf->vfs[vf_id];
2763 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
2764 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
2769 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
2770 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
2772 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
2775 mac_filter.filter_type = filter->filter_type;
2776 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
2777 if (ret != I40E_SUCCESS) {
2778 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
2781 ether_addr_copy(new_mac, &pf->dev_addr);
2783 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
2785 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
2786 if (ret != I40E_SUCCESS) {
2787 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
2791 /* Clear device address as it has been removed */
2792 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
2793 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
2799 /* MAC filter handle */
2801 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
2804 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2805 struct rte_eth_mac_filter *filter;
2806 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2807 int ret = I40E_NOT_SUPPORTED;
2809 filter = (struct rte_eth_mac_filter *)(arg);
2811 switch (filter_op) {
2812 case RTE_ETH_FILTER_NOP:
2815 case RTE_ETH_FILTER_ADD:
2816 i40e_pf_disable_irq0(hw);
2818 ret = i40e_vf_mac_filter_set(pf, filter, 1);
2819 i40e_pf_enable_irq0(hw);
2821 case RTE_ETH_FILTER_DELETE:
2822 i40e_pf_disable_irq0(hw);
2824 ret = i40e_vf_mac_filter_set(pf, filter, 0);
2825 i40e_pf_enable_irq0(hw);
2828 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2829 ret = I40E_ERR_PARAM;
2837 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2839 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2840 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2846 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2847 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
2850 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2854 uint32_t *lut_dw = (uint32_t *)lut;
2855 uint16_t i, lut_size_dw = lut_size / 4;
2857 for (i = 0; i < lut_size_dw; i++)
2858 lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
2865 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2867 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2868 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2874 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2875 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
2878 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2882 uint32_t *lut_dw = (uint32_t *)lut;
2883 uint16_t i, lut_size_dw = lut_size / 4;
2885 for (i = 0; i < lut_size_dw; i++)
2886 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
2887 I40E_WRITE_FLUSH(hw);
2894 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
2895 struct rte_eth_rss_reta_entry64 *reta_conf,
2898 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2899 uint16_t i, lut_size = pf->hash_lut_size;
2900 uint16_t idx, shift;
2904 if (reta_size != lut_size ||
2905 reta_size > ETH_RSS_RETA_SIZE_512) {
2906 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2907 "(%d) doesn't match the number hardware can supported "
2908 "(%d)\n", reta_size, lut_size);
2912 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2914 PMD_DRV_LOG(ERR, "No memory can be allocated");
2917 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2920 for (i = 0; i < reta_size; i++) {
2921 idx = i / RTE_RETA_GROUP_SIZE;
2922 shift = i % RTE_RETA_GROUP_SIZE;
2923 if (reta_conf[idx].mask & (1ULL << shift))
2924 lut[i] = reta_conf[idx].reta[shift];
2926 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
2935 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
2936 struct rte_eth_rss_reta_entry64 *reta_conf,
2939 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2940 uint16_t i, lut_size = pf->hash_lut_size;
2941 uint16_t idx, shift;
2945 if (reta_size != lut_size ||
2946 reta_size > ETH_RSS_RETA_SIZE_512) {
2947 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2948 "(%d) doesn't match the number hardware can supported "
2949 "(%d)\n", reta_size, lut_size);
2953 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2955 PMD_DRV_LOG(ERR, "No memory can be allocated");
2959 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
2962 for (i = 0; i < reta_size; i++) {
2963 idx = i / RTE_RETA_GROUP_SIZE;
2964 shift = i % RTE_RETA_GROUP_SIZE;
2965 if (reta_conf[idx].mask & (1ULL << shift))
2966 reta_conf[idx].reta[shift] = lut[i];
2976 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
2977 * @hw: pointer to the HW structure
2978 * @mem: pointer to mem struct to fill out
2979 * @size: size of memory requested
2980 * @alignment: what to align the allocation to
2982 enum i40e_status_code
2983 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2984 struct i40e_dma_mem *mem,
2988 const struct rte_memzone *mz = NULL;
2989 char z_name[RTE_MEMZONE_NAMESIZE];
2992 return I40E_ERR_PARAM;
2994 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
2995 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
2996 alignment, RTE_PGSIZE_2M);
2998 return I40E_ERR_NO_MEMORY;
3002 mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3003 mem->zone = (const void *)mz;
3004 PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3005 "%"PRIu64, mz->name, mem->pa);
3007 return I40E_SUCCESS;
3011 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3012 * @hw: pointer to the HW structure
3013 * @mem: ptr to mem struct to free
3015 enum i40e_status_code
3016 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3017 struct i40e_dma_mem *mem)
3020 return I40E_ERR_PARAM;
3022 PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3023 "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3025 rte_memzone_free((const struct rte_memzone *)mem->zone);
3030 return I40E_SUCCESS;
3034 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3035 * @hw: pointer to the HW structure
3036 * @mem: pointer to mem struct to fill out
3037 * @size: size of memory requested
3039 enum i40e_status_code
3040 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3041 struct i40e_virt_mem *mem,
3045 return I40E_ERR_PARAM;
3048 mem->va = rte_zmalloc("i40e", size, 0);
3051 return I40E_SUCCESS;
3053 return I40E_ERR_NO_MEMORY;
3057 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3058 * @hw: pointer to the HW structure
3059 * @mem: pointer to mem struct to free
3061 enum i40e_status_code
3062 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3063 struct i40e_virt_mem *mem)
3066 return I40E_ERR_PARAM;
3071 return I40E_SUCCESS;
3075 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3077 rte_spinlock_init(&sp->spinlock);
3081 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3083 rte_spinlock_lock(&sp->spinlock);
3087 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3089 rte_spinlock_unlock(&sp->spinlock);
3093 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3099 * Get the hardware capabilities, which will be parsed
3100 * and saved into struct i40e_hw.
3103 i40e_get_cap(struct i40e_hw *hw)
3105 struct i40e_aqc_list_capabilities_element_resp *buf;
3106 uint16_t len, size = 0;
3109 /* Calculate a huge enough buff for saving response data temporarily */
3110 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3111 I40E_MAX_CAP_ELE_NUM;
3112 buf = rte_zmalloc("i40e", len, 0);
3114 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3115 return I40E_ERR_NO_MEMORY;
3118 /* Get, parse the capabilities and save it to hw */
3119 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3120 i40e_aqc_opc_list_func_capabilities, NULL);
3121 if (ret != I40E_SUCCESS)
3122 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3124 /* Free the temporary buffer after being used */
3131 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3133 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3134 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3135 uint16_t qp_count = 0, vsi_count = 0;
3137 if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3138 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3141 /* Add the parameter init for LFC */
3142 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3143 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3144 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3146 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3147 pf->max_num_vsi = hw->func_caps.num_vsis;
3148 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3149 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3150 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3152 /* FDir queue/VSI allocation */
3153 pf->fdir_qp_offset = 0;
3154 if (hw->func_caps.fd) {
3155 pf->flags |= I40E_FLAG_FDIR;
3156 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3158 pf->fdir_nb_qps = 0;
3160 qp_count += pf->fdir_nb_qps;
3163 /* LAN queue/VSI allocation */
3164 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3165 if (!hw->func_caps.rss) {
3168 pf->flags |= I40E_FLAG_RSS;
3169 if (hw->mac.type == I40E_MAC_X722)
3170 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3171 pf->lan_nb_qps = pf->lan_nb_qp_max;
3173 qp_count += pf->lan_nb_qps;
3176 /* VF queue/VSI allocation */
3177 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3178 if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3179 pf->flags |= I40E_FLAG_SRIOV;
3180 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3181 pf->vf_num = dev->pci_dev->max_vfs;
3182 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3183 "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3184 pf->vf_nb_qps * pf->vf_num);
3189 qp_count += pf->vf_nb_qps * pf->vf_num;
3190 vsi_count += pf->vf_num;
3192 /* VMDq queue/VSI allocation */
3193 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3194 pf->vmdq_nb_qps = 0;
3195 pf->max_nb_vmdq_vsi = 0;
3196 if (hw->func_caps.vmdq) {
3197 if (qp_count < hw->func_caps.num_tx_qp &&
3198 vsi_count < hw->func_caps.num_vsis) {
3199 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3200 qp_count) / pf->vmdq_nb_qp_max;
3202 /* Limit the maximum number of VMDq vsi to the maximum
3203 * ethdev can support
3205 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3206 hw->func_caps.num_vsis - vsi_count);
3207 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3209 if (pf->max_nb_vmdq_vsi) {
3210 pf->flags |= I40E_FLAG_VMDQ;
3211 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3212 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3213 "per VMDQ VSI, in total %u queues",
3214 pf->max_nb_vmdq_vsi,
3215 pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3216 pf->max_nb_vmdq_vsi);
3218 PMD_DRV_LOG(INFO, "No enough queues left for "
3222 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3225 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3226 vsi_count += pf->max_nb_vmdq_vsi;
3228 if (hw->func_caps.dcb)
3229 pf->flags |= I40E_FLAG_DCB;
3231 if (qp_count > hw->func_caps.num_tx_qp) {
3232 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3233 "the hardware maximum %u", qp_count,
3234 hw->func_caps.num_tx_qp);
3237 if (vsi_count > hw->func_caps.num_vsis) {
3238 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3239 "the hardware maximum %u", vsi_count,
3240 hw->func_caps.num_vsis);
3248 i40e_pf_get_switch_config(struct i40e_pf *pf)
3250 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3251 struct i40e_aqc_get_switch_config_resp *switch_config;
3252 struct i40e_aqc_switch_config_element_resp *element;
3253 uint16_t start_seid = 0, num_reported;
3256 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3257 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3258 if (!switch_config) {
3259 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3263 /* Get the switch configurations */
3264 ret = i40e_aq_get_switch_config(hw, switch_config,
3265 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3266 if (ret != I40E_SUCCESS) {
3267 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3270 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3271 if (num_reported != 1) { /* The number should be 1 */
3272 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3276 /* Parse the switch configuration elements */
3277 element = &(switch_config->element[0]);
3278 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3279 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3280 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3282 PMD_DRV_LOG(INFO, "Unknown element type");
3285 rte_free(switch_config);
3291 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3294 struct pool_entry *entry;
3296 if (pool == NULL || num == 0)
3299 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3300 if (entry == NULL) {
3301 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3305 /* queue heap initialize */
3306 pool->num_free = num;
3307 pool->num_alloc = 0;
3309 LIST_INIT(&pool->alloc_list);
3310 LIST_INIT(&pool->free_list);
3312 /* Initialize element */
3316 LIST_INSERT_HEAD(&pool->free_list, entry, next);
3321 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3323 struct pool_entry *entry;
3328 LIST_FOREACH(entry, &pool->alloc_list, next) {
3329 LIST_REMOVE(entry, next);
3333 LIST_FOREACH(entry, &pool->free_list, next) {
3334 LIST_REMOVE(entry, next);
3339 pool->num_alloc = 0;
3341 LIST_INIT(&pool->alloc_list);
3342 LIST_INIT(&pool->free_list);
3346 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3349 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3350 uint32_t pool_offset;
3354 PMD_DRV_LOG(ERR, "Invalid parameter");
3358 pool_offset = base - pool->base;
3359 /* Lookup in alloc list */
3360 LIST_FOREACH(entry, &pool->alloc_list, next) {
3361 if (entry->base == pool_offset) {
3362 valid_entry = entry;
3363 LIST_REMOVE(entry, next);
3368 /* Not find, return */
3369 if (valid_entry == NULL) {
3370 PMD_DRV_LOG(ERR, "Failed to find entry");
3375 * Found it, move it to free list and try to merge.
3376 * In order to make merge easier, always sort it by qbase.
3377 * Find adjacent prev and last entries.
3380 LIST_FOREACH(entry, &pool->free_list, next) {
3381 if (entry->base > valid_entry->base) {
3389 /* Try to merge with next one*/
3391 /* Merge with next one */
3392 if (valid_entry->base + valid_entry->len == next->base) {
3393 next->base = valid_entry->base;
3394 next->len += valid_entry->len;
3395 rte_free(valid_entry);
3402 /* Merge with previous one */
3403 if (prev->base + prev->len == valid_entry->base) {
3404 prev->len += valid_entry->len;
3405 /* If it merge with next one, remove next node */
3407 LIST_REMOVE(valid_entry, next);
3408 rte_free(valid_entry);
3410 rte_free(valid_entry);
3416 /* Not find any entry to merge, insert */
3419 LIST_INSERT_AFTER(prev, valid_entry, next);
3420 else if (next != NULL)
3421 LIST_INSERT_BEFORE(next, valid_entry, next);
3422 else /* It's empty list, insert to head */
3423 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3426 pool->num_free += valid_entry->len;
3427 pool->num_alloc -= valid_entry->len;
3433 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3436 struct pool_entry *entry, *valid_entry;
3438 if (pool == NULL || num == 0) {
3439 PMD_DRV_LOG(ERR, "Invalid parameter");
3443 if (pool->num_free < num) {
3444 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3445 num, pool->num_free);
3450 /* Lookup in free list and find most fit one */
3451 LIST_FOREACH(entry, &pool->free_list, next) {
3452 if (entry->len >= num) {
3454 if (entry->len == num) {
3455 valid_entry = entry;
3458 if (valid_entry == NULL || valid_entry->len > entry->len)
3459 valid_entry = entry;
3463 /* Not find one to satisfy the request, return */
3464 if (valid_entry == NULL) {
3465 PMD_DRV_LOG(ERR, "No valid entry found");
3469 * The entry have equal queue number as requested,
3470 * remove it from alloc_list.
3472 if (valid_entry->len == num) {
3473 LIST_REMOVE(valid_entry, next);
3476 * The entry have more numbers than requested,
3477 * create a new entry for alloc_list and minus its
3478 * queue base and number in free_list.
3480 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3481 if (entry == NULL) {
3482 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3486 entry->base = valid_entry->base;
3488 valid_entry->base += num;
3489 valid_entry->len -= num;
3490 valid_entry = entry;
3493 /* Insert it into alloc list, not sorted */
3494 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3496 pool->num_free -= valid_entry->len;
3497 pool->num_alloc += valid_entry->len;
3499 return valid_entry->base + pool->base;
3503 * bitmap_is_subset - Check whether src2 is subset of src1
3506 bitmap_is_subset(uint8_t src1, uint8_t src2)
3508 return !((src1 ^ src2) & src2);
3511 static enum i40e_status_code
3512 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3514 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3516 /* If DCB is not supported, only default TC is supported */
3517 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3518 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3519 return I40E_NOT_SUPPORTED;
3522 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3523 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3524 "HW support 0x%x", hw->func_caps.enabled_tcmap,
3526 return I40E_NOT_SUPPORTED;
3528 return I40E_SUCCESS;
3532 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3533 struct i40e_vsi_vlan_pvid_info *info)
3536 struct i40e_vsi_context ctxt;
3537 uint8_t vlan_flags = 0;
3540 if (vsi == NULL || info == NULL) {
3541 PMD_DRV_LOG(ERR, "invalid parameters");
3542 return I40E_ERR_PARAM;
3546 vsi->info.pvid = info->config.pvid;
3548 * If insert pvid is enabled, only tagged pkts are
3549 * allowed to be sent out.
3551 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3552 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3555 if (info->config.reject.tagged == 0)
3556 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3558 if (info->config.reject.untagged == 0)
3559 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3561 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3562 I40E_AQ_VSI_PVLAN_MODE_MASK);
3563 vsi->info.port_vlan_flags |= vlan_flags;
3564 vsi->info.valid_sections =
3565 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3566 memset(&ctxt, 0, sizeof(ctxt));
3567 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3568 ctxt.seid = vsi->seid;
3570 hw = I40E_VSI_TO_HW(vsi);
3571 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3572 if (ret != I40E_SUCCESS)
3573 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3579 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3581 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3583 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3585 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3586 if (ret != I40E_SUCCESS)
3590 PMD_DRV_LOG(ERR, "seid not valid");
3594 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3595 tc_bw_data.tc_valid_bits = enabled_tcmap;
3596 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3597 tc_bw_data.tc_bw_credits[i] =
3598 (enabled_tcmap & (1 << i)) ? 1 : 0;
3600 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3601 if (ret != I40E_SUCCESS) {
3602 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3606 (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3607 sizeof(vsi->info.qs_handle));
3608 return I40E_SUCCESS;
3611 static enum i40e_status_code
3612 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3613 struct i40e_aqc_vsi_properties_data *info,
3614 uint8_t enabled_tcmap)
3616 enum i40e_status_code ret;
3617 int i, total_tc = 0;
3618 uint16_t qpnum_per_tc, bsf, qp_idx;
3620 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3621 if (ret != I40E_SUCCESS)
3624 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3625 if (enabled_tcmap & (1 << i))
3627 vsi->enabled_tc = enabled_tcmap;
3629 /* Number of queues per enabled TC */
3630 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3631 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3632 bsf = rte_bsf32(qpnum_per_tc);
3634 /* Adjust the queue number to actual queues that can be applied */
3635 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3636 vsi->nb_qps = qpnum_per_tc * total_tc;
3639 * Configure TC and queue mapping parameters, for enabled TC,
3640 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3641 * default queue will serve it.
3644 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3645 if (vsi->enabled_tc & (1 << i)) {
3646 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3647 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3648 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
3649 qp_idx += qpnum_per_tc;
3651 info->tc_mapping[i] = 0;
3654 /* Associate queue number with VSI */
3655 if (vsi->type == I40E_VSI_SRIOV) {
3656 info->mapping_flags |=
3657 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
3658 for (i = 0; i < vsi->nb_qps; i++)
3659 info->queue_mapping[i] =
3660 rte_cpu_to_le_16(vsi->base_queue + i);
3662 info->mapping_flags |=
3663 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3664 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3666 info->valid_sections |=
3667 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
3669 return I40E_SUCCESS;
3673 i40e_veb_release(struct i40e_veb *veb)
3675 struct i40e_vsi *vsi;
3678 if (veb == NULL || veb->associate_vsi == NULL)
3681 if (!TAILQ_EMPTY(&veb->head)) {
3682 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
3686 vsi = veb->associate_vsi;
3687 hw = I40E_VSI_TO_HW(vsi);
3689 vsi->uplink_seid = veb->uplink_seid;
3690 i40e_aq_delete_element(hw, veb->seid, NULL);
3693 return I40E_SUCCESS;
3697 static struct i40e_veb *
3698 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
3700 struct i40e_veb *veb;
3704 if (NULL == pf || vsi == NULL) {
3705 PMD_DRV_LOG(ERR, "veb setup failed, "
3706 "associated VSI shouldn't null");
3709 hw = I40E_PF_TO_HW(pf);
3711 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
3713 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
3717 veb->associate_vsi = vsi;
3718 TAILQ_INIT(&veb->head);
3719 veb->uplink_seid = vsi->uplink_seid;
3721 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
3722 I40E_DEFAULT_TCMAP, false, &veb->seid, false, NULL);
3724 if (ret != I40E_SUCCESS) {
3725 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
3726 hw->aq.asq_last_status);
3730 /* get statistics index */
3731 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
3732 &veb->stats_idx, NULL, NULL, NULL);
3733 if (ret != I40E_SUCCESS) {
3734 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
3735 hw->aq.asq_last_status);
3739 /* Get VEB bandwidth, to be implemented */
3740 /* Now associated vsi binding to the VEB, set uplink to this VEB */
3741 vsi->uplink_seid = veb->seid;
3750 i40e_vsi_release(struct i40e_vsi *vsi)
3754 struct i40e_vsi_list *vsi_list;
3756 struct i40e_mac_filter *f;
3759 return I40E_SUCCESS;
3761 pf = I40E_VSI_TO_PF(vsi);
3762 hw = I40E_VSI_TO_HW(vsi);
3764 /* VSI has child to attach, release child first */
3766 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
3767 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
3769 TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
3771 i40e_veb_release(vsi->veb);
3774 /* Remove all macvlan filters of the VSI */
3775 i40e_vsi_remove_all_macvlan_filter(vsi);
3776 TAILQ_FOREACH(f, &vsi->mac_list, next)
3779 if (vsi->type != I40E_VSI_MAIN) {
3780 /* Remove vsi from parent's sibling list */
3781 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
3782 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
3783 return I40E_ERR_PARAM;
3785 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
3786 &vsi->sib_vsi_list, list);
3788 /* Remove all switch element of the VSI */
3789 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
3790 if (ret != I40E_SUCCESS)
3791 PMD_DRV_LOG(ERR, "Failed to delete element");
3793 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
3795 if (vsi->type != I40E_VSI_SRIOV)
3796 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
3799 return I40E_SUCCESS;
3803 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
3805 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3806 struct i40e_aqc_remove_macvlan_element_data def_filter;
3807 struct i40e_mac_filter_info filter;
3810 if (vsi->type != I40E_VSI_MAIN)
3811 return I40E_ERR_CONFIG;
3812 memset(&def_filter, 0, sizeof(def_filter));
3813 (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
3815 def_filter.vlan_tag = 0;
3816 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
3817 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
3818 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
3819 if (ret != I40E_SUCCESS) {
3820 struct i40e_mac_filter *f;
3821 struct ether_addr *mac;
3823 PMD_DRV_LOG(WARNING, "Cannot remove the default "
3825 /* It needs to add the permanent mac into mac list */
3826 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3828 PMD_DRV_LOG(ERR, "failed to allocate memory");
3829 return I40E_ERR_NO_MEMORY;
3831 mac = &f->mac_info.mac_addr;
3832 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
3834 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3835 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3840 (void)rte_memcpy(&filter.mac_addr,
3841 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
3842 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3843 return i40e_vsi_add_mac(vsi, &filter);
3847 * i40e_vsi_get_bw_config - Query VSI BW Information
3848 * @vsi: the VSI to be queried
3850 * Returns 0 on success, negative value on failure
3852 static enum i40e_status_code
3853 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
3855 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
3856 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
3857 struct i40e_hw *hw = &vsi->adapter->hw;
3862 memset(&bw_config, 0, sizeof(bw_config));
3863 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3864 if (ret != I40E_SUCCESS) {
3865 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
3866 hw->aq.asq_last_status);
3870 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
3871 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
3872 &ets_sla_config, NULL);
3873 if (ret != I40E_SUCCESS) {
3874 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
3875 "configuration %u", hw->aq.asq_last_status);
3879 /* store and print out BW info */
3880 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
3881 vsi->bw_info.bw_max = bw_config.max_bw;
3882 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
3883 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
3884 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
3885 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
3887 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3888 vsi->bw_info.bw_ets_share_credits[i] =
3889 ets_sla_config.share_credits[i];
3890 vsi->bw_info.bw_ets_credits[i] =
3891 rte_le_to_cpu_16(ets_sla_config.credits[i]);
3892 /* 4 bits per TC, 4th bit is reserved */
3893 vsi->bw_info.bw_ets_max[i] =
3894 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
3895 RTE_LEN2MASK(3, uint8_t));
3896 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
3897 vsi->bw_info.bw_ets_share_credits[i]);
3898 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
3899 vsi->bw_info.bw_ets_credits[i]);
3900 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
3901 vsi->bw_info.bw_ets_max[i]);
3904 return I40E_SUCCESS;
3909 i40e_vsi_setup(struct i40e_pf *pf,
3910 enum i40e_vsi_type type,
3911 struct i40e_vsi *uplink_vsi,
3912 uint16_t user_param)
3914 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3915 struct i40e_vsi *vsi;
3916 struct i40e_mac_filter_info filter;
3918 struct i40e_vsi_context ctxt;
3919 struct ether_addr broadcast =
3920 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
3922 if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
3923 PMD_DRV_LOG(ERR, "VSI setup failed, "
3924 "VSI link shouldn't be NULL");
3928 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
3929 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
3930 "uplink VSI should be NULL");
3934 /* If uplink vsi didn't setup VEB, create one first */
3935 if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
3936 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
3938 if (NULL == uplink_vsi->veb) {
3939 PMD_DRV_LOG(ERR, "VEB setup failed");
3944 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
3946 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
3949 TAILQ_INIT(&vsi->mac_list);
3951 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
3952 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
3953 vsi->parent_vsi = uplink_vsi;
3954 vsi->user_param = user_param;
3955 /* Allocate queues */
3956 switch (vsi->type) {
3957 case I40E_VSI_MAIN :
3958 vsi->nb_qps = pf->lan_nb_qps;
3960 case I40E_VSI_SRIOV :
3961 vsi->nb_qps = pf->vf_nb_qps;
3963 case I40E_VSI_VMDQ2:
3964 vsi->nb_qps = pf->vmdq_nb_qps;
3967 vsi->nb_qps = pf->fdir_nb_qps;
3973 * The filter status descriptor is reported in rx queue 0,
3974 * while the tx queue for fdir filter programming has no
3975 * such constraints, can be non-zero queues.
3976 * To simplify it, choose FDIR vsi use queue 0 pair.
3977 * To make sure it will use queue 0 pair, queue allocation
3978 * need be done before this function is called
3980 if (type != I40E_VSI_FDIR) {
3981 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
3983 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
3987 vsi->base_queue = ret;
3989 vsi->base_queue = I40E_FDIR_QUEUE_ID;
3991 /* VF has MSIX interrupt in VF range, don't allocate here */
3992 if (type == I40E_VSI_MAIN) {
3993 ret = i40e_res_pool_alloc(&pf->msix_pool,
3994 RTE_MIN(vsi->nb_qps,
3995 RTE_MAX_RXTX_INTR_VEC_ID));
3997 PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
3999 goto fail_queue_alloc;
4001 vsi->msix_intr = ret;
4002 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4003 } else if (type != I40E_VSI_SRIOV) {
4004 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4006 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4007 goto fail_queue_alloc;
4009 vsi->msix_intr = ret;
4017 if (type == I40E_VSI_MAIN) {
4018 /* For main VSI, no need to add since it's default one */
4019 vsi->uplink_seid = pf->mac_seid;
4020 vsi->seid = pf->main_vsi_seid;
4021 /* Bind queues with specific MSIX interrupt */
4023 * Needs 2 interrupt at least, one for misc cause which will
4024 * enabled from OS side, Another for queues binding the
4025 * interrupt from device side only.
4028 /* Get default VSI parameters from hardware */
4029 memset(&ctxt, 0, sizeof(ctxt));
4030 ctxt.seid = vsi->seid;
4031 ctxt.pf_num = hw->pf_id;
4032 ctxt.uplink_seid = vsi->uplink_seid;
4034 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4035 if (ret != I40E_SUCCESS) {
4036 PMD_DRV_LOG(ERR, "Failed to get VSI params");
4037 goto fail_msix_alloc;
4039 (void)rte_memcpy(&vsi->info, &ctxt.info,
4040 sizeof(struct i40e_aqc_vsi_properties_data));
4041 vsi->vsi_id = ctxt.vsi_number;
4042 vsi->info.valid_sections = 0;
4044 /* Configure tc, enabled TC0 only */
4045 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4047 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4048 goto fail_msix_alloc;
4051 /* TC, queue mapping */
4052 memset(&ctxt, 0, sizeof(ctxt));
4053 vsi->info.valid_sections |=
4054 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4055 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4056 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4057 (void)rte_memcpy(&ctxt.info, &vsi->info,
4058 sizeof(struct i40e_aqc_vsi_properties_data));
4059 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4060 I40E_DEFAULT_TCMAP);
4061 if (ret != I40E_SUCCESS) {
4062 PMD_DRV_LOG(ERR, "Failed to configure "
4063 "TC queue mapping");
4064 goto fail_msix_alloc;
4066 ctxt.seid = vsi->seid;
4067 ctxt.pf_num = hw->pf_id;
4068 ctxt.uplink_seid = vsi->uplink_seid;
4071 /* Update VSI parameters */
4072 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4073 if (ret != I40E_SUCCESS) {
4074 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4075 goto fail_msix_alloc;
4078 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4079 sizeof(vsi->info.tc_mapping));
4080 (void)rte_memcpy(&vsi->info.queue_mapping,
4081 &ctxt.info.queue_mapping,
4082 sizeof(vsi->info.queue_mapping));
4083 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4084 vsi->info.valid_sections = 0;
4086 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4090 * Updating default filter settings are necessary to prevent
4091 * reception of tagged packets.
4092 * Some old firmware configurations load a default macvlan
4093 * filter which accepts both tagged and untagged packets.
4094 * The updating is to use a normal filter instead if needed.
4095 * For NVM 4.2.2 or after, the updating is not needed anymore.
4096 * The firmware with correct configurations load the default
4097 * macvlan filter which is expected and cannot be removed.
4099 i40e_update_default_filter_setting(vsi);
4100 i40e_config_qinq(hw, vsi);
4101 } else if (type == I40E_VSI_SRIOV) {
4102 memset(&ctxt, 0, sizeof(ctxt));
4104 * For other VSI, the uplink_seid equals to uplink VSI's
4105 * uplink_seid since they share same VEB
4107 vsi->uplink_seid = uplink_vsi->uplink_seid;
4108 ctxt.pf_num = hw->pf_id;
4109 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4110 ctxt.uplink_seid = vsi->uplink_seid;
4111 ctxt.connection_type = 0x1;
4112 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4115 * Do not configure switch ID to enable VEB switch by
4116 * I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB. Because in Fortville,
4117 * if the source mac address of packet sent from VF is not
4118 * listed in the VEB's mac table, the VEB will switch the
4119 * packet back to the VF. Need to enable it when HW issue
4123 /* Configure port/vlan */
4124 ctxt.info.valid_sections |=
4125 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4126 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4127 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4128 I40E_DEFAULT_TCMAP);
4129 if (ret != I40E_SUCCESS) {
4130 PMD_DRV_LOG(ERR, "Failed to configure "
4131 "TC queue mapping");
4132 goto fail_msix_alloc;
4134 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4135 ctxt.info.valid_sections |=
4136 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4138 * Since VSI is not created yet, only configure parameter,
4139 * will add vsi below.
4142 i40e_config_qinq(hw, vsi);
4143 } else if (type == I40E_VSI_VMDQ2) {
4144 memset(&ctxt, 0, sizeof(ctxt));
4146 * For other VSI, the uplink_seid equals to uplink VSI's
4147 * uplink_seid since they share same VEB
4149 vsi->uplink_seid = uplink_vsi->uplink_seid;
4150 ctxt.pf_num = hw->pf_id;
4152 ctxt.uplink_seid = vsi->uplink_seid;
4153 ctxt.connection_type = 0x1;
4154 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4156 ctxt.info.valid_sections |=
4157 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4158 /* user_param carries flag to enable loop back */
4160 ctxt.info.switch_id =
4161 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4162 ctxt.info.switch_id |=
4163 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4166 /* Configure port/vlan */
4167 ctxt.info.valid_sections |=
4168 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4169 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4170 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4171 I40E_DEFAULT_TCMAP);
4172 if (ret != I40E_SUCCESS) {
4173 PMD_DRV_LOG(ERR, "Failed to configure "
4174 "TC queue mapping");
4175 goto fail_msix_alloc;
4177 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4178 ctxt.info.valid_sections |=
4179 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4180 } else if (type == I40E_VSI_FDIR) {
4181 memset(&ctxt, 0, sizeof(ctxt));
4182 vsi->uplink_seid = uplink_vsi->uplink_seid;
4183 ctxt.pf_num = hw->pf_id;
4185 ctxt.uplink_seid = vsi->uplink_seid;
4186 ctxt.connection_type = 0x1; /* regular data port */
4187 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4188 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4189 I40E_DEFAULT_TCMAP);
4190 if (ret != I40E_SUCCESS) {
4191 PMD_DRV_LOG(ERR, "Failed to configure "
4192 "TC queue mapping.");
4193 goto fail_msix_alloc;
4195 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4196 ctxt.info.valid_sections |=
4197 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4199 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4200 goto fail_msix_alloc;
4203 if (vsi->type != I40E_VSI_MAIN) {
4204 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4205 if (ret != I40E_SUCCESS) {
4206 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4207 hw->aq.asq_last_status);
4208 goto fail_msix_alloc;
4210 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4211 vsi->info.valid_sections = 0;
4212 vsi->seid = ctxt.seid;
4213 vsi->vsi_id = ctxt.vsi_number;
4214 vsi->sib_vsi_list.vsi = vsi;
4215 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4216 &vsi->sib_vsi_list, list);
4219 /* MAC/VLAN configuration */
4220 (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4221 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4223 ret = i40e_vsi_add_mac(vsi, &filter);
4224 if (ret != I40E_SUCCESS) {
4225 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4226 goto fail_msix_alloc;
4229 /* Get VSI BW information */
4230 i40e_vsi_get_bw_config(vsi);
4233 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4235 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4241 /* Configure vlan filter on or off */
4243 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4246 struct i40e_mac_filter *f;
4247 struct i40e_mac_filter_info *mac_filter;
4248 enum rte_mac_filter_type desired_filter;
4249 int ret = I40E_SUCCESS;
4252 /* Filter to match MAC and VLAN */
4253 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4255 /* Filter to match only MAC */
4256 desired_filter = RTE_MAC_PERFECT_MATCH;
4261 mac_filter = rte_zmalloc("mac_filter_info_data",
4262 num * sizeof(*mac_filter), 0);
4263 if (mac_filter == NULL) {
4264 PMD_DRV_LOG(ERR, "failed to allocate memory");
4265 return I40E_ERR_NO_MEMORY;
4270 /* Remove all existing mac */
4271 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4272 mac_filter[i] = f->mac_info;
4273 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4275 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4276 on ? "enable" : "disable");
4282 /* Override with new filter */
4283 for (i = 0; i < num; i++) {
4284 mac_filter[i].filter_type = desired_filter;
4285 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4287 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4288 on ? "enable" : "disable");
4294 rte_free(mac_filter);
4298 /* Configure vlan stripping on or off */
4300 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4302 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4303 struct i40e_vsi_context ctxt;
4305 int ret = I40E_SUCCESS;
4307 /* Check if it has been already on or off */
4308 if (vsi->info.valid_sections &
4309 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4311 if ((vsi->info.port_vlan_flags &
4312 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4313 return 0; /* already on */
4315 if ((vsi->info.port_vlan_flags &
4316 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4317 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4318 return 0; /* already off */
4323 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4325 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4326 vsi->info.valid_sections =
4327 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4328 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4329 vsi->info.port_vlan_flags |= vlan_flags;
4330 ctxt.seid = vsi->seid;
4331 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4332 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4334 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4335 on ? "enable" : "disable");
4341 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4343 struct rte_eth_dev_data *data = dev->data;
4347 /* Apply vlan offload setting */
4348 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
4349 i40e_vlan_offload_set(dev, mask);
4351 /* Apply double-vlan setting, not implemented yet */
4353 /* Apply pvid setting */
4354 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4355 data->dev_conf.txmode.hw_vlan_insert_pvid);
4357 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4363 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4365 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4367 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4371 i40e_update_flow_control(struct i40e_hw *hw)
4373 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4374 struct i40e_link_status link_status;
4375 uint32_t rxfc = 0, txfc = 0, reg;
4379 memset(&link_status, 0, sizeof(link_status));
4380 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4381 if (ret != I40E_SUCCESS) {
4382 PMD_DRV_LOG(ERR, "Failed to get link status information");
4383 goto write_reg; /* Disable flow control */
4386 an_info = hw->phy.link_info.an_info;
4387 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4388 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4389 ret = I40E_ERR_NOT_READY;
4390 goto write_reg; /* Disable flow control */
4393 * If link auto negotiation is enabled, flow control needs to
4394 * be configured according to it
4396 switch (an_info & I40E_LINK_PAUSE_RXTX) {
4397 case I40E_LINK_PAUSE_RXTX:
4400 hw->fc.current_mode = I40E_FC_FULL;
4402 case I40E_AQ_LINK_PAUSE_RX:
4404 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4406 case I40E_AQ_LINK_PAUSE_TX:
4408 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4411 hw->fc.current_mode = I40E_FC_NONE;
4416 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4417 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4418 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4419 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4420 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4421 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4428 i40e_pf_setup(struct i40e_pf *pf)
4430 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4431 struct i40e_filter_control_settings settings;
4432 struct i40e_vsi *vsi;
4435 /* Clear all stats counters */
4436 pf->offset_loaded = FALSE;
4437 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4438 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4440 ret = i40e_pf_get_switch_config(pf);
4441 if (ret != I40E_SUCCESS) {
4442 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4445 if (pf->flags & I40E_FLAG_FDIR) {
4446 /* make queue allocated first, let FDIR use queue pair 0*/
4447 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4448 if (ret != I40E_FDIR_QUEUE_ID) {
4449 PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4451 pf->flags &= ~I40E_FLAG_FDIR;
4454 /* main VSI setup */
4455 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4457 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4458 return I40E_ERR_NOT_READY;
4462 /* Configure filter control */
4463 memset(&settings, 0, sizeof(settings));
4464 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4465 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4466 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4467 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4469 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4470 hw->func_caps.rss_table_size);
4471 return I40E_ERR_PARAM;
4473 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4474 "size: %u\n", hw->func_caps.rss_table_size);
4475 pf->hash_lut_size = hw->func_caps.rss_table_size;
4477 /* Enable ethtype and macvlan filters */
4478 settings.enable_ethtype = TRUE;
4479 settings.enable_macvlan = TRUE;
4480 ret = i40e_set_filter_control(hw, &settings);
4482 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4485 /* Update flow control according to the auto negotiation */
4486 i40e_update_flow_control(hw);
4488 return I40E_SUCCESS;
4492 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4498 * Set or clear TX Queue Disable flags,
4499 * which is required by hardware.
4501 i40e_pre_tx_queue_cfg(hw, q_idx, on);
4502 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4504 /* Wait until the request is finished */
4505 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4506 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4507 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4508 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4509 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4515 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4516 return I40E_SUCCESS; /* already on, skip next steps */
4518 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4519 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4521 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4522 return I40E_SUCCESS; /* already off, skip next steps */
4523 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4525 /* Write the register */
4526 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4527 /* Check the result */
4528 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4529 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4530 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4532 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4533 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
4536 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4537 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4541 /* Check if it is timeout */
4542 if (j >= I40E_CHK_Q_ENA_COUNT) {
4543 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
4544 (on ? "enable" : "disable"), q_idx);
4545 return I40E_ERR_TIMEOUT;
4548 return I40E_SUCCESS;
4551 /* Swith on or off the tx queues */
4553 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
4555 struct rte_eth_dev_data *dev_data = pf->dev_data;
4556 struct i40e_tx_queue *txq;
4557 struct rte_eth_dev *dev = pf->adapter->eth_dev;
4561 for (i = 0; i < dev_data->nb_tx_queues; i++) {
4562 txq = dev_data->tx_queues[i];
4563 /* Don't operate the queue if not configured or
4564 * if starting only per queue */
4565 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
4568 ret = i40e_dev_tx_queue_start(dev, i);
4570 ret = i40e_dev_tx_queue_stop(dev, i);
4571 if ( ret != I40E_SUCCESS)
4575 return I40E_SUCCESS;
4579 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4584 /* Wait until the request is finished */
4585 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4586 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4587 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4588 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4589 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
4594 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
4595 return I40E_SUCCESS; /* Already on, skip next steps */
4596 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
4598 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4599 return I40E_SUCCESS; /* Already off, skip next steps */
4600 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
4603 /* Write the register */
4604 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
4605 /* Check the result */
4606 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4607 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4608 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
4610 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4611 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
4614 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
4615 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
4620 /* Check if it is timeout */
4621 if (j >= I40E_CHK_Q_ENA_COUNT) {
4622 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
4623 (on ? "enable" : "disable"), q_idx);
4624 return I40E_ERR_TIMEOUT;
4627 return I40E_SUCCESS;
4629 /* Switch on or off the rx queues */
4631 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
4633 struct rte_eth_dev_data *dev_data = pf->dev_data;
4634 struct i40e_rx_queue *rxq;
4635 struct rte_eth_dev *dev = pf->adapter->eth_dev;
4639 for (i = 0; i < dev_data->nb_rx_queues; i++) {
4640 rxq = dev_data->rx_queues[i];
4641 /* Don't operate the queue if not configured or
4642 * if starting only per queue */
4643 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
4646 ret = i40e_dev_rx_queue_start(dev, i);
4648 ret = i40e_dev_rx_queue_stop(dev, i);
4649 if (ret != I40E_SUCCESS)
4653 return I40E_SUCCESS;
4656 /* Switch on or off all the rx/tx queues */
4658 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
4663 /* enable rx queues before enabling tx queues */
4664 ret = i40e_dev_switch_rx_queues(pf, on);
4666 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
4669 ret = i40e_dev_switch_tx_queues(pf, on);
4671 /* Stop tx queues before stopping rx queues */
4672 ret = i40e_dev_switch_tx_queues(pf, on);
4674 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
4677 ret = i40e_dev_switch_rx_queues(pf, on);
4683 /* Initialize VSI for TX */
4685 i40e_dev_tx_init(struct i40e_pf *pf)
4687 struct rte_eth_dev_data *data = pf->dev_data;
4689 uint32_t ret = I40E_SUCCESS;
4690 struct i40e_tx_queue *txq;
4692 for (i = 0; i < data->nb_tx_queues; i++) {
4693 txq = data->tx_queues[i];
4694 if (!txq || !txq->q_set)
4696 ret = i40e_tx_queue_init(txq);
4697 if (ret != I40E_SUCCESS)
4700 if (ret == I40E_SUCCESS)
4701 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
4707 /* Initialize VSI for RX */
4709 i40e_dev_rx_init(struct i40e_pf *pf)
4711 struct rte_eth_dev_data *data = pf->dev_data;
4712 int ret = I40E_SUCCESS;
4714 struct i40e_rx_queue *rxq;
4716 i40e_pf_config_mq_rx(pf);
4717 for (i = 0; i < data->nb_rx_queues; i++) {
4718 rxq = data->rx_queues[i];
4719 if (!rxq || !rxq->q_set)
4722 ret = i40e_rx_queue_init(rxq);
4723 if (ret != I40E_SUCCESS) {
4724 PMD_DRV_LOG(ERR, "Failed to do RX queue "
4729 if (ret == I40E_SUCCESS)
4730 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
4737 i40e_dev_rxtx_init(struct i40e_pf *pf)
4741 err = i40e_dev_tx_init(pf);
4743 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
4746 err = i40e_dev_rx_init(pf);
4748 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
4756 i40e_vmdq_setup(struct rte_eth_dev *dev)
4758 struct rte_eth_conf *conf = &dev->data->dev_conf;
4759 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4760 int i, err, conf_vsis, j, loop;
4761 struct i40e_vsi *vsi;
4762 struct i40e_vmdq_info *vmdq_info;
4763 struct rte_eth_vmdq_rx_conf *vmdq_conf;
4764 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4767 * Disable interrupt to avoid message from VF. Furthermore, it will
4768 * avoid race condition in VSI creation/destroy.
4770 i40e_pf_disable_irq0(hw);
4772 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
4773 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
4777 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
4778 if (conf_vsis > pf->max_nb_vmdq_vsi) {
4779 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
4780 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
4781 pf->max_nb_vmdq_vsi);
4785 if (pf->vmdq != NULL) {
4786 PMD_INIT_LOG(INFO, "VMDQ already configured");
4790 pf->vmdq = rte_zmalloc("vmdq_info_struct",
4791 sizeof(*vmdq_info) * conf_vsis, 0);
4793 if (pf->vmdq == NULL) {
4794 PMD_INIT_LOG(ERR, "Failed to allocate memory");
4798 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
4800 /* Create VMDQ VSI */
4801 for (i = 0; i < conf_vsis; i++) {
4802 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
4803 vmdq_conf->enable_loop_back);
4805 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
4809 vmdq_info = &pf->vmdq[i];
4811 vmdq_info->vsi = vsi;
4813 pf->nb_cfg_vmdq_vsi = conf_vsis;
4815 /* Configure Vlan */
4816 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
4817 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
4818 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
4819 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
4820 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
4821 vmdq_conf->pool_map[i].vlan_id, j);
4823 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
4824 vmdq_conf->pool_map[i].vlan_id);
4826 PMD_INIT_LOG(ERR, "Failed to add vlan");
4834 i40e_pf_enable_irq0(hw);
4839 for (i = 0; i < conf_vsis; i++)
4840 if (pf->vmdq[i].vsi == NULL)
4843 i40e_vsi_release(pf->vmdq[i].vsi);
4847 i40e_pf_enable_irq0(hw);
4852 i40e_stat_update_32(struct i40e_hw *hw,
4860 new_data = (uint64_t)I40E_READ_REG(hw, reg);
4864 if (new_data >= *offset)
4865 *stat = (uint64_t)(new_data - *offset);
4867 *stat = (uint64_t)((new_data +
4868 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
4872 i40e_stat_update_48(struct i40e_hw *hw,
4881 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
4882 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
4883 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
4888 if (new_data >= *offset)
4889 *stat = new_data - *offset;
4891 *stat = (uint64_t)((new_data +
4892 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
4894 *stat &= I40E_48_BIT_MASK;
4899 i40e_pf_disable_irq0(struct i40e_hw *hw)
4901 /* Disable all interrupt types */
4902 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
4903 I40E_WRITE_FLUSH(hw);
4908 i40e_pf_enable_irq0(struct i40e_hw *hw)
4910 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
4911 I40E_PFINT_DYN_CTL0_INTENA_MASK |
4912 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
4913 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
4914 I40E_WRITE_FLUSH(hw);
4918 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
4920 /* read pending request and disable first */
4921 i40e_pf_disable_irq0(hw);
4922 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
4923 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
4924 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
4927 /* Link no queues with irq0 */
4928 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
4929 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
4933 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
4935 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4936 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4939 uint32_t index, offset, val;
4944 * Try to find which VF trigger a reset, use absolute VF id to access
4945 * since the reg is global register.
4947 for (i = 0; i < pf->vf_num; i++) {
4948 abs_vf_id = hw->func_caps.vf_base_id + i;
4949 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
4950 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
4951 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
4952 /* VFR event occured */
4953 if (val & (0x1 << offset)) {
4956 /* Clear the event first */
4957 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
4959 PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
4961 * Only notify a VF reset event occured,
4962 * don't trigger another SW reset
4964 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
4965 if (ret != I40E_SUCCESS)
4966 PMD_DRV_LOG(ERR, "Failed to do VF reset");
4972 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
4974 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4975 struct i40e_arq_event_info info;
4976 uint16_t pending, opcode;
4979 info.buf_len = I40E_AQ_BUF_SZ;
4980 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
4981 if (!info.msg_buf) {
4982 PMD_DRV_LOG(ERR, "Failed to allocate mem");
4988 ret = i40e_clean_arq_element(hw, &info, &pending);
4990 if (ret != I40E_SUCCESS) {
4991 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
4992 "aq_err: %u", hw->aq.asq_last_status);
4995 opcode = rte_le_to_cpu_16(info.desc.opcode);
4998 case i40e_aqc_opc_send_msg_to_pf:
4999 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5000 i40e_pf_host_handle_vf_msg(dev,
5001 rte_le_to_cpu_16(info.desc.retval),
5002 rte_le_to_cpu_32(info.desc.cookie_high),
5003 rte_le_to_cpu_32(info.desc.cookie_low),
5008 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5013 rte_free(info.msg_buf);
5017 * Interrupt handler is registered as the alarm callback for handling LSC
5018 * interrupt in a definite of time, in order to wait the NIC into a stable
5019 * state. Currently it waits 1 sec in i40e for the link up interrupt, and
5020 * no need for link down interrupt.
5023 i40e_dev_interrupt_delayed_handler(void *param)
5025 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5026 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5029 /* read interrupt causes again */
5030 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5032 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5033 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5034 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
5035 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5036 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
5037 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5038 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
5039 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5040 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
5041 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5042 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
5044 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5045 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
5046 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5047 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
5048 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5050 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5051 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
5052 i40e_dev_handle_vfr_event(dev);
5054 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5055 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
5056 i40e_dev_handle_aq_msg(dev);
5059 /* handle the link up interrupt in an alarm callback */
5060 i40e_dev_link_update(dev, 0);
5061 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
5063 i40e_pf_enable_irq0(hw);
5064 rte_intr_enable(&(dev->pci_dev->intr_handle));
5068 * Interrupt handler triggered by NIC for handling
5069 * specific interrupt.
5072 * Pointer to interrupt handle.
5074 * The address of parameter (struct rte_eth_dev *) regsitered before.
5080 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
5083 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5084 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5087 /* Disable interrupt */
5088 i40e_pf_disable_irq0(hw);
5090 /* read out interrupt causes */
5091 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5093 /* No interrupt event indicated */
5094 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5095 PMD_DRV_LOG(INFO, "No interrupt event");
5098 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5099 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5100 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5101 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5102 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5103 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5104 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5105 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5106 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5107 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5108 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5109 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5110 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5111 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5112 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5113 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5115 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5116 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5117 i40e_dev_handle_vfr_event(dev);
5119 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5120 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5121 i40e_dev_handle_aq_msg(dev);
5124 /* Link Status Change interrupt */
5125 if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
5126 #define I40E_US_PER_SECOND 1000000
5127 struct rte_eth_link link;
5129 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
5130 memset(&link, 0, sizeof(link));
5131 rte_i40e_dev_atomic_read_link_status(dev, &link);
5132 i40e_dev_link_update(dev, 0);
5135 * For link up interrupt, it needs to wait 1 second to let the
5136 * hardware be a stable state. Otherwise several consecutive
5137 * interrupts can be observed.
5138 * For link down interrupt, no need to wait.
5140 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
5141 i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
5144 _rte_eth_dev_callback_process(dev,
5145 RTE_ETH_EVENT_INTR_LSC);
5149 /* Enable interrupt */
5150 i40e_pf_enable_irq0(hw);
5151 rte_intr_enable(&(dev->pci_dev->intr_handle));
5155 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5156 struct i40e_macvlan_filter *filter,
5159 int ele_num, ele_buff_size;
5160 int num, actual_num, i;
5162 int ret = I40E_SUCCESS;
5163 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5164 struct i40e_aqc_add_macvlan_element_data *req_list;
5166 if (filter == NULL || total == 0)
5167 return I40E_ERR_PARAM;
5168 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5169 ele_buff_size = hw->aq.asq_buf_size;
5171 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5172 if (req_list == NULL) {
5173 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5174 return I40E_ERR_NO_MEMORY;
5179 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5180 memset(req_list, 0, ele_buff_size);
5182 for (i = 0; i < actual_num; i++) {
5183 (void)rte_memcpy(req_list[i].mac_addr,
5184 &filter[num + i].macaddr, ETH_ADDR_LEN);
5185 req_list[i].vlan_tag =
5186 rte_cpu_to_le_16(filter[num + i].vlan_id);
5188 switch (filter[num + i].filter_type) {
5189 case RTE_MAC_PERFECT_MATCH:
5190 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5191 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5193 case RTE_MACVLAN_PERFECT_MATCH:
5194 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5196 case RTE_MAC_HASH_MATCH:
5197 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5198 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5200 case RTE_MACVLAN_HASH_MATCH:
5201 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5204 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5205 ret = I40E_ERR_PARAM;
5209 req_list[i].queue_number = 0;
5211 req_list[i].flags = rte_cpu_to_le_16(flags);
5214 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5216 if (ret != I40E_SUCCESS) {
5217 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5221 } while (num < total);
5229 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5230 struct i40e_macvlan_filter *filter,
5233 int ele_num, ele_buff_size;
5234 int num, actual_num, i;
5236 int ret = I40E_SUCCESS;
5237 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5238 struct i40e_aqc_remove_macvlan_element_data *req_list;
5240 if (filter == NULL || total == 0)
5241 return I40E_ERR_PARAM;
5243 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5244 ele_buff_size = hw->aq.asq_buf_size;
5246 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5247 if (req_list == NULL) {
5248 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5249 return I40E_ERR_NO_MEMORY;
5254 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5255 memset(req_list, 0, ele_buff_size);
5257 for (i = 0; i < actual_num; i++) {
5258 (void)rte_memcpy(req_list[i].mac_addr,
5259 &filter[num + i].macaddr, ETH_ADDR_LEN);
5260 req_list[i].vlan_tag =
5261 rte_cpu_to_le_16(filter[num + i].vlan_id);
5263 switch (filter[num + i].filter_type) {
5264 case RTE_MAC_PERFECT_MATCH:
5265 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5266 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5268 case RTE_MACVLAN_PERFECT_MATCH:
5269 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5271 case RTE_MAC_HASH_MATCH:
5272 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5273 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5275 case RTE_MACVLAN_HASH_MATCH:
5276 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5279 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5280 ret = I40E_ERR_PARAM;
5283 req_list[i].flags = rte_cpu_to_le_16(flags);
5286 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5288 if (ret != I40E_SUCCESS) {
5289 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5293 } while (num < total);
5300 /* Find out specific MAC filter */
5301 static struct i40e_mac_filter *
5302 i40e_find_mac_filter(struct i40e_vsi *vsi,
5303 struct ether_addr *macaddr)
5305 struct i40e_mac_filter *f;
5307 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5308 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5316 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5319 uint32_t vid_idx, vid_bit;
5321 if (vlan_id > ETH_VLAN_ID_MAX)
5324 vid_idx = I40E_VFTA_IDX(vlan_id);
5325 vid_bit = I40E_VFTA_BIT(vlan_id);
5327 if (vsi->vfta[vid_idx] & vid_bit)
5334 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5335 uint16_t vlan_id, bool on)
5337 uint32_t vid_idx, vid_bit;
5339 if (vlan_id > ETH_VLAN_ID_MAX)
5342 vid_idx = I40E_VFTA_IDX(vlan_id);
5343 vid_bit = I40E_VFTA_BIT(vlan_id);
5346 vsi->vfta[vid_idx] |= vid_bit;
5348 vsi->vfta[vid_idx] &= ~vid_bit;
5352 * Find all vlan options for specific mac addr,
5353 * return with actual vlan found.
5356 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5357 struct i40e_macvlan_filter *mv_f,
5358 int num, struct ether_addr *addr)
5364 * Not to use i40e_find_vlan_filter to decrease the loop time,
5365 * although the code looks complex.
5367 if (num < vsi->vlan_num)
5368 return I40E_ERR_PARAM;
5371 for (j = 0; j < I40E_VFTA_SIZE; j++) {
5373 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5374 if (vsi->vfta[j] & (1 << k)) {
5376 PMD_DRV_LOG(ERR, "vlan number "
5378 return I40E_ERR_PARAM;
5380 (void)rte_memcpy(&mv_f[i].macaddr,
5381 addr, ETH_ADDR_LEN);
5383 j * I40E_UINT32_BIT_SIZE + k;
5389 return I40E_SUCCESS;
5393 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5394 struct i40e_macvlan_filter *mv_f,
5399 struct i40e_mac_filter *f;
5401 if (num < vsi->mac_num)
5402 return I40E_ERR_PARAM;
5404 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5406 PMD_DRV_LOG(ERR, "buffer number not match");
5407 return I40E_ERR_PARAM;
5409 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5411 mv_f[i].vlan_id = vlan;
5412 mv_f[i].filter_type = f->mac_info.filter_type;
5416 return I40E_SUCCESS;
5420 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5423 struct i40e_mac_filter *f;
5424 struct i40e_macvlan_filter *mv_f;
5425 int ret = I40E_SUCCESS;
5427 if (vsi == NULL || vsi->mac_num == 0)
5428 return I40E_ERR_PARAM;
5430 /* Case that no vlan is set */
5431 if (vsi->vlan_num == 0)
5434 num = vsi->mac_num * vsi->vlan_num;
5436 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5438 PMD_DRV_LOG(ERR, "failed to allocate memory");
5439 return I40E_ERR_NO_MEMORY;
5443 if (vsi->vlan_num == 0) {
5444 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5445 (void)rte_memcpy(&mv_f[i].macaddr,
5446 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5447 mv_f[i].vlan_id = 0;
5451 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5452 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5453 vsi->vlan_num, &f->mac_info.mac_addr);
5454 if (ret != I40E_SUCCESS)
5460 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5468 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5470 struct i40e_macvlan_filter *mv_f;
5472 int ret = I40E_SUCCESS;
5474 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5475 return I40E_ERR_PARAM;
5477 /* If it's already set, just return */
5478 if (i40e_find_vlan_filter(vsi,vlan))
5479 return I40E_SUCCESS;
5481 mac_num = vsi->mac_num;
5484 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5485 return I40E_ERR_PARAM;
5488 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5491 PMD_DRV_LOG(ERR, "failed to allocate memory");
5492 return I40E_ERR_NO_MEMORY;
5495 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5497 if (ret != I40E_SUCCESS)
5500 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5502 if (ret != I40E_SUCCESS)
5505 i40e_set_vlan_filter(vsi, vlan, 1);
5515 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5517 struct i40e_macvlan_filter *mv_f;
5519 int ret = I40E_SUCCESS;
5522 * Vlan 0 is the generic filter for untagged packets
5523 * and can't be removed.
5525 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5526 return I40E_ERR_PARAM;
5528 /* If can't find it, just return */
5529 if (!i40e_find_vlan_filter(vsi, vlan))
5530 return I40E_ERR_PARAM;
5532 mac_num = vsi->mac_num;
5535 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5536 return I40E_ERR_PARAM;
5539 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5542 PMD_DRV_LOG(ERR, "failed to allocate memory");
5543 return I40E_ERR_NO_MEMORY;
5546 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5548 if (ret != I40E_SUCCESS)
5551 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5553 if (ret != I40E_SUCCESS)
5556 /* This is last vlan to remove, replace all mac filter with vlan 0 */
5557 if (vsi->vlan_num == 1) {
5558 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5559 if (ret != I40E_SUCCESS)
5562 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5563 if (ret != I40E_SUCCESS)
5567 i40e_set_vlan_filter(vsi, vlan, 0);
5577 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
5579 struct i40e_mac_filter *f;
5580 struct i40e_macvlan_filter *mv_f;
5581 int i, vlan_num = 0;
5582 int ret = I40E_SUCCESS;
5584 /* If it's add and we've config it, return */
5585 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
5587 return I40E_SUCCESS;
5588 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
5589 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
5592 * If vlan_num is 0, that's the first time to add mac,
5593 * set mask for vlan_id 0.
5595 if (vsi->vlan_num == 0) {
5596 i40e_set_vlan_filter(vsi, 0, 1);
5599 vlan_num = vsi->vlan_num;
5600 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
5601 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
5604 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5606 PMD_DRV_LOG(ERR, "failed to allocate memory");
5607 return I40E_ERR_NO_MEMORY;
5610 for (i = 0; i < vlan_num; i++) {
5611 mv_f[i].filter_type = mac_filter->filter_type;
5612 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
5616 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5617 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
5618 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
5619 &mac_filter->mac_addr);
5620 if (ret != I40E_SUCCESS)
5624 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
5625 if (ret != I40E_SUCCESS)
5628 /* Add the mac addr into mac list */
5629 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5631 PMD_DRV_LOG(ERR, "failed to allocate memory");
5632 ret = I40E_ERR_NO_MEMORY;
5635 (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
5637 f->mac_info.filter_type = mac_filter->filter_type;
5638 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5649 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
5651 struct i40e_mac_filter *f;
5652 struct i40e_macvlan_filter *mv_f;
5654 enum rte_mac_filter_type filter_type;
5655 int ret = I40E_SUCCESS;
5657 /* Can't find it, return an error */
5658 f = i40e_find_mac_filter(vsi, addr);
5660 return I40E_ERR_PARAM;
5662 vlan_num = vsi->vlan_num;
5663 filter_type = f->mac_info.filter_type;
5664 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5665 filter_type == RTE_MACVLAN_HASH_MATCH) {
5666 if (vlan_num == 0) {
5667 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
5668 return I40E_ERR_PARAM;
5670 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
5671 filter_type == RTE_MAC_HASH_MATCH)
5674 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
5676 PMD_DRV_LOG(ERR, "failed to allocate memory");
5677 return I40E_ERR_NO_MEMORY;
5680 for (i = 0; i < vlan_num; i++) {
5681 mv_f[i].filter_type = filter_type;
5682 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5685 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
5686 filter_type == RTE_MACVLAN_HASH_MATCH) {
5687 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
5688 if (ret != I40E_SUCCESS)
5692 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
5693 if (ret != I40E_SUCCESS)
5696 /* Remove the mac addr into mac list */
5697 TAILQ_REMOVE(&vsi->mac_list, f, next);
5707 /* Configure hash enable flags for RSS */
5709 i40e_config_hena(uint64_t flags)
5716 if (flags & ETH_RSS_FRAG_IPV4)
5717 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
5718 if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
5719 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
5720 if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
5721 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
5722 if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
5723 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
5724 if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
5725 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
5726 if (flags & ETH_RSS_FRAG_IPV6)
5727 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
5728 if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
5729 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
5730 if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
5731 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
5732 if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
5733 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
5734 if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
5735 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
5736 if (flags & ETH_RSS_L2_PAYLOAD)
5737 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
5742 /* Parse the hash enable flags */
5744 i40e_parse_hena(uint64_t flags)
5746 uint64_t rss_hf = 0;
5750 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
5751 rss_hf |= ETH_RSS_FRAG_IPV4;
5752 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
5753 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
5754 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
5755 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
5756 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
5757 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
5758 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
5759 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
5760 if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
5761 rss_hf |= ETH_RSS_FRAG_IPV6;
5762 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
5763 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
5764 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
5765 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
5766 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
5767 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
5768 if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
5769 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
5770 if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
5771 rss_hf |= ETH_RSS_L2_PAYLOAD;
5778 i40e_pf_disable_rss(struct i40e_pf *pf)
5780 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5783 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
5784 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
5785 hena &= ~I40E_RSS_HENA_ALL;
5786 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5787 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5788 I40E_WRITE_FLUSH(hw);
5792 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
5794 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5795 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5798 if (!key || key_len == 0) {
5799 PMD_DRV_LOG(DEBUG, "No key to be configured");
5801 } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5803 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
5807 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5808 struct i40e_aqc_get_set_rss_key_data *key_dw =
5809 (struct i40e_aqc_get_set_rss_key_data *)key;
5811 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
5813 PMD_INIT_LOG(ERR, "Failed to configure RSS key "
5816 uint32_t *hash_key = (uint32_t *)key;
5819 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5820 i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
5821 I40E_WRITE_FLUSH(hw);
5828 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
5830 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
5831 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5834 if (!key || !key_len)
5837 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
5838 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
5839 (struct i40e_aqc_get_set_rss_key_data *)key);
5841 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
5845 uint32_t *key_dw = (uint32_t *)key;
5848 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5849 key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
5851 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
5857 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
5859 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5864 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
5865 rss_conf->rss_key_len);
5869 rss_hf = rss_conf->rss_hf;
5870 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
5871 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
5872 hena &= ~I40E_RSS_HENA_ALL;
5873 hena |= i40e_config_hena(rss_hf);
5874 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5875 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5876 I40E_WRITE_FLUSH(hw);
5882 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
5883 struct rte_eth_rss_conf *rss_conf)
5885 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5886 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5887 uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
5890 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
5891 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
5892 if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
5893 if (rss_hf != 0) /* Enable RSS */
5895 return 0; /* Nothing to do */
5898 if (rss_hf == 0) /* Disable RSS */
5901 return i40e_hw_rss_hash_set(pf, rss_conf);
5905 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
5906 struct rte_eth_rss_conf *rss_conf)
5908 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5909 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5912 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
5913 &rss_conf->rss_key_len);
5915 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
5916 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
5917 rss_conf->rss_hf = i40e_parse_hena(hena);
5923 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
5925 switch (filter_type) {
5926 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
5927 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
5929 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
5930 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
5932 case RTE_TUNNEL_FILTER_IMAC_TENID:
5933 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
5935 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
5936 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
5938 case ETH_TUNNEL_FILTER_IMAC:
5939 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
5941 case ETH_TUNNEL_FILTER_OIP:
5942 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
5944 case ETH_TUNNEL_FILTER_IIP:
5945 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
5948 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
5956 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
5957 struct rte_eth_tunnel_filter_conf *tunnel_filter,
5961 uint8_t i, tun_type = 0;
5962 /* internal varialbe to convert ipv6 byte order */
5963 uint32_t convert_ipv6[4];
5965 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5966 struct i40e_vsi *vsi = pf->main_vsi;
5967 struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter;
5968 struct i40e_aqc_add_remove_cloud_filters_element_data *pfilter;
5970 cld_filter = rte_zmalloc("tunnel_filter",
5971 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
5974 if (NULL == cld_filter) {
5975 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
5978 pfilter = cld_filter;
5980 ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
5981 ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
5983 pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
5984 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
5985 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
5986 rte_memcpy(&pfilter->ipaddr.v4.data,
5987 &rte_cpu_to_le_32(tunnel_filter->ip_addr.ipv4_addr),
5988 sizeof(pfilter->ipaddr.v4.data));
5990 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
5991 for (i = 0; i < 4; i++) {
5993 rte_cpu_to_le_32(tunnel_filter->ip_addr.ipv6_addr[i]);
5995 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
5996 sizeof(pfilter->ipaddr.v6.data));
5999 /* check tunneled type */
6000 switch (tunnel_filter->tunnel_type) {
6001 case RTE_TUNNEL_TYPE_VXLAN:
6002 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6004 case RTE_TUNNEL_TYPE_NVGRE:
6005 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6007 case RTE_TUNNEL_TYPE_IP_IN_GRE:
6008 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6011 /* Other tunnel types is not supported. */
6012 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6013 rte_free(cld_filter);
6017 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6020 rte_free(cld_filter);
6024 pfilter->flags |= rte_cpu_to_le_16(
6025 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6026 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6027 pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6028 pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6031 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6033 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6036 rte_free(cld_filter);
6041 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6045 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6046 if (pf->vxlan_ports[i] == port)
6054 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6058 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6060 idx = i40e_get_vxlan_port_idx(pf, port);
6062 /* Check if port already exists */
6064 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6068 /* Now check if there is space to add the new port */
6069 idx = i40e_get_vxlan_port_idx(pf, 0);
6071 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6072 "not adding port %d", port);
6076 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6079 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6083 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6086 /* New port: add it and mark its index in the bitmap */
6087 pf->vxlan_ports[idx] = port;
6088 pf->vxlan_bitmap |= (1 << idx);
6090 if (!(pf->flags & I40E_FLAG_VXLAN))
6091 pf->flags |= I40E_FLAG_VXLAN;
6097 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6100 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6102 if (!(pf->flags & I40E_FLAG_VXLAN)) {
6103 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6107 idx = i40e_get_vxlan_port_idx(pf, port);
6110 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6114 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6115 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6119 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6122 pf->vxlan_ports[idx] = 0;
6123 pf->vxlan_bitmap &= ~(1 << idx);
6125 if (!pf->vxlan_bitmap)
6126 pf->flags &= ~I40E_FLAG_VXLAN;
6131 /* Add UDP tunneling port */
6133 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6134 struct rte_eth_udp_tunnel *udp_tunnel)
6137 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6139 if (udp_tunnel == NULL)
6142 switch (udp_tunnel->prot_type) {
6143 case RTE_TUNNEL_TYPE_VXLAN:
6144 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6147 case RTE_TUNNEL_TYPE_GENEVE:
6148 case RTE_TUNNEL_TYPE_TEREDO:
6149 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6154 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6162 /* Remove UDP tunneling port */
6164 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6165 struct rte_eth_udp_tunnel *udp_tunnel)
6168 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6170 if (udp_tunnel == NULL)
6173 switch (udp_tunnel->prot_type) {
6174 case RTE_TUNNEL_TYPE_VXLAN:
6175 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6177 case RTE_TUNNEL_TYPE_GENEVE:
6178 case RTE_TUNNEL_TYPE_TEREDO:
6179 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6183 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6191 /* Calculate the maximum number of contiguous PF queues that are configured */
6193 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6195 struct rte_eth_dev_data *data = pf->dev_data;
6197 struct i40e_rx_queue *rxq;
6200 for (i = 0; i < pf->lan_nb_qps; i++) {
6201 rxq = data->rx_queues[i];
6202 if (rxq && rxq->q_set)
6213 i40e_pf_config_rss(struct i40e_pf *pf)
6215 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6216 struct rte_eth_rss_conf rss_conf;
6217 uint32_t i, lut = 0;
6221 * If both VMDQ and RSS enabled, not all of PF queues are configured.
6222 * It's necessary to calulate the actual PF queues that are configured.
6224 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6225 num = i40e_pf_calc_configured_queues_num(pf);
6227 num = pf->dev_data->nb_rx_queues;
6229 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6230 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6234 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6238 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6241 lut = (lut << 8) | (j & ((0x1 <<
6242 hw->func_caps.rss_table_entry_width) - 1));
6244 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6247 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6248 if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6249 i40e_pf_disable_rss(pf);
6252 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6253 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6254 /* Random default keys */
6255 static uint32_t rss_key_default[] = {0x6b793944,
6256 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6257 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6258 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6260 rss_conf.rss_key = (uint8_t *)rss_key_default;
6261 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6265 return i40e_hw_rss_hash_set(pf, &rss_conf);
6269 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6270 struct rte_eth_tunnel_filter_conf *filter)
6272 if (pf == NULL || filter == NULL) {
6273 PMD_DRV_LOG(ERR, "Invalid parameter");
6277 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6278 PMD_DRV_LOG(ERR, "Invalid queue ID");
6282 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6283 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6287 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6288 (is_zero_ether_addr(&filter->outer_mac))) {
6289 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6293 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6294 (is_zero_ether_addr(&filter->inner_mac))) {
6295 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6302 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6303 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
6305 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6310 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6311 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6314 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6315 } else if (len == 4) {
6316 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6318 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6323 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6330 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6331 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6337 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6344 switch (cfg->cfg_type) {
6345 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6346 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6349 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6357 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6358 enum rte_filter_op filter_op,
6361 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6362 int ret = I40E_ERR_PARAM;
6364 switch (filter_op) {
6365 case RTE_ETH_FILTER_SET:
6366 ret = i40e_dev_global_config_set(hw,
6367 (struct rte_eth_global_cfg *)arg);
6370 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6378 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6379 enum rte_filter_op filter_op,
6382 struct rte_eth_tunnel_filter_conf *filter;
6383 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6384 int ret = I40E_SUCCESS;
6386 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6388 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6389 return I40E_ERR_PARAM;
6391 switch (filter_op) {
6392 case RTE_ETH_FILTER_NOP:
6393 if (!(pf->flags & I40E_FLAG_VXLAN))
6394 ret = I40E_NOT_SUPPORTED;
6396 case RTE_ETH_FILTER_ADD:
6397 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6399 case RTE_ETH_FILTER_DELETE:
6400 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6403 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6404 ret = I40E_ERR_PARAM;
6412 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6415 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6418 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6419 ret = i40e_pf_config_rss(pf);
6421 i40e_pf_disable_rss(pf);
6426 /* Get the symmetric hash enable configurations per port */
6428 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6430 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6432 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6435 /* Set the symmetric hash enable configurations per port */
6437 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6439 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6442 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6443 PMD_DRV_LOG(INFO, "Symmetric hash has already "
6447 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6449 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6450 PMD_DRV_LOG(INFO, "Symmetric hash has already "
6454 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6456 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
6457 I40E_WRITE_FLUSH(hw);
6461 * Get global configurations of hash function type and symmetric hash enable
6462 * per flow type (pctype). Note that global configuration means it affects all
6463 * the ports on the same NIC.
6466 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6467 struct rte_eth_hash_global_conf *g_cfg)
6469 uint32_t reg, mask = I40E_FLOW_TYPES;
6471 enum i40e_filter_pctype pctype;
6473 memset(g_cfg, 0, sizeof(*g_cfg));
6474 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6475 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6476 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6478 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6479 PMD_DRV_LOG(DEBUG, "Hash function is %s",
6480 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6482 for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6483 if (!(mask & (1UL << i)))
6485 mask &= ~(1UL << i);
6486 /* Bit set indicats the coresponding flow type is supported */
6487 g_cfg->valid_bit_mask[0] |= (1UL << i);
6488 pctype = i40e_flowtype_to_pctype(i);
6489 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
6490 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6491 g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6498 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6501 uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6503 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
6504 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
6505 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
6506 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
6512 * As i40e supports less than 32 flow types, only first 32 bits need to
6515 mask0 = g_cfg->valid_bit_mask[0];
6516 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
6518 /* Check if any unsupported flow type configured */
6519 if ((mask0 | i40e_mask) ^ i40e_mask)
6522 if (g_cfg->valid_bit_mask[i])
6530 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
6536 * Set global configurations of hash function type and symmetric hash enable
6537 * per flow type (pctype). Note any modifying global configuration will affect
6538 * all the ports on the same NIC.
6541 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
6542 struct rte_eth_hash_global_conf *g_cfg)
6547 uint32_t mask0 = g_cfg->valid_bit_mask[0];
6548 enum i40e_filter_pctype pctype;
6550 /* Check the input parameters */
6551 ret = i40e_hash_global_config_check(g_cfg);
6555 for (i = 0; mask0 && i < UINT32_BIT; i++) {
6556 if (!(mask0 & (1UL << i)))
6558 mask0 &= ~(1UL << i);
6559 pctype = i40e_flowtype_to_pctype(i);
6560 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
6561 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
6562 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
6565 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6566 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
6568 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
6569 PMD_DRV_LOG(DEBUG, "Hash function already set to "
6573 reg |= I40E_GLQF_CTL_HTOEP_MASK;
6574 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
6576 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
6577 PMD_DRV_LOG(DEBUG, "Hash function already set to "
6581 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
6583 /* Use the default, and keep it as it is */
6586 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
6589 I40E_WRITE_FLUSH(hw);
6595 * Valid input sets for hash and flow director filters per PCTYPE
6598 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
6599 enum rte_filter_type filter)
6603 static const uint64_t valid_hash_inset_table[] = {
6604 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6605 I40E_INSET_DMAC | I40E_INSET_SMAC |
6606 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6607 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
6608 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
6609 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6610 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6611 I40E_INSET_FLEX_PAYLOAD,
6612 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6613 I40E_INSET_DMAC | I40E_INSET_SMAC |
6614 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6615 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6616 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6617 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6618 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6619 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6620 I40E_INSET_FLEX_PAYLOAD,
6621 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6622 I40E_INSET_DMAC | I40E_INSET_SMAC |
6623 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6624 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6625 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6626 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6627 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6628 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6629 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
6630 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6631 I40E_INSET_DMAC | I40E_INSET_SMAC |
6632 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6633 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6634 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6635 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6636 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6637 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6638 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6639 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6640 I40E_INSET_DMAC | I40E_INSET_SMAC |
6641 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6642 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
6643 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
6644 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
6645 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6646 I40E_INSET_FLEX_PAYLOAD,
6647 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6648 I40E_INSET_DMAC | I40E_INSET_SMAC |
6649 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6650 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6651 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6652 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
6653 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
6654 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
6655 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6656 I40E_INSET_DMAC | I40E_INSET_SMAC |
6657 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6658 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6659 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6660 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6661 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6662 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
6663 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6664 I40E_INSET_DMAC | I40E_INSET_SMAC |
6665 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6666 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6667 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6668 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6669 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6670 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
6671 I40E_INSET_FLEX_PAYLOAD,
6672 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6673 I40E_INSET_DMAC | I40E_INSET_SMAC |
6674 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6675 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6676 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6677 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6678 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
6679 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
6680 I40E_INSET_FLEX_PAYLOAD,
6681 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6682 I40E_INSET_DMAC | I40E_INSET_SMAC |
6683 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6684 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
6685 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
6686 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
6687 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
6688 I40E_INSET_FLEX_PAYLOAD,
6689 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6690 I40E_INSET_DMAC | I40E_INSET_SMAC |
6691 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
6692 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
6693 I40E_INSET_FLEX_PAYLOAD,
6697 * Flow director supports only fields defined in
6698 * union rte_eth_fdir_flow.
6700 static const uint64_t valid_fdir_inset_table[] = {
6701 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6702 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6703 I40E_INSET_FLEX_PAYLOAD,
6704 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6705 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6706 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6707 I40E_INSET_FLEX_PAYLOAD,
6708 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6709 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6710 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6711 I40E_INSET_FLEX_PAYLOAD,
6712 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6713 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6714 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6715 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6716 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6717 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6718 I40E_INSET_FLEX_PAYLOAD,
6719 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6720 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6721 I40E_INSET_FLEX_PAYLOAD,
6722 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6723 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6724 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6725 I40E_INSET_FLEX_PAYLOAD,
6726 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6727 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6728 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6729 I40E_INSET_FLEX_PAYLOAD,
6730 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6731 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6732 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6733 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
6734 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6735 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6736 I40E_INSET_FLEX_PAYLOAD,
6737 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6738 I40E_INSET_LAST_ETHER_TYPE | I40E_INSET_FLEX_PAYLOAD,
6741 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6743 if (filter == RTE_ETH_FILTER_HASH)
6744 valid = valid_hash_inset_table[pctype];
6746 valid = valid_fdir_inset_table[pctype];
6752 * Validate if the input set is allowed for a specific PCTYPE
6755 i40e_validate_input_set(enum i40e_filter_pctype pctype,
6756 enum rte_filter_type filter, uint64_t inset)
6760 valid = i40e_get_valid_input_set(pctype, filter);
6761 if (inset & (~valid))
6767 /* default input set fields combination per pctype */
6769 i40e_get_default_input_set(uint16_t pctype)
6771 static const uint64_t default_inset_table[] = {
6772 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
6773 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6774 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
6775 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6776 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6777 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
6778 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6779 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6780 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
6781 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
6782 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6784 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
6785 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
6786 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
6787 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6788 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
6789 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6790 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6791 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
6792 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6793 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
6794 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
6795 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
6796 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
6798 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
6799 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
6800 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
6801 I40E_INSET_LAST_ETHER_TYPE,
6804 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
6807 return default_inset_table[pctype];
6811 * Parse the input set from index to logical bit masks
6814 i40e_parse_input_set(uint64_t *inset,
6815 enum i40e_filter_pctype pctype,
6816 enum rte_eth_input_set_field *field,
6822 static const struct {
6823 enum rte_eth_input_set_field field;
6825 } inset_convert_table[] = {
6826 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
6827 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
6828 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
6829 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
6830 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
6831 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
6832 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
6833 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
6834 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
6835 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
6836 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
6837 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
6838 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
6839 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
6840 I40E_INSET_IPV6_NEXT_HDR},
6841 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
6842 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
6843 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
6844 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
6845 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
6846 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
6847 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
6848 I40E_INSET_SCTP_VT},
6849 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
6850 I40E_INSET_TUNNEL_DMAC},
6851 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
6852 I40E_INSET_VLAN_TUNNEL},
6853 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
6854 I40E_INSET_TUNNEL_ID},
6855 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
6856 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
6857 I40E_INSET_FLEX_PAYLOAD_W1},
6858 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
6859 I40E_INSET_FLEX_PAYLOAD_W2},
6860 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
6861 I40E_INSET_FLEX_PAYLOAD_W3},
6862 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
6863 I40E_INSET_FLEX_PAYLOAD_W4},
6864 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
6865 I40E_INSET_FLEX_PAYLOAD_W5},
6866 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
6867 I40E_INSET_FLEX_PAYLOAD_W6},
6868 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
6869 I40E_INSET_FLEX_PAYLOAD_W7},
6870 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
6871 I40E_INSET_FLEX_PAYLOAD_W8},
6874 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
6877 /* Only one item allowed for default or all */
6879 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
6880 *inset = i40e_get_default_input_set(pctype);
6882 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
6883 *inset = I40E_INSET_NONE;
6888 for (i = 0, *inset = 0; i < size; i++) {
6889 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
6890 if (field[i] == inset_convert_table[j].field) {
6891 *inset |= inset_convert_table[j].inset;
6896 /* It contains unsupported input set, return immediately */
6897 if (j == RTE_DIM(inset_convert_table))
6905 * Translate the input set from bit masks to register aware bit masks
6909 i40e_translate_input_set_reg(uint64_t input)
6914 static const struct {
6918 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
6919 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
6920 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
6921 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
6922 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
6923 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
6924 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
6925 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
6926 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
6927 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
6928 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
6929 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
6930 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
6931 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
6932 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
6933 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
6934 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
6935 {I40E_INSET_TUNNEL_DMAC,
6936 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
6937 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
6938 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
6939 {I40E_INSET_TUNNEL_SRC_PORT,
6940 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
6941 {I40E_INSET_TUNNEL_DST_PORT,
6942 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
6943 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
6944 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
6945 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
6946 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
6947 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
6948 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
6949 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
6950 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
6951 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
6957 /* Translate input set to register aware inset */
6958 for (i = 0; i < RTE_DIM(inset_map); i++) {
6959 if (input & inset_map[i].inset)
6960 val |= inset_map[i].inset_reg;
6967 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
6971 static const struct {
6974 } inset_mask_map[] = {
6975 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
6976 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
6977 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
6978 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
6981 if (!inset || !mask || !nb_elem)
6984 if (!inset && nb_elem >= I40E_INSET_MASK_NUM_REG) {
6985 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++)
6987 return I40E_INSET_MASK_NUM_REG;
6990 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
6993 if (inset & inset_mask_map[i].inset) {
6994 mask[idx] = inset_mask_map[i].mask;
7003 i40e_get_reg_inset(struct i40e_hw *hw, enum rte_filter_type filter,
7004 enum i40e_filter_pctype pctype)
7008 if (filter == RTE_ETH_FILTER_HASH) {
7009 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
7010 reg <<= I40E_32_BIT_WIDTH;
7011 reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
7012 } else if (filter == RTE_ETH_FILTER_FDIR) {
7013 reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
7014 reg <<= I40E_32_BIT_WIDTH;
7015 reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
7022 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7024 uint32_t reg = i40e_read_rx_ctl(hw, addr);
7026 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7028 i40e_write_rx_ctl(hw, addr, val);
7029 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7030 (uint32_t)i40e_read_rx_ctl(hw, addr));
7034 i40e_set_hash_inset_mask(struct i40e_hw *hw,
7035 enum i40e_filter_pctype pctype,
7036 enum rte_filter_input_set_op op,
7043 if (!mask_reg || num > RTE_ETH_INPUT_SET_SELECT)
7046 if (op == RTE_ETH_INPUT_SET_SELECT) {
7047 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
7048 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7052 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7055 } else if (op == RTE_ETH_INPUT_SET_ADD) {
7056 uint8_t j, count = 0;
7058 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
7059 reg = i40e_read_rx_ctl(hw,
7060 I40E_GLQF_HASH_MSK(i, pctype));
7061 if (reg & I40E_GLQF_HASH_MSK_MASK_MASK)
7064 if (count + num > I40E_INSET_MASK_NUM_REG)
7067 for (i = count, j = 0; i < I40E_INSET_MASK_NUM_REG; i++, j++)
7068 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7076 i40e_set_fd_inset_mask(struct i40e_hw *hw,
7077 enum i40e_filter_pctype pctype,
7078 enum rte_filter_input_set_op op,
7085 if (!mask_reg || num > RTE_ETH_INPUT_SET_SELECT)
7088 if (op == RTE_ETH_INPUT_SET_SELECT) {
7089 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
7090 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7094 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7097 } else if (op == RTE_ETH_INPUT_SET_ADD) {
7098 uint8_t j, count = 0;
7100 for (i = 0; i < I40E_INSET_MASK_NUM_REG; i++) {
7101 reg = i40e_read_rx_ctl(hw,
7102 I40E_GLQF_FD_MSK(i, pctype));
7103 if (reg & I40E_GLQF_FD_MSK_MASK_MASK)
7106 if (count + num > I40E_INSET_MASK_NUM_REG)
7109 for (i = count, j = 0; i < I40E_INSET_MASK_NUM_REG; i++, j++)
7110 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7118 i40e_filter_inset_select(struct i40e_hw *hw,
7119 struct rte_eth_input_set_conf *conf,
7120 enum rte_filter_type filter)
7122 enum i40e_filter_pctype pctype;
7123 uint64_t inset_reg = 0, input_set;
7124 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG];
7129 PMD_DRV_LOG(ERR, "Invalid pointer");
7133 pctype = i40e_flowtype_to_pctype(conf->flow_type);
7134 if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
7135 PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
7139 if (filter != RTE_ETH_FILTER_HASH && filter != RTE_ETH_FILTER_FDIR) {
7140 PMD_DRV_LOG(ERR, "Not supported filter type (%u)", filter);
7144 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7147 PMD_DRV_LOG(ERR, "Failed to parse input set");
7150 if (i40e_validate_input_set(pctype, filter, input_set) != 0) {
7151 PMD_DRV_LOG(ERR, "Invalid input set");
7155 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
7156 inset_reg |= i40e_get_reg_inset(hw, filter, pctype);
7157 } else if (conf->op != RTE_ETH_INPUT_SET_SELECT) {
7158 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7161 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7162 I40E_INSET_MASK_NUM_REG);
7163 inset_reg |= i40e_translate_input_set_reg(input_set);
7165 if (filter == RTE_ETH_FILTER_HASH) {
7166 ret = i40e_set_hash_inset_mask(hw, pctype, conf->op, mask_reg,
7171 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7172 (uint32_t)(inset_reg & UINT32_MAX));
7173 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7174 (uint32_t)((inset_reg >>
7175 I40E_32_BIT_WIDTH) & UINT32_MAX));
7176 } else if (filter == RTE_ETH_FILTER_FDIR) {
7177 ret = i40e_set_fd_inset_mask(hw, pctype, conf->op, mask_reg,
7182 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7183 (uint32_t)(inset_reg & UINT32_MAX));
7184 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7185 (uint32_t)((inset_reg >>
7186 I40E_32_BIT_WIDTH) & UINT32_MAX));
7188 PMD_DRV_LOG(ERR, "Not supported filter type (%u)", filter);
7191 I40E_WRITE_FLUSH(hw);
7197 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7202 PMD_DRV_LOG(ERR, "Invalid pointer");
7206 switch (info->info_type) {
7207 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7208 i40e_get_symmetric_hash_enable_per_port(hw,
7209 &(info->info.enable));
7211 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7212 ret = i40e_get_hash_filter_global_config(hw,
7213 &(info->info.global_conf));
7216 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7226 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7231 PMD_DRV_LOG(ERR, "Invalid pointer");
7235 switch (info->info_type) {
7236 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7237 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7239 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7240 ret = i40e_set_hash_filter_global_config(hw,
7241 &(info->info.global_conf));
7243 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7244 ret = i40e_filter_inset_select(hw,
7245 &(info->info.input_set_conf),
7246 RTE_ETH_FILTER_HASH);
7250 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7259 /* Operations for hash function */
7261 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7262 enum rte_filter_op filter_op,
7265 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7268 switch (filter_op) {
7269 case RTE_ETH_FILTER_NOP:
7271 case RTE_ETH_FILTER_GET:
7272 ret = i40e_hash_filter_get(hw,
7273 (struct rte_eth_hash_filter_info *)arg);
7275 case RTE_ETH_FILTER_SET:
7276 ret = i40e_hash_filter_set(hw,
7277 (struct rte_eth_hash_filter_info *)arg);
7280 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
7290 * Configure ethertype filter, which can director packet by filtering
7291 * with mac address and ether_type or only ether_type
7294 i40e_ethertype_filter_set(struct i40e_pf *pf,
7295 struct rte_eth_ethertype_filter *filter,
7298 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7299 struct i40e_control_filter_stats stats;
7303 if (filter->queue >= pf->dev_data->nb_rx_queues) {
7304 PMD_DRV_LOG(ERR, "Invalid queue ID");
7307 if (filter->ether_type == ETHER_TYPE_IPv4 ||
7308 filter->ether_type == ETHER_TYPE_IPv6) {
7309 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
7310 " control packet filter.", filter->ether_type);
7313 if (filter->ether_type == ETHER_TYPE_VLAN)
7314 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
7317 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
7318 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
7319 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
7320 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
7321 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
7323 memset(&stats, 0, sizeof(stats));
7324 ret = i40e_aq_add_rem_control_packet_filter(hw,
7325 filter->mac_addr.addr_bytes,
7326 filter->ether_type, flags,
7328 filter->queue, add, &stats, NULL);
7330 PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
7331 " mac_etype_used = %u, etype_used = %u,"
7332 " mac_etype_free = %u, etype_free = %u\n",
7333 ret, stats.mac_etype_used, stats.etype_used,
7334 stats.mac_etype_free, stats.etype_free);
7341 * Handle operations for ethertype filter.
7344 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
7345 enum rte_filter_op filter_op,
7348 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7351 if (filter_op == RTE_ETH_FILTER_NOP)
7355 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
7360 switch (filter_op) {
7361 case RTE_ETH_FILTER_ADD:
7362 ret = i40e_ethertype_filter_set(pf,
7363 (struct rte_eth_ethertype_filter *)arg,
7366 case RTE_ETH_FILTER_DELETE:
7367 ret = i40e_ethertype_filter_set(pf,
7368 (struct rte_eth_ethertype_filter *)arg,
7372 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
7380 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
7381 enum rte_filter_type filter_type,
7382 enum rte_filter_op filter_op,
7390 switch (filter_type) {
7391 case RTE_ETH_FILTER_NONE:
7392 /* For global configuration */
7393 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
7395 case RTE_ETH_FILTER_HASH:
7396 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
7398 case RTE_ETH_FILTER_MACVLAN:
7399 ret = i40e_mac_filter_handle(dev, filter_op, arg);
7401 case RTE_ETH_FILTER_ETHERTYPE:
7402 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
7404 case RTE_ETH_FILTER_TUNNEL:
7405 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
7407 case RTE_ETH_FILTER_FDIR:
7408 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
7411 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7421 * Check and enable Extended Tag.
7422 * Enabling Extended Tag is important for 40G performance.
7425 i40e_enable_extended_tag(struct rte_eth_dev *dev)
7430 ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7433 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7437 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
7438 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
7443 ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7446 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7450 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
7451 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
7454 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
7455 ret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf),
7458 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
7465 * As some registers wouldn't be reset unless a global hardware reset,
7466 * hardware initialization is needed to put those registers into an
7467 * expected initial state.
7470 i40e_hw_init(struct rte_eth_dev *dev)
7472 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7474 i40e_enable_extended_tag(dev);
7476 /* clear the PF Queue Filter control register */
7477 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
7479 /* Disable symmetric hash per port */
7480 i40e_set_symmetric_hash_enable_per_port(hw, 0);
7483 enum i40e_filter_pctype
7484 i40e_flowtype_to_pctype(uint16_t flow_type)
7486 static const enum i40e_filter_pctype pctype_table[] = {
7487 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
7488 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
7489 I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
7490 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
7491 I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
7492 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
7493 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
7494 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
7495 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
7496 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
7497 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
7498 I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
7499 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
7500 I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
7501 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
7502 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
7503 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
7504 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
7505 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
7508 return pctype_table[flow_type];
7512 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
7514 static const uint16_t flowtype_table[] = {
7515 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
7516 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7517 RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
7518 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7519 RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
7520 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7521 RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
7522 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7523 RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
7524 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
7525 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7526 RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
7527 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7528 RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
7529 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7530 RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
7531 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7532 RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
7533 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
7536 return flowtype_table[pctype];
7540 * On X710, performance number is far from the expectation on recent firmware
7541 * versions; on XL710, performance number is also far from the expectation on
7542 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
7543 * mode is enabled and port MAC address is equal to the packet destination MAC
7544 * address. The fix for this issue may not be integrated in the following
7545 * firmware version. So the workaround in software driver is needed. It needs
7546 * to modify the initial values of 3 internal only registers for both X710 and
7547 * XL710. Note that the values for X710 or XL710 could be different, and the
7548 * workaround can be removed when it is fixed in firmware in the future.
7551 /* For both X710 and XL710 */
7552 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
7553 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
7555 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
7556 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
7559 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
7561 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
7562 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
7565 i40e_configure_registers(struct i40e_hw *hw)
7571 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
7572 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
7573 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
7579 for (i = 0; i < RTE_DIM(reg_table); i++) {
7580 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
7581 if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
7583 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
7586 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
7589 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
7592 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
7596 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
7597 reg_table[i].addr, reg);
7598 if (reg == reg_table[i].val)
7601 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
7602 reg_table[i].val, NULL);
7604 PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
7605 "address of 0x%"PRIx32, reg_table[i].val,
7609 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
7610 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
7614 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
7615 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
7616 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
7617 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
7619 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
7624 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
7625 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
7629 /* Configure for double VLAN RX stripping */
7630 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
7631 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
7632 reg |= I40E_VSI_TSR_QINQ_CONFIG;
7633 ret = i40e_aq_debug_write_register(hw,
7634 I40E_VSI_TSR(vsi->vsi_id),
7637 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
7639 return I40E_ERR_CONFIG;
7643 /* Configure for double VLAN TX insertion */
7644 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
7645 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
7646 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
7647 ret = i40e_aq_debug_write_register(hw,
7648 I40E_VSI_L2TAGSTXVALID(
7649 vsi->vsi_id), reg, NULL);
7651 PMD_DRV_LOG(ERR, "Failed to update "
7652 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
7653 return I40E_ERR_CONFIG;
7661 * i40e_aq_add_mirror_rule
7662 * @hw: pointer to the hardware structure
7663 * @seid: VEB seid to add mirror rule to
7664 * @dst_id: destination vsi seid
7665 * @entries: Buffer which contains the entities to be mirrored
7666 * @count: number of entities contained in the buffer
7667 * @rule_id:the rule_id of the rule to be added
7669 * Add a mirror rule for a given veb.
7672 static enum i40e_status_code
7673 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
7674 uint16_t seid, uint16_t dst_id,
7675 uint16_t rule_type, uint16_t *entries,
7676 uint16_t count, uint16_t *rule_id)
7678 struct i40e_aq_desc desc;
7679 struct i40e_aqc_add_delete_mirror_rule cmd;
7680 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
7681 (struct i40e_aqc_add_delete_mirror_rule_completion *)
7684 enum i40e_status_code status;
7686 i40e_fill_default_direct_cmd_desc(&desc,
7687 i40e_aqc_opc_add_mirror_rule);
7688 memset(&cmd, 0, sizeof(cmd));
7690 buff_len = sizeof(uint16_t) * count;
7691 desc.datalen = rte_cpu_to_le_16(buff_len);
7693 desc.flags |= rte_cpu_to_le_16(
7694 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
7695 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7696 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7697 cmd.num_entries = rte_cpu_to_le_16(count);
7698 cmd.seid = rte_cpu_to_le_16(seid);
7699 cmd.destination = rte_cpu_to_le_16(dst_id);
7701 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7702 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
7703 PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
7705 " mirror_rules_used = %u, mirror_rules_free = %u,",
7706 hw->aq.asq_last_status, resp->rule_id,
7707 resp->mirror_rules_used, resp->mirror_rules_free);
7708 *rule_id = rte_le_to_cpu_16(resp->rule_id);
7714 * i40e_aq_del_mirror_rule
7715 * @hw: pointer to the hardware structure
7716 * @seid: VEB seid to add mirror rule to
7717 * @entries: Buffer which contains the entities to be mirrored
7718 * @count: number of entities contained in the buffer
7719 * @rule_id:the rule_id of the rule to be delete
7721 * Delete a mirror rule for a given veb.
7724 static enum i40e_status_code
7725 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
7726 uint16_t seid, uint16_t rule_type, uint16_t *entries,
7727 uint16_t count, uint16_t rule_id)
7729 struct i40e_aq_desc desc;
7730 struct i40e_aqc_add_delete_mirror_rule cmd;
7731 uint16_t buff_len = 0;
7732 enum i40e_status_code status;
7735 i40e_fill_default_direct_cmd_desc(&desc,
7736 i40e_aqc_opc_delete_mirror_rule);
7737 memset(&cmd, 0, sizeof(cmd));
7738 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
7739 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
7741 cmd.num_entries = count;
7742 buff_len = sizeof(uint16_t) * count;
7743 desc.datalen = rte_cpu_to_le_16(buff_len);
7744 buff = (void *)entries;
7746 /* rule id is filled in destination field for deleting mirror rule */
7747 cmd.destination = rte_cpu_to_le_16(rule_id);
7749 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
7750 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
7751 cmd.seid = rte_cpu_to_le_16(seid);
7753 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
7754 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
7760 * i40e_mirror_rule_set
7761 * @dev: pointer to the hardware structure
7762 * @mirror_conf: mirror rule info
7763 * @sw_id: mirror rule's sw_id
7764 * @on: enable/disable
7766 * set a mirror rule.
7770 i40e_mirror_rule_set(struct rte_eth_dev *dev,
7771 struct rte_eth_mirror_conf *mirror_conf,
7772 uint8_t sw_id, uint8_t on)
7774 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7775 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7776 struct i40e_mirror_rule *it, *mirr_rule = NULL;
7777 struct i40e_mirror_rule *parent = NULL;
7778 uint16_t seid, dst_seid, rule_id;
7782 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
7784 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
7785 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
7786 " without veb or vfs.");
7789 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
7790 PMD_DRV_LOG(ERR, "mirror table is full.");
7793 if (mirror_conf->dst_pool > pf->vf_num) {
7794 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
7795 mirror_conf->dst_pool);
7799 seid = pf->main_vsi->veb->seid;
7801 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
7802 if (sw_id <= it->index) {
7808 if (mirr_rule && sw_id == mirr_rule->index) {
7810 PMD_DRV_LOG(ERR, "mirror rule exists.");
7813 ret = i40e_aq_del_mirror_rule(hw, seid,
7814 mirr_rule->rule_type,
7816 mirr_rule->num_entries, mirr_rule->id);
7818 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
7819 " ret = %d, aq_err = %d.",
7820 ret, hw->aq.asq_last_status);
7823 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
7824 rte_free(mirr_rule);
7825 pf->nb_mirror_rule--;
7829 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
7833 mirr_rule = rte_zmalloc("i40e_mirror_rule",
7834 sizeof(struct i40e_mirror_rule) , 0);
7836 PMD_DRV_LOG(ERR, "failed to allocate memory");
7837 return I40E_ERR_NO_MEMORY;
7839 switch (mirror_conf->rule_type) {
7840 case ETH_MIRROR_VLAN:
7841 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
7842 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
7843 mirr_rule->entries[j] =
7844 mirror_conf->vlan.vlan_id[i];
7849 PMD_DRV_LOG(ERR, "vlan is not specified.");
7850 rte_free(mirr_rule);
7853 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
7855 case ETH_MIRROR_VIRTUAL_POOL_UP:
7856 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
7857 /* check if the specified pool bit is out of range */
7858 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
7859 PMD_DRV_LOG(ERR, "pool mask is out of range.");
7860 rte_free(mirr_rule);
7863 for (i = 0, j = 0; i < pf->vf_num; i++) {
7864 if (mirror_conf->pool_mask & (1ULL << i)) {
7865 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
7869 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
7870 /* add pf vsi to entries */
7871 mirr_rule->entries[j] = pf->main_vsi_seid;
7875 PMD_DRV_LOG(ERR, "pool is not specified.");
7876 rte_free(mirr_rule);
7879 /* egress and ingress in aq commands means from switch but not port */
7880 mirr_rule->rule_type =
7881 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
7882 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
7883 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
7885 case ETH_MIRROR_UPLINK_PORT:
7886 /* egress and ingress in aq commands means from switch but not port*/
7887 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
7889 case ETH_MIRROR_DOWNLINK_PORT:
7890 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
7893 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
7894 mirror_conf->rule_type);
7895 rte_free(mirr_rule);
7899 /* If the dst_pool is equal to vf_num, consider it as PF */
7900 if (mirror_conf->dst_pool == pf->vf_num)
7901 dst_seid = pf->main_vsi_seid;
7903 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
7905 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
7906 mirr_rule->rule_type, mirr_rule->entries,
7909 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
7910 " ret = %d, aq_err = %d.",
7911 ret, hw->aq.asq_last_status);
7912 rte_free(mirr_rule);
7916 mirr_rule->index = sw_id;
7917 mirr_rule->num_entries = j;
7918 mirr_rule->id = rule_id;
7919 mirr_rule->dst_vsi_seid = dst_seid;
7922 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
7924 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
7926 pf->nb_mirror_rule++;
7931 * i40e_mirror_rule_reset
7932 * @dev: pointer to the device
7933 * @sw_id: mirror rule's sw_id
7935 * reset a mirror rule.
7939 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
7941 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7942 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7943 struct i40e_mirror_rule *it, *mirr_rule = NULL;
7947 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
7949 seid = pf->main_vsi->veb->seid;
7951 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
7952 if (sw_id == it->index) {
7958 ret = i40e_aq_del_mirror_rule(hw, seid,
7959 mirr_rule->rule_type,
7961 mirr_rule->num_entries, mirr_rule->id);
7963 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
7964 " status = %d, aq_err = %d.",
7965 ret, hw->aq.asq_last_status);
7968 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
7969 rte_free(mirr_rule);
7970 pf->nb_mirror_rule--;
7972 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
7979 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
7981 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7982 uint64_t systim_cycles;
7984 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
7985 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
7988 return systim_cycles;
7992 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
7994 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7997 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
7998 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
8005 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
8007 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8010 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
8011 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
8018 i40e_start_timecounters(struct rte_eth_dev *dev)
8020 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8021 struct i40e_adapter *adapter =
8022 (struct i40e_adapter *)dev->data->dev_private;
8023 struct rte_eth_link link;
8024 uint32_t tsync_inc_l;
8025 uint32_t tsync_inc_h;
8027 /* Get current link speed. */
8028 memset(&link, 0, sizeof(link));
8029 i40e_dev_link_update(dev, 1);
8030 rte_i40e_dev_atomic_read_link_status(dev, &link);
8032 switch (link.link_speed) {
8033 case ETH_LINK_SPEED_40G:
8034 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
8035 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
8037 case ETH_LINK_SPEED_10G:
8038 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
8039 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
8041 case ETH_LINK_SPEED_1000:
8042 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
8043 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
8050 /* Set the timesync increment value. */
8051 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
8052 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
8054 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
8055 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8056 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8058 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8059 adapter->systime_tc.cc_shift = 0;
8060 adapter->systime_tc.nsec_mask = 0;
8062 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8063 adapter->rx_tstamp_tc.cc_shift = 0;
8064 adapter->rx_tstamp_tc.nsec_mask = 0;
8066 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8067 adapter->tx_tstamp_tc.cc_shift = 0;
8068 adapter->tx_tstamp_tc.nsec_mask = 0;
8072 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
8074 struct i40e_adapter *adapter =
8075 (struct i40e_adapter *)dev->data->dev_private;
8077 adapter->systime_tc.nsec += delta;
8078 adapter->rx_tstamp_tc.nsec += delta;
8079 adapter->tx_tstamp_tc.nsec += delta;
8085 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
8088 struct i40e_adapter *adapter =
8089 (struct i40e_adapter *)dev->data->dev_private;
8091 ns = rte_timespec_to_ns(ts);
8093 /* Set the timecounters to a new value. */
8094 adapter->systime_tc.nsec = ns;
8095 adapter->rx_tstamp_tc.nsec = ns;
8096 adapter->tx_tstamp_tc.nsec = ns;
8102 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
8104 uint64_t ns, systime_cycles;
8105 struct i40e_adapter *adapter =
8106 (struct i40e_adapter *)dev->data->dev_private;
8108 systime_cycles = i40e_read_systime_cyclecounter(dev);
8109 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
8110 *ts = rte_ns_to_timespec(ns);
8116 i40e_timesync_enable(struct rte_eth_dev *dev)
8118 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8119 uint32_t tsync_ctl_l;
8120 uint32_t tsync_ctl_h;
8122 /* Stop the timesync system time. */
8123 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8124 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8125 /* Reset the timesync system time value. */
8126 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
8127 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
8129 i40e_start_timecounters(dev);
8131 /* Clear timesync registers. */
8132 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8133 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
8134 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
8135 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
8136 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
8137 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
8139 /* Enable timestamping of PTP packets. */
8140 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8141 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
8143 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8144 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
8145 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
8147 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8148 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8154 i40e_timesync_disable(struct rte_eth_dev *dev)
8156 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8157 uint32_t tsync_ctl_l;
8158 uint32_t tsync_ctl_h;
8160 /* Disable timestamping of transmitted PTP packets. */
8161 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8162 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
8164 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8165 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
8167 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8168 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8170 /* Reset the timesync increment value. */
8171 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8172 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8178 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
8179 struct timespec *timestamp, uint32_t flags)
8181 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8182 struct i40e_adapter *adapter =
8183 (struct i40e_adapter *)dev->data->dev_private;
8185 uint32_t sync_status;
8186 uint32_t index = flags & 0x03;
8187 uint64_t rx_tstamp_cycles;
8190 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
8191 if ((sync_status & (1 << index)) == 0)
8194 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
8195 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
8196 *timestamp = rte_ns_to_timespec(ns);
8202 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
8203 struct timespec *timestamp)
8205 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8206 struct i40e_adapter *adapter =
8207 (struct i40e_adapter *)dev->data->dev_private;
8209 uint32_t sync_status;
8210 uint64_t tx_tstamp_cycles;
8213 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8214 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
8217 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
8218 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
8219 *timestamp = rte_ns_to_timespec(ns);
8225 * i40e_parse_dcb_configure - parse dcb configure from user
8226 * @dev: the device being configured
8227 * @dcb_cfg: pointer of the result of parse
8228 * @*tc_map: bit map of enabled traffic classes
8230 * Returns 0 on success, negative value on failure
8233 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
8234 struct i40e_dcbx_config *dcb_cfg,
8237 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
8238 uint8_t i, tc_bw, bw_lf;
8240 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
8242 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
8243 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
8244 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
8248 /* assume each tc has the same bw */
8249 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
8250 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8251 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
8252 /* to ensure the sum of tcbw is equal to 100 */
8253 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
8254 for (i = 0; i < bw_lf; i++)
8255 dcb_cfg->etscfg.tcbwtable[i]++;
8257 /* assume each tc has the same Transmission Selection Algorithm */
8258 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8259 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
8261 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8262 dcb_cfg->etscfg.prioritytable[i] =
8263 dcb_rx_conf->dcb_tc[i];
8265 /* FW needs one App to configure HW */
8266 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
8267 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
8268 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
8269 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
8271 if (dcb_rx_conf->nb_tcs == 0)
8272 *tc_map = 1; /* tc0 only */
8274 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
8276 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
8277 dcb_cfg->pfc.willing = 0;
8278 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
8279 dcb_cfg->pfc.pfcenable = *tc_map;
8285 static enum i40e_status_code
8286 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
8287 struct i40e_aqc_vsi_properties_data *info,
8288 uint8_t enabled_tcmap)
8290 enum i40e_status_code ret;
8291 int i, total_tc = 0;
8292 uint16_t qpnum_per_tc, bsf, qp_idx;
8293 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
8294 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
8295 uint16_t used_queues;
8297 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
8298 if (ret != I40E_SUCCESS)
8301 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8302 if (enabled_tcmap & (1 << i))
8307 vsi->enabled_tc = enabled_tcmap;
8309 /* different VSI has different queues assigned */
8310 if (vsi->type == I40E_VSI_MAIN)
8311 used_queues = dev_data->nb_rx_queues -
8312 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8313 else if (vsi->type == I40E_VSI_VMDQ2)
8314 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8316 PMD_INIT_LOG(ERR, "unsupported VSI type.");
8317 return I40E_ERR_NO_AVAILABLE_VSI;
8320 qpnum_per_tc = used_queues / total_tc;
8321 /* Number of queues per enabled TC */
8322 if (qpnum_per_tc == 0) {
8323 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
8324 return I40E_ERR_INVALID_QP_ID;
8326 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
8328 bsf = rte_bsf32(qpnum_per_tc);
8331 * Configure TC and queue mapping parameters, for enabled TC,
8332 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
8333 * default queue will serve it.
8336 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8337 if (vsi->enabled_tc & (1 << i)) {
8338 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
8339 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
8340 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
8341 qp_idx += qpnum_per_tc;
8343 info->tc_mapping[i] = 0;
8346 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
8347 if (vsi->type == I40E_VSI_SRIOV) {
8348 info->mapping_flags |=
8349 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
8350 for (i = 0; i < vsi->nb_qps; i++)
8351 info->queue_mapping[i] =
8352 rte_cpu_to_le_16(vsi->base_queue + i);
8354 info->mapping_flags |=
8355 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
8356 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
8358 info->valid_sections |=
8359 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
8361 return I40E_SUCCESS;
8365 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
8366 * @veb: VEB to be configured
8367 * @tc_map: enabled TC bitmap
8369 * Returns 0 on success, negative value on failure
8371 static enum i40e_status_code
8372 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
8374 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
8375 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
8376 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
8377 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
8378 enum i40e_status_code ret = I40E_SUCCESS;
8382 /* Check if enabled_tc is same as existing or new TCs */
8383 if (veb->enabled_tc == tc_map)
8386 /* configure tc bandwidth */
8387 memset(&veb_bw, 0, sizeof(veb_bw));
8388 veb_bw.tc_valid_bits = tc_map;
8389 /* Enable ETS TCs with equal BW Share for now across all VSIs */
8390 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8391 if (tc_map & BIT_ULL(i))
8392 veb_bw.tc_bw_share_credits[i] = 1;
8394 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
8397 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
8398 " per TC failed = %d",
8399 hw->aq.asq_last_status);
8403 memset(&ets_query, 0, sizeof(ets_query));
8404 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
8406 if (ret != I40E_SUCCESS) {
8407 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
8408 " configuration %u", hw->aq.asq_last_status);
8411 memset(&bw_query, 0, sizeof(bw_query));
8412 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
8414 if (ret != I40E_SUCCESS) {
8415 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
8416 " configuration %u", hw->aq.asq_last_status);
8420 /* store and print out BW info */
8421 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
8422 veb->bw_info.bw_max = ets_query.tc_bw_max;
8423 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
8424 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
8425 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
8426 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
8428 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8429 veb->bw_info.bw_ets_share_credits[i] =
8430 bw_query.tc_bw_share_credits[i];
8431 veb->bw_info.bw_ets_credits[i] =
8432 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
8433 /* 4 bits per TC, 4th bit is reserved */
8434 veb->bw_info.bw_ets_max[i] =
8435 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
8436 RTE_LEN2MASK(3, uint8_t));
8437 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
8438 veb->bw_info.bw_ets_share_credits[i]);
8439 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
8440 veb->bw_info.bw_ets_credits[i]);
8441 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
8442 veb->bw_info.bw_ets_max[i]);
8445 veb->enabled_tc = tc_map;
8452 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
8453 * @vsi: VSI to be configured
8454 * @tc_map: enabled TC bitmap
8456 * Returns 0 on success, negative value on failure
8458 static enum i40e_status_code
8459 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
8461 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
8462 struct i40e_vsi_context ctxt;
8463 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
8464 enum i40e_status_code ret = I40E_SUCCESS;
8467 /* Check if enabled_tc is same as existing or new TCs */
8468 if (vsi->enabled_tc == tc_map)
8471 /* configure tc bandwidth */
8472 memset(&bw_data, 0, sizeof(bw_data));
8473 bw_data.tc_valid_bits = tc_map;
8474 /* Enable ETS TCs with equal BW Share for now across all VSIs */
8475 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8476 if (tc_map & BIT_ULL(i))
8477 bw_data.tc_bw_credits[i] = 1;
8479 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
8481 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
8482 " per TC failed = %d",
8483 hw->aq.asq_last_status);
8486 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
8487 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
8489 /* Update Queue Pairs Mapping for currently enabled UPs */
8490 ctxt.seid = vsi->seid;
8491 ctxt.pf_num = hw->pf_id;
8493 ctxt.uplink_seid = vsi->uplink_seid;
8494 ctxt.info = vsi->info;
8496 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
8500 /* Update the VSI after updating the VSI queue-mapping information */
8501 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8503 PMD_INIT_LOG(ERR, "Failed to configure "
8504 "TC queue mapping = %d",
8505 hw->aq.asq_last_status);
8508 /* update the local VSI info with updated queue map */
8509 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
8510 sizeof(vsi->info.tc_mapping));
8511 (void)rte_memcpy(&vsi->info.queue_mapping,
8512 &ctxt.info.queue_mapping,
8513 sizeof(vsi->info.queue_mapping));
8514 vsi->info.mapping_flags = ctxt.info.mapping_flags;
8515 vsi->info.valid_sections = 0;
8517 /* query and update current VSI BW information */
8518 ret = i40e_vsi_get_bw_config(vsi);
8521 "Failed updating vsi bw info, err %s aq_err %s",
8522 i40e_stat_str(hw, ret),
8523 i40e_aq_str(hw, hw->aq.asq_last_status));
8527 vsi->enabled_tc = tc_map;
8534 * i40e_dcb_hw_configure - program the dcb setting to hw
8535 * @pf: pf the configuration is taken on
8536 * @new_cfg: new configuration
8537 * @tc_map: enabled TC bitmap
8539 * Returns 0 on success, negative value on failure
8541 static enum i40e_status_code
8542 i40e_dcb_hw_configure(struct i40e_pf *pf,
8543 struct i40e_dcbx_config *new_cfg,
8546 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8547 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
8548 struct i40e_vsi *main_vsi = pf->main_vsi;
8549 struct i40e_vsi_list *vsi_list;
8550 enum i40e_status_code ret;
8554 /* Use the FW API if FW > v4.4*/
8555 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
8556 (hw->aq.fw_maj_ver >= 5))) {
8557 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
8558 " to configure DCB");
8559 return I40E_ERR_FIRMWARE_API_VERSION;
8562 /* Check if need reconfiguration */
8563 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
8564 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
8565 return I40E_SUCCESS;
8568 /* Copy the new config to the current config */
8569 *old_cfg = *new_cfg;
8570 old_cfg->etsrec = old_cfg->etscfg;
8571 ret = i40e_set_dcb_config(hw);
8574 "Set DCB Config failed, err %s aq_err %s\n",
8575 i40e_stat_str(hw, ret),
8576 i40e_aq_str(hw, hw->aq.asq_last_status));
8579 /* set receive Arbiter to RR mode and ETS scheme by default */
8580 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
8581 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
8582 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
8583 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
8584 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
8585 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
8586 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
8587 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
8588 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
8589 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
8590 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
8591 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
8592 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
8594 /* get local mib to check whether it is configured correctly */
8596 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
8597 /* Get Local DCB Config */
8598 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
8599 &hw->local_dcbx_config);
8601 /* if Veb is created, need to update TC of it at first */
8602 if (main_vsi->veb) {
8603 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
8605 PMD_INIT_LOG(WARNING,
8606 "Failed configuring TC for VEB seid=%d\n",
8607 main_vsi->veb->seid);
8609 /* Update each VSI */
8610 i40e_vsi_config_tc(main_vsi, tc_map);
8611 if (main_vsi->veb) {
8612 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
8613 /* Beside main VSI and VMDQ VSIs, only enable default
8616 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
8617 ret = i40e_vsi_config_tc(vsi_list->vsi,
8620 ret = i40e_vsi_config_tc(vsi_list->vsi,
8621 I40E_DEFAULT_TCMAP);
8623 PMD_INIT_LOG(WARNING,
8624 "Failed configuring TC for VSI seid=%d\n",
8625 vsi_list->vsi->seid);
8629 return I40E_SUCCESS;
8633 * i40e_dcb_init_configure - initial dcb config
8634 * @dev: device being configured
8635 * @sw_dcb: indicate whether dcb is sw configured or hw offload
8637 * Returns 0 on success, negative value on failure
8640 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
8642 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8643 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8646 if ((pf->flags & I40E_FLAG_DCB) == 0) {
8647 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8651 /* DCB initialization:
8652 * Update DCB configuration from the Firmware and configure
8653 * LLDP MIB change event.
8655 if (sw_dcb == TRUE) {
8656 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
8657 if (ret != I40E_SUCCESS)
8658 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
8660 ret = i40e_init_dcb(hw);
8661 /* if sw_dcb, lldp agent is stopped, the return from
8662 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
8665 if (ret != I40E_SUCCESS &&
8666 hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
8667 memset(&hw->local_dcbx_config, 0,
8668 sizeof(struct i40e_dcbx_config));
8669 /* set dcb default configuration */
8670 hw->local_dcbx_config.etscfg.willing = 0;
8671 hw->local_dcbx_config.etscfg.maxtcs = 0;
8672 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
8673 hw->local_dcbx_config.etscfg.tsatable[0] =
8675 hw->local_dcbx_config.etsrec =
8676 hw->local_dcbx_config.etscfg;
8677 hw->local_dcbx_config.pfc.willing = 0;
8678 hw->local_dcbx_config.pfc.pfccap =
8679 I40E_MAX_TRAFFIC_CLASS;
8680 /* FW needs one App to configure HW */
8681 hw->local_dcbx_config.numapps = 1;
8682 hw->local_dcbx_config.app[0].selector =
8683 I40E_APP_SEL_ETHTYPE;
8684 hw->local_dcbx_config.app[0].priority = 3;
8685 hw->local_dcbx_config.app[0].protocolid =
8686 I40E_APP_PROTOID_FCOE;
8687 ret = i40e_set_dcb_config(hw);
8689 PMD_INIT_LOG(ERR, "default dcb config fails."
8690 " err = %d, aq_err = %d.", ret,
8691 hw->aq.asq_last_status);
8695 PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8696 " aq_err = %d.", ret,
8697 hw->aq.asq_last_status);
8701 ret = i40e_aq_start_lldp(hw, NULL);
8702 if (ret != I40E_SUCCESS)
8703 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
8705 ret = i40e_init_dcb(hw);
8707 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
8708 PMD_INIT_LOG(ERR, "HW doesn't support"
8713 PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
8714 " aq_err = %d.", ret,
8715 hw->aq.asq_last_status);
8723 * i40e_dcb_setup - setup dcb related config
8724 * @dev: device being configured
8726 * Returns 0 on success, negative value on failure
8729 i40e_dcb_setup(struct rte_eth_dev *dev)
8731 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8732 struct i40e_dcbx_config dcb_cfg;
8736 if ((pf->flags & I40E_FLAG_DCB) == 0) {
8737 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
8741 if (pf->vf_num != 0)
8742 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
8744 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
8746 PMD_INIT_LOG(ERR, "invalid dcb config");
8749 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
8751 PMD_INIT_LOG(ERR, "dcb sw configure fails");
8759 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
8760 struct rte_eth_dcb_info *dcb_info)
8762 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8763 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8764 struct i40e_vsi *vsi = pf->main_vsi;
8765 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
8766 uint16_t bsf, tc_mapping;
8769 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
8770 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
8772 dcb_info->nb_tcs = 1;
8773 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8774 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
8775 for (i = 0; i < dcb_info->nb_tcs; i++)
8776 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
8780 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8781 if (!(vsi->enabled_tc & (1 << i)))
8783 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
8784 /* only main vsi support multi TCs */
8785 dcb_info->tc_queue.tc_rxq[j][i].base =
8786 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
8787 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
8788 dcb_info->tc_queue.tc_txq[j][i].base =
8789 dcb_info->tc_queue.tc_rxq[j][i].base;
8790 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
8791 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
8792 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
8793 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
8794 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
8796 vsi = pf->vmdq[j].vsi;
8798 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
8803 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
8805 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
8806 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8808 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
8811 msix_intr = intr_handle->intr_vec[queue_id];
8812 if (msix_intr == I40E_MISC_VEC_ID)
8813 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
8814 I40E_PFINT_DYN_CTLN_INTENA_MASK |
8815 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
8816 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
8818 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
8821 I40E_PFINT_DYN_CTLN(msix_intr -
8823 I40E_PFINT_DYN_CTLN_INTENA_MASK |
8824 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
8825 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
8827 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
8829 I40E_WRITE_FLUSH(hw);
8830 rte_intr_enable(&dev->pci_dev->intr_handle);
8836 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
8838 struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
8839 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8842 msix_intr = intr_handle->intr_vec[queue_id];
8843 if (msix_intr == I40E_MISC_VEC_ID)
8844 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
8847 I40E_PFINT_DYN_CTLN(msix_intr -
8850 I40E_WRITE_FLUSH(hw);