4 * Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44 #include <rte_string_fns.h>
46 #include <rte_ether.h>
47 #include <rte_ethdev.h>
48 #include <rte_ethdev_pci.h>
49 #include <rte_memzone.h>
50 #include <rte_malloc.h>
51 #include <rte_memcpy.h>
52 #include <rte_alarm.h>
54 #include <rte_eth_ctrl.h>
55 #include <rte_tailq.h>
56 #include <rte_hash_crc.h>
58 #include "i40e_logs.h"
59 #include "base/i40e_prototype.h"
60 #include "base/i40e_adminq_cmd.h"
61 #include "base/i40e_type.h"
62 #include "base/i40e_register.h"
63 #include "base/i40e_dcb.h"
64 #include "i40e_ethdev.h"
65 #include "i40e_rxtx.h"
67 #include "i40e_regs.h"
68 #include "rte_pmd_i40e.h"
70 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
71 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
73 #define I40E_CLEAR_PXE_WAIT_MS 200
75 /* Maximun number of capability elements */
76 #define I40E_MAX_CAP_ELE_NUM 128
78 /* Wait count and interval */
79 #define I40E_CHK_Q_ENA_COUNT 1000
80 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
82 /* Maximun number of VSI */
83 #define I40E_MAX_NUM_VSIS (384UL)
85 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
87 /* Flow control default timer */
88 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
90 /* Flow control enable fwd bit */
91 #define I40E_PRTMAC_FWD_CTRL 0x00000001
93 /* Receive Packet Buffer size */
94 #define I40E_RXPBSIZE (968 * 1024)
97 #define I40E_KILOSHIFT 10
99 /* Flow control default high water */
100 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
102 /* Flow control default low water */
103 #define I40E_DEFAULT_LOW_WATER (0xF2000 >> I40E_KILOSHIFT)
105 /* Receive Average Packet Size in Byte*/
106 #define I40E_PACKET_AVERAGE_SIZE 128
108 /* Mask of PF interrupt causes */
109 #define I40E_PFINT_ICR0_ENA_MASK ( \
110 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
111 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
112 I40E_PFINT_ICR0_ENA_GRST_MASK | \
113 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
114 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
115 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
116 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
117 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
118 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
120 #define I40E_FLOW_TYPES ( \
121 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
122 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
123 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
124 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
125 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
126 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
127 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
128 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
129 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
130 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
131 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
133 /* Additional timesync values. */
134 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
135 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
136 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
137 #define I40E_PRTTSYN_TSYNENA 0x80000000
138 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
139 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
142 * Below are values for writing un-exposed registers suggested
145 /* Destination MAC address */
146 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
147 /* Source MAC address */
148 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
149 /* Outer (S-Tag) VLAN tag in the outer L2 header */
150 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
151 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
152 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
153 /* Single VLAN tag in the inner L2 header */
154 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
155 /* Source IPv4 address */
156 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
157 /* Destination IPv4 address */
158 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
159 /* Source IPv4 address for X722 */
160 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
161 /* Destination IPv4 address for X722 */
162 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
163 /* IPv4 Protocol for X722 */
164 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
165 /* IPv4 Time to Live for X722 */
166 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
167 /* IPv4 Type of Service (TOS) */
168 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
170 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
171 /* IPv4 Time to Live */
172 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
173 /* Source IPv6 address */
174 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
175 /* Destination IPv6 address */
176 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
177 /* IPv6 Traffic Class (TC) */
178 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
179 /* IPv6 Next Header */
180 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
182 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
184 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
185 /* Destination L4 port */
186 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
187 /* SCTP verification tag */
188 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
189 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
190 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
191 /* Source port of tunneling UDP */
192 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
193 /* Destination port of tunneling UDP */
194 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
195 /* UDP Tunneling ID, NVGRE/GRE key */
196 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
197 /* Last ether type */
198 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
199 /* Tunneling outer destination IPv4 address */
200 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
201 /* Tunneling outer destination IPv6 address */
202 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
203 /* 1st word of flex payload */
204 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
205 /* 2nd word of flex payload */
206 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
207 /* 3rd word of flex payload */
208 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
209 /* 4th word of flex payload */
210 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
211 /* 5th word of flex payload */
212 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
213 /* 6th word of flex payload */
214 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
215 /* 7th word of flex payload */
216 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
217 /* 8th word of flex payload */
218 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
219 /* all 8 words flex payload */
220 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
221 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
223 #define I40E_TRANSLATE_INSET 0
224 #define I40E_TRANSLATE_REG 1
226 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
227 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
228 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
229 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
230 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
231 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
233 /* PCI offset for querying capability */
234 #define PCI_DEV_CAP_REG 0xA4
235 /* PCI offset for enabling/disabling Extended Tag */
236 #define PCI_DEV_CTRL_REG 0xA8
237 /* Bit mask of Extended Tag capability */
238 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
239 /* Bit shift of Extended Tag enable/disable */
240 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
241 /* Bit mask of Extended Tag enable/disable */
242 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
244 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
245 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
246 static int i40e_dev_configure(struct rte_eth_dev *dev);
247 static int i40e_dev_start(struct rte_eth_dev *dev);
248 static void i40e_dev_stop(struct rte_eth_dev *dev);
249 static void i40e_dev_close(struct rte_eth_dev *dev);
250 static int i40e_dev_reset(struct rte_eth_dev *dev);
251 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
252 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
253 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
254 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
255 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
256 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
257 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
258 struct rte_eth_stats *stats);
259 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
260 struct rte_eth_xstat *xstats, unsigned n);
261 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
262 struct rte_eth_xstat_name *xstats_names,
264 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
265 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
269 static int i40e_fw_version_get(struct rte_eth_dev *dev,
270 char *fw_version, size_t fw_size);
271 static void i40e_dev_info_get(struct rte_eth_dev *dev,
272 struct rte_eth_dev_info *dev_info);
273 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
276 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
277 enum rte_vlan_type vlan_type,
279 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
280 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
283 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
284 static int i40e_dev_led_on(struct rte_eth_dev *dev);
285 static int i40e_dev_led_off(struct rte_eth_dev *dev);
286 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
287 struct rte_eth_fc_conf *fc_conf);
288 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
289 struct rte_eth_fc_conf *fc_conf);
290 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
291 struct rte_eth_pfc_conf *pfc_conf);
292 static int i40e_macaddr_add(struct rte_eth_dev *dev,
293 struct ether_addr *mac_addr,
296 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
297 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
298 struct rte_eth_rss_reta_entry64 *reta_conf,
300 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
301 struct rte_eth_rss_reta_entry64 *reta_conf,
304 static int i40e_get_cap(struct i40e_hw *hw);
305 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
306 static int i40e_pf_setup(struct i40e_pf *pf);
307 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
308 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
309 static int i40e_dcb_setup(struct rte_eth_dev *dev);
310 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
311 bool offset_loaded, uint64_t *offset, uint64_t *stat);
312 static void i40e_stat_update_48(struct i40e_hw *hw,
318 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
319 static void i40e_dev_interrupt_handler(void *param);
320 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
321 uint32_t base, uint32_t num);
322 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
323 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
325 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
327 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
328 static int i40e_veb_release(struct i40e_veb *veb);
329 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
330 struct i40e_vsi *vsi);
331 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
332 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
333 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
334 struct i40e_macvlan_filter *mv_f,
337 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
338 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
339 struct rte_eth_rss_conf *rss_conf);
340 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
341 struct rte_eth_rss_conf *rss_conf);
342 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
343 struct rte_eth_udp_tunnel *udp_tunnel);
344 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
345 struct rte_eth_udp_tunnel *udp_tunnel);
346 static void i40e_filter_input_set_init(struct i40e_pf *pf);
347 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
348 enum rte_filter_op filter_op,
350 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
351 enum rte_filter_type filter_type,
352 enum rte_filter_op filter_op,
354 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
355 struct rte_eth_dcb_info *dcb_info);
356 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
357 static void i40e_configure_registers(struct i40e_hw *hw);
358 static void i40e_hw_init(struct rte_eth_dev *dev);
359 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
360 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
366 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
367 struct rte_eth_mirror_conf *mirror_conf,
368 uint8_t sw_id, uint8_t on);
369 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
371 static int i40e_timesync_enable(struct rte_eth_dev *dev);
372 static int i40e_timesync_disable(struct rte_eth_dev *dev);
373 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
374 struct timespec *timestamp,
376 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
377 struct timespec *timestamp);
378 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
380 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
382 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
383 struct timespec *timestamp);
384 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
385 const struct timespec *timestamp);
387 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
389 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
392 static int i40e_get_regs(struct rte_eth_dev *dev,
393 struct rte_dev_reg_info *regs);
395 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
397 static int i40e_get_eeprom(struct rte_eth_dev *dev,
398 struct rte_dev_eeprom_info *eeprom);
400 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
401 struct ether_addr *mac_addr);
403 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
405 static int i40e_ethertype_filter_convert(
406 const struct rte_eth_ethertype_filter *input,
407 struct i40e_ethertype_filter *filter);
408 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
409 struct i40e_ethertype_filter *filter);
411 static int i40e_tunnel_filter_convert(
412 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
413 struct i40e_tunnel_filter *tunnel_filter);
414 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
415 struct i40e_tunnel_filter *tunnel_filter);
416 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
418 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
419 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
420 static void i40e_filter_restore(struct i40e_pf *pf);
421 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
423 int i40e_logtype_init;
424 int i40e_logtype_driver;
426 static const struct rte_pci_id pci_id_i40e_map[] = {
427 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
428 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
429 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
430 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
431 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
432 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
435 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
436 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
437 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
438 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
439 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
440 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
441 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
442 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
443 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
444 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
445 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
446 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
447 { .vendor_id = 0, /* sentinel */ },
450 static const struct eth_dev_ops i40e_eth_dev_ops = {
451 .dev_configure = i40e_dev_configure,
452 .dev_start = i40e_dev_start,
453 .dev_stop = i40e_dev_stop,
454 .dev_close = i40e_dev_close,
455 .dev_reset = i40e_dev_reset,
456 .promiscuous_enable = i40e_dev_promiscuous_enable,
457 .promiscuous_disable = i40e_dev_promiscuous_disable,
458 .allmulticast_enable = i40e_dev_allmulticast_enable,
459 .allmulticast_disable = i40e_dev_allmulticast_disable,
460 .dev_set_link_up = i40e_dev_set_link_up,
461 .dev_set_link_down = i40e_dev_set_link_down,
462 .link_update = i40e_dev_link_update,
463 .stats_get = i40e_dev_stats_get,
464 .xstats_get = i40e_dev_xstats_get,
465 .xstats_get_names = i40e_dev_xstats_get_names,
466 .stats_reset = i40e_dev_stats_reset,
467 .xstats_reset = i40e_dev_stats_reset,
468 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
469 .fw_version_get = i40e_fw_version_get,
470 .dev_infos_get = i40e_dev_info_get,
471 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
472 .vlan_filter_set = i40e_vlan_filter_set,
473 .vlan_tpid_set = i40e_vlan_tpid_set,
474 .vlan_offload_set = i40e_vlan_offload_set,
475 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
476 .vlan_pvid_set = i40e_vlan_pvid_set,
477 .rx_queue_start = i40e_dev_rx_queue_start,
478 .rx_queue_stop = i40e_dev_rx_queue_stop,
479 .tx_queue_start = i40e_dev_tx_queue_start,
480 .tx_queue_stop = i40e_dev_tx_queue_stop,
481 .rx_queue_setup = i40e_dev_rx_queue_setup,
482 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
483 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
484 .rx_queue_release = i40e_dev_rx_queue_release,
485 .rx_queue_count = i40e_dev_rx_queue_count,
486 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
487 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
488 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
489 .tx_queue_setup = i40e_dev_tx_queue_setup,
490 .tx_queue_release = i40e_dev_tx_queue_release,
491 .dev_led_on = i40e_dev_led_on,
492 .dev_led_off = i40e_dev_led_off,
493 .flow_ctrl_get = i40e_flow_ctrl_get,
494 .flow_ctrl_set = i40e_flow_ctrl_set,
495 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
496 .mac_addr_add = i40e_macaddr_add,
497 .mac_addr_remove = i40e_macaddr_remove,
498 .reta_update = i40e_dev_rss_reta_update,
499 .reta_query = i40e_dev_rss_reta_query,
500 .rss_hash_update = i40e_dev_rss_hash_update,
501 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
502 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
503 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
504 .filter_ctrl = i40e_dev_filter_ctrl,
505 .rxq_info_get = i40e_rxq_info_get,
506 .txq_info_get = i40e_txq_info_get,
507 .mirror_rule_set = i40e_mirror_rule_set,
508 .mirror_rule_reset = i40e_mirror_rule_reset,
509 .timesync_enable = i40e_timesync_enable,
510 .timesync_disable = i40e_timesync_disable,
511 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
512 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
513 .get_dcb_info = i40e_dev_get_dcb_info,
514 .timesync_adjust_time = i40e_timesync_adjust_time,
515 .timesync_read_time = i40e_timesync_read_time,
516 .timesync_write_time = i40e_timesync_write_time,
517 .get_reg = i40e_get_regs,
518 .get_eeprom_length = i40e_get_eeprom_length,
519 .get_eeprom = i40e_get_eeprom,
520 .mac_addr_set = i40e_set_default_mac_addr,
521 .mtu_set = i40e_dev_mtu_set,
522 .tm_ops_get = i40e_tm_ops_get,
525 /* store statistics names and its offset in stats structure */
526 struct rte_i40e_xstats_name_off {
527 char name[RTE_ETH_XSTATS_NAME_SIZE];
531 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
532 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
533 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
534 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
535 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
536 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
537 rx_unknown_protocol)},
538 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
539 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
540 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
541 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
544 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
545 sizeof(rte_i40e_stats_strings[0]))
547 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
548 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
549 tx_dropped_link_down)},
550 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
551 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
553 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
554 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
556 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
558 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
560 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
561 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
562 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
563 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
564 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
565 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
567 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
569 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
571 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
573 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
575 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
577 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
579 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
581 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
582 mac_short_packet_dropped)},
583 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
585 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
586 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
587 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
589 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
591 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
593 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
595 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
597 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
599 {"rx_flow_director_atr_match_packets",
600 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
601 {"rx_flow_director_sb_match_packets",
602 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
603 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
605 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
607 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
609 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
613 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
614 sizeof(rte_i40e_hw_port_strings[0]))
616 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
617 {"xon_packets", offsetof(struct i40e_hw_port_stats,
619 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
623 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
624 sizeof(rte_i40e_rxq_prio_strings[0]))
626 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
627 {"xon_packets", offsetof(struct i40e_hw_port_stats,
629 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
631 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
632 priority_xon_2_xoff)},
635 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
636 sizeof(rte_i40e_txq_prio_strings[0]))
638 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
639 struct rte_pci_device *pci_dev)
641 return rte_eth_dev_pci_generic_probe(pci_dev,
642 sizeof(struct i40e_adapter), eth_i40e_dev_init);
645 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
647 return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
650 static struct rte_pci_driver rte_i40e_pmd = {
651 .id_table = pci_id_i40e_map,
652 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
653 RTE_PCI_DRV_IOVA_AS_VA,
654 .probe = eth_i40e_pci_probe,
655 .remove = eth_i40e_pci_remove,
659 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
660 struct rte_eth_link *link)
662 struct rte_eth_link *dst = link;
663 struct rte_eth_link *src = &(dev->data->dev_link);
665 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
666 *(uint64_t *)src) == 0)
673 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
674 struct rte_eth_link *link)
676 struct rte_eth_link *dst = &(dev->data->dev_link);
677 struct rte_eth_link *src = link;
679 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
680 *(uint64_t *)src) == 0)
686 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
687 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
688 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
690 #ifndef I40E_GLQF_ORT
691 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
693 #ifndef I40E_GLQF_PIT
694 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
696 #ifndef I40E_GLQF_L3_MAP
697 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
700 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
703 * Force global configuration for flexible payload
704 * to the first 16 bytes of the corresponding L2/L3/L4 paylod.
705 * This should be removed from code once proper
706 * configuration API is added to avoid configuration conflicts
707 * between ports of the same device.
709 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
710 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
711 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
714 * Initialize registers for parsing packet type of QinQ
715 * This should be removed from code once proper
716 * configuration API is added to avoid configuration conflicts
717 * between ports of the same device.
719 I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
720 I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
723 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
726 * Add a ethertype filter to drop all flow control frames transmitted
730 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
732 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
733 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
734 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
735 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
738 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
739 I40E_FLOW_CONTROL_ETHERTYPE, flags,
740 pf->main_vsi_seid, 0,
744 "Failed to add filter to drop flow control frames from VSIs.");
748 floating_veb_list_handler(__rte_unused const char *key,
749 const char *floating_veb_value,
753 unsigned int count = 0;
756 bool *vf_floating_veb = opaque;
758 while (isblank(*floating_veb_value))
759 floating_veb_value++;
761 /* Reset floating VEB configuration for VFs */
762 for (idx = 0; idx < I40E_MAX_VF; idx++)
763 vf_floating_veb[idx] = false;
767 while (isblank(*floating_veb_value))
768 floating_veb_value++;
769 if (*floating_veb_value == '\0')
772 idx = strtoul(floating_veb_value, &end, 10);
773 if (errno || end == NULL)
775 while (isblank(*end))
779 } else if ((*end == ';') || (*end == '\0')) {
781 if (min == I40E_MAX_VF)
783 if (max >= I40E_MAX_VF)
784 max = I40E_MAX_VF - 1;
785 for (idx = min; idx <= max; idx++) {
786 vf_floating_veb[idx] = true;
793 floating_veb_value = end + 1;
794 } while (*end != '\0');
803 config_vf_floating_veb(struct rte_devargs *devargs,
804 uint16_t floating_veb,
805 bool *vf_floating_veb)
807 struct rte_kvargs *kvlist;
809 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
813 /* All the VFs attach to the floating VEB by default
814 * when the floating VEB is enabled.
816 for (i = 0; i < I40E_MAX_VF; i++)
817 vf_floating_veb[i] = true;
822 kvlist = rte_kvargs_parse(devargs->args, NULL);
826 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
827 rte_kvargs_free(kvlist);
830 /* When the floating_veb_list parameter exists, all the VFs
831 * will attach to the legacy VEB firstly, then configure VFs
832 * to the floating VEB according to the floating_veb_list.
834 if (rte_kvargs_process(kvlist, floating_veb_list,
835 floating_veb_list_handler,
836 vf_floating_veb) < 0) {
837 rte_kvargs_free(kvlist);
840 rte_kvargs_free(kvlist);
844 i40e_check_floating_handler(__rte_unused const char *key,
846 __rte_unused void *opaque)
848 if (strcmp(value, "1"))
855 is_floating_veb_supported(struct rte_devargs *devargs)
857 struct rte_kvargs *kvlist;
858 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
863 kvlist = rte_kvargs_parse(devargs->args, NULL);
867 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
868 rte_kvargs_free(kvlist);
871 /* Floating VEB is enabled when there's key-value:
872 * enable_floating_veb=1
874 if (rte_kvargs_process(kvlist, floating_veb_key,
875 i40e_check_floating_handler, NULL) < 0) {
876 rte_kvargs_free(kvlist);
879 rte_kvargs_free(kvlist);
885 config_floating_veb(struct rte_eth_dev *dev)
887 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
888 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
889 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
891 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
893 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
895 is_floating_veb_supported(pci_dev->device.devargs);
896 config_vf_floating_veb(pci_dev->device.devargs,
898 pf->floating_veb_list);
900 pf->floating_veb = false;
904 #define I40E_L2_TAGS_S_TAG_SHIFT 1
905 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
908 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
910 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
911 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
912 char ethertype_hash_name[RTE_HASH_NAMESIZE];
915 struct rte_hash_parameters ethertype_hash_params = {
916 .name = ethertype_hash_name,
917 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
918 .key_len = sizeof(struct i40e_ethertype_filter_input),
919 .hash_func = rte_hash_crc,
920 .hash_func_init_val = 0,
921 .socket_id = rte_socket_id(),
924 /* Initialize ethertype filter rule list and hash */
925 TAILQ_INIT(ðertype_rule->ethertype_list);
926 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
927 "ethertype_%s", dev->device->name);
928 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
929 if (!ethertype_rule->hash_table) {
930 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
933 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
934 sizeof(struct i40e_ethertype_filter *) *
935 I40E_MAX_ETHERTYPE_FILTER_NUM,
937 if (!ethertype_rule->hash_map) {
939 "Failed to allocate memory for ethertype hash map!");
941 goto err_ethertype_hash_map_alloc;
946 err_ethertype_hash_map_alloc:
947 rte_hash_free(ethertype_rule->hash_table);
953 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
955 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
956 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
957 char tunnel_hash_name[RTE_HASH_NAMESIZE];
960 struct rte_hash_parameters tunnel_hash_params = {
961 .name = tunnel_hash_name,
962 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
963 .key_len = sizeof(struct i40e_tunnel_filter_input),
964 .hash_func = rte_hash_crc,
965 .hash_func_init_val = 0,
966 .socket_id = rte_socket_id(),
969 /* Initialize tunnel filter rule list and hash */
970 TAILQ_INIT(&tunnel_rule->tunnel_list);
971 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
972 "tunnel_%s", dev->device->name);
973 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
974 if (!tunnel_rule->hash_table) {
975 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
978 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
979 sizeof(struct i40e_tunnel_filter *) *
980 I40E_MAX_TUNNEL_FILTER_NUM,
982 if (!tunnel_rule->hash_map) {
984 "Failed to allocate memory for tunnel hash map!");
986 goto err_tunnel_hash_map_alloc;
991 err_tunnel_hash_map_alloc:
992 rte_hash_free(tunnel_rule->hash_table);
998 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1000 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1001 struct i40e_fdir_info *fdir_info = &pf->fdir;
1002 char fdir_hash_name[RTE_HASH_NAMESIZE];
1005 struct rte_hash_parameters fdir_hash_params = {
1006 .name = fdir_hash_name,
1007 .entries = I40E_MAX_FDIR_FILTER_NUM,
1008 .key_len = sizeof(struct rte_eth_fdir_input),
1009 .hash_func = rte_hash_crc,
1010 .hash_func_init_val = 0,
1011 .socket_id = rte_socket_id(),
1014 /* Initialize flow director filter rule list and hash */
1015 TAILQ_INIT(&fdir_info->fdir_list);
1016 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1017 "fdir_%s", dev->device->name);
1018 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1019 if (!fdir_info->hash_table) {
1020 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1023 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1024 sizeof(struct i40e_fdir_filter *) *
1025 I40E_MAX_FDIR_FILTER_NUM,
1027 if (!fdir_info->hash_map) {
1029 "Failed to allocate memory for fdir hash map!");
1031 goto err_fdir_hash_map_alloc;
1035 err_fdir_hash_map_alloc:
1036 rte_hash_free(fdir_info->hash_table);
1042 i40e_init_customized_info(struct i40e_pf *pf)
1046 /* Initialize customized pctype */
1047 for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1048 pf->customized_pctype[i].index = i;
1049 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1050 pf->customized_pctype[i].valid = false;
1053 pf->gtp_support = false;
1057 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1059 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1060 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1061 struct i40e_queue_regions *info = &pf->queue_region;
1064 for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1065 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1067 memset(info, 0, sizeof(struct i40e_queue_regions));
1071 eth_i40e_dev_init(struct rte_eth_dev *dev)
1073 struct rte_pci_device *pci_dev;
1074 struct rte_intr_handle *intr_handle;
1075 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1076 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1077 struct i40e_vsi *vsi;
1080 uint8_t aq_fail = 0;
1082 PMD_INIT_FUNC_TRACE();
1084 dev->dev_ops = &i40e_eth_dev_ops;
1085 dev->rx_pkt_burst = i40e_recv_pkts;
1086 dev->tx_pkt_burst = i40e_xmit_pkts;
1087 dev->tx_pkt_prepare = i40e_prep_pkts;
1089 /* for secondary processes, we don't initialise any further as primary
1090 * has already done this work. Only check we don't need a different
1092 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1093 i40e_set_rx_function(dev);
1094 i40e_set_tx_function(dev);
1097 i40e_set_default_ptype_table(dev);
1098 i40e_set_default_pctype_table(dev);
1099 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1100 intr_handle = &pci_dev->intr_handle;
1102 rte_eth_copy_pci_info(dev, pci_dev);
1103 dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1105 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1106 pf->adapter->eth_dev = dev;
1107 pf->dev_data = dev->data;
1109 hw->back = I40E_PF_TO_ADAPTER(pf);
1110 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1113 "Hardware is not available, as address is NULL");
1117 hw->vendor_id = pci_dev->id.vendor_id;
1118 hw->device_id = pci_dev->id.device_id;
1119 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1120 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1121 hw->bus.device = pci_dev->addr.devid;
1122 hw->bus.func = pci_dev->addr.function;
1123 hw->adapter_stopped = 0;
1125 /* Make sure all is clean before doing PF reset */
1128 /* Initialize the hardware */
1131 /* Reset here to make sure all is clean for each PF */
1132 ret = i40e_pf_reset(hw);
1134 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1138 /* Initialize the shared code (base driver) */
1139 ret = i40e_init_shared_code(hw);
1141 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1146 * To work around the NVM issue, initialize registers
1147 * for flexible payload and packet type of QinQ by
1148 * software. It should be removed once issues are fixed
1151 i40e_GLQF_reg_init(hw);
1153 /* Initialize the input set for filters (hash and fd) to default value */
1154 i40e_filter_input_set_init(pf);
1156 /* Initialize the parameters for adminq */
1157 i40e_init_adminq_parameter(hw);
1158 ret = i40e_init_adminq(hw);
1159 if (ret != I40E_SUCCESS) {
1160 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1163 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1164 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1165 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1166 ((hw->nvm.version >> 12) & 0xf),
1167 ((hw->nvm.version >> 4) & 0xff),
1168 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1170 /* initialise the L3_MAP register */
1171 ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1174 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
1176 /* Need the special FW version to support floating VEB */
1177 config_floating_veb(dev);
1178 /* Clear PXE mode */
1179 i40e_clear_pxe_mode(hw);
1180 i40e_dev_sync_phy_type(hw);
1183 * On X710, performance number is far from the expectation on recent
1184 * firmware versions. The fix for this issue may not be integrated in
1185 * the following firmware version. So the workaround in software driver
1186 * is needed. It needs to modify the initial values of 3 internal only
1187 * registers. Note that the workaround can be removed when it is fixed
1188 * in firmware in the future.
1190 i40e_configure_registers(hw);
1192 /* Get hw capabilities */
1193 ret = i40e_get_cap(hw);
1194 if (ret != I40E_SUCCESS) {
1195 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1196 goto err_get_capabilities;
1199 /* Initialize parameters for PF */
1200 ret = i40e_pf_parameter_init(dev);
1202 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1203 goto err_parameter_init;
1206 /* Initialize the queue management */
1207 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1209 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1210 goto err_qp_pool_init;
1212 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1213 hw->func_caps.num_msix_vectors - 1);
1215 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1216 goto err_msix_pool_init;
1219 /* Initialize lan hmc */
1220 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1221 hw->func_caps.num_rx_qp, 0, 0);
1222 if (ret != I40E_SUCCESS) {
1223 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1224 goto err_init_lan_hmc;
1227 /* Configure lan hmc */
1228 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1229 if (ret != I40E_SUCCESS) {
1230 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1231 goto err_configure_lan_hmc;
1234 /* Get and check the mac address */
1235 i40e_get_mac_addr(hw, hw->mac.addr);
1236 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1237 PMD_INIT_LOG(ERR, "mac address is not valid");
1239 goto err_get_mac_addr;
1241 /* Copy the permanent MAC address */
1242 ether_addr_copy((struct ether_addr *) hw->mac.addr,
1243 (struct ether_addr *) hw->mac.perm_addr);
1245 /* Disable flow control */
1246 hw->fc.requested_mode = I40E_FC_NONE;
1247 i40e_set_fc(hw, &aq_fail, TRUE);
1249 /* Set the global registers with default ether type value */
1250 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1251 if (ret != I40E_SUCCESS) {
1253 "Failed to set the default outer VLAN ether type");
1254 goto err_setup_pf_switch;
1257 /* PF setup, which includes VSI setup */
1258 ret = i40e_pf_setup(pf);
1260 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1261 goto err_setup_pf_switch;
1264 /* reset all stats of the device, including pf and main vsi */
1265 i40e_dev_stats_reset(dev);
1269 /* Disable double vlan by default */
1270 i40e_vsi_config_double_vlan(vsi, FALSE);
1272 /* Disable S-TAG identification when floating_veb is disabled */
1273 if (!pf->floating_veb) {
1274 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1275 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1276 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1277 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1281 if (!vsi->max_macaddrs)
1282 len = ETHER_ADDR_LEN;
1284 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1286 /* Should be after VSI initialized */
1287 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1288 if (!dev->data->mac_addrs) {
1290 "Failed to allocated memory for storing mac address");
1293 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1294 &dev->data->mac_addrs[0]);
1296 /* Init dcb to sw mode by default */
1297 ret = i40e_dcb_init_configure(dev, TRUE);
1298 if (ret != I40E_SUCCESS) {
1299 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1300 pf->flags &= ~I40E_FLAG_DCB;
1302 /* Update HW struct after DCB configuration */
1305 /* initialize pf host driver to setup SRIOV resource if applicable */
1306 i40e_pf_host_init(dev);
1308 /* register callback func to eal lib */
1309 rte_intr_callback_register(intr_handle,
1310 i40e_dev_interrupt_handler, dev);
1312 /* configure and enable device interrupt */
1313 i40e_pf_config_irq0(hw, TRUE);
1314 i40e_pf_enable_irq0(hw);
1316 /* enable uio intr after callback register */
1317 rte_intr_enable(intr_handle);
1319 * Add an ethertype filter to drop all flow control frames transmitted
1320 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1323 i40e_add_tx_flow_control_drop_filter(pf);
1325 /* Set the max frame size to 0x2600 by default,
1326 * in case other drivers changed the default value.
1328 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1330 /* initialize mirror rule list */
1331 TAILQ_INIT(&pf->mirror_list);
1333 /* initialize Traffic Manager configuration */
1334 i40e_tm_conf_init(dev);
1336 /* Initialize customized information */
1337 i40e_init_customized_info(pf);
1339 ret = i40e_init_ethtype_filter_list(dev);
1341 goto err_init_ethtype_filter_list;
1342 ret = i40e_init_tunnel_filter_list(dev);
1344 goto err_init_tunnel_filter_list;
1345 ret = i40e_init_fdir_filter_list(dev);
1347 goto err_init_fdir_filter_list;
1349 /* initialize queue region configuration */
1350 i40e_init_queue_region_conf(dev);
1354 err_init_fdir_filter_list:
1355 rte_free(pf->tunnel.hash_table);
1356 rte_free(pf->tunnel.hash_map);
1357 err_init_tunnel_filter_list:
1358 rte_free(pf->ethertype.hash_table);
1359 rte_free(pf->ethertype.hash_map);
1360 err_init_ethtype_filter_list:
1361 rte_free(dev->data->mac_addrs);
1363 i40e_vsi_release(pf->main_vsi);
1364 err_setup_pf_switch:
1366 err_configure_lan_hmc:
1367 (void)i40e_shutdown_lan_hmc(hw);
1369 i40e_res_pool_destroy(&pf->msix_pool);
1371 i40e_res_pool_destroy(&pf->qp_pool);
1374 err_get_capabilities:
1375 (void)i40e_shutdown_adminq(hw);
1381 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1383 struct i40e_ethertype_filter *p_ethertype;
1384 struct i40e_ethertype_rule *ethertype_rule;
1386 ethertype_rule = &pf->ethertype;
1387 /* Remove all ethertype filter rules and hash */
1388 if (ethertype_rule->hash_map)
1389 rte_free(ethertype_rule->hash_map);
1390 if (ethertype_rule->hash_table)
1391 rte_hash_free(ethertype_rule->hash_table);
1393 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1394 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1395 p_ethertype, rules);
1396 rte_free(p_ethertype);
1401 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1403 struct i40e_tunnel_filter *p_tunnel;
1404 struct i40e_tunnel_rule *tunnel_rule;
1406 tunnel_rule = &pf->tunnel;
1407 /* Remove all tunnel director rules and hash */
1408 if (tunnel_rule->hash_map)
1409 rte_free(tunnel_rule->hash_map);
1410 if (tunnel_rule->hash_table)
1411 rte_hash_free(tunnel_rule->hash_table);
1413 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1414 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1420 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1422 struct i40e_fdir_filter *p_fdir;
1423 struct i40e_fdir_info *fdir_info;
1425 fdir_info = &pf->fdir;
1426 /* Remove all flow director rules and hash */
1427 if (fdir_info->hash_map)
1428 rte_free(fdir_info->hash_map);
1429 if (fdir_info->hash_table)
1430 rte_hash_free(fdir_info->hash_table);
1432 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1433 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1439 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1442 struct rte_pci_device *pci_dev;
1443 struct rte_intr_handle *intr_handle;
1445 struct i40e_filter_control_settings settings;
1446 struct rte_flow *p_flow;
1448 uint8_t aq_fail = 0;
1450 PMD_INIT_FUNC_TRACE();
1452 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1455 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1456 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1457 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1458 intr_handle = &pci_dev->intr_handle;
1460 if (hw->adapter_stopped == 0)
1461 i40e_dev_close(dev);
1463 dev->dev_ops = NULL;
1464 dev->rx_pkt_burst = NULL;
1465 dev->tx_pkt_burst = NULL;
1467 /* Clear PXE mode */
1468 i40e_clear_pxe_mode(hw);
1470 /* Unconfigure filter control */
1471 memset(&settings, 0, sizeof(settings));
1472 ret = i40e_set_filter_control(hw, &settings);
1474 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1477 /* Disable flow control */
1478 hw->fc.requested_mode = I40E_FC_NONE;
1479 i40e_set_fc(hw, &aq_fail, TRUE);
1481 /* uninitialize pf host driver */
1482 i40e_pf_host_uninit(dev);
1484 rte_free(dev->data->mac_addrs);
1485 dev->data->mac_addrs = NULL;
1487 /* disable uio intr before callback unregister */
1488 rte_intr_disable(intr_handle);
1490 /* register callback func to eal lib */
1491 rte_intr_callback_unregister(intr_handle,
1492 i40e_dev_interrupt_handler, dev);
1494 i40e_rm_ethtype_filter_list(pf);
1495 i40e_rm_tunnel_filter_list(pf);
1496 i40e_rm_fdir_filter_list(pf);
1498 /* Remove all flows */
1499 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1500 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1504 /* Remove all Traffic Manager configuration */
1505 i40e_tm_conf_uninit(dev);
1511 i40e_dev_configure(struct rte_eth_dev *dev)
1513 struct i40e_adapter *ad =
1514 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1515 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1516 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1517 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1520 ret = i40e_dev_sync_phy_type(hw);
1524 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1525 * bulk allocation or vector Rx preconditions we will reset it.
1527 ad->rx_bulk_alloc_allowed = true;
1528 ad->rx_vec_allowed = true;
1529 ad->tx_simple_allowed = true;
1530 ad->tx_vec_allowed = true;
1532 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1533 ret = i40e_fdir_setup(pf);
1534 if (ret != I40E_SUCCESS) {
1535 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1538 ret = i40e_fdir_configure(dev);
1540 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1544 i40e_fdir_teardown(pf);
1546 ret = i40e_dev_init_vlan(dev);
1551 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1552 * RSS setting have different requirements.
1553 * General PMD driver call sequence are NIC init, configure,
1554 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1555 * will try to lookup the VSI that specific queue belongs to if VMDQ
1556 * applicable. So, VMDQ setting has to be done before
1557 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1558 * For RSS setting, it will try to calculate actual configured RX queue
1559 * number, which will be available after rx_queue_setup(). dev_start()
1560 * function is good to place RSS setup.
1562 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1563 ret = i40e_vmdq_setup(dev);
1568 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1569 ret = i40e_dcb_setup(dev);
1571 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1576 TAILQ_INIT(&pf->flow_list);
1581 /* need to release vmdq resource if exists */
1582 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1583 i40e_vsi_release(pf->vmdq[i].vsi);
1584 pf->vmdq[i].vsi = NULL;
1589 /* need to release fdir resource if exists */
1590 i40e_fdir_teardown(pf);
1595 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1597 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1598 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1599 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1600 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1601 uint16_t msix_vect = vsi->msix_intr;
1604 for (i = 0; i < vsi->nb_qps; i++) {
1605 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1606 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1610 if (vsi->type != I40E_VSI_SRIOV) {
1611 if (!rte_intr_allow_others(intr_handle)) {
1612 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1613 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1615 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1618 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1619 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1621 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1626 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1627 vsi->user_param + (msix_vect - 1);
1629 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1630 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1632 I40E_WRITE_FLUSH(hw);
1636 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1637 int base_queue, int nb_queue,
1642 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1644 /* Bind all RX queues to allocated MSIX interrupt */
1645 for (i = 0; i < nb_queue; i++) {
1646 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1647 itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1648 ((base_queue + i + 1) <<
1649 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1650 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1651 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1653 if (i == nb_queue - 1)
1654 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1655 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1658 /* Write first RX queue to Link list register as the head element */
1659 if (vsi->type != I40E_VSI_SRIOV) {
1661 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1663 if (msix_vect == I40E_MISC_VEC_ID) {
1664 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1666 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1668 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1670 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1673 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1675 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1677 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1679 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1686 if (msix_vect == I40E_MISC_VEC_ID) {
1688 I40E_VPINT_LNKLST0(vsi->user_param),
1690 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1692 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1694 /* num_msix_vectors_vf needs to minus irq0 */
1695 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1696 vsi->user_param + (msix_vect - 1);
1698 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1700 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1702 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1706 I40E_WRITE_FLUSH(hw);
1710 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1712 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1713 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1714 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1715 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1716 uint16_t msix_vect = vsi->msix_intr;
1717 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1718 uint16_t queue_idx = 0;
1723 for (i = 0; i < vsi->nb_qps; i++) {
1724 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1725 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1728 /* INTENA flag is not auto-cleared for interrupt */
1729 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1730 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1731 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1732 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1733 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1735 /* VF bind interrupt */
1736 if (vsi->type == I40E_VSI_SRIOV) {
1737 __vsi_queues_bind_intr(vsi, msix_vect,
1738 vsi->base_queue, vsi->nb_qps,
1743 /* PF & VMDq bind interrupt */
1744 if (rte_intr_dp_is_en(intr_handle)) {
1745 if (vsi->type == I40E_VSI_MAIN) {
1748 } else if (vsi->type == I40E_VSI_VMDQ2) {
1749 struct i40e_vsi *main_vsi =
1750 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1751 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1756 for (i = 0; i < vsi->nb_used_qps; i++) {
1758 if (!rte_intr_allow_others(intr_handle))
1759 /* allow to share MISC_VEC_ID */
1760 msix_vect = I40E_MISC_VEC_ID;
1762 /* no enough msix_vect, map all to one */
1763 __vsi_queues_bind_intr(vsi, msix_vect,
1764 vsi->base_queue + i,
1765 vsi->nb_used_qps - i,
1767 for (; !!record && i < vsi->nb_used_qps; i++)
1768 intr_handle->intr_vec[queue_idx + i] =
1772 /* 1:1 queue/msix_vect mapping */
1773 __vsi_queues_bind_intr(vsi, msix_vect,
1774 vsi->base_queue + i, 1,
1777 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1785 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1787 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1788 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1789 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1790 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1791 uint16_t interval = i40e_calc_itr_interval(\
1792 RTE_LIBRTE_I40E_ITR_INTERVAL);
1793 uint16_t msix_intr, i;
1795 if (rte_intr_allow_others(intr_handle))
1796 for (i = 0; i < vsi->nb_msix; i++) {
1797 msix_intr = vsi->msix_intr + i;
1798 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1799 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1800 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1801 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1803 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1806 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1807 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1808 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1809 (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1811 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1813 I40E_WRITE_FLUSH(hw);
1817 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1819 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1820 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1821 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1822 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1823 uint16_t msix_intr, i;
1825 if (rte_intr_allow_others(intr_handle))
1826 for (i = 0; i < vsi->nb_msix; i++) {
1827 msix_intr = vsi->msix_intr + i;
1828 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1832 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1834 I40E_WRITE_FLUSH(hw);
1837 static inline uint8_t
1838 i40e_parse_link_speeds(uint16_t link_speeds)
1840 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1842 if (link_speeds & ETH_LINK_SPEED_40G)
1843 link_speed |= I40E_LINK_SPEED_40GB;
1844 if (link_speeds & ETH_LINK_SPEED_25G)
1845 link_speed |= I40E_LINK_SPEED_25GB;
1846 if (link_speeds & ETH_LINK_SPEED_20G)
1847 link_speed |= I40E_LINK_SPEED_20GB;
1848 if (link_speeds & ETH_LINK_SPEED_10G)
1849 link_speed |= I40E_LINK_SPEED_10GB;
1850 if (link_speeds & ETH_LINK_SPEED_1G)
1851 link_speed |= I40E_LINK_SPEED_1GB;
1852 if (link_speeds & ETH_LINK_SPEED_100M)
1853 link_speed |= I40E_LINK_SPEED_100MB;
1859 i40e_phy_conf_link(struct i40e_hw *hw,
1861 uint8_t force_speed,
1864 enum i40e_status_code status;
1865 struct i40e_aq_get_phy_abilities_resp phy_ab;
1866 struct i40e_aq_set_phy_config phy_conf;
1867 enum i40e_aq_phy_type cnt;
1868 uint32_t phy_type_mask = 0;
1870 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1871 I40E_AQ_PHY_FLAG_PAUSE_RX |
1872 I40E_AQ_PHY_FLAG_PAUSE_RX |
1873 I40E_AQ_PHY_FLAG_LOW_POWER;
1874 const uint8_t advt = I40E_LINK_SPEED_40GB |
1875 I40E_LINK_SPEED_25GB |
1876 I40E_LINK_SPEED_10GB |
1877 I40E_LINK_SPEED_1GB |
1878 I40E_LINK_SPEED_100MB;
1882 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1887 /* If link already up, no need to set up again */
1888 if (is_up && phy_ab.phy_type != 0)
1889 return I40E_SUCCESS;
1891 memset(&phy_conf, 0, sizeof(phy_conf));
1893 /* bits 0-2 use the values from get_phy_abilities_resp */
1895 abilities |= phy_ab.abilities & mask;
1897 /* update ablities and speed */
1898 if (abilities & I40E_AQ_PHY_AN_ENABLED)
1899 phy_conf.link_speed = advt;
1901 phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed;
1903 phy_conf.abilities = abilities;
1907 /* To enable link, phy_type mask needs to include each type */
1908 for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_MAX; cnt++)
1909 phy_type_mask |= 1 << cnt;
1911 /* use get_phy_abilities_resp value for the rest */
1912 phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
1913 phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
1914 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
1915 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
1916 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1917 phy_conf.eee_capability = phy_ab.eee_capability;
1918 phy_conf.eeer = phy_ab.eeer_val;
1919 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1921 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1922 phy_ab.abilities, phy_ab.link_speed);
1923 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
1924 phy_conf.abilities, phy_conf.link_speed);
1926 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1930 return I40E_SUCCESS;
1934 i40e_apply_link_speed(struct rte_eth_dev *dev)
1937 uint8_t abilities = 0;
1938 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1939 struct rte_eth_conf *conf = &dev->data->dev_conf;
1941 speed = i40e_parse_link_speeds(conf->link_speeds);
1942 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1943 if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1944 abilities |= I40E_AQ_PHY_AN_ENABLED;
1945 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1947 return i40e_phy_conf_link(hw, abilities, speed, true);
1951 i40e_dev_start(struct rte_eth_dev *dev)
1953 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1954 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1955 struct i40e_vsi *main_vsi = pf->main_vsi;
1957 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1958 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1959 uint32_t intr_vector = 0;
1960 struct i40e_vsi *vsi;
1962 hw->adapter_stopped = 0;
1964 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1966 "Invalid link_speeds for port %u, autonegotiation disabled",
1967 dev->data->port_id);
1971 rte_intr_disable(intr_handle);
1973 if ((rte_intr_cap_multiple(intr_handle) ||
1974 !RTE_ETH_DEV_SRIOV(dev).active) &&
1975 dev->data->dev_conf.intr_conf.rxq != 0) {
1976 intr_vector = dev->data->nb_rx_queues;
1977 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1982 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1983 intr_handle->intr_vec =
1984 rte_zmalloc("intr_vec",
1985 dev->data->nb_rx_queues * sizeof(int),
1987 if (!intr_handle->intr_vec) {
1989 "Failed to allocate %d rx_queues intr_vec",
1990 dev->data->nb_rx_queues);
1995 /* Initialize VSI */
1996 ret = i40e_dev_rxtx_init(pf);
1997 if (ret != I40E_SUCCESS) {
1998 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2002 /* Map queues with MSIX interrupt */
2003 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2004 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2005 i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2006 i40e_vsi_enable_queues_intr(main_vsi);
2008 /* Map VMDQ VSI queues with MSIX interrupt */
2009 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2010 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2011 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2012 I40E_ITR_INDEX_DEFAULT);
2013 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2016 /* enable FDIR MSIX interrupt */
2017 if (pf->fdir.fdir_vsi) {
2018 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2019 I40E_ITR_INDEX_NONE);
2020 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2023 /* Enable all queues which have been configured */
2024 ret = i40e_dev_switch_queues(pf, TRUE);
2025 if (ret != I40E_SUCCESS) {
2026 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2030 /* Enable receiving broadcast packets */
2031 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2032 if (ret != I40E_SUCCESS)
2033 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2035 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2036 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2038 if (ret != I40E_SUCCESS)
2039 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2042 /* Enable the VLAN promiscuous mode. */
2044 for (i = 0; i < pf->vf_num; i++) {
2045 vsi = pf->vfs[i].vsi;
2046 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2051 /* Apply link configure */
2052 if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
2053 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
2054 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
2055 ETH_LINK_SPEED_40G)) {
2056 PMD_DRV_LOG(ERR, "Invalid link setting");
2059 ret = i40e_apply_link_speed(dev);
2060 if (I40E_SUCCESS != ret) {
2061 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2065 if (!rte_intr_allow_others(intr_handle)) {
2066 rte_intr_callback_unregister(intr_handle,
2067 i40e_dev_interrupt_handler,
2069 /* configure and enable device interrupt */
2070 i40e_pf_config_irq0(hw, FALSE);
2071 i40e_pf_enable_irq0(hw);
2073 if (dev->data->dev_conf.intr_conf.lsc != 0)
2075 "lsc won't enable because of no intr multiplex");
2077 ret = i40e_aq_set_phy_int_mask(hw,
2078 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2079 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2080 I40E_AQ_EVENT_MEDIA_NA), NULL);
2081 if (ret != I40E_SUCCESS)
2082 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2084 /* Call get_link_info aq commond to enable/disable LSE */
2085 i40e_dev_link_update(dev, 0);
2088 /* enable uio intr after callback register */
2089 rte_intr_enable(intr_handle);
2091 i40e_filter_restore(pf);
2093 if (pf->tm_conf.root && !pf->tm_conf.committed)
2094 PMD_DRV_LOG(WARNING,
2095 "please call hierarchy_commit() "
2096 "before starting the port");
2098 return I40E_SUCCESS;
2101 i40e_dev_switch_queues(pf, FALSE);
2102 i40e_dev_clear_queues(dev);
2108 i40e_dev_stop(struct rte_eth_dev *dev)
2110 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2111 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2112 struct i40e_vsi *main_vsi = pf->main_vsi;
2113 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2114 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2117 if (hw->adapter_stopped == 1)
2119 /* Disable all queues */
2120 i40e_dev_switch_queues(pf, FALSE);
2122 /* un-map queues with interrupt registers */
2123 i40e_vsi_disable_queues_intr(main_vsi);
2124 i40e_vsi_queues_unbind_intr(main_vsi);
2126 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2127 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2128 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2131 if (pf->fdir.fdir_vsi) {
2132 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2133 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2135 /* Clear all queues and release memory */
2136 i40e_dev_clear_queues(dev);
2139 i40e_dev_set_link_down(dev);
2141 if (!rte_intr_allow_others(intr_handle))
2142 /* resume to the default handler */
2143 rte_intr_callback_register(intr_handle,
2144 i40e_dev_interrupt_handler,
2147 /* Clean datapath event and queue/vec mapping */
2148 rte_intr_efd_disable(intr_handle);
2149 if (intr_handle->intr_vec) {
2150 rte_free(intr_handle->intr_vec);
2151 intr_handle->intr_vec = NULL;
2154 /* reset hierarchy commit */
2155 pf->tm_conf.committed = false;
2157 /* Remove all the queue region configuration */
2158 i40e_flush_queue_region_all_conf(dev, hw, pf, 0);
2160 hw->adapter_stopped = 1;
2164 i40e_dev_close(struct rte_eth_dev *dev)
2166 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2167 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2168 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2169 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2170 struct i40e_mirror_rule *p_mirror;
2175 PMD_INIT_FUNC_TRACE();
2179 /* Remove all mirror rules */
2180 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2181 ret = i40e_aq_del_mirror_rule(hw,
2182 pf->main_vsi->veb->seid,
2183 p_mirror->rule_type,
2185 p_mirror->num_entries,
2188 PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2189 "status = %d, aq_err = %d.", ret,
2190 hw->aq.asq_last_status);
2192 /* remove mirror software resource anyway */
2193 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2195 pf->nb_mirror_rule--;
2198 i40e_dev_free_queues(dev);
2200 /* Disable interrupt */
2201 i40e_pf_disable_irq0(hw);
2202 rte_intr_disable(intr_handle);
2204 /* shutdown and destroy the HMC */
2205 i40e_shutdown_lan_hmc(hw);
2207 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2208 i40e_vsi_release(pf->vmdq[i].vsi);
2209 pf->vmdq[i].vsi = NULL;
2214 /* release all the existing VSIs and VEBs */
2215 i40e_fdir_teardown(pf);
2216 i40e_vsi_release(pf->main_vsi);
2218 /* shutdown the adminq */
2219 i40e_aq_queue_shutdown(hw, true);
2220 i40e_shutdown_adminq(hw);
2222 i40e_res_pool_destroy(&pf->qp_pool);
2223 i40e_res_pool_destroy(&pf->msix_pool);
2225 /* force a PF reset to clean anything leftover */
2226 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2227 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2228 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2229 I40E_WRITE_FLUSH(hw);
2233 * Reset PF device only to re-initialize resources in PMD layer
2236 i40e_dev_reset(struct rte_eth_dev *dev)
2240 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2241 * its VF to make them align with it. The detailed notification
2242 * mechanism is PMD specific. As to i40e PF, it is rather complex.
2243 * To avoid unexpected behavior in VF, currently reset of PF with
2244 * SR-IOV activation is not supported. It might be supported later.
2246 if (dev->data->sriov.active)
2249 ret = eth_i40e_dev_uninit(dev);
2253 ret = eth_i40e_dev_init(dev);
2259 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2261 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2262 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2263 struct i40e_vsi *vsi = pf->main_vsi;
2266 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2268 if (status != I40E_SUCCESS)
2269 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2271 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2273 if (status != I40E_SUCCESS)
2274 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2279 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2281 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2282 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2283 struct i40e_vsi *vsi = pf->main_vsi;
2286 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2288 if (status != I40E_SUCCESS)
2289 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2291 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2293 if (status != I40E_SUCCESS)
2294 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2298 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2300 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2301 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2302 struct i40e_vsi *vsi = pf->main_vsi;
2305 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2306 if (ret != I40E_SUCCESS)
2307 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2311 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2313 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2314 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2315 struct i40e_vsi *vsi = pf->main_vsi;
2318 if (dev->data->promiscuous == 1)
2319 return; /* must remain in all_multicast mode */
2321 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2322 vsi->seid, FALSE, NULL);
2323 if (ret != I40E_SUCCESS)
2324 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2328 * Set device link up.
2331 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2333 /* re-apply link speed setting */
2334 return i40e_apply_link_speed(dev);
2338 * Set device link down.
2341 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2343 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2344 uint8_t abilities = 0;
2345 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2347 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2348 return i40e_phy_conf_link(hw, abilities, speed, false);
2352 i40e_dev_link_update(struct rte_eth_dev *dev,
2353 int wait_to_complete)
2355 #define CHECK_INTERVAL 100 /* 100ms */
2356 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2357 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2358 struct i40e_link_status link_status;
2359 struct rte_eth_link link, old;
2361 unsigned rep_cnt = MAX_REPEAT_TIME;
2362 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2364 memset(&link, 0, sizeof(link));
2365 memset(&old, 0, sizeof(old));
2366 memset(&link_status, 0, sizeof(link_status));
2367 rte_i40e_dev_atomic_read_link_status(dev, &old);
2370 /* Get link status information from hardware */
2371 status = i40e_aq_get_link_info(hw, enable_lse,
2372 &link_status, NULL);
2373 if (status != I40E_SUCCESS) {
2374 link.link_speed = ETH_SPEED_NUM_100M;
2375 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2376 PMD_DRV_LOG(ERR, "Failed to get link info");
2380 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2381 if (!wait_to_complete || link.link_status)
2384 rte_delay_ms(CHECK_INTERVAL);
2385 } while (--rep_cnt);
2387 if (!link.link_status)
2390 /* i40e uses full duplex only */
2391 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2393 /* Parse the link status */
2394 switch (link_status.link_speed) {
2395 case I40E_LINK_SPEED_100MB:
2396 link.link_speed = ETH_SPEED_NUM_100M;
2398 case I40E_LINK_SPEED_1GB:
2399 link.link_speed = ETH_SPEED_NUM_1G;
2401 case I40E_LINK_SPEED_10GB:
2402 link.link_speed = ETH_SPEED_NUM_10G;
2404 case I40E_LINK_SPEED_20GB:
2405 link.link_speed = ETH_SPEED_NUM_20G;
2407 case I40E_LINK_SPEED_25GB:
2408 link.link_speed = ETH_SPEED_NUM_25G;
2410 case I40E_LINK_SPEED_40GB:
2411 link.link_speed = ETH_SPEED_NUM_40G;
2414 link.link_speed = ETH_SPEED_NUM_100M;
2418 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2419 ETH_LINK_SPEED_FIXED);
2422 rte_i40e_dev_atomic_write_link_status(dev, &link);
2423 if (link.link_status == old.link_status)
2426 i40e_notify_all_vfs_link_status(dev);
2431 /* Get all the statistics of a VSI */
2433 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2435 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2436 struct i40e_eth_stats *nes = &vsi->eth_stats;
2437 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2438 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2440 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2441 vsi->offset_loaded, &oes->rx_bytes,
2443 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2444 vsi->offset_loaded, &oes->rx_unicast,
2446 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2447 vsi->offset_loaded, &oes->rx_multicast,
2448 &nes->rx_multicast);
2449 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2450 vsi->offset_loaded, &oes->rx_broadcast,
2451 &nes->rx_broadcast);
2452 /* exclude CRC bytes */
2453 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2454 nes->rx_broadcast) * ETHER_CRC_LEN;
2456 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2457 &oes->rx_discards, &nes->rx_discards);
2458 /* GLV_REPC not supported */
2459 /* GLV_RMPC not supported */
2460 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2461 &oes->rx_unknown_protocol,
2462 &nes->rx_unknown_protocol);
2463 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2464 vsi->offset_loaded, &oes->tx_bytes,
2466 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2467 vsi->offset_loaded, &oes->tx_unicast,
2469 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2470 vsi->offset_loaded, &oes->tx_multicast,
2471 &nes->tx_multicast);
2472 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2473 vsi->offset_loaded, &oes->tx_broadcast,
2474 &nes->tx_broadcast);
2475 /* GLV_TDPC not supported */
2476 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2477 &oes->tx_errors, &nes->tx_errors);
2478 vsi->offset_loaded = true;
2480 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2482 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2483 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2484 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2485 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2486 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2487 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2488 nes->rx_unknown_protocol);
2489 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2490 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2491 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2492 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2493 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2494 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2495 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2500 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2503 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2504 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2506 /* Get rx/tx bytes of internal transfer packets */
2507 i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2508 I40E_GLV_GORCL(hw->port),
2510 &pf->internal_stats_offset.rx_bytes,
2511 &pf->internal_stats.rx_bytes);
2513 i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2514 I40E_GLV_GOTCL(hw->port),
2516 &pf->internal_stats_offset.tx_bytes,
2517 &pf->internal_stats.tx_bytes);
2518 /* Get total internal rx packet count */
2519 i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2520 I40E_GLV_UPRCL(hw->port),
2522 &pf->internal_stats_offset.rx_unicast,
2523 &pf->internal_stats.rx_unicast);
2524 i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2525 I40E_GLV_MPRCL(hw->port),
2527 &pf->internal_stats_offset.rx_multicast,
2528 &pf->internal_stats.rx_multicast);
2529 i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2530 I40E_GLV_BPRCL(hw->port),
2532 &pf->internal_stats_offset.rx_broadcast,
2533 &pf->internal_stats.rx_broadcast);
2535 /* exclude CRC size */
2536 pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2537 pf->internal_stats.rx_multicast +
2538 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2540 /* Get statistics of struct i40e_eth_stats */
2541 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2542 I40E_GLPRT_GORCL(hw->port),
2543 pf->offset_loaded, &os->eth.rx_bytes,
2545 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2546 I40E_GLPRT_UPRCL(hw->port),
2547 pf->offset_loaded, &os->eth.rx_unicast,
2548 &ns->eth.rx_unicast);
2549 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2550 I40E_GLPRT_MPRCL(hw->port),
2551 pf->offset_loaded, &os->eth.rx_multicast,
2552 &ns->eth.rx_multicast);
2553 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2554 I40E_GLPRT_BPRCL(hw->port),
2555 pf->offset_loaded, &os->eth.rx_broadcast,
2556 &ns->eth.rx_broadcast);
2557 /* Workaround: CRC size should not be included in byte statistics,
2558 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2560 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2561 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2563 /* Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2564 * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negtive
2567 if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2568 ns->eth.rx_bytes = 0;
2569 /* exlude internal rx bytes */
2571 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2573 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2574 pf->offset_loaded, &os->eth.rx_discards,
2575 &ns->eth.rx_discards);
2576 /* GLPRT_REPC not supported */
2577 /* GLPRT_RMPC not supported */
2578 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2580 &os->eth.rx_unknown_protocol,
2581 &ns->eth.rx_unknown_protocol);
2582 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2583 I40E_GLPRT_GOTCL(hw->port),
2584 pf->offset_loaded, &os->eth.tx_bytes,
2586 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2587 I40E_GLPRT_UPTCL(hw->port),
2588 pf->offset_loaded, &os->eth.tx_unicast,
2589 &ns->eth.tx_unicast);
2590 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2591 I40E_GLPRT_MPTCL(hw->port),
2592 pf->offset_loaded, &os->eth.tx_multicast,
2593 &ns->eth.tx_multicast);
2594 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2595 I40E_GLPRT_BPTCL(hw->port),
2596 pf->offset_loaded, &os->eth.tx_broadcast,
2597 &ns->eth.tx_broadcast);
2598 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2599 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2601 /* exclude internal tx bytes */
2602 if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2603 ns->eth.tx_bytes = 0;
2605 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2607 /* GLPRT_TEPC not supported */
2609 /* additional port specific stats */
2610 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2611 pf->offset_loaded, &os->tx_dropped_link_down,
2612 &ns->tx_dropped_link_down);
2613 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2614 pf->offset_loaded, &os->crc_errors,
2616 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2617 pf->offset_loaded, &os->illegal_bytes,
2618 &ns->illegal_bytes);
2619 /* GLPRT_ERRBC not supported */
2620 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2621 pf->offset_loaded, &os->mac_local_faults,
2622 &ns->mac_local_faults);
2623 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2624 pf->offset_loaded, &os->mac_remote_faults,
2625 &ns->mac_remote_faults);
2626 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2627 pf->offset_loaded, &os->rx_length_errors,
2628 &ns->rx_length_errors);
2629 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2630 pf->offset_loaded, &os->link_xon_rx,
2632 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2633 pf->offset_loaded, &os->link_xoff_rx,
2635 for (i = 0; i < 8; i++) {
2636 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2638 &os->priority_xon_rx[i],
2639 &ns->priority_xon_rx[i]);
2640 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2642 &os->priority_xoff_rx[i],
2643 &ns->priority_xoff_rx[i]);
2645 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2646 pf->offset_loaded, &os->link_xon_tx,
2648 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2649 pf->offset_loaded, &os->link_xoff_tx,
2651 for (i = 0; i < 8; i++) {
2652 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2654 &os->priority_xon_tx[i],
2655 &ns->priority_xon_tx[i]);
2656 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2658 &os->priority_xoff_tx[i],
2659 &ns->priority_xoff_tx[i]);
2660 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2662 &os->priority_xon_2_xoff[i],
2663 &ns->priority_xon_2_xoff[i]);
2665 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2666 I40E_GLPRT_PRC64L(hw->port),
2667 pf->offset_loaded, &os->rx_size_64,
2669 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2670 I40E_GLPRT_PRC127L(hw->port),
2671 pf->offset_loaded, &os->rx_size_127,
2673 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2674 I40E_GLPRT_PRC255L(hw->port),
2675 pf->offset_loaded, &os->rx_size_255,
2677 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2678 I40E_GLPRT_PRC511L(hw->port),
2679 pf->offset_loaded, &os->rx_size_511,
2681 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2682 I40E_GLPRT_PRC1023L(hw->port),
2683 pf->offset_loaded, &os->rx_size_1023,
2685 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2686 I40E_GLPRT_PRC1522L(hw->port),
2687 pf->offset_loaded, &os->rx_size_1522,
2689 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2690 I40E_GLPRT_PRC9522L(hw->port),
2691 pf->offset_loaded, &os->rx_size_big,
2693 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2694 pf->offset_loaded, &os->rx_undersize,
2696 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2697 pf->offset_loaded, &os->rx_fragments,
2699 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2700 pf->offset_loaded, &os->rx_oversize,
2702 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2703 pf->offset_loaded, &os->rx_jabber,
2705 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2706 I40E_GLPRT_PTC64L(hw->port),
2707 pf->offset_loaded, &os->tx_size_64,
2709 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2710 I40E_GLPRT_PTC127L(hw->port),
2711 pf->offset_loaded, &os->tx_size_127,
2713 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2714 I40E_GLPRT_PTC255L(hw->port),
2715 pf->offset_loaded, &os->tx_size_255,
2717 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2718 I40E_GLPRT_PTC511L(hw->port),
2719 pf->offset_loaded, &os->tx_size_511,
2721 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2722 I40E_GLPRT_PTC1023L(hw->port),
2723 pf->offset_loaded, &os->tx_size_1023,
2725 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2726 I40E_GLPRT_PTC1522L(hw->port),
2727 pf->offset_loaded, &os->tx_size_1522,
2729 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2730 I40E_GLPRT_PTC9522L(hw->port),
2731 pf->offset_loaded, &os->tx_size_big,
2733 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2735 &os->fd_sb_match, &ns->fd_sb_match);
2736 /* GLPRT_MSPDC not supported */
2737 /* GLPRT_XEC not supported */
2739 pf->offset_loaded = true;
2742 i40e_update_vsi_stats(pf->main_vsi);
2745 /* Get all statistics of a port */
2747 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2749 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2750 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2751 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2754 /* call read registers - updates values, now write them to struct */
2755 i40e_read_stats_registers(pf, hw);
2757 stats->ipackets = ns->eth.rx_unicast +
2758 ns->eth.rx_multicast +
2759 ns->eth.rx_broadcast -
2760 ns->eth.rx_discards -
2761 pf->main_vsi->eth_stats.rx_discards;
2762 stats->opackets = ns->eth.tx_unicast +
2763 ns->eth.tx_multicast +
2764 ns->eth.tx_broadcast;
2765 stats->ibytes = ns->eth.rx_bytes;
2766 stats->obytes = ns->eth.tx_bytes;
2767 stats->oerrors = ns->eth.tx_errors +
2768 pf->main_vsi->eth_stats.tx_errors;
2771 stats->imissed = ns->eth.rx_discards +
2772 pf->main_vsi->eth_stats.rx_discards;
2773 stats->ierrors = ns->crc_errors +
2774 ns->rx_length_errors + ns->rx_undersize +
2775 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2777 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2778 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
2779 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
2780 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
2781 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
2782 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
2783 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2784 ns->eth.rx_unknown_protocol);
2785 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
2786 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
2787 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
2788 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
2789 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
2790 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
2792 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
2793 ns->tx_dropped_link_down);
2794 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
2795 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
2797 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
2798 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
2799 ns->mac_local_faults);
2800 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
2801 ns->mac_remote_faults);
2802 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
2803 ns->rx_length_errors);
2804 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
2805 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
2806 for (i = 0; i < 8; i++) {
2807 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
2808 i, ns->priority_xon_rx[i]);
2809 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
2810 i, ns->priority_xoff_rx[i]);
2812 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
2813 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
2814 for (i = 0; i < 8; i++) {
2815 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
2816 i, ns->priority_xon_tx[i]);
2817 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
2818 i, ns->priority_xoff_tx[i]);
2819 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
2820 i, ns->priority_xon_2_xoff[i]);
2822 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
2823 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
2824 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
2825 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
2826 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
2827 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
2828 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
2829 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
2830 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
2831 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
2832 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
2833 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
2834 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
2835 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
2836 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
2837 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
2838 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
2839 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
2840 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2841 ns->mac_short_packet_dropped);
2842 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
2843 ns->checksum_error);
2844 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
2845 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2849 /* Reset the statistics */
2851 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2853 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2854 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2856 /* Mark PF and VSI stats to update the offset, aka "reset" */
2857 pf->offset_loaded = false;
2859 pf->main_vsi->offset_loaded = false;
2861 /* read the stats, reading current register values into offset */
2862 i40e_read_stats_registers(pf, hw);
2866 i40e_xstats_calc_num(void)
2868 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2869 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2870 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2873 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2874 struct rte_eth_xstat_name *xstats_names,
2875 __rte_unused unsigned limit)
2880 if (xstats_names == NULL)
2881 return i40e_xstats_calc_num();
2883 /* Note: limit checked in rte_eth_xstats_names() */
2885 /* Get stats from i40e_eth_stats struct */
2886 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2887 snprintf(xstats_names[count].name,
2888 sizeof(xstats_names[count].name),
2889 "%s", rte_i40e_stats_strings[i].name);
2893 /* Get individiual stats from i40e_hw_port struct */
2894 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2895 snprintf(xstats_names[count].name,
2896 sizeof(xstats_names[count].name),
2897 "%s", rte_i40e_hw_port_strings[i].name);
2901 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2902 for (prio = 0; prio < 8; prio++) {
2903 snprintf(xstats_names[count].name,
2904 sizeof(xstats_names[count].name),
2905 "rx_priority%u_%s", prio,
2906 rte_i40e_rxq_prio_strings[i].name);
2911 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2912 for (prio = 0; prio < 8; prio++) {
2913 snprintf(xstats_names[count].name,
2914 sizeof(xstats_names[count].name),
2915 "tx_priority%u_%s", prio,
2916 rte_i40e_txq_prio_strings[i].name);
2924 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2927 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2928 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2929 unsigned i, count, prio;
2930 struct i40e_hw_port_stats *hw_stats = &pf->stats;
2932 count = i40e_xstats_calc_num();
2936 i40e_read_stats_registers(pf, hw);
2943 /* Get stats from i40e_eth_stats struct */
2944 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2945 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2946 rte_i40e_stats_strings[i].offset);
2947 xstats[count].id = count;
2951 /* Get individiual stats from i40e_hw_port struct */
2952 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2953 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2954 rte_i40e_hw_port_strings[i].offset);
2955 xstats[count].id = count;
2959 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2960 for (prio = 0; prio < 8; prio++) {
2961 xstats[count].value =
2962 *(uint64_t *)(((char *)hw_stats) +
2963 rte_i40e_rxq_prio_strings[i].offset +
2964 (sizeof(uint64_t) * prio));
2965 xstats[count].id = count;
2970 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2971 for (prio = 0; prio < 8; prio++) {
2972 xstats[count].value =
2973 *(uint64_t *)(((char *)hw_stats) +
2974 rte_i40e_txq_prio_strings[i].offset +
2975 (sizeof(uint64_t) * prio));
2976 xstats[count].id = count;
2985 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2986 __rte_unused uint16_t queue_id,
2987 __rte_unused uint8_t stat_idx,
2988 __rte_unused uint8_t is_rx)
2990 PMD_INIT_FUNC_TRACE();
2996 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2998 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3004 full_ver = hw->nvm.oem_ver;
3005 ver = (u8)(full_ver >> 24);
3006 build = (u16)((full_ver >> 8) & 0xffff);
3007 patch = (u8)(full_ver & 0xff);
3009 ret = snprintf(fw_version, fw_size,
3010 "%d.%d%d 0x%08x %d.%d.%d",
3011 ((hw->nvm.version >> 12) & 0xf),
3012 ((hw->nvm.version >> 4) & 0xff),
3013 (hw->nvm.version & 0xf), hw->nvm.eetrack,
3016 ret += 1; /* add the size of '\0' */
3017 if (fw_size < (u32)ret)
3024 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3026 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3027 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3028 struct i40e_vsi *vsi = pf->main_vsi;
3029 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3031 dev_info->pci_dev = pci_dev;
3032 dev_info->max_rx_queues = vsi->nb_qps;
3033 dev_info->max_tx_queues = vsi->nb_qps;
3034 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3035 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3036 dev_info->max_mac_addrs = vsi->max_macaddrs;
3037 dev_info->max_vfs = pci_dev->max_vfs;
3038 dev_info->rx_offload_capa =
3039 DEV_RX_OFFLOAD_VLAN_STRIP |
3040 DEV_RX_OFFLOAD_QINQ_STRIP |
3041 DEV_RX_OFFLOAD_IPV4_CKSUM |
3042 DEV_RX_OFFLOAD_UDP_CKSUM |
3043 DEV_RX_OFFLOAD_TCP_CKSUM;
3044 dev_info->tx_offload_capa =
3045 DEV_TX_OFFLOAD_VLAN_INSERT |
3046 DEV_TX_OFFLOAD_QINQ_INSERT |
3047 DEV_TX_OFFLOAD_IPV4_CKSUM |
3048 DEV_TX_OFFLOAD_UDP_CKSUM |
3049 DEV_TX_OFFLOAD_TCP_CKSUM |
3050 DEV_TX_OFFLOAD_SCTP_CKSUM |
3051 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3052 DEV_TX_OFFLOAD_TCP_TSO |
3053 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3054 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3055 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3056 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
3057 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3059 dev_info->reta_size = pf->hash_lut_size;
3060 dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3062 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3064 .pthresh = I40E_DEFAULT_RX_PTHRESH,
3065 .hthresh = I40E_DEFAULT_RX_HTHRESH,
3066 .wthresh = I40E_DEFAULT_RX_WTHRESH,
3068 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3072 dev_info->default_txconf = (struct rte_eth_txconf) {
3074 .pthresh = I40E_DEFAULT_TX_PTHRESH,
3075 .hthresh = I40E_DEFAULT_TX_HTHRESH,
3076 .wthresh = I40E_DEFAULT_TX_WTHRESH,
3078 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3079 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3080 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3081 ETH_TXQ_FLAGS_NOOFFLOADS,
3084 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3085 .nb_max = I40E_MAX_RING_DESC,
3086 .nb_min = I40E_MIN_RING_DESC,
3087 .nb_align = I40E_ALIGN_RING_DESC,
3090 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3091 .nb_max = I40E_MAX_RING_DESC,
3092 .nb_min = I40E_MIN_RING_DESC,
3093 .nb_align = I40E_ALIGN_RING_DESC,
3094 .nb_seg_max = I40E_TX_MAX_SEG,
3095 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3098 if (pf->flags & I40E_FLAG_VMDQ) {
3099 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3100 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3101 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3102 pf->max_nb_vmdq_vsi;
3103 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3104 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3105 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3108 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
3110 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3111 else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
3113 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3116 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3120 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3122 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3123 struct i40e_vsi *vsi = pf->main_vsi;
3124 PMD_INIT_FUNC_TRACE();
3127 return i40e_vsi_add_vlan(vsi, vlan_id);
3129 return i40e_vsi_delete_vlan(vsi, vlan_id);
3133 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3134 enum rte_vlan_type vlan_type,
3135 uint16_t tpid, int qinq)
3137 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3140 uint16_t reg_id = 3;
3144 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3148 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3150 if (ret != I40E_SUCCESS) {
3152 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3157 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3160 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3161 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3162 if (reg_r == reg_w) {
3163 PMD_DRV_LOG(DEBUG, "No need to write");
3167 ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3169 if (ret != I40E_SUCCESS) {
3171 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3176 "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3183 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3184 enum rte_vlan_type vlan_type,
3187 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3188 int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
3191 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3192 vlan_type != ETH_VLAN_TYPE_OUTER) ||
3193 (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3195 "Unsupported vlan type.");
3198 /* 802.1ad frames ability is added in NVM API 1.7*/
3199 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3201 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3202 hw->first_tag = rte_cpu_to_le_16(tpid);
3203 else if (vlan_type == ETH_VLAN_TYPE_INNER)
3204 hw->second_tag = rte_cpu_to_le_16(tpid);
3206 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3207 hw->second_tag = rte_cpu_to_le_16(tpid);
3209 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3210 if (ret != I40E_SUCCESS) {
3212 "Set switch config failed aq_err: %d",
3213 hw->aq.asq_last_status);
3217 /* If NVM API < 1.7, keep the register setting */
3218 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3225 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3227 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3228 struct i40e_vsi *vsi = pf->main_vsi;
3230 if (mask & ETH_VLAN_FILTER_MASK) {
3231 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3232 i40e_vsi_config_vlan_filter(vsi, TRUE);
3234 i40e_vsi_config_vlan_filter(vsi, FALSE);
3237 if (mask & ETH_VLAN_STRIP_MASK) {
3238 /* Enable or disable VLAN stripping */
3239 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3240 i40e_vsi_config_vlan_stripping(vsi, TRUE);
3242 i40e_vsi_config_vlan_stripping(vsi, FALSE);
3245 if (mask & ETH_VLAN_EXTEND_MASK) {
3246 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3247 i40e_vsi_config_double_vlan(vsi, TRUE);
3248 /* Set global registers with default ethertype. */
3249 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3251 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3255 i40e_vsi_config_double_vlan(vsi, FALSE);
3260 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3261 __rte_unused uint16_t queue,
3262 __rte_unused int on)
3264 PMD_INIT_FUNC_TRACE();
3268 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3270 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3271 struct i40e_vsi *vsi = pf->main_vsi;
3272 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3273 struct i40e_vsi_vlan_pvid_info info;
3275 memset(&info, 0, sizeof(info));
3278 info.config.pvid = pvid;
3280 info.config.reject.tagged =
3281 data->dev_conf.txmode.hw_vlan_reject_tagged;
3282 info.config.reject.untagged =
3283 data->dev_conf.txmode.hw_vlan_reject_untagged;
3286 return i40e_vsi_vlan_pvid_set(vsi, &info);
3290 i40e_dev_led_on(struct rte_eth_dev *dev)
3292 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3293 uint32_t mode = i40e_led_get(hw);
3296 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3302 i40e_dev_led_off(struct rte_eth_dev *dev)
3304 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3305 uint32_t mode = i40e_led_get(hw);
3308 i40e_led_set(hw, 0, false);
3314 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3316 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3317 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3319 fc_conf->pause_time = pf->fc_conf.pause_time;
3321 /* read out from register, in case they are modified by other port */
3322 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3323 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3324 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3325 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3327 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3328 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3330 /* Return current mode according to actual setting*/
3331 switch (hw->fc.current_mode) {
3333 fc_conf->mode = RTE_FC_FULL;
3335 case I40E_FC_TX_PAUSE:
3336 fc_conf->mode = RTE_FC_TX_PAUSE;
3338 case I40E_FC_RX_PAUSE:
3339 fc_conf->mode = RTE_FC_RX_PAUSE;
3343 fc_conf->mode = RTE_FC_NONE;
3350 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3352 uint32_t mflcn_reg, fctrl_reg, reg;
3353 uint32_t max_high_water;
3354 uint8_t i, aq_failure;
3358 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3359 [RTE_FC_NONE] = I40E_FC_NONE,
3360 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3361 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3362 [RTE_FC_FULL] = I40E_FC_FULL
3365 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3367 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3368 if ((fc_conf->high_water > max_high_water) ||
3369 (fc_conf->high_water < fc_conf->low_water)) {
3371 "Invalid high/low water setup value in KB, High_water must be <= %d.",
3376 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3377 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3378 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3380 pf->fc_conf.pause_time = fc_conf->pause_time;
3381 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3382 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3384 PMD_INIT_FUNC_TRACE();
3386 /* All the link flow control related enable/disable register
3387 * configuration is handle by the F/W
3389 err = i40e_set_fc(hw, &aq_failure, true);
3393 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3394 /* Configure flow control refresh threshold,
3395 * the value for stat_tx_pause_refresh_timer[8]
3396 * is used for global pause operation.
3400 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3401 pf->fc_conf.pause_time);
3403 /* configure the timer value included in transmitted pause
3405 * the value for stat_tx_pause_quanta[8] is used for global
3408 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3409 pf->fc_conf.pause_time);
3411 fctrl_reg = I40E_READ_REG(hw,
3412 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3414 if (fc_conf->mac_ctrl_frame_fwd != 0)
3415 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3417 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3419 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3422 /* Configure pause time (2 TCs per register) */
3423 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3424 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3425 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3427 /* Configure flow control refresh threshold value */
3428 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3429 pf->fc_conf.pause_time / 2);
3431 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3433 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3434 *depending on configuration
3436 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3437 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3438 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3440 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3441 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3444 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3447 /* config the water marker both based on the packets and bytes */
3448 I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3449 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3450 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3451 I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3452 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3453 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3454 I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3455 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3457 I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3458 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3461 I40E_WRITE_FLUSH(hw);
3467 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3468 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3470 PMD_INIT_FUNC_TRACE();
3475 /* Add a MAC address, and update filters */
3477 i40e_macaddr_add(struct rte_eth_dev *dev,
3478 struct ether_addr *mac_addr,
3479 __rte_unused uint32_t index,
3482 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3483 struct i40e_mac_filter_info mac_filter;
3484 struct i40e_vsi *vsi;
3487 /* If VMDQ not enabled or configured, return */
3488 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3489 !pf->nb_cfg_vmdq_vsi)) {
3490 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3491 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3496 if (pool > pf->nb_cfg_vmdq_vsi) {
3497 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3498 pool, pf->nb_cfg_vmdq_vsi);
3502 rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3503 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3504 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3506 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3511 vsi = pf->vmdq[pool - 1].vsi;
3513 ret = i40e_vsi_add_mac(vsi, &mac_filter);
3514 if (ret != I40E_SUCCESS) {
3515 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3521 /* Remove a MAC address, and update filters */
3523 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3525 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3526 struct i40e_vsi *vsi;
3527 struct rte_eth_dev_data *data = dev->data;
3528 struct ether_addr *macaddr;
3533 macaddr = &(data->mac_addrs[index]);
3535 pool_sel = dev->data->mac_pool_sel[index];
3537 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3538 if (pool_sel & (1ULL << i)) {
3542 /* No VMDQ pool enabled or configured */
3543 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3544 (i > pf->nb_cfg_vmdq_vsi)) {
3546 "No VMDQ pool enabled/configured");
3549 vsi = pf->vmdq[i - 1].vsi;
3551 ret = i40e_vsi_delete_mac(vsi, macaddr);
3554 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3561 /* Set perfect match or hash match of MAC and VLAN for a VF */
3563 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3564 struct rte_eth_mac_filter *filter,
3568 struct i40e_mac_filter_info mac_filter;
3569 struct ether_addr old_mac;
3570 struct ether_addr *new_mac;
3571 struct i40e_pf_vf *vf = NULL;
3576 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3579 hw = I40E_PF_TO_HW(pf);
3581 if (filter == NULL) {
3582 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3586 new_mac = &filter->mac_addr;
3588 if (is_zero_ether_addr(new_mac)) {
3589 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3593 vf_id = filter->dst_id;
3595 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3596 PMD_DRV_LOG(ERR, "Invalid argument.");
3599 vf = &pf->vfs[vf_id];
3601 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3602 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3607 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3608 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3610 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3613 mac_filter.filter_type = filter->filter_type;
3614 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3615 if (ret != I40E_SUCCESS) {
3616 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3619 ether_addr_copy(new_mac, &pf->dev_addr);
3621 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3623 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3624 if (ret != I40E_SUCCESS) {
3625 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3629 /* Clear device address as it has been removed */
3630 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3631 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3637 /* MAC filter handle */
3639 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3642 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3643 struct rte_eth_mac_filter *filter;
3644 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3645 int ret = I40E_NOT_SUPPORTED;
3647 filter = (struct rte_eth_mac_filter *)(arg);
3649 switch (filter_op) {
3650 case RTE_ETH_FILTER_NOP:
3653 case RTE_ETH_FILTER_ADD:
3654 i40e_pf_disable_irq0(hw);
3656 ret = i40e_vf_mac_filter_set(pf, filter, 1);
3657 i40e_pf_enable_irq0(hw);
3659 case RTE_ETH_FILTER_DELETE:
3660 i40e_pf_disable_irq0(hw);
3662 ret = i40e_vf_mac_filter_set(pf, filter, 0);
3663 i40e_pf_enable_irq0(hw);
3666 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3667 ret = I40E_ERR_PARAM;
3675 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3677 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3678 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3684 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3685 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3688 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3692 uint32_t *lut_dw = (uint32_t *)lut;
3693 uint16_t i, lut_size_dw = lut_size / 4;
3695 for (i = 0; i < lut_size_dw; i++)
3696 lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3703 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3712 pf = I40E_VSI_TO_PF(vsi);
3713 hw = I40E_VSI_TO_HW(vsi);
3715 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3716 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3719 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3723 uint32_t *lut_dw = (uint32_t *)lut;
3724 uint16_t i, lut_size_dw = lut_size / 4;
3726 for (i = 0; i < lut_size_dw; i++)
3727 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3728 I40E_WRITE_FLUSH(hw);
3735 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3736 struct rte_eth_rss_reta_entry64 *reta_conf,
3739 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3740 uint16_t i, lut_size = pf->hash_lut_size;
3741 uint16_t idx, shift;
3745 if (reta_size != lut_size ||
3746 reta_size > ETH_RSS_RETA_SIZE_512) {
3748 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3749 reta_size, lut_size);
3753 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3755 PMD_DRV_LOG(ERR, "No memory can be allocated");
3758 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3761 for (i = 0; i < reta_size; i++) {
3762 idx = i / RTE_RETA_GROUP_SIZE;
3763 shift = i % RTE_RETA_GROUP_SIZE;
3764 if (reta_conf[idx].mask & (1ULL << shift))
3765 lut[i] = reta_conf[idx].reta[shift];
3767 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3776 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3777 struct rte_eth_rss_reta_entry64 *reta_conf,
3780 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3781 uint16_t i, lut_size = pf->hash_lut_size;
3782 uint16_t idx, shift;
3786 if (reta_size != lut_size ||
3787 reta_size > ETH_RSS_RETA_SIZE_512) {
3789 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3790 reta_size, lut_size);
3794 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3796 PMD_DRV_LOG(ERR, "No memory can be allocated");
3800 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3803 for (i = 0; i < reta_size; i++) {
3804 idx = i / RTE_RETA_GROUP_SIZE;
3805 shift = i % RTE_RETA_GROUP_SIZE;
3806 if (reta_conf[idx].mask & (1ULL << shift))
3807 reta_conf[idx].reta[shift] = lut[i];
3817 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3818 * @hw: pointer to the HW structure
3819 * @mem: pointer to mem struct to fill out
3820 * @size: size of memory requested
3821 * @alignment: what to align the allocation to
3823 enum i40e_status_code
3824 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3825 struct i40e_dma_mem *mem,
3829 const struct rte_memzone *mz = NULL;
3830 char z_name[RTE_MEMZONE_NAMESIZE];
3833 return I40E_ERR_PARAM;
3835 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3836 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3837 alignment, RTE_PGSIZE_2M);
3839 return I40E_ERR_NO_MEMORY;
3843 mem->pa = mz->phys_addr;
3844 mem->zone = (const void *)mz;
3846 "memzone %s allocated with physical address: %"PRIu64,
3849 return I40E_SUCCESS;
3853 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3854 * @hw: pointer to the HW structure
3855 * @mem: ptr to mem struct to free
3857 enum i40e_status_code
3858 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3859 struct i40e_dma_mem *mem)
3862 return I40E_ERR_PARAM;
3865 "memzone %s to be freed with physical address: %"PRIu64,
3866 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3867 rte_memzone_free((const struct rte_memzone *)mem->zone);
3872 return I40E_SUCCESS;
3876 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3877 * @hw: pointer to the HW structure
3878 * @mem: pointer to mem struct to fill out
3879 * @size: size of memory requested
3881 enum i40e_status_code
3882 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3883 struct i40e_virt_mem *mem,
3887 return I40E_ERR_PARAM;
3890 mem->va = rte_zmalloc("i40e", size, 0);
3893 return I40E_SUCCESS;
3895 return I40E_ERR_NO_MEMORY;
3899 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3900 * @hw: pointer to the HW structure
3901 * @mem: pointer to mem struct to free
3903 enum i40e_status_code
3904 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3905 struct i40e_virt_mem *mem)
3908 return I40E_ERR_PARAM;
3913 return I40E_SUCCESS;
3917 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3919 rte_spinlock_init(&sp->spinlock);
3923 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3925 rte_spinlock_lock(&sp->spinlock);
3929 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3931 rte_spinlock_unlock(&sp->spinlock);
3935 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3941 * Get the hardware capabilities, which will be parsed
3942 * and saved into struct i40e_hw.
3945 i40e_get_cap(struct i40e_hw *hw)
3947 struct i40e_aqc_list_capabilities_element_resp *buf;
3948 uint16_t len, size = 0;
3951 /* Calculate a huge enough buff for saving response data temporarily */
3952 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3953 I40E_MAX_CAP_ELE_NUM;
3954 buf = rte_zmalloc("i40e", len, 0);
3956 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3957 return I40E_ERR_NO_MEMORY;
3960 /* Get, parse the capabilities and save it to hw */
3961 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3962 i40e_aqc_opc_list_func_capabilities, NULL);
3963 if (ret != I40E_SUCCESS)
3964 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3966 /* Free the temporary buffer after being used */
3973 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3975 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3976 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3977 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3978 uint16_t qp_count = 0, vsi_count = 0;
3980 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3981 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3984 /* Add the parameter init for LFC */
3985 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3986 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3987 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3989 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3990 pf->max_num_vsi = hw->func_caps.num_vsis;
3991 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3992 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3993 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3995 /* FDir queue/VSI allocation */
3996 pf->fdir_qp_offset = 0;
3997 if (hw->func_caps.fd) {
3998 pf->flags |= I40E_FLAG_FDIR;
3999 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4001 pf->fdir_nb_qps = 0;
4003 qp_count += pf->fdir_nb_qps;
4006 /* LAN queue/VSI allocation */
4007 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4008 if (!hw->func_caps.rss) {
4011 pf->flags |= I40E_FLAG_RSS;
4012 if (hw->mac.type == I40E_MAC_X722)
4013 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4014 pf->lan_nb_qps = pf->lan_nb_qp_max;
4016 qp_count += pf->lan_nb_qps;
4019 /* VF queue/VSI allocation */
4020 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4021 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4022 pf->flags |= I40E_FLAG_SRIOV;
4023 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4024 pf->vf_num = pci_dev->max_vfs;
4026 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4027 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4032 qp_count += pf->vf_nb_qps * pf->vf_num;
4033 vsi_count += pf->vf_num;
4035 /* VMDq queue/VSI allocation */
4036 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4037 pf->vmdq_nb_qps = 0;
4038 pf->max_nb_vmdq_vsi = 0;
4039 if (hw->func_caps.vmdq) {
4040 if (qp_count < hw->func_caps.num_tx_qp &&
4041 vsi_count < hw->func_caps.num_vsis) {
4042 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4043 qp_count) / pf->vmdq_nb_qp_max;
4045 /* Limit the maximum number of VMDq vsi to the maximum
4046 * ethdev can support
4048 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4049 hw->func_caps.num_vsis - vsi_count);
4050 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4052 if (pf->max_nb_vmdq_vsi) {
4053 pf->flags |= I40E_FLAG_VMDQ;
4054 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4056 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4057 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4058 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4061 "No enough queues left for VMDq");
4064 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4067 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4068 vsi_count += pf->max_nb_vmdq_vsi;
4070 if (hw->func_caps.dcb)
4071 pf->flags |= I40E_FLAG_DCB;
4073 if (qp_count > hw->func_caps.num_tx_qp) {
4075 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4076 qp_count, hw->func_caps.num_tx_qp);
4079 if (vsi_count > hw->func_caps.num_vsis) {
4081 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4082 vsi_count, hw->func_caps.num_vsis);
4090 i40e_pf_get_switch_config(struct i40e_pf *pf)
4092 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4093 struct i40e_aqc_get_switch_config_resp *switch_config;
4094 struct i40e_aqc_switch_config_element_resp *element;
4095 uint16_t start_seid = 0, num_reported;
4098 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4099 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4100 if (!switch_config) {
4101 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4105 /* Get the switch configurations */
4106 ret = i40e_aq_get_switch_config(hw, switch_config,
4107 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4108 if (ret != I40E_SUCCESS) {
4109 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4112 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4113 if (num_reported != 1) { /* The number should be 1 */
4114 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4118 /* Parse the switch configuration elements */
4119 element = &(switch_config->element[0]);
4120 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4121 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4122 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4124 PMD_DRV_LOG(INFO, "Unknown element type");
4127 rte_free(switch_config);
4133 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4136 struct pool_entry *entry;
4138 if (pool == NULL || num == 0)
4141 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4142 if (entry == NULL) {
4143 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4147 /* queue heap initialize */
4148 pool->num_free = num;
4149 pool->num_alloc = 0;
4151 LIST_INIT(&pool->alloc_list);
4152 LIST_INIT(&pool->free_list);
4154 /* Initialize element */
4158 LIST_INSERT_HEAD(&pool->free_list, entry, next);
4163 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4165 struct pool_entry *entry, *next_entry;
4170 for (entry = LIST_FIRST(&pool->alloc_list);
4171 entry && (next_entry = LIST_NEXT(entry, next), 1);
4172 entry = next_entry) {
4173 LIST_REMOVE(entry, next);
4177 for (entry = LIST_FIRST(&pool->free_list);
4178 entry && (next_entry = LIST_NEXT(entry, next), 1);
4179 entry = next_entry) {
4180 LIST_REMOVE(entry, next);
4185 pool->num_alloc = 0;
4187 LIST_INIT(&pool->alloc_list);
4188 LIST_INIT(&pool->free_list);
4192 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4195 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4196 uint32_t pool_offset;
4200 PMD_DRV_LOG(ERR, "Invalid parameter");
4204 pool_offset = base - pool->base;
4205 /* Lookup in alloc list */
4206 LIST_FOREACH(entry, &pool->alloc_list, next) {
4207 if (entry->base == pool_offset) {
4208 valid_entry = entry;
4209 LIST_REMOVE(entry, next);
4214 /* Not find, return */
4215 if (valid_entry == NULL) {
4216 PMD_DRV_LOG(ERR, "Failed to find entry");
4221 * Found it, move it to free list and try to merge.
4222 * In order to make merge easier, always sort it by qbase.
4223 * Find adjacent prev and last entries.
4226 LIST_FOREACH(entry, &pool->free_list, next) {
4227 if (entry->base > valid_entry->base) {
4235 /* Try to merge with next one*/
4237 /* Merge with next one */
4238 if (valid_entry->base + valid_entry->len == next->base) {
4239 next->base = valid_entry->base;
4240 next->len += valid_entry->len;
4241 rte_free(valid_entry);
4248 /* Merge with previous one */
4249 if (prev->base + prev->len == valid_entry->base) {
4250 prev->len += valid_entry->len;
4251 /* If it merge with next one, remove next node */
4253 LIST_REMOVE(valid_entry, next);
4254 rte_free(valid_entry);
4256 rte_free(valid_entry);
4262 /* Not find any entry to merge, insert */
4265 LIST_INSERT_AFTER(prev, valid_entry, next);
4266 else if (next != NULL)
4267 LIST_INSERT_BEFORE(next, valid_entry, next);
4268 else /* It's empty list, insert to head */
4269 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4272 pool->num_free += valid_entry->len;
4273 pool->num_alloc -= valid_entry->len;
4279 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4282 struct pool_entry *entry, *valid_entry;
4284 if (pool == NULL || num == 0) {
4285 PMD_DRV_LOG(ERR, "Invalid parameter");
4289 if (pool->num_free < num) {
4290 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4291 num, pool->num_free);
4296 /* Lookup in free list and find most fit one */
4297 LIST_FOREACH(entry, &pool->free_list, next) {
4298 if (entry->len >= num) {
4300 if (entry->len == num) {
4301 valid_entry = entry;
4304 if (valid_entry == NULL || valid_entry->len > entry->len)
4305 valid_entry = entry;
4309 /* Not find one to satisfy the request, return */
4310 if (valid_entry == NULL) {
4311 PMD_DRV_LOG(ERR, "No valid entry found");
4315 * The entry have equal queue number as requested,
4316 * remove it from alloc_list.
4318 if (valid_entry->len == num) {
4319 LIST_REMOVE(valid_entry, next);
4322 * The entry have more numbers than requested,
4323 * create a new entry for alloc_list and minus its
4324 * queue base and number in free_list.
4326 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4327 if (entry == NULL) {
4329 "Failed to allocate memory for resource pool");
4332 entry->base = valid_entry->base;
4334 valid_entry->base += num;
4335 valid_entry->len -= num;
4336 valid_entry = entry;
4339 /* Insert it into alloc list, not sorted */
4340 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4342 pool->num_free -= valid_entry->len;
4343 pool->num_alloc += valid_entry->len;
4345 return valid_entry->base + pool->base;
4349 * bitmap_is_subset - Check whether src2 is subset of src1
4352 bitmap_is_subset(uint8_t src1, uint8_t src2)
4354 return !((src1 ^ src2) & src2);
4357 static enum i40e_status_code
4358 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4360 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4362 /* If DCB is not supported, only default TC is supported */
4363 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4364 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4365 return I40E_NOT_SUPPORTED;
4368 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4370 "Enabled TC map 0x%x not applicable to HW support 0x%x",
4371 hw->func_caps.enabled_tcmap, enabled_tcmap);
4372 return I40E_NOT_SUPPORTED;
4374 return I40E_SUCCESS;
4378 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4379 struct i40e_vsi_vlan_pvid_info *info)
4382 struct i40e_vsi_context ctxt;
4383 uint8_t vlan_flags = 0;
4386 if (vsi == NULL || info == NULL) {
4387 PMD_DRV_LOG(ERR, "invalid parameters");
4388 return I40E_ERR_PARAM;
4392 vsi->info.pvid = info->config.pvid;
4394 * If insert pvid is enabled, only tagged pkts are
4395 * allowed to be sent out.
4397 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4398 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4401 if (info->config.reject.tagged == 0)
4402 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4404 if (info->config.reject.untagged == 0)
4405 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4407 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4408 I40E_AQ_VSI_PVLAN_MODE_MASK);
4409 vsi->info.port_vlan_flags |= vlan_flags;
4410 vsi->info.valid_sections =
4411 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4412 memset(&ctxt, 0, sizeof(ctxt));
4413 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4414 ctxt.seid = vsi->seid;
4416 hw = I40E_VSI_TO_HW(vsi);
4417 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4418 if (ret != I40E_SUCCESS)
4419 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4425 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4427 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4429 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4431 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4432 if (ret != I40E_SUCCESS)
4436 PMD_DRV_LOG(ERR, "seid not valid");
4440 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4441 tc_bw_data.tc_valid_bits = enabled_tcmap;
4442 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4443 tc_bw_data.tc_bw_credits[i] =
4444 (enabled_tcmap & (1 << i)) ? 1 : 0;
4446 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4447 if (ret != I40E_SUCCESS) {
4448 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4452 rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4453 sizeof(vsi->info.qs_handle));
4454 return I40E_SUCCESS;
4457 static enum i40e_status_code
4458 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4459 struct i40e_aqc_vsi_properties_data *info,
4460 uint8_t enabled_tcmap)
4462 enum i40e_status_code ret;
4463 int i, total_tc = 0;
4464 uint16_t qpnum_per_tc, bsf, qp_idx;
4466 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4467 if (ret != I40E_SUCCESS)
4470 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4471 if (enabled_tcmap & (1 << i))
4475 vsi->enabled_tc = enabled_tcmap;
4477 /* Number of queues per enabled TC */
4478 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4479 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4480 bsf = rte_bsf32(qpnum_per_tc);
4482 /* Adjust the queue number to actual queues that can be applied */
4483 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4484 vsi->nb_qps = qpnum_per_tc * total_tc;
4487 * Configure TC and queue mapping parameters, for enabled TC,
4488 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4489 * default queue will serve it.
4492 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4493 if (vsi->enabled_tc & (1 << i)) {
4494 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4495 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4496 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4497 qp_idx += qpnum_per_tc;
4499 info->tc_mapping[i] = 0;
4502 /* Associate queue number with VSI */
4503 if (vsi->type == I40E_VSI_SRIOV) {
4504 info->mapping_flags |=
4505 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4506 for (i = 0; i < vsi->nb_qps; i++)
4507 info->queue_mapping[i] =
4508 rte_cpu_to_le_16(vsi->base_queue + i);
4510 info->mapping_flags |=
4511 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4512 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4514 info->valid_sections |=
4515 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4517 return I40E_SUCCESS;
4521 i40e_veb_release(struct i40e_veb *veb)
4523 struct i40e_vsi *vsi;
4529 if (!TAILQ_EMPTY(&veb->head)) {
4530 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4533 /* associate_vsi field is NULL for floating VEB */
4534 if (veb->associate_vsi != NULL) {
4535 vsi = veb->associate_vsi;
4536 hw = I40E_VSI_TO_HW(vsi);
4538 vsi->uplink_seid = veb->uplink_seid;
4541 veb->associate_pf->main_vsi->floating_veb = NULL;
4542 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4545 i40e_aq_delete_element(hw, veb->seid, NULL);
4547 return I40E_SUCCESS;
4551 static struct i40e_veb *
4552 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4554 struct i40e_veb *veb;
4560 "veb setup failed, associated PF shouldn't null");
4563 hw = I40E_PF_TO_HW(pf);
4565 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4567 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4571 veb->associate_vsi = vsi;
4572 veb->associate_pf = pf;
4573 TAILQ_INIT(&veb->head);
4574 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4576 /* create floating veb if vsi is NULL */
4578 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4579 I40E_DEFAULT_TCMAP, false,
4580 &veb->seid, false, NULL);
4582 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4583 true, &veb->seid, false, NULL);
4586 if (ret != I40E_SUCCESS) {
4587 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4588 hw->aq.asq_last_status);
4591 veb->enabled_tc = I40E_DEFAULT_TCMAP;
4593 /* get statistics index */
4594 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4595 &veb->stats_idx, NULL, NULL, NULL);
4596 if (ret != I40E_SUCCESS) {
4597 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4598 hw->aq.asq_last_status);
4601 /* Get VEB bandwidth, to be implemented */
4602 /* Now associated vsi binding to the VEB, set uplink to this VEB */
4604 vsi->uplink_seid = veb->seid;
4613 i40e_vsi_release(struct i40e_vsi *vsi)
4617 struct i40e_vsi_list *vsi_list;
4620 struct i40e_mac_filter *f;
4621 uint16_t user_param;
4624 return I40E_SUCCESS;
4629 user_param = vsi->user_param;
4631 pf = I40E_VSI_TO_PF(vsi);
4632 hw = I40E_VSI_TO_HW(vsi);
4634 /* VSI has child to attach, release child first */
4636 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4637 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4640 i40e_veb_release(vsi->veb);
4643 if (vsi->floating_veb) {
4644 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4645 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4650 /* Remove all macvlan filters of the VSI */
4651 i40e_vsi_remove_all_macvlan_filter(vsi);
4652 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4655 if (vsi->type != I40E_VSI_MAIN &&
4656 ((vsi->type != I40E_VSI_SRIOV) ||
4657 !pf->floating_veb_list[user_param])) {
4658 /* Remove vsi from parent's sibling list */
4659 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4660 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4661 return I40E_ERR_PARAM;
4663 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4664 &vsi->sib_vsi_list, list);
4666 /* Remove all switch element of the VSI */
4667 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4668 if (ret != I40E_SUCCESS)
4669 PMD_DRV_LOG(ERR, "Failed to delete element");
4672 if ((vsi->type == I40E_VSI_SRIOV) &&
4673 pf->floating_veb_list[user_param]) {
4674 /* Remove vsi from parent's sibling list */
4675 if (vsi->parent_vsi == NULL ||
4676 vsi->parent_vsi->floating_veb == NULL) {
4677 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4678 return I40E_ERR_PARAM;
4680 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4681 &vsi->sib_vsi_list, list);
4683 /* Remove all switch element of the VSI */
4684 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4685 if (ret != I40E_SUCCESS)
4686 PMD_DRV_LOG(ERR, "Failed to delete element");
4689 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4691 if (vsi->type != I40E_VSI_SRIOV)
4692 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4695 return I40E_SUCCESS;
4699 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4701 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4702 struct i40e_aqc_remove_macvlan_element_data def_filter;
4703 struct i40e_mac_filter_info filter;
4706 if (vsi->type != I40E_VSI_MAIN)
4707 return I40E_ERR_CONFIG;
4708 memset(&def_filter, 0, sizeof(def_filter));
4709 rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4711 def_filter.vlan_tag = 0;
4712 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4713 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4714 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4715 if (ret != I40E_SUCCESS) {
4716 struct i40e_mac_filter *f;
4717 struct ether_addr *mac;
4720 "Cannot remove the default macvlan filter");
4721 /* It needs to add the permanent mac into mac list */
4722 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4724 PMD_DRV_LOG(ERR, "failed to allocate memory");
4725 return I40E_ERR_NO_MEMORY;
4727 mac = &f->mac_info.mac_addr;
4728 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4730 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4731 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4736 rte_memcpy(&filter.mac_addr,
4737 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4738 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4739 return i40e_vsi_add_mac(vsi, &filter);
4743 * i40e_vsi_get_bw_config - Query VSI BW Information
4744 * @vsi: the VSI to be queried
4746 * Returns 0 on success, negative value on failure
4748 static enum i40e_status_code
4749 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4751 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4752 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4753 struct i40e_hw *hw = &vsi->adapter->hw;
4758 memset(&bw_config, 0, sizeof(bw_config));
4759 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4760 if (ret != I40E_SUCCESS) {
4761 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4762 hw->aq.asq_last_status);
4766 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4767 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4768 &ets_sla_config, NULL);
4769 if (ret != I40E_SUCCESS) {
4771 "VSI failed to get TC bandwdith configuration %u",
4772 hw->aq.asq_last_status);
4776 /* store and print out BW info */
4777 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4778 vsi->bw_info.bw_max = bw_config.max_bw;
4779 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4780 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4781 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4782 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4784 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4785 vsi->bw_info.bw_ets_share_credits[i] =
4786 ets_sla_config.share_credits[i];
4787 vsi->bw_info.bw_ets_credits[i] =
4788 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4789 /* 4 bits per TC, 4th bit is reserved */
4790 vsi->bw_info.bw_ets_max[i] =
4791 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4792 RTE_LEN2MASK(3, uint8_t));
4793 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4794 vsi->bw_info.bw_ets_share_credits[i]);
4795 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4796 vsi->bw_info.bw_ets_credits[i]);
4797 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4798 vsi->bw_info.bw_ets_max[i]);
4801 return I40E_SUCCESS;
4804 /* i40e_enable_pf_lb
4805 * @pf: pointer to the pf structure
4807 * allow loopback on pf
4810 i40e_enable_pf_lb(struct i40e_pf *pf)
4812 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4813 struct i40e_vsi_context ctxt;
4816 /* Use the FW API if FW >= v5.0 */
4817 if (hw->aq.fw_maj_ver < 5) {
4818 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4822 memset(&ctxt, 0, sizeof(ctxt));
4823 ctxt.seid = pf->main_vsi_seid;
4824 ctxt.pf_num = hw->pf_id;
4825 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4827 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4828 ret, hw->aq.asq_last_status);
4831 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4832 ctxt.info.valid_sections =
4833 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4834 ctxt.info.switch_id |=
4835 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4837 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4839 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4840 hw->aq.asq_last_status);
4845 i40e_vsi_setup(struct i40e_pf *pf,
4846 enum i40e_vsi_type type,
4847 struct i40e_vsi *uplink_vsi,
4848 uint16_t user_param)
4850 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4851 struct i40e_vsi *vsi;
4852 struct i40e_mac_filter_info filter;
4854 struct i40e_vsi_context ctxt;
4855 struct ether_addr broadcast =
4856 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4858 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4859 uplink_vsi == NULL) {
4861 "VSI setup failed, VSI link shouldn't be NULL");
4865 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4867 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4872 * 1.type is not MAIN and uplink vsi is not NULL
4873 * If uplink vsi didn't setup VEB, create one first under veb field
4874 * 2.type is SRIOV and the uplink is NULL
4875 * If floating VEB is NULL, create one veb under floating veb field
4878 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4879 uplink_vsi->veb == NULL) {
4880 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4882 if (uplink_vsi->veb == NULL) {
4883 PMD_DRV_LOG(ERR, "VEB setup failed");
4886 /* set ALLOWLOOPBACk on pf, when veb is created */
4887 i40e_enable_pf_lb(pf);
4890 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4891 pf->main_vsi->floating_veb == NULL) {
4892 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4894 if (pf->main_vsi->floating_veb == NULL) {
4895 PMD_DRV_LOG(ERR, "VEB setup failed");
4900 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4902 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4905 TAILQ_INIT(&vsi->mac_list);
4907 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4908 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4909 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4910 vsi->user_param = user_param;
4911 vsi->vlan_anti_spoof_on = 0;
4912 vsi->vlan_filter_on = 0;
4913 /* Allocate queues */
4914 switch (vsi->type) {
4915 case I40E_VSI_MAIN :
4916 vsi->nb_qps = pf->lan_nb_qps;
4918 case I40E_VSI_SRIOV :
4919 vsi->nb_qps = pf->vf_nb_qps;
4921 case I40E_VSI_VMDQ2:
4922 vsi->nb_qps = pf->vmdq_nb_qps;
4925 vsi->nb_qps = pf->fdir_nb_qps;
4931 * The filter status descriptor is reported in rx queue 0,
4932 * while the tx queue for fdir filter programming has no
4933 * such constraints, can be non-zero queues.
4934 * To simplify it, choose FDIR vsi use queue 0 pair.
4935 * To make sure it will use queue 0 pair, queue allocation
4936 * need be done before this function is called
4938 if (type != I40E_VSI_FDIR) {
4939 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4941 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4945 vsi->base_queue = ret;
4947 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4949 /* VF has MSIX interrupt in VF range, don't allocate here */
4950 if (type == I40E_VSI_MAIN) {
4951 ret = i40e_res_pool_alloc(&pf->msix_pool,
4952 RTE_MIN(vsi->nb_qps,
4953 RTE_MAX_RXTX_INTR_VEC_ID));
4955 PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4957 goto fail_queue_alloc;
4959 vsi->msix_intr = ret;
4960 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4961 } else if (type != I40E_VSI_SRIOV) {
4962 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4964 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4965 goto fail_queue_alloc;
4967 vsi->msix_intr = ret;
4975 if (type == I40E_VSI_MAIN) {
4976 /* For main VSI, no need to add since it's default one */
4977 vsi->uplink_seid = pf->mac_seid;
4978 vsi->seid = pf->main_vsi_seid;
4979 /* Bind queues with specific MSIX interrupt */
4981 * Needs 2 interrupt at least, one for misc cause which will
4982 * enabled from OS side, Another for queues binding the
4983 * interrupt from device side only.
4986 /* Get default VSI parameters from hardware */
4987 memset(&ctxt, 0, sizeof(ctxt));
4988 ctxt.seid = vsi->seid;
4989 ctxt.pf_num = hw->pf_id;
4990 ctxt.uplink_seid = vsi->uplink_seid;
4992 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4993 if (ret != I40E_SUCCESS) {
4994 PMD_DRV_LOG(ERR, "Failed to get VSI params");
4995 goto fail_msix_alloc;
4997 rte_memcpy(&vsi->info, &ctxt.info,
4998 sizeof(struct i40e_aqc_vsi_properties_data));
4999 vsi->vsi_id = ctxt.vsi_number;
5000 vsi->info.valid_sections = 0;
5002 /* Configure tc, enabled TC0 only */
5003 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5005 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5006 goto fail_msix_alloc;
5009 /* TC, queue mapping */
5010 memset(&ctxt, 0, sizeof(ctxt));
5011 vsi->info.valid_sections |=
5012 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5013 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5014 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5015 rte_memcpy(&ctxt.info, &vsi->info,
5016 sizeof(struct i40e_aqc_vsi_properties_data));
5017 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5018 I40E_DEFAULT_TCMAP);
5019 if (ret != I40E_SUCCESS) {
5021 "Failed to configure TC queue mapping");
5022 goto fail_msix_alloc;
5024 ctxt.seid = vsi->seid;
5025 ctxt.pf_num = hw->pf_id;
5026 ctxt.uplink_seid = vsi->uplink_seid;
5029 /* Update VSI parameters */
5030 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5031 if (ret != I40E_SUCCESS) {
5032 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5033 goto fail_msix_alloc;
5036 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5037 sizeof(vsi->info.tc_mapping));
5038 rte_memcpy(&vsi->info.queue_mapping,
5039 &ctxt.info.queue_mapping,
5040 sizeof(vsi->info.queue_mapping));
5041 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5042 vsi->info.valid_sections = 0;
5044 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5048 * Updating default filter settings are necessary to prevent
5049 * reception of tagged packets.
5050 * Some old firmware configurations load a default macvlan
5051 * filter which accepts both tagged and untagged packets.
5052 * The updating is to use a normal filter instead if needed.
5053 * For NVM 4.2.2 or after, the updating is not needed anymore.
5054 * The firmware with correct configurations load the default
5055 * macvlan filter which is expected and cannot be removed.
5057 i40e_update_default_filter_setting(vsi);
5058 i40e_config_qinq(hw, vsi);
5059 } else if (type == I40E_VSI_SRIOV) {
5060 memset(&ctxt, 0, sizeof(ctxt));
5062 * For other VSI, the uplink_seid equals to uplink VSI's
5063 * uplink_seid since they share same VEB
5065 if (uplink_vsi == NULL)
5066 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5068 vsi->uplink_seid = uplink_vsi->uplink_seid;
5069 ctxt.pf_num = hw->pf_id;
5070 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5071 ctxt.uplink_seid = vsi->uplink_seid;
5072 ctxt.connection_type = 0x1;
5073 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5075 /* Use the VEB configuration if FW >= v5.0 */
5076 if (hw->aq.fw_maj_ver >= 5) {
5077 /* Configure switch ID */
5078 ctxt.info.valid_sections |=
5079 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5080 ctxt.info.switch_id =
5081 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5084 /* Configure port/vlan */
5085 ctxt.info.valid_sections |=
5086 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5087 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5088 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5089 hw->func_caps.enabled_tcmap);
5090 if (ret != I40E_SUCCESS) {
5092 "Failed to configure TC queue mapping");
5093 goto fail_msix_alloc;
5096 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5097 ctxt.info.valid_sections |=
5098 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5100 * Since VSI is not created yet, only configure parameter,
5101 * will add vsi below.
5104 i40e_config_qinq(hw, vsi);
5105 } else if (type == I40E_VSI_VMDQ2) {
5106 memset(&ctxt, 0, sizeof(ctxt));
5108 * For other VSI, the uplink_seid equals to uplink VSI's
5109 * uplink_seid since they share same VEB
5111 vsi->uplink_seid = uplink_vsi->uplink_seid;
5112 ctxt.pf_num = hw->pf_id;
5114 ctxt.uplink_seid = vsi->uplink_seid;
5115 ctxt.connection_type = 0x1;
5116 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5118 ctxt.info.valid_sections |=
5119 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5120 /* user_param carries flag to enable loop back */
5122 ctxt.info.switch_id =
5123 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5124 ctxt.info.switch_id |=
5125 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5128 /* Configure port/vlan */
5129 ctxt.info.valid_sections |=
5130 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5131 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5132 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5133 I40E_DEFAULT_TCMAP);
5134 if (ret != I40E_SUCCESS) {
5136 "Failed to configure TC queue mapping");
5137 goto fail_msix_alloc;
5139 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5140 ctxt.info.valid_sections |=
5141 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5142 } else if (type == I40E_VSI_FDIR) {
5143 memset(&ctxt, 0, sizeof(ctxt));
5144 vsi->uplink_seid = uplink_vsi->uplink_seid;
5145 ctxt.pf_num = hw->pf_id;
5147 ctxt.uplink_seid = vsi->uplink_seid;
5148 ctxt.connection_type = 0x1; /* regular data port */
5149 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5150 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5151 I40E_DEFAULT_TCMAP);
5152 if (ret != I40E_SUCCESS) {
5154 "Failed to configure TC queue mapping.");
5155 goto fail_msix_alloc;
5157 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5158 ctxt.info.valid_sections |=
5159 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5161 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5162 goto fail_msix_alloc;
5165 if (vsi->type != I40E_VSI_MAIN) {
5166 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5167 if (ret != I40E_SUCCESS) {
5168 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5169 hw->aq.asq_last_status);
5170 goto fail_msix_alloc;
5172 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5173 vsi->info.valid_sections = 0;
5174 vsi->seid = ctxt.seid;
5175 vsi->vsi_id = ctxt.vsi_number;
5176 vsi->sib_vsi_list.vsi = vsi;
5177 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5178 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5179 &vsi->sib_vsi_list, list);
5181 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5182 &vsi->sib_vsi_list, list);
5186 /* MAC/VLAN configuration */
5187 rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5188 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5190 ret = i40e_vsi_add_mac(vsi, &filter);
5191 if (ret != I40E_SUCCESS) {
5192 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5193 goto fail_msix_alloc;
5196 /* Get VSI BW information */
5197 i40e_vsi_get_bw_config(vsi);
5200 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5202 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5208 /* Configure vlan filter on or off */
5210 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5213 struct i40e_mac_filter *f;
5215 struct i40e_mac_filter_info *mac_filter;
5216 enum rte_mac_filter_type desired_filter;
5217 int ret = I40E_SUCCESS;
5220 /* Filter to match MAC and VLAN */
5221 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5223 /* Filter to match only MAC */
5224 desired_filter = RTE_MAC_PERFECT_MATCH;
5229 mac_filter = rte_zmalloc("mac_filter_info_data",
5230 num * sizeof(*mac_filter), 0);
5231 if (mac_filter == NULL) {
5232 PMD_DRV_LOG(ERR, "failed to allocate memory");
5233 return I40E_ERR_NO_MEMORY;
5238 /* Remove all existing mac */
5239 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5240 mac_filter[i] = f->mac_info;
5241 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5243 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5244 on ? "enable" : "disable");
5250 /* Override with new filter */
5251 for (i = 0; i < num; i++) {
5252 mac_filter[i].filter_type = desired_filter;
5253 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5255 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5256 on ? "enable" : "disable");
5262 rte_free(mac_filter);
5266 /* Configure vlan stripping on or off */
5268 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5270 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5271 struct i40e_vsi_context ctxt;
5273 int ret = I40E_SUCCESS;
5275 /* Check if it has been already on or off */
5276 if (vsi->info.valid_sections &
5277 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5279 if ((vsi->info.port_vlan_flags &
5280 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5281 return 0; /* already on */
5283 if ((vsi->info.port_vlan_flags &
5284 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5285 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5286 return 0; /* already off */
5291 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5293 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5294 vsi->info.valid_sections =
5295 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5296 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5297 vsi->info.port_vlan_flags |= vlan_flags;
5298 ctxt.seid = vsi->seid;
5299 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5300 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5302 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5303 on ? "enable" : "disable");
5309 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5311 struct rte_eth_dev_data *data = dev->data;
5315 /* Apply vlan offload setting */
5316 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5317 i40e_vlan_offload_set(dev, mask);
5319 /* Apply double-vlan setting, not implemented yet */
5321 /* Apply pvid setting */
5322 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5323 data->dev_conf.txmode.hw_vlan_insert_pvid);
5325 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5331 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5333 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5335 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5339 i40e_update_flow_control(struct i40e_hw *hw)
5341 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5342 struct i40e_link_status link_status;
5343 uint32_t rxfc = 0, txfc = 0, reg;
5347 memset(&link_status, 0, sizeof(link_status));
5348 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5349 if (ret != I40E_SUCCESS) {
5350 PMD_DRV_LOG(ERR, "Failed to get link status information");
5351 goto write_reg; /* Disable flow control */
5354 an_info = hw->phy.link_info.an_info;
5355 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5356 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5357 ret = I40E_ERR_NOT_READY;
5358 goto write_reg; /* Disable flow control */
5361 * If link auto negotiation is enabled, flow control needs to
5362 * be configured according to it
5364 switch (an_info & I40E_LINK_PAUSE_RXTX) {
5365 case I40E_LINK_PAUSE_RXTX:
5368 hw->fc.current_mode = I40E_FC_FULL;
5370 case I40E_AQ_LINK_PAUSE_RX:
5372 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5374 case I40E_AQ_LINK_PAUSE_TX:
5376 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5379 hw->fc.current_mode = I40E_FC_NONE;
5384 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5385 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5386 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5387 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5388 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5389 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5396 i40e_pf_setup(struct i40e_pf *pf)
5398 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5399 struct i40e_filter_control_settings settings;
5400 struct i40e_vsi *vsi;
5403 /* Clear all stats counters */
5404 pf->offset_loaded = FALSE;
5405 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5406 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5407 memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5408 memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5410 ret = i40e_pf_get_switch_config(pf);
5411 if (ret != I40E_SUCCESS) {
5412 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5415 if (pf->flags & I40E_FLAG_FDIR) {
5416 /* make queue allocated first, let FDIR use queue pair 0*/
5417 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5418 if (ret != I40E_FDIR_QUEUE_ID) {
5420 "queue allocation fails for FDIR: ret =%d",
5422 pf->flags &= ~I40E_FLAG_FDIR;
5425 /* main VSI setup */
5426 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5428 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5429 return I40E_ERR_NOT_READY;
5433 /* Configure filter control */
5434 memset(&settings, 0, sizeof(settings));
5435 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5436 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5437 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5438 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5440 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5441 hw->func_caps.rss_table_size);
5442 return I40E_ERR_PARAM;
5444 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5445 hw->func_caps.rss_table_size);
5446 pf->hash_lut_size = hw->func_caps.rss_table_size;
5448 /* Enable ethtype and macvlan filters */
5449 settings.enable_ethtype = TRUE;
5450 settings.enable_macvlan = TRUE;
5451 ret = i40e_set_filter_control(hw, &settings);
5453 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5456 /* Update flow control according to the auto negotiation */
5457 i40e_update_flow_control(hw);
5459 return I40E_SUCCESS;
5463 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5469 * Set or clear TX Queue Disable flags,
5470 * which is required by hardware.
5472 i40e_pre_tx_queue_cfg(hw, q_idx, on);
5473 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5475 /* Wait until the request is finished */
5476 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5477 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5478 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5479 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5480 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5486 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5487 return I40E_SUCCESS; /* already on, skip next steps */
5489 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5490 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5492 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5493 return I40E_SUCCESS; /* already off, skip next steps */
5494 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5496 /* Write the register */
5497 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5498 /* Check the result */
5499 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5500 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5501 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5503 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5504 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5507 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5508 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5512 /* Check if it is timeout */
5513 if (j >= I40E_CHK_Q_ENA_COUNT) {
5514 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5515 (on ? "enable" : "disable"), q_idx);
5516 return I40E_ERR_TIMEOUT;
5519 return I40E_SUCCESS;
5522 /* Swith on or off the tx queues */
5524 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5526 struct rte_eth_dev_data *dev_data = pf->dev_data;
5527 struct i40e_tx_queue *txq;
5528 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5532 for (i = 0; i < dev_data->nb_tx_queues; i++) {
5533 txq = dev_data->tx_queues[i];
5534 /* Don't operate the queue if not configured or
5535 * if starting only per queue */
5536 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5539 ret = i40e_dev_tx_queue_start(dev, i);
5541 ret = i40e_dev_tx_queue_stop(dev, i);
5542 if ( ret != I40E_SUCCESS)
5546 return I40E_SUCCESS;
5550 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5555 /* Wait until the request is finished */
5556 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5557 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5558 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5559 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5560 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5565 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5566 return I40E_SUCCESS; /* Already on, skip next steps */
5567 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5569 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5570 return I40E_SUCCESS; /* Already off, skip next steps */
5571 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5574 /* Write the register */
5575 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5576 /* Check the result */
5577 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5578 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5579 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5581 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5582 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5585 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5586 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5591 /* Check if it is timeout */
5592 if (j >= I40E_CHK_Q_ENA_COUNT) {
5593 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5594 (on ? "enable" : "disable"), q_idx);
5595 return I40E_ERR_TIMEOUT;
5598 return I40E_SUCCESS;
5600 /* Switch on or off the rx queues */
5602 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5604 struct rte_eth_dev_data *dev_data = pf->dev_data;
5605 struct i40e_rx_queue *rxq;
5606 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5610 for (i = 0; i < dev_data->nb_rx_queues; i++) {
5611 rxq = dev_data->rx_queues[i];
5612 /* Don't operate the queue if not configured or
5613 * if starting only per queue */
5614 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5617 ret = i40e_dev_rx_queue_start(dev, i);
5619 ret = i40e_dev_rx_queue_stop(dev, i);
5620 if (ret != I40E_SUCCESS)
5624 return I40E_SUCCESS;
5627 /* Switch on or off all the rx/tx queues */
5629 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5634 /* enable rx queues before enabling tx queues */
5635 ret = i40e_dev_switch_rx_queues(pf, on);
5637 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5640 ret = i40e_dev_switch_tx_queues(pf, on);
5642 /* Stop tx queues before stopping rx queues */
5643 ret = i40e_dev_switch_tx_queues(pf, on);
5645 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5648 ret = i40e_dev_switch_rx_queues(pf, on);
5654 /* Initialize VSI for TX */
5656 i40e_dev_tx_init(struct i40e_pf *pf)
5658 struct rte_eth_dev_data *data = pf->dev_data;
5660 uint32_t ret = I40E_SUCCESS;
5661 struct i40e_tx_queue *txq;
5663 for (i = 0; i < data->nb_tx_queues; i++) {
5664 txq = data->tx_queues[i];
5665 if (!txq || !txq->q_set)
5667 ret = i40e_tx_queue_init(txq);
5668 if (ret != I40E_SUCCESS)
5671 if (ret == I40E_SUCCESS)
5672 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5678 /* Initialize VSI for RX */
5680 i40e_dev_rx_init(struct i40e_pf *pf)
5682 struct rte_eth_dev_data *data = pf->dev_data;
5683 int ret = I40E_SUCCESS;
5685 struct i40e_rx_queue *rxq;
5687 i40e_pf_config_mq_rx(pf);
5688 for (i = 0; i < data->nb_rx_queues; i++) {
5689 rxq = data->rx_queues[i];
5690 if (!rxq || !rxq->q_set)
5693 ret = i40e_rx_queue_init(rxq);
5694 if (ret != I40E_SUCCESS) {
5696 "Failed to do RX queue initialization");
5700 if (ret == I40E_SUCCESS)
5701 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5708 i40e_dev_rxtx_init(struct i40e_pf *pf)
5712 err = i40e_dev_tx_init(pf);
5714 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5717 err = i40e_dev_rx_init(pf);
5719 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5727 i40e_vmdq_setup(struct rte_eth_dev *dev)
5729 struct rte_eth_conf *conf = &dev->data->dev_conf;
5730 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5731 int i, err, conf_vsis, j, loop;
5732 struct i40e_vsi *vsi;
5733 struct i40e_vmdq_info *vmdq_info;
5734 struct rte_eth_vmdq_rx_conf *vmdq_conf;
5735 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5738 * Disable interrupt to avoid message from VF. Furthermore, it will
5739 * avoid race condition in VSI creation/destroy.
5741 i40e_pf_disable_irq0(hw);
5743 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5744 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5748 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5749 if (conf_vsis > pf->max_nb_vmdq_vsi) {
5750 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5751 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5752 pf->max_nb_vmdq_vsi);
5756 if (pf->vmdq != NULL) {
5757 PMD_INIT_LOG(INFO, "VMDQ already configured");
5761 pf->vmdq = rte_zmalloc("vmdq_info_struct",
5762 sizeof(*vmdq_info) * conf_vsis, 0);
5764 if (pf->vmdq == NULL) {
5765 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5769 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5771 /* Create VMDQ VSI */
5772 for (i = 0; i < conf_vsis; i++) {
5773 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5774 vmdq_conf->enable_loop_back);
5776 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5780 vmdq_info = &pf->vmdq[i];
5782 vmdq_info->vsi = vsi;
5784 pf->nb_cfg_vmdq_vsi = conf_vsis;
5786 /* Configure Vlan */
5787 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5788 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5789 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5790 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5791 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5792 vmdq_conf->pool_map[i].vlan_id, j);
5794 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5795 vmdq_conf->pool_map[i].vlan_id);
5797 PMD_INIT_LOG(ERR, "Failed to add vlan");
5805 i40e_pf_enable_irq0(hw);
5810 for (i = 0; i < conf_vsis; i++)
5811 if (pf->vmdq[i].vsi == NULL)
5814 i40e_vsi_release(pf->vmdq[i].vsi);
5818 i40e_pf_enable_irq0(hw);
5823 i40e_stat_update_32(struct i40e_hw *hw,
5831 new_data = (uint64_t)I40E_READ_REG(hw, reg);
5835 if (new_data >= *offset)
5836 *stat = (uint64_t)(new_data - *offset);
5838 *stat = (uint64_t)((new_data +
5839 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5843 i40e_stat_update_48(struct i40e_hw *hw,
5852 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5853 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5854 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5859 if (new_data >= *offset)
5860 *stat = new_data - *offset;
5862 *stat = (uint64_t)((new_data +
5863 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5865 *stat &= I40E_48_BIT_MASK;
5870 i40e_pf_disable_irq0(struct i40e_hw *hw)
5872 /* Disable all interrupt types */
5873 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5874 I40E_WRITE_FLUSH(hw);
5879 i40e_pf_enable_irq0(struct i40e_hw *hw)
5881 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5882 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5883 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5884 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5885 I40E_WRITE_FLUSH(hw);
5889 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5891 /* read pending request and disable first */
5892 i40e_pf_disable_irq0(hw);
5893 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5894 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5895 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5898 /* Link no queues with irq0 */
5899 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5900 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5904 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5906 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5907 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5910 uint32_t index, offset, val;
5915 * Try to find which VF trigger a reset, use absolute VF id to access
5916 * since the reg is global register.
5918 for (i = 0; i < pf->vf_num; i++) {
5919 abs_vf_id = hw->func_caps.vf_base_id + i;
5920 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5921 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5922 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5923 /* VFR event occurred */
5924 if (val & (0x1 << offset)) {
5927 /* Clear the event first */
5928 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5930 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
5932 * Only notify a VF reset event occurred,
5933 * don't trigger another SW reset
5935 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5936 if (ret != I40E_SUCCESS)
5937 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5943 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5945 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5948 for (i = 0; i < pf->vf_num; i++)
5949 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
5953 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5955 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5956 struct i40e_arq_event_info info;
5957 uint16_t pending, opcode;
5960 info.buf_len = I40E_AQ_BUF_SZ;
5961 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5962 if (!info.msg_buf) {
5963 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5969 ret = i40e_clean_arq_element(hw, &info, &pending);
5971 if (ret != I40E_SUCCESS) {
5973 "Failed to read msg from AdminQ, aq_err: %u",
5974 hw->aq.asq_last_status);
5977 opcode = rte_le_to_cpu_16(info.desc.opcode);
5980 case i40e_aqc_opc_send_msg_to_pf:
5981 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5982 i40e_pf_host_handle_vf_msg(dev,
5983 rte_le_to_cpu_16(info.desc.retval),
5984 rte_le_to_cpu_32(info.desc.cookie_high),
5985 rte_le_to_cpu_32(info.desc.cookie_low),
5989 case i40e_aqc_opc_get_link_status:
5990 ret = i40e_dev_link_update(dev, 0);
5992 _rte_eth_dev_callback_process(dev,
5993 RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
5996 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6001 rte_free(info.msg_buf);
6005 * Interrupt handler triggered by NIC for handling
6006 * specific interrupt.
6009 * Pointer to interrupt handle.
6011 * The address of parameter (struct rte_eth_dev *) regsitered before.
6017 i40e_dev_interrupt_handler(void *param)
6019 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6020 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6023 /* Disable interrupt */
6024 i40e_pf_disable_irq0(hw);
6026 /* read out interrupt causes */
6027 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6029 /* No interrupt event indicated */
6030 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6031 PMD_DRV_LOG(INFO, "No interrupt event");
6034 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6035 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6036 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6037 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6038 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6039 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6040 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6041 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6042 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6043 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6044 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6045 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6046 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6047 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6049 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6050 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6051 i40e_dev_handle_vfr_event(dev);
6053 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6054 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6055 i40e_dev_handle_aq_msg(dev);
6059 /* Enable interrupt */
6060 i40e_pf_enable_irq0(hw);
6061 rte_intr_enable(dev->intr_handle);
6065 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6066 struct i40e_macvlan_filter *filter,
6069 int ele_num, ele_buff_size;
6070 int num, actual_num, i;
6072 int ret = I40E_SUCCESS;
6073 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6074 struct i40e_aqc_add_macvlan_element_data *req_list;
6076 if (filter == NULL || total == 0)
6077 return I40E_ERR_PARAM;
6078 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6079 ele_buff_size = hw->aq.asq_buf_size;
6081 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6082 if (req_list == NULL) {
6083 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6084 return I40E_ERR_NO_MEMORY;
6089 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6090 memset(req_list, 0, ele_buff_size);
6092 for (i = 0; i < actual_num; i++) {
6093 rte_memcpy(req_list[i].mac_addr,
6094 &filter[num + i].macaddr, ETH_ADDR_LEN);
6095 req_list[i].vlan_tag =
6096 rte_cpu_to_le_16(filter[num + i].vlan_id);
6098 switch (filter[num + i].filter_type) {
6099 case RTE_MAC_PERFECT_MATCH:
6100 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6101 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6103 case RTE_MACVLAN_PERFECT_MATCH:
6104 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6106 case RTE_MAC_HASH_MATCH:
6107 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6108 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6110 case RTE_MACVLAN_HASH_MATCH:
6111 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6114 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6115 ret = I40E_ERR_PARAM;
6119 req_list[i].queue_number = 0;
6121 req_list[i].flags = rte_cpu_to_le_16(flags);
6124 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6126 if (ret != I40E_SUCCESS) {
6127 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6131 } while (num < total);
6139 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6140 struct i40e_macvlan_filter *filter,
6143 int ele_num, ele_buff_size;
6144 int num, actual_num, i;
6146 int ret = I40E_SUCCESS;
6147 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6148 struct i40e_aqc_remove_macvlan_element_data *req_list;
6150 if (filter == NULL || total == 0)
6151 return I40E_ERR_PARAM;
6153 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6154 ele_buff_size = hw->aq.asq_buf_size;
6156 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6157 if (req_list == NULL) {
6158 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6159 return I40E_ERR_NO_MEMORY;
6164 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6165 memset(req_list, 0, ele_buff_size);
6167 for (i = 0; i < actual_num; i++) {
6168 rte_memcpy(req_list[i].mac_addr,
6169 &filter[num + i].macaddr, ETH_ADDR_LEN);
6170 req_list[i].vlan_tag =
6171 rte_cpu_to_le_16(filter[num + i].vlan_id);
6173 switch (filter[num + i].filter_type) {
6174 case RTE_MAC_PERFECT_MATCH:
6175 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6176 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6178 case RTE_MACVLAN_PERFECT_MATCH:
6179 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6181 case RTE_MAC_HASH_MATCH:
6182 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6183 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6185 case RTE_MACVLAN_HASH_MATCH:
6186 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6189 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6190 ret = I40E_ERR_PARAM;
6193 req_list[i].flags = rte_cpu_to_le_16(flags);
6196 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6198 if (ret != I40E_SUCCESS) {
6199 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6203 } while (num < total);
6210 /* Find out specific MAC filter */
6211 static struct i40e_mac_filter *
6212 i40e_find_mac_filter(struct i40e_vsi *vsi,
6213 struct ether_addr *macaddr)
6215 struct i40e_mac_filter *f;
6217 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6218 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6226 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6229 uint32_t vid_idx, vid_bit;
6231 if (vlan_id > ETH_VLAN_ID_MAX)
6234 vid_idx = I40E_VFTA_IDX(vlan_id);
6235 vid_bit = I40E_VFTA_BIT(vlan_id);
6237 if (vsi->vfta[vid_idx] & vid_bit)
6244 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6245 uint16_t vlan_id, bool on)
6247 uint32_t vid_idx, vid_bit;
6249 vid_idx = I40E_VFTA_IDX(vlan_id);
6250 vid_bit = I40E_VFTA_BIT(vlan_id);
6253 vsi->vfta[vid_idx] |= vid_bit;
6255 vsi->vfta[vid_idx] &= ~vid_bit;
6259 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6260 uint16_t vlan_id, bool on)
6262 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6263 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6266 if (vlan_id > ETH_VLAN_ID_MAX)
6269 i40e_store_vlan_filter(vsi, vlan_id, on);
6271 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6274 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6277 ret = i40e_aq_add_vlan(hw, vsi->seid,
6278 &vlan_data, 1, NULL);
6279 if (ret != I40E_SUCCESS)
6280 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6282 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6283 &vlan_data, 1, NULL);
6284 if (ret != I40E_SUCCESS)
6286 "Failed to remove vlan filter");
6291 * Find all vlan options for specific mac addr,
6292 * return with actual vlan found.
6295 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6296 struct i40e_macvlan_filter *mv_f,
6297 int num, struct ether_addr *addr)
6303 * Not to use i40e_find_vlan_filter to decrease the loop time,
6304 * although the code looks complex.
6306 if (num < vsi->vlan_num)
6307 return I40E_ERR_PARAM;
6310 for (j = 0; j < I40E_VFTA_SIZE; j++) {
6312 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6313 if (vsi->vfta[j] & (1 << k)) {
6316 "vlan number doesn't match");
6317 return I40E_ERR_PARAM;
6319 rte_memcpy(&mv_f[i].macaddr,
6320 addr, ETH_ADDR_LEN);
6322 j * I40E_UINT32_BIT_SIZE + k;
6328 return I40E_SUCCESS;
6332 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6333 struct i40e_macvlan_filter *mv_f,
6338 struct i40e_mac_filter *f;
6340 if (num < vsi->mac_num)
6341 return I40E_ERR_PARAM;
6343 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6345 PMD_DRV_LOG(ERR, "buffer number not match");
6346 return I40E_ERR_PARAM;
6348 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6350 mv_f[i].vlan_id = vlan;
6351 mv_f[i].filter_type = f->mac_info.filter_type;
6355 return I40E_SUCCESS;
6359 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6362 struct i40e_mac_filter *f;
6363 struct i40e_macvlan_filter *mv_f;
6364 int ret = I40E_SUCCESS;
6366 if (vsi == NULL || vsi->mac_num == 0)
6367 return I40E_ERR_PARAM;
6369 /* Case that no vlan is set */
6370 if (vsi->vlan_num == 0)
6373 num = vsi->mac_num * vsi->vlan_num;
6375 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6377 PMD_DRV_LOG(ERR, "failed to allocate memory");
6378 return I40E_ERR_NO_MEMORY;
6382 if (vsi->vlan_num == 0) {
6383 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6384 rte_memcpy(&mv_f[i].macaddr,
6385 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6386 mv_f[i].filter_type = f->mac_info.filter_type;
6387 mv_f[i].vlan_id = 0;
6391 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6392 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6393 vsi->vlan_num, &f->mac_info.mac_addr);
6394 if (ret != I40E_SUCCESS)
6396 for (j = i; j < i + vsi->vlan_num; j++)
6397 mv_f[j].filter_type = f->mac_info.filter_type;
6402 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6410 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6412 struct i40e_macvlan_filter *mv_f;
6414 int ret = I40E_SUCCESS;
6416 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6417 return I40E_ERR_PARAM;
6419 /* If it's already set, just return */
6420 if (i40e_find_vlan_filter(vsi,vlan))
6421 return I40E_SUCCESS;
6423 mac_num = vsi->mac_num;
6426 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6427 return I40E_ERR_PARAM;
6430 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6433 PMD_DRV_LOG(ERR, "failed to allocate memory");
6434 return I40E_ERR_NO_MEMORY;
6437 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6439 if (ret != I40E_SUCCESS)
6442 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6444 if (ret != I40E_SUCCESS)
6447 i40e_set_vlan_filter(vsi, vlan, 1);
6457 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6459 struct i40e_macvlan_filter *mv_f;
6461 int ret = I40E_SUCCESS;
6464 * Vlan 0 is the generic filter for untagged packets
6465 * and can't be removed.
6467 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6468 return I40E_ERR_PARAM;
6470 /* If can't find it, just return */
6471 if (!i40e_find_vlan_filter(vsi, vlan))
6472 return I40E_ERR_PARAM;
6474 mac_num = vsi->mac_num;
6477 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6478 return I40E_ERR_PARAM;
6481 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6484 PMD_DRV_LOG(ERR, "failed to allocate memory");
6485 return I40E_ERR_NO_MEMORY;
6488 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6490 if (ret != I40E_SUCCESS)
6493 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6495 if (ret != I40E_SUCCESS)
6498 /* This is last vlan to remove, replace all mac filter with vlan 0 */
6499 if (vsi->vlan_num == 1) {
6500 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6501 if (ret != I40E_SUCCESS)
6504 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6505 if (ret != I40E_SUCCESS)
6509 i40e_set_vlan_filter(vsi, vlan, 0);
6519 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6521 struct i40e_mac_filter *f;
6522 struct i40e_macvlan_filter *mv_f;
6523 int i, vlan_num = 0;
6524 int ret = I40E_SUCCESS;
6526 /* If it's add and we've config it, return */
6527 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6529 return I40E_SUCCESS;
6530 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6531 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6534 * If vlan_num is 0, that's the first time to add mac,
6535 * set mask for vlan_id 0.
6537 if (vsi->vlan_num == 0) {
6538 i40e_set_vlan_filter(vsi, 0, 1);
6541 vlan_num = vsi->vlan_num;
6542 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6543 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6546 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6548 PMD_DRV_LOG(ERR, "failed to allocate memory");
6549 return I40E_ERR_NO_MEMORY;
6552 for (i = 0; i < vlan_num; i++) {
6553 mv_f[i].filter_type = mac_filter->filter_type;
6554 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6558 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6559 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6560 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6561 &mac_filter->mac_addr);
6562 if (ret != I40E_SUCCESS)
6566 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6567 if (ret != I40E_SUCCESS)
6570 /* Add the mac addr into mac list */
6571 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6573 PMD_DRV_LOG(ERR, "failed to allocate memory");
6574 ret = I40E_ERR_NO_MEMORY;
6577 rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6579 f->mac_info.filter_type = mac_filter->filter_type;
6580 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6591 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6593 struct i40e_mac_filter *f;
6594 struct i40e_macvlan_filter *mv_f;
6596 enum rte_mac_filter_type filter_type;
6597 int ret = I40E_SUCCESS;
6599 /* Can't find it, return an error */
6600 f = i40e_find_mac_filter(vsi, addr);
6602 return I40E_ERR_PARAM;
6604 vlan_num = vsi->vlan_num;
6605 filter_type = f->mac_info.filter_type;
6606 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6607 filter_type == RTE_MACVLAN_HASH_MATCH) {
6608 if (vlan_num == 0) {
6609 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6610 return I40E_ERR_PARAM;
6612 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6613 filter_type == RTE_MAC_HASH_MATCH)
6616 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6618 PMD_DRV_LOG(ERR, "failed to allocate memory");
6619 return I40E_ERR_NO_MEMORY;
6622 for (i = 0; i < vlan_num; i++) {
6623 mv_f[i].filter_type = filter_type;
6624 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6627 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6628 filter_type == RTE_MACVLAN_HASH_MATCH) {
6629 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6630 if (ret != I40E_SUCCESS)
6634 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6635 if (ret != I40E_SUCCESS)
6638 /* Remove the mac addr into mac list */
6639 TAILQ_REMOVE(&vsi->mac_list, f, next);
6649 /* Configure hash enable flags for RSS */
6651 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
6659 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6660 if (flags & (1ULL << i))
6661 hena |= adapter->pctypes_tbl[i];
6667 /* Parse the hash enable flags */
6669 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
6671 uint64_t rss_hf = 0;
6677 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6678 if (flags & adapter->pctypes_tbl[i])
6679 rss_hf |= (1ULL << i);
6686 i40e_pf_disable_rss(struct i40e_pf *pf)
6688 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6690 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
6691 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
6692 I40E_WRITE_FLUSH(hw);
6696 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6698 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6699 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6702 if (!key || key_len == 0) {
6703 PMD_DRV_LOG(DEBUG, "No key to be configured");
6705 } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6707 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6711 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6712 struct i40e_aqc_get_set_rss_key_data *key_dw =
6713 (struct i40e_aqc_get_set_rss_key_data *)key;
6715 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6717 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6719 uint32_t *hash_key = (uint32_t *)key;
6722 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6723 i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6724 I40E_WRITE_FLUSH(hw);
6731 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6733 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6734 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6737 if (!key || !key_len)
6740 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6741 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6742 (struct i40e_aqc_get_set_rss_key_data *)key);
6744 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6748 uint32_t *key_dw = (uint32_t *)key;
6751 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6752 key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6754 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6760 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6762 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6766 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6767 rss_conf->rss_key_len);
6771 hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
6772 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6773 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6774 I40E_WRITE_FLUSH(hw);
6780 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6781 struct rte_eth_rss_conf *rss_conf)
6783 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6784 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6785 uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
6788 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6789 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6791 if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
6792 if (rss_hf != 0) /* Enable RSS */
6794 return 0; /* Nothing to do */
6797 if (rss_hf == 0) /* Disable RSS */
6800 return i40e_hw_rss_hash_set(pf, rss_conf);
6804 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6805 struct rte_eth_rss_conf *rss_conf)
6807 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6808 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6811 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6812 &rss_conf->rss_key_len);
6814 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6815 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6816 rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
6822 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6824 switch (filter_type) {
6825 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6826 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6828 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6829 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6831 case RTE_TUNNEL_FILTER_IMAC_TENID:
6832 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6834 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6835 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6837 case ETH_TUNNEL_FILTER_IMAC:
6838 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6840 case ETH_TUNNEL_FILTER_OIP:
6841 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6843 case ETH_TUNNEL_FILTER_IIP:
6844 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6847 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6854 /* Convert tunnel filter structure */
6856 i40e_tunnel_filter_convert(
6857 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
6858 struct i40e_tunnel_filter *tunnel_filter)
6860 ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
6861 (struct ether_addr *)&tunnel_filter->input.outer_mac);
6862 ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
6863 (struct ether_addr *)&tunnel_filter->input.inner_mac);
6864 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
6865 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
6866 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6867 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6868 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6870 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6871 tunnel_filter->input.flags = cld_filter->element.flags;
6872 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
6873 tunnel_filter->queue = cld_filter->element.queue_number;
6874 rte_memcpy(tunnel_filter->input.general_fields,
6875 cld_filter->general_fields,
6876 sizeof(cld_filter->general_fields));
6881 /* Check if there exists the tunnel filter */
6882 struct i40e_tunnel_filter *
6883 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6884 const struct i40e_tunnel_filter_input *input)
6888 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6892 return tunnel_rule->hash_map[ret];
6895 /* Add a tunnel filter into the SW list */
6897 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6898 struct i40e_tunnel_filter *tunnel_filter)
6900 struct i40e_tunnel_rule *rule = &pf->tunnel;
6903 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6906 "Failed to insert tunnel filter to hash table %d!",
6910 rule->hash_map[ret] = tunnel_filter;
6912 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6917 /* Delete a tunnel filter from the SW list */
6919 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6920 struct i40e_tunnel_filter_input *input)
6922 struct i40e_tunnel_rule *rule = &pf->tunnel;
6923 struct i40e_tunnel_filter *tunnel_filter;
6926 ret = rte_hash_del_key(rule->hash_table, input);
6929 "Failed to delete tunnel filter to hash table %d!",
6933 tunnel_filter = rule->hash_map[ret];
6934 rule->hash_map[ret] = NULL;
6936 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6937 rte_free(tunnel_filter);
6943 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6944 struct rte_eth_tunnel_filter_conf *tunnel_filter,
6949 uint8_t i, tun_type = 0;
6950 /* internal varialbe to convert ipv6 byte order */
6951 uint32_t convert_ipv6[4];
6953 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6954 struct i40e_vsi *vsi = pf->main_vsi;
6955 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
6956 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
6957 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6958 struct i40e_tunnel_filter *tunnel, *node;
6959 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6961 cld_filter = rte_zmalloc("tunnel_filter",
6962 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
6965 if (NULL == cld_filter) {
6966 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6969 pfilter = cld_filter;
6971 ether_addr_copy(&tunnel_filter->outer_mac,
6972 (struct ether_addr *)&pfilter->element.outer_mac);
6973 ether_addr_copy(&tunnel_filter->inner_mac,
6974 (struct ether_addr *)&pfilter->element.inner_mac);
6976 pfilter->element.inner_vlan =
6977 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6978 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6979 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6980 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6981 rte_memcpy(&pfilter->element.ipaddr.v4.data,
6982 &rte_cpu_to_le_32(ipv4_addr),
6983 sizeof(pfilter->element.ipaddr.v4.data));
6985 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6986 for (i = 0; i < 4; i++) {
6988 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6990 rte_memcpy(&pfilter->element.ipaddr.v6.data,
6992 sizeof(pfilter->element.ipaddr.v6.data));
6995 /* check tunneled type */
6996 switch (tunnel_filter->tunnel_type) {
6997 case RTE_TUNNEL_TYPE_VXLAN:
6998 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7000 case RTE_TUNNEL_TYPE_NVGRE:
7001 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7003 case RTE_TUNNEL_TYPE_IP_IN_GRE:
7004 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7007 /* Other tunnel types is not supported. */
7008 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7009 rte_free(cld_filter);
7013 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7014 &pfilter->element.flags);
7016 rte_free(cld_filter);
7020 pfilter->element.flags |= rte_cpu_to_le_16(
7021 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7022 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7023 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7024 pfilter->element.queue_number =
7025 rte_cpu_to_le_16(tunnel_filter->queue_id);
7027 /* Check if there is the filter in SW list */
7028 memset(&check_filter, 0, sizeof(check_filter));
7029 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7030 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7032 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7036 if (!add && !node) {
7037 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7042 ret = i40e_aq_add_cloud_filters(hw,
7043 vsi->seid, &cld_filter->element, 1);
7045 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7048 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7049 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7050 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7052 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7053 &cld_filter->element, 1);
7055 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7058 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7061 rte_free(cld_filter);
7065 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7066 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
7067 #define I40E_TR_GENEVE_KEY_MASK 0x8
7068 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
7069 #define I40E_TR_GRE_KEY_MASK 0x400
7070 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
7071 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
7074 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7076 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7077 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7078 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7079 enum i40e_status_code status = I40E_SUCCESS;
7081 memset(&filter_replace, 0,
7082 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7083 memset(&filter_replace_buf, 0,
7084 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7086 /* create L1 filter */
7087 filter_replace.old_filter_type =
7088 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7089 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7090 filter_replace.tr_bit = 0;
7092 /* Prepare the buffer, 3 entries */
7093 filter_replace_buf.data[0] =
7094 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7095 filter_replace_buf.data[0] |=
7096 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7097 filter_replace_buf.data[2] = 0xFF;
7098 filter_replace_buf.data[3] = 0xFF;
7099 filter_replace_buf.data[4] =
7100 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7101 filter_replace_buf.data[4] |=
7102 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7103 filter_replace_buf.data[7] = 0xF0;
7104 filter_replace_buf.data[8]
7105 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7106 filter_replace_buf.data[8] |=
7107 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7108 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7109 I40E_TR_GENEVE_KEY_MASK |
7110 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7111 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7112 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7113 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7115 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7116 &filter_replace_buf);
7121 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7123 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7124 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7125 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7126 enum i40e_status_code status = I40E_SUCCESS;
7129 memset(&filter_replace, 0,
7130 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7131 memset(&filter_replace_buf, 0,
7132 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7133 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7134 I40E_AQC_MIRROR_CLOUD_FILTER;
7135 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7136 filter_replace.new_filter_type =
7137 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7138 /* Prepare the buffer, 2 entries */
7139 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7140 filter_replace_buf.data[0] |=
7141 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7142 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7143 filter_replace_buf.data[4] |=
7144 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7145 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7146 &filter_replace_buf);
7151 memset(&filter_replace, 0,
7152 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7153 memset(&filter_replace_buf, 0,
7154 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7156 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7157 I40E_AQC_MIRROR_CLOUD_FILTER;
7158 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7159 filter_replace.new_filter_type =
7160 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7161 /* Prepare the buffer, 2 entries */
7162 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7163 filter_replace_buf.data[0] |=
7164 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7165 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7166 filter_replace_buf.data[4] |=
7167 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7169 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7170 &filter_replace_buf);
7174 static enum i40e_status_code
7175 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7177 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7178 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7179 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7180 enum i40e_status_code status = I40E_SUCCESS;
7183 memset(&filter_replace, 0,
7184 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7185 memset(&filter_replace_buf, 0,
7186 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7187 /* create L1 filter */
7188 filter_replace.old_filter_type =
7189 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7190 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7191 filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7192 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7193 /* Prepare the buffer, 2 entries */
7194 filter_replace_buf.data[0] =
7195 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7196 filter_replace_buf.data[0] |=
7197 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7198 filter_replace_buf.data[2] = 0xFF;
7199 filter_replace_buf.data[3] = 0xFF;
7200 filter_replace_buf.data[4] =
7201 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7202 filter_replace_buf.data[4] |=
7203 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7204 filter_replace_buf.data[6] = 0xFF;
7205 filter_replace_buf.data[7] = 0xFF;
7206 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7207 &filter_replace_buf);
7212 memset(&filter_replace, 0,
7213 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7214 memset(&filter_replace_buf, 0,
7215 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7216 /* create L1 filter */
7217 filter_replace.old_filter_type =
7218 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
7219 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
7220 filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
7221 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7222 /* Prepare the buffer, 2 entries */
7223 filter_replace_buf.data[0] =
7224 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7225 filter_replace_buf.data[0] |=
7226 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7227 filter_replace_buf.data[2] = 0xFF;
7228 filter_replace_buf.data[3] = 0xFF;
7229 filter_replace_buf.data[4] =
7230 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7231 filter_replace_buf.data[4] |=
7232 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7233 filter_replace_buf.data[6] = 0xFF;
7234 filter_replace_buf.data[7] = 0xFF;
7236 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7237 &filter_replace_buf);
7242 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
7244 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7245 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7246 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7247 enum i40e_status_code status = I40E_SUCCESS;
7250 memset(&filter_replace, 0,
7251 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7252 memset(&filter_replace_buf, 0,
7253 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7254 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7255 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7256 filter_replace.new_filter_type =
7257 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7258 /* Prepare the buffer, 2 entries */
7259 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
7260 filter_replace_buf.data[0] |=
7261 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7262 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7263 filter_replace_buf.data[4] |=
7264 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7265 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7266 &filter_replace_buf);
7271 memset(&filter_replace, 0,
7272 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7273 memset(&filter_replace_buf, 0,
7274 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7275 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7276 filter_replace.old_filter_type =
7277 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7278 filter_replace.new_filter_type =
7279 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7280 /* Prepare the buffer, 2 entries */
7281 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
7282 filter_replace_buf.data[0] |=
7283 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7284 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7285 filter_replace_buf.data[4] |=
7286 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7288 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7289 &filter_replace_buf);
7294 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7295 struct i40e_tunnel_filter_conf *tunnel_filter,
7300 uint8_t i, tun_type = 0;
7301 /* internal variable to convert ipv6 byte order */
7302 uint32_t convert_ipv6[4];
7304 struct i40e_pf_vf *vf = NULL;
7305 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7306 struct i40e_vsi *vsi;
7307 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7308 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7309 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7310 struct i40e_tunnel_filter *tunnel, *node;
7311 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7313 bool big_buffer = 0;
7315 cld_filter = rte_zmalloc("tunnel_filter",
7316 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7319 if (cld_filter == NULL) {
7320 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7323 pfilter = cld_filter;
7325 ether_addr_copy(&tunnel_filter->outer_mac,
7326 (struct ether_addr *)&pfilter->element.outer_mac);
7327 ether_addr_copy(&tunnel_filter->inner_mac,
7328 (struct ether_addr *)&pfilter->element.inner_mac);
7330 pfilter->element.inner_vlan =
7331 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7332 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7333 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7334 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7335 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7336 &rte_cpu_to_le_32(ipv4_addr),
7337 sizeof(pfilter->element.ipaddr.v4.data));
7339 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7340 for (i = 0; i < 4; i++) {
7342 rte_cpu_to_le_32(rte_be_to_cpu_32(
7343 tunnel_filter->ip_addr.ipv6_addr[i]));
7345 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7347 sizeof(pfilter->element.ipaddr.v6.data));
7350 /* check tunneled type */
7351 switch (tunnel_filter->tunnel_type) {
7352 case I40E_TUNNEL_TYPE_VXLAN:
7353 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7355 case I40E_TUNNEL_TYPE_NVGRE:
7356 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7358 case I40E_TUNNEL_TYPE_IP_IN_GRE:
7359 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7361 case I40E_TUNNEL_TYPE_MPLSoUDP:
7362 if (!pf->mpls_replace_flag) {
7363 i40e_replace_mpls_l1_filter(pf);
7364 i40e_replace_mpls_cloud_filter(pf);
7365 pf->mpls_replace_flag = 1;
7367 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7368 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7370 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7371 (teid_le & 0xF) << 12;
7372 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7375 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
7377 case I40E_TUNNEL_TYPE_MPLSoGRE:
7378 if (!pf->mpls_replace_flag) {
7379 i40e_replace_mpls_l1_filter(pf);
7380 i40e_replace_mpls_cloud_filter(pf);
7381 pf->mpls_replace_flag = 1;
7383 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7384 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7386 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7387 (teid_le & 0xF) << 12;
7388 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7391 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
7393 case I40E_TUNNEL_TYPE_GTPC:
7394 if (!pf->gtp_replace_flag) {
7395 i40e_replace_gtp_l1_filter(pf);
7396 i40e_replace_gtp_cloud_filter(pf);
7397 pf->gtp_replace_flag = 1;
7399 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7400 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
7401 (teid_le >> 16) & 0xFFFF;
7402 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
7404 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
7408 case I40E_TUNNEL_TYPE_GTPU:
7409 if (!pf->gtp_replace_flag) {
7410 i40e_replace_gtp_l1_filter(pf);
7411 i40e_replace_gtp_cloud_filter(pf);
7412 pf->gtp_replace_flag = 1;
7414 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7415 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
7416 (teid_le >> 16) & 0xFFFF;
7417 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
7419 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
7423 case I40E_TUNNEL_TYPE_QINQ:
7424 if (!pf->qinq_replace_flag) {
7425 ret = i40e_cloud_filter_qinq_create(pf);
7428 "QinQ tunnel filter already created.");
7429 pf->qinq_replace_flag = 1;
7431 /* Add in the General fields the values of
7432 * the Outer and Inner VLAN
7433 * Big Buffer should be set, see changes in
7434 * i40e_aq_add_cloud_filters
7436 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7437 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7441 /* Other tunnel types is not supported. */
7442 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7443 rte_free(cld_filter);
7447 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7448 pfilter->element.flags =
7449 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7450 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7451 pfilter->element.flags =
7452 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7453 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
7454 pfilter->element.flags =
7455 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7456 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
7457 pfilter->element.flags =
7458 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7459 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7460 pfilter->element.flags |=
7461 I40E_AQC_ADD_CLOUD_FILTER_0X10;
7463 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7464 &pfilter->element.flags);
7466 rte_free(cld_filter);
7471 pfilter->element.flags |= rte_cpu_to_le_16(
7472 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7473 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7474 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7475 pfilter->element.queue_number =
7476 rte_cpu_to_le_16(tunnel_filter->queue_id);
7478 if (!tunnel_filter->is_to_vf)
7481 if (tunnel_filter->vf_id >= pf->vf_num) {
7482 PMD_DRV_LOG(ERR, "Invalid argument.");
7485 vf = &pf->vfs[tunnel_filter->vf_id];
7489 /* Check if there is the filter in SW list */
7490 memset(&check_filter, 0, sizeof(check_filter));
7491 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7492 check_filter.is_to_vf = tunnel_filter->is_to_vf;
7493 check_filter.vf_id = tunnel_filter->vf_id;
7494 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7496 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7500 if (!add && !node) {
7501 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7507 ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7508 vsi->seid, cld_filter, 1);
7510 ret = i40e_aq_add_cloud_filters(hw,
7511 vsi->seid, &cld_filter->element, 1);
7513 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7516 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7517 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7518 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7521 ret = i40e_aq_remove_cloud_filters_big_buffer(
7522 hw, vsi->seid, cld_filter, 1);
7524 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7525 &cld_filter->element, 1);
7527 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7530 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7533 rte_free(cld_filter);
7538 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7542 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7543 if (pf->vxlan_ports[i] == port)
7551 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7555 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7557 idx = i40e_get_vxlan_port_idx(pf, port);
7559 /* Check if port already exists */
7561 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7565 /* Now check if there is space to add the new port */
7566 idx = i40e_get_vxlan_port_idx(pf, 0);
7569 "Maximum number of UDP ports reached, not adding port %d",
7574 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7577 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7581 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7584 /* New port: add it and mark its index in the bitmap */
7585 pf->vxlan_ports[idx] = port;
7586 pf->vxlan_bitmap |= (1 << idx);
7588 if (!(pf->flags & I40E_FLAG_VXLAN))
7589 pf->flags |= I40E_FLAG_VXLAN;
7595 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7598 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7600 if (!(pf->flags & I40E_FLAG_VXLAN)) {
7601 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7605 idx = i40e_get_vxlan_port_idx(pf, port);
7608 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7612 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7613 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7617 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7620 pf->vxlan_ports[idx] = 0;
7621 pf->vxlan_bitmap &= ~(1 << idx);
7623 if (!pf->vxlan_bitmap)
7624 pf->flags &= ~I40E_FLAG_VXLAN;
7629 /* Add UDP tunneling port */
7631 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7632 struct rte_eth_udp_tunnel *udp_tunnel)
7635 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7637 if (udp_tunnel == NULL)
7640 switch (udp_tunnel->prot_type) {
7641 case RTE_TUNNEL_TYPE_VXLAN:
7642 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7645 case RTE_TUNNEL_TYPE_GENEVE:
7646 case RTE_TUNNEL_TYPE_TEREDO:
7647 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7652 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7660 /* Remove UDP tunneling port */
7662 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7663 struct rte_eth_udp_tunnel *udp_tunnel)
7666 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7668 if (udp_tunnel == NULL)
7671 switch (udp_tunnel->prot_type) {
7672 case RTE_TUNNEL_TYPE_VXLAN:
7673 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7675 case RTE_TUNNEL_TYPE_GENEVE:
7676 case RTE_TUNNEL_TYPE_TEREDO:
7677 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7681 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7689 /* Calculate the maximum number of contiguous PF queues that are configured */
7691 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7693 struct rte_eth_dev_data *data = pf->dev_data;
7695 struct i40e_rx_queue *rxq;
7698 for (i = 0; i < pf->lan_nb_qps; i++) {
7699 rxq = data->rx_queues[i];
7700 if (rxq && rxq->q_set)
7711 i40e_pf_config_rss(struct i40e_pf *pf)
7713 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7714 struct rte_eth_rss_conf rss_conf;
7715 uint32_t i, lut = 0;
7719 * If both VMDQ and RSS enabled, not all of PF queues are configured.
7720 * It's necessary to calculate the actual PF queues that are configured.
7722 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7723 num = i40e_pf_calc_configured_queues_num(pf);
7725 num = pf->dev_data->nb_rx_queues;
7727 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7728 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7732 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7736 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7739 lut = (lut << 8) | (j & ((0x1 <<
7740 hw->func_caps.rss_table_entry_width) - 1));
7742 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7745 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7746 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
7747 i40e_pf_disable_rss(pf);
7750 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7751 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7752 /* Random default keys */
7753 static uint32_t rss_key_default[] = {0x6b793944,
7754 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7755 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7756 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7758 rss_conf.rss_key = (uint8_t *)rss_key_default;
7759 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7763 return i40e_hw_rss_hash_set(pf, &rss_conf);
7767 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7768 struct rte_eth_tunnel_filter_conf *filter)
7770 if (pf == NULL || filter == NULL) {
7771 PMD_DRV_LOG(ERR, "Invalid parameter");
7775 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7776 PMD_DRV_LOG(ERR, "Invalid queue ID");
7780 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7781 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7785 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7786 (is_zero_ether_addr(&filter->outer_mac))) {
7787 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7791 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7792 (is_zero_ether_addr(&filter->inner_mac))) {
7793 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7800 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7801 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
7803 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7808 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7809 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7812 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7813 } else if (len == 4) {
7814 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7816 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7821 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7828 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7829 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7835 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7842 switch (cfg->cfg_type) {
7843 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7844 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7847 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7855 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7856 enum rte_filter_op filter_op,
7859 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7860 int ret = I40E_ERR_PARAM;
7862 switch (filter_op) {
7863 case RTE_ETH_FILTER_SET:
7864 ret = i40e_dev_global_config_set(hw,
7865 (struct rte_eth_global_cfg *)arg);
7868 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7876 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7877 enum rte_filter_op filter_op,
7880 struct rte_eth_tunnel_filter_conf *filter;
7881 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7882 int ret = I40E_SUCCESS;
7884 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7886 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7887 return I40E_ERR_PARAM;
7889 switch (filter_op) {
7890 case RTE_ETH_FILTER_NOP:
7891 if (!(pf->flags & I40E_FLAG_VXLAN))
7892 ret = I40E_NOT_SUPPORTED;
7894 case RTE_ETH_FILTER_ADD:
7895 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7897 case RTE_ETH_FILTER_DELETE:
7898 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7901 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7902 ret = I40E_ERR_PARAM;
7910 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7913 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7916 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7917 ret = i40e_pf_config_rss(pf);
7919 i40e_pf_disable_rss(pf);
7924 /* Get the symmetric hash enable configurations per port */
7926 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7928 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7930 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7933 /* Set the symmetric hash enable configurations per port */
7935 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7937 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7940 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7942 "Symmetric hash has already been enabled");
7945 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7947 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7949 "Symmetric hash has already been disabled");
7952 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7954 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7955 I40E_WRITE_FLUSH(hw);
7959 * Get global configurations of hash function type and symmetric hash enable
7960 * per flow type (pctype). Note that global configuration means it affects all
7961 * the ports on the same NIC.
7964 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7965 struct rte_eth_hash_global_conf *g_cfg)
7967 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
7971 memset(g_cfg, 0, sizeof(*g_cfg));
7972 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7973 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7974 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7976 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7977 PMD_DRV_LOG(DEBUG, "Hash function is %s",
7978 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7981 * We work only with lowest 32 bits which is not correct, but to work
7982 * properly the valid_bit_mask size should be increased up to 64 bits
7983 * and this will brake ABI. This modification will be done in next
7986 g_cfg->valid_bit_mask[0] = (uint32_t)adapter->flow_types_mask;
7988 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT32_BIT; i++) {
7989 if (!adapter->pctypes_tbl[i])
7991 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
7992 j < I40E_FILTER_PCTYPE_MAX; j++) {
7993 if (adapter->pctypes_tbl[i] & (1ULL << j)) {
7994 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
7995 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
7996 g_cfg->sym_hash_enable_mask[0] |=
8007 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8008 const struct rte_eth_hash_global_conf *g_cfg)
8011 uint32_t mask0, i40e_mask = adapter->flow_types_mask;
8013 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8014 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8015 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8016 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8022 * As i40e supports less than 32 flow types, only first 32 bits need to
8025 mask0 = g_cfg->valid_bit_mask[0];
8026 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8028 /* Check if any unsupported flow type configured */
8029 if ((mask0 | i40e_mask) ^ i40e_mask)
8032 if (g_cfg->valid_bit_mask[i])
8040 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8046 * Set global configurations of hash function type and symmetric hash enable
8047 * per flow type (pctype). Note any modifying global configuration will affect
8048 * all the ports on the same NIC.
8051 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8052 struct rte_eth_hash_global_conf *g_cfg)
8054 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8059 * We work only with lowest 32 bits which is not correct, but to work
8060 * properly the valid_bit_mask size should be increased up to 64 bits
8061 * and this will brake ABI. This modification will be done in next
8064 uint32_t mask0 = g_cfg->valid_bit_mask[0] &
8065 (uint32_t)adapter->flow_types_mask;
8067 /* Check the input parameters */
8068 ret = i40e_hash_global_config_check(adapter, g_cfg);
8072 for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT32_BIT; i++) {
8073 if (mask0 & (1UL << i)) {
8074 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
8075 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8077 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8078 j < I40E_FILTER_PCTYPE_MAX; j++) {
8079 if (adapter->pctypes_tbl[i] & (1ULL << j))
8080 i40e_write_rx_ctl(hw,
8087 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8088 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8090 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8092 "Hash function already set to Toeplitz");
8095 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8096 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8098 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8100 "Hash function already set to Simple XOR");
8103 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8105 /* Use the default, and keep it as it is */
8108 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
8111 I40E_WRITE_FLUSH(hw);
8117 * Valid input sets for hash and flow director filters per PCTYPE
8120 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8121 enum rte_filter_type filter)
8125 static const uint64_t valid_hash_inset_table[] = {
8126 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8127 I40E_INSET_DMAC | I40E_INSET_SMAC |
8128 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8129 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8130 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8131 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8132 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8133 I40E_INSET_FLEX_PAYLOAD,
8134 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8135 I40E_INSET_DMAC | I40E_INSET_SMAC |
8136 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8137 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8138 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8139 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8140 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8141 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8142 I40E_INSET_FLEX_PAYLOAD,
8143 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8144 I40E_INSET_DMAC | I40E_INSET_SMAC |
8145 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8146 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8147 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8148 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8149 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8150 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8151 I40E_INSET_FLEX_PAYLOAD,
8152 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8153 I40E_INSET_DMAC | I40E_INSET_SMAC |
8154 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8155 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8156 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8157 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8158 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8159 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8160 I40E_INSET_FLEX_PAYLOAD,
8161 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8162 I40E_INSET_DMAC | I40E_INSET_SMAC |
8163 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8164 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8165 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8166 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8167 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8168 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8169 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8170 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8171 I40E_INSET_DMAC | I40E_INSET_SMAC |
8172 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8173 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8174 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8175 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8176 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8177 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8178 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8179 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8180 I40E_INSET_DMAC | I40E_INSET_SMAC |
8181 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8182 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8183 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8184 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8185 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8186 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8187 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8188 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8189 I40E_INSET_DMAC | I40E_INSET_SMAC |
8190 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8191 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8192 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8193 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8194 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8195 I40E_INSET_FLEX_PAYLOAD,
8196 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8197 I40E_INSET_DMAC | I40E_INSET_SMAC |
8198 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8199 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8200 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8201 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8202 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8203 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8204 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8205 I40E_INSET_DMAC | I40E_INSET_SMAC |
8206 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8207 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8208 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8209 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8210 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8211 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8212 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8213 I40E_INSET_DMAC | I40E_INSET_SMAC |
8214 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8215 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8216 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8217 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8218 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8219 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8220 I40E_INSET_FLEX_PAYLOAD,
8221 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8222 I40E_INSET_DMAC | I40E_INSET_SMAC |
8223 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8224 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8225 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8226 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8227 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8228 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8229 I40E_INSET_FLEX_PAYLOAD,
8230 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8231 I40E_INSET_DMAC | I40E_INSET_SMAC |
8232 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8233 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8234 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8235 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8236 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8237 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8238 I40E_INSET_FLEX_PAYLOAD,
8239 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8240 I40E_INSET_DMAC | I40E_INSET_SMAC |
8241 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8242 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8243 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8244 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8245 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8246 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8247 I40E_INSET_FLEX_PAYLOAD,
8248 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8249 I40E_INSET_DMAC | I40E_INSET_SMAC |
8250 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8251 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8252 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8253 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8254 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8255 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8256 I40E_INSET_FLEX_PAYLOAD,
8257 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8258 I40E_INSET_DMAC | I40E_INSET_SMAC |
8259 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8260 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8261 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8262 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8263 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8264 I40E_INSET_FLEX_PAYLOAD,
8265 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8266 I40E_INSET_DMAC | I40E_INSET_SMAC |
8267 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8268 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8269 I40E_INSET_FLEX_PAYLOAD,
8273 * Flow director supports only fields defined in
8274 * union rte_eth_fdir_flow.
8276 static const uint64_t valid_fdir_inset_table[] = {
8277 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8278 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8279 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8280 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8281 I40E_INSET_IPV4_TTL,
8282 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8283 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8284 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8285 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8286 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8287 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8288 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8289 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8290 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8291 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8292 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8293 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8294 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8295 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8296 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8297 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8298 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8299 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8300 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8301 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8302 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8303 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8304 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8305 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8306 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8307 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8308 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8309 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8310 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8311 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8313 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8314 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8315 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8316 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8317 I40E_INSET_IPV4_TTL,
8318 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8319 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8320 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8321 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8322 I40E_INSET_IPV6_HOP_LIMIT,
8323 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8324 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8325 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8326 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8327 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8328 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8329 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8330 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8331 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8332 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8333 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8334 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8335 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8336 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8337 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8338 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8339 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8340 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8341 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8342 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8343 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8344 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8345 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8346 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8347 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8348 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8349 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8350 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8351 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8352 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8354 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8355 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8356 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8357 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8358 I40E_INSET_IPV6_HOP_LIMIT,
8359 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8360 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8361 I40E_INSET_LAST_ETHER_TYPE,
8364 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8366 if (filter == RTE_ETH_FILTER_HASH)
8367 valid = valid_hash_inset_table[pctype];
8369 valid = valid_fdir_inset_table[pctype];
8375 * Validate if the input set is allowed for a specific PCTYPE
8378 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8379 enum rte_filter_type filter, uint64_t inset)
8383 valid = i40e_get_valid_input_set(pctype, filter);
8384 if (inset & (~valid))
8390 /* default input set fields combination per pctype */
8392 i40e_get_default_input_set(uint16_t pctype)
8394 static const uint64_t default_inset_table[] = {
8395 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8396 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8397 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8398 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8399 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8400 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8401 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8402 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8403 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8404 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8405 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8406 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8407 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8408 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8409 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8410 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8411 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8412 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8413 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8414 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8416 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8417 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8418 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8419 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8420 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8421 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8422 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8423 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8424 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8425 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8426 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8427 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8428 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8429 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8430 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8431 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8432 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8433 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8434 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8435 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8436 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8437 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8439 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8440 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8441 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8442 I40E_INSET_LAST_ETHER_TYPE,
8445 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8448 return default_inset_table[pctype];
8452 * Parse the input set from index to logical bit masks
8455 i40e_parse_input_set(uint64_t *inset,
8456 enum i40e_filter_pctype pctype,
8457 enum rte_eth_input_set_field *field,
8463 static const struct {
8464 enum rte_eth_input_set_field field;
8466 } inset_convert_table[] = {
8467 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8468 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8469 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8470 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8471 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8472 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8473 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8474 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8475 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8476 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8477 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8478 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8479 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8480 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8481 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8482 I40E_INSET_IPV6_NEXT_HDR},
8483 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8484 I40E_INSET_IPV6_HOP_LIMIT},
8485 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8486 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8487 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8488 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8489 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8490 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8491 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8492 I40E_INSET_SCTP_VT},
8493 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8494 I40E_INSET_TUNNEL_DMAC},
8495 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8496 I40E_INSET_VLAN_TUNNEL},
8497 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8498 I40E_INSET_TUNNEL_ID},
8499 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8500 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8501 I40E_INSET_FLEX_PAYLOAD_W1},
8502 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8503 I40E_INSET_FLEX_PAYLOAD_W2},
8504 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8505 I40E_INSET_FLEX_PAYLOAD_W3},
8506 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8507 I40E_INSET_FLEX_PAYLOAD_W4},
8508 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8509 I40E_INSET_FLEX_PAYLOAD_W5},
8510 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8511 I40E_INSET_FLEX_PAYLOAD_W6},
8512 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8513 I40E_INSET_FLEX_PAYLOAD_W7},
8514 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8515 I40E_INSET_FLEX_PAYLOAD_W8},
8518 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8521 /* Only one item allowed for default or all */
8523 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8524 *inset = i40e_get_default_input_set(pctype);
8526 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8527 *inset = I40E_INSET_NONE;
8532 for (i = 0, *inset = 0; i < size; i++) {
8533 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8534 if (field[i] == inset_convert_table[j].field) {
8535 *inset |= inset_convert_table[j].inset;
8540 /* It contains unsupported input set, return immediately */
8541 if (j == RTE_DIM(inset_convert_table))
8549 * Translate the input set from bit masks to register aware bit masks
8553 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8563 static const struct inset_map inset_map_common[] = {
8564 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8565 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8566 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8567 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8568 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8569 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8570 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8571 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8572 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8573 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8574 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8575 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8576 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8577 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8578 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8579 {I40E_INSET_TUNNEL_DMAC,
8580 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8581 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8582 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8583 {I40E_INSET_TUNNEL_SRC_PORT,
8584 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8585 {I40E_INSET_TUNNEL_DST_PORT,
8586 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8587 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8588 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8589 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8590 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8591 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8592 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8593 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8594 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8595 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8598 /* some different registers map in x722*/
8599 static const struct inset_map inset_map_diff_x722[] = {
8600 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8601 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8602 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8603 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8606 static const struct inset_map inset_map_diff_not_x722[] = {
8607 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8608 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8609 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8610 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8616 /* Translate input set to register aware inset */
8617 if (type == I40E_MAC_X722) {
8618 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8619 if (input & inset_map_diff_x722[i].inset)
8620 val |= inset_map_diff_x722[i].inset_reg;
8623 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8624 if (input & inset_map_diff_not_x722[i].inset)
8625 val |= inset_map_diff_not_x722[i].inset_reg;
8629 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8630 if (input & inset_map_common[i].inset)
8631 val |= inset_map_common[i].inset_reg;
8638 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8641 uint64_t inset_need_mask = inset;
8643 static const struct {
8646 } inset_mask_map[] = {
8647 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8648 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8649 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8650 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8651 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8652 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8653 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8654 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8657 if (!inset || !mask || !nb_elem)
8660 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8661 /* Clear the inset bit, if no MASK is required,
8662 * for example proto + ttl
8664 if ((inset & inset_mask_map[i].inset) ==
8665 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8666 inset_need_mask &= ~inset_mask_map[i].inset;
8667 if (!inset_need_mask)
8670 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8671 if ((inset_need_mask & inset_mask_map[i].inset) ==
8672 inset_mask_map[i].inset) {
8673 if (idx >= nb_elem) {
8674 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8677 mask[idx] = inset_mask_map[i].mask;
8686 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8688 uint32_t reg = i40e_read_rx_ctl(hw, addr);
8690 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8692 i40e_write_rx_ctl(hw, addr, val);
8693 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8694 (uint32_t)i40e_read_rx_ctl(hw, addr));
8698 i40e_filter_input_set_init(struct i40e_pf *pf)
8700 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8701 enum i40e_filter_pctype pctype;
8702 uint64_t input_set, inset_reg;
8703 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8707 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8708 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8709 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
8711 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
8714 input_set = i40e_get_default_input_set(pctype);
8716 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8717 I40E_INSET_MASK_NUM_REG);
8720 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8723 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8724 (uint32_t)(inset_reg & UINT32_MAX));
8725 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8726 (uint32_t)((inset_reg >>
8727 I40E_32_BIT_WIDTH) & UINT32_MAX));
8728 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8729 (uint32_t)(inset_reg & UINT32_MAX));
8730 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8731 (uint32_t)((inset_reg >>
8732 I40E_32_BIT_WIDTH) & UINT32_MAX));
8734 for (i = 0; i < num; i++) {
8735 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8737 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8740 /*clear unused mask registers of the pctype */
8741 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8742 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8744 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8747 I40E_WRITE_FLUSH(hw);
8749 /* store the default input set */
8750 pf->hash_input_set[pctype] = input_set;
8751 pf->fdir.input_set[pctype] = input_set;
8756 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8757 struct rte_eth_input_set_conf *conf)
8759 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8760 enum i40e_filter_pctype pctype;
8761 uint64_t input_set, inset_reg = 0;
8762 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8766 PMD_DRV_LOG(ERR, "Invalid pointer");
8769 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8770 conf->op != RTE_ETH_INPUT_SET_ADD) {
8771 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8775 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
8776 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
8777 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8781 if (hw->mac.type == I40E_MAC_X722) {
8782 /* get translated pctype value in fd pctype register */
8783 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8784 I40E_GLQF_FD_PCTYPES((int)pctype));
8787 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8790 PMD_DRV_LOG(ERR, "Failed to parse input set");
8794 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8795 /* get inset value in register */
8796 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8797 inset_reg <<= I40E_32_BIT_WIDTH;
8798 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8799 input_set |= pf->hash_input_set[pctype];
8801 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8802 I40E_INSET_MASK_NUM_REG);
8806 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8808 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8809 (uint32_t)(inset_reg & UINT32_MAX));
8810 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8811 (uint32_t)((inset_reg >>
8812 I40E_32_BIT_WIDTH) & UINT32_MAX));
8814 for (i = 0; i < num; i++)
8815 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8817 /*clear unused mask registers of the pctype */
8818 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8819 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8821 I40E_WRITE_FLUSH(hw);
8823 pf->hash_input_set[pctype] = input_set;
8828 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8829 struct rte_eth_input_set_conf *conf)
8831 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8832 enum i40e_filter_pctype pctype;
8833 uint64_t input_set, inset_reg = 0;
8834 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8838 PMD_DRV_LOG(ERR, "Invalid pointer");
8841 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8842 conf->op != RTE_ETH_INPUT_SET_ADD) {
8843 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8847 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
8849 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
8850 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8854 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8857 PMD_DRV_LOG(ERR, "Failed to parse input set");
8861 /* get inset value in register */
8862 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8863 inset_reg <<= I40E_32_BIT_WIDTH;
8864 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8866 /* Can not change the inset reg for flex payload for fdir,
8867 * it is done by writing I40E_PRTQF_FD_FLXINSET
8868 * in i40e_set_flex_mask_on_pctype.
8870 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8871 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8873 input_set |= pf->fdir.input_set[pctype];
8874 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8875 I40E_INSET_MASK_NUM_REG);
8879 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8881 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8882 (uint32_t)(inset_reg & UINT32_MAX));
8883 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8884 (uint32_t)((inset_reg >>
8885 I40E_32_BIT_WIDTH) & UINT32_MAX));
8887 for (i = 0; i < num; i++)
8888 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8890 /*clear unused mask registers of the pctype */
8891 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8892 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8894 I40E_WRITE_FLUSH(hw);
8896 pf->fdir.input_set[pctype] = input_set;
8901 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8906 PMD_DRV_LOG(ERR, "Invalid pointer");
8910 switch (info->info_type) {
8911 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8912 i40e_get_symmetric_hash_enable_per_port(hw,
8913 &(info->info.enable));
8915 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8916 ret = i40e_get_hash_filter_global_config(hw,
8917 &(info->info.global_conf));
8920 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8930 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8935 PMD_DRV_LOG(ERR, "Invalid pointer");
8939 switch (info->info_type) {
8940 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8941 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8943 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8944 ret = i40e_set_hash_filter_global_config(hw,
8945 &(info->info.global_conf));
8947 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8948 ret = i40e_hash_filter_inset_select(hw,
8949 &(info->info.input_set_conf));
8953 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8962 /* Operations for hash function */
8964 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8965 enum rte_filter_op filter_op,
8968 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8971 switch (filter_op) {
8972 case RTE_ETH_FILTER_NOP:
8974 case RTE_ETH_FILTER_GET:
8975 ret = i40e_hash_filter_get(hw,
8976 (struct rte_eth_hash_filter_info *)arg);
8978 case RTE_ETH_FILTER_SET:
8979 ret = i40e_hash_filter_set(hw,
8980 (struct rte_eth_hash_filter_info *)arg);
8983 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8992 /* Convert ethertype filter structure */
8994 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8995 struct i40e_ethertype_filter *filter)
8997 rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8998 filter->input.ether_type = input->ether_type;
8999 filter->flags = input->flags;
9000 filter->queue = input->queue;
9005 /* Check if there exists the ehtertype filter */
9006 struct i40e_ethertype_filter *
9007 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9008 const struct i40e_ethertype_filter_input *input)
9012 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9016 return ethertype_rule->hash_map[ret];
9019 /* Add ethertype filter in SW list */
9021 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9022 struct i40e_ethertype_filter *filter)
9024 struct i40e_ethertype_rule *rule = &pf->ethertype;
9027 ret = rte_hash_add_key(rule->hash_table, &filter->input);
9030 "Failed to insert ethertype filter"
9031 " to hash table %d!",
9035 rule->hash_map[ret] = filter;
9037 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9042 /* Delete ethertype filter in SW list */
9044 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9045 struct i40e_ethertype_filter_input *input)
9047 struct i40e_ethertype_rule *rule = &pf->ethertype;
9048 struct i40e_ethertype_filter *filter;
9051 ret = rte_hash_del_key(rule->hash_table, input);
9054 "Failed to delete ethertype filter"
9055 " to hash table %d!",
9059 filter = rule->hash_map[ret];
9060 rule->hash_map[ret] = NULL;
9062 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9069 * Configure ethertype filter, which can director packet by filtering
9070 * with mac address and ether_type or only ether_type
9073 i40e_ethertype_filter_set(struct i40e_pf *pf,
9074 struct rte_eth_ethertype_filter *filter,
9077 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9078 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9079 struct i40e_ethertype_filter *ethertype_filter, *node;
9080 struct i40e_ethertype_filter check_filter;
9081 struct i40e_control_filter_stats stats;
9085 if (filter->queue >= pf->dev_data->nb_rx_queues) {
9086 PMD_DRV_LOG(ERR, "Invalid queue ID");
9089 if (filter->ether_type == ETHER_TYPE_IPv4 ||
9090 filter->ether_type == ETHER_TYPE_IPv6) {
9092 "unsupported ether_type(0x%04x) in control packet filter.",
9093 filter->ether_type);
9096 if (filter->ether_type == ETHER_TYPE_VLAN)
9097 PMD_DRV_LOG(WARNING,
9098 "filter vlan ether_type in first tag is not supported.");
9100 /* Check if there is the filter in SW list */
9101 memset(&check_filter, 0, sizeof(check_filter));
9102 i40e_ethertype_filter_convert(filter, &check_filter);
9103 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9104 &check_filter.input);
9106 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9110 if (!add && !node) {
9111 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9115 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9116 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9117 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9118 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9119 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9121 memset(&stats, 0, sizeof(stats));
9122 ret = i40e_aq_add_rem_control_packet_filter(hw,
9123 filter->mac_addr.addr_bytes,
9124 filter->ether_type, flags,
9126 filter->queue, add, &stats, NULL);
9129 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9130 ret, stats.mac_etype_used, stats.etype_used,
9131 stats.mac_etype_free, stats.etype_free);
9135 /* Add or delete a filter in SW list */
9137 ethertype_filter = rte_zmalloc("ethertype_filter",
9138 sizeof(*ethertype_filter), 0);
9139 rte_memcpy(ethertype_filter, &check_filter,
9140 sizeof(check_filter));
9141 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9143 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9150 * Handle operations for ethertype filter.
9153 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9154 enum rte_filter_op filter_op,
9157 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9160 if (filter_op == RTE_ETH_FILTER_NOP)
9164 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9169 switch (filter_op) {
9170 case RTE_ETH_FILTER_ADD:
9171 ret = i40e_ethertype_filter_set(pf,
9172 (struct rte_eth_ethertype_filter *)arg,
9175 case RTE_ETH_FILTER_DELETE:
9176 ret = i40e_ethertype_filter_set(pf,
9177 (struct rte_eth_ethertype_filter *)arg,
9181 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9189 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9190 enum rte_filter_type filter_type,
9191 enum rte_filter_op filter_op,
9199 switch (filter_type) {
9200 case RTE_ETH_FILTER_NONE:
9201 /* For global configuration */
9202 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9204 case RTE_ETH_FILTER_HASH:
9205 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9207 case RTE_ETH_FILTER_MACVLAN:
9208 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9210 case RTE_ETH_FILTER_ETHERTYPE:
9211 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9213 case RTE_ETH_FILTER_TUNNEL:
9214 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9216 case RTE_ETH_FILTER_FDIR:
9217 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9219 case RTE_ETH_FILTER_GENERIC:
9220 if (filter_op != RTE_ETH_FILTER_GET)
9222 *(const void **)arg = &i40e_flow_ops;
9225 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9235 * Check and enable Extended Tag.
9236 * Enabling Extended Tag is important for 40G performance.
9239 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9241 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9245 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9248 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9252 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9253 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9258 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9261 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9265 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9266 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9269 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9270 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9273 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9280 * As some registers wouldn't be reset unless a global hardware reset,
9281 * hardware initialization is needed to put those registers into an
9282 * expected initial state.
9285 i40e_hw_init(struct rte_eth_dev *dev)
9287 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9289 i40e_enable_extended_tag(dev);
9291 /* clear the PF Queue Filter control register */
9292 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9294 /* Disable symmetric hash per port */
9295 i40e_set_symmetric_hash_enable_per_port(hw, 0);
9299 * For X722 it is possible to have multiple pctypes mapped to the same flowtype
9300 * however this function will return only one highest pctype index,
9301 * which is not quite correct. This is known problem of i40e driver
9302 * and needs to be fixed later.
9304 enum i40e_filter_pctype
9305 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
9308 uint64_t pctype_mask;
9310 if (flow_type < I40E_FLOW_TYPE_MAX) {
9311 pctype_mask = adapter->pctypes_tbl[flow_type];
9312 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
9313 if (pctype_mask & (1ULL << i))
9314 return (enum i40e_filter_pctype)i;
9317 return I40E_FILTER_PCTYPE_INVALID;
9321 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
9322 enum i40e_filter_pctype pctype)
9325 uint64_t pctype_mask = 1ULL << pctype;
9327 for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
9329 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
9333 return RTE_ETH_FLOW_UNKNOWN;
9337 * On X710, performance number is far from the expectation on recent firmware
9338 * versions; on XL710, performance number is also far from the expectation on
9339 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9340 * mode is enabled and port MAC address is equal to the packet destination MAC
9341 * address. The fix for this issue may not be integrated in the following
9342 * firmware version. So the workaround in software driver is needed. It needs
9343 * to modify the initial values of 3 internal only registers for both X710 and
9344 * XL710. Note that the values for X710 or XL710 could be different, and the
9345 * workaround can be removed when it is fixed in firmware in the future.
9348 /* For both X710 and XL710 */
9349 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1 0x10000200
9350 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x20000200
9351 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
9353 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9354 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
9357 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9358 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9361 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
9363 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
9364 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
9367 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9369 enum i40e_status_code status;
9370 struct i40e_aq_get_phy_abilities_resp phy_ab;
9374 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9378 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
9381 rte_delay_us(100000);
9383 status = i40e_aq_get_phy_capabilities(hw, false,
9384 true, &phy_ab, NULL);
9392 i40e_configure_registers(struct i40e_hw *hw)
9398 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9399 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9400 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9406 for (i = 0; i < RTE_DIM(reg_table); i++) {
9407 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9408 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9410 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9411 else /* For X710/XL710/XXV710 */
9412 if (hw->aq.fw_maj_ver < 6)
9414 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
9417 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
9420 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9421 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9423 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9424 else /* For X710/XL710/XXV710 */
9426 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9429 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9430 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9431 I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9433 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9436 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9439 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9442 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9446 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9447 reg_table[i].addr, reg);
9448 if (reg == reg_table[i].val)
9451 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9452 reg_table[i].val, NULL);
9455 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9456 reg_table[i].val, reg_table[i].addr);
9459 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9460 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9464 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
9465 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
9466 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
9467 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9469 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9474 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9475 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9479 /* Configure for double VLAN RX stripping */
9480 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9481 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9482 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9483 ret = i40e_aq_debug_write_register(hw,
9484 I40E_VSI_TSR(vsi->vsi_id),
9487 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9489 return I40E_ERR_CONFIG;
9493 /* Configure for double VLAN TX insertion */
9494 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9495 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9496 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9497 ret = i40e_aq_debug_write_register(hw,
9498 I40E_VSI_L2TAGSTXVALID(
9499 vsi->vsi_id), reg, NULL);
9502 "Failed to update VSI_L2TAGSTXVALID[%d]",
9504 return I40E_ERR_CONFIG;
9512 * i40e_aq_add_mirror_rule
9513 * @hw: pointer to the hardware structure
9514 * @seid: VEB seid to add mirror rule to
9515 * @dst_id: destination vsi seid
9516 * @entries: Buffer which contains the entities to be mirrored
9517 * @count: number of entities contained in the buffer
9518 * @rule_id:the rule_id of the rule to be added
9520 * Add a mirror rule for a given veb.
9523 static enum i40e_status_code
9524 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9525 uint16_t seid, uint16_t dst_id,
9526 uint16_t rule_type, uint16_t *entries,
9527 uint16_t count, uint16_t *rule_id)
9529 struct i40e_aq_desc desc;
9530 struct i40e_aqc_add_delete_mirror_rule cmd;
9531 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9532 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9535 enum i40e_status_code status;
9537 i40e_fill_default_direct_cmd_desc(&desc,
9538 i40e_aqc_opc_add_mirror_rule);
9539 memset(&cmd, 0, sizeof(cmd));
9541 buff_len = sizeof(uint16_t) * count;
9542 desc.datalen = rte_cpu_to_le_16(buff_len);
9544 desc.flags |= rte_cpu_to_le_16(
9545 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9546 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9547 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9548 cmd.num_entries = rte_cpu_to_le_16(count);
9549 cmd.seid = rte_cpu_to_le_16(seid);
9550 cmd.destination = rte_cpu_to_le_16(dst_id);
9552 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9553 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9555 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9556 hw->aq.asq_last_status, resp->rule_id,
9557 resp->mirror_rules_used, resp->mirror_rules_free);
9558 *rule_id = rte_le_to_cpu_16(resp->rule_id);
9564 * i40e_aq_del_mirror_rule
9565 * @hw: pointer to the hardware structure
9566 * @seid: VEB seid to add mirror rule to
9567 * @entries: Buffer which contains the entities to be mirrored
9568 * @count: number of entities contained in the buffer
9569 * @rule_id:the rule_id of the rule to be delete
9571 * Delete a mirror rule for a given veb.
9574 static enum i40e_status_code
9575 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9576 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9577 uint16_t count, uint16_t rule_id)
9579 struct i40e_aq_desc desc;
9580 struct i40e_aqc_add_delete_mirror_rule cmd;
9581 uint16_t buff_len = 0;
9582 enum i40e_status_code status;
9585 i40e_fill_default_direct_cmd_desc(&desc,
9586 i40e_aqc_opc_delete_mirror_rule);
9587 memset(&cmd, 0, sizeof(cmd));
9588 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9589 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9591 cmd.num_entries = count;
9592 buff_len = sizeof(uint16_t) * count;
9593 desc.datalen = rte_cpu_to_le_16(buff_len);
9594 buff = (void *)entries;
9596 /* rule id is filled in destination field for deleting mirror rule */
9597 cmd.destination = rte_cpu_to_le_16(rule_id);
9599 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9600 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9601 cmd.seid = rte_cpu_to_le_16(seid);
9603 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9604 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9610 * i40e_mirror_rule_set
9611 * @dev: pointer to the hardware structure
9612 * @mirror_conf: mirror rule info
9613 * @sw_id: mirror rule's sw_id
9614 * @on: enable/disable
9616 * set a mirror rule.
9620 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9621 struct rte_eth_mirror_conf *mirror_conf,
9622 uint8_t sw_id, uint8_t on)
9624 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9625 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9626 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9627 struct i40e_mirror_rule *parent = NULL;
9628 uint16_t seid, dst_seid, rule_id;
9632 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9634 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9636 "mirror rule can not be configured without veb or vfs.");
9639 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9640 PMD_DRV_LOG(ERR, "mirror table is full.");
9643 if (mirror_conf->dst_pool > pf->vf_num) {
9644 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9645 mirror_conf->dst_pool);
9649 seid = pf->main_vsi->veb->seid;
9651 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9652 if (sw_id <= it->index) {
9658 if (mirr_rule && sw_id == mirr_rule->index) {
9660 PMD_DRV_LOG(ERR, "mirror rule exists.");
9663 ret = i40e_aq_del_mirror_rule(hw, seid,
9664 mirr_rule->rule_type,
9666 mirr_rule->num_entries, mirr_rule->id);
9669 "failed to remove mirror rule: ret = %d, aq_err = %d.",
9670 ret, hw->aq.asq_last_status);
9673 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9674 rte_free(mirr_rule);
9675 pf->nb_mirror_rule--;
9679 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9683 mirr_rule = rte_zmalloc("i40e_mirror_rule",
9684 sizeof(struct i40e_mirror_rule) , 0);
9686 PMD_DRV_LOG(ERR, "failed to allocate memory");
9687 return I40E_ERR_NO_MEMORY;
9689 switch (mirror_conf->rule_type) {
9690 case ETH_MIRROR_VLAN:
9691 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9692 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9693 mirr_rule->entries[j] =
9694 mirror_conf->vlan.vlan_id[i];
9699 PMD_DRV_LOG(ERR, "vlan is not specified.");
9700 rte_free(mirr_rule);
9703 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9705 case ETH_MIRROR_VIRTUAL_POOL_UP:
9706 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9707 /* check if the specified pool bit is out of range */
9708 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9709 PMD_DRV_LOG(ERR, "pool mask is out of range.");
9710 rte_free(mirr_rule);
9713 for (i = 0, j = 0; i < pf->vf_num; i++) {
9714 if (mirror_conf->pool_mask & (1ULL << i)) {
9715 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9719 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9720 /* add pf vsi to entries */
9721 mirr_rule->entries[j] = pf->main_vsi_seid;
9725 PMD_DRV_LOG(ERR, "pool is not specified.");
9726 rte_free(mirr_rule);
9729 /* egress and ingress in aq commands means from switch but not port */
9730 mirr_rule->rule_type =
9731 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9732 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9733 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9735 case ETH_MIRROR_UPLINK_PORT:
9736 /* egress and ingress in aq commands means from switch but not port*/
9737 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9739 case ETH_MIRROR_DOWNLINK_PORT:
9740 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9743 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9744 mirror_conf->rule_type);
9745 rte_free(mirr_rule);
9749 /* If the dst_pool is equal to vf_num, consider it as PF */
9750 if (mirror_conf->dst_pool == pf->vf_num)
9751 dst_seid = pf->main_vsi_seid;
9753 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9755 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9756 mirr_rule->rule_type, mirr_rule->entries,
9760 "failed to add mirror rule: ret = %d, aq_err = %d.",
9761 ret, hw->aq.asq_last_status);
9762 rte_free(mirr_rule);
9766 mirr_rule->index = sw_id;
9767 mirr_rule->num_entries = j;
9768 mirr_rule->id = rule_id;
9769 mirr_rule->dst_vsi_seid = dst_seid;
9772 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9774 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9776 pf->nb_mirror_rule++;
9781 * i40e_mirror_rule_reset
9782 * @dev: pointer to the device
9783 * @sw_id: mirror rule's sw_id
9785 * reset a mirror rule.
9789 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9791 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9792 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9793 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9797 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9799 seid = pf->main_vsi->veb->seid;
9801 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9802 if (sw_id == it->index) {
9808 ret = i40e_aq_del_mirror_rule(hw, seid,
9809 mirr_rule->rule_type,
9811 mirr_rule->num_entries, mirr_rule->id);
9814 "failed to remove mirror rule: status = %d, aq_err = %d.",
9815 ret, hw->aq.asq_last_status);
9818 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9819 rte_free(mirr_rule);
9820 pf->nb_mirror_rule--;
9822 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9829 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9831 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9832 uint64_t systim_cycles;
9834 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9835 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9838 return systim_cycles;
9842 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9844 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9847 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9848 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9855 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9857 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9860 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9861 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9868 i40e_start_timecounters(struct rte_eth_dev *dev)
9870 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9871 struct i40e_adapter *adapter =
9872 (struct i40e_adapter *)dev->data->dev_private;
9873 struct rte_eth_link link;
9874 uint32_t tsync_inc_l;
9875 uint32_t tsync_inc_h;
9877 /* Get current link speed. */
9878 memset(&link, 0, sizeof(link));
9879 i40e_dev_link_update(dev, 1);
9880 rte_i40e_dev_atomic_read_link_status(dev, &link);
9882 switch (link.link_speed) {
9883 case ETH_SPEED_NUM_40G:
9884 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9885 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9887 case ETH_SPEED_NUM_10G:
9888 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9889 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9891 case ETH_SPEED_NUM_1G:
9892 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9893 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9900 /* Set the timesync increment value. */
9901 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9902 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9904 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9905 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9906 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9908 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9909 adapter->systime_tc.cc_shift = 0;
9910 adapter->systime_tc.nsec_mask = 0;
9912 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9913 adapter->rx_tstamp_tc.cc_shift = 0;
9914 adapter->rx_tstamp_tc.nsec_mask = 0;
9916 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9917 adapter->tx_tstamp_tc.cc_shift = 0;
9918 adapter->tx_tstamp_tc.nsec_mask = 0;
9922 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9924 struct i40e_adapter *adapter =
9925 (struct i40e_adapter *)dev->data->dev_private;
9927 adapter->systime_tc.nsec += delta;
9928 adapter->rx_tstamp_tc.nsec += delta;
9929 adapter->tx_tstamp_tc.nsec += delta;
9935 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9938 struct i40e_adapter *adapter =
9939 (struct i40e_adapter *)dev->data->dev_private;
9941 ns = rte_timespec_to_ns(ts);
9943 /* Set the timecounters to a new value. */
9944 adapter->systime_tc.nsec = ns;
9945 adapter->rx_tstamp_tc.nsec = ns;
9946 adapter->tx_tstamp_tc.nsec = ns;
9952 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9954 uint64_t ns, systime_cycles;
9955 struct i40e_adapter *adapter =
9956 (struct i40e_adapter *)dev->data->dev_private;
9958 systime_cycles = i40e_read_systime_cyclecounter(dev);
9959 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9960 *ts = rte_ns_to_timespec(ns);
9966 i40e_timesync_enable(struct rte_eth_dev *dev)
9968 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9969 uint32_t tsync_ctl_l;
9970 uint32_t tsync_ctl_h;
9972 /* Stop the timesync system time. */
9973 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9974 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9975 /* Reset the timesync system time value. */
9976 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9977 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9979 i40e_start_timecounters(dev);
9981 /* Clear timesync registers. */
9982 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9983 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9984 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9985 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9986 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9987 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9989 /* Enable timestamping of PTP packets. */
9990 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9991 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9993 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9994 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9995 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9997 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9998 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10004 i40e_timesync_disable(struct rte_eth_dev *dev)
10006 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10007 uint32_t tsync_ctl_l;
10008 uint32_t tsync_ctl_h;
10010 /* Disable timestamping of transmitted PTP packets. */
10011 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10012 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10014 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10015 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10017 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10018 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10020 /* Reset the timesync increment value. */
10021 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10022 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10028 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10029 struct timespec *timestamp, uint32_t flags)
10031 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10032 struct i40e_adapter *adapter =
10033 (struct i40e_adapter *)dev->data->dev_private;
10035 uint32_t sync_status;
10036 uint32_t index = flags & 0x03;
10037 uint64_t rx_tstamp_cycles;
10040 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10041 if ((sync_status & (1 << index)) == 0)
10044 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10045 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10046 *timestamp = rte_ns_to_timespec(ns);
10052 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10053 struct timespec *timestamp)
10055 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10056 struct i40e_adapter *adapter =
10057 (struct i40e_adapter *)dev->data->dev_private;
10059 uint32_t sync_status;
10060 uint64_t tx_tstamp_cycles;
10063 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10064 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10067 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10068 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10069 *timestamp = rte_ns_to_timespec(ns);
10075 * i40e_parse_dcb_configure - parse dcb configure from user
10076 * @dev: the device being configured
10077 * @dcb_cfg: pointer of the result of parse
10078 * @*tc_map: bit map of enabled traffic classes
10080 * Returns 0 on success, negative value on failure
10083 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10084 struct i40e_dcbx_config *dcb_cfg,
10087 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10088 uint8_t i, tc_bw, bw_lf;
10090 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10092 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10093 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10094 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10098 /* assume each tc has the same bw */
10099 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10100 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10101 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10102 /* to ensure the sum of tcbw is equal to 100 */
10103 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10104 for (i = 0; i < bw_lf; i++)
10105 dcb_cfg->etscfg.tcbwtable[i]++;
10107 /* assume each tc has the same Transmission Selection Algorithm */
10108 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10109 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10111 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10112 dcb_cfg->etscfg.prioritytable[i] =
10113 dcb_rx_conf->dcb_tc[i];
10115 /* FW needs one App to configure HW */
10116 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10117 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10118 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10119 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10121 if (dcb_rx_conf->nb_tcs == 0)
10122 *tc_map = 1; /* tc0 only */
10124 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10126 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10127 dcb_cfg->pfc.willing = 0;
10128 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10129 dcb_cfg->pfc.pfcenable = *tc_map;
10135 static enum i40e_status_code
10136 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10137 struct i40e_aqc_vsi_properties_data *info,
10138 uint8_t enabled_tcmap)
10140 enum i40e_status_code ret;
10141 int i, total_tc = 0;
10142 uint16_t qpnum_per_tc, bsf, qp_idx;
10143 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10144 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10145 uint16_t used_queues;
10147 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10148 if (ret != I40E_SUCCESS)
10151 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10152 if (enabled_tcmap & (1 << i))
10157 vsi->enabled_tc = enabled_tcmap;
10159 /* different VSI has different queues assigned */
10160 if (vsi->type == I40E_VSI_MAIN)
10161 used_queues = dev_data->nb_rx_queues -
10162 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10163 else if (vsi->type == I40E_VSI_VMDQ2)
10164 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10166 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10167 return I40E_ERR_NO_AVAILABLE_VSI;
10170 qpnum_per_tc = used_queues / total_tc;
10171 /* Number of queues per enabled TC */
10172 if (qpnum_per_tc == 0) {
10173 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10174 return I40E_ERR_INVALID_QP_ID;
10176 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10177 I40E_MAX_Q_PER_TC);
10178 bsf = rte_bsf32(qpnum_per_tc);
10181 * Configure TC and queue mapping parameters, for enabled TC,
10182 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10183 * default queue will serve it.
10186 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10187 if (vsi->enabled_tc & (1 << i)) {
10188 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10189 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10190 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10191 qp_idx += qpnum_per_tc;
10193 info->tc_mapping[i] = 0;
10196 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10197 if (vsi->type == I40E_VSI_SRIOV) {
10198 info->mapping_flags |=
10199 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10200 for (i = 0; i < vsi->nb_qps; i++)
10201 info->queue_mapping[i] =
10202 rte_cpu_to_le_16(vsi->base_queue + i);
10204 info->mapping_flags |=
10205 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10206 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10208 info->valid_sections |=
10209 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10211 return I40E_SUCCESS;
10215 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10216 * @veb: VEB to be configured
10217 * @tc_map: enabled TC bitmap
10219 * Returns 0 on success, negative value on failure
10221 static enum i40e_status_code
10222 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10224 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10225 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10226 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10227 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10228 enum i40e_status_code ret = I40E_SUCCESS;
10232 /* Check if enabled_tc is same as existing or new TCs */
10233 if (veb->enabled_tc == tc_map)
10236 /* configure tc bandwidth */
10237 memset(&veb_bw, 0, sizeof(veb_bw));
10238 veb_bw.tc_valid_bits = tc_map;
10239 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10240 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10241 if (tc_map & BIT_ULL(i))
10242 veb_bw.tc_bw_share_credits[i] = 1;
10244 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10248 "AQ command Config switch_comp BW allocation per TC failed = %d",
10249 hw->aq.asq_last_status);
10253 memset(&ets_query, 0, sizeof(ets_query));
10254 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10256 if (ret != I40E_SUCCESS) {
10258 "Failed to get switch_comp ETS configuration %u",
10259 hw->aq.asq_last_status);
10262 memset(&bw_query, 0, sizeof(bw_query));
10263 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10265 if (ret != I40E_SUCCESS) {
10267 "Failed to get switch_comp bandwidth configuration %u",
10268 hw->aq.asq_last_status);
10272 /* store and print out BW info */
10273 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10274 veb->bw_info.bw_max = ets_query.tc_bw_max;
10275 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10276 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10277 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10278 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10279 I40E_16_BIT_WIDTH);
10280 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10281 veb->bw_info.bw_ets_share_credits[i] =
10282 bw_query.tc_bw_share_credits[i];
10283 veb->bw_info.bw_ets_credits[i] =
10284 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10285 /* 4 bits per TC, 4th bit is reserved */
10286 veb->bw_info.bw_ets_max[i] =
10287 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10288 RTE_LEN2MASK(3, uint8_t));
10289 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10290 veb->bw_info.bw_ets_share_credits[i]);
10291 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10292 veb->bw_info.bw_ets_credits[i]);
10293 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10294 veb->bw_info.bw_ets_max[i]);
10297 veb->enabled_tc = tc_map;
10304 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10305 * @vsi: VSI to be configured
10306 * @tc_map: enabled TC bitmap
10308 * Returns 0 on success, negative value on failure
10310 static enum i40e_status_code
10311 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10313 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10314 struct i40e_vsi_context ctxt;
10315 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10316 enum i40e_status_code ret = I40E_SUCCESS;
10319 /* Check if enabled_tc is same as existing or new TCs */
10320 if (vsi->enabled_tc == tc_map)
10323 /* configure tc bandwidth */
10324 memset(&bw_data, 0, sizeof(bw_data));
10325 bw_data.tc_valid_bits = tc_map;
10326 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10327 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10328 if (tc_map & BIT_ULL(i))
10329 bw_data.tc_bw_credits[i] = 1;
10331 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10334 "AQ command Config VSI BW allocation per TC failed = %d",
10335 hw->aq.asq_last_status);
10338 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10339 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10341 /* Update Queue Pairs Mapping for currently enabled UPs */
10342 ctxt.seid = vsi->seid;
10343 ctxt.pf_num = hw->pf_id;
10345 ctxt.uplink_seid = vsi->uplink_seid;
10346 ctxt.info = vsi->info;
10348 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10352 /* Update the VSI after updating the VSI queue-mapping information */
10353 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10355 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10356 hw->aq.asq_last_status);
10359 /* update the local VSI info with updated queue map */
10360 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10361 sizeof(vsi->info.tc_mapping));
10362 rte_memcpy(&vsi->info.queue_mapping,
10363 &ctxt.info.queue_mapping,
10364 sizeof(vsi->info.queue_mapping));
10365 vsi->info.mapping_flags = ctxt.info.mapping_flags;
10366 vsi->info.valid_sections = 0;
10368 /* query and update current VSI BW information */
10369 ret = i40e_vsi_get_bw_config(vsi);
10372 "Failed updating vsi bw info, err %s aq_err %s",
10373 i40e_stat_str(hw, ret),
10374 i40e_aq_str(hw, hw->aq.asq_last_status));
10378 vsi->enabled_tc = tc_map;
10385 * i40e_dcb_hw_configure - program the dcb setting to hw
10386 * @pf: pf the configuration is taken on
10387 * @new_cfg: new configuration
10388 * @tc_map: enabled TC bitmap
10390 * Returns 0 on success, negative value on failure
10392 static enum i40e_status_code
10393 i40e_dcb_hw_configure(struct i40e_pf *pf,
10394 struct i40e_dcbx_config *new_cfg,
10397 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10398 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10399 struct i40e_vsi *main_vsi = pf->main_vsi;
10400 struct i40e_vsi_list *vsi_list;
10401 enum i40e_status_code ret;
10405 /* Use the FW API if FW > v4.4*/
10406 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10407 (hw->aq.fw_maj_ver >= 5))) {
10409 "FW < v4.4, can not use FW LLDP API to configure DCB");
10410 return I40E_ERR_FIRMWARE_API_VERSION;
10413 /* Check if need reconfiguration */
10414 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10415 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10416 return I40E_SUCCESS;
10419 /* Copy the new config to the current config */
10420 *old_cfg = *new_cfg;
10421 old_cfg->etsrec = old_cfg->etscfg;
10422 ret = i40e_set_dcb_config(hw);
10424 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10425 i40e_stat_str(hw, ret),
10426 i40e_aq_str(hw, hw->aq.asq_last_status));
10429 /* set receive Arbiter to RR mode and ETS scheme by default */
10430 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10431 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10432 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
10433 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10434 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10435 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10436 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10437 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10438 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10439 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10440 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10441 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10442 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10444 /* get local mib to check whether it is configured correctly */
10446 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10447 /* Get Local DCB Config */
10448 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10449 &hw->local_dcbx_config);
10451 /* if Veb is created, need to update TC of it at first */
10452 if (main_vsi->veb) {
10453 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10455 PMD_INIT_LOG(WARNING,
10456 "Failed configuring TC for VEB seid=%d",
10457 main_vsi->veb->seid);
10459 /* Update each VSI */
10460 i40e_vsi_config_tc(main_vsi, tc_map);
10461 if (main_vsi->veb) {
10462 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10463 /* Beside main VSI and VMDQ VSIs, only enable default
10464 * TC for other VSIs
10466 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10467 ret = i40e_vsi_config_tc(vsi_list->vsi,
10470 ret = i40e_vsi_config_tc(vsi_list->vsi,
10471 I40E_DEFAULT_TCMAP);
10473 PMD_INIT_LOG(WARNING,
10474 "Failed configuring TC for VSI seid=%d",
10475 vsi_list->vsi->seid);
10479 return I40E_SUCCESS;
10483 * i40e_dcb_init_configure - initial dcb config
10484 * @dev: device being configured
10485 * @sw_dcb: indicate whether dcb is sw configured or hw offload
10487 * Returns 0 on success, negative value on failure
10490 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10492 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10493 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10496 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10497 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10501 /* DCB initialization:
10502 * Update DCB configuration from the Firmware and configure
10503 * LLDP MIB change event.
10505 if (sw_dcb == TRUE) {
10506 ret = i40e_init_dcb(hw);
10507 /* If lldp agent is stopped, the return value from
10508 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10509 * adminq status. Otherwise, it should return success.
10511 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10512 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10513 memset(&hw->local_dcbx_config, 0,
10514 sizeof(struct i40e_dcbx_config));
10515 /* set dcb default configuration */
10516 hw->local_dcbx_config.etscfg.willing = 0;
10517 hw->local_dcbx_config.etscfg.maxtcs = 0;
10518 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10519 hw->local_dcbx_config.etscfg.tsatable[0] =
10521 /* all UPs mapping to TC0 */
10522 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10523 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10524 hw->local_dcbx_config.etsrec =
10525 hw->local_dcbx_config.etscfg;
10526 hw->local_dcbx_config.pfc.willing = 0;
10527 hw->local_dcbx_config.pfc.pfccap =
10528 I40E_MAX_TRAFFIC_CLASS;
10529 /* FW needs one App to configure HW */
10530 hw->local_dcbx_config.numapps = 1;
10531 hw->local_dcbx_config.app[0].selector =
10532 I40E_APP_SEL_ETHTYPE;
10533 hw->local_dcbx_config.app[0].priority = 3;
10534 hw->local_dcbx_config.app[0].protocolid =
10535 I40E_APP_PROTOID_FCOE;
10536 ret = i40e_set_dcb_config(hw);
10539 "default dcb config fails. err = %d, aq_err = %d.",
10540 ret, hw->aq.asq_last_status);
10545 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10546 ret, hw->aq.asq_last_status);
10550 ret = i40e_aq_start_lldp(hw, NULL);
10551 if (ret != I40E_SUCCESS)
10552 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10554 ret = i40e_init_dcb(hw);
10556 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10558 "HW doesn't support DCBX offload.");
10563 "DCBX configuration failed, err = %d, aq_err = %d.",
10564 ret, hw->aq.asq_last_status);
10572 * i40e_dcb_setup - setup dcb related config
10573 * @dev: device being configured
10575 * Returns 0 on success, negative value on failure
10578 i40e_dcb_setup(struct rte_eth_dev *dev)
10580 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10581 struct i40e_dcbx_config dcb_cfg;
10582 uint8_t tc_map = 0;
10585 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10586 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10590 if (pf->vf_num != 0)
10591 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10593 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10595 PMD_INIT_LOG(ERR, "invalid dcb config");
10598 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10600 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10608 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10609 struct rte_eth_dcb_info *dcb_info)
10611 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10612 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10613 struct i40e_vsi *vsi = pf->main_vsi;
10614 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10615 uint16_t bsf, tc_mapping;
10618 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10619 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10621 dcb_info->nb_tcs = 1;
10622 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10623 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10624 for (i = 0; i < dcb_info->nb_tcs; i++)
10625 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10627 /* get queue mapping if vmdq is disabled */
10628 if (!pf->nb_cfg_vmdq_vsi) {
10629 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10630 if (!(vsi->enabled_tc & (1 << i)))
10632 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10633 dcb_info->tc_queue.tc_rxq[j][i].base =
10634 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10635 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10636 dcb_info->tc_queue.tc_txq[j][i].base =
10637 dcb_info->tc_queue.tc_rxq[j][i].base;
10638 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10639 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10640 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10641 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10642 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10647 /* get queue mapping if vmdq is enabled */
10649 vsi = pf->vmdq[j].vsi;
10650 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10651 if (!(vsi->enabled_tc & (1 << i)))
10653 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10654 dcb_info->tc_queue.tc_rxq[j][i].base =
10655 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10656 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10657 dcb_info->tc_queue.tc_txq[j][i].base =
10658 dcb_info->tc_queue.tc_rxq[j][i].base;
10659 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10660 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10661 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10662 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10663 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10666 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10671 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10673 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10674 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10675 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10676 uint16_t interval =
10677 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10678 uint16_t msix_intr;
10680 msix_intr = intr_handle->intr_vec[queue_id];
10681 if (msix_intr == I40E_MISC_VEC_ID)
10682 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10683 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10684 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10685 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10687 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10690 I40E_PFINT_DYN_CTLN(msix_intr -
10691 I40E_RX_VEC_START),
10692 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10693 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10694 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10696 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10698 I40E_WRITE_FLUSH(hw);
10699 rte_intr_enable(&pci_dev->intr_handle);
10705 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10707 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10708 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10709 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10710 uint16_t msix_intr;
10712 msix_intr = intr_handle->intr_vec[queue_id];
10713 if (msix_intr == I40E_MISC_VEC_ID)
10714 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10717 I40E_PFINT_DYN_CTLN(msix_intr -
10718 I40E_RX_VEC_START),
10720 I40E_WRITE_FLUSH(hw);
10725 static int i40e_get_regs(struct rte_eth_dev *dev,
10726 struct rte_dev_reg_info *regs)
10728 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10729 uint32_t *ptr_data = regs->data;
10730 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10731 const struct i40e_reg_info *reg_info;
10733 if (ptr_data == NULL) {
10734 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10735 regs->width = sizeof(uint32_t);
10739 /* The first few registers have to be read using AQ operations */
10741 while (i40e_regs_adminq[reg_idx].name) {
10742 reg_info = &i40e_regs_adminq[reg_idx++];
10743 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10745 arr_idx2 <= reg_info->count2;
10747 reg_offset = arr_idx * reg_info->stride1 +
10748 arr_idx2 * reg_info->stride2;
10749 reg_offset += reg_info->base_addr;
10750 ptr_data[reg_offset >> 2] =
10751 i40e_read_rx_ctl(hw, reg_offset);
10755 /* The remaining registers can be read using primitives */
10757 while (i40e_regs_others[reg_idx].name) {
10758 reg_info = &i40e_regs_others[reg_idx++];
10759 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10761 arr_idx2 <= reg_info->count2;
10763 reg_offset = arr_idx * reg_info->stride1 +
10764 arr_idx2 * reg_info->stride2;
10765 reg_offset += reg_info->base_addr;
10766 ptr_data[reg_offset >> 2] =
10767 I40E_READ_REG(hw, reg_offset);
10774 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10776 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10778 /* Convert word count to byte count */
10779 return hw->nvm.sr_size << 1;
10782 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10783 struct rte_dev_eeprom_info *eeprom)
10785 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10786 uint16_t *data = eeprom->data;
10787 uint16_t offset, length, cnt_words;
10790 offset = eeprom->offset >> 1;
10791 length = eeprom->length >> 1;
10792 cnt_words = length;
10794 if (offset > hw->nvm.sr_size ||
10795 offset + length > hw->nvm.sr_size) {
10796 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10800 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10802 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10803 if (ret_code != I40E_SUCCESS || cnt_words != length) {
10804 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10811 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10812 struct ether_addr *mac_addr)
10814 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10816 if (!is_valid_assigned_ether_addr(mac_addr)) {
10817 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10821 /* Flags: 0x3 updates port address */
10822 i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10826 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10828 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10829 struct rte_eth_dev_data *dev_data = pf->dev_data;
10830 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
10833 /* check if mtu is within the allowed range */
10834 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10837 /* mtu setting is forbidden if port is start */
10838 if (dev_data->dev_started) {
10839 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10840 dev_data->port_id);
10844 if (frame_size > ETHER_MAX_LEN)
10845 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10847 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10849 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10854 /* Restore ethertype filter */
10856 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10858 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10859 struct i40e_ethertype_filter_list
10860 *ethertype_list = &pf->ethertype.ethertype_list;
10861 struct i40e_ethertype_filter *f;
10862 struct i40e_control_filter_stats stats;
10865 TAILQ_FOREACH(f, ethertype_list, rules) {
10867 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10868 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10869 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10870 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10871 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10873 memset(&stats, 0, sizeof(stats));
10874 i40e_aq_add_rem_control_packet_filter(hw,
10875 f->input.mac_addr.addr_bytes,
10876 f->input.ether_type,
10877 flags, pf->main_vsi->seid,
10878 f->queue, 1, &stats, NULL);
10880 PMD_DRV_LOG(INFO, "Ethertype filter:"
10881 " mac_etype_used = %u, etype_used = %u,"
10882 " mac_etype_free = %u, etype_free = %u",
10883 stats.mac_etype_used, stats.etype_used,
10884 stats.mac_etype_free, stats.etype_free);
10887 /* Restore tunnel filter */
10889 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10891 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10892 struct i40e_vsi *vsi;
10893 struct i40e_pf_vf *vf;
10894 struct i40e_tunnel_filter_list
10895 *tunnel_list = &pf->tunnel.tunnel_list;
10896 struct i40e_tunnel_filter *f;
10897 struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
10898 bool big_buffer = 0;
10900 TAILQ_FOREACH(f, tunnel_list, rules) {
10902 vsi = pf->main_vsi;
10904 vf = &pf->vfs[f->vf_id];
10907 memset(&cld_filter, 0, sizeof(cld_filter));
10908 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
10909 (struct ether_addr *)&cld_filter.element.outer_mac);
10910 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
10911 (struct ether_addr *)&cld_filter.element.inner_mac);
10912 cld_filter.element.inner_vlan = f->input.inner_vlan;
10913 cld_filter.element.flags = f->input.flags;
10914 cld_filter.element.tenant_id = f->input.tenant_id;
10915 cld_filter.element.queue_number = f->queue;
10916 rte_memcpy(cld_filter.general_fields,
10917 f->input.general_fields,
10918 sizeof(f->input.general_fields));
10920 if (((f->input.flags &
10921 I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
10922 I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
10924 I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
10925 I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
10927 I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
10928 I40E_AQC_ADD_CLOUD_FILTER_0X10))
10932 i40e_aq_add_cloud_filters_big_buffer(hw,
10933 vsi->seid, &cld_filter, 1);
10935 i40e_aq_add_cloud_filters(hw, vsi->seid,
10936 &cld_filter.element, 1);
10941 i40e_filter_restore(struct i40e_pf *pf)
10943 i40e_ethertype_filter_restore(pf);
10944 i40e_tunnel_filter_restore(pf);
10945 i40e_fdir_filter_restore(pf);
10949 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
10951 if (strcmp(dev->device->driver->name, drv->driver.name))
10958 is_i40e_supported(struct rte_eth_dev *dev)
10960 return is_device_supported(dev, &rte_i40e_pmd);
10963 struct i40e_customized_pctype*
10964 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
10968 for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
10969 if (pf->customized_pctype[i].index == index)
10970 return &pf->customized_pctype[i];
10976 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
10977 uint32_t pkg_size, uint32_t proto_num,
10978 struct rte_pmd_i40e_proto_info *proto)
10980 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10981 uint32_t pctype_num;
10982 struct rte_pmd_i40e_ptype_info *pctype;
10983 uint32_t buff_size;
10984 struct i40e_customized_pctype *new_pctype = NULL;
10986 uint8_t pctype_value;
10991 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
10992 (uint8_t *)&pctype_num, sizeof(pctype_num),
10993 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
10995 PMD_DRV_LOG(ERR, "Failed to get pctype number");
10999 PMD_DRV_LOG(INFO, "No new pctype added");
11003 buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
11004 pctype = rte_zmalloc("new_pctype", buff_size, 0);
11006 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11009 /* get information about new pctype list */
11010 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11011 (uint8_t *)pctype, buff_size,
11012 RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
11014 PMD_DRV_LOG(ERR, "Failed to get pctype list");
11019 /* Update customized pctype. */
11020 for (i = 0; i < pctype_num; i++) {
11021 pctype_value = pctype[i].ptype_id;
11022 memset(name, 0, sizeof(name));
11023 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11024 proto_id = pctype[i].protocols[j];
11025 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11027 for (n = 0; n < proto_num; n++) {
11028 if (proto[n].proto_id != proto_id)
11030 strcat(name, proto[n].name);
11035 name[strlen(name) - 1] = '\0';
11036 if (!strcmp(name, "GTPC"))
11038 i40e_find_customized_pctype(pf,
11039 I40E_CUSTOMIZED_GTPC);
11040 else if (!strcmp(name, "GTPU_IPV4"))
11042 i40e_find_customized_pctype(pf,
11043 I40E_CUSTOMIZED_GTPU_IPV4);
11044 else if (!strcmp(name, "GTPU_IPV6"))
11046 i40e_find_customized_pctype(pf,
11047 I40E_CUSTOMIZED_GTPU_IPV6);
11048 else if (!strcmp(name, "GTPU"))
11050 i40e_find_customized_pctype(pf,
11051 I40E_CUSTOMIZED_GTPU);
11053 new_pctype->pctype = pctype_value;
11054 new_pctype->valid = true;
11063 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
11064 uint32_t pkg_size, uint32_t proto_num,
11065 struct rte_pmd_i40e_proto_info *proto)
11067 struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
11068 uint16_t port_id = dev->data->port_id;
11069 uint32_t ptype_num;
11070 struct rte_pmd_i40e_ptype_info *ptype;
11071 uint32_t buff_size;
11073 char name[RTE_PMD_I40E_DDP_NAME_SIZE];
11078 /* get information about new ptype num */
11079 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11080 (uint8_t *)&ptype_num, sizeof(ptype_num),
11081 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
11083 PMD_DRV_LOG(ERR, "Failed to get ptype number");
11087 PMD_DRV_LOG(INFO, "No new ptype added");
11091 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
11092 ptype = rte_zmalloc("new_ptype", buff_size, 0);
11094 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11098 /* get information about new ptype list */
11099 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11100 (uint8_t *)ptype, buff_size,
11101 RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
11103 PMD_DRV_LOG(ERR, "Failed to get ptype list");
11108 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
11109 ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
11110 if (!ptype_mapping) {
11111 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11116 /* Update ptype mapping table. */
11117 for (i = 0; i < ptype_num; i++) {
11118 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
11119 ptype_mapping[i].sw_ptype = 0;
11121 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11122 proto_id = ptype[i].protocols[j];
11123 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11125 for (n = 0; n < proto_num; n++) {
11126 if (proto[n].proto_id != proto_id)
11128 memset(name, 0, sizeof(name));
11129 strcpy(name, proto[n].name);
11130 if (!strncmp(name, "IPV4", 4) && !inner_ip) {
11131 ptype_mapping[i].sw_ptype |=
11132 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11134 } else if (!strncmp(name, "IPV4", 4) &&
11136 ptype_mapping[i].sw_ptype |=
11137 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11138 } else if (!strncmp(name, "IPV6", 4) &&
11140 ptype_mapping[i].sw_ptype |=
11141 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11143 } else if (!strncmp(name, "IPV6", 4) &&
11145 ptype_mapping[i].sw_ptype |=
11146 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11147 } else if (!strncmp(name, "IPV4FRAG", 8)) {
11148 ptype_mapping[i].sw_ptype |=
11149 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11150 ptype_mapping[i].sw_ptype |=
11151 RTE_PTYPE_INNER_L4_FRAG;
11152 } else if (!strncmp(name, "IPV6FRAG", 8)) {
11153 ptype_mapping[i].sw_ptype |=
11154 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11155 ptype_mapping[i].sw_ptype |=
11156 RTE_PTYPE_INNER_L4_FRAG;
11157 } else if (!strncmp(name, "GTPC", 4))
11158 ptype_mapping[i].sw_ptype |=
11159 RTE_PTYPE_TUNNEL_GTPC;
11160 else if (!strncmp(name, "GTPU", 4))
11161 ptype_mapping[i].sw_ptype |=
11162 RTE_PTYPE_TUNNEL_GTPU;
11163 else if (!strncmp(name, "UDP", 3))
11164 ptype_mapping[i].sw_ptype |=
11165 RTE_PTYPE_INNER_L4_UDP;
11166 else if (!strncmp(name, "TCP", 3))
11167 ptype_mapping[i].sw_ptype |=
11168 RTE_PTYPE_INNER_L4_TCP;
11169 else if (!strncmp(name, "SCTP", 4))
11170 ptype_mapping[i].sw_ptype |=
11171 RTE_PTYPE_INNER_L4_SCTP;
11172 else if (!strncmp(name, "ICMP", 4) ||
11173 !strncmp(name, "ICMPV6", 6))
11174 ptype_mapping[i].sw_ptype |=
11175 RTE_PTYPE_INNER_L4_ICMP;
11182 ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
11185 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
11187 rte_free(ptype_mapping);
11193 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
11196 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11197 uint32_t proto_num;
11198 struct rte_pmd_i40e_proto_info *proto;
11199 uint32_t buff_size;
11203 /* get information about protocol number */
11204 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11205 (uint8_t *)&proto_num, sizeof(proto_num),
11206 RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
11208 PMD_DRV_LOG(ERR, "Failed to get protocol number");
11212 PMD_DRV_LOG(INFO, "No new protocol added");
11216 buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
11217 proto = rte_zmalloc("new_proto", buff_size, 0);
11219 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11223 /* get information about protocol list */
11224 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11225 (uint8_t *)proto, buff_size,
11226 RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
11228 PMD_DRV_LOG(ERR, "Failed to get protocol list");
11233 /* Check if GTP is supported. */
11234 for (i = 0; i < proto_num; i++) {
11235 if (!strncmp(proto[i].name, "GTP", 3)) {
11236 pf->gtp_support = true;
11241 /* Update customized pctype info */
11242 ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
11245 PMD_DRV_LOG(INFO, "No pctype is updated.");
11247 /* Update customized ptype info */
11248 ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
11251 PMD_DRV_LOG(INFO, "No ptype is updated.");
11256 /* Create a QinQ cloud filter
11258 * The Fortville NIC has limited resources for tunnel filters,
11259 * so we can only reuse existing filters.
11261 * In step 1 we define which Field Vector fields can be used for
11263 * As we do not have the inner tag defined as a field,
11264 * we have to define it first, by reusing one of L1 entries.
11266 * In step 2 we are replacing one of existing filter types with
11267 * a new one for QinQ.
11268 * As we reusing L1 and replacing L2, some of the default filter
11269 * types will disappear,which depends on L1 and L2 entries we reuse.
11271 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
11273 * 1. Create L1 filter of outer vlan (12b) which will be in use
11274 * later when we define the cloud filter.
11275 * a. Valid_flags.replace_cloud = 0
11276 * b. Old_filter = 10 (Stag_Inner_Vlan)
11277 * c. New_filter = 0x10
11278 * d. TR bit = 0xff (optional, not used here)
11279 * e. Buffer – 2 entries:
11280 * i. Byte 0 = 8 (outer vlan FV index).
11282 * Byte 2-3 = 0x0fff
11283 * ii. Byte 0 = 37 (inner vlan FV index).
11285 * Byte 2-3 = 0x0fff
11288 * 2. Create cloud filter using two L1 filters entries: stag and
11289 * new filter(outer vlan+ inner vlan)
11290 * a. Valid_flags.replace_cloud = 1
11291 * b. Old_filter = 1 (instead of outer IP)
11292 * c. New_filter = 0x10
11293 * d. Buffer – 2 entries:
11294 * i. Byte 0 = 0x80 | 7 (valid | Stag).
11295 * Byte 1-3 = 0 (rsv)
11296 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
11297 * Byte 9-11 = 0 (rsv)
11300 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
11302 int ret = -ENOTSUP;
11303 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
11304 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
11305 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11308 memset(&filter_replace, 0,
11309 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11310 memset(&filter_replace_buf, 0,
11311 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11313 /* create L1 filter */
11314 filter_replace.old_filter_type =
11315 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
11316 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11317 filter_replace.tr_bit = 0;
11319 /* Prepare the buffer, 2 entries */
11320 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
11321 filter_replace_buf.data[0] |=
11322 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11323 /* Field Vector 12b mask */
11324 filter_replace_buf.data[2] = 0xff;
11325 filter_replace_buf.data[3] = 0x0f;
11326 filter_replace_buf.data[4] =
11327 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
11328 filter_replace_buf.data[4] |=
11329 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11330 /* Field Vector 12b mask */
11331 filter_replace_buf.data[6] = 0xff;
11332 filter_replace_buf.data[7] = 0x0f;
11333 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11334 &filter_replace_buf);
11335 if (ret != I40E_SUCCESS)
11338 /* Apply the second L2 cloud filter */
11339 memset(&filter_replace, 0,
11340 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11341 memset(&filter_replace_buf, 0,
11342 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11344 /* create L2 filter, input for L2 filter will be L1 filter */
11345 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
11346 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
11347 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11349 /* Prepare the buffer, 2 entries */
11350 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
11351 filter_replace_buf.data[0] |=
11352 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11353 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11354 filter_replace_buf.data[4] |=
11355 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11356 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11357 &filter_replace_buf);
11361 RTE_INIT(i40e_init_log);
11363 i40e_init_log(void)
11365 i40e_logtype_init = rte_log_register("pmd.i40e.init");
11366 if (i40e_logtype_init >= 0)
11367 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
11368 i40e_logtype_driver = rte_log_register("pmd.i40e.driver");
11369 if (i40e_logtype_driver >= 0)
11370 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);