1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
14 #include <rte_common.h>
16 #include <rte_string_fns.h>
18 #include <rte_bus_pci.h>
19 #include <rte_ether.h>
20 #include <rte_ethdev_driver.h>
21 #include <rte_ethdev_pci.h>
22 #include <rte_memzone.h>
23 #include <rte_malloc.h>
24 #include <rte_memcpy.h>
25 #include <rte_alarm.h>
27 #include <rte_tailq.h>
28 #include <rte_hash_crc.h>
30 #include "i40e_logs.h"
31 #include "base/i40e_prototype.h"
32 #include "base/i40e_adminq_cmd.h"
33 #include "base/i40e_type.h"
34 #include "base/i40e_register.h"
35 #include "base/i40e_dcb.h"
36 #include "i40e_ethdev.h"
37 #include "i40e_rxtx.h"
39 #include "i40e_regs.h"
40 #include "rte_pmd_i40e.h"
42 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
43 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
44 #define ETH_I40E_SUPPORT_MULTI_DRIVER "support-multi-driver"
45 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG "queue-num-per-vf"
46 #define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec"
48 #define I40E_CLEAR_PXE_WAIT_MS 200
50 /* Maximun number of capability elements */
51 #define I40E_MAX_CAP_ELE_NUM 128
53 /* Wait count and interval */
54 #define I40E_CHK_Q_ENA_COUNT 1000
55 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
57 /* Maximun number of VSI */
58 #define I40E_MAX_NUM_VSIS (384UL)
60 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
62 /* Flow control default timer */
63 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
65 /* Flow control enable fwd bit */
66 #define I40E_PRTMAC_FWD_CTRL 0x00000001
68 /* Receive Packet Buffer size */
69 #define I40E_RXPBSIZE (968 * 1024)
72 #define I40E_KILOSHIFT 10
74 /* Flow control default high water */
75 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
77 /* Flow control default low water */
78 #define I40E_DEFAULT_LOW_WATER (0xF2000 >> I40E_KILOSHIFT)
80 /* Receive Average Packet Size in Byte*/
81 #define I40E_PACKET_AVERAGE_SIZE 128
83 /* Mask of PF interrupt causes */
84 #define I40E_PFINT_ICR0_ENA_MASK ( \
85 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
86 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
87 I40E_PFINT_ICR0_ENA_GRST_MASK | \
88 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
89 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
90 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
91 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
92 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
93 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
95 #define I40E_FLOW_TYPES ( \
96 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
97 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
98 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
99 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
100 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
101 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
102 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
103 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
104 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
105 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
106 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
108 /* Additional timesync values. */
109 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
110 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
111 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
112 #define I40E_PRTTSYN_TSYNENA 0x80000000
113 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
114 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
117 * Below are values for writing un-exposed registers suggested
120 /* Destination MAC address */
121 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
122 /* Source MAC address */
123 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
124 /* Outer (S-Tag) VLAN tag in the outer L2 header */
125 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
126 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
127 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
128 /* Single VLAN tag in the inner L2 header */
129 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
130 /* Source IPv4 address */
131 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
132 /* Destination IPv4 address */
133 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
134 /* Source IPv4 address for X722 */
135 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
136 /* Destination IPv4 address for X722 */
137 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
138 /* IPv4 Protocol for X722 */
139 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
140 /* IPv4 Time to Live for X722 */
141 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
142 /* IPv4 Type of Service (TOS) */
143 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
145 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
146 /* IPv4 Time to Live */
147 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
148 /* Source IPv6 address */
149 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
150 /* Destination IPv6 address */
151 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
152 /* IPv6 Traffic Class (TC) */
153 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
154 /* IPv6 Next Header */
155 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
157 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
159 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
160 /* Destination L4 port */
161 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
162 /* SCTP verification tag */
163 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
164 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
165 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
166 /* Source port of tunneling UDP */
167 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
168 /* Destination port of tunneling UDP */
169 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
170 /* UDP Tunneling ID, NVGRE/GRE key */
171 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
172 /* Last ether type */
173 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
174 /* Tunneling outer destination IPv4 address */
175 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
176 /* Tunneling outer destination IPv6 address */
177 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
178 /* 1st word of flex payload */
179 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
180 /* 2nd word of flex payload */
181 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
182 /* 3rd word of flex payload */
183 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
184 /* 4th word of flex payload */
185 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
186 /* 5th word of flex payload */
187 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
188 /* 6th word of flex payload */
189 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
190 /* 7th word of flex payload */
191 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
192 /* 8th word of flex payload */
193 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
194 /* all 8 words flex payload */
195 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
196 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
198 #define I40E_TRANSLATE_INSET 0
199 #define I40E_TRANSLATE_REG 1
201 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
202 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
203 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
204 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
205 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
206 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
208 /* PCI offset for querying capability */
209 #define PCI_DEV_CAP_REG 0xA4
210 /* PCI offset for enabling/disabling Extended Tag */
211 #define PCI_DEV_CTRL_REG 0xA8
212 /* Bit mask of Extended Tag capability */
213 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
214 /* Bit shift of Extended Tag enable/disable */
215 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
216 /* Bit mask of Extended Tag enable/disable */
217 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
219 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
220 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
221 static int i40e_dev_configure(struct rte_eth_dev *dev);
222 static int i40e_dev_start(struct rte_eth_dev *dev);
223 static void i40e_dev_stop(struct rte_eth_dev *dev);
224 static void i40e_dev_close(struct rte_eth_dev *dev);
225 static int i40e_dev_reset(struct rte_eth_dev *dev);
226 static int i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
227 static int i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
228 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
229 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
230 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
231 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
232 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
233 struct rte_eth_stats *stats);
234 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
235 struct rte_eth_xstat *xstats, unsigned n);
236 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
237 struct rte_eth_xstat_name *xstats_names,
239 static int i40e_dev_stats_reset(struct rte_eth_dev *dev);
240 static int i40e_fw_version_get(struct rte_eth_dev *dev,
241 char *fw_version, size_t fw_size);
242 static int i40e_dev_info_get(struct rte_eth_dev *dev,
243 struct rte_eth_dev_info *dev_info);
244 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
247 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
248 enum rte_vlan_type vlan_type,
250 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
251 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
254 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
255 static int i40e_dev_led_on(struct rte_eth_dev *dev);
256 static int i40e_dev_led_off(struct rte_eth_dev *dev);
257 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
258 struct rte_eth_fc_conf *fc_conf);
259 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
260 struct rte_eth_fc_conf *fc_conf);
261 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
262 struct rte_eth_pfc_conf *pfc_conf);
263 static int i40e_macaddr_add(struct rte_eth_dev *dev,
264 struct rte_ether_addr *mac_addr,
267 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
268 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
269 struct rte_eth_rss_reta_entry64 *reta_conf,
271 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
272 struct rte_eth_rss_reta_entry64 *reta_conf,
275 static int i40e_get_cap(struct i40e_hw *hw);
276 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
277 static int i40e_pf_setup(struct i40e_pf *pf);
278 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
279 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
280 static int i40e_dcb_setup(struct rte_eth_dev *dev);
281 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
282 bool offset_loaded, uint64_t *offset, uint64_t *stat);
283 static void i40e_stat_update_48(struct i40e_hw *hw,
289 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
290 static void i40e_dev_interrupt_handler(void *param);
291 static void i40e_dev_alarm_handler(void *param);
292 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
293 uint32_t base, uint32_t num);
294 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
295 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
297 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
299 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
300 static int i40e_veb_release(struct i40e_veb *veb);
301 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
302 struct i40e_vsi *vsi);
303 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
304 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
305 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
306 struct i40e_macvlan_filter *mv_f,
309 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
310 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
311 struct rte_eth_rss_conf *rss_conf);
312 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
313 struct rte_eth_rss_conf *rss_conf);
314 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
315 struct rte_eth_udp_tunnel *udp_tunnel);
316 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
317 struct rte_eth_udp_tunnel *udp_tunnel);
318 static void i40e_filter_input_set_init(struct i40e_pf *pf);
319 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
320 enum rte_filter_op filter_op,
322 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
323 enum rte_filter_type filter_type,
324 enum rte_filter_op filter_op,
326 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
327 struct rte_eth_dcb_info *dcb_info);
328 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
329 static void i40e_configure_registers(struct i40e_hw *hw);
330 static void i40e_hw_init(struct rte_eth_dev *dev);
331 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
332 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
338 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
339 struct rte_eth_mirror_conf *mirror_conf,
340 uint8_t sw_id, uint8_t on);
341 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
343 static int i40e_timesync_enable(struct rte_eth_dev *dev);
344 static int i40e_timesync_disable(struct rte_eth_dev *dev);
345 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
346 struct timespec *timestamp,
348 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
349 struct timespec *timestamp);
350 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
352 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
354 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
355 struct timespec *timestamp);
356 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
357 const struct timespec *timestamp);
359 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
361 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
364 static int i40e_get_regs(struct rte_eth_dev *dev,
365 struct rte_dev_reg_info *regs);
367 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
369 static int i40e_get_eeprom(struct rte_eth_dev *dev,
370 struct rte_dev_eeprom_info *eeprom);
372 static int i40e_get_module_info(struct rte_eth_dev *dev,
373 struct rte_eth_dev_module_info *modinfo);
374 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
375 struct rte_dev_eeprom_info *info);
377 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
378 struct rte_ether_addr *mac_addr);
380 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
382 static int i40e_ethertype_filter_convert(
383 const struct rte_eth_ethertype_filter *input,
384 struct i40e_ethertype_filter *filter);
385 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
386 struct i40e_ethertype_filter *filter);
388 static int i40e_tunnel_filter_convert(
389 struct i40e_aqc_cloud_filters_element_bb *cld_filter,
390 struct i40e_tunnel_filter *tunnel_filter);
391 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
392 struct i40e_tunnel_filter *tunnel_filter);
393 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
395 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
396 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
397 static void i40e_filter_restore(struct i40e_pf *pf);
398 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
400 int i40e_logtype_init;
401 int i40e_logtype_driver;
403 static const char *const valid_keys[] = {
404 ETH_I40E_FLOATING_VEB_ARG,
405 ETH_I40E_FLOATING_VEB_LIST_ARG,
406 ETH_I40E_SUPPORT_MULTI_DRIVER,
407 ETH_I40E_QUEUE_NUM_PER_VF_ARG,
408 ETH_I40E_USE_LATEST_VEC,
411 static const struct rte_pci_id pci_id_i40e_map[] = {
412 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
413 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
414 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
415 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
416 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
417 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
418 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
419 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
420 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
421 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
422 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
423 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
424 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
425 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
426 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
427 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
428 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
429 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
430 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
431 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
432 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X710_N3000) },
433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_XXV710_N3000) },
434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_BC) },
435 { .vendor_id = 0, /* sentinel */ },
438 static const struct eth_dev_ops i40e_eth_dev_ops = {
439 .dev_configure = i40e_dev_configure,
440 .dev_start = i40e_dev_start,
441 .dev_stop = i40e_dev_stop,
442 .dev_close = i40e_dev_close,
443 .dev_reset = i40e_dev_reset,
444 .promiscuous_enable = i40e_dev_promiscuous_enable,
445 .promiscuous_disable = i40e_dev_promiscuous_disable,
446 .allmulticast_enable = i40e_dev_allmulticast_enable,
447 .allmulticast_disable = i40e_dev_allmulticast_disable,
448 .dev_set_link_up = i40e_dev_set_link_up,
449 .dev_set_link_down = i40e_dev_set_link_down,
450 .link_update = i40e_dev_link_update,
451 .stats_get = i40e_dev_stats_get,
452 .xstats_get = i40e_dev_xstats_get,
453 .xstats_get_names = i40e_dev_xstats_get_names,
454 .stats_reset = i40e_dev_stats_reset,
455 .xstats_reset = i40e_dev_stats_reset,
456 .fw_version_get = i40e_fw_version_get,
457 .dev_infos_get = i40e_dev_info_get,
458 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
459 .vlan_filter_set = i40e_vlan_filter_set,
460 .vlan_tpid_set = i40e_vlan_tpid_set,
461 .vlan_offload_set = i40e_vlan_offload_set,
462 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
463 .vlan_pvid_set = i40e_vlan_pvid_set,
464 .rx_queue_start = i40e_dev_rx_queue_start,
465 .rx_queue_stop = i40e_dev_rx_queue_stop,
466 .tx_queue_start = i40e_dev_tx_queue_start,
467 .tx_queue_stop = i40e_dev_tx_queue_stop,
468 .rx_queue_setup = i40e_dev_rx_queue_setup,
469 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
470 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
471 .rx_queue_release = i40e_dev_rx_queue_release,
472 .rx_queue_count = i40e_dev_rx_queue_count,
473 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
474 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
475 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
476 .tx_queue_setup = i40e_dev_tx_queue_setup,
477 .tx_queue_release = i40e_dev_tx_queue_release,
478 .dev_led_on = i40e_dev_led_on,
479 .dev_led_off = i40e_dev_led_off,
480 .flow_ctrl_get = i40e_flow_ctrl_get,
481 .flow_ctrl_set = i40e_flow_ctrl_set,
482 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
483 .mac_addr_add = i40e_macaddr_add,
484 .mac_addr_remove = i40e_macaddr_remove,
485 .reta_update = i40e_dev_rss_reta_update,
486 .reta_query = i40e_dev_rss_reta_query,
487 .rss_hash_update = i40e_dev_rss_hash_update,
488 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
489 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
490 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
491 .filter_ctrl = i40e_dev_filter_ctrl,
492 .rxq_info_get = i40e_rxq_info_get,
493 .txq_info_get = i40e_txq_info_get,
494 .mirror_rule_set = i40e_mirror_rule_set,
495 .mirror_rule_reset = i40e_mirror_rule_reset,
496 .timesync_enable = i40e_timesync_enable,
497 .timesync_disable = i40e_timesync_disable,
498 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
499 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
500 .get_dcb_info = i40e_dev_get_dcb_info,
501 .timesync_adjust_time = i40e_timesync_adjust_time,
502 .timesync_read_time = i40e_timesync_read_time,
503 .timesync_write_time = i40e_timesync_write_time,
504 .get_reg = i40e_get_regs,
505 .get_eeprom_length = i40e_get_eeprom_length,
506 .get_eeprom = i40e_get_eeprom,
507 .get_module_info = i40e_get_module_info,
508 .get_module_eeprom = i40e_get_module_eeprom,
509 .mac_addr_set = i40e_set_default_mac_addr,
510 .mtu_set = i40e_dev_mtu_set,
511 .tm_ops_get = i40e_tm_ops_get,
514 /* store statistics names and its offset in stats structure */
515 struct rte_i40e_xstats_name_off {
516 char name[RTE_ETH_XSTATS_NAME_SIZE];
520 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
521 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
522 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
523 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
524 {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
525 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
526 rx_unknown_protocol)},
527 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
528 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
529 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
530 {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
533 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
534 sizeof(rte_i40e_stats_strings[0]))
536 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
537 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
538 tx_dropped_link_down)},
539 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
540 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
542 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
543 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
545 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
547 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
549 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
550 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
551 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
552 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
553 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
554 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
556 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
558 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
560 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
562 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
564 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
566 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
568 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
570 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
571 mac_short_packet_dropped)},
572 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
574 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
575 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
576 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
578 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
580 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
582 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
584 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
586 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
588 {"rx_flow_director_atr_match_packets",
589 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
590 {"rx_flow_director_sb_match_packets",
591 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
592 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
594 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
596 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
598 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
602 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
603 sizeof(rte_i40e_hw_port_strings[0]))
605 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
606 {"xon_packets", offsetof(struct i40e_hw_port_stats,
608 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
612 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
613 sizeof(rte_i40e_rxq_prio_strings[0]))
615 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
616 {"xon_packets", offsetof(struct i40e_hw_port_stats,
618 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
620 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
621 priority_xon_2_xoff)},
624 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
625 sizeof(rte_i40e_txq_prio_strings[0]))
628 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
629 struct rte_pci_device *pci_dev)
631 char name[RTE_ETH_NAME_MAX_LEN];
632 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
635 if (pci_dev->device.devargs) {
636 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
642 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
643 sizeof(struct i40e_adapter),
644 eth_dev_pci_specific_init, pci_dev,
645 eth_i40e_dev_init, NULL);
647 if (retval || eth_da.nb_representor_ports < 1)
650 /* probe VF representor ports */
651 struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
652 pci_dev->device.name);
654 if (pf_ethdev == NULL)
657 for (i = 0; i < eth_da.nb_representor_ports; i++) {
658 struct i40e_vf_representor representor = {
659 .vf_id = eth_da.representor_ports[i],
660 .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
661 pf_ethdev->data->dev_private)->switch_domain_id,
662 .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
663 pf_ethdev->data->dev_private)
666 /* representor port net_bdf_port */
667 snprintf(name, sizeof(name), "net_%s_representor_%d",
668 pci_dev->device.name, eth_da.representor_ports[i]);
670 retval = rte_eth_dev_create(&pci_dev->device, name,
671 sizeof(struct i40e_vf_representor), NULL, NULL,
672 i40e_vf_representor_init, &representor);
675 PMD_DRV_LOG(ERR, "failed to create i40e vf "
676 "representor %s.", name);
682 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
684 struct rte_eth_dev *ethdev;
686 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
691 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
692 return rte_eth_dev_destroy(ethdev, i40e_vf_representor_uninit);
694 return rte_eth_dev_destroy(ethdev, eth_i40e_dev_uninit);
697 static struct rte_pci_driver rte_i40e_pmd = {
698 .id_table = pci_id_i40e_map,
699 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
700 .probe = eth_i40e_pci_probe,
701 .remove = eth_i40e_pci_remove,
705 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
708 uint32_t ori_reg_val;
709 struct rte_eth_dev *dev;
711 ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
712 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
713 i40e_write_rx_ctl(hw, reg_addr, reg_val);
714 if (ori_reg_val != reg_val)
716 "i40e device %s changed global register [0x%08x]."
717 " original: 0x%08x, new: 0x%08x",
718 dev->device->name, reg_addr, ori_reg_val, reg_val);
721 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
722 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
723 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
725 #ifndef I40E_GLQF_ORT
726 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
728 #ifndef I40E_GLQF_PIT
729 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
731 #ifndef I40E_GLQF_L3_MAP
732 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
735 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
738 * Initialize registers for parsing packet type of QinQ
739 * This should be removed from code once proper
740 * configuration API is added to avoid configuration conflicts
741 * between ports of the same device.
743 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
744 I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
747 static inline void i40e_config_automask(struct i40e_pf *pf)
749 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
752 /* INTENA flag is not auto-cleared for interrupt */
753 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
754 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
755 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
757 /* If support multi-driver, PF will use INT0. */
758 if (!pf->support_multi_driver)
759 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
761 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
764 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
767 * Add a ethertype filter to drop all flow control frames transmitted
771 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
773 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
774 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
775 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
776 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
779 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
780 I40E_FLOW_CONTROL_ETHERTYPE, flags,
781 pf->main_vsi_seid, 0,
785 "Failed to add filter to drop flow control frames from VSIs.");
789 floating_veb_list_handler(__rte_unused const char *key,
790 const char *floating_veb_value,
794 unsigned int count = 0;
797 bool *vf_floating_veb = opaque;
799 while (isblank(*floating_veb_value))
800 floating_veb_value++;
802 /* Reset floating VEB configuration for VFs */
803 for (idx = 0; idx < I40E_MAX_VF; idx++)
804 vf_floating_veb[idx] = false;
808 while (isblank(*floating_veb_value))
809 floating_veb_value++;
810 if (*floating_veb_value == '\0')
813 idx = strtoul(floating_veb_value, &end, 10);
814 if (errno || end == NULL)
816 while (isblank(*end))
820 } else if ((*end == ';') || (*end == '\0')) {
822 if (min == I40E_MAX_VF)
824 if (max >= I40E_MAX_VF)
825 max = I40E_MAX_VF - 1;
826 for (idx = min; idx <= max; idx++) {
827 vf_floating_veb[idx] = true;
834 floating_veb_value = end + 1;
835 } while (*end != '\0');
844 config_vf_floating_veb(struct rte_devargs *devargs,
845 uint16_t floating_veb,
846 bool *vf_floating_veb)
848 struct rte_kvargs *kvlist;
850 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
854 /* All the VFs attach to the floating VEB by default
855 * when the floating VEB is enabled.
857 for (i = 0; i < I40E_MAX_VF; i++)
858 vf_floating_veb[i] = true;
863 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
867 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
868 rte_kvargs_free(kvlist);
871 /* When the floating_veb_list parameter exists, all the VFs
872 * will attach to the legacy VEB firstly, then configure VFs
873 * to the floating VEB according to the floating_veb_list.
875 if (rte_kvargs_process(kvlist, floating_veb_list,
876 floating_veb_list_handler,
877 vf_floating_veb) < 0) {
878 rte_kvargs_free(kvlist);
881 rte_kvargs_free(kvlist);
885 i40e_check_floating_handler(__rte_unused const char *key,
887 __rte_unused void *opaque)
889 if (strcmp(value, "1"))
896 is_floating_veb_supported(struct rte_devargs *devargs)
898 struct rte_kvargs *kvlist;
899 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
904 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
908 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
909 rte_kvargs_free(kvlist);
912 /* Floating VEB is enabled when there's key-value:
913 * enable_floating_veb=1
915 if (rte_kvargs_process(kvlist, floating_veb_key,
916 i40e_check_floating_handler, NULL) < 0) {
917 rte_kvargs_free(kvlist);
920 rte_kvargs_free(kvlist);
926 config_floating_veb(struct rte_eth_dev *dev)
928 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
929 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
930 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
932 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
934 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
936 is_floating_veb_supported(pci_dev->device.devargs);
937 config_vf_floating_veb(pci_dev->device.devargs,
939 pf->floating_veb_list);
941 pf->floating_veb = false;
945 #define I40E_L2_TAGS_S_TAG_SHIFT 1
946 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
949 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
951 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
952 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
953 char ethertype_hash_name[RTE_HASH_NAMESIZE];
956 struct rte_hash_parameters ethertype_hash_params = {
957 .name = ethertype_hash_name,
958 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
959 .key_len = sizeof(struct i40e_ethertype_filter_input),
960 .hash_func = rte_hash_crc,
961 .hash_func_init_val = 0,
962 .socket_id = rte_socket_id(),
965 /* Initialize ethertype filter rule list and hash */
966 TAILQ_INIT(ðertype_rule->ethertype_list);
967 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
968 "ethertype_%s", dev->device->name);
969 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
970 if (!ethertype_rule->hash_table) {
971 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
974 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
975 sizeof(struct i40e_ethertype_filter *) *
976 I40E_MAX_ETHERTYPE_FILTER_NUM,
978 if (!ethertype_rule->hash_map) {
980 "Failed to allocate memory for ethertype hash map!");
982 goto err_ethertype_hash_map_alloc;
987 err_ethertype_hash_map_alloc:
988 rte_hash_free(ethertype_rule->hash_table);
994 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
996 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
997 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
998 char tunnel_hash_name[RTE_HASH_NAMESIZE];
1001 struct rte_hash_parameters tunnel_hash_params = {
1002 .name = tunnel_hash_name,
1003 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1004 .key_len = sizeof(struct i40e_tunnel_filter_input),
1005 .hash_func = rte_hash_crc,
1006 .hash_func_init_val = 0,
1007 .socket_id = rte_socket_id(),
1010 /* Initialize tunnel filter rule list and hash */
1011 TAILQ_INIT(&tunnel_rule->tunnel_list);
1012 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1013 "tunnel_%s", dev->device->name);
1014 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1015 if (!tunnel_rule->hash_table) {
1016 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1019 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1020 sizeof(struct i40e_tunnel_filter *) *
1021 I40E_MAX_TUNNEL_FILTER_NUM,
1023 if (!tunnel_rule->hash_map) {
1025 "Failed to allocate memory for tunnel hash map!");
1027 goto err_tunnel_hash_map_alloc;
1032 err_tunnel_hash_map_alloc:
1033 rte_hash_free(tunnel_rule->hash_table);
1039 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1041 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1042 struct i40e_fdir_info *fdir_info = &pf->fdir;
1043 char fdir_hash_name[RTE_HASH_NAMESIZE];
1046 struct rte_hash_parameters fdir_hash_params = {
1047 .name = fdir_hash_name,
1048 .entries = I40E_MAX_FDIR_FILTER_NUM,
1049 .key_len = sizeof(struct i40e_fdir_input),
1050 .hash_func = rte_hash_crc,
1051 .hash_func_init_val = 0,
1052 .socket_id = rte_socket_id(),
1055 /* Initialize flow director filter rule list and hash */
1056 TAILQ_INIT(&fdir_info->fdir_list);
1057 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1058 "fdir_%s", dev->device->name);
1059 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1060 if (!fdir_info->hash_table) {
1061 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1064 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1065 sizeof(struct i40e_fdir_filter *) *
1066 I40E_MAX_FDIR_FILTER_NUM,
1068 if (!fdir_info->hash_map) {
1070 "Failed to allocate memory for fdir hash map!");
1072 goto err_fdir_hash_map_alloc;
1076 err_fdir_hash_map_alloc:
1077 rte_hash_free(fdir_info->hash_table);
1083 i40e_init_customized_info(struct i40e_pf *pf)
1087 /* Initialize customized pctype */
1088 for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1089 pf->customized_pctype[i].index = i;
1090 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1091 pf->customized_pctype[i].valid = false;
1094 pf->gtp_support = false;
1098 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1100 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1101 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1102 struct i40e_queue_regions *info = &pf->queue_region;
1105 for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1106 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1108 memset(info, 0, sizeof(struct i40e_queue_regions));
1112 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1117 unsigned long support_multi_driver;
1120 pf = (struct i40e_pf *)opaque;
1123 support_multi_driver = strtoul(value, &end, 10);
1124 if (errno != 0 || end == value || *end != 0) {
1125 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1129 if (support_multi_driver == 1 || support_multi_driver == 0)
1130 pf->support_multi_driver = (bool)support_multi_driver;
1132 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1133 "enable global configuration by default."
1134 ETH_I40E_SUPPORT_MULTI_DRIVER);
1139 i40e_support_multi_driver(struct rte_eth_dev *dev)
1141 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1142 struct rte_kvargs *kvlist;
1145 /* Enable global configuration by default */
1146 pf->support_multi_driver = false;
1148 if (!dev->device->devargs)
1151 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1155 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1156 if (!kvargs_count) {
1157 rte_kvargs_free(kvlist);
1161 if (kvargs_count > 1)
1162 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1163 "the first invalid or last valid one is used !",
1164 ETH_I40E_SUPPORT_MULTI_DRIVER);
1166 if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1167 i40e_parse_multi_drv_handler, pf) < 0) {
1168 rte_kvargs_free(kvlist);
1172 rte_kvargs_free(kvlist);
1177 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1178 uint32_t reg_addr, uint64_t reg_val,
1179 struct i40e_asq_cmd_details *cmd_details)
1181 uint64_t ori_reg_val;
1182 struct rte_eth_dev *dev;
1185 ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1186 if (ret != I40E_SUCCESS) {
1188 "Fail to debug read from 0x%08x",
1192 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1194 if (ori_reg_val != reg_val)
1195 PMD_DRV_LOG(WARNING,
1196 "i40e device %s changed global register [0x%08x]."
1197 " original: 0x%"PRIx64", after: 0x%"PRIx64,
1198 dev->device->name, reg_addr, ori_reg_val, reg_val);
1200 return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1204 i40e_parse_latest_vec_handler(__rte_unused const char *key,
1208 struct i40e_adapter *ad = opaque;
1211 use_latest_vec = atoi(value);
1213 if (use_latest_vec != 0 && use_latest_vec != 1)
1214 PMD_DRV_LOG(WARNING, "Value should be 0 or 1, set it as 1!");
1216 ad->use_latest_vec = (uint8_t)use_latest_vec;
1222 i40e_use_latest_vec(struct rte_eth_dev *dev)
1224 struct i40e_adapter *ad =
1225 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1226 struct rte_kvargs *kvlist;
1229 ad->use_latest_vec = false;
1231 if (!dev->device->devargs)
1234 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1238 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_USE_LATEST_VEC);
1239 if (!kvargs_count) {
1240 rte_kvargs_free(kvlist);
1244 if (kvargs_count > 1)
1245 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1246 "the first invalid or last valid one is used !",
1247 ETH_I40E_USE_LATEST_VEC);
1249 if (rte_kvargs_process(kvlist, ETH_I40E_USE_LATEST_VEC,
1250 i40e_parse_latest_vec_handler, ad) < 0) {
1251 rte_kvargs_free(kvlist);
1255 rte_kvargs_free(kvlist);
1259 #define I40E_ALARM_INTERVAL 50000 /* us */
1262 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1264 struct rte_pci_device *pci_dev;
1265 struct rte_intr_handle *intr_handle;
1266 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1267 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1268 struct i40e_vsi *vsi;
1271 uint8_t aq_fail = 0;
1273 PMD_INIT_FUNC_TRACE();
1275 dev->dev_ops = &i40e_eth_dev_ops;
1276 dev->rx_pkt_burst = i40e_recv_pkts;
1277 dev->tx_pkt_burst = i40e_xmit_pkts;
1278 dev->tx_pkt_prepare = i40e_prep_pkts;
1280 /* for secondary processes, we don't initialise any further as primary
1281 * has already done this work. Only check we don't need a different
1283 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1284 i40e_set_rx_function(dev);
1285 i40e_set_tx_function(dev);
1288 i40e_set_default_ptype_table(dev);
1289 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1290 intr_handle = &pci_dev->intr_handle;
1292 rte_eth_copy_pci_info(dev, pci_dev);
1294 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1295 pf->adapter->eth_dev = dev;
1296 pf->dev_data = dev->data;
1298 hw->back = I40E_PF_TO_ADAPTER(pf);
1299 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1302 "Hardware is not available, as address is NULL");
1306 hw->vendor_id = pci_dev->id.vendor_id;
1307 hw->device_id = pci_dev->id.device_id;
1308 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1309 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1310 hw->bus.device = pci_dev->addr.devid;
1311 hw->bus.func = pci_dev->addr.function;
1312 hw->adapter_stopped = 0;
1313 hw->adapter_closed = 0;
1316 * Switch Tag value should not be identical to either the First Tag
1317 * or Second Tag values. So set something other than common Ethertype
1318 * for internal switching.
1320 hw->switch_tag = 0xffff;
1322 val = I40E_READ_REG(hw, I40E_GL_FWSTS);
1323 if (val & I40E_GL_FWSTS_FWS1B_MASK) {
1324 PMD_INIT_LOG(ERR, "\nERROR: "
1325 "Firmware recovery mode detected. Limiting functionality.\n"
1326 "Refer to the Intel(R) Ethernet Adapters and Devices "
1327 "User Guide for details on firmware recovery mode.");
1331 /* Check if need to support multi-driver */
1332 i40e_support_multi_driver(dev);
1333 /* Check if users want the latest supported vec path */
1334 i40e_use_latest_vec(dev);
1336 /* Make sure all is clean before doing PF reset */
1339 /* Reset here to make sure all is clean for each PF */
1340 ret = i40e_pf_reset(hw);
1342 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1346 /* Initialize the shared code (base driver) */
1347 ret = i40e_init_shared_code(hw);
1349 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1353 /* Initialize the parameters for adminq */
1354 i40e_init_adminq_parameter(hw);
1355 ret = i40e_init_adminq(hw);
1356 if (ret != I40E_SUCCESS) {
1357 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1360 /* Firmware of SFP x722 does not support adminq option */
1361 if (hw->device_id == I40E_DEV_ID_SFP_X722)
1362 hw->flags &= ~I40E_HW_FLAG_802_1AD_CAPABLE;
1364 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1365 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1366 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1367 ((hw->nvm.version >> 12) & 0xf),
1368 ((hw->nvm.version >> 4) & 0xff),
1369 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1371 /* Initialize the hardware */
1374 i40e_config_automask(pf);
1376 i40e_set_default_pctype_table(dev);
1379 * To work around the NVM issue, initialize registers
1380 * for packet type of QinQ by software.
1381 * It should be removed once issues are fixed in NVM.
1383 if (!pf->support_multi_driver)
1384 i40e_GLQF_reg_init(hw);
1386 /* Initialize the input set for filters (hash and fd) to default value */
1387 i40e_filter_input_set_init(pf);
1389 /* initialise the L3_MAP register */
1390 if (!pf->support_multi_driver) {
1391 ret = i40e_aq_debug_write_global_register(hw,
1392 I40E_GLQF_L3_MAP(40),
1395 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1398 "Global register 0x%08x is changed with 0x28",
1399 I40E_GLQF_L3_MAP(40));
1402 /* Need the special FW version to support floating VEB */
1403 config_floating_veb(dev);
1404 /* Clear PXE mode */
1405 i40e_clear_pxe_mode(hw);
1406 i40e_dev_sync_phy_type(hw);
1409 * On X710, performance number is far from the expectation on recent
1410 * firmware versions. The fix for this issue may not be integrated in
1411 * the following firmware version. So the workaround in software driver
1412 * is needed. It needs to modify the initial values of 3 internal only
1413 * registers. Note that the workaround can be removed when it is fixed
1414 * in firmware in the future.
1416 i40e_configure_registers(hw);
1418 /* Get hw capabilities */
1419 ret = i40e_get_cap(hw);
1420 if (ret != I40E_SUCCESS) {
1421 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1422 goto err_get_capabilities;
1425 /* Initialize parameters for PF */
1426 ret = i40e_pf_parameter_init(dev);
1428 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1429 goto err_parameter_init;
1432 /* Initialize the queue management */
1433 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1435 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1436 goto err_qp_pool_init;
1438 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1439 hw->func_caps.num_msix_vectors - 1);
1441 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1442 goto err_msix_pool_init;
1445 /* Initialize lan hmc */
1446 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1447 hw->func_caps.num_rx_qp, 0, 0);
1448 if (ret != I40E_SUCCESS) {
1449 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1450 goto err_init_lan_hmc;
1453 /* Configure lan hmc */
1454 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1455 if (ret != I40E_SUCCESS) {
1456 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1457 goto err_configure_lan_hmc;
1460 /* Get and check the mac address */
1461 i40e_get_mac_addr(hw, hw->mac.addr);
1462 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1463 PMD_INIT_LOG(ERR, "mac address is not valid");
1465 goto err_get_mac_addr;
1467 /* Copy the permanent MAC address */
1468 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1469 (struct rte_ether_addr *)hw->mac.perm_addr);
1471 /* Disable flow control */
1472 hw->fc.requested_mode = I40E_FC_NONE;
1473 i40e_set_fc(hw, &aq_fail, TRUE);
1475 /* Set the global registers with default ether type value */
1476 if (!pf->support_multi_driver) {
1477 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1478 RTE_ETHER_TYPE_VLAN);
1479 if (ret != I40E_SUCCESS) {
1481 "Failed to set the default outer "
1483 goto err_setup_pf_switch;
1487 /* PF setup, which includes VSI setup */
1488 ret = i40e_pf_setup(pf);
1490 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1491 goto err_setup_pf_switch;
1496 /* Disable double vlan by default */
1497 i40e_vsi_config_double_vlan(vsi, FALSE);
1499 /* Disable S-TAG identification when floating_veb is disabled */
1500 if (!pf->floating_veb) {
1501 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1502 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1503 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1504 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1508 if (!vsi->max_macaddrs)
1509 len = RTE_ETHER_ADDR_LEN;
1511 len = RTE_ETHER_ADDR_LEN * vsi->max_macaddrs;
1513 /* Should be after VSI initialized */
1514 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1515 if (!dev->data->mac_addrs) {
1517 "Failed to allocated memory for storing mac address");
1520 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1521 &dev->data->mac_addrs[0]);
1523 /* Init dcb to sw mode by default */
1524 ret = i40e_dcb_init_configure(dev, TRUE);
1525 if (ret != I40E_SUCCESS) {
1526 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1527 pf->flags &= ~I40E_FLAG_DCB;
1529 /* Update HW struct after DCB configuration */
1532 /* initialize pf host driver to setup SRIOV resource if applicable */
1533 i40e_pf_host_init(dev);
1535 /* register callback func to eal lib */
1536 rte_intr_callback_register(intr_handle,
1537 i40e_dev_interrupt_handler, dev);
1539 /* configure and enable device interrupt */
1540 i40e_pf_config_irq0(hw, TRUE);
1541 i40e_pf_enable_irq0(hw);
1543 /* enable uio intr after callback register */
1544 rte_intr_enable(intr_handle);
1546 /* By default disable flexible payload in global configuration */
1547 if (!pf->support_multi_driver)
1548 i40e_flex_payload_reg_set_default(hw);
1551 * Add an ethertype filter to drop all flow control frames transmitted
1552 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1555 i40e_add_tx_flow_control_drop_filter(pf);
1557 /* Set the max frame size to 0x2600 by default,
1558 * in case other drivers changed the default value.
1560 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1562 /* initialize mirror rule list */
1563 TAILQ_INIT(&pf->mirror_list);
1565 /* initialize Traffic Manager configuration */
1566 i40e_tm_conf_init(dev);
1568 /* Initialize customized information */
1569 i40e_init_customized_info(pf);
1571 ret = i40e_init_ethtype_filter_list(dev);
1573 goto err_init_ethtype_filter_list;
1574 ret = i40e_init_tunnel_filter_list(dev);
1576 goto err_init_tunnel_filter_list;
1577 ret = i40e_init_fdir_filter_list(dev);
1579 goto err_init_fdir_filter_list;
1581 /* initialize queue region configuration */
1582 i40e_init_queue_region_conf(dev);
1584 /* initialize rss configuration from rte_flow */
1585 memset(&pf->rss_info, 0,
1586 sizeof(struct i40e_rte_flow_rss_conf));
1588 /* reset all stats of the device, including pf and main vsi */
1589 i40e_dev_stats_reset(dev);
1593 err_init_fdir_filter_list:
1594 rte_free(pf->tunnel.hash_table);
1595 rte_free(pf->tunnel.hash_map);
1596 err_init_tunnel_filter_list:
1597 rte_free(pf->ethertype.hash_table);
1598 rte_free(pf->ethertype.hash_map);
1599 err_init_ethtype_filter_list:
1600 rte_free(dev->data->mac_addrs);
1601 dev->data->mac_addrs = NULL;
1603 i40e_vsi_release(pf->main_vsi);
1604 err_setup_pf_switch:
1606 err_configure_lan_hmc:
1607 (void)i40e_shutdown_lan_hmc(hw);
1609 i40e_res_pool_destroy(&pf->msix_pool);
1611 i40e_res_pool_destroy(&pf->qp_pool);
1614 err_get_capabilities:
1615 (void)i40e_shutdown_adminq(hw);
1621 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1623 struct i40e_ethertype_filter *p_ethertype;
1624 struct i40e_ethertype_rule *ethertype_rule;
1626 ethertype_rule = &pf->ethertype;
1627 /* Remove all ethertype filter rules and hash */
1628 if (ethertype_rule->hash_map)
1629 rte_free(ethertype_rule->hash_map);
1630 if (ethertype_rule->hash_table)
1631 rte_hash_free(ethertype_rule->hash_table);
1633 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1634 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1635 p_ethertype, rules);
1636 rte_free(p_ethertype);
1641 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1643 struct i40e_tunnel_filter *p_tunnel;
1644 struct i40e_tunnel_rule *tunnel_rule;
1646 tunnel_rule = &pf->tunnel;
1647 /* Remove all tunnel director rules and hash */
1648 if (tunnel_rule->hash_map)
1649 rte_free(tunnel_rule->hash_map);
1650 if (tunnel_rule->hash_table)
1651 rte_hash_free(tunnel_rule->hash_table);
1653 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1654 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1660 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1662 struct i40e_fdir_filter *p_fdir;
1663 struct i40e_fdir_info *fdir_info;
1665 fdir_info = &pf->fdir;
1666 /* Remove all flow director rules and hash */
1667 if (fdir_info->hash_map)
1668 rte_free(fdir_info->hash_map);
1669 if (fdir_info->hash_table)
1670 rte_hash_free(fdir_info->hash_table);
1672 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1673 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1678 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1681 * Disable by default flexible payload
1682 * for corresponding L2/L3/L4 layers.
1684 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1685 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1686 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1690 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1693 struct rte_pci_device *pci_dev;
1694 struct rte_intr_handle *intr_handle;
1696 struct i40e_filter_control_settings settings;
1697 struct rte_flow *p_flow;
1699 uint8_t aq_fail = 0;
1702 PMD_INIT_FUNC_TRACE();
1704 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1707 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1708 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1709 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1710 intr_handle = &pci_dev->intr_handle;
1712 ret = rte_eth_switch_domain_free(pf->switch_domain_id);
1714 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
1716 if (hw->adapter_closed == 0)
1717 i40e_dev_close(dev);
1719 dev->dev_ops = NULL;
1720 dev->rx_pkt_burst = NULL;
1721 dev->tx_pkt_burst = NULL;
1723 /* Clear PXE mode */
1724 i40e_clear_pxe_mode(hw);
1726 /* Unconfigure filter control */
1727 memset(&settings, 0, sizeof(settings));
1728 ret = i40e_set_filter_control(hw, &settings);
1730 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1733 /* Disable flow control */
1734 hw->fc.requested_mode = I40E_FC_NONE;
1735 i40e_set_fc(hw, &aq_fail, TRUE);
1737 /* uninitialize pf host driver */
1738 i40e_pf_host_uninit(dev);
1740 /* disable uio intr before callback unregister */
1741 rte_intr_disable(intr_handle);
1743 /* unregister callback func to eal lib */
1745 ret = rte_intr_callback_unregister(intr_handle,
1746 i40e_dev_interrupt_handler, dev);
1749 } else if (ret != -EAGAIN) {
1751 "intr callback unregister failed: %d",
1755 i40e_msec_delay(500);
1756 } while (retries++ < 5);
1758 i40e_rm_ethtype_filter_list(pf);
1759 i40e_rm_tunnel_filter_list(pf);
1760 i40e_rm_fdir_filter_list(pf);
1762 /* Remove all flows */
1763 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1764 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1768 /* Remove all Traffic Manager configuration */
1769 i40e_tm_conf_uninit(dev);
1775 i40e_dev_configure(struct rte_eth_dev *dev)
1777 struct i40e_adapter *ad =
1778 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1779 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1780 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1781 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1784 ret = i40e_dev_sync_phy_type(hw);
1788 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1789 * bulk allocation or vector Rx preconditions we will reset it.
1791 ad->rx_bulk_alloc_allowed = true;
1792 ad->rx_vec_allowed = true;
1793 ad->tx_simple_allowed = true;
1794 ad->tx_vec_allowed = true;
1796 /* Only legacy filter API needs the following fdir config. So when the
1797 * legacy filter API is deprecated, the following codes should also be
1800 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1801 ret = i40e_fdir_setup(pf);
1802 if (ret != I40E_SUCCESS) {
1803 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1806 ret = i40e_fdir_configure(dev);
1808 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1812 i40e_fdir_teardown(pf);
1814 ret = i40e_dev_init_vlan(dev);
1819 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1820 * RSS setting have different requirements.
1821 * General PMD driver call sequence are NIC init, configure,
1822 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1823 * will try to lookup the VSI that specific queue belongs to if VMDQ
1824 * applicable. So, VMDQ setting has to be done before
1825 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1826 * For RSS setting, it will try to calculate actual configured RX queue
1827 * number, which will be available after rx_queue_setup(). dev_start()
1828 * function is good to place RSS setup.
1830 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1831 ret = i40e_vmdq_setup(dev);
1836 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1837 ret = i40e_dcb_setup(dev);
1839 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1844 TAILQ_INIT(&pf->flow_list);
1849 /* need to release vmdq resource if exists */
1850 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1851 i40e_vsi_release(pf->vmdq[i].vsi);
1852 pf->vmdq[i].vsi = NULL;
1857 /* Need to release fdir resource if exists.
1858 * Only legacy filter API needs the following fdir config. So when the
1859 * legacy filter API is deprecated, the following code should also be
1862 i40e_fdir_teardown(pf);
1867 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1869 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1870 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1871 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1872 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1873 uint16_t msix_vect = vsi->msix_intr;
1876 for (i = 0; i < vsi->nb_qps; i++) {
1877 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1878 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1882 if (vsi->type != I40E_VSI_SRIOV) {
1883 if (!rte_intr_allow_others(intr_handle)) {
1884 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1885 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1887 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1890 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1891 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1893 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1898 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1899 vsi->user_param + (msix_vect - 1);
1901 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1902 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1904 I40E_WRITE_FLUSH(hw);
1908 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1909 int base_queue, int nb_queue,
1914 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1915 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1917 /* Bind all RX queues to allocated MSIX interrupt */
1918 for (i = 0; i < nb_queue; i++) {
1919 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1920 itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1921 ((base_queue + i + 1) <<
1922 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1923 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1924 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1926 if (i == nb_queue - 1)
1927 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1928 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1931 /* Write first RX queue to Link list register as the head element */
1932 if (vsi->type != I40E_VSI_SRIOV) {
1934 i40e_calc_itr_interval(1, pf->support_multi_driver);
1936 if (msix_vect == I40E_MISC_VEC_ID) {
1937 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1939 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1941 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1943 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1946 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1948 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1950 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1952 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1959 if (msix_vect == I40E_MISC_VEC_ID) {
1961 I40E_VPINT_LNKLST0(vsi->user_param),
1963 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1965 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1967 /* num_msix_vectors_vf needs to minus irq0 */
1968 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1969 vsi->user_param + (msix_vect - 1);
1971 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1973 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1975 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1979 I40E_WRITE_FLUSH(hw);
1983 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1985 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1986 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1987 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1988 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1989 uint16_t msix_vect = vsi->msix_intr;
1990 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1991 uint16_t queue_idx = 0;
1995 for (i = 0; i < vsi->nb_qps; i++) {
1996 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1997 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2000 /* VF bind interrupt */
2001 if (vsi->type == I40E_VSI_SRIOV) {
2002 __vsi_queues_bind_intr(vsi, msix_vect,
2003 vsi->base_queue, vsi->nb_qps,
2008 /* PF & VMDq bind interrupt */
2009 if (rte_intr_dp_is_en(intr_handle)) {
2010 if (vsi->type == I40E_VSI_MAIN) {
2013 } else if (vsi->type == I40E_VSI_VMDQ2) {
2014 struct i40e_vsi *main_vsi =
2015 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2016 queue_idx = vsi->base_queue - main_vsi->nb_qps;
2021 for (i = 0; i < vsi->nb_used_qps; i++) {
2023 if (!rte_intr_allow_others(intr_handle))
2024 /* allow to share MISC_VEC_ID */
2025 msix_vect = I40E_MISC_VEC_ID;
2027 /* no enough msix_vect, map all to one */
2028 __vsi_queues_bind_intr(vsi, msix_vect,
2029 vsi->base_queue + i,
2030 vsi->nb_used_qps - i,
2032 for (; !!record && i < vsi->nb_used_qps; i++)
2033 intr_handle->intr_vec[queue_idx + i] =
2037 /* 1:1 queue/msix_vect mapping */
2038 __vsi_queues_bind_intr(vsi, msix_vect,
2039 vsi->base_queue + i, 1,
2042 intr_handle->intr_vec[queue_idx + i] = msix_vect;
2050 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2052 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2053 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2054 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2055 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2056 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2057 uint16_t msix_intr, i;
2059 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2060 for (i = 0; i < vsi->nb_msix; i++) {
2061 msix_intr = vsi->msix_intr + i;
2062 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2063 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2064 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2065 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2068 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2069 I40E_PFINT_DYN_CTL0_INTENA_MASK |
2070 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2071 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2073 I40E_WRITE_FLUSH(hw);
2077 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2079 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2080 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2081 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2082 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2083 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2084 uint16_t msix_intr, i;
2086 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2087 for (i = 0; i < vsi->nb_msix; i++) {
2088 msix_intr = vsi->msix_intr + i;
2089 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2090 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2093 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2094 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2096 I40E_WRITE_FLUSH(hw);
2099 static inline uint8_t
2100 i40e_parse_link_speeds(uint16_t link_speeds)
2102 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2104 if (link_speeds & ETH_LINK_SPEED_40G)
2105 link_speed |= I40E_LINK_SPEED_40GB;
2106 if (link_speeds & ETH_LINK_SPEED_25G)
2107 link_speed |= I40E_LINK_SPEED_25GB;
2108 if (link_speeds & ETH_LINK_SPEED_20G)
2109 link_speed |= I40E_LINK_SPEED_20GB;
2110 if (link_speeds & ETH_LINK_SPEED_10G)
2111 link_speed |= I40E_LINK_SPEED_10GB;
2112 if (link_speeds & ETH_LINK_SPEED_1G)
2113 link_speed |= I40E_LINK_SPEED_1GB;
2114 if (link_speeds & ETH_LINK_SPEED_100M)
2115 link_speed |= I40E_LINK_SPEED_100MB;
2121 i40e_phy_conf_link(struct i40e_hw *hw,
2123 uint8_t force_speed,
2126 enum i40e_status_code status;
2127 struct i40e_aq_get_phy_abilities_resp phy_ab;
2128 struct i40e_aq_set_phy_config phy_conf;
2129 enum i40e_aq_phy_type cnt;
2130 uint8_t avail_speed;
2131 uint32_t phy_type_mask = 0;
2133 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2134 I40E_AQ_PHY_FLAG_PAUSE_RX |
2135 I40E_AQ_PHY_FLAG_PAUSE_RX |
2136 I40E_AQ_PHY_FLAG_LOW_POWER;
2139 /* To get phy capabilities of available speeds. */
2140 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2143 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2147 avail_speed = phy_ab.link_speed;
2149 /* To get the current phy config. */
2150 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2153 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2158 /* If link needs to go up and it is in autoneg mode the speed is OK,
2159 * no need to set up again.
2161 if (is_up && phy_ab.phy_type != 0 &&
2162 abilities & I40E_AQ_PHY_AN_ENABLED &&
2163 phy_ab.link_speed != 0)
2164 return I40E_SUCCESS;
2166 memset(&phy_conf, 0, sizeof(phy_conf));
2168 /* bits 0-2 use the values from get_phy_abilities_resp */
2170 abilities |= phy_ab.abilities & mask;
2172 phy_conf.abilities = abilities;
2174 /* If link needs to go up, but the force speed is not supported,
2175 * Warn users and config the default available speeds.
2177 if (is_up && !(force_speed & avail_speed)) {
2178 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2179 phy_conf.link_speed = avail_speed;
2181 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2184 /* PHY type mask needs to include each type except PHY type extension */
2185 for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2186 phy_type_mask |= 1 << cnt;
2188 /* use get_phy_abilities_resp value for the rest */
2189 phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2190 phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2191 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2192 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2193 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2194 phy_conf.eee_capability = phy_ab.eee_capability;
2195 phy_conf.eeer = phy_ab.eeer_val;
2196 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2198 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2199 phy_ab.abilities, phy_ab.link_speed);
2200 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
2201 phy_conf.abilities, phy_conf.link_speed);
2203 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2207 return I40E_SUCCESS;
2211 i40e_apply_link_speed(struct rte_eth_dev *dev)
2214 uint8_t abilities = 0;
2215 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2216 struct rte_eth_conf *conf = &dev->data->dev_conf;
2218 if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2219 conf->link_speeds = ETH_LINK_SPEED_40G |
2220 ETH_LINK_SPEED_25G |
2221 ETH_LINK_SPEED_20G |
2222 ETH_LINK_SPEED_10G |
2224 ETH_LINK_SPEED_100M;
2226 speed = i40e_parse_link_speeds(conf->link_speeds);
2227 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2228 I40E_AQ_PHY_AN_ENABLED |
2229 I40E_AQ_PHY_LINK_ENABLED;
2231 return i40e_phy_conf_link(hw, abilities, speed, true);
2235 i40e_dev_start(struct rte_eth_dev *dev)
2237 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2238 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2239 struct i40e_vsi *main_vsi = pf->main_vsi;
2241 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2242 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2243 uint32_t intr_vector = 0;
2244 struct i40e_vsi *vsi;
2246 hw->adapter_stopped = 0;
2248 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2250 "Invalid link_speeds for port %u, autonegotiation disabled",
2251 dev->data->port_id);
2255 rte_intr_disable(intr_handle);
2257 if ((rte_intr_cap_multiple(intr_handle) ||
2258 !RTE_ETH_DEV_SRIOV(dev).active) &&
2259 dev->data->dev_conf.intr_conf.rxq != 0) {
2260 intr_vector = dev->data->nb_rx_queues;
2261 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2266 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2267 intr_handle->intr_vec =
2268 rte_zmalloc("intr_vec",
2269 dev->data->nb_rx_queues * sizeof(int),
2271 if (!intr_handle->intr_vec) {
2273 "Failed to allocate %d rx_queues intr_vec",
2274 dev->data->nb_rx_queues);
2279 /* Initialize VSI */
2280 ret = i40e_dev_rxtx_init(pf);
2281 if (ret != I40E_SUCCESS) {
2282 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2286 /* Map queues with MSIX interrupt */
2287 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2288 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2289 i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2290 i40e_vsi_enable_queues_intr(main_vsi);
2292 /* Map VMDQ VSI queues with MSIX interrupt */
2293 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2294 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2295 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2296 I40E_ITR_INDEX_DEFAULT);
2297 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2300 /* enable FDIR MSIX interrupt */
2301 if (pf->fdir.fdir_vsi) {
2302 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2303 I40E_ITR_INDEX_NONE);
2304 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2307 /* Enable all queues which have been configured */
2308 ret = i40e_dev_switch_queues(pf, TRUE);
2309 if (ret != I40E_SUCCESS) {
2310 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2314 /* Enable receiving broadcast packets */
2315 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2316 if (ret != I40E_SUCCESS)
2317 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2319 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2320 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2322 if (ret != I40E_SUCCESS)
2323 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2326 /* Enable the VLAN promiscuous mode. */
2328 for (i = 0; i < pf->vf_num; i++) {
2329 vsi = pf->vfs[i].vsi;
2330 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2335 /* Enable mac loopback mode */
2336 if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2337 dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2338 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2339 if (ret != I40E_SUCCESS) {
2340 PMD_DRV_LOG(ERR, "fail to set loopback link");
2345 /* Apply link configure */
2346 ret = i40e_apply_link_speed(dev);
2347 if (I40E_SUCCESS != ret) {
2348 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2352 if (!rte_intr_allow_others(intr_handle)) {
2353 rte_intr_callback_unregister(intr_handle,
2354 i40e_dev_interrupt_handler,
2356 /* configure and enable device interrupt */
2357 i40e_pf_config_irq0(hw, FALSE);
2358 i40e_pf_enable_irq0(hw);
2360 if (dev->data->dev_conf.intr_conf.lsc != 0)
2362 "lsc won't enable because of no intr multiplex");
2364 ret = i40e_aq_set_phy_int_mask(hw,
2365 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2366 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2367 I40E_AQ_EVENT_MEDIA_NA), NULL);
2368 if (ret != I40E_SUCCESS)
2369 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2371 /* Call get_link_info aq commond to enable/disable LSE */
2372 i40e_dev_link_update(dev, 0);
2375 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2376 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2377 i40e_dev_alarm_handler, dev);
2379 /* enable uio intr after callback register */
2380 rte_intr_enable(intr_handle);
2383 i40e_filter_restore(pf);
2385 if (pf->tm_conf.root && !pf->tm_conf.committed)
2386 PMD_DRV_LOG(WARNING,
2387 "please call hierarchy_commit() "
2388 "before starting the port");
2390 return I40E_SUCCESS;
2393 i40e_dev_switch_queues(pf, FALSE);
2394 i40e_dev_clear_queues(dev);
2400 i40e_dev_stop(struct rte_eth_dev *dev)
2402 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2403 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2404 struct i40e_vsi *main_vsi = pf->main_vsi;
2405 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2406 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2409 if (hw->adapter_stopped == 1)
2412 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2413 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2414 rte_intr_enable(intr_handle);
2417 /* Disable all queues */
2418 i40e_dev_switch_queues(pf, FALSE);
2420 /* un-map queues with interrupt registers */
2421 i40e_vsi_disable_queues_intr(main_vsi);
2422 i40e_vsi_queues_unbind_intr(main_vsi);
2424 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2425 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2426 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2429 if (pf->fdir.fdir_vsi) {
2430 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2431 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2433 /* Clear all queues and release memory */
2434 i40e_dev_clear_queues(dev);
2437 i40e_dev_set_link_down(dev);
2439 if (!rte_intr_allow_others(intr_handle))
2440 /* resume to the default handler */
2441 rte_intr_callback_register(intr_handle,
2442 i40e_dev_interrupt_handler,
2445 /* Clean datapath event and queue/vec mapping */
2446 rte_intr_efd_disable(intr_handle);
2447 if (intr_handle->intr_vec) {
2448 rte_free(intr_handle->intr_vec);
2449 intr_handle->intr_vec = NULL;
2452 /* reset hierarchy commit */
2453 pf->tm_conf.committed = false;
2455 hw->adapter_stopped = 1;
2457 pf->adapter->rss_reta_updated = 0;
2461 i40e_dev_close(struct rte_eth_dev *dev)
2463 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2464 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2465 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2466 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2467 struct i40e_mirror_rule *p_mirror;
2472 PMD_INIT_FUNC_TRACE();
2476 /* Remove all mirror rules */
2477 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2478 ret = i40e_aq_del_mirror_rule(hw,
2479 pf->main_vsi->veb->seid,
2480 p_mirror->rule_type,
2482 p_mirror->num_entries,
2485 PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2486 "status = %d, aq_err = %d.", ret,
2487 hw->aq.asq_last_status);
2489 /* remove mirror software resource anyway */
2490 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2492 pf->nb_mirror_rule--;
2495 i40e_dev_free_queues(dev);
2497 /* Disable interrupt */
2498 i40e_pf_disable_irq0(hw);
2499 rte_intr_disable(intr_handle);
2502 * Only legacy filter API needs the following fdir config. So when the
2503 * legacy filter API is deprecated, the following code should also be
2506 i40e_fdir_teardown(pf);
2508 /* shutdown and destroy the HMC */
2509 i40e_shutdown_lan_hmc(hw);
2511 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2512 i40e_vsi_release(pf->vmdq[i].vsi);
2513 pf->vmdq[i].vsi = NULL;
2518 /* release all the existing VSIs and VEBs */
2519 i40e_vsi_release(pf->main_vsi);
2521 /* shutdown the adminq */
2522 i40e_aq_queue_shutdown(hw, true);
2523 i40e_shutdown_adminq(hw);
2525 i40e_res_pool_destroy(&pf->qp_pool);
2526 i40e_res_pool_destroy(&pf->msix_pool);
2528 /* Disable flexible payload in global configuration */
2529 if (!pf->support_multi_driver)
2530 i40e_flex_payload_reg_set_default(hw);
2532 /* force a PF reset to clean anything leftover */
2533 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2534 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2535 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2536 I40E_WRITE_FLUSH(hw);
2538 hw->adapter_closed = 1;
2542 * Reset PF device only to re-initialize resources in PMD layer
2545 i40e_dev_reset(struct rte_eth_dev *dev)
2549 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2550 * its VF to make them align with it. The detailed notification
2551 * mechanism is PMD specific. As to i40e PF, it is rather complex.
2552 * To avoid unexpected behavior in VF, currently reset of PF with
2553 * SR-IOV activation is not supported. It might be supported later.
2555 if (dev->data->sriov.active)
2558 ret = eth_i40e_dev_uninit(dev);
2562 ret = eth_i40e_dev_init(dev, NULL);
2568 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2570 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2571 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2572 struct i40e_vsi *vsi = pf->main_vsi;
2575 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2577 if (status != I40E_SUCCESS) {
2578 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2582 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2584 if (status != I40E_SUCCESS) {
2585 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2586 /* Rollback unicast promiscuous mode */
2587 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2596 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2598 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2599 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2600 struct i40e_vsi *vsi = pf->main_vsi;
2603 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2605 if (status != I40E_SUCCESS) {
2606 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2610 /* must remain in all_multicast mode */
2611 if (dev->data->all_multicast == 1)
2614 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2616 if (status != I40E_SUCCESS) {
2617 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2618 /* Rollback unicast promiscuous mode */
2619 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2628 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2630 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2631 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2632 struct i40e_vsi *vsi = pf->main_vsi;
2635 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2636 if (ret != I40E_SUCCESS)
2637 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2641 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2643 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2644 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2645 struct i40e_vsi *vsi = pf->main_vsi;
2648 if (dev->data->promiscuous == 1)
2649 return; /* must remain in all_multicast mode */
2651 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2652 vsi->seid, FALSE, NULL);
2653 if (ret != I40E_SUCCESS)
2654 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2658 * Set device link up.
2661 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2663 /* re-apply link speed setting */
2664 return i40e_apply_link_speed(dev);
2668 * Set device link down.
2671 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2673 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2674 uint8_t abilities = 0;
2675 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2677 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2678 return i40e_phy_conf_link(hw, abilities, speed, false);
2681 static __rte_always_inline void
2682 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2684 /* Link status registers and values*/
2685 #define I40E_PRTMAC_LINKSTA 0x001E2420
2686 #define I40E_REG_LINK_UP 0x40000080
2687 #define I40E_PRTMAC_MACC 0x001E24E0
2688 #define I40E_REG_MACC_25GB 0x00020000
2689 #define I40E_REG_SPEED_MASK 0x38000000
2690 #define I40E_REG_SPEED_0 0x00000000
2691 #define I40E_REG_SPEED_1 0x08000000
2692 #define I40E_REG_SPEED_2 0x10000000
2693 #define I40E_REG_SPEED_3 0x18000000
2694 #define I40E_REG_SPEED_4 0x20000000
2695 uint32_t link_speed;
2698 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2699 link_speed = reg_val & I40E_REG_SPEED_MASK;
2700 reg_val &= I40E_REG_LINK_UP;
2701 link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2703 if (unlikely(link->link_status == 0))
2706 /* Parse the link status */
2707 switch (link_speed) {
2708 case I40E_REG_SPEED_0:
2709 link->link_speed = ETH_SPEED_NUM_100M;
2711 case I40E_REG_SPEED_1:
2712 link->link_speed = ETH_SPEED_NUM_1G;
2714 case I40E_REG_SPEED_2:
2715 if (hw->mac.type == I40E_MAC_X722)
2716 link->link_speed = ETH_SPEED_NUM_2_5G;
2718 link->link_speed = ETH_SPEED_NUM_10G;
2720 case I40E_REG_SPEED_3:
2721 if (hw->mac.type == I40E_MAC_X722) {
2722 link->link_speed = ETH_SPEED_NUM_5G;
2724 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2726 if (reg_val & I40E_REG_MACC_25GB)
2727 link->link_speed = ETH_SPEED_NUM_25G;
2729 link->link_speed = ETH_SPEED_NUM_40G;
2732 case I40E_REG_SPEED_4:
2733 if (hw->mac.type == I40E_MAC_X722)
2734 link->link_speed = ETH_SPEED_NUM_10G;
2736 link->link_speed = ETH_SPEED_NUM_20G;
2739 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2744 static __rte_always_inline void
2745 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2746 bool enable_lse, int wait_to_complete)
2748 #define CHECK_INTERVAL 100 /* 100ms */
2749 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2750 uint32_t rep_cnt = MAX_REPEAT_TIME;
2751 struct i40e_link_status link_status;
2754 memset(&link_status, 0, sizeof(link_status));
2757 memset(&link_status, 0, sizeof(link_status));
2759 /* Get link status information from hardware */
2760 status = i40e_aq_get_link_info(hw, enable_lse,
2761 &link_status, NULL);
2762 if (unlikely(status != I40E_SUCCESS)) {
2763 link->link_speed = ETH_SPEED_NUM_100M;
2764 link->link_duplex = ETH_LINK_FULL_DUPLEX;
2765 PMD_DRV_LOG(ERR, "Failed to get link info");
2769 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2770 if (!wait_to_complete || link->link_status)
2773 rte_delay_ms(CHECK_INTERVAL);
2774 } while (--rep_cnt);
2776 /* Parse the link status */
2777 switch (link_status.link_speed) {
2778 case I40E_LINK_SPEED_100MB:
2779 link->link_speed = ETH_SPEED_NUM_100M;
2781 case I40E_LINK_SPEED_1GB:
2782 link->link_speed = ETH_SPEED_NUM_1G;
2784 case I40E_LINK_SPEED_10GB:
2785 link->link_speed = ETH_SPEED_NUM_10G;
2787 case I40E_LINK_SPEED_20GB:
2788 link->link_speed = ETH_SPEED_NUM_20G;
2790 case I40E_LINK_SPEED_25GB:
2791 link->link_speed = ETH_SPEED_NUM_25G;
2793 case I40E_LINK_SPEED_40GB:
2794 link->link_speed = ETH_SPEED_NUM_40G;
2797 link->link_speed = ETH_SPEED_NUM_100M;
2803 i40e_dev_link_update(struct rte_eth_dev *dev,
2804 int wait_to_complete)
2806 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2807 struct rte_eth_link link;
2808 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2811 memset(&link, 0, sizeof(link));
2813 /* i40e uses full duplex only */
2814 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2815 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2816 ETH_LINK_SPEED_FIXED);
2818 if (!wait_to_complete && !enable_lse)
2819 update_link_reg(hw, &link);
2821 update_link_aq(hw, &link, enable_lse, wait_to_complete);
2823 ret = rte_eth_linkstatus_set(dev, &link);
2824 i40e_notify_all_vfs_link_status(dev);
2829 /* Get all the statistics of a VSI */
2831 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2833 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2834 struct i40e_eth_stats *nes = &vsi->eth_stats;
2835 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2836 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2838 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2839 vsi->offset_loaded, &oes->rx_bytes,
2841 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2842 vsi->offset_loaded, &oes->rx_unicast,
2844 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2845 vsi->offset_loaded, &oes->rx_multicast,
2846 &nes->rx_multicast);
2847 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2848 vsi->offset_loaded, &oes->rx_broadcast,
2849 &nes->rx_broadcast);
2850 /* exclude CRC bytes */
2851 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2852 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
2854 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2855 &oes->rx_discards, &nes->rx_discards);
2856 /* GLV_REPC not supported */
2857 /* GLV_RMPC not supported */
2858 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2859 &oes->rx_unknown_protocol,
2860 &nes->rx_unknown_protocol);
2861 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2862 vsi->offset_loaded, &oes->tx_bytes,
2864 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2865 vsi->offset_loaded, &oes->tx_unicast,
2867 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2868 vsi->offset_loaded, &oes->tx_multicast,
2869 &nes->tx_multicast);
2870 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2871 vsi->offset_loaded, &oes->tx_broadcast,
2872 &nes->tx_broadcast);
2873 /* GLV_TDPC not supported */
2874 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2875 &oes->tx_errors, &nes->tx_errors);
2876 vsi->offset_loaded = true;
2878 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2880 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2881 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2882 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2883 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2884 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2885 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2886 nes->rx_unknown_protocol);
2887 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2888 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2889 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2890 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2891 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2892 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2893 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2898 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2901 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2902 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2904 /* Get rx/tx bytes of internal transfer packets */
2905 i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2906 I40E_GLV_GORCL(hw->port),
2908 &pf->internal_stats_offset.rx_bytes,
2909 &pf->internal_stats.rx_bytes);
2911 i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2912 I40E_GLV_GOTCL(hw->port),
2914 &pf->internal_stats_offset.tx_bytes,
2915 &pf->internal_stats.tx_bytes);
2916 /* Get total internal rx packet count */
2917 i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2918 I40E_GLV_UPRCL(hw->port),
2920 &pf->internal_stats_offset.rx_unicast,
2921 &pf->internal_stats.rx_unicast);
2922 i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2923 I40E_GLV_MPRCL(hw->port),
2925 &pf->internal_stats_offset.rx_multicast,
2926 &pf->internal_stats.rx_multicast);
2927 i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2928 I40E_GLV_BPRCL(hw->port),
2930 &pf->internal_stats_offset.rx_broadcast,
2931 &pf->internal_stats.rx_broadcast);
2932 /* Get total internal tx packet count */
2933 i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
2934 I40E_GLV_UPTCL(hw->port),
2936 &pf->internal_stats_offset.tx_unicast,
2937 &pf->internal_stats.tx_unicast);
2938 i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
2939 I40E_GLV_MPTCL(hw->port),
2941 &pf->internal_stats_offset.tx_multicast,
2942 &pf->internal_stats.tx_multicast);
2943 i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
2944 I40E_GLV_BPTCL(hw->port),
2946 &pf->internal_stats_offset.tx_broadcast,
2947 &pf->internal_stats.tx_broadcast);
2949 /* exclude CRC size */
2950 pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2951 pf->internal_stats.rx_multicast +
2952 pf->internal_stats.rx_broadcast) * RTE_ETHER_CRC_LEN;
2954 /* Get statistics of struct i40e_eth_stats */
2955 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2956 I40E_GLPRT_GORCL(hw->port),
2957 pf->offset_loaded, &os->eth.rx_bytes,
2959 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2960 I40E_GLPRT_UPRCL(hw->port),
2961 pf->offset_loaded, &os->eth.rx_unicast,
2962 &ns->eth.rx_unicast);
2963 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2964 I40E_GLPRT_MPRCL(hw->port),
2965 pf->offset_loaded, &os->eth.rx_multicast,
2966 &ns->eth.rx_multicast);
2967 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2968 I40E_GLPRT_BPRCL(hw->port),
2969 pf->offset_loaded, &os->eth.rx_broadcast,
2970 &ns->eth.rx_broadcast);
2971 /* Workaround: CRC size should not be included in byte statistics,
2972 * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
2975 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2976 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
2978 /* exclude internal rx bytes
2979 * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2980 * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
2982 * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
2984 if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2985 ns->eth.rx_bytes = 0;
2987 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2989 if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
2990 ns->eth.rx_unicast = 0;
2992 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
2994 if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
2995 ns->eth.rx_multicast = 0;
2997 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
2999 if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
3000 ns->eth.rx_broadcast = 0;
3002 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
3004 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
3005 pf->offset_loaded, &os->eth.rx_discards,
3006 &ns->eth.rx_discards);
3007 /* GLPRT_REPC not supported */
3008 /* GLPRT_RMPC not supported */
3009 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
3011 &os->eth.rx_unknown_protocol,
3012 &ns->eth.rx_unknown_protocol);
3013 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
3014 I40E_GLPRT_GOTCL(hw->port),
3015 pf->offset_loaded, &os->eth.tx_bytes,
3017 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
3018 I40E_GLPRT_UPTCL(hw->port),
3019 pf->offset_loaded, &os->eth.tx_unicast,
3020 &ns->eth.tx_unicast);
3021 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
3022 I40E_GLPRT_MPTCL(hw->port),
3023 pf->offset_loaded, &os->eth.tx_multicast,
3024 &ns->eth.tx_multicast);
3025 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
3026 I40E_GLPRT_BPTCL(hw->port),
3027 pf->offset_loaded, &os->eth.tx_broadcast,
3028 &ns->eth.tx_broadcast);
3029 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3030 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3032 /* exclude internal tx bytes
3033 * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
3034 * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
3036 * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
3038 if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
3039 ns->eth.tx_bytes = 0;
3041 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3043 if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3044 ns->eth.tx_unicast = 0;
3046 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3048 if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3049 ns->eth.tx_multicast = 0;
3051 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3053 if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3054 ns->eth.tx_broadcast = 0;
3056 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3058 /* GLPRT_TEPC not supported */
3060 /* additional port specific stats */
3061 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3062 pf->offset_loaded, &os->tx_dropped_link_down,
3063 &ns->tx_dropped_link_down);
3064 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3065 pf->offset_loaded, &os->crc_errors,
3067 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3068 pf->offset_loaded, &os->illegal_bytes,
3069 &ns->illegal_bytes);
3070 /* GLPRT_ERRBC not supported */
3071 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3072 pf->offset_loaded, &os->mac_local_faults,
3073 &ns->mac_local_faults);
3074 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3075 pf->offset_loaded, &os->mac_remote_faults,
3076 &ns->mac_remote_faults);
3077 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3078 pf->offset_loaded, &os->rx_length_errors,
3079 &ns->rx_length_errors);
3080 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3081 pf->offset_loaded, &os->link_xon_rx,
3083 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3084 pf->offset_loaded, &os->link_xoff_rx,
3086 for (i = 0; i < 8; i++) {
3087 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3089 &os->priority_xon_rx[i],
3090 &ns->priority_xon_rx[i]);
3091 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3093 &os->priority_xoff_rx[i],
3094 &ns->priority_xoff_rx[i]);
3096 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3097 pf->offset_loaded, &os->link_xon_tx,
3099 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3100 pf->offset_loaded, &os->link_xoff_tx,
3102 for (i = 0; i < 8; i++) {
3103 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3105 &os->priority_xon_tx[i],
3106 &ns->priority_xon_tx[i]);
3107 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3109 &os->priority_xoff_tx[i],
3110 &ns->priority_xoff_tx[i]);
3111 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3113 &os->priority_xon_2_xoff[i],
3114 &ns->priority_xon_2_xoff[i]);
3116 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3117 I40E_GLPRT_PRC64L(hw->port),
3118 pf->offset_loaded, &os->rx_size_64,
3120 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3121 I40E_GLPRT_PRC127L(hw->port),
3122 pf->offset_loaded, &os->rx_size_127,
3124 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3125 I40E_GLPRT_PRC255L(hw->port),
3126 pf->offset_loaded, &os->rx_size_255,
3128 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3129 I40E_GLPRT_PRC511L(hw->port),
3130 pf->offset_loaded, &os->rx_size_511,
3132 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3133 I40E_GLPRT_PRC1023L(hw->port),
3134 pf->offset_loaded, &os->rx_size_1023,
3136 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3137 I40E_GLPRT_PRC1522L(hw->port),
3138 pf->offset_loaded, &os->rx_size_1522,
3140 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3141 I40E_GLPRT_PRC9522L(hw->port),
3142 pf->offset_loaded, &os->rx_size_big,
3144 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3145 pf->offset_loaded, &os->rx_undersize,
3147 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3148 pf->offset_loaded, &os->rx_fragments,
3150 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3151 pf->offset_loaded, &os->rx_oversize,
3153 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3154 pf->offset_loaded, &os->rx_jabber,
3156 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3157 I40E_GLPRT_PTC64L(hw->port),
3158 pf->offset_loaded, &os->tx_size_64,
3160 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3161 I40E_GLPRT_PTC127L(hw->port),
3162 pf->offset_loaded, &os->tx_size_127,
3164 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3165 I40E_GLPRT_PTC255L(hw->port),
3166 pf->offset_loaded, &os->tx_size_255,
3168 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3169 I40E_GLPRT_PTC511L(hw->port),
3170 pf->offset_loaded, &os->tx_size_511,
3172 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3173 I40E_GLPRT_PTC1023L(hw->port),
3174 pf->offset_loaded, &os->tx_size_1023,
3176 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3177 I40E_GLPRT_PTC1522L(hw->port),
3178 pf->offset_loaded, &os->tx_size_1522,
3180 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3181 I40E_GLPRT_PTC9522L(hw->port),
3182 pf->offset_loaded, &os->tx_size_big,
3184 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3186 &os->fd_sb_match, &ns->fd_sb_match);
3187 /* GLPRT_MSPDC not supported */
3188 /* GLPRT_XEC not supported */
3190 pf->offset_loaded = true;
3193 i40e_update_vsi_stats(pf->main_vsi);
3196 /* Get all statistics of a port */
3198 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3200 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3201 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3202 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3203 struct i40e_vsi *vsi;
3206 /* call read registers - updates values, now write them to struct */
3207 i40e_read_stats_registers(pf, hw);
3209 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3210 pf->main_vsi->eth_stats.rx_multicast +
3211 pf->main_vsi->eth_stats.rx_broadcast -
3212 pf->main_vsi->eth_stats.rx_discards;
3213 stats->opackets = ns->eth.tx_unicast +
3214 ns->eth.tx_multicast +
3215 ns->eth.tx_broadcast;
3216 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes;
3217 stats->obytes = ns->eth.tx_bytes;
3218 stats->oerrors = ns->eth.tx_errors +
3219 pf->main_vsi->eth_stats.tx_errors;
3222 stats->imissed = ns->eth.rx_discards +
3223 pf->main_vsi->eth_stats.rx_discards;
3224 stats->ierrors = ns->crc_errors +
3225 ns->rx_length_errors + ns->rx_undersize +
3226 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3229 for (i = 0; i < pf->vf_num; i++) {
3230 vsi = pf->vfs[i].vsi;
3231 i40e_update_vsi_stats(vsi);
3233 stats->ipackets += (vsi->eth_stats.rx_unicast +
3234 vsi->eth_stats.rx_multicast +
3235 vsi->eth_stats.rx_broadcast -
3236 vsi->eth_stats.rx_discards);
3237 stats->ibytes += vsi->eth_stats.rx_bytes;
3238 stats->oerrors += vsi->eth_stats.tx_errors;
3239 stats->imissed += vsi->eth_stats.rx_discards;
3243 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3244 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
3245 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
3246 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
3247 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
3248 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
3249 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3250 ns->eth.rx_unknown_protocol);
3251 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
3252 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
3253 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
3254 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
3255 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
3256 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
3258 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
3259 ns->tx_dropped_link_down);
3260 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
3261 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
3263 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
3264 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
3265 ns->mac_local_faults);
3266 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
3267 ns->mac_remote_faults);
3268 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
3269 ns->rx_length_errors);
3270 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
3271 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
3272 for (i = 0; i < 8; i++) {
3273 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
3274 i, ns->priority_xon_rx[i]);
3275 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
3276 i, ns->priority_xoff_rx[i]);
3278 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
3279 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
3280 for (i = 0; i < 8; i++) {
3281 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
3282 i, ns->priority_xon_tx[i]);
3283 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
3284 i, ns->priority_xoff_tx[i]);
3285 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
3286 i, ns->priority_xon_2_xoff[i]);
3288 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
3289 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
3290 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
3291 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
3292 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
3293 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
3294 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
3295 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
3296 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
3297 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
3298 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
3299 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
3300 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
3301 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
3302 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
3303 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
3304 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
3305 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
3306 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3307 ns->mac_short_packet_dropped);
3308 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
3309 ns->checksum_error);
3310 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
3311 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3315 /* Reset the statistics */
3317 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3319 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3320 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3322 /* Mark PF and VSI stats to update the offset, aka "reset" */
3323 pf->offset_loaded = false;
3325 pf->main_vsi->offset_loaded = false;
3327 /* read the stats, reading current register values into offset */
3328 i40e_read_stats_registers(pf, hw);
3334 i40e_xstats_calc_num(void)
3336 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3337 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3338 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3341 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3342 struct rte_eth_xstat_name *xstats_names,
3343 __rte_unused unsigned limit)
3348 if (xstats_names == NULL)
3349 return i40e_xstats_calc_num();
3351 /* Note: limit checked in rte_eth_xstats_names() */
3353 /* Get stats from i40e_eth_stats struct */
3354 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3355 strlcpy(xstats_names[count].name,
3356 rte_i40e_stats_strings[i].name,
3357 sizeof(xstats_names[count].name));
3361 /* Get individiual stats from i40e_hw_port struct */
3362 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3363 strlcpy(xstats_names[count].name,
3364 rte_i40e_hw_port_strings[i].name,
3365 sizeof(xstats_names[count].name));
3369 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3370 for (prio = 0; prio < 8; prio++) {
3371 snprintf(xstats_names[count].name,
3372 sizeof(xstats_names[count].name),
3373 "rx_priority%u_%s", prio,
3374 rte_i40e_rxq_prio_strings[i].name);
3379 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3380 for (prio = 0; prio < 8; prio++) {
3381 snprintf(xstats_names[count].name,
3382 sizeof(xstats_names[count].name),
3383 "tx_priority%u_%s", prio,
3384 rte_i40e_txq_prio_strings[i].name);
3392 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3395 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3396 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3397 unsigned i, count, prio;
3398 struct i40e_hw_port_stats *hw_stats = &pf->stats;
3400 count = i40e_xstats_calc_num();
3404 i40e_read_stats_registers(pf, hw);
3411 /* Get stats from i40e_eth_stats struct */
3412 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3413 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3414 rte_i40e_stats_strings[i].offset);
3415 xstats[count].id = count;
3419 /* Get individiual stats from i40e_hw_port struct */
3420 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3421 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3422 rte_i40e_hw_port_strings[i].offset);
3423 xstats[count].id = count;
3427 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3428 for (prio = 0; prio < 8; prio++) {
3429 xstats[count].value =
3430 *(uint64_t *)(((char *)hw_stats) +
3431 rte_i40e_rxq_prio_strings[i].offset +
3432 (sizeof(uint64_t) * prio));
3433 xstats[count].id = count;
3438 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3439 for (prio = 0; prio < 8; prio++) {
3440 xstats[count].value =
3441 *(uint64_t *)(((char *)hw_stats) +
3442 rte_i40e_txq_prio_strings[i].offset +
3443 (sizeof(uint64_t) * prio));
3444 xstats[count].id = count;
3453 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3455 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3461 full_ver = hw->nvm.oem_ver;
3462 ver = (u8)(full_ver >> 24);
3463 build = (u16)((full_ver >> 8) & 0xffff);
3464 patch = (u8)(full_ver & 0xff);
3466 ret = snprintf(fw_version, fw_size,
3467 "%d.%d%d 0x%08x %d.%d.%d",
3468 ((hw->nvm.version >> 12) & 0xf),
3469 ((hw->nvm.version >> 4) & 0xff),
3470 (hw->nvm.version & 0xf), hw->nvm.eetrack,
3473 ret += 1; /* add the size of '\0' */
3474 if (fw_size < (u32)ret)
3481 * When using NVM 6.01(for X710 XL710 XXV710)/3.33(for X722) or later,
3482 * the Rx data path does not hang if the FW LLDP is stopped.
3483 * return true if lldp need to stop
3484 * return false if we cannot disable the LLDP to avoid Rx data path blocking.
3487 i40e_need_stop_lldp(struct rte_eth_dev *dev)
3490 char ver_str[64] = {0};
3491 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3493 i40e_fw_version_get(dev, ver_str, 64);
3494 nvm_ver = atof(ver_str);
3495 if ((hw->mac.type == I40E_MAC_X722 ||
3496 hw->mac.type == I40E_MAC_X722_VF) &&
3497 ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(3.33 * 1000)))
3499 else if ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(6.01 * 1000))
3506 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3508 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3509 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3510 struct i40e_vsi *vsi = pf->main_vsi;
3511 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3513 dev_info->max_rx_queues = vsi->nb_qps;
3514 dev_info->max_tx_queues = vsi->nb_qps;
3515 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3516 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3517 dev_info->max_mac_addrs = vsi->max_macaddrs;
3518 dev_info->max_vfs = pci_dev->max_vfs;
3519 dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
3520 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3521 dev_info->rx_queue_offload_capa = 0;
3522 dev_info->rx_offload_capa =
3523 DEV_RX_OFFLOAD_VLAN_STRIP |
3524 DEV_RX_OFFLOAD_QINQ_STRIP |
3525 DEV_RX_OFFLOAD_IPV4_CKSUM |
3526 DEV_RX_OFFLOAD_UDP_CKSUM |
3527 DEV_RX_OFFLOAD_TCP_CKSUM |
3528 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3529 DEV_RX_OFFLOAD_KEEP_CRC |
3530 DEV_RX_OFFLOAD_SCATTER |
3531 DEV_RX_OFFLOAD_VLAN_EXTEND |
3532 DEV_RX_OFFLOAD_VLAN_FILTER |
3533 DEV_RX_OFFLOAD_JUMBO_FRAME;
3535 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3536 dev_info->tx_offload_capa =
3537 DEV_TX_OFFLOAD_VLAN_INSERT |
3538 DEV_TX_OFFLOAD_QINQ_INSERT |
3539 DEV_TX_OFFLOAD_IPV4_CKSUM |
3540 DEV_TX_OFFLOAD_UDP_CKSUM |
3541 DEV_TX_OFFLOAD_TCP_CKSUM |
3542 DEV_TX_OFFLOAD_SCTP_CKSUM |
3543 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3544 DEV_TX_OFFLOAD_TCP_TSO |
3545 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3546 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3547 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3548 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3549 DEV_TX_OFFLOAD_MULTI_SEGS |
3550 dev_info->tx_queue_offload_capa;
3551 dev_info->dev_capa =
3552 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3553 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3555 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3557 dev_info->reta_size = pf->hash_lut_size;
3558 dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3560 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3562 .pthresh = I40E_DEFAULT_RX_PTHRESH,
3563 .hthresh = I40E_DEFAULT_RX_HTHRESH,
3564 .wthresh = I40E_DEFAULT_RX_WTHRESH,
3566 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3571 dev_info->default_txconf = (struct rte_eth_txconf) {
3573 .pthresh = I40E_DEFAULT_TX_PTHRESH,
3574 .hthresh = I40E_DEFAULT_TX_HTHRESH,
3575 .wthresh = I40E_DEFAULT_TX_WTHRESH,
3577 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3578 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3582 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3583 .nb_max = I40E_MAX_RING_DESC,
3584 .nb_min = I40E_MIN_RING_DESC,
3585 .nb_align = I40E_ALIGN_RING_DESC,
3588 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3589 .nb_max = I40E_MAX_RING_DESC,
3590 .nb_min = I40E_MIN_RING_DESC,
3591 .nb_align = I40E_ALIGN_RING_DESC,
3592 .nb_seg_max = I40E_TX_MAX_SEG,
3593 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3596 if (pf->flags & I40E_FLAG_VMDQ) {
3597 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3598 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3599 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3600 pf->max_nb_vmdq_vsi;
3601 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3602 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3603 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3606 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3608 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3609 dev_info->default_rxportconf.nb_queues = 2;
3610 dev_info->default_txportconf.nb_queues = 2;
3611 if (dev->data->nb_rx_queues == 1)
3612 dev_info->default_rxportconf.ring_size = 2048;
3614 dev_info->default_rxportconf.ring_size = 1024;
3615 if (dev->data->nb_tx_queues == 1)
3616 dev_info->default_txportconf.ring_size = 1024;
3618 dev_info->default_txportconf.ring_size = 512;
3620 } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3622 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3623 dev_info->default_rxportconf.nb_queues = 1;
3624 dev_info->default_txportconf.nb_queues = 1;
3625 dev_info->default_rxportconf.ring_size = 256;
3626 dev_info->default_txportconf.ring_size = 256;
3629 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3630 dev_info->default_rxportconf.nb_queues = 1;
3631 dev_info->default_txportconf.nb_queues = 1;
3632 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3633 dev_info->default_rxportconf.ring_size = 512;
3634 dev_info->default_txportconf.ring_size = 256;
3636 dev_info->default_rxportconf.ring_size = 256;
3637 dev_info->default_txportconf.ring_size = 256;
3640 dev_info->default_rxportconf.burst_size = 32;
3641 dev_info->default_txportconf.burst_size = 32;
3647 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3649 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3650 struct i40e_vsi *vsi = pf->main_vsi;
3651 PMD_INIT_FUNC_TRACE();
3654 return i40e_vsi_add_vlan(vsi, vlan_id);
3656 return i40e_vsi_delete_vlan(vsi, vlan_id);
3660 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3661 enum rte_vlan_type vlan_type,
3662 uint16_t tpid, int qinq)
3664 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3667 uint16_t reg_id = 3;
3671 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3675 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3677 if (ret != I40E_SUCCESS) {
3679 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3684 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3687 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3688 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3689 if (reg_r == reg_w) {
3690 PMD_DRV_LOG(DEBUG, "No need to write");
3694 ret = i40e_aq_debug_write_global_register(hw,
3695 I40E_GL_SWT_L2TAGCTRL(reg_id),
3697 if (ret != I40E_SUCCESS) {
3699 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3704 "Global register 0x%08x is changed with value 0x%08x",
3705 I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3711 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3712 enum rte_vlan_type vlan_type,
3715 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3716 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3717 int qinq = dev->data->dev_conf.rxmode.offloads &
3718 DEV_RX_OFFLOAD_VLAN_EXTEND;
3721 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3722 vlan_type != ETH_VLAN_TYPE_OUTER) ||
3723 (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3725 "Unsupported vlan type.");
3729 if (pf->support_multi_driver) {
3730 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3734 /* 802.1ad frames ability is added in NVM API 1.7*/
3735 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3737 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3738 hw->first_tag = rte_cpu_to_le_16(tpid);
3739 else if (vlan_type == ETH_VLAN_TYPE_INNER)
3740 hw->second_tag = rte_cpu_to_le_16(tpid);
3742 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3743 hw->second_tag = rte_cpu_to_le_16(tpid);
3745 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL);
3746 if (ret != I40E_SUCCESS) {
3748 "Set switch config failed aq_err: %d",
3749 hw->aq.asq_last_status);
3753 /* If NVM API < 1.7, keep the register setting */
3754 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3761 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3763 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3764 struct i40e_vsi *vsi = pf->main_vsi;
3765 struct rte_eth_rxmode *rxmode;
3767 rxmode = &dev->data->dev_conf.rxmode;
3768 if (mask & ETH_VLAN_FILTER_MASK) {
3769 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3770 i40e_vsi_config_vlan_filter(vsi, TRUE);
3772 i40e_vsi_config_vlan_filter(vsi, FALSE);
3775 if (mask & ETH_VLAN_STRIP_MASK) {
3776 /* Enable or disable VLAN stripping */
3777 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3778 i40e_vsi_config_vlan_stripping(vsi, TRUE);
3780 i40e_vsi_config_vlan_stripping(vsi, FALSE);
3783 if (mask & ETH_VLAN_EXTEND_MASK) {
3784 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
3785 i40e_vsi_config_double_vlan(vsi, TRUE);
3786 /* Set global registers with default ethertype. */
3787 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3788 RTE_ETHER_TYPE_VLAN);
3789 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3790 RTE_ETHER_TYPE_VLAN);
3793 i40e_vsi_config_double_vlan(vsi, FALSE);
3800 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3801 __rte_unused uint16_t queue,
3802 __rte_unused int on)
3804 PMD_INIT_FUNC_TRACE();
3808 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3810 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3811 struct i40e_vsi *vsi = pf->main_vsi;
3812 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3813 struct i40e_vsi_vlan_pvid_info info;
3815 memset(&info, 0, sizeof(info));
3818 info.config.pvid = pvid;
3820 info.config.reject.tagged =
3821 data->dev_conf.txmode.hw_vlan_reject_tagged;
3822 info.config.reject.untagged =
3823 data->dev_conf.txmode.hw_vlan_reject_untagged;
3826 return i40e_vsi_vlan_pvid_set(vsi, &info);
3830 i40e_dev_led_on(struct rte_eth_dev *dev)
3832 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3833 uint32_t mode = i40e_led_get(hw);
3836 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3842 i40e_dev_led_off(struct rte_eth_dev *dev)
3844 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3845 uint32_t mode = i40e_led_get(hw);
3848 i40e_led_set(hw, 0, false);
3854 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3856 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3857 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3859 fc_conf->pause_time = pf->fc_conf.pause_time;
3861 /* read out from register, in case they are modified by other port */
3862 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3863 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3864 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3865 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3867 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3868 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3870 /* Return current mode according to actual setting*/
3871 switch (hw->fc.current_mode) {
3873 fc_conf->mode = RTE_FC_FULL;
3875 case I40E_FC_TX_PAUSE:
3876 fc_conf->mode = RTE_FC_TX_PAUSE;
3878 case I40E_FC_RX_PAUSE:
3879 fc_conf->mode = RTE_FC_RX_PAUSE;
3883 fc_conf->mode = RTE_FC_NONE;
3890 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3892 uint32_t mflcn_reg, fctrl_reg, reg;
3893 uint32_t max_high_water;
3894 uint8_t i, aq_failure;
3898 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3899 [RTE_FC_NONE] = I40E_FC_NONE,
3900 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3901 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3902 [RTE_FC_FULL] = I40E_FC_FULL
3905 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3907 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3908 if ((fc_conf->high_water > max_high_water) ||
3909 (fc_conf->high_water < fc_conf->low_water)) {
3911 "Invalid high/low water setup value in KB, High_water must be <= %d.",
3916 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3917 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3918 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3920 pf->fc_conf.pause_time = fc_conf->pause_time;
3921 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3922 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3924 PMD_INIT_FUNC_TRACE();
3926 /* All the link flow control related enable/disable register
3927 * configuration is handle by the F/W
3929 err = i40e_set_fc(hw, &aq_failure, true);
3933 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3934 /* Configure flow control refresh threshold,
3935 * the value for stat_tx_pause_refresh_timer[8]
3936 * is used for global pause operation.
3940 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3941 pf->fc_conf.pause_time);
3943 /* configure the timer value included in transmitted pause
3945 * the value for stat_tx_pause_quanta[8] is used for global
3948 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3949 pf->fc_conf.pause_time);
3951 fctrl_reg = I40E_READ_REG(hw,
3952 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3954 if (fc_conf->mac_ctrl_frame_fwd != 0)
3955 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3957 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3959 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3962 /* Configure pause time (2 TCs per register) */
3963 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3964 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3965 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3967 /* Configure flow control refresh threshold value */
3968 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3969 pf->fc_conf.pause_time / 2);
3971 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3973 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3974 *depending on configuration
3976 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3977 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3978 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3980 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3981 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3984 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3987 if (!pf->support_multi_driver) {
3988 /* config water marker both based on the packets and bytes */
3989 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
3990 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3991 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3992 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
3993 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3994 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3995 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
3996 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3998 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
3999 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4003 "Water marker configuration is not supported.");
4006 I40E_WRITE_FLUSH(hw);
4012 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
4013 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
4015 PMD_INIT_FUNC_TRACE();
4020 /* Add a MAC address, and update filters */
4022 i40e_macaddr_add(struct rte_eth_dev *dev,
4023 struct rte_ether_addr *mac_addr,
4024 __rte_unused uint32_t index,
4027 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4028 struct i40e_mac_filter_info mac_filter;
4029 struct i40e_vsi *vsi;
4030 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
4033 /* If VMDQ not enabled or configured, return */
4034 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
4035 !pf->nb_cfg_vmdq_vsi)) {
4036 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
4037 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
4042 if (pool > pf->nb_cfg_vmdq_vsi) {
4043 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
4044 pool, pf->nb_cfg_vmdq_vsi);
4048 rte_memcpy(&mac_filter.mac_addr, mac_addr, RTE_ETHER_ADDR_LEN);
4049 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4050 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4052 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
4057 vsi = pf->vmdq[pool - 1].vsi;
4059 ret = i40e_vsi_add_mac(vsi, &mac_filter);
4060 if (ret != I40E_SUCCESS) {
4061 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4067 /* Remove a MAC address, and update filters */
4069 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4071 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4072 struct i40e_vsi *vsi;
4073 struct rte_eth_dev_data *data = dev->data;
4074 struct rte_ether_addr *macaddr;
4079 macaddr = &(data->mac_addrs[index]);
4081 pool_sel = dev->data->mac_pool_sel[index];
4083 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4084 if (pool_sel & (1ULL << i)) {
4088 /* No VMDQ pool enabled or configured */
4089 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4090 (i > pf->nb_cfg_vmdq_vsi)) {
4092 "No VMDQ pool enabled/configured");
4095 vsi = pf->vmdq[i - 1].vsi;
4097 ret = i40e_vsi_delete_mac(vsi, macaddr);
4100 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4107 /* Set perfect match or hash match of MAC and VLAN for a VF */
4109 i40e_vf_mac_filter_set(struct i40e_pf *pf,
4110 struct rte_eth_mac_filter *filter,
4114 struct i40e_mac_filter_info mac_filter;
4115 struct rte_ether_addr old_mac;
4116 struct rte_ether_addr *new_mac;
4117 struct i40e_pf_vf *vf = NULL;
4122 PMD_DRV_LOG(ERR, "Invalid PF argument.");
4125 hw = I40E_PF_TO_HW(pf);
4127 if (filter == NULL) {
4128 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
4132 new_mac = &filter->mac_addr;
4134 if (rte_is_zero_ether_addr(new_mac)) {
4135 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
4139 vf_id = filter->dst_id;
4141 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
4142 PMD_DRV_LOG(ERR, "Invalid argument.");
4145 vf = &pf->vfs[vf_id];
4147 if (add && rte_is_same_ether_addr(new_mac, &pf->dev_addr)) {
4148 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
4153 rte_memcpy(&old_mac, hw->mac.addr, RTE_ETHER_ADDR_LEN);
4154 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
4155 RTE_ETHER_ADDR_LEN);
4156 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
4157 RTE_ETHER_ADDR_LEN);
4159 mac_filter.filter_type = filter->filter_type;
4160 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
4161 if (ret != I40E_SUCCESS) {
4162 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
4165 rte_ether_addr_copy(new_mac, &pf->dev_addr);
4167 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
4168 RTE_ETHER_ADDR_LEN);
4169 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
4170 if (ret != I40E_SUCCESS) {
4171 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
4175 /* Clear device address as it has been removed */
4176 if (rte_is_same_ether_addr(&pf->dev_addr, new_mac))
4177 memset(&pf->dev_addr, 0, sizeof(struct rte_ether_addr));
4183 /* MAC filter handle */
4185 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4188 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4189 struct rte_eth_mac_filter *filter;
4190 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4191 int ret = I40E_NOT_SUPPORTED;
4193 filter = (struct rte_eth_mac_filter *)(arg);
4195 switch (filter_op) {
4196 case RTE_ETH_FILTER_NOP:
4199 case RTE_ETH_FILTER_ADD:
4200 i40e_pf_disable_irq0(hw);
4202 ret = i40e_vf_mac_filter_set(pf, filter, 1);
4203 i40e_pf_enable_irq0(hw);
4205 case RTE_ETH_FILTER_DELETE:
4206 i40e_pf_disable_irq0(hw);
4208 ret = i40e_vf_mac_filter_set(pf, filter, 0);
4209 i40e_pf_enable_irq0(hw);
4212 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4213 ret = I40E_ERR_PARAM;
4221 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4223 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4224 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4231 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4232 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id,
4233 vsi->type != I40E_VSI_SRIOV,
4236 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4240 uint32_t *lut_dw = (uint32_t *)lut;
4241 uint16_t i, lut_size_dw = lut_size / 4;
4243 if (vsi->type == I40E_VSI_SRIOV) {
4244 for (i = 0; i <= lut_size_dw; i++) {
4245 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4246 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4249 for (i = 0; i < lut_size_dw; i++)
4250 lut_dw[i] = I40E_READ_REG(hw,
4259 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4268 pf = I40E_VSI_TO_PF(vsi);
4269 hw = I40E_VSI_TO_HW(vsi);
4271 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4272 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id,
4273 vsi->type != I40E_VSI_SRIOV,
4276 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4280 uint32_t *lut_dw = (uint32_t *)lut;
4281 uint16_t i, lut_size_dw = lut_size / 4;
4283 if (vsi->type == I40E_VSI_SRIOV) {
4284 for (i = 0; i < lut_size_dw; i++)
4287 I40E_VFQF_HLUT1(i, vsi->user_param),
4290 for (i = 0; i < lut_size_dw; i++)
4291 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4294 I40E_WRITE_FLUSH(hw);
4301 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4302 struct rte_eth_rss_reta_entry64 *reta_conf,
4305 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4306 uint16_t i, lut_size = pf->hash_lut_size;
4307 uint16_t idx, shift;
4311 if (reta_size != lut_size ||
4312 reta_size > ETH_RSS_RETA_SIZE_512) {
4314 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4315 reta_size, lut_size);
4319 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4321 PMD_DRV_LOG(ERR, "No memory can be allocated");
4324 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4327 for (i = 0; i < reta_size; i++) {
4328 idx = i / RTE_RETA_GROUP_SIZE;
4329 shift = i % RTE_RETA_GROUP_SIZE;
4330 if (reta_conf[idx].mask & (1ULL << shift))
4331 lut[i] = reta_conf[idx].reta[shift];
4333 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4335 pf->adapter->rss_reta_updated = 1;
4344 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4345 struct rte_eth_rss_reta_entry64 *reta_conf,
4348 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4349 uint16_t i, lut_size = pf->hash_lut_size;
4350 uint16_t idx, shift;
4354 if (reta_size != lut_size ||
4355 reta_size > ETH_RSS_RETA_SIZE_512) {
4357 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4358 reta_size, lut_size);
4362 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4364 PMD_DRV_LOG(ERR, "No memory can be allocated");
4368 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4371 for (i = 0; i < reta_size; i++) {
4372 idx = i / RTE_RETA_GROUP_SIZE;
4373 shift = i % RTE_RETA_GROUP_SIZE;
4374 if (reta_conf[idx].mask & (1ULL << shift))
4375 reta_conf[idx].reta[shift] = lut[i];
4385 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4386 * @hw: pointer to the HW structure
4387 * @mem: pointer to mem struct to fill out
4388 * @size: size of memory requested
4389 * @alignment: what to align the allocation to
4391 enum i40e_status_code
4392 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4393 struct i40e_dma_mem *mem,
4397 const struct rte_memzone *mz = NULL;
4398 char z_name[RTE_MEMZONE_NAMESIZE];
4401 return I40E_ERR_PARAM;
4403 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4404 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4405 RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4407 return I40E_ERR_NO_MEMORY;
4412 mem->zone = (const void *)mz;
4414 "memzone %s allocated with physical address: %"PRIu64,
4417 return I40E_SUCCESS;
4421 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4422 * @hw: pointer to the HW structure
4423 * @mem: ptr to mem struct to free
4425 enum i40e_status_code
4426 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4427 struct i40e_dma_mem *mem)
4430 return I40E_ERR_PARAM;
4433 "memzone %s to be freed with physical address: %"PRIu64,
4434 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4435 rte_memzone_free((const struct rte_memzone *)mem->zone);
4440 return I40E_SUCCESS;
4444 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4445 * @hw: pointer to the HW structure
4446 * @mem: pointer to mem struct to fill out
4447 * @size: size of memory requested
4449 enum i40e_status_code
4450 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4451 struct i40e_virt_mem *mem,
4455 return I40E_ERR_PARAM;
4458 mem->va = rte_zmalloc("i40e", size, 0);
4461 return I40E_SUCCESS;
4463 return I40E_ERR_NO_MEMORY;
4467 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4468 * @hw: pointer to the HW structure
4469 * @mem: pointer to mem struct to free
4471 enum i40e_status_code
4472 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4473 struct i40e_virt_mem *mem)
4476 return I40E_ERR_PARAM;
4481 return I40E_SUCCESS;
4485 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4487 rte_spinlock_init(&sp->spinlock);
4491 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4493 rte_spinlock_lock(&sp->spinlock);
4497 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4499 rte_spinlock_unlock(&sp->spinlock);
4503 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4509 * Get the hardware capabilities, which will be parsed
4510 * and saved into struct i40e_hw.
4513 i40e_get_cap(struct i40e_hw *hw)
4515 struct i40e_aqc_list_capabilities_element_resp *buf;
4516 uint16_t len, size = 0;
4519 /* Calculate a huge enough buff for saving response data temporarily */
4520 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4521 I40E_MAX_CAP_ELE_NUM;
4522 buf = rte_zmalloc("i40e", len, 0);
4524 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4525 return I40E_ERR_NO_MEMORY;
4528 /* Get, parse the capabilities and save it to hw */
4529 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4530 i40e_aqc_opc_list_func_capabilities, NULL);
4531 if (ret != I40E_SUCCESS)
4532 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4534 /* Free the temporary buffer after being used */
4540 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4
4542 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4550 pf = (struct i40e_pf *)opaque;
4554 num = strtoul(value, &end, 0);
4555 if (errno != 0 || end == value || *end != 0) {
4556 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4557 "kept the value = %hu", value, pf->vf_nb_qp_max);
4561 if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4562 pf->vf_nb_qp_max = (uint16_t)num;
4564 /* here return 0 to make next valid same argument work */
4565 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4566 "power of 2 and equal or less than 16 !, Now it is "
4567 "kept the value = %hu", num, pf->vf_nb_qp_max);
4572 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4574 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4575 struct rte_kvargs *kvlist;
4578 /* set default queue number per VF as 4 */
4579 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4581 if (dev->device->devargs == NULL)
4584 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4588 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4589 if (!kvargs_count) {
4590 rte_kvargs_free(kvlist);
4594 if (kvargs_count > 1)
4595 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4596 "the first invalid or last valid one is used !",
4597 ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4599 rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4600 i40e_pf_parse_vf_queue_number_handler, pf);
4602 rte_kvargs_free(kvlist);
4608 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4610 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4611 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4612 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4613 uint16_t qp_count = 0, vsi_count = 0;
4615 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4616 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4620 i40e_pf_config_vf_rxq_number(dev);
4622 /* Add the parameter init for LFC */
4623 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4624 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4625 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4627 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4628 pf->max_num_vsi = hw->func_caps.num_vsis;
4629 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4630 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4632 /* FDir queue/VSI allocation */
4633 pf->fdir_qp_offset = 0;
4634 if (hw->func_caps.fd) {
4635 pf->flags |= I40E_FLAG_FDIR;
4636 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4638 pf->fdir_nb_qps = 0;
4640 qp_count += pf->fdir_nb_qps;
4643 /* LAN queue/VSI allocation */
4644 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4645 if (!hw->func_caps.rss) {
4648 pf->flags |= I40E_FLAG_RSS;
4649 if (hw->mac.type == I40E_MAC_X722)
4650 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4651 pf->lan_nb_qps = pf->lan_nb_qp_max;
4653 qp_count += pf->lan_nb_qps;
4656 /* VF queue/VSI allocation */
4657 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4658 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4659 pf->flags |= I40E_FLAG_SRIOV;
4660 pf->vf_nb_qps = pf->vf_nb_qp_max;
4661 pf->vf_num = pci_dev->max_vfs;
4663 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4664 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4669 qp_count += pf->vf_nb_qps * pf->vf_num;
4670 vsi_count += pf->vf_num;
4672 /* VMDq queue/VSI allocation */
4673 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4674 pf->vmdq_nb_qps = 0;
4675 pf->max_nb_vmdq_vsi = 0;
4676 if (hw->func_caps.vmdq) {
4677 if (qp_count < hw->func_caps.num_tx_qp &&
4678 vsi_count < hw->func_caps.num_vsis) {
4679 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4680 qp_count) / pf->vmdq_nb_qp_max;
4682 /* Limit the maximum number of VMDq vsi to the maximum
4683 * ethdev can support
4685 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4686 hw->func_caps.num_vsis - vsi_count);
4687 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4689 if (pf->max_nb_vmdq_vsi) {
4690 pf->flags |= I40E_FLAG_VMDQ;
4691 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4693 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4694 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4695 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4698 "No enough queues left for VMDq");
4701 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4704 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4705 vsi_count += pf->max_nb_vmdq_vsi;
4707 if (hw->func_caps.dcb)
4708 pf->flags |= I40E_FLAG_DCB;
4710 if (qp_count > hw->func_caps.num_tx_qp) {
4712 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4713 qp_count, hw->func_caps.num_tx_qp);
4716 if (vsi_count > hw->func_caps.num_vsis) {
4718 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4719 vsi_count, hw->func_caps.num_vsis);
4727 i40e_pf_get_switch_config(struct i40e_pf *pf)
4729 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4730 struct i40e_aqc_get_switch_config_resp *switch_config;
4731 struct i40e_aqc_switch_config_element_resp *element;
4732 uint16_t start_seid = 0, num_reported;
4735 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4736 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4737 if (!switch_config) {
4738 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4742 /* Get the switch configurations */
4743 ret = i40e_aq_get_switch_config(hw, switch_config,
4744 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4745 if (ret != I40E_SUCCESS) {
4746 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4749 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4750 if (num_reported != 1) { /* The number should be 1 */
4751 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4755 /* Parse the switch configuration elements */
4756 element = &(switch_config->element[0]);
4757 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4758 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4759 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4761 PMD_DRV_LOG(INFO, "Unknown element type");
4764 rte_free(switch_config);
4770 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4773 struct pool_entry *entry;
4775 if (pool == NULL || num == 0)
4778 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4779 if (entry == NULL) {
4780 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4784 /* queue heap initialize */
4785 pool->num_free = num;
4786 pool->num_alloc = 0;
4788 LIST_INIT(&pool->alloc_list);
4789 LIST_INIT(&pool->free_list);
4791 /* Initialize element */
4795 LIST_INSERT_HEAD(&pool->free_list, entry, next);
4800 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4802 struct pool_entry *entry, *next_entry;
4807 for (entry = LIST_FIRST(&pool->alloc_list);
4808 entry && (next_entry = LIST_NEXT(entry, next), 1);
4809 entry = next_entry) {
4810 LIST_REMOVE(entry, next);
4814 for (entry = LIST_FIRST(&pool->free_list);
4815 entry && (next_entry = LIST_NEXT(entry, next), 1);
4816 entry = next_entry) {
4817 LIST_REMOVE(entry, next);
4822 pool->num_alloc = 0;
4824 LIST_INIT(&pool->alloc_list);
4825 LIST_INIT(&pool->free_list);
4829 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4832 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4833 uint32_t pool_offset;
4837 PMD_DRV_LOG(ERR, "Invalid parameter");
4841 pool_offset = base - pool->base;
4842 /* Lookup in alloc list */
4843 LIST_FOREACH(entry, &pool->alloc_list, next) {
4844 if (entry->base == pool_offset) {
4845 valid_entry = entry;
4846 LIST_REMOVE(entry, next);
4851 /* Not find, return */
4852 if (valid_entry == NULL) {
4853 PMD_DRV_LOG(ERR, "Failed to find entry");
4858 * Found it, move it to free list and try to merge.
4859 * In order to make merge easier, always sort it by qbase.
4860 * Find adjacent prev and last entries.
4863 LIST_FOREACH(entry, &pool->free_list, next) {
4864 if (entry->base > valid_entry->base) {
4872 /* Try to merge with next one*/
4874 /* Merge with next one */
4875 if (valid_entry->base + valid_entry->len == next->base) {
4876 next->base = valid_entry->base;
4877 next->len += valid_entry->len;
4878 rte_free(valid_entry);
4885 /* Merge with previous one */
4886 if (prev->base + prev->len == valid_entry->base) {
4887 prev->len += valid_entry->len;
4888 /* If it merge with next one, remove next node */
4890 LIST_REMOVE(valid_entry, next);
4891 rte_free(valid_entry);
4893 rte_free(valid_entry);
4899 /* Not find any entry to merge, insert */
4902 LIST_INSERT_AFTER(prev, valid_entry, next);
4903 else if (next != NULL)
4904 LIST_INSERT_BEFORE(next, valid_entry, next);
4905 else /* It's empty list, insert to head */
4906 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4909 pool->num_free += valid_entry->len;
4910 pool->num_alloc -= valid_entry->len;
4916 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4919 struct pool_entry *entry, *valid_entry;
4921 if (pool == NULL || num == 0) {
4922 PMD_DRV_LOG(ERR, "Invalid parameter");
4926 if (pool->num_free < num) {
4927 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4928 num, pool->num_free);
4933 /* Lookup in free list and find most fit one */
4934 LIST_FOREACH(entry, &pool->free_list, next) {
4935 if (entry->len >= num) {
4937 if (entry->len == num) {
4938 valid_entry = entry;
4941 if (valid_entry == NULL || valid_entry->len > entry->len)
4942 valid_entry = entry;
4946 /* Not find one to satisfy the request, return */
4947 if (valid_entry == NULL) {
4948 PMD_DRV_LOG(ERR, "No valid entry found");
4952 * The entry have equal queue number as requested,
4953 * remove it from alloc_list.
4955 if (valid_entry->len == num) {
4956 LIST_REMOVE(valid_entry, next);
4959 * The entry have more numbers than requested,
4960 * create a new entry for alloc_list and minus its
4961 * queue base and number in free_list.
4963 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4964 if (entry == NULL) {
4966 "Failed to allocate memory for resource pool");
4969 entry->base = valid_entry->base;
4971 valid_entry->base += num;
4972 valid_entry->len -= num;
4973 valid_entry = entry;
4976 /* Insert it into alloc list, not sorted */
4977 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4979 pool->num_free -= valid_entry->len;
4980 pool->num_alloc += valid_entry->len;
4982 return valid_entry->base + pool->base;
4986 * bitmap_is_subset - Check whether src2 is subset of src1
4989 bitmap_is_subset(uint8_t src1, uint8_t src2)
4991 return !((src1 ^ src2) & src2);
4994 static enum i40e_status_code
4995 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4997 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4999 /* If DCB is not supported, only default TC is supported */
5000 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
5001 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
5002 return I40E_NOT_SUPPORTED;
5005 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
5007 "Enabled TC map 0x%x not applicable to HW support 0x%x",
5008 hw->func_caps.enabled_tcmap, enabled_tcmap);
5009 return I40E_NOT_SUPPORTED;
5011 return I40E_SUCCESS;
5015 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
5016 struct i40e_vsi_vlan_pvid_info *info)
5019 struct i40e_vsi_context ctxt;
5020 uint8_t vlan_flags = 0;
5023 if (vsi == NULL || info == NULL) {
5024 PMD_DRV_LOG(ERR, "invalid parameters");
5025 return I40E_ERR_PARAM;
5029 vsi->info.pvid = info->config.pvid;
5031 * If insert pvid is enabled, only tagged pkts are
5032 * allowed to be sent out.
5034 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
5035 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5038 if (info->config.reject.tagged == 0)
5039 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5041 if (info->config.reject.untagged == 0)
5042 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
5044 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
5045 I40E_AQ_VSI_PVLAN_MODE_MASK);
5046 vsi->info.port_vlan_flags |= vlan_flags;
5047 vsi->info.valid_sections =
5048 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5049 memset(&ctxt, 0, sizeof(ctxt));
5050 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5051 ctxt.seid = vsi->seid;
5053 hw = I40E_VSI_TO_HW(vsi);
5054 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5055 if (ret != I40E_SUCCESS)
5056 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5062 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5064 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5066 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
5068 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5069 if (ret != I40E_SUCCESS)
5073 PMD_DRV_LOG(ERR, "seid not valid");
5077 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
5078 tc_bw_data.tc_valid_bits = enabled_tcmap;
5079 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5080 tc_bw_data.tc_bw_credits[i] =
5081 (enabled_tcmap & (1 << i)) ? 1 : 0;
5083 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5084 if (ret != I40E_SUCCESS) {
5085 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5089 rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5090 sizeof(vsi->info.qs_handle));
5091 return I40E_SUCCESS;
5094 static enum i40e_status_code
5095 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5096 struct i40e_aqc_vsi_properties_data *info,
5097 uint8_t enabled_tcmap)
5099 enum i40e_status_code ret;
5100 int i, total_tc = 0;
5101 uint16_t qpnum_per_tc, bsf, qp_idx;
5103 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5104 if (ret != I40E_SUCCESS)
5107 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5108 if (enabled_tcmap & (1 << i))
5112 vsi->enabled_tc = enabled_tcmap;
5114 /* Number of queues per enabled TC */
5115 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5116 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5117 bsf = rte_bsf32(qpnum_per_tc);
5119 /* Adjust the queue number to actual queues that can be applied */
5120 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5121 vsi->nb_qps = qpnum_per_tc * total_tc;
5124 * Configure TC and queue mapping parameters, for enabled TC,
5125 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5126 * default queue will serve it.
5129 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5130 if (vsi->enabled_tc & (1 << i)) {
5131 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5132 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5133 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5134 qp_idx += qpnum_per_tc;
5136 info->tc_mapping[i] = 0;
5139 /* Associate queue number with VSI */
5140 if (vsi->type == I40E_VSI_SRIOV) {
5141 info->mapping_flags |=
5142 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5143 for (i = 0; i < vsi->nb_qps; i++)
5144 info->queue_mapping[i] =
5145 rte_cpu_to_le_16(vsi->base_queue + i);
5147 info->mapping_flags |=
5148 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5149 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5151 info->valid_sections |=
5152 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5154 return I40E_SUCCESS;
5158 i40e_veb_release(struct i40e_veb *veb)
5160 struct i40e_vsi *vsi;
5166 if (!TAILQ_EMPTY(&veb->head)) {
5167 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5170 /* associate_vsi field is NULL for floating VEB */
5171 if (veb->associate_vsi != NULL) {
5172 vsi = veb->associate_vsi;
5173 hw = I40E_VSI_TO_HW(vsi);
5175 vsi->uplink_seid = veb->uplink_seid;
5178 veb->associate_pf->main_vsi->floating_veb = NULL;
5179 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5182 i40e_aq_delete_element(hw, veb->seid, NULL);
5184 return I40E_SUCCESS;
5188 static struct i40e_veb *
5189 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5191 struct i40e_veb *veb;
5197 "veb setup failed, associated PF shouldn't null");
5200 hw = I40E_PF_TO_HW(pf);
5202 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5204 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5208 veb->associate_vsi = vsi;
5209 veb->associate_pf = pf;
5210 TAILQ_INIT(&veb->head);
5211 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5213 /* create floating veb if vsi is NULL */
5215 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5216 I40E_DEFAULT_TCMAP, false,
5217 &veb->seid, false, NULL);
5219 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5220 true, &veb->seid, false, NULL);
5223 if (ret != I40E_SUCCESS) {
5224 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5225 hw->aq.asq_last_status);
5228 veb->enabled_tc = I40E_DEFAULT_TCMAP;
5230 /* get statistics index */
5231 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5232 &veb->stats_idx, NULL, NULL, NULL);
5233 if (ret != I40E_SUCCESS) {
5234 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5235 hw->aq.asq_last_status);
5238 /* Get VEB bandwidth, to be implemented */
5239 /* Now associated vsi binding to the VEB, set uplink to this VEB */
5241 vsi->uplink_seid = veb->seid;
5250 i40e_vsi_release(struct i40e_vsi *vsi)
5254 struct i40e_vsi_list *vsi_list;
5257 struct i40e_mac_filter *f;
5258 uint16_t user_param;
5261 return I40E_SUCCESS;
5266 user_param = vsi->user_param;
5268 pf = I40E_VSI_TO_PF(vsi);
5269 hw = I40E_VSI_TO_HW(vsi);
5271 /* VSI has child to attach, release child first */
5273 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5274 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5277 i40e_veb_release(vsi->veb);
5280 if (vsi->floating_veb) {
5281 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5282 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5287 /* Remove all macvlan filters of the VSI */
5288 i40e_vsi_remove_all_macvlan_filter(vsi);
5289 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5292 if (vsi->type != I40E_VSI_MAIN &&
5293 ((vsi->type != I40E_VSI_SRIOV) ||
5294 !pf->floating_veb_list[user_param])) {
5295 /* Remove vsi from parent's sibling list */
5296 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5297 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5298 return I40E_ERR_PARAM;
5300 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5301 &vsi->sib_vsi_list, list);
5303 /* Remove all switch element of the VSI */
5304 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5305 if (ret != I40E_SUCCESS)
5306 PMD_DRV_LOG(ERR, "Failed to delete element");
5309 if ((vsi->type == I40E_VSI_SRIOV) &&
5310 pf->floating_veb_list[user_param]) {
5311 /* Remove vsi from parent's sibling list */
5312 if (vsi->parent_vsi == NULL ||
5313 vsi->parent_vsi->floating_veb == NULL) {
5314 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5315 return I40E_ERR_PARAM;
5317 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5318 &vsi->sib_vsi_list, list);
5320 /* Remove all switch element of the VSI */
5321 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5322 if (ret != I40E_SUCCESS)
5323 PMD_DRV_LOG(ERR, "Failed to delete element");
5326 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5328 if (vsi->type != I40E_VSI_SRIOV)
5329 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5332 return I40E_SUCCESS;
5336 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5338 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5339 struct i40e_aqc_remove_macvlan_element_data def_filter;
5340 struct i40e_mac_filter_info filter;
5343 if (vsi->type != I40E_VSI_MAIN)
5344 return I40E_ERR_CONFIG;
5345 memset(&def_filter, 0, sizeof(def_filter));
5346 rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5348 def_filter.vlan_tag = 0;
5349 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5350 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5351 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5352 if (ret != I40E_SUCCESS) {
5353 struct i40e_mac_filter *f;
5354 struct rte_ether_addr *mac;
5357 "Cannot remove the default macvlan filter");
5358 /* It needs to add the permanent mac into mac list */
5359 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5361 PMD_DRV_LOG(ERR, "failed to allocate memory");
5362 return I40E_ERR_NO_MEMORY;
5364 mac = &f->mac_info.mac_addr;
5365 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5367 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5368 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5373 rte_memcpy(&filter.mac_addr,
5374 (struct rte_ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5375 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5376 return i40e_vsi_add_mac(vsi, &filter);
5380 * i40e_vsi_get_bw_config - Query VSI BW Information
5381 * @vsi: the VSI to be queried
5383 * Returns 0 on success, negative value on failure
5385 static enum i40e_status_code
5386 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5388 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5389 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5390 struct i40e_hw *hw = &vsi->adapter->hw;
5395 memset(&bw_config, 0, sizeof(bw_config));
5396 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5397 if (ret != I40E_SUCCESS) {
5398 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5399 hw->aq.asq_last_status);
5403 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5404 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5405 &ets_sla_config, NULL);
5406 if (ret != I40E_SUCCESS) {
5408 "VSI failed to get TC bandwdith configuration %u",
5409 hw->aq.asq_last_status);
5413 /* store and print out BW info */
5414 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5415 vsi->bw_info.bw_max = bw_config.max_bw;
5416 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5417 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5418 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5419 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5421 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5422 vsi->bw_info.bw_ets_share_credits[i] =
5423 ets_sla_config.share_credits[i];
5424 vsi->bw_info.bw_ets_credits[i] =
5425 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5426 /* 4 bits per TC, 4th bit is reserved */
5427 vsi->bw_info.bw_ets_max[i] =
5428 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5429 RTE_LEN2MASK(3, uint8_t));
5430 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5431 vsi->bw_info.bw_ets_share_credits[i]);
5432 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5433 vsi->bw_info.bw_ets_credits[i]);
5434 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5435 vsi->bw_info.bw_ets_max[i]);
5438 return I40E_SUCCESS;
5441 /* i40e_enable_pf_lb
5442 * @pf: pointer to the pf structure
5444 * allow loopback on pf
5447 i40e_enable_pf_lb(struct i40e_pf *pf)
5449 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5450 struct i40e_vsi_context ctxt;
5453 /* Use the FW API if FW >= v5.0 */
5454 if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
5455 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5459 memset(&ctxt, 0, sizeof(ctxt));
5460 ctxt.seid = pf->main_vsi_seid;
5461 ctxt.pf_num = hw->pf_id;
5462 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5464 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5465 ret, hw->aq.asq_last_status);
5468 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5469 ctxt.info.valid_sections =
5470 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5471 ctxt.info.switch_id |=
5472 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5474 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5476 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5477 hw->aq.asq_last_status);
5482 i40e_vsi_setup(struct i40e_pf *pf,
5483 enum i40e_vsi_type type,
5484 struct i40e_vsi *uplink_vsi,
5485 uint16_t user_param)
5487 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5488 struct i40e_vsi *vsi;
5489 struct i40e_mac_filter_info filter;
5491 struct i40e_vsi_context ctxt;
5492 struct rte_ether_addr broadcast =
5493 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5495 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5496 uplink_vsi == NULL) {
5498 "VSI setup failed, VSI link shouldn't be NULL");
5502 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5504 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5509 * 1.type is not MAIN and uplink vsi is not NULL
5510 * If uplink vsi didn't setup VEB, create one first under veb field
5511 * 2.type is SRIOV and the uplink is NULL
5512 * If floating VEB is NULL, create one veb under floating veb field
5515 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5516 uplink_vsi->veb == NULL) {
5517 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5519 if (uplink_vsi->veb == NULL) {
5520 PMD_DRV_LOG(ERR, "VEB setup failed");
5523 /* set ALLOWLOOPBACk on pf, when veb is created */
5524 i40e_enable_pf_lb(pf);
5527 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5528 pf->main_vsi->floating_veb == NULL) {
5529 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5531 if (pf->main_vsi->floating_veb == NULL) {
5532 PMD_DRV_LOG(ERR, "VEB setup failed");
5537 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5539 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5542 TAILQ_INIT(&vsi->mac_list);
5544 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5545 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5546 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5547 vsi->user_param = user_param;
5548 vsi->vlan_anti_spoof_on = 0;
5549 vsi->vlan_filter_on = 0;
5550 /* Allocate queues */
5551 switch (vsi->type) {
5552 case I40E_VSI_MAIN :
5553 vsi->nb_qps = pf->lan_nb_qps;
5555 case I40E_VSI_SRIOV :
5556 vsi->nb_qps = pf->vf_nb_qps;
5558 case I40E_VSI_VMDQ2:
5559 vsi->nb_qps = pf->vmdq_nb_qps;
5562 vsi->nb_qps = pf->fdir_nb_qps;
5568 * The filter status descriptor is reported in rx queue 0,
5569 * while the tx queue for fdir filter programming has no
5570 * such constraints, can be non-zero queues.
5571 * To simplify it, choose FDIR vsi use queue 0 pair.
5572 * To make sure it will use queue 0 pair, queue allocation
5573 * need be done before this function is called
5575 if (type != I40E_VSI_FDIR) {
5576 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5578 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5582 vsi->base_queue = ret;
5584 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5586 /* VF has MSIX interrupt in VF range, don't allocate here */
5587 if (type == I40E_VSI_MAIN) {
5588 if (pf->support_multi_driver) {
5589 /* If support multi-driver, need to use INT0 instead of
5590 * allocating from msix pool. The Msix pool is init from
5591 * INT1, so it's OK just set msix_intr to 0 and nb_msix
5592 * to 1 without calling i40e_res_pool_alloc.
5597 ret = i40e_res_pool_alloc(&pf->msix_pool,
5598 RTE_MIN(vsi->nb_qps,
5599 RTE_MAX_RXTX_INTR_VEC_ID));
5602 "VSI MAIN %d get heap failed %d",
5604 goto fail_queue_alloc;
5606 vsi->msix_intr = ret;
5607 vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5608 RTE_MAX_RXTX_INTR_VEC_ID);
5610 } else if (type != I40E_VSI_SRIOV) {
5611 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5613 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5614 goto fail_queue_alloc;
5616 vsi->msix_intr = ret;
5624 if (type == I40E_VSI_MAIN) {
5625 /* For main VSI, no need to add since it's default one */
5626 vsi->uplink_seid = pf->mac_seid;
5627 vsi->seid = pf->main_vsi_seid;
5628 /* Bind queues with specific MSIX interrupt */
5630 * Needs 2 interrupt at least, one for misc cause which will
5631 * enabled from OS side, Another for queues binding the
5632 * interrupt from device side only.
5635 /* Get default VSI parameters from hardware */
5636 memset(&ctxt, 0, sizeof(ctxt));
5637 ctxt.seid = vsi->seid;
5638 ctxt.pf_num = hw->pf_id;
5639 ctxt.uplink_seid = vsi->uplink_seid;
5641 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5642 if (ret != I40E_SUCCESS) {
5643 PMD_DRV_LOG(ERR, "Failed to get VSI params");
5644 goto fail_msix_alloc;
5646 rte_memcpy(&vsi->info, &ctxt.info,
5647 sizeof(struct i40e_aqc_vsi_properties_data));
5648 vsi->vsi_id = ctxt.vsi_number;
5649 vsi->info.valid_sections = 0;
5651 /* Configure tc, enabled TC0 only */
5652 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5654 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5655 goto fail_msix_alloc;
5658 /* TC, queue mapping */
5659 memset(&ctxt, 0, sizeof(ctxt));
5660 vsi->info.valid_sections |=
5661 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5662 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5663 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5664 rte_memcpy(&ctxt.info, &vsi->info,
5665 sizeof(struct i40e_aqc_vsi_properties_data));
5666 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5667 I40E_DEFAULT_TCMAP);
5668 if (ret != I40E_SUCCESS) {
5670 "Failed to configure TC queue mapping");
5671 goto fail_msix_alloc;
5673 ctxt.seid = vsi->seid;
5674 ctxt.pf_num = hw->pf_id;
5675 ctxt.uplink_seid = vsi->uplink_seid;
5678 /* Update VSI parameters */
5679 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5680 if (ret != I40E_SUCCESS) {
5681 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5682 goto fail_msix_alloc;
5685 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5686 sizeof(vsi->info.tc_mapping));
5687 rte_memcpy(&vsi->info.queue_mapping,
5688 &ctxt.info.queue_mapping,
5689 sizeof(vsi->info.queue_mapping));
5690 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5691 vsi->info.valid_sections = 0;
5693 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5697 * Updating default filter settings are necessary to prevent
5698 * reception of tagged packets.
5699 * Some old firmware configurations load a default macvlan
5700 * filter which accepts both tagged and untagged packets.
5701 * The updating is to use a normal filter instead if needed.
5702 * For NVM 4.2.2 or after, the updating is not needed anymore.
5703 * The firmware with correct configurations load the default
5704 * macvlan filter which is expected and cannot be removed.
5706 i40e_update_default_filter_setting(vsi);
5707 i40e_config_qinq(hw, vsi);
5708 } else if (type == I40E_VSI_SRIOV) {
5709 memset(&ctxt, 0, sizeof(ctxt));
5711 * For other VSI, the uplink_seid equals to uplink VSI's
5712 * uplink_seid since they share same VEB
5714 if (uplink_vsi == NULL)
5715 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5717 vsi->uplink_seid = uplink_vsi->uplink_seid;
5718 ctxt.pf_num = hw->pf_id;
5719 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5720 ctxt.uplink_seid = vsi->uplink_seid;
5721 ctxt.connection_type = 0x1;
5722 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5724 /* Use the VEB configuration if FW >= v5.0 */
5725 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
5726 /* Configure switch ID */
5727 ctxt.info.valid_sections |=
5728 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5729 ctxt.info.switch_id =
5730 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5733 /* Configure port/vlan */
5734 ctxt.info.valid_sections |=
5735 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5736 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5737 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5738 hw->func_caps.enabled_tcmap);
5739 if (ret != I40E_SUCCESS) {
5741 "Failed to configure TC queue mapping");
5742 goto fail_msix_alloc;
5745 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5746 ctxt.info.valid_sections |=
5747 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5749 * Since VSI is not created yet, only configure parameter,
5750 * will add vsi below.
5753 i40e_config_qinq(hw, vsi);
5754 } else if (type == I40E_VSI_VMDQ2) {
5755 memset(&ctxt, 0, sizeof(ctxt));
5757 * For other VSI, the uplink_seid equals to uplink VSI's
5758 * uplink_seid since they share same VEB
5760 vsi->uplink_seid = uplink_vsi->uplink_seid;
5761 ctxt.pf_num = hw->pf_id;
5763 ctxt.uplink_seid = vsi->uplink_seid;
5764 ctxt.connection_type = 0x1;
5765 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5767 ctxt.info.valid_sections |=
5768 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5769 /* user_param carries flag to enable loop back */
5771 ctxt.info.switch_id =
5772 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5773 ctxt.info.switch_id |=
5774 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5777 /* Configure port/vlan */
5778 ctxt.info.valid_sections |=
5779 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5780 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5781 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5782 I40E_DEFAULT_TCMAP);
5783 if (ret != I40E_SUCCESS) {
5785 "Failed to configure TC queue mapping");
5786 goto fail_msix_alloc;
5788 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5789 ctxt.info.valid_sections |=
5790 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5791 } else if (type == I40E_VSI_FDIR) {
5792 memset(&ctxt, 0, sizeof(ctxt));
5793 vsi->uplink_seid = uplink_vsi->uplink_seid;
5794 ctxt.pf_num = hw->pf_id;
5796 ctxt.uplink_seid = vsi->uplink_seid;
5797 ctxt.connection_type = 0x1; /* regular data port */
5798 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5799 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5800 I40E_DEFAULT_TCMAP);
5801 if (ret != I40E_SUCCESS) {
5803 "Failed to configure TC queue mapping.");
5804 goto fail_msix_alloc;
5806 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5807 ctxt.info.valid_sections |=
5808 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5810 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5811 goto fail_msix_alloc;
5814 if (vsi->type != I40E_VSI_MAIN) {
5815 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5816 if (ret != I40E_SUCCESS) {
5817 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5818 hw->aq.asq_last_status);
5819 goto fail_msix_alloc;
5821 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5822 vsi->info.valid_sections = 0;
5823 vsi->seid = ctxt.seid;
5824 vsi->vsi_id = ctxt.vsi_number;
5825 vsi->sib_vsi_list.vsi = vsi;
5826 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5827 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5828 &vsi->sib_vsi_list, list);
5830 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5831 &vsi->sib_vsi_list, list);
5835 /* MAC/VLAN configuration */
5836 rte_memcpy(&filter.mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
5837 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5839 ret = i40e_vsi_add_mac(vsi, &filter);
5840 if (ret != I40E_SUCCESS) {
5841 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5842 goto fail_msix_alloc;
5845 /* Get VSI BW information */
5846 i40e_vsi_get_bw_config(vsi);
5849 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5851 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5857 /* Configure vlan filter on or off */
5859 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5862 struct i40e_mac_filter *f;
5864 struct i40e_mac_filter_info *mac_filter;
5865 enum rte_mac_filter_type desired_filter;
5866 int ret = I40E_SUCCESS;
5869 /* Filter to match MAC and VLAN */
5870 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5872 /* Filter to match only MAC */
5873 desired_filter = RTE_MAC_PERFECT_MATCH;
5878 mac_filter = rte_zmalloc("mac_filter_info_data",
5879 num * sizeof(*mac_filter), 0);
5880 if (mac_filter == NULL) {
5881 PMD_DRV_LOG(ERR, "failed to allocate memory");
5882 return I40E_ERR_NO_MEMORY;
5887 /* Remove all existing mac */
5888 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5889 mac_filter[i] = f->mac_info;
5890 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5892 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5893 on ? "enable" : "disable");
5899 /* Override with new filter */
5900 for (i = 0; i < num; i++) {
5901 mac_filter[i].filter_type = desired_filter;
5902 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5904 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5905 on ? "enable" : "disable");
5911 rte_free(mac_filter);
5915 /* Configure vlan stripping on or off */
5917 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5919 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5920 struct i40e_vsi_context ctxt;
5922 int ret = I40E_SUCCESS;
5924 /* Check if it has been already on or off */
5925 if (vsi->info.valid_sections &
5926 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5928 if ((vsi->info.port_vlan_flags &
5929 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5930 return 0; /* already on */
5932 if ((vsi->info.port_vlan_flags &
5933 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5934 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5935 return 0; /* already off */
5940 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5942 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5943 vsi->info.valid_sections =
5944 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5945 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5946 vsi->info.port_vlan_flags |= vlan_flags;
5947 ctxt.seid = vsi->seid;
5948 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5949 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5951 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5952 on ? "enable" : "disable");
5958 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5960 struct rte_eth_dev_data *data = dev->data;
5964 /* Apply vlan offload setting */
5965 mask = ETH_VLAN_STRIP_MASK |
5966 ETH_VLAN_FILTER_MASK |
5967 ETH_VLAN_EXTEND_MASK;
5968 ret = i40e_vlan_offload_set(dev, mask);
5970 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5974 /* Apply pvid setting */
5975 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5976 data->dev_conf.txmode.hw_vlan_insert_pvid);
5978 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5984 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5986 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5988 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5992 i40e_update_flow_control(struct i40e_hw *hw)
5994 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5995 struct i40e_link_status link_status;
5996 uint32_t rxfc = 0, txfc = 0, reg;
6000 memset(&link_status, 0, sizeof(link_status));
6001 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
6002 if (ret != I40E_SUCCESS) {
6003 PMD_DRV_LOG(ERR, "Failed to get link status information");
6004 goto write_reg; /* Disable flow control */
6007 an_info = hw->phy.link_info.an_info;
6008 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
6009 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
6010 ret = I40E_ERR_NOT_READY;
6011 goto write_reg; /* Disable flow control */
6014 * If link auto negotiation is enabled, flow control needs to
6015 * be configured according to it
6017 switch (an_info & I40E_LINK_PAUSE_RXTX) {
6018 case I40E_LINK_PAUSE_RXTX:
6021 hw->fc.current_mode = I40E_FC_FULL;
6023 case I40E_AQ_LINK_PAUSE_RX:
6025 hw->fc.current_mode = I40E_FC_RX_PAUSE;
6027 case I40E_AQ_LINK_PAUSE_TX:
6029 hw->fc.current_mode = I40E_FC_TX_PAUSE;
6032 hw->fc.current_mode = I40E_FC_NONE;
6037 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
6038 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
6039 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
6040 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
6041 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
6042 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
6049 i40e_pf_setup(struct i40e_pf *pf)
6051 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6052 struct i40e_filter_control_settings settings;
6053 struct i40e_vsi *vsi;
6056 /* Clear all stats counters */
6057 pf->offset_loaded = FALSE;
6058 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
6059 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
6060 memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
6061 memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
6063 ret = i40e_pf_get_switch_config(pf);
6064 if (ret != I40E_SUCCESS) {
6065 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
6069 ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
6071 PMD_INIT_LOG(WARNING,
6072 "failed to allocate switch domain for device %d", ret);
6074 if (pf->flags & I40E_FLAG_FDIR) {
6075 /* make queue allocated first, let FDIR use queue pair 0*/
6076 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
6077 if (ret != I40E_FDIR_QUEUE_ID) {
6079 "queue allocation fails for FDIR: ret =%d",
6081 pf->flags &= ~I40E_FLAG_FDIR;
6084 /* main VSI setup */
6085 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6087 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6088 return I40E_ERR_NOT_READY;
6092 /* Configure filter control */
6093 memset(&settings, 0, sizeof(settings));
6094 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
6095 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6096 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
6097 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6099 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6100 hw->func_caps.rss_table_size);
6101 return I40E_ERR_PARAM;
6103 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6104 hw->func_caps.rss_table_size);
6105 pf->hash_lut_size = hw->func_caps.rss_table_size;
6107 /* Enable ethtype and macvlan filters */
6108 settings.enable_ethtype = TRUE;
6109 settings.enable_macvlan = TRUE;
6110 ret = i40e_set_filter_control(hw, &settings);
6112 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6115 /* Update flow control according to the auto negotiation */
6116 i40e_update_flow_control(hw);
6118 return I40E_SUCCESS;
6122 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6128 * Set or clear TX Queue Disable flags,
6129 * which is required by hardware.
6131 i40e_pre_tx_queue_cfg(hw, q_idx, on);
6132 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6134 /* Wait until the request is finished */
6135 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6136 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6137 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6138 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6139 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6145 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6146 return I40E_SUCCESS; /* already on, skip next steps */
6148 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6149 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6151 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6152 return I40E_SUCCESS; /* already off, skip next steps */
6153 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6155 /* Write the register */
6156 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6157 /* Check the result */
6158 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6159 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6160 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6162 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6163 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6166 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6167 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6171 /* Check if it is timeout */
6172 if (j >= I40E_CHK_Q_ENA_COUNT) {
6173 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6174 (on ? "enable" : "disable"), q_idx);
6175 return I40E_ERR_TIMEOUT;
6178 return I40E_SUCCESS;
6181 /* Swith on or off the tx queues */
6183 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
6185 struct rte_eth_dev_data *dev_data = pf->dev_data;
6186 struct i40e_tx_queue *txq;
6187 struct rte_eth_dev *dev = pf->adapter->eth_dev;
6191 for (i = 0; i < dev_data->nb_tx_queues; i++) {
6192 txq = dev_data->tx_queues[i];
6193 /* Don't operate the queue if not configured or
6194 * if starting only per queue */
6195 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
6198 ret = i40e_dev_tx_queue_start(dev, i);
6200 ret = i40e_dev_tx_queue_stop(dev, i);
6201 if ( ret != I40E_SUCCESS)
6205 return I40E_SUCCESS;
6209 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6214 /* Wait until the request is finished */
6215 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6216 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6217 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6218 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6219 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6224 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6225 return I40E_SUCCESS; /* Already on, skip next steps */
6226 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6228 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6229 return I40E_SUCCESS; /* Already off, skip next steps */
6230 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6233 /* Write the register */
6234 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6235 /* Check the result */
6236 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6237 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6238 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6240 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6241 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6244 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6245 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6250 /* Check if it is timeout */
6251 if (j >= I40E_CHK_Q_ENA_COUNT) {
6252 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6253 (on ? "enable" : "disable"), q_idx);
6254 return I40E_ERR_TIMEOUT;
6257 return I40E_SUCCESS;
6259 /* Switch on or off the rx queues */
6261 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
6263 struct rte_eth_dev_data *dev_data = pf->dev_data;
6264 struct i40e_rx_queue *rxq;
6265 struct rte_eth_dev *dev = pf->adapter->eth_dev;
6269 for (i = 0; i < dev_data->nb_rx_queues; i++) {
6270 rxq = dev_data->rx_queues[i];
6271 /* Don't operate the queue if not configured or
6272 * if starting only per queue */
6273 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
6276 ret = i40e_dev_rx_queue_start(dev, i);
6278 ret = i40e_dev_rx_queue_stop(dev, i);
6279 if (ret != I40E_SUCCESS)
6283 return I40E_SUCCESS;
6286 /* Switch on or off all the rx/tx queues */
6288 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
6293 /* enable rx queues before enabling tx queues */
6294 ret = i40e_dev_switch_rx_queues(pf, on);
6296 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
6299 ret = i40e_dev_switch_tx_queues(pf, on);
6301 /* Stop tx queues before stopping rx queues */
6302 ret = i40e_dev_switch_tx_queues(pf, on);
6304 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
6307 ret = i40e_dev_switch_rx_queues(pf, on);
6313 /* Initialize VSI for TX */
6315 i40e_dev_tx_init(struct i40e_pf *pf)
6317 struct rte_eth_dev_data *data = pf->dev_data;
6319 uint32_t ret = I40E_SUCCESS;
6320 struct i40e_tx_queue *txq;
6322 for (i = 0; i < data->nb_tx_queues; i++) {
6323 txq = data->tx_queues[i];
6324 if (!txq || !txq->q_set)
6326 ret = i40e_tx_queue_init(txq);
6327 if (ret != I40E_SUCCESS)
6330 if (ret == I40E_SUCCESS)
6331 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6337 /* Initialize VSI for RX */
6339 i40e_dev_rx_init(struct i40e_pf *pf)
6341 struct rte_eth_dev_data *data = pf->dev_data;
6342 int ret = I40E_SUCCESS;
6344 struct i40e_rx_queue *rxq;
6346 i40e_pf_config_mq_rx(pf);
6347 for (i = 0; i < data->nb_rx_queues; i++) {
6348 rxq = data->rx_queues[i];
6349 if (!rxq || !rxq->q_set)
6352 ret = i40e_rx_queue_init(rxq);
6353 if (ret != I40E_SUCCESS) {
6355 "Failed to do RX queue initialization");
6359 if (ret == I40E_SUCCESS)
6360 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6367 i40e_dev_rxtx_init(struct i40e_pf *pf)
6371 err = i40e_dev_tx_init(pf);
6373 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6376 err = i40e_dev_rx_init(pf);
6378 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6386 i40e_vmdq_setup(struct rte_eth_dev *dev)
6388 struct rte_eth_conf *conf = &dev->data->dev_conf;
6389 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6390 int i, err, conf_vsis, j, loop;
6391 struct i40e_vsi *vsi;
6392 struct i40e_vmdq_info *vmdq_info;
6393 struct rte_eth_vmdq_rx_conf *vmdq_conf;
6394 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6397 * Disable interrupt to avoid message from VF. Furthermore, it will
6398 * avoid race condition in VSI creation/destroy.
6400 i40e_pf_disable_irq0(hw);
6402 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6403 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6407 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6408 if (conf_vsis > pf->max_nb_vmdq_vsi) {
6409 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6410 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6411 pf->max_nb_vmdq_vsi);
6415 if (pf->vmdq != NULL) {
6416 PMD_INIT_LOG(INFO, "VMDQ already configured");
6420 pf->vmdq = rte_zmalloc("vmdq_info_struct",
6421 sizeof(*vmdq_info) * conf_vsis, 0);
6423 if (pf->vmdq == NULL) {
6424 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6428 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6430 /* Create VMDQ VSI */
6431 for (i = 0; i < conf_vsis; i++) {
6432 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6433 vmdq_conf->enable_loop_back);
6435 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6439 vmdq_info = &pf->vmdq[i];
6441 vmdq_info->vsi = vsi;
6443 pf->nb_cfg_vmdq_vsi = conf_vsis;
6445 /* Configure Vlan */
6446 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6447 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6448 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6449 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6450 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6451 vmdq_conf->pool_map[i].vlan_id, j);
6453 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6454 vmdq_conf->pool_map[i].vlan_id);
6456 PMD_INIT_LOG(ERR, "Failed to add vlan");
6464 i40e_pf_enable_irq0(hw);
6469 for (i = 0; i < conf_vsis; i++)
6470 if (pf->vmdq[i].vsi == NULL)
6473 i40e_vsi_release(pf->vmdq[i].vsi);
6477 i40e_pf_enable_irq0(hw);
6482 i40e_stat_update_32(struct i40e_hw *hw,
6490 new_data = (uint64_t)I40E_READ_REG(hw, reg);
6494 if (new_data >= *offset)
6495 *stat = (uint64_t)(new_data - *offset);
6497 *stat = (uint64_t)((new_data +
6498 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6502 i40e_stat_update_48(struct i40e_hw *hw,
6511 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6512 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6513 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6518 if (new_data >= *offset)
6519 *stat = new_data - *offset;
6521 *stat = (uint64_t)((new_data +
6522 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6524 *stat &= I40E_48_BIT_MASK;
6529 i40e_pf_disable_irq0(struct i40e_hw *hw)
6531 /* Disable all interrupt types */
6532 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6533 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6534 I40E_WRITE_FLUSH(hw);
6539 i40e_pf_enable_irq0(struct i40e_hw *hw)
6541 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6542 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6543 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6544 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6545 I40E_WRITE_FLUSH(hw);
6549 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6551 /* read pending request and disable first */
6552 i40e_pf_disable_irq0(hw);
6553 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6554 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6555 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6558 /* Link no queues with irq0 */
6559 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6560 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6564 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6566 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6567 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6570 uint32_t index, offset, val;
6575 * Try to find which VF trigger a reset, use absolute VF id to access
6576 * since the reg is global register.
6578 for (i = 0; i < pf->vf_num; i++) {
6579 abs_vf_id = hw->func_caps.vf_base_id + i;
6580 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6581 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6582 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6583 /* VFR event occurred */
6584 if (val & (0x1 << offset)) {
6587 /* Clear the event first */
6588 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6590 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6592 * Only notify a VF reset event occurred,
6593 * don't trigger another SW reset
6595 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6596 if (ret != I40E_SUCCESS)
6597 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6603 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6605 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6608 for (i = 0; i < pf->vf_num; i++)
6609 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6613 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6615 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6616 struct i40e_arq_event_info info;
6617 uint16_t pending, opcode;
6620 info.buf_len = I40E_AQ_BUF_SZ;
6621 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6622 if (!info.msg_buf) {
6623 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6629 ret = i40e_clean_arq_element(hw, &info, &pending);
6631 if (ret != I40E_SUCCESS) {
6633 "Failed to read msg from AdminQ, aq_err: %u",
6634 hw->aq.asq_last_status);
6637 opcode = rte_le_to_cpu_16(info.desc.opcode);
6640 case i40e_aqc_opc_send_msg_to_pf:
6641 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6642 i40e_pf_host_handle_vf_msg(dev,
6643 rte_le_to_cpu_16(info.desc.retval),
6644 rte_le_to_cpu_32(info.desc.cookie_high),
6645 rte_le_to_cpu_32(info.desc.cookie_low),
6649 case i40e_aqc_opc_get_link_status:
6650 ret = i40e_dev_link_update(dev, 0);
6652 _rte_eth_dev_callback_process(dev,
6653 RTE_ETH_EVENT_INTR_LSC, NULL);
6656 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6661 rte_free(info.msg_buf);
6665 * Interrupt handler triggered by NIC for handling
6666 * specific interrupt.
6669 * Pointer to interrupt handle.
6671 * The address of parameter (struct rte_eth_dev *) regsitered before.
6677 i40e_dev_interrupt_handler(void *param)
6679 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6680 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6683 /* Disable interrupt */
6684 i40e_pf_disable_irq0(hw);
6686 /* read out interrupt causes */
6687 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6689 /* No interrupt event indicated */
6690 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6691 PMD_DRV_LOG(INFO, "No interrupt event");
6694 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6695 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6696 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6697 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6698 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6699 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6700 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6701 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6702 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6703 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6704 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6705 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6706 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6707 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6709 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6710 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6711 i40e_dev_handle_vfr_event(dev);
6713 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6714 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6715 i40e_dev_handle_aq_msg(dev);
6719 /* Enable interrupt */
6720 i40e_pf_enable_irq0(hw);
6724 i40e_dev_alarm_handler(void *param)
6726 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6727 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6730 /* Disable interrupt */
6731 i40e_pf_disable_irq0(hw);
6733 /* read out interrupt causes */
6734 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6736 /* No interrupt event indicated */
6737 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
6739 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6740 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6741 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6742 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6743 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6744 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6745 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6746 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6747 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6748 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6749 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6750 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6751 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6752 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6754 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6755 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6756 i40e_dev_handle_vfr_event(dev);
6758 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6759 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6760 i40e_dev_handle_aq_msg(dev);
6764 /* Enable interrupt */
6765 i40e_pf_enable_irq0(hw);
6766 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
6767 i40e_dev_alarm_handler, dev);
6771 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6772 struct i40e_macvlan_filter *filter,
6775 int ele_num, ele_buff_size;
6776 int num, actual_num, i;
6778 int ret = I40E_SUCCESS;
6779 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6780 struct i40e_aqc_add_macvlan_element_data *req_list;
6782 if (filter == NULL || total == 0)
6783 return I40E_ERR_PARAM;
6784 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6785 ele_buff_size = hw->aq.asq_buf_size;
6787 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6788 if (req_list == NULL) {
6789 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6790 return I40E_ERR_NO_MEMORY;
6795 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6796 memset(req_list, 0, ele_buff_size);
6798 for (i = 0; i < actual_num; i++) {
6799 rte_memcpy(req_list[i].mac_addr,
6800 &filter[num + i].macaddr, ETH_ADDR_LEN);
6801 req_list[i].vlan_tag =
6802 rte_cpu_to_le_16(filter[num + i].vlan_id);
6804 switch (filter[num + i].filter_type) {
6805 case RTE_MAC_PERFECT_MATCH:
6806 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6807 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6809 case RTE_MACVLAN_PERFECT_MATCH:
6810 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6812 case RTE_MAC_HASH_MATCH:
6813 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6814 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6816 case RTE_MACVLAN_HASH_MATCH:
6817 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6820 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6821 ret = I40E_ERR_PARAM;
6825 req_list[i].queue_number = 0;
6827 req_list[i].flags = rte_cpu_to_le_16(flags);
6830 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6832 if (ret != I40E_SUCCESS) {
6833 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6837 } while (num < total);
6845 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6846 struct i40e_macvlan_filter *filter,
6849 int ele_num, ele_buff_size;
6850 int num, actual_num, i;
6852 int ret = I40E_SUCCESS;
6853 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6854 struct i40e_aqc_remove_macvlan_element_data *req_list;
6856 if (filter == NULL || total == 0)
6857 return I40E_ERR_PARAM;
6859 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6860 ele_buff_size = hw->aq.asq_buf_size;
6862 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6863 if (req_list == NULL) {
6864 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6865 return I40E_ERR_NO_MEMORY;
6870 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6871 memset(req_list, 0, ele_buff_size);
6873 for (i = 0; i < actual_num; i++) {
6874 rte_memcpy(req_list[i].mac_addr,
6875 &filter[num + i].macaddr, ETH_ADDR_LEN);
6876 req_list[i].vlan_tag =
6877 rte_cpu_to_le_16(filter[num + i].vlan_id);
6879 switch (filter[num + i].filter_type) {
6880 case RTE_MAC_PERFECT_MATCH:
6881 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6882 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6884 case RTE_MACVLAN_PERFECT_MATCH:
6885 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6887 case RTE_MAC_HASH_MATCH:
6888 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6889 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6891 case RTE_MACVLAN_HASH_MATCH:
6892 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6895 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6896 ret = I40E_ERR_PARAM;
6899 req_list[i].flags = rte_cpu_to_le_16(flags);
6902 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6904 if (ret != I40E_SUCCESS) {
6905 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6909 } while (num < total);
6916 /* Find out specific MAC filter */
6917 static struct i40e_mac_filter *
6918 i40e_find_mac_filter(struct i40e_vsi *vsi,
6919 struct rte_ether_addr *macaddr)
6921 struct i40e_mac_filter *f;
6923 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6924 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6932 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6935 uint32_t vid_idx, vid_bit;
6937 if (vlan_id > ETH_VLAN_ID_MAX)
6940 vid_idx = I40E_VFTA_IDX(vlan_id);
6941 vid_bit = I40E_VFTA_BIT(vlan_id);
6943 if (vsi->vfta[vid_idx] & vid_bit)
6950 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6951 uint16_t vlan_id, bool on)
6953 uint32_t vid_idx, vid_bit;
6955 vid_idx = I40E_VFTA_IDX(vlan_id);
6956 vid_bit = I40E_VFTA_BIT(vlan_id);
6959 vsi->vfta[vid_idx] |= vid_bit;
6961 vsi->vfta[vid_idx] &= ~vid_bit;
6965 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6966 uint16_t vlan_id, bool on)
6968 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6969 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6972 if (vlan_id > ETH_VLAN_ID_MAX)
6975 i40e_store_vlan_filter(vsi, vlan_id, on);
6977 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6980 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6983 ret = i40e_aq_add_vlan(hw, vsi->seid,
6984 &vlan_data, 1, NULL);
6985 if (ret != I40E_SUCCESS)
6986 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6988 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6989 &vlan_data, 1, NULL);
6990 if (ret != I40E_SUCCESS)
6992 "Failed to remove vlan filter");
6997 * Find all vlan options for specific mac addr,
6998 * return with actual vlan found.
7001 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
7002 struct i40e_macvlan_filter *mv_f,
7003 int num, struct rte_ether_addr *addr)
7009 * Not to use i40e_find_vlan_filter to decrease the loop time,
7010 * although the code looks complex.
7012 if (num < vsi->vlan_num)
7013 return I40E_ERR_PARAM;
7016 for (j = 0; j < I40E_VFTA_SIZE; j++) {
7018 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
7019 if (vsi->vfta[j] & (1 << k)) {
7022 "vlan number doesn't match");
7023 return I40E_ERR_PARAM;
7025 rte_memcpy(&mv_f[i].macaddr,
7026 addr, ETH_ADDR_LEN);
7028 j * I40E_UINT32_BIT_SIZE + k;
7034 return I40E_SUCCESS;
7038 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
7039 struct i40e_macvlan_filter *mv_f,
7044 struct i40e_mac_filter *f;
7046 if (num < vsi->mac_num)
7047 return I40E_ERR_PARAM;
7049 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7051 PMD_DRV_LOG(ERR, "buffer number not match");
7052 return I40E_ERR_PARAM;
7054 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7056 mv_f[i].vlan_id = vlan;
7057 mv_f[i].filter_type = f->mac_info.filter_type;
7061 return I40E_SUCCESS;
7065 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
7068 struct i40e_mac_filter *f;
7069 struct i40e_macvlan_filter *mv_f;
7070 int ret = I40E_SUCCESS;
7072 if (vsi == NULL || vsi->mac_num == 0)
7073 return I40E_ERR_PARAM;
7075 /* Case that no vlan is set */
7076 if (vsi->vlan_num == 0)
7079 num = vsi->mac_num * vsi->vlan_num;
7081 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7083 PMD_DRV_LOG(ERR, "failed to allocate memory");
7084 return I40E_ERR_NO_MEMORY;
7088 if (vsi->vlan_num == 0) {
7089 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7090 rte_memcpy(&mv_f[i].macaddr,
7091 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7092 mv_f[i].filter_type = f->mac_info.filter_type;
7093 mv_f[i].vlan_id = 0;
7097 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7098 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7099 vsi->vlan_num, &f->mac_info.mac_addr);
7100 if (ret != I40E_SUCCESS)
7102 for (j = i; j < i + vsi->vlan_num; j++)
7103 mv_f[j].filter_type = f->mac_info.filter_type;
7108 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7116 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7118 struct i40e_macvlan_filter *mv_f;
7120 int ret = I40E_SUCCESS;
7122 if (!vsi || vlan > RTE_ETHER_MAX_VLAN_ID)
7123 return I40E_ERR_PARAM;
7125 /* If it's already set, just return */
7126 if (i40e_find_vlan_filter(vsi,vlan))
7127 return I40E_SUCCESS;
7129 mac_num = vsi->mac_num;
7132 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7133 return I40E_ERR_PARAM;
7136 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7139 PMD_DRV_LOG(ERR, "failed to allocate memory");
7140 return I40E_ERR_NO_MEMORY;
7143 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7145 if (ret != I40E_SUCCESS)
7148 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7150 if (ret != I40E_SUCCESS)
7153 i40e_set_vlan_filter(vsi, vlan, 1);
7163 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7165 struct i40e_macvlan_filter *mv_f;
7167 int ret = I40E_SUCCESS;
7170 * Vlan 0 is the generic filter for untagged packets
7171 * and can't be removed.
7173 if (!vsi || vlan == 0 || vlan > RTE_ETHER_MAX_VLAN_ID)
7174 return I40E_ERR_PARAM;
7176 /* If can't find it, just return */
7177 if (!i40e_find_vlan_filter(vsi, vlan))
7178 return I40E_ERR_PARAM;
7180 mac_num = vsi->mac_num;
7183 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7184 return I40E_ERR_PARAM;
7187 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7190 PMD_DRV_LOG(ERR, "failed to allocate memory");
7191 return I40E_ERR_NO_MEMORY;
7194 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7196 if (ret != I40E_SUCCESS)
7199 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7201 if (ret != I40E_SUCCESS)
7204 /* This is last vlan to remove, replace all mac filter with vlan 0 */
7205 if (vsi->vlan_num == 1) {
7206 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7207 if (ret != I40E_SUCCESS)
7210 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7211 if (ret != I40E_SUCCESS)
7215 i40e_set_vlan_filter(vsi, vlan, 0);
7225 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7227 struct i40e_mac_filter *f;
7228 struct i40e_macvlan_filter *mv_f;
7229 int i, vlan_num = 0;
7230 int ret = I40E_SUCCESS;
7232 /* If it's add and we've config it, return */
7233 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7235 return I40E_SUCCESS;
7236 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
7237 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
7240 * If vlan_num is 0, that's the first time to add mac,
7241 * set mask for vlan_id 0.
7243 if (vsi->vlan_num == 0) {
7244 i40e_set_vlan_filter(vsi, 0, 1);
7247 vlan_num = vsi->vlan_num;
7248 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
7249 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
7252 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7254 PMD_DRV_LOG(ERR, "failed to allocate memory");
7255 return I40E_ERR_NO_MEMORY;
7258 for (i = 0; i < vlan_num; i++) {
7259 mv_f[i].filter_type = mac_filter->filter_type;
7260 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7264 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7265 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
7266 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7267 &mac_filter->mac_addr);
7268 if (ret != I40E_SUCCESS)
7272 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7273 if (ret != I40E_SUCCESS)
7276 /* Add the mac addr into mac list */
7277 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7279 PMD_DRV_LOG(ERR, "failed to allocate memory");
7280 ret = I40E_ERR_NO_MEMORY;
7283 rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7285 f->mac_info.filter_type = mac_filter->filter_type;
7286 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7297 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr)
7299 struct i40e_mac_filter *f;
7300 struct i40e_macvlan_filter *mv_f;
7302 enum rte_mac_filter_type filter_type;
7303 int ret = I40E_SUCCESS;
7305 /* Can't find it, return an error */
7306 f = i40e_find_mac_filter(vsi, addr);
7308 return I40E_ERR_PARAM;
7310 vlan_num = vsi->vlan_num;
7311 filter_type = f->mac_info.filter_type;
7312 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7313 filter_type == RTE_MACVLAN_HASH_MATCH) {
7314 if (vlan_num == 0) {
7315 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7316 return I40E_ERR_PARAM;
7318 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7319 filter_type == RTE_MAC_HASH_MATCH)
7322 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7324 PMD_DRV_LOG(ERR, "failed to allocate memory");
7325 return I40E_ERR_NO_MEMORY;
7328 for (i = 0; i < vlan_num; i++) {
7329 mv_f[i].filter_type = filter_type;
7330 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7333 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7334 filter_type == RTE_MACVLAN_HASH_MATCH) {
7335 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7336 if (ret != I40E_SUCCESS)
7340 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7341 if (ret != I40E_SUCCESS)
7344 /* Remove the mac addr into mac list */
7345 TAILQ_REMOVE(&vsi->mac_list, f, next);
7355 /* Configure hash enable flags for RSS */
7357 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7365 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7366 if (flags & (1ULL << i))
7367 hena |= adapter->pctypes_tbl[i];
7373 /* Parse the hash enable flags */
7375 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7377 uint64_t rss_hf = 0;
7383 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7384 if (flags & adapter->pctypes_tbl[i])
7385 rss_hf |= (1ULL << i);
7392 i40e_pf_disable_rss(struct i40e_pf *pf)
7394 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7396 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7397 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7398 I40E_WRITE_FLUSH(hw);
7402 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7404 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7405 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7406 uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7407 I40E_VFQF_HKEY_MAX_INDEX :
7408 I40E_PFQF_HKEY_MAX_INDEX;
7411 if (!key || key_len == 0) {
7412 PMD_DRV_LOG(DEBUG, "No key to be configured");
7414 } else if (key_len != (key_idx + 1) *
7416 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7420 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7421 struct i40e_aqc_get_set_rss_key_data *key_dw =
7422 (struct i40e_aqc_get_set_rss_key_data *)key;
7424 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7426 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7428 uint32_t *hash_key = (uint32_t *)key;
7431 if (vsi->type == I40E_VSI_SRIOV) {
7432 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7435 I40E_VFQF_HKEY1(i, vsi->user_param),
7439 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7440 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7443 I40E_WRITE_FLUSH(hw);
7450 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7452 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7453 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7457 if (!key || !key_len)
7460 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7461 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7462 (struct i40e_aqc_get_set_rss_key_data *)key);
7464 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7468 uint32_t *key_dw = (uint32_t *)key;
7471 if (vsi->type == I40E_VSI_SRIOV) {
7472 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7473 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7474 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7476 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7479 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7480 reg = I40E_PFQF_HKEY(i);
7481 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7483 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7491 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7493 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7497 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7498 rss_conf->rss_key_len);
7502 hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7503 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7504 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7505 I40E_WRITE_FLUSH(hw);
7511 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7512 struct rte_eth_rss_conf *rss_conf)
7514 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7515 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7516 uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7519 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7520 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7522 if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7523 if (rss_hf != 0) /* Enable RSS */
7525 return 0; /* Nothing to do */
7528 if (rss_hf == 0) /* Disable RSS */
7531 return i40e_hw_rss_hash_set(pf, rss_conf);
7535 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7536 struct rte_eth_rss_conf *rss_conf)
7538 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7539 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7546 ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7547 &rss_conf->rss_key_len);
7551 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7552 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7553 rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7559 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7561 switch (filter_type) {
7562 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7563 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7565 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7566 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7568 case RTE_TUNNEL_FILTER_IMAC_TENID:
7569 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7571 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7572 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7574 case ETH_TUNNEL_FILTER_IMAC:
7575 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7577 case ETH_TUNNEL_FILTER_OIP:
7578 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7580 case ETH_TUNNEL_FILTER_IIP:
7581 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7584 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7591 /* Convert tunnel filter structure */
7593 i40e_tunnel_filter_convert(
7594 struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7595 struct i40e_tunnel_filter *tunnel_filter)
7597 rte_ether_addr_copy((struct rte_ether_addr *)
7598 &cld_filter->element.outer_mac,
7599 (struct rte_ether_addr *)&tunnel_filter->input.outer_mac);
7600 rte_ether_addr_copy((struct rte_ether_addr *)
7601 &cld_filter->element.inner_mac,
7602 (struct rte_ether_addr *)&tunnel_filter->input.inner_mac);
7603 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7604 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7605 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7606 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7607 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7609 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7610 tunnel_filter->input.flags = cld_filter->element.flags;
7611 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7612 tunnel_filter->queue = cld_filter->element.queue_number;
7613 rte_memcpy(tunnel_filter->input.general_fields,
7614 cld_filter->general_fields,
7615 sizeof(cld_filter->general_fields));
7620 /* Check if there exists the tunnel filter */
7621 struct i40e_tunnel_filter *
7622 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7623 const struct i40e_tunnel_filter_input *input)
7627 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7631 return tunnel_rule->hash_map[ret];
7634 /* Add a tunnel filter into the SW list */
7636 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7637 struct i40e_tunnel_filter *tunnel_filter)
7639 struct i40e_tunnel_rule *rule = &pf->tunnel;
7642 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7645 "Failed to insert tunnel filter to hash table %d!",
7649 rule->hash_map[ret] = tunnel_filter;
7651 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7656 /* Delete a tunnel filter from the SW list */
7658 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7659 struct i40e_tunnel_filter_input *input)
7661 struct i40e_tunnel_rule *rule = &pf->tunnel;
7662 struct i40e_tunnel_filter *tunnel_filter;
7665 ret = rte_hash_del_key(rule->hash_table, input);
7668 "Failed to delete tunnel filter to hash table %d!",
7672 tunnel_filter = rule->hash_map[ret];
7673 rule->hash_map[ret] = NULL;
7675 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7676 rte_free(tunnel_filter);
7682 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7683 struct rte_eth_tunnel_filter_conf *tunnel_filter,
7687 uint32_t ipv4_addr, ipv4_addr_le;
7688 uint8_t i, tun_type = 0;
7689 /* internal varialbe to convert ipv6 byte order */
7690 uint32_t convert_ipv6[4];
7692 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7693 struct i40e_vsi *vsi = pf->main_vsi;
7694 struct i40e_aqc_cloud_filters_element_bb *cld_filter;
7695 struct i40e_aqc_cloud_filters_element_bb *pfilter;
7696 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7697 struct i40e_tunnel_filter *tunnel, *node;
7698 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7700 cld_filter = rte_zmalloc("tunnel_filter",
7701 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7704 if (NULL == cld_filter) {
7705 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7708 pfilter = cld_filter;
7710 rte_ether_addr_copy(&tunnel_filter->outer_mac,
7711 (struct rte_ether_addr *)&pfilter->element.outer_mac);
7712 rte_ether_addr_copy(&tunnel_filter->inner_mac,
7713 (struct rte_ether_addr *)&pfilter->element.inner_mac);
7715 pfilter->element.inner_vlan =
7716 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7717 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7718 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7719 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7720 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7721 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7723 sizeof(pfilter->element.ipaddr.v4.data));
7725 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7726 for (i = 0; i < 4; i++) {
7728 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7730 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7732 sizeof(pfilter->element.ipaddr.v6.data));
7735 /* check tunneled type */
7736 switch (tunnel_filter->tunnel_type) {
7737 case RTE_TUNNEL_TYPE_VXLAN:
7738 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7740 case RTE_TUNNEL_TYPE_NVGRE:
7741 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7743 case RTE_TUNNEL_TYPE_IP_IN_GRE:
7744 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7746 case RTE_TUNNEL_TYPE_VXLAN_GPE:
7747 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE;
7750 /* Other tunnel types is not supported. */
7751 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7752 rte_free(cld_filter);
7756 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7757 &pfilter->element.flags);
7759 rte_free(cld_filter);
7763 pfilter->element.flags |= rte_cpu_to_le_16(
7764 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7765 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7766 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7767 pfilter->element.queue_number =
7768 rte_cpu_to_le_16(tunnel_filter->queue_id);
7770 /* Check if there is the filter in SW list */
7771 memset(&check_filter, 0, sizeof(check_filter));
7772 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7773 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7775 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7776 rte_free(cld_filter);
7780 if (!add && !node) {
7781 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7782 rte_free(cld_filter);
7787 ret = i40e_aq_add_cloud_filters(hw,
7788 vsi->seid, &cld_filter->element, 1);
7790 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7791 rte_free(cld_filter);
7794 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7795 if (tunnel == NULL) {
7796 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7797 rte_free(cld_filter);
7801 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7802 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7806 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
7807 &cld_filter->element, 1);
7809 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7810 rte_free(cld_filter);
7813 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7816 rte_free(cld_filter);
7820 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7821 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
7822 #define I40E_TR_GENEVE_KEY_MASK 0x8
7823 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
7824 #define I40E_TR_GRE_KEY_MASK 0x400
7825 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
7826 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
7829 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7831 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7832 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7833 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7834 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7835 enum i40e_status_code status = I40E_SUCCESS;
7837 if (pf->support_multi_driver) {
7838 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7839 return I40E_NOT_SUPPORTED;
7842 memset(&filter_replace, 0,
7843 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7844 memset(&filter_replace_buf, 0,
7845 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7847 /* create L1 filter */
7848 filter_replace.old_filter_type =
7849 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7850 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7851 filter_replace.tr_bit = 0;
7853 /* Prepare the buffer, 3 entries */
7854 filter_replace_buf.data[0] =
7855 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7856 filter_replace_buf.data[0] |=
7857 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7858 filter_replace_buf.data[2] = 0xFF;
7859 filter_replace_buf.data[3] = 0xFF;
7860 filter_replace_buf.data[4] =
7861 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7862 filter_replace_buf.data[4] |=
7863 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7864 filter_replace_buf.data[7] = 0xF0;
7865 filter_replace_buf.data[8]
7866 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7867 filter_replace_buf.data[8] |=
7868 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7869 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7870 I40E_TR_GENEVE_KEY_MASK |
7871 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7872 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7873 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7874 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7876 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7877 &filter_replace_buf);
7878 if (!status && (filter_replace.old_filter_type !=
7879 filter_replace.new_filter_type))
7880 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7881 " original: 0x%x, new: 0x%x",
7883 filter_replace.old_filter_type,
7884 filter_replace.new_filter_type);
7890 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7892 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7893 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7894 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7895 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7896 enum i40e_status_code status = I40E_SUCCESS;
7898 if (pf->support_multi_driver) {
7899 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7900 return I40E_NOT_SUPPORTED;
7904 memset(&filter_replace, 0,
7905 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7906 memset(&filter_replace_buf, 0,
7907 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7908 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7909 I40E_AQC_MIRROR_CLOUD_FILTER;
7910 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7911 filter_replace.new_filter_type =
7912 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7913 /* Prepare the buffer, 2 entries */
7914 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7915 filter_replace_buf.data[0] |=
7916 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7917 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7918 filter_replace_buf.data[4] |=
7919 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7920 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7921 &filter_replace_buf);
7924 if (filter_replace.old_filter_type !=
7925 filter_replace.new_filter_type)
7926 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7927 " original: 0x%x, new: 0x%x",
7929 filter_replace.old_filter_type,
7930 filter_replace.new_filter_type);
7933 memset(&filter_replace, 0,
7934 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7935 memset(&filter_replace_buf, 0,
7936 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7938 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7939 I40E_AQC_MIRROR_CLOUD_FILTER;
7940 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7941 filter_replace.new_filter_type =
7942 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7943 /* Prepare the buffer, 2 entries */
7944 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7945 filter_replace_buf.data[0] |=
7946 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7947 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7948 filter_replace_buf.data[4] |=
7949 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7951 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7952 &filter_replace_buf);
7953 if (!status && (filter_replace.old_filter_type !=
7954 filter_replace.new_filter_type))
7955 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7956 " original: 0x%x, new: 0x%x",
7958 filter_replace.old_filter_type,
7959 filter_replace.new_filter_type);
7964 static enum i40e_status_code
7965 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7967 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7968 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7969 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7970 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7971 enum i40e_status_code status = I40E_SUCCESS;
7973 if (pf->support_multi_driver) {
7974 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7975 return I40E_NOT_SUPPORTED;
7979 memset(&filter_replace, 0,
7980 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7981 memset(&filter_replace_buf, 0,
7982 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7983 /* create L1 filter */
7984 filter_replace.old_filter_type =
7985 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7986 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7987 filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7988 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7989 /* Prepare the buffer, 2 entries */
7990 filter_replace_buf.data[0] =
7991 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7992 filter_replace_buf.data[0] |=
7993 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7994 filter_replace_buf.data[2] = 0xFF;
7995 filter_replace_buf.data[3] = 0xFF;
7996 filter_replace_buf.data[4] =
7997 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7998 filter_replace_buf.data[4] |=
7999 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8000 filter_replace_buf.data[6] = 0xFF;
8001 filter_replace_buf.data[7] = 0xFF;
8002 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8003 &filter_replace_buf);
8006 if (filter_replace.old_filter_type !=
8007 filter_replace.new_filter_type)
8008 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8009 " original: 0x%x, new: 0x%x",
8011 filter_replace.old_filter_type,
8012 filter_replace.new_filter_type);
8015 memset(&filter_replace, 0,
8016 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8017 memset(&filter_replace_buf, 0,
8018 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8019 /* create L1 filter */
8020 filter_replace.old_filter_type =
8021 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8022 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
8023 filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
8024 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8025 /* Prepare the buffer, 2 entries */
8026 filter_replace_buf.data[0] =
8027 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8028 filter_replace_buf.data[0] |=
8029 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8030 filter_replace_buf.data[2] = 0xFF;
8031 filter_replace_buf.data[3] = 0xFF;
8032 filter_replace_buf.data[4] =
8033 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8034 filter_replace_buf.data[4] |=
8035 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8036 filter_replace_buf.data[6] = 0xFF;
8037 filter_replace_buf.data[7] = 0xFF;
8039 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8040 &filter_replace_buf);
8041 if (!status && (filter_replace.old_filter_type !=
8042 filter_replace.new_filter_type))
8043 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8044 " original: 0x%x, new: 0x%x",
8046 filter_replace.old_filter_type,
8047 filter_replace.new_filter_type);
8053 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
8055 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8056 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8057 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8058 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8059 enum i40e_status_code status = I40E_SUCCESS;
8061 if (pf->support_multi_driver) {
8062 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8063 return I40E_NOT_SUPPORTED;
8067 memset(&filter_replace, 0,
8068 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8069 memset(&filter_replace_buf, 0,
8070 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8071 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8072 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
8073 filter_replace.new_filter_type =
8074 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8075 /* Prepare the buffer, 2 entries */
8076 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
8077 filter_replace_buf.data[0] |=
8078 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8079 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8080 filter_replace_buf.data[4] |=
8081 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8082 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8083 &filter_replace_buf);
8086 if (filter_replace.old_filter_type !=
8087 filter_replace.new_filter_type)
8088 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8089 " original: 0x%x, new: 0x%x",
8091 filter_replace.old_filter_type,
8092 filter_replace.new_filter_type);
8095 memset(&filter_replace, 0,
8096 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8097 memset(&filter_replace_buf, 0,
8098 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8099 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8100 filter_replace.old_filter_type =
8101 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8102 filter_replace.new_filter_type =
8103 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8104 /* Prepare the buffer, 2 entries */
8105 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8106 filter_replace_buf.data[0] |=
8107 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8108 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8109 filter_replace_buf.data[4] |=
8110 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8112 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8113 &filter_replace_buf);
8114 if (!status && (filter_replace.old_filter_type !=
8115 filter_replace.new_filter_type))
8116 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8117 " original: 0x%x, new: 0x%x",
8119 filter_replace.old_filter_type,
8120 filter_replace.new_filter_type);
8126 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8127 struct i40e_tunnel_filter_conf *tunnel_filter,
8131 uint32_t ipv4_addr, ipv4_addr_le;
8132 uint8_t i, tun_type = 0;
8133 /* internal variable to convert ipv6 byte order */
8134 uint32_t convert_ipv6[4];
8136 struct i40e_pf_vf *vf = NULL;
8137 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8138 struct i40e_vsi *vsi;
8139 struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8140 struct i40e_aqc_cloud_filters_element_bb *pfilter;
8141 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8142 struct i40e_tunnel_filter *tunnel, *node;
8143 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8145 bool big_buffer = 0;
8147 cld_filter = rte_zmalloc("tunnel_filter",
8148 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8151 if (cld_filter == NULL) {
8152 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8155 pfilter = cld_filter;
8157 rte_ether_addr_copy(&tunnel_filter->outer_mac,
8158 (struct rte_ether_addr *)&pfilter->element.outer_mac);
8159 rte_ether_addr_copy(&tunnel_filter->inner_mac,
8160 (struct rte_ether_addr *)&pfilter->element.inner_mac);
8162 pfilter->element.inner_vlan =
8163 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8164 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8165 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8166 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8167 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8168 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8170 sizeof(pfilter->element.ipaddr.v4.data));
8172 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8173 for (i = 0; i < 4; i++) {
8175 rte_cpu_to_le_32(rte_be_to_cpu_32(
8176 tunnel_filter->ip_addr.ipv6_addr[i]));
8178 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8180 sizeof(pfilter->element.ipaddr.v6.data));
8183 /* check tunneled type */
8184 switch (tunnel_filter->tunnel_type) {
8185 case I40E_TUNNEL_TYPE_VXLAN:
8186 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8188 case I40E_TUNNEL_TYPE_NVGRE:
8189 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8191 case I40E_TUNNEL_TYPE_IP_IN_GRE:
8192 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8194 case I40E_TUNNEL_TYPE_MPLSoUDP:
8195 if (!pf->mpls_replace_flag) {
8196 i40e_replace_mpls_l1_filter(pf);
8197 i40e_replace_mpls_cloud_filter(pf);
8198 pf->mpls_replace_flag = 1;
8200 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8201 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8203 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8204 (teid_le & 0xF) << 12;
8205 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8208 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8210 case I40E_TUNNEL_TYPE_MPLSoGRE:
8211 if (!pf->mpls_replace_flag) {
8212 i40e_replace_mpls_l1_filter(pf);
8213 i40e_replace_mpls_cloud_filter(pf);
8214 pf->mpls_replace_flag = 1;
8216 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8217 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8219 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8220 (teid_le & 0xF) << 12;
8221 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8224 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8226 case I40E_TUNNEL_TYPE_GTPC:
8227 if (!pf->gtp_replace_flag) {
8228 i40e_replace_gtp_l1_filter(pf);
8229 i40e_replace_gtp_cloud_filter(pf);
8230 pf->gtp_replace_flag = 1;
8232 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8233 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8234 (teid_le >> 16) & 0xFFFF;
8235 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8237 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8241 case I40E_TUNNEL_TYPE_GTPU:
8242 if (!pf->gtp_replace_flag) {
8243 i40e_replace_gtp_l1_filter(pf);
8244 i40e_replace_gtp_cloud_filter(pf);
8245 pf->gtp_replace_flag = 1;
8247 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8248 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8249 (teid_le >> 16) & 0xFFFF;
8250 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8252 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8256 case I40E_TUNNEL_TYPE_QINQ:
8257 if (!pf->qinq_replace_flag) {
8258 ret = i40e_cloud_filter_qinq_create(pf);
8261 "QinQ tunnel filter already created.");
8262 pf->qinq_replace_flag = 1;
8264 /* Add in the General fields the values of
8265 * the Outer and Inner VLAN
8266 * Big Buffer should be set, see changes in
8267 * i40e_aq_add_cloud_filters
8269 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8270 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8274 /* Other tunnel types is not supported. */
8275 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8276 rte_free(cld_filter);
8280 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8281 pfilter->element.flags =
8282 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8283 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8284 pfilter->element.flags =
8285 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8286 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8287 pfilter->element.flags =
8288 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8289 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8290 pfilter->element.flags =
8291 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8292 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8293 pfilter->element.flags |=
8294 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8296 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8297 &pfilter->element.flags);
8299 rte_free(cld_filter);
8304 pfilter->element.flags |= rte_cpu_to_le_16(
8305 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8306 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8307 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8308 pfilter->element.queue_number =
8309 rte_cpu_to_le_16(tunnel_filter->queue_id);
8311 if (!tunnel_filter->is_to_vf)
8314 if (tunnel_filter->vf_id >= pf->vf_num) {
8315 PMD_DRV_LOG(ERR, "Invalid argument.");
8316 rte_free(cld_filter);
8319 vf = &pf->vfs[tunnel_filter->vf_id];
8323 /* Check if there is the filter in SW list */
8324 memset(&check_filter, 0, sizeof(check_filter));
8325 i40e_tunnel_filter_convert(cld_filter, &check_filter);
8326 check_filter.is_to_vf = tunnel_filter->is_to_vf;
8327 check_filter.vf_id = tunnel_filter->vf_id;
8328 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8330 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8331 rte_free(cld_filter);
8335 if (!add && !node) {
8336 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8337 rte_free(cld_filter);
8343 ret = i40e_aq_add_cloud_filters_bb(hw,
8344 vsi->seid, cld_filter, 1);
8346 ret = i40e_aq_add_cloud_filters(hw,
8347 vsi->seid, &cld_filter->element, 1);
8349 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8350 rte_free(cld_filter);
8353 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8354 if (tunnel == NULL) {
8355 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8356 rte_free(cld_filter);
8360 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8361 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8366 ret = i40e_aq_rem_cloud_filters_bb(
8367 hw, vsi->seid, cld_filter, 1);
8369 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8370 &cld_filter->element, 1);
8372 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8373 rte_free(cld_filter);
8376 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8379 rte_free(cld_filter);
8384 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8388 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8389 if (pf->vxlan_ports[i] == port)
8397 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port, int udp_type)
8401 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8403 idx = i40e_get_vxlan_port_idx(pf, port);
8405 /* Check if port already exists */
8407 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8411 /* Now check if there is space to add the new port */
8412 idx = i40e_get_vxlan_port_idx(pf, 0);
8415 "Maximum number of UDP ports reached, not adding port %d",
8420 ret = i40e_aq_add_udp_tunnel(hw, port, udp_type,
8423 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8427 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8430 /* New port: add it and mark its index in the bitmap */
8431 pf->vxlan_ports[idx] = port;
8432 pf->vxlan_bitmap |= (1 << idx);
8434 if (!(pf->flags & I40E_FLAG_VXLAN))
8435 pf->flags |= I40E_FLAG_VXLAN;
8441 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8444 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8446 if (!(pf->flags & I40E_FLAG_VXLAN)) {
8447 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8451 idx = i40e_get_vxlan_port_idx(pf, port);
8454 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8458 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8459 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8463 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8466 pf->vxlan_ports[idx] = 0;
8467 pf->vxlan_bitmap &= ~(1 << idx);
8469 if (!pf->vxlan_bitmap)
8470 pf->flags &= ~I40E_FLAG_VXLAN;
8475 /* Add UDP tunneling port */
8477 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8478 struct rte_eth_udp_tunnel *udp_tunnel)
8481 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8483 if (udp_tunnel == NULL)
8486 switch (udp_tunnel->prot_type) {
8487 case RTE_TUNNEL_TYPE_VXLAN:
8488 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8489 I40E_AQC_TUNNEL_TYPE_VXLAN);
8491 case RTE_TUNNEL_TYPE_VXLAN_GPE:
8492 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8493 I40E_AQC_TUNNEL_TYPE_VXLAN_GPE);
8495 case RTE_TUNNEL_TYPE_GENEVE:
8496 case RTE_TUNNEL_TYPE_TEREDO:
8497 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8502 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8510 /* Remove UDP tunneling port */
8512 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8513 struct rte_eth_udp_tunnel *udp_tunnel)
8516 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8518 if (udp_tunnel == NULL)
8521 switch (udp_tunnel->prot_type) {
8522 case RTE_TUNNEL_TYPE_VXLAN:
8523 case RTE_TUNNEL_TYPE_VXLAN_GPE:
8524 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8526 case RTE_TUNNEL_TYPE_GENEVE:
8527 case RTE_TUNNEL_TYPE_TEREDO:
8528 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8532 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8540 /* Calculate the maximum number of contiguous PF queues that are configured */
8542 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8544 struct rte_eth_dev_data *data = pf->dev_data;
8546 struct i40e_rx_queue *rxq;
8549 for (i = 0; i < pf->lan_nb_qps; i++) {
8550 rxq = data->rx_queues[i];
8551 if (rxq && rxq->q_set)
8562 i40e_pf_config_rss(struct i40e_pf *pf)
8564 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8565 struct rte_eth_rss_conf rss_conf;
8566 uint32_t i, lut = 0;
8570 * If both VMDQ and RSS enabled, not all of PF queues are configured.
8571 * It's necessary to calculate the actual PF queues that are configured.
8573 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8574 num = i40e_pf_calc_configured_queues_num(pf);
8576 num = pf->dev_data->nb_rx_queues;
8578 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8579 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8583 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
8587 if (pf->adapter->rss_reta_updated == 0) {
8588 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8591 lut = (lut << 8) | (j & ((0x1 <<
8592 hw->func_caps.rss_table_entry_width) - 1));
8594 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2),
8599 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8600 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8601 i40e_pf_disable_rss(pf);
8604 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8605 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8606 /* Random default keys */
8607 static uint32_t rss_key_default[] = {0x6b793944,
8608 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8609 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8610 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8612 rss_conf.rss_key = (uint8_t *)rss_key_default;
8613 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8617 return i40e_hw_rss_hash_set(pf, &rss_conf);
8621 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8622 struct rte_eth_tunnel_filter_conf *filter)
8624 if (pf == NULL || filter == NULL) {
8625 PMD_DRV_LOG(ERR, "Invalid parameter");
8629 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8630 PMD_DRV_LOG(ERR, "Invalid queue ID");
8634 if (filter->inner_vlan > RTE_ETHER_MAX_VLAN_ID) {
8635 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8639 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8640 (rte_is_zero_ether_addr(&filter->outer_mac))) {
8641 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8645 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8646 (rte_is_zero_ether_addr(&filter->inner_mac))) {
8647 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8654 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8655 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
8657 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8659 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8663 if (pf->support_multi_driver) {
8664 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8668 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8669 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8672 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8673 } else if (len == 4) {
8674 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8676 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8681 ret = i40e_aq_debug_write_global_register(hw,
8682 I40E_GL_PRS_FVBM(2),
8686 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8687 "with value 0x%08x",
8688 I40E_GL_PRS_FVBM(2), reg);
8692 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8693 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8699 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8706 switch (cfg->cfg_type) {
8707 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8708 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8711 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8719 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8720 enum rte_filter_op filter_op,
8723 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8724 int ret = I40E_ERR_PARAM;
8726 switch (filter_op) {
8727 case RTE_ETH_FILTER_SET:
8728 ret = i40e_dev_global_config_set(hw,
8729 (struct rte_eth_global_cfg *)arg);
8732 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8740 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8741 enum rte_filter_op filter_op,
8744 struct rte_eth_tunnel_filter_conf *filter;
8745 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8746 int ret = I40E_SUCCESS;
8748 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8750 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8751 return I40E_ERR_PARAM;
8753 switch (filter_op) {
8754 case RTE_ETH_FILTER_NOP:
8755 if (!(pf->flags & I40E_FLAG_VXLAN))
8756 ret = I40E_NOT_SUPPORTED;
8758 case RTE_ETH_FILTER_ADD:
8759 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8761 case RTE_ETH_FILTER_DELETE:
8762 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8765 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8766 ret = I40E_ERR_PARAM;
8774 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8777 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8780 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8781 ret = i40e_pf_config_rss(pf);
8783 i40e_pf_disable_rss(pf);
8788 /* Get the symmetric hash enable configurations per port */
8790 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8792 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8794 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8797 /* Set the symmetric hash enable configurations per port */
8799 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8801 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8804 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8806 "Symmetric hash has already been enabled");
8809 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8811 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8813 "Symmetric hash has already been disabled");
8816 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8818 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8819 I40E_WRITE_FLUSH(hw);
8823 * Get global configurations of hash function type and symmetric hash enable
8824 * per flow type (pctype). Note that global configuration means it affects all
8825 * the ports on the same NIC.
8828 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8829 struct rte_eth_hash_global_conf *g_cfg)
8831 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8835 memset(g_cfg, 0, sizeof(*g_cfg));
8836 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8837 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8838 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8840 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8841 PMD_DRV_LOG(DEBUG, "Hash function is %s",
8842 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8845 * As i40e supports less than 64 flow types, only first 64 bits need to
8848 for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8849 g_cfg->valid_bit_mask[i] = 0ULL;
8850 g_cfg->sym_hash_enable_mask[i] = 0ULL;
8853 g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
8855 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
8856 if (!adapter->pctypes_tbl[i])
8858 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8859 j < I40E_FILTER_PCTYPE_MAX; j++) {
8860 if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8861 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8862 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8863 g_cfg->sym_hash_enable_mask[0] |=
8874 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8875 const struct rte_eth_hash_global_conf *g_cfg)
8878 uint64_t mask0, i40e_mask = adapter->flow_types_mask;
8880 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8881 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8882 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8883 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8889 * As i40e supports less than 64 flow types, only first 64 bits need to
8892 mask0 = g_cfg->valid_bit_mask[0];
8893 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8895 /* Check if any unsupported flow type configured */
8896 if ((mask0 | i40e_mask) ^ i40e_mask)
8899 if (g_cfg->valid_bit_mask[i])
8907 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8913 * Set global configurations of hash function type and symmetric hash enable
8914 * per flow type (pctype). Note any modifying global configuration will affect
8915 * all the ports on the same NIC.
8918 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8919 struct rte_eth_hash_global_conf *g_cfg)
8921 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8922 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8926 uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
8928 if (pf->support_multi_driver) {
8929 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
8933 /* Check the input parameters */
8934 ret = i40e_hash_global_config_check(adapter, g_cfg);
8939 * As i40e supports less than 64 flow types, only first 64 bits need to
8942 for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
8943 if (mask0 & (1UL << i)) {
8944 reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
8945 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8947 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8948 j < I40E_FILTER_PCTYPE_MAX; j++) {
8949 if (adapter->pctypes_tbl[i] & (1ULL << j))
8950 i40e_write_global_rx_ctl(hw,
8957 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8958 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8960 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8962 "Hash function already set to Toeplitz");
8965 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8966 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8968 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8970 "Hash function already set to Simple XOR");
8973 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8975 /* Use the default, and keep it as it is */
8978 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
8981 I40E_WRITE_FLUSH(hw);
8987 * Valid input sets for hash and flow director filters per PCTYPE
8990 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8991 enum rte_filter_type filter)
8995 static const uint64_t valid_hash_inset_table[] = {
8996 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8997 I40E_INSET_DMAC | I40E_INSET_SMAC |
8998 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8999 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
9000 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
9001 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9002 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9003 I40E_INSET_FLEX_PAYLOAD,
9004 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9005 I40E_INSET_DMAC | I40E_INSET_SMAC |
9006 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9007 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9008 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9009 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9010 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9011 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9012 I40E_INSET_FLEX_PAYLOAD,
9013 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9014 I40E_INSET_DMAC | I40E_INSET_SMAC |
9015 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9016 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9017 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9018 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9019 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9020 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9021 I40E_INSET_FLEX_PAYLOAD,
9022 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9023 I40E_INSET_DMAC | I40E_INSET_SMAC |
9024 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9025 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9026 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9027 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9028 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9029 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9030 I40E_INSET_FLEX_PAYLOAD,
9031 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9032 I40E_INSET_DMAC | I40E_INSET_SMAC |
9033 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9034 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9035 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9036 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9037 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9038 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9039 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9040 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9041 I40E_INSET_DMAC | I40E_INSET_SMAC |
9042 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9043 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9044 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9045 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9046 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9047 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9048 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9049 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9050 I40E_INSET_DMAC | I40E_INSET_SMAC |
9051 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9052 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9053 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9054 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9055 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9056 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9057 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
9058 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9059 I40E_INSET_DMAC | I40E_INSET_SMAC |
9060 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9061 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9062 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9063 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9064 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9065 I40E_INSET_FLEX_PAYLOAD,
9066 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9067 I40E_INSET_DMAC | I40E_INSET_SMAC |
9068 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9069 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9070 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9071 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
9072 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
9073 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
9074 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9075 I40E_INSET_DMAC | I40E_INSET_SMAC |
9076 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9077 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9078 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9079 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9080 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9081 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
9082 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9083 I40E_INSET_DMAC | I40E_INSET_SMAC |
9084 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9085 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9086 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9087 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9088 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9089 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9090 I40E_INSET_FLEX_PAYLOAD,
9091 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9092 I40E_INSET_DMAC | I40E_INSET_SMAC |
9093 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9094 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9095 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9096 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9097 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9098 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9099 I40E_INSET_FLEX_PAYLOAD,
9100 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9101 I40E_INSET_DMAC | I40E_INSET_SMAC |
9102 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9103 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9104 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9105 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9106 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9107 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9108 I40E_INSET_FLEX_PAYLOAD,
9109 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9110 I40E_INSET_DMAC | I40E_INSET_SMAC |
9111 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9112 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9113 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9114 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9115 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9116 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9117 I40E_INSET_FLEX_PAYLOAD,
9118 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9119 I40E_INSET_DMAC | I40E_INSET_SMAC |
9120 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9121 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9122 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9123 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9124 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9125 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9126 I40E_INSET_FLEX_PAYLOAD,
9127 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9128 I40E_INSET_DMAC | I40E_INSET_SMAC |
9129 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9130 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9131 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9132 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9133 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9134 I40E_INSET_FLEX_PAYLOAD,
9135 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9136 I40E_INSET_DMAC | I40E_INSET_SMAC |
9137 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9138 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9139 I40E_INSET_FLEX_PAYLOAD,
9143 * Flow director supports only fields defined in
9144 * union rte_eth_fdir_flow.
9146 static const uint64_t valid_fdir_inset_table[] = {
9147 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9148 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9149 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9150 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9151 I40E_INSET_IPV4_TTL,
9152 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9153 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9154 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9155 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9156 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9157 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9158 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9159 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9160 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9161 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9162 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9163 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9164 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9165 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9166 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9167 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9168 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9169 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9170 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9171 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9172 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9173 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9174 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9175 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9176 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9177 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9178 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9179 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9180 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9181 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9183 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9184 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9185 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9186 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9187 I40E_INSET_IPV4_TTL,
9188 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9189 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9190 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9191 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9192 I40E_INSET_IPV6_HOP_LIMIT,
9193 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9194 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9195 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9196 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9197 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9198 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9199 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9200 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9201 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9202 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9203 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9204 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9205 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9206 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9207 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9208 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9209 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9210 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9211 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9212 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9213 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9214 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9215 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9216 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9217 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9218 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9219 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9220 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9221 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9222 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9224 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9225 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9226 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9227 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9228 I40E_INSET_IPV6_HOP_LIMIT,
9229 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9230 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9231 I40E_INSET_LAST_ETHER_TYPE,
9234 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9236 if (filter == RTE_ETH_FILTER_HASH)
9237 valid = valid_hash_inset_table[pctype];
9239 valid = valid_fdir_inset_table[pctype];
9245 * Validate if the input set is allowed for a specific PCTYPE
9248 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9249 enum rte_filter_type filter, uint64_t inset)
9253 valid = i40e_get_valid_input_set(pctype, filter);
9254 if (inset & (~valid))
9260 /* default input set fields combination per pctype */
9262 i40e_get_default_input_set(uint16_t pctype)
9264 static const uint64_t default_inset_table[] = {
9265 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9266 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9267 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9268 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9269 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9270 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9271 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9272 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9273 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9274 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9275 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9276 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9277 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9278 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9279 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9280 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9281 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9282 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9283 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9284 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9286 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9287 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9288 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9289 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9290 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9291 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9292 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9293 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9294 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9295 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9296 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9297 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9298 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9299 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9300 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9301 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9302 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9303 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9304 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9305 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9306 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9307 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9309 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9310 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9311 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9312 I40E_INSET_LAST_ETHER_TYPE,
9315 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9318 return default_inset_table[pctype];
9322 * Parse the input set from index to logical bit masks
9325 i40e_parse_input_set(uint64_t *inset,
9326 enum i40e_filter_pctype pctype,
9327 enum rte_eth_input_set_field *field,
9333 static const struct {
9334 enum rte_eth_input_set_field field;
9336 } inset_convert_table[] = {
9337 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9338 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9339 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9340 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9341 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9342 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9343 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9344 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9345 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9346 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9347 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9348 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9349 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9350 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9351 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9352 I40E_INSET_IPV6_NEXT_HDR},
9353 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9354 I40E_INSET_IPV6_HOP_LIMIT},
9355 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9356 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9357 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9358 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9359 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9360 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9361 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9362 I40E_INSET_SCTP_VT},
9363 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9364 I40E_INSET_TUNNEL_DMAC},
9365 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9366 I40E_INSET_VLAN_TUNNEL},
9367 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9368 I40E_INSET_TUNNEL_ID},
9369 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9370 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9371 I40E_INSET_FLEX_PAYLOAD_W1},
9372 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9373 I40E_INSET_FLEX_PAYLOAD_W2},
9374 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9375 I40E_INSET_FLEX_PAYLOAD_W3},
9376 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9377 I40E_INSET_FLEX_PAYLOAD_W4},
9378 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9379 I40E_INSET_FLEX_PAYLOAD_W5},
9380 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9381 I40E_INSET_FLEX_PAYLOAD_W6},
9382 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9383 I40E_INSET_FLEX_PAYLOAD_W7},
9384 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9385 I40E_INSET_FLEX_PAYLOAD_W8},
9388 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9391 /* Only one item allowed for default or all */
9393 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9394 *inset = i40e_get_default_input_set(pctype);
9396 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9397 *inset = I40E_INSET_NONE;
9402 for (i = 0, *inset = 0; i < size; i++) {
9403 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9404 if (field[i] == inset_convert_table[j].field) {
9405 *inset |= inset_convert_table[j].inset;
9410 /* It contains unsupported input set, return immediately */
9411 if (j == RTE_DIM(inset_convert_table))
9419 * Translate the input set from bit masks to register aware bit masks
9423 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9433 static const struct inset_map inset_map_common[] = {
9434 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9435 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9436 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9437 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9438 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9439 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9440 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9441 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9442 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9443 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9444 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9445 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9446 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9447 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9448 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9449 {I40E_INSET_TUNNEL_DMAC,
9450 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9451 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9452 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9453 {I40E_INSET_TUNNEL_SRC_PORT,
9454 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9455 {I40E_INSET_TUNNEL_DST_PORT,
9456 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9457 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9458 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9459 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9460 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9461 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9462 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9463 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9464 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9465 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9468 /* some different registers map in x722*/
9469 static const struct inset_map inset_map_diff_x722[] = {
9470 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9471 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9472 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9473 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9476 static const struct inset_map inset_map_diff_not_x722[] = {
9477 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9478 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9479 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9480 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9486 /* Translate input set to register aware inset */
9487 if (type == I40E_MAC_X722) {
9488 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9489 if (input & inset_map_diff_x722[i].inset)
9490 val |= inset_map_diff_x722[i].inset_reg;
9493 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9494 if (input & inset_map_diff_not_x722[i].inset)
9495 val |= inset_map_diff_not_x722[i].inset_reg;
9499 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9500 if (input & inset_map_common[i].inset)
9501 val |= inset_map_common[i].inset_reg;
9508 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9511 uint64_t inset_need_mask = inset;
9513 static const struct {
9516 } inset_mask_map[] = {
9517 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9518 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9519 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9520 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9521 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9522 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9523 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9524 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9527 if (!inset || !mask || !nb_elem)
9530 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9531 /* Clear the inset bit, if no MASK is required,
9532 * for example proto + ttl
9534 if ((inset & inset_mask_map[i].inset) ==
9535 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9536 inset_need_mask &= ~inset_mask_map[i].inset;
9537 if (!inset_need_mask)
9540 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9541 if ((inset_need_mask & inset_mask_map[i].inset) ==
9542 inset_mask_map[i].inset) {
9543 if (idx >= nb_elem) {
9544 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9547 mask[idx] = inset_mask_map[i].mask;
9556 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9558 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9560 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9562 i40e_write_rx_ctl(hw, addr, val);
9563 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9564 (uint32_t)i40e_read_rx_ctl(hw, addr));
9568 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9570 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9571 struct rte_eth_dev *dev;
9573 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
9575 i40e_write_rx_ctl(hw, addr, val);
9576 PMD_DRV_LOG(WARNING,
9577 "i40e device %s changed global register [0x%08x]."
9578 " original: 0x%08x, new: 0x%08x",
9579 dev->device->name, addr, reg,
9580 (uint32_t)i40e_read_rx_ctl(hw, addr));
9585 i40e_filter_input_set_init(struct i40e_pf *pf)
9587 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9588 enum i40e_filter_pctype pctype;
9589 uint64_t input_set, inset_reg;
9590 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9594 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9595 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9596 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9598 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9601 input_set = i40e_get_default_input_set(pctype);
9603 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9604 I40E_INSET_MASK_NUM_REG);
9607 if (pf->support_multi_driver && num > 0) {
9608 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9611 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9614 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9615 (uint32_t)(inset_reg & UINT32_MAX));
9616 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9617 (uint32_t)((inset_reg >>
9618 I40E_32_BIT_WIDTH) & UINT32_MAX));
9619 if (!pf->support_multi_driver) {
9620 i40e_check_write_global_reg(hw,
9621 I40E_GLQF_HASH_INSET(0, pctype),
9622 (uint32_t)(inset_reg & UINT32_MAX));
9623 i40e_check_write_global_reg(hw,
9624 I40E_GLQF_HASH_INSET(1, pctype),
9625 (uint32_t)((inset_reg >>
9626 I40E_32_BIT_WIDTH) & UINT32_MAX));
9628 for (i = 0; i < num; i++) {
9629 i40e_check_write_global_reg(hw,
9630 I40E_GLQF_FD_MSK(i, pctype),
9632 i40e_check_write_global_reg(hw,
9633 I40E_GLQF_HASH_MSK(i, pctype),
9636 /*clear unused mask registers of the pctype */
9637 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9638 i40e_check_write_global_reg(hw,
9639 I40E_GLQF_FD_MSK(i, pctype),
9641 i40e_check_write_global_reg(hw,
9642 I40E_GLQF_HASH_MSK(i, pctype),
9646 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9648 I40E_WRITE_FLUSH(hw);
9650 /* store the default input set */
9651 if (!pf->support_multi_driver)
9652 pf->hash_input_set[pctype] = input_set;
9653 pf->fdir.input_set[pctype] = input_set;
9658 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9659 struct rte_eth_input_set_conf *conf)
9661 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9662 enum i40e_filter_pctype pctype;
9663 uint64_t input_set, inset_reg = 0;
9664 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9668 PMD_DRV_LOG(ERR, "Invalid pointer");
9671 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9672 conf->op != RTE_ETH_INPUT_SET_ADD) {
9673 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9677 if (pf->support_multi_driver) {
9678 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9682 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9683 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9684 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9688 if (hw->mac.type == I40E_MAC_X722) {
9689 /* get translated pctype value in fd pctype register */
9690 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9691 I40E_GLQF_FD_PCTYPES((int)pctype));
9694 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9697 PMD_DRV_LOG(ERR, "Failed to parse input set");
9701 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9702 /* get inset value in register */
9703 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9704 inset_reg <<= I40E_32_BIT_WIDTH;
9705 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9706 input_set |= pf->hash_input_set[pctype];
9708 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9709 I40E_INSET_MASK_NUM_REG);
9713 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9715 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9716 (uint32_t)(inset_reg & UINT32_MAX));
9717 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9718 (uint32_t)((inset_reg >>
9719 I40E_32_BIT_WIDTH) & UINT32_MAX));
9721 for (i = 0; i < num; i++)
9722 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9724 /*clear unused mask registers of the pctype */
9725 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9726 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9728 I40E_WRITE_FLUSH(hw);
9730 pf->hash_input_set[pctype] = input_set;
9735 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9736 struct rte_eth_input_set_conf *conf)
9738 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9739 enum i40e_filter_pctype pctype;
9740 uint64_t input_set, inset_reg = 0;
9741 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9745 PMD_DRV_LOG(ERR, "Invalid pointer");
9748 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9749 conf->op != RTE_ETH_INPUT_SET_ADD) {
9750 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9754 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9756 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9757 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9761 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9764 PMD_DRV_LOG(ERR, "Failed to parse input set");
9768 /* get inset value in register */
9769 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9770 inset_reg <<= I40E_32_BIT_WIDTH;
9771 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9773 /* Can not change the inset reg for flex payload for fdir,
9774 * it is done by writing I40E_PRTQF_FD_FLXINSET
9775 * in i40e_set_flex_mask_on_pctype.
9777 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9778 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9780 input_set |= pf->fdir.input_set[pctype];
9781 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9782 I40E_INSET_MASK_NUM_REG);
9785 if (pf->support_multi_driver && num > 0) {
9786 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9790 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9792 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9793 (uint32_t)(inset_reg & UINT32_MAX));
9794 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9795 (uint32_t)((inset_reg >>
9796 I40E_32_BIT_WIDTH) & UINT32_MAX));
9798 if (!pf->support_multi_driver) {
9799 for (i = 0; i < num; i++)
9800 i40e_check_write_global_reg(hw,
9801 I40E_GLQF_FD_MSK(i, pctype),
9803 /*clear unused mask registers of the pctype */
9804 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9805 i40e_check_write_global_reg(hw,
9806 I40E_GLQF_FD_MSK(i, pctype),
9809 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9811 I40E_WRITE_FLUSH(hw);
9813 pf->fdir.input_set[pctype] = input_set;
9818 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9823 PMD_DRV_LOG(ERR, "Invalid pointer");
9827 switch (info->info_type) {
9828 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9829 i40e_get_symmetric_hash_enable_per_port(hw,
9830 &(info->info.enable));
9832 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9833 ret = i40e_get_hash_filter_global_config(hw,
9834 &(info->info.global_conf));
9837 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9847 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9852 PMD_DRV_LOG(ERR, "Invalid pointer");
9856 switch (info->info_type) {
9857 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9858 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9860 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9861 ret = i40e_set_hash_filter_global_config(hw,
9862 &(info->info.global_conf));
9864 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9865 ret = i40e_hash_filter_inset_select(hw,
9866 &(info->info.input_set_conf));
9870 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9879 /* Operations for hash function */
9881 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9882 enum rte_filter_op filter_op,
9885 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9888 switch (filter_op) {
9889 case RTE_ETH_FILTER_NOP:
9891 case RTE_ETH_FILTER_GET:
9892 ret = i40e_hash_filter_get(hw,
9893 (struct rte_eth_hash_filter_info *)arg);
9895 case RTE_ETH_FILTER_SET:
9896 ret = i40e_hash_filter_set(hw,
9897 (struct rte_eth_hash_filter_info *)arg);
9900 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9909 /* Convert ethertype filter structure */
9911 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9912 struct i40e_ethertype_filter *filter)
9914 rte_memcpy(&filter->input.mac_addr, &input->mac_addr,
9915 RTE_ETHER_ADDR_LEN);
9916 filter->input.ether_type = input->ether_type;
9917 filter->flags = input->flags;
9918 filter->queue = input->queue;
9923 /* Check if there exists the ehtertype filter */
9924 struct i40e_ethertype_filter *
9925 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9926 const struct i40e_ethertype_filter_input *input)
9930 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9934 return ethertype_rule->hash_map[ret];
9937 /* Add ethertype filter in SW list */
9939 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9940 struct i40e_ethertype_filter *filter)
9942 struct i40e_ethertype_rule *rule = &pf->ethertype;
9945 ret = rte_hash_add_key(rule->hash_table, &filter->input);
9948 "Failed to insert ethertype filter"
9949 " to hash table %d!",
9953 rule->hash_map[ret] = filter;
9955 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9960 /* Delete ethertype filter in SW list */
9962 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9963 struct i40e_ethertype_filter_input *input)
9965 struct i40e_ethertype_rule *rule = &pf->ethertype;
9966 struct i40e_ethertype_filter *filter;
9969 ret = rte_hash_del_key(rule->hash_table, input);
9972 "Failed to delete ethertype filter"
9973 " to hash table %d!",
9977 filter = rule->hash_map[ret];
9978 rule->hash_map[ret] = NULL;
9980 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9987 * Configure ethertype filter, which can director packet by filtering
9988 * with mac address and ether_type or only ether_type
9991 i40e_ethertype_filter_set(struct i40e_pf *pf,
9992 struct rte_eth_ethertype_filter *filter,
9995 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9996 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9997 struct i40e_ethertype_filter *ethertype_filter, *node;
9998 struct i40e_ethertype_filter check_filter;
9999 struct i40e_control_filter_stats stats;
10000 uint16_t flags = 0;
10003 if (filter->queue >= pf->dev_data->nb_rx_queues) {
10004 PMD_DRV_LOG(ERR, "Invalid queue ID");
10007 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
10008 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
10010 "unsupported ether_type(0x%04x) in control packet filter.",
10011 filter->ether_type);
10014 if (filter->ether_type == RTE_ETHER_TYPE_VLAN)
10015 PMD_DRV_LOG(WARNING,
10016 "filter vlan ether_type in first tag is not supported.");
10018 /* Check if there is the filter in SW list */
10019 memset(&check_filter, 0, sizeof(check_filter));
10020 i40e_ethertype_filter_convert(filter, &check_filter);
10021 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
10022 &check_filter.input);
10024 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
10028 if (!add && !node) {
10029 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
10033 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
10034 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10035 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
10036 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10037 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10039 memset(&stats, 0, sizeof(stats));
10040 ret = i40e_aq_add_rem_control_packet_filter(hw,
10041 filter->mac_addr.addr_bytes,
10042 filter->ether_type, flags,
10043 pf->main_vsi->seid,
10044 filter->queue, add, &stats, NULL);
10047 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
10048 ret, stats.mac_etype_used, stats.etype_used,
10049 stats.mac_etype_free, stats.etype_free);
10053 /* Add or delete a filter in SW list */
10055 ethertype_filter = rte_zmalloc("ethertype_filter",
10056 sizeof(*ethertype_filter), 0);
10057 if (ethertype_filter == NULL) {
10058 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
10062 rte_memcpy(ethertype_filter, &check_filter,
10063 sizeof(check_filter));
10064 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
10066 rte_free(ethertype_filter);
10068 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
10075 * Handle operations for ethertype filter.
10078 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
10079 enum rte_filter_op filter_op,
10082 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10085 if (filter_op == RTE_ETH_FILTER_NOP)
10089 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
10094 switch (filter_op) {
10095 case RTE_ETH_FILTER_ADD:
10096 ret = i40e_ethertype_filter_set(pf,
10097 (struct rte_eth_ethertype_filter *)arg,
10100 case RTE_ETH_FILTER_DELETE:
10101 ret = i40e_ethertype_filter_set(pf,
10102 (struct rte_eth_ethertype_filter *)arg,
10106 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
10114 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
10115 enum rte_filter_type filter_type,
10116 enum rte_filter_op filter_op,
10124 switch (filter_type) {
10125 case RTE_ETH_FILTER_NONE:
10126 /* For global configuration */
10127 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
10129 case RTE_ETH_FILTER_HASH:
10130 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
10132 case RTE_ETH_FILTER_MACVLAN:
10133 ret = i40e_mac_filter_handle(dev, filter_op, arg);
10135 case RTE_ETH_FILTER_ETHERTYPE:
10136 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
10138 case RTE_ETH_FILTER_TUNNEL:
10139 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
10141 case RTE_ETH_FILTER_FDIR:
10142 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
10144 case RTE_ETH_FILTER_GENERIC:
10145 if (filter_op != RTE_ETH_FILTER_GET)
10147 *(const void **)arg = &i40e_flow_ops;
10150 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
10160 * Check and enable Extended Tag.
10161 * Enabling Extended Tag is important for 40G performance.
10164 i40e_enable_extended_tag(struct rte_eth_dev *dev)
10166 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10170 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10173 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10177 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
10178 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
10183 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10186 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10190 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
10191 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
10194 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
10195 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
10198 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
10205 * As some registers wouldn't be reset unless a global hardware reset,
10206 * hardware initialization is needed to put those registers into an
10207 * expected initial state.
10210 i40e_hw_init(struct rte_eth_dev *dev)
10212 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10214 i40e_enable_extended_tag(dev);
10216 /* clear the PF Queue Filter control register */
10217 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
10219 /* Disable symmetric hash per port */
10220 i40e_set_symmetric_hash_enable_per_port(hw, 0);
10224 * For X722 it is possible to have multiple pctypes mapped to the same flowtype
10225 * however this function will return only one highest pctype index,
10226 * which is not quite correct. This is known problem of i40e driver
10227 * and needs to be fixed later.
10229 enum i40e_filter_pctype
10230 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
10233 uint64_t pctype_mask;
10235 if (flow_type < I40E_FLOW_TYPE_MAX) {
10236 pctype_mask = adapter->pctypes_tbl[flow_type];
10237 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
10238 if (pctype_mask & (1ULL << i))
10239 return (enum i40e_filter_pctype)i;
10242 return I40E_FILTER_PCTYPE_INVALID;
10246 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
10247 enum i40e_filter_pctype pctype)
10250 uint64_t pctype_mask = 1ULL << pctype;
10252 for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
10254 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
10258 return RTE_ETH_FLOW_UNKNOWN;
10262 * On X710, performance number is far from the expectation on recent firmware
10263 * versions; on XL710, performance number is also far from the expectation on
10264 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10265 * mode is enabled and port MAC address is equal to the packet destination MAC
10266 * address. The fix for this issue may not be integrated in the following
10267 * firmware version. So the workaround in software driver is needed. It needs
10268 * to modify the initial values of 3 internal only registers for both X710 and
10269 * XL710. Note that the values for X710 or XL710 could be different, and the
10270 * workaround can be removed when it is fixed in firmware in the future.
10273 /* For both X710 and XL710 */
10274 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1 0x10000200
10275 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x203F0200
10276 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
10278 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10279 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
10282 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10283 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10286 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
10288 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
10289 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
10292 * GL_SWR_PM_UP_THR:
10293 * The value is not impacted from the link speed, its value is set according
10294 * to the total number of ports for a better pipe-monitor configuration.
10297 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10299 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10300 .device_id = (dev), \
10301 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10303 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10304 .device_id = (dev), \
10305 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10307 static const struct {
10308 uint16_t device_id;
10310 } swr_pm_table[] = {
10311 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10312 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10313 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10314 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10316 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10317 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10318 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10319 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10320 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10321 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10322 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10326 if (value == NULL) {
10327 PMD_DRV_LOG(ERR, "value is NULL");
10331 for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10332 if (hw->device_id == swr_pm_table[i].device_id) {
10333 *value = swr_pm_table[i].val;
10335 PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10337 hw->device_id, *value);
10346 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10348 enum i40e_status_code status;
10349 struct i40e_aq_get_phy_abilities_resp phy_ab;
10350 int ret = -ENOTSUP;
10353 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10357 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10360 rte_delay_us(100000);
10362 status = i40e_aq_get_phy_capabilities(hw, false,
10363 true, &phy_ab, NULL);
10371 i40e_configure_registers(struct i40e_hw *hw)
10377 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10378 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10379 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10385 for (i = 0; i < RTE_DIM(reg_table); i++) {
10386 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10387 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10389 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10390 else /* For X710/XL710/XXV710 */
10391 if (hw->aq.fw_maj_ver < 6)
10393 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10396 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10399 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10400 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10402 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10403 else /* For X710/XL710/XXV710 */
10405 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10408 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10411 if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10412 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10413 "GL_SWR_PM_UP_THR value fixup",
10418 reg_table[i].val = cfg_val;
10421 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10424 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10425 reg_table[i].addr);
10428 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10429 reg_table[i].addr, reg);
10430 if (reg == reg_table[i].val)
10433 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10434 reg_table[i].val, NULL);
10437 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10438 reg_table[i].val, reg_table[i].addr);
10441 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10442 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10446 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
10447 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
10448 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
10449 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10451 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10456 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10457 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10461 /* Configure for double VLAN RX stripping */
10462 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10463 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10464 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10465 ret = i40e_aq_debug_write_register(hw,
10466 I40E_VSI_TSR(vsi->vsi_id),
10469 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10471 return I40E_ERR_CONFIG;
10475 /* Configure for double VLAN TX insertion */
10476 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10477 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10478 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10479 ret = i40e_aq_debug_write_register(hw,
10480 I40E_VSI_L2TAGSTXVALID(
10481 vsi->vsi_id), reg, NULL);
10484 "Failed to update VSI_L2TAGSTXVALID[%d]",
10486 return I40E_ERR_CONFIG;
10494 * i40e_aq_add_mirror_rule
10495 * @hw: pointer to the hardware structure
10496 * @seid: VEB seid to add mirror rule to
10497 * @dst_id: destination vsi seid
10498 * @entries: Buffer which contains the entities to be mirrored
10499 * @count: number of entities contained in the buffer
10500 * @rule_id:the rule_id of the rule to be added
10502 * Add a mirror rule for a given veb.
10505 static enum i40e_status_code
10506 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10507 uint16_t seid, uint16_t dst_id,
10508 uint16_t rule_type, uint16_t *entries,
10509 uint16_t count, uint16_t *rule_id)
10511 struct i40e_aq_desc desc;
10512 struct i40e_aqc_add_delete_mirror_rule cmd;
10513 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10514 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10517 enum i40e_status_code status;
10519 i40e_fill_default_direct_cmd_desc(&desc,
10520 i40e_aqc_opc_add_mirror_rule);
10521 memset(&cmd, 0, sizeof(cmd));
10523 buff_len = sizeof(uint16_t) * count;
10524 desc.datalen = rte_cpu_to_le_16(buff_len);
10526 desc.flags |= rte_cpu_to_le_16(
10527 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10528 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10529 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10530 cmd.num_entries = rte_cpu_to_le_16(count);
10531 cmd.seid = rte_cpu_to_le_16(seid);
10532 cmd.destination = rte_cpu_to_le_16(dst_id);
10534 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10535 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10537 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10538 hw->aq.asq_last_status, resp->rule_id,
10539 resp->mirror_rules_used, resp->mirror_rules_free);
10540 *rule_id = rte_le_to_cpu_16(resp->rule_id);
10546 * i40e_aq_del_mirror_rule
10547 * @hw: pointer to the hardware structure
10548 * @seid: VEB seid to add mirror rule to
10549 * @entries: Buffer which contains the entities to be mirrored
10550 * @count: number of entities contained in the buffer
10551 * @rule_id:the rule_id of the rule to be delete
10553 * Delete a mirror rule for a given veb.
10556 static enum i40e_status_code
10557 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10558 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10559 uint16_t count, uint16_t rule_id)
10561 struct i40e_aq_desc desc;
10562 struct i40e_aqc_add_delete_mirror_rule cmd;
10563 uint16_t buff_len = 0;
10564 enum i40e_status_code status;
10567 i40e_fill_default_direct_cmd_desc(&desc,
10568 i40e_aqc_opc_delete_mirror_rule);
10569 memset(&cmd, 0, sizeof(cmd));
10570 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10571 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10573 cmd.num_entries = count;
10574 buff_len = sizeof(uint16_t) * count;
10575 desc.datalen = rte_cpu_to_le_16(buff_len);
10576 buff = (void *)entries;
10578 /* rule id is filled in destination field for deleting mirror rule */
10579 cmd.destination = rte_cpu_to_le_16(rule_id);
10581 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10582 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10583 cmd.seid = rte_cpu_to_le_16(seid);
10585 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10586 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10592 * i40e_mirror_rule_set
10593 * @dev: pointer to the hardware structure
10594 * @mirror_conf: mirror rule info
10595 * @sw_id: mirror rule's sw_id
10596 * @on: enable/disable
10598 * set a mirror rule.
10602 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10603 struct rte_eth_mirror_conf *mirror_conf,
10604 uint8_t sw_id, uint8_t on)
10606 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10607 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10608 struct i40e_mirror_rule *it, *mirr_rule = NULL;
10609 struct i40e_mirror_rule *parent = NULL;
10610 uint16_t seid, dst_seid, rule_id;
10614 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10616 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10618 "mirror rule can not be configured without veb or vfs.");
10621 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10622 PMD_DRV_LOG(ERR, "mirror table is full.");
10625 if (mirror_conf->dst_pool > pf->vf_num) {
10626 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10627 mirror_conf->dst_pool);
10631 seid = pf->main_vsi->veb->seid;
10633 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10634 if (sw_id <= it->index) {
10640 if (mirr_rule && sw_id == mirr_rule->index) {
10642 PMD_DRV_LOG(ERR, "mirror rule exists.");
10645 ret = i40e_aq_del_mirror_rule(hw, seid,
10646 mirr_rule->rule_type,
10647 mirr_rule->entries,
10648 mirr_rule->num_entries, mirr_rule->id);
10651 "failed to remove mirror rule: ret = %d, aq_err = %d.",
10652 ret, hw->aq.asq_last_status);
10655 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10656 rte_free(mirr_rule);
10657 pf->nb_mirror_rule--;
10661 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10665 mirr_rule = rte_zmalloc("i40e_mirror_rule",
10666 sizeof(struct i40e_mirror_rule) , 0);
10668 PMD_DRV_LOG(ERR, "failed to allocate memory");
10669 return I40E_ERR_NO_MEMORY;
10671 switch (mirror_conf->rule_type) {
10672 case ETH_MIRROR_VLAN:
10673 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10674 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10675 mirr_rule->entries[j] =
10676 mirror_conf->vlan.vlan_id[i];
10681 PMD_DRV_LOG(ERR, "vlan is not specified.");
10682 rte_free(mirr_rule);
10685 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10687 case ETH_MIRROR_VIRTUAL_POOL_UP:
10688 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10689 /* check if the specified pool bit is out of range */
10690 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10691 PMD_DRV_LOG(ERR, "pool mask is out of range.");
10692 rte_free(mirr_rule);
10695 for (i = 0, j = 0; i < pf->vf_num; i++) {
10696 if (mirror_conf->pool_mask & (1ULL << i)) {
10697 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10701 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10702 /* add pf vsi to entries */
10703 mirr_rule->entries[j] = pf->main_vsi_seid;
10707 PMD_DRV_LOG(ERR, "pool is not specified.");
10708 rte_free(mirr_rule);
10711 /* egress and ingress in aq commands means from switch but not port */
10712 mirr_rule->rule_type =
10713 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10714 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10715 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10717 case ETH_MIRROR_UPLINK_PORT:
10718 /* egress and ingress in aq commands means from switch but not port*/
10719 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10721 case ETH_MIRROR_DOWNLINK_PORT:
10722 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10725 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10726 mirror_conf->rule_type);
10727 rte_free(mirr_rule);
10731 /* If the dst_pool is equal to vf_num, consider it as PF */
10732 if (mirror_conf->dst_pool == pf->vf_num)
10733 dst_seid = pf->main_vsi_seid;
10735 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10737 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10738 mirr_rule->rule_type, mirr_rule->entries,
10742 "failed to add mirror rule: ret = %d, aq_err = %d.",
10743 ret, hw->aq.asq_last_status);
10744 rte_free(mirr_rule);
10748 mirr_rule->index = sw_id;
10749 mirr_rule->num_entries = j;
10750 mirr_rule->id = rule_id;
10751 mirr_rule->dst_vsi_seid = dst_seid;
10754 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10756 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10758 pf->nb_mirror_rule++;
10763 * i40e_mirror_rule_reset
10764 * @dev: pointer to the device
10765 * @sw_id: mirror rule's sw_id
10767 * reset a mirror rule.
10771 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10773 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10774 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10775 struct i40e_mirror_rule *it, *mirr_rule = NULL;
10779 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10781 seid = pf->main_vsi->veb->seid;
10783 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10784 if (sw_id == it->index) {
10790 ret = i40e_aq_del_mirror_rule(hw, seid,
10791 mirr_rule->rule_type,
10792 mirr_rule->entries,
10793 mirr_rule->num_entries, mirr_rule->id);
10796 "failed to remove mirror rule: status = %d, aq_err = %d.",
10797 ret, hw->aq.asq_last_status);
10800 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10801 rte_free(mirr_rule);
10802 pf->nb_mirror_rule--;
10804 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10811 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10813 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10814 uint64_t systim_cycles;
10816 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10817 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10820 return systim_cycles;
10824 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10826 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10827 uint64_t rx_tstamp;
10829 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10830 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10837 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10839 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10840 uint64_t tx_tstamp;
10842 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10843 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10850 i40e_start_timecounters(struct rte_eth_dev *dev)
10852 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10853 struct i40e_adapter *adapter = dev->data->dev_private;
10854 struct rte_eth_link link;
10855 uint32_t tsync_inc_l;
10856 uint32_t tsync_inc_h;
10858 /* Get current link speed. */
10859 i40e_dev_link_update(dev, 1);
10860 rte_eth_linkstatus_get(dev, &link);
10862 switch (link.link_speed) {
10863 case ETH_SPEED_NUM_40G:
10864 case ETH_SPEED_NUM_25G:
10865 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10866 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10868 case ETH_SPEED_NUM_10G:
10869 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10870 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10872 case ETH_SPEED_NUM_1G:
10873 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10874 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10881 /* Set the timesync increment value. */
10882 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10883 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10885 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10886 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10887 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10889 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10890 adapter->systime_tc.cc_shift = 0;
10891 adapter->systime_tc.nsec_mask = 0;
10893 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10894 adapter->rx_tstamp_tc.cc_shift = 0;
10895 adapter->rx_tstamp_tc.nsec_mask = 0;
10897 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10898 adapter->tx_tstamp_tc.cc_shift = 0;
10899 adapter->tx_tstamp_tc.nsec_mask = 0;
10903 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10905 struct i40e_adapter *adapter = dev->data->dev_private;
10907 adapter->systime_tc.nsec += delta;
10908 adapter->rx_tstamp_tc.nsec += delta;
10909 adapter->tx_tstamp_tc.nsec += delta;
10915 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10918 struct i40e_adapter *adapter = dev->data->dev_private;
10920 ns = rte_timespec_to_ns(ts);
10922 /* Set the timecounters to a new value. */
10923 adapter->systime_tc.nsec = ns;
10924 adapter->rx_tstamp_tc.nsec = ns;
10925 adapter->tx_tstamp_tc.nsec = ns;
10931 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10933 uint64_t ns, systime_cycles;
10934 struct i40e_adapter *adapter = dev->data->dev_private;
10936 systime_cycles = i40e_read_systime_cyclecounter(dev);
10937 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10938 *ts = rte_ns_to_timespec(ns);
10944 i40e_timesync_enable(struct rte_eth_dev *dev)
10946 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10947 uint32_t tsync_ctl_l;
10948 uint32_t tsync_ctl_h;
10950 /* Stop the timesync system time. */
10951 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10952 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10953 /* Reset the timesync system time value. */
10954 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10955 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10957 i40e_start_timecounters(dev);
10959 /* Clear timesync registers. */
10960 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10961 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10962 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10963 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10964 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10965 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10967 /* Enable timestamping of PTP packets. */
10968 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10969 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10971 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10972 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10973 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10975 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10976 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10982 i40e_timesync_disable(struct rte_eth_dev *dev)
10984 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10985 uint32_t tsync_ctl_l;
10986 uint32_t tsync_ctl_h;
10988 /* Disable timestamping of transmitted PTP packets. */
10989 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10990 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10992 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10993 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10995 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10996 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10998 /* Reset the timesync increment value. */
10999 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
11000 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11006 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
11007 struct timespec *timestamp, uint32_t flags)
11009 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11010 struct i40e_adapter *adapter = dev->data->dev_private;
11011 uint32_t sync_status;
11012 uint32_t index = flags & 0x03;
11013 uint64_t rx_tstamp_cycles;
11016 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
11017 if ((sync_status & (1 << index)) == 0)
11020 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
11021 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
11022 *timestamp = rte_ns_to_timespec(ns);
11028 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
11029 struct timespec *timestamp)
11031 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11032 struct i40e_adapter *adapter = dev->data->dev_private;
11033 uint32_t sync_status;
11034 uint64_t tx_tstamp_cycles;
11037 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11038 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
11041 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
11042 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
11043 *timestamp = rte_ns_to_timespec(ns);
11049 * i40e_parse_dcb_configure - parse dcb configure from user
11050 * @dev: the device being configured
11051 * @dcb_cfg: pointer of the result of parse
11052 * @*tc_map: bit map of enabled traffic classes
11054 * Returns 0 on success, negative value on failure
11057 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
11058 struct i40e_dcbx_config *dcb_cfg,
11061 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
11062 uint8_t i, tc_bw, bw_lf;
11064 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
11066 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
11067 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
11068 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
11072 /* assume each tc has the same bw */
11073 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
11074 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11075 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
11076 /* to ensure the sum of tcbw is equal to 100 */
11077 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
11078 for (i = 0; i < bw_lf; i++)
11079 dcb_cfg->etscfg.tcbwtable[i]++;
11081 /* assume each tc has the same Transmission Selection Algorithm */
11082 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11083 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
11085 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11086 dcb_cfg->etscfg.prioritytable[i] =
11087 dcb_rx_conf->dcb_tc[i];
11089 /* FW needs one App to configure HW */
11090 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
11091 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
11092 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
11093 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
11095 if (dcb_rx_conf->nb_tcs == 0)
11096 *tc_map = 1; /* tc0 only */
11098 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
11100 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
11101 dcb_cfg->pfc.willing = 0;
11102 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
11103 dcb_cfg->pfc.pfcenable = *tc_map;
11109 static enum i40e_status_code
11110 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
11111 struct i40e_aqc_vsi_properties_data *info,
11112 uint8_t enabled_tcmap)
11114 enum i40e_status_code ret;
11115 int i, total_tc = 0;
11116 uint16_t qpnum_per_tc, bsf, qp_idx;
11117 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
11118 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
11119 uint16_t used_queues;
11121 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
11122 if (ret != I40E_SUCCESS)
11125 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11126 if (enabled_tcmap & (1 << i))
11131 vsi->enabled_tc = enabled_tcmap;
11133 /* different VSI has different queues assigned */
11134 if (vsi->type == I40E_VSI_MAIN)
11135 used_queues = dev_data->nb_rx_queues -
11136 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11137 else if (vsi->type == I40E_VSI_VMDQ2)
11138 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11140 PMD_INIT_LOG(ERR, "unsupported VSI type.");
11141 return I40E_ERR_NO_AVAILABLE_VSI;
11144 qpnum_per_tc = used_queues / total_tc;
11145 /* Number of queues per enabled TC */
11146 if (qpnum_per_tc == 0) {
11147 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
11148 return I40E_ERR_INVALID_QP_ID;
11150 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
11151 I40E_MAX_Q_PER_TC);
11152 bsf = rte_bsf32(qpnum_per_tc);
11155 * Configure TC and queue mapping parameters, for enabled TC,
11156 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
11157 * default queue will serve it.
11160 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11161 if (vsi->enabled_tc & (1 << i)) {
11162 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
11163 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
11164 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
11165 qp_idx += qpnum_per_tc;
11167 info->tc_mapping[i] = 0;
11170 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
11171 if (vsi->type == I40E_VSI_SRIOV) {
11172 info->mapping_flags |=
11173 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
11174 for (i = 0; i < vsi->nb_qps; i++)
11175 info->queue_mapping[i] =
11176 rte_cpu_to_le_16(vsi->base_queue + i);
11178 info->mapping_flags |=
11179 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
11180 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
11182 info->valid_sections |=
11183 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
11185 return I40E_SUCCESS;
11189 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
11190 * @veb: VEB to be configured
11191 * @tc_map: enabled TC bitmap
11193 * Returns 0 on success, negative value on failure
11195 static enum i40e_status_code
11196 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
11198 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
11199 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
11200 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
11201 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
11202 enum i40e_status_code ret = I40E_SUCCESS;
11206 /* Check if enabled_tc is same as existing or new TCs */
11207 if (veb->enabled_tc == tc_map)
11210 /* configure tc bandwidth */
11211 memset(&veb_bw, 0, sizeof(veb_bw));
11212 veb_bw.tc_valid_bits = tc_map;
11213 /* Enable ETS TCs with equal BW Share for now across all VSIs */
11214 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11215 if (tc_map & BIT_ULL(i))
11216 veb_bw.tc_bw_share_credits[i] = 1;
11218 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
11222 "AQ command Config switch_comp BW allocation per TC failed = %d",
11223 hw->aq.asq_last_status);
11227 memset(&ets_query, 0, sizeof(ets_query));
11228 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
11230 if (ret != I40E_SUCCESS) {
11232 "Failed to get switch_comp ETS configuration %u",
11233 hw->aq.asq_last_status);
11236 memset(&bw_query, 0, sizeof(bw_query));
11237 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
11239 if (ret != I40E_SUCCESS) {
11241 "Failed to get switch_comp bandwidth configuration %u",
11242 hw->aq.asq_last_status);
11246 /* store and print out BW info */
11247 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
11248 veb->bw_info.bw_max = ets_query.tc_bw_max;
11249 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
11250 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
11251 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
11252 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
11253 I40E_16_BIT_WIDTH);
11254 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11255 veb->bw_info.bw_ets_share_credits[i] =
11256 bw_query.tc_bw_share_credits[i];
11257 veb->bw_info.bw_ets_credits[i] =
11258 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
11259 /* 4 bits per TC, 4th bit is reserved */
11260 veb->bw_info.bw_ets_max[i] =
11261 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
11262 RTE_LEN2MASK(3, uint8_t));
11263 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
11264 veb->bw_info.bw_ets_share_credits[i]);
11265 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11266 veb->bw_info.bw_ets_credits[i]);
11267 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11268 veb->bw_info.bw_ets_max[i]);
11271 veb->enabled_tc = tc_map;
11278 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11279 * @vsi: VSI to be configured
11280 * @tc_map: enabled TC bitmap
11282 * Returns 0 on success, negative value on failure
11284 static enum i40e_status_code
11285 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11287 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11288 struct i40e_vsi_context ctxt;
11289 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11290 enum i40e_status_code ret = I40E_SUCCESS;
11293 /* Check if enabled_tc is same as existing or new TCs */
11294 if (vsi->enabled_tc == tc_map)
11297 /* configure tc bandwidth */
11298 memset(&bw_data, 0, sizeof(bw_data));
11299 bw_data.tc_valid_bits = tc_map;
11300 /* Enable ETS TCs with equal BW Share for now across all VSIs */
11301 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11302 if (tc_map & BIT_ULL(i))
11303 bw_data.tc_bw_credits[i] = 1;
11305 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11308 "AQ command Config VSI BW allocation per TC failed = %d",
11309 hw->aq.asq_last_status);
11312 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11313 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11315 /* Update Queue Pairs Mapping for currently enabled UPs */
11316 ctxt.seid = vsi->seid;
11317 ctxt.pf_num = hw->pf_id;
11319 ctxt.uplink_seid = vsi->uplink_seid;
11320 ctxt.info = vsi->info;
11322 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11326 /* Update the VSI after updating the VSI queue-mapping information */
11327 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11329 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11330 hw->aq.asq_last_status);
11333 /* update the local VSI info with updated queue map */
11334 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11335 sizeof(vsi->info.tc_mapping));
11336 rte_memcpy(&vsi->info.queue_mapping,
11337 &ctxt.info.queue_mapping,
11338 sizeof(vsi->info.queue_mapping));
11339 vsi->info.mapping_flags = ctxt.info.mapping_flags;
11340 vsi->info.valid_sections = 0;
11342 /* query and update current VSI BW information */
11343 ret = i40e_vsi_get_bw_config(vsi);
11346 "Failed updating vsi bw info, err %s aq_err %s",
11347 i40e_stat_str(hw, ret),
11348 i40e_aq_str(hw, hw->aq.asq_last_status));
11352 vsi->enabled_tc = tc_map;
11359 * i40e_dcb_hw_configure - program the dcb setting to hw
11360 * @pf: pf the configuration is taken on
11361 * @new_cfg: new configuration
11362 * @tc_map: enabled TC bitmap
11364 * Returns 0 on success, negative value on failure
11366 static enum i40e_status_code
11367 i40e_dcb_hw_configure(struct i40e_pf *pf,
11368 struct i40e_dcbx_config *new_cfg,
11371 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11372 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11373 struct i40e_vsi *main_vsi = pf->main_vsi;
11374 struct i40e_vsi_list *vsi_list;
11375 enum i40e_status_code ret;
11379 /* Use the FW API if FW > v4.4*/
11380 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11381 (hw->aq.fw_maj_ver >= 5))) {
11383 "FW < v4.4, can not use FW LLDP API to configure DCB");
11384 return I40E_ERR_FIRMWARE_API_VERSION;
11387 /* Check if need reconfiguration */
11388 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11389 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11390 return I40E_SUCCESS;
11393 /* Copy the new config to the current config */
11394 *old_cfg = *new_cfg;
11395 old_cfg->etsrec = old_cfg->etscfg;
11396 ret = i40e_set_dcb_config(hw);
11398 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11399 i40e_stat_str(hw, ret),
11400 i40e_aq_str(hw, hw->aq.asq_last_status));
11403 /* set receive Arbiter to RR mode and ETS scheme by default */
11404 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11405 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11406 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
11407 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11408 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11409 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11410 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11411 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11412 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11413 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11414 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11415 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11416 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11418 /* get local mib to check whether it is configured correctly */
11420 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11421 /* Get Local DCB Config */
11422 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11423 &hw->local_dcbx_config);
11425 /* if Veb is created, need to update TC of it at first */
11426 if (main_vsi->veb) {
11427 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11429 PMD_INIT_LOG(WARNING,
11430 "Failed configuring TC for VEB seid=%d",
11431 main_vsi->veb->seid);
11433 /* Update each VSI */
11434 i40e_vsi_config_tc(main_vsi, tc_map);
11435 if (main_vsi->veb) {
11436 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11437 /* Beside main VSI and VMDQ VSIs, only enable default
11438 * TC for other VSIs
11440 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11441 ret = i40e_vsi_config_tc(vsi_list->vsi,
11444 ret = i40e_vsi_config_tc(vsi_list->vsi,
11445 I40E_DEFAULT_TCMAP);
11447 PMD_INIT_LOG(WARNING,
11448 "Failed configuring TC for VSI seid=%d",
11449 vsi_list->vsi->seid);
11453 return I40E_SUCCESS;
11457 * i40e_dcb_init_configure - initial dcb config
11458 * @dev: device being configured
11459 * @sw_dcb: indicate whether dcb is sw configured or hw offload
11461 * Returns 0 on success, negative value on failure
11464 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11466 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11467 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11470 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11471 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11475 /* DCB initialization:
11476 * Update DCB configuration from the Firmware and configure
11477 * LLDP MIB change event.
11479 if (sw_dcb == TRUE) {
11480 if (i40e_need_stop_lldp(dev)) {
11481 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
11482 if (ret != I40E_SUCCESS)
11483 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
11486 ret = i40e_init_dcb(hw);
11487 /* If lldp agent is stopped, the return value from
11488 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11489 * adminq status. Otherwise, it should return success.
11491 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11492 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11493 memset(&hw->local_dcbx_config, 0,
11494 sizeof(struct i40e_dcbx_config));
11495 /* set dcb default configuration */
11496 hw->local_dcbx_config.etscfg.willing = 0;
11497 hw->local_dcbx_config.etscfg.maxtcs = 0;
11498 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11499 hw->local_dcbx_config.etscfg.tsatable[0] =
11501 /* all UPs mapping to TC0 */
11502 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11503 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11504 hw->local_dcbx_config.etsrec =
11505 hw->local_dcbx_config.etscfg;
11506 hw->local_dcbx_config.pfc.willing = 0;
11507 hw->local_dcbx_config.pfc.pfccap =
11508 I40E_MAX_TRAFFIC_CLASS;
11509 /* FW needs one App to configure HW */
11510 hw->local_dcbx_config.numapps = 1;
11511 hw->local_dcbx_config.app[0].selector =
11512 I40E_APP_SEL_ETHTYPE;
11513 hw->local_dcbx_config.app[0].priority = 3;
11514 hw->local_dcbx_config.app[0].protocolid =
11515 I40E_APP_PROTOID_FCOE;
11516 ret = i40e_set_dcb_config(hw);
11519 "default dcb config fails. err = %d, aq_err = %d.",
11520 ret, hw->aq.asq_last_status);
11525 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11526 ret, hw->aq.asq_last_status);
11530 ret = i40e_aq_start_lldp(hw, NULL);
11531 if (ret != I40E_SUCCESS)
11532 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11534 ret = i40e_init_dcb(hw);
11536 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11538 "HW doesn't support DCBX offload.");
11543 "DCBX configuration failed, err = %d, aq_err = %d.",
11544 ret, hw->aq.asq_last_status);
11552 * i40e_dcb_setup - setup dcb related config
11553 * @dev: device being configured
11555 * Returns 0 on success, negative value on failure
11558 i40e_dcb_setup(struct rte_eth_dev *dev)
11560 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11561 struct i40e_dcbx_config dcb_cfg;
11562 uint8_t tc_map = 0;
11565 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11566 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11570 if (pf->vf_num != 0)
11571 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11573 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11575 PMD_INIT_LOG(ERR, "invalid dcb config");
11578 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11580 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11588 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11589 struct rte_eth_dcb_info *dcb_info)
11591 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11592 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11593 struct i40e_vsi *vsi = pf->main_vsi;
11594 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11595 uint16_t bsf, tc_mapping;
11598 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11599 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11601 dcb_info->nb_tcs = 1;
11602 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11603 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11604 for (i = 0; i < dcb_info->nb_tcs; i++)
11605 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11607 /* get queue mapping if vmdq is disabled */
11608 if (!pf->nb_cfg_vmdq_vsi) {
11609 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11610 if (!(vsi->enabled_tc & (1 << i)))
11612 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11613 dcb_info->tc_queue.tc_rxq[j][i].base =
11614 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11615 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11616 dcb_info->tc_queue.tc_txq[j][i].base =
11617 dcb_info->tc_queue.tc_rxq[j][i].base;
11618 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11619 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11620 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11621 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11622 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11627 /* get queue mapping if vmdq is enabled */
11629 vsi = pf->vmdq[j].vsi;
11630 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11631 if (!(vsi->enabled_tc & (1 << i)))
11633 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11634 dcb_info->tc_queue.tc_rxq[j][i].base =
11635 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11636 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11637 dcb_info->tc_queue.tc_txq[j][i].base =
11638 dcb_info->tc_queue.tc_rxq[j][i].base;
11639 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11640 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11641 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11642 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11643 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11646 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11651 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11653 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11654 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11655 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11656 uint16_t msix_intr;
11658 msix_intr = intr_handle->intr_vec[queue_id];
11659 if (msix_intr == I40E_MISC_VEC_ID)
11660 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11661 I40E_PFINT_DYN_CTL0_INTENA_MASK |
11662 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11663 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11666 I40E_PFINT_DYN_CTLN(msix_intr -
11667 I40E_RX_VEC_START),
11668 I40E_PFINT_DYN_CTLN_INTENA_MASK |
11669 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11670 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11672 I40E_WRITE_FLUSH(hw);
11673 rte_intr_ack(&pci_dev->intr_handle);
11679 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11681 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11682 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11683 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11684 uint16_t msix_intr;
11686 msix_intr = intr_handle->intr_vec[queue_id];
11687 if (msix_intr == I40E_MISC_VEC_ID)
11688 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11689 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11692 I40E_PFINT_DYN_CTLN(msix_intr -
11693 I40E_RX_VEC_START),
11694 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11695 I40E_WRITE_FLUSH(hw);
11701 * This function is used to check if the register is valid.
11702 * Below is the valid registers list for X722 only:
11706 * 0x208e00--0x209000
11707 * 0x20be00--0x20c000
11708 * 0x263c00--0x264000
11709 * 0x265c00--0x266000
11711 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset)
11713 if ((type != I40E_MAC_X722) &&
11714 ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) ||
11715 (reg_offset >= 0x38700 && reg_offset <= 0x38a00) ||
11716 (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) ||
11717 (reg_offset >= 0x208e00 && reg_offset <= 0x209000) ||
11718 (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) ||
11719 (reg_offset >= 0x263c00 && reg_offset <= 0x264000) ||
11720 (reg_offset >= 0x265c00 && reg_offset <= 0x266000)))
11726 static int i40e_get_regs(struct rte_eth_dev *dev,
11727 struct rte_dev_reg_info *regs)
11729 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11730 uint32_t *ptr_data = regs->data;
11731 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11732 const struct i40e_reg_info *reg_info;
11734 if (ptr_data == NULL) {
11735 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11736 regs->width = sizeof(uint32_t);
11740 /* The first few registers have to be read using AQ operations */
11742 while (i40e_regs_adminq[reg_idx].name) {
11743 reg_info = &i40e_regs_adminq[reg_idx++];
11744 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11746 arr_idx2 <= reg_info->count2;
11748 reg_offset = arr_idx * reg_info->stride1 +
11749 arr_idx2 * reg_info->stride2;
11750 reg_offset += reg_info->base_addr;
11751 ptr_data[reg_offset >> 2] =
11752 i40e_read_rx_ctl(hw, reg_offset);
11756 /* The remaining registers can be read using primitives */
11758 while (i40e_regs_others[reg_idx].name) {
11759 reg_info = &i40e_regs_others[reg_idx++];
11760 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11762 arr_idx2 <= reg_info->count2;
11764 reg_offset = arr_idx * reg_info->stride1 +
11765 arr_idx2 * reg_info->stride2;
11766 reg_offset += reg_info->base_addr;
11767 if (!i40e_valid_regs(hw->mac.type, reg_offset))
11768 ptr_data[reg_offset >> 2] = 0;
11770 ptr_data[reg_offset >> 2] =
11771 I40E_READ_REG(hw, reg_offset);
11778 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11780 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11782 /* Convert word count to byte count */
11783 return hw->nvm.sr_size << 1;
11786 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11787 struct rte_dev_eeprom_info *eeprom)
11789 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11790 uint16_t *data = eeprom->data;
11791 uint16_t offset, length, cnt_words;
11794 offset = eeprom->offset >> 1;
11795 length = eeprom->length >> 1;
11796 cnt_words = length;
11798 if (offset > hw->nvm.sr_size ||
11799 offset + length > hw->nvm.sr_size) {
11800 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11804 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11806 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11807 if (ret_code != I40E_SUCCESS || cnt_words != length) {
11808 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11815 static int i40e_get_module_info(struct rte_eth_dev *dev,
11816 struct rte_eth_dev_module_info *modinfo)
11818 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11819 uint32_t sff8472_comp = 0;
11820 uint32_t sff8472_swap = 0;
11821 uint32_t sff8636_rev = 0;
11822 i40e_status status;
11825 /* Check if firmware supports reading module EEPROM. */
11826 if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
11828 "Module EEPROM memory read not supported. "
11829 "Please update the NVM image.\n");
11833 status = i40e_update_link_info(hw);
11837 if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
11839 "Cannot read module EEPROM memory. "
11840 "No module connected.\n");
11844 type = hw->phy.link_info.module_type[0];
11847 case I40E_MODULE_TYPE_SFP:
11848 status = i40e_aq_get_phy_register(hw,
11849 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11850 I40E_I2C_EEPROM_DEV_ADDR, 1,
11851 I40E_MODULE_SFF_8472_COMP,
11852 &sff8472_comp, NULL);
11856 status = i40e_aq_get_phy_register(hw,
11857 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11858 I40E_I2C_EEPROM_DEV_ADDR, 1,
11859 I40E_MODULE_SFF_8472_SWAP,
11860 &sff8472_swap, NULL);
11864 /* Check if the module requires address swap to access
11865 * the other EEPROM memory page.
11867 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
11868 PMD_DRV_LOG(WARNING,
11869 "Module address swap to access "
11870 "page 0xA2 is not supported.\n");
11871 modinfo->type = RTE_ETH_MODULE_SFF_8079;
11872 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11873 } else if (sff8472_comp == 0x00) {
11874 /* Module is not SFF-8472 compliant */
11875 modinfo->type = RTE_ETH_MODULE_SFF_8079;
11876 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11878 modinfo->type = RTE_ETH_MODULE_SFF_8472;
11879 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
11882 case I40E_MODULE_TYPE_QSFP_PLUS:
11883 /* Read from memory page 0. */
11884 status = i40e_aq_get_phy_register(hw,
11885 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11887 I40E_MODULE_REVISION_ADDR,
11888 &sff8636_rev, NULL);
11891 /* Determine revision compliance byte */
11892 if (sff8636_rev > 0x02) {
11893 /* Module is SFF-8636 compliant */
11894 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11895 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11897 modinfo->type = RTE_ETH_MODULE_SFF_8436;
11898 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11901 case I40E_MODULE_TYPE_QSFP28:
11902 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11903 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11906 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
11912 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
11913 struct rte_dev_eeprom_info *info)
11915 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11916 bool is_sfp = false;
11917 i40e_status status;
11919 uint32_t value = 0;
11922 if (!info || !info->length || !info->data)
11925 if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
11929 for (i = 0; i < info->length; i++) {
11930 u32 offset = i + info->offset;
11931 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
11933 /* Check if we need to access the other memory page */
11935 if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
11936 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
11937 addr = I40E_I2C_EEPROM_DEV_ADDR2;
11940 while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
11941 /* Compute memory page number and offset. */
11942 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
11946 status = i40e_aq_get_phy_register(hw,
11947 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11948 addr, offset, 1, &value, NULL);
11951 data[i] = (uint8_t)value;
11956 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11957 struct rte_ether_addr *mac_addr)
11959 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11960 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11961 struct i40e_vsi *vsi = pf->main_vsi;
11962 struct i40e_mac_filter_info mac_filter;
11963 struct i40e_mac_filter *f;
11966 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
11967 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11971 TAILQ_FOREACH(f, &vsi->mac_list, next) {
11972 if (rte_is_same_ether_addr(&pf->dev_addr,
11973 &f->mac_info.mac_addr))
11978 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11982 mac_filter = f->mac_info;
11983 ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11984 if (ret != I40E_SUCCESS) {
11985 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11988 memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11989 ret = i40e_vsi_add_mac(vsi, &mac_filter);
11990 if (ret != I40E_SUCCESS) {
11991 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11994 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11996 ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11997 mac_addr->addr_bytes, NULL);
11998 if (ret != I40E_SUCCESS) {
11999 PMD_DRV_LOG(ERR, "Failed to change mac");
12007 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
12009 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12010 struct rte_eth_dev_data *dev_data = pf->dev_data;
12011 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
12014 /* check if mtu is within the allowed range */
12015 if (mtu < RTE_ETHER_MIN_MTU || frame_size > I40E_FRAME_SIZE_MAX)
12018 /* mtu setting is forbidden if port is start */
12019 if (dev_data->dev_started) {
12020 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
12021 dev_data->port_id);
12025 if (frame_size > RTE_ETHER_MAX_LEN)
12026 dev_data->dev_conf.rxmode.offloads |=
12027 DEV_RX_OFFLOAD_JUMBO_FRAME;
12029 dev_data->dev_conf.rxmode.offloads &=
12030 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
12032 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
12037 /* Restore ethertype filter */
12039 i40e_ethertype_filter_restore(struct i40e_pf *pf)
12041 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12042 struct i40e_ethertype_filter_list
12043 *ethertype_list = &pf->ethertype.ethertype_list;
12044 struct i40e_ethertype_filter *f;
12045 struct i40e_control_filter_stats stats;
12048 TAILQ_FOREACH(f, ethertype_list, rules) {
12050 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
12051 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
12052 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
12053 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
12054 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
12056 memset(&stats, 0, sizeof(stats));
12057 i40e_aq_add_rem_control_packet_filter(hw,
12058 f->input.mac_addr.addr_bytes,
12059 f->input.ether_type,
12060 flags, pf->main_vsi->seid,
12061 f->queue, 1, &stats, NULL);
12063 PMD_DRV_LOG(INFO, "Ethertype filter:"
12064 " mac_etype_used = %u, etype_used = %u,"
12065 " mac_etype_free = %u, etype_free = %u",
12066 stats.mac_etype_used, stats.etype_used,
12067 stats.mac_etype_free, stats.etype_free);
12070 /* Restore tunnel filter */
12072 i40e_tunnel_filter_restore(struct i40e_pf *pf)
12074 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12075 struct i40e_vsi *vsi;
12076 struct i40e_pf_vf *vf;
12077 struct i40e_tunnel_filter_list
12078 *tunnel_list = &pf->tunnel.tunnel_list;
12079 struct i40e_tunnel_filter *f;
12080 struct i40e_aqc_cloud_filters_element_bb cld_filter;
12081 bool big_buffer = 0;
12083 TAILQ_FOREACH(f, tunnel_list, rules) {
12085 vsi = pf->main_vsi;
12087 vf = &pf->vfs[f->vf_id];
12090 memset(&cld_filter, 0, sizeof(cld_filter));
12091 rte_ether_addr_copy((struct rte_ether_addr *)
12092 &f->input.outer_mac,
12093 (struct rte_ether_addr *)&cld_filter.element.outer_mac);
12094 rte_ether_addr_copy((struct rte_ether_addr *)
12095 &f->input.inner_mac,
12096 (struct rte_ether_addr *)&cld_filter.element.inner_mac);
12097 cld_filter.element.inner_vlan = f->input.inner_vlan;
12098 cld_filter.element.flags = f->input.flags;
12099 cld_filter.element.tenant_id = f->input.tenant_id;
12100 cld_filter.element.queue_number = f->queue;
12101 rte_memcpy(cld_filter.general_fields,
12102 f->input.general_fields,
12103 sizeof(f->input.general_fields));
12105 if (((f->input.flags &
12106 I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
12107 I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
12109 I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
12110 I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
12112 I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
12113 I40E_AQC_ADD_CLOUD_FILTER_0X10))
12117 i40e_aq_add_cloud_filters_bb(hw,
12118 vsi->seid, &cld_filter, 1);
12120 i40e_aq_add_cloud_filters(hw, vsi->seid,
12121 &cld_filter.element, 1);
12125 /* Restore rss filter */
12127 i40e_rss_filter_restore(struct i40e_pf *pf)
12129 struct i40e_rte_flow_rss_conf *conf =
12131 if (conf->conf.queue_num)
12132 i40e_config_rss_filter(pf, conf, TRUE);
12136 i40e_filter_restore(struct i40e_pf *pf)
12138 i40e_ethertype_filter_restore(pf);
12139 i40e_tunnel_filter_restore(pf);
12140 i40e_fdir_filter_restore(pf);
12141 i40e_rss_filter_restore(pf);
12145 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
12147 if (strcmp(dev->device->driver->name, drv->driver.name))
12154 is_i40e_supported(struct rte_eth_dev *dev)
12156 return is_device_supported(dev, &rte_i40e_pmd);
12159 struct i40e_customized_pctype*
12160 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
12164 for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
12165 if (pf->customized_pctype[i].index == index)
12166 return &pf->customized_pctype[i];
12172 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
12173 uint32_t pkg_size, uint32_t proto_num,
12174 struct rte_pmd_i40e_proto_info *proto,
12175 enum rte_pmd_i40e_package_op op)
12177 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12178 uint32_t pctype_num;
12179 struct rte_pmd_i40e_ptype_info *pctype;
12180 uint32_t buff_size;
12181 struct i40e_customized_pctype *new_pctype = NULL;
12183 uint8_t pctype_value;
12188 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12189 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12190 PMD_DRV_LOG(ERR, "Unsupported operation.");
12194 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12195 (uint8_t *)&pctype_num, sizeof(pctype_num),
12196 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
12198 PMD_DRV_LOG(ERR, "Failed to get pctype number");
12202 PMD_DRV_LOG(INFO, "No new pctype added");
12206 buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
12207 pctype = rte_zmalloc("new_pctype", buff_size, 0);
12209 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12212 /* get information about new pctype list */
12213 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12214 (uint8_t *)pctype, buff_size,
12215 RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
12217 PMD_DRV_LOG(ERR, "Failed to get pctype list");
12222 /* Update customized pctype. */
12223 for (i = 0; i < pctype_num; i++) {
12224 pctype_value = pctype[i].ptype_id;
12225 memset(name, 0, sizeof(name));
12226 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12227 proto_id = pctype[i].protocols[j];
12228 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12230 for (n = 0; n < proto_num; n++) {
12231 if (proto[n].proto_id != proto_id)
12233 strlcat(name, proto[n].name, sizeof(name));
12234 strlcat(name, "_", sizeof(name));
12238 name[strlen(name) - 1] = '\0';
12239 if (!strcmp(name, "GTPC"))
12241 i40e_find_customized_pctype(pf,
12242 I40E_CUSTOMIZED_GTPC);
12243 else if (!strcmp(name, "GTPU_IPV4"))
12245 i40e_find_customized_pctype(pf,
12246 I40E_CUSTOMIZED_GTPU_IPV4);
12247 else if (!strcmp(name, "GTPU_IPV6"))
12249 i40e_find_customized_pctype(pf,
12250 I40E_CUSTOMIZED_GTPU_IPV6);
12251 else if (!strcmp(name, "GTPU"))
12253 i40e_find_customized_pctype(pf,
12254 I40E_CUSTOMIZED_GTPU);
12256 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12257 new_pctype->pctype = pctype_value;
12258 new_pctype->valid = true;
12260 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
12261 new_pctype->valid = false;
12271 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
12272 uint32_t pkg_size, uint32_t proto_num,
12273 struct rte_pmd_i40e_proto_info *proto,
12274 enum rte_pmd_i40e_package_op op)
12276 struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
12277 uint16_t port_id = dev->data->port_id;
12278 uint32_t ptype_num;
12279 struct rte_pmd_i40e_ptype_info *ptype;
12280 uint32_t buff_size;
12282 char name[RTE_PMD_I40E_DDP_NAME_SIZE];
12287 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12288 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12289 PMD_DRV_LOG(ERR, "Unsupported operation.");
12293 if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
12294 rte_pmd_i40e_ptype_mapping_reset(port_id);
12298 /* get information about new ptype num */
12299 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12300 (uint8_t *)&ptype_num, sizeof(ptype_num),
12301 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12303 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12307 PMD_DRV_LOG(INFO, "No new ptype added");
12311 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12312 ptype = rte_zmalloc("new_ptype", buff_size, 0);
12314 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12318 /* get information about new ptype list */
12319 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12320 (uint8_t *)ptype, buff_size,
12321 RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12323 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12328 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12329 ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12330 if (!ptype_mapping) {
12331 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12336 /* Update ptype mapping table. */
12337 for (i = 0; i < ptype_num; i++) {
12338 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12339 ptype_mapping[i].sw_ptype = 0;
12341 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12342 proto_id = ptype[i].protocols[j];
12343 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12345 for (n = 0; n < proto_num; n++) {
12346 if (proto[n].proto_id != proto_id)
12348 memset(name, 0, sizeof(name));
12349 strcpy(name, proto[n].name);
12350 if (!strncasecmp(name, "PPPOE", 5))
12351 ptype_mapping[i].sw_ptype |=
12352 RTE_PTYPE_L2_ETHER_PPPOE;
12353 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12355 ptype_mapping[i].sw_ptype |=
12356 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12357 ptype_mapping[i].sw_ptype |=
12359 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12361 ptype_mapping[i].sw_ptype |=
12362 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12363 ptype_mapping[i].sw_ptype |=
12364 RTE_PTYPE_INNER_L4_FRAG;
12365 } else if (!strncasecmp(name, "OIPV4", 5)) {
12366 ptype_mapping[i].sw_ptype |=
12367 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12369 } else if (!strncasecmp(name, "IPV4", 4) &&
12371 ptype_mapping[i].sw_ptype |=
12372 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12373 else if (!strncasecmp(name, "IPV4", 4) &&
12375 ptype_mapping[i].sw_ptype |=
12376 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12377 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12379 ptype_mapping[i].sw_ptype |=
12380 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12381 ptype_mapping[i].sw_ptype |=
12383 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12385 ptype_mapping[i].sw_ptype |=
12386 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12387 ptype_mapping[i].sw_ptype |=
12388 RTE_PTYPE_INNER_L4_FRAG;
12389 } else if (!strncasecmp(name, "OIPV6", 5)) {
12390 ptype_mapping[i].sw_ptype |=
12391 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12393 } else if (!strncasecmp(name, "IPV6", 4) &&
12395 ptype_mapping[i].sw_ptype |=
12396 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12397 else if (!strncasecmp(name, "IPV6", 4) &&
12399 ptype_mapping[i].sw_ptype |=
12400 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12401 else if (!strncasecmp(name, "UDP", 3) &&
12403 ptype_mapping[i].sw_ptype |=
12405 else if (!strncasecmp(name, "UDP", 3) &&
12407 ptype_mapping[i].sw_ptype |=
12408 RTE_PTYPE_INNER_L4_UDP;
12409 else if (!strncasecmp(name, "TCP", 3) &&
12411 ptype_mapping[i].sw_ptype |=
12413 else if (!strncasecmp(name, "TCP", 3) &&
12415 ptype_mapping[i].sw_ptype |=
12416 RTE_PTYPE_INNER_L4_TCP;
12417 else if (!strncasecmp(name, "SCTP", 4) &&
12419 ptype_mapping[i].sw_ptype |=
12421 else if (!strncasecmp(name, "SCTP", 4) &&
12423 ptype_mapping[i].sw_ptype |=
12424 RTE_PTYPE_INNER_L4_SCTP;
12425 else if ((!strncasecmp(name, "ICMP", 4) ||
12426 !strncasecmp(name, "ICMPV6", 6)) &&
12428 ptype_mapping[i].sw_ptype |=
12430 else if ((!strncasecmp(name, "ICMP", 4) ||
12431 !strncasecmp(name, "ICMPV6", 6)) &&
12433 ptype_mapping[i].sw_ptype |=
12434 RTE_PTYPE_INNER_L4_ICMP;
12435 else if (!strncasecmp(name, "GTPC", 4)) {
12436 ptype_mapping[i].sw_ptype |=
12437 RTE_PTYPE_TUNNEL_GTPC;
12439 } else if (!strncasecmp(name, "GTPU", 4)) {
12440 ptype_mapping[i].sw_ptype |=
12441 RTE_PTYPE_TUNNEL_GTPU;
12443 } else if (!strncasecmp(name, "GRENAT", 6)) {
12444 ptype_mapping[i].sw_ptype |=
12445 RTE_PTYPE_TUNNEL_GRENAT;
12447 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12448 !strncasecmp(name, "L2TPV2", 6)) {
12449 ptype_mapping[i].sw_ptype |=
12450 RTE_PTYPE_TUNNEL_L2TP;
12459 ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12462 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
12464 rte_free(ptype_mapping);
12470 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12471 uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12473 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12474 uint32_t proto_num;
12475 struct rte_pmd_i40e_proto_info *proto;
12476 uint32_t buff_size;
12480 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12481 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12482 PMD_DRV_LOG(ERR, "Unsupported operation.");
12486 /* get information about protocol number */
12487 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12488 (uint8_t *)&proto_num, sizeof(proto_num),
12489 RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12491 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12495 PMD_DRV_LOG(INFO, "No new protocol added");
12499 buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12500 proto = rte_zmalloc("new_proto", buff_size, 0);
12502 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12506 /* get information about protocol list */
12507 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12508 (uint8_t *)proto, buff_size,
12509 RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12511 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12516 /* Check if GTP is supported. */
12517 for (i = 0; i < proto_num; i++) {
12518 if (!strncmp(proto[i].name, "GTP", 3)) {
12519 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12520 pf->gtp_support = true;
12522 pf->gtp_support = false;
12527 /* Update customized pctype info */
12528 ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12529 proto_num, proto, op);
12531 PMD_DRV_LOG(INFO, "No pctype is updated.");
12533 /* Update customized ptype info */
12534 ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12535 proto_num, proto, op);
12537 PMD_DRV_LOG(INFO, "No ptype is updated.");
12542 /* Create a QinQ cloud filter
12544 * The Fortville NIC has limited resources for tunnel filters,
12545 * so we can only reuse existing filters.
12547 * In step 1 we define which Field Vector fields can be used for
12549 * As we do not have the inner tag defined as a field,
12550 * we have to define it first, by reusing one of L1 entries.
12552 * In step 2 we are replacing one of existing filter types with
12553 * a new one for QinQ.
12554 * As we reusing L1 and replacing L2, some of the default filter
12555 * types will disappear,which depends on L1 and L2 entries we reuse.
12557 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12559 * 1. Create L1 filter of outer vlan (12b) which will be in use
12560 * later when we define the cloud filter.
12561 * a. Valid_flags.replace_cloud = 0
12562 * b. Old_filter = 10 (Stag_Inner_Vlan)
12563 * c. New_filter = 0x10
12564 * d. TR bit = 0xff (optional, not used here)
12565 * e. Buffer – 2 entries:
12566 * i. Byte 0 = 8 (outer vlan FV index).
12568 * Byte 2-3 = 0x0fff
12569 * ii. Byte 0 = 37 (inner vlan FV index).
12571 * Byte 2-3 = 0x0fff
12574 * 2. Create cloud filter using two L1 filters entries: stag and
12575 * new filter(outer vlan+ inner vlan)
12576 * a. Valid_flags.replace_cloud = 1
12577 * b. Old_filter = 1 (instead of outer IP)
12578 * c. New_filter = 0x10
12579 * d. Buffer – 2 entries:
12580 * i. Byte 0 = 0x80 | 7 (valid | Stag).
12581 * Byte 1-3 = 0 (rsv)
12582 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12583 * Byte 9-11 = 0 (rsv)
12586 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12588 int ret = -ENOTSUP;
12589 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
12590 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
12591 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12592 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
12594 if (pf->support_multi_driver) {
12595 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12600 memset(&filter_replace, 0,
12601 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12602 memset(&filter_replace_buf, 0,
12603 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12605 /* create L1 filter */
12606 filter_replace.old_filter_type =
12607 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12608 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12609 filter_replace.tr_bit = 0;
12611 /* Prepare the buffer, 2 entries */
12612 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12613 filter_replace_buf.data[0] |=
12614 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12615 /* Field Vector 12b mask */
12616 filter_replace_buf.data[2] = 0xff;
12617 filter_replace_buf.data[3] = 0x0f;
12618 filter_replace_buf.data[4] =
12619 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12620 filter_replace_buf.data[4] |=
12621 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12622 /* Field Vector 12b mask */
12623 filter_replace_buf.data[6] = 0xff;
12624 filter_replace_buf.data[7] = 0x0f;
12625 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12626 &filter_replace_buf);
12627 if (ret != I40E_SUCCESS)
12630 if (filter_replace.old_filter_type !=
12631 filter_replace.new_filter_type)
12632 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
12633 " original: 0x%x, new: 0x%x",
12635 filter_replace.old_filter_type,
12636 filter_replace.new_filter_type);
12638 /* Apply the second L2 cloud filter */
12639 memset(&filter_replace, 0,
12640 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12641 memset(&filter_replace_buf, 0,
12642 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12644 /* create L2 filter, input for L2 filter will be L1 filter */
12645 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12646 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12647 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12649 /* Prepare the buffer, 2 entries */
12650 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12651 filter_replace_buf.data[0] |=
12652 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12653 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12654 filter_replace_buf.data[4] |=
12655 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12656 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12657 &filter_replace_buf);
12658 if (!ret && (filter_replace.old_filter_type !=
12659 filter_replace.new_filter_type))
12660 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
12661 " original: 0x%x, new: 0x%x",
12663 filter_replace.old_filter_type,
12664 filter_replace.new_filter_type);
12670 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
12671 const struct rte_flow_action_rss *in)
12673 if (in->key_len > RTE_DIM(out->key) ||
12674 in->queue_num > RTE_DIM(out->queue))
12676 if (!in->key && in->key_len)
12678 out->conf = (struct rte_flow_action_rss){
12680 .level = in->level,
12681 .types = in->types,
12682 .key_len = in->key_len,
12683 .queue_num = in->queue_num,
12684 .queue = memcpy(out->queue, in->queue,
12685 sizeof(*in->queue) * in->queue_num),
12688 out->conf.key = memcpy(out->key, in->key, in->key_len);
12693 i40e_action_rss_same(const struct rte_flow_action_rss *comp,
12694 const struct rte_flow_action_rss *with)
12696 return (comp->func == with->func &&
12697 comp->level == with->level &&
12698 comp->types == with->types &&
12699 comp->key_len == with->key_len &&
12700 comp->queue_num == with->queue_num &&
12701 !memcmp(comp->key, with->key, with->key_len) &&
12702 !memcmp(comp->queue, with->queue,
12703 sizeof(*with->queue) * with->queue_num));
12707 i40e_config_rss_filter(struct i40e_pf *pf,
12708 struct i40e_rte_flow_rss_conf *conf, bool add)
12710 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12711 uint32_t i, lut = 0;
12713 struct rte_eth_rss_conf rss_conf = {
12714 .rss_key = conf->conf.key_len ?
12715 (void *)(uintptr_t)conf->conf.key : NULL,
12716 .rss_key_len = conf->conf.key_len,
12717 .rss_hf = conf->conf.types,
12719 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
12722 if (i40e_action_rss_same(&rss_info->conf, &conf->conf)) {
12723 i40e_pf_disable_rss(pf);
12724 memset(rss_info, 0,
12725 sizeof(struct i40e_rte_flow_rss_conf));
12731 /* If both VMDQ and RSS enabled, not all of PF queues are configured.
12732 * It's necessary to calculate the actual PF queues that are configured.
12734 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
12735 num = i40e_pf_calc_configured_queues_num(pf);
12737 num = pf->dev_data->nb_rx_queues;
12739 num = RTE_MIN(num, conf->conf.queue_num);
12740 PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
12744 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS");
12748 /* Fill in redirection table */
12749 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
12752 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
12753 hw->func_caps.rss_table_entry_width) - 1));
12755 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
12758 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
12759 i40e_pf_disable_rss(pf);
12762 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
12763 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
12764 /* Random default keys */
12765 static uint32_t rss_key_default[] = {0x6b793944,
12766 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
12767 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
12768 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
12770 rss_conf.rss_key = (uint8_t *)rss_key_default;
12771 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
12774 "No valid RSS key config for i40e, using default\n");
12777 i40e_hw_rss_hash_set(pf, &rss_conf);
12779 if (i40e_rss_conf_init(rss_info, &conf->conf))
12785 RTE_INIT(i40e_init_log)
12787 i40e_logtype_init = rte_log_register("pmd.net.i40e.init");
12788 if (i40e_logtype_init >= 0)
12789 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
12790 i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver");
12791 if (i40e_logtype_driver >= 0)
12792 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
12795 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12796 ETH_I40E_FLOATING_VEB_ARG "=1"
12797 ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
12798 ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12799 ETH_I40E_SUPPORT_MULTI_DRIVER "=1"
12800 ETH_I40E_USE_LATEST_VEC "=0|1");