drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2017 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53 #include <rte_tailq.h>
  54 #include <rte_hash_crc.h>
  55
  56 #include "i40e_logs.h"
  57 #include "base/i40e_prototype.h"
  58 #include "base/i40e_adminq_cmd.h"
  59 #include "base/i40e_type.h"
  60 #include "base/i40e_register.h"
  61 #include "base/i40e_dcb.h"
  62 #include "i40e_ethdev.h"
  63 #include "i40e_rxtx.h"
  64 #include "i40e_pf.h"
  65 #include "i40e_regs.h"
  66 #include "rte_pmd_i40e.h"
  67
  68 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  69 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  70
  71 #define I40E_CLEAR_PXE_WAIT_MS     200
  72
  73 /* Maximun number of capability elements */
  74 #define I40E_MAX_CAP_ELE_NUM       128
  75
  76 /* Wait count and inteval */
  77 #define I40E_CHK_Q_ENA_COUNT       1000
  78 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  79
  80 /* Maximun number of VSI */
  81 #define I40E_MAX_NUM_VSIS          (384UL)
  82
  83 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  84
  85 /* Flow control default timer */
  86 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  87
  88 /* Flow control default high water */
  89 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  90
  91 /* Flow control default low water */
  92 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  93
  94 /* Flow control enable fwd bit */
  95 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  96
  97 /* Receive Packet Buffer size */
  98 #define I40E_RXPBSIZE (968 * 1024)
  99
 100 /* Kilobytes shift */
 101 #define I40E_KILOSHIFT 10
 102
 103 /* Receive Average Packet Size in Byte*/
 104 #define I40E_PACKET_AVERAGE_SIZE 128
 105
 106 /* Mask of PF interrupt causes */
 107 #define I40E_PFINT_ICR0_ENA_MASK ( \
 108                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 109                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 110                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 111                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 112                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 113                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 114                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 115                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 116                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 117
 118 #define I40E_FLOW_TYPES ( \
 119         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 124         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 128         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 129         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 130
 131 /* Additional timesync values. */
 132 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 133 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 134 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 135 #define I40E_PRTTSYN_TSYNENA     0x80000000
 136 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 137 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 138
 139 #define I40E_MAX_PERCENT            100
 140 #define I40E_DEFAULT_DCB_APP_NUM    1
 141 #define I40E_DEFAULT_DCB_APP_PRIO   3
 142
 143 /**
 144  * Below are values for writing un-exposed registers suggested
 145  * by silicon experts
 146  */
 147 /* Destination MAC address */
 148 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 149 /* Source MAC address */
 150 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 151 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 152 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 153 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 154 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 155 /* Single VLAN tag in the inner L2 header */
 156 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 157 /* Source IPv4 address */
 158 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 159 /* Destination IPv4 address */
 160 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 161 /* Source IPv4 address for X722 */
 162 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 163 /* Destination IPv4 address for X722 */
 164 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 165 /* IPv4 Protocol for X722 */
 166 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 167 /* IPv4 Time to Live for X722 */
 168 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 169 /* IPv4 Type of Service (TOS) */
 170 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 171 /* IPv4 Protocol */
 172 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 173 /* IPv4 Time to Live */
 174 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 175 /* Source IPv6 address */
 176 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 177 /* Destination IPv6 address */
 178 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 179 /* IPv6 Traffic Class (TC) */
 180 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 181 /* IPv6 Next Header */
 182 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 183 /* IPv6 Hop Limit */
 184 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 185 /* Source L4 port */
 186 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 187 /* Destination L4 port */
 188 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 189 /* SCTP verification tag */
 190 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 191 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 192 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 193 /* Source port of tunneling UDP */
 194 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 195 /* Destination port of tunneling UDP */
 196 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 197 /* UDP Tunneling ID, NVGRE/GRE key */
 198 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 199 /* Last ether type */
 200 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 201 /* Tunneling outer destination IPv4 address */
 202 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 203 /* Tunneling outer destination IPv6 address */
 204 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 205 /* 1st word of flex payload */
 206 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 207 /* 2nd word of flex payload */
 208 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 209 /* 3rd word of flex payload */
 210 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 211 /* 4th word of flex payload */
 212 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 213 /* 5th word of flex payload */
 214 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 215 /* 6th word of flex payload */
 216 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 217 /* 7th word of flex payload */
 218 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 219 /* 8th word of flex payload */
 220 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 221 /* all 8 words flex payload */
 222 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 223 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 224
 225 #define I40E_TRANSLATE_INSET 0
 226 #define I40E_TRANSLATE_REG   1
 227
 228 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 229 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 230 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 231 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 232 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 233 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 234
 235 /* PCI offset for querying capability */
 236 #define PCI_DEV_CAP_REG            0xA4
 237 /* PCI offset for enabling/disabling Extended Tag */
 238 #define PCI_DEV_CTRL_REG           0xA8
 239 /* Bit mask of Extended Tag capability */
 240 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 241 /* Bit shift of Extended Tag enable/disable */
 242 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 243 /* Bit mask of Extended Tag enable/disable */
 244 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 245
 246 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 247 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 248 static int i40e_dev_configure(struct rte_eth_dev *dev);
 249 static int i40e_dev_start(struct rte_eth_dev *dev);
 250 static void i40e_dev_stop(struct rte_eth_dev *dev);
 251 static void i40e_dev_close(struct rte_eth_dev *dev);
 252 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 253 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 254 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 255 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 256 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 257 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 258 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 259                                struct rte_eth_stats *stats);
 260 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 261                                struct rte_eth_xstat *xstats, unsigned n);
 262 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 263                                      struct rte_eth_xstat_name *xstats_names,
 264                                      unsigned limit);
 265 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 266 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 267                                             uint16_t queue_id,
 268                                             uint8_t stat_idx,
 269                                             uint8_t is_rx);
 270 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 271                                 char *fw_version, size_t fw_size);
 272 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 273                               struct rte_eth_dev_info *dev_info);
 274 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 275                                 uint16_t vlan_id,
 276                                 int on);
 277 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 278                               enum rte_vlan_type vlan_type,
 279                               uint16_t tpid);
 280 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 281 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 282                                       uint16_t queue,
 283                                       int on);
 284 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 285 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 286 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 287 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 288                               struct rte_eth_fc_conf *fc_conf);
 289 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 290                               struct rte_eth_fc_conf *fc_conf);
 291 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 292                                        struct rte_eth_pfc_conf *pfc_conf);
 293 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 294                           struct ether_addr *mac_addr,
 295                           uint32_t index,
 296                           uint32_t pool);
 297 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 298 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 299                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 300                                     uint16_t reta_size);
 301 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 302                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 303                                    uint16_t reta_size);
 304
 305 static int i40e_get_cap(struct i40e_hw *hw);
 306 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 307 static int i40e_pf_setup(struct i40e_pf *pf);
 308 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 309 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 310 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 311 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 312 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 313                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 314 static void i40e_stat_update_48(struct i40e_hw *hw,
 315                                uint32_t hireg,
 316                                uint32_t loreg,
 317                                bool offset_loaded,
 318                                uint64_t *offset,
 319                                uint64_t *stat);
 320 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 321 static void i40e_dev_interrupt_handler(struct rte_intr_handle *handle,
 322                                        void *param);
 323 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 324                                 uint32_t base, uint32_t num);
 325 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 326 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 327                         uint32_t base);
 328 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 329                         uint16_t num);
 330 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 331 static int i40e_veb_release(struct i40e_veb *veb);
 332 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 333                                                 struct i40e_vsi *vsi);
 334 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 335 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 336 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 337                                              struct i40e_macvlan_filter *mv_f,
 338                                              int num,
 339                                              struct ether_addr *addr);
 340 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 341                                              struct i40e_macvlan_filter *mv_f,
 342                                              int num,
 343                                              uint16_t vlan);
 344 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 345 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 346                                     struct rte_eth_rss_conf *rss_conf);
 347 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 348                                       struct rte_eth_rss_conf *rss_conf);
 349 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 350                                         struct rte_eth_udp_tunnel *udp_tunnel);
 351 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 352                                         struct rte_eth_udp_tunnel *udp_tunnel);
 353 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 354 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 355                                 enum rte_filter_op filter_op,
 356                                 void *arg);
 357 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 358                                 enum rte_filter_type filter_type,
 359                                 enum rte_filter_op filter_op,
 360                                 void *arg);
 361 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 362                                   struct rte_eth_dcb_info *dcb_info);
 363 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 364 static void i40e_configure_registers(struct i40e_hw *hw);
 365 static void i40e_hw_init(struct rte_eth_dev *dev);
 366 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 367 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 368                         struct rte_eth_mirror_conf *mirror_conf,
 369                         uint8_t sw_id, uint8_t on);
 370 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 371
 372 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 373 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 374 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 375                                            struct timespec *timestamp,
 376                                            uint32_t flags);
 377 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 378                                            struct timespec *timestamp);
 379 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 380
 381 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 382
 383 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 384                                    struct timespec *timestamp);
 385 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 386                                     const struct timespec *timestamp);
 387
 388 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 389                                          uint16_t queue_id);
 390 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 391                                           uint16_t queue_id);
 392
 393 static int i40e_get_regs(struct rte_eth_dev *dev,
 394                          struct rte_dev_reg_info *regs);
 395
 396 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 397
 398 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 399                            struct rte_dev_eeprom_info *eeprom);
 400
 401 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 402                                       struct ether_addr *mac_addr);
 403
 404 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 405
 406 static int i40e_ethertype_filter_convert(
 407         const struct rte_eth_ethertype_filter *input,
 408         struct i40e_ethertype_filter *filter);
 409 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 410                                    struct i40e_ethertype_filter *filter);
 411
 412 static int i40e_tunnel_filter_convert(
 413         struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter,
 414         struct i40e_tunnel_filter *tunnel_filter);
 415 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 416                                 struct i40e_tunnel_filter *tunnel_filter);
 417
 418 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 419 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 420 static void i40e_filter_restore(struct i40e_pf *pf);
 421
 422 static const struct rte_pci_id pci_id_i40e_map[] = {
 423         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 424         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 425         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 426         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 438         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 439         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 440         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 441         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 442         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 443         { .vendor_id = 0, /* sentinel */ },
 444 };
 445
 446 static const struct eth_dev_ops i40e_eth_dev_ops = {
 447         .dev_configure                = i40e_dev_configure,
 448         .dev_start                    = i40e_dev_start,
 449         .dev_stop                     = i40e_dev_stop,
 450         .dev_close                    = i40e_dev_close,
 451         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 452         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 453         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 454         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 455         .dev_set_link_up              = i40e_dev_set_link_up,
 456         .dev_set_link_down            = i40e_dev_set_link_down,
 457         .link_update                  = i40e_dev_link_update,
 458         .stats_get                    = i40e_dev_stats_get,
 459         .xstats_get                   = i40e_dev_xstats_get,
 460         .xstats_get_names             = i40e_dev_xstats_get_names,
 461         .stats_reset                  = i40e_dev_stats_reset,
 462         .xstats_reset                 = i40e_dev_stats_reset,
 463         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 464         .fw_version_get               = i40e_fw_version_get,
 465         .dev_infos_get                = i40e_dev_info_get,
 466         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 467         .vlan_filter_set              = i40e_vlan_filter_set,
 468         .vlan_tpid_set                = i40e_vlan_tpid_set,
 469         .vlan_offload_set             = i40e_vlan_offload_set,
 470         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 471         .vlan_pvid_set                = i40e_vlan_pvid_set,
 472         .rx_queue_start               = i40e_dev_rx_queue_start,
 473         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 474         .tx_queue_start               = i40e_dev_tx_queue_start,
 475         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 476         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 477         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 478         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 479         .rx_queue_release             = i40e_dev_rx_queue_release,
 480         .rx_queue_count               = i40e_dev_rx_queue_count,
 481         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 482         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 483         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 484         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 485         .tx_queue_release             = i40e_dev_tx_queue_release,
 486         .dev_led_on                   = i40e_dev_led_on,
 487         .dev_led_off                  = i40e_dev_led_off,
 488         .flow_ctrl_get                = i40e_flow_ctrl_get,
 489         .flow_ctrl_set                = i40e_flow_ctrl_set,
 490         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 491         .mac_addr_add                 = i40e_macaddr_add,
 492         .mac_addr_remove              = i40e_macaddr_remove,
 493         .reta_update                  = i40e_dev_rss_reta_update,
 494         .reta_query                   = i40e_dev_rss_reta_query,
 495         .rss_hash_update              = i40e_dev_rss_hash_update,
 496         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 497         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 498         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 499         .filter_ctrl                  = i40e_dev_filter_ctrl,
 500         .rxq_info_get                 = i40e_rxq_info_get,
 501         .txq_info_get                 = i40e_txq_info_get,
 502         .mirror_rule_set              = i40e_mirror_rule_set,
 503         .mirror_rule_reset            = i40e_mirror_rule_reset,
 504         .timesync_enable              = i40e_timesync_enable,
 505         .timesync_disable             = i40e_timesync_disable,
 506         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 507         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 508         .get_dcb_info                 = i40e_dev_get_dcb_info,
 509         .timesync_adjust_time         = i40e_timesync_adjust_time,
 510         .timesync_read_time           = i40e_timesync_read_time,
 511         .timesync_write_time          = i40e_timesync_write_time,
 512         .get_reg                      = i40e_get_regs,
 513         .get_eeprom_length            = i40e_get_eeprom_length,
 514         .get_eeprom                   = i40e_get_eeprom,
 515         .mac_addr_set                 = i40e_set_default_mac_addr,
 516         .mtu_set                      = i40e_dev_mtu_set,
 517 };
 518
 519 /* store statistics names and its offset in stats structure */
 520 struct rte_i40e_xstats_name_off {
 521         char name[RTE_ETH_XSTATS_NAME_SIZE];
 522         unsigned offset;
 523 };
 524
 525 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 526         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 527         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 528         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 529         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 530         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 531                 rx_unknown_protocol)},
 532         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 533         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 534         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 535         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 536 };
 537
 538 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 539                 sizeof(rte_i40e_stats_strings[0]))
 540
 541 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 542         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 543                 tx_dropped_link_down)},
 544         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 545         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 546                 illegal_bytes)},
 547         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 548         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 549                 mac_local_faults)},
 550         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 551                 mac_remote_faults)},
 552         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 553                 rx_length_errors)},
 554         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 555         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 556         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 557         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 558         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 559         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 560                 rx_size_127)},
 561         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 562                 rx_size_255)},
 563         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 564                 rx_size_511)},
 565         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 566                 rx_size_1023)},
 567         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 568                 rx_size_1522)},
 569         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 570                 rx_size_big)},
 571         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 572                 rx_undersize)},
 573         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 574                 rx_oversize)},
 575         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 576                 mac_short_packet_dropped)},
 577         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 578                 rx_fragments)},
 579         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 580         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 581         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 582                 tx_size_127)},
 583         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 584                 tx_size_255)},
 585         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 586                 tx_size_511)},
 587         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 588                 tx_size_1023)},
 589         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 590                 tx_size_1522)},
 591         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 592                 tx_size_big)},
 593         {"rx_flow_director_atr_match_packets",
 594                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 595         {"rx_flow_director_sb_match_packets",
 596                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 597         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 598                 tx_lpi_status)},
 599         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 600                 rx_lpi_status)},
 601         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 602                 tx_lpi_count)},
 603         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 604                 rx_lpi_count)},
 605 };
 606
 607 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 608                 sizeof(rte_i40e_hw_port_strings[0]))
 609
 610 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 611         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 612                 priority_xon_rx)},
 613         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 614                 priority_xoff_rx)},
 615 };
 616
 617 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 618                 sizeof(rte_i40e_rxq_prio_strings[0]))
 619
 620 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 621         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 622                 priority_xon_tx)},
 623         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 624                 priority_xoff_tx)},
 625         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 626                 priority_xon_2_xoff)},
 627 };
 628
 629 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 630                 sizeof(rte_i40e_txq_prio_strings[0]))
 631
 632 static struct eth_driver rte_i40e_pmd = {
 633         .pci_drv = {
 634                 .id_table = pci_id_i40e_map,
 635                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 636                 .probe = rte_eth_dev_pci_probe,
 637                 .remove = rte_eth_dev_pci_remove,
 638         },
 639         .eth_dev_init = eth_i40e_dev_init,
 640         .eth_dev_uninit = eth_i40e_dev_uninit,
 641         .dev_private_size = sizeof(struct i40e_adapter),
 642 };
 643
 644 static inline int
 645 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 646                                      struct rte_eth_link *link)
 647 {
 648         struct rte_eth_link *dst = link;
 649         struct rte_eth_link *src = &(dev->data->dev_link);
 650
 651         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 652                                         *(uint64_t *)src) == 0)
 653                 return -1;
 654
 655         return 0;
 656 }
 657
 658 static inline int
 659 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 660                                       struct rte_eth_link *link)
 661 {
 662         struct rte_eth_link *dst = &(dev->data->dev_link);
 663         struct rte_eth_link *src = link;
 664
 665         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 666                                         *(uint64_t *)src) == 0)
 667                 return -1;
 668
 669         return 0;
 670 }
 671
 672 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
 673 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 674 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio");
 675
 676 #ifndef I40E_GLQF_ORT
 677 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 678 #endif
 679 #ifndef I40E_GLQF_PIT
 680 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 681 #endif
 682
 683 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 684 {
 685         /*
 686          * Initialize registers for flexible payload, which should be set by NVM.
 687          * This should be removed from code once it is fixed in NVM.
 688          */
 689         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 690         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 691         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 692         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 693         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 694         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 695         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 696         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 697         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 698         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 699         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 700         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 701
 702         /* Initialize registers for parsing packet type of QinQ */
 703         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 704         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 705 }
 706
 707 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 708
 709 /*
 710  * Add a ethertype filter to drop all flow control frames transmitted
 711  * from VSIs.
 712 */
 713 static void
 714 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 715 {
 716         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 717         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 718                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 719                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 720         int ret;
 721
 722         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 723                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 724                                 pf->main_vsi_seid, 0,
 725                                 TRUE, NULL, NULL);
 726         if (ret)
 727                 PMD_INIT_LOG(ERR,
 728                         "Failed to add filter to drop flow control frames from VSIs.");
 729 }
 730
 731 static int
 732 floating_veb_list_handler(__rte_unused const char *key,
 733                           const char *floating_veb_value,
 734                           void *opaque)
 735 {
 736         int idx = 0;
 737         unsigned int count = 0;
 738         char *end = NULL;
 739         int min, max;
 740         bool *vf_floating_veb = opaque;
 741
 742         while (isblank(*floating_veb_value))
 743                 floating_veb_value++;
 744
 745         /* Reset floating VEB configuration for VFs */
 746         for (idx = 0; idx < I40E_MAX_VF; idx++)
 747                 vf_floating_veb[idx] = false;
 748
 749         min = I40E_MAX_VF;
 750         do {
 751                 while (isblank(*floating_veb_value))
 752                         floating_veb_value++;
 753                 if (*floating_veb_value == '\0')
 754                         return -1;
 755                 errno = 0;
 756                 idx = strtoul(floating_veb_value, &end, 10);
 757                 if (errno || end == NULL)
 758                         return -1;
 759                 while (isblank(*end))
 760                         end++;
 761                 if (*end == '-') {
 762                         min = idx;
 763                 } else if ((*end == ';') || (*end == '\0')) {
 764                         max = idx;
 765                         if (min == I40E_MAX_VF)
 766                                 min = idx;
 767                         if (max >= I40E_MAX_VF)
 768                                 max = I40E_MAX_VF - 1;
 769                         for (idx = min; idx <= max; idx++) {
 770                                 vf_floating_veb[idx] = true;
 771                                 count++;
 772                         }
 773                         min = I40E_MAX_VF;
 774                 } else {
 775                         return -1;
 776                 }
 777                 floating_veb_value = end + 1;
 778         } while (*end != '\0');
 779
 780         if (count == 0)
 781                 return -1;
 782
 783         return 0;
 784 }
 785
 786 static void
 787 config_vf_floating_veb(struct rte_devargs *devargs,
 788                        uint16_t floating_veb,
 789                        bool *vf_floating_veb)
 790 {
 791         struct rte_kvargs *kvlist;
 792         int i;
 793         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 794
 795         if (!floating_veb)
 796                 return;
 797         /* All the VFs attach to the floating VEB by default
 798          * when the floating VEB is enabled.
 799          */
 800         for (i = 0; i < I40E_MAX_VF; i++)
 801                 vf_floating_veb[i] = true;
 802
 803         if (devargs == NULL)
 804                 return;
 805
 806         kvlist = rte_kvargs_parse(devargs->args, NULL);
 807         if (kvlist == NULL)
 808                 return;
 809
 810         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 811                 rte_kvargs_free(kvlist);
 812                 return;
 813         }
 814         /* When the floating_veb_list parameter exists, all the VFs
 815          * will attach to the legacy VEB firstly, then configure VFs
 816          * to the floating VEB according to the floating_veb_list.
 817          */
 818         if (rte_kvargs_process(kvlist, floating_veb_list,
 819                                floating_veb_list_handler,
 820                                vf_floating_veb) < 0) {
 821                 rte_kvargs_free(kvlist);
 822                 return;
 823         }
 824         rte_kvargs_free(kvlist);
 825 }
 826
 827 static int
 828 i40e_check_floating_handler(__rte_unused const char *key,
 829                             const char *value,
 830                             __rte_unused void *opaque)
 831 {
 832         if (strcmp(value, "1"))
 833                 return -1;
 834
 835         return 0;
 836 }
 837
 838 static int
 839 is_floating_veb_supported(struct rte_devargs *devargs)
 840 {
 841         struct rte_kvargs *kvlist;
 842         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 843
 844         if (devargs == NULL)
 845                 return 0;
 846
 847         kvlist = rte_kvargs_parse(devargs->args, NULL);
 848         if (kvlist == NULL)
 849                 return 0;
 850
 851         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 852                 rte_kvargs_free(kvlist);
 853                 return 0;
 854         }
 855         /* Floating VEB is enabled when there's key-value:
 856          * enable_floating_veb=1
 857          */
 858         if (rte_kvargs_process(kvlist, floating_veb_key,
 859                                i40e_check_floating_handler, NULL) < 0) {
 860                 rte_kvargs_free(kvlist);
 861                 return 0;
 862         }
 863         rte_kvargs_free(kvlist);
 864
 865         return 1;
 866 }
 867
 868 static void
 869 config_floating_veb(struct rte_eth_dev *dev)
 870 {
 871         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
 872         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 873         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 874
 875         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 876
 877         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 878                 pf->floating_veb =
 879                         is_floating_veb_supported(pci_dev->device.devargs);
 880                 config_vf_floating_veb(pci_dev->device.devargs,
 881                                        pf->floating_veb,
 882                                        pf->floating_veb_list);
 883         } else {
 884                 pf->floating_veb = false;
 885         }
 886 }
 887
 888 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 889 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 890
 891 static int
 892 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 893 {
 894         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 895         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 896         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 897         int ret;
 898
 899         struct rte_hash_parameters ethertype_hash_params = {
 900                 .name = ethertype_hash_name,
 901                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 902                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 903                 .hash_func = rte_hash_crc,
 904         };
 905
 906         /* Initialize ethertype filter rule list and hash */
 907         TAILQ_INIT(&ethertype_rule->ethertype_list);
 908         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 909                  "ethertype_%s", dev->data->name);
 910         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 911         if (!ethertype_rule->hash_table) {
 912                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 913                 return -EINVAL;
 914         }
 915         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 916                                        sizeof(struct i40e_ethertype_filter *) *
 917                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 918                                        0);
 919         if (!ethertype_rule->hash_map) {
 920                 PMD_INIT_LOG(ERR,
 921                              "Failed to allocate memory for ethertype hash map!");
 922                 ret = -ENOMEM;
 923                 goto err_ethertype_hash_map_alloc;
 924         }
 925
 926         return 0;
 927
 928 err_ethertype_hash_map_alloc:
 929         rte_hash_free(ethertype_rule->hash_table);
 930
 931         return ret;
 932 }
 933
 934 static int
 935 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 936 {
 937         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 938         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 939         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 940         int ret;
 941
 942         struct rte_hash_parameters tunnel_hash_params = {
 943                 .name = tunnel_hash_name,
 944                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 945                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 946                 .hash_func = rte_hash_crc,
 947         };
 948
 949         /* Initialize tunnel filter rule list and hash */
 950         TAILQ_INIT(&tunnel_rule->tunnel_list);
 951         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
 952                  "tunnel_%s", dev->data->name);
 953         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
 954         if (!tunnel_rule->hash_table) {
 955                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
 956                 return -EINVAL;
 957         }
 958         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
 959                                     sizeof(struct i40e_tunnel_filter *) *
 960                                     I40E_MAX_TUNNEL_FILTER_NUM,
 961                                     0);
 962         if (!tunnel_rule->hash_map) {
 963                 PMD_INIT_LOG(ERR,
 964                              "Failed to allocate memory for tunnel hash map!");
 965                 ret = -ENOMEM;
 966                 goto err_tunnel_hash_map_alloc;
 967         }
 968
 969         return 0;
 970
 971 err_tunnel_hash_map_alloc:
 972         rte_hash_free(tunnel_rule->hash_table);
 973
 974         return ret;
 975 }
 976
 977 static int
 978 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
 979 {
 980         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 981         struct i40e_fdir_info *fdir_info = &pf->fdir;
 982         char fdir_hash_name[RTE_HASH_NAMESIZE];
 983         int ret;
 984
 985         struct rte_hash_parameters fdir_hash_params = {
 986                 .name = fdir_hash_name,
 987                 .entries = I40E_MAX_FDIR_FILTER_NUM,
 988                 .key_len = sizeof(struct rte_eth_fdir_input),
 989                 .hash_func = rte_hash_crc,
 990         };
 991
 992         /* Initialize flow director filter rule list and hash */
 993         TAILQ_INIT(&fdir_info->fdir_list);
 994         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
 995                  "fdir_%s", dev->data->name);
 996         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
 997         if (!fdir_info->hash_table) {
 998                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
 999                 return -EINVAL;
1000         }
1001         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1002                                           sizeof(struct i40e_fdir_filter *) *
1003                                           I40E_MAX_FDIR_FILTER_NUM,
1004                                           0);
1005         if (!fdir_info->hash_map) {
1006                 PMD_INIT_LOG(ERR,
1007                              "Failed to allocate memory for fdir hash map!");
1008                 ret = -ENOMEM;
1009                 goto err_fdir_hash_map_alloc;
1010         }
1011         return 0;
1012
1013 err_fdir_hash_map_alloc:
1014         rte_hash_free(fdir_info->hash_table);
1015
1016         return ret;
1017 }
1018
1019 static int
1020 eth_i40e_dev_init(struct rte_eth_dev *dev)
1021 {
1022         struct rte_pci_device *pci_dev;
1023         struct rte_intr_handle *intr_handle;
1024         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1025         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1026         struct i40e_vsi *vsi;
1027         int ret;
1028         uint32_t len;
1029         uint8_t aq_fail = 0;
1030
1031         PMD_INIT_FUNC_TRACE();
1032
1033         dev->dev_ops = &i40e_eth_dev_ops;
1034         dev->rx_pkt_burst = i40e_recv_pkts;
1035         dev->tx_pkt_burst = i40e_xmit_pkts;
1036         dev->tx_pkt_prepare = i40e_prep_pkts;
1037
1038         /* for secondary processes, we don't initialise any further as primary
1039          * has already done this work. Only check we don't need a different
1040          * RX function */
1041         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1042                 i40e_set_rx_function(dev);
1043                 i40e_set_tx_function(dev);
1044                 return 0;
1045         }
1046         pci_dev = I40E_DEV_TO_PCI(dev);
1047         intr_handle = &pci_dev->intr_handle;
1048
1049         rte_eth_copy_pci_info(dev, pci_dev);
1050         dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1051
1052         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1053         pf->adapter->eth_dev = dev;
1054         pf->dev_data = dev->data;
1055
1056         hw->back = I40E_PF_TO_ADAPTER(pf);
1057         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1058         if (!hw->hw_addr) {
1059                 PMD_INIT_LOG(ERR,
1060                         "Hardware is not available, as address is NULL");
1061                 return -ENODEV;
1062         }
1063
1064         hw->vendor_id = pci_dev->id.vendor_id;
1065         hw->device_id = pci_dev->id.device_id;
1066         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1067         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1068         hw->bus.device = pci_dev->addr.devid;
1069         hw->bus.func = pci_dev->addr.function;
1070         hw->adapter_stopped = 0;
1071
1072         /* Make sure all is clean before doing PF reset */
1073         i40e_clear_hw(hw);
1074
1075         /* Initialize the hardware */
1076         i40e_hw_init(dev);
1077
1078         /* Reset here to make sure all is clean for each PF */
1079         ret = i40e_pf_reset(hw);
1080         if (ret) {
1081                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1082                 return ret;
1083         }
1084
1085         /* Initialize the shared code (base driver) */
1086         ret = i40e_init_shared_code(hw);
1087         if (ret) {
1088                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1089                 return ret;
1090         }
1091
1092         /*
1093          * To work around the NVM issue, initialize registers
1094          * for flexible payload and packet type of QinQ by
1095          * software. It should be removed once issues are fixed
1096          * in NVM.
1097          */
1098         i40e_GLQF_reg_init(hw);
1099
1100         /* Initialize the input set for filters (hash and fd) to default value */
1101         i40e_filter_input_set_init(pf);
1102
1103         /* Initialize the parameters for adminq */
1104         i40e_init_adminq_parameter(hw);
1105         ret = i40e_init_adminq(hw);
1106         if (ret != I40E_SUCCESS) {
1107                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1108                 return -EIO;
1109         }
1110         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1111                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1112                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1113                      ((hw->nvm.version >> 12) & 0xf),
1114                      ((hw->nvm.version >> 4) & 0xff),
1115                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1116
1117         /* Need the special FW version to support floating VEB */
1118         config_floating_veb(dev);
1119         /* Clear PXE mode */
1120         i40e_clear_pxe_mode(hw);
1121         ret = i40e_dev_sync_phy_type(hw);
1122         if (ret) {
1123                 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1124                 goto err_sync_phy_type;
1125         }
1126         /*
1127          * On X710, performance number is far from the expectation on recent
1128          * firmware versions. The fix for this issue may not be integrated in
1129          * the following firmware version. So the workaround in software driver
1130          * is needed. It needs to modify the initial values of 3 internal only
1131          * registers. Note that the workaround can be removed when it is fixed
1132          * in firmware in the future.
1133          */
1134         i40e_configure_registers(hw);
1135
1136         /* Get hw capabilities */
1137         ret = i40e_get_cap(hw);
1138         if (ret != I40E_SUCCESS) {
1139                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1140                 goto err_get_capabilities;
1141         }
1142
1143         /* Initialize parameters for PF */
1144         ret = i40e_pf_parameter_init(dev);
1145         if (ret != 0) {
1146                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1147                 goto err_parameter_init;
1148         }
1149
1150         /* Initialize the queue management */
1151         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1152         if (ret < 0) {
1153                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1154                 goto err_qp_pool_init;
1155         }
1156         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1157                                 hw->func_caps.num_msix_vectors - 1);
1158         if (ret < 0) {
1159                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1160                 goto err_msix_pool_init;
1161         }
1162
1163         /* Initialize lan hmc */
1164         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1165                                 hw->func_caps.num_rx_qp, 0, 0);
1166         if (ret != I40E_SUCCESS) {
1167                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1168                 goto err_init_lan_hmc;
1169         }
1170
1171         /* Configure lan hmc */
1172         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1173         if (ret != I40E_SUCCESS) {
1174                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1175                 goto err_configure_lan_hmc;
1176         }
1177
1178         /* Get and check the mac address */
1179         i40e_get_mac_addr(hw, hw->mac.addr);
1180         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1181                 PMD_INIT_LOG(ERR, "mac address is not valid");
1182                 ret = -EIO;
1183                 goto err_get_mac_addr;
1184         }
1185         /* Copy the permanent MAC address */
1186         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1187                         (struct ether_addr *) hw->mac.perm_addr);
1188
1189         /* Disable flow control */
1190         hw->fc.requested_mode = I40E_FC_NONE;
1191         i40e_set_fc(hw, &aq_fail, TRUE);
1192
1193         /* Set the global registers with default ether type value */
1194         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1195         if (ret != I40E_SUCCESS) {
1196                 PMD_INIT_LOG(ERR,
1197                         "Failed to set the default outer VLAN ether type");
1198                 goto err_setup_pf_switch;
1199         }
1200
1201         /* PF setup, which includes VSI setup */
1202         ret = i40e_pf_setup(pf);
1203         if (ret) {
1204                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1205                 goto err_setup_pf_switch;
1206         }
1207
1208         /* reset all stats of the device, including pf and main vsi */
1209         i40e_dev_stats_reset(dev);
1210
1211         vsi = pf->main_vsi;
1212
1213         /* Disable double vlan by default */
1214         i40e_vsi_config_double_vlan(vsi, FALSE);
1215
1216         /* Disable S-TAG identification when floating_veb is disabled */
1217         if (!pf->floating_veb) {
1218                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1219                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1220                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1221                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1222                 }
1223         }
1224
1225         if (!vsi->max_macaddrs)
1226                 len = ETHER_ADDR_LEN;
1227         else
1228                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1229
1230         /* Should be after VSI initialized */
1231         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1232         if (!dev->data->mac_addrs) {
1233                 PMD_INIT_LOG(ERR,
1234                         "Failed to allocated memory for storing mac address");
1235                 goto err_mac_alloc;
1236         }
1237         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1238                                         &dev->data->mac_addrs[0]);
1239
1240         /* initialize pf host driver to setup SRIOV resource if applicable */
1241         i40e_pf_host_init(dev);
1242
1243         /* register callback func to eal lib */
1244         rte_intr_callback_register(intr_handle,
1245                                    i40e_dev_interrupt_handler, dev);
1246
1247         /* configure and enable device interrupt */
1248         i40e_pf_config_irq0(hw, TRUE);
1249         i40e_pf_enable_irq0(hw);
1250
1251         /* enable uio intr after callback register */
1252         rte_intr_enable(intr_handle);
1253         /*
1254          * Add an ethertype filter to drop all flow control frames transmitted
1255          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1256          * frames to wire.
1257          */
1258         i40e_add_tx_flow_control_drop_filter(pf);
1259
1260         /* Set the max frame size to 0x2600 by default,
1261          * in case other drivers changed the default value.
1262          */
1263         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1264
1265         /* initialize mirror rule list */
1266         TAILQ_INIT(&pf->mirror_list);
1267
1268         /* Init dcb to sw mode by default */
1269         ret = i40e_dcb_init_configure(dev, TRUE);
1270         if (ret != I40E_SUCCESS) {
1271                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1272                 pf->flags &= ~I40E_FLAG_DCB;
1273         }
1274
1275         ret = i40e_init_ethtype_filter_list(dev);
1276         if (ret < 0)
1277                 goto err_init_ethtype_filter_list;
1278         ret = i40e_init_tunnel_filter_list(dev);
1279         if (ret < 0)
1280                 goto err_init_tunnel_filter_list;
1281         ret = i40e_init_fdir_filter_list(dev);
1282         if (ret < 0)
1283                 goto err_init_fdir_filter_list;
1284
1285         return 0;
1286
1287 err_init_fdir_filter_list:
1288         rte_free(pf->tunnel.hash_table);
1289         rte_free(pf->tunnel.hash_map);
1290 err_init_tunnel_filter_list:
1291         rte_free(pf->ethertype.hash_table);
1292         rte_free(pf->ethertype.hash_map);
1293 err_init_ethtype_filter_list:
1294         rte_free(dev->data->mac_addrs);
1295 err_mac_alloc:
1296         i40e_vsi_release(pf->main_vsi);
1297 err_setup_pf_switch:
1298 err_get_mac_addr:
1299 err_configure_lan_hmc:
1300         (void)i40e_shutdown_lan_hmc(hw);
1301 err_init_lan_hmc:
1302         i40e_res_pool_destroy(&pf->msix_pool);
1303 err_msix_pool_init:
1304         i40e_res_pool_destroy(&pf->qp_pool);
1305 err_qp_pool_init:
1306 err_parameter_init:
1307 err_get_capabilities:
1308 err_sync_phy_type:
1309         (void)i40e_shutdown_adminq(hw);
1310
1311         return ret;
1312 }
1313
1314 static void
1315 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1316 {
1317         struct i40e_ethertype_filter *p_ethertype;
1318         struct i40e_ethertype_rule *ethertype_rule;
1319
1320         ethertype_rule = &pf->ethertype;
1321         /* Remove all ethertype filter rules and hash */
1322         if (ethertype_rule->hash_map)
1323                 rte_free(ethertype_rule->hash_map);
1324         if (ethertype_rule->hash_table)
1325                 rte_hash_free(ethertype_rule->hash_table);
1326
1327         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1328                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1329                              p_ethertype, rules);
1330                 rte_free(p_ethertype);
1331         }
1332 }
1333
1334 static void
1335 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1336 {
1337         struct i40e_tunnel_filter *p_tunnel;
1338         struct i40e_tunnel_rule *tunnel_rule;
1339
1340         tunnel_rule = &pf->tunnel;
1341         /* Remove all tunnel director rules and hash */
1342         if (tunnel_rule->hash_map)
1343                 rte_free(tunnel_rule->hash_map);
1344         if (tunnel_rule->hash_table)
1345                 rte_hash_free(tunnel_rule->hash_table);
1346
1347         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1348                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1349                 rte_free(p_tunnel);
1350         }
1351 }
1352
1353 static void
1354 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1355 {
1356         struct i40e_fdir_filter *p_fdir;
1357         struct i40e_fdir_info *fdir_info;
1358
1359         fdir_info = &pf->fdir;
1360         /* Remove all flow director rules and hash */
1361         if (fdir_info->hash_map)
1362                 rte_free(fdir_info->hash_map);
1363         if (fdir_info->hash_table)
1364                 rte_hash_free(fdir_info->hash_table);
1365
1366         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1367                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1368                 rte_free(p_fdir);
1369         }
1370 }
1371
1372 static int
1373 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1374 {
1375         struct i40e_pf *pf;
1376         struct rte_pci_device *pci_dev;
1377         struct rte_intr_handle *intr_handle;
1378         struct i40e_hw *hw;
1379         struct i40e_filter_control_settings settings;
1380         struct rte_flow *p_flow;
1381         int ret;
1382         uint8_t aq_fail = 0;
1383
1384         PMD_INIT_FUNC_TRACE();
1385
1386         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1387                 return 0;
1388
1389         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1390         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1391         pci_dev = I40E_DEV_TO_PCI(dev);
1392         intr_handle = &pci_dev->intr_handle;
1393
1394         if (hw->adapter_stopped == 0)
1395                 i40e_dev_close(dev);
1396
1397         dev->dev_ops = NULL;
1398         dev->rx_pkt_burst = NULL;
1399         dev->tx_pkt_burst = NULL;
1400
1401         /* Clear PXE mode */
1402         i40e_clear_pxe_mode(hw);
1403
1404         /* Unconfigure filter control */
1405         memset(&settings, 0, sizeof(settings));
1406         ret = i40e_set_filter_control(hw, &settings);
1407         if (ret)
1408                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1409                                         ret);
1410
1411         /* Disable flow control */
1412         hw->fc.requested_mode = I40E_FC_NONE;
1413         i40e_set_fc(hw, &aq_fail, TRUE);
1414
1415         /* uninitialize pf host driver */
1416         i40e_pf_host_uninit(dev);
1417
1418         rte_free(dev->data->mac_addrs);
1419         dev->data->mac_addrs = NULL;
1420
1421         /* disable uio intr before callback unregister */
1422         rte_intr_disable(intr_handle);
1423
1424         /* register callback func to eal lib */
1425         rte_intr_callback_unregister(intr_handle,
1426                                      i40e_dev_interrupt_handler, dev);
1427
1428         i40e_rm_ethtype_filter_list(pf);
1429         i40e_rm_tunnel_filter_list(pf);
1430         i40e_rm_fdir_filter_list(pf);
1431
1432         /* Remove all flows */
1433         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1434                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1435                 rte_free(p_flow);
1436         }
1437
1438         return 0;
1439 }
1440
1441 static int
1442 i40e_dev_configure(struct rte_eth_dev *dev)
1443 {
1444         struct i40e_adapter *ad =
1445                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1446         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1447         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1448         int i, ret;
1449
1450         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1451          * bulk allocation or vector Rx preconditions we will reset it.
1452          */
1453         ad->rx_bulk_alloc_allowed = true;
1454         ad->rx_vec_allowed = true;
1455         ad->tx_simple_allowed = true;
1456         ad->tx_vec_allowed = true;
1457
1458         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1459                 ret = i40e_fdir_setup(pf);
1460                 if (ret != I40E_SUCCESS) {
1461                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1462                         return -ENOTSUP;
1463                 }
1464                 ret = i40e_fdir_configure(dev);
1465                 if (ret < 0) {
1466                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1467                         goto err;
1468                 }
1469         } else
1470                 i40e_fdir_teardown(pf);
1471
1472         ret = i40e_dev_init_vlan(dev);
1473         if (ret < 0)
1474                 goto err;
1475
1476         /* VMDQ setup.
1477          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1478          *  RSS setting have different requirements.
1479          *  General PMD driver call sequence are NIC init, configure,
1480          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1481          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1482          *  applicable. So, VMDQ setting has to be done before
1483          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1484          *  For RSS setting, it will try to calculate actual configured RX queue
1485          *  number, which will be available after rx_queue_setup(). dev_start()
1486          *  function is good to place RSS setup.
1487          */
1488         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1489                 ret = i40e_vmdq_setup(dev);
1490                 if (ret)
1491                         goto err;
1492         }
1493
1494         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1495                 ret = i40e_dcb_setup(dev);
1496                 if (ret) {
1497                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1498                         goto err_dcb;
1499                 }
1500         }
1501
1502         TAILQ_INIT(&pf->flow_list);
1503
1504         return 0;
1505
1506 err_dcb:
1507         /* need to release vmdq resource if exists */
1508         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1509                 i40e_vsi_release(pf->vmdq[i].vsi);
1510                 pf->vmdq[i].vsi = NULL;
1511         }
1512         rte_free(pf->vmdq);
1513         pf->vmdq = NULL;
1514 err:
1515         /* need to release fdir resource if exists */
1516         i40e_fdir_teardown(pf);
1517         return ret;
1518 }
1519
1520 void
1521 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1522 {
1523         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1524         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1525         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1526         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1527         uint16_t msix_vect = vsi->msix_intr;
1528         uint16_t i;
1529
1530         for (i = 0; i < vsi->nb_qps; i++) {
1531                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1532                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1533                 rte_wmb();
1534         }
1535
1536         if (vsi->type != I40E_VSI_SRIOV) {
1537                 if (!rte_intr_allow_others(intr_handle)) {
1538                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1539                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1540                         I40E_WRITE_REG(hw,
1541                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1542                                        0);
1543                 } else {
1544                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1545                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1546                         I40E_WRITE_REG(hw,
1547                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1548                                                        msix_vect - 1), 0);
1549                 }
1550         } else {
1551                 uint32_t reg;
1552                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1553                         vsi->user_param + (msix_vect - 1);
1554
1555                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1556                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1557         }
1558         I40E_WRITE_FLUSH(hw);
1559 }
1560
1561 static void
1562 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1563                        int base_queue, int nb_queue)
1564 {
1565         int i;
1566         uint32_t val;
1567         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1568
1569         /* Bind all RX queues to allocated MSIX interrupt */
1570         for (i = 0; i < nb_queue; i++) {
1571                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1572                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1573                         ((base_queue + i + 1) <<
1574                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1575                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1576                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1577
1578                 if (i == nb_queue - 1)
1579                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1580                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1581         }
1582
1583         /* Write first RX queue to Link list register as the head element */
1584         if (vsi->type != I40E_VSI_SRIOV) {
1585                 uint16_t interval =
1586                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1587
1588                 if (msix_vect == I40E_MISC_VEC_ID) {
1589                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1590                                        (base_queue <<
1591                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1592                                        (0x0 <<
1593                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1594                         I40E_WRITE_REG(hw,
1595                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1596                                        interval);
1597                 } else {
1598                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1599                                        (base_queue <<
1600                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1601                                        (0x0 <<
1602                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1603                         I40E_WRITE_REG(hw,
1604                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1605                                                        msix_vect - 1),
1606                                        interval);
1607                 }
1608         } else {
1609                 uint32_t reg;
1610
1611                 if (msix_vect == I40E_MISC_VEC_ID) {
1612                         I40E_WRITE_REG(hw,
1613                                        I40E_VPINT_LNKLST0(vsi->user_param),
1614                                        (base_queue <<
1615                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1616                                        (0x0 <<
1617                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1618                 } else {
1619                         /* num_msix_vectors_vf needs to minus irq0 */
1620                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1621                                 vsi->user_param + (msix_vect - 1);
1622
1623                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1624                                        (base_queue <<
1625                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1626                                        (0x0 <<
1627                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1628                 }
1629         }
1630
1631         I40E_WRITE_FLUSH(hw);
1632 }
1633
1634 void
1635 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1636 {
1637         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1638         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1639         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1640         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1641         uint16_t msix_vect = vsi->msix_intr;
1642         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1643         uint16_t queue_idx = 0;
1644         int record = 0;
1645         uint32_t val;
1646         int i;
1647
1648         for (i = 0; i < vsi->nb_qps; i++) {
1649                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1650                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1651         }
1652
1653         /* INTENA flag is not auto-cleared for interrupt */
1654         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1655         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1656                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1657                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1658         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1659
1660         /* VF bind interrupt */
1661         if (vsi->type == I40E_VSI_SRIOV) {
1662                 __vsi_queues_bind_intr(vsi, msix_vect,
1663                                        vsi->base_queue, vsi->nb_qps);
1664                 return;
1665         }
1666
1667         /* PF & VMDq bind interrupt */
1668         if (rte_intr_dp_is_en(intr_handle)) {
1669                 if (vsi->type == I40E_VSI_MAIN) {
1670                         queue_idx = 0;
1671                         record = 1;
1672                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1673                         struct i40e_vsi *main_vsi =
1674                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1675                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1676                         record = 1;
1677                 }
1678         }
1679
1680         for (i = 0; i < vsi->nb_used_qps; i++) {
1681                 if (nb_msix <= 1) {
1682                         if (!rte_intr_allow_others(intr_handle))
1683                                 /* allow to share MISC_VEC_ID */
1684                                 msix_vect = I40E_MISC_VEC_ID;
1685
1686                         /* no enough msix_vect, map all to one */
1687                         __vsi_queues_bind_intr(vsi, msix_vect,
1688                                                vsi->base_queue + i,
1689                                                vsi->nb_used_qps - i);
1690                         for (; !!record && i < vsi->nb_used_qps; i++)
1691                                 intr_handle->intr_vec[queue_idx + i] =
1692                                         msix_vect;
1693                         break;
1694                 }
1695                 /* 1:1 queue/msix_vect mapping */
1696                 __vsi_queues_bind_intr(vsi, msix_vect,
1697                                        vsi->base_queue + i, 1);
1698                 if (!!record)
1699                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1700
1701                 msix_vect++;
1702                 nb_msix--;
1703         }
1704 }
1705
1706 static void
1707 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1708 {
1709         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1710         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1711         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1712         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1713         uint16_t interval = i40e_calc_itr_interval(\
1714                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1715         uint16_t msix_intr, i;
1716
1717         if (rte_intr_allow_others(intr_handle))
1718                 for (i = 0; i < vsi->nb_msix; i++) {
1719                         msix_intr = vsi->msix_intr + i;
1720                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1721                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1722                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1723                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1724                                 (interval <<
1725                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1726                 }
1727         else
1728                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1729                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1730                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1731                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1732                                (interval <<
1733                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1734
1735         I40E_WRITE_FLUSH(hw);
1736 }
1737
1738 static void
1739 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1740 {
1741         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1742         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1743         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1744         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1745         uint16_t msix_intr, i;
1746
1747         if (rte_intr_allow_others(intr_handle))
1748                 for (i = 0; i < vsi->nb_msix; i++) {
1749                         msix_intr = vsi->msix_intr + i;
1750                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1751                                        0);
1752                 }
1753         else
1754                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1755
1756         I40E_WRITE_FLUSH(hw);
1757 }
1758
1759 static inline uint8_t
1760 i40e_parse_link_speeds(uint16_t link_speeds)
1761 {
1762         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1763
1764         if (link_speeds & ETH_LINK_SPEED_40G)
1765                 link_speed |= I40E_LINK_SPEED_40GB;
1766         if (link_speeds & ETH_LINK_SPEED_25G)
1767                 link_speed |= I40E_LINK_SPEED_25GB;
1768         if (link_speeds & ETH_LINK_SPEED_20G)
1769                 link_speed |= I40E_LINK_SPEED_20GB;
1770         if (link_speeds & ETH_LINK_SPEED_10G)
1771                 link_speed |= I40E_LINK_SPEED_10GB;
1772         if (link_speeds & ETH_LINK_SPEED_1G)
1773                 link_speed |= I40E_LINK_SPEED_1GB;
1774         if (link_speeds & ETH_LINK_SPEED_100M)
1775                 link_speed |= I40E_LINK_SPEED_100MB;
1776
1777         return link_speed;
1778 }
1779
1780 static int
1781 i40e_phy_conf_link(struct i40e_hw *hw,
1782                    uint8_t abilities,
1783                    uint8_t force_speed)
1784 {
1785         enum i40e_status_code status;
1786         struct i40e_aq_get_phy_abilities_resp phy_ab;
1787         struct i40e_aq_set_phy_config phy_conf;
1788         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1789                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1790                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1791                         I40E_AQ_PHY_FLAG_LOW_POWER;
1792         const uint8_t advt = I40E_LINK_SPEED_40GB |
1793                         I40E_LINK_SPEED_25GB |
1794                         I40E_LINK_SPEED_10GB |
1795                         I40E_LINK_SPEED_1GB |
1796                         I40E_LINK_SPEED_100MB;
1797         int ret = -ENOTSUP;
1798
1799
1800         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1801                                               NULL);
1802         if (status)
1803                 return ret;
1804
1805         memset(&phy_conf, 0, sizeof(phy_conf));
1806
1807         /* bits 0-2 use the values from get_phy_abilities_resp */
1808         abilities &= ~mask;
1809         abilities |= phy_ab.abilities & mask;
1810
1811         /* update ablities and speed */
1812         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1813                 phy_conf.link_speed = advt;
1814         else
1815                 phy_conf.link_speed = force_speed;
1816
1817         phy_conf.abilities = abilities;
1818
1819         /* use get_phy_abilities_resp value for the rest */
1820         phy_conf.phy_type = phy_ab.phy_type;
1821         phy_conf.phy_type_ext = phy_ab.phy_type_ext;
1822         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1823         phy_conf.eee_capability = phy_ab.eee_capability;
1824         phy_conf.eeer = phy_ab.eeer_val;
1825         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1826
1827         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1828                     phy_ab.abilities, phy_ab.link_speed);
1829         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1830                     phy_conf.abilities, phy_conf.link_speed);
1831
1832         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1833         if (status)
1834                 return ret;
1835
1836         return I40E_SUCCESS;
1837 }
1838
1839 static int
1840 i40e_apply_link_speed(struct rte_eth_dev *dev)
1841 {
1842         uint8_t speed;
1843         uint8_t abilities = 0;
1844         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1845         struct rte_eth_conf *conf = &dev->data->dev_conf;
1846
1847         speed = i40e_parse_link_speeds(conf->link_speeds);
1848         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1849         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1850                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1851         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1852
1853         /* Skip changing speed on 40G interfaces, FW does not support */
1854         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1855                 speed =  I40E_LINK_SPEED_UNKNOWN;
1856                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1857         }
1858
1859         return i40e_phy_conf_link(hw, abilities, speed);
1860 }
1861
1862 static int
1863 i40e_dev_start(struct rte_eth_dev *dev)
1864 {
1865         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1866         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1867         struct i40e_vsi *main_vsi = pf->main_vsi;
1868         int ret, i;
1869         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1870         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1871         uint32_t intr_vector = 0;
1872
1873         hw->adapter_stopped = 0;
1874
1875         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1876                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1877                              dev->data->port_id);
1878                 return -EINVAL;
1879         }
1880
1881         rte_intr_disable(intr_handle);
1882
1883         if ((rte_intr_cap_multiple(intr_handle) ||
1884              !RTE_ETH_DEV_SRIOV(dev).active) &&
1885             dev->data->dev_conf.intr_conf.rxq != 0) {
1886                 intr_vector = dev->data->nb_rx_queues;
1887                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1888                 if (ret)
1889                         return ret;
1890         }
1891
1892         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1893                 intr_handle->intr_vec =
1894                         rte_zmalloc("intr_vec",
1895                                     dev->data->nb_rx_queues * sizeof(int),
1896                                     0);
1897                 if (!intr_handle->intr_vec) {
1898                         PMD_INIT_LOG(ERR,
1899                                 "Failed to allocate %d rx_queues intr_vec",
1900                                 dev->data->nb_rx_queues);
1901                         return -ENOMEM;
1902                 }
1903         }
1904
1905         /* Initialize VSI */
1906         ret = i40e_dev_rxtx_init(pf);
1907         if (ret != I40E_SUCCESS) {
1908                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1909                 goto err_up;
1910         }
1911
1912         /* Map queues with MSIX interrupt */
1913         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1914                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1915         i40e_vsi_queues_bind_intr(main_vsi);
1916         i40e_vsi_enable_queues_intr(main_vsi);
1917
1918         /* Map VMDQ VSI queues with MSIX interrupt */
1919         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1920                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1921                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1922                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1923         }
1924
1925         /* enable FDIR MSIX interrupt */
1926         if (pf->fdir.fdir_vsi) {
1927                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1928                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1929         }
1930
1931         /* Enable all queues which have been configured */
1932         ret = i40e_dev_switch_queues(pf, TRUE);
1933         if (ret != I40E_SUCCESS) {
1934                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1935                 goto err_up;
1936         }
1937
1938         /* Enable receiving broadcast packets */
1939         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1940         if (ret != I40E_SUCCESS)
1941                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1942
1943         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1944                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1945                                                 true, NULL);
1946                 if (ret != I40E_SUCCESS)
1947                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1948         }
1949
1950         /* Apply link configure */
1951         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1952                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1953                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1954                                 ETH_LINK_SPEED_40G)) {
1955                 PMD_DRV_LOG(ERR, "Invalid link setting");
1956                 goto err_up;
1957         }
1958         ret = i40e_apply_link_speed(dev);
1959         if (I40E_SUCCESS != ret) {
1960                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1961                 goto err_up;
1962         }
1963
1964         if (!rte_intr_allow_others(intr_handle)) {
1965                 rte_intr_callback_unregister(intr_handle,
1966                                              i40e_dev_interrupt_handler,
1967                                              (void *)dev);
1968                 /* configure and enable device interrupt */
1969                 i40e_pf_config_irq0(hw, FALSE);
1970                 i40e_pf_enable_irq0(hw);
1971
1972                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1973                         PMD_INIT_LOG(INFO,
1974                                 "lsc won't enable because of no intr multiplex");
1975         } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
1976                 ret = i40e_aq_set_phy_int_mask(hw,
1977                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
1978                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
1979                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
1980                 if (ret != I40E_SUCCESS)
1981                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
1982
1983                 /* Call get_link_info aq commond to enable LSE */
1984                 i40e_dev_link_update(dev, 0);
1985         }
1986
1987         /* enable uio intr after callback register */
1988         rte_intr_enable(intr_handle);
1989
1990         i40e_filter_restore(pf);
1991
1992         return I40E_SUCCESS;
1993
1994 err_up:
1995         i40e_dev_switch_queues(pf, FALSE);
1996         i40e_dev_clear_queues(dev);
1997
1998         return ret;
1999 }
2000
2001 static void
2002 i40e_dev_stop(struct rte_eth_dev *dev)
2003 {
2004         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2005         struct i40e_vsi *main_vsi = pf->main_vsi;
2006         struct i40e_mirror_rule *p_mirror;
2007         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2008         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2009         int i;
2010
2011         /* Disable all queues */
2012         i40e_dev_switch_queues(pf, FALSE);
2013
2014         /* un-map queues with interrupt registers */
2015         i40e_vsi_disable_queues_intr(main_vsi);
2016         i40e_vsi_queues_unbind_intr(main_vsi);
2017
2018         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2019                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2020                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2021         }
2022
2023         if (pf->fdir.fdir_vsi) {
2024                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2025                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2026         }
2027         /* Clear all queues and release memory */
2028         i40e_dev_clear_queues(dev);
2029
2030         /* Set link down */
2031         i40e_dev_set_link_down(dev);
2032
2033         /* Remove all mirror rules */
2034         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2035                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2036                 rte_free(p_mirror);
2037         }
2038         pf->nb_mirror_rule = 0;
2039
2040         if (!rte_intr_allow_others(intr_handle))
2041                 /* resume to the default handler */
2042                 rte_intr_callback_register(intr_handle,
2043                                            i40e_dev_interrupt_handler,
2044                                            (void *)dev);
2045
2046         /* Clean datapath event and queue/vec mapping */
2047         rte_intr_efd_disable(intr_handle);
2048         if (intr_handle->intr_vec) {
2049                 rte_free(intr_handle->intr_vec);
2050                 intr_handle->intr_vec = NULL;
2051         }
2052 }
2053
2054 static void
2055 i40e_dev_close(struct rte_eth_dev *dev)
2056 {
2057         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2058         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2059         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2060         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2061         uint32_t reg;
2062         int i;
2063
2064         PMD_INIT_FUNC_TRACE();
2065
2066         i40e_dev_stop(dev);
2067         hw->adapter_stopped = 1;
2068         i40e_dev_free_queues(dev);
2069
2070         /* Disable interrupt */
2071         i40e_pf_disable_irq0(hw);
2072         rte_intr_disable(intr_handle);
2073
2074         /* shutdown and destroy the HMC */
2075         i40e_shutdown_lan_hmc(hw);
2076
2077         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2078                 i40e_vsi_release(pf->vmdq[i].vsi);
2079                 pf->vmdq[i].vsi = NULL;
2080         }
2081         rte_free(pf->vmdq);
2082         pf->vmdq = NULL;
2083
2084         /* release all the existing VSIs and VEBs */
2085         i40e_fdir_teardown(pf);
2086         i40e_vsi_release(pf->main_vsi);
2087
2088         /* shutdown the adminq */
2089         i40e_aq_queue_shutdown(hw, true);
2090         i40e_shutdown_adminq(hw);
2091
2092         i40e_res_pool_destroy(&pf->qp_pool);
2093         i40e_res_pool_destroy(&pf->msix_pool);
2094
2095         /* force a PF reset to clean anything leftover */
2096         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2097         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2098                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2099         I40E_WRITE_FLUSH(hw);
2100 }
2101
2102 static void
2103 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2104 {
2105         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2106         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2107         struct i40e_vsi *vsi = pf->main_vsi;
2108         int status;
2109
2110         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2111                                                      true, NULL, true);
2112         if (status != I40E_SUCCESS)
2113                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2114
2115         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2116                                                         TRUE, NULL);
2117         if (status != I40E_SUCCESS)
2118                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2119
2120 }
2121
2122 static void
2123 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2124 {
2125         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2126         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2127         struct i40e_vsi *vsi = pf->main_vsi;
2128         int status;
2129
2130         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2131                                                      false, NULL, true);
2132         if (status != I40E_SUCCESS)
2133                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2134
2135         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2136                                                         false, NULL);
2137         if (status != I40E_SUCCESS)
2138                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2139 }
2140
2141 static void
2142 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2143 {
2144         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2145         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2146         struct i40e_vsi *vsi = pf->main_vsi;
2147         int ret;
2148
2149         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2150         if (ret != I40E_SUCCESS)
2151                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2152 }
2153
2154 static void
2155 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2156 {
2157         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2158         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2159         struct i40e_vsi *vsi = pf->main_vsi;
2160         int ret;
2161
2162         if (dev->data->promiscuous == 1)
2163                 return; /* must remain in all_multicast mode */
2164
2165         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2166                                 vsi->seid, FALSE, NULL);
2167         if (ret != I40E_SUCCESS)
2168                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2169 }
2170
2171 /*
2172  * Set device link up.
2173  */
2174 static int
2175 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2176 {
2177         /* re-apply link speed setting */
2178         return i40e_apply_link_speed(dev);
2179 }
2180
2181 /*
2182  * Set device link down.
2183  */
2184 static int
2185 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2186 {
2187         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2188         uint8_t abilities = 0;
2189         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2190
2191         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2192         return i40e_phy_conf_link(hw, abilities, speed);
2193 }
2194
2195 int
2196 i40e_dev_link_update(struct rte_eth_dev *dev,
2197                      int wait_to_complete)
2198 {
2199 #define CHECK_INTERVAL 100  /* 100ms */
2200 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2201         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2202         struct i40e_link_status link_status;
2203         struct rte_eth_link link, old;
2204         int status;
2205         unsigned rep_cnt = MAX_REPEAT_TIME;
2206         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2207
2208         memset(&link, 0, sizeof(link));
2209         memset(&old, 0, sizeof(old));
2210         memset(&link_status, 0, sizeof(link_status));
2211         rte_i40e_dev_atomic_read_link_status(dev, &old);
2212
2213         do {
2214                 /* Get link status information from hardware */
2215                 status = i40e_aq_get_link_info(hw, enable_lse,
2216                                                 &link_status, NULL);
2217                 if (status != I40E_SUCCESS) {
2218                         link.link_speed = ETH_SPEED_NUM_100M;
2219                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2220                         PMD_DRV_LOG(ERR, "Failed to get link info");
2221                         goto out;
2222                 }
2223
2224                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2225                 if (!wait_to_complete || link.link_status)
2226                         break;
2227
2228                 rte_delay_ms(CHECK_INTERVAL);
2229         } while (--rep_cnt);
2230
2231         if (!link.link_status)
2232                 goto out;
2233
2234         /* i40e uses full duplex only */
2235         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2236
2237         /* Parse the link status */
2238         switch (link_status.link_speed) {
2239         case I40E_LINK_SPEED_100MB:
2240                 link.link_speed = ETH_SPEED_NUM_100M;
2241                 break;
2242         case I40E_LINK_SPEED_1GB:
2243                 link.link_speed = ETH_SPEED_NUM_1G;
2244                 break;
2245         case I40E_LINK_SPEED_10GB:
2246                 link.link_speed = ETH_SPEED_NUM_10G;
2247                 break;
2248         case I40E_LINK_SPEED_20GB:
2249                 link.link_speed = ETH_SPEED_NUM_20G;
2250                 break;
2251         case I40E_LINK_SPEED_25GB:
2252                 link.link_speed = ETH_SPEED_NUM_25G;
2253                 break;
2254         case I40E_LINK_SPEED_40GB:
2255                 link.link_speed = ETH_SPEED_NUM_40G;
2256                 break;
2257         default:
2258                 link.link_speed = ETH_SPEED_NUM_100M;
2259                 break;
2260         }
2261
2262         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2263                         ETH_LINK_SPEED_FIXED);
2264
2265 out:
2266         rte_i40e_dev_atomic_write_link_status(dev, &link);
2267         if (link.link_status == old.link_status)
2268                 return -1;
2269
2270         return 0;
2271 }
2272
2273 /* Get all the statistics of a VSI */
2274 void
2275 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2276 {
2277         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2278         struct i40e_eth_stats *nes = &vsi->eth_stats;
2279         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2280         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2281
2282         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2283                             vsi->offset_loaded, &oes->rx_bytes,
2284                             &nes->rx_bytes);
2285         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2286                             vsi->offset_loaded, &oes->rx_unicast,
2287                             &nes->rx_unicast);
2288         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2289                             vsi->offset_loaded, &oes->rx_multicast,
2290                             &nes->rx_multicast);
2291         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2292                             vsi->offset_loaded, &oes->rx_broadcast,
2293                             &nes->rx_broadcast);
2294         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2295                             &oes->rx_discards, &nes->rx_discards);
2296         /* GLV_REPC not supported */
2297         /* GLV_RMPC not supported */
2298         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2299                             &oes->rx_unknown_protocol,
2300                             &nes->rx_unknown_protocol);
2301         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2302                             vsi->offset_loaded, &oes->tx_bytes,
2303                             &nes->tx_bytes);
2304         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2305                             vsi->offset_loaded, &oes->tx_unicast,
2306                             &nes->tx_unicast);
2307         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2308                             vsi->offset_loaded, &oes->tx_multicast,
2309                             &nes->tx_multicast);
2310         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2311                             vsi->offset_loaded,  &oes->tx_broadcast,
2312                             &nes->tx_broadcast);
2313         /* GLV_TDPC not supported */
2314         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2315                             &oes->tx_errors, &nes->tx_errors);
2316         vsi->offset_loaded = true;
2317
2318         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2319                     vsi->vsi_id);
2320         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2321         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2322         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2323         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2324         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2325         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2326                     nes->rx_unknown_protocol);
2327         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2328         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2329         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2330         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2331         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2332         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2333         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2334                     vsi->vsi_id);
2335 }
2336
2337 static void
2338 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2339 {
2340         unsigned int i;
2341         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2342         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2343
2344         /* Get statistics of struct i40e_eth_stats */
2345         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2346                             I40E_GLPRT_GORCL(hw->port),
2347                             pf->offset_loaded, &os->eth.rx_bytes,
2348                             &ns->eth.rx_bytes);
2349         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2350                             I40E_GLPRT_UPRCL(hw->port),
2351                             pf->offset_loaded, &os->eth.rx_unicast,
2352                             &ns->eth.rx_unicast);
2353         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2354                             I40E_GLPRT_MPRCL(hw->port),
2355                             pf->offset_loaded, &os->eth.rx_multicast,
2356                             &ns->eth.rx_multicast);
2357         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2358                             I40E_GLPRT_BPRCL(hw->port),
2359                             pf->offset_loaded, &os->eth.rx_broadcast,
2360                             &ns->eth.rx_broadcast);
2361         /* Workaround: CRC size should not be included in byte statistics,
2362          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2363          */
2364         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2365                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2366
2367         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2368                             pf->offset_loaded, &os->eth.rx_discards,
2369                             &ns->eth.rx_discards);
2370         /* GLPRT_REPC not supported */
2371         /* GLPRT_RMPC not supported */
2372         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2373                             pf->offset_loaded,
2374                             &os->eth.rx_unknown_protocol,
2375                             &ns->eth.rx_unknown_protocol);
2376         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2377                             I40E_GLPRT_GOTCL(hw->port),
2378                             pf->offset_loaded, &os->eth.tx_bytes,
2379                             &ns->eth.tx_bytes);
2380         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2381                             I40E_GLPRT_UPTCL(hw->port),
2382                             pf->offset_loaded, &os->eth.tx_unicast,
2383                             &ns->eth.tx_unicast);
2384         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2385                             I40E_GLPRT_MPTCL(hw->port),
2386                             pf->offset_loaded, &os->eth.tx_multicast,
2387                             &ns->eth.tx_multicast);
2388         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2389                             I40E_GLPRT_BPTCL(hw->port),
2390                             pf->offset_loaded, &os->eth.tx_broadcast,
2391                             &ns->eth.tx_broadcast);
2392         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2393                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2394         /* GLPRT_TEPC not supported */
2395
2396         /* additional port specific stats */
2397         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2398                             pf->offset_loaded, &os->tx_dropped_link_down,
2399                             &ns->tx_dropped_link_down);
2400         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2401                             pf->offset_loaded, &os->crc_errors,
2402                             &ns->crc_errors);
2403         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2404                             pf->offset_loaded, &os->illegal_bytes,
2405                             &ns->illegal_bytes);
2406         /* GLPRT_ERRBC not supported */
2407         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2408                             pf->offset_loaded, &os->mac_local_faults,
2409                             &ns->mac_local_faults);
2410         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2411                             pf->offset_loaded, &os->mac_remote_faults,
2412                             &ns->mac_remote_faults);
2413         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2414                             pf->offset_loaded, &os->rx_length_errors,
2415                             &ns->rx_length_errors);
2416         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2417                             pf->offset_loaded, &os->link_xon_rx,
2418                             &ns->link_xon_rx);
2419         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2420                             pf->offset_loaded, &os->link_xoff_rx,
2421                             &ns->link_xoff_rx);
2422         for (i = 0; i < 8; i++) {
2423                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2424                                     pf->offset_loaded,
2425                                     &os->priority_xon_rx[i],
2426                                     &ns->priority_xon_rx[i]);
2427                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2428                                     pf->offset_loaded,
2429                                     &os->priority_xoff_rx[i],
2430                                     &ns->priority_xoff_rx[i]);
2431         }
2432         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2433                             pf->offset_loaded, &os->link_xon_tx,
2434                             &ns->link_xon_tx);
2435         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2436                             pf->offset_loaded, &os->link_xoff_tx,
2437                             &ns->link_xoff_tx);
2438         for (i = 0; i < 8; i++) {
2439                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2440                                     pf->offset_loaded,
2441                                     &os->priority_xon_tx[i],
2442                                     &ns->priority_xon_tx[i]);
2443                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2444                                     pf->offset_loaded,
2445                                     &os->priority_xoff_tx[i],
2446                                     &ns->priority_xoff_tx[i]);
2447                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2448                                     pf->offset_loaded,
2449                                     &os->priority_xon_2_xoff[i],
2450                                     &ns->priority_xon_2_xoff[i]);
2451         }
2452         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2453                             I40E_GLPRT_PRC64L(hw->port),
2454                             pf->offset_loaded, &os->rx_size_64,
2455                             &ns->rx_size_64);
2456         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2457                             I40E_GLPRT_PRC127L(hw->port),
2458                             pf->offset_loaded, &os->rx_size_127,
2459                             &ns->rx_size_127);
2460         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2461                             I40E_GLPRT_PRC255L(hw->port),
2462                             pf->offset_loaded, &os->rx_size_255,
2463                             &ns->rx_size_255);
2464         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2465                             I40E_GLPRT_PRC511L(hw->port),
2466                             pf->offset_loaded, &os->rx_size_511,
2467                             &ns->rx_size_511);
2468         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2469                             I40E_GLPRT_PRC1023L(hw->port),
2470                             pf->offset_loaded, &os->rx_size_1023,
2471                             &ns->rx_size_1023);
2472         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2473                             I40E_GLPRT_PRC1522L(hw->port),
2474                             pf->offset_loaded, &os->rx_size_1522,
2475                             &ns->rx_size_1522);
2476         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2477                             I40E_GLPRT_PRC9522L(hw->port),
2478                             pf->offset_loaded, &os->rx_size_big,
2479                             &ns->rx_size_big);
2480         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2481                             pf->offset_loaded, &os->rx_undersize,
2482                             &ns->rx_undersize);
2483         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2484                             pf->offset_loaded, &os->rx_fragments,
2485                             &ns->rx_fragments);
2486         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2487                             pf->offset_loaded, &os->rx_oversize,
2488                             &ns->rx_oversize);
2489         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2490                             pf->offset_loaded, &os->rx_jabber,
2491                             &ns->rx_jabber);
2492         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2493                             I40E_GLPRT_PTC64L(hw->port),
2494                             pf->offset_loaded, &os->tx_size_64,
2495                             &ns->tx_size_64);
2496         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2497                             I40E_GLPRT_PTC127L(hw->port),
2498                             pf->offset_loaded, &os->tx_size_127,
2499                             &ns->tx_size_127);
2500         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2501                             I40E_GLPRT_PTC255L(hw->port),
2502                             pf->offset_loaded, &os->tx_size_255,
2503                             &ns->tx_size_255);
2504         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2505                             I40E_GLPRT_PTC511L(hw->port),
2506                             pf->offset_loaded, &os->tx_size_511,
2507                             &ns->tx_size_511);
2508         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2509                             I40E_GLPRT_PTC1023L(hw->port),
2510                             pf->offset_loaded, &os->tx_size_1023,
2511                             &ns->tx_size_1023);
2512         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2513                             I40E_GLPRT_PTC1522L(hw->port),
2514                             pf->offset_loaded, &os->tx_size_1522,
2515                             &ns->tx_size_1522);
2516         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2517                             I40E_GLPRT_PTC9522L(hw->port),
2518                             pf->offset_loaded, &os->tx_size_big,
2519                             &ns->tx_size_big);
2520         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2521                            pf->offset_loaded,
2522                            &os->fd_sb_match, &ns->fd_sb_match);
2523         /* GLPRT_MSPDC not supported */
2524         /* GLPRT_XEC not supported */
2525
2526         pf->offset_loaded = true;
2527
2528         if (pf->main_vsi)
2529                 i40e_update_vsi_stats(pf->main_vsi);
2530 }
2531
2532 /* Get all statistics of a port */
2533 static void
2534 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2535 {
2536         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2537         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2538         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2539         unsigned i;
2540
2541         /* call read registers - updates values, now write them to struct */
2542         i40e_read_stats_registers(pf, hw);
2543
2544         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2545                         pf->main_vsi->eth_stats.rx_multicast +
2546                         pf->main_vsi->eth_stats.rx_broadcast -
2547                         pf->main_vsi->eth_stats.rx_discards;
2548         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2549                         pf->main_vsi->eth_stats.tx_multicast +
2550                         pf->main_vsi->eth_stats.tx_broadcast;
2551         stats->ibytes   = ns->eth.rx_bytes;
2552         stats->obytes   = ns->eth.tx_bytes;
2553         stats->oerrors  = ns->eth.tx_errors +
2554                         pf->main_vsi->eth_stats.tx_errors;
2555
2556         /* Rx Errors */
2557         stats->imissed  = ns->eth.rx_discards +
2558                         pf->main_vsi->eth_stats.rx_discards;
2559         stats->ierrors  = ns->crc_errors +
2560                         ns->rx_length_errors + ns->rx_undersize +
2561                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2562
2563         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2564         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2565         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2566         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2567         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2568         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2569         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2570                     ns->eth.rx_unknown_protocol);
2571         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2572         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2573         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2574         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2575         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2576         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2577
2578         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2579                     ns->tx_dropped_link_down);
2580         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2581         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2582                     ns->illegal_bytes);
2583         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2584         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2585                     ns->mac_local_faults);
2586         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2587                     ns->mac_remote_faults);
2588         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2589                     ns->rx_length_errors);
2590         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2591         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2592         for (i = 0; i < 8; i++) {
2593                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2594                                 i, ns->priority_xon_rx[i]);
2595                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2596                                 i, ns->priority_xoff_rx[i]);
2597         }
2598         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2599         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2600         for (i = 0; i < 8; i++) {
2601                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2602                                 i, ns->priority_xon_tx[i]);
2603                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2604                                 i, ns->priority_xoff_tx[i]);
2605                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2606                                 i, ns->priority_xon_2_xoff[i]);
2607         }
2608         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2609         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2610         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2611         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2612         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2613         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2614         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2615         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2616         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2617         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2618         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2619         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2620         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2621         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2622         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2623         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2624         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2625         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2626         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2627                         ns->mac_short_packet_dropped);
2628         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2629                     ns->checksum_error);
2630         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2631         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2632 }
2633
2634 /* Reset the statistics */
2635 static void
2636 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2637 {
2638         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2639         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2640
2641         /* Mark PF and VSI stats to update the offset, aka "reset" */
2642         pf->offset_loaded = false;
2643         if (pf->main_vsi)
2644                 pf->main_vsi->offset_loaded = false;
2645
2646         /* read the stats, reading current register values into offset */
2647         i40e_read_stats_registers(pf, hw);
2648 }
2649
2650 static uint32_t
2651 i40e_xstats_calc_num(void)
2652 {
2653         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2654                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2655                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2656 }
2657
2658 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2659                                      struct rte_eth_xstat_name *xstats_names,
2660                                      __rte_unused unsigned limit)
2661 {
2662         unsigned count = 0;
2663         unsigned i, prio;
2664
2665         if (xstats_names == NULL)
2666                 return i40e_xstats_calc_num();
2667
2668         /* Note: limit checked in rte_eth_xstats_names() */
2669
2670         /* Get stats from i40e_eth_stats struct */
2671         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2672                 snprintf(xstats_names[count].name,
2673                          sizeof(xstats_names[count].name),
2674                          "%s", rte_i40e_stats_strings[i].name);
2675                 count++;
2676         }
2677
2678         /* Get individiual stats from i40e_hw_port struct */
2679         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2680                 snprintf(xstats_names[count].name,
2681                         sizeof(xstats_names[count].name),
2682                          "%s", rte_i40e_hw_port_strings[i].name);
2683                 count++;
2684         }
2685
2686         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2687                 for (prio = 0; prio < 8; prio++) {
2688                         snprintf(xstats_names[count].name,
2689                                  sizeof(xstats_names[count].name),
2690                                  "rx_priority%u_%s", prio,
2691                                  rte_i40e_rxq_prio_strings[i].name);
2692                         count++;
2693                 }
2694         }
2695
2696         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2697                 for (prio = 0; prio < 8; prio++) {
2698                         snprintf(xstats_names[count].name,
2699                                  sizeof(xstats_names[count].name),
2700                                  "tx_priority%u_%s", prio,
2701                                  rte_i40e_txq_prio_strings[i].name);
2702                         count++;
2703                 }
2704         }
2705         return count;
2706 }
2707
2708 static int
2709 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2710                     unsigned n)
2711 {
2712         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2713         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2714         unsigned i, count, prio;
2715         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2716
2717         count = i40e_xstats_calc_num();
2718         if (n < count)
2719                 return count;
2720
2721         i40e_read_stats_registers(pf, hw);
2722
2723         if (xstats == NULL)
2724                 return 0;
2725
2726         count = 0;
2727
2728         /* Get stats from i40e_eth_stats struct */
2729         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2730                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2731                         rte_i40e_stats_strings[i].offset);
2732                 xstats[count].id = count;
2733                 count++;
2734         }
2735
2736         /* Get individiual stats from i40e_hw_port struct */
2737         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2738                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2739                         rte_i40e_hw_port_strings[i].offset);
2740                 xstats[count].id = count;
2741                 count++;
2742         }
2743
2744         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2745                 for (prio = 0; prio < 8; prio++) {
2746                         xstats[count].value =
2747                                 *(uint64_t *)(((char *)hw_stats) +
2748                                 rte_i40e_rxq_prio_strings[i].offset +
2749                                 (sizeof(uint64_t) * prio));
2750                         xstats[count].id = count;
2751                         count++;
2752                 }
2753         }
2754
2755         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2756                 for (prio = 0; prio < 8; prio++) {
2757                         xstats[count].value =
2758                                 *(uint64_t *)(((char *)hw_stats) +
2759                                 rte_i40e_txq_prio_strings[i].offset +
2760                                 (sizeof(uint64_t) * prio));
2761                         xstats[count].id = count;
2762                         count++;
2763                 }
2764         }
2765
2766         return count;
2767 }
2768
2769 static int
2770 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2771                                  __rte_unused uint16_t queue_id,
2772                                  __rte_unused uint8_t stat_idx,
2773                                  __rte_unused uint8_t is_rx)
2774 {
2775         PMD_INIT_FUNC_TRACE();
2776
2777         return -ENOSYS;
2778 }
2779
2780 static int
2781 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2782 {
2783         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2784         u32 full_ver;
2785         u8 ver, patch;
2786         u16 build;
2787         int ret;
2788
2789         full_ver = hw->nvm.oem_ver;
2790         ver = (u8)(full_ver >> 24);
2791         build = (u16)((full_ver >> 8) & 0xffff);
2792         patch = (u8)(full_ver & 0xff);
2793
2794         ret = snprintf(fw_version, fw_size,
2795                  "%d.%d%d 0x%08x %d.%d.%d",
2796                  ((hw->nvm.version >> 12) & 0xf),
2797                  ((hw->nvm.version >> 4) & 0xff),
2798                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
2799                  ver, build, patch);
2800
2801         ret += 1; /* add the size of '\0' */
2802         if (fw_size < (u32)ret)
2803                 return ret;
2804         else
2805                 return 0;
2806 }
2807
2808 static void
2809 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2810 {
2811         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2812         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2813         struct i40e_vsi *vsi = pf->main_vsi;
2814         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2815
2816         dev_info->pci_dev = pci_dev;
2817         dev_info->max_rx_queues = vsi->nb_qps;
2818         dev_info->max_tx_queues = vsi->nb_qps;
2819         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2820         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2821         dev_info->max_mac_addrs = vsi->max_macaddrs;
2822         dev_info->max_vfs = pci_dev->max_vfs;
2823         dev_info->rx_offload_capa =
2824                 DEV_RX_OFFLOAD_VLAN_STRIP |
2825                 DEV_RX_OFFLOAD_QINQ_STRIP |
2826                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2827                 DEV_RX_OFFLOAD_UDP_CKSUM |
2828                 DEV_RX_OFFLOAD_TCP_CKSUM;
2829         dev_info->tx_offload_capa =
2830                 DEV_TX_OFFLOAD_VLAN_INSERT |
2831                 DEV_TX_OFFLOAD_QINQ_INSERT |
2832                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2833                 DEV_TX_OFFLOAD_UDP_CKSUM |
2834                 DEV_TX_OFFLOAD_TCP_CKSUM |
2835                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2836                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2837                 DEV_TX_OFFLOAD_TCP_TSO |
2838                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2839                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2840                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2841                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2842         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2843                                                 sizeof(uint32_t);
2844         dev_info->reta_size = pf->hash_lut_size;
2845         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2846
2847         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2848                 .rx_thresh = {
2849                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2850                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2851                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2852                 },
2853                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2854                 .rx_drop_en = 0,
2855         };
2856
2857         dev_info->default_txconf = (struct rte_eth_txconf) {
2858                 .tx_thresh = {
2859                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2860                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2861                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2862                 },
2863                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2864                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2865                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2866                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2867         };
2868
2869         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2870                 .nb_max = I40E_MAX_RING_DESC,
2871                 .nb_min = I40E_MIN_RING_DESC,
2872                 .nb_align = I40E_ALIGN_RING_DESC,
2873         };
2874
2875         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2876                 .nb_max = I40E_MAX_RING_DESC,
2877                 .nb_min = I40E_MIN_RING_DESC,
2878                 .nb_align = I40E_ALIGN_RING_DESC,
2879                 .nb_seg_max = I40E_TX_MAX_SEG,
2880                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
2881         };
2882
2883         if (pf->flags & I40E_FLAG_VMDQ) {
2884                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2885                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2886                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2887                                                 pf->max_nb_vmdq_vsi;
2888                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2889                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2890                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2891         }
2892
2893         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2894                 /* For XL710 */
2895                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2896         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2897                 /* For XXV710 */
2898                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2899         else
2900                 /* For X710 */
2901                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2902 }
2903
2904 static int
2905 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2906 {
2907         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2908         struct i40e_vsi *vsi = pf->main_vsi;
2909         PMD_INIT_FUNC_TRACE();
2910
2911         if (on)
2912                 return i40e_vsi_add_vlan(vsi, vlan_id);
2913         else
2914                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2915 }
2916
2917 static int
2918 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2919                    enum rte_vlan_type vlan_type,
2920                    uint16_t tpid)
2921 {
2922         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2923         uint64_t reg_r = 0, reg_w = 0;
2924         uint16_t reg_id = 0;
2925         int ret = 0;
2926         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2927
2928         switch (vlan_type) {
2929         case ETH_VLAN_TYPE_OUTER:
2930                 if (qinq)
2931                         reg_id = 2;
2932                 else
2933                         reg_id = 3;
2934                 break;
2935         case ETH_VLAN_TYPE_INNER:
2936                 if (qinq)
2937                         reg_id = 3;
2938                 else {
2939                         ret = -EINVAL;
2940                         PMD_DRV_LOG(ERR,
2941                                 "Unsupported vlan type in single vlan.");
2942                         return ret;
2943                 }
2944                 break;
2945         default:
2946                 ret = -EINVAL;
2947                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2948                 return ret;
2949         }
2950         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2951                                           &reg_r, NULL);
2952         if (ret != I40E_SUCCESS) {
2953                 PMD_DRV_LOG(ERR,
2954                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
2955                            reg_id);
2956                 ret = -EIO;
2957                 return ret;
2958         }
2959         PMD_DRV_LOG(DEBUG,
2960                 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
2961                 reg_id, reg_r);
2962
2963         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2964         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2965         if (reg_r == reg_w) {
2966                 ret = 0;
2967                 PMD_DRV_LOG(DEBUG, "No need to write");
2968                 return ret;
2969         }
2970
2971         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2972                                            reg_w, NULL);
2973         if (ret != I40E_SUCCESS) {
2974                 ret = -EIO;
2975                 PMD_DRV_LOG(ERR,
2976                         "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
2977                         reg_id);
2978                 return ret;
2979         }
2980         PMD_DRV_LOG(DEBUG,
2981                 "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
2982                 reg_w, reg_id);
2983
2984         return ret;
2985 }
2986
2987 static void
2988 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2989 {
2990         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2991         struct i40e_vsi *vsi = pf->main_vsi;
2992
2993         if (mask & ETH_VLAN_FILTER_MASK) {
2994                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2995                         i40e_vsi_config_vlan_filter(vsi, TRUE);
2996                 else
2997                         i40e_vsi_config_vlan_filter(vsi, FALSE);
2998         }
2999
3000         if (mask & ETH_VLAN_STRIP_MASK) {
3001                 /* Enable or disable VLAN stripping */
3002                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3003                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3004                 else
3005                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3006         }
3007
3008         if (mask & ETH_VLAN_EXTEND_MASK) {
3009                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3010                         i40e_vsi_config_double_vlan(vsi, TRUE);
3011                         /* Set global registers with default ether type value */
3012                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3013                                            ETHER_TYPE_VLAN);
3014                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3015                                            ETHER_TYPE_VLAN);
3016                 }
3017                 else
3018                         i40e_vsi_config_double_vlan(vsi, FALSE);
3019         }
3020 }
3021
3022 static void
3023 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3024                           __rte_unused uint16_t queue,
3025                           __rte_unused int on)
3026 {
3027         PMD_INIT_FUNC_TRACE();
3028 }
3029
3030 static int
3031 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3032 {
3033         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3034         struct i40e_vsi *vsi = pf->main_vsi;
3035         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3036         struct i40e_vsi_vlan_pvid_info info;
3037
3038         memset(&info, 0, sizeof(info));
3039         info.on = on;
3040         if (info.on)
3041                 info.config.pvid = pvid;
3042         else {
3043                 info.config.reject.tagged =
3044                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3045                 info.config.reject.untagged =
3046                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3047         }
3048
3049         return i40e_vsi_vlan_pvid_set(vsi, &info);
3050 }
3051
3052 static int
3053 i40e_dev_led_on(struct rte_eth_dev *dev)
3054 {
3055         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3056         uint32_t mode = i40e_led_get(hw);
3057
3058         if (mode == 0)
3059                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3060
3061         return 0;
3062 }
3063
3064 static int
3065 i40e_dev_led_off(struct rte_eth_dev *dev)
3066 {
3067         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3068         uint32_t mode = i40e_led_get(hw);
3069
3070         if (mode != 0)
3071                 i40e_led_set(hw, 0, false);
3072
3073         return 0;
3074 }
3075
3076 static int
3077 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3078 {
3079         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3080         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3081
3082         fc_conf->pause_time = pf->fc_conf.pause_time;
3083         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3084         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3085
3086          /* Return current mode according to actual setting*/
3087         switch (hw->fc.current_mode) {
3088         case I40E_FC_FULL:
3089                 fc_conf->mode = RTE_FC_FULL;
3090                 break;
3091         case I40E_FC_TX_PAUSE:
3092                 fc_conf->mode = RTE_FC_TX_PAUSE;
3093                 break;
3094         case I40E_FC_RX_PAUSE:
3095                 fc_conf->mode = RTE_FC_RX_PAUSE;
3096                 break;
3097         case I40E_FC_NONE:
3098         default:
3099                 fc_conf->mode = RTE_FC_NONE;
3100         };
3101
3102         return 0;
3103 }
3104
3105 static int
3106 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3107 {
3108         uint32_t mflcn_reg, fctrl_reg, reg;
3109         uint32_t max_high_water;
3110         uint8_t i, aq_failure;
3111         int err;
3112         struct i40e_hw *hw;
3113         struct i40e_pf *pf;
3114         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3115                 [RTE_FC_NONE] = I40E_FC_NONE,
3116                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3117                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3118                 [RTE_FC_FULL] = I40E_FC_FULL
3119         };
3120
3121         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3122
3123         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3124         if ((fc_conf->high_water > max_high_water) ||
3125                         (fc_conf->high_water < fc_conf->low_water)) {
3126                 PMD_INIT_LOG(ERR,
3127                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3128                         max_high_water);
3129                 return -EINVAL;
3130         }
3131
3132         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3133         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3134         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3135
3136         pf->fc_conf.pause_time = fc_conf->pause_time;
3137         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3138         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3139
3140         PMD_INIT_FUNC_TRACE();
3141
3142         /* All the link flow control related enable/disable register
3143          * configuration is handle by the F/W
3144          */
3145         err = i40e_set_fc(hw, &aq_failure, true);
3146         if (err < 0)
3147                 return -ENOSYS;
3148
3149         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3150                 /* Configure flow control refresh threshold,
3151                  * the value for stat_tx_pause_refresh_timer[8]
3152                  * is used for global pause operation.
3153                  */
3154
3155                 I40E_WRITE_REG(hw,
3156                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3157                                pf->fc_conf.pause_time);
3158
3159                 /* configure the timer value included in transmitted pause
3160                  * frame,
3161                  * the value for stat_tx_pause_quanta[8] is used for global
3162                  * pause operation
3163                  */
3164                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3165                                pf->fc_conf.pause_time);
3166
3167                 fctrl_reg = I40E_READ_REG(hw,
3168                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3169
3170                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3171                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3172                 else
3173                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3174
3175                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3176                                fctrl_reg);
3177         } else {
3178                 /* Configure pause time (2 TCs per register) */
3179                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3180                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3181                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3182
3183                 /* Configure flow control refresh threshold value */
3184                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3185                                pf->fc_conf.pause_time / 2);
3186
3187                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3188
3189                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3190                  *depending on configuration
3191                  */
3192                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3193                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3194                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3195                 } else {
3196                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3197                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3198                 }
3199
3200                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3201         }
3202
3203         /* config the water marker both based on the packets and bytes */
3204         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3205                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3206                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3207         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3208                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3209                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3210         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3211                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3212                        << I40E_KILOSHIFT);
3213         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3214                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3215                        << I40E_KILOSHIFT);
3216
3217         I40E_WRITE_FLUSH(hw);
3218
3219         return 0;
3220 }
3221
3222 static int
3223 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3224                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3225 {
3226         PMD_INIT_FUNC_TRACE();
3227
3228         return -ENOSYS;
3229 }
3230
3231 /* Add a MAC address, and update filters */
3232 static void
3233 i40e_macaddr_add(struct rte_eth_dev *dev,
3234                  struct ether_addr *mac_addr,
3235                  __rte_unused uint32_t index,
3236                  uint32_t pool)
3237 {
3238         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3239         struct i40e_mac_filter_info mac_filter;
3240         struct i40e_vsi *vsi;
3241         int ret;
3242
3243         /* If VMDQ not enabled or configured, return */
3244         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3245                           !pf->nb_cfg_vmdq_vsi)) {
3246                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3247                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3248                         pool);
3249                 return;
3250         }
3251
3252         if (pool > pf->nb_cfg_vmdq_vsi) {
3253                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3254                                 pool, pf->nb_cfg_vmdq_vsi);
3255                 return;
3256         }
3257
3258         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3259         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3260                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3261         else
3262                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3263
3264         if (pool == 0)
3265                 vsi = pf->main_vsi;
3266         else
3267                 vsi = pf->vmdq[pool - 1].vsi;
3268
3269         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3270         if (ret != I40E_SUCCESS) {
3271                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3272                 return;
3273         }
3274 }
3275
3276 /* Remove a MAC address, and update filters */
3277 static void
3278 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3279 {
3280         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3281         struct i40e_vsi *vsi;
3282         struct rte_eth_dev_data *data = dev->data;
3283         struct ether_addr *macaddr;
3284         int ret;
3285         uint32_t i;
3286         uint64_t pool_sel;
3287
3288         macaddr = &(data->mac_addrs[index]);
3289
3290         pool_sel = dev->data->mac_pool_sel[index];
3291
3292         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3293                 if (pool_sel & (1ULL << i)) {
3294                         if (i == 0)
3295                                 vsi = pf->main_vsi;
3296                         else {
3297                                 /* No VMDQ pool enabled or configured */
3298                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3299                                         (i > pf->nb_cfg_vmdq_vsi)) {
3300                                         PMD_DRV_LOG(ERR,
3301                                                 "No VMDQ pool enabled/configured");
3302                                         return;
3303                                 }
3304                                 vsi = pf->vmdq[i - 1].vsi;
3305                         }
3306                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3307
3308                         if (ret) {
3309                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3310                                 return;
3311                         }
3312                 }
3313         }
3314 }
3315
3316 /* Set perfect match or hash match of MAC and VLAN for a VF */
3317 static int
3318 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3319                  struct rte_eth_mac_filter *filter,
3320                  bool add)
3321 {
3322         struct i40e_hw *hw;
3323         struct i40e_mac_filter_info mac_filter;
3324         struct ether_addr old_mac;
3325         struct ether_addr *new_mac;
3326         struct i40e_pf_vf *vf = NULL;
3327         uint16_t vf_id;
3328         int ret;
3329
3330         if (pf == NULL) {
3331                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3332                 return -EINVAL;
3333         }
3334         hw = I40E_PF_TO_HW(pf);
3335
3336         if (filter == NULL) {
3337                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3338                 return -EINVAL;
3339         }
3340
3341         new_mac = &filter->mac_addr;
3342
3343         if (is_zero_ether_addr(new_mac)) {
3344                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3345                 return -EINVAL;
3346         }
3347
3348         vf_id = filter->dst_id;
3349
3350         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3351                 PMD_DRV_LOG(ERR, "Invalid argument.");
3352                 return -EINVAL;
3353         }
3354         vf = &pf->vfs[vf_id];
3355
3356         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3357                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3358                 return -EINVAL;
3359         }
3360
3361         if (add) {
3362                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3363                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3364                                 ETHER_ADDR_LEN);
3365                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3366                                  ETHER_ADDR_LEN);
3367
3368                 mac_filter.filter_type = filter->filter_type;
3369                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3370                 if (ret != I40E_SUCCESS) {
3371                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3372                         return -1;
3373                 }
3374                 ether_addr_copy(new_mac, &pf->dev_addr);
3375         } else {
3376                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3377                                 ETHER_ADDR_LEN);
3378                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3379                 if (ret != I40E_SUCCESS) {
3380                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3381                         return -1;
3382                 }
3383
3384                 /* Clear device address as it has been removed */
3385                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3386                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3387         }
3388
3389         return 0;
3390 }
3391
3392 /* MAC filter handle */
3393 static int
3394 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3395                 void *arg)
3396 {
3397         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3398         struct rte_eth_mac_filter *filter;
3399         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3400         int ret = I40E_NOT_SUPPORTED;
3401
3402         filter = (struct rte_eth_mac_filter *)(arg);
3403
3404         switch (filter_op) {
3405         case RTE_ETH_FILTER_NOP:
3406                 ret = I40E_SUCCESS;
3407                 break;
3408         case RTE_ETH_FILTER_ADD:
3409                 i40e_pf_disable_irq0(hw);
3410                 if (filter->is_vf)
3411                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3412                 i40e_pf_enable_irq0(hw);
3413                 break;
3414         case RTE_ETH_FILTER_DELETE:
3415                 i40e_pf_disable_irq0(hw);
3416                 if (filter->is_vf)
3417                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3418                 i40e_pf_enable_irq0(hw);
3419                 break;
3420         default:
3421                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3422                 ret = I40E_ERR_PARAM;
3423                 break;
3424         }
3425
3426         return ret;
3427 }
3428
3429 static int
3430 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3431 {
3432         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3433         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3434         int ret;
3435
3436         if (!lut)
3437                 return -EINVAL;
3438
3439         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3440                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3441                                           lut, lut_size);
3442                 if (ret) {
3443                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3444                         return ret;
3445                 }
3446         } else {
3447                 uint32_t *lut_dw = (uint32_t *)lut;
3448                 uint16_t i, lut_size_dw = lut_size / 4;
3449
3450                 for (i = 0; i < lut_size_dw; i++)
3451                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3452         }
3453
3454         return 0;
3455 }
3456
3457 static int
3458 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3459 {
3460         struct i40e_pf *pf;
3461         struct i40e_hw *hw;
3462         int ret;
3463
3464         if (!vsi || !lut)
3465                 return -EINVAL;
3466
3467         pf = I40E_VSI_TO_PF(vsi);
3468         hw = I40E_VSI_TO_HW(vsi);
3469
3470         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3471                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3472                                           lut, lut_size);
3473                 if (ret) {
3474                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3475                         return ret;
3476                 }
3477         } else {
3478                 uint32_t *lut_dw = (uint32_t *)lut;
3479                 uint16_t i, lut_size_dw = lut_size / 4;
3480
3481                 for (i = 0; i < lut_size_dw; i++)
3482                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3483                 I40E_WRITE_FLUSH(hw);
3484         }
3485
3486         return 0;
3487 }
3488
3489 static int
3490 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3491                          struct rte_eth_rss_reta_entry64 *reta_conf,
3492                          uint16_t reta_size)
3493 {
3494         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3495         uint16_t i, lut_size = pf->hash_lut_size;
3496         uint16_t idx, shift;
3497         uint8_t *lut;
3498         int ret;
3499
3500         if (reta_size != lut_size ||
3501                 reta_size > ETH_RSS_RETA_SIZE_512) {
3502                 PMD_DRV_LOG(ERR,
3503                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3504                         reta_size, lut_size);
3505                 return -EINVAL;
3506         }
3507
3508         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3509         if (!lut) {
3510                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3511                 return -ENOMEM;
3512         }
3513         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3514         if (ret)
3515                 goto out;
3516         for (i = 0; i < reta_size; i++) {
3517                 idx = i / RTE_RETA_GROUP_SIZE;
3518                 shift = i % RTE_RETA_GROUP_SIZE;
3519                 if (reta_conf[idx].mask & (1ULL << shift))
3520                         lut[i] = reta_conf[idx].reta[shift];
3521         }
3522         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3523
3524 out:
3525         rte_free(lut);
3526
3527         return ret;
3528 }
3529
3530 static int
3531 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3532                         struct rte_eth_rss_reta_entry64 *reta_conf,
3533                         uint16_t reta_size)
3534 {
3535         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3536         uint16_t i, lut_size = pf->hash_lut_size;
3537         uint16_t idx, shift;
3538         uint8_t *lut;
3539         int ret;
3540
3541         if (reta_size != lut_size ||
3542                 reta_size > ETH_RSS_RETA_SIZE_512) {
3543                 PMD_DRV_LOG(ERR,
3544                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3545                         reta_size, lut_size);
3546                 return -EINVAL;
3547         }
3548
3549         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3550         if (!lut) {
3551                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3552                 return -ENOMEM;
3553         }
3554
3555         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3556         if (ret)
3557                 goto out;
3558         for (i = 0; i < reta_size; i++) {
3559                 idx = i / RTE_RETA_GROUP_SIZE;
3560                 shift = i % RTE_RETA_GROUP_SIZE;
3561                 if (reta_conf[idx].mask & (1ULL << shift))
3562                         reta_conf[idx].reta[shift] = lut[i];
3563         }
3564
3565 out:
3566         rte_free(lut);
3567
3568         return ret;
3569 }
3570
3571 /**
3572  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3573  * @hw:   pointer to the HW structure
3574  * @mem:  pointer to mem struct to fill out
3575  * @size: size of memory requested
3576  * @alignment: what to align the allocation to
3577  **/
3578 enum i40e_status_code
3579 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3580                         struct i40e_dma_mem *mem,
3581                         u64 size,
3582                         u32 alignment)
3583 {
3584         const struct rte_memzone *mz = NULL;
3585         char z_name[RTE_MEMZONE_NAMESIZE];
3586
3587         if (!mem)
3588                 return I40E_ERR_PARAM;
3589
3590         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3591         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3592                                          alignment, RTE_PGSIZE_2M);
3593         if (!mz)
3594                 return I40E_ERR_NO_MEMORY;
3595
3596         mem->size = size;
3597         mem->va = mz->addr;
3598         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3599         mem->zone = (const void *)mz;
3600         PMD_DRV_LOG(DEBUG,
3601                 "memzone %s allocated with physical address: %"PRIu64,
3602                 mz->name, mem->pa);
3603
3604         return I40E_SUCCESS;
3605 }
3606
3607 /**
3608  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3609  * @hw:   pointer to the HW structure
3610  * @mem:  ptr to mem struct to free
3611  **/
3612 enum i40e_status_code
3613 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3614                     struct i40e_dma_mem *mem)
3615 {
3616         if (!mem)
3617                 return I40E_ERR_PARAM;
3618
3619         PMD_DRV_LOG(DEBUG,
3620                 "memzone %s to be freed with physical address: %"PRIu64,
3621                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3622         rte_memzone_free((const struct rte_memzone *)mem->zone);
3623         mem->zone = NULL;
3624         mem->va = NULL;
3625         mem->pa = (u64)0;
3626
3627         return I40E_SUCCESS;
3628 }
3629
3630 /**
3631  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3632  * @hw:   pointer to the HW structure
3633  * @mem:  pointer to mem struct to fill out
3634  * @size: size of memory requested
3635  **/
3636 enum i40e_status_code
3637 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3638                          struct i40e_virt_mem *mem,
3639                          u32 size)
3640 {
3641         if (!mem)
3642                 return I40E_ERR_PARAM;
3643
3644         mem->size = size;
3645         mem->va = rte_zmalloc("i40e", size, 0);
3646
3647         if (mem->va)
3648                 return I40E_SUCCESS;
3649         else
3650                 return I40E_ERR_NO_MEMORY;
3651 }
3652
3653 /**
3654  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3655  * @hw:   pointer to the HW structure
3656  * @mem:  pointer to mem struct to free
3657  **/
3658 enum i40e_status_code
3659 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3660                      struct i40e_virt_mem *mem)
3661 {
3662         if (!mem)
3663                 return I40E_ERR_PARAM;
3664
3665         rte_free(mem->va);
3666         mem->va = NULL;
3667
3668         return I40E_SUCCESS;
3669 }
3670
3671 void
3672 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3673 {
3674         rte_spinlock_init(&sp->spinlock);
3675 }
3676
3677 void
3678 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3679 {
3680         rte_spinlock_lock(&sp->spinlock);
3681 }
3682
3683 void
3684 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3685 {
3686         rte_spinlock_unlock(&sp->spinlock);
3687 }
3688
3689 void
3690 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3691 {
3692         return;
3693 }
3694
3695 /**
3696  * Get the hardware capabilities, which will be parsed
3697  * and saved into struct i40e_hw.
3698  */
3699 static int
3700 i40e_get_cap(struct i40e_hw *hw)
3701 {
3702         struct i40e_aqc_list_capabilities_element_resp *buf;
3703         uint16_t len, size = 0;
3704         int ret;
3705
3706         /* Calculate a huge enough buff for saving response data temporarily */
3707         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3708                                                 I40E_MAX_CAP_ELE_NUM;
3709         buf = rte_zmalloc("i40e", len, 0);
3710         if (!buf) {
3711                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3712                 return I40E_ERR_NO_MEMORY;
3713         }
3714
3715         /* Get, parse the capabilities and save it to hw */
3716         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3717                         i40e_aqc_opc_list_func_capabilities, NULL);
3718         if (ret != I40E_SUCCESS)
3719                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3720
3721         /* Free the temporary buffer after being used */
3722         rte_free(buf);
3723
3724         return ret;
3725 }
3726
3727 static int
3728 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3729 {
3730         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3731         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3732         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
3733         uint16_t qp_count = 0, vsi_count = 0;
3734
3735         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3736                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3737                 return -EINVAL;
3738         }
3739         /* Add the parameter init for LFC */
3740         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3741         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3742         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3743
3744         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3745         pf->max_num_vsi = hw->func_caps.num_vsis;
3746         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3747         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3748         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3749
3750         /* FDir queue/VSI allocation */
3751         pf->fdir_qp_offset = 0;
3752         if (hw->func_caps.fd) {
3753                 pf->flags |= I40E_FLAG_FDIR;
3754                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3755         } else {
3756                 pf->fdir_nb_qps = 0;
3757         }
3758         qp_count += pf->fdir_nb_qps;
3759         vsi_count += 1;
3760
3761         /* LAN queue/VSI allocation */
3762         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3763         if (!hw->func_caps.rss) {
3764                 pf->lan_nb_qps = 1;
3765         } else {
3766                 pf->flags |= I40E_FLAG_RSS;
3767                 if (hw->mac.type == I40E_MAC_X722)
3768                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3769                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3770         }
3771         qp_count += pf->lan_nb_qps;
3772         vsi_count += 1;
3773
3774         /* VF queue/VSI allocation */
3775         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3776         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3777                 pf->flags |= I40E_FLAG_SRIOV;
3778                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3779                 pf->vf_num = pci_dev->max_vfs;
3780                 PMD_DRV_LOG(DEBUG,
3781                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
3782                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
3783         } else {
3784                 pf->vf_nb_qps = 0;
3785                 pf->vf_num = 0;
3786         }
3787         qp_count += pf->vf_nb_qps * pf->vf_num;
3788         vsi_count += pf->vf_num;
3789
3790         /* VMDq queue/VSI allocation */
3791         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3792         pf->vmdq_nb_qps = 0;
3793         pf->max_nb_vmdq_vsi = 0;
3794         if (hw->func_caps.vmdq) {
3795                 if (qp_count < hw->func_caps.num_tx_qp &&
3796                         vsi_count < hw->func_caps.num_vsis) {
3797                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3798                                 qp_count) / pf->vmdq_nb_qp_max;
3799
3800                         /* Limit the maximum number of VMDq vsi to the maximum
3801                          * ethdev can support
3802                          */
3803                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3804                                 hw->func_caps.num_vsis - vsi_count);
3805                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3806                                 ETH_64_POOLS);
3807                         if (pf->max_nb_vmdq_vsi) {
3808                                 pf->flags |= I40E_FLAG_VMDQ;
3809                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3810                                 PMD_DRV_LOG(DEBUG,
3811                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
3812                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
3813                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
3814                         } else {
3815                                 PMD_DRV_LOG(INFO,
3816                                         "No enough queues left for VMDq");
3817                         }
3818                 } else {
3819                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3820                 }
3821         }
3822         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3823         vsi_count += pf->max_nb_vmdq_vsi;
3824
3825         if (hw->func_caps.dcb)
3826                 pf->flags |= I40E_FLAG_DCB;
3827
3828         if (qp_count > hw->func_caps.num_tx_qp) {
3829                 PMD_DRV_LOG(ERR,
3830                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
3831                         qp_count, hw->func_caps.num_tx_qp);
3832                 return -EINVAL;
3833         }
3834         if (vsi_count > hw->func_caps.num_vsis) {
3835                 PMD_DRV_LOG(ERR,
3836                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
3837                         vsi_count, hw->func_caps.num_vsis);
3838                 return -EINVAL;
3839         }
3840
3841         return 0;
3842 }
3843
3844 static int
3845 i40e_pf_get_switch_config(struct i40e_pf *pf)
3846 {
3847         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3848         struct i40e_aqc_get_switch_config_resp *switch_config;
3849         struct i40e_aqc_switch_config_element_resp *element;
3850         uint16_t start_seid = 0, num_reported;
3851         int ret;
3852
3853         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3854                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3855         if (!switch_config) {
3856                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3857                 return -ENOMEM;
3858         }
3859
3860         /* Get the switch configurations */
3861         ret = i40e_aq_get_switch_config(hw, switch_config,
3862                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3863         if (ret != I40E_SUCCESS) {
3864                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3865                 goto fail;
3866         }
3867         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3868         if (num_reported != 1) { /* The number should be 1 */
3869                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3870                 goto fail;
3871         }
3872
3873         /* Parse the switch configuration elements */
3874         element = &(switch_config->element[0]);
3875         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3876                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3877                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3878         } else
3879                 PMD_DRV_LOG(INFO, "Unknown element type");
3880
3881 fail:
3882         rte_free(switch_config);
3883
3884         return ret;
3885 }
3886
3887 static int
3888 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3889                         uint32_t num)
3890 {
3891         struct pool_entry *entry;
3892
3893         if (pool == NULL || num == 0)
3894                 return -EINVAL;
3895
3896         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3897         if (entry == NULL) {
3898                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3899                 return -ENOMEM;
3900         }
3901
3902         /* queue heap initialize */
3903         pool->num_free = num;
3904         pool->num_alloc = 0;
3905         pool->base = base;
3906         LIST_INIT(&pool->alloc_list);
3907         LIST_INIT(&pool->free_list);
3908
3909         /* Initialize element  */
3910         entry->base = 0;
3911         entry->len = num;
3912
3913         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3914         return 0;
3915 }
3916
3917 static void
3918 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3919 {
3920         struct pool_entry *entry, *next_entry;
3921
3922         if (pool == NULL)
3923                 return;
3924
3925         for (entry = LIST_FIRST(&pool->alloc_list);
3926                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3927                         entry = next_entry) {
3928                 LIST_REMOVE(entry, next);
3929                 rte_free(entry);
3930         }
3931
3932         for (entry = LIST_FIRST(&pool->free_list);
3933                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3934                         entry = next_entry) {
3935                 LIST_REMOVE(entry, next);
3936                 rte_free(entry);
3937         }
3938
3939         pool->num_free = 0;
3940         pool->num_alloc = 0;
3941         pool->base = 0;
3942         LIST_INIT(&pool->alloc_list);
3943         LIST_INIT(&pool->free_list);
3944 }
3945
3946 static int
3947 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3948                        uint32_t base)
3949 {
3950         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3951         uint32_t pool_offset;
3952         int insert;
3953
3954         if (pool == NULL) {
3955                 PMD_DRV_LOG(ERR, "Invalid parameter");
3956                 return -EINVAL;
3957         }
3958
3959         pool_offset = base - pool->base;
3960         /* Lookup in alloc list */
3961         LIST_FOREACH(entry, &pool->alloc_list, next) {
3962                 if (entry->base == pool_offset) {
3963                         valid_entry = entry;
3964                         LIST_REMOVE(entry, next);
3965                         break;
3966                 }
3967         }
3968
3969         /* Not find, return */
3970         if (valid_entry == NULL) {
3971                 PMD_DRV_LOG(ERR, "Failed to find entry");
3972                 return -EINVAL;
3973         }
3974
3975         /**
3976          * Found it, move it to free list  and try to merge.
3977          * In order to make merge easier, always sort it by qbase.
3978          * Find adjacent prev and last entries.
3979          */
3980         prev = next = NULL;
3981         LIST_FOREACH(entry, &pool->free_list, next) {
3982                 if (entry->base > valid_entry->base) {
3983                         next = entry;
3984                         break;
3985                 }
3986                 prev = entry;
3987         }
3988
3989         insert = 0;
3990         /* Try to merge with next one*/
3991         if (next != NULL) {
3992                 /* Merge with next one */
3993                 if (valid_entry->base + valid_entry->len == next->base) {
3994                         next->base = valid_entry->base;
3995                         next->len += valid_entry->len;
3996                         rte_free(valid_entry);
3997                         valid_entry = next;
3998                         insert = 1;
3999                 }
4000         }
4001
4002         if (prev != NULL) {
4003                 /* Merge with previous one */
4004                 if (prev->base + prev->len == valid_entry->base) {
4005                         prev->len += valid_entry->len;
4006                         /* If it merge with next one, remove next node */
4007                         if (insert == 1) {
4008                                 LIST_REMOVE(valid_entry, next);
4009                                 rte_free(valid_entry);
4010                         } else {
4011                                 rte_free(valid_entry);
4012                                 insert = 1;
4013                         }
4014                 }
4015         }
4016
4017         /* Not find any entry to merge, insert */
4018         if (insert == 0) {
4019                 if (prev != NULL)
4020                         LIST_INSERT_AFTER(prev, valid_entry, next);
4021                 else if (next != NULL)
4022                         LIST_INSERT_BEFORE(next, valid_entry, next);
4023                 else /* It's empty list, insert to head */
4024                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4025         }
4026
4027         pool->num_free += valid_entry->len;
4028         pool->num_alloc -= valid_entry->len;
4029
4030         return 0;
4031 }
4032
4033 static int
4034 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4035                        uint16_t num)
4036 {
4037         struct pool_entry *entry, *valid_entry;
4038
4039         if (pool == NULL || num == 0) {
4040                 PMD_DRV_LOG(ERR, "Invalid parameter");
4041                 return -EINVAL;
4042         }
4043
4044         if (pool->num_free < num) {
4045                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4046                             num, pool->num_free);
4047                 return -ENOMEM;
4048         }
4049
4050         valid_entry = NULL;
4051         /* Lookup  in free list and find most fit one */
4052         LIST_FOREACH(entry, &pool->free_list, next) {
4053                 if (entry->len >= num) {
4054                         /* Find best one */
4055                         if (entry->len == num) {
4056                                 valid_entry = entry;
4057                                 break;
4058                         }
4059                         if (valid_entry == NULL || valid_entry->len > entry->len)
4060                                 valid_entry = entry;
4061                 }
4062         }
4063
4064         /* Not find one to satisfy the request, return */
4065         if (valid_entry == NULL) {
4066                 PMD_DRV_LOG(ERR, "No valid entry found");
4067                 return -ENOMEM;
4068         }
4069         /**
4070          * The entry have equal queue number as requested,
4071          * remove it from alloc_list.
4072          */
4073         if (valid_entry->len == num) {
4074                 LIST_REMOVE(valid_entry, next);
4075         } else {
4076                 /**
4077                  * The entry have more numbers than requested,
4078                  * create a new entry for alloc_list and minus its
4079                  * queue base and number in free_list.
4080                  */
4081                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4082                 if (entry == NULL) {
4083                         PMD_DRV_LOG(ERR,
4084                                 "Failed to allocate memory for resource pool");
4085                         return -ENOMEM;
4086                 }
4087                 entry->base = valid_entry->base;
4088                 entry->len = num;
4089                 valid_entry->base += num;
4090                 valid_entry->len -= num;
4091                 valid_entry = entry;
4092         }
4093
4094         /* Insert it into alloc list, not sorted */
4095         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4096
4097         pool->num_free -= valid_entry->len;
4098         pool->num_alloc += valid_entry->len;
4099
4100         return valid_entry->base + pool->base;
4101 }
4102
4103 /**
4104  * bitmap_is_subset - Check whether src2 is subset of src1
4105  **/
4106 static inline int
4107 bitmap_is_subset(uint8_t src1, uint8_t src2)
4108 {
4109         return !((src1 ^ src2) & src2);
4110 }
4111
4112 static enum i40e_status_code
4113 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4114 {
4115         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4116
4117         /* If DCB is not supported, only default TC is supported */
4118         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4119                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4120                 return I40E_NOT_SUPPORTED;
4121         }
4122
4123         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4124                 PMD_DRV_LOG(ERR,
4125                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4126                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4127                 return I40E_NOT_SUPPORTED;
4128         }
4129         return I40E_SUCCESS;
4130 }
4131
4132 int
4133 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4134                                 struct i40e_vsi_vlan_pvid_info *info)
4135 {
4136         struct i40e_hw *hw;
4137         struct i40e_vsi_context ctxt;
4138         uint8_t vlan_flags = 0;
4139         int ret;
4140
4141         if (vsi == NULL || info == NULL) {
4142                 PMD_DRV_LOG(ERR, "invalid parameters");
4143                 return I40E_ERR_PARAM;
4144         }
4145
4146         if (info->on) {
4147                 vsi->info.pvid = info->config.pvid;
4148                 /**
4149                  * If insert pvid is enabled, only tagged pkts are
4150                  * allowed to be sent out.
4151                  */
4152                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4153                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4154         } else {
4155                 vsi->info.pvid = 0;
4156                 if (info->config.reject.tagged == 0)
4157                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4158
4159                 if (info->config.reject.untagged == 0)
4160                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4161         }
4162         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4163                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4164         vsi->info.port_vlan_flags |= vlan_flags;
4165         vsi->info.valid_sections =
4166                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4167         memset(&ctxt, 0, sizeof(ctxt));
4168         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4169         ctxt.seid = vsi->seid;
4170
4171         hw = I40E_VSI_TO_HW(vsi);
4172         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4173         if (ret != I40E_SUCCESS)
4174                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4175
4176         return ret;
4177 }
4178
4179 static int
4180 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4181 {
4182         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4183         int i, ret;
4184         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4185
4186         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4187         if (ret != I40E_SUCCESS)
4188                 return ret;
4189
4190         if (!vsi->seid) {
4191                 PMD_DRV_LOG(ERR, "seid not valid");
4192                 return -EINVAL;
4193         }
4194
4195         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4196         tc_bw_data.tc_valid_bits = enabled_tcmap;
4197         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4198                 tc_bw_data.tc_bw_credits[i] =
4199                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4200
4201         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4202         if (ret != I40E_SUCCESS) {
4203                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4204                 return ret;
4205         }
4206
4207         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4208                                         sizeof(vsi->info.qs_handle));
4209         return I40E_SUCCESS;
4210 }
4211
4212 static enum i40e_status_code
4213 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4214                                  struct i40e_aqc_vsi_properties_data *info,
4215                                  uint8_t enabled_tcmap)
4216 {
4217         enum i40e_status_code ret;
4218         int i, total_tc = 0;
4219         uint16_t qpnum_per_tc, bsf, qp_idx;
4220
4221         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4222         if (ret != I40E_SUCCESS)
4223                 return ret;
4224
4225         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4226                 if (enabled_tcmap & (1 << i))
4227                         total_tc++;
4228         vsi->enabled_tc = enabled_tcmap;
4229
4230         /* Number of queues per enabled TC */
4231         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4232         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4233         bsf = rte_bsf32(qpnum_per_tc);
4234
4235         /* Adjust the queue number to actual queues that can be applied */
4236         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4237                 vsi->nb_qps = qpnum_per_tc * total_tc;
4238
4239         /**
4240          * Configure TC and queue mapping parameters, for enabled TC,
4241          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4242          * default queue will serve it.
4243          */
4244         qp_idx = 0;
4245         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4246                 if (vsi->enabled_tc & (1 << i)) {
4247                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4248                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4249                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4250                         qp_idx += qpnum_per_tc;
4251                 } else
4252                         info->tc_mapping[i] = 0;
4253         }
4254
4255         /* Associate queue number with VSI */
4256         if (vsi->type == I40E_VSI_SRIOV) {
4257                 info->mapping_flags |=
4258                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4259                 for (i = 0; i < vsi->nb_qps; i++)
4260                         info->queue_mapping[i] =
4261                                 rte_cpu_to_le_16(vsi->base_queue + i);
4262         } else {
4263                 info->mapping_flags |=
4264                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4265                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4266         }
4267         info->valid_sections |=
4268                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4269
4270         return I40E_SUCCESS;
4271 }
4272
4273 static int
4274 i40e_veb_release(struct i40e_veb *veb)
4275 {
4276         struct i40e_vsi *vsi;
4277         struct i40e_hw *hw;
4278
4279         if (veb == NULL)
4280                 return -EINVAL;
4281
4282         if (!TAILQ_EMPTY(&veb->head)) {
4283                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4284                 return -EACCES;
4285         }
4286         /* associate_vsi field is NULL for floating VEB */
4287         if (veb->associate_vsi != NULL) {
4288                 vsi = veb->associate_vsi;
4289                 hw = I40E_VSI_TO_HW(vsi);
4290
4291                 vsi->uplink_seid = veb->uplink_seid;
4292                 vsi->veb = NULL;
4293         } else {
4294                 veb->associate_pf->main_vsi->floating_veb = NULL;
4295                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4296         }
4297
4298         i40e_aq_delete_element(hw, veb->seid, NULL);
4299         rte_free(veb);
4300         return I40E_SUCCESS;
4301 }
4302
4303 /* Setup a veb */
4304 static struct i40e_veb *
4305 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4306 {
4307         struct i40e_veb *veb;
4308         int ret;
4309         struct i40e_hw *hw;
4310
4311         if (pf == NULL) {
4312                 PMD_DRV_LOG(ERR,
4313                             "veb setup failed, associated PF shouldn't null");
4314                 return NULL;
4315         }
4316         hw = I40E_PF_TO_HW(pf);
4317
4318         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4319         if (!veb) {
4320                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4321                 goto fail;
4322         }
4323
4324         veb->associate_vsi = vsi;
4325         veb->associate_pf = pf;
4326         TAILQ_INIT(&veb->head);
4327         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4328
4329         /* create floating veb if vsi is NULL */
4330         if (vsi != NULL) {
4331                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4332                                       I40E_DEFAULT_TCMAP, false,
4333                                       &veb->seid, false, NULL);
4334         } else {
4335                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4336                                       true, &veb->seid, false, NULL);
4337         }
4338
4339         if (ret != I40E_SUCCESS) {
4340                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4341                             hw->aq.asq_last_status);
4342                 goto fail;
4343         }
4344         veb->enabled_tc = I40E_DEFAULT_TCMAP;
4345
4346         /* get statistics index */
4347         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4348                                 &veb->stats_idx, NULL, NULL, NULL);
4349         if (ret != I40E_SUCCESS) {
4350                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4351                             hw->aq.asq_last_status);
4352                 goto fail;
4353         }
4354         /* Get VEB bandwidth, to be implemented */
4355         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4356         if (vsi)
4357                 vsi->uplink_seid = veb->seid;
4358
4359         return veb;
4360 fail:
4361         rte_free(veb);
4362         return NULL;
4363 }
4364
4365 int
4366 i40e_vsi_release(struct i40e_vsi *vsi)
4367 {
4368         struct i40e_pf *pf;
4369         struct i40e_hw *hw;
4370         struct i40e_vsi_list *vsi_list;
4371         void *temp;
4372         int ret;
4373         struct i40e_mac_filter *f;
4374         uint16_t user_param;
4375
4376         if (!vsi)
4377                 return I40E_SUCCESS;
4378
4379         if (!vsi->adapter)
4380                 return -EFAULT;
4381
4382         user_param = vsi->user_param;
4383
4384         pf = I40E_VSI_TO_PF(vsi);
4385         hw = I40E_VSI_TO_HW(vsi);
4386
4387         /* VSI has child to attach, release child first */
4388         if (vsi->veb) {
4389                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4390                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4391                                 return -1;
4392                 }
4393                 i40e_veb_release(vsi->veb);
4394         }
4395
4396         if (vsi->floating_veb) {
4397                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4398                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4399                                 return -1;
4400                 }
4401         }
4402
4403         /* Remove all macvlan filters of the VSI */
4404         i40e_vsi_remove_all_macvlan_filter(vsi);
4405         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4406                 rte_free(f);
4407
4408         if (vsi->type != I40E_VSI_MAIN &&
4409             ((vsi->type != I40E_VSI_SRIOV) ||
4410             !pf->floating_veb_list[user_param])) {
4411                 /* Remove vsi from parent's sibling list */
4412                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4413                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4414                         return I40E_ERR_PARAM;
4415                 }
4416                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4417                                 &vsi->sib_vsi_list, list);
4418
4419                 /* Remove all switch element of the VSI */
4420                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4421                 if (ret != I40E_SUCCESS)
4422                         PMD_DRV_LOG(ERR, "Failed to delete element");
4423         }
4424
4425         if ((vsi->type == I40E_VSI_SRIOV) &&
4426             pf->floating_veb_list[user_param]) {
4427                 /* Remove vsi from parent's sibling list */
4428                 if (vsi->parent_vsi == NULL ||
4429                     vsi->parent_vsi->floating_veb == NULL) {
4430                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4431                         return I40E_ERR_PARAM;
4432                 }
4433                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4434                              &vsi->sib_vsi_list, list);
4435
4436                 /* Remove all switch element of the VSI */
4437                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4438                 if (ret != I40E_SUCCESS)
4439                         PMD_DRV_LOG(ERR, "Failed to delete element");
4440         }
4441
4442         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4443
4444         if (vsi->type != I40E_VSI_SRIOV)
4445                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4446         rte_free(vsi);
4447
4448         return I40E_SUCCESS;
4449 }
4450
4451 static int
4452 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4453 {
4454         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4455         struct i40e_aqc_remove_macvlan_element_data def_filter;
4456         struct i40e_mac_filter_info filter;
4457         int ret;
4458
4459         if (vsi->type != I40E_VSI_MAIN)
4460                 return I40E_ERR_CONFIG;
4461         memset(&def_filter, 0, sizeof(def_filter));
4462         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4463                                         ETH_ADDR_LEN);
4464         def_filter.vlan_tag = 0;
4465         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4466                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4467         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4468         if (ret != I40E_SUCCESS) {
4469                 struct i40e_mac_filter *f;
4470                 struct ether_addr *mac;
4471
4472                 PMD_DRV_LOG(WARNING,
4473                         "Cannot remove the default macvlan filter");
4474                 /* It needs to add the permanent mac into mac list */
4475                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4476                 if (f == NULL) {
4477                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4478                         return I40E_ERR_NO_MEMORY;
4479                 }
4480                 mac = &f->mac_info.mac_addr;
4481                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4482                                 ETH_ADDR_LEN);
4483                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4484                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4485                 vsi->mac_num++;
4486
4487                 return ret;
4488         }
4489         (void)rte_memcpy(&filter.mac_addr,
4490                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4491         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4492         return i40e_vsi_add_mac(vsi, &filter);
4493 }
4494
4495 /*
4496  * i40e_vsi_get_bw_config - Query VSI BW Information
4497  * @vsi: the VSI to be queried
4498  *
4499  * Returns 0 on success, negative value on failure
4500  */
4501 static enum i40e_status_code
4502 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4503 {
4504         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4505         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4506         struct i40e_hw *hw = &vsi->adapter->hw;
4507         i40e_status ret;
4508         int i;
4509         uint32_t bw_max;
4510
4511         memset(&bw_config, 0, sizeof(bw_config));
4512         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4513         if (ret != I40E_SUCCESS) {
4514                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4515                             hw->aq.asq_last_status);
4516                 return ret;
4517         }
4518
4519         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4520         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4521                                         &ets_sla_config, NULL);
4522         if (ret != I40E_SUCCESS) {
4523                 PMD_DRV_LOG(ERR,
4524                         "VSI failed to get TC bandwdith configuration %u",
4525                         hw->aq.asq_last_status);
4526                 return ret;
4527         }
4528
4529         /* store and print out BW info */
4530         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4531         vsi->bw_info.bw_max = bw_config.max_bw;
4532         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4533         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4534         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4535                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4536                      I40E_16_BIT_WIDTH);
4537         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4538                 vsi->bw_info.bw_ets_share_credits[i] =
4539                                 ets_sla_config.share_credits[i];
4540                 vsi->bw_info.bw_ets_credits[i] =
4541                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4542                 /* 4 bits per TC, 4th bit is reserved */
4543                 vsi->bw_info.bw_ets_max[i] =
4544                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4545                                   RTE_LEN2MASK(3, uint8_t));
4546                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4547                             vsi->bw_info.bw_ets_share_credits[i]);
4548                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4549                             vsi->bw_info.bw_ets_credits[i]);
4550                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4551                             vsi->bw_info.bw_ets_max[i]);
4552         }
4553
4554         return I40E_SUCCESS;
4555 }
4556
4557 /* i40e_enable_pf_lb
4558  * @pf: pointer to the pf structure
4559  *
4560  * allow loopback on pf
4561  */
4562 static inline void
4563 i40e_enable_pf_lb(struct i40e_pf *pf)
4564 {
4565         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4566         struct i40e_vsi_context ctxt;
4567         int ret;
4568
4569         /* Use the FW API if FW >= v5.0 */
4570         if (hw->aq.fw_maj_ver < 5) {
4571                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4572                 return;
4573         }
4574
4575         memset(&ctxt, 0, sizeof(ctxt));
4576         ctxt.seid = pf->main_vsi_seid;
4577         ctxt.pf_num = hw->pf_id;
4578         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4579         if (ret) {
4580                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4581                             ret, hw->aq.asq_last_status);
4582                 return;
4583         }
4584         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4585         ctxt.info.valid_sections =
4586                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4587         ctxt.info.switch_id |=
4588                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4589
4590         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4591         if (ret)
4592                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4593                             hw->aq.asq_last_status);
4594 }
4595
4596 /* Setup a VSI */
4597 struct i40e_vsi *
4598 i40e_vsi_setup(struct i40e_pf *pf,
4599                enum i40e_vsi_type type,
4600                struct i40e_vsi *uplink_vsi,
4601                uint16_t user_param)
4602 {
4603         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4604         struct i40e_vsi *vsi;
4605         struct i40e_mac_filter_info filter;
4606         int ret;
4607         struct i40e_vsi_context ctxt;
4608         struct ether_addr broadcast =
4609                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4610
4611         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4612             uplink_vsi == NULL) {
4613                 PMD_DRV_LOG(ERR,
4614                         "VSI setup failed, VSI link shouldn't be NULL");
4615                 return NULL;
4616         }
4617
4618         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4619                 PMD_DRV_LOG(ERR,
4620                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4621                 return NULL;
4622         }
4623
4624         /* two situations
4625          * 1.type is not MAIN and uplink vsi is not NULL
4626          * If uplink vsi didn't setup VEB, create one first under veb field
4627          * 2.type is SRIOV and the uplink is NULL
4628          * If floating VEB is NULL, create one veb under floating veb field
4629          */
4630
4631         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4632             uplink_vsi->veb == NULL) {
4633                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4634
4635                 if (uplink_vsi->veb == NULL) {
4636                         PMD_DRV_LOG(ERR, "VEB setup failed");
4637                         return NULL;
4638                 }
4639                 /* set ALLOWLOOPBACk on pf, when veb is created */
4640                 i40e_enable_pf_lb(pf);
4641         }
4642
4643         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4644             pf->main_vsi->floating_veb == NULL) {
4645                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4646
4647                 if (pf->main_vsi->floating_veb == NULL) {
4648                         PMD_DRV_LOG(ERR, "VEB setup failed");
4649                         return NULL;
4650                 }
4651         }
4652
4653         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4654         if (!vsi) {
4655                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4656                 return NULL;
4657         }
4658         TAILQ_INIT(&vsi->mac_list);
4659         vsi->type = type;
4660         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4661         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4662         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4663         vsi->user_param = user_param;
4664         vsi->vlan_anti_spoof_on = 0;
4665         /* Allocate queues */
4666         switch (vsi->type) {
4667         case I40E_VSI_MAIN  :
4668                 vsi->nb_qps = pf->lan_nb_qps;
4669                 break;
4670         case I40E_VSI_SRIOV :
4671                 vsi->nb_qps = pf->vf_nb_qps;
4672                 break;
4673         case I40E_VSI_VMDQ2:
4674                 vsi->nb_qps = pf->vmdq_nb_qps;
4675                 break;
4676         case I40E_VSI_FDIR:
4677                 vsi->nb_qps = pf->fdir_nb_qps;
4678                 break;
4679         default:
4680                 goto fail_mem;
4681         }
4682         /*
4683          * The filter status descriptor is reported in rx queue 0,
4684          * while the tx queue for fdir filter programming has no
4685          * such constraints, can be non-zero queues.
4686          * To simplify it, choose FDIR vsi use queue 0 pair.
4687          * To make sure it will use queue 0 pair, queue allocation
4688          * need be done before this function is called
4689          */
4690         if (type != I40E_VSI_FDIR) {
4691                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4692                         if (ret < 0) {
4693                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4694                                                 vsi->seid, ret);
4695                                 goto fail_mem;
4696                         }
4697                         vsi->base_queue = ret;
4698         } else
4699                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4700
4701         /* VF has MSIX interrupt in VF range, don't allocate here */
4702         if (type == I40E_VSI_MAIN) {
4703                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4704                                           RTE_MIN(vsi->nb_qps,
4705                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4706                 if (ret < 0) {
4707                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4708                                     vsi->seid, ret);
4709                         goto fail_queue_alloc;
4710                 }
4711                 vsi->msix_intr = ret;
4712                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4713         } else if (type != I40E_VSI_SRIOV) {
4714                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4715                 if (ret < 0) {
4716                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4717                         goto fail_queue_alloc;
4718                 }
4719                 vsi->msix_intr = ret;
4720                 vsi->nb_msix = 1;
4721         } else {
4722                 vsi->msix_intr = 0;
4723                 vsi->nb_msix = 0;
4724         }
4725
4726         /* Add VSI */
4727         if (type == I40E_VSI_MAIN) {
4728                 /* For main VSI, no need to add since it's default one */
4729                 vsi->uplink_seid = pf->mac_seid;
4730                 vsi->seid = pf->main_vsi_seid;
4731                 /* Bind queues with specific MSIX interrupt */
4732                 /**
4733                  * Needs 2 interrupt at least, one for misc cause which will
4734                  * enabled from OS side, Another for queues binding the
4735                  * interrupt from device side only.
4736                  */
4737
4738                 /* Get default VSI parameters from hardware */
4739                 memset(&ctxt, 0, sizeof(ctxt));
4740                 ctxt.seid = vsi->seid;
4741                 ctxt.pf_num = hw->pf_id;
4742                 ctxt.uplink_seid = vsi->uplink_seid;
4743                 ctxt.vf_num = 0;
4744                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4745                 if (ret != I40E_SUCCESS) {
4746                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4747                         goto fail_msix_alloc;
4748                 }
4749                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4750                         sizeof(struct i40e_aqc_vsi_properties_data));
4751                 vsi->vsi_id = ctxt.vsi_number;
4752                 vsi->info.valid_sections = 0;
4753
4754                 /* Configure tc, enabled TC0 only */
4755                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4756                         I40E_SUCCESS) {
4757                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4758                         goto fail_msix_alloc;
4759                 }
4760
4761                 /* TC, queue mapping */
4762                 memset(&ctxt, 0, sizeof(ctxt));
4763                 vsi->info.valid_sections |=
4764                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4765                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4766                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4767                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4768                         sizeof(struct i40e_aqc_vsi_properties_data));
4769                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4770                                                 I40E_DEFAULT_TCMAP);
4771                 if (ret != I40E_SUCCESS) {
4772                         PMD_DRV_LOG(ERR,
4773                                 "Failed to configure TC queue mapping");
4774                         goto fail_msix_alloc;
4775                 }
4776                 ctxt.seid = vsi->seid;
4777                 ctxt.pf_num = hw->pf_id;
4778                 ctxt.uplink_seid = vsi->uplink_seid;
4779                 ctxt.vf_num = 0;
4780
4781                 /* Update VSI parameters */
4782                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4783                 if (ret != I40E_SUCCESS) {
4784                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4785                         goto fail_msix_alloc;
4786                 }
4787
4788                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4789                                                 sizeof(vsi->info.tc_mapping));
4790                 (void)rte_memcpy(&vsi->info.queue_mapping,
4791                                 &ctxt.info.queue_mapping,
4792                         sizeof(vsi->info.queue_mapping));
4793                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4794                 vsi->info.valid_sections = 0;
4795
4796                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4797                                 ETH_ADDR_LEN);
4798
4799                 /**
4800                  * Updating default filter settings are necessary to prevent
4801                  * reception of tagged packets.
4802                  * Some old firmware configurations load a default macvlan
4803                  * filter which accepts both tagged and untagged packets.
4804                  * The updating is to use a normal filter instead if needed.
4805                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4806                  * The firmware with correct configurations load the default
4807                  * macvlan filter which is expected and cannot be removed.
4808                  */
4809                 i40e_update_default_filter_setting(vsi);
4810                 i40e_config_qinq(hw, vsi);
4811         } else if (type == I40E_VSI_SRIOV) {
4812                 memset(&ctxt, 0, sizeof(ctxt));
4813                 /**
4814                  * For other VSI, the uplink_seid equals to uplink VSI's
4815                  * uplink_seid since they share same VEB
4816                  */
4817                 if (uplink_vsi == NULL)
4818                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4819                 else
4820                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4821                 ctxt.pf_num = hw->pf_id;
4822                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4823                 ctxt.uplink_seid = vsi->uplink_seid;
4824                 ctxt.connection_type = 0x1;
4825                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4826
4827                 /* Use the VEB configuration if FW >= v5.0 */
4828                 if (hw->aq.fw_maj_ver >= 5) {
4829                         /* Configure switch ID */
4830                         ctxt.info.valid_sections |=
4831                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4832                         ctxt.info.switch_id =
4833                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4834                 }
4835
4836                 /* Configure port/vlan */
4837                 ctxt.info.valid_sections |=
4838                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4839                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4840                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4841                                                 I40E_DEFAULT_TCMAP);
4842                 if (ret != I40E_SUCCESS) {
4843                         PMD_DRV_LOG(ERR,
4844                                 "Failed to configure TC queue mapping");
4845                         goto fail_msix_alloc;
4846                 }
4847                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4848                 ctxt.info.valid_sections |=
4849                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4850                 /**
4851                  * Since VSI is not created yet, only configure parameter,
4852                  * will add vsi below.
4853                  */
4854
4855                 i40e_config_qinq(hw, vsi);
4856         } else if (type == I40E_VSI_VMDQ2) {
4857                 memset(&ctxt, 0, sizeof(ctxt));
4858                 /*
4859                  * For other VSI, the uplink_seid equals to uplink VSI's
4860                  * uplink_seid since they share same VEB
4861                  */
4862                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4863                 ctxt.pf_num = hw->pf_id;
4864                 ctxt.vf_num = 0;
4865                 ctxt.uplink_seid = vsi->uplink_seid;
4866                 ctxt.connection_type = 0x1;
4867                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4868
4869                 ctxt.info.valid_sections |=
4870                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4871                 /* user_param carries flag to enable loop back */
4872                 if (user_param) {
4873                         ctxt.info.switch_id =
4874                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4875                         ctxt.info.switch_id |=
4876                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4877                 }
4878
4879                 /* Configure port/vlan */
4880                 ctxt.info.valid_sections |=
4881                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4882                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4883                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4884                                                 I40E_DEFAULT_TCMAP);
4885                 if (ret != I40E_SUCCESS) {
4886                         PMD_DRV_LOG(ERR,
4887                                 "Failed to configure TC queue mapping");
4888                         goto fail_msix_alloc;
4889                 }
4890                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4891                 ctxt.info.valid_sections |=
4892                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4893         } else if (type == I40E_VSI_FDIR) {
4894                 memset(&ctxt, 0, sizeof(ctxt));
4895                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4896                 ctxt.pf_num = hw->pf_id;
4897                 ctxt.vf_num = 0;
4898                 ctxt.uplink_seid = vsi->uplink_seid;
4899                 ctxt.connection_type = 0x1;     /* regular data port */
4900                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4901                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4902                                                 I40E_DEFAULT_TCMAP);
4903                 if (ret != I40E_SUCCESS) {
4904                         PMD_DRV_LOG(ERR,
4905                                 "Failed to configure TC queue mapping.");
4906                         goto fail_msix_alloc;
4907                 }
4908                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4909                 ctxt.info.valid_sections |=
4910                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4911         } else {
4912                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4913                 goto fail_msix_alloc;
4914         }
4915
4916         if (vsi->type != I40E_VSI_MAIN) {
4917                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4918                 if (ret != I40E_SUCCESS) {
4919                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4920                                     hw->aq.asq_last_status);
4921                         goto fail_msix_alloc;
4922                 }
4923                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4924                 vsi->info.valid_sections = 0;
4925                 vsi->seid = ctxt.seid;
4926                 vsi->vsi_id = ctxt.vsi_number;
4927                 vsi->sib_vsi_list.vsi = vsi;
4928                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4929                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4930                                           &vsi->sib_vsi_list, list);
4931                 } else {
4932                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4933                                           &vsi->sib_vsi_list, list);
4934                 }
4935         }
4936
4937         /* MAC/VLAN configuration */
4938         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4939         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4940
4941         ret = i40e_vsi_add_mac(vsi, &filter);
4942         if (ret != I40E_SUCCESS) {
4943                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4944                 goto fail_msix_alloc;
4945         }
4946
4947         /* Get VSI BW information */
4948         i40e_vsi_get_bw_config(vsi);
4949         return vsi;
4950 fail_msix_alloc:
4951         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4952 fail_queue_alloc:
4953         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4954 fail_mem:
4955         rte_free(vsi);
4956         return NULL;
4957 }
4958
4959 /* Configure vlan filter on or off */
4960 int
4961 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4962 {
4963         int i, num;
4964         struct i40e_mac_filter *f;
4965         void *temp;
4966         struct i40e_mac_filter_info *mac_filter;
4967         enum rte_mac_filter_type desired_filter;
4968         int ret = I40E_SUCCESS;
4969
4970         if (on) {
4971                 /* Filter to match MAC and VLAN */
4972                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4973         } else {
4974                 /* Filter to match only MAC */
4975                 desired_filter = RTE_MAC_PERFECT_MATCH;
4976         }
4977
4978         num = vsi->mac_num;
4979
4980         mac_filter = rte_zmalloc("mac_filter_info_data",
4981                                  num * sizeof(*mac_filter), 0);
4982         if (mac_filter == NULL) {
4983                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4984                 return I40E_ERR_NO_MEMORY;
4985         }
4986
4987         i = 0;
4988
4989         /* Remove all existing mac */
4990         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
4991                 mac_filter[i] = f->mac_info;
4992                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4993                 if (ret) {
4994                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4995                                     on ? "enable" : "disable");
4996                         goto DONE;
4997                 }
4998                 i++;
4999         }
5000
5001         /* Override with new filter */
5002         for (i = 0; i < num; i++) {
5003                 mac_filter[i].filter_type = desired_filter;
5004                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5005                 if (ret) {
5006                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5007                                     on ? "enable" : "disable");
5008                         goto DONE;
5009                 }
5010         }
5011
5012 DONE:
5013         rte_free(mac_filter);
5014         return ret;
5015 }
5016
5017 /* Configure vlan stripping on or off */
5018 int
5019 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5020 {
5021         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5022         struct i40e_vsi_context ctxt;
5023         uint8_t vlan_flags;
5024         int ret = I40E_SUCCESS;
5025
5026         /* Check if it has been already on or off */
5027         if (vsi->info.valid_sections &
5028                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5029                 if (on) {
5030                         if ((vsi->info.port_vlan_flags &
5031                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5032                                 return 0; /* already on */
5033                 } else {
5034                         if ((vsi->info.port_vlan_flags &
5035                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5036                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5037                                 return 0; /* already off */
5038                 }
5039         }
5040
5041         if (on)
5042                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5043         else
5044                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5045         vsi->info.valid_sections =
5046                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5047         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5048         vsi->info.port_vlan_flags |= vlan_flags;
5049         ctxt.seid = vsi->seid;
5050         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5051         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5052         if (ret)
5053                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5054                             on ? "enable" : "disable");
5055
5056         return ret;
5057 }
5058
5059 static int
5060 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5061 {
5062         struct rte_eth_dev_data *data = dev->data;
5063         int ret;
5064         int mask = 0;
5065
5066         /* Apply vlan offload setting */
5067         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5068         i40e_vlan_offload_set(dev, mask);
5069
5070         /* Apply double-vlan setting, not implemented yet */
5071
5072         /* Apply pvid setting */
5073         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5074                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5075         if (ret)
5076                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5077
5078         return ret;
5079 }
5080
5081 static int
5082 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5083 {
5084         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5085
5086         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5087 }
5088
5089 static int
5090 i40e_update_flow_control(struct i40e_hw *hw)
5091 {
5092 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5093         struct i40e_link_status link_status;
5094         uint32_t rxfc = 0, txfc = 0, reg;
5095         uint8_t an_info;
5096         int ret;
5097
5098         memset(&link_status, 0, sizeof(link_status));
5099         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5100         if (ret != I40E_SUCCESS) {
5101                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5102                 goto write_reg; /* Disable flow control */
5103         }
5104
5105         an_info = hw->phy.link_info.an_info;
5106         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5107                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5108                 ret = I40E_ERR_NOT_READY;
5109                 goto write_reg; /* Disable flow control */
5110         }
5111         /**
5112          * If link auto negotiation is enabled, flow control needs to
5113          * be configured according to it
5114          */
5115         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5116         case I40E_LINK_PAUSE_RXTX:
5117                 rxfc = 1;
5118                 txfc = 1;
5119                 hw->fc.current_mode = I40E_FC_FULL;
5120                 break;
5121         case I40E_AQ_LINK_PAUSE_RX:
5122                 rxfc = 1;
5123                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5124                 break;
5125         case I40E_AQ_LINK_PAUSE_TX:
5126                 txfc = 1;
5127                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5128                 break;
5129         default:
5130                 hw->fc.current_mode = I40E_FC_NONE;
5131                 break;
5132         }
5133
5134 write_reg:
5135         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5136                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5137         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5138         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5139         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5140         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5141
5142         return ret;
5143 }
5144
5145 /* PF setup */
5146 static int
5147 i40e_pf_setup(struct i40e_pf *pf)
5148 {
5149         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5150         struct i40e_filter_control_settings settings;
5151         struct i40e_vsi *vsi;
5152         int ret;
5153
5154         /* Clear all stats counters */
5155         pf->offset_loaded = FALSE;
5156         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5157         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5158
5159         ret = i40e_pf_get_switch_config(pf);
5160         if (ret != I40E_SUCCESS) {
5161                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5162                 return ret;
5163         }
5164         if (pf->flags & I40E_FLAG_FDIR) {
5165                 /* make queue allocated first, let FDIR use queue pair 0*/
5166                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5167                 if (ret != I40E_FDIR_QUEUE_ID) {
5168                         PMD_DRV_LOG(ERR,
5169                                 "queue allocation fails for FDIR: ret =%d",
5170                                 ret);
5171                         pf->flags &= ~I40E_FLAG_FDIR;
5172                 }
5173         }
5174         /*  main VSI setup */
5175         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5176         if (!vsi) {
5177                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5178                 return I40E_ERR_NOT_READY;
5179         }
5180         pf->main_vsi = vsi;
5181
5182         /* Configure filter control */
5183         memset(&settings, 0, sizeof(settings));
5184         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5185                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5186         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5187                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5188         else {
5189                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5190                         hw->func_caps.rss_table_size);
5191                 return I40E_ERR_PARAM;
5192         }
5193         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5194                 hw->func_caps.rss_table_size);
5195         pf->hash_lut_size = hw->func_caps.rss_table_size;
5196
5197         /* Enable ethtype and macvlan filters */
5198         settings.enable_ethtype = TRUE;
5199         settings.enable_macvlan = TRUE;
5200         ret = i40e_set_filter_control(hw, &settings);
5201         if (ret)
5202                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5203                                                                 ret);
5204
5205         /* Update flow control according to the auto negotiation */
5206         i40e_update_flow_control(hw);
5207
5208         return I40E_SUCCESS;
5209 }
5210
5211 int
5212 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5213 {
5214         uint32_t reg;
5215         uint16_t j;
5216
5217         /**
5218          * Set or clear TX Queue Disable flags,
5219          * which is required by hardware.
5220          */
5221         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5222         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5223
5224         /* Wait until the request is finished */
5225         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5226                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5227                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5228                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5229                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5230                                                         & 0x1))) {
5231                         break;
5232                 }
5233         }
5234         if (on) {
5235                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5236                         return I40E_SUCCESS; /* already on, skip next steps */
5237
5238                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5239                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5240         } else {
5241                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5242                         return I40E_SUCCESS; /* already off, skip next steps */
5243                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5244         }
5245         /* Write the register */
5246         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5247         /* Check the result */
5248         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5249                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5250                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5251                 if (on) {
5252                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5253                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5254                                 break;
5255                 } else {
5256                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5257                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5258                                 break;
5259                 }
5260         }
5261         /* Check if it is timeout */
5262         if (j >= I40E_CHK_Q_ENA_COUNT) {
5263                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5264                             (on ? "enable" : "disable"), q_idx);
5265                 return I40E_ERR_TIMEOUT;
5266         }
5267
5268         return I40E_SUCCESS;
5269 }
5270
5271 /* Swith on or off the tx queues */
5272 static int
5273 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5274 {
5275         struct rte_eth_dev_data *dev_data = pf->dev_data;
5276         struct i40e_tx_queue *txq;
5277         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5278         uint16_t i;
5279         int ret;
5280
5281         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5282                 txq = dev_data->tx_queues[i];
5283                 /* Don't operate the queue if not configured or
5284                  * if starting only per queue */
5285                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5286                         continue;
5287                 if (on)
5288                         ret = i40e_dev_tx_queue_start(dev, i);
5289                 else
5290                         ret = i40e_dev_tx_queue_stop(dev, i);
5291                 if ( ret != I40E_SUCCESS)
5292                         return ret;
5293         }
5294
5295         return I40E_SUCCESS;
5296 }
5297
5298 int
5299 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5300 {
5301         uint32_t reg;
5302         uint16_t j;
5303
5304         /* Wait until the request is finished */
5305         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5306                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5307                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5308                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5309                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5310                         break;
5311         }
5312
5313         if (on) {
5314                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5315                         return I40E_SUCCESS; /* Already on, skip next steps */
5316                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5317         } else {
5318                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5319                         return I40E_SUCCESS; /* Already off, skip next steps */
5320                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5321         }
5322
5323         /* Write the register */
5324         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5325         /* Check the result */
5326         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5327                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5328                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5329                 if (on) {
5330                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5331                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5332                                 break;
5333                 } else {
5334                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5335                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5336                                 break;
5337                 }
5338         }
5339
5340         /* Check if it is timeout */
5341         if (j >= I40E_CHK_Q_ENA_COUNT) {
5342                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5343                             (on ? "enable" : "disable"), q_idx);
5344                 return I40E_ERR_TIMEOUT;
5345         }
5346
5347         return I40E_SUCCESS;
5348 }
5349 /* Switch on or off the rx queues */
5350 static int
5351 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5352 {
5353         struct rte_eth_dev_data *dev_data = pf->dev_data;
5354         struct i40e_rx_queue *rxq;
5355         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5356         uint16_t i;
5357         int ret;
5358
5359         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5360                 rxq = dev_data->rx_queues[i];
5361                 /* Don't operate the queue if not configured or
5362                  * if starting only per queue */
5363                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5364                         continue;
5365                 if (on)
5366                         ret = i40e_dev_rx_queue_start(dev, i);
5367                 else
5368                         ret = i40e_dev_rx_queue_stop(dev, i);
5369                 if (ret != I40E_SUCCESS)
5370                         return ret;
5371         }
5372
5373         return I40E_SUCCESS;
5374 }
5375
5376 /* Switch on or off all the rx/tx queues */
5377 int
5378 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5379 {
5380         int ret;
5381
5382         if (on) {
5383                 /* enable rx queues before enabling tx queues */
5384                 ret = i40e_dev_switch_rx_queues(pf, on);
5385                 if (ret) {
5386                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5387                         return ret;
5388                 }
5389                 ret = i40e_dev_switch_tx_queues(pf, on);
5390         } else {
5391                 /* Stop tx queues before stopping rx queues */
5392                 ret = i40e_dev_switch_tx_queues(pf, on);
5393                 if (ret) {
5394                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5395                         return ret;
5396                 }
5397                 ret = i40e_dev_switch_rx_queues(pf, on);
5398         }
5399
5400         return ret;
5401 }
5402
5403 /* Initialize VSI for TX */
5404 static int
5405 i40e_dev_tx_init(struct i40e_pf *pf)
5406 {
5407         struct rte_eth_dev_data *data = pf->dev_data;
5408         uint16_t i;
5409         uint32_t ret = I40E_SUCCESS;
5410         struct i40e_tx_queue *txq;
5411
5412         for (i = 0; i < data->nb_tx_queues; i++) {
5413                 txq = data->tx_queues[i];
5414                 if (!txq || !txq->q_set)
5415                         continue;
5416                 ret = i40e_tx_queue_init(txq);
5417                 if (ret != I40E_SUCCESS)
5418                         break;
5419         }
5420         if (ret == I40E_SUCCESS)
5421                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5422                                      ->eth_dev);
5423
5424         return ret;
5425 }
5426
5427 /* Initialize VSI for RX */
5428 static int
5429 i40e_dev_rx_init(struct i40e_pf *pf)
5430 {
5431         struct rte_eth_dev_data *data = pf->dev_data;
5432         int ret = I40E_SUCCESS;
5433         uint16_t i;
5434         struct i40e_rx_queue *rxq;
5435
5436         i40e_pf_config_mq_rx(pf);
5437         for (i = 0; i < data->nb_rx_queues; i++) {
5438                 rxq = data->rx_queues[i];
5439                 if (!rxq || !rxq->q_set)
5440                         continue;
5441
5442                 ret = i40e_rx_queue_init(rxq);
5443                 if (ret != I40E_SUCCESS) {
5444                         PMD_DRV_LOG(ERR,
5445                                 "Failed to do RX queue initialization");
5446                         break;
5447                 }
5448         }
5449         if (ret == I40E_SUCCESS)
5450                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5451                                      ->eth_dev);
5452
5453         return ret;
5454 }
5455
5456 static int
5457 i40e_dev_rxtx_init(struct i40e_pf *pf)
5458 {
5459         int err;
5460
5461         err = i40e_dev_tx_init(pf);
5462         if (err) {
5463                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5464                 return err;
5465         }
5466         err = i40e_dev_rx_init(pf);
5467         if (err) {
5468                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5469                 return err;
5470         }
5471
5472         return err;
5473 }
5474
5475 static int
5476 i40e_vmdq_setup(struct rte_eth_dev *dev)
5477 {
5478         struct rte_eth_conf *conf = &dev->data->dev_conf;
5479         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5480         int i, err, conf_vsis, j, loop;
5481         struct i40e_vsi *vsi;
5482         struct i40e_vmdq_info *vmdq_info;
5483         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5484         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5485
5486         /*
5487          * Disable interrupt to avoid message from VF. Furthermore, it will
5488          * avoid race condition in VSI creation/destroy.
5489          */
5490         i40e_pf_disable_irq0(hw);
5491
5492         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5493                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5494                 return -ENOTSUP;
5495         }
5496
5497         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5498         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5499                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5500                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5501                         pf->max_nb_vmdq_vsi);
5502                 return -ENOTSUP;
5503         }
5504
5505         if (pf->vmdq != NULL) {
5506                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5507                 return 0;
5508         }
5509
5510         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5511                                 sizeof(*vmdq_info) * conf_vsis, 0);
5512
5513         if (pf->vmdq == NULL) {
5514                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5515                 return -ENOMEM;
5516         }
5517
5518         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5519
5520         /* Create VMDQ VSI */
5521         for (i = 0; i < conf_vsis; i++) {
5522                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5523                                 vmdq_conf->enable_loop_back);
5524                 if (vsi == NULL) {
5525                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5526                         err = -1;
5527                         goto err_vsi_setup;
5528                 }
5529                 vmdq_info = &pf->vmdq[i];
5530                 vmdq_info->pf = pf;
5531                 vmdq_info->vsi = vsi;
5532         }
5533         pf->nb_cfg_vmdq_vsi = conf_vsis;
5534
5535         /* Configure Vlan */
5536         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5537         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5538                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5539                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5540                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5541                                         vmdq_conf->pool_map[i].vlan_id, j);
5542
5543                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5544                                                 vmdq_conf->pool_map[i].vlan_id);
5545                                 if (err) {
5546                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5547                                         err = -1;
5548                                         goto err_vsi_setup;
5549                                 }
5550                         }
5551                 }
5552         }
5553
5554         i40e_pf_enable_irq0(hw);
5555
5556         return 0;
5557
5558 err_vsi_setup:
5559         for (i = 0; i < conf_vsis; i++)
5560                 if (pf->vmdq[i].vsi == NULL)
5561                         break;
5562                 else
5563                         i40e_vsi_release(pf->vmdq[i].vsi);
5564
5565         rte_free(pf->vmdq);
5566         pf->vmdq = NULL;
5567         i40e_pf_enable_irq0(hw);
5568         return err;
5569 }
5570
5571 static void
5572 i40e_stat_update_32(struct i40e_hw *hw,
5573                    uint32_t reg,
5574                    bool offset_loaded,
5575                    uint64_t *offset,
5576                    uint64_t *stat)
5577 {
5578         uint64_t new_data;
5579
5580         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5581         if (!offset_loaded)
5582                 *offset = new_data;
5583
5584         if (new_data >= *offset)
5585                 *stat = (uint64_t)(new_data - *offset);
5586         else
5587                 *stat = (uint64_t)((new_data +
5588                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5589 }
5590
5591 static void
5592 i40e_stat_update_48(struct i40e_hw *hw,
5593                    uint32_t hireg,
5594                    uint32_t loreg,
5595                    bool offset_loaded,
5596                    uint64_t *offset,
5597                    uint64_t *stat)
5598 {
5599         uint64_t new_data;
5600
5601         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5602         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5603                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5604
5605         if (!offset_loaded)
5606                 *offset = new_data;
5607
5608         if (new_data >= *offset)
5609                 *stat = new_data - *offset;
5610         else
5611                 *stat = (uint64_t)((new_data +
5612                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5613
5614         *stat &= I40E_48_BIT_MASK;
5615 }
5616
5617 /* Disable IRQ0 */
5618 void
5619 i40e_pf_disable_irq0(struct i40e_hw *hw)
5620 {
5621         /* Disable all interrupt types */
5622         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5623         I40E_WRITE_FLUSH(hw);
5624 }
5625
5626 /* Enable IRQ0 */
5627 void
5628 i40e_pf_enable_irq0(struct i40e_hw *hw)
5629 {
5630         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5631                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5632                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5633                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5634         I40E_WRITE_FLUSH(hw);
5635 }
5636
5637 static void
5638 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5639 {
5640         /* read pending request and disable first */
5641         i40e_pf_disable_irq0(hw);
5642         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5643         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5644                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5645
5646         if (no_queue)
5647                 /* Link no queues with irq0 */
5648                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5649                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5650 }
5651
5652 static void
5653 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5654 {
5655         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5656         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5657         int i;
5658         uint16_t abs_vf_id;
5659         uint32_t index, offset, val;
5660
5661         if (!pf->vfs)
5662                 return;
5663         /**
5664          * Try to find which VF trigger a reset, use absolute VF id to access
5665          * since the reg is global register.
5666          */
5667         for (i = 0; i < pf->vf_num; i++) {
5668                 abs_vf_id = hw->func_caps.vf_base_id + i;
5669                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5670                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5671                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5672                 /* VFR event occured */
5673                 if (val & (0x1 << offset)) {
5674                         int ret;
5675
5676                         /* Clear the event first */
5677                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5678                                                         (0x1 << offset));
5679                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5680                         /**
5681                          * Only notify a VF reset event occured,
5682                          * don't trigger another SW reset
5683                          */
5684                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5685                         if (ret != I40E_SUCCESS)
5686                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5687                 }
5688         }
5689 }
5690
5691 static void
5692 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5693 {
5694         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5695         struct i40e_virtchnl_pf_event event;
5696         int i;
5697
5698         event.event = I40E_VIRTCHNL_EVENT_LINK_CHANGE;
5699         event.event_data.link_event.link_status =
5700                 dev->data->dev_link.link_status;
5701         event.event_data.link_event.link_speed =
5702                 (enum i40e_aq_link_speed)dev->data->dev_link.link_speed;
5703
5704         for (i = 0; i < pf->vf_num; i++)
5705                 i40e_pf_host_send_msg_to_vf(&pf->vfs[i], I40E_VIRTCHNL_OP_EVENT,
5706                                 I40E_SUCCESS, (uint8_t *)&event, sizeof(event));
5707 }
5708
5709 static void
5710 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5711 {
5712         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5713         struct i40e_arq_event_info info;
5714         uint16_t pending, opcode;
5715         int ret;
5716
5717         info.buf_len = I40E_AQ_BUF_SZ;
5718         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5719         if (!info.msg_buf) {
5720                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5721                 return;
5722         }
5723
5724         pending = 1;
5725         while (pending) {
5726                 ret = i40e_clean_arq_element(hw, &info, &pending);
5727
5728                 if (ret != I40E_SUCCESS) {
5729                         PMD_DRV_LOG(INFO,
5730                                 "Failed to read msg from AdminQ, aq_err: %u",
5731                                 hw->aq.asq_last_status);
5732                         break;
5733                 }
5734                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5735
5736                 switch (opcode) {
5737                 case i40e_aqc_opc_send_msg_to_pf:
5738                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5739                         i40e_pf_host_handle_vf_msg(dev,
5740                                         rte_le_to_cpu_16(info.desc.retval),
5741                                         rte_le_to_cpu_32(info.desc.cookie_high),
5742                                         rte_le_to_cpu_32(info.desc.cookie_low),
5743                                         info.msg_buf,
5744                                         info.msg_len);
5745                         break;
5746                 case i40e_aqc_opc_get_link_status:
5747                         ret = i40e_dev_link_update(dev, 0);
5748                         if (!ret) {
5749                                 i40e_notify_all_vfs_link_status(dev);
5750                                 _rte_eth_dev_callback_process(dev,
5751                                         RTE_ETH_EVENT_INTR_LSC, NULL);
5752                         }
5753                         break;
5754                 default:
5755                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5756                                     opcode);
5757                         break;
5758                 }
5759         }
5760         rte_free(info.msg_buf);
5761 }
5762
5763 /**
5764  * Interrupt handler triggered by NIC  for handling
5765  * specific interrupt.
5766  *
5767  * @param handle
5768  *  Pointer to interrupt handle.
5769  * @param param
5770  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5771  *
5772  * @return
5773  *  void
5774  */
5775 static void
5776 i40e_dev_interrupt_handler(struct rte_intr_handle *intr_handle,
5777                            void *param)
5778 {
5779         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5780         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5781         uint32_t icr0;
5782
5783         /* Disable interrupt */
5784         i40e_pf_disable_irq0(hw);
5785
5786         /* read out interrupt causes */
5787         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5788
5789         /* No interrupt event indicated */
5790         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5791                 PMD_DRV_LOG(INFO, "No interrupt event");
5792                 goto done;
5793         }
5794 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5795         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5796                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5797         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5798                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5799         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5800                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5801         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5802                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5803         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5804                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5805         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5806                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5807         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5808                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5809 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5810
5811         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5812                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5813                 i40e_dev_handle_vfr_event(dev);
5814         }
5815         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5816                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5817                 i40e_dev_handle_aq_msg(dev);
5818         }
5819
5820 done:
5821         /* Enable interrupt */
5822         i40e_pf_enable_irq0(hw);
5823         rte_intr_enable(intr_handle);
5824 }
5825
5826 static int
5827 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5828                          struct i40e_macvlan_filter *filter,
5829                          int total)
5830 {
5831         int ele_num, ele_buff_size;
5832         int num, actual_num, i;
5833         uint16_t flags;
5834         int ret = I40E_SUCCESS;
5835         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5836         struct i40e_aqc_add_macvlan_element_data *req_list;
5837
5838         if (filter == NULL  || total == 0)
5839                 return I40E_ERR_PARAM;
5840         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5841         ele_buff_size = hw->aq.asq_buf_size;
5842
5843         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5844         if (req_list == NULL) {
5845                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5846                 return I40E_ERR_NO_MEMORY;
5847         }
5848
5849         num = 0;
5850         do {
5851                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5852                 memset(req_list, 0, ele_buff_size);
5853
5854                 for (i = 0; i < actual_num; i++) {
5855                         (void)rte_memcpy(req_list[i].mac_addr,
5856                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5857                         req_list[i].vlan_tag =
5858                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5859
5860                         switch (filter[num + i].filter_type) {
5861                         case RTE_MAC_PERFECT_MATCH:
5862                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5863                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5864                                 break;
5865                         case RTE_MACVLAN_PERFECT_MATCH:
5866                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5867                                 break;
5868                         case RTE_MAC_HASH_MATCH:
5869                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5870                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5871                                 break;
5872                         case RTE_MACVLAN_HASH_MATCH:
5873                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5874                                 break;
5875                         default:
5876                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
5877                                 ret = I40E_ERR_PARAM;
5878                                 goto DONE;
5879                         }
5880
5881                         req_list[i].queue_number = 0;
5882
5883                         req_list[i].flags = rte_cpu_to_le_16(flags);
5884                 }
5885
5886                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5887                                                 actual_num, NULL);
5888                 if (ret != I40E_SUCCESS) {
5889                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5890                         goto DONE;
5891                 }
5892                 num += actual_num;
5893         } while (num < total);
5894
5895 DONE:
5896         rte_free(req_list);
5897         return ret;
5898 }
5899
5900 static int
5901 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5902                             struct i40e_macvlan_filter *filter,
5903                             int total)
5904 {
5905         int ele_num, ele_buff_size;
5906         int num, actual_num, i;
5907         uint16_t flags;
5908         int ret = I40E_SUCCESS;
5909         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5910         struct i40e_aqc_remove_macvlan_element_data *req_list;
5911
5912         if (filter == NULL  || total == 0)
5913                 return I40E_ERR_PARAM;
5914
5915         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5916         ele_buff_size = hw->aq.asq_buf_size;
5917
5918         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5919         if (req_list == NULL) {
5920                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5921                 return I40E_ERR_NO_MEMORY;
5922         }
5923
5924         num = 0;
5925         do {
5926                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5927                 memset(req_list, 0, ele_buff_size);
5928
5929                 for (i = 0; i < actual_num; i++) {
5930                         (void)rte_memcpy(req_list[i].mac_addr,
5931                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5932                         req_list[i].vlan_tag =
5933                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5934
5935                         switch (filter[num + i].filter_type) {
5936                         case RTE_MAC_PERFECT_MATCH:
5937                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5938                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5939                                 break;
5940                         case RTE_MACVLAN_PERFECT_MATCH:
5941                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5942                                 break;
5943                         case RTE_MAC_HASH_MATCH:
5944                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5945                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5946                                 break;
5947                         case RTE_MACVLAN_HASH_MATCH:
5948                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5949                                 break;
5950                         default:
5951                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
5952                                 ret = I40E_ERR_PARAM;
5953                                 goto DONE;
5954                         }
5955                         req_list[i].flags = rte_cpu_to_le_16(flags);
5956                 }
5957
5958                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5959                                                 actual_num, NULL);
5960                 if (ret != I40E_SUCCESS) {
5961                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5962                         goto DONE;
5963                 }
5964                 num += actual_num;
5965         } while (num < total);
5966
5967 DONE:
5968         rte_free(req_list);
5969         return ret;
5970 }
5971
5972 /* Find out specific MAC filter */
5973 static struct i40e_mac_filter *
5974 i40e_find_mac_filter(struct i40e_vsi *vsi,
5975                          struct ether_addr *macaddr)
5976 {
5977         struct i40e_mac_filter *f;
5978
5979         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5980                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5981                         return f;
5982         }
5983
5984         return NULL;
5985 }
5986
5987 static bool
5988 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5989                          uint16_t vlan_id)
5990 {
5991         uint32_t vid_idx, vid_bit;
5992
5993         if (vlan_id > ETH_VLAN_ID_MAX)
5994                 return 0;
5995
5996         vid_idx = I40E_VFTA_IDX(vlan_id);
5997         vid_bit = I40E_VFTA_BIT(vlan_id);
5998
5999         if (vsi->vfta[vid_idx] & vid_bit)
6000                 return 1;
6001         else
6002                 return 0;
6003 }
6004
6005 static void
6006 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6007                        uint16_t vlan_id, bool on)
6008 {
6009         uint32_t vid_idx, vid_bit;
6010
6011         vid_idx = I40E_VFTA_IDX(vlan_id);
6012         vid_bit = I40E_VFTA_BIT(vlan_id);
6013
6014         if (on)
6015                 vsi->vfta[vid_idx] |= vid_bit;
6016         else
6017                 vsi->vfta[vid_idx] &= ~vid_bit;
6018 }
6019
6020 static void
6021 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6022                      uint16_t vlan_id, bool on)
6023 {
6024         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6025         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6026         int ret;
6027
6028         if (vlan_id > ETH_VLAN_ID_MAX)
6029                 return;
6030
6031         i40e_store_vlan_filter(vsi, vlan_id, on);
6032
6033         if (!vsi->vlan_anti_spoof_on || !vlan_id)
6034                 return;
6035
6036         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6037
6038         if (on) {
6039                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6040                                        &vlan_data, 1, NULL);
6041                 if (ret != I40E_SUCCESS)
6042                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6043         } else {
6044                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6045                                           &vlan_data, 1, NULL);
6046                 if (ret != I40E_SUCCESS)
6047                         PMD_DRV_LOG(ERR,
6048                                     "Failed to remove vlan filter");
6049         }
6050 }
6051
6052 /**
6053  * Find all vlan options for specific mac addr,
6054  * return with actual vlan found.
6055  */
6056 static inline int
6057 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6058                            struct i40e_macvlan_filter *mv_f,
6059                            int num, struct ether_addr *addr)
6060 {
6061         int i;
6062         uint32_t j, k;
6063
6064         /**
6065          * Not to use i40e_find_vlan_filter to decrease the loop time,
6066          * although the code looks complex.
6067           */
6068         if (num < vsi->vlan_num)
6069                 return I40E_ERR_PARAM;
6070
6071         i = 0;
6072         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6073                 if (vsi->vfta[j]) {
6074                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6075                                 if (vsi->vfta[j] & (1 << k)) {
6076                                         if (i > num - 1) {
6077                                                 PMD_DRV_LOG(ERR,
6078                                                         "vlan number doesn't match");
6079                                                 return I40E_ERR_PARAM;
6080                                         }
6081                                         (void)rte_memcpy(&mv_f[i].macaddr,
6082                                                         addr, ETH_ADDR_LEN);
6083                                         mv_f[i].vlan_id =
6084                                                 j * I40E_UINT32_BIT_SIZE + k;
6085                                         i++;
6086                                 }
6087                         }
6088                 }
6089         }
6090         return I40E_SUCCESS;
6091 }
6092
6093 static inline int
6094 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6095                            struct i40e_macvlan_filter *mv_f,
6096                            int num,
6097                            uint16_t vlan)
6098 {
6099         int i = 0;
6100         struct i40e_mac_filter *f;
6101
6102         if (num < vsi->mac_num)
6103                 return I40E_ERR_PARAM;
6104
6105         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6106                 if (i > num - 1) {
6107                         PMD_DRV_LOG(ERR, "buffer number not match");
6108                         return I40E_ERR_PARAM;
6109                 }
6110                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6111                                 ETH_ADDR_LEN);
6112                 mv_f[i].vlan_id = vlan;
6113                 mv_f[i].filter_type = f->mac_info.filter_type;
6114                 i++;
6115         }
6116
6117         return I40E_SUCCESS;
6118 }
6119
6120 static int
6121 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6122 {
6123         int i, j, num;
6124         struct i40e_mac_filter *f;
6125         struct i40e_macvlan_filter *mv_f;
6126         int ret = I40E_SUCCESS;
6127
6128         if (vsi == NULL || vsi->mac_num == 0)
6129                 return I40E_ERR_PARAM;
6130
6131         /* Case that no vlan is set */
6132         if (vsi->vlan_num == 0)
6133                 num = vsi->mac_num;
6134         else
6135                 num = vsi->mac_num * vsi->vlan_num;
6136
6137         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6138         if (mv_f == NULL) {
6139                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6140                 return I40E_ERR_NO_MEMORY;
6141         }
6142
6143         i = 0;
6144         if (vsi->vlan_num == 0) {
6145                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6146                         (void)rte_memcpy(&mv_f[i].macaddr,
6147                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6148                         mv_f[i].filter_type = f->mac_info.filter_type;
6149                         mv_f[i].vlan_id = 0;
6150                         i++;
6151                 }
6152         } else {
6153                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6154                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6155                                         vsi->vlan_num, &f->mac_info.mac_addr);
6156                         if (ret != I40E_SUCCESS)
6157                                 goto DONE;
6158                         for (j = i; j < i + vsi->vlan_num; j++)
6159                                 mv_f[j].filter_type = f->mac_info.filter_type;
6160                         i += vsi->vlan_num;
6161                 }
6162         }
6163
6164         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6165 DONE:
6166         rte_free(mv_f);
6167
6168         return ret;
6169 }
6170
6171 int
6172 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6173 {
6174         struct i40e_macvlan_filter *mv_f;
6175         int mac_num;
6176         int ret = I40E_SUCCESS;
6177
6178         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6179                 return I40E_ERR_PARAM;
6180
6181         /* If it's already set, just return */
6182         if (i40e_find_vlan_filter(vsi,vlan))
6183                 return I40E_SUCCESS;
6184
6185         mac_num = vsi->mac_num;
6186
6187         if (mac_num == 0) {
6188                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6189                 return I40E_ERR_PARAM;
6190         }
6191
6192         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6193
6194         if (mv_f == NULL) {
6195                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6196                 return I40E_ERR_NO_MEMORY;
6197         }
6198
6199         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6200
6201         if (ret != I40E_SUCCESS)
6202                 goto DONE;
6203
6204         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6205
6206         if (ret != I40E_SUCCESS)
6207                 goto DONE;
6208
6209         i40e_set_vlan_filter(vsi, vlan, 1);
6210
6211         vsi->vlan_num++;
6212         ret = I40E_SUCCESS;
6213 DONE:
6214         rte_free(mv_f);
6215         return ret;
6216 }
6217
6218 int
6219 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6220 {
6221         struct i40e_macvlan_filter *mv_f;
6222         int mac_num;
6223         int ret = I40E_SUCCESS;
6224
6225         /**
6226          * Vlan 0 is the generic filter for untagged packets
6227          * and can't be removed.
6228          */
6229         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6230                 return I40E_ERR_PARAM;
6231
6232         /* If can't find it, just return */
6233         if (!i40e_find_vlan_filter(vsi, vlan))
6234                 return I40E_ERR_PARAM;
6235
6236         mac_num = vsi->mac_num;
6237
6238         if (mac_num == 0) {
6239                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6240                 return I40E_ERR_PARAM;
6241         }
6242
6243         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6244
6245         if (mv_f == NULL) {
6246                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6247                 return I40E_ERR_NO_MEMORY;
6248         }
6249
6250         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6251
6252         if (ret != I40E_SUCCESS)
6253                 goto DONE;
6254
6255         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6256
6257         if (ret != I40E_SUCCESS)
6258                 goto DONE;
6259
6260         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6261         if (vsi->vlan_num == 1) {
6262                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6263                 if (ret != I40E_SUCCESS)
6264                         goto DONE;
6265
6266                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6267                 if (ret != I40E_SUCCESS)
6268                         goto DONE;
6269         }
6270
6271         i40e_set_vlan_filter(vsi, vlan, 0);
6272
6273         vsi->vlan_num--;
6274         ret = I40E_SUCCESS;
6275 DONE:
6276         rte_free(mv_f);
6277         return ret;
6278 }
6279
6280 int
6281 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6282 {
6283         struct i40e_mac_filter *f;
6284         struct i40e_macvlan_filter *mv_f;
6285         int i, vlan_num = 0;
6286         int ret = I40E_SUCCESS;
6287
6288         /* If it's add and we've config it, return */
6289         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6290         if (f != NULL)
6291                 return I40E_SUCCESS;
6292         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6293                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6294
6295                 /**
6296                  * If vlan_num is 0, that's the first time to add mac,
6297                  * set mask for vlan_id 0.
6298                  */
6299                 if (vsi->vlan_num == 0) {
6300                         i40e_set_vlan_filter(vsi, 0, 1);
6301                         vsi->vlan_num = 1;
6302                 }
6303                 vlan_num = vsi->vlan_num;
6304         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6305                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6306                 vlan_num = 1;
6307
6308         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6309         if (mv_f == NULL) {
6310                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6311                 return I40E_ERR_NO_MEMORY;
6312         }
6313
6314         for (i = 0; i < vlan_num; i++) {
6315                 mv_f[i].filter_type = mac_filter->filter_type;
6316                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6317                                 ETH_ADDR_LEN);
6318         }
6319
6320         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6321                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6322                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6323                                         &mac_filter->mac_addr);
6324                 if (ret != I40E_SUCCESS)
6325                         goto DONE;
6326         }
6327
6328         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6329         if (ret != I40E_SUCCESS)
6330                 goto DONE;
6331
6332         /* Add the mac addr into mac list */
6333         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6334         if (f == NULL) {
6335                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6336                 ret = I40E_ERR_NO_MEMORY;
6337                 goto DONE;
6338         }
6339         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6340                         ETH_ADDR_LEN);
6341         f->mac_info.filter_type = mac_filter->filter_type;
6342         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6343         vsi->mac_num++;
6344
6345         ret = I40E_SUCCESS;
6346 DONE:
6347         rte_free(mv_f);
6348
6349         return ret;
6350 }
6351
6352 int
6353 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6354 {
6355         struct i40e_mac_filter *f;
6356         struct i40e_macvlan_filter *mv_f;
6357         int i, vlan_num;
6358         enum rte_mac_filter_type filter_type;
6359         int ret = I40E_SUCCESS;
6360
6361         /* Can't find it, return an error */
6362         f = i40e_find_mac_filter(vsi, addr);
6363         if (f == NULL)
6364                 return I40E_ERR_PARAM;
6365
6366         vlan_num = vsi->vlan_num;
6367         filter_type = f->mac_info.filter_type;
6368         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6369                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6370                 if (vlan_num == 0) {
6371                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6372                         return I40E_ERR_PARAM;
6373                 }
6374         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6375                         filter_type == RTE_MAC_HASH_MATCH)
6376                 vlan_num = 1;
6377
6378         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6379         if (mv_f == NULL) {
6380                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6381                 return I40E_ERR_NO_MEMORY;
6382         }
6383
6384         for (i = 0; i < vlan_num; i++) {
6385                 mv_f[i].filter_type = filter_type;
6386                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6387                                 ETH_ADDR_LEN);
6388         }
6389         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6390                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6391                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6392                 if (ret != I40E_SUCCESS)
6393                         goto DONE;
6394         }
6395
6396         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6397         if (ret != I40E_SUCCESS)
6398                 goto DONE;
6399
6400         /* Remove the mac addr into mac list */
6401         TAILQ_REMOVE(&vsi->mac_list, f, next);
6402         rte_free(f);
6403         vsi->mac_num--;
6404
6405         ret = I40E_SUCCESS;
6406 DONE:
6407         rte_free(mv_f);
6408         return ret;
6409 }
6410
6411 /* Configure hash enable flags for RSS */
6412 uint64_t
6413 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6414 {
6415         uint64_t hena = 0;
6416
6417         if (!flags)
6418                 return hena;
6419
6420         if (flags & ETH_RSS_FRAG_IPV4)
6421                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6422         if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6423                 if (type == I40E_MAC_X722) {
6424                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6425                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6426                 } else
6427                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6428         }
6429         if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6430                 if (type == I40E_MAC_X722) {
6431                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6432                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6433                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6434                 } else
6435                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6436         }
6437         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6438                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6439         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6440                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6441         if (flags & ETH_RSS_FRAG_IPV6)
6442                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6443         if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6444                 if (type == I40E_MAC_X722) {
6445                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6446                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6447                 } else
6448                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6449         }
6450         if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6451                 if (type == I40E_MAC_X722) {
6452                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6453                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6454                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6455                 } else
6456                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6457         }
6458         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6459                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6460         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6461                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6462         if (flags & ETH_RSS_L2_PAYLOAD)
6463                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6464
6465         return hena;
6466 }
6467
6468 /* Parse the hash enable flags */
6469 uint64_t
6470 i40e_parse_hena(uint64_t flags)
6471 {
6472         uint64_t rss_hf = 0;
6473
6474         if (!flags)
6475                 return rss_hf;
6476         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6477                 rss_hf |= ETH_RSS_FRAG_IPV4;
6478         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6479                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6480         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6481                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6482         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6483                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6484         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6485                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6486         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6487                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6488         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6489                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6490         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6491                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6492         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6493                 rss_hf |= ETH_RSS_FRAG_IPV6;
6494         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6495                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6496         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6497                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6498         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6499                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6500         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6501                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6502         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6503                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6504         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6505                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6506         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6507                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6508         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6509                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6510
6511         return rss_hf;
6512 }
6513
6514 /* Disable RSS */
6515 static void
6516 i40e_pf_disable_rss(struct i40e_pf *pf)
6517 {
6518         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6519         uint64_t hena;
6520
6521         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6522         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6523         if (hw->mac.type == I40E_MAC_X722)
6524                 hena &= ~I40E_RSS_HENA_ALL_X722;
6525         else
6526                 hena &= ~I40E_RSS_HENA_ALL;
6527         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6528         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6529         I40E_WRITE_FLUSH(hw);
6530 }
6531
6532 static int
6533 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6534 {
6535         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6536         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6537         int ret = 0;
6538
6539         if (!key || key_len == 0) {
6540                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6541                 return 0;
6542         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6543                 sizeof(uint32_t)) {
6544                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6545                 return -EINVAL;
6546         }
6547
6548         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6549                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6550                         (struct i40e_aqc_get_set_rss_key_data *)key;
6551
6552                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6553                 if (ret)
6554                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6555         } else {
6556                 uint32_t *hash_key = (uint32_t *)key;
6557                 uint16_t i;
6558
6559                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6560                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6561                 I40E_WRITE_FLUSH(hw);
6562         }
6563
6564         return ret;
6565 }
6566
6567 static int
6568 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6569 {
6570         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6571         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6572         int ret;
6573
6574         if (!key || !key_len)
6575                 return -EINVAL;
6576
6577         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6578                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6579                         (struct i40e_aqc_get_set_rss_key_data *)key);
6580                 if (ret) {
6581                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6582                         return ret;
6583                 }
6584         } else {
6585                 uint32_t *key_dw = (uint32_t *)key;
6586                 uint16_t i;
6587
6588                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6589                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6590         }
6591         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6592
6593         return 0;
6594 }
6595
6596 static int
6597 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6598 {
6599         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6600         uint64_t rss_hf;
6601         uint64_t hena;
6602         int ret;
6603
6604         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6605                                rss_conf->rss_key_len);
6606         if (ret)
6607                 return ret;
6608
6609         rss_hf = rss_conf->rss_hf;
6610         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6611         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6612         if (hw->mac.type == I40E_MAC_X722)
6613                 hena &= ~I40E_RSS_HENA_ALL_X722;
6614         else
6615                 hena &= ~I40E_RSS_HENA_ALL;
6616         hena |= i40e_config_hena(rss_hf, hw->mac.type);
6617         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6618         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6619         I40E_WRITE_FLUSH(hw);
6620
6621         return 0;
6622 }
6623
6624 static int
6625 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6626                          struct rte_eth_rss_conf *rss_conf)
6627 {
6628         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6629         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6630         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6631         uint64_t hena;
6632
6633         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6634         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6635         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6636                  ? I40E_RSS_HENA_ALL_X722
6637                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6638                 if (rss_hf != 0) /* Enable RSS */
6639                         return -EINVAL;
6640                 return 0; /* Nothing to do */
6641         }
6642         /* RSS enabled */
6643         if (rss_hf == 0) /* Disable RSS */
6644                 return -EINVAL;
6645
6646         return i40e_hw_rss_hash_set(pf, rss_conf);
6647 }
6648
6649 static int
6650 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6651                            struct rte_eth_rss_conf *rss_conf)
6652 {
6653         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6654         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6655         uint64_t hena;
6656
6657         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6658                          &rss_conf->rss_key_len);
6659
6660         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6661         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6662         rss_conf->rss_hf = i40e_parse_hena(hena);
6663
6664         return 0;
6665 }
6666
6667 static int
6668 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6669 {
6670         switch (filter_type) {
6671         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6672                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6673                 break;
6674         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6675                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6676                 break;
6677         case RTE_TUNNEL_FILTER_IMAC_TENID:
6678                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6679                 break;
6680         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6681                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6682                 break;
6683         case ETH_TUNNEL_FILTER_IMAC:
6684                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6685                 break;
6686         case ETH_TUNNEL_FILTER_OIP:
6687                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6688                 break;
6689         case ETH_TUNNEL_FILTER_IIP:
6690                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6691                 break;
6692         default:
6693                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6694                 return -EINVAL;
6695         }
6696
6697         return 0;
6698 }
6699
6700 /* Convert tunnel filter structure */
6701 static int
6702 i40e_tunnel_filter_convert(struct i40e_aqc_add_remove_cloud_filters_element_data
6703                            *cld_filter,
6704                            struct i40e_tunnel_filter *tunnel_filter)
6705 {
6706         ether_addr_copy((struct ether_addr *)&cld_filter->outer_mac,
6707                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
6708         ether_addr_copy((struct ether_addr *)&cld_filter->inner_mac,
6709                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
6710         tunnel_filter->input.inner_vlan = cld_filter->inner_vlan;
6711         if ((rte_le_to_cpu_16(cld_filter->flags) &
6712              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6713             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6714                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6715         else
6716                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6717         tunnel_filter->input.flags = cld_filter->flags;
6718         tunnel_filter->input.tenant_id = cld_filter->tenant_id;
6719         tunnel_filter->queue = cld_filter->queue_number;
6720
6721         return 0;
6722 }
6723
6724 /* Check if there exists the tunnel filter */
6725 struct i40e_tunnel_filter *
6726 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6727                              const struct i40e_tunnel_filter_input *input)
6728 {
6729         int ret;
6730
6731         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6732         if (ret < 0)
6733                 return NULL;
6734
6735         return tunnel_rule->hash_map[ret];
6736 }
6737
6738 /* Add a tunnel filter into the SW list */
6739 static int
6740 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6741                              struct i40e_tunnel_filter *tunnel_filter)
6742 {
6743         struct i40e_tunnel_rule *rule = &pf->tunnel;
6744         int ret;
6745
6746         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6747         if (ret < 0) {
6748                 PMD_DRV_LOG(ERR,
6749                             "Failed to insert tunnel filter to hash table %d!",
6750                             ret);
6751                 return ret;
6752         }
6753         rule->hash_map[ret] = tunnel_filter;
6754
6755         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6756
6757         return 0;
6758 }
6759
6760 /* Delete a tunnel filter from the SW list */
6761 int
6762 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6763                           struct i40e_tunnel_filter_input *input)
6764 {
6765         struct i40e_tunnel_rule *rule = &pf->tunnel;
6766         struct i40e_tunnel_filter *tunnel_filter;
6767         int ret;
6768
6769         ret = rte_hash_del_key(rule->hash_table, input);
6770         if (ret < 0) {
6771                 PMD_DRV_LOG(ERR,
6772                             "Failed to delete tunnel filter to hash table %d!",
6773                             ret);
6774                 return ret;
6775         }
6776         tunnel_filter = rule->hash_map[ret];
6777         rule->hash_map[ret] = NULL;
6778
6779         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6780         rte_free(tunnel_filter);
6781
6782         return 0;
6783 }
6784
6785 int
6786 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6787                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6788                         uint8_t add)
6789 {
6790         uint16_t ip_type;
6791         uint32_t ipv4_addr;
6792         uint8_t i, tun_type = 0;
6793         /* internal varialbe to convert ipv6 byte order */
6794         uint32_t convert_ipv6[4];
6795         int val, ret = 0;
6796         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6797         struct i40e_vsi *vsi = pf->main_vsi;
6798         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
6799         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
6800         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6801         struct i40e_tunnel_filter *tunnel, *node;
6802         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6803
6804         cld_filter = rte_zmalloc("tunnel_filter",
6805                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6806                 0);
6807
6808         if (NULL == cld_filter) {
6809                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6810                 return -EINVAL;
6811         }
6812         pfilter = cld_filter;
6813
6814         ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6815         ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6816
6817         pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6818         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6819                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6820                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6821                 rte_memcpy(&pfilter->ipaddr.v4.data,
6822                                 &rte_cpu_to_le_32(ipv4_addr),
6823                                 sizeof(pfilter->ipaddr.v4.data));
6824         } else {
6825                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6826                 for (i = 0; i < 4; i++) {
6827                         convert_ipv6[i] =
6828                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6829                 }
6830                 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6831                                 sizeof(pfilter->ipaddr.v6.data));
6832         }
6833
6834         /* check tunneled type */
6835         switch (tunnel_filter->tunnel_type) {
6836         case RTE_TUNNEL_TYPE_VXLAN:
6837                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6838                 break;
6839         case RTE_TUNNEL_TYPE_NVGRE:
6840                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6841                 break;
6842         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6843                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6844                 break;
6845         default:
6846                 /* Other tunnel types is not supported. */
6847                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6848                 rte_free(cld_filter);
6849                 return -EINVAL;
6850         }
6851
6852         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6853                                                 &pfilter->flags);
6854         if (val < 0) {
6855                 rte_free(cld_filter);
6856                 return -EINVAL;
6857         }
6858
6859         pfilter->flags |= rte_cpu_to_le_16(
6860                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6861                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6862         pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6863         pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6864
6865         /* Check if there is the filter in SW list */
6866         memset(&check_filter, 0, sizeof(check_filter));
6867         i40e_tunnel_filter_convert(cld_filter, &check_filter);
6868         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
6869         if (add && node) {
6870                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
6871                 return -EINVAL;
6872         }
6873
6874         if (!add && !node) {
6875                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
6876                 return -EINVAL;
6877         }
6878
6879         if (add) {
6880                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6881                 if (ret < 0) {
6882                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
6883                         return ret;
6884                 }
6885                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
6886                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
6887                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
6888         } else {
6889                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6890                                                    cld_filter, 1);
6891                 if (ret < 0) {
6892                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
6893                         return ret;
6894                 }
6895                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
6896         }
6897
6898         rte_free(cld_filter);
6899         return ret;
6900 }
6901
6902 static int
6903 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6904 {
6905         uint8_t i;
6906
6907         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6908                 if (pf->vxlan_ports[i] == port)
6909                         return i;
6910         }
6911
6912         return -1;
6913 }
6914
6915 static int
6916 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6917 {
6918         int  idx, ret;
6919         uint8_t filter_idx;
6920         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6921
6922         idx = i40e_get_vxlan_port_idx(pf, port);
6923
6924         /* Check if port already exists */
6925         if (idx >= 0) {
6926                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6927                 return -EINVAL;
6928         }
6929
6930         /* Now check if there is space to add the new port */
6931         idx = i40e_get_vxlan_port_idx(pf, 0);
6932         if (idx < 0) {
6933                 PMD_DRV_LOG(ERR,
6934                         "Maximum number of UDP ports reached, not adding port %d",
6935                         port);
6936                 return -ENOSPC;
6937         }
6938
6939         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6940                                         &filter_idx, NULL);
6941         if (ret < 0) {
6942                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6943                 return -1;
6944         }
6945
6946         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6947                          port,  filter_idx);
6948
6949         /* New port: add it and mark its index in the bitmap */
6950         pf->vxlan_ports[idx] = port;
6951         pf->vxlan_bitmap |= (1 << idx);
6952
6953         if (!(pf->flags & I40E_FLAG_VXLAN))
6954                 pf->flags |= I40E_FLAG_VXLAN;
6955
6956         return 0;
6957 }
6958
6959 static int
6960 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6961 {
6962         int idx;
6963         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6964
6965         if (!(pf->flags & I40E_FLAG_VXLAN)) {
6966                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6967                 return -EINVAL;
6968         }
6969
6970         idx = i40e_get_vxlan_port_idx(pf, port);
6971
6972         if (idx < 0) {
6973                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6974                 return -EINVAL;
6975         }
6976
6977         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6978                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6979                 return -1;
6980         }
6981
6982         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6983                         port, idx);
6984
6985         pf->vxlan_ports[idx] = 0;
6986         pf->vxlan_bitmap &= ~(1 << idx);
6987
6988         if (!pf->vxlan_bitmap)
6989                 pf->flags &= ~I40E_FLAG_VXLAN;
6990
6991         return 0;
6992 }
6993
6994 /* Add UDP tunneling port */
6995 static int
6996 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6997                              struct rte_eth_udp_tunnel *udp_tunnel)
6998 {
6999         int ret = 0;
7000         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7001
7002         if (udp_tunnel == NULL)
7003                 return -EINVAL;
7004
7005         switch (udp_tunnel->prot_type) {
7006         case RTE_TUNNEL_TYPE_VXLAN:
7007                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7008                 break;
7009
7010         case RTE_TUNNEL_TYPE_GENEVE:
7011         case RTE_TUNNEL_TYPE_TEREDO:
7012                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7013                 ret = -1;
7014                 break;
7015
7016         default:
7017                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7018                 ret = -1;
7019                 break;
7020         }
7021
7022         return ret;
7023 }
7024
7025 /* Remove UDP tunneling port */
7026 static int
7027 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7028                              struct rte_eth_udp_tunnel *udp_tunnel)
7029 {
7030         int ret = 0;
7031         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7032
7033         if (udp_tunnel == NULL)
7034                 return -EINVAL;
7035
7036         switch (udp_tunnel->prot_type) {
7037         case RTE_TUNNEL_TYPE_VXLAN:
7038                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7039                 break;
7040         case RTE_TUNNEL_TYPE_GENEVE:
7041         case RTE_TUNNEL_TYPE_TEREDO:
7042                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7043                 ret = -1;
7044                 break;
7045         default:
7046                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7047                 ret = -1;
7048                 break;
7049         }
7050
7051         return ret;
7052 }
7053
7054 /* Calculate the maximum number of contiguous PF queues that are configured */
7055 static int
7056 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7057 {
7058         struct rte_eth_dev_data *data = pf->dev_data;
7059         int i, num;
7060         struct i40e_rx_queue *rxq;
7061
7062         num = 0;
7063         for (i = 0; i < pf->lan_nb_qps; i++) {
7064                 rxq = data->rx_queues[i];
7065                 if (rxq && rxq->q_set)
7066                         num++;
7067                 else
7068                         break;
7069         }
7070
7071         return num;
7072 }
7073
7074 /* Configure RSS */
7075 static int
7076 i40e_pf_config_rss(struct i40e_pf *pf)
7077 {
7078         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7079         struct rte_eth_rss_conf rss_conf;
7080         uint32_t i, lut = 0;
7081         uint16_t j, num;
7082
7083         /*
7084          * If both VMDQ and RSS enabled, not all of PF queues are configured.
7085          * It's necessary to calulate the actual PF queues that are configured.
7086          */
7087         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7088                 num = i40e_pf_calc_configured_queues_num(pf);
7089         else
7090                 num = pf->dev_data->nb_rx_queues;
7091
7092         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7093         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7094                         num);
7095
7096         if (num == 0) {
7097                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7098                 return -ENOTSUP;
7099         }
7100
7101         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7102                 if (j == num)
7103                         j = 0;
7104                 lut = (lut << 8) | (j & ((0x1 <<
7105                         hw->func_caps.rss_table_entry_width) - 1));
7106                 if ((i & 3) == 3)
7107                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7108         }
7109
7110         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7111         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
7112                 i40e_pf_disable_rss(pf);
7113                 return 0;
7114         }
7115         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7116                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7117                 /* Random default keys */
7118                 static uint32_t rss_key_default[] = {0x6b793944,
7119                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7120                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7121                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7122
7123                 rss_conf.rss_key = (uint8_t *)rss_key_default;
7124                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7125                                                         sizeof(uint32_t);
7126         }
7127
7128         return i40e_hw_rss_hash_set(pf, &rss_conf);
7129 }
7130
7131 static int
7132 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7133                                struct rte_eth_tunnel_filter_conf *filter)
7134 {
7135         if (pf == NULL || filter == NULL) {
7136                 PMD_DRV_LOG(ERR, "Invalid parameter");
7137                 return -EINVAL;
7138         }
7139
7140         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7141                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7142                 return -EINVAL;
7143         }
7144
7145         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7146                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7147                 return -EINVAL;
7148         }
7149
7150         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7151                 (is_zero_ether_addr(&filter->outer_mac))) {
7152                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7153                 return -EINVAL;
7154         }
7155
7156         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7157                 (is_zero_ether_addr(&filter->inner_mac))) {
7158                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7159                 return -EINVAL;
7160         }
7161
7162         return 0;
7163 }
7164
7165 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7166 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
7167 static int
7168 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7169 {
7170         uint32_t val, reg;
7171         int ret = -EINVAL;
7172
7173         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7174         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7175
7176         if (len == 3) {
7177                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7178         } else if (len == 4) {
7179                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7180         } else {
7181                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7182                 return ret;
7183         }
7184
7185         if (reg != val) {
7186                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7187                                                    reg, NULL);
7188                 if (ret != 0)
7189                         return ret;
7190         } else {
7191                 ret = 0;
7192         }
7193         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7194                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7195
7196         return ret;
7197 }
7198
7199 static int
7200 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7201 {
7202         int ret = -EINVAL;
7203
7204         if (!hw || !cfg)
7205                 return -EINVAL;
7206
7207         switch (cfg->cfg_type) {
7208         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7209                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7210                 break;
7211         default:
7212                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7213                 break;
7214         }
7215
7216         return ret;
7217 }
7218
7219 static int
7220 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7221                                enum rte_filter_op filter_op,
7222                                void *arg)
7223 {
7224         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7225         int ret = I40E_ERR_PARAM;
7226
7227         switch (filter_op) {
7228         case RTE_ETH_FILTER_SET:
7229                 ret = i40e_dev_global_config_set(hw,
7230                         (struct rte_eth_global_cfg *)arg);
7231                 break;
7232         default:
7233                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7234                 break;
7235         }
7236
7237         return ret;
7238 }
7239
7240 static int
7241 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7242                           enum rte_filter_op filter_op,
7243                           void *arg)
7244 {
7245         struct rte_eth_tunnel_filter_conf *filter;
7246         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7247         int ret = I40E_SUCCESS;
7248
7249         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7250
7251         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7252                 return I40E_ERR_PARAM;
7253
7254         switch (filter_op) {
7255         case RTE_ETH_FILTER_NOP:
7256                 if (!(pf->flags & I40E_FLAG_VXLAN))
7257                         ret = I40E_NOT_SUPPORTED;
7258                 break;
7259         case RTE_ETH_FILTER_ADD:
7260                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7261                 break;
7262         case RTE_ETH_FILTER_DELETE:
7263                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7264                 break;
7265         default:
7266                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7267                 ret = I40E_ERR_PARAM;
7268                 break;
7269         }
7270
7271         return ret;
7272 }
7273
7274 static int
7275 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7276 {
7277         int ret = 0;
7278         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7279
7280         /* RSS setup */
7281         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7282                 ret = i40e_pf_config_rss(pf);
7283         else
7284                 i40e_pf_disable_rss(pf);
7285
7286         return ret;
7287 }
7288
7289 /* Get the symmetric hash enable configurations per port */
7290 static void
7291 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7292 {
7293         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7294
7295         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7296 }
7297
7298 /* Set the symmetric hash enable configurations per port */
7299 static void
7300 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7301 {
7302         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7303
7304         if (enable > 0) {
7305                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7306                         PMD_DRV_LOG(INFO,
7307                                 "Symmetric hash has already been enabled");
7308                         return;
7309                 }
7310                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7311         } else {
7312                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7313                         PMD_DRV_LOG(INFO,
7314                                 "Symmetric hash has already been disabled");
7315                         return;
7316                 }
7317                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7318         }
7319         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7320         I40E_WRITE_FLUSH(hw);
7321 }
7322
7323 /*
7324  * Get global configurations of hash function type and symmetric hash enable
7325  * per flow type (pctype). Note that global configuration means it affects all
7326  * the ports on the same NIC.
7327  */
7328 static int
7329 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7330                                    struct rte_eth_hash_global_conf *g_cfg)
7331 {
7332         uint32_t reg, mask = I40E_FLOW_TYPES;
7333         uint16_t i;
7334         enum i40e_filter_pctype pctype;
7335
7336         memset(g_cfg, 0, sizeof(*g_cfg));
7337         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7338         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7339                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7340         else
7341                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7342         PMD_DRV_LOG(DEBUG, "Hash function is %s",
7343                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7344
7345         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7346                 if (!(mask & (1UL << i)))
7347                         continue;
7348                 mask &= ~(1UL << i);
7349                 /* Bit set indicats the coresponding flow type is supported */
7350                 g_cfg->valid_bit_mask[0] |= (1UL << i);
7351                 /* if flowtype is invalid, continue */
7352                 if (!I40E_VALID_FLOW(i))
7353                         continue;
7354                 pctype = i40e_flowtype_to_pctype(i);
7355                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7356                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7357                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7358         }
7359
7360         return 0;
7361 }
7362
7363 static int
7364 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7365 {
7366         uint32_t i;
7367         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7368
7369         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7370                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7371                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7372                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7373                                                 g_cfg->hash_func);
7374                 return -EINVAL;
7375         }
7376
7377         /*
7378          * As i40e supports less than 32 flow types, only first 32 bits need to
7379          * be checked.
7380          */
7381         mask0 = g_cfg->valid_bit_mask[0];
7382         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7383                 if (i == 0) {
7384                         /* Check if any unsupported flow type configured */
7385                         if ((mask0 | i40e_mask) ^ i40e_mask)
7386                                 goto mask_err;
7387                 } else {
7388                         if (g_cfg->valid_bit_mask[i])
7389                                 goto mask_err;
7390                 }
7391         }
7392
7393         return 0;
7394
7395 mask_err:
7396         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7397
7398         return -EINVAL;
7399 }
7400
7401 /*
7402  * Set global configurations of hash function type and symmetric hash enable
7403  * per flow type (pctype). Note any modifying global configuration will affect
7404  * all the ports on the same NIC.
7405  */
7406 static int
7407 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7408                                    struct rte_eth_hash_global_conf *g_cfg)
7409 {
7410         int ret;
7411         uint16_t i;
7412         uint32_t reg;
7413         uint32_t mask0 = g_cfg->valid_bit_mask[0];
7414         enum i40e_filter_pctype pctype;
7415
7416         /* Check the input parameters */
7417         ret = i40e_hash_global_config_check(g_cfg);
7418         if (ret < 0)
7419                 return ret;
7420
7421         for (i = 0; mask0 && i < UINT32_BIT; i++) {
7422                 if (!(mask0 & (1UL << i)))
7423                         continue;
7424                 mask0 &= ~(1UL << i);
7425                 /* if flowtype is invalid, continue */
7426                 if (!I40E_VALID_FLOW(i))
7427                         continue;
7428                 pctype = i40e_flowtype_to_pctype(i);
7429                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7430                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7431                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7432         }
7433
7434         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7435         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7436                 /* Toeplitz */
7437                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7438                         PMD_DRV_LOG(DEBUG,
7439                                 "Hash function already set to Toeplitz");
7440                         goto out;
7441                 }
7442                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7443         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7444                 /* Simple XOR */
7445                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7446                         PMD_DRV_LOG(DEBUG,
7447                                 "Hash function already set to Simple XOR");
7448                         goto out;
7449                 }
7450                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7451         } else
7452                 /* Use the default, and keep it as it is */
7453                 goto out;
7454
7455         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7456
7457 out:
7458         I40E_WRITE_FLUSH(hw);
7459
7460         return 0;
7461 }
7462
7463 /**
7464  * Valid input sets for hash and flow director filters per PCTYPE
7465  */
7466 static uint64_t
7467 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7468                 enum rte_filter_type filter)
7469 {
7470         uint64_t valid;
7471
7472         static const uint64_t valid_hash_inset_table[] = {
7473                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7474                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7475                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7476                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7477                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7478                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7479                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7480                         I40E_INSET_FLEX_PAYLOAD,
7481                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7482                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7483                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7484                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7485                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7486                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7487                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7488                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7489                         I40E_INSET_FLEX_PAYLOAD,
7490                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7491                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7492                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7493                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7494                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7495                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7496                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7497                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7498                         I40E_INSET_FLEX_PAYLOAD,
7499                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7500                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7501                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7502                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7503                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7504                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7505                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7506                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7507                         I40E_INSET_FLEX_PAYLOAD,
7508                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7509                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7510                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7511                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7512                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7513                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7514                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7515                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7516                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7517                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7518                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7519                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7520                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7521                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7522                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7523                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7524                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7525                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7526                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7527                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7528                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7529                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7530                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7531                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7532                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7533                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7534                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7535                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7536                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7537                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7538                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7539                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7540                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7541                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7542                         I40E_INSET_FLEX_PAYLOAD,
7543                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7544                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7545                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7546                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7547                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7548                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7549                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7550                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7551                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7552                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7553                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7554                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7555                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7556                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7557                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7558                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7559                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7560                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7561                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7562                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7563                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7564                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7565                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7566                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7567                         I40E_INSET_FLEX_PAYLOAD,
7568                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7569                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7570                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7571                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7572                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7573                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7574                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7575                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7576                         I40E_INSET_FLEX_PAYLOAD,
7577                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7578                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7579                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7580                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7581                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7582                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7583                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7584                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7585                         I40E_INSET_FLEX_PAYLOAD,
7586                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7587                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7588                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7589                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7590                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7591                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7592                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7593                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7594                         I40E_INSET_FLEX_PAYLOAD,
7595                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7596                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7597                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7598                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7599                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7600                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7601                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7602                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7603                         I40E_INSET_FLEX_PAYLOAD,
7604                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7605                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7606                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7607                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7608                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7609                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7610                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7611                         I40E_INSET_FLEX_PAYLOAD,
7612                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7613                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7614                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7615                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7616                         I40E_INSET_FLEX_PAYLOAD,
7617         };
7618
7619         /**
7620          * Flow director supports only fields defined in
7621          * union rte_eth_fdir_flow.
7622          */
7623         static const uint64_t valid_fdir_inset_table[] = {
7624                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7625                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7626                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7627                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7628                 I40E_INSET_IPV4_TTL,
7629                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7630                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7631                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7632                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7633                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7634                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7635                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7636                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7637                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7638                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7639                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7640                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7641                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7642                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7643                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7644                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7645                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7646                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7647                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7648                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7649                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7650                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7651                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7652                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7653                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7654                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7655                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7656                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7657                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7658                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7659                 I40E_INSET_SCTP_VT,
7660                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7661                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7662                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7663                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7664                 I40E_INSET_IPV4_TTL,
7665                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7666                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7667                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7668                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7669                 I40E_INSET_IPV6_HOP_LIMIT,
7670                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7671                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7672                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7673                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7674                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7675                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7676                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7677                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7678                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7679                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7680                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7681                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7682                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7683                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7684                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7685                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7686                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7687                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7688                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7689                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7690                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7691                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7692                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7693                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7694                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7695                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7696                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7697                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7698                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7699                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7700                 I40E_INSET_SCTP_VT,
7701                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7702                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7703                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7704                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7705                 I40E_INSET_IPV6_HOP_LIMIT,
7706                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7707                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7708                 I40E_INSET_LAST_ETHER_TYPE,
7709         };
7710
7711         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7712                 return 0;
7713         if (filter == RTE_ETH_FILTER_HASH)
7714                 valid = valid_hash_inset_table[pctype];
7715         else
7716                 valid = valid_fdir_inset_table[pctype];
7717
7718         return valid;
7719 }
7720
7721 /**
7722  * Validate if the input set is allowed for a specific PCTYPE
7723  */
7724 static int
7725 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7726                 enum rte_filter_type filter, uint64_t inset)
7727 {
7728         uint64_t valid;
7729
7730         valid = i40e_get_valid_input_set(pctype, filter);
7731         if (inset & (~valid))
7732                 return -EINVAL;
7733
7734         return 0;
7735 }
7736
7737 /* default input set fields combination per pctype */
7738 uint64_t
7739 i40e_get_default_input_set(uint16_t pctype)
7740 {
7741         static const uint64_t default_inset_table[] = {
7742                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7743                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7744                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7745                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7746                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7747                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7748                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7749                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7750                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7751                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7752                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7753                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7754                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7755                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7756                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7757                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7758                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7759                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7760                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7761                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7762                         I40E_INSET_SCTP_VT,
7763                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7764                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7765                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7766                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7767                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7768                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7769                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7770                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7771                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7772                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7773                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7774                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7775                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7776                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7777                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7778                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7779                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7780                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7781                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7782                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7783                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7784                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7785                         I40E_INSET_SCTP_VT,
7786                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7787                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7788                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7789                         I40E_INSET_LAST_ETHER_TYPE,
7790         };
7791
7792         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7793                 return 0;
7794
7795         return default_inset_table[pctype];
7796 }
7797
7798 /**
7799  * Parse the input set from index to logical bit masks
7800  */
7801 static int
7802 i40e_parse_input_set(uint64_t *inset,
7803                      enum i40e_filter_pctype pctype,
7804                      enum rte_eth_input_set_field *field,
7805                      uint16_t size)
7806 {
7807         uint16_t i, j;
7808         int ret = -EINVAL;
7809
7810         static const struct {
7811                 enum rte_eth_input_set_field field;
7812                 uint64_t inset;
7813         } inset_convert_table[] = {
7814                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7815                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7816                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7817                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7818                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7819                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7820                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7821                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7822                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7823                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7824                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7825                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7826                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7827                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7828                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7829                         I40E_INSET_IPV6_NEXT_HDR},
7830                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7831                         I40E_INSET_IPV6_HOP_LIMIT},
7832                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7833                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7834                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7835                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7836                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7837                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7838                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7839                         I40E_INSET_SCTP_VT},
7840                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7841                         I40E_INSET_TUNNEL_DMAC},
7842                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7843                         I40E_INSET_VLAN_TUNNEL},
7844                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7845                         I40E_INSET_TUNNEL_ID},
7846                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7847                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7848                         I40E_INSET_FLEX_PAYLOAD_W1},
7849                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7850                         I40E_INSET_FLEX_PAYLOAD_W2},
7851                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7852                         I40E_INSET_FLEX_PAYLOAD_W3},
7853                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7854                         I40E_INSET_FLEX_PAYLOAD_W4},
7855                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7856                         I40E_INSET_FLEX_PAYLOAD_W5},
7857                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7858                         I40E_INSET_FLEX_PAYLOAD_W6},
7859                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7860                         I40E_INSET_FLEX_PAYLOAD_W7},
7861                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7862                         I40E_INSET_FLEX_PAYLOAD_W8},
7863         };
7864
7865         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7866                 return ret;
7867
7868         /* Only one item allowed for default or all */
7869         if (size == 1) {
7870                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7871                         *inset = i40e_get_default_input_set(pctype);
7872                         return 0;
7873                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7874                         *inset = I40E_INSET_NONE;
7875                         return 0;
7876                 }
7877         }
7878
7879         for (i = 0, *inset = 0; i < size; i++) {
7880                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7881                         if (field[i] == inset_convert_table[j].field) {
7882                                 *inset |= inset_convert_table[j].inset;
7883                                 break;
7884                         }
7885                 }
7886
7887                 /* It contains unsupported input set, return immediately */
7888                 if (j == RTE_DIM(inset_convert_table))
7889                         return ret;
7890         }
7891
7892         return 0;
7893 }
7894
7895 /**
7896  * Translate the input set from bit masks to register aware bit masks
7897  * and vice versa
7898  */
7899 static uint64_t
7900 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
7901 {
7902         uint64_t val = 0;
7903         uint16_t i;
7904
7905         struct inset_map {
7906                 uint64_t inset;
7907                 uint64_t inset_reg;
7908         };
7909
7910         static const struct inset_map inset_map_common[] = {
7911                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7912                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7913                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7914                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7915                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7916                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7917                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7918                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7919                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7920                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7921                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7922                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7923                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7924                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7925                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7926                 {I40E_INSET_TUNNEL_DMAC,
7927                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7928                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7929                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7930                 {I40E_INSET_TUNNEL_SRC_PORT,
7931                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7932                 {I40E_INSET_TUNNEL_DST_PORT,
7933                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7934                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7935                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7936                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7937                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7938                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7939                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7940                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7941                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7942                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7943         };
7944
7945     /* some different registers map in x722*/
7946         static const struct inset_map inset_map_diff_x722[] = {
7947                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
7948                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
7949                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
7950                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
7951         };
7952
7953         static const struct inset_map inset_map_diff_not_x722[] = {
7954                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7955                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7956                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7957                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7958         };
7959
7960         if (input == 0)
7961                 return val;
7962
7963         /* Translate input set to register aware inset */
7964         if (type == I40E_MAC_X722) {
7965                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
7966                         if (input & inset_map_diff_x722[i].inset)
7967                                 val |= inset_map_diff_x722[i].inset_reg;
7968                 }
7969         } else {
7970                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
7971                         if (input & inset_map_diff_not_x722[i].inset)
7972                                 val |= inset_map_diff_not_x722[i].inset_reg;
7973                 }
7974         }
7975
7976         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
7977                 if (input & inset_map_common[i].inset)
7978                         val |= inset_map_common[i].inset_reg;
7979         }
7980
7981         return val;
7982 }
7983
7984 static int
7985 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7986 {
7987         uint8_t i, idx = 0;
7988         uint64_t inset_need_mask = inset;
7989
7990         static const struct {
7991                 uint64_t inset;
7992                 uint32_t mask;
7993         } inset_mask_map[] = {
7994                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7995                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7996                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7997                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7998                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7999                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8000                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8001                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8002         };
8003
8004         if (!inset || !mask || !nb_elem)
8005                 return 0;
8006
8007         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8008                 /* Clear the inset bit, if no MASK is required,
8009                  * for example proto + ttl
8010                  */
8011                 if ((inset & inset_mask_map[i].inset) ==
8012                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8013                         inset_need_mask &= ~inset_mask_map[i].inset;
8014                 if (!inset_need_mask)
8015                         return 0;
8016         }
8017         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8018                 if ((inset_need_mask & inset_mask_map[i].inset) ==
8019                     inset_mask_map[i].inset) {
8020                         if (idx >= nb_elem) {
8021                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8022                                 return -EINVAL;
8023                         }
8024                         mask[idx] = inset_mask_map[i].mask;
8025                         idx++;
8026                 }
8027         }
8028
8029         return idx;
8030 }
8031
8032 static void
8033 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8034 {
8035         uint32_t reg = i40e_read_rx_ctl(hw, addr);
8036
8037         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8038         if (reg != val)
8039                 i40e_write_rx_ctl(hw, addr, val);
8040         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8041                     (uint32_t)i40e_read_rx_ctl(hw, addr));
8042 }
8043
8044 static void
8045 i40e_filter_input_set_init(struct i40e_pf *pf)
8046 {
8047         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8048         enum i40e_filter_pctype pctype;
8049         uint64_t input_set, inset_reg;
8050         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8051         int num, i;
8052
8053         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8054              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8055                 if (hw->mac.type == I40E_MAC_X722) {
8056                         if (!I40E_VALID_PCTYPE_X722(pctype))
8057                                 continue;
8058                 } else {
8059                         if (!I40E_VALID_PCTYPE(pctype))
8060                                 continue;
8061                 }
8062
8063                 input_set = i40e_get_default_input_set(pctype);
8064
8065                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8066                                                    I40E_INSET_MASK_NUM_REG);
8067                 if (num < 0)
8068                         return;
8069                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8070                                         input_set);
8071
8072                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8073                                       (uint32_t)(inset_reg & UINT32_MAX));
8074                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8075                                      (uint32_t)((inset_reg >>
8076                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8077                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8078                                       (uint32_t)(inset_reg & UINT32_MAX));
8079                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8080                                      (uint32_t)((inset_reg >>
8081                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8082
8083                 for (i = 0; i < num; i++) {
8084                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8085                                              mask_reg[i]);
8086                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8087                                              mask_reg[i]);
8088                 }
8089                 /*clear unused mask registers of the pctype */
8090                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8091                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8092                                              0);
8093                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8094                                              0);
8095                 }
8096                 I40E_WRITE_FLUSH(hw);
8097
8098                 /* store the default input set */
8099                 pf->hash_input_set[pctype] = input_set;
8100                 pf->fdir.input_set[pctype] = input_set;
8101         }
8102 }
8103
8104 int
8105 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8106                          struct rte_eth_input_set_conf *conf)
8107 {
8108         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8109         enum i40e_filter_pctype pctype;
8110         uint64_t input_set, inset_reg = 0;
8111         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8112         int ret, i, num;
8113
8114         if (!conf) {
8115                 PMD_DRV_LOG(ERR, "Invalid pointer");
8116                 return -EFAULT;
8117         }
8118         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8119             conf->op != RTE_ETH_INPUT_SET_ADD) {
8120                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8121                 return -EINVAL;
8122         }
8123
8124         if (!I40E_VALID_FLOW(conf->flow_type)) {
8125                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8126                 return -EINVAL;
8127         }
8128
8129         if (hw->mac.type == I40E_MAC_X722) {
8130                 /* get translated pctype value in fd pctype register */
8131                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8132                         I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8133                         conf->flow_type)));
8134         } else
8135                 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8136
8137         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8138                                    conf->inset_size);
8139         if (ret) {
8140                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8141                 return -EINVAL;
8142         }
8143         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8144                                     input_set) != 0) {
8145                 PMD_DRV_LOG(ERR, "Invalid input set");
8146                 return -EINVAL;
8147         }
8148         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8149                 /* get inset value in register */
8150                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8151                 inset_reg <<= I40E_32_BIT_WIDTH;
8152                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8153                 input_set |= pf->hash_input_set[pctype];
8154         }
8155         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8156                                            I40E_INSET_MASK_NUM_REG);
8157         if (num < 0)
8158                 return -EINVAL;
8159
8160         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8161
8162         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8163                               (uint32_t)(inset_reg & UINT32_MAX));
8164         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8165                              (uint32_t)((inset_reg >>
8166                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8167
8168         for (i = 0; i < num; i++)
8169                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8170                                      mask_reg[i]);
8171         /*clear unused mask registers of the pctype */
8172         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8173                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8174                                      0);
8175         I40E_WRITE_FLUSH(hw);
8176
8177         pf->hash_input_set[pctype] = input_set;
8178         return 0;
8179 }
8180
8181 int
8182 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8183                          struct rte_eth_input_set_conf *conf)
8184 {
8185         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8186         enum i40e_filter_pctype pctype;
8187         uint64_t input_set, inset_reg = 0;
8188         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8189         int ret, i, num;
8190
8191         if (!hw || !conf) {
8192                 PMD_DRV_LOG(ERR, "Invalid pointer");
8193                 return -EFAULT;
8194         }
8195         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8196             conf->op != RTE_ETH_INPUT_SET_ADD) {
8197                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8198                 return -EINVAL;
8199         }
8200
8201         if (!I40E_VALID_FLOW(conf->flow_type)) {
8202                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8203                 return -EINVAL;
8204         }
8205
8206         pctype = i40e_flowtype_to_pctype(conf->flow_type);
8207
8208         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8209                                    conf->inset_size);
8210         if (ret) {
8211                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8212                 return -EINVAL;
8213         }
8214         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8215                                     input_set) != 0) {
8216                 PMD_DRV_LOG(ERR, "Invalid input set");
8217                 return -EINVAL;
8218         }
8219
8220         /* get inset value in register */
8221         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8222         inset_reg <<= I40E_32_BIT_WIDTH;
8223         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8224
8225         /* Can not change the inset reg for flex payload for fdir,
8226          * it is done by writing I40E_PRTQF_FD_FLXINSET
8227          * in i40e_set_flex_mask_on_pctype.
8228          */
8229         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8230                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8231         else
8232                 input_set |= pf->fdir.input_set[pctype];
8233         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8234                                            I40E_INSET_MASK_NUM_REG);
8235         if (num < 0)
8236                 return -EINVAL;
8237
8238         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8239
8240         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8241                               (uint32_t)(inset_reg & UINT32_MAX));
8242         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8243                              (uint32_t)((inset_reg >>
8244                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8245
8246         for (i = 0; i < num; i++)
8247                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8248                                      mask_reg[i]);
8249         /*clear unused mask registers of the pctype */
8250         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8251                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8252                                      0);
8253         I40E_WRITE_FLUSH(hw);
8254
8255         pf->fdir.input_set[pctype] = input_set;
8256         return 0;
8257 }
8258
8259 static int
8260 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8261 {
8262         int ret = 0;
8263
8264         if (!hw || !info) {
8265                 PMD_DRV_LOG(ERR, "Invalid pointer");
8266                 return -EFAULT;
8267         }
8268
8269         switch (info->info_type) {
8270         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8271                 i40e_get_symmetric_hash_enable_per_port(hw,
8272                                         &(info->info.enable));
8273                 break;
8274         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8275                 ret = i40e_get_hash_filter_global_config(hw,
8276                                 &(info->info.global_conf));
8277                 break;
8278         default:
8279                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8280                                                         info->info_type);
8281                 ret = -EINVAL;
8282                 break;
8283         }
8284
8285         return ret;
8286 }
8287
8288 static int
8289 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8290 {
8291         int ret = 0;
8292
8293         if (!hw || !info) {
8294                 PMD_DRV_LOG(ERR, "Invalid pointer");
8295                 return -EFAULT;
8296         }
8297
8298         switch (info->info_type) {
8299         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8300                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8301                 break;
8302         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8303                 ret = i40e_set_hash_filter_global_config(hw,
8304                                 &(info->info.global_conf));
8305                 break;
8306         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8307                 ret = i40e_hash_filter_inset_select(hw,
8308                                                &(info->info.input_set_conf));
8309                 break;
8310
8311         default:
8312                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8313                                                         info->info_type);
8314                 ret = -EINVAL;
8315                 break;
8316         }
8317
8318         return ret;
8319 }
8320
8321 /* Operations for hash function */
8322 static int
8323 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8324                       enum rte_filter_op filter_op,
8325                       void *arg)
8326 {
8327         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8328         int ret = 0;
8329
8330         switch (filter_op) {
8331         case RTE_ETH_FILTER_NOP:
8332                 break;
8333         case RTE_ETH_FILTER_GET:
8334                 ret = i40e_hash_filter_get(hw,
8335                         (struct rte_eth_hash_filter_info *)arg);
8336                 break;
8337         case RTE_ETH_FILTER_SET:
8338                 ret = i40e_hash_filter_set(hw,
8339                         (struct rte_eth_hash_filter_info *)arg);
8340                 break;
8341         default:
8342                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8343                                                                 filter_op);
8344                 ret = -ENOTSUP;
8345                 break;
8346         }
8347
8348         return ret;
8349 }
8350
8351 /* Convert ethertype filter structure */
8352 static int
8353 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8354                               struct i40e_ethertype_filter *filter)
8355 {
8356         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8357         filter->input.ether_type = input->ether_type;
8358         filter->flags = input->flags;
8359         filter->queue = input->queue;
8360
8361         return 0;
8362 }
8363
8364 /* Check if there exists the ehtertype filter */
8365 struct i40e_ethertype_filter *
8366 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8367                                 const struct i40e_ethertype_filter_input *input)
8368 {
8369         int ret;
8370
8371         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8372         if (ret < 0)
8373                 return NULL;
8374
8375         return ethertype_rule->hash_map[ret];
8376 }
8377
8378 /* Add ethertype filter in SW list */
8379 static int
8380 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8381                                 struct i40e_ethertype_filter *filter)
8382 {
8383         struct i40e_ethertype_rule *rule = &pf->ethertype;
8384         int ret;
8385
8386         ret = rte_hash_add_key(rule->hash_table, &filter->input);
8387         if (ret < 0) {
8388                 PMD_DRV_LOG(ERR,
8389                             "Failed to insert ethertype filter"
8390                             " to hash table %d!",
8391                             ret);
8392                 return ret;
8393         }
8394         rule->hash_map[ret] = filter;
8395
8396         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8397
8398         return 0;
8399 }
8400
8401 /* Delete ethertype filter in SW list */
8402 int
8403 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8404                              struct i40e_ethertype_filter_input *input)
8405 {
8406         struct i40e_ethertype_rule *rule = &pf->ethertype;
8407         struct i40e_ethertype_filter *filter;
8408         int ret;
8409
8410         ret = rte_hash_del_key(rule->hash_table, input);
8411         if (ret < 0) {
8412                 PMD_DRV_LOG(ERR,
8413                             "Failed to delete ethertype filter"
8414                             " to hash table %d!",
8415                             ret);
8416                 return ret;
8417         }
8418         filter = rule->hash_map[ret];
8419         rule->hash_map[ret] = NULL;
8420
8421         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8422         rte_free(filter);
8423
8424         return 0;
8425 }
8426
8427 /*
8428  * Configure ethertype filter, which can director packet by filtering
8429  * with mac address and ether_type or only ether_type
8430  */
8431 int
8432 i40e_ethertype_filter_set(struct i40e_pf *pf,
8433                         struct rte_eth_ethertype_filter *filter,
8434                         bool add)
8435 {
8436         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8437         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
8438         struct i40e_ethertype_filter *ethertype_filter, *node;
8439         struct i40e_ethertype_filter check_filter;
8440         struct i40e_control_filter_stats stats;
8441         uint16_t flags = 0;
8442         int ret;
8443
8444         if (filter->queue >= pf->dev_data->nb_rx_queues) {
8445                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8446                 return -EINVAL;
8447         }
8448         if (filter->ether_type == ETHER_TYPE_IPv4 ||
8449                 filter->ether_type == ETHER_TYPE_IPv6) {
8450                 PMD_DRV_LOG(ERR,
8451                         "unsupported ether_type(0x%04x) in control packet filter.",
8452                         filter->ether_type);
8453                 return -EINVAL;
8454         }
8455         if (filter->ether_type == ETHER_TYPE_VLAN)
8456                 PMD_DRV_LOG(WARNING,
8457                         "filter vlan ether_type in first tag is not supported.");
8458
8459         /* Check if there is the filter in SW list */
8460         memset(&check_filter, 0, sizeof(check_filter));
8461         i40e_ethertype_filter_convert(filter, &check_filter);
8462         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
8463                                                &check_filter.input);
8464         if (add && node) {
8465                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
8466                 return -EINVAL;
8467         }
8468
8469         if (!add && !node) {
8470                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
8471                 return -EINVAL;
8472         }
8473
8474         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8475                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8476         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8477                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8478         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8479
8480         memset(&stats, 0, sizeof(stats));
8481         ret = i40e_aq_add_rem_control_packet_filter(hw,
8482                         filter->mac_addr.addr_bytes,
8483                         filter->ether_type, flags,
8484                         pf->main_vsi->seid,
8485                         filter->queue, add, &stats, NULL);
8486
8487         PMD_DRV_LOG(INFO,
8488                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
8489                 ret, stats.mac_etype_used, stats.etype_used,
8490                 stats.mac_etype_free, stats.etype_free);
8491         if (ret < 0)
8492                 return -ENOSYS;
8493
8494         /* Add or delete a filter in SW list */
8495         if (add) {
8496                 ethertype_filter = rte_zmalloc("ethertype_filter",
8497                                        sizeof(*ethertype_filter), 0);
8498                 rte_memcpy(ethertype_filter, &check_filter,
8499                            sizeof(check_filter));
8500                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
8501         } else {
8502                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
8503         }
8504
8505         return ret;
8506 }
8507
8508 /*
8509  * Handle operations for ethertype filter.
8510  */
8511 static int
8512 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8513                                 enum rte_filter_op filter_op,
8514                                 void *arg)
8515 {
8516         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8517         int ret = 0;
8518
8519         if (filter_op == RTE_ETH_FILTER_NOP)
8520                 return ret;
8521
8522         if (arg == NULL) {
8523                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8524                             filter_op);
8525                 return -EINVAL;
8526         }
8527
8528         switch (filter_op) {
8529         case RTE_ETH_FILTER_ADD:
8530                 ret = i40e_ethertype_filter_set(pf,
8531                         (struct rte_eth_ethertype_filter *)arg,
8532                         TRUE);
8533                 break;
8534         case RTE_ETH_FILTER_DELETE:
8535                 ret = i40e_ethertype_filter_set(pf,
8536                         (struct rte_eth_ethertype_filter *)arg,
8537                         FALSE);
8538                 break;
8539         default:
8540                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
8541                 ret = -ENOSYS;
8542                 break;
8543         }
8544         return ret;
8545 }
8546
8547 static int
8548 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8549                      enum rte_filter_type filter_type,
8550                      enum rte_filter_op filter_op,
8551                      void *arg)
8552 {
8553         int ret = 0;
8554
8555         if (dev == NULL)
8556                 return -EINVAL;
8557
8558         switch (filter_type) {
8559         case RTE_ETH_FILTER_NONE:
8560                 /* For global configuration */
8561                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8562                 break;
8563         case RTE_ETH_FILTER_HASH:
8564                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8565                 break;
8566         case RTE_ETH_FILTER_MACVLAN:
8567                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8568                 break;
8569         case RTE_ETH_FILTER_ETHERTYPE:
8570                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8571                 break;
8572         case RTE_ETH_FILTER_TUNNEL:
8573                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8574                 break;
8575         case RTE_ETH_FILTER_FDIR:
8576                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8577                 break;
8578         case RTE_ETH_FILTER_GENERIC:
8579                 if (filter_op != RTE_ETH_FILTER_GET)
8580                         return -EINVAL;
8581                 *(const void **)arg = &i40e_flow_ops;
8582                 break;
8583         default:
8584                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8585                                                         filter_type);
8586                 ret = -EINVAL;
8587                 break;
8588         }
8589
8590         return ret;
8591 }
8592
8593 /*
8594  * Check and enable Extended Tag.
8595  * Enabling Extended Tag is important for 40G performance.
8596  */
8597 static void
8598 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8599 {
8600         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
8601         uint32_t buf = 0;
8602         int ret;
8603
8604         ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8605                                       PCI_DEV_CAP_REG);
8606         if (ret < 0) {
8607                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8608                             PCI_DEV_CAP_REG);
8609                 return;
8610         }
8611         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
8612                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
8613                 return;
8614         }
8615
8616         buf = 0;
8617         ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8618                                       PCI_DEV_CTRL_REG);
8619         if (ret < 0) {
8620                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8621                             PCI_DEV_CTRL_REG);
8622                 return;
8623         }
8624         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
8625                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
8626                 return;
8627         }
8628         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
8629         ret = rte_eal_pci_write_config(pci_dev, &buf, sizeof(buf),
8630                                        PCI_DEV_CTRL_REG);
8631         if (ret < 0) {
8632                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
8633                             PCI_DEV_CTRL_REG);
8634                 return;
8635         }
8636 }
8637
8638 /*
8639  * As some registers wouldn't be reset unless a global hardware reset,
8640  * hardware initialization is needed to put those registers into an
8641  * expected initial state.
8642  */
8643 static void
8644 i40e_hw_init(struct rte_eth_dev *dev)
8645 {
8646         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8647
8648         i40e_enable_extended_tag(dev);
8649
8650         /* clear the PF Queue Filter control register */
8651         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
8652
8653         /* Disable symmetric hash per port */
8654         i40e_set_symmetric_hash_enable_per_port(hw, 0);
8655 }
8656
8657 enum i40e_filter_pctype
8658 i40e_flowtype_to_pctype(uint16_t flow_type)
8659 {
8660         static const enum i40e_filter_pctype pctype_table[] = {
8661                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
8662                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
8663                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
8664                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
8665                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
8666                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
8667                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
8668                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
8669                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
8670                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
8671                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
8672                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
8673                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
8674                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
8675                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
8676                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
8677                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
8678                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
8679                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
8680         };
8681
8682         return pctype_table[flow_type];
8683 }
8684
8685 uint16_t
8686 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
8687 {
8688         static const uint16_t flowtype_table[] = {
8689                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
8690                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8691                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8692                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8693                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8694                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8695                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8696                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8697                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8698                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8699                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8700                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8701                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
8702                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8703                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
8704                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
8705                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8706                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8707                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8708                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8709                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8710                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8711                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8712                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8713                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8714                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8715                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8716                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8717                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8718                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8719                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8720         };
8721
8722         return flowtype_table[pctype];
8723 }
8724
8725 /*
8726  * On X710, performance number is far from the expectation on recent firmware
8727  * versions; on XL710, performance number is also far from the expectation on
8728  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8729  * mode is enabled and port MAC address is equal to the packet destination MAC
8730  * address. The fix for this issue may not be integrated in the following
8731  * firmware version. So the workaround in software driver is needed. It needs
8732  * to modify the initial values of 3 internal only registers for both X710 and
8733  * XL710. Note that the values for X710 or XL710 could be different, and the
8734  * workaround can be removed when it is fixed in firmware in the future.
8735  */
8736
8737 /* For both X710 and XL710 */
8738 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
8739 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
8740
8741 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8742 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
8743
8744 /* For X722 */
8745 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
8746 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
8747
8748 /* For X710 */
8749 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
8750 /* For XL710 */
8751 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
8752 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
8753
8754 static int
8755 i40e_dev_sync_phy_type(struct i40e_hw *hw)
8756 {
8757         enum i40e_status_code status;
8758         struct i40e_aq_get_phy_abilities_resp phy_ab;
8759         int ret = -ENOTSUP;
8760
8761         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
8762                                               NULL);
8763
8764         if (status)
8765                 return ret;
8766
8767         return 0;
8768 }
8769
8770 static void
8771 i40e_configure_registers(struct i40e_hw *hw)
8772 {
8773         static struct {
8774                 uint32_t addr;
8775                 uint64_t val;
8776         } reg_table[] = {
8777                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
8778                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
8779                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8780         };
8781         uint64_t reg;
8782         uint32_t i;
8783         int ret;
8784
8785         for (i = 0; i < RTE_DIM(reg_table); i++) {
8786                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
8787                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
8788                                 reg_table[i].val =
8789                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
8790                         else /* For X710/XL710/XXV710 */
8791                                 reg_table[i].val =
8792                                         I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE;
8793                 }
8794
8795                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
8796                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
8797                                 reg_table[i].val =
8798                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
8799                         else /* For X710/XL710/XXV710 */
8800                                 reg_table[i].val =
8801                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
8802                 }
8803
8804                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8805                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
8806                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
8807                                 reg_table[i].val =
8808                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
8809                         else /* For X710 */
8810                                 reg_table[i].val =
8811                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
8812                 }
8813
8814                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8815                                                         &reg, NULL);
8816                 if (ret < 0) {
8817                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8818                                                         reg_table[i].addr);
8819                         break;
8820                 }
8821                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8822                                                 reg_table[i].addr, reg);
8823                 if (reg == reg_table[i].val)
8824                         continue;
8825
8826                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
8827                                                 reg_table[i].val, NULL);
8828                 if (ret < 0) {
8829                         PMD_DRV_LOG(ERR,
8830                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
8831                                 reg_table[i].val, reg_table[i].addr);
8832                         break;
8833                 }
8834                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
8835                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
8836         }
8837 }
8838
8839 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
8840 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
8841 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
8842 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
8843 static int
8844 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
8845 {
8846         uint32_t reg;
8847         int ret;
8848
8849         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
8850                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
8851                 return -EINVAL;
8852         }
8853
8854         /* Configure for double VLAN RX stripping */
8855         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
8856         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
8857                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
8858                 ret = i40e_aq_debug_write_register(hw,
8859                                                    I40E_VSI_TSR(vsi->vsi_id),
8860                                                    reg, NULL);
8861                 if (ret < 0) {
8862                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
8863                                     vsi->vsi_id);
8864                         return I40E_ERR_CONFIG;
8865                 }
8866         }
8867
8868         /* Configure for double VLAN TX insertion */
8869         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
8870         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
8871                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
8872                 ret = i40e_aq_debug_write_register(hw,
8873                                                    I40E_VSI_L2TAGSTXVALID(
8874                                                    vsi->vsi_id), reg, NULL);
8875                 if (ret < 0) {
8876                         PMD_DRV_LOG(ERR,
8877                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
8878                                 vsi->vsi_id);
8879                         return I40E_ERR_CONFIG;
8880                 }
8881         }
8882
8883         return 0;
8884 }
8885
8886 /**
8887  * i40e_aq_add_mirror_rule
8888  * @hw: pointer to the hardware structure
8889  * @seid: VEB seid to add mirror rule to
8890  * @dst_id: destination vsi seid
8891  * @entries: Buffer which contains the entities to be mirrored
8892  * @count: number of entities contained in the buffer
8893  * @rule_id:the rule_id of the rule to be added
8894  *
8895  * Add a mirror rule for a given veb.
8896  *
8897  **/
8898 static enum i40e_status_code
8899 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
8900                         uint16_t seid, uint16_t dst_id,
8901                         uint16_t rule_type, uint16_t *entries,
8902                         uint16_t count, uint16_t *rule_id)
8903 {
8904         struct i40e_aq_desc desc;
8905         struct i40e_aqc_add_delete_mirror_rule cmd;
8906         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8907                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8908                 &desc.params.raw;
8909         uint16_t buff_len;
8910         enum i40e_status_code status;
8911
8912         i40e_fill_default_direct_cmd_desc(&desc,
8913                                           i40e_aqc_opc_add_mirror_rule);
8914         memset(&cmd, 0, sizeof(cmd));
8915
8916         buff_len = sizeof(uint16_t) * count;
8917         desc.datalen = rte_cpu_to_le_16(buff_len);
8918         if (buff_len > 0)
8919                 desc.flags |= rte_cpu_to_le_16(
8920                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8921         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8922                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8923         cmd.num_entries = rte_cpu_to_le_16(count);
8924         cmd.seid = rte_cpu_to_le_16(seid);
8925         cmd.destination = rte_cpu_to_le_16(dst_id);
8926
8927         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8928         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8929         PMD_DRV_LOG(INFO,
8930                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
8931                 hw->aq.asq_last_status, resp->rule_id,
8932                 resp->mirror_rules_used, resp->mirror_rules_free);
8933         *rule_id = rte_le_to_cpu_16(resp->rule_id);
8934
8935         return status;
8936 }
8937
8938 /**
8939  * i40e_aq_del_mirror_rule
8940  * @hw: pointer to the hardware structure
8941  * @seid: VEB seid to add mirror rule to
8942  * @entries: Buffer which contains the entities to be mirrored
8943  * @count: number of entities contained in the buffer
8944  * @rule_id:the rule_id of the rule to be delete
8945  *
8946  * Delete a mirror rule for a given veb.
8947  *
8948  **/
8949 static enum i40e_status_code
8950 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8951                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8952                 uint16_t count, uint16_t rule_id)
8953 {
8954         struct i40e_aq_desc desc;
8955         struct i40e_aqc_add_delete_mirror_rule cmd;
8956         uint16_t buff_len = 0;
8957         enum i40e_status_code status;
8958         void *buff = NULL;
8959
8960         i40e_fill_default_direct_cmd_desc(&desc,
8961                                           i40e_aqc_opc_delete_mirror_rule);
8962         memset(&cmd, 0, sizeof(cmd));
8963         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8964                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8965                                                           I40E_AQ_FLAG_RD));
8966                 cmd.num_entries = count;
8967                 buff_len = sizeof(uint16_t) * count;
8968                 desc.datalen = rte_cpu_to_le_16(buff_len);
8969                 buff = (void *)entries;
8970         } else
8971                 /* rule id is filled in destination field for deleting mirror rule */
8972                 cmd.destination = rte_cpu_to_le_16(rule_id);
8973
8974         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8975                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8976         cmd.seid = rte_cpu_to_le_16(seid);
8977
8978         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8979         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
8980
8981         return status;
8982 }
8983
8984 /**
8985  * i40e_mirror_rule_set
8986  * @dev: pointer to the hardware structure
8987  * @mirror_conf: mirror rule info
8988  * @sw_id: mirror rule's sw_id
8989  * @on: enable/disable
8990  *
8991  * set a mirror rule.
8992  *
8993  **/
8994 static int
8995 i40e_mirror_rule_set(struct rte_eth_dev *dev,
8996                         struct rte_eth_mirror_conf *mirror_conf,
8997                         uint8_t sw_id, uint8_t on)
8998 {
8999         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9000         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9001         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9002         struct i40e_mirror_rule *parent = NULL;
9003         uint16_t seid, dst_seid, rule_id;
9004         uint16_t i, j = 0;
9005         int ret;
9006
9007         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9008
9009         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9010                 PMD_DRV_LOG(ERR,
9011                         "mirror rule can not be configured without veb or vfs.");
9012                 return -ENOSYS;
9013         }
9014         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9015                 PMD_DRV_LOG(ERR, "mirror table is full.");
9016                 return -ENOSPC;
9017         }
9018         if (mirror_conf->dst_pool > pf->vf_num) {
9019                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9020                                  mirror_conf->dst_pool);
9021                 return -EINVAL;
9022         }
9023
9024         seid = pf->main_vsi->veb->seid;
9025
9026         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9027                 if (sw_id <= it->index) {
9028                         mirr_rule = it;
9029                         break;
9030                 }
9031                 parent = it;
9032         }
9033         if (mirr_rule && sw_id == mirr_rule->index) {
9034                 if (on) {
9035                         PMD_DRV_LOG(ERR, "mirror rule exists.");
9036                         return -EEXIST;
9037                 } else {
9038                         ret = i40e_aq_del_mirror_rule(hw, seid,
9039                                         mirr_rule->rule_type,
9040                                         mirr_rule->entries,
9041                                         mirr_rule->num_entries, mirr_rule->id);
9042                         if (ret < 0) {
9043                                 PMD_DRV_LOG(ERR,
9044                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
9045                                         ret, hw->aq.asq_last_status);
9046                                 return -ENOSYS;
9047                         }
9048                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9049                         rte_free(mirr_rule);
9050                         pf->nb_mirror_rule--;
9051                         return 0;
9052                 }
9053         } else if (!on) {
9054                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9055                 return -ENOENT;
9056         }
9057
9058         mirr_rule = rte_zmalloc("i40e_mirror_rule",
9059                                 sizeof(struct i40e_mirror_rule) , 0);
9060         if (!mirr_rule) {
9061                 PMD_DRV_LOG(ERR, "failed to allocate memory");
9062                 return I40E_ERR_NO_MEMORY;
9063         }
9064         switch (mirror_conf->rule_type) {
9065         case ETH_MIRROR_VLAN:
9066                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9067                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9068                                 mirr_rule->entries[j] =
9069                                         mirror_conf->vlan.vlan_id[i];
9070                                 j++;
9071                         }
9072                 }
9073                 if (j == 0) {
9074                         PMD_DRV_LOG(ERR, "vlan is not specified.");
9075                         rte_free(mirr_rule);
9076                         return -EINVAL;
9077                 }
9078                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9079                 break;
9080         case ETH_MIRROR_VIRTUAL_POOL_UP:
9081         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9082                 /* check if the specified pool bit is out of range */
9083                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9084                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
9085                         rte_free(mirr_rule);
9086                         return -EINVAL;
9087                 }
9088                 for (i = 0, j = 0; i < pf->vf_num; i++) {
9089                         if (mirror_conf->pool_mask & (1ULL << i)) {
9090                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9091                                 j++;
9092                         }
9093                 }
9094                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9095                         /* add pf vsi to entries */
9096                         mirr_rule->entries[j] = pf->main_vsi_seid;
9097                         j++;
9098                 }
9099                 if (j == 0) {
9100                         PMD_DRV_LOG(ERR, "pool is not specified.");
9101                         rte_free(mirr_rule);
9102                         return -EINVAL;
9103                 }
9104                 /* egress and ingress in aq commands means from switch but not port */
9105                 mirr_rule->rule_type =
9106                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9107                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9108                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9109                 break;
9110         case ETH_MIRROR_UPLINK_PORT:
9111                 /* egress and ingress in aq commands means from switch but not port*/
9112                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9113                 break;
9114         case ETH_MIRROR_DOWNLINK_PORT:
9115                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9116                 break;
9117         default:
9118                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9119                         mirror_conf->rule_type);
9120                 rte_free(mirr_rule);
9121                 return -EINVAL;
9122         }
9123
9124         /* If the dst_pool is equal to vf_num, consider it as PF */
9125         if (mirror_conf->dst_pool == pf->vf_num)
9126                 dst_seid = pf->main_vsi_seid;
9127         else
9128                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9129
9130         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9131                                       mirr_rule->rule_type, mirr_rule->entries,
9132                                       j, &rule_id);
9133         if (ret < 0) {
9134                 PMD_DRV_LOG(ERR,
9135                         "failed to add mirror rule: ret = %d, aq_err = %d.",
9136                         ret, hw->aq.asq_last_status);
9137                 rte_free(mirr_rule);
9138                 return -ENOSYS;
9139         }
9140
9141         mirr_rule->index = sw_id;
9142         mirr_rule->num_entries = j;
9143         mirr_rule->id = rule_id;
9144         mirr_rule->dst_vsi_seid = dst_seid;
9145
9146         if (parent)
9147                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9148         else
9149                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9150
9151         pf->nb_mirror_rule++;
9152         return 0;
9153 }
9154
9155 /**
9156  * i40e_mirror_rule_reset
9157  * @dev: pointer to the device
9158  * @sw_id: mirror rule's sw_id
9159  *
9160  * reset a mirror rule.
9161  *
9162  **/
9163 static int
9164 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9165 {
9166         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9167         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9168         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9169         uint16_t seid;
9170         int ret;
9171
9172         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9173
9174         seid = pf->main_vsi->veb->seid;
9175
9176         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9177                 if (sw_id == it->index) {
9178                         mirr_rule = it;
9179                         break;
9180                 }
9181         }
9182         if (mirr_rule) {
9183                 ret = i40e_aq_del_mirror_rule(hw, seid,
9184                                 mirr_rule->rule_type,
9185                                 mirr_rule->entries,
9186                                 mirr_rule->num_entries, mirr_rule->id);
9187                 if (ret < 0) {
9188                         PMD_DRV_LOG(ERR,
9189                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
9190                                 ret, hw->aq.asq_last_status);
9191                         return -ENOSYS;
9192                 }
9193                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9194                 rte_free(mirr_rule);
9195                 pf->nb_mirror_rule--;
9196         } else {
9197                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9198                 return -ENOENT;
9199         }
9200         return 0;
9201 }
9202
9203 static uint64_t
9204 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9205 {
9206         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9207         uint64_t systim_cycles;
9208
9209         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9210         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9211                         << 32;
9212
9213         return systim_cycles;
9214 }
9215
9216 static uint64_t
9217 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9218 {
9219         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9220         uint64_t rx_tstamp;
9221
9222         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9223         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9224                         << 32;
9225
9226         return rx_tstamp;
9227 }
9228
9229 static uint64_t
9230 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9231 {
9232         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9233         uint64_t tx_tstamp;
9234
9235         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9236         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9237                         << 32;
9238
9239         return tx_tstamp;
9240 }
9241
9242 static void
9243 i40e_start_timecounters(struct rte_eth_dev *dev)
9244 {
9245         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9246         struct i40e_adapter *adapter =
9247                         (struct i40e_adapter *)dev->data->dev_private;
9248         struct rte_eth_link link;
9249         uint32_t tsync_inc_l;
9250         uint32_t tsync_inc_h;
9251
9252         /* Get current link speed. */
9253         memset(&link, 0, sizeof(link));
9254         i40e_dev_link_update(dev, 1);
9255         rte_i40e_dev_atomic_read_link_status(dev, &link);
9256
9257         switch (link.link_speed) {
9258         case ETH_SPEED_NUM_40G:
9259                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9260                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9261                 break;
9262         case ETH_SPEED_NUM_10G:
9263                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9264                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9265                 break;
9266         case ETH_SPEED_NUM_1G:
9267                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9268                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9269                 break;
9270         default:
9271                 tsync_inc_l = 0x0;
9272                 tsync_inc_h = 0x0;
9273         }
9274
9275         /* Set the timesync increment value. */
9276         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9277         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9278
9279         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9280         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9281         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9282
9283         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9284         adapter->systime_tc.cc_shift = 0;
9285         adapter->systime_tc.nsec_mask = 0;
9286
9287         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9288         adapter->rx_tstamp_tc.cc_shift = 0;
9289         adapter->rx_tstamp_tc.nsec_mask = 0;
9290
9291         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9292         adapter->tx_tstamp_tc.cc_shift = 0;
9293         adapter->tx_tstamp_tc.nsec_mask = 0;
9294 }
9295
9296 static int
9297 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9298 {
9299         struct i40e_adapter *adapter =
9300                         (struct i40e_adapter *)dev->data->dev_private;
9301
9302         adapter->systime_tc.nsec += delta;
9303         adapter->rx_tstamp_tc.nsec += delta;
9304         adapter->tx_tstamp_tc.nsec += delta;
9305
9306         return 0;
9307 }
9308
9309 static int
9310 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9311 {
9312         uint64_t ns;
9313         struct i40e_adapter *adapter =
9314                         (struct i40e_adapter *)dev->data->dev_private;
9315
9316         ns = rte_timespec_to_ns(ts);
9317
9318         /* Set the timecounters to a new value. */
9319         adapter->systime_tc.nsec = ns;
9320         adapter->rx_tstamp_tc.nsec = ns;
9321         adapter->tx_tstamp_tc.nsec = ns;
9322
9323         return 0;
9324 }
9325
9326 static int
9327 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9328 {
9329         uint64_t ns, systime_cycles;
9330         struct i40e_adapter *adapter =
9331                         (struct i40e_adapter *)dev->data->dev_private;
9332
9333         systime_cycles = i40e_read_systime_cyclecounter(dev);
9334         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9335         *ts = rte_ns_to_timespec(ns);
9336
9337         return 0;
9338 }
9339
9340 static int
9341 i40e_timesync_enable(struct rte_eth_dev *dev)
9342 {
9343         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9344         uint32_t tsync_ctl_l;
9345         uint32_t tsync_ctl_h;
9346
9347         /* Stop the timesync system time. */
9348         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9349         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9350         /* Reset the timesync system time value. */
9351         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9352         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9353
9354         i40e_start_timecounters(dev);
9355
9356         /* Clear timesync registers. */
9357         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9358         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9359         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9360         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9361         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9362         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9363
9364         /* Enable timestamping of PTP packets. */
9365         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9366         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9367
9368         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9369         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9370         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9371
9372         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9373         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9374
9375         return 0;
9376 }
9377
9378 static int
9379 i40e_timesync_disable(struct rte_eth_dev *dev)
9380 {
9381         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9382         uint32_t tsync_ctl_l;
9383         uint32_t tsync_ctl_h;
9384
9385         /* Disable timestamping of transmitted PTP packets. */
9386         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9387         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9388
9389         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9390         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9391
9392         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9393         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9394
9395         /* Reset the timesync increment value. */
9396         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9397         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9398
9399         return 0;
9400 }
9401
9402 static int
9403 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9404                                 struct timespec *timestamp, uint32_t flags)
9405 {
9406         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9407         struct i40e_adapter *adapter =
9408                 (struct i40e_adapter *)dev->data->dev_private;
9409
9410         uint32_t sync_status;
9411         uint32_t index = flags & 0x03;
9412         uint64_t rx_tstamp_cycles;
9413         uint64_t ns;
9414
9415         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9416         if ((sync_status & (1 << index)) == 0)
9417                 return -EINVAL;
9418
9419         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9420         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9421         *timestamp = rte_ns_to_timespec(ns);
9422
9423         return 0;
9424 }
9425
9426 static int
9427 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9428                                 struct timespec *timestamp)
9429 {
9430         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9431         struct i40e_adapter *adapter =
9432                 (struct i40e_adapter *)dev->data->dev_private;
9433
9434         uint32_t sync_status;
9435         uint64_t tx_tstamp_cycles;
9436         uint64_t ns;
9437
9438         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9439         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9440                 return -EINVAL;
9441
9442         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9443         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9444         *timestamp = rte_ns_to_timespec(ns);
9445
9446         return 0;
9447 }
9448
9449 /*
9450  * i40e_parse_dcb_configure - parse dcb configure from user
9451  * @dev: the device being configured
9452  * @dcb_cfg: pointer of the result of parse
9453  * @*tc_map: bit map of enabled traffic classes
9454  *
9455  * Returns 0 on success, negative value on failure
9456  */
9457 static int
9458 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9459                          struct i40e_dcbx_config *dcb_cfg,
9460                          uint8_t *tc_map)
9461 {
9462         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9463         uint8_t i, tc_bw, bw_lf;
9464
9465         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9466
9467         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9468         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9469                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9470                 return -EINVAL;
9471         }
9472
9473         /* assume each tc has the same bw */
9474         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9475         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9476                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9477         /* to ensure the sum of tcbw is equal to 100 */
9478         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9479         for (i = 0; i < bw_lf; i++)
9480                 dcb_cfg->etscfg.tcbwtable[i]++;
9481
9482         /* assume each tc has the same Transmission Selection Algorithm */
9483         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9484                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9485
9486         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9487                 dcb_cfg->etscfg.prioritytable[i] =
9488                                 dcb_rx_conf->dcb_tc[i];
9489
9490         /* FW needs one App to configure HW */
9491         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9492         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9493         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9494         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9495
9496         if (dcb_rx_conf->nb_tcs == 0)
9497                 *tc_map = 1; /* tc0 only */
9498         else
9499                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9500
9501         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9502                 dcb_cfg->pfc.willing = 0;
9503                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9504                 dcb_cfg->pfc.pfcenable = *tc_map;
9505         }
9506         return 0;
9507 }
9508
9509
9510 static enum i40e_status_code
9511 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9512                               struct i40e_aqc_vsi_properties_data *info,
9513                               uint8_t enabled_tcmap)
9514 {
9515         enum i40e_status_code ret;
9516         int i, total_tc = 0;
9517         uint16_t qpnum_per_tc, bsf, qp_idx;
9518         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9519         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9520         uint16_t used_queues;
9521
9522         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9523         if (ret != I40E_SUCCESS)
9524                 return ret;
9525
9526         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9527                 if (enabled_tcmap & (1 << i))
9528                         total_tc++;
9529         }
9530         if (total_tc == 0)
9531                 total_tc = 1;
9532         vsi->enabled_tc = enabled_tcmap;
9533
9534         /* different VSI has different queues assigned */
9535         if (vsi->type == I40E_VSI_MAIN)
9536                 used_queues = dev_data->nb_rx_queues -
9537                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9538         else if (vsi->type == I40E_VSI_VMDQ2)
9539                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9540         else {
9541                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9542                 return I40E_ERR_NO_AVAILABLE_VSI;
9543         }
9544
9545         qpnum_per_tc = used_queues / total_tc;
9546         /* Number of queues per enabled TC */
9547         if (qpnum_per_tc == 0) {
9548                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9549                 return I40E_ERR_INVALID_QP_ID;
9550         }
9551         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9552                                 I40E_MAX_Q_PER_TC);
9553         bsf = rte_bsf32(qpnum_per_tc);
9554
9555         /**
9556          * Configure TC and queue mapping parameters, for enabled TC,
9557          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9558          * default queue will serve it.
9559          */
9560         qp_idx = 0;
9561         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9562                 if (vsi->enabled_tc & (1 << i)) {
9563                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9564                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9565                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9566                         qp_idx += qpnum_per_tc;
9567                 } else
9568                         info->tc_mapping[i] = 0;
9569         }
9570
9571         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9572         if (vsi->type == I40E_VSI_SRIOV) {
9573                 info->mapping_flags |=
9574                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9575                 for (i = 0; i < vsi->nb_qps; i++)
9576                         info->queue_mapping[i] =
9577                                 rte_cpu_to_le_16(vsi->base_queue + i);
9578         } else {
9579                 info->mapping_flags |=
9580                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9581                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9582         }
9583         info->valid_sections |=
9584                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9585
9586         return I40E_SUCCESS;
9587 }
9588
9589 /*
9590  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9591  * @veb: VEB to be configured
9592  * @tc_map: enabled TC bitmap
9593  *
9594  * Returns 0 on success, negative value on failure
9595  */
9596 static enum i40e_status_code
9597 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9598 {
9599         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9600         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9601         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9602         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9603         enum i40e_status_code ret = I40E_SUCCESS;
9604         int i;
9605         uint32_t bw_max;
9606
9607         /* Check if enabled_tc is same as existing or new TCs */
9608         if (veb->enabled_tc == tc_map)
9609                 return ret;
9610
9611         /* configure tc bandwidth */
9612         memset(&veb_bw, 0, sizeof(veb_bw));
9613         veb_bw.tc_valid_bits = tc_map;
9614         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9615         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9616                 if (tc_map & BIT_ULL(i))
9617                         veb_bw.tc_bw_share_credits[i] = 1;
9618         }
9619         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
9620                                                    &veb_bw, NULL);
9621         if (ret) {
9622                 PMD_INIT_LOG(ERR,
9623                         "AQ command Config switch_comp BW allocation per TC failed = %d",
9624                         hw->aq.asq_last_status);
9625                 return ret;
9626         }
9627
9628         memset(&ets_query, 0, sizeof(ets_query));
9629         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9630                                                    &ets_query, NULL);
9631         if (ret != I40E_SUCCESS) {
9632                 PMD_DRV_LOG(ERR,
9633                         "Failed to get switch_comp ETS configuration %u",
9634                         hw->aq.asq_last_status);
9635                 return ret;
9636         }
9637         memset(&bw_query, 0, sizeof(bw_query));
9638         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9639                                                   &bw_query, NULL);
9640         if (ret != I40E_SUCCESS) {
9641                 PMD_DRV_LOG(ERR,
9642                         "Failed to get switch_comp bandwidth configuration %u",
9643                         hw->aq.asq_last_status);
9644                 return ret;
9645         }
9646
9647         /* store and print out BW info */
9648         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
9649         veb->bw_info.bw_max = ets_query.tc_bw_max;
9650         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
9651         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
9652         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
9653                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
9654                      I40E_16_BIT_WIDTH);
9655         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9656                 veb->bw_info.bw_ets_share_credits[i] =
9657                                 bw_query.tc_bw_share_credits[i];
9658                 veb->bw_info.bw_ets_credits[i] =
9659                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
9660                 /* 4 bits per TC, 4th bit is reserved */
9661                 veb->bw_info.bw_ets_max[i] =
9662                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
9663                                   RTE_LEN2MASK(3, uint8_t));
9664                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
9665                             veb->bw_info.bw_ets_share_credits[i]);
9666                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
9667                             veb->bw_info.bw_ets_credits[i]);
9668                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
9669                             veb->bw_info.bw_ets_max[i]);
9670         }
9671
9672         veb->enabled_tc = tc_map;
9673
9674         return ret;
9675 }
9676
9677
9678 /*
9679  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
9680  * @vsi: VSI to be configured
9681  * @tc_map: enabled TC bitmap
9682  *
9683  * Returns 0 on success, negative value on failure
9684  */
9685 static enum i40e_status_code
9686 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
9687 {
9688         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
9689         struct i40e_vsi_context ctxt;
9690         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
9691         enum i40e_status_code ret = I40E_SUCCESS;
9692         int i;
9693
9694         /* Check if enabled_tc is same as existing or new TCs */
9695         if (vsi->enabled_tc == tc_map)
9696                 return ret;
9697
9698         /* configure tc bandwidth */
9699         memset(&bw_data, 0, sizeof(bw_data));
9700         bw_data.tc_valid_bits = tc_map;
9701         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9702         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9703                 if (tc_map & BIT_ULL(i))
9704                         bw_data.tc_bw_credits[i] = 1;
9705         }
9706         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
9707         if (ret) {
9708                 PMD_INIT_LOG(ERR,
9709                         "AQ command Config VSI BW allocation per TC failed = %d",
9710                         hw->aq.asq_last_status);
9711                 goto out;
9712         }
9713         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
9714                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
9715
9716         /* Update Queue Pairs Mapping for currently enabled UPs */
9717         ctxt.seid = vsi->seid;
9718         ctxt.pf_num = hw->pf_id;
9719         ctxt.vf_num = 0;
9720         ctxt.uplink_seid = vsi->uplink_seid;
9721         ctxt.info = vsi->info;
9722         i40e_get_cap(hw);
9723         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
9724         if (ret)
9725                 goto out;
9726
9727         /* Update the VSI after updating the VSI queue-mapping information */
9728         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9729         if (ret) {
9730                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
9731                         hw->aq.asq_last_status);
9732                 goto out;
9733         }
9734         /* update the local VSI info with updated queue map */
9735         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
9736                                         sizeof(vsi->info.tc_mapping));
9737         (void)rte_memcpy(&vsi->info.queue_mapping,
9738                         &ctxt.info.queue_mapping,
9739                 sizeof(vsi->info.queue_mapping));
9740         vsi->info.mapping_flags = ctxt.info.mapping_flags;
9741         vsi->info.valid_sections = 0;
9742
9743         /* query and update current VSI BW information */
9744         ret = i40e_vsi_get_bw_config(vsi);
9745         if (ret) {
9746                 PMD_INIT_LOG(ERR,
9747                          "Failed updating vsi bw info, err %s aq_err %s",
9748                          i40e_stat_str(hw, ret),
9749                          i40e_aq_str(hw, hw->aq.asq_last_status));
9750                 goto out;
9751         }
9752
9753         vsi->enabled_tc = tc_map;
9754
9755 out:
9756         return ret;
9757 }
9758
9759 /*
9760  * i40e_dcb_hw_configure - program the dcb setting to hw
9761  * @pf: pf the configuration is taken on
9762  * @new_cfg: new configuration
9763  * @tc_map: enabled TC bitmap
9764  *
9765  * Returns 0 on success, negative value on failure
9766  */
9767 static enum i40e_status_code
9768 i40e_dcb_hw_configure(struct i40e_pf *pf,
9769                       struct i40e_dcbx_config *new_cfg,
9770                       uint8_t tc_map)
9771 {
9772         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9773         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9774         struct i40e_vsi *main_vsi = pf->main_vsi;
9775         struct i40e_vsi_list *vsi_list;
9776         enum i40e_status_code ret;
9777         int i;
9778         uint32_t val;
9779
9780         /* Use the FW API if FW > v4.4*/
9781         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9782               (hw->aq.fw_maj_ver >= 5))) {
9783                 PMD_INIT_LOG(ERR,
9784                         "FW < v4.4, can not use FW LLDP API to configure DCB");
9785                 return I40E_ERR_FIRMWARE_API_VERSION;
9786         }
9787
9788         /* Check if need reconfiguration */
9789         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9790                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9791                 return I40E_SUCCESS;
9792         }
9793
9794         /* Copy the new config to the current config */
9795         *old_cfg = *new_cfg;
9796         old_cfg->etsrec = old_cfg->etscfg;
9797         ret = i40e_set_dcb_config(hw);
9798         if (ret) {
9799                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
9800                          i40e_stat_str(hw, ret),
9801                          i40e_aq_str(hw, hw->aq.asq_last_status));
9802                 return ret;
9803         }
9804         /* set receive Arbiter to RR mode and ETS scheme by default */
9805         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9806                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9807                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
9808                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9809                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9810                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9811                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9812                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9813                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9814                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9815                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9816                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9817                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9818         }
9819         /* get local mib to check whether it is configured correctly */
9820         /* IEEE mode */
9821         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9822         /* Get Local DCB Config */
9823         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9824                                      &hw->local_dcbx_config);
9825
9826         /* if Veb is created, need to update TC of it at first */
9827         if (main_vsi->veb) {
9828                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
9829                 if (ret)
9830                         PMD_INIT_LOG(WARNING,
9831                                  "Failed configuring TC for VEB seid=%d",
9832                                  main_vsi->veb->seid);
9833         }
9834         /* Update each VSI */
9835         i40e_vsi_config_tc(main_vsi, tc_map);
9836         if (main_vsi->veb) {
9837                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
9838                         /* Beside main VSI and VMDQ VSIs, only enable default
9839                          * TC for other VSIs
9840                          */
9841                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
9842                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9843                                                          tc_map);
9844                         else
9845                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9846                                                          I40E_DEFAULT_TCMAP);
9847                         if (ret)
9848                                 PMD_INIT_LOG(WARNING,
9849                                         "Failed configuring TC for VSI seid=%d",
9850                                         vsi_list->vsi->seid);
9851                         /* continue */
9852                 }
9853         }
9854         return I40E_SUCCESS;
9855 }
9856
9857 /*
9858  * i40e_dcb_init_configure - initial dcb config
9859  * @dev: device being configured
9860  * @sw_dcb: indicate whether dcb is sw configured or hw offload
9861  *
9862  * Returns 0 on success, negative value on failure
9863  */
9864 static int
9865 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
9866 {
9867         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9868         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9869         int ret = 0;
9870
9871         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9872                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9873                 return -ENOTSUP;
9874         }
9875
9876         /* DCB initialization:
9877          * Update DCB configuration from the Firmware and configure
9878          * LLDP MIB change event.
9879          */
9880         if (sw_dcb == TRUE) {
9881                 ret = i40e_init_dcb(hw);
9882                 /* If lldp agent is stopped, the return value from
9883                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
9884                  * adminq status. Otherwise, it should return success.
9885                  */
9886                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
9887                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
9888                         memset(&hw->local_dcbx_config, 0,
9889                                 sizeof(struct i40e_dcbx_config));
9890                         /* set dcb default configuration */
9891                         hw->local_dcbx_config.etscfg.willing = 0;
9892                         hw->local_dcbx_config.etscfg.maxtcs = 0;
9893                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
9894                         hw->local_dcbx_config.etscfg.tsatable[0] =
9895                                                 I40E_IEEE_TSA_ETS;
9896                         hw->local_dcbx_config.etsrec =
9897                                 hw->local_dcbx_config.etscfg;
9898                         hw->local_dcbx_config.pfc.willing = 0;
9899                         hw->local_dcbx_config.pfc.pfccap =
9900                                                 I40E_MAX_TRAFFIC_CLASS;
9901                         /* FW needs one App to configure HW */
9902                         hw->local_dcbx_config.numapps = 1;
9903                         hw->local_dcbx_config.app[0].selector =
9904                                                 I40E_APP_SEL_ETHTYPE;
9905                         hw->local_dcbx_config.app[0].priority = 3;
9906                         hw->local_dcbx_config.app[0].protocolid =
9907                                                 I40E_APP_PROTOID_FCOE;
9908                         ret = i40e_set_dcb_config(hw);
9909                         if (ret) {
9910                                 PMD_INIT_LOG(ERR,
9911                                         "default dcb config fails. err = %d, aq_err = %d.",
9912                                         ret, hw->aq.asq_last_status);
9913                                 return -ENOSYS;
9914                         }
9915                 } else {
9916                         PMD_INIT_LOG(ERR,
9917                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
9918                                 ret, hw->aq.asq_last_status);
9919                         return -ENOTSUP;
9920                 }
9921         } else {
9922                 ret = i40e_aq_start_lldp(hw, NULL);
9923                 if (ret != I40E_SUCCESS)
9924                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9925
9926                 ret = i40e_init_dcb(hw);
9927                 if (!ret) {
9928                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9929                                 PMD_INIT_LOG(ERR,
9930                                         "HW doesn't support DCBX offload.");
9931                                 return -ENOTSUP;
9932                         }
9933                 } else {
9934                         PMD_INIT_LOG(ERR,
9935                                 "DCBX configuration failed, err = %d, aq_err = %d.",
9936                                 ret, hw->aq.asq_last_status);
9937                         return -ENOTSUP;
9938                 }
9939         }
9940         return 0;
9941 }
9942
9943 /*
9944  * i40e_dcb_setup - setup dcb related config
9945  * @dev: device being configured
9946  *
9947  * Returns 0 on success, negative value on failure
9948  */
9949 static int
9950 i40e_dcb_setup(struct rte_eth_dev *dev)
9951 {
9952         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9953         struct i40e_dcbx_config dcb_cfg;
9954         uint8_t tc_map = 0;
9955         int ret = 0;
9956
9957         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9958                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9959                 return -ENOTSUP;
9960         }
9961
9962         if (pf->vf_num != 0)
9963                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9964
9965         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9966         if (ret) {
9967                 PMD_INIT_LOG(ERR, "invalid dcb config");
9968                 return -EINVAL;
9969         }
9970         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9971         if (ret) {
9972                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
9973                 return -ENOSYS;
9974         }
9975
9976         return 0;
9977 }
9978
9979 static int
9980 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
9981                       struct rte_eth_dcb_info *dcb_info)
9982 {
9983         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9984         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9985         struct i40e_vsi *vsi = pf->main_vsi;
9986         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
9987         uint16_t bsf, tc_mapping;
9988         int i, j = 0;
9989
9990         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
9991                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
9992         else
9993                 dcb_info->nb_tcs = 1;
9994         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9995                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
9996         for (i = 0; i < dcb_info->nb_tcs; i++)
9997                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
9998
9999         /* get queue mapping if vmdq is disabled */
10000         if (!pf->nb_cfg_vmdq_vsi) {
10001                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10002                         if (!(vsi->enabled_tc & (1 << i)))
10003                                 continue;
10004                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10005                         dcb_info->tc_queue.tc_rxq[j][i].base =
10006                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10007                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10008                         dcb_info->tc_queue.tc_txq[j][i].base =
10009                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10010                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10011                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10012                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10013                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10014                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10015                 }
10016                 return 0;
10017         }
10018
10019         /* get queue mapping if vmdq is enabled */
10020         do {
10021                 vsi = pf->vmdq[j].vsi;
10022                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10023                         if (!(vsi->enabled_tc & (1 << i)))
10024                                 continue;
10025                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10026                         dcb_info->tc_queue.tc_rxq[j][i].base =
10027                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10028                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10029                         dcb_info->tc_queue.tc_txq[j][i].base =
10030                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10031                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10032                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10033                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10034                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10035                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10036                 }
10037                 j++;
10038         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10039         return 0;
10040 }
10041
10042 static int
10043 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10044 {
10045         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10046         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10047         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10048         uint16_t interval =
10049                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10050         uint16_t msix_intr;
10051
10052         msix_intr = intr_handle->intr_vec[queue_id];
10053         if (msix_intr == I40E_MISC_VEC_ID)
10054                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10055                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10056                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10057                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10058                                (interval <<
10059                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10060         else
10061                 I40E_WRITE_REG(hw,
10062                                I40E_PFINT_DYN_CTLN(msix_intr -
10063                                                    I40E_RX_VEC_START),
10064                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10065                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10066                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10067                                (interval <<
10068                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10069
10070         I40E_WRITE_FLUSH(hw);
10071         rte_intr_enable(&pci_dev->intr_handle);
10072
10073         return 0;
10074 }
10075
10076 static int
10077 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10078 {
10079         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10080         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10081         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10082         uint16_t msix_intr;
10083
10084         msix_intr = intr_handle->intr_vec[queue_id];
10085         if (msix_intr == I40E_MISC_VEC_ID)
10086                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10087         else
10088                 I40E_WRITE_REG(hw,
10089                                I40E_PFINT_DYN_CTLN(msix_intr -
10090                                                    I40E_RX_VEC_START),
10091                                0);
10092         I40E_WRITE_FLUSH(hw);
10093
10094         return 0;
10095 }
10096
10097 static int i40e_get_regs(struct rte_eth_dev *dev,
10098                          struct rte_dev_reg_info *regs)
10099 {
10100         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10101         uint32_t *ptr_data = regs->data;
10102         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10103         const struct i40e_reg_info *reg_info;
10104
10105         if (ptr_data == NULL) {
10106                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10107                 regs->width = sizeof(uint32_t);
10108                 return 0;
10109         }
10110
10111         /* The first few registers have to be read using AQ operations */
10112         reg_idx = 0;
10113         while (i40e_regs_adminq[reg_idx].name) {
10114                 reg_info = &i40e_regs_adminq[reg_idx++];
10115                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10116                         for (arr_idx2 = 0;
10117                                         arr_idx2 <= reg_info->count2;
10118                                         arr_idx2++) {
10119                                 reg_offset = arr_idx * reg_info->stride1 +
10120                                         arr_idx2 * reg_info->stride2;
10121                                 reg_offset += reg_info->base_addr;
10122                                 ptr_data[reg_offset >> 2] =
10123                                         i40e_read_rx_ctl(hw, reg_offset);
10124                         }
10125         }
10126
10127         /* The remaining registers can be read using primitives */
10128         reg_idx = 0;
10129         while (i40e_regs_others[reg_idx].name) {
10130                 reg_info = &i40e_regs_others[reg_idx++];
10131                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10132                         for (arr_idx2 = 0;
10133                                         arr_idx2 <= reg_info->count2;
10134                                         arr_idx2++) {
10135                                 reg_offset = arr_idx * reg_info->stride1 +
10136                                         arr_idx2 * reg_info->stride2;
10137                                 reg_offset += reg_info->base_addr;
10138                                 ptr_data[reg_offset >> 2] =
10139                                         I40E_READ_REG(hw, reg_offset);
10140                         }
10141         }
10142
10143         return 0;
10144 }
10145
10146 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10147 {
10148         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10149
10150         /* Convert word count to byte count */
10151         return hw->nvm.sr_size << 1;
10152 }
10153
10154 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10155                            struct rte_dev_eeprom_info *eeprom)
10156 {
10157         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10158         uint16_t *data = eeprom->data;
10159         uint16_t offset, length, cnt_words;
10160         int ret_code;
10161
10162         offset = eeprom->offset >> 1;
10163         length = eeprom->length >> 1;
10164         cnt_words = length;
10165
10166         if (offset > hw->nvm.sr_size ||
10167                 offset + length > hw->nvm.sr_size) {
10168                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10169                 return -EINVAL;
10170         }
10171
10172         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10173
10174         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10175         if (ret_code != I40E_SUCCESS || cnt_words != length) {
10176                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10177                 return -EIO;
10178         }
10179
10180         return 0;
10181 }
10182
10183 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10184                                       struct ether_addr *mac_addr)
10185 {
10186         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10187
10188         if (!is_valid_assigned_ether_addr(mac_addr)) {
10189                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10190                 return;
10191         }
10192
10193         /* Flags: 0x3 updates port address */
10194         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10195 }
10196
10197 static int
10198 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10199 {
10200         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10201         struct rte_eth_dev_data *dev_data = pf->dev_data;
10202         uint32_t frame_size = mtu + ETHER_HDR_LEN
10203                               + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
10204         int ret = 0;
10205
10206         /* check if mtu is within the allowed range */
10207         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10208                 return -EINVAL;
10209
10210         /* mtu setting is forbidden if port is start */
10211         if (dev_data->dev_started) {
10212                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10213                             dev_data->port_id);
10214                 return -EBUSY;
10215         }
10216
10217         if (frame_size > ETHER_MAX_LEN)
10218                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10219         else
10220                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10221
10222         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10223
10224         return ret;
10225 }
10226
10227 /* Restore ethertype filter */
10228 static void
10229 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10230 {
10231         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10232         struct i40e_ethertype_filter_list
10233                 *ethertype_list = &pf->ethertype.ethertype_list;
10234         struct i40e_ethertype_filter *f;
10235         struct i40e_control_filter_stats stats;
10236         uint16_t flags;
10237
10238         TAILQ_FOREACH(f, ethertype_list, rules) {
10239                 flags = 0;
10240                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10241                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10242                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10243                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10244                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10245
10246                 memset(&stats, 0, sizeof(stats));
10247                 i40e_aq_add_rem_control_packet_filter(hw,
10248                                             f->input.mac_addr.addr_bytes,
10249                                             f->input.ether_type,
10250                                             flags, pf->main_vsi->seid,
10251                                             f->queue, 1, &stats, NULL);
10252         }
10253         PMD_DRV_LOG(INFO, "Ethertype filter:"
10254                     " mac_etype_used = %u, etype_used = %u,"
10255                     " mac_etype_free = %u, etype_free = %u",
10256                     stats.mac_etype_used, stats.etype_used,
10257                     stats.mac_etype_free, stats.etype_free);
10258 }
10259
10260 /* Restore tunnel filter */
10261 static void
10262 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10263 {
10264         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10265         struct i40e_vsi *vsi = pf->main_vsi;
10266         struct i40e_tunnel_filter_list
10267                 *tunnel_list = &pf->tunnel.tunnel_list;
10268         struct i40e_tunnel_filter *f;
10269         struct i40e_aqc_add_remove_cloud_filters_element_data cld_filter;
10270
10271         TAILQ_FOREACH(f, tunnel_list, rules) {
10272                 memset(&cld_filter, 0, sizeof(cld_filter));
10273                 rte_memcpy(&cld_filter, &f->input, sizeof(f->input));
10274                 cld_filter.queue_number = f->queue;
10275                 i40e_aq_add_cloud_filters(hw, vsi->seid, &cld_filter, 1);
10276         }
10277 }
10278
10279 static void
10280 i40e_filter_restore(struct i40e_pf *pf)
10281 {
10282         i40e_ethertype_filter_restore(pf);
10283         i40e_tunnel_filter_restore(pf);
10284         i40e_fdir_filter_restore(pf);
10285 }
10286
10287 static bool
10288 is_device_supported(struct rte_eth_dev *dev, struct eth_driver *drv)
10289 {
10290         if (strcmp(dev->driver->pci_drv.driver.name,
10291                    drv->pci_drv.driver.name))
10292                 return false;
10293
10294         return true;
10295 }
10296
10297 int
10298 rte_pmd_i40e_ping_vfs(uint8_t port, uint16_t vf)
10299 {
10300         struct rte_eth_dev *dev;
10301         struct i40e_pf *pf;
10302
10303         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10304
10305         dev = &rte_eth_devices[port];
10306
10307         if (!is_device_supported(dev, &rte_i40e_pmd))
10308                 return -ENOTSUP;
10309
10310         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10311
10312         if (vf >= pf->vf_num || !pf->vfs) {
10313                 PMD_DRV_LOG(ERR, "Invalid argument.");
10314                 return -EINVAL;
10315         }
10316
10317         i40e_notify_vf_link_status(dev, &pf->vfs[vf]);
10318
10319         return 0;
10320 }
10321
10322 int
10323 rte_pmd_i40e_set_vf_mac_anti_spoof(uint8_t port, uint16_t vf_id, uint8_t on)
10324 {
10325         struct rte_eth_dev *dev;
10326         struct i40e_pf *pf;
10327         struct i40e_vsi *vsi;
10328         struct i40e_hw *hw;
10329         struct i40e_vsi_context ctxt;
10330         int ret;
10331
10332         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10333
10334         dev = &rte_eth_devices[port];
10335
10336         if (!is_device_supported(dev, &rte_i40e_pmd))
10337                 return -ENOTSUP;
10338
10339         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10340
10341         if (vf_id >= pf->vf_num || !pf->vfs) {
10342                 PMD_DRV_LOG(ERR, "Invalid argument.");
10343                 return -EINVAL;
10344         }
10345
10346         vsi = pf->vfs[vf_id].vsi;
10347         if (!vsi) {
10348                 PMD_DRV_LOG(ERR, "Invalid VSI.");
10349                 return -EINVAL;
10350         }
10351
10352         /* Check if it has been already on or off */
10353         if (vsi->info.valid_sections &
10354                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SECURITY_VALID)) {
10355                 if (on) {
10356                         if ((vsi->info.sec_flags &
10357                              I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK) ==
10358                             I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK)
10359                                 return 0; /* already on */
10360                 } else {
10361                         if ((vsi->info.sec_flags &
10362                              I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK) == 0)
10363                                 return 0; /* already off */
10364                 }
10365         }
10366
10367         vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
10368         if (on)
10369                 vsi->info.sec_flags |= I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK;
10370         else
10371                 vsi->info.sec_flags &= ~I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK;
10372
10373         memset(&ctxt, 0, sizeof(ctxt));
10374         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10375         ctxt.seid = vsi->seid;
10376
10377         hw = I40E_VSI_TO_HW(vsi);
10378         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10379         if (ret != I40E_SUCCESS) {
10380                 ret = -ENOTSUP;
10381                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10382         }
10383
10384         return ret;
10385 }
10386
10387 static int
10388 i40e_add_rm_all_vlan_filter(struct i40e_vsi *vsi, uint8_t add)
10389 {
10390         uint32_t j, k;
10391         uint16_t vlan_id;
10392         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10393         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
10394         int ret;
10395
10396         for (j = 0; j < I40E_VFTA_SIZE; j++) {
10397                 if (!vsi->vfta[j])
10398                         continue;
10399
10400                 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
10401                         if (!(vsi->vfta[j] & (1 << k)))
10402                                 continue;
10403
10404                         vlan_id = j * I40E_UINT32_BIT_SIZE + k;
10405                         if (!vlan_id)
10406                                 continue;
10407
10408                         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
10409                         if (add)
10410                                 ret = i40e_aq_add_vlan(hw, vsi->seid,
10411                                                        &vlan_data, 1, NULL);
10412                         else
10413                                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
10414                                                           &vlan_data, 1, NULL);
10415                         if (ret != I40E_SUCCESS) {
10416                                 PMD_DRV_LOG(ERR,
10417                                             "Failed to add/rm vlan filter");
10418                                 return ret;
10419                         }
10420                 }
10421         }
10422
10423         return I40E_SUCCESS;
10424 }
10425
10426 int
10427 rte_pmd_i40e_set_vf_vlan_anti_spoof(uint8_t port, uint16_t vf_id, uint8_t on)
10428 {
10429         struct rte_eth_dev *dev;
10430         struct i40e_pf *pf;
10431         struct i40e_vsi *vsi;
10432         struct i40e_hw *hw;
10433         struct i40e_vsi_context ctxt;
10434         int ret;
10435
10436         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10437
10438         dev = &rte_eth_devices[port];
10439
10440         if (!is_device_supported(dev, &rte_i40e_pmd))
10441                 return -ENOTSUP;
10442
10443         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10444
10445         if (vf_id >= pf->vf_num || !pf->vfs) {
10446                 PMD_DRV_LOG(ERR, "Invalid argument.");
10447                 return -EINVAL;
10448         }
10449
10450         vsi = pf->vfs[vf_id].vsi;
10451         if (!vsi) {
10452                 PMD_DRV_LOG(ERR, "Invalid VSI.");
10453                 return -EINVAL;
10454         }
10455
10456         /* Check if it has been already on or off */
10457         if (vsi->vlan_anti_spoof_on == on)
10458                 return 0; /* already on or off */
10459
10460         vsi->vlan_anti_spoof_on = on;
10461         ret = i40e_add_rm_all_vlan_filter(vsi, on);
10462         if (ret) {
10463                 PMD_DRV_LOG(ERR, "Failed to remove VLAN filters.");
10464                 return -ENOTSUP;
10465         }
10466
10467         vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
10468         if (on)
10469                 vsi->info.sec_flags |= I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK;
10470         else
10471                 vsi->info.sec_flags &= ~I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK;
10472
10473         memset(&ctxt, 0, sizeof(ctxt));
10474         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10475         ctxt.seid = vsi->seid;
10476
10477         hw = I40E_VSI_TO_HW(vsi);
10478         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10479         if (ret != I40E_SUCCESS) {
10480                 ret = -ENOTSUP;
10481                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10482         }
10483
10484         return ret;
10485 }
10486
10487 static int
10488 i40e_vsi_rm_mac_filter(struct i40e_vsi *vsi)
10489 {
10490         struct i40e_mac_filter *f;
10491         struct i40e_macvlan_filter *mv_f;
10492         int i, vlan_num;
10493         enum rte_mac_filter_type filter_type;
10494         int ret = I40E_SUCCESS;
10495         void *temp;
10496
10497         /* remove all the MACs */
10498         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
10499                 vlan_num = vsi->vlan_num;
10500                 filter_type = f->mac_info.filter_type;
10501                 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10502                     filter_type == RTE_MACVLAN_HASH_MATCH) {
10503                         if (vlan_num == 0) {
10504                                 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
10505                                 return I40E_ERR_PARAM;
10506                         }
10507                 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
10508                            filter_type == RTE_MAC_HASH_MATCH)
10509                         vlan_num = 1;
10510
10511                 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
10512                 if (!mv_f) {
10513                         PMD_DRV_LOG(ERR, "failed to allocate memory");
10514                         return I40E_ERR_NO_MEMORY;
10515                 }
10516
10517                 for (i = 0; i < vlan_num; i++) {
10518                         mv_f[i].filter_type = filter_type;
10519                         (void)rte_memcpy(&mv_f[i].macaddr,
10520                                          &f->mac_info.mac_addr,
10521                                          ETH_ADDR_LEN);
10522                 }
10523                 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10524                     filter_type == RTE_MACVLAN_HASH_MATCH) {
10525                         ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
10526                                                          &f->mac_info.mac_addr);
10527                         if (ret != I40E_SUCCESS) {
10528                                 rte_free(mv_f);
10529                                 return ret;
10530                         }
10531                 }
10532
10533                 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
10534                 if (ret != I40E_SUCCESS) {
10535                         rte_free(mv_f);
10536                         return ret;
10537                 }
10538
10539                 rte_free(mv_f);
10540                 ret = I40E_SUCCESS;
10541         }
10542
10543         return ret;
10544 }
10545
10546 static int
10547 i40e_vsi_restore_mac_filter(struct i40e_vsi *vsi)
10548 {
10549         struct i40e_mac_filter *f;
10550         struct i40e_macvlan_filter *mv_f;
10551         int i, vlan_num = 0;
10552         int ret = I40E_SUCCESS;
10553         void *temp;
10554
10555         /* restore all the MACs */
10556         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
10557                 if ((f->mac_info.filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
10558                     (f->mac_info.filter_type == RTE_MACVLAN_HASH_MATCH)) {
10559                         /**
10560                          * If vlan_num is 0, that's the first time to add mac,
10561                          * set mask for vlan_id 0.
10562                          */
10563                         if (vsi->vlan_num == 0) {
10564                                 i40e_set_vlan_filter(vsi, 0, 1);
10565                                 vsi->vlan_num = 1;
10566                         }
10567                         vlan_num = vsi->vlan_num;
10568                 } else if ((f->mac_info.filter_type == RTE_MAC_PERFECT_MATCH) ||
10569                            (f->mac_info.filter_type == RTE_MAC_HASH_MATCH))
10570                         vlan_num = 1;
10571
10572                 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
10573                 if (!mv_f) {
10574                         PMD_DRV_LOG(ERR, "failed to allocate memory");
10575                         return I40E_ERR_NO_MEMORY;
10576                 }
10577
10578                 for (i = 0; i < vlan_num; i++) {
10579                         mv_f[i].filter_type = f->mac_info.filter_type;
10580                         (void)rte_memcpy(&mv_f[i].macaddr,
10581                                          &f->mac_info.mac_addr,
10582                                          ETH_ADDR_LEN);
10583                 }
10584
10585                 if (f->mac_info.filter_type == RTE_MACVLAN_PERFECT_MATCH ||
10586                     f->mac_info.filter_type == RTE_MACVLAN_HASH_MATCH) {
10587                         ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
10588                                                          &f->mac_info.mac_addr);
10589                         if (ret != I40E_SUCCESS) {
10590                                 rte_free(mv_f);
10591                                 return ret;
10592                         }
10593                 }
10594
10595                 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
10596                 if (ret != I40E_SUCCESS) {
10597                         rte_free(mv_f);
10598                         return ret;
10599                 }
10600
10601                 rte_free(mv_f);
10602                 ret = I40E_SUCCESS;
10603         }
10604
10605         return ret;
10606 }
10607
10608 static int
10609 i40e_vsi_set_tx_loopback(struct i40e_vsi *vsi, uint8_t on)
10610 {
10611         struct i40e_vsi_context ctxt;
10612         struct i40e_hw *hw;
10613         int ret;
10614
10615         if (!vsi)
10616                 return -EINVAL;
10617
10618         hw = I40E_VSI_TO_HW(vsi);
10619
10620         /* Use the FW API if FW >= v5.0 */
10621         if (hw->aq.fw_maj_ver < 5) {
10622                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
10623                 return -ENOTSUP;
10624         }
10625
10626         /* Check if it has been already on or off */
10627         if (vsi->info.valid_sections &
10628                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID)) {
10629                 if (on) {
10630                         if ((vsi->info.switch_id &
10631                              I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB) ==
10632                             I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB)
10633                                 return 0; /* already on */
10634                 } else {
10635                         if ((vsi->info.switch_id &
10636                              I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB) == 0)
10637                                 return 0; /* already off */
10638                 }
10639         }
10640
10641         /* remove all the MAC and VLAN first */
10642         ret = i40e_vsi_rm_mac_filter(vsi);
10643         if (ret) {
10644                 PMD_INIT_LOG(ERR, "Failed to remove MAC filters.");
10645                 return ret;
10646         }
10647         if (vsi->vlan_anti_spoof_on) {
10648                 ret = i40e_add_rm_all_vlan_filter(vsi, 0);
10649                 if (ret) {
10650                         PMD_INIT_LOG(ERR, "Failed to remove VLAN filters.");
10651                         return ret;
10652                 }
10653         }
10654
10655         vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
10656         if (on)
10657                 vsi->info.switch_id |= I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB;
10658         else
10659                 vsi->info.switch_id &= ~I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB;
10660
10661         memset(&ctxt, 0, sizeof(ctxt));
10662         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10663         ctxt.seid = vsi->seid;
10664
10665         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10666         if (ret != I40E_SUCCESS) {
10667                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10668                 return ret;
10669         }
10670
10671         /* add all the MAC and VLAN back */
10672         ret = i40e_vsi_restore_mac_filter(vsi);
10673         if (ret)
10674                 return ret;
10675         if (vsi->vlan_anti_spoof_on) {
10676                 ret = i40e_add_rm_all_vlan_filter(vsi, 1);
10677                 if (ret)
10678                         return ret;
10679         }
10680
10681         return ret;
10682 }
10683
10684 int
10685 rte_pmd_i40e_set_tx_loopback(uint8_t port, uint8_t on)
10686 {
10687         struct rte_eth_dev *dev;
10688         struct i40e_pf *pf;
10689         struct i40e_pf_vf *vf;
10690         struct i40e_vsi *vsi;
10691         uint16_t vf_id;
10692         int ret;
10693
10694         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10695
10696         dev = &rte_eth_devices[port];
10697
10698         if (!is_device_supported(dev, &rte_i40e_pmd))
10699                 return -ENOTSUP;
10700
10701         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10702
10703         /* setup PF TX loopback */
10704         vsi = pf->main_vsi;
10705         ret = i40e_vsi_set_tx_loopback(vsi, on);
10706         if (ret)
10707                 return -ENOTSUP;
10708
10709         /* setup TX loopback for all the VFs */
10710         if (!pf->vfs) {
10711                 /* if no VF, do nothing. */
10712                 return 0;
10713         }
10714
10715         for (vf_id = 0; vf_id < pf->vf_num; vf_id++) {
10716                 vf = &pf->vfs[vf_id];
10717                 vsi = vf->vsi;
10718
10719                 ret = i40e_vsi_set_tx_loopback(vsi, on);
10720                 if (ret)
10721                         return -ENOTSUP;
10722         }
10723
10724         return ret;
10725 }
10726
10727 int
10728 rte_pmd_i40e_set_vf_unicast_promisc(uint8_t port, uint16_t vf_id, uint8_t on)
10729 {
10730         struct rte_eth_dev *dev;
10731         struct i40e_pf *pf;
10732         struct i40e_vsi *vsi;
10733         struct i40e_hw *hw;
10734         int ret;
10735
10736         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10737
10738         dev = &rte_eth_devices[port];
10739
10740         if (!is_device_supported(dev, &rte_i40e_pmd))
10741                 return -ENOTSUP;
10742
10743         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10744
10745         if (vf_id >= pf->vf_num || !pf->vfs) {
10746                 PMD_DRV_LOG(ERR, "Invalid argument.");
10747                 return -EINVAL;
10748         }
10749
10750         vsi = pf->vfs[vf_id].vsi;
10751         if (!vsi) {
10752                 PMD_DRV_LOG(ERR, "Invalid VSI.");
10753                 return -EINVAL;
10754         }
10755
10756         hw = I40E_VSI_TO_HW(vsi);
10757
10758         ret = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
10759                                                   on, NULL, true);
10760         if (ret != I40E_SUCCESS) {
10761                 ret = -ENOTSUP;
10762                 PMD_DRV_LOG(ERR, "Failed to set unicast promiscuous mode");
10763         }
10764
10765         return ret;
10766 }
10767
10768 int
10769 rte_pmd_i40e_set_vf_multicast_promisc(uint8_t port, uint16_t vf_id, uint8_t on)
10770 {
10771         struct rte_eth_dev *dev;
10772         struct i40e_pf *pf;
10773         struct i40e_vsi *vsi;
10774         struct i40e_hw *hw;
10775         int ret;
10776
10777         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10778
10779         dev = &rte_eth_devices[port];
10780
10781         if (!is_device_supported(dev, &rte_i40e_pmd))
10782                 return -ENOTSUP;
10783
10784         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10785
10786         if (vf_id >= pf->vf_num || !pf->vfs) {
10787                 PMD_DRV_LOG(ERR, "Invalid argument.");
10788                 return -EINVAL;
10789         }
10790
10791         vsi = pf->vfs[vf_id].vsi;
10792         if (!vsi) {
10793                 PMD_DRV_LOG(ERR, "Invalid VSI.");
10794                 return -EINVAL;
10795         }
10796
10797         hw = I40E_VSI_TO_HW(vsi);
10798
10799         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
10800                                                     on, NULL);
10801         if (ret != I40E_SUCCESS) {
10802                 ret = -ENOTSUP;
10803                 PMD_DRV_LOG(ERR, "Failed to set multicast promiscuous mode");
10804         }
10805
10806         return ret;
10807 }
10808
10809 int
10810 rte_pmd_i40e_set_vf_mac_addr(uint8_t port, uint16_t vf_id,
10811                              struct ether_addr *mac_addr)
10812 {
10813         struct i40e_mac_filter *f;
10814         struct rte_eth_dev *dev;
10815         struct i40e_pf_vf *vf;
10816         struct i40e_vsi *vsi;
10817         struct i40e_pf *pf;
10818         void *temp;
10819
10820         if (i40e_validate_mac_addr((u8 *)mac_addr) != I40E_SUCCESS)
10821                 return -EINVAL;
10822
10823         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10824
10825         dev = &rte_eth_devices[port];
10826
10827         if (!is_device_supported(dev, &rte_i40e_pmd))
10828                 return -ENOTSUP;
10829
10830         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10831
10832         if (vf_id >= pf->vf_num || !pf->vfs)
10833                 return -EINVAL;
10834
10835         vf = &pf->vfs[vf_id];
10836         vsi = vf->vsi;
10837         if (!vsi) {
10838                 PMD_DRV_LOG(ERR, "Invalid VSI.");
10839                 return -EINVAL;
10840         }
10841
10842         ether_addr_copy(mac_addr, &vf->mac_addr);
10843
10844         /* Remove all existing mac */
10845         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
10846                 i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
10847
10848         return 0;
10849 }
10850
10851 /* Set vlan strip on/off for specific VF from host */
10852 int
10853 rte_pmd_i40e_set_vf_vlan_stripq(uint8_t port, uint16_t vf_id, uint8_t on)
10854 {
10855         struct rte_eth_dev *dev;
10856         struct i40e_pf *pf;
10857         struct i40e_vsi *vsi;
10858         int ret;
10859
10860         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10861
10862         dev = &rte_eth_devices[port];
10863
10864         if (!is_device_supported(dev, &rte_i40e_pmd))
10865                 return -ENOTSUP;
10866
10867         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10868
10869         if (vf_id >= pf->vf_num || !pf->vfs) {
10870                 PMD_DRV_LOG(ERR, "Invalid argument.");
10871                 return -EINVAL;
10872         }
10873
10874         vsi = pf->vfs[vf_id].vsi;
10875
10876         if (!vsi)
10877                 return -EINVAL;
10878
10879         ret = i40e_vsi_config_vlan_stripping(vsi, !!on);
10880         if (ret != I40E_SUCCESS) {
10881                 ret = -ENOTSUP;
10882                 PMD_DRV_LOG(ERR, "Failed to set VLAN stripping!");
10883         }
10884
10885         return ret;
10886 }
10887
10888 int rte_pmd_i40e_set_vf_vlan_insert(uint8_t port, uint16_t vf_id,
10889                                     uint16_t vlan_id)
10890 {
10891         struct rte_eth_dev *dev;
10892         struct i40e_pf *pf;
10893         struct i40e_hw *hw;
10894         struct i40e_vsi *vsi;
10895         struct i40e_vsi_context ctxt;
10896         int ret;
10897
10898         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10899
10900         if (vlan_id > ETHER_MAX_VLAN_ID) {
10901                 PMD_DRV_LOG(ERR, "Invalid VLAN ID.");
10902                 return -EINVAL;
10903         }
10904
10905         dev = &rte_eth_devices[port];
10906
10907         if (!is_device_supported(dev, &rte_i40e_pmd))
10908                 return -ENOTSUP;
10909
10910         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10911         hw = I40E_PF_TO_HW(pf);
10912
10913         /**
10914          * return -ENODEV if SRIOV not enabled, VF number not configured
10915          * or no queue assigned.
10916          */
10917         if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
10918             pf->vf_nb_qps == 0)
10919                 return -ENODEV;
10920
10921         if (vf_id >= pf->vf_num || !pf->vfs) {
10922                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
10923                 return -EINVAL;
10924         }
10925
10926         vsi = pf->vfs[vf_id].vsi;
10927         if (!vsi) {
10928                 PMD_DRV_LOG(ERR, "Invalid VSI.");
10929                 return -EINVAL;
10930         }
10931
10932         vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
10933         vsi->info.pvid = vlan_id;
10934         if (vlan_id > 0)
10935                 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID;
10936         else
10937                 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_INSERT_PVID;
10938
10939         memset(&ctxt, 0, sizeof(ctxt));
10940         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
10941         ctxt.seid = vsi->seid;
10942
10943         hw = I40E_VSI_TO_HW(vsi);
10944         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10945         if (ret != I40E_SUCCESS) {
10946                 ret = -ENOTSUP;
10947                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
10948         }
10949
10950         return ret;
10951 }
10952
10953 int rte_pmd_i40e_set_vf_broadcast(uint8_t port, uint16_t vf_id,
10954                                   uint8_t on)
10955 {
10956         struct rte_eth_dev *dev;
10957         struct i40e_pf *pf;
10958         struct i40e_vsi *vsi;
10959         struct i40e_hw *hw;
10960         int ret;
10961
10962         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
10963
10964         if (on > 1) {
10965                 PMD_DRV_LOG(ERR, "on should be 0 or 1.");
10966                 return -EINVAL;
10967         }
10968
10969         dev = &rte_eth_devices[port];
10970
10971         if (!is_device_supported(dev, &rte_i40e_pmd))
10972                 return -ENOTSUP;
10973
10974         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10975         hw = I40E_PF_TO_HW(pf);
10976
10977         if (vf_id >= pf->vf_num || !pf->vfs) {
10978                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
10979                 return -EINVAL;
10980         }
10981
10982         /**
10983          * return -ENODEV if SRIOV not enabled, VF number not configured
10984          * or no queue assigned.
10985          */
10986         if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
10987             pf->vf_nb_qps == 0) {
10988                 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
10989                 return -ENODEV;
10990         }
10991
10992         vsi = pf->vfs[vf_id].vsi;
10993         if (!vsi) {
10994                 PMD_DRV_LOG(ERR, "Invalid VSI.");
10995                 return -EINVAL;
10996         }
10997
10998         hw = I40E_VSI_TO_HW(vsi);
10999
11000         ret = i40e_aq_set_vsi_broadcast(hw, vsi->seid, on, NULL);
11001         if (ret != I40E_SUCCESS) {
11002                 ret = -ENOTSUP;
11003                 PMD_DRV_LOG(ERR, "Failed to set VSI broadcast");
11004         }
11005
11006         return ret;
11007 }
11008
11009 int rte_pmd_i40e_set_vf_vlan_tag(uint8_t port, uint16_t vf_id, uint8_t on)
11010 {
11011         struct rte_eth_dev *dev;
11012         struct i40e_pf *pf;
11013         struct i40e_hw *hw;
11014         struct i40e_vsi *vsi;
11015         struct i40e_vsi_context ctxt;
11016         int ret;
11017
11018         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11019
11020         if (on > 1) {
11021                 PMD_DRV_LOG(ERR, "on should be 0 or 1.");
11022                 return -EINVAL;
11023         }
11024
11025         dev = &rte_eth_devices[port];
11026
11027         if (!is_device_supported(dev, &rte_i40e_pmd))
11028                 return -ENOTSUP;
11029
11030         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11031         hw = I40E_PF_TO_HW(pf);
11032
11033         /**
11034          * return -ENODEV if SRIOV not enabled, VF number not configured
11035          * or no queue assigned.
11036          */
11037         if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11038             pf->vf_nb_qps == 0) {
11039                 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
11040                 return -ENODEV;
11041         }
11042
11043         if (vf_id >= pf->vf_num || !pf->vfs) {
11044                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11045                 return -EINVAL;
11046         }
11047
11048         vsi = pf->vfs[vf_id].vsi;
11049         if (!vsi) {
11050                 PMD_DRV_LOG(ERR, "Invalid VSI.");
11051                 return -EINVAL;
11052         }
11053
11054         vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
11055         if (on) {
11056                 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
11057                 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
11058         } else {
11059                 vsi->info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
11060                 vsi->info.port_vlan_flags &= ~I40E_AQ_VSI_PVLAN_MODE_TAGGED;
11061         }
11062
11063         memset(&ctxt, 0, sizeof(ctxt));
11064         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
11065         ctxt.seid = vsi->seid;
11066
11067         hw = I40E_VSI_TO_HW(vsi);
11068         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11069         if (ret != I40E_SUCCESS) {
11070                 ret = -ENOTSUP;
11071                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
11072         }
11073
11074         return ret;
11075 }
11076
11077 int rte_pmd_i40e_set_vf_vlan_filter(uint8_t port, uint16_t vlan_id,
11078                                     uint64_t vf_mask, uint8_t on)
11079 {
11080         struct rte_eth_dev *dev;
11081         struct i40e_pf *pf;
11082         struct i40e_hw *hw;
11083         uint16_t vf_idx;
11084         int ret = I40E_SUCCESS;
11085
11086         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11087
11088         dev = &rte_eth_devices[port];
11089
11090         if (!is_device_supported(dev, &rte_i40e_pmd))
11091                 return -ENOTSUP;
11092
11093         if (vlan_id > ETHER_MAX_VLAN_ID) {
11094                 PMD_DRV_LOG(ERR, "Invalid VLAN ID.");
11095                 return -EINVAL;
11096         }
11097
11098         if (vf_mask == 0) {
11099                 PMD_DRV_LOG(ERR, "No VF.");
11100                 return -EINVAL;
11101         }
11102
11103         if (on > 1) {
11104                 PMD_DRV_LOG(ERR, "on is should be 0 or 1.");
11105                 return -EINVAL;
11106         }
11107
11108         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11109         hw = I40E_PF_TO_HW(pf);
11110
11111         /**
11112          * return -ENODEV if SRIOV not enabled, VF number not configured
11113          * or no queue assigned.
11114          */
11115         if (!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 ||
11116             pf->vf_nb_qps == 0) {
11117                 PMD_DRV_LOG(ERR, "SRIOV is not enabled or no queue.");
11118                 return -ENODEV;
11119         }
11120
11121         for (vf_idx = 0; vf_idx < 64 && ret == I40E_SUCCESS; vf_idx++) {
11122                 if (vf_mask & ((uint64_t)(1ULL << vf_idx))) {
11123                         if (on)
11124                                 ret = i40e_vsi_add_vlan(pf->vfs[vf_idx].vsi,
11125                                                         vlan_id);
11126                         else
11127                                 ret = i40e_vsi_delete_vlan(pf->vfs[vf_idx].vsi,
11128                                                            vlan_id);
11129                 }
11130         }
11131
11132         if (ret != I40E_SUCCESS) {
11133                 ret = -ENOTSUP;
11134                 PMD_DRV_LOG(ERR, "Failed to set VF VLAN filter, on = %d", on);
11135         }
11136
11137         return ret;
11138 }
11139
11140 int
11141 rte_pmd_i40e_get_vf_stats(uint8_t port,
11142                           uint16_t vf_id,
11143                           struct rte_eth_stats *stats)
11144 {
11145         struct rte_eth_dev *dev;
11146         struct i40e_pf *pf;
11147         struct i40e_vsi *vsi;
11148
11149         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11150
11151         dev = &rte_eth_devices[port];
11152
11153         if (!is_device_supported(dev, &rte_i40e_pmd))
11154                 return -ENOTSUP;
11155
11156         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11157
11158         if (vf_id >= pf->vf_num || !pf->vfs) {
11159                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11160                 return -EINVAL;
11161         }
11162
11163         vsi = pf->vfs[vf_id].vsi;
11164         if (!vsi) {
11165                 PMD_DRV_LOG(ERR, "Invalid VSI.");
11166                 return -EINVAL;
11167         }
11168
11169         i40e_update_vsi_stats(vsi);
11170
11171         stats->ipackets = vsi->eth_stats.rx_unicast +
11172                         vsi->eth_stats.rx_multicast +
11173                         vsi->eth_stats.rx_broadcast;
11174         stats->opackets = vsi->eth_stats.tx_unicast +
11175                         vsi->eth_stats.tx_multicast +
11176                         vsi->eth_stats.tx_broadcast;
11177         stats->ibytes   = vsi->eth_stats.rx_bytes;
11178         stats->obytes   = vsi->eth_stats.tx_bytes;
11179         stats->ierrors  = vsi->eth_stats.rx_discards;
11180         stats->oerrors  = vsi->eth_stats.tx_errors + vsi->eth_stats.tx_discards;
11181
11182         return 0;
11183 }
11184
11185 int
11186 rte_pmd_i40e_reset_vf_stats(uint8_t port,
11187                             uint16_t vf_id)
11188 {
11189         struct rte_eth_dev *dev;
11190         struct i40e_pf *pf;
11191         struct i40e_vsi *vsi;
11192
11193         RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV);
11194
11195         dev = &rte_eth_devices[port];
11196
11197         if (!is_device_supported(dev, &rte_i40e_pmd))
11198                 return -ENOTSUP;
11199
11200         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11201
11202         if (vf_id >= pf->vf_num || !pf->vfs) {
11203                 PMD_DRV_LOG(ERR, "Invalid VF ID.");
11204                 return -EINVAL;
11205         }
11206
11207         vsi = pf->vfs[vf_id].vsi;
11208         if (!vsi) {
11209                 PMD_DRV_LOG(ERR, "Invalid VSI.");
11210                 return -EINVAL;
11211         }
11212
11213         vsi->offset_loaded = false;
11214         i40e_update_vsi_stats(vsi);
11215
11216         return 0;
11217 }