1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
14 #include <rte_common.h>
16 #include <rte_string_fns.h>
18 #include <rte_bus_pci.h>
19 #include <rte_ether.h>
20 #include <ethdev_driver.h>
21 #include <ethdev_pci.h>
22 #include <rte_memzone.h>
23 #include <rte_malloc.h>
24 #include <rte_memcpy.h>
25 #include <rte_alarm.h>
27 #include <rte_tailq.h>
28 #include <rte_hash_crc.h>
29 #include <rte_bitmap.h>
30 #include <rte_os_shim.h>
32 #include "i40e_logs.h"
33 #include "base/i40e_prototype.h"
34 #include "base/i40e_adminq_cmd.h"
35 #include "base/i40e_type.h"
36 #include "base/i40e_register.h"
37 #include "base/i40e_dcb.h"
38 #include "i40e_ethdev.h"
39 #include "i40e_rxtx.h"
41 #include "i40e_regs.h"
42 #include "rte_pmd_i40e.h"
43 #include "i40e_hash.h"
45 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
46 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
47 #define ETH_I40E_SUPPORT_MULTI_DRIVER "support-multi-driver"
48 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG "queue-num-per-vf"
49 #define ETH_I40E_VF_MSG_CFG "vf_msg_cfg"
51 #define I40E_CLEAR_PXE_WAIT_MS 200
52 #define I40E_VSI_TSR_QINQ_STRIP 0x4010
53 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
55 /* Maximun number of capability elements */
56 #define I40E_MAX_CAP_ELE_NUM 128
58 /* Wait count and interval */
59 #define I40E_CHK_Q_ENA_COUNT 1000
60 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
62 /* Maximun number of VSI */
63 #define I40E_MAX_NUM_VSIS (384UL)
65 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
67 /* Flow control default timer */
68 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
70 /* Flow control enable fwd bit */
71 #define I40E_PRTMAC_FWD_CTRL 0x00000001
73 /* Receive Packet Buffer size */
74 #define I40E_RXPBSIZE (968 * 1024)
77 #define I40E_KILOSHIFT 10
79 /* Flow control default high water */
80 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
82 /* Flow control default low water */
83 #define I40E_DEFAULT_LOW_WATER (0xF2000 >> I40E_KILOSHIFT)
85 /* Receive Average Packet Size in Byte*/
86 #define I40E_PACKET_AVERAGE_SIZE 128
88 /* Mask of PF interrupt causes */
89 #define I40E_PFINT_ICR0_ENA_MASK ( \
90 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
91 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
92 I40E_PFINT_ICR0_ENA_GRST_MASK | \
93 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
94 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
95 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
96 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
97 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
98 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
100 #define I40E_FLOW_TYPES ( \
101 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
102 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
103 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
104 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
105 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
106 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
107 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
108 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
109 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
110 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
111 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
113 /* Additional timesync values. */
114 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
115 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
116 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
117 #define I40E_PRTTSYN_TSYNENA 0x80000000
118 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
119 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
122 * Below are values for writing un-exposed registers suggested
125 /* Destination MAC address */
126 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
127 /* Source MAC address */
128 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
129 /* Outer (S-Tag) VLAN tag in the outer L2 header */
130 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
131 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
132 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
133 /* Single VLAN tag in the inner L2 header */
134 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
135 /* Source IPv4 address */
136 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
137 /* Destination IPv4 address */
138 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
139 /* Source IPv4 address for X722 */
140 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
141 /* Destination IPv4 address for X722 */
142 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
143 /* IPv4 Protocol for X722 */
144 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
145 /* IPv4 Time to Live for X722 */
146 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
147 /* IPv4 Type of Service (TOS) */
148 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
150 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
151 /* IPv4 Time to Live */
152 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
153 /* Source IPv6 address */
154 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
155 /* Destination IPv6 address */
156 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
157 /* IPv6 Traffic Class (TC) */
158 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
159 /* IPv6 Next Header */
160 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
162 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
164 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
165 /* Destination L4 port */
166 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
167 /* SCTP verification tag */
168 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
169 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
170 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
171 /* Source port of tunneling UDP */
172 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
173 /* Destination port of tunneling UDP */
174 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
175 /* UDP Tunneling ID, NVGRE/GRE key */
176 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
177 /* Last ether type */
178 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
179 /* Tunneling outer destination IPv4 address */
180 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
181 /* Tunneling outer destination IPv6 address */
182 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
183 /* 1st word of flex payload */
184 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
185 /* 2nd word of flex payload */
186 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
187 /* 3rd word of flex payload */
188 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
189 /* 4th word of flex payload */
190 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
191 /* 5th word of flex payload */
192 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
193 /* 6th word of flex payload */
194 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
195 /* 7th word of flex payload */
196 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
197 /* 8th word of flex payload */
198 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
199 /* all 8 words flex payload */
200 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
201 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
203 #define I40E_TRANSLATE_INSET 0
204 #define I40E_TRANSLATE_REG 1
206 #define I40E_INSET_IPV4_TOS_MASK 0x0000FF00UL
207 #define I40E_INSET_IPV4_TTL_MASK 0x000000FFUL
208 #define I40E_INSET_IPV4_PROTO_MASK 0x0000FF00UL
209 #define I40E_INSET_IPV6_TC_MASK 0x0000F00FUL
210 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x0000FF00UL
211 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000000FFUL
213 /* PCI offset for querying capability */
214 #define PCI_DEV_CAP_REG 0xA4
215 /* PCI offset for enabling/disabling Extended Tag */
216 #define PCI_DEV_CTRL_REG 0xA8
217 /* Bit mask of Extended Tag capability */
218 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
219 /* Bit shift of Extended Tag enable/disable */
220 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
221 /* Bit mask of Extended Tag enable/disable */
222 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
224 #define I40E_GLQF_PIT_IPV4_START 2
225 #define I40E_GLQF_PIT_IPV4_COUNT 2
226 #define I40E_GLQF_PIT_IPV6_START 4
227 #define I40E_GLQF_PIT_IPV6_COUNT 2
229 #define I40E_GLQF_PIT_SOURCE_OFF_GET(a) \
230 (((a) & I40E_GLQF_PIT_SOURCE_OFF_MASK) >> \
231 I40E_GLQF_PIT_SOURCE_OFF_SHIFT)
233 #define I40E_GLQF_PIT_DEST_OFF_GET(a) \
234 (((a) & I40E_GLQF_PIT_DEST_OFF_MASK) >> \
235 I40E_GLQF_PIT_DEST_OFF_SHIFT)
237 #define I40E_GLQF_PIT_FSIZE_GET(a) (((a) & I40E_GLQF_PIT_FSIZE_MASK) >> \
238 I40E_GLQF_PIT_FSIZE_SHIFT)
240 #define I40E_GLQF_PIT_BUILD(off, mask) (((off) << 16) | (mask))
241 #define I40E_FDIR_FIELD_OFFSET(a) ((a) >> 1)
243 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
244 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
245 static int i40e_dev_configure(struct rte_eth_dev *dev);
246 static int i40e_dev_start(struct rte_eth_dev *dev);
247 static int i40e_dev_stop(struct rte_eth_dev *dev);
248 static int i40e_dev_close(struct rte_eth_dev *dev);
249 static int i40e_dev_reset(struct rte_eth_dev *dev);
250 static int i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
251 static int i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
252 static int i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
253 static int i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
254 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
255 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
256 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
257 struct rte_eth_stats *stats);
258 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
259 struct rte_eth_xstat *xstats, unsigned n);
260 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
261 struct rte_eth_xstat_name *xstats_names,
263 static int i40e_dev_stats_reset(struct rte_eth_dev *dev);
264 static int i40e_fw_version_get(struct rte_eth_dev *dev,
265 char *fw_version, size_t fw_size);
266 static int i40e_dev_info_get(struct rte_eth_dev *dev,
267 struct rte_eth_dev_info *dev_info);
268 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
271 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
272 enum rte_vlan_type vlan_type,
274 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
275 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
278 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
279 static int i40e_dev_led_on(struct rte_eth_dev *dev);
280 static int i40e_dev_led_off(struct rte_eth_dev *dev);
281 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
282 struct rte_eth_fc_conf *fc_conf);
283 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
284 struct rte_eth_fc_conf *fc_conf);
285 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
286 struct rte_eth_pfc_conf *pfc_conf);
287 static int i40e_macaddr_add(struct rte_eth_dev *dev,
288 struct rte_ether_addr *mac_addr,
291 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
292 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
293 struct rte_eth_rss_reta_entry64 *reta_conf,
295 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
296 struct rte_eth_rss_reta_entry64 *reta_conf,
299 static int i40e_get_cap(struct i40e_hw *hw);
300 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
301 static int i40e_pf_setup(struct i40e_pf *pf);
302 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
303 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
304 static int i40e_dcb_setup(struct rte_eth_dev *dev);
305 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
306 bool offset_loaded, uint64_t *offset, uint64_t *stat);
307 static void i40e_stat_update_48(struct i40e_hw *hw,
313 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
314 static void i40e_dev_interrupt_handler(void *param);
315 static void i40e_dev_alarm_handler(void *param);
316 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
317 uint32_t base, uint32_t num);
318 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
319 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
321 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
323 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
324 static int i40e_veb_release(struct i40e_veb *veb);
325 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
326 struct i40e_vsi *vsi);
327 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
328 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
329 struct i40e_macvlan_filter *mv_f,
332 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
333 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
334 struct rte_eth_rss_conf *rss_conf);
335 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
336 struct rte_eth_rss_conf *rss_conf);
337 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
338 struct rte_eth_udp_tunnel *udp_tunnel);
339 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
340 struct rte_eth_udp_tunnel *udp_tunnel);
341 static void i40e_filter_input_set_init(struct i40e_pf *pf);
342 static int i40e_dev_flow_ops_get(struct rte_eth_dev *dev,
343 const struct rte_flow_ops **ops);
344 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
345 struct rte_eth_dcb_info *dcb_info);
346 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
347 static void i40e_configure_registers(struct i40e_hw *hw);
348 static void i40e_hw_init(struct rte_eth_dev *dev);
349 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
351 static int i40e_timesync_enable(struct rte_eth_dev *dev);
352 static int i40e_timesync_disable(struct rte_eth_dev *dev);
353 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
354 struct timespec *timestamp,
356 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
357 struct timespec *timestamp);
358 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
360 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
362 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
363 struct timespec *timestamp);
364 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
365 const struct timespec *timestamp);
367 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
369 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
372 static int i40e_get_regs(struct rte_eth_dev *dev,
373 struct rte_dev_reg_info *regs);
375 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
377 static int i40e_get_eeprom(struct rte_eth_dev *dev,
378 struct rte_dev_eeprom_info *eeprom);
380 static int i40e_get_module_info(struct rte_eth_dev *dev,
381 struct rte_eth_dev_module_info *modinfo);
382 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
383 struct rte_dev_eeprom_info *info);
385 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
386 struct rte_ether_addr *mac_addr);
388 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
390 static int i40e_ethertype_filter_convert(
391 const struct rte_eth_ethertype_filter *input,
392 struct i40e_ethertype_filter *filter);
393 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
394 struct i40e_ethertype_filter *filter);
396 static int i40e_tunnel_filter_convert(
397 struct i40e_aqc_cloud_filters_element_bb *cld_filter,
398 struct i40e_tunnel_filter *tunnel_filter);
399 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
400 struct i40e_tunnel_filter *tunnel_filter);
401 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
403 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
404 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
405 static void i40e_filter_restore(struct i40e_pf *pf);
406 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
408 static const char *const valid_keys[] = {
409 ETH_I40E_FLOATING_VEB_ARG,
410 ETH_I40E_FLOATING_VEB_LIST_ARG,
411 ETH_I40E_SUPPORT_MULTI_DRIVER,
412 ETH_I40E_QUEUE_NUM_PER_VF_ARG,
416 static const struct rte_pci_id pci_id_i40e_map[] = {
417 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
418 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
419 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
420 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
421 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
422 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
423 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
424 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
425 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
426 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
427 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
428 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
429 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
430 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
431 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
432 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
435 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
436 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
437 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X710_N3000) },
438 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_XXV710_N3000) },
439 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_BC) },
440 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_5G_BASE_T_BC) },
441 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_B) },
442 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_SFP) },
443 { .vendor_id = 0, /* sentinel */ },
446 static const struct eth_dev_ops i40e_eth_dev_ops = {
447 .dev_configure = i40e_dev_configure,
448 .dev_start = i40e_dev_start,
449 .dev_stop = i40e_dev_stop,
450 .dev_close = i40e_dev_close,
451 .dev_reset = i40e_dev_reset,
452 .promiscuous_enable = i40e_dev_promiscuous_enable,
453 .promiscuous_disable = i40e_dev_promiscuous_disable,
454 .allmulticast_enable = i40e_dev_allmulticast_enable,
455 .allmulticast_disable = i40e_dev_allmulticast_disable,
456 .dev_set_link_up = i40e_dev_set_link_up,
457 .dev_set_link_down = i40e_dev_set_link_down,
458 .link_update = i40e_dev_link_update,
459 .stats_get = i40e_dev_stats_get,
460 .xstats_get = i40e_dev_xstats_get,
461 .xstats_get_names = i40e_dev_xstats_get_names,
462 .stats_reset = i40e_dev_stats_reset,
463 .xstats_reset = i40e_dev_stats_reset,
464 .fw_version_get = i40e_fw_version_get,
465 .dev_infos_get = i40e_dev_info_get,
466 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
467 .vlan_filter_set = i40e_vlan_filter_set,
468 .vlan_tpid_set = i40e_vlan_tpid_set,
469 .vlan_offload_set = i40e_vlan_offload_set,
470 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
471 .vlan_pvid_set = i40e_vlan_pvid_set,
472 .rx_queue_start = i40e_dev_rx_queue_start,
473 .rx_queue_stop = i40e_dev_rx_queue_stop,
474 .tx_queue_start = i40e_dev_tx_queue_start,
475 .tx_queue_stop = i40e_dev_tx_queue_stop,
476 .rx_queue_setup = i40e_dev_rx_queue_setup,
477 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
478 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
479 .rx_queue_release = i40e_dev_rx_queue_release,
480 .tx_queue_setup = i40e_dev_tx_queue_setup,
481 .tx_queue_release = i40e_dev_tx_queue_release,
482 .dev_led_on = i40e_dev_led_on,
483 .dev_led_off = i40e_dev_led_off,
484 .flow_ctrl_get = i40e_flow_ctrl_get,
485 .flow_ctrl_set = i40e_flow_ctrl_set,
486 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
487 .mac_addr_add = i40e_macaddr_add,
488 .mac_addr_remove = i40e_macaddr_remove,
489 .reta_update = i40e_dev_rss_reta_update,
490 .reta_query = i40e_dev_rss_reta_query,
491 .rss_hash_update = i40e_dev_rss_hash_update,
492 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
493 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
494 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
495 .flow_ops_get = i40e_dev_flow_ops_get,
496 .rxq_info_get = i40e_rxq_info_get,
497 .txq_info_get = i40e_txq_info_get,
498 .rx_burst_mode_get = i40e_rx_burst_mode_get,
499 .tx_burst_mode_get = i40e_tx_burst_mode_get,
500 .timesync_enable = i40e_timesync_enable,
501 .timesync_disable = i40e_timesync_disable,
502 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
503 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
504 .get_dcb_info = i40e_dev_get_dcb_info,
505 .timesync_adjust_time = i40e_timesync_adjust_time,
506 .timesync_read_time = i40e_timesync_read_time,
507 .timesync_write_time = i40e_timesync_write_time,
508 .get_reg = i40e_get_regs,
509 .get_eeprom_length = i40e_get_eeprom_length,
510 .get_eeprom = i40e_get_eeprom,
511 .get_module_info = i40e_get_module_info,
512 .get_module_eeprom = i40e_get_module_eeprom,
513 .mac_addr_set = i40e_set_default_mac_addr,
514 .mtu_set = i40e_dev_mtu_set,
515 .tm_ops_get = i40e_tm_ops_get,
516 .tx_done_cleanup = i40e_tx_done_cleanup,
517 .get_monitor_addr = i40e_get_monitor_addr,
520 /* store statistics names and its offset in stats structure */
521 struct rte_i40e_xstats_name_off {
522 char name[RTE_ETH_XSTATS_NAME_SIZE];
526 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
527 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
528 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
529 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
530 {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
531 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
532 rx_unknown_protocol)},
533 {"rx_size_error_packets", offsetof(struct i40e_pf, rx_err1) -
534 offsetof(struct i40e_pf, stats)},
535 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
536 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
537 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
538 {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
541 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
542 sizeof(rte_i40e_stats_strings[0]))
544 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
545 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
546 tx_dropped_link_down)},
547 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
548 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
550 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
551 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
553 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
555 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
557 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
558 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
559 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
560 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
561 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
562 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
564 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
566 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
568 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
570 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
572 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
574 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
576 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
578 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
579 mac_short_packet_dropped)},
580 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
582 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
583 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
584 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
586 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
588 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
590 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
592 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
594 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
596 {"rx_flow_director_atr_match_packets",
597 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
598 {"rx_flow_director_sb_match_packets",
599 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
600 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
602 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
604 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
606 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
610 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
611 sizeof(rte_i40e_hw_port_strings[0]))
613 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
614 {"xon_packets", offsetof(struct i40e_hw_port_stats,
616 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
620 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
621 sizeof(rte_i40e_rxq_prio_strings[0]))
623 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
624 {"xon_packets", offsetof(struct i40e_hw_port_stats,
626 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
628 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
629 priority_xon_2_xoff)},
632 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
633 sizeof(rte_i40e_txq_prio_strings[0]))
636 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
637 struct rte_pci_device *pci_dev)
639 char name[RTE_ETH_NAME_MAX_LEN];
640 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
643 if (pci_dev->device.devargs) {
644 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
650 if (eth_da.nb_representor_ports > 0 &&
651 eth_da.type != RTE_ETH_REPRESENTOR_VF) {
652 PMD_DRV_LOG(ERR, "unsupported representor type: %s\n",
653 pci_dev->device.devargs->args);
657 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
658 sizeof(struct i40e_adapter),
659 eth_dev_pci_specific_init, pci_dev,
660 eth_i40e_dev_init, NULL);
662 if (retval || eth_da.nb_representor_ports < 1)
665 /* probe VF representor ports */
666 struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
667 pci_dev->device.name);
669 if (pf_ethdev == NULL)
672 for (i = 0; i < eth_da.nb_representor_ports; i++) {
673 struct i40e_vf_representor representor = {
674 .vf_id = eth_da.representor_ports[i],
675 .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
676 pf_ethdev->data->dev_private)->switch_domain_id,
677 .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
678 pf_ethdev->data->dev_private)
681 /* representor port net_bdf_port */
682 snprintf(name, sizeof(name), "net_%s_representor_%d",
683 pci_dev->device.name, eth_da.representor_ports[i]);
685 retval = rte_eth_dev_create(&pci_dev->device, name,
686 sizeof(struct i40e_vf_representor), NULL, NULL,
687 i40e_vf_representor_init, &representor);
690 PMD_DRV_LOG(ERR, "failed to create i40e vf "
691 "representor %s.", name);
697 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
699 struct rte_eth_dev *ethdev;
701 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
705 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
706 return rte_eth_dev_pci_generic_remove(pci_dev,
707 i40e_vf_representor_uninit);
709 return rte_eth_dev_pci_generic_remove(pci_dev,
710 eth_i40e_dev_uninit);
713 static struct rte_pci_driver rte_i40e_pmd = {
714 .id_table = pci_id_i40e_map,
715 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
716 .probe = eth_i40e_pci_probe,
717 .remove = eth_i40e_pci_remove,
721 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
724 uint32_t ori_reg_val;
725 struct rte_eth_dev_data *dev_data =
726 ((struct i40e_adapter *)hw->back)->pf.dev_data;
727 struct rte_eth_dev *dev = &rte_eth_devices[dev_data->port_id];
729 ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
730 i40e_write_rx_ctl(hw, reg_addr, reg_val);
731 if (ori_reg_val != reg_val)
733 "i40e device %s changed global register [0x%08x]."
734 " original: 0x%08x, new: 0x%08x",
735 dev->device->name, reg_addr, ori_reg_val, reg_val);
738 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
739 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
740 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
742 #ifndef I40E_GLQF_ORT
743 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
745 #ifndef I40E_GLQF_PIT
746 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
748 #ifndef I40E_GLQF_L3_MAP
749 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
752 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
755 * Initialize registers for parsing packet type of QinQ
756 * This should be removed from code once proper
757 * configuration API is added to avoid configuration conflicts
758 * between ports of the same device.
760 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
761 I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
764 static inline void i40e_config_automask(struct i40e_pf *pf)
766 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
769 /* INTENA flag is not auto-cleared for interrupt */
770 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
771 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
772 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
774 /* If support multi-driver, PF will use INT0. */
775 if (!pf->support_multi_driver)
776 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
778 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
781 static inline void i40e_clear_automask(struct i40e_pf *pf)
783 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
786 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
787 val &= ~(I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
788 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK);
790 if (!pf->support_multi_driver)
791 val &= ~I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
793 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
796 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
799 * Add a ethertype filter to drop all flow control frames transmitted
803 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
805 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
806 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
807 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
808 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
811 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
812 I40E_FLOW_CONTROL_ETHERTYPE, flags,
813 pf->main_vsi_seid, 0,
817 "Failed to add filter to drop flow control frames from VSIs.");
821 floating_veb_list_handler(__rte_unused const char *key,
822 const char *floating_veb_value,
826 unsigned int count = 0;
829 bool *vf_floating_veb = opaque;
831 while (isblank(*floating_veb_value))
832 floating_veb_value++;
834 /* Reset floating VEB configuration for VFs */
835 for (idx = 0; idx < I40E_MAX_VF; idx++)
836 vf_floating_veb[idx] = false;
840 while (isblank(*floating_veb_value))
841 floating_veb_value++;
842 if (*floating_veb_value == '\0')
845 idx = strtoul(floating_veb_value, &end, 10);
846 if (errno || end == NULL)
850 while (isblank(*end))
854 } else if ((*end == ';') || (*end == '\0')) {
856 if (min == I40E_MAX_VF)
858 if (max >= I40E_MAX_VF)
859 max = I40E_MAX_VF - 1;
860 for (idx = min; idx <= max; idx++) {
861 vf_floating_veb[idx] = true;
868 floating_veb_value = end + 1;
869 } while (*end != '\0');
878 config_vf_floating_veb(struct rte_devargs *devargs,
879 uint16_t floating_veb,
880 bool *vf_floating_veb)
882 struct rte_kvargs *kvlist;
884 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
888 /* All the VFs attach to the floating VEB by default
889 * when the floating VEB is enabled.
891 for (i = 0; i < I40E_MAX_VF; i++)
892 vf_floating_veb[i] = true;
897 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
901 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
902 rte_kvargs_free(kvlist);
905 /* When the floating_veb_list parameter exists, all the VFs
906 * will attach to the legacy VEB firstly, then configure VFs
907 * to the floating VEB according to the floating_veb_list.
909 if (rte_kvargs_process(kvlist, floating_veb_list,
910 floating_veb_list_handler,
911 vf_floating_veb) < 0) {
912 rte_kvargs_free(kvlist);
915 rte_kvargs_free(kvlist);
919 i40e_check_floating_handler(__rte_unused const char *key,
921 __rte_unused void *opaque)
923 if (strcmp(value, "1"))
930 is_floating_veb_supported(struct rte_devargs *devargs)
932 struct rte_kvargs *kvlist;
933 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
938 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
942 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
943 rte_kvargs_free(kvlist);
946 /* Floating VEB is enabled when there's key-value:
947 * enable_floating_veb=1
949 if (rte_kvargs_process(kvlist, floating_veb_key,
950 i40e_check_floating_handler, NULL) < 0) {
951 rte_kvargs_free(kvlist);
954 rte_kvargs_free(kvlist);
960 config_floating_veb(struct rte_eth_dev *dev)
962 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
963 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
964 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
966 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
968 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
970 is_floating_veb_supported(pci_dev->device.devargs);
971 config_vf_floating_veb(pci_dev->device.devargs,
973 pf->floating_veb_list);
975 pf->floating_veb = false;
979 #define I40E_L2_TAGS_S_TAG_SHIFT 1
980 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
983 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
985 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
986 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
987 char ethertype_hash_name[RTE_HASH_NAMESIZE];
990 struct rte_hash_parameters ethertype_hash_params = {
991 .name = ethertype_hash_name,
992 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
993 .key_len = sizeof(struct i40e_ethertype_filter_input),
994 .hash_func = rte_hash_crc,
995 .hash_func_init_val = 0,
996 .socket_id = rte_socket_id(),
999 /* Initialize ethertype filter rule list and hash */
1000 TAILQ_INIT(ðertype_rule->ethertype_list);
1001 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
1002 "ethertype_%s", dev->device->name);
1003 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
1004 if (!ethertype_rule->hash_table) {
1005 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
1008 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
1009 sizeof(struct i40e_ethertype_filter *) *
1010 I40E_MAX_ETHERTYPE_FILTER_NUM,
1012 if (!ethertype_rule->hash_map) {
1014 "Failed to allocate memory for ethertype hash map!");
1016 goto err_ethertype_hash_map_alloc;
1021 err_ethertype_hash_map_alloc:
1022 rte_hash_free(ethertype_rule->hash_table);
1028 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
1030 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1031 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
1032 char tunnel_hash_name[RTE_HASH_NAMESIZE];
1035 struct rte_hash_parameters tunnel_hash_params = {
1036 .name = tunnel_hash_name,
1037 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1038 .key_len = sizeof(struct i40e_tunnel_filter_input),
1039 .hash_func = rte_hash_crc,
1040 .hash_func_init_val = 0,
1041 .socket_id = rte_socket_id(),
1044 /* Initialize tunnel filter rule list and hash */
1045 TAILQ_INIT(&tunnel_rule->tunnel_list);
1046 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1047 "tunnel_%s", dev->device->name);
1048 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1049 if (!tunnel_rule->hash_table) {
1050 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1053 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1054 sizeof(struct i40e_tunnel_filter *) *
1055 I40E_MAX_TUNNEL_FILTER_NUM,
1057 if (!tunnel_rule->hash_map) {
1059 "Failed to allocate memory for tunnel hash map!");
1061 goto err_tunnel_hash_map_alloc;
1066 err_tunnel_hash_map_alloc:
1067 rte_hash_free(tunnel_rule->hash_table);
1073 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1075 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1076 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1077 struct i40e_fdir_info *fdir_info = &pf->fdir;
1078 char fdir_hash_name[RTE_HASH_NAMESIZE];
1079 uint32_t alloc = hw->func_caps.fd_filters_guaranteed;
1080 uint32_t best = hw->func_caps.fd_filters_best_effort;
1081 enum i40e_filter_pctype pctype;
1082 struct rte_bitmap *bmp = NULL;
1088 struct rte_hash_parameters fdir_hash_params = {
1089 .name = fdir_hash_name,
1090 .entries = I40E_MAX_FDIR_FILTER_NUM,
1091 .key_len = sizeof(struct i40e_fdir_input),
1092 .hash_func = rte_hash_crc,
1093 .hash_func_init_val = 0,
1094 .socket_id = rte_socket_id(),
1097 /* Initialize flow director filter rule list and hash */
1098 TAILQ_INIT(&fdir_info->fdir_list);
1099 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1100 "fdir_%s", dev->device->name);
1101 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1102 if (!fdir_info->hash_table) {
1103 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1107 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1108 sizeof(struct i40e_fdir_filter *) *
1109 I40E_MAX_FDIR_FILTER_NUM,
1111 if (!fdir_info->hash_map) {
1113 "Failed to allocate memory for fdir hash map!");
1115 goto err_fdir_hash_map_alloc;
1118 fdir_info->fdir_filter_array = rte_zmalloc("fdir_filter",
1119 sizeof(struct i40e_fdir_filter) *
1120 I40E_MAX_FDIR_FILTER_NUM,
1123 if (!fdir_info->fdir_filter_array) {
1125 "Failed to allocate memory for fdir filter array!");
1127 goto err_fdir_filter_array_alloc;
1130 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
1131 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++)
1132 pf->fdir.flow_count[pctype] = 0;
1134 fdir_info->fdir_space_size = alloc + best;
1135 fdir_info->fdir_actual_cnt = 0;
1136 fdir_info->fdir_guarantee_total_space = alloc;
1137 fdir_info->fdir_guarantee_free_space =
1138 fdir_info->fdir_guarantee_total_space;
1140 PMD_DRV_LOG(INFO, "FDIR guarantee space: %u, best_effort space %u.", alloc, best);
1142 fdir_info->fdir_flow_pool.pool =
1143 rte_zmalloc("i40e_fdir_entry",
1144 sizeof(struct i40e_fdir_entry) *
1145 fdir_info->fdir_space_size,
1148 if (!fdir_info->fdir_flow_pool.pool) {
1150 "Failed to allocate memory for bitmap flow!");
1152 goto err_fdir_bitmap_flow_alloc;
1155 for (i = 0; i < fdir_info->fdir_space_size; i++)
1156 fdir_info->fdir_flow_pool.pool[i].idx = i;
1159 rte_bitmap_get_memory_footprint(fdir_info->fdir_space_size);
1160 mem = rte_zmalloc("fdir_bmap", bmp_size, RTE_CACHE_LINE_SIZE);
1163 "Failed to allocate memory for fdir bitmap!");
1165 goto err_fdir_mem_alloc;
1167 bmp = rte_bitmap_init(fdir_info->fdir_space_size, mem, bmp_size);
1170 "Failed to initialization fdir bitmap!");
1172 goto err_fdir_bmp_alloc;
1174 for (i = 0; i < fdir_info->fdir_space_size; i++)
1175 rte_bitmap_set(bmp, i);
1177 fdir_info->fdir_flow_pool.bitmap = bmp;
1184 rte_free(fdir_info->fdir_flow_pool.pool);
1185 err_fdir_bitmap_flow_alloc:
1186 rte_free(fdir_info->fdir_filter_array);
1187 err_fdir_filter_array_alloc:
1188 rte_free(fdir_info->hash_map);
1189 err_fdir_hash_map_alloc:
1190 rte_hash_free(fdir_info->hash_table);
1196 i40e_init_customized_info(struct i40e_pf *pf)
1200 /* Initialize customized pctype */
1201 for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1202 pf->customized_pctype[i].index = i;
1203 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1204 pf->customized_pctype[i].valid = false;
1207 pf->gtp_support = false;
1208 pf->esp_support = false;
1212 i40e_init_filter_invalidation(struct i40e_pf *pf)
1214 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1215 struct i40e_fdir_info *fdir_info = &pf->fdir;
1216 uint32_t glqf_ctl_reg = 0;
1218 glqf_ctl_reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
1219 if (!pf->support_multi_driver) {
1220 fdir_info->fdir_invalprio = 1;
1221 glqf_ctl_reg |= I40E_GLQF_CTL_INVALPRIO_MASK;
1222 PMD_DRV_LOG(INFO, "FDIR INVALPRIO set to guaranteed first");
1223 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, glqf_ctl_reg);
1225 if (glqf_ctl_reg & I40E_GLQF_CTL_INVALPRIO_MASK) {
1226 fdir_info->fdir_invalprio = 1;
1227 PMD_DRV_LOG(INFO, "FDIR INVALPRIO is: guaranteed first");
1229 fdir_info->fdir_invalprio = 0;
1230 PMD_DRV_LOG(INFO, "FDIR INVALPRIO is: shared first");
1236 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1238 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1239 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1240 struct i40e_queue_regions *info = &pf->queue_region;
1243 for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1244 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1246 memset(info, 0, sizeof(struct i40e_queue_regions));
1250 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1255 unsigned long support_multi_driver;
1258 pf = (struct i40e_pf *)opaque;
1261 support_multi_driver = strtoul(value, &end, 10);
1262 if (errno != 0 || end == value || *end != 0) {
1263 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1267 if (support_multi_driver == 1 || support_multi_driver == 0)
1268 pf->support_multi_driver = (bool)support_multi_driver;
1270 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1271 "enable global configuration by default."
1272 ETH_I40E_SUPPORT_MULTI_DRIVER);
1277 i40e_support_multi_driver(struct rte_eth_dev *dev)
1279 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1280 struct rte_kvargs *kvlist;
1283 /* Enable global configuration by default */
1284 pf->support_multi_driver = false;
1286 if (!dev->device->devargs)
1289 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1293 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1294 if (!kvargs_count) {
1295 rte_kvargs_free(kvlist);
1299 if (kvargs_count > 1)
1300 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1301 "the first invalid or last valid one is used !",
1302 ETH_I40E_SUPPORT_MULTI_DRIVER);
1304 if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1305 i40e_parse_multi_drv_handler, pf) < 0) {
1306 rte_kvargs_free(kvlist);
1310 rte_kvargs_free(kvlist);
1315 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1316 uint32_t reg_addr, uint64_t reg_val,
1317 struct i40e_asq_cmd_details *cmd_details)
1319 uint64_t ori_reg_val;
1320 struct rte_eth_dev_data *dev_data =
1321 ((struct i40e_adapter *)hw->back)->pf.dev_data;
1322 struct rte_eth_dev *dev = &rte_eth_devices[dev_data->port_id];
1325 ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1326 if (ret != I40E_SUCCESS) {
1328 "Fail to debug read from 0x%08x",
1333 if (ori_reg_val != reg_val)
1334 PMD_DRV_LOG(WARNING,
1335 "i40e device %s changed global register [0x%08x]."
1336 " original: 0x%"PRIx64", after: 0x%"PRIx64,
1337 dev->device->name, reg_addr, ori_reg_val, reg_val);
1339 return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1343 read_vf_msg_config(__rte_unused const char *key,
1347 struct i40e_vf_msg_cfg *cfg = opaque;
1349 if (sscanf(value, "%u@%u:%u", &cfg->max_msg, &cfg->period,
1350 &cfg->ignore_second) != 3) {
1351 memset(cfg, 0, sizeof(*cfg));
1352 PMD_DRV_LOG(ERR, "format error! example: "
1353 "%s=60@120:180", ETH_I40E_VF_MSG_CFG);
1358 * If the message validation function been enabled, the 'period'
1359 * and 'ignore_second' must greater than 0.
1361 if (cfg->max_msg && (!cfg->period || !cfg->ignore_second)) {
1362 memset(cfg, 0, sizeof(*cfg));
1363 PMD_DRV_LOG(ERR, "%s error! the second and third"
1364 " number must be greater than 0!",
1365 ETH_I40E_VF_MSG_CFG);
1373 i40e_parse_vf_msg_config(struct rte_eth_dev *dev,
1374 struct i40e_vf_msg_cfg *msg_cfg)
1376 struct rte_kvargs *kvlist;
1380 memset(msg_cfg, 0, sizeof(*msg_cfg));
1382 if (!dev->device->devargs)
1385 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1389 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_VF_MSG_CFG);
1393 if (kvargs_count > 1) {
1394 PMD_DRV_LOG(ERR, "More than one argument \"%s\"!",
1395 ETH_I40E_VF_MSG_CFG);
1400 if (rte_kvargs_process(kvlist, ETH_I40E_VF_MSG_CFG,
1401 read_vf_msg_config, msg_cfg) < 0)
1405 rte_kvargs_free(kvlist);
1409 #define I40E_ALARM_INTERVAL 50000 /* us */
1412 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1414 struct rte_pci_device *pci_dev;
1415 struct rte_intr_handle *intr_handle;
1416 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1417 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1418 struct i40e_vsi *vsi;
1421 uint8_t aq_fail = 0;
1423 PMD_INIT_FUNC_TRACE();
1425 dev->dev_ops = &i40e_eth_dev_ops;
1426 dev->rx_queue_count = i40e_dev_rx_queue_count;
1427 dev->rx_descriptor_status = i40e_dev_rx_descriptor_status;
1428 dev->tx_descriptor_status = i40e_dev_tx_descriptor_status;
1429 dev->rx_pkt_burst = i40e_recv_pkts;
1430 dev->tx_pkt_burst = i40e_xmit_pkts;
1431 dev->tx_pkt_prepare = i40e_prep_pkts;
1433 /* for secondary processes, we don't initialise any further as primary
1434 * has already done this work. Only check we don't need a different
1436 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1437 i40e_set_rx_function(dev);
1438 i40e_set_tx_function(dev);
1441 i40e_set_default_ptype_table(dev);
1442 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1443 intr_handle = &pci_dev->intr_handle;
1445 rte_eth_copy_pci_info(dev, pci_dev);
1447 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1448 pf->dev_data = dev->data;
1450 hw->back = I40E_PF_TO_ADAPTER(pf);
1451 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1454 "Hardware is not available, as address is NULL");
1458 hw->vendor_id = pci_dev->id.vendor_id;
1459 hw->device_id = pci_dev->id.device_id;
1460 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1461 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1462 hw->bus.device = pci_dev->addr.devid;
1463 hw->bus.func = pci_dev->addr.function;
1464 hw->adapter_stopped = 0;
1465 hw->adapter_closed = 0;
1467 /* Init switch device pointer */
1468 hw->switch_dev = NULL;
1471 * Switch Tag value should not be identical to either the First Tag
1472 * or Second Tag values. So set something other than common Ethertype
1473 * for internal switching.
1475 hw->switch_tag = 0xffff;
1477 val = I40E_READ_REG(hw, I40E_GL_FWSTS);
1478 if (val & I40E_GL_FWSTS_FWS1B_MASK) {
1479 PMD_INIT_LOG(ERR, "\nERROR: "
1480 "Firmware recovery mode detected. Limiting functionality.\n"
1481 "Refer to the Intel(R) Ethernet Adapters and Devices "
1482 "User Guide for details on firmware recovery mode.");
1486 i40e_parse_vf_msg_config(dev, &pf->vf_msg_cfg);
1487 /* Check if need to support multi-driver */
1488 i40e_support_multi_driver(dev);
1490 /* Make sure all is clean before doing PF reset */
1493 /* Reset here to make sure all is clean for each PF */
1494 ret = i40e_pf_reset(hw);
1496 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1500 /* Initialize the shared code (base driver) */
1501 ret = i40e_init_shared_code(hw);
1503 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1507 /* Initialize the parameters for adminq */
1508 i40e_init_adminq_parameter(hw);
1509 ret = i40e_init_adminq(hw);
1510 if (ret != I40E_SUCCESS) {
1511 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1514 /* Firmware of SFP x722 does not support 802.1ad frames ability */
1515 if (hw->device_id == I40E_DEV_ID_SFP_X722 ||
1516 hw->device_id == I40E_DEV_ID_SFP_I_X722)
1517 hw->flags &= ~I40E_HW_FLAG_802_1AD_CAPABLE;
1519 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1520 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1521 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1522 ((hw->nvm.version >> 12) & 0xf),
1523 ((hw->nvm.version >> 4) & 0xff),
1524 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1526 /* Initialize the hardware */
1529 i40e_config_automask(pf);
1531 i40e_set_default_pctype_table(dev);
1534 * To work around the NVM issue, initialize registers
1535 * for packet type of QinQ by software.
1536 * It should be removed once issues are fixed in NVM.
1538 if (!pf->support_multi_driver)
1539 i40e_GLQF_reg_init(hw);
1541 /* Initialize the input set for filters (hash and fd) to default value */
1542 i40e_filter_input_set_init(pf);
1544 /* initialise the L3_MAP register */
1545 if (!pf->support_multi_driver) {
1546 ret = i40e_aq_debug_write_global_register(hw,
1547 I40E_GLQF_L3_MAP(40),
1550 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1553 "Global register 0x%08x is changed with 0x28",
1554 I40E_GLQF_L3_MAP(40));
1557 /* Need the special FW version to support floating VEB */
1558 config_floating_veb(dev);
1559 /* Clear PXE mode */
1560 i40e_clear_pxe_mode(hw);
1561 i40e_dev_sync_phy_type(hw);
1564 * On X710, performance number is far from the expectation on recent
1565 * firmware versions. The fix for this issue may not be integrated in
1566 * the following firmware version. So the workaround in software driver
1567 * is needed. It needs to modify the initial values of 3 internal only
1568 * registers. Note that the workaround can be removed when it is fixed
1569 * in firmware in the future.
1571 i40e_configure_registers(hw);
1573 /* Get hw capabilities */
1574 ret = i40e_get_cap(hw);
1575 if (ret != I40E_SUCCESS) {
1576 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1577 goto err_get_capabilities;
1580 /* Initialize parameters for PF */
1581 ret = i40e_pf_parameter_init(dev);
1583 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1584 goto err_parameter_init;
1587 /* Initialize the queue management */
1588 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1590 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1591 goto err_qp_pool_init;
1593 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1594 hw->func_caps.num_msix_vectors - 1);
1596 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1597 goto err_msix_pool_init;
1600 /* Initialize lan hmc */
1601 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1602 hw->func_caps.num_rx_qp, 0, 0);
1603 if (ret != I40E_SUCCESS) {
1604 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1605 goto err_init_lan_hmc;
1608 /* Configure lan hmc */
1609 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1610 if (ret != I40E_SUCCESS) {
1611 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1612 goto err_configure_lan_hmc;
1615 /* Get and check the mac address */
1616 i40e_get_mac_addr(hw, hw->mac.addr);
1617 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1618 PMD_INIT_LOG(ERR, "mac address is not valid");
1620 goto err_get_mac_addr;
1622 /* Copy the permanent MAC address */
1623 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1624 (struct rte_ether_addr *)hw->mac.perm_addr);
1626 /* Disable flow control */
1627 hw->fc.requested_mode = I40E_FC_NONE;
1628 i40e_set_fc(hw, &aq_fail, TRUE);
1630 /* Set the global registers with default ether type value */
1631 if (!pf->support_multi_driver) {
1632 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1633 RTE_ETHER_TYPE_VLAN);
1634 if (ret != I40E_SUCCESS) {
1636 "Failed to set the default outer "
1638 goto err_setup_pf_switch;
1642 /* PF setup, which includes VSI setup */
1643 ret = i40e_pf_setup(pf);
1645 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1646 goto err_setup_pf_switch;
1651 /* Disable double vlan by default */
1652 i40e_vsi_config_double_vlan(vsi, FALSE);
1654 /* Disable S-TAG identification when floating_veb is disabled */
1655 if (!pf->floating_veb) {
1656 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1657 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1658 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1659 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1663 if (!vsi->max_macaddrs)
1664 len = RTE_ETHER_ADDR_LEN;
1666 len = RTE_ETHER_ADDR_LEN * vsi->max_macaddrs;
1668 /* Should be after VSI initialized */
1669 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1670 if (!dev->data->mac_addrs) {
1672 "Failed to allocated memory for storing mac address");
1675 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1676 &dev->data->mac_addrs[0]);
1678 /* Init dcb to sw mode by default */
1679 ret = i40e_dcb_init_configure(dev, TRUE);
1680 if (ret != I40E_SUCCESS) {
1681 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1682 pf->flags &= ~I40E_FLAG_DCB;
1684 /* Update HW struct after DCB configuration */
1687 /* initialize pf host driver to setup SRIOV resource if applicable */
1688 i40e_pf_host_init(dev);
1690 /* register callback func to eal lib */
1691 rte_intr_callback_register(intr_handle,
1692 i40e_dev_interrupt_handler, dev);
1694 /* configure and enable device interrupt */
1695 i40e_pf_config_irq0(hw, TRUE);
1696 i40e_pf_enable_irq0(hw);
1698 /* enable uio intr after callback register */
1699 rte_intr_enable(intr_handle);
1701 /* By default disable flexible payload in global configuration */
1702 if (!pf->support_multi_driver)
1703 i40e_flex_payload_reg_set_default(hw);
1706 * Add an ethertype filter to drop all flow control frames transmitted
1707 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1710 i40e_add_tx_flow_control_drop_filter(pf);
1712 /* Set the max frame size to 0x2600 by default,
1713 * in case other drivers changed the default value.
1715 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, false, 0, NULL);
1717 /* initialize RSS rule list */
1718 TAILQ_INIT(&pf->rss_config_list);
1720 /* initialize Traffic Manager configuration */
1721 i40e_tm_conf_init(dev);
1723 /* Initialize customized information */
1724 i40e_init_customized_info(pf);
1726 /* Initialize the filter invalidation configuration */
1727 i40e_init_filter_invalidation(pf);
1729 ret = i40e_init_ethtype_filter_list(dev);
1731 goto err_init_ethtype_filter_list;
1732 ret = i40e_init_tunnel_filter_list(dev);
1734 goto err_init_tunnel_filter_list;
1735 ret = i40e_init_fdir_filter_list(dev);
1737 goto err_init_fdir_filter_list;
1739 /* initialize queue region configuration */
1740 i40e_init_queue_region_conf(dev);
1742 /* reset all stats of the device, including pf and main vsi */
1743 i40e_dev_stats_reset(dev);
1747 err_init_fdir_filter_list:
1748 rte_hash_free(pf->tunnel.hash_table);
1749 rte_free(pf->tunnel.hash_map);
1750 err_init_tunnel_filter_list:
1751 rte_hash_free(pf->ethertype.hash_table);
1752 rte_free(pf->ethertype.hash_map);
1753 err_init_ethtype_filter_list:
1754 rte_intr_callback_unregister(intr_handle,
1755 i40e_dev_interrupt_handler, dev);
1756 rte_free(dev->data->mac_addrs);
1757 dev->data->mac_addrs = NULL;
1759 i40e_vsi_release(pf->main_vsi);
1760 err_setup_pf_switch:
1762 err_configure_lan_hmc:
1763 (void)i40e_shutdown_lan_hmc(hw);
1765 i40e_res_pool_destroy(&pf->msix_pool);
1767 i40e_res_pool_destroy(&pf->qp_pool);
1770 err_get_capabilities:
1771 (void)i40e_shutdown_adminq(hw);
1777 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1779 struct i40e_ethertype_filter *p_ethertype;
1780 struct i40e_ethertype_rule *ethertype_rule;
1782 ethertype_rule = &pf->ethertype;
1783 /* Remove all ethertype filter rules and hash */
1784 if (ethertype_rule->hash_map)
1785 rte_free(ethertype_rule->hash_map);
1786 if (ethertype_rule->hash_table)
1787 rte_hash_free(ethertype_rule->hash_table);
1789 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1790 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1791 p_ethertype, rules);
1792 rte_free(p_ethertype);
1797 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1799 struct i40e_tunnel_filter *p_tunnel;
1800 struct i40e_tunnel_rule *tunnel_rule;
1802 tunnel_rule = &pf->tunnel;
1803 /* Remove all tunnel director rules and hash */
1804 if (tunnel_rule->hash_map)
1805 rte_free(tunnel_rule->hash_map);
1806 if (tunnel_rule->hash_table)
1807 rte_hash_free(tunnel_rule->hash_table);
1809 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1810 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1816 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1818 struct i40e_fdir_filter *p_fdir;
1819 struct i40e_fdir_info *fdir_info;
1821 fdir_info = &pf->fdir;
1823 /* Remove all flow director rules */
1824 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list)))
1825 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1829 i40e_fdir_memory_cleanup(struct i40e_pf *pf)
1831 struct i40e_fdir_info *fdir_info;
1833 fdir_info = &pf->fdir;
1835 /* flow director memory cleanup */
1836 if (fdir_info->hash_map)
1837 rte_free(fdir_info->hash_map);
1838 if (fdir_info->hash_table)
1839 rte_hash_free(fdir_info->hash_table);
1840 if (fdir_info->fdir_flow_pool.bitmap)
1841 rte_free(fdir_info->fdir_flow_pool.bitmap);
1842 if (fdir_info->fdir_flow_pool.pool)
1843 rte_free(fdir_info->fdir_flow_pool.pool);
1844 if (fdir_info->fdir_filter_array)
1845 rte_free(fdir_info->fdir_filter_array);
1848 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1851 * Disable by default flexible payload
1852 * for corresponding L2/L3/L4 layers.
1854 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1855 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1856 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1860 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1864 PMD_INIT_FUNC_TRACE();
1866 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1869 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1871 if (hw->adapter_closed == 0)
1872 i40e_dev_close(dev);
1878 i40e_dev_configure(struct rte_eth_dev *dev)
1880 struct i40e_adapter *ad =
1881 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1882 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1883 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1884 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1887 ret = i40e_dev_sync_phy_type(hw);
1891 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1892 * bulk allocation or vector Rx preconditions we will reset it.
1894 ad->rx_bulk_alloc_allowed = true;
1895 ad->rx_vec_allowed = true;
1896 ad->tx_simple_allowed = true;
1897 ad->tx_vec_allowed = true;
1899 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1900 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1902 /* Only legacy filter API needs the following fdir config. So when the
1903 * legacy filter API is deprecated, the following codes should also be
1906 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1907 ret = i40e_fdir_setup(pf);
1908 if (ret != I40E_SUCCESS) {
1909 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1912 ret = i40e_fdir_configure(dev);
1914 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1918 i40e_fdir_teardown(pf);
1920 ret = i40e_dev_init_vlan(dev);
1925 * General PMD driver call sequence are NIC init, configure,
1926 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1927 * will try to lookup the VSI that specific queue belongs to if VMDQ
1928 * applicable. So, VMDQ setting has to be done before
1929 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1930 * For RSS setting, it will try to calculate actual configured RX queue
1931 * number, which will be available after rx_queue_setup(). dev_start()
1932 * function is good to place RSS setup.
1934 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1935 ret = i40e_vmdq_setup(dev);
1940 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1941 ret = i40e_dcb_setup(dev);
1943 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1948 TAILQ_INIT(&pf->flow_list);
1953 /* need to release vmdq resource if exists */
1954 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1955 i40e_vsi_release(pf->vmdq[i].vsi);
1956 pf->vmdq[i].vsi = NULL;
1961 /* Need to release fdir resource if exists.
1962 * Only legacy filter API needs the following fdir config. So when the
1963 * legacy filter API is deprecated, the following code should also be
1966 i40e_fdir_teardown(pf);
1971 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1973 struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
1974 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1975 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1976 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1977 uint16_t msix_vect = vsi->msix_intr;
1980 for (i = 0; i < vsi->nb_qps; i++) {
1981 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1982 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1986 if (vsi->type != I40E_VSI_SRIOV) {
1987 if (!rte_intr_allow_others(intr_handle)) {
1988 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1989 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1991 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1994 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1995 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1997 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
2002 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
2003 vsi->user_param + (msix_vect - 1);
2005 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
2006 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
2008 I40E_WRITE_FLUSH(hw);
2012 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
2013 int base_queue, int nb_queue,
2018 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2019 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2021 /* Bind all RX queues to allocated MSIX interrupt */
2022 for (i = 0; i < nb_queue; i++) {
2023 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
2024 itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
2025 ((base_queue + i + 1) <<
2026 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
2027 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
2028 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
2030 if (i == nb_queue - 1)
2031 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
2032 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
2035 /* Write first RX queue to Link list register as the head element */
2036 if (vsi->type != I40E_VSI_SRIOV) {
2038 i40e_calc_itr_interval(1, pf->support_multi_driver);
2040 if (msix_vect == I40E_MISC_VEC_ID) {
2041 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
2043 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
2045 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
2047 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
2050 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
2052 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
2054 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2056 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
2063 if (msix_vect == I40E_MISC_VEC_ID) {
2065 I40E_VPINT_LNKLST0(vsi->user_param),
2067 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
2069 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
2071 /* num_msix_vectors_vf needs to minus irq0 */
2072 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
2073 vsi->user_param + (msix_vect - 1);
2075 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
2077 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
2079 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2083 I40E_WRITE_FLUSH(hw);
2087 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
2089 struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
2090 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2091 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2092 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2093 uint16_t msix_vect = vsi->msix_intr;
2094 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2095 uint16_t queue_idx = 0;
2099 for (i = 0; i < vsi->nb_qps; i++) {
2100 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
2101 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2104 /* VF bind interrupt */
2105 if (vsi->type == I40E_VSI_SRIOV) {
2106 if (vsi->nb_msix == 0) {
2107 PMD_DRV_LOG(ERR, "No msix resource");
2110 __vsi_queues_bind_intr(vsi, msix_vect,
2111 vsi->base_queue, vsi->nb_qps,
2116 /* PF & VMDq bind interrupt */
2117 if (rte_intr_dp_is_en(intr_handle)) {
2118 if (vsi->type == I40E_VSI_MAIN) {
2121 } else if (vsi->type == I40E_VSI_VMDQ2) {
2122 struct i40e_vsi *main_vsi =
2123 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2124 queue_idx = vsi->base_queue - main_vsi->nb_qps;
2129 for (i = 0; i < vsi->nb_used_qps; i++) {
2130 if (vsi->nb_msix == 0) {
2131 PMD_DRV_LOG(ERR, "No msix resource");
2133 } else if (nb_msix <= 1) {
2134 if (!rte_intr_allow_others(intr_handle))
2135 /* allow to share MISC_VEC_ID */
2136 msix_vect = I40E_MISC_VEC_ID;
2138 /* no enough msix_vect, map all to one */
2139 __vsi_queues_bind_intr(vsi, msix_vect,
2140 vsi->base_queue + i,
2141 vsi->nb_used_qps - i,
2143 for (; !!record && i < vsi->nb_used_qps; i++)
2144 intr_handle->intr_vec[queue_idx + i] =
2148 /* 1:1 queue/msix_vect mapping */
2149 __vsi_queues_bind_intr(vsi, msix_vect,
2150 vsi->base_queue + i, 1,
2153 intr_handle->intr_vec[queue_idx + i] = msix_vect;
2163 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2165 struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
2166 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2167 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2168 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2169 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2170 uint16_t msix_intr, i;
2172 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2173 for (i = 0; i < vsi->nb_msix; i++) {
2174 msix_intr = vsi->msix_intr + i;
2175 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2176 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2177 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2178 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2181 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2182 I40E_PFINT_DYN_CTL0_INTENA_MASK |
2183 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2184 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2186 I40E_WRITE_FLUSH(hw);
2190 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2192 struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vsi);
2193 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2194 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2195 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2196 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2197 uint16_t msix_intr, i;
2199 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2200 for (i = 0; i < vsi->nb_msix; i++) {
2201 msix_intr = vsi->msix_intr + i;
2202 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2203 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2206 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2207 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2209 I40E_WRITE_FLUSH(hw);
2212 static inline uint8_t
2213 i40e_parse_link_speeds(uint16_t link_speeds)
2215 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2217 if (link_speeds & ETH_LINK_SPEED_40G)
2218 link_speed |= I40E_LINK_SPEED_40GB;
2219 if (link_speeds & ETH_LINK_SPEED_25G)
2220 link_speed |= I40E_LINK_SPEED_25GB;
2221 if (link_speeds & ETH_LINK_SPEED_20G)
2222 link_speed |= I40E_LINK_SPEED_20GB;
2223 if (link_speeds & ETH_LINK_SPEED_10G)
2224 link_speed |= I40E_LINK_SPEED_10GB;
2225 if (link_speeds & ETH_LINK_SPEED_1G)
2226 link_speed |= I40E_LINK_SPEED_1GB;
2227 if (link_speeds & ETH_LINK_SPEED_100M)
2228 link_speed |= I40E_LINK_SPEED_100MB;
2234 i40e_phy_conf_link(struct i40e_hw *hw,
2236 uint8_t force_speed,
2239 enum i40e_status_code status;
2240 struct i40e_aq_get_phy_abilities_resp phy_ab;
2241 struct i40e_aq_set_phy_config phy_conf;
2242 enum i40e_aq_phy_type cnt;
2243 uint8_t avail_speed;
2244 uint32_t phy_type_mask = 0;
2246 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2247 I40E_AQ_PHY_FLAG_PAUSE_RX |
2248 I40E_AQ_PHY_FLAG_PAUSE_RX |
2249 I40E_AQ_PHY_FLAG_LOW_POWER;
2252 /* To get phy capabilities of available speeds. */
2253 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2256 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2260 avail_speed = phy_ab.link_speed;
2262 /* To get the current phy config. */
2263 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2266 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2271 /* If link needs to go up and it is in autoneg mode the speed is OK,
2272 * no need to set up again.
2274 if (is_up && phy_ab.phy_type != 0 &&
2275 abilities & I40E_AQ_PHY_AN_ENABLED &&
2276 phy_ab.link_speed != 0)
2277 return I40E_SUCCESS;
2279 memset(&phy_conf, 0, sizeof(phy_conf));
2281 /* bits 0-2 use the values from get_phy_abilities_resp */
2283 abilities |= phy_ab.abilities & mask;
2285 phy_conf.abilities = abilities;
2287 /* If link needs to go up, but the force speed is not supported,
2288 * Warn users and config the default available speeds.
2290 if (is_up && !(force_speed & avail_speed)) {
2291 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2292 phy_conf.link_speed = avail_speed;
2294 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2297 /* PHY type mask needs to include each type except PHY type extension */
2298 for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2299 phy_type_mask |= 1 << cnt;
2301 /* use get_phy_abilities_resp value for the rest */
2302 phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2303 phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2304 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2305 I40E_AQ_PHY_TYPE_EXT_25G_LR | I40E_AQ_PHY_TYPE_EXT_25G_AOC |
2306 I40E_AQ_PHY_TYPE_EXT_25G_ACC) : 0;
2307 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2308 phy_conf.eee_capability = phy_ab.eee_capability;
2309 phy_conf.eeer = phy_ab.eeer_val;
2310 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2312 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2313 phy_ab.abilities, phy_ab.link_speed);
2314 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
2315 phy_conf.abilities, phy_conf.link_speed);
2317 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2321 return I40E_SUCCESS;
2325 i40e_apply_link_speed(struct rte_eth_dev *dev)
2328 uint8_t abilities = 0;
2329 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2330 struct rte_eth_conf *conf = &dev->data->dev_conf;
2332 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2333 I40E_AQ_PHY_LINK_ENABLED;
2335 if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2336 conf->link_speeds = ETH_LINK_SPEED_40G |
2337 ETH_LINK_SPEED_25G |
2338 ETH_LINK_SPEED_20G |
2339 ETH_LINK_SPEED_10G |
2341 ETH_LINK_SPEED_100M;
2343 abilities |= I40E_AQ_PHY_AN_ENABLED;
2345 abilities &= ~I40E_AQ_PHY_AN_ENABLED;
2347 speed = i40e_parse_link_speeds(conf->link_speeds);
2349 return i40e_phy_conf_link(hw, abilities, speed, true);
2353 i40e_dev_start(struct rte_eth_dev *dev)
2355 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2356 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2357 struct i40e_vsi *main_vsi = pf->main_vsi;
2359 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2360 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2361 uint32_t intr_vector = 0;
2362 struct i40e_vsi *vsi;
2363 uint16_t nb_rxq, nb_txq;
2365 hw->adapter_stopped = 0;
2367 rte_intr_disable(intr_handle);
2369 if ((rte_intr_cap_multiple(intr_handle) ||
2370 !RTE_ETH_DEV_SRIOV(dev).active) &&
2371 dev->data->dev_conf.intr_conf.rxq != 0) {
2372 intr_vector = dev->data->nb_rx_queues;
2373 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2378 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2379 intr_handle->intr_vec =
2380 rte_zmalloc("intr_vec",
2381 dev->data->nb_rx_queues * sizeof(int),
2383 if (!intr_handle->intr_vec) {
2385 "Failed to allocate %d rx_queues intr_vec",
2386 dev->data->nb_rx_queues);
2391 /* Initialize VSI */
2392 ret = i40e_dev_rxtx_init(pf);
2393 if (ret != I40E_SUCCESS) {
2394 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2398 /* Map queues with MSIX interrupt */
2399 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2400 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2401 ret = i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2404 i40e_vsi_enable_queues_intr(main_vsi);
2406 /* Map VMDQ VSI queues with MSIX interrupt */
2407 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2408 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2409 ret = i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2410 I40E_ITR_INDEX_DEFAULT);
2413 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2416 /* Enable all queues which have been configured */
2417 for (nb_rxq = 0; nb_rxq < dev->data->nb_rx_queues; nb_rxq++) {
2418 ret = i40e_dev_rx_queue_start(dev, nb_rxq);
2423 for (nb_txq = 0; nb_txq < dev->data->nb_tx_queues; nb_txq++) {
2424 ret = i40e_dev_tx_queue_start(dev, nb_txq);
2429 /* Enable receiving broadcast packets */
2430 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2431 if (ret != I40E_SUCCESS)
2432 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2434 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2435 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2437 if (ret != I40E_SUCCESS)
2438 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2441 /* Enable the VLAN promiscuous mode. */
2443 for (i = 0; i < pf->vf_num; i++) {
2444 vsi = pf->vfs[i].vsi;
2445 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2450 /* Enable mac loopback mode */
2451 if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2452 dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2453 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2454 if (ret != I40E_SUCCESS) {
2455 PMD_DRV_LOG(ERR, "fail to set loopback link");
2460 /* Apply link configure */
2461 ret = i40e_apply_link_speed(dev);
2462 if (I40E_SUCCESS != ret) {
2463 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2467 if (!rte_intr_allow_others(intr_handle)) {
2468 rte_intr_callback_unregister(intr_handle,
2469 i40e_dev_interrupt_handler,
2471 /* configure and enable device interrupt */
2472 i40e_pf_config_irq0(hw, FALSE);
2473 i40e_pf_enable_irq0(hw);
2475 if (dev->data->dev_conf.intr_conf.lsc != 0)
2477 "lsc won't enable because of no intr multiplex");
2479 ret = i40e_aq_set_phy_int_mask(hw,
2480 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2481 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2482 I40E_AQ_EVENT_MEDIA_NA), NULL);
2483 if (ret != I40E_SUCCESS)
2484 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2486 /* Call get_link_info aq commond to enable/disable LSE */
2487 i40e_dev_link_update(dev, 0);
2490 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2491 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2492 i40e_dev_alarm_handler, dev);
2494 /* enable uio intr after callback register */
2495 rte_intr_enable(intr_handle);
2498 i40e_filter_restore(pf);
2500 if (pf->tm_conf.root && !pf->tm_conf.committed)
2501 PMD_DRV_LOG(WARNING,
2502 "please call hierarchy_commit() "
2503 "before starting the port");
2505 return I40E_SUCCESS;
2508 for (i = 0; i < nb_txq; i++)
2509 i40e_dev_tx_queue_stop(dev, i);
2511 for (i = 0; i < nb_rxq; i++)
2512 i40e_dev_rx_queue_stop(dev, i);
2518 i40e_dev_stop(struct rte_eth_dev *dev)
2520 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2521 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2522 struct i40e_vsi *main_vsi = pf->main_vsi;
2523 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2524 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2527 if (hw->adapter_stopped == 1)
2530 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2531 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2532 rte_intr_enable(intr_handle);
2535 /* Disable all queues */
2536 for (i = 0; i < dev->data->nb_tx_queues; i++)
2537 i40e_dev_tx_queue_stop(dev, i);
2539 for (i = 0; i < dev->data->nb_rx_queues; i++)
2540 i40e_dev_rx_queue_stop(dev, i);
2542 /* un-map queues with interrupt registers */
2543 i40e_vsi_disable_queues_intr(main_vsi);
2544 i40e_vsi_queues_unbind_intr(main_vsi);
2546 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2547 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2548 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2551 /* Clear all queues and release memory */
2552 i40e_dev_clear_queues(dev);
2555 i40e_dev_set_link_down(dev);
2557 if (!rte_intr_allow_others(intr_handle))
2558 /* resume to the default handler */
2559 rte_intr_callback_register(intr_handle,
2560 i40e_dev_interrupt_handler,
2563 /* Clean datapath event and queue/vec mapping */
2564 rte_intr_efd_disable(intr_handle);
2565 if (intr_handle->intr_vec) {
2566 rte_free(intr_handle->intr_vec);
2567 intr_handle->intr_vec = NULL;
2570 /* reset hierarchy commit */
2571 pf->tm_conf.committed = false;
2573 hw->adapter_stopped = 1;
2574 dev->data->dev_started = 0;
2576 pf->adapter->rss_reta_updated = 0;
2582 i40e_dev_close(struct rte_eth_dev *dev)
2584 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2585 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2586 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2587 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2588 struct i40e_filter_control_settings settings;
2589 struct rte_flow *p_flow;
2593 uint8_t aq_fail = 0;
2596 PMD_INIT_FUNC_TRACE();
2597 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2600 ret = rte_eth_switch_domain_free(pf->switch_domain_id);
2602 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
2605 ret = i40e_dev_stop(dev);
2607 i40e_dev_free_queues(dev);
2609 /* Disable interrupt */
2610 i40e_pf_disable_irq0(hw);
2611 rte_intr_disable(intr_handle);
2614 * Only legacy filter API needs the following fdir config. So when the
2615 * legacy filter API is deprecated, the following code should also be
2618 i40e_fdir_teardown(pf);
2620 /* shutdown and destroy the HMC */
2621 i40e_shutdown_lan_hmc(hw);
2623 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2624 i40e_vsi_release(pf->vmdq[i].vsi);
2625 pf->vmdq[i].vsi = NULL;
2630 /* release all the existing VSIs and VEBs */
2631 i40e_vsi_release(pf->main_vsi);
2633 /* shutdown the adminq */
2634 i40e_aq_queue_shutdown(hw, true);
2635 i40e_shutdown_adminq(hw);
2637 i40e_res_pool_destroy(&pf->qp_pool);
2638 i40e_res_pool_destroy(&pf->msix_pool);
2640 /* Disable flexible payload in global configuration */
2641 if (!pf->support_multi_driver)
2642 i40e_flex_payload_reg_set_default(hw);
2644 /* force a PF reset to clean anything leftover */
2645 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2646 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2647 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2648 I40E_WRITE_FLUSH(hw);
2650 /* Clear PXE mode */
2651 i40e_clear_pxe_mode(hw);
2653 /* Unconfigure filter control */
2654 memset(&settings, 0, sizeof(settings));
2655 ret = i40e_set_filter_control(hw, &settings);
2657 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
2660 /* Disable flow control */
2661 hw->fc.requested_mode = I40E_FC_NONE;
2662 i40e_set_fc(hw, &aq_fail, TRUE);
2664 /* uninitialize pf host driver */
2665 i40e_pf_host_uninit(dev);
2668 ret = rte_intr_callback_unregister(intr_handle,
2669 i40e_dev_interrupt_handler, dev);
2670 if (ret >= 0 || ret == -ENOENT) {
2672 } else if (ret != -EAGAIN) {
2674 "intr callback unregister failed: %d",
2677 i40e_msec_delay(500);
2678 } while (retries++ < 5);
2680 i40e_rm_ethtype_filter_list(pf);
2681 i40e_rm_tunnel_filter_list(pf);
2682 i40e_rm_fdir_filter_list(pf);
2684 /* Remove all flows */
2685 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
2686 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
2687 /* Do not free FDIR flows since they are static allocated */
2688 if (p_flow->filter_type != RTE_ETH_FILTER_FDIR)
2692 /* release the fdir static allocated memory */
2693 i40e_fdir_memory_cleanup(pf);
2695 /* Remove all Traffic Manager configuration */
2696 i40e_tm_conf_uninit(dev);
2698 i40e_clear_automask(pf);
2700 hw->adapter_closed = 1;
2705 * Reset PF device only to re-initialize resources in PMD layer
2708 i40e_dev_reset(struct rte_eth_dev *dev)
2712 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2713 * its VF to make them align with it. The detailed notification
2714 * mechanism is PMD specific. As to i40e PF, it is rather complex.
2715 * To avoid unexpected behavior in VF, currently reset of PF with
2716 * SR-IOV activation is not supported. It might be supported later.
2718 if (dev->data->sriov.active)
2721 ret = eth_i40e_dev_uninit(dev);
2725 ret = eth_i40e_dev_init(dev, NULL);
2731 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2733 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2734 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2735 struct i40e_vsi *vsi = pf->main_vsi;
2738 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2740 if (status != I40E_SUCCESS) {
2741 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2745 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2747 if (status != I40E_SUCCESS) {
2748 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2749 /* Rollback unicast promiscuous mode */
2750 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2759 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2761 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2762 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2763 struct i40e_vsi *vsi = pf->main_vsi;
2766 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2768 if (status != I40E_SUCCESS) {
2769 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2773 /* must remain in all_multicast mode */
2774 if (dev->data->all_multicast == 1)
2777 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2779 if (status != I40E_SUCCESS) {
2780 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2781 /* Rollback unicast promiscuous mode */
2782 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2791 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2793 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2794 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2795 struct i40e_vsi *vsi = pf->main_vsi;
2798 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2799 if (ret != I40E_SUCCESS) {
2800 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2808 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2810 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2811 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2812 struct i40e_vsi *vsi = pf->main_vsi;
2815 if (dev->data->promiscuous == 1)
2816 return 0; /* must remain in all_multicast mode */
2818 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2819 vsi->seid, FALSE, NULL);
2820 if (ret != I40E_SUCCESS) {
2821 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2829 * Set device link up.
2832 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2834 /* re-apply link speed setting */
2835 return i40e_apply_link_speed(dev);
2839 * Set device link down.
2842 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2844 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2845 uint8_t abilities = 0;
2846 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2848 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2849 return i40e_phy_conf_link(hw, abilities, speed, false);
2852 static __rte_always_inline void
2853 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2855 /* Link status registers and values*/
2856 #define I40E_REG_LINK_UP 0x40000080
2857 #define I40E_PRTMAC_MACC 0x001E24E0
2858 #define I40E_REG_MACC_25GB 0x00020000
2859 #define I40E_REG_SPEED_MASK 0x38000000
2860 #define I40E_REG_SPEED_0 0x00000000
2861 #define I40E_REG_SPEED_1 0x08000000
2862 #define I40E_REG_SPEED_2 0x10000000
2863 #define I40E_REG_SPEED_3 0x18000000
2864 #define I40E_REG_SPEED_4 0x20000000
2865 uint32_t link_speed;
2868 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA(0));
2869 link_speed = reg_val & I40E_REG_SPEED_MASK;
2870 reg_val &= I40E_REG_LINK_UP;
2871 link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2873 if (unlikely(link->link_status == 0))
2876 /* Parse the link status */
2877 switch (link_speed) {
2878 case I40E_REG_SPEED_0:
2879 link->link_speed = ETH_SPEED_NUM_100M;
2881 case I40E_REG_SPEED_1:
2882 link->link_speed = ETH_SPEED_NUM_1G;
2884 case I40E_REG_SPEED_2:
2885 if (hw->mac.type == I40E_MAC_X722)
2886 link->link_speed = ETH_SPEED_NUM_2_5G;
2888 link->link_speed = ETH_SPEED_NUM_10G;
2890 case I40E_REG_SPEED_3:
2891 if (hw->mac.type == I40E_MAC_X722) {
2892 link->link_speed = ETH_SPEED_NUM_5G;
2894 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2896 if (reg_val & I40E_REG_MACC_25GB)
2897 link->link_speed = ETH_SPEED_NUM_25G;
2899 link->link_speed = ETH_SPEED_NUM_40G;
2902 case I40E_REG_SPEED_4:
2903 if (hw->mac.type == I40E_MAC_X722)
2904 link->link_speed = ETH_SPEED_NUM_10G;
2906 link->link_speed = ETH_SPEED_NUM_20G;
2909 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2914 static __rte_always_inline void
2915 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2916 bool enable_lse, int wait_to_complete)
2918 #define CHECK_INTERVAL 100 /* 100ms */
2919 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2920 uint32_t rep_cnt = MAX_REPEAT_TIME;
2921 struct i40e_link_status link_status;
2924 memset(&link_status, 0, sizeof(link_status));
2927 memset(&link_status, 0, sizeof(link_status));
2929 /* Get link status information from hardware */
2930 status = i40e_aq_get_link_info(hw, enable_lse,
2931 &link_status, NULL);
2932 if (unlikely(status != I40E_SUCCESS)) {
2933 link->link_speed = ETH_SPEED_NUM_NONE;
2934 link->link_duplex = ETH_LINK_FULL_DUPLEX;
2935 PMD_DRV_LOG(ERR, "Failed to get link info");
2939 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2940 if (!wait_to_complete || link->link_status)
2943 rte_delay_ms(CHECK_INTERVAL);
2944 } while (--rep_cnt);
2946 /* Parse the link status */
2947 switch (link_status.link_speed) {
2948 case I40E_LINK_SPEED_100MB:
2949 link->link_speed = ETH_SPEED_NUM_100M;
2951 case I40E_LINK_SPEED_1GB:
2952 link->link_speed = ETH_SPEED_NUM_1G;
2954 case I40E_LINK_SPEED_10GB:
2955 link->link_speed = ETH_SPEED_NUM_10G;
2957 case I40E_LINK_SPEED_20GB:
2958 link->link_speed = ETH_SPEED_NUM_20G;
2960 case I40E_LINK_SPEED_25GB:
2961 link->link_speed = ETH_SPEED_NUM_25G;
2963 case I40E_LINK_SPEED_40GB:
2964 link->link_speed = ETH_SPEED_NUM_40G;
2967 if (link->link_status)
2968 link->link_speed = ETH_SPEED_NUM_UNKNOWN;
2970 link->link_speed = ETH_SPEED_NUM_NONE;
2976 i40e_dev_link_update(struct rte_eth_dev *dev,
2977 int wait_to_complete)
2979 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2980 struct rte_eth_link link;
2981 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2984 memset(&link, 0, sizeof(link));
2986 /* i40e uses full duplex only */
2987 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2988 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2989 ETH_LINK_SPEED_FIXED);
2991 if (!wait_to_complete && !enable_lse)
2992 update_link_reg(hw, &link);
2994 update_link_aq(hw, &link, enable_lse, wait_to_complete);
2997 rte_eth_linkstatus_get(hw->switch_dev, &link);
2999 ret = rte_eth_linkstatus_set(dev, &link);
3000 i40e_notify_all_vfs_link_status(dev);
3006 i40e_stat_update_48_in_64(struct i40e_hw *hw, uint32_t hireg,
3007 uint32_t loreg, bool offset_loaded, uint64_t *offset,
3008 uint64_t *stat, uint64_t *prev_stat)
3010 i40e_stat_update_48(hw, hireg, loreg, offset_loaded, offset, stat);
3011 /* enlarge the limitation when statistics counters overflowed */
3012 if (offset_loaded) {
3013 if (I40E_RXTX_BYTES_L_48_BIT(*prev_stat) > *stat)
3014 *stat += (uint64_t)1 << I40E_48_BIT_WIDTH;
3015 *stat += I40E_RXTX_BYTES_H_16_BIT(*prev_stat);
3020 /* Get all the statistics of a VSI */
3022 i40e_update_vsi_stats(struct i40e_vsi *vsi)
3024 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
3025 struct i40e_eth_stats *nes = &vsi->eth_stats;
3026 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3027 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
3029 i40e_stat_update_48_in_64(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
3030 vsi->offset_loaded, &oes->rx_bytes,
3031 &nes->rx_bytes, &vsi->prev_rx_bytes);
3032 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
3033 vsi->offset_loaded, &oes->rx_unicast,
3035 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
3036 vsi->offset_loaded, &oes->rx_multicast,
3037 &nes->rx_multicast);
3038 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
3039 vsi->offset_loaded, &oes->rx_broadcast,
3040 &nes->rx_broadcast);
3041 /* exclude CRC bytes */
3042 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
3043 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
3045 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
3046 &oes->rx_discards, &nes->rx_discards);
3047 /* GLV_REPC not supported */
3048 /* GLV_RMPC not supported */
3049 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
3050 &oes->rx_unknown_protocol,
3051 &nes->rx_unknown_protocol);
3052 i40e_stat_update_48_in_64(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
3053 vsi->offset_loaded, &oes->tx_bytes,
3054 &nes->tx_bytes, &vsi->prev_tx_bytes);
3055 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
3056 vsi->offset_loaded, &oes->tx_unicast,
3058 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
3059 vsi->offset_loaded, &oes->tx_multicast,
3060 &nes->tx_multicast);
3061 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
3062 vsi->offset_loaded, &oes->tx_broadcast,
3063 &nes->tx_broadcast);
3064 /* GLV_TDPC not supported */
3065 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
3066 &oes->tx_errors, &nes->tx_errors);
3067 vsi->offset_loaded = true;
3069 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
3071 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
3072 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
3073 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
3074 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
3075 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
3076 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3077 nes->rx_unknown_protocol);
3078 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
3079 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
3080 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
3081 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
3082 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
3083 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
3084 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
3089 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
3092 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3093 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
3095 /* Get rx/tx bytes of internal transfer packets */
3096 i40e_stat_update_48_in_64(hw, I40E_GLV_GORCH(hw->port),
3097 I40E_GLV_GORCL(hw->port),
3099 &pf->internal_stats_offset.rx_bytes,
3100 &pf->internal_stats.rx_bytes,
3101 &pf->internal_prev_rx_bytes);
3102 i40e_stat_update_48_in_64(hw, I40E_GLV_GOTCH(hw->port),
3103 I40E_GLV_GOTCL(hw->port),
3105 &pf->internal_stats_offset.tx_bytes,
3106 &pf->internal_stats.tx_bytes,
3107 &pf->internal_prev_tx_bytes);
3108 /* Get total internal rx packet count */
3109 i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
3110 I40E_GLV_UPRCL(hw->port),
3112 &pf->internal_stats_offset.rx_unicast,
3113 &pf->internal_stats.rx_unicast);
3114 i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
3115 I40E_GLV_MPRCL(hw->port),
3117 &pf->internal_stats_offset.rx_multicast,
3118 &pf->internal_stats.rx_multicast);
3119 i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
3120 I40E_GLV_BPRCL(hw->port),
3122 &pf->internal_stats_offset.rx_broadcast,
3123 &pf->internal_stats.rx_broadcast);
3124 /* Get total internal tx packet count */
3125 i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
3126 I40E_GLV_UPTCL(hw->port),
3128 &pf->internal_stats_offset.tx_unicast,
3129 &pf->internal_stats.tx_unicast);
3130 i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
3131 I40E_GLV_MPTCL(hw->port),
3133 &pf->internal_stats_offset.tx_multicast,
3134 &pf->internal_stats.tx_multicast);
3135 i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
3136 I40E_GLV_BPTCL(hw->port),
3138 &pf->internal_stats_offset.tx_broadcast,
3139 &pf->internal_stats.tx_broadcast);
3141 /* exclude CRC size */
3142 pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
3143 pf->internal_stats.rx_multicast +
3144 pf->internal_stats.rx_broadcast) * RTE_ETHER_CRC_LEN;
3146 /* Get statistics of struct i40e_eth_stats */
3147 i40e_stat_update_48_in_64(hw, I40E_GLPRT_GORCH(hw->port),
3148 I40E_GLPRT_GORCL(hw->port),
3149 pf->offset_loaded, &os->eth.rx_bytes,
3150 &ns->eth.rx_bytes, &pf->prev_rx_bytes);
3151 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
3152 I40E_GLPRT_UPRCL(hw->port),
3153 pf->offset_loaded, &os->eth.rx_unicast,
3154 &ns->eth.rx_unicast);
3155 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
3156 I40E_GLPRT_MPRCL(hw->port),
3157 pf->offset_loaded, &os->eth.rx_multicast,
3158 &ns->eth.rx_multicast);
3159 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
3160 I40E_GLPRT_BPRCL(hw->port),
3161 pf->offset_loaded, &os->eth.rx_broadcast,
3162 &ns->eth.rx_broadcast);
3163 /* Workaround: CRC size should not be included in byte statistics,
3164 * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
3167 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
3168 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
3170 /* exclude internal rx bytes
3171 * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
3172 * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
3174 * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
3176 if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
3177 ns->eth.rx_bytes = 0;
3179 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
3181 if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
3182 ns->eth.rx_unicast = 0;
3184 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
3186 if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
3187 ns->eth.rx_multicast = 0;
3189 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
3191 if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
3192 ns->eth.rx_broadcast = 0;
3194 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
3196 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
3197 pf->offset_loaded, &os->eth.rx_discards,
3198 &ns->eth.rx_discards);
3199 /* GLPRT_REPC not supported */
3200 /* GLPRT_RMPC not supported */
3201 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
3203 &os->eth.rx_unknown_protocol,
3204 &ns->eth.rx_unknown_protocol);
3205 i40e_stat_update_48(hw, I40E_GL_RXERR1_H(hw->pf_id + I40E_MAX_VF),
3206 I40E_GL_RXERR1_L(hw->pf_id + I40E_MAX_VF),
3207 pf->offset_loaded, &pf->rx_err1_offset,
3209 i40e_stat_update_48_in_64(hw, I40E_GLPRT_GOTCH(hw->port),
3210 I40E_GLPRT_GOTCL(hw->port),
3211 pf->offset_loaded, &os->eth.tx_bytes,
3212 &ns->eth.tx_bytes, &pf->prev_tx_bytes);
3213 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
3214 I40E_GLPRT_UPTCL(hw->port),
3215 pf->offset_loaded, &os->eth.tx_unicast,
3216 &ns->eth.tx_unicast);
3217 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
3218 I40E_GLPRT_MPTCL(hw->port),
3219 pf->offset_loaded, &os->eth.tx_multicast,
3220 &ns->eth.tx_multicast);
3221 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
3222 I40E_GLPRT_BPTCL(hw->port),
3223 pf->offset_loaded, &os->eth.tx_broadcast,
3224 &ns->eth.tx_broadcast);
3225 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3226 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3228 /* exclude internal tx bytes
3229 * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
3230 * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
3232 * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
3234 if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
3235 ns->eth.tx_bytes = 0;
3237 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3239 if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3240 ns->eth.tx_unicast = 0;
3242 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3244 if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3245 ns->eth.tx_multicast = 0;
3247 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3249 if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3250 ns->eth.tx_broadcast = 0;
3252 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3254 /* GLPRT_TEPC not supported */
3256 /* additional port specific stats */
3257 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3258 pf->offset_loaded, &os->tx_dropped_link_down,
3259 &ns->tx_dropped_link_down);
3260 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3261 pf->offset_loaded, &os->crc_errors,
3263 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3264 pf->offset_loaded, &os->illegal_bytes,
3265 &ns->illegal_bytes);
3266 /* GLPRT_ERRBC not supported */
3267 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3268 pf->offset_loaded, &os->mac_local_faults,
3269 &ns->mac_local_faults);
3270 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3271 pf->offset_loaded, &os->mac_remote_faults,
3272 &ns->mac_remote_faults);
3273 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3274 pf->offset_loaded, &os->rx_length_errors,
3275 &ns->rx_length_errors);
3276 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3277 pf->offset_loaded, &os->link_xon_rx,
3279 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3280 pf->offset_loaded, &os->link_xoff_rx,
3282 for (i = 0; i < 8; i++) {
3283 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3285 &os->priority_xon_rx[i],
3286 &ns->priority_xon_rx[i]);
3287 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3289 &os->priority_xoff_rx[i],
3290 &ns->priority_xoff_rx[i]);
3292 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3293 pf->offset_loaded, &os->link_xon_tx,
3295 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3296 pf->offset_loaded, &os->link_xoff_tx,
3298 for (i = 0; i < 8; i++) {
3299 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3301 &os->priority_xon_tx[i],
3302 &ns->priority_xon_tx[i]);
3303 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3305 &os->priority_xoff_tx[i],
3306 &ns->priority_xoff_tx[i]);
3307 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3309 &os->priority_xon_2_xoff[i],
3310 &ns->priority_xon_2_xoff[i]);
3312 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3313 I40E_GLPRT_PRC64L(hw->port),
3314 pf->offset_loaded, &os->rx_size_64,
3316 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3317 I40E_GLPRT_PRC127L(hw->port),
3318 pf->offset_loaded, &os->rx_size_127,
3320 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3321 I40E_GLPRT_PRC255L(hw->port),
3322 pf->offset_loaded, &os->rx_size_255,
3324 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3325 I40E_GLPRT_PRC511L(hw->port),
3326 pf->offset_loaded, &os->rx_size_511,
3328 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3329 I40E_GLPRT_PRC1023L(hw->port),
3330 pf->offset_loaded, &os->rx_size_1023,
3332 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3333 I40E_GLPRT_PRC1522L(hw->port),
3334 pf->offset_loaded, &os->rx_size_1522,
3336 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3337 I40E_GLPRT_PRC9522L(hw->port),
3338 pf->offset_loaded, &os->rx_size_big,
3340 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3341 pf->offset_loaded, &os->rx_undersize,
3343 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3344 pf->offset_loaded, &os->rx_fragments,
3346 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3347 pf->offset_loaded, &os->rx_oversize,
3349 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3350 pf->offset_loaded, &os->rx_jabber,
3352 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3353 I40E_GLPRT_PTC64L(hw->port),
3354 pf->offset_loaded, &os->tx_size_64,
3356 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3357 I40E_GLPRT_PTC127L(hw->port),
3358 pf->offset_loaded, &os->tx_size_127,
3360 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3361 I40E_GLPRT_PTC255L(hw->port),
3362 pf->offset_loaded, &os->tx_size_255,
3364 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3365 I40E_GLPRT_PTC511L(hw->port),
3366 pf->offset_loaded, &os->tx_size_511,
3368 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3369 I40E_GLPRT_PTC1023L(hw->port),
3370 pf->offset_loaded, &os->tx_size_1023,
3372 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3373 I40E_GLPRT_PTC1522L(hw->port),
3374 pf->offset_loaded, &os->tx_size_1522,
3376 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3377 I40E_GLPRT_PTC9522L(hw->port),
3378 pf->offset_loaded, &os->tx_size_big,
3380 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3382 &os->fd_sb_match, &ns->fd_sb_match);
3383 /* GLPRT_MSPDC not supported */
3384 /* GLPRT_XEC not supported */
3386 pf->offset_loaded = true;
3389 i40e_update_vsi_stats(pf->main_vsi);
3392 /* Get all statistics of a port */
3394 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3396 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3397 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3398 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3399 struct i40e_vsi *vsi;
3402 /* call read registers - updates values, now write them to struct */
3403 i40e_read_stats_registers(pf, hw);
3405 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3406 pf->main_vsi->eth_stats.rx_multicast +
3407 pf->main_vsi->eth_stats.rx_broadcast -
3408 pf->main_vsi->eth_stats.rx_discards -
3410 stats->opackets = ns->eth.tx_unicast +
3411 ns->eth.tx_multicast +
3412 ns->eth.tx_broadcast;
3413 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes;
3414 stats->obytes = ns->eth.tx_bytes;
3415 stats->oerrors = ns->eth.tx_errors +
3416 pf->main_vsi->eth_stats.tx_errors;
3419 stats->imissed = ns->eth.rx_discards +
3420 pf->main_vsi->eth_stats.rx_discards;
3421 stats->ierrors = ns->crc_errors +
3422 ns->rx_length_errors + ns->rx_undersize +
3423 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber +
3427 for (i = 0; i < pf->vf_num; i++) {
3428 vsi = pf->vfs[i].vsi;
3429 i40e_update_vsi_stats(vsi);
3431 stats->ipackets += (vsi->eth_stats.rx_unicast +
3432 vsi->eth_stats.rx_multicast +
3433 vsi->eth_stats.rx_broadcast -
3434 vsi->eth_stats.rx_discards);
3435 stats->ibytes += vsi->eth_stats.rx_bytes;
3436 stats->oerrors += vsi->eth_stats.tx_errors;
3437 stats->imissed += vsi->eth_stats.rx_discards;
3441 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3442 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
3443 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
3444 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
3445 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
3446 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
3447 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3448 ns->eth.rx_unknown_protocol);
3449 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
3450 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
3451 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
3452 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
3453 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
3454 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
3456 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
3457 ns->tx_dropped_link_down);
3458 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
3459 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
3461 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
3462 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
3463 ns->mac_local_faults);
3464 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
3465 ns->mac_remote_faults);
3466 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
3467 ns->rx_length_errors);
3468 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
3469 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
3470 for (i = 0; i < 8; i++) {
3471 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
3472 i, ns->priority_xon_rx[i]);
3473 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
3474 i, ns->priority_xoff_rx[i]);
3476 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
3477 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
3478 for (i = 0; i < 8; i++) {
3479 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
3480 i, ns->priority_xon_tx[i]);
3481 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
3482 i, ns->priority_xoff_tx[i]);
3483 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
3484 i, ns->priority_xon_2_xoff[i]);
3486 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
3487 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
3488 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
3489 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
3490 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
3491 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
3492 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
3493 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
3494 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
3495 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
3496 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
3497 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
3498 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
3499 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
3500 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
3501 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
3502 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
3503 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
3504 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3505 ns->mac_short_packet_dropped);
3506 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
3507 ns->checksum_error);
3508 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
3509 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3513 /* Reset the statistics */
3515 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3517 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3518 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3520 /* Mark PF and VSI stats to update the offset, aka "reset" */
3521 pf->offset_loaded = false;
3523 pf->main_vsi->offset_loaded = false;
3525 /* read the stats, reading current register values into offset */
3526 i40e_read_stats_registers(pf, hw);
3532 i40e_xstats_calc_num(void)
3534 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3535 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3536 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3539 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3540 struct rte_eth_xstat_name *xstats_names,
3541 __rte_unused unsigned limit)
3546 if (xstats_names == NULL)
3547 return i40e_xstats_calc_num();
3549 /* Note: limit checked in rte_eth_xstats_names() */
3551 /* Get stats from i40e_eth_stats struct */
3552 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3553 strlcpy(xstats_names[count].name,
3554 rte_i40e_stats_strings[i].name,
3555 sizeof(xstats_names[count].name));
3559 /* Get individiual stats from i40e_hw_port struct */
3560 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3561 strlcpy(xstats_names[count].name,
3562 rte_i40e_hw_port_strings[i].name,
3563 sizeof(xstats_names[count].name));
3567 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3568 for (prio = 0; prio < 8; prio++) {
3569 snprintf(xstats_names[count].name,
3570 sizeof(xstats_names[count].name),
3571 "rx_priority%u_%s", prio,
3572 rte_i40e_rxq_prio_strings[i].name);
3577 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3578 for (prio = 0; prio < 8; prio++) {
3579 snprintf(xstats_names[count].name,
3580 sizeof(xstats_names[count].name),
3581 "tx_priority%u_%s", prio,
3582 rte_i40e_txq_prio_strings[i].name);
3590 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3593 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3594 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3595 unsigned i, count, prio;
3596 struct i40e_hw_port_stats *hw_stats = &pf->stats;
3598 count = i40e_xstats_calc_num();
3602 i40e_read_stats_registers(pf, hw);
3609 /* Get stats from i40e_eth_stats struct */
3610 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3611 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3612 rte_i40e_stats_strings[i].offset);
3613 xstats[count].id = count;
3617 /* Get individiual stats from i40e_hw_port struct */
3618 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3619 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3620 rte_i40e_hw_port_strings[i].offset);
3621 xstats[count].id = count;
3625 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3626 for (prio = 0; prio < 8; prio++) {
3627 xstats[count].value =
3628 *(uint64_t *)(((char *)hw_stats) +
3629 rte_i40e_rxq_prio_strings[i].offset +
3630 (sizeof(uint64_t) * prio));
3631 xstats[count].id = count;
3636 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3637 for (prio = 0; prio < 8; prio++) {
3638 xstats[count].value =
3639 *(uint64_t *)(((char *)hw_stats) +
3640 rte_i40e_txq_prio_strings[i].offset +
3641 (sizeof(uint64_t) * prio));
3642 xstats[count].id = count;
3651 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3653 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3659 full_ver = hw->nvm.oem_ver;
3660 ver = (u8)(full_ver >> 24);
3661 build = (u16)((full_ver >> 8) & 0xffff);
3662 patch = (u8)(full_ver & 0xff);
3664 ret = snprintf(fw_version, fw_size,
3665 "%d.%d%d 0x%08x %d.%d.%d",
3666 ((hw->nvm.version >> 12) & 0xf),
3667 ((hw->nvm.version >> 4) & 0xff),
3668 (hw->nvm.version & 0xf), hw->nvm.eetrack,
3673 ret += 1; /* add the size of '\0' */
3674 if (fw_size < (size_t)ret)
3681 * When using NVM 6.01(for X710 XL710 XXV710)/3.33(for X722) or later,
3682 * the Rx data path does not hang if the FW LLDP is stopped.
3683 * return true if lldp need to stop
3684 * return false if we cannot disable the LLDP to avoid Rx data path blocking.
3687 i40e_need_stop_lldp(struct rte_eth_dev *dev)
3690 char ver_str[64] = {0};
3691 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3693 i40e_fw_version_get(dev, ver_str, 64);
3694 nvm_ver = atof(ver_str);
3695 if ((hw->mac.type == I40E_MAC_X722 ||
3696 hw->mac.type == I40E_MAC_X722_VF) &&
3697 ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(3.33 * 1000)))
3699 else if ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(6.01 * 1000))
3706 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3708 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3709 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3710 struct i40e_vsi *vsi = pf->main_vsi;
3711 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3713 dev_info->max_rx_queues = vsi->nb_qps;
3714 dev_info->max_tx_queues = vsi->nb_qps;
3715 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3716 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3717 dev_info->max_mac_addrs = vsi->max_macaddrs;
3718 dev_info->max_vfs = pci_dev->max_vfs;
3719 dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
3720 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3721 dev_info->rx_queue_offload_capa = 0;
3722 dev_info->rx_offload_capa =
3723 DEV_RX_OFFLOAD_VLAN_STRIP |
3724 DEV_RX_OFFLOAD_QINQ_STRIP |
3725 DEV_RX_OFFLOAD_IPV4_CKSUM |
3726 DEV_RX_OFFLOAD_UDP_CKSUM |
3727 DEV_RX_OFFLOAD_TCP_CKSUM |
3728 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3729 DEV_RX_OFFLOAD_KEEP_CRC |
3730 DEV_RX_OFFLOAD_SCATTER |
3731 DEV_RX_OFFLOAD_VLAN_EXTEND |
3732 DEV_RX_OFFLOAD_VLAN_FILTER |
3733 DEV_RX_OFFLOAD_JUMBO_FRAME |
3734 DEV_RX_OFFLOAD_RSS_HASH;
3736 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3737 dev_info->tx_offload_capa =
3738 DEV_TX_OFFLOAD_VLAN_INSERT |
3739 DEV_TX_OFFLOAD_QINQ_INSERT |
3740 DEV_TX_OFFLOAD_IPV4_CKSUM |
3741 DEV_TX_OFFLOAD_UDP_CKSUM |
3742 DEV_TX_OFFLOAD_TCP_CKSUM |
3743 DEV_TX_OFFLOAD_SCTP_CKSUM |
3744 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3745 DEV_TX_OFFLOAD_TCP_TSO |
3746 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3747 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3748 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3749 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3750 DEV_TX_OFFLOAD_MULTI_SEGS |
3751 dev_info->tx_queue_offload_capa;
3752 dev_info->dev_capa =
3753 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3754 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3756 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3758 dev_info->reta_size = pf->hash_lut_size;
3759 dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3761 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3763 .pthresh = I40E_DEFAULT_RX_PTHRESH,
3764 .hthresh = I40E_DEFAULT_RX_HTHRESH,
3765 .wthresh = I40E_DEFAULT_RX_WTHRESH,
3767 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3772 dev_info->default_txconf = (struct rte_eth_txconf) {
3774 .pthresh = I40E_DEFAULT_TX_PTHRESH,
3775 .hthresh = I40E_DEFAULT_TX_HTHRESH,
3776 .wthresh = I40E_DEFAULT_TX_WTHRESH,
3778 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3779 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3783 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3784 .nb_max = I40E_MAX_RING_DESC,
3785 .nb_min = I40E_MIN_RING_DESC,
3786 .nb_align = I40E_ALIGN_RING_DESC,
3789 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3790 .nb_max = I40E_MAX_RING_DESC,
3791 .nb_min = I40E_MIN_RING_DESC,
3792 .nb_align = I40E_ALIGN_RING_DESC,
3793 .nb_seg_max = I40E_TX_MAX_SEG,
3794 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3797 if (pf->flags & I40E_FLAG_VMDQ) {
3798 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3799 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3800 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3801 pf->max_nb_vmdq_vsi;
3802 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3803 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3804 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3807 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3809 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3810 dev_info->default_rxportconf.nb_queues = 2;
3811 dev_info->default_txportconf.nb_queues = 2;
3812 if (dev->data->nb_rx_queues == 1)
3813 dev_info->default_rxportconf.ring_size = 2048;
3815 dev_info->default_rxportconf.ring_size = 1024;
3816 if (dev->data->nb_tx_queues == 1)
3817 dev_info->default_txportconf.ring_size = 1024;
3819 dev_info->default_txportconf.ring_size = 512;
3821 } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3823 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3824 dev_info->default_rxportconf.nb_queues = 1;
3825 dev_info->default_txportconf.nb_queues = 1;
3826 dev_info->default_rxportconf.ring_size = 256;
3827 dev_info->default_txportconf.ring_size = 256;
3830 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3831 dev_info->default_rxportconf.nb_queues = 1;
3832 dev_info->default_txportconf.nb_queues = 1;
3833 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3834 dev_info->default_rxportconf.ring_size = 512;
3835 dev_info->default_txportconf.ring_size = 256;
3837 dev_info->default_rxportconf.ring_size = 256;
3838 dev_info->default_txportconf.ring_size = 256;
3841 dev_info->default_rxportconf.burst_size = 32;
3842 dev_info->default_txportconf.burst_size = 32;
3848 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3850 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3851 struct i40e_vsi *vsi = pf->main_vsi;
3852 PMD_INIT_FUNC_TRACE();
3855 return i40e_vsi_add_vlan(vsi, vlan_id);
3857 return i40e_vsi_delete_vlan(vsi, vlan_id);
3861 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3862 enum rte_vlan_type vlan_type,
3863 uint16_t tpid, int qinq)
3865 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3868 uint16_t reg_id = 3;
3872 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3876 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3878 if (ret != I40E_SUCCESS) {
3880 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3885 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3888 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3889 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3890 if (reg_r == reg_w) {
3891 PMD_DRV_LOG(DEBUG, "No need to write");
3895 ret = i40e_aq_debug_write_global_register(hw,
3896 I40E_GL_SWT_L2TAGCTRL(reg_id),
3898 if (ret != I40E_SUCCESS) {
3900 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3905 "Global register 0x%08x is changed with value 0x%08x",
3906 I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3912 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3913 enum rte_vlan_type vlan_type,
3916 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3917 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3918 int qinq = dev->data->dev_conf.rxmode.offloads &
3919 DEV_RX_OFFLOAD_VLAN_EXTEND;
3922 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3923 vlan_type != ETH_VLAN_TYPE_OUTER) ||
3924 (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3926 "Unsupported vlan type.");
3930 if (pf->support_multi_driver) {
3931 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3935 /* 802.1ad frames ability is added in NVM API 1.7*/
3936 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3938 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3939 hw->first_tag = rte_cpu_to_le_16(tpid);
3940 else if (vlan_type == ETH_VLAN_TYPE_INNER)
3941 hw->second_tag = rte_cpu_to_le_16(tpid);
3943 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3944 hw->second_tag = rte_cpu_to_le_16(tpid);
3946 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL);
3947 if (ret != I40E_SUCCESS) {
3949 "Set switch config failed aq_err: %d",
3950 hw->aq.asq_last_status);
3954 /* If NVM API < 1.7, keep the register setting */
3955 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3961 /* Configure outer vlan stripping on or off in QinQ mode */
3963 i40e_vsi_config_outer_vlan_stripping(struct i40e_vsi *vsi, bool on)
3965 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3966 int ret = I40E_SUCCESS;
3969 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
3970 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
3974 /* Configure for outer VLAN RX stripping */
3975 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
3978 reg |= I40E_VSI_TSR_QINQ_STRIP;
3980 reg &= ~I40E_VSI_TSR_QINQ_STRIP;
3982 ret = i40e_aq_debug_write_register(hw,
3983 I40E_VSI_TSR(vsi->vsi_id),
3986 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
3988 return I40E_ERR_CONFIG;
3995 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3997 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3998 struct i40e_vsi *vsi = pf->main_vsi;
3999 struct rte_eth_rxmode *rxmode;
4001 rxmode = &dev->data->dev_conf.rxmode;
4002 if (mask & ETH_VLAN_FILTER_MASK) {
4003 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4004 i40e_vsi_config_vlan_filter(vsi, TRUE);
4006 i40e_vsi_config_vlan_filter(vsi, FALSE);
4009 if (mask & ETH_VLAN_STRIP_MASK) {
4010 /* Enable or disable VLAN stripping */
4011 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
4012 i40e_vsi_config_vlan_stripping(vsi, TRUE);
4014 i40e_vsi_config_vlan_stripping(vsi, FALSE);
4017 if (mask & ETH_VLAN_EXTEND_MASK) {
4018 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
4019 i40e_vsi_config_double_vlan(vsi, TRUE);
4020 /* Set global registers with default ethertype. */
4021 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
4022 RTE_ETHER_TYPE_VLAN);
4023 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
4024 RTE_ETHER_TYPE_VLAN);
4027 i40e_vsi_config_double_vlan(vsi, FALSE);
4030 if (mask & ETH_QINQ_STRIP_MASK) {
4031 /* Enable or disable outer VLAN stripping */
4032 if (rxmode->offloads & DEV_RX_OFFLOAD_QINQ_STRIP)
4033 i40e_vsi_config_outer_vlan_stripping(vsi, TRUE);
4035 i40e_vsi_config_outer_vlan_stripping(vsi, FALSE);
4042 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
4043 __rte_unused uint16_t queue,
4044 __rte_unused int on)
4046 PMD_INIT_FUNC_TRACE();
4050 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
4052 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4053 struct i40e_vsi *vsi = pf->main_vsi;
4054 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
4055 struct i40e_vsi_vlan_pvid_info info;
4057 memset(&info, 0, sizeof(info));
4060 info.config.pvid = pvid;
4062 info.config.reject.tagged =
4063 data->dev_conf.txmode.hw_vlan_reject_tagged;
4064 info.config.reject.untagged =
4065 data->dev_conf.txmode.hw_vlan_reject_untagged;
4068 return i40e_vsi_vlan_pvid_set(vsi, &info);
4072 i40e_dev_led_on(struct rte_eth_dev *dev)
4074 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4075 uint32_t mode = i40e_led_get(hw);
4078 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
4084 i40e_dev_led_off(struct rte_eth_dev *dev)
4086 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4087 uint32_t mode = i40e_led_get(hw);
4090 i40e_led_set(hw, 0, false);
4096 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4098 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4099 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4101 fc_conf->pause_time = pf->fc_conf.pause_time;
4103 /* read out from register, in case they are modified by other port */
4104 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
4105 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
4106 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
4107 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
4109 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
4110 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
4112 /* Return current mode according to actual setting*/
4113 switch (hw->fc.current_mode) {
4115 fc_conf->mode = RTE_FC_FULL;
4117 case I40E_FC_TX_PAUSE:
4118 fc_conf->mode = RTE_FC_TX_PAUSE;
4120 case I40E_FC_RX_PAUSE:
4121 fc_conf->mode = RTE_FC_RX_PAUSE;
4125 fc_conf->mode = RTE_FC_NONE;
4132 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4134 uint32_t mflcn_reg, fctrl_reg, reg;
4135 uint32_t max_high_water;
4136 uint8_t i, aq_failure;
4140 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
4141 [RTE_FC_NONE] = I40E_FC_NONE,
4142 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
4143 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
4144 [RTE_FC_FULL] = I40E_FC_FULL
4147 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
4149 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
4150 if ((fc_conf->high_water > max_high_water) ||
4151 (fc_conf->high_water < fc_conf->low_water)) {
4153 "Invalid high/low water setup value in KB, High_water must be <= %d.",
4158 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4159 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4160 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
4162 pf->fc_conf.pause_time = fc_conf->pause_time;
4163 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
4164 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
4166 PMD_INIT_FUNC_TRACE();
4168 /* All the link flow control related enable/disable register
4169 * configuration is handle by the F/W
4171 err = i40e_set_fc(hw, &aq_failure, true);
4175 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
4176 /* Configure flow control refresh threshold,
4177 * the value for stat_tx_pause_refresh_timer[8]
4178 * is used for global pause operation.
4182 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
4183 pf->fc_conf.pause_time);
4185 /* configure the timer value included in transmitted pause
4187 * the value for stat_tx_pause_quanta[8] is used for global
4190 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
4191 pf->fc_conf.pause_time);
4193 fctrl_reg = I40E_READ_REG(hw,
4194 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
4196 if (fc_conf->mac_ctrl_frame_fwd != 0)
4197 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
4199 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
4201 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
4204 /* Configure pause time (2 TCs per register) */
4205 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
4206 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
4207 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
4209 /* Configure flow control refresh threshold value */
4210 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
4211 pf->fc_conf.pause_time / 2);
4213 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4215 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
4216 *depending on configuration
4218 if (fc_conf->mac_ctrl_frame_fwd != 0) {
4219 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
4220 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
4222 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
4223 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
4226 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
4229 if (!pf->support_multi_driver) {
4230 /* config water marker both based on the packets and bytes */
4231 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
4232 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4233 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4234 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
4235 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4236 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4237 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
4238 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4240 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
4241 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4245 "Water marker configuration is not supported.");
4248 I40E_WRITE_FLUSH(hw);
4254 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
4255 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
4257 PMD_INIT_FUNC_TRACE();
4262 /* Add a MAC address, and update filters */
4264 i40e_macaddr_add(struct rte_eth_dev *dev,
4265 struct rte_ether_addr *mac_addr,
4266 __rte_unused uint32_t index,
4269 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4270 struct i40e_mac_filter_info mac_filter;
4271 struct i40e_vsi *vsi;
4272 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
4275 /* If VMDQ not enabled or configured, return */
4276 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
4277 !pf->nb_cfg_vmdq_vsi)) {
4278 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
4279 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
4284 if (pool > pf->nb_cfg_vmdq_vsi) {
4285 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
4286 pool, pf->nb_cfg_vmdq_vsi);
4290 rte_memcpy(&mac_filter.mac_addr, mac_addr, RTE_ETHER_ADDR_LEN);
4291 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4292 mac_filter.filter_type = I40E_MACVLAN_PERFECT_MATCH;
4294 mac_filter.filter_type = I40E_MAC_PERFECT_MATCH;
4299 vsi = pf->vmdq[pool - 1].vsi;
4301 ret = i40e_vsi_add_mac(vsi, &mac_filter);
4302 if (ret != I40E_SUCCESS) {
4303 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4309 /* Remove a MAC address, and update filters */
4311 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4313 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4314 struct i40e_vsi *vsi;
4315 struct rte_eth_dev_data *data = dev->data;
4316 struct rte_ether_addr *macaddr;
4321 macaddr = &(data->mac_addrs[index]);
4323 pool_sel = dev->data->mac_pool_sel[index];
4325 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4326 if (pool_sel & (1ULL << i)) {
4330 /* No VMDQ pool enabled or configured */
4331 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4332 (i > pf->nb_cfg_vmdq_vsi)) {
4334 "No VMDQ pool enabled/configured");
4337 vsi = pf->vmdq[i - 1].vsi;
4339 ret = i40e_vsi_delete_mac(vsi, macaddr);
4342 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4350 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4352 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4353 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4360 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4361 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id,
4362 vsi->type != I40E_VSI_SRIOV,
4365 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4369 uint32_t *lut_dw = (uint32_t *)lut;
4370 uint16_t i, lut_size_dw = lut_size / 4;
4372 if (vsi->type == I40E_VSI_SRIOV) {
4373 for (i = 0; i <= lut_size_dw; i++) {
4374 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4375 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4378 for (i = 0; i < lut_size_dw; i++)
4379 lut_dw[i] = I40E_READ_REG(hw,
4388 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4396 pf = I40E_VSI_TO_PF(vsi);
4397 hw = I40E_VSI_TO_HW(vsi);
4399 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4400 enum i40e_status_code status;
4402 status = i40e_aq_set_rss_lut(hw, vsi->vsi_id,
4403 vsi->type != I40E_VSI_SRIOV,
4407 "Failed to update RSS lookup table, error status: %d",
4412 uint32_t *lut_dw = (uint32_t *)lut;
4413 uint16_t i, lut_size_dw = lut_size / 4;
4415 if (vsi->type == I40E_VSI_SRIOV) {
4416 for (i = 0; i < lut_size_dw; i++)
4419 I40E_VFQF_HLUT1(i, vsi->user_param),
4422 for (i = 0; i < lut_size_dw; i++)
4423 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4426 I40E_WRITE_FLUSH(hw);
4433 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4434 struct rte_eth_rss_reta_entry64 *reta_conf,
4437 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4438 uint16_t i, lut_size = pf->hash_lut_size;
4439 uint16_t idx, shift;
4443 if (reta_size != lut_size ||
4444 reta_size > ETH_RSS_RETA_SIZE_512) {
4446 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4447 reta_size, lut_size);
4451 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4453 PMD_DRV_LOG(ERR, "No memory can be allocated");
4456 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4459 for (i = 0; i < reta_size; i++) {
4460 idx = i / RTE_RETA_GROUP_SIZE;
4461 shift = i % RTE_RETA_GROUP_SIZE;
4462 if (reta_conf[idx].mask & (1ULL << shift))
4463 lut[i] = reta_conf[idx].reta[shift];
4465 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4467 pf->adapter->rss_reta_updated = 1;
4476 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4477 struct rte_eth_rss_reta_entry64 *reta_conf,
4480 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4481 uint16_t i, lut_size = pf->hash_lut_size;
4482 uint16_t idx, shift;
4486 if (reta_size != lut_size ||
4487 reta_size > ETH_RSS_RETA_SIZE_512) {
4489 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4490 reta_size, lut_size);
4494 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4496 PMD_DRV_LOG(ERR, "No memory can be allocated");
4500 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4503 for (i = 0; i < reta_size; i++) {
4504 idx = i / RTE_RETA_GROUP_SIZE;
4505 shift = i % RTE_RETA_GROUP_SIZE;
4506 if (reta_conf[idx].mask & (1ULL << shift))
4507 reta_conf[idx].reta[shift] = lut[i];
4517 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4518 * @hw: pointer to the HW structure
4519 * @mem: pointer to mem struct to fill out
4520 * @size: size of memory requested
4521 * @alignment: what to align the allocation to
4523 enum i40e_status_code
4524 i40e_allocate_dma_mem_d(__rte_unused struct i40e_hw *hw,
4525 struct i40e_dma_mem *mem,
4529 static uint64_t i40e_dma_memzone_id;
4530 const struct rte_memzone *mz = NULL;
4531 char z_name[RTE_MEMZONE_NAMESIZE];
4534 return I40E_ERR_PARAM;
4536 snprintf(z_name, sizeof(z_name), "i40e_dma_%" PRIu64,
4537 __atomic_fetch_add(&i40e_dma_memzone_id, 1, __ATOMIC_RELAXED));
4538 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4539 RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4541 return I40E_ERR_NO_MEMORY;
4546 mem->zone = (const void *)mz;
4548 "memzone %s allocated with physical address: %"PRIu64,
4551 return I40E_SUCCESS;
4555 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4556 * @hw: pointer to the HW structure
4557 * @mem: ptr to mem struct to free
4559 enum i40e_status_code
4560 i40e_free_dma_mem_d(__rte_unused struct i40e_hw *hw,
4561 struct i40e_dma_mem *mem)
4564 return I40E_ERR_PARAM;
4567 "memzone %s to be freed with physical address: %"PRIu64,
4568 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4569 rte_memzone_free((const struct rte_memzone *)mem->zone);
4574 return I40E_SUCCESS;
4578 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4579 * @hw: pointer to the HW structure
4580 * @mem: pointer to mem struct to fill out
4581 * @size: size of memory requested
4583 enum i40e_status_code
4584 i40e_allocate_virt_mem_d(__rte_unused struct i40e_hw *hw,
4585 struct i40e_virt_mem *mem,
4589 return I40E_ERR_PARAM;
4592 mem->va = rte_zmalloc("i40e", size, 0);
4595 return I40E_SUCCESS;
4597 return I40E_ERR_NO_MEMORY;
4601 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4602 * @hw: pointer to the HW structure
4603 * @mem: pointer to mem struct to free
4605 enum i40e_status_code
4606 i40e_free_virt_mem_d(__rte_unused struct i40e_hw *hw,
4607 struct i40e_virt_mem *mem)
4610 return I40E_ERR_PARAM;
4615 return I40E_SUCCESS;
4619 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4621 rte_spinlock_init(&sp->spinlock);
4625 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4627 rte_spinlock_lock(&sp->spinlock);
4631 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4633 rte_spinlock_unlock(&sp->spinlock);
4637 i40e_destroy_spinlock_d(__rte_unused struct i40e_spinlock *sp)
4643 * Get the hardware capabilities, which will be parsed
4644 * and saved into struct i40e_hw.
4647 i40e_get_cap(struct i40e_hw *hw)
4649 struct i40e_aqc_list_capabilities_element_resp *buf;
4650 uint16_t len, size = 0;
4653 /* Calculate a huge enough buff for saving response data temporarily */
4654 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4655 I40E_MAX_CAP_ELE_NUM;
4656 buf = rte_zmalloc("i40e", len, 0);
4658 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4659 return I40E_ERR_NO_MEMORY;
4662 /* Get, parse the capabilities and save it to hw */
4663 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4664 i40e_aqc_opc_list_func_capabilities, NULL);
4665 if (ret != I40E_SUCCESS)
4666 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4668 /* Free the temporary buffer after being used */
4674 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4
4676 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4684 pf = (struct i40e_pf *)opaque;
4688 num = strtoul(value, &end, 0);
4689 if (errno != 0 || end == value || *end != 0) {
4690 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4691 "kept the value = %hu", value, pf->vf_nb_qp_max);
4695 if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4696 pf->vf_nb_qp_max = (uint16_t)num;
4698 /* here return 0 to make next valid same argument work */
4699 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4700 "power of 2 and equal or less than 16 !, Now it is "
4701 "kept the value = %hu", num, pf->vf_nb_qp_max);
4706 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4708 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4709 struct rte_kvargs *kvlist;
4712 /* set default queue number per VF as 4 */
4713 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4715 if (dev->device->devargs == NULL)
4718 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4722 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4723 if (!kvargs_count) {
4724 rte_kvargs_free(kvlist);
4728 if (kvargs_count > 1)
4729 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4730 "the first invalid or last valid one is used !",
4731 ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4733 rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4734 i40e_pf_parse_vf_queue_number_handler, pf);
4736 rte_kvargs_free(kvlist);
4742 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4744 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4745 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4746 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4747 uint16_t qp_count = 0, vsi_count = 0;
4749 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4750 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4754 i40e_pf_config_vf_rxq_number(dev);
4756 /* Add the parameter init for LFC */
4757 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4758 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4759 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4761 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4762 pf->max_num_vsi = hw->func_caps.num_vsis;
4763 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4764 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4766 /* FDir queue/VSI allocation */
4767 pf->fdir_qp_offset = 0;
4768 if (hw->func_caps.fd) {
4769 pf->flags |= I40E_FLAG_FDIR;
4770 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4772 pf->fdir_nb_qps = 0;
4774 qp_count += pf->fdir_nb_qps;
4777 /* LAN queue/VSI allocation */
4778 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4779 if (!hw->func_caps.rss) {
4782 pf->flags |= I40E_FLAG_RSS;
4783 if (hw->mac.type == I40E_MAC_X722)
4784 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4785 pf->lan_nb_qps = pf->lan_nb_qp_max;
4787 qp_count += pf->lan_nb_qps;
4790 /* VF queue/VSI allocation */
4791 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4792 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4793 pf->flags |= I40E_FLAG_SRIOV;
4794 pf->vf_nb_qps = pf->vf_nb_qp_max;
4795 pf->vf_num = pci_dev->max_vfs;
4797 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4798 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4803 qp_count += pf->vf_nb_qps * pf->vf_num;
4804 vsi_count += pf->vf_num;
4806 /* VMDq queue/VSI allocation */
4807 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4808 pf->vmdq_nb_qps = 0;
4809 pf->max_nb_vmdq_vsi = 0;
4810 if (hw->func_caps.vmdq) {
4811 if (qp_count < hw->func_caps.num_tx_qp &&
4812 vsi_count < hw->func_caps.num_vsis) {
4813 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4814 qp_count) / pf->vmdq_nb_qp_max;
4816 /* Limit the maximum number of VMDq vsi to the maximum
4817 * ethdev can support
4819 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4820 hw->func_caps.num_vsis - vsi_count);
4821 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4823 if (pf->max_nb_vmdq_vsi) {
4824 pf->flags |= I40E_FLAG_VMDQ;
4825 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4827 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4828 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4829 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4832 "No enough queues left for VMDq");
4835 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4838 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4839 vsi_count += pf->max_nb_vmdq_vsi;
4841 if (hw->func_caps.dcb)
4842 pf->flags |= I40E_FLAG_DCB;
4844 if (qp_count > hw->func_caps.num_tx_qp) {
4846 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4847 qp_count, hw->func_caps.num_tx_qp);
4850 if (vsi_count > hw->func_caps.num_vsis) {
4852 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4853 vsi_count, hw->func_caps.num_vsis);
4861 i40e_pf_get_switch_config(struct i40e_pf *pf)
4863 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4864 struct i40e_aqc_get_switch_config_resp *switch_config;
4865 struct i40e_aqc_switch_config_element_resp *element;
4866 uint16_t start_seid = 0, num_reported;
4869 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4870 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4871 if (!switch_config) {
4872 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4876 /* Get the switch configurations */
4877 ret = i40e_aq_get_switch_config(hw, switch_config,
4878 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4879 if (ret != I40E_SUCCESS) {
4880 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4883 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4884 if (num_reported != 1) { /* The number should be 1 */
4885 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4889 /* Parse the switch configuration elements */
4890 element = &(switch_config->element[0]);
4891 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4892 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4893 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4895 PMD_DRV_LOG(INFO, "Unknown element type");
4898 rte_free(switch_config);
4904 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4907 struct pool_entry *entry;
4909 if (pool == NULL || num == 0)
4912 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4913 if (entry == NULL) {
4914 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4918 /* queue heap initialize */
4919 pool->num_free = num;
4920 pool->num_alloc = 0;
4922 LIST_INIT(&pool->alloc_list);
4923 LIST_INIT(&pool->free_list);
4925 /* Initialize element */
4929 LIST_INSERT_HEAD(&pool->free_list, entry, next);
4934 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4936 struct pool_entry *entry, *next_entry;
4941 for (entry = LIST_FIRST(&pool->alloc_list);
4942 entry && (next_entry = LIST_NEXT(entry, next), 1);
4943 entry = next_entry) {
4944 LIST_REMOVE(entry, next);
4948 for (entry = LIST_FIRST(&pool->free_list);
4949 entry && (next_entry = LIST_NEXT(entry, next), 1);
4950 entry = next_entry) {
4951 LIST_REMOVE(entry, next);
4956 pool->num_alloc = 0;
4958 LIST_INIT(&pool->alloc_list);
4959 LIST_INIT(&pool->free_list);
4963 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4966 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4967 uint32_t pool_offset;
4972 PMD_DRV_LOG(ERR, "Invalid parameter");
4976 pool_offset = base - pool->base;
4977 /* Lookup in alloc list */
4978 LIST_FOREACH(entry, &pool->alloc_list, next) {
4979 if (entry->base == pool_offset) {
4980 valid_entry = entry;
4981 LIST_REMOVE(entry, next);
4986 /* Not find, return */
4987 if (valid_entry == NULL) {
4988 PMD_DRV_LOG(ERR, "Failed to find entry");
4993 * Found it, move it to free list and try to merge.
4994 * In order to make merge easier, always sort it by qbase.
4995 * Find adjacent prev and last entries.
4998 LIST_FOREACH(entry, &pool->free_list, next) {
4999 if (entry->base > valid_entry->base) {
5007 len = valid_entry->len;
5008 /* Try to merge with next one*/
5010 /* Merge with next one */
5011 if (valid_entry->base + len == next->base) {
5012 next->base = valid_entry->base;
5014 rte_free(valid_entry);
5021 /* Merge with previous one */
5022 if (prev->base + prev->len == valid_entry->base) {
5024 /* If it merge with next one, remove next node */
5026 LIST_REMOVE(valid_entry, next);
5027 rte_free(valid_entry);
5030 rte_free(valid_entry);
5037 /* Not find any entry to merge, insert */
5040 LIST_INSERT_AFTER(prev, valid_entry, next);
5041 else if (next != NULL)
5042 LIST_INSERT_BEFORE(next, valid_entry, next);
5043 else /* It's empty list, insert to head */
5044 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
5047 pool->num_free += len;
5048 pool->num_alloc -= len;
5054 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
5057 struct pool_entry *entry, *valid_entry;
5059 if (pool == NULL || num == 0) {
5060 PMD_DRV_LOG(ERR, "Invalid parameter");
5064 if (pool->num_free < num) {
5065 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
5066 num, pool->num_free);
5071 /* Lookup in free list and find most fit one */
5072 LIST_FOREACH(entry, &pool->free_list, next) {
5073 if (entry->len >= num) {
5075 if (entry->len == num) {
5076 valid_entry = entry;
5079 if (valid_entry == NULL || valid_entry->len > entry->len)
5080 valid_entry = entry;
5084 /* Not find one to satisfy the request, return */
5085 if (valid_entry == NULL) {
5086 PMD_DRV_LOG(ERR, "No valid entry found");
5090 * The entry have equal queue number as requested,
5091 * remove it from alloc_list.
5093 if (valid_entry->len == num) {
5094 LIST_REMOVE(valid_entry, next);
5097 * The entry have more numbers than requested,
5098 * create a new entry for alloc_list and minus its
5099 * queue base and number in free_list.
5101 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
5102 if (entry == NULL) {
5104 "Failed to allocate memory for resource pool");
5107 entry->base = valid_entry->base;
5109 valid_entry->base += num;
5110 valid_entry->len -= num;
5111 valid_entry = entry;
5114 /* Insert it into alloc list, not sorted */
5115 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
5117 pool->num_free -= valid_entry->len;
5118 pool->num_alloc += valid_entry->len;
5120 return valid_entry->base + pool->base;
5124 * bitmap_is_subset - Check whether src2 is subset of src1
5127 bitmap_is_subset(uint8_t src1, uint8_t src2)
5129 return !((src1 ^ src2) & src2);
5132 static enum i40e_status_code
5133 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5135 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5137 /* If DCB is not supported, only default TC is supported */
5138 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
5139 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
5140 return I40E_NOT_SUPPORTED;
5143 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
5145 "Enabled TC map 0x%x not applicable to HW support 0x%x",
5146 hw->func_caps.enabled_tcmap, enabled_tcmap);
5147 return I40E_NOT_SUPPORTED;
5149 return I40E_SUCCESS;
5153 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
5154 struct i40e_vsi_vlan_pvid_info *info)
5157 struct i40e_vsi_context ctxt;
5158 uint8_t vlan_flags = 0;
5161 if (vsi == NULL || info == NULL) {
5162 PMD_DRV_LOG(ERR, "invalid parameters");
5163 return I40E_ERR_PARAM;
5167 vsi->info.pvid = info->config.pvid;
5169 * If insert pvid is enabled, only tagged pkts are
5170 * allowed to be sent out.
5172 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
5173 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5176 if (info->config.reject.tagged == 0)
5177 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5179 if (info->config.reject.untagged == 0)
5180 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
5182 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
5183 I40E_AQ_VSI_PVLAN_MODE_MASK);
5184 vsi->info.port_vlan_flags |= vlan_flags;
5185 vsi->info.valid_sections =
5186 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5187 memset(&ctxt, 0, sizeof(ctxt));
5188 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5189 ctxt.seid = vsi->seid;
5191 hw = I40E_VSI_TO_HW(vsi);
5192 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5193 if (ret != I40E_SUCCESS)
5194 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5200 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5202 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5204 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
5206 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5207 if (ret != I40E_SUCCESS)
5211 PMD_DRV_LOG(ERR, "seid not valid");
5215 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
5216 tc_bw_data.tc_valid_bits = enabled_tcmap;
5217 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5218 tc_bw_data.tc_bw_credits[i] =
5219 (enabled_tcmap & (1 << i)) ? 1 : 0;
5221 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5222 if (ret != I40E_SUCCESS) {
5223 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5227 rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5228 sizeof(vsi->info.qs_handle));
5229 return I40E_SUCCESS;
5232 static enum i40e_status_code
5233 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5234 struct i40e_aqc_vsi_properties_data *info,
5235 uint8_t enabled_tcmap)
5237 enum i40e_status_code ret;
5238 int i, total_tc = 0;
5239 uint16_t qpnum_per_tc, bsf, qp_idx;
5241 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5242 if (ret != I40E_SUCCESS)
5245 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5246 if (enabled_tcmap & (1 << i))
5250 vsi->enabled_tc = enabled_tcmap;
5252 /* Number of queues per enabled TC */
5253 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5254 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5255 bsf = rte_bsf32(qpnum_per_tc);
5257 /* Adjust the queue number to actual queues that can be applied */
5258 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5259 vsi->nb_qps = qpnum_per_tc * total_tc;
5262 * Configure TC and queue mapping parameters, for enabled TC,
5263 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5264 * default queue will serve it.
5267 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5268 if (vsi->enabled_tc & (1 << i)) {
5269 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5270 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5271 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5272 qp_idx += qpnum_per_tc;
5274 info->tc_mapping[i] = 0;
5277 /* Associate queue number with VSI */
5278 if (vsi->type == I40E_VSI_SRIOV) {
5279 info->mapping_flags |=
5280 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5281 for (i = 0; i < vsi->nb_qps; i++)
5282 info->queue_mapping[i] =
5283 rte_cpu_to_le_16(vsi->base_queue + i);
5285 info->mapping_flags |=
5286 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5287 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5289 info->valid_sections |=
5290 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5292 return I40E_SUCCESS;
5296 i40e_veb_release(struct i40e_veb *veb)
5298 struct i40e_vsi *vsi;
5304 if (!TAILQ_EMPTY(&veb->head)) {
5305 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5308 /* associate_vsi field is NULL for floating VEB */
5309 if (veb->associate_vsi != NULL) {
5310 vsi = veb->associate_vsi;
5311 hw = I40E_VSI_TO_HW(vsi);
5313 vsi->uplink_seid = veb->uplink_seid;
5316 veb->associate_pf->main_vsi->floating_veb = NULL;
5317 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5320 i40e_aq_delete_element(hw, veb->seid, NULL);
5322 return I40E_SUCCESS;
5326 static struct i40e_veb *
5327 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5329 struct i40e_veb *veb;
5335 "veb setup failed, associated PF shouldn't null");
5338 hw = I40E_PF_TO_HW(pf);
5340 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5342 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5346 veb->associate_vsi = vsi;
5347 veb->associate_pf = pf;
5348 TAILQ_INIT(&veb->head);
5349 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5351 /* create floating veb if vsi is NULL */
5353 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5354 I40E_DEFAULT_TCMAP, false,
5355 &veb->seid, false, NULL);
5357 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5358 true, &veb->seid, false, NULL);
5361 if (ret != I40E_SUCCESS) {
5362 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5363 hw->aq.asq_last_status);
5366 veb->enabled_tc = I40E_DEFAULT_TCMAP;
5368 /* get statistics index */
5369 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5370 &veb->stats_idx, NULL, NULL, NULL);
5371 if (ret != I40E_SUCCESS) {
5372 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5373 hw->aq.asq_last_status);
5376 /* Get VEB bandwidth, to be implemented */
5377 /* Now associated vsi binding to the VEB, set uplink to this VEB */
5379 vsi->uplink_seid = veb->seid;
5388 i40e_vsi_release(struct i40e_vsi *vsi)
5392 struct i40e_vsi_list *vsi_list;
5395 struct i40e_mac_filter *f;
5396 uint16_t user_param;
5399 return I40E_SUCCESS;
5404 user_param = vsi->user_param;
5406 pf = I40E_VSI_TO_PF(vsi);
5407 hw = I40E_VSI_TO_HW(vsi);
5409 /* VSI has child to attach, release child first */
5411 RTE_TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5412 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5415 i40e_veb_release(vsi->veb);
5418 if (vsi->floating_veb) {
5419 RTE_TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head,
5421 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5426 /* Remove all macvlan filters of the VSI */
5427 i40e_vsi_remove_all_macvlan_filter(vsi);
5428 RTE_TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5431 if (vsi->type != I40E_VSI_MAIN &&
5432 ((vsi->type != I40E_VSI_SRIOV) ||
5433 !pf->floating_veb_list[user_param])) {
5434 /* Remove vsi from parent's sibling list */
5435 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5436 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5437 return I40E_ERR_PARAM;
5439 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5440 &vsi->sib_vsi_list, list);
5442 /* Remove all switch element of the VSI */
5443 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5444 if (ret != I40E_SUCCESS)
5445 PMD_DRV_LOG(ERR, "Failed to delete element");
5448 if ((vsi->type == I40E_VSI_SRIOV) &&
5449 pf->floating_veb_list[user_param]) {
5450 /* Remove vsi from parent's sibling list */
5451 if (vsi->parent_vsi == NULL ||
5452 vsi->parent_vsi->floating_veb == NULL) {
5453 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5454 return I40E_ERR_PARAM;
5456 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5457 &vsi->sib_vsi_list, list);
5459 /* Remove all switch element of the VSI */
5460 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5461 if (ret != I40E_SUCCESS)
5462 PMD_DRV_LOG(ERR, "Failed to delete element");
5465 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5467 if (vsi->type != I40E_VSI_SRIOV)
5468 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5471 return I40E_SUCCESS;
5475 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5477 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5478 struct i40e_aqc_remove_macvlan_element_data def_filter;
5479 struct i40e_mac_filter_info filter;
5482 if (vsi->type != I40E_VSI_MAIN)
5483 return I40E_ERR_CONFIG;
5484 memset(&def_filter, 0, sizeof(def_filter));
5485 rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5487 def_filter.vlan_tag = 0;
5488 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5489 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5490 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5491 if (ret != I40E_SUCCESS) {
5492 struct i40e_mac_filter *f;
5493 struct rte_ether_addr *mac;
5496 "Cannot remove the default macvlan filter");
5497 /* It needs to add the permanent mac into mac list */
5498 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5500 PMD_DRV_LOG(ERR, "failed to allocate memory");
5501 return I40E_ERR_NO_MEMORY;
5503 mac = &f->mac_info.mac_addr;
5504 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5506 f->mac_info.filter_type = I40E_MACVLAN_PERFECT_MATCH;
5507 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5512 rte_memcpy(&filter.mac_addr,
5513 (struct rte_ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5514 filter.filter_type = I40E_MACVLAN_PERFECT_MATCH;
5515 return i40e_vsi_add_mac(vsi, &filter);
5519 * i40e_vsi_get_bw_config - Query VSI BW Information
5520 * @vsi: the VSI to be queried
5522 * Returns 0 on success, negative value on failure
5524 static enum i40e_status_code
5525 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5527 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5528 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5529 struct i40e_hw *hw = &vsi->adapter->hw;
5534 memset(&bw_config, 0, sizeof(bw_config));
5535 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5536 if (ret != I40E_SUCCESS) {
5537 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5538 hw->aq.asq_last_status);
5542 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5543 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5544 &ets_sla_config, NULL);
5545 if (ret != I40E_SUCCESS) {
5547 "VSI failed to get TC bandwdith configuration %u",
5548 hw->aq.asq_last_status);
5552 /* store and print out BW info */
5553 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5554 vsi->bw_info.bw_max = bw_config.max_bw;
5555 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5556 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5557 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5558 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5560 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5561 vsi->bw_info.bw_ets_share_credits[i] =
5562 ets_sla_config.share_credits[i];
5563 vsi->bw_info.bw_ets_credits[i] =
5564 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5565 /* 4 bits per TC, 4th bit is reserved */
5566 vsi->bw_info.bw_ets_max[i] =
5567 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5568 RTE_LEN2MASK(3, uint8_t));
5569 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5570 vsi->bw_info.bw_ets_share_credits[i]);
5571 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5572 vsi->bw_info.bw_ets_credits[i]);
5573 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5574 vsi->bw_info.bw_ets_max[i]);
5577 return I40E_SUCCESS;
5580 /* i40e_enable_pf_lb
5581 * @pf: pointer to the pf structure
5583 * allow loopback on pf
5586 i40e_enable_pf_lb(struct i40e_pf *pf)
5588 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5589 struct i40e_vsi_context ctxt;
5592 /* Use the FW API if FW >= v5.0 */
5593 if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
5594 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5598 memset(&ctxt, 0, sizeof(ctxt));
5599 ctxt.seid = pf->main_vsi_seid;
5600 ctxt.pf_num = hw->pf_id;
5601 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5603 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5604 ret, hw->aq.asq_last_status);
5607 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5608 ctxt.info.valid_sections =
5609 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5610 ctxt.info.switch_id |=
5611 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5613 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5615 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5616 hw->aq.asq_last_status);
5621 i40e_vsi_setup(struct i40e_pf *pf,
5622 enum i40e_vsi_type type,
5623 struct i40e_vsi *uplink_vsi,
5624 uint16_t user_param)
5626 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5627 struct i40e_vsi *vsi;
5628 struct i40e_mac_filter_info filter;
5630 struct i40e_vsi_context ctxt;
5631 struct rte_ether_addr broadcast =
5632 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5634 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5635 uplink_vsi == NULL) {
5637 "VSI setup failed, VSI link shouldn't be NULL");
5641 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5643 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5648 * 1.type is not MAIN and uplink vsi is not NULL
5649 * If uplink vsi didn't setup VEB, create one first under veb field
5650 * 2.type is SRIOV and the uplink is NULL
5651 * If floating VEB is NULL, create one veb under floating veb field
5654 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5655 uplink_vsi->veb == NULL) {
5656 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5658 if (uplink_vsi->veb == NULL) {
5659 PMD_DRV_LOG(ERR, "VEB setup failed");
5662 /* set ALLOWLOOPBACk on pf, when veb is created */
5663 i40e_enable_pf_lb(pf);
5666 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5667 pf->main_vsi->floating_veb == NULL) {
5668 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5670 if (pf->main_vsi->floating_veb == NULL) {
5671 PMD_DRV_LOG(ERR, "VEB setup failed");
5676 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5678 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5681 TAILQ_INIT(&vsi->mac_list);
5683 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5684 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5685 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5686 vsi->user_param = user_param;
5687 vsi->vlan_anti_spoof_on = 0;
5688 vsi->vlan_filter_on = 0;
5689 /* Allocate queues */
5690 switch (vsi->type) {
5691 case I40E_VSI_MAIN :
5692 vsi->nb_qps = pf->lan_nb_qps;
5694 case I40E_VSI_SRIOV :
5695 vsi->nb_qps = pf->vf_nb_qps;
5697 case I40E_VSI_VMDQ2:
5698 vsi->nb_qps = pf->vmdq_nb_qps;
5701 vsi->nb_qps = pf->fdir_nb_qps;
5707 * The filter status descriptor is reported in rx queue 0,
5708 * while the tx queue for fdir filter programming has no
5709 * such constraints, can be non-zero queues.
5710 * To simplify it, choose FDIR vsi use queue 0 pair.
5711 * To make sure it will use queue 0 pair, queue allocation
5712 * need be done before this function is called
5714 if (type != I40E_VSI_FDIR) {
5715 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5717 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5721 vsi->base_queue = ret;
5723 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5725 /* VF has MSIX interrupt in VF range, don't allocate here */
5726 if (type == I40E_VSI_MAIN) {
5727 if (pf->support_multi_driver) {
5728 /* If support multi-driver, need to use INT0 instead of
5729 * allocating from msix pool. The Msix pool is init from
5730 * INT1, so it's OK just set msix_intr to 0 and nb_msix
5731 * to 1 without calling i40e_res_pool_alloc.
5736 ret = i40e_res_pool_alloc(&pf->msix_pool,
5737 RTE_MIN(vsi->nb_qps,
5738 RTE_MAX_RXTX_INTR_VEC_ID));
5741 "VSI MAIN %d get heap failed %d",
5743 goto fail_queue_alloc;
5745 vsi->msix_intr = ret;
5746 vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5747 RTE_MAX_RXTX_INTR_VEC_ID);
5749 } else if (type != I40E_VSI_SRIOV) {
5750 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5752 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5753 if (type != I40E_VSI_FDIR)
5754 goto fail_queue_alloc;
5758 vsi->msix_intr = ret;
5767 if (type == I40E_VSI_MAIN) {
5768 /* For main VSI, no need to add since it's default one */
5769 vsi->uplink_seid = pf->mac_seid;
5770 vsi->seid = pf->main_vsi_seid;
5771 /* Bind queues with specific MSIX interrupt */
5773 * Needs 2 interrupt at least, one for misc cause which will
5774 * enabled from OS side, Another for queues binding the
5775 * interrupt from device side only.
5778 /* Get default VSI parameters from hardware */
5779 memset(&ctxt, 0, sizeof(ctxt));
5780 ctxt.seid = vsi->seid;
5781 ctxt.pf_num = hw->pf_id;
5782 ctxt.uplink_seid = vsi->uplink_seid;
5784 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5785 if (ret != I40E_SUCCESS) {
5786 PMD_DRV_LOG(ERR, "Failed to get VSI params");
5787 goto fail_msix_alloc;
5789 rte_memcpy(&vsi->info, &ctxt.info,
5790 sizeof(struct i40e_aqc_vsi_properties_data));
5791 vsi->vsi_id = ctxt.vsi_number;
5792 vsi->info.valid_sections = 0;
5794 /* Configure tc, enabled TC0 only */
5795 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5797 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5798 goto fail_msix_alloc;
5801 /* TC, queue mapping */
5802 memset(&ctxt, 0, sizeof(ctxt));
5803 vsi->info.valid_sections |=
5804 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5805 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5806 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5807 rte_memcpy(&ctxt.info, &vsi->info,
5808 sizeof(struct i40e_aqc_vsi_properties_data));
5809 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5810 I40E_DEFAULT_TCMAP);
5811 if (ret != I40E_SUCCESS) {
5813 "Failed to configure TC queue mapping");
5814 goto fail_msix_alloc;
5816 ctxt.seid = vsi->seid;
5817 ctxt.pf_num = hw->pf_id;
5818 ctxt.uplink_seid = vsi->uplink_seid;
5821 /* Update VSI parameters */
5822 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5823 if (ret != I40E_SUCCESS) {
5824 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5825 goto fail_msix_alloc;
5828 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5829 sizeof(vsi->info.tc_mapping));
5830 rte_memcpy(&vsi->info.queue_mapping,
5831 &ctxt.info.queue_mapping,
5832 sizeof(vsi->info.queue_mapping));
5833 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5834 vsi->info.valid_sections = 0;
5836 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5840 * Updating default filter settings are necessary to prevent
5841 * reception of tagged packets.
5842 * Some old firmware configurations load a default macvlan
5843 * filter which accepts both tagged and untagged packets.
5844 * The updating is to use a normal filter instead if needed.
5845 * For NVM 4.2.2 or after, the updating is not needed anymore.
5846 * The firmware with correct configurations load the default
5847 * macvlan filter which is expected and cannot be removed.
5849 i40e_update_default_filter_setting(vsi);
5850 i40e_config_qinq(hw, vsi);
5851 } else if (type == I40E_VSI_SRIOV) {
5852 memset(&ctxt, 0, sizeof(ctxt));
5854 * For other VSI, the uplink_seid equals to uplink VSI's
5855 * uplink_seid since they share same VEB
5857 if (uplink_vsi == NULL)
5858 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5860 vsi->uplink_seid = uplink_vsi->uplink_seid;
5861 ctxt.pf_num = hw->pf_id;
5862 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5863 ctxt.uplink_seid = vsi->uplink_seid;
5864 ctxt.connection_type = 0x1;
5865 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5867 /* Use the VEB configuration if FW >= v5.0 */
5868 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
5869 /* Configure switch ID */
5870 ctxt.info.valid_sections |=
5871 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5872 ctxt.info.switch_id =
5873 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5876 /* Configure port/vlan */
5877 ctxt.info.valid_sections |=
5878 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5879 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5880 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5881 hw->func_caps.enabled_tcmap);
5882 if (ret != I40E_SUCCESS) {
5884 "Failed to configure TC queue mapping");
5885 goto fail_msix_alloc;
5888 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5889 ctxt.info.valid_sections |=
5890 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5892 * Since VSI is not created yet, only configure parameter,
5893 * will add vsi below.
5896 i40e_config_qinq(hw, vsi);
5897 } else if (type == I40E_VSI_VMDQ2) {
5898 memset(&ctxt, 0, sizeof(ctxt));
5900 * For other VSI, the uplink_seid equals to uplink VSI's
5901 * uplink_seid since they share same VEB
5903 vsi->uplink_seid = uplink_vsi->uplink_seid;
5904 ctxt.pf_num = hw->pf_id;
5906 ctxt.uplink_seid = vsi->uplink_seid;
5907 ctxt.connection_type = 0x1;
5908 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5910 ctxt.info.valid_sections |=
5911 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5912 /* user_param carries flag to enable loop back */
5914 ctxt.info.switch_id =
5915 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5916 ctxt.info.switch_id |=
5917 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5920 /* Configure port/vlan */
5921 ctxt.info.valid_sections |=
5922 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5923 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5924 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5925 I40E_DEFAULT_TCMAP);
5926 if (ret != I40E_SUCCESS) {
5928 "Failed to configure TC queue mapping");
5929 goto fail_msix_alloc;
5931 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5932 ctxt.info.valid_sections |=
5933 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5934 } else if (type == I40E_VSI_FDIR) {
5935 memset(&ctxt, 0, sizeof(ctxt));
5936 vsi->uplink_seid = uplink_vsi->uplink_seid;
5937 ctxt.pf_num = hw->pf_id;
5939 ctxt.uplink_seid = vsi->uplink_seid;
5940 ctxt.connection_type = 0x1; /* regular data port */
5941 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5942 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5943 I40E_DEFAULT_TCMAP);
5944 if (ret != I40E_SUCCESS) {
5946 "Failed to configure TC queue mapping.");
5947 goto fail_msix_alloc;
5949 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5950 ctxt.info.valid_sections |=
5951 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5953 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5954 goto fail_msix_alloc;
5957 if (vsi->type != I40E_VSI_MAIN) {
5958 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5959 if (ret != I40E_SUCCESS) {
5960 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5961 hw->aq.asq_last_status);
5962 goto fail_msix_alloc;
5964 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5965 vsi->info.valid_sections = 0;
5966 vsi->seid = ctxt.seid;
5967 vsi->vsi_id = ctxt.vsi_number;
5968 vsi->sib_vsi_list.vsi = vsi;
5969 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5970 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5971 &vsi->sib_vsi_list, list);
5973 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5974 &vsi->sib_vsi_list, list);
5978 /* MAC/VLAN configuration */
5979 rte_memcpy(&filter.mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
5980 filter.filter_type = I40E_MACVLAN_PERFECT_MATCH;
5982 ret = i40e_vsi_add_mac(vsi, &filter);
5983 if (ret != I40E_SUCCESS) {
5984 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5985 goto fail_msix_alloc;
5988 /* Get VSI BW information */
5989 i40e_vsi_get_bw_config(vsi);
5992 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5994 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
6000 /* Configure vlan filter on or off */
6002 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
6005 struct i40e_mac_filter *f;
6007 struct i40e_mac_filter_info *mac_filter;
6008 enum i40e_mac_filter_type desired_filter;
6009 int ret = I40E_SUCCESS;
6012 /* Filter to match MAC and VLAN */
6013 desired_filter = I40E_MACVLAN_PERFECT_MATCH;
6015 /* Filter to match only MAC */
6016 desired_filter = I40E_MAC_PERFECT_MATCH;
6021 mac_filter = rte_zmalloc("mac_filter_info_data",
6022 num * sizeof(*mac_filter), 0);
6023 if (mac_filter == NULL) {
6024 PMD_DRV_LOG(ERR, "failed to allocate memory");
6025 return I40E_ERR_NO_MEMORY;
6030 /* Remove all existing mac */
6031 RTE_TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
6032 mac_filter[i] = f->mac_info;
6033 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
6035 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6036 on ? "enable" : "disable");
6042 /* Override with new filter */
6043 for (i = 0; i < num; i++) {
6044 mac_filter[i].filter_type = desired_filter;
6045 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
6047 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6048 on ? "enable" : "disable");
6054 rte_free(mac_filter);
6058 /* Configure vlan stripping on or off */
6060 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
6062 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6063 struct i40e_vsi_context ctxt;
6065 int ret = I40E_SUCCESS;
6067 /* Check if it has been already on or off */
6068 if (vsi->info.valid_sections &
6069 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
6071 if ((vsi->info.port_vlan_flags &
6072 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
6073 return 0; /* already on */
6075 if ((vsi->info.port_vlan_flags &
6076 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
6077 I40E_AQ_VSI_PVLAN_EMOD_MASK)
6078 return 0; /* already off */
6083 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
6085 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
6086 vsi->info.valid_sections =
6087 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
6088 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
6089 vsi->info.port_vlan_flags |= vlan_flags;
6090 ctxt.seid = vsi->seid;
6091 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
6092 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6094 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
6095 on ? "enable" : "disable");
6101 i40e_dev_init_vlan(struct rte_eth_dev *dev)
6103 struct rte_eth_dev_data *data = dev->data;
6107 /* Apply vlan offload setting */
6108 mask = ETH_VLAN_STRIP_MASK |
6109 ETH_QINQ_STRIP_MASK |
6110 ETH_VLAN_FILTER_MASK |
6111 ETH_VLAN_EXTEND_MASK;
6112 ret = i40e_vlan_offload_set(dev, mask);
6114 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
6118 /* Apply pvid setting */
6119 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
6120 data->dev_conf.txmode.hw_vlan_insert_pvid);
6122 PMD_DRV_LOG(INFO, "Failed to update VSI params");
6128 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
6130 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6132 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
6136 i40e_update_flow_control(struct i40e_hw *hw)
6138 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
6139 struct i40e_link_status link_status;
6140 uint32_t rxfc = 0, txfc = 0, reg;
6144 memset(&link_status, 0, sizeof(link_status));
6145 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
6146 if (ret != I40E_SUCCESS) {
6147 PMD_DRV_LOG(ERR, "Failed to get link status information");
6148 goto write_reg; /* Disable flow control */
6151 an_info = hw->phy.link_info.an_info;
6152 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
6153 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
6154 ret = I40E_ERR_NOT_READY;
6155 goto write_reg; /* Disable flow control */
6158 * If link auto negotiation is enabled, flow control needs to
6159 * be configured according to it
6161 switch (an_info & I40E_LINK_PAUSE_RXTX) {
6162 case I40E_LINK_PAUSE_RXTX:
6165 hw->fc.current_mode = I40E_FC_FULL;
6167 case I40E_AQ_LINK_PAUSE_RX:
6169 hw->fc.current_mode = I40E_FC_RX_PAUSE;
6171 case I40E_AQ_LINK_PAUSE_TX:
6173 hw->fc.current_mode = I40E_FC_TX_PAUSE;
6176 hw->fc.current_mode = I40E_FC_NONE;
6181 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
6182 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
6183 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
6184 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
6185 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
6186 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
6193 i40e_pf_setup(struct i40e_pf *pf)
6195 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6196 struct i40e_filter_control_settings settings;
6197 struct i40e_vsi *vsi;
6200 /* Clear all stats counters */
6201 pf->offset_loaded = FALSE;
6202 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
6203 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
6204 memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
6205 memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
6207 pf->rx_err1_offset = 0;
6209 ret = i40e_pf_get_switch_config(pf);
6210 if (ret != I40E_SUCCESS) {
6211 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
6215 ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
6217 PMD_INIT_LOG(WARNING,
6218 "failed to allocate switch domain for device %d", ret);
6220 if (pf->flags & I40E_FLAG_FDIR) {
6221 /* make queue allocated first, let FDIR use queue pair 0*/
6222 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
6223 if (ret != I40E_FDIR_QUEUE_ID) {
6225 "queue allocation fails for FDIR: ret =%d",
6227 pf->flags &= ~I40E_FLAG_FDIR;
6230 /* main VSI setup */
6231 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6233 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6234 return I40E_ERR_NOT_READY;
6238 /* Configure filter control */
6239 memset(&settings, 0, sizeof(settings));
6240 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
6241 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6242 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
6243 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6245 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6246 hw->func_caps.rss_table_size);
6247 return I40E_ERR_PARAM;
6249 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6250 hw->func_caps.rss_table_size);
6251 pf->hash_lut_size = hw->func_caps.rss_table_size;
6253 /* Enable ethtype and macvlan filters */
6254 settings.enable_ethtype = TRUE;
6255 settings.enable_macvlan = TRUE;
6256 ret = i40e_set_filter_control(hw, &settings);
6258 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6261 /* Update flow control according to the auto negotiation */
6262 i40e_update_flow_control(hw);
6264 return I40E_SUCCESS;
6268 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6274 * Set or clear TX Queue Disable flags,
6275 * which is required by hardware.
6277 i40e_pre_tx_queue_cfg(hw, q_idx, on);
6278 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6280 /* Wait until the request is finished */
6281 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6282 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6283 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6284 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6285 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6291 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6292 return I40E_SUCCESS; /* already on, skip next steps */
6294 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6295 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6297 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6298 return I40E_SUCCESS; /* already off, skip next steps */
6299 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6301 /* Write the register */
6302 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6303 /* Check the result */
6304 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6305 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6306 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6308 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6309 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6312 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6313 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6317 /* Check if it is timeout */
6318 if (j >= I40E_CHK_Q_ENA_COUNT) {
6319 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6320 (on ? "enable" : "disable"), q_idx);
6321 return I40E_ERR_TIMEOUT;
6324 return I40E_SUCCESS;
6328 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6333 /* Wait until the request is finished */
6334 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6335 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6336 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6337 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6338 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6343 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6344 return I40E_SUCCESS; /* Already on, skip next steps */
6345 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6347 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6348 return I40E_SUCCESS; /* Already off, skip next steps */
6349 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6352 /* Write the register */
6353 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6354 /* Check the result */
6355 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6356 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6357 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6359 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6360 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6363 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6364 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6369 /* Check if it is timeout */
6370 if (j >= I40E_CHK_Q_ENA_COUNT) {
6371 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6372 (on ? "enable" : "disable"), q_idx);
6373 return I40E_ERR_TIMEOUT;
6376 return I40E_SUCCESS;
6379 /* Initialize VSI for TX */
6381 i40e_dev_tx_init(struct i40e_pf *pf)
6383 struct rte_eth_dev_data *data = pf->dev_data;
6385 uint32_t ret = I40E_SUCCESS;
6386 struct i40e_tx_queue *txq;
6388 for (i = 0; i < data->nb_tx_queues; i++) {
6389 txq = data->tx_queues[i];
6390 if (!txq || !txq->q_set)
6392 ret = i40e_tx_queue_init(txq);
6393 if (ret != I40E_SUCCESS)
6396 if (ret == I40E_SUCCESS)
6397 i40e_set_tx_function(&rte_eth_devices[pf->dev_data->port_id]);
6402 /* Initialize VSI for RX */
6404 i40e_dev_rx_init(struct i40e_pf *pf)
6406 struct rte_eth_dev_data *data = pf->dev_data;
6407 int ret = I40E_SUCCESS;
6409 struct i40e_rx_queue *rxq;
6411 i40e_pf_config_rss(pf);
6412 for (i = 0; i < data->nb_rx_queues; i++) {
6413 rxq = data->rx_queues[i];
6414 if (!rxq || !rxq->q_set)
6417 ret = i40e_rx_queue_init(rxq);
6418 if (ret != I40E_SUCCESS) {
6420 "Failed to do RX queue initialization");
6424 if (ret == I40E_SUCCESS)
6425 i40e_set_rx_function(&rte_eth_devices[pf->dev_data->port_id]);
6431 i40e_dev_rxtx_init(struct i40e_pf *pf)
6435 err = i40e_dev_tx_init(pf);
6437 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6440 err = i40e_dev_rx_init(pf);
6442 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6450 i40e_vmdq_setup(struct rte_eth_dev *dev)
6452 struct rte_eth_conf *conf = &dev->data->dev_conf;
6453 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6454 int i, err, conf_vsis, j, loop;
6455 struct i40e_vsi *vsi;
6456 struct i40e_vmdq_info *vmdq_info;
6457 struct rte_eth_vmdq_rx_conf *vmdq_conf;
6458 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6461 * Disable interrupt to avoid message from VF. Furthermore, it will
6462 * avoid race condition in VSI creation/destroy.
6464 i40e_pf_disable_irq0(hw);
6466 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6467 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6471 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6472 if (conf_vsis > pf->max_nb_vmdq_vsi) {
6473 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6474 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6475 pf->max_nb_vmdq_vsi);
6479 if (pf->vmdq != NULL) {
6480 PMD_INIT_LOG(INFO, "VMDQ already configured");
6484 pf->vmdq = rte_zmalloc("vmdq_info_struct",
6485 sizeof(*vmdq_info) * conf_vsis, 0);
6487 if (pf->vmdq == NULL) {
6488 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6492 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6494 /* Create VMDQ VSI */
6495 for (i = 0; i < conf_vsis; i++) {
6496 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6497 vmdq_conf->enable_loop_back);
6499 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6503 vmdq_info = &pf->vmdq[i];
6505 vmdq_info->vsi = vsi;
6507 pf->nb_cfg_vmdq_vsi = conf_vsis;
6509 /* Configure Vlan */
6510 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6511 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6512 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6513 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6514 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6515 vmdq_conf->pool_map[i].vlan_id, j);
6517 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6518 vmdq_conf->pool_map[i].vlan_id);
6520 PMD_INIT_LOG(ERR, "Failed to add vlan");
6528 i40e_pf_enable_irq0(hw);
6533 for (i = 0; i < conf_vsis; i++)
6534 if (pf->vmdq[i].vsi == NULL)
6537 i40e_vsi_release(pf->vmdq[i].vsi);
6541 i40e_pf_enable_irq0(hw);
6546 i40e_stat_update_32(struct i40e_hw *hw,
6554 new_data = (uint64_t)I40E_READ_REG(hw, reg);
6558 if (new_data >= *offset)
6559 *stat = (uint64_t)(new_data - *offset);
6561 *stat = (uint64_t)((new_data +
6562 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6566 i40e_stat_update_48(struct i40e_hw *hw,
6575 if (hw->device_id == I40E_DEV_ID_QEMU) {
6576 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6577 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6578 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6580 new_data = I40E_READ_REG64(hw, loreg);
6586 if (new_data >= *offset)
6587 *stat = new_data - *offset;
6589 *stat = (uint64_t)((new_data +
6590 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6592 *stat &= I40E_48_BIT_MASK;
6597 i40e_pf_disable_irq0(struct i40e_hw *hw)
6599 /* Disable all interrupt types */
6600 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6601 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6602 I40E_WRITE_FLUSH(hw);
6607 i40e_pf_enable_irq0(struct i40e_hw *hw)
6609 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6610 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6611 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6612 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6613 I40E_WRITE_FLUSH(hw);
6617 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6619 /* read pending request and disable first */
6620 i40e_pf_disable_irq0(hw);
6621 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6622 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6623 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6626 /* Link no queues with irq0 */
6627 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6628 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6632 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6634 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6635 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6638 uint32_t index, offset, val;
6643 * Try to find which VF trigger a reset, use absolute VF id to access
6644 * since the reg is global register.
6646 for (i = 0; i < pf->vf_num; i++) {
6647 abs_vf_id = hw->func_caps.vf_base_id + i;
6648 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6649 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6650 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6651 /* VFR event occurred */
6652 if (val & (0x1 << offset)) {
6655 /* Clear the event first */
6656 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6658 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6660 * Only notify a VF reset event occurred,
6661 * don't trigger another SW reset
6663 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6664 if (ret != I40E_SUCCESS)
6665 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6671 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6673 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6676 for (i = 0; i < pf->vf_num; i++)
6677 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6681 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6683 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6684 struct i40e_arq_event_info info;
6685 uint16_t pending, opcode;
6688 info.buf_len = I40E_AQ_BUF_SZ;
6689 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6690 if (!info.msg_buf) {
6691 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6697 ret = i40e_clean_arq_element(hw, &info, &pending);
6699 if (ret != I40E_SUCCESS) {
6701 "Failed to read msg from AdminQ, aq_err: %u",
6702 hw->aq.asq_last_status);
6705 opcode = rte_le_to_cpu_16(info.desc.opcode);
6708 case i40e_aqc_opc_send_msg_to_pf:
6709 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6710 i40e_pf_host_handle_vf_msg(dev,
6711 rte_le_to_cpu_16(info.desc.retval),
6712 rte_le_to_cpu_32(info.desc.cookie_high),
6713 rte_le_to_cpu_32(info.desc.cookie_low),
6717 case i40e_aqc_opc_get_link_status:
6718 ret = i40e_dev_link_update(dev, 0);
6720 rte_eth_dev_callback_process(dev,
6721 RTE_ETH_EVENT_INTR_LSC, NULL);
6724 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6729 rte_free(info.msg_buf);
6733 i40e_handle_mdd_event(struct rte_eth_dev *dev)
6735 #define I40E_MDD_CLEAR32 0xFFFFFFFF
6736 #define I40E_MDD_CLEAR16 0xFFFF
6737 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6738 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6739 bool mdd_detected = false;
6740 struct i40e_pf_vf *vf;
6744 /* find what triggered the MDD event */
6745 reg = I40E_READ_REG(hw, I40E_GL_MDET_TX);
6746 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
6747 uint8_t pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6748 I40E_GL_MDET_TX_PF_NUM_SHIFT;
6749 uint16_t vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
6750 I40E_GL_MDET_TX_VF_NUM_SHIFT;
6751 uint8_t event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
6752 I40E_GL_MDET_TX_EVENT_SHIFT;
6753 uint16_t queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6754 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6755 hw->func_caps.base_queue;
6756 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on TX "
6757 "queue %d PF number 0x%02x VF number 0x%02x device %s\n",
6758 event, queue, pf_num, vf_num, dev->data->name);
6759 I40E_WRITE_REG(hw, I40E_GL_MDET_TX, I40E_MDD_CLEAR32);
6760 mdd_detected = true;
6762 reg = I40E_READ_REG(hw, I40E_GL_MDET_RX);
6763 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
6764 uint8_t func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6765 I40E_GL_MDET_RX_FUNCTION_SHIFT;
6766 uint8_t event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
6767 I40E_GL_MDET_RX_EVENT_SHIFT;
6768 uint16_t queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6769 I40E_GL_MDET_RX_QUEUE_SHIFT) -
6770 hw->func_caps.base_queue;
6772 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on RX "
6773 "queue %d of function 0x%02x device %s\n",
6774 event, queue, func, dev->data->name);
6775 I40E_WRITE_REG(hw, I40E_GL_MDET_RX, I40E_MDD_CLEAR32);
6776 mdd_detected = true;
6780 reg = I40E_READ_REG(hw, I40E_PF_MDET_TX);
6781 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
6782 I40E_WRITE_REG(hw, I40E_PF_MDET_TX, I40E_MDD_CLEAR16);
6783 PMD_DRV_LOG(WARNING, "TX driver issue detected on PF\n");
6785 reg = I40E_READ_REG(hw, I40E_PF_MDET_RX);
6786 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
6787 I40E_WRITE_REG(hw, I40E_PF_MDET_RX,
6789 PMD_DRV_LOG(WARNING, "RX driver issue detected on PF\n");
6793 /* see if one of the VFs needs its hand slapped */
6794 for (i = 0; i < pf->vf_num && mdd_detected; i++) {
6796 reg = I40E_READ_REG(hw, I40E_VP_MDET_TX(i));
6797 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
6798 I40E_WRITE_REG(hw, I40E_VP_MDET_TX(i),
6800 vf->num_mdd_events++;
6801 PMD_DRV_LOG(WARNING, "TX driver issue detected on VF %d %-"
6803 i, vf->num_mdd_events);
6806 reg = I40E_READ_REG(hw, I40E_VP_MDET_RX(i));
6807 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
6808 I40E_WRITE_REG(hw, I40E_VP_MDET_RX(i),
6810 vf->num_mdd_events++;
6811 PMD_DRV_LOG(WARNING, "RX driver issue detected on VF %d %-"
6813 i, vf->num_mdd_events);
6819 * Interrupt handler triggered by NIC for handling
6820 * specific interrupt.
6823 * Pointer to interrupt handle.
6825 * The address of parameter (struct rte_eth_dev *) regsitered before.
6831 i40e_dev_interrupt_handler(void *param)
6833 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6834 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6837 /* Disable interrupt */
6838 i40e_pf_disable_irq0(hw);
6840 /* read out interrupt causes */
6841 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6843 /* No interrupt event indicated */
6844 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6845 PMD_DRV_LOG(INFO, "No interrupt event");
6848 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6849 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6850 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
6851 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6852 i40e_handle_mdd_event(dev);
6854 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6855 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6856 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6857 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6858 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6859 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6860 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6861 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6862 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6863 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6865 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6866 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6867 i40e_dev_handle_vfr_event(dev);
6869 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6870 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6871 i40e_dev_handle_aq_msg(dev);
6875 /* Enable interrupt */
6876 i40e_pf_enable_irq0(hw);
6880 i40e_dev_alarm_handler(void *param)
6882 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6883 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6886 /* Disable interrupt */
6887 i40e_pf_disable_irq0(hw);
6889 /* read out interrupt causes */
6890 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6892 /* No interrupt event indicated */
6893 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
6895 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6896 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6897 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
6898 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6899 i40e_handle_mdd_event(dev);
6901 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6902 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6903 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6904 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6905 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6906 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6907 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6908 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6909 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6910 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6912 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6913 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6914 i40e_dev_handle_vfr_event(dev);
6916 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6917 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6918 i40e_dev_handle_aq_msg(dev);
6922 /* Enable interrupt */
6923 i40e_pf_enable_irq0(hw);
6924 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
6925 i40e_dev_alarm_handler, dev);
6929 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6930 struct i40e_macvlan_filter *filter,
6933 int ele_num, ele_buff_size;
6934 int num, actual_num, i;
6936 int ret = I40E_SUCCESS;
6937 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6938 struct i40e_aqc_add_macvlan_element_data *req_list;
6940 if (filter == NULL || total == 0)
6941 return I40E_ERR_PARAM;
6942 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6943 ele_buff_size = hw->aq.asq_buf_size;
6945 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6946 if (req_list == NULL) {
6947 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6948 return I40E_ERR_NO_MEMORY;
6953 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6954 memset(req_list, 0, ele_buff_size);
6956 for (i = 0; i < actual_num; i++) {
6957 rte_memcpy(req_list[i].mac_addr,
6958 &filter[num + i].macaddr, ETH_ADDR_LEN);
6959 req_list[i].vlan_tag =
6960 rte_cpu_to_le_16(filter[num + i].vlan_id);
6962 switch (filter[num + i].filter_type) {
6963 case I40E_MAC_PERFECT_MATCH:
6964 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6965 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6967 case I40E_MACVLAN_PERFECT_MATCH:
6968 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6970 case I40E_MAC_HASH_MATCH:
6971 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6972 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6974 case I40E_MACVLAN_HASH_MATCH:
6975 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6978 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6979 ret = I40E_ERR_PARAM;
6983 req_list[i].queue_number = 0;
6985 req_list[i].flags = rte_cpu_to_le_16(flags);
6988 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6990 if (ret != I40E_SUCCESS) {
6991 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6995 } while (num < total);
7003 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
7004 struct i40e_macvlan_filter *filter,
7007 int ele_num, ele_buff_size;
7008 int num, actual_num, i;
7010 int ret = I40E_SUCCESS;
7011 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7012 struct i40e_aqc_remove_macvlan_element_data *req_list;
7013 enum i40e_admin_queue_err aq_status;
7015 if (filter == NULL || total == 0)
7016 return I40E_ERR_PARAM;
7018 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
7019 ele_buff_size = hw->aq.asq_buf_size;
7021 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
7022 if (req_list == NULL) {
7023 PMD_DRV_LOG(ERR, "Fail to allocate memory");
7024 return I40E_ERR_NO_MEMORY;
7029 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
7030 memset(req_list, 0, ele_buff_size);
7032 for (i = 0; i < actual_num; i++) {
7033 rte_memcpy(req_list[i].mac_addr,
7034 &filter[num + i].macaddr, ETH_ADDR_LEN);
7035 req_list[i].vlan_tag =
7036 rte_cpu_to_le_16(filter[num + i].vlan_id);
7038 switch (filter[num + i].filter_type) {
7039 case I40E_MAC_PERFECT_MATCH:
7040 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
7041 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7043 case I40E_MACVLAN_PERFECT_MATCH:
7044 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
7046 case I40E_MAC_HASH_MATCH:
7047 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
7048 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7050 case I40E_MACVLAN_HASH_MATCH:
7051 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
7054 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
7055 ret = I40E_ERR_PARAM;
7058 req_list[i].flags = rte_cpu_to_le_16(flags);
7061 ret = i40e_aq_remove_macvlan_v2(hw, vsi->seid, req_list,
7062 actual_num, NULL, &aq_status);
7064 if (ret != I40E_SUCCESS) {
7065 /* Do not report as an error when firmware returns ENOENT */
7066 if (aq_status == I40E_AQ_RC_ENOENT) {
7069 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
7074 } while (num < total);
7081 /* Find out specific MAC filter */
7082 static struct i40e_mac_filter *
7083 i40e_find_mac_filter(struct i40e_vsi *vsi,
7084 struct rte_ether_addr *macaddr)
7086 struct i40e_mac_filter *f;
7088 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7089 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
7097 i40e_find_vlan_filter(struct i40e_vsi *vsi,
7100 uint32_t vid_idx, vid_bit;
7102 if (vlan_id > ETH_VLAN_ID_MAX)
7105 vid_idx = I40E_VFTA_IDX(vlan_id);
7106 vid_bit = I40E_VFTA_BIT(vlan_id);
7108 if (vsi->vfta[vid_idx] & vid_bit)
7115 i40e_store_vlan_filter(struct i40e_vsi *vsi,
7116 uint16_t vlan_id, bool on)
7118 uint32_t vid_idx, vid_bit;
7120 vid_idx = I40E_VFTA_IDX(vlan_id);
7121 vid_bit = I40E_VFTA_BIT(vlan_id);
7124 vsi->vfta[vid_idx] |= vid_bit;
7126 vsi->vfta[vid_idx] &= ~vid_bit;
7130 i40e_set_vlan_filter(struct i40e_vsi *vsi,
7131 uint16_t vlan_id, bool on)
7133 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7134 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
7137 if (vlan_id > ETH_VLAN_ID_MAX)
7140 i40e_store_vlan_filter(vsi, vlan_id, on);
7142 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
7145 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
7148 ret = i40e_aq_add_vlan(hw, vsi->seid,
7149 &vlan_data, 1, NULL);
7150 if (ret != I40E_SUCCESS)
7151 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
7153 ret = i40e_aq_remove_vlan(hw, vsi->seid,
7154 &vlan_data, 1, NULL);
7155 if (ret != I40E_SUCCESS)
7157 "Failed to remove vlan filter");
7162 * Find all vlan options for specific mac addr,
7163 * return with actual vlan found.
7166 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
7167 struct i40e_macvlan_filter *mv_f,
7168 int num, struct rte_ether_addr *addr)
7174 * Not to use i40e_find_vlan_filter to decrease the loop time,
7175 * although the code looks complex.
7177 if (num < vsi->vlan_num)
7178 return I40E_ERR_PARAM;
7181 for (j = 0; j < I40E_VFTA_SIZE; j++) {
7183 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
7184 if (vsi->vfta[j] & (1 << k)) {
7187 "vlan number doesn't match");
7188 return I40E_ERR_PARAM;
7190 rte_memcpy(&mv_f[i].macaddr,
7191 addr, ETH_ADDR_LEN);
7193 j * I40E_UINT32_BIT_SIZE + k;
7199 return I40E_SUCCESS;
7203 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
7204 struct i40e_macvlan_filter *mv_f,
7209 struct i40e_mac_filter *f;
7211 if (num < vsi->mac_num)
7212 return I40E_ERR_PARAM;
7214 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7216 PMD_DRV_LOG(ERR, "buffer number not match");
7217 return I40E_ERR_PARAM;
7219 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7221 mv_f[i].vlan_id = vlan;
7222 mv_f[i].filter_type = f->mac_info.filter_type;
7226 return I40E_SUCCESS;
7230 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
7233 struct i40e_mac_filter *f;
7234 struct i40e_macvlan_filter *mv_f;
7235 int ret = I40E_SUCCESS;
7237 if (vsi == NULL || vsi->mac_num == 0)
7238 return I40E_ERR_PARAM;
7240 /* Case that no vlan is set */
7241 if (vsi->vlan_num == 0)
7244 num = vsi->mac_num * vsi->vlan_num;
7246 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7248 PMD_DRV_LOG(ERR, "failed to allocate memory");
7249 return I40E_ERR_NO_MEMORY;
7253 if (vsi->vlan_num == 0) {
7254 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7255 rte_memcpy(&mv_f[i].macaddr,
7256 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7257 mv_f[i].filter_type = f->mac_info.filter_type;
7258 mv_f[i].vlan_id = 0;
7262 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7263 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7264 vsi->vlan_num, &f->mac_info.mac_addr);
7265 if (ret != I40E_SUCCESS)
7267 for (j = i; j < i + vsi->vlan_num; j++)
7268 mv_f[j].filter_type = f->mac_info.filter_type;
7273 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7281 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7283 struct i40e_macvlan_filter *mv_f;
7285 int ret = I40E_SUCCESS;
7287 if (!vsi || vlan > RTE_ETHER_MAX_VLAN_ID)
7288 return I40E_ERR_PARAM;
7290 /* If it's already set, just return */
7291 if (i40e_find_vlan_filter(vsi,vlan))
7292 return I40E_SUCCESS;
7294 mac_num = vsi->mac_num;
7297 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7298 return I40E_ERR_PARAM;
7301 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7304 PMD_DRV_LOG(ERR, "failed to allocate memory");
7305 return I40E_ERR_NO_MEMORY;
7308 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7310 if (ret != I40E_SUCCESS)
7313 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7315 if (ret != I40E_SUCCESS)
7318 i40e_set_vlan_filter(vsi, vlan, 1);
7328 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7330 struct i40e_macvlan_filter *mv_f;
7332 int ret = I40E_SUCCESS;
7335 * Vlan 0 is the generic filter for untagged packets
7336 * and can't be removed.
7338 if (!vsi || vlan == 0 || vlan > RTE_ETHER_MAX_VLAN_ID)
7339 return I40E_ERR_PARAM;
7341 /* If can't find it, just return */
7342 if (!i40e_find_vlan_filter(vsi, vlan))
7343 return I40E_ERR_PARAM;
7345 mac_num = vsi->mac_num;
7348 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7349 return I40E_ERR_PARAM;
7352 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7355 PMD_DRV_LOG(ERR, "failed to allocate memory");
7356 return I40E_ERR_NO_MEMORY;
7359 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7361 if (ret != I40E_SUCCESS)
7364 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7366 if (ret != I40E_SUCCESS)
7369 /* This is last vlan to remove, replace all mac filter with vlan 0 */
7370 if (vsi->vlan_num == 1) {
7371 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7372 if (ret != I40E_SUCCESS)
7375 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7376 if (ret != I40E_SUCCESS)
7380 i40e_set_vlan_filter(vsi, vlan, 0);
7390 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7392 struct i40e_mac_filter *f;
7393 struct i40e_macvlan_filter *mv_f;
7394 int i, vlan_num = 0;
7395 int ret = I40E_SUCCESS;
7397 /* If it's add and we've config it, return */
7398 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7400 return I40E_SUCCESS;
7401 if (mac_filter->filter_type == I40E_MACVLAN_PERFECT_MATCH ||
7402 mac_filter->filter_type == I40E_MACVLAN_HASH_MATCH) {
7405 * If vlan_num is 0, that's the first time to add mac,
7406 * set mask for vlan_id 0.
7408 if (vsi->vlan_num == 0) {
7409 i40e_set_vlan_filter(vsi, 0, 1);
7412 vlan_num = vsi->vlan_num;
7413 } else if (mac_filter->filter_type == I40E_MAC_PERFECT_MATCH ||
7414 mac_filter->filter_type == I40E_MAC_HASH_MATCH)
7417 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7419 PMD_DRV_LOG(ERR, "failed to allocate memory");
7420 return I40E_ERR_NO_MEMORY;
7423 for (i = 0; i < vlan_num; i++) {
7424 mv_f[i].filter_type = mac_filter->filter_type;
7425 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7429 if (mac_filter->filter_type == I40E_MACVLAN_PERFECT_MATCH ||
7430 mac_filter->filter_type == I40E_MACVLAN_HASH_MATCH) {
7431 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7432 &mac_filter->mac_addr);
7433 if (ret != I40E_SUCCESS)
7437 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7438 if (ret != I40E_SUCCESS)
7441 /* Add the mac addr into mac list */
7442 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7444 PMD_DRV_LOG(ERR, "failed to allocate memory");
7445 ret = I40E_ERR_NO_MEMORY;
7448 rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7450 f->mac_info.filter_type = mac_filter->filter_type;
7451 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7462 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr)
7464 struct i40e_mac_filter *f;
7465 struct i40e_macvlan_filter *mv_f;
7467 enum i40e_mac_filter_type filter_type;
7468 int ret = I40E_SUCCESS;
7470 /* Can't find it, return an error */
7471 f = i40e_find_mac_filter(vsi, addr);
7473 return I40E_ERR_PARAM;
7475 vlan_num = vsi->vlan_num;
7476 filter_type = f->mac_info.filter_type;
7477 if (filter_type == I40E_MACVLAN_PERFECT_MATCH ||
7478 filter_type == I40E_MACVLAN_HASH_MATCH) {
7479 if (vlan_num == 0) {
7480 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7481 return I40E_ERR_PARAM;
7483 } else if (filter_type == I40E_MAC_PERFECT_MATCH ||
7484 filter_type == I40E_MAC_HASH_MATCH)
7487 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7489 PMD_DRV_LOG(ERR, "failed to allocate memory");
7490 return I40E_ERR_NO_MEMORY;
7493 for (i = 0; i < vlan_num; i++) {
7494 mv_f[i].filter_type = filter_type;
7495 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7498 if (filter_type == I40E_MACVLAN_PERFECT_MATCH ||
7499 filter_type == I40E_MACVLAN_HASH_MATCH) {
7500 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7501 if (ret != I40E_SUCCESS)
7505 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7506 if (ret != I40E_SUCCESS)
7509 /* Remove the mac addr into mac list */
7510 TAILQ_REMOVE(&vsi->mac_list, f, next);
7520 /* Configure hash enable flags for RSS */
7522 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7530 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7531 if (flags & (1ULL << i))
7532 hena |= adapter->pctypes_tbl[i];
7538 /* Parse the hash enable flags */
7540 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7542 uint64_t rss_hf = 0;
7548 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7549 if (flags & adapter->pctypes_tbl[i])
7550 rss_hf |= (1ULL << i);
7557 i40e_pf_disable_rss(struct i40e_pf *pf)
7559 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7561 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7562 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7563 I40E_WRITE_FLUSH(hw);
7567 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7569 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7570 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7571 uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7572 I40E_VFQF_HKEY_MAX_INDEX :
7573 I40E_PFQF_HKEY_MAX_INDEX;
7575 if (!key || key_len == 0) {
7576 PMD_DRV_LOG(DEBUG, "No key to be configured");
7578 } else if (key_len != (key_idx + 1) *
7580 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7584 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7585 struct i40e_aqc_get_set_rss_key_data *key_dw =
7586 (struct i40e_aqc_get_set_rss_key_data *)key;
7587 enum i40e_status_code status =
7588 i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7592 "Failed to configure RSS key via AQ, error status: %d",
7597 uint32_t *hash_key = (uint32_t *)key;
7600 if (vsi->type == I40E_VSI_SRIOV) {
7601 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7604 I40E_VFQF_HKEY1(i, vsi->user_param),
7608 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7609 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7612 I40E_WRITE_FLUSH(hw);
7619 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7621 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7622 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7626 if (!key || !key_len)
7629 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7630 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7631 (struct i40e_aqc_get_set_rss_key_data *)key);
7633 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7637 uint32_t *key_dw = (uint32_t *)key;
7640 if (vsi->type == I40E_VSI_SRIOV) {
7641 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7642 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7643 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7645 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7648 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7649 reg = I40E_PFQF_HKEY(i);
7650 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7652 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7660 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7662 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7666 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7667 rss_conf->rss_key_len);
7671 hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7672 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7673 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7674 I40E_WRITE_FLUSH(hw);
7680 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7681 struct rte_eth_rss_conf *rss_conf)
7683 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7684 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7685 uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7688 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7689 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7691 if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7692 if (rss_hf != 0) /* Enable RSS */
7694 return 0; /* Nothing to do */
7697 if (rss_hf == 0) /* Disable RSS */
7700 return i40e_hw_rss_hash_set(pf, rss_conf);
7704 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7705 struct rte_eth_rss_conf *rss_conf)
7707 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7708 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7715 ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7716 &rss_conf->rss_key_len);
7720 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7721 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7722 rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7728 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7730 switch (filter_type) {
7731 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7732 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7734 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7735 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7737 case RTE_TUNNEL_FILTER_IMAC_TENID:
7738 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7740 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7741 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7743 case ETH_TUNNEL_FILTER_IMAC:
7744 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7746 case ETH_TUNNEL_FILTER_OIP:
7747 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7749 case ETH_TUNNEL_FILTER_IIP:
7750 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7753 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7760 /* Convert tunnel filter structure */
7762 i40e_tunnel_filter_convert(
7763 struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7764 struct i40e_tunnel_filter *tunnel_filter)
7766 rte_ether_addr_copy((struct rte_ether_addr *)
7767 &cld_filter->element.outer_mac,
7768 (struct rte_ether_addr *)&tunnel_filter->input.outer_mac);
7769 rte_ether_addr_copy((struct rte_ether_addr *)
7770 &cld_filter->element.inner_mac,
7771 (struct rte_ether_addr *)&tunnel_filter->input.inner_mac);
7772 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7773 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7774 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7775 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7776 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7778 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7779 tunnel_filter->input.flags = cld_filter->element.flags;
7780 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7781 tunnel_filter->queue = cld_filter->element.queue_number;
7782 rte_memcpy(tunnel_filter->input.general_fields,
7783 cld_filter->general_fields,
7784 sizeof(cld_filter->general_fields));
7789 /* Check if there exists the tunnel filter */
7790 struct i40e_tunnel_filter *
7791 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7792 const struct i40e_tunnel_filter_input *input)
7796 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7800 return tunnel_rule->hash_map[ret];
7803 /* Add a tunnel filter into the SW list */
7805 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7806 struct i40e_tunnel_filter *tunnel_filter)
7808 struct i40e_tunnel_rule *rule = &pf->tunnel;
7811 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7814 "Failed to insert tunnel filter to hash table %d!",
7818 rule->hash_map[ret] = tunnel_filter;
7820 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7825 /* Delete a tunnel filter from the SW list */
7827 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7828 struct i40e_tunnel_filter_input *input)
7830 struct i40e_tunnel_rule *rule = &pf->tunnel;
7831 struct i40e_tunnel_filter *tunnel_filter;
7834 ret = rte_hash_del_key(rule->hash_table, input);
7837 "Failed to delete tunnel filter to hash table %d!",
7841 tunnel_filter = rule->hash_map[ret];
7842 rule->hash_map[ret] = NULL;
7844 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7845 rte_free(tunnel_filter);
7850 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7851 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
7852 #define I40E_TR_GENEVE_KEY_MASK 0x8
7853 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
7854 #define I40E_TR_GRE_KEY_MASK 0x400
7855 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
7856 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
7857 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_PORT_TR_WORD0 0x49
7858 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_DIRECTION_WORD0 0x41
7859 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_INGRESS_WORD0 0x80
7860 #define I40E_DIRECTION_INGRESS_KEY 0x8000
7861 #define I40E_TR_L4_TYPE_TCP 0x2
7862 #define I40E_TR_L4_TYPE_UDP 0x4
7863 #define I40E_TR_L4_TYPE_SCTP 0x8
7866 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7868 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7869 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7870 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7871 struct rte_eth_dev *dev = &rte_eth_devices[pf->dev_data->port_id];
7872 enum i40e_status_code status = I40E_SUCCESS;
7874 if (pf->support_multi_driver) {
7875 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7876 return I40E_NOT_SUPPORTED;
7879 memset(&filter_replace, 0,
7880 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7881 memset(&filter_replace_buf, 0,
7882 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7884 /* create L1 filter */
7885 filter_replace.old_filter_type =
7886 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7887 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7888 filter_replace.tr_bit = 0;
7890 /* Prepare the buffer, 3 entries */
7891 filter_replace_buf.data[0] =
7892 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7893 filter_replace_buf.data[0] |=
7894 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7895 filter_replace_buf.data[2] = 0xFF;
7896 filter_replace_buf.data[3] = 0xFF;
7897 filter_replace_buf.data[4] =
7898 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7899 filter_replace_buf.data[4] |=
7900 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7901 filter_replace_buf.data[7] = 0xF0;
7902 filter_replace_buf.data[8]
7903 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7904 filter_replace_buf.data[8] |=
7905 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7906 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7907 I40E_TR_GENEVE_KEY_MASK |
7908 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7909 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7910 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7911 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7913 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7914 &filter_replace_buf);
7915 if (!status && (filter_replace.old_filter_type !=
7916 filter_replace.new_filter_type))
7917 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7918 " original: 0x%x, new: 0x%x",
7920 filter_replace.old_filter_type,
7921 filter_replace.new_filter_type);
7927 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7929 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7930 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7931 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7932 struct rte_eth_dev *dev = &rte_eth_devices[pf->dev_data->port_id];
7933 enum i40e_status_code status = I40E_SUCCESS;
7935 if (pf->support_multi_driver) {
7936 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7937 return I40E_NOT_SUPPORTED;
7941 memset(&filter_replace, 0,
7942 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7943 memset(&filter_replace_buf, 0,
7944 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7945 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7946 I40E_AQC_MIRROR_CLOUD_FILTER;
7947 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7948 filter_replace.new_filter_type =
7949 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7950 /* Prepare the buffer, 2 entries */
7951 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7952 filter_replace_buf.data[0] |=
7953 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7954 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7955 filter_replace_buf.data[4] |=
7956 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7957 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7958 &filter_replace_buf);
7961 if (filter_replace.old_filter_type !=
7962 filter_replace.new_filter_type)
7963 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7964 " original: 0x%x, new: 0x%x",
7966 filter_replace.old_filter_type,
7967 filter_replace.new_filter_type);
7970 memset(&filter_replace, 0,
7971 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7972 memset(&filter_replace_buf, 0,
7973 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7975 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7976 I40E_AQC_MIRROR_CLOUD_FILTER;
7977 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7978 filter_replace.new_filter_type =
7979 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7980 /* Prepare the buffer, 2 entries */
7981 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7982 filter_replace_buf.data[0] |=
7983 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7984 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7985 filter_replace_buf.data[4] |=
7986 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7988 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7989 &filter_replace_buf);
7990 if (!status && (filter_replace.old_filter_type !=
7991 filter_replace.new_filter_type))
7992 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7993 " original: 0x%x, new: 0x%x",
7995 filter_replace.old_filter_type,
7996 filter_replace.new_filter_type);
8001 static enum i40e_status_code
8002 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
8004 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8005 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8006 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8007 struct rte_eth_dev *dev = &rte_eth_devices[pf->dev_data->port_id];
8008 enum i40e_status_code status = I40E_SUCCESS;
8010 if (pf->support_multi_driver) {
8011 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8012 return I40E_NOT_SUPPORTED;
8016 memset(&filter_replace, 0,
8017 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8018 memset(&filter_replace_buf, 0,
8019 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8020 /* create L1 filter */
8021 filter_replace.old_filter_type =
8022 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
8023 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
8024 filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
8025 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8026 /* Prepare the buffer, 2 entries */
8027 filter_replace_buf.data[0] =
8028 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8029 filter_replace_buf.data[0] |=
8030 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8031 filter_replace_buf.data[2] = 0xFF;
8032 filter_replace_buf.data[3] = 0xFF;
8033 filter_replace_buf.data[4] =
8034 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8035 filter_replace_buf.data[4] |=
8036 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8037 filter_replace_buf.data[6] = 0xFF;
8038 filter_replace_buf.data[7] = 0xFF;
8039 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8040 &filter_replace_buf);
8043 if (filter_replace.old_filter_type !=
8044 filter_replace.new_filter_type)
8045 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8046 " original: 0x%x, new: 0x%x",
8048 filter_replace.old_filter_type,
8049 filter_replace.new_filter_type);
8052 memset(&filter_replace, 0,
8053 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8054 memset(&filter_replace_buf, 0,
8055 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8056 /* create L1 filter */
8057 filter_replace.old_filter_type =
8058 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8059 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
8060 filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
8061 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8062 /* Prepare the buffer, 2 entries */
8063 filter_replace_buf.data[0] =
8064 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8065 filter_replace_buf.data[0] |=
8066 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8067 filter_replace_buf.data[2] = 0xFF;
8068 filter_replace_buf.data[3] = 0xFF;
8069 filter_replace_buf.data[4] =
8070 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8071 filter_replace_buf.data[4] |=
8072 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8073 filter_replace_buf.data[6] = 0xFF;
8074 filter_replace_buf.data[7] = 0xFF;
8076 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8077 &filter_replace_buf);
8078 if (!status && (filter_replace.old_filter_type !=
8079 filter_replace.new_filter_type))
8080 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8081 " original: 0x%x, new: 0x%x",
8083 filter_replace.old_filter_type,
8084 filter_replace.new_filter_type);
8090 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
8092 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8093 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8094 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8095 struct rte_eth_dev *dev = &rte_eth_devices[pf->dev_data->port_id];
8096 enum i40e_status_code status = I40E_SUCCESS;
8098 if (pf->support_multi_driver) {
8099 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8100 return I40E_NOT_SUPPORTED;
8104 memset(&filter_replace, 0,
8105 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8106 memset(&filter_replace_buf, 0,
8107 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8108 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8109 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
8110 filter_replace.new_filter_type =
8111 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8112 /* Prepare the buffer, 2 entries */
8113 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
8114 filter_replace_buf.data[0] |=
8115 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8116 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8117 filter_replace_buf.data[4] |=
8118 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8119 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8120 &filter_replace_buf);
8123 if (filter_replace.old_filter_type !=
8124 filter_replace.new_filter_type)
8125 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8126 " original: 0x%x, new: 0x%x",
8128 filter_replace.old_filter_type,
8129 filter_replace.new_filter_type);
8132 memset(&filter_replace, 0,
8133 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8134 memset(&filter_replace_buf, 0,
8135 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8136 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8137 filter_replace.old_filter_type =
8138 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8139 filter_replace.new_filter_type =
8140 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8141 /* Prepare the buffer, 2 entries */
8142 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8143 filter_replace_buf.data[0] |=
8144 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8145 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8146 filter_replace_buf.data[4] |=
8147 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8149 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8150 &filter_replace_buf);
8151 if (!status && (filter_replace.old_filter_type !=
8152 filter_replace.new_filter_type))
8153 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8154 " original: 0x%x, new: 0x%x",
8156 filter_replace.old_filter_type,
8157 filter_replace.new_filter_type);
8162 static enum i40e_status_code
8163 i40e_replace_port_l1_filter(struct i40e_pf *pf,
8164 enum i40e_l4_port_type l4_port_type)
8166 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8167 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8168 enum i40e_status_code status = I40E_SUCCESS;
8169 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8170 struct rte_eth_dev *dev = &rte_eth_devices[pf->dev_data->port_id];
8172 if (pf->support_multi_driver) {
8173 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8174 return I40E_NOT_SUPPORTED;
8177 memset(&filter_replace, 0,
8178 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8179 memset(&filter_replace_buf, 0,
8180 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8182 /* create L1 filter */
8183 if (l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8184 filter_replace.old_filter_type =
8185 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8186 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
8187 filter_replace_buf.data[8] =
8188 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_SRC_PORT;
8190 filter_replace.old_filter_type =
8191 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
8192 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X10;
8193 filter_replace_buf.data[8] =
8194 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_DST_PORT;
8197 filter_replace.tr_bit = 0;
8198 /* Prepare the buffer, 3 entries */
8199 filter_replace_buf.data[0] =
8200 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_DIRECTION_WORD0;
8201 filter_replace_buf.data[0] |=
8202 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8203 filter_replace_buf.data[2] = 0x00;
8204 filter_replace_buf.data[3] =
8205 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_INGRESS_WORD0;
8206 filter_replace_buf.data[4] =
8207 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_PORT_TR_WORD0;
8208 filter_replace_buf.data[4] |=
8209 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8210 filter_replace_buf.data[5] = 0x00;
8211 filter_replace_buf.data[6] = I40E_TR_L4_TYPE_UDP |
8212 I40E_TR_L4_TYPE_TCP |
8213 I40E_TR_L4_TYPE_SCTP;
8214 filter_replace_buf.data[7] = 0x00;
8215 filter_replace_buf.data[8] |=
8216 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8217 filter_replace_buf.data[9] = 0x00;
8218 filter_replace_buf.data[10] = 0xFF;
8219 filter_replace_buf.data[11] = 0xFF;
8221 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8222 &filter_replace_buf);
8223 if (!status && filter_replace.old_filter_type !=
8224 filter_replace.new_filter_type)
8225 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8226 " original: 0x%x, new: 0x%x",
8228 filter_replace.old_filter_type,
8229 filter_replace.new_filter_type);
8234 static enum i40e_status_code
8235 i40e_replace_port_cloud_filter(struct i40e_pf *pf,
8236 enum i40e_l4_port_type l4_port_type)
8238 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8239 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8240 enum i40e_status_code status = I40E_SUCCESS;
8241 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8242 struct rte_eth_dev *dev = &rte_eth_devices[pf->dev_data->port_id];
8244 if (pf->support_multi_driver) {
8245 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8246 return I40E_NOT_SUPPORTED;
8249 memset(&filter_replace, 0,
8250 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8251 memset(&filter_replace_buf, 0,
8252 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8254 if (l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8255 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
8256 filter_replace.new_filter_type =
8257 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8258 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X11;
8260 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
8261 filter_replace.new_filter_type =
8262 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8263 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
8266 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8267 filter_replace.tr_bit = 0;
8268 /* Prepare the buffer, 2 entries */
8269 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8270 filter_replace_buf.data[0] |=
8271 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8272 filter_replace_buf.data[4] |=
8273 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8274 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8275 &filter_replace_buf);
8277 if (!status && filter_replace.old_filter_type !=
8278 filter_replace.new_filter_type)
8279 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8280 " original: 0x%x, new: 0x%x",
8282 filter_replace.old_filter_type,
8283 filter_replace.new_filter_type);
8289 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8290 struct i40e_tunnel_filter_conf *tunnel_filter,
8294 uint32_t ipv4_addr, ipv4_addr_le;
8295 uint8_t i, tun_type = 0;
8296 /* internal variable to convert ipv6 byte order */
8297 uint32_t convert_ipv6[4];
8299 struct i40e_pf_vf *vf = NULL;
8300 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8301 struct i40e_vsi *vsi;
8302 struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8303 struct i40e_aqc_cloud_filters_element_bb *pfilter;
8304 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8305 struct i40e_tunnel_filter *tunnel, *node;
8306 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8308 bool big_buffer = 0;
8310 cld_filter = rte_zmalloc("tunnel_filter",
8311 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8314 if (cld_filter == NULL) {
8315 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8318 pfilter = cld_filter;
8320 rte_ether_addr_copy(&tunnel_filter->outer_mac,
8321 (struct rte_ether_addr *)&pfilter->element.outer_mac);
8322 rte_ether_addr_copy(&tunnel_filter->inner_mac,
8323 (struct rte_ether_addr *)&pfilter->element.inner_mac);
8325 pfilter->element.inner_vlan =
8326 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8327 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8328 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8329 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8330 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8331 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8333 sizeof(pfilter->element.ipaddr.v4.data));
8335 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8336 for (i = 0; i < 4; i++) {
8338 rte_cpu_to_le_32(rte_be_to_cpu_32(
8339 tunnel_filter->ip_addr.ipv6_addr[i]));
8341 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8343 sizeof(pfilter->element.ipaddr.v6.data));
8346 /* check tunneled type */
8347 switch (tunnel_filter->tunnel_type) {
8348 case I40E_TUNNEL_TYPE_VXLAN:
8349 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8351 case I40E_TUNNEL_TYPE_NVGRE:
8352 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8354 case I40E_TUNNEL_TYPE_IP_IN_GRE:
8355 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8357 case I40E_TUNNEL_TYPE_MPLSoUDP:
8358 if (!pf->mpls_replace_flag) {
8359 i40e_replace_mpls_l1_filter(pf);
8360 i40e_replace_mpls_cloud_filter(pf);
8361 pf->mpls_replace_flag = 1;
8363 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8364 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8366 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8367 (teid_le & 0xF) << 12;
8368 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8371 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8373 case I40E_TUNNEL_TYPE_MPLSoGRE:
8374 if (!pf->mpls_replace_flag) {
8375 i40e_replace_mpls_l1_filter(pf);
8376 i40e_replace_mpls_cloud_filter(pf);
8377 pf->mpls_replace_flag = 1;
8379 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8380 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8382 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8383 (teid_le & 0xF) << 12;
8384 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8387 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8389 case I40E_TUNNEL_TYPE_GTPC:
8390 if (!pf->gtp_replace_flag) {
8391 i40e_replace_gtp_l1_filter(pf);
8392 i40e_replace_gtp_cloud_filter(pf);
8393 pf->gtp_replace_flag = 1;
8395 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8396 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8397 (teid_le >> 16) & 0xFFFF;
8398 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8400 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8404 case I40E_TUNNEL_TYPE_GTPU:
8405 if (!pf->gtp_replace_flag) {
8406 i40e_replace_gtp_l1_filter(pf);
8407 i40e_replace_gtp_cloud_filter(pf);
8408 pf->gtp_replace_flag = 1;
8410 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8411 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8412 (teid_le >> 16) & 0xFFFF;
8413 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8415 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8419 case I40E_TUNNEL_TYPE_QINQ:
8420 if (!pf->qinq_replace_flag) {
8421 ret = i40e_cloud_filter_qinq_create(pf);
8424 "QinQ tunnel filter already created.");
8425 pf->qinq_replace_flag = 1;
8427 /* Add in the General fields the values of
8428 * the Outer and Inner VLAN
8429 * Big Buffer should be set, see changes in
8430 * i40e_aq_add_cloud_filters
8432 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8433 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8436 case I40E_CLOUD_TYPE_UDP:
8437 case I40E_CLOUD_TYPE_TCP:
8438 case I40E_CLOUD_TYPE_SCTP:
8439 if (tunnel_filter->l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8440 if (!pf->sport_replace_flag) {
8441 i40e_replace_port_l1_filter(pf,
8442 tunnel_filter->l4_port_type);
8443 i40e_replace_port_cloud_filter(pf,
8444 tunnel_filter->l4_port_type);
8445 pf->sport_replace_flag = 1;
8447 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8448 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8449 I40E_DIRECTION_INGRESS_KEY;
8451 if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP)
8452 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8453 I40E_TR_L4_TYPE_UDP;
8454 else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP)
8455 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8456 I40E_TR_L4_TYPE_TCP;
8458 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8459 I40E_TR_L4_TYPE_SCTP;
8461 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8462 (teid_le >> 16) & 0xFFFF;
8465 if (!pf->dport_replace_flag) {
8466 i40e_replace_port_l1_filter(pf,
8467 tunnel_filter->l4_port_type);
8468 i40e_replace_port_cloud_filter(pf,
8469 tunnel_filter->l4_port_type);
8470 pf->dport_replace_flag = 1;
8472 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8473 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0] =
8474 I40E_DIRECTION_INGRESS_KEY;
8476 if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP)
8477 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8478 I40E_TR_L4_TYPE_UDP;
8479 else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP)
8480 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8481 I40E_TR_L4_TYPE_TCP;
8483 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8484 I40E_TR_L4_TYPE_SCTP;
8486 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2] =
8487 (teid_le >> 16) & 0xFFFF;
8493 /* Other tunnel types is not supported. */
8494 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8495 rte_free(cld_filter);
8499 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8500 pfilter->element.flags =
8501 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8502 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8503 pfilter->element.flags =
8504 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8505 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8506 pfilter->element.flags =
8507 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8508 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8509 pfilter->element.flags =
8510 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8511 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8512 pfilter->element.flags |=
8513 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8514 else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP ||
8515 tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP ||
8516 tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_SCTP) {
8517 if (tunnel_filter->l4_port_type == I40E_L4_PORT_TYPE_SRC)
8518 pfilter->element.flags |=
8519 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8521 pfilter->element.flags |=
8522 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8524 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8525 &pfilter->element.flags);
8527 rte_free(cld_filter);
8532 pfilter->element.flags |= rte_cpu_to_le_16(
8533 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8534 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8535 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8536 pfilter->element.queue_number =
8537 rte_cpu_to_le_16(tunnel_filter->queue_id);
8539 if (!tunnel_filter->is_to_vf)
8542 if (tunnel_filter->vf_id >= pf->vf_num) {
8543 PMD_DRV_LOG(ERR, "Invalid argument.");
8544 rte_free(cld_filter);
8547 vf = &pf->vfs[tunnel_filter->vf_id];
8551 /* Check if there is the filter in SW list */
8552 memset(&check_filter, 0, sizeof(check_filter));
8553 i40e_tunnel_filter_convert(cld_filter, &check_filter);
8554 check_filter.is_to_vf = tunnel_filter->is_to_vf;
8555 check_filter.vf_id = tunnel_filter->vf_id;
8556 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8558 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8559 rte_free(cld_filter);
8563 if (!add && !node) {
8564 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8565 rte_free(cld_filter);
8571 ret = i40e_aq_add_cloud_filters_bb(hw,
8572 vsi->seid, cld_filter, 1);
8574 ret = i40e_aq_add_cloud_filters(hw,
8575 vsi->seid, &cld_filter->element, 1);
8577 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8578 rte_free(cld_filter);
8581 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8582 if (tunnel == NULL) {
8583 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8584 rte_free(cld_filter);
8588 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8589 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8594 ret = i40e_aq_rem_cloud_filters_bb(
8595 hw, vsi->seid, cld_filter, 1);
8597 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8598 &cld_filter->element, 1);
8600 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8601 rte_free(cld_filter);
8604 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8607 rte_free(cld_filter);
8612 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8616 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8617 if (pf->vxlan_ports[i] == port)
8625 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port, int udp_type)
8628 uint8_t filter_idx = 0;
8629 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8631 idx = i40e_get_vxlan_port_idx(pf, port);
8633 /* Check if port already exists */
8635 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8639 /* Now check if there is space to add the new port */
8640 idx = i40e_get_vxlan_port_idx(pf, 0);
8643 "Maximum number of UDP ports reached, not adding port %d",
8648 ret = i40e_aq_add_udp_tunnel(hw, port, udp_type,
8651 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8655 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8658 /* New port: add it and mark its index in the bitmap */
8659 pf->vxlan_ports[idx] = port;
8660 pf->vxlan_bitmap |= (1 << idx);
8662 if (!(pf->flags & I40E_FLAG_VXLAN))
8663 pf->flags |= I40E_FLAG_VXLAN;
8669 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8672 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8674 if (!(pf->flags & I40E_FLAG_VXLAN)) {
8675 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8679 idx = i40e_get_vxlan_port_idx(pf, port);
8682 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8686 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8687 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8691 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8694 pf->vxlan_ports[idx] = 0;
8695 pf->vxlan_bitmap &= ~(1 << idx);
8697 if (!pf->vxlan_bitmap)
8698 pf->flags &= ~I40E_FLAG_VXLAN;
8703 /* Add UDP tunneling port */
8705 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8706 struct rte_eth_udp_tunnel *udp_tunnel)
8709 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8711 if (udp_tunnel == NULL)
8714 switch (udp_tunnel->prot_type) {
8715 case RTE_TUNNEL_TYPE_VXLAN:
8716 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8717 I40E_AQC_TUNNEL_TYPE_VXLAN);
8719 case RTE_TUNNEL_TYPE_VXLAN_GPE:
8720 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8721 I40E_AQC_TUNNEL_TYPE_VXLAN_GPE);
8723 case RTE_TUNNEL_TYPE_GENEVE:
8724 case RTE_TUNNEL_TYPE_TEREDO:
8725 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8730 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8738 /* Remove UDP tunneling port */
8740 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8741 struct rte_eth_udp_tunnel *udp_tunnel)
8744 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8746 if (udp_tunnel == NULL)
8749 switch (udp_tunnel->prot_type) {
8750 case RTE_TUNNEL_TYPE_VXLAN:
8751 case RTE_TUNNEL_TYPE_VXLAN_GPE:
8752 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8754 case RTE_TUNNEL_TYPE_GENEVE:
8755 case RTE_TUNNEL_TYPE_TEREDO:
8756 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8760 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8768 /* Calculate the maximum number of contiguous PF queues that are configured */
8770 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8772 struct rte_eth_dev_data *data = pf->dev_data;
8774 struct i40e_rx_queue *rxq;
8777 for (i = 0; i < pf->lan_nb_qps; i++) {
8778 rxq = data->rx_queues[i];
8779 if (rxq && rxq->q_set)
8788 /* Reset the global configure of hash function and input sets */
8790 i40e_pf_global_rss_reset(struct i40e_pf *pf)
8792 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8793 uint32_t reg, reg_val;
8796 /* Reset global RSS function sets */
8797 reg_val = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8798 if (!(reg_val & I40E_GLQF_CTL_HTOEP_MASK)) {
8799 reg_val |= I40E_GLQF_CTL_HTOEP_MASK;
8800 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg_val);
8803 for (i = 0; i <= I40E_FILTER_PCTYPE_L2_PAYLOAD; i++) {
8807 if (hw->mac.type == I40E_MAC_X722)
8808 pctype = i40e_read_rx_ctl(hw, I40E_GLQF_FD_PCTYPES(i));
8812 /* Reset pctype insets */
8813 inset = i40e_get_default_input_set(i);
8815 pf->hash_input_set[pctype] = inset;
8816 inset = i40e_translate_input_set_reg(hw->mac.type,
8819 reg = I40E_GLQF_HASH_INSET(0, pctype);
8820 i40e_check_write_global_reg(hw, reg, (uint32_t)inset);
8821 reg = I40E_GLQF_HASH_INSET(1, pctype);
8822 i40e_check_write_global_reg(hw, reg,
8823 (uint32_t)(inset >> 32));
8825 /* Clear unused mask registers of the pctype */
8826 for (j = 0; j < I40E_INSET_MASK_NUM_REG; j++) {
8827 reg = I40E_GLQF_HASH_MSK(j, pctype);
8828 i40e_check_write_global_reg(hw, reg, 0);
8832 /* Reset pctype symmetric sets */
8833 reg = I40E_GLQF_HSYM(pctype);
8834 reg_val = i40e_read_rx_ctl(hw, reg);
8835 if (reg_val & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8836 reg_val &= ~I40E_GLQF_HSYM_SYMH_ENA_MASK;
8837 i40e_write_global_rx_ctl(hw, reg, reg_val);
8840 I40E_WRITE_FLUSH(hw);
8844 i40e_pf_reset_rss_reta(struct i40e_pf *pf)
8846 struct i40e_hw *hw = &pf->adapter->hw;
8847 uint8_t lut[ETH_RSS_RETA_SIZE_512];
8851 /* If both VMDQ and RSS enabled, not all of PF queues are
8852 * configured. It's necessary to calculate the actual PF
8853 * queues that are configured.
8855 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8856 num = i40e_pf_calc_configured_queues_num(pf);
8858 num = pf->dev_data->nb_rx_queues;
8860 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8864 for (i = 0; i < hw->func_caps.rss_table_size; i++)
8865 lut[i] = (uint8_t)(i % (uint32_t)num);
8867 return i40e_set_rss_lut(pf->main_vsi, lut, (uint16_t)i);
8871 i40e_pf_reset_rss_key(struct i40e_pf *pf)
8873 const uint8_t key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8878 rss_key = pf->dev_data->dev_conf.rx_adv_conf.rss_conf.rss_key;
8880 pf->dev_data->dev_conf.rx_adv_conf.rss_conf.rss_key_len < key_len) {
8881 static uint32_t rss_key_default[] = {0x6b793944,
8882 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8883 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8884 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8886 rss_key = (uint8_t *)rss_key_default;
8889 return i40e_set_rss_key(pf->main_vsi, rss_key, key_len);
8893 i40e_pf_rss_reset(struct i40e_pf *pf)
8895 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8899 pf->hash_filter_enabled = 0;
8900 i40e_pf_disable_rss(pf);
8901 i40e_set_symmetric_hash_enable_per_port(hw, 0);
8903 if (!pf->support_multi_driver)
8904 i40e_pf_global_rss_reset(pf);
8906 /* Reset RETA table */
8907 if (pf->adapter->rss_reta_updated == 0) {
8908 ret = i40e_pf_reset_rss_reta(pf);
8913 return i40e_pf_reset_rss_key(pf);
8918 i40e_pf_config_rss(struct i40e_pf *pf)
8921 enum rte_eth_rx_mq_mode mq_mode;
8922 uint64_t rss_hf, hena;
8925 ret = i40e_pf_rss_reset(pf);
8927 PMD_DRV_LOG(ERR, "Reset RSS failed, RSS has been disabled");
8931 rss_hf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf.rss_hf;
8932 mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8933 if (!(rss_hf & pf->adapter->flow_types_mask) ||
8934 !(mq_mode & ETH_MQ_RX_RSS_FLAG))
8937 hw = I40E_PF_TO_HW(pf);
8938 hena = i40e_config_hena(pf->adapter, rss_hf);
8939 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
8940 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
8941 I40E_WRITE_FLUSH(hw);
8946 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8947 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
8949 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8951 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8955 if (pf->support_multi_driver) {
8956 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8960 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8961 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8964 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8965 } else if (len == 4) {
8966 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8968 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8973 ret = i40e_aq_debug_write_global_register(hw,
8974 I40E_GL_PRS_FVBM(2),
8978 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8979 "with value 0x%08x",
8980 I40E_GL_PRS_FVBM(2), reg);
8984 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8985 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8990 /* Set the symmetric hash enable configurations per port */
8992 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8994 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8997 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)
9000 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
9002 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK))
9005 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
9007 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
9008 I40E_WRITE_FLUSH(hw);
9012 * Valid input sets for hash and flow director filters per PCTYPE
9015 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
9016 enum rte_filter_type filter)
9020 static const uint64_t valid_hash_inset_table[] = {
9021 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9022 I40E_INSET_DMAC | I40E_INSET_SMAC |
9023 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9024 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
9025 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
9026 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9027 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9028 I40E_INSET_FLEX_PAYLOAD,
9029 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9030 I40E_INSET_DMAC | I40E_INSET_SMAC |
9031 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9032 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9033 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9034 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9035 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9036 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9037 I40E_INSET_FLEX_PAYLOAD,
9038 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9039 I40E_INSET_DMAC | I40E_INSET_SMAC |
9040 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9041 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9042 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9043 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9044 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9045 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9046 I40E_INSET_FLEX_PAYLOAD,
9047 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9048 I40E_INSET_DMAC | I40E_INSET_SMAC |
9049 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9050 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9051 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9052 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9053 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9054 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9055 I40E_INSET_FLEX_PAYLOAD,
9056 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9057 I40E_INSET_DMAC | I40E_INSET_SMAC |
9058 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9059 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9060 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9061 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9062 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9063 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9064 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9065 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9066 I40E_INSET_DMAC | I40E_INSET_SMAC |
9067 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9068 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9069 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9070 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9071 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9072 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9073 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9074 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9075 I40E_INSET_DMAC | I40E_INSET_SMAC |
9076 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9077 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9078 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9079 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9080 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9081 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9082 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
9083 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9084 I40E_INSET_DMAC | I40E_INSET_SMAC |
9085 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9086 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9087 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9088 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9089 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9090 I40E_INSET_FLEX_PAYLOAD,
9091 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9092 I40E_INSET_DMAC | I40E_INSET_SMAC |
9093 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9094 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9095 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9096 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
9097 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
9098 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
9099 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9100 I40E_INSET_DMAC | I40E_INSET_SMAC |
9101 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9102 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9103 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9104 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9105 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9106 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
9107 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9108 I40E_INSET_DMAC | I40E_INSET_SMAC |
9109 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9110 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9111 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9112 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9113 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9114 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9115 I40E_INSET_FLEX_PAYLOAD,
9116 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9117 I40E_INSET_DMAC | I40E_INSET_SMAC |
9118 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9119 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9120 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9121 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9122 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9123 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9124 I40E_INSET_FLEX_PAYLOAD,
9125 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9126 I40E_INSET_DMAC | I40E_INSET_SMAC |
9127 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9128 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9129 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9130 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9131 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9132 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9133 I40E_INSET_FLEX_PAYLOAD,
9134 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9135 I40E_INSET_DMAC | I40E_INSET_SMAC |
9136 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9137 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9138 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9139 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9140 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9141 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9142 I40E_INSET_FLEX_PAYLOAD,
9143 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9144 I40E_INSET_DMAC | I40E_INSET_SMAC |
9145 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9146 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9147 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9148 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9149 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9150 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9151 I40E_INSET_FLEX_PAYLOAD,
9152 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9153 I40E_INSET_DMAC | I40E_INSET_SMAC |
9154 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9155 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9156 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9157 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9158 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9159 I40E_INSET_FLEX_PAYLOAD,
9160 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9161 I40E_INSET_DMAC | I40E_INSET_SMAC |
9162 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9163 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9164 I40E_INSET_FLEX_PAYLOAD,
9168 * Flow director supports only fields defined in
9169 * union rte_eth_fdir_flow.
9171 static const uint64_t valid_fdir_inset_table[] = {
9172 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9173 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9174 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9175 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9176 I40E_INSET_IPV4_TTL,
9177 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9178 I40E_INSET_DMAC | I40E_INSET_SMAC |
9179 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9180 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9181 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9182 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9183 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9184 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9185 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9186 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9187 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9188 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9189 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9190 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9191 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9192 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9193 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9194 I40E_INSET_DMAC | I40E_INSET_SMAC |
9195 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9196 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9197 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9198 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9199 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9200 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9201 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9202 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9203 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9204 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9205 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9206 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9207 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9208 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9210 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9211 I40E_INSET_DMAC | I40E_INSET_SMAC |
9212 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9213 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9214 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9215 I40E_INSET_IPV4_TTL,
9216 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9217 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9218 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9219 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9220 I40E_INSET_IPV6_HOP_LIMIT,
9221 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9222 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9223 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9224 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9225 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9226 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9227 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9228 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9229 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9230 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9231 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9232 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9233 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9234 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9235 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9236 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9237 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9238 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9239 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9240 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9241 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9242 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9243 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9244 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9245 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9246 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9247 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9248 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9249 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9250 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9252 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9253 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9254 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9255 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9256 I40E_INSET_IPV6_HOP_LIMIT,
9257 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9258 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9259 I40E_INSET_LAST_ETHER_TYPE,
9262 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9264 if (filter == RTE_ETH_FILTER_HASH)
9265 valid = valid_hash_inset_table[pctype];
9267 valid = valid_fdir_inset_table[pctype];
9273 * Validate if the input set is allowed for a specific PCTYPE
9276 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9277 enum rte_filter_type filter, uint64_t inset)
9281 valid = i40e_get_valid_input_set(pctype, filter);
9282 if (inset & (~valid))
9288 /* default input set fields combination per pctype */
9290 i40e_get_default_input_set(uint16_t pctype)
9292 static const uint64_t default_inset_table[] = {
9293 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9294 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9295 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9296 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9297 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9298 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9299 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9300 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9301 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9302 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9303 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9304 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9305 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9306 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9307 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9308 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9309 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9310 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9311 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9312 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9314 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9315 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9316 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9317 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9318 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9319 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9320 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9321 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9322 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9323 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9324 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9325 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9326 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9327 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9328 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9329 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9330 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9331 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9332 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9333 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9334 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9335 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9337 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9338 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9339 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9340 I40E_INSET_LAST_ETHER_TYPE,
9343 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9346 return default_inset_table[pctype];
9350 * Translate the input set from bit masks to register aware bit masks
9354 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9364 static const struct inset_map inset_map_common[] = {
9365 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9366 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9367 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9368 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9369 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9370 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9371 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9372 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9373 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9374 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9375 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9376 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9377 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9378 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9379 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9380 {I40E_INSET_TUNNEL_DMAC,
9381 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9382 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9383 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9384 {I40E_INSET_TUNNEL_SRC_PORT,
9385 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9386 {I40E_INSET_TUNNEL_DST_PORT,
9387 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9388 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9389 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9390 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9391 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9392 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9393 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9394 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9395 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9396 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9399 /* some different registers map in x722*/
9400 static const struct inset_map inset_map_diff_x722[] = {
9401 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9402 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9403 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9404 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9407 static const struct inset_map inset_map_diff_not_x722[] = {
9408 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9409 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9410 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9411 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9417 /* Translate input set to register aware inset */
9418 if (type == I40E_MAC_X722) {
9419 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9420 if (input & inset_map_diff_x722[i].inset)
9421 val |= inset_map_diff_x722[i].inset_reg;
9424 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9425 if (input & inset_map_diff_not_x722[i].inset)
9426 val |= inset_map_diff_not_x722[i].inset_reg;
9430 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9431 if (input & inset_map_common[i].inset)
9432 val |= inset_map_common[i].inset_reg;
9439 i40e_get_inset_field_offset(struct i40e_hw *hw, uint32_t pit_reg_start,
9440 uint32_t pit_reg_count, uint32_t hdr_off)
9442 const uint32_t pit_reg_end = pit_reg_start + pit_reg_count;
9443 uint32_t field_off = I40E_FDIR_FIELD_OFFSET(hdr_off);
9444 uint32_t i, reg_val, src_off, count;
9446 for (i = pit_reg_start; i < pit_reg_end; i++) {
9447 reg_val = i40e_read_rx_ctl(hw, I40E_GLQF_PIT(i));
9449 src_off = I40E_GLQF_PIT_SOURCE_OFF_GET(reg_val);
9450 count = I40E_GLQF_PIT_FSIZE_GET(reg_val);
9452 if (src_off <= field_off && (src_off + count) > field_off)
9456 if (i >= pit_reg_end) {
9458 "Hardware GLQF_PIT configuration does not support this field mask");
9462 return I40E_GLQF_PIT_DEST_OFF_GET(reg_val) + field_off - src_off;
9466 i40e_generate_inset_mask_reg(struct i40e_hw *hw, uint64_t inset,
9467 uint32_t *mask, uint8_t nb_elem)
9469 static const uint64_t mask_inset[] = {
9470 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL,
9471 I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT };
9473 static const struct {
9477 } inset_mask_offset_map[] = {
9478 { I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK,
9479 offsetof(struct rte_ipv4_hdr, type_of_service) },
9481 { I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK,
9482 offsetof(struct rte_ipv4_hdr, next_proto_id) },
9484 { I40E_INSET_IPV4_TTL, I40E_INSET_IPV4_TTL_MASK,
9485 offsetof(struct rte_ipv4_hdr, time_to_live) },
9487 { I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK,
9488 offsetof(struct rte_ipv6_hdr, vtc_flow) },
9490 { I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK,
9491 offsetof(struct rte_ipv6_hdr, proto) },
9493 { I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK,
9494 offsetof(struct rte_ipv6_hdr, hop_limits) },
9504 for (i = 0; i < RTE_DIM(mask_inset); i++) {
9505 /* Clear the inset bit, if no MASK is required,
9506 * for example proto + ttl
9508 if ((mask_inset[i] & inset) == mask_inset[i]) {
9509 inset &= ~mask_inset[i];
9515 for (i = 0; i < RTE_DIM(inset_mask_offset_map); i++) {
9516 uint32_t pit_start, pit_count;
9519 if (!(inset_mask_offset_map[i].inset & inset))
9522 if (inset_mask_offset_map[i].inset &
9523 (I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9524 I40E_INSET_IPV4_TTL)) {
9525 pit_start = I40E_GLQF_PIT_IPV4_START;
9526 pit_count = I40E_GLQF_PIT_IPV4_COUNT;
9528 pit_start = I40E_GLQF_PIT_IPV6_START;
9529 pit_count = I40E_GLQF_PIT_IPV6_COUNT;
9532 offset = i40e_get_inset_field_offset(hw, pit_start, pit_count,
9533 inset_mask_offset_map[i].offset);
9538 if (idx >= nb_elem) {
9540 "Configuration of inset mask out of range %u",
9545 mask[idx] = I40E_GLQF_PIT_BUILD((uint32_t)offset,
9546 inset_mask_offset_map[i].mask);
9554 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9556 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9558 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9560 i40e_write_rx_ctl(hw, addr, val);
9561 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9562 (uint32_t)i40e_read_rx_ctl(hw, addr));
9566 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9568 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9569 struct rte_eth_dev_data *dev_data =
9570 ((struct i40e_adapter *)hw->back)->pf.dev_data;
9571 struct rte_eth_dev *dev = &rte_eth_devices[dev_data->port_id];
9574 i40e_write_rx_ctl(hw, addr, val);
9575 PMD_DRV_LOG(WARNING,
9576 "i40e device %s changed global register [0x%08x]."
9577 " original: 0x%08x, new: 0x%08x",
9578 dev->device->name, addr, reg,
9579 (uint32_t)i40e_read_rx_ctl(hw, addr));
9584 i40e_filter_input_set_init(struct i40e_pf *pf)
9586 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9587 enum i40e_filter_pctype pctype;
9588 uint64_t input_set, inset_reg;
9589 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9593 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9594 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9595 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9597 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9600 input_set = i40e_get_default_input_set(pctype);
9602 num = i40e_generate_inset_mask_reg(hw, input_set, mask_reg,
9603 I40E_INSET_MASK_NUM_REG);
9606 if (pf->support_multi_driver && num > 0) {
9607 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9610 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9613 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9614 (uint32_t)(inset_reg & UINT32_MAX));
9615 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9616 (uint32_t)((inset_reg >>
9617 I40E_32_BIT_WIDTH) & UINT32_MAX));
9618 if (!pf->support_multi_driver) {
9619 i40e_check_write_global_reg(hw,
9620 I40E_GLQF_HASH_INSET(0, pctype),
9621 (uint32_t)(inset_reg & UINT32_MAX));
9622 i40e_check_write_global_reg(hw,
9623 I40E_GLQF_HASH_INSET(1, pctype),
9624 (uint32_t)((inset_reg >>
9625 I40E_32_BIT_WIDTH) & UINT32_MAX));
9627 for (i = 0; i < num; i++) {
9628 i40e_check_write_global_reg(hw,
9629 I40E_GLQF_FD_MSK(i, pctype),
9631 i40e_check_write_global_reg(hw,
9632 I40E_GLQF_HASH_MSK(i, pctype),
9635 /*clear unused mask registers of the pctype */
9636 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9637 i40e_check_write_global_reg(hw,
9638 I40E_GLQF_FD_MSK(i, pctype),
9640 i40e_check_write_global_reg(hw,
9641 I40E_GLQF_HASH_MSK(i, pctype),
9645 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9647 I40E_WRITE_FLUSH(hw);
9649 /* store the default input set */
9650 if (!pf->support_multi_driver)
9651 pf->hash_input_set[pctype] = input_set;
9652 pf->fdir.input_set[pctype] = input_set;
9657 i40e_set_hash_inset(struct i40e_hw *hw, uint64_t input_set,
9658 uint32_t pctype, bool add)
9660 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9661 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9662 uint64_t inset_reg = 0;
9665 if (pf->support_multi_driver) {
9667 "Modify input set is not permitted when multi-driver enabled.");
9671 /* For X722, get translated pctype in fd pctype register */
9672 if (hw->mac.type == I40E_MAC_X722)
9673 pctype = i40e_read_rx_ctl(hw, I40E_GLQF_FD_PCTYPES(pctype));
9676 /* get inset value in register */
9677 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9678 inset_reg <<= I40E_32_BIT_WIDTH;
9679 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9680 input_set |= pf->hash_input_set[pctype];
9682 num = i40e_generate_inset_mask_reg(hw, input_set, mask_reg,
9683 I40E_INSET_MASK_NUM_REG);
9687 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9689 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9690 (uint32_t)(inset_reg & UINT32_MAX));
9691 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9692 (uint32_t)((inset_reg >>
9693 I40E_32_BIT_WIDTH) & UINT32_MAX));
9695 for (i = 0; i < num; i++)
9696 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9698 /*clear unused mask registers of the pctype */
9699 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9700 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9702 I40E_WRITE_FLUSH(hw);
9704 pf->hash_input_set[pctype] = input_set;
9708 /* Convert ethertype filter structure */
9710 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9711 struct i40e_ethertype_filter *filter)
9713 rte_memcpy(&filter->input.mac_addr, &input->mac_addr,
9714 RTE_ETHER_ADDR_LEN);
9715 filter->input.ether_type = input->ether_type;
9716 filter->flags = input->flags;
9717 filter->queue = input->queue;
9722 /* Check if there exists the ehtertype filter */
9723 struct i40e_ethertype_filter *
9724 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9725 const struct i40e_ethertype_filter_input *input)
9729 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9733 return ethertype_rule->hash_map[ret];
9736 /* Add ethertype filter in SW list */
9738 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9739 struct i40e_ethertype_filter *filter)
9741 struct i40e_ethertype_rule *rule = &pf->ethertype;
9744 ret = rte_hash_add_key(rule->hash_table, &filter->input);
9747 "Failed to insert ethertype filter"
9748 " to hash table %d!",
9752 rule->hash_map[ret] = filter;
9754 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9759 /* Delete ethertype filter in SW list */
9761 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9762 struct i40e_ethertype_filter_input *input)
9764 struct i40e_ethertype_rule *rule = &pf->ethertype;
9765 struct i40e_ethertype_filter *filter;
9768 ret = rte_hash_del_key(rule->hash_table, input);
9771 "Failed to delete ethertype filter"
9772 " to hash table %d!",
9776 filter = rule->hash_map[ret];
9777 rule->hash_map[ret] = NULL;
9779 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9786 * Configure ethertype filter, which can director packet by filtering
9787 * with mac address and ether_type or only ether_type
9790 i40e_ethertype_filter_set(struct i40e_pf *pf,
9791 struct rte_eth_ethertype_filter *filter,
9794 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9795 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9796 struct i40e_ethertype_filter *ethertype_filter, *node;
9797 struct i40e_ethertype_filter check_filter;
9798 struct i40e_control_filter_stats stats;
9802 if (filter->queue >= pf->dev_data->nb_rx_queues) {
9803 PMD_DRV_LOG(ERR, "Invalid queue ID");
9806 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
9807 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
9809 "unsupported ether_type(0x%04x) in control packet filter.",
9810 filter->ether_type);
9813 if (filter->ether_type == RTE_ETHER_TYPE_VLAN)
9814 PMD_DRV_LOG(WARNING,
9815 "filter vlan ether_type in first tag is not supported.");
9817 /* Check if there is the filter in SW list */
9818 memset(&check_filter, 0, sizeof(check_filter));
9819 i40e_ethertype_filter_convert(filter, &check_filter);
9820 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9821 &check_filter.input);
9823 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9827 if (!add && !node) {
9828 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9832 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9833 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9834 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9835 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9836 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9838 memset(&stats, 0, sizeof(stats));
9839 ret = i40e_aq_add_rem_control_packet_filter(hw,
9840 filter->mac_addr.addr_bytes,
9841 filter->ether_type, flags,
9843 filter->queue, add, &stats, NULL);
9846 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9847 ret, stats.mac_etype_used, stats.etype_used,
9848 stats.mac_etype_free, stats.etype_free);
9852 /* Add or delete a filter in SW list */
9854 ethertype_filter = rte_zmalloc("ethertype_filter",
9855 sizeof(*ethertype_filter), 0);
9856 if (ethertype_filter == NULL) {
9857 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
9861 rte_memcpy(ethertype_filter, &check_filter,
9862 sizeof(check_filter));
9863 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9865 rte_free(ethertype_filter);
9867 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9874 i40e_dev_flow_ops_get(struct rte_eth_dev *dev,
9875 const struct rte_flow_ops **ops)
9880 *ops = &i40e_flow_ops;
9885 * Check and enable Extended Tag.
9886 * Enabling Extended Tag is important for 40G performance.
9889 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9891 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9895 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9898 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9902 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9903 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9908 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9911 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9915 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9916 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9919 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9920 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9923 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9930 * As some registers wouldn't be reset unless a global hardware reset,
9931 * hardware initialization is needed to put those registers into an
9932 * expected initial state.
9935 i40e_hw_init(struct rte_eth_dev *dev)
9937 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9939 i40e_enable_extended_tag(dev);
9941 /* clear the PF Queue Filter control register */
9942 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9944 /* Disable symmetric hash per port */
9945 i40e_set_symmetric_hash_enable_per_port(hw, 0);
9949 * For X722 it is possible to have multiple pctypes mapped to the same flowtype
9950 * however this function will return only one highest pctype index,
9951 * which is not quite correct. This is known problem of i40e driver
9952 * and needs to be fixed later.
9954 enum i40e_filter_pctype
9955 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
9958 uint64_t pctype_mask;
9960 if (flow_type < I40E_FLOW_TYPE_MAX) {
9961 pctype_mask = adapter->pctypes_tbl[flow_type];
9962 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
9963 if (pctype_mask & (1ULL << i))
9964 return (enum i40e_filter_pctype)i;
9967 return I40E_FILTER_PCTYPE_INVALID;
9971 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
9972 enum i40e_filter_pctype pctype)
9975 uint64_t pctype_mask = 1ULL << pctype;
9977 for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
9979 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
9983 return RTE_ETH_FLOW_UNKNOWN;
9987 * On X710, performance number is far from the expectation on recent firmware
9988 * versions; on XL710, performance number is also far from the expectation on
9989 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9990 * mode is enabled and port MAC address is equal to the packet destination MAC
9991 * address. The fix for this issue may not be integrated in the following
9992 * firmware version. So the workaround in software driver is needed. It needs
9993 * to modify the initial values of 3 internal only registers for both X710 and
9994 * XL710. Note that the values for X710 or XL710 could be different, and the
9995 * workaround can be removed when it is fixed in firmware in the future.
9998 /* For both X710 and XL710 */
9999 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1 0x10000200
10000 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x203F0200
10001 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
10003 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10004 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
10007 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10008 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10011 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
10013 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
10014 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
10017 * GL_SWR_PM_UP_THR:
10018 * The value is not impacted from the link speed, its value is set according
10019 * to the total number of ports for a better pipe-monitor configuration.
10022 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10024 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10025 .device_id = (dev), \
10026 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10028 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10029 .device_id = (dev), \
10030 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10032 static const struct {
10033 uint16_t device_id;
10035 } swr_pm_table[] = {
10036 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10037 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10038 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10039 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10040 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_X722) },
10042 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10043 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10044 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10045 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10046 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10047 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10048 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10052 if (value == NULL) {
10053 PMD_DRV_LOG(ERR, "value is NULL");
10057 for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10058 if (hw->device_id == swr_pm_table[i].device_id) {
10059 *value = swr_pm_table[i].val;
10061 PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10063 hw->device_id, *value);
10072 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10074 enum i40e_status_code status;
10075 struct i40e_aq_get_phy_abilities_resp phy_ab;
10076 int ret = -ENOTSUP;
10079 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10083 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10086 rte_delay_us(100000);
10088 status = i40e_aq_get_phy_capabilities(hw, false,
10089 true, &phy_ab, NULL);
10097 i40e_configure_registers(struct i40e_hw *hw)
10103 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10104 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10105 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10111 for (i = 0; i < RTE_DIM(reg_table); i++) {
10112 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10113 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10115 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10116 else /* For X710/XL710/XXV710 */
10117 if (hw->aq.fw_maj_ver < 6)
10119 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10122 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10125 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10126 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10128 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10129 else /* For X710/XL710/XXV710 */
10131 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10134 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10137 if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10138 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10139 "GL_SWR_PM_UP_THR value fixup",
10144 reg_table[i].val = cfg_val;
10147 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10150 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10151 reg_table[i].addr);
10154 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10155 reg_table[i].addr, reg);
10156 if (reg == reg_table[i].val)
10159 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10160 reg_table[i].val, NULL);
10163 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10164 reg_table[i].val, reg_table[i].addr);
10167 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10168 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10172 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
10173 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
10174 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10176 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10181 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10182 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10186 /* Configure for double VLAN RX stripping */
10187 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10188 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10189 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10190 ret = i40e_aq_debug_write_register(hw,
10191 I40E_VSI_TSR(vsi->vsi_id),
10194 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10196 return I40E_ERR_CONFIG;
10200 /* Configure for double VLAN TX insertion */
10201 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10202 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10203 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10204 ret = i40e_aq_debug_write_register(hw,
10205 I40E_VSI_L2TAGSTXVALID(
10206 vsi->vsi_id), reg, NULL);
10209 "Failed to update VSI_L2TAGSTXVALID[%d]",
10211 return I40E_ERR_CONFIG;
10219 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10221 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10222 uint64_t systim_cycles;
10224 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10225 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10228 return systim_cycles;
10232 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10234 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10235 uint64_t rx_tstamp;
10237 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10238 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10245 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10247 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10248 uint64_t tx_tstamp;
10250 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10251 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10258 i40e_start_timecounters(struct rte_eth_dev *dev)
10260 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10261 struct i40e_adapter *adapter = dev->data->dev_private;
10262 struct rte_eth_link link;
10263 uint32_t tsync_inc_l;
10264 uint32_t tsync_inc_h;
10266 /* Get current link speed. */
10267 i40e_dev_link_update(dev, 1);
10268 rte_eth_linkstatus_get(dev, &link);
10270 switch (link.link_speed) {
10271 case ETH_SPEED_NUM_40G:
10272 case ETH_SPEED_NUM_25G:
10273 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10274 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10276 case ETH_SPEED_NUM_10G:
10277 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10278 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10280 case ETH_SPEED_NUM_1G:
10281 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10282 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10289 /* Set the timesync increment value. */
10290 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10291 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10293 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10294 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10295 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10297 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10298 adapter->systime_tc.cc_shift = 0;
10299 adapter->systime_tc.nsec_mask = 0;
10301 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10302 adapter->rx_tstamp_tc.cc_shift = 0;
10303 adapter->rx_tstamp_tc.nsec_mask = 0;
10305 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10306 adapter->tx_tstamp_tc.cc_shift = 0;
10307 adapter->tx_tstamp_tc.nsec_mask = 0;
10311 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10313 struct i40e_adapter *adapter = dev->data->dev_private;
10315 adapter->systime_tc.nsec += delta;
10316 adapter->rx_tstamp_tc.nsec += delta;
10317 adapter->tx_tstamp_tc.nsec += delta;
10323 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10326 struct i40e_adapter *adapter = dev->data->dev_private;
10328 ns = rte_timespec_to_ns(ts);
10330 /* Set the timecounters to a new value. */
10331 adapter->systime_tc.nsec = ns;
10332 adapter->rx_tstamp_tc.nsec = ns;
10333 adapter->tx_tstamp_tc.nsec = ns;
10339 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10341 uint64_t ns, systime_cycles;
10342 struct i40e_adapter *adapter = dev->data->dev_private;
10344 systime_cycles = i40e_read_systime_cyclecounter(dev);
10345 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10346 *ts = rte_ns_to_timespec(ns);
10352 i40e_timesync_enable(struct rte_eth_dev *dev)
10354 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10355 uint32_t tsync_ctl_l;
10356 uint32_t tsync_ctl_h;
10358 /* Stop the timesync system time. */
10359 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10360 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10361 /* Reset the timesync system time value. */
10362 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10363 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10365 i40e_start_timecounters(dev);
10367 /* Clear timesync registers. */
10368 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10369 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10370 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10371 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10372 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10373 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10375 /* Enable timestamping of PTP packets. */
10376 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10377 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10379 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10380 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10381 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10383 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10384 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10390 i40e_timesync_disable(struct rte_eth_dev *dev)
10392 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10393 uint32_t tsync_ctl_l;
10394 uint32_t tsync_ctl_h;
10396 /* Disable timestamping of transmitted PTP packets. */
10397 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10398 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10400 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10401 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10403 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10404 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10406 /* Reset the timesync increment value. */
10407 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10408 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10414 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10415 struct timespec *timestamp, uint32_t flags)
10417 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10418 struct i40e_adapter *adapter = dev->data->dev_private;
10419 uint32_t sync_status;
10420 uint32_t index = flags & 0x03;
10421 uint64_t rx_tstamp_cycles;
10424 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10425 if ((sync_status & (1 << index)) == 0)
10428 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10429 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10430 *timestamp = rte_ns_to_timespec(ns);
10436 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10437 struct timespec *timestamp)
10439 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10440 struct i40e_adapter *adapter = dev->data->dev_private;
10441 uint32_t sync_status;
10442 uint64_t tx_tstamp_cycles;
10445 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10446 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10449 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10450 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10451 *timestamp = rte_ns_to_timespec(ns);
10457 * i40e_parse_dcb_configure - parse dcb configure from user
10458 * @dev: the device being configured
10459 * @dcb_cfg: pointer of the result of parse
10460 * @*tc_map: bit map of enabled traffic classes
10462 * Returns 0 on success, negative value on failure
10465 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10466 struct i40e_dcbx_config *dcb_cfg,
10469 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10470 uint8_t i, tc_bw, bw_lf;
10472 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10474 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10475 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10476 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10480 /* assume each tc has the same bw */
10481 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10482 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10483 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10484 /* to ensure the sum of tcbw is equal to 100 */
10485 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10486 for (i = 0; i < bw_lf; i++)
10487 dcb_cfg->etscfg.tcbwtable[i]++;
10489 /* assume each tc has the same Transmission Selection Algorithm */
10490 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10491 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10493 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10494 dcb_cfg->etscfg.prioritytable[i] =
10495 dcb_rx_conf->dcb_tc[i];
10497 /* FW needs one App to configure HW */
10498 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10499 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10500 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10501 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10503 if (dcb_rx_conf->nb_tcs == 0)
10504 *tc_map = 1; /* tc0 only */
10506 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10508 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10509 dcb_cfg->pfc.willing = 0;
10510 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10511 dcb_cfg->pfc.pfcenable = *tc_map;
10517 static enum i40e_status_code
10518 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10519 struct i40e_aqc_vsi_properties_data *info,
10520 uint8_t enabled_tcmap)
10522 enum i40e_status_code ret;
10523 int i, total_tc = 0;
10524 uint16_t qpnum_per_tc, bsf, qp_idx;
10525 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10526 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10527 uint16_t used_queues;
10529 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10530 if (ret != I40E_SUCCESS)
10533 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10534 if (enabled_tcmap & (1 << i))
10539 vsi->enabled_tc = enabled_tcmap;
10541 /* different VSI has different queues assigned */
10542 if (vsi->type == I40E_VSI_MAIN)
10543 used_queues = dev_data->nb_rx_queues -
10544 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10545 else if (vsi->type == I40E_VSI_VMDQ2)
10546 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10548 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10549 return I40E_ERR_NO_AVAILABLE_VSI;
10552 qpnum_per_tc = used_queues / total_tc;
10553 /* Number of queues per enabled TC */
10554 if (qpnum_per_tc == 0) {
10555 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10556 return I40E_ERR_INVALID_QP_ID;
10558 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10559 I40E_MAX_Q_PER_TC);
10560 bsf = rte_bsf32(qpnum_per_tc);
10563 * Configure TC and queue mapping parameters, for enabled TC,
10564 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10565 * default queue will serve it.
10568 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10569 if (vsi->enabled_tc & (1 << i)) {
10570 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10571 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10572 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10573 qp_idx += qpnum_per_tc;
10575 info->tc_mapping[i] = 0;
10578 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10579 if (vsi->type == I40E_VSI_SRIOV) {
10580 info->mapping_flags |=
10581 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10582 for (i = 0; i < vsi->nb_qps; i++)
10583 info->queue_mapping[i] =
10584 rte_cpu_to_le_16(vsi->base_queue + i);
10586 info->mapping_flags |=
10587 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10588 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10590 info->valid_sections |=
10591 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10593 return I40E_SUCCESS;
10597 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10598 * @veb: VEB to be configured
10599 * @tc_map: enabled TC bitmap
10601 * Returns 0 on success, negative value on failure
10603 static enum i40e_status_code
10604 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10606 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10607 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10608 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10609 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10610 enum i40e_status_code ret = I40E_SUCCESS;
10614 /* Check if enabled_tc is same as existing or new TCs */
10615 if (veb->enabled_tc == tc_map)
10618 /* configure tc bandwidth */
10619 memset(&veb_bw, 0, sizeof(veb_bw));
10620 veb_bw.tc_valid_bits = tc_map;
10621 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10622 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10623 if (tc_map & BIT_ULL(i))
10624 veb_bw.tc_bw_share_credits[i] = 1;
10626 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10630 "AQ command Config switch_comp BW allocation per TC failed = %d",
10631 hw->aq.asq_last_status);
10635 memset(&ets_query, 0, sizeof(ets_query));
10636 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10638 if (ret != I40E_SUCCESS) {
10640 "Failed to get switch_comp ETS configuration %u",
10641 hw->aq.asq_last_status);
10644 memset(&bw_query, 0, sizeof(bw_query));
10645 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10647 if (ret != I40E_SUCCESS) {
10649 "Failed to get switch_comp bandwidth configuration %u",
10650 hw->aq.asq_last_status);
10654 /* store and print out BW info */
10655 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10656 veb->bw_info.bw_max = ets_query.tc_bw_max;
10657 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10658 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10659 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10660 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10661 I40E_16_BIT_WIDTH);
10662 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10663 veb->bw_info.bw_ets_share_credits[i] =
10664 bw_query.tc_bw_share_credits[i];
10665 veb->bw_info.bw_ets_credits[i] =
10666 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10667 /* 4 bits per TC, 4th bit is reserved */
10668 veb->bw_info.bw_ets_max[i] =
10669 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10670 RTE_LEN2MASK(3, uint8_t));
10671 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10672 veb->bw_info.bw_ets_share_credits[i]);
10673 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10674 veb->bw_info.bw_ets_credits[i]);
10675 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10676 veb->bw_info.bw_ets_max[i]);
10679 veb->enabled_tc = tc_map;
10686 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10687 * @vsi: VSI to be configured
10688 * @tc_map: enabled TC bitmap
10690 * Returns 0 on success, negative value on failure
10692 static enum i40e_status_code
10693 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10695 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10696 struct i40e_vsi_context ctxt;
10697 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10698 enum i40e_status_code ret = I40E_SUCCESS;
10701 /* Check if enabled_tc is same as existing or new TCs */
10702 if (vsi->enabled_tc == tc_map)
10705 /* configure tc bandwidth */
10706 memset(&bw_data, 0, sizeof(bw_data));
10707 bw_data.tc_valid_bits = tc_map;
10708 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10709 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10710 if (tc_map & BIT_ULL(i))
10711 bw_data.tc_bw_credits[i] = 1;
10713 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10716 "AQ command Config VSI BW allocation per TC failed = %d",
10717 hw->aq.asq_last_status);
10720 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10721 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10723 /* Update Queue Pairs Mapping for currently enabled UPs */
10724 ctxt.seid = vsi->seid;
10725 ctxt.pf_num = hw->pf_id;
10727 ctxt.uplink_seid = vsi->uplink_seid;
10728 ctxt.info = vsi->info;
10730 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10734 /* Update the VSI after updating the VSI queue-mapping information */
10735 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10737 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10738 hw->aq.asq_last_status);
10741 /* update the local VSI info with updated queue map */
10742 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10743 sizeof(vsi->info.tc_mapping));
10744 rte_memcpy(&vsi->info.queue_mapping,
10745 &ctxt.info.queue_mapping,
10746 sizeof(vsi->info.queue_mapping));
10747 vsi->info.mapping_flags = ctxt.info.mapping_flags;
10748 vsi->info.valid_sections = 0;
10750 /* query and update current VSI BW information */
10751 ret = i40e_vsi_get_bw_config(vsi);
10754 "Failed updating vsi bw info, err %s aq_err %s",
10755 i40e_stat_str(hw, ret),
10756 i40e_aq_str(hw, hw->aq.asq_last_status));
10760 vsi->enabled_tc = tc_map;
10767 * i40e_dcb_hw_configure - program the dcb setting to hw
10768 * @pf: pf the configuration is taken on
10769 * @new_cfg: new configuration
10770 * @tc_map: enabled TC bitmap
10772 * Returns 0 on success, negative value on failure
10774 static enum i40e_status_code
10775 i40e_dcb_hw_configure(struct i40e_pf *pf,
10776 struct i40e_dcbx_config *new_cfg,
10779 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10780 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10781 struct i40e_vsi *main_vsi = pf->main_vsi;
10782 struct i40e_vsi_list *vsi_list;
10783 enum i40e_status_code ret;
10787 /* Use the FW API if FW > v4.4*/
10788 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10789 (hw->aq.fw_maj_ver >= 5))) {
10791 "FW < v4.4, can not use FW LLDP API to configure DCB");
10792 return I40E_ERR_FIRMWARE_API_VERSION;
10795 /* Check if need reconfiguration */
10796 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10797 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10798 return I40E_SUCCESS;
10801 /* Copy the new config to the current config */
10802 *old_cfg = *new_cfg;
10803 old_cfg->etsrec = old_cfg->etscfg;
10804 ret = i40e_set_dcb_config(hw);
10806 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10807 i40e_stat_str(hw, ret),
10808 i40e_aq_str(hw, hw->aq.asq_last_status));
10811 /* set receive Arbiter to RR mode and ETS scheme by default */
10812 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10813 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10814 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
10815 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10816 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10817 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10818 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10819 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10820 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10821 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10822 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10823 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10824 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10826 /* get local mib to check whether it is configured correctly */
10828 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10829 /* Get Local DCB Config */
10830 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10831 &hw->local_dcbx_config);
10833 /* if Veb is created, need to update TC of it at first */
10834 if (main_vsi->veb) {
10835 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10837 PMD_INIT_LOG(WARNING,
10838 "Failed configuring TC for VEB seid=%d",
10839 main_vsi->veb->seid);
10841 /* Update each VSI */
10842 i40e_vsi_config_tc(main_vsi, tc_map);
10843 if (main_vsi->veb) {
10844 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10845 /* Beside main VSI and VMDQ VSIs, only enable default
10846 * TC for other VSIs
10848 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10849 ret = i40e_vsi_config_tc(vsi_list->vsi,
10852 ret = i40e_vsi_config_tc(vsi_list->vsi,
10853 I40E_DEFAULT_TCMAP);
10855 PMD_INIT_LOG(WARNING,
10856 "Failed configuring TC for VSI seid=%d",
10857 vsi_list->vsi->seid);
10861 return I40E_SUCCESS;
10865 * i40e_dcb_init_configure - initial dcb config
10866 * @dev: device being configured
10867 * @sw_dcb: indicate whether dcb is sw configured or hw offload
10869 * Returns 0 on success, negative value on failure
10872 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10874 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10875 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10878 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10879 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10883 /* DCB initialization:
10884 * Update DCB configuration from the Firmware and configure
10885 * LLDP MIB change event.
10887 if (sw_dcb == TRUE) {
10888 /* Stopping lldp is necessary for DPDK, but it will cause
10889 * DCB init failed. For i40e_init_dcb(), the prerequisite
10890 * for successful initialization of DCB is that LLDP is
10891 * enabled. So it is needed to start lldp before DCB init
10892 * and stop it after initialization.
10894 ret = i40e_aq_start_lldp(hw, true, NULL);
10895 if (ret != I40E_SUCCESS)
10896 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10898 ret = i40e_init_dcb(hw, true);
10899 /* If lldp agent is stopped, the return value from
10900 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10901 * adminq status. Otherwise, it should return success.
10903 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10904 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10905 memset(&hw->local_dcbx_config, 0,
10906 sizeof(struct i40e_dcbx_config));
10907 /* set dcb default configuration */
10908 hw->local_dcbx_config.etscfg.willing = 0;
10909 hw->local_dcbx_config.etscfg.maxtcs = 0;
10910 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10911 hw->local_dcbx_config.etscfg.tsatable[0] =
10913 /* all UPs mapping to TC0 */
10914 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10915 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10916 hw->local_dcbx_config.etsrec =
10917 hw->local_dcbx_config.etscfg;
10918 hw->local_dcbx_config.pfc.willing = 0;
10919 hw->local_dcbx_config.pfc.pfccap =
10920 I40E_MAX_TRAFFIC_CLASS;
10921 /* FW needs one App to configure HW */
10922 hw->local_dcbx_config.numapps = 1;
10923 hw->local_dcbx_config.app[0].selector =
10924 I40E_APP_SEL_ETHTYPE;
10925 hw->local_dcbx_config.app[0].priority = 3;
10926 hw->local_dcbx_config.app[0].protocolid =
10927 I40E_APP_PROTOID_FCOE;
10928 ret = i40e_set_dcb_config(hw);
10931 "default dcb config fails. err = %d, aq_err = %d.",
10932 ret, hw->aq.asq_last_status);
10937 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10938 ret, hw->aq.asq_last_status);
10942 if (i40e_need_stop_lldp(dev)) {
10943 ret = i40e_aq_stop_lldp(hw, true, true, NULL);
10944 if (ret != I40E_SUCCESS)
10945 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
10948 ret = i40e_aq_start_lldp(hw, true, NULL);
10949 if (ret != I40E_SUCCESS)
10950 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10952 ret = i40e_init_dcb(hw, true);
10954 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10956 "HW doesn't support DCBX offload.");
10961 "DCBX configuration failed, err = %d, aq_err = %d.",
10962 ret, hw->aq.asq_last_status);
10970 * i40e_dcb_setup - setup dcb related config
10971 * @dev: device being configured
10973 * Returns 0 on success, negative value on failure
10976 i40e_dcb_setup(struct rte_eth_dev *dev)
10978 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10979 struct i40e_dcbx_config dcb_cfg;
10980 uint8_t tc_map = 0;
10983 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10984 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10988 if (pf->vf_num != 0)
10989 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10991 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10993 PMD_INIT_LOG(ERR, "invalid dcb config");
10996 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10998 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11006 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11007 struct rte_eth_dcb_info *dcb_info)
11009 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11010 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11011 struct i40e_vsi *vsi = pf->main_vsi;
11012 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11013 uint16_t bsf, tc_mapping;
11016 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11017 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11019 dcb_info->nb_tcs = 1;
11020 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11021 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11022 for (i = 0; i < dcb_info->nb_tcs; i++)
11023 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11025 /* get queue mapping if vmdq is disabled */
11026 if (!pf->nb_cfg_vmdq_vsi) {
11027 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11028 if (!(vsi->enabled_tc & (1 << i)))
11030 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11031 dcb_info->tc_queue.tc_rxq[j][i].base =
11032 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11033 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11034 dcb_info->tc_queue.tc_txq[j][i].base =
11035 dcb_info->tc_queue.tc_rxq[j][i].base;
11036 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11037 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11038 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11039 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11040 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11045 /* get queue mapping if vmdq is enabled */
11047 vsi = pf->vmdq[j].vsi;
11048 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11049 if (!(vsi->enabled_tc & (1 << i)))
11051 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11052 dcb_info->tc_queue.tc_rxq[j][i].base =
11053 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11054 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11055 dcb_info->tc_queue.tc_txq[j][i].base =
11056 dcb_info->tc_queue.tc_rxq[j][i].base;
11057 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11058 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11059 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11060 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11061 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11064 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11069 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11071 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11072 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11073 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11074 uint16_t msix_intr;
11076 msix_intr = intr_handle->intr_vec[queue_id];
11077 if (msix_intr == I40E_MISC_VEC_ID)
11078 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11079 I40E_PFINT_DYN_CTL0_INTENA_MASK |
11080 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11081 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11084 I40E_PFINT_DYN_CTLN(msix_intr -
11085 I40E_RX_VEC_START),
11086 I40E_PFINT_DYN_CTLN_INTENA_MASK |
11087 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11088 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11090 I40E_WRITE_FLUSH(hw);
11091 rte_intr_ack(&pci_dev->intr_handle);
11097 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11099 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11100 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11101 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11102 uint16_t msix_intr;
11104 msix_intr = intr_handle->intr_vec[queue_id];
11105 if (msix_intr == I40E_MISC_VEC_ID)
11106 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11107 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11110 I40E_PFINT_DYN_CTLN(msix_intr -
11111 I40E_RX_VEC_START),
11112 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11113 I40E_WRITE_FLUSH(hw);
11119 * This function is used to check if the register is valid.
11120 * Below is the valid registers list for X722 only:
11124 * 0x208e00--0x209000
11125 * 0x20be00--0x20c000
11126 * 0x263c00--0x264000
11127 * 0x265c00--0x266000
11129 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset)
11131 if ((type != I40E_MAC_X722) &&
11132 ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) ||
11133 (reg_offset >= 0x38700 && reg_offset <= 0x38a00) ||
11134 (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) ||
11135 (reg_offset >= 0x208e00 && reg_offset <= 0x209000) ||
11136 (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) ||
11137 (reg_offset >= 0x263c00 && reg_offset <= 0x264000) ||
11138 (reg_offset >= 0x265c00 && reg_offset <= 0x266000)))
11144 static int i40e_get_regs(struct rte_eth_dev *dev,
11145 struct rte_dev_reg_info *regs)
11147 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11148 uint32_t *ptr_data = regs->data;
11149 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11150 const struct i40e_reg_info *reg_info;
11152 if (ptr_data == NULL) {
11153 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11154 regs->width = sizeof(uint32_t);
11158 /* The first few registers have to be read using AQ operations */
11160 while (i40e_regs_adminq[reg_idx].name) {
11161 reg_info = &i40e_regs_adminq[reg_idx++];
11162 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11164 arr_idx2 <= reg_info->count2;
11166 reg_offset = arr_idx * reg_info->stride1 +
11167 arr_idx2 * reg_info->stride2;
11168 reg_offset += reg_info->base_addr;
11169 ptr_data[reg_offset >> 2] =
11170 i40e_read_rx_ctl(hw, reg_offset);
11174 /* The remaining registers can be read using primitives */
11176 while (i40e_regs_others[reg_idx].name) {
11177 reg_info = &i40e_regs_others[reg_idx++];
11178 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11180 arr_idx2 <= reg_info->count2;
11182 reg_offset = arr_idx * reg_info->stride1 +
11183 arr_idx2 * reg_info->stride2;
11184 reg_offset += reg_info->base_addr;
11185 if (!i40e_valid_regs(hw->mac.type, reg_offset))
11186 ptr_data[reg_offset >> 2] = 0;
11188 ptr_data[reg_offset >> 2] =
11189 I40E_READ_REG(hw, reg_offset);
11196 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11198 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11200 /* Convert word count to byte count */
11201 return hw->nvm.sr_size << 1;
11204 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11205 struct rte_dev_eeprom_info *eeprom)
11207 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11208 uint16_t *data = eeprom->data;
11209 uint16_t offset, length, cnt_words;
11212 offset = eeprom->offset >> 1;
11213 length = eeprom->length >> 1;
11214 cnt_words = length;
11216 if (offset > hw->nvm.sr_size ||
11217 offset + length > hw->nvm.sr_size) {
11218 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11222 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11224 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11225 if (ret_code != I40E_SUCCESS || cnt_words != length) {
11226 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11233 static int i40e_get_module_info(struct rte_eth_dev *dev,
11234 struct rte_eth_dev_module_info *modinfo)
11236 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11237 uint32_t sff8472_comp = 0;
11238 uint32_t sff8472_swap = 0;
11239 uint32_t sff8636_rev = 0;
11240 i40e_status status;
11243 /* Check if firmware supports reading module EEPROM. */
11244 if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
11246 "Module EEPROM memory read not supported. "
11247 "Please update the NVM image.\n");
11251 status = i40e_update_link_info(hw);
11255 if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
11257 "Cannot read module EEPROM memory. "
11258 "No module connected.\n");
11262 type = hw->phy.link_info.module_type[0];
11265 case I40E_MODULE_TYPE_SFP:
11266 status = i40e_aq_get_phy_register(hw,
11267 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11268 I40E_I2C_EEPROM_DEV_ADDR, 1,
11269 I40E_MODULE_SFF_8472_COMP,
11270 &sff8472_comp, NULL);
11274 status = i40e_aq_get_phy_register(hw,
11275 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11276 I40E_I2C_EEPROM_DEV_ADDR, 1,
11277 I40E_MODULE_SFF_8472_SWAP,
11278 &sff8472_swap, NULL);
11282 /* Check if the module requires address swap to access
11283 * the other EEPROM memory page.
11285 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
11286 PMD_DRV_LOG(WARNING,
11287 "Module address swap to access "
11288 "page 0xA2 is not supported.\n");
11289 modinfo->type = RTE_ETH_MODULE_SFF_8079;
11290 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11291 } else if (sff8472_comp == 0x00) {
11292 /* Module is not SFF-8472 compliant */
11293 modinfo->type = RTE_ETH_MODULE_SFF_8079;
11294 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11296 modinfo->type = RTE_ETH_MODULE_SFF_8472;
11297 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
11300 case I40E_MODULE_TYPE_QSFP_PLUS:
11301 /* Read from memory page 0. */
11302 status = i40e_aq_get_phy_register(hw,
11303 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11305 I40E_MODULE_REVISION_ADDR,
11306 &sff8636_rev, NULL);
11309 /* Determine revision compliance byte */
11310 if (sff8636_rev > 0x02) {
11311 /* Module is SFF-8636 compliant */
11312 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11313 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11315 modinfo->type = RTE_ETH_MODULE_SFF_8436;
11316 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11319 case I40E_MODULE_TYPE_QSFP28:
11320 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11321 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11324 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
11330 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
11331 struct rte_dev_eeprom_info *info)
11333 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11334 bool is_sfp = false;
11335 i40e_status status;
11337 uint32_t value = 0;
11340 if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
11344 for (i = 0; i < info->length; i++) {
11345 u32 offset = i + info->offset;
11346 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
11348 /* Check if we need to access the other memory page */
11350 if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
11351 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
11352 addr = I40E_I2C_EEPROM_DEV_ADDR2;
11355 while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
11356 /* Compute memory page number and offset. */
11357 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
11361 status = i40e_aq_get_phy_register(hw,
11362 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11363 addr, 1, offset, &value, NULL);
11366 data[i] = (uint8_t)value;
11371 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11372 struct rte_ether_addr *mac_addr)
11374 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11375 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11376 struct i40e_vsi *vsi = pf->main_vsi;
11377 struct i40e_mac_filter_info mac_filter;
11378 struct i40e_mac_filter *f;
11381 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
11382 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11386 TAILQ_FOREACH(f, &vsi->mac_list, next) {
11387 if (rte_is_same_ether_addr(&pf->dev_addr,
11388 &f->mac_info.mac_addr))
11393 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11397 mac_filter = f->mac_info;
11398 ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11399 if (ret != I40E_SUCCESS) {
11400 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11403 memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11404 ret = i40e_vsi_add_mac(vsi, &mac_filter);
11405 if (ret != I40E_SUCCESS) {
11406 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11409 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11411 ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11412 mac_addr->addr_bytes, NULL);
11413 if (ret != I40E_SUCCESS) {
11414 PMD_DRV_LOG(ERR, "Failed to change mac");
11422 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
11424 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11425 struct rte_eth_dev_data *dev_data = pf->dev_data;
11426 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
11429 /* check if mtu is within the allowed range */
11430 if (mtu < RTE_ETHER_MIN_MTU || frame_size > I40E_FRAME_SIZE_MAX)
11433 /* mtu setting is forbidden if port is start */
11434 if (dev_data->dev_started) {
11435 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
11436 dev_data->port_id);
11440 if (frame_size > I40E_ETH_MAX_LEN)
11441 dev_data->dev_conf.rxmode.offloads |=
11442 DEV_RX_OFFLOAD_JUMBO_FRAME;
11444 dev_data->dev_conf.rxmode.offloads &=
11445 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
11447 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
11452 /* Restore ethertype filter */
11454 i40e_ethertype_filter_restore(struct i40e_pf *pf)
11456 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11457 struct i40e_ethertype_filter_list
11458 *ethertype_list = &pf->ethertype.ethertype_list;
11459 struct i40e_ethertype_filter *f;
11460 struct i40e_control_filter_stats stats;
11463 TAILQ_FOREACH(f, ethertype_list, rules) {
11465 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
11466 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
11467 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
11468 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
11469 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
11471 memset(&stats, 0, sizeof(stats));
11472 i40e_aq_add_rem_control_packet_filter(hw,
11473 f->input.mac_addr.addr_bytes,
11474 f->input.ether_type,
11475 flags, pf->main_vsi->seid,
11476 f->queue, 1, &stats, NULL);
11478 PMD_DRV_LOG(INFO, "Ethertype filter:"
11479 " mac_etype_used = %u, etype_used = %u,"
11480 " mac_etype_free = %u, etype_free = %u",
11481 stats.mac_etype_used, stats.etype_used,
11482 stats.mac_etype_free, stats.etype_free);
11485 /* Restore tunnel filter */
11487 i40e_tunnel_filter_restore(struct i40e_pf *pf)
11489 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11490 struct i40e_vsi *vsi;
11491 struct i40e_pf_vf *vf;
11492 struct i40e_tunnel_filter_list
11493 *tunnel_list = &pf->tunnel.tunnel_list;
11494 struct i40e_tunnel_filter *f;
11495 struct i40e_aqc_cloud_filters_element_bb cld_filter;
11496 bool big_buffer = 0;
11498 TAILQ_FOREACH(f, tunnel_list, rules) {
11500 vsi = pf->main_vsi;
11502 vf = &pf->vfs[f->vf_id];
11505 memset(&cld_filter, 0, sizeof(cld_filter));
11506 rte_ether_addr_copy((struct rte_ether_addr *)
11507 &f->input.outer_mac,
11508 (struct rte_ether_addr *)&cld_filter.element.outer_mac);
11509 rte_ether_addr_copy((struct rte_ether_addr *)
11510 &f->input.inner_mac,
11511 (struct rte_ether_addr *)&cld_filter.element.inner_mac);
11512 cld_filter.element.inner_vlan = f->input.inner_vlan;
11513 cld_filter.element.flags = f->input.flags;
11514 cld_filter.element.tenant_id = f->input.tenant_id;
11515 cld_filter.element.queue_number = f->queue;
11516 rte_memcpy(cld_filter.general_fields,
11517 f->input.general_fields,
11518 sizeof(f->input.general_fields));
11520 if (((f->input.flags &
11521 I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
11522 I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
11524 I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
11525 I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
11527 I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
11528 I40E_AQC_ADD_CLOUD_FILTER_0X10))
11532 i40e_aq_add_cloud_filters_bb(hw,
11533 vsi->seid, &cld_filter, 1);
11535 i40e_aq_add_cloud_filters(hw, vsi->seid,
11536 &cld_filter.element, 1);
11541 i40e_filter_restore(struct i40e_pf *pf)
11543 i40e_ethertype_filter_restore(pf);
11544 i40e_tunnel_filter_restore(pf);
11545 i40e_fdir_filter_restore(pf);
11546 (void)i40e_hash_filter_restore(pf);
11550 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
11552 if (strcmp(dev->device->driver->name, drv->driver.name))
11559 is_i40e_supported(struct rte_eth_dev *dev)
11561 return is_device_supported(dev, &rte_i40e_pmd);
11564 struct i40e_customized_pctype*
11565 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
11569 for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
11570 if (pf->customized_pctype[i].index == index)
11571 return &pf->customized_pctype[i];
11577 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
11578 uint32_t pkg_size, uint32_t proto_num,
11579 struct rte_pmd_i40e_proto_info *proto,
11580 enum rte_pmd_i40e_package_op op)
11582 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11583 uint32_t pctype_num;
11584 struct rte_pmd_i40e_ptype_info *pctype;
11585 uint32_t buff_size;
11586 struct i40e_customized_pctype *new_pctype = NULL;
11588 uint8_t pctype_value;
11593 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11594 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11595 PMD_DRV_LOG(ERR, "Unsupported operation.");
11599 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11600 (uint8_t *)&pctype_num, sizeof(pctype_num),
11601 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
11603 PMD_DRV_LOG(ERR, "Failed to get pctype number");
11607 PMD_DRV_LOG(INFO, "No new pctype added");
11611 buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
11612 pctype = rte_zmalloc("new_pctype", buff_size, 0);
11614 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11617 /* get information about new pctype list */
11618 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11619 (uint8_t *)pctype, buff_size,
11620 RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
11622 PMD_DRV_LOG(ERR, "Failed to get pctype list");
11627 /* Update customized pctype. */
11628 for (i = 0; i < pctype_num; i++) {
11629 pctype_value = pctype[i].ptype_id;
11630 memset(name, 0, sizeof(name));
11631 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11632 proto_id = pctype[i].protocols[j];
11633 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11635 for (n = 0; n < proto_num; n++) {
11636 if (proto[n].proto_id != proto_id)
11638 strlcat(name, proto[n].name, sizeof(name));
11639 strlcat(name, "_", sizeof(name));
11643 name[strlen(name) - 1] = '\0';
11644 PMD_DRV_LOG(INFO, "name = %s\n", name);
11645 if (!strcmp(name, "GTPC"))
11647 i40e_find_customized_pctype(pf,
11648 I40E_CUSTOMIZED_GTPC);
11649 else if (!strcmp(name, "GTPU_IPV4"))
11651 i40e_find_customized_pctype(pf,
11652 I40E_CUSTOMIZED_GTPU_IPV4);
11653 else if (!strcmp(name, "GTPU_IPV6"))
11655 i40e_find_customized_pctype(pf,
11656 I40E_CUSTOMIZED_GTPU_IPV6);
11657 else if (!strcmp(name, "GTPU"))
11659 i40e_find_customized_pctype(pf,
11660 I40E_CUSTOMIZED_GTPU);
11661 else if (!strcmp(name, "IPV4_L2TPV3"))
11663 i40e_find_customized_pctype(pf,
11664 I40E_CUSTOMIZED_IPV4_L2TPV3);
11665 else if (!strcmp(name, "IPV6_L2TPV3"))
11667 i40e_find_customized_pctype(pf,
11668 I40E_CUSTOMIZED_IPV6_L2TPV3);
11669 else if (!strcmp(name, "IPV4_ESP"))
11671 i40e_find_customized_pctype(pf,
11672 I40E_CUSTOMIZED_ESP_IPV4);
11673 else if (!strcmp(name, "IPV6_ESP"))
11675 i40e_find_customized_pctype(pf,
11676 I40E_CUSTOMIZED_ESP_IPV6);
11677 else if (!strcmp(name, "IPV4_UDP_ESP"))
11679 i40e_find_customized_pctype(pf,
11680 I40E_CUSTOMIZED_ESP_IPV4_UDP);
11681 else if (!strcmp(name, "IPV6_UDP_ESP"))
11683 i40e_find_customized_pctype(pf,
11684 I40E_CUSTOMIZED_ESP_IPV6_UDP);
11685 else if (!strcmp(name, "IPV4_AH"))
11687 i40e_find_customized_pctype(pf,
11688 I40E_CUSTOMIZED_AH_IPV4);
11689 else if (!strcmp(name, "IPV6_AH"))
11691 i40e_find_customized_pctype(pf,
11692 I40E_CUSTOMIZED_AH_IPV6);
11694 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
11695 new_pctype->pctype = pctype_value;
11696 new_pctype->valid = true;
11698 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
11699 new_pctype->valid = false;
11709 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
11710 uint32_t pkg_size, uint32_t proto_num,
11711 struct rte_pmd_i40e_proto_info *proto,
11712 enum rte_pmd_i40e_package_op op)
11714 struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
11715 uint16_t port_id = dev->data->port_id;
11716 uint32_t ptype_num;
11717 struct rte_pmd_i40e_ptype_info *ptype;
11718 uint32_t buff_size;
11720 char name[RTE_PMD_I40E_DDP_NAME_SIZE];
11725 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11726 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11727 PMD_DRV_LOG(ERR, "Unsupported operation.");
11731 if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
11732 rte_pmd_i40e_ptype_mapping_reset(port_id);
11736 /* get information about new ptype num */
11737 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11738 (uint8_t *)&ptype_num, sizeof(ptype_num),
11739 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
11741 PMD_DRV_LOG(ERR, "Failed to get ptype number");
11745 PMD_DRV_LOG(INFO, "No new ptype added");
11749 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
11750 ptype = rte_zmalloc("new_ptype", buff_size, 0);
11752 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11756 /* get information about new ptype list */
11757 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11758 (uint8_t *)ptype, buff_size,
11759 RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
11761 PMD_DRV_LOG(ERR, "Failed to get ptype list");
11766 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
11767 ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
11768 if (!ptype_mapping) {
11769 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11774 /* Update ptype mapping table. */
11775 for (i = 0; i < ptype_num; i++) {
11776 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
11777 ptype_mapping[i].sw_ptype = 0;
11779 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11780 proto_id = ptype[i].protocols[j];
11781 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11783 for (n = 0; n < proto_num; n++) {
11784 if (proto[n].proto_id != proto_id)
11786 memset(name, 0, sizeof(name));
11787 strcpy(name, proto[n].name);
11788 PMD_DRV_LOG(INFO, "name = %s\n", name);
11789 if (!strncasecmp(name, "PPPOE", 5))
11790 ptype_mapping[i].sw_ptype |=
11791 RTE_PTYPE_L2_ETHER_PPPOE;
11792 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
11794 ptype_mapping[i].sw_ptype |=
11795 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11796 ptype_mapping[i].sw_ptype |=
11798 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
11800 ptype_mapping[i].sw_ptype |=
11801 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11802 ptype_mapping[i].sw_ptype |=
11803 RTE_PTYPE_INNER_L4_FRAG;
11804 } else if (!strncasecmp(name, "OIPV4", 5)) {
11805 ptype_mapping[i].sw_ptype |=
11806 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11808 } else if (!strncasecmp(name, "IPV4", 4) &&
11810 ptype_mapping[i].sw_ptype |=
11811 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11812 else if (!strncasecmp(name, "IPV4", 4) &&
11814 ptype_mapping[i].sw_ptype |=
11815 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11816 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
11818 ptype_mapping[i].sw_ptype |=
11819 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11820 ptype_mapping[i].sw_ptype |=
11822 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
11824 ptype_mapping[i].sw_ptype |=
11825 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11826 ptype_mapping[i].sw_ptype |=
11827 RTE_PTYPE_INNER_L4_FRAG;
11828 } else if (!strncasecmp(name, "OIPV6", 5)) {
11829 ptype_mapping[i].sw_ptype |=
11830 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11832 } else if (!strncasecmp(name, "IPV6", 4) &&
11834 ptype_mapping[i].sw_ptype |=
11835 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11836 else if (!strncasecmp(name, "IPV6", 4) &&
11838 ptype_mapping[i].sw_ptype |=
11839 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11840 else if (!strncasecmp(name, "UDP", 3) &&
11842 ptype_mapping[i].sw_ptype |=
11844 else if (!strncasecmp(name, "UDP", 3) &&
11846 ptype_mapping[i].sw_ptype |=
11847 RTE_PTYPE_INNER_L4_UDP;
11848 else if (!strncasecmp(name, "TCP", 3) &&
11850 ptype_mapping[i].sw_ptype |=
11852 else if (!strncasecmp(name, "TCP", 3) &&
11854 ptype_mapping[i].sw_ptype |=
11855 RTE_PTYPE_INNER_L4_TCP;
11856 else if (!strncasecmp(name, "SCTP", 4) &&
11858 ptype_mapping[i].sw_ptype |=
11860 else if (!strncasecmp(name, "SCTP", 4) &&
11862 ptype_mapping[i].sw_ptype |=
11863 RTE_PTYPE_INNER_L4_SCTP;
11864 else if ((!strncasecmp(name, "ICMP", 4) ||
11865 !strncasecmp(name, "ICMPV6", 6)) &&
11867 ptype_mapping[i].sw_ptype |=
11869 else if ((!strncasecmp(name, "ICMP", 4) ||
11870 !strncasecmp(name, "ICMPV6", 6)) &&
11872 ptype_mapping[i].sw_ptype |=
11873 RTE_PTYPE_INNER_L4_ICMP;
11874 else if (!strncasecmp(name, "GTPC", 4)) {
11875 ptype_mapping[i].sw_ptype |=
11876 RTE_PTYPE_TUNNEL_GTPC;
11878 } else if (!strncasecmp(name, "GTPU", 4)) {
11879 ptype_mapping[i].sw_ptype |=
11880 RTE_PTYPE_TUNNEL_GTPU;
11882 } else if (!strncasecmp(name, "ESP", 3)) {
11883 ptype_mapping[i].sw_ptype |=
11884 RTE_PTYPE_TUNNEL_ESP;
11886 } else if (!strncasecmp(name, "GRENAT", 6)) {
11887 ptype_mapping[i].sw_ptype |=
11888 RTE_PTYPE_TUNNEL_GRENAT;
11890 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
11891 !strncasecmp(name, "L2TPV2", 6) ||
11892 !strncasecmp(name, "L2TPV3", 6)) {
11893 ptype_mapping[i].sw_ptype |=
11894 RTE_PTYPE_TUNNEL_L2TP;
11903 ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
11906 PMD_DRV_LOG(ERR, "Failed to update ptype mapping table.");
11908 rte_free(ptype_mapping);
11914 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
11915 uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
11917 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11918 uint32_t proto_num;
11919 struct rte_pmd_i40e_proto_info *proto;
11920 uint32_t buff_size;
11924 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
11925 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
11926 PMD_DRV_LOG(ERR, "Unsupported operation.");
11930 /* get information about protocol number */
11931 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11932 (uint8_t *)&proto_num, sizeof(proto_num),
11933 RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
11935 PMD_DRV_LOG(ERR, "Failed to get protocol number");
11939 PMD_DRV_LOG(INFO, "No new protocol added");
11943 buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
11944 proto = rte_zmalloc("new_proto", buff_size, 0);
11946 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11950 /* get information about protocol list */
11951 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11952 (uint8_t *)proto, buff_size,
11953 RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
11955 PMD_DRV_LOG(ERR, "Failed to get protocol list");
11960 /* Check if GTP is supported. */
11961 for (i = 0; i < proto_num; i++) {
11962 if (!strncmp(proto[i].name, "GTP", 3)) {
11963 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
11964 pf->gtp_support = true;
11966 pf->gtp_support = false;
11971 /* Check if ESP is supported. */
11972 for (i = 0; i < proto_num; i++) {
11973 if (!strncmp(proto[i].name, "ESP", 3)) {
11974 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
11975 pf->esp_support = true;
11977 pf->esp_support = false;
11982 /* Update customized pctype info */
11983 ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
11984 proto_num, proto, op);
11986 PMD_DRV_LOG(INFO, "No pctype is updated.");
11988 /* Update customized ptype info */
11989 ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
11990 proto_num, proto, op);
11992 PMD_DRV_LOG(INFO, "No ptype is updated.");
11997 /* Create a QinQ cloud filter
11999 * The Fortville NIC has limited resources for tunnel filters,
12000 * so we can only reuse existing filters.
12002 * In step 1 we define which Field Vector fields can be used for
12004 * As we do not have the inner tag defined as a field,
12005 * we have to define it first, by reusing one of L1 entries.
12007 * In step 2 we are replacing one of existing filter types with
12008 * a new one for QinQ.
12009 * As we reusing L1 and replacing L2, some of the default filter
12010 * types will disappear,which depends on L1 and L2 entries we reuse.
12012 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12014 * 1. Create L1 filter of outer vlan (12b) which will be in use
12015 * later when we define the cloud filter.
12016 * a. Valid_flags.replace_cloud = 0
12017 * b. Old_filter = 10 (Stag_Inner_Vlan)
12018 * c. New_filter = 0x10
12019 * d. TR bit = 0xff (optional, not used here)
12020 * e. Buffer – 2 entries:
12021 * i. Byte 0 = 8 (outer vlan FV index).
12023 * Byte 2-3 = 0x0fff
12024 * ii. Byte 0 = 37 (inner vlan FV index).
12026 * Byte 2-3 = 0x0fff
12029 * 2. Create cloud filter using two L1 filters entries: stag and
12030 * new filter(outer vlan+ inner vlan)
12031 * a. Valid_flags.replace_cloud = 1
12032 * b. Old_filter = 1 (instead of outer IP)
12033 * c. New_filter = 0x10
12034 * d. Buffer – 2 entries:
12035 * i. Byte 0 = 0x80 | 7 (valid | Stag).
12036 * Byte 1-3 = 0 (rsv)
12037 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12038 * Byte 9-11 = 0 (rsv)
12041 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12043 int ret = -ENOTSUP;
12044 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
12045 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
12046 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12047 struct rte_eth_dev *dev = &rte_eth_devices[pf->dev_data->port_id];
12049 if (pf->support_multi_driver) {
12050 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12055 memset(&filter_replace, 0,
12056 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12057 memset(&filter_replace_buf, 0,
12058 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12060 /* create L1 filter */
12061 filter_replace.old_filter_type =
12062 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12063 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12064 filter_replace.tr_bit = 0;
12066 /* Prepare the buffer, 2 entries */
12067 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12068 filter_replace_buf.data[0] |=
12069 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12070 /* Field Vector 12b mask */
12071 filter_replace_buf.data[2] = 0xff;
12072 filter_replace_buf.data[3] = 0x0f;
12073 filter_replace_buf.data[4] =
12074 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12075 filter_replace_buf.data[4] |=
12076 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12077 /* Field Vector 12b mask */
12078 filter_replace_buf.data[6] = 0xff;
12079 filter_replace_buf.data[7] = 0x0f;
12080 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12081 &filter_replace_buf);
12082 if (ret != I40E_SUCCESS)
12085 if (filter_replace.old_filter_type !=
12086 filter_replace.new_filter_type)
12087 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
12088 " original: 0x%x, new: 0x%x",
12090 filter_replace.old_filter_type,
12091 filter_replace.new_filter_type);
12093 /* Apply the second L2 cloud filter */
12094 memset(&filter_replace, 0,
12095 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12096 memset(&filter_replace_buf, 0,
12097 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12099 /* create L2 filter, input for L2 filter will be L1 filter */
12100 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12101 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12102 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12104 /* Prepare the buffer, 2 entries */
12105 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12106 filter_replace_buf.data[0] |=
12107 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12108 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12109 filter_replace_buf.data[4] |=
12110 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12111 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12112 &filter_replace_buf);
12113 if (!ret && (filter_replace.old_filter_type !=
12114 filter_replace.new_filter_type))
12115 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
12116 " original: 0x%x, new: 0x%x",
12118 filter_replace.old_filter_type,
12119 filter_replace.new_filter_type);
12124 RTE_LOG_REGISTER_SUFFIX(i40e_logtype_init, init, NOTICE);
12125 RTE_LOG_REGISTER_SUFFIX(i40e_logtype_driver, driver, NOTICE);
12126 #ifdef RTE_ETHDEV_DEBUG_RX
12127 RTE_LOG_REGISTER_SUFFIX(i40e_logtype_rx, rx, DEBUG);
12129 #ifdef RTE_ETHDEV_DEBUG_TX
12130 RTE_LOG_REGISTER_SUFFIX(i40e_logtype_tx, tx, DEBUG);
12133 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12134 ETH_I40E_FLOATING_VEB_ARG "=1"
12135 ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
12136 ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12137 ETH_I40E_SUPPORT_MULTI_DRIVER "=1");