1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
15 #include <rte_string_fns.h>
17 #include <rte_bus_pci.h>
18 #include <rte_ether.h>
19 #include <rte_ethdev.h>
20 #include <rte_ethdev_pci.h>
21 #include <rte_memzone.h>
22 #include <rte_malloc.h>
23 #include <rte_memcpy.h>
24 #include <rte_alarm.h>
26 #include <rte_eth_ctrl.h>
27 #include <rte_tailq.h>
28 #include <rte_hash_crc.h>
30 #include "i40e_logs.h"
31 #include "base/i40e_prototype.h"
32 #include "base/i40e_adminq_cmd.h"
33 #include "base/i40e_type.h"
34 #include "base/i40e_register.h"
35 #include "base/i40e_dcb.h"
36 #include "base/i40e_diag.h"
37 #include "i40e_ethdev.h"
38 #include "i40e_rxtx.h"
40 #include "i40e_regs.h"
41 #include "rte_pmd_i40e.h"
43 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
44 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
46 #define I40E_CLEAR_PXE_WAIT_MS 200
48 /* Maximun number of capability elements */
49 #define I40E_MAX_CAP_ELE_NUM 128
51 /* Wait count and interval */
52 #define I40E_CHK_Q_ENA_COUNT 1000
53 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
55 /* Maximun number of VSI */
56 #define I40E_MAX_NUM_VSIS (384UL)
58 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
60 /* Flow control default timer */
61 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
63 /* Flow control enable fwd bit */
64 #define I40E_PRTMAC_FWD_CTRL 0x00000001
66 /* Receive Packet Buffer size */
67 #define I40E_RXPBSIZE (968 * 1024)
70 #define I40E_KILOSHIFT 10
72 /* Flow control default high water */
73 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
75 /* Flow control default low water */
76 #define I40E_DEFAULT_LOW_WATER (0xF2000 >> I40E_KILOSHIFT)
78 /* Receive Average Packet Size in Byte*/
79 #define I40E_PACKET_AVERAGE_SIZE 128
81 /* Mask of PF interrupt causes */
82 #define I40E_PFINT_ICR0_ENA_MASK ( \
83 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
84 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
85 I40E_PFINT_ICR0_ENA_GRST_MASK | \
86 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
87 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
88 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
89 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
90 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
91 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
93 #define I40E_FLOW_TYPES ( \
94 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
95 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
96 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
97 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
98 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
99 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
100 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
101 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
102 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
103 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
104 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
106 /* Additional timesync values. */
107 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
108 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
109 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
110 #define I40E_PRTTSYN_TSYNENA 0x80000000
111 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
112 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
115 * Below are values for writing un-exposed registers suggested
118 /* Destination MAC address */
119 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
120 /* Source MAC address */
121 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
122 /* Outer (S-Tag) VLAN tag in the outer L2 header */
123 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
124 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
125 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
126 /* Single VLAN tag in the inner L2 header */
127 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
128 /* Source IPv4 address */
129 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
130 /* Destination IPv4 address */
131 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
132 /* Source IPv4 address for X722 */
133 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
134 /* Destination IPv4 address for X722 */
135 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
136 /* IPv4 Protocol for X722 */
137 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
138 /* IPv4 Time to Live for X722 */
139 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
140 /* IPv4 Type of Service (TOS) */
141 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
143 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
144 /* IPv4 Time to Live */
145 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
146 /* Source IPv6 address */
147 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
148 /* Destination IPv6 address */
149 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
150 /* IPv6 Traffic Class (TC) */
151 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
152 /* IPv6 Next Header */
153 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
155 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
157 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
158 /* Destination L4 port */
159 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
160 /* SCTP verification tag */
161 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
162 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
163 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
164 /* Source port of tunneling UDP */
165 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
166 /* Destination port of tunneling UDP */
167 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
168 /* UDP Tunneling ID, NVGRE/GRE key */
169 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
170 /* Last ether type */
171 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
172 /* Tunneling outer destination IPv4 address */
173 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
174 /* Tunneling outer destination IPv6 address */
175 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
176 /* 1st word of flex payload */
177 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
178 /* 2nd word of flex payload */
179 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
180 /* 3rd word of flex payload */
181 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
182 /* 4th word of flex payload */
183 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
184 /* 5th word of flex payload */
185 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
186 /* 6th word of flex payload */
187 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
188 /* 7th word of flex payload */
189 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
190 /* 8th word of flex payload */
191 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
192 /* all 8 words flex payload */
193 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
194 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
196 #define I40E_TRANSLATE_INSET 0
197 #define I40E_TRANSLATE_REG 1
199 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
200 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
201 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
202 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
203 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
204 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
206 /* PCI offset for querying capability */
207 #define PCI_DEV_CAP_REG 0xA4
208 /* PCI offset for enabling/disabling Extended Tag */
209 #define PCI_DEV_CTRL_REG 0xA8
210 /* Bit mask of Extended Tag capability */
211 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
212 /* Bit shift of Extended Tag enable/disable */
213 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
214 /* Bit mask of Extended Tag enable/disable */
215 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
217 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
218 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
219 static int i40e_dev_configure(struct rte_eth_dev *dev);
220 static int i40e_dev_start(struct rte_eth_dev *dev);
221 static void i40e_dev_stop(struct rte_eth_dev *dev);
222 static void i40e_dev_close(struct rte_eth_dev *dev);
223 static int i40e_dev_reset(struct rte_eth_dev *dev);
224 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
225 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
226 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
227 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
228 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
229 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
230 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
231 struct rte_eth_stats *stats);
232 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
233 struct rte_eth_xstat *xstats, unsigned n);
234 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
235 struct rte_eth_xstat_name *xstats_names,
237 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
238 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
242 static int i40e_fw_version_get(struct rte_eth_dev *dev,
243 char *fw_version, size_t fw_size);
244 static void i40e_dev_info_get(struct rte_eth_dev *dev,
245 struct rte_eth_dev_info *dev_info);
246 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
249 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
250 enum rte_vlan_type vlan_type,
252 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
253 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
256 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
257 static int i40e_dev_led_on(struct rte_eth_dev *dev);
258 static int i40e_dev_led_off(struct rte_eth_dev *dev);
259 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
260 struct rte_eth_fc_conf *fc_conf);
261 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
262 struct rte_eth_fc_conf *fc_conf);
263 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
264 struct rte_eth_pfc_conf *pfc_conf);
265 static int i40e_macaddr_add(struct rte_eth_dev *dev,
266 struct ether_addr *mac_addr,
269 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
270 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
271 struct rte_eth_rss_reta_entry64 *reta_conf,
273 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
274 struct rte_eth_rss_reta_entry64 *reta_conf,
277 static int i40e_get_cap(struct i40e_hw *hw);
278 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
279 static int i40e_pf_setup(struct i40e_pf *pf);
280 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
281 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
282 static int i40e_dcb_setup(struct rte_eth_dev *dev);
283 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
284 bool offset_loaded, uint64_t *offset, uint64_t *stat);
285 static void i40e_stat_update_48(struct i40e_hw *hw,
291 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
292 static void i40e_dev_interrupt_handler(void *param);
293 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
294 uint32_t base, uint32_t num);
295 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
296 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
298 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
300 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
301 static int i40e_veb_release(struct i40e_veb *veb);
302 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
303 struct i40e_vsi *vsi);
304 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
305 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
306 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
307 struct i40e_macvlan_filter *mv_f,
310 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
311 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
312 struct rte_eth_rss_conf *rss_conf);
313 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
314 struct rte_eth_rss_conf *rss_conf);
315 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
316 struct rte_eth_udp_tunnel *udp_tunnel);
317 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
318 struct rte_eth_udp_tunnel *udp_tunnel);
319 static void i40e_filter_input_set_init(struct i40e_pf *pf);
320 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
321 enum rte_filter_op filter_op,
323 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
324 enum rte_filter_type filter_type,
325 enum rte_filter_op filter_op,
327 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
328 struct rte_eth_dcb_info *dcb_info);
329 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
330 static void i40e_configure_registers(struct i40e_hw *hw);
331 static void i40e_hw_init(struct rte_eth_dev *dev);
332 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
333 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
339 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
340 struct rte_eth_mirror_conf *mirror_conf,
341 uint8_t sw_id, uint8_t on);
342 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
344 static int i40e_timesync_enable(struct rte_eth_dev *dev);
345 static int i40e_timesync_disable(struct rte_eth_dev *dev);
346 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
347 struct timespec *timestamp,
349 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
350 struct timespec *timestamp);
351 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
353 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
355 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
356 struct timespec *timestamp);
357 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
358 const struct timespec *timestamp);
360 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
362 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
365 static int i40e_get_regs(struct rte_eth_dev *dev,
366 struct rte_dev_reg_info *regs);
368 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
370 static int i40e_get_eeprom(struct rte_eth_dev *dev,
371 struct rte_dev_eeprom_info *eeprom);
373 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
374 struct ether_addr *mac_addr);
376 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
378 static int i40e_ethertype_filter_convert(
379 const struct rte_eth_ethertype_filter *input,
380 struct i40e_ethertype_filter *filter);
381 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
382 struct i40e_ethertype_filter *filter);
384 static int i40e_tunnel_filter_convert(
385 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
386 struct i40e_tunnel_filter *tunnel_filter);
387 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
388 struct i40e_tunnel_filter *tunnel_filter);
389 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
391 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
392 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
393 static void i40e_filter_restore(struct i40e_pf *pf);
394 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
396 int i40e_logtype_init;
397 int i40e_logtype_driver;
399 static const struct rte_pci_id pci_id_i40e_map[] = {
400 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
401 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
402 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
403 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
404 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
405 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
406 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
407 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
408 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
409 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
410 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
411 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
412 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
413 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
414 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
415 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
416 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
417 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
418 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
419 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
420 { .vendor_id = 0, /* sentinel */ },
423 static const struct eth_dev_ops i40e_eth_dev_ops = {
424 .dev_configure = i40e_dev_configure,
425 .dev_start = i40e_dev_start,
426 .dev_stop = i40e_dev_stop,
427 .dev_close = i40e_dev_close,
428 .dev_reset = i40e_dev_reset,
429 .promiscuous_enable = i40e_dev_promiscuous_enable,
430 .promiscuous_disable = i40e_dev_promiscuous_disable,
431 .allmulticast_enable = i40e_dev_allmulticast_enable,
432 .allmulticast_disable = i40e_dev_allmulticast_disable,
433 .dev_set_link_up = i40e_dev_set_link_up,
434 .dev_set_link_down = i40e_dev_set_link_down,
435 .link_update = i40e_dev_link_update,
436 .stats_get = i40e_dev_stats_get,
437 .xstats_get = i40e_dev_xstats_get,
438 .xstats_get_names = i40e_dev_xstats_get_names,
439 .stats_reset = i40e_dev_stats_reset,
440 .xstats_reset = i40e_dev_stats_reset,
441 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
442 .fw_version_get = i40e_fw_version_get,
443 .dev_infos_get = i40e_dev_info_get,
444 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
445 .vlan_filter_set = i40e_vlan_filter_set,
446 .vlan_tpid_set = i40e_vlan_tpid_set,
447 .vlan_offload_set = i40e_vlan_offload_set,
448 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
449 .vlan_pvid_set = i40e_vlan_pvid_set,
450 .rx_queue_start = i40e_dev_rx_queue_start,
451 .rx_queue_stop = i40e_dev_rx_queue_stop,
452 .tx_queue_start = i40e_dev_tx_queue_start,
453 .tx_queue_stop = i40e_dev_tx_queue_stop,
454 .rx_queue_setup = i40e_dev_rx_queue_setup,
455 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
456 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
457 .rx_queue_release = i40e_dev_rx_queue_release,
458 .rx_queue_count = i40e_dev_rx_queue_count,
459 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
460 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
461 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
462 .tx_queue_setup = i40e_dev_tx_queue_setup,
463 .tx_queue_release = i40e_dev_tx_queue_release,
464 .dev_led_on = i40e_dev_led_on,
465 .dev_led_off = i40e_dev_led_off,
466 .flow_ctrl_get = i40e_flow_ctrl_get,
467 .flow_ctrl_set = i40e_flow_ctrl_set,
468 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
469 .mac_addr_add = i40e_macaddr_add,
470 .mac_addr_remove = i40e_macaddr_remove,
471 .reta_update = i40e_dev_rss_reta_update,
472 .reta_query = i40e_dev_rss_reta_query,
473 .rss_hash_update = i40e_dev_rss_hash_update,
474 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
475 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
476 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
477 .filter_ctrl = i40e_dev_filter_ctrl,
478 .rxq_info_get = i40e_rxq_info_get,
479 .txq_info_get = i40e_txq_info_get,
480 .mirror_rule_set = i40e_mirror_rule_set,
481 .mirror_rule_reset = i40e_mirror_rule_reset,
482 .timesync_enable = i40e_timesync_enable,
483 .timesync_disable = i40e_timesync_disable,
484 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
485 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
486 .get_dcb_info = i40e_dev_get_dcb_info,
487 .timesync_adjust_time = i40e_timesync_adjust_time,
488 .timesync_read_time = i40e_timesync_read_time,
489 .timesync_write_time = i40e_timesync_write_time,
490 .get_reg = i40e_get_regs,
491 .get_eeprom_length = i40e_get_eeprom_length,
492 .get_eeprom = i40e_get_eeprom,
493 .mac_addr_set = i40e_set_default_mac_addr,
494 .mtu_set = i40e_dev_mtu_set,
495 .tm_ops_get = i40e_tm_ops_get,
498 /* store statistics names and its offset in stats structure */
499 struct rte_i40e_xstats_name_off {
500 char name[RTE_ETH_XSTATS_NAME_SIZE];
504 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
505 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
506 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
507 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
508 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
509 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
510 rx_unknown_protocol)},
511 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
512 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
513 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
514 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
517 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
518 sizeof(rte_i40e_stats_strings[0]))
520 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
521 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
522 tx_dropped_link_down)},
523 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
524 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
526 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
527 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
529 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
531 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
533 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
534 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
535 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
536 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
537 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
538 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
540 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
542 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
544 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
546 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
548 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
550 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
552 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
554 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
555 mac_short_packet_dropped)},
556 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
558 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
559 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
560 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
562 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
564 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
566 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
568 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
570 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
572 {"rx_flow_director_atr_match_packets",
573 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
574 {"rx_flow_director_sb_match_packets",
575 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
576 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
578 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
580 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
582 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
586 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
587 sizeof(rte_i40e_hw_port_strings[0]))
589 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
590 {"xon_packets", offsetof(struct i40e_hw_port_stats,
592 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
596 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
597 sizeof(rte_i40e_rxq_prio_strings[0]))
599 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
600 {"xon_packets", offsetof(struct i40e_hw_port_stats,
602 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
604 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
605 priority_xon_2_xoff)},
608 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
609 sizeof(rte_i40e_txq_prio_strings[0]))
611 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
612 struct rte_pci_device *pci_dev)
614 return rte_eth_dev_pci_generic_probe(pci_dev,
615 sizeof(struct i40e_adapter), eth_i40e_dev_init);
618 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
620 return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
623 static struct rte_pci_driver rte_i40e_pmd = {
624 .id_table = pci_id_i40e_map,
625 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
626 RTE_PCI_DRV_IOVA_AS_VA,
627 .probe = eth_i40e_pci_probe,
628 .remove = eth_i40e_pci_remove,
632 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
633 struct rte_eth_link *link)
635 struct rte_eth_link *dst = link;
636 struct rte_eth_link *src = &(dev->data->dev_link);
638 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
639 *(uint64_t *)src) == 0)
646 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
647 struct rte_eth_link *link)
649 struct rte_eth_link *dst = &(dev->data->dev_link);
650 struct rte_eth_link *src = link;
652 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
653 *(uint64_t *)src) == 0)
659 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
660 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
661 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
663 #ifndef I40E_GLQF_ORT
664 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
666 #ifndef I40E_GLQF_PIT
667 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
669 #ifndef I40E_GLQF_L3_MAP
670 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
673 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
676 * Initialize registers for parsing packet type of QinQ
677 * This should be removed from code once proper
678 * configuration API is added to avoid configuration conflicts
679 * between ports of the same device.
681 I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
682 I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
685 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
688 * Add a ethertype filter to drop all flow control frames transmitted
692 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
694 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
695 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
696 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
697 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
700 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
701 I40E_FLOW_CONTROL_ETHERTYPE, flags,
702 pf->main_vsi_seid, 0,
706 "Failed to add filter to drop flow control frames from VSIs.");
710 floating_veb_list_handler(__rte_unused const char *key,
711 const char *floating_veb_value,
715 unsigned int count = 0;
718 bool *vf_floating_veb = opaque;
720 while (isblank(*floating_veb_value))
721 floating_veb_value++;
723 /* Reset floating VEB configuration for VFs */
724 for (idx = 0; idx < I40E_MAX_VF; idx++)
725 vf_floating_veb[idx] = false;
729 while (isblank(*floating_veb_value))
730 floating_veb_value++;
731 if (*floating_veb_value == '\0')
734 idx = strtoul(floating_veb_value, &end, 10);
735 if (errno || end == NULL)
737 while (isblank(*end))
741 } else if ((*end == ';') || (*end == '\0')) {
743 if (min == I40E_MAX_VF)
745 if (max >= I40E_MAX_VF)
746 max = I40E_MAX_VF - 1;
747 for (idx = min; idx <= max; idx++) {
748 vf_floating_veb[idx] = true;
755 floating_veb_value = end + 1;
756 } while (*end != '\0');
765 config_vf_floating_veb(struct rte_devargs *devargs,
766 uint16_t floating_veb,
767 bool *vf_floating_veb)
769 struct rte_kvargs *kvlist;
771 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
775 /* All the VFs attach to the floating VEB by default
776 * when the floating VEB is enabled.
778 for (i = 0; i < I40E_MAX_VF; i++)
779 vf_floating_veb[i] = true;
784 kvlist = rte_kvargs_parse(devargs->args, NULL);
788 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
789 rte_kvargs_free(kvlist);
792 /* When the floating_veb_list parameter exists, all the VFs
793 * will attach to the legacy VEB firstly, then configure VFs
794 * to the floating VEB according to the floating_veb_list.
796 if (rte_kvargs_process(kvlist, floating_veb_list,
797 floating_veb_list_handler,
798 vf_floating_veb) < 0) {
799 rte_kvargs_free(kvlist);
802 rte_kvargs_free(kvlist);
806 i40e_check_floating_handler(__rte_unused const char *key,
808 __rte_unused void *opaque)
810 if (strcmp(value, "1"))
817 is_floating_veb_supported(struct rte_devargs *devargs)
819 struct rte_kvargs *kvlist;
820 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
825 kvlist = rte_kvargs_parse(devargs->args, NULL);
829 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
830 rte_kvargs_free(kvlist);
833 /* Floating VEB is enabled when there's key-value:
834 * enable_floating_veb=1
836 if (rte_kvargs_process(kvlist, floating_veb_key,
837 i40e_check_floating_handler, NULL) < 0) {
838 rte_kvargs_free(kvlist);
841 rte_kvargs_free(kvlist);
847 config_floating_veb(struct rte_eth_dev *dev)
849 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
850 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
851 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
853 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
855 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
857 is_floating_veb_supported(pci_dev->device.devargs);
858 config_vf_floating_veb(pci_dev->device.devargs,
860 pf->floating_veb_list);
862 pf->floating_veb = false;
866 #define I40E_L2_TAGS_S_TAG_SHIFT 1
867 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
870 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
872 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
873 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
874 char ethertype_hash_name[RTE_HASH_NAMESIZE];
877 struct rte_hash_parameters ethertype_hash_params = {
878 .name = ethertype_hash_name,
879 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
880 .key_len = sizeof(struct i40e_ethertype_filter_input),
881 .hash_func = rte_hash_crc,
882 .hash_func_init_val = 0,
883 .socket_id = rte_socket_id(),
886 /* Initialize ethertype filter rule list and hash */
887 TAILQ_INIT(ðertype_rule->ethertype_list);
888 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
889 "ethertype_%s", dev->device->name);
890 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
891 if (!ethertype_rule->hash_table) {
892 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
895 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
896 sizeof(struct i40e_ethertype_filter *) *
897 I40E_MAX_ETHERTYPE_FILTER_NUM,
899 if (!ethertype_rule->hash_map) {
901 "Failed to allocate memory for ethertype hash map!");
903 goto err_ethertype_hash_map_alloc;
908 err_ethertype_hash_map_alloc:
909 rte_hash_free(ethertype_rule->hash_table);
915 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
917 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
918 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
919 char tunnel_hash_name[RTE_HASH_NAMESIZE];
922 struct rte_hash_parameters tunnel_hash_params = {
923 .name = tunnel_hash_name,
924 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
925 .key_len = sizeof(struct i40e_tunnel_filter_input),
926 .hash_func = rte_hash_crc,
927 .hash_func_init_val = 0,
928 .socket_id = rte_socket_id(),
931 /* Initialize tunnel filter rule list and hash */
932 TAILQ_INIT(&tunnel_rule->tunnel_list);
933 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
934 "tunnel_%s", dev->device->name);
935 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
936 if (!tunnel_rule->hash_table) {
937 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
940 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
941 sizeof(struct i40e_tunnel_filter *) *
942 I40E_MAX_TUNNEL_FILTER_NUM,
944 if (!tunnel_rule->hash_map) {
946 "Failed to allocate memory for tunnel hash map!");
948 goto err_tunnel_hash_map_alloc;
953 err_tunnel_hash_map_alloc:
954 rte_hash_free(tunnel_rule->hash_table);
960 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
962 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
963 struct i40e_fdir_info *fdir_info = &pf->fdir;
964 char fdir_hash_name[RTE_HASH_NAMESIZE];
967 struct rte_hash_parameters fdir_hash_params = {
968 .name = fdir_hash_name,
969 .entries = I40E_MAX_FDIR_FILTER_NUM,
970 .key_len = sizeof(struct i40e_fdir_input),
971 .hash_func = rte_hash_crc,
972 .hash_func_init_val = 0,
973 .socket_id = rte_socket_id(),
976 /* Initialize flow director filter rule list and hash */
977 TAILQ_INIT(&fdir_info->fdir_list);
978 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
979 "fdir_%s", dev->device->name);
980 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
981 if (!fdir_info->hash_table) {
982 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
985 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
986 sizeof(struct i40e_fdir_filter *) *
987 I40E_MAX_FDIR_FILTER_NUM,
989 if (!fdir_info->hash_map) {
991 "Failed to allocate memory for fdir hash map!");
993 goto err_fdir_hash_map_alloc;
997 err_fdir_hash_map_alloc:
998 rte_hash_free(fdir_info->hash_table);
1004 i40e_init_customized_info(struct i40e_pf *pf)
1008 /* Initialize customized pctype */
1009 for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1010 pf->customized_pctype[i].index = i;
1011 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1012 pf->customized_pctype[i].valid = false;
1015 pf->gtp_support = false;
1019 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1021 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1022 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1023 struct i40e_queue_regions *info = &pf->queue_region;
1026 for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1027 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1029 memset(info, 0, sizeof(struct i40e_queue_regions));
1033 eth_i40e_dev_init(struct rte_eth_dev *dev)
1035 struct rte_pci_device *pci_dev;
1036 struct rte_intr_handle *intr_handle;
1037 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1038 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1039 struct i40e_vsi *vsi;
1042 uint8_t aq_fail = 0;
1044 PMD_INIT_FUNC_TRACE();
1046 dev->dev_ops = &i40e_eth_dev_ops;
1047 dev->rx_pkt_burst = i40e_recv_pkts;
1048 dev->tx_pkt_burst = i40e_xmit_pkts;
1049 dev->tx_pkt_prepare = i40e_prep_pkts;
1051 /* for secondary processes, we don't initialise any further as primary
1052 * has already done this work. Only check we don't need a different
1054 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1055 i40e_set_rx_function(dev);
1056 i40e_set_tx_function(dev);
1059 i40e_set_default_ptype_table(dev);
1060 i40e_set_default_pctype_table(dev);
1061 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1062 intr_handle = &pci_dev->intr_handle;
1064 rte_eth_copy_pci_info(dev, pci_dev);
1066 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1067 pf->adapter->eth_dev = dev;
1068 pf->dev_data = dev->data;
1070 hw->back = I40E_PF_TO_ADAPTER(pf);
1071 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1074 "Hardware is not available, as address is NULL");
1078 hw->vendor_id = pci_dev->id.vendor_id;
1079 hw->device_id = pci_dev->id.device_id;
1080 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1081 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1082 hw->bus.device = pci_dev->addr.devid;
1083 hw->bus.func = pci_dev->addr.function;
1084 hw->adapter_stopped = 0;
1086 /* Make sure all is clean before doing PF reset */
1089 /* Initialize the hardware */
1092 /* Reset here to make sure all is clean for each PF */
1093 ret = i40e_pf_reset(hw);
1095 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1099 /* Initialize the shared code (base driver) */
1100 ret = i40e_init_shared_code(hw);
1102 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1107 * To work around the NVM issue, initialize registers
1108 * for packet type of QinQ by software.
1109 * It should be removed once issues are fixed in NVM.
1111 i40e_GLQF_reg_init(hw);
1113 /* Initialize the input set for filters (hash and fd) to default value */
1114 i40e_filter_input_set_init(pf);
1116 /* Initialize the parameters for adminq */
1117 i40e_init_adminq_parameter(hw);
1118 ret = i40e_init_adminq(hw);
1119 if (ret != I40E_SUCCESS) {
1120 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1123 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1124 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1125 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1126 ((hw->nvm.version >> 12) & 0xf),
1127 ((hw->nvm.version >> 4) & 0xff),
1128 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1130 /* initialise the L3_MAP register */
1131 ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1134 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
1136 /* Need the special FW version to support floating VEB */
1137 config_floating_veb(dev);
1138 /* Clear PXE mode */
1139 i40e_clear_pxe_mode(hw);
1140 i40e_dev_sync_phy_type(hw);
1143 * On X710, performance number is far from the expectation on recent
1144 * firmware versions. The fix for this issue may not be integrated in
1145 * the following firmware version. So the workaround in software driver
1146 * is needed. It needs to modify the initial values of 3 internal only
1147 * registers. Note that the workaround can be removed when it is fixed
1148 * in firmware in the future.
1150 i40e_configure_registers(hw);
1152 /* Get hw capabilities */
1153 ret = i40e_get_cap(hw);
1154 if (ret != I40E_SUCCESS) {
1155 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1156 goto err_get_capabilities;
1159 /* Initialize parameters for PF */
1160 ret = i40e_pf_parameter_init(dev);
1162 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1163 goto err_parameter_init;
1166 /* Initialize the queue management */
1167 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1169 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1170 goto err_qp_pool_init;
1172 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1173 hw->func_caps.num_msix_vectors - 1);
1175 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1176 goto err_msix_pool_init;
1179 /* Initialize lan hmc */
1180 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1181 hw->func_caps.num_rx_qp, 0, 0);
1182 if (ret != I40E_SUCCESS) {
1183 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1184 goto err_init_lan_hmc;
1187 /* Configure lan hmc */
1188 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1189 if (ret != I40E_SUCCESS) {
1190 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1191 goto err_configure_lan_hmc;
1194 /* Get and check the mac address */
1195 i40e_get_mac_addr(hw, hw->mac.addr);
1196 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1197 PMD_INIT_LOG(ERR, "mac address is not valid");
1199 goto err_get_mac_addr;
1201 /* Copy the permanent MAC address */
1202 ether_addr_copy((struct ether_addr *) hw->mac.addr,
1203 (struct ether_addr *) hw->mac.perm_addr);
1205 /* Disable flow control */
1206 hw->fc.requested_mode = I40E_FC_NONE;
1207 i40e_set_fc(hw, &aq_fail, TRUE);
1209 /* Set the global registers with default ether type value */
1210 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1211 if (ret != I40E_SUCCESS) {
1213 "Failed to set the default outer VLAN ether type");
1214 goto err_setup_pf_switch;
1217 /* PF setup, which includes VSI setup */
1218 ret = i40e_pf_setup(pf);
1220 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1221 goto err_setup_pf_switch;
1224 /* reset all stats of the device, including pf and main vsi */
1225 i40e_dev_stats_reset(dev);
1229 /* Disable double vlan by default */
1230 i40e_vsi_config_double_vlan(vsi, FALSE);
1232 /* Disable S-TAG identification when floating_veb is disabled */
1233 if (!pf->floating_veb) {
1234 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1235 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1236 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1237 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1241 if (!vsi->max_macaddrs)
1242 len = ETHER_ADDR_LEN;
1244 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1246 /* Should be after VSI initialized */
1247 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1248 if (!dev->data->mac_addrs) {
1250 "Failed to allocated memory for storing mac address");
1253 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1254 &dev->data->mac_addrs[0]);
1256 /* Init dcb to sw mode by default */
1257 ret = i40e_dcb_init_configure(dev, TRUE);
1258 if (ret != I40E_SUCCESS) {
1259 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1260 pf->flags &= ~I40E_FLAG_DCB;
1262 /* Update HW struct after DCB configuration */
1265 /* initialize pf host driver to setup SRIOV resource if applicable */
1266 i40e_pf_host_init(dev);
1268 /* register callback func to eal lib */
1269 rte_intr_callback_register(intr_handle,
1270 i40e_dev_interrupt_handler, dev);
1272 /* configure and enable device interrupt */
1273 i40e_pf_config_irq0(hw, TRUE);
1274 i40e_pf_enable_irq0(hw);
1276 /* enable uio intr after callback register */
1277 rte_intr_enable(intr_handle);
1279 /* By default disable flexible payload in global configuration */
1280 i40e_flex_payload_reg_set_default(hw);
1283 * Add an ethertype filter to drop all flow control frames transmitted
1284 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1287 i40e_add_tx_flow_control_drop_filter(pf);
1289 /* Set the max frame size to 0x2600 by default,
1290 * in case other drivers changed the default value.
1292 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1294 /* initialize mirror rule list */
1295 TAILQ_INIT(&pf->mirror_list);
1297 /* initialize Traffic Manager configuration */
1298 i40e_tm_conf_init(dev);
1300 /* Initialize customized information */
1301 i40e_init_customized_info(pf);
1303 ret = i40e_init_ethtype_filter_list(dev);
1305 goto err_init_ethtype_filter_list;
1306 ret = i40e_init_tunnel_filter_list(dev);
1308 goto err_init_tunnel_filter_list;
1309 ret = i40e_init_fdir_filter_list(dev);
1311 goto err_init_fdir_filter_list;
1313 /* initialize queue region configuration */
1314 i40e_init_queue_region_conf(dev);
1316 /* initialize rss configuration from rte_flow */
1317 memset(&pf->rss_info, 0,
1318 sizeof(struct i40e_rte_flow_rss_conf));
1322 err_init_fdir_filter_list:
1323 rte_free(pf->tunnel.hash_table);
1324 rte_free(pf->tunnel.hash_map);
1325 err_init_tunnel_filter_list:
1326 rte_free(pf->ethertype.hash_table);
1327 rte_free(pf->ethertype.hash_map);
1328 err_init_ethtype_filter_list:
1329 rte_free(dev->data->mac_addrs);
1331 i40e_vsi_release(pf->main_vsi);
1332 err_setup_pf_switch:
1334 err_configure_lan_hmc:
1335 (void)i40e_shutdown_lan_hmc(hw);
1337 i40e_res_pool_destroy(&pf->msix_pool);
1339 i40e_res_pool_destroy(&pf->qp_pool);
1342 err_get_capabilities:
1343 (void)i40e_shutdown_adminq(hw);
1349 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1351 struct i40e_ethertype_filter *p_ethertype;
1352 struct i40e_ethertype_rule *ethertype_rule;
1354 ethertype_rule = &pf->ethertype;
1355 /* Remove all ethertype filter rules and hash */
1356 if (ethertype_rule->hash_map)
1357 rte_free(ethertype_rule->hash_map);
1358 if (ethertype_rule->hash_table)
1359 rte_hash_free(ethertype_rule->hash_table);
1361 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1362 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1363 p_ethertype, rules);
1364 rte_free(p_ethertype);
1369 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1371 struct i40e_tunnel_filter *p_tunnel;
1372 struct i40e_tunnel_rule *tunnel_rule;
1374 tunnel_rule = &pf->tunnel;
1375 /* Remove all tunnel director rules and hash */
1376 if (tunnel_rule->hash_map)
1377 rte_free(tunnel_rule->hash_map);
1378 if (tunnel_rule->hash_table)
1379 rte_hash_free(tunnel_rule->hash_table);
1381 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1382 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1388 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1390 struct i40e_fdir_filter *p_fdir;
1391 struct i40e_fdir_info *fdir_info;
1393 fdir_info = &pf->fdir;
1394 /* Remove all flow director rules and hash */
1395 if (fdir_info->hash_map)
1396 rte_free(fdir_info->hash_map);
1397 if (fdir_info->hash_table)
1398 rte_hash_free(fdir_info->hash_table);
1400 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1401 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1406 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1409 * Disable by default flexible payload
1410 * for corresponding L2/L3/L4 layers.
1412 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1413 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1414 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1418 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1421 struct rte_pci_device *pci_dev;
1422 struct rte_intr_handle *intr_handle;
1424 struct i40e_filter_control_settings settings;
1425 struct rte_flow *p_flow;
1427 uint8_t aq_fail = 0;
1429 PMD_INIT_FUNC_TRACE();
1431 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1434 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1435 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1436 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1437 intr_handle = &pci_dev->intr_handle;
1439 if (hw->adapter_stopped == 0)
1440 i40e_dev_close(dev);
1442 dev->dev_ops = NULL;
1443 dev->rx_pkt_burst = NULL;
1444 dev->tx_pkt_burst = NULL;
1446 /* Clear PXE mode */
1447 i40e_clear_pxe_mode(hw);
1449 /* Unconfigure filter control */
1450 memset(&settings, 0, sizeof(settings));
1451 ret = i40e_set_filter_control(hw, &settings);
1453 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1456 /* Disable flow control */
1457 hw->fc.requested_mode = I40E_FC_NONE;
1458 i40e_set_fc(hw, &aq_fail, TRUE);
1460 /* uninitialize pf host driver */
1461 i40e_pf_host_uninit(dev);
1463 rte_free(dev->data->mac_addrs);
1464 dev->data->mac_addrs = NULL;
1466 /* disable uio intr before callback unregister */
1467 rte_intr_disable(intr_handle);
1469 /* register callback func to eal lib */
1470 rte_intr_callback_unregister(intr_handle,
1471 i40e_dev_interrupt_handler, dev);
1473 i40e_rm_ethtype_filter_list(pf);
1474 i40e_rm_tunnel_filter_list(pf);
1475 i40e_rm_fdir_filter_list(pf);
1477 /* Remove all flows */
1478 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1479 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1483 /* Remove all Traffic Manager configuration */
1484 i40e_tm_conf_uninit(dev);
1490 i40e_dev_configure(struct rte_eth_dev *dev)
1492 struct i40e_adapter *ad =
1493 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1494 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1495 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1496 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1499 ret = i40e_dev_sync_phy_type(hw);
1503 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1504 * bulk allocation or vector Rx preconditions we will reset it.
1506 ad->rx_bulk_alloc_allowed = true;
1507 ad->rx_vec_allowed = true;
1508 ad->tx_simple_allowed = true;
1509 ad->tx_vec_allowed = true;
1511 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1512 ret = i40e_fdir_setup(pf);
1513 if (ret != I40E_SUCCESS) {
1514 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1517 ret = i40e_fdir_configure(dev);
1519 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1523 i40e_fdir_teardown(pf);
1525 ret = i40e_dev_init_vlan(dev);
1530 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1531 * RSS setting have different requirements.
1532 * General PMD driver call sequence are NIC init, configure,
1533 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1534 * will try to lookup the VSI that specific queue belongs to if VMDQ
1535 * applicable. So, VMDQ setting has to be done before
1536 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1537 * For RSS setting, it will try to calculate actual configured RX queue
1538 * number, which will be available after rx_queue_setup(). dev_start()
1539 * function is good to place RSS setup.
1541 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1542 ret = i40e_vmdq_setup(dev);
1547 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1548 ret = i40e_dcb_setup(dev);
1550 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1555 TAILQ_INIT(&pf->flow_list);
1560 /* need to release vmdq resource if exists */
1561 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1562 i40e_vsi_release(pf->vmdq[i].vsi);
1563 pf->vmdq[i].vsi = NULL;
1568 /* need to release fdir resource if exists */
1569 i40e_fdir_teardown(pf);
1574 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1576 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1577 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1578 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1579 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1580 uint16_t msix_vect = vsi->msix_intr;
1583 for (i = 0; i < vsi->nb_qps; i++) {
1584 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1585 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1589 if (vsi->type != I40E_VSI_SRIOV) {
1590 if (!rte_intr_allow_others(intr_handle)) {
1591 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1592 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1594 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1597 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1598 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1600 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1605 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1606 vsi->user_param + (msix_vect - 1);
1608 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1609 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1611 I40E_WRITE_FLUSH(hw);
1615 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1616 int base_queue, int nb_queue,
1621 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1623 /* Bind all RX queues to allocated MSIX interrupt */
1624 for (i = 0; i < nb_queue; i++) {
1625 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1626 itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1627 ((base_queue + i + 1) <<
1628 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1629 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1630 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1632 if (i == nb_queue - 1)
1633 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1634 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1637 /* Write first RX queue to Link list register as the head element */
1638 if (vsi->type != I40E_VSI_SRIOV) {
1640 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL, 1);
1642 if (msix_vect == I40E_MISC_VEC_ID) {
1643 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1645 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1647 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1649 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1652 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1654 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1656 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1658 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1665 if (msix_vect == I40E_MISC_VEC_ID) {
1667 I40E_VPINT_LNKLST0(vsi->user_param),
1669 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1671 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1673 /* num_msix_vectors_vf needs to minus irq0 */
1674 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1675 vsi->user_param + (msix_vect - 1);
1677 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1679 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1681 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1685 I40E_WRITE_FLUSH(hw);
1689 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1691 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1692 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1693 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1694 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1695 uint16_t msix_vect = vsi->msix_intr;
1696 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1697 uint16_t queue_idx = 0;
1702 for (i = 0; i < vsi->nb_qps; i++) {
1703 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1704 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1707 /* INTENA flag is not auto-cleared for interrupt */
1708 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1709 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1710 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1711 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1712 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1714 /* VF bind interrupt */
1715 if (vsi->type == I40E_VSI_SRIOV) {
1716 __vsi_queues_bind_intr(vsi, msix_vect,
1717 vsi->base_queue, vsi->nb_qps,
1722 /* PF & VMDq bind interrupt */
1723 if (rte_intr_dp_is_en(intr_handle)) {
1724 if (vsi->type == I40E_VSI_MAIN) {
1727 } else if (vsi->type == I40E_VSI_VMDQ2) {
1728 struct i40e_vsi *main_vsi =
1729 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1730 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1735 for (i = 0; i < vsi->nb_used_qps; i++) {
1737 if (!rte_intr_allow_others(intr_handle))
1738 /* allow to share MISC_VEC_ID */
1739 msix_vect = I40E_MISC_VEC_ID;
1741 /* no enough msix_vect, map all to one */
1742 __vsi_queues_bind_intr(vsi, msix_vect,
1743 vsi->base_queue + i,
1744 vsi->nb_used_qps - i,
1746 for (; !!record && i < vsi->nb_used_qps; i++)
1747 intr_handle->intr_vec[queue_idx + i] =
1751 /* 1:1 queue/msix_vect mapping */
1752 __vsi_queues_bind_intr(vsi, msix_vect,
1753 vsi->base_queue + i, 1,
1756 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1764 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1766 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1767 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1768 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1769 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1770 uint16_t interval = i40e_calc_itr_interval(\
1771 RTE_LIBRTE_I40E_ITR_INTERVAL, 1);
1772 uint16_t msix_intr, i;
1774 if (rte_intr_allow_others(intr_handle))
1775 for (i = 0; i < vsi->nb_msix; i++) {
1776 msix_intr = vsi->msix_intr + i;
1777 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1778 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1779 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1780 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1782 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1785 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1786 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1787 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1788 (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1790 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1792 I40E_WRITE_FLUSH(hw);
1796 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1798 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1799 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1800 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1801 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1802 uint16_t msix_intr, i;
1804 if (rte_intr_allow_others(intr_handle))
1805 for (i = 0; i < vsi->nb_msix; i++) {
1806 msix_intr = vsi->msix_intr + i;
1807 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1811 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1813 I40E_WRITE_FLUSH(hw);
1816 static inline uint8_t
1817 i40e_parse_link_speeds(uint16_t link_speeds)
1819 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1821 if (link_speeds & ETH_LINK_SPEED_40G)
1822 link_speed |= I40E_LINK_SPEED_40GB;
1823 if (link_speeds & ETH_LINK_SPEED_25G)
1824 link_speed |= I40E_LINK_SPEED_25GB;
1825 if (link_speeds & ETH_LINK_SPEED_20G)
1826 link_speed |= I40E_LINK_SPEED_20GB;
1827 if (link_speeds & ETH_LINK_SPEED_10G)
1828 link_speed |= I40E_LINK_SPEED_10GB;
1829 if (link_speeds & ETH_LINK_SPEED_1G)
1830 link_speed |= I40E_LINK_SPEED_1GB;
1831 if (link_speeds & ETH_LINK_SPEED_100M)
1832 link_speed |= I40E_LINK_SPEED_100MB;
1838 i40e_phy_conf_link(struct i40e_hw *hw,
1840 uint8_t force_speed,
1843 enum i40e_status_code status;
1844 struct i40e_aq_get_phy_abilities_resp phy_ab;
1845 struct i40e_aq_set_phy_config phy_conf;
1846 enum i40e_aq_phy_type cnt;
1847 uint32_t phy_type_mask = 0;
1849 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1850 I40E_AQ_PHY_FLAG_PAUSE_RX |
1851 I40E_AQ_PHY_FLAG_PAUSE_RX |
1852 I40E_AQ_PHY_FLAG_LOW_POWER;
1853 const uint8_t advt = I40E_LINK_SPEED_40GB |
1854 I40E_LINK_SPEED_25GB |
1855 I40E_LINK_SPEED_10GB |
1856 I40E_LINK_SPEED_1GB |
1857 I40E_LINK_SPEED_100MB;
1861 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1866 /* If link already up, no need to set up again */
1867 if (is_up && phy_ab.phy_type != 0)
1868 return I40E_SUCCESS;
1870 memset(&phy_conf, 0, sizeof(phy_conf));
1872 /* bits 0-2 use the values from get_phy_abilities_resp */
1874 abilities |= phy_ab.abilities & mask;
1876 /* update ablities and speed */
1877 if (abilities & I40E_AQ_PHY_AN_ENABLED)
1878 phy_conf.link_speed = advt;
1880 phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed;
1882 phy_conf.abilities = abilities;
1886 /* To enable link, phy_type mask needs to include each type */
1887 for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_MAX; cnt++)
1888 phy_type_mask |= 1 << cnt;
1890 /* use get_phy_abilities_resp value for the rest */
1891 phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
1892 phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
1893 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
1894 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
1895 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1896 phy_conf.eee_capability = phy_ab.eee_capability;
1897 phy_conf.eeer = phy_ab.eeer_val;
1898 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1900 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1901 phy_ab.abilities, phy_ab.link_speed);
1902 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
1903 phy_conf.abilities, phy_conf.link_speed);
1905 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1909 return I40E_SUCCESS;
1913 i40e_apply_link_speed(struct rte_eth_dev *dev)
1916 uint8_t abilities = 0;
1917 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1918 struct rte_eth_conf *conf = &dev->data->dev_conf;
1920 speed = i40e_parse_link_speeds(conf->link_speeds);
1921 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1922 if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1923 abilities |= I40E_AQ_PHY_AN_ENABLED;
1924 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1926 return i40e_phy_conf_link(hw, abilities, speed, true);
1930 i40e_dev_start(struct rte_eth_dev *dev)
1932 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1933 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1934 struct i40e_vsi *main_vsi = pf->main_vsi;
1936 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1937 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1938 uint32_t intr_vector = 0;
1939 struct i40e_vsi *vsi;
1941 hw->adapter_stopped = 0;
1943 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1945 "Invalid link_speeds for port %u, autonegotiation disabled",
1946 dev->data->port_id);
1950 rte_intr_disable(intr_handle);
1952 if ((rte_intr_cap_multiple(intr_handle) ||
1953 !RTE_ETH_DEV_SRIOV(dev).active) &&
1954 dev->data->dev_conf.intr_conf.rxq != 0) {
1955 intr_vector = dev->data->nb_rx_queues;
1956 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1961 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1962 intr_handle->intr_vec =
1963 rte_zmalloc("intr_vec",
1964 dev->data->nb_rx_queues * sizeof(int),
1966 if (!intr_handle->intr_vec) {
1968 "Failed to allocate %d rx_queues intr_vec",
1969 dev->data->nb_rx_queues);
1974 /* Initialize VSI */
1975 ret = i40e_dev_rxtx_init(pf);
1976 if (ret != I40E_SUCCESS) {
1977 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1981 /* Map queues with MSIX interrupt */
1982 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1983 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1984 i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
1985 i40e_vsi_enable_queues_intr(main_vsi);
1987 /* Map VMDQ VSI queues with MSIX interrupt */
1988 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1989 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1990 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
1991 I40E_ITR_INDEX_DEFAULT);
1992 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1995 /* enable FDIR MSIX interrupt */
1996 if (pf->fdir.fdir_vsi) {
1997 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
1998 I40E_ITR_INDEX_NONE);
1999 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2002 /* Enable all queues which have been configured */
2003 ret = i40e_dev_switch_queues(pf, TRUE);
2005 if (ret != I40E_SUCCESS) {
2006 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2010 /* Enable receiving broadcast packets */
2011 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2012 if (ret != I40E_SUCCESS)
2013 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2015 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2016 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2018 if (ret != I40E_SUCCESS)
2019 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2022 /* Enable the VLAN promiscuous mode. */
2024 for (i = 0; i < pf->vf_num; i++) {
2025 vsi = pf->vfs[i].vsi;
2026 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2031 /* Enable mac loopback mode */
2032 if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2033 dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2034 ret = i40e_diag_set_loopback(hw, dev->data->dev_conf.lpbk_mode);
2035 if (ret != I40E_SUCCESS) {
2036 PMD_DRV_LOG(ERR, "fail to set loopback link");
2041 /* Apply link configure */
2042 if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
2043 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
2044 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
2045 ETH_LINK_SPEED_40G)) {
2046 PMD_DRV_LOG(ERR, "Invalid link setting");
2049 ret = i40e_apply_link_speed(dev);
2050 if (I40E_SUCCESS != ret) {
2051 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2055 if (!rte_intr_allow_others(intr_handle)) {
2056 rte_intr_callback_unregister(intr_handle,
2057 i40e_dev_interrupt_handler,
2059 /* configure and enable device interrupt */
2060 i40e_pf_config_irq0(hw, FALSE);
2061 i40e_pf_enable_irq0(hw);
2063 if (dev->data->dev_conf.intr_conf.lsc != 0)
2065 "lsc won't enable because of no intr multiplex");
2067 ret = i40e_aq_set_phy_int_mask(hw,
2068 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2069 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2070 I40E_AQ_EVENT_MEDIA_NA), NULL);
2071 if (ret != I40E_SUCCESS)
2072 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2074 /* Call get_link_info aq commond to enable/disable LSE */
2075 i40e_dev_link_update(dev, 0);
2078 /* enable uio intr after callback register */
2079 rte_intr_enable(intr_handle);
2081 i40e_filter_restore(pf);
2083 if (pf->tm_conf.root && !pf->tm_conf.committed)
2084 PMD_DRV_LOG(WARNING,
2085 "please call hierarchy_commit() "
2086 "before starting the port");
2088 return I40E_SUCCESS;
2091 i40e_dev_switch_queues(pf, FALSE);
2092 i40e_dev_clear_queues(dev);
2098 i40e_dev_stop(struct rte_eth_dev *dev)
2100 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2101 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2102 struct i40e_vsi *main_vsi = pf->main_vsi;
2103 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2104 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2107 if (hw->adapter_stopped == 1)
2109 /* Disable all queues */
2110 i40e_dev_switch_queues(pf, FALSE);
2112 /* un-map queues with interrupt registers */
2113 i40e_vsi_disable_queues_intr(main_vsi);
2114 i40e_vsi_queues_unbind_intr(main_vsi);
2116 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2117 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2118 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2121 if (pf->fdir.fdir_vsi) {
2122 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2123 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2125 /* Clear all queues and release memory */
2126 i40e_dev_clear_queues(dev);
2129 i40e_dev_set_link_down(dev);
2131 if (!rte_intr_allow_others(intr_handle))
2132 /* resume to the default handler */
2133 rte_intr_callback_register(intr_handle,
2134 i40e_dev_interrupt_handler,
2137 /* Clean datapath event and queue/vec mapping */
2138 rte_intr_efd_disable(intr_handle);
2139 if (intr_handle->intr_vec) {
2140 rte_free(intr_handle->intr_vec);
2141 intr_handle->intr_vec = NULL;
2144 /* reset hierarchy commit */
2145 pf->tm_conf.committed = false;
2147 /* Remove all the queue region configuration */
2148 i40e_flush_queue_region_all_conf(dev, hw, pf, 0);
2150 hw->adapter_stopped = 1;
2154 i40e_dev_close(struct rte_eth_dev *dev)
2156 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2157 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2158 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2159 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2160 struct i40e_mirror_rule *p_mirror;
2165 PMD_INIT_FUNC_TRACE();
2169 /* Remove all mirror rules */
2170 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2171 ret = i40e_aq_del_mirror_rule(hw,
2172 pf->main_vsi->veb->seid,
2173 p_mirror->rule_type,
2175 p_mirror->num_entries,
2178 PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2179 "status = %d, aq_err = %d.", ret,
2180 hw->aq.asq_last_status);
2182 /* remove mirror software resource anyway */
2183 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2185 pf->nb_mirror_rule--;
2188 i40e_dev_free_queues(dev);
2190 /* Disable interrupt */
2191 i40e_pf_disable_irq0(hw);
2192 rte_intr_disable(intr_handle);
2194 /* shutdown and destroy the HMC */
2195 i40e_shutdown_lan_hmc(hw);
2197 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2198 i40e_vsi_release(pf->vmdq[i].vsi);
2199 pf->vmdq[i].vsi = NULL;
2204 /* release all the existing VSIs and VEBs */
2205 i40e_fdir_teardown(pf);
2206 i40e_vsi_release(pf->main_vsi);
2208 /* shutdown the adminq */
2209 i40e_aq_queue_shutdown(hw, true);
2210 i40e_shutdown_adminq(hw);
2212 i40e_res_pool_destroy(&pf->qp_pool);
2213 i40e_res_pool_destroy(&pf->msix_pool);
2215 /* Disable flexible payload in global configuration */
2216 i40e_flex_payload_reg_set_default(hw);
2218 /* force a PF reset to clean anything leftover */
2219 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2220 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2221 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2222 I40E_WRITE_FLUSH(hw);
2226 * Reset PF device only to re-initialize resources in PMD layer
2229 i40e_dev_reset(struct rte_eth_dev *dev)
2233 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2234 * its VF to make them align with it. The detailed notification
2235 * mechanism is PMD specific. As to i40e PF, it is rather complex.
2236 * To avoid unexpected behavior in VF, currently reset of PF with
2237 * SR-IOV activation is not supported. It might be supported later.
2239 if (dev->data->sriov.active)
2242 ret = eth_i40e_dev_uninit(dev);
2246 ret = eth_i40e_dev_init(dev);
2252 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2254 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2255 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2256 struct i40e_vsi *vsi = pf->main_vsi;
2259 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2261 if (status != I40E_SUCCESS)
2262 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2264 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2266 if (status != I40E_SUCCESS)
2267 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2272 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2274 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2275 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2276 struct i40e_vsi *vsi = pf->main_vsi;
2279 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2281 if (status != I40E_SUCCESS)
2282 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2284 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2286 if (status != I40E_SUCCESS)
2287 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2291 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2293 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2294 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2295 struct i40e_vsi *vsi = pf->main_vsi;
2298 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2299 if (ret != I40E_SUCCESS)
2300 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2304 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2306 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2307 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2308 struct i40e_vsi *vsi = pf->main_vsi;
2311 if (dev->data->promiscuous == 1)
2312 return; /* must remain in all_multicast mode */
2314 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2315 vsi->seid, FALSE, NULL);
2316 if (ret != I40E_SUCCESS)
2317 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2321 * Set device link up.
2324 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2326 /* re-apply link speed setting */
2327 return i40e_apply_link_speed(dev);
2331 * Set device link down.
2334 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2336 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2337 uint8_t abilities = 0;
2338 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2340 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2341 return i40e_phy_conf_link(hw, abilities, speed, false);
2345 i40e_dev_link_update(struct rte_eth_dev *dev,
2346 int wait_to_complete)
2348 #define CHECK_INTERVAL 100 /* 100ms */
2349 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2350 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2351 struct i40e_link_status link_status;
2352 struct rte_eth_link link, old;
2354 unsigned rep_cnt = MAX_REPEAT_TIME;
2355 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2357 memset(&link, 0, sizeof(link));
2358 memset(&old, 0, sizeof(old));
2359 memset(&link_status, 0, sizeof(link_status));
2360 rte_i40e_dev_atomic_read_link_status(dev, &old);
2363 /* Get link status information from hardware */
2364 status = i40e_aq_get_link_info(hw, enable_lse,
2365 &link_status, NULL);
2366 if (status != I40E_SUCCESS) {
2367 link.link_speed = ETH_SPEED_NUM_100M;
2368 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2369 PMD_DRV_LOG(ERR, "Failed to get link info");
2373 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2374 if (!wait_to_complete || link.link_status)
2377 rte_delay_ms(CHECK_INTERVAL);
2378 } while (--rep_cnt);
2380 if (!link.link_status)
2383 /* i40e uses full duplex only */
2384 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2386 /* Parse the link status */
2387 switch (link_status.link_speed) {
2388 case I40E_LINK_SPEED_100MB:
2389 link.link_speed = ETH_SPEED_NUM_100M;
2391 case I40E_LINK_SPEED_1GB:
2392 link.link_speed = ETH_SPEED_NUM_1G;
2394 case I40E_LINK_SPEED_10GB:
2395 link.link_speed = ETH_SPEED_NUM_10G;
2397 case I40E_LINK_SPEED_20GB:
2398 link.link_speed = ETH_SPEED_NUM_20G;
2400 case I40E_LINK_SPEED_25GB:
2401 link.link_speed = ETH_SPEED_NUM_25G;
2403 case I40E_LINK_SPEED_40GB:
2404 link.link_speed = ETH_SPEED_NUM_40G;
2407 link.link_speed = ETH_SPEED_NUM_100M;
2411 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2412 ETH_LINK_SPEED_FIXED);
2415 rte_i40e_dev_atomic_write_link_status(dev, &link);
2416 if (link.link_status == old.link_status)
2419 i40e_notify_all_vfs_link_status(dev);
2424 /* Get all the statistics of a VSI */
2426 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2428 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2429 struct i40e_eth_stats *nes = &vsi->eth_stats;
2430 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2431 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2433 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2434 vsi->offset_loaded, &oes->rx_bytes,
2436 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2437 vsi->offset_loaded, &oes->rx_unicast,
2439 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2440 vsi->offset_loaded, &oes->rx_multicast,
2441 &nes->rx_multicast);
2442 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2443 vsi->offset_loaded, &oes->rx_broadcast,
2444 &nes->rx_broadcast);
2445 /* exclude CRC bytes */
2446 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2447 nes->rx_broadcast) * ETHER_CRC_LEN;
2449 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2450 &oes->rx_discards, &nes->rx_discards);
2451 /* GLV_REPC not supported */
2452 /* GLV_RMPC not supported */
2453 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2454 &oes->rx_unknown_protocol,
2455 &nes->rx_unknown_protocol);
2456 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2457 vsi->offset_loaded, &oes->tx_bytes,
2459 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2460 vsi->offset_loaded, &oes->tx_unicast,
2462 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2463 vsi->offset_loaded, &oes->tx_multicast,
2464 &nes->tx_multicast);
2465 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2466 vsi->offset_loaded, &oes->tx_broadcast,
2467 &nes->tx_broadcast);
2468 /* GLV_TDPC not supported */
2469 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2470 &oes->tx_errors, &nes->tx_errors);
2471 vsi->offset_loaded = true;
2473 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2475 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2476 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2477 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2478 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2479 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2480 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2481 nes->rx_unknown_protocol);
2482 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2483 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2484 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2485 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2486 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2487 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2488 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2493 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2496 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2497 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2499 /* Get rx/tx bytes of internal transfer packets */
2500 i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2501 I40E_GLV_GORCL(hw->port),
2503 &pf->internal_stats_offset.rx_bytes,
2504 &pf->internal_stats.rx_bytes);
2506 i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2507 I40E_GLV_GOTCL(hw->port),
2509 &pf->internal_stats_offset.tx_bytes,
2510 &pf->internal_stats.tx_bytes);
2511 /* Get total internal rx packet count */
2512 i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2513 I40E_GLV_UPRCL(hw->port),
2515 &pf->internal_stats_offset.rx_unicast,
2516 &pf->internal_stats.rx_unicast);
2517 i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2518 I40E_GLV_MPRCL(hw->port),
2520 &pf->internal_stats_offset.rx_multicast,
2521 &pf->internal_stats.rx_multicast);
2522 i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2523 I40E_GLV_BPRCL(hw->port),
2525 &pf->internal_stats_offset.rx_broadcast,
2526 &pf->internal_stats.rx_broadcast);
2527 /* Get total internal tx packet count */
2528 i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
2529 I40E_GLV_UPTCL(hw->port),
2531 &pf->internal_stats_offset.tx_unicast,
2532 &pf->internal_stats.tx_unicast);
2533 i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
2534 I40E_GLV_MPTCL(hw->port),
2536 &pf->internal_stats_offset.tx_multicast,
2537 &pf->internal_stats.tx_multicast);
2538 i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
2539 I40E_GLV_BPTCL(hw->port),
2541 &pf->internal_stats_offset.tx_broadcast,
2542 &pf->internal_stats.tx_broadcast);
2544 /* exclude CRC size */
2545 pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2546 pf->internal_stats.rx_multicast +
2547 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2549 /* Get statistics of struct i40e_eth_stats */
2550 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2551 I40E_GLPRT_GORCL(hw->port),
2552 pf->offset_loaded, &os->eth.rx_bytes,
2554 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2555 I40E_GLPRT_UPRCL(hw->port),
2556 pf->offset_loaded, &os->eth.rx_unicast,
2557 &ns->eth.rx_unicast);
2558 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2559 I40E_GLPRT_MPRCL(hw->port),
2560 pf->offset_loaded, &os->eth.rx_multicast,
2561 &ns->eth.rx_multicast);
2562 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2563 I40E_GLPRT_BPRCL(hw->port),
2564 pf->offset_loaded, &os->eth.rx_broadcast,
2565 &ns->eth.rx_broadcast);
2566 /* Workaround: CRC size should not be included in byte statistics,
2567 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2569 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2570 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2572 /* exclude internal rx bytes
2573 * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2574 * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
2576 * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
2578 if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2579 ns->eth.rx_bytes = 0;
2581 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2583 if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
2584 ns->eth.rx_unicast = 0;
2586 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
2588 if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
2589 ns->eth.rx_multicast = 0;
2591 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
2593 if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
2594 ns->eth.rx_broadcast = 0;
2596 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
2598 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2599 pf->offset_loaded, &os->eth.rx_discards,
2600 &ns->eth.rx_discards);
2601 /* GLPRT_REPC not supported */
2602 /* GLPRT_RMPC not supported */
2603 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2605 &os->eth.rx_unknown_protocol,
2606 &ns->eth.rx_unknown_protocol);
2607 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2608 I40E_GLPRT_GOTCL(hw->port),
2609 pf->offset_loaded, &os->eth.tx_bytes,
2611 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2612 I40E_GLPRT_UPTCL(hw->port),
2613 pf->offset_loaded, &os->eth.tx_unicast,
2614 &ns->eth.tx_unicast);
2615 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2616 I40E_GLPRT_MPTCL(hw->port),
2617 pf->offset_loaded, &os->eth.tx_multicast,
2618 &ns->eth.tx_multicast);
2619 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2620 I40E_GLPRT_BPTCL(hw->port),
2621 pf->offset_loaded, &os->eth.tx_broadcast,
2622 &ns->eth.tx_broadcast);
2623 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2624 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2626 /* exclude internal tx bytes
2627 * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
2628 * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
2630 * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
2632 if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2633 ns->eth.tx_bytes = 0;
2635 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2637 if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
2638 ns->eth.tx_unicast = 0;
2640 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
2642 if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
2643 ns->eth.tx_multicast = 0;
2645 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
2647 if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
2648 ns->eth.tx_broadcast = 0;
2650 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
2652 /* GLPRT_TEPC not supported */
2654 /* additional port specific stats */
2655 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2656 pf->offset_loaded, &os->tx_dropped_link_down,
2657 &ns->tx_dropped_link_down);
2658 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2659 pf->offset_loaded, &os->crc_errors,
2661 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2662 pf->offset_loaded, &os->illegal_bytes,
2663 &ns->illegal_bytes);
2664 /* GLPRT_ERRBC not supported */
2665 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2666 pf->offset_loaded, &os->mac_local_faults,
2667 &ns->mac_local_faults);
2668 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2669 pf->offset_loaded, &os->mac_remote_faults,
2670 &ns->mac_remote_faults);
2671 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2672 pf->offset_loaded, &os->rx_length_errors,
2673 &ns->rx_length_errors);
2674 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2675 pf->offset_loaded, &os->link_xon_rx,
2677 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2678 pf->offset_loaded, &os->link_xoff_rx,
2680 for (i = 0; i < 8; i++) {
2681 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2683 &os->priority_xon_rx[i],
2684 &ns->priority_xon_rx[i]);
2685 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2687 &os->priority_xoff_rx[i],
2688 &ns->priority_xoff_rx[i]);
2690 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2691 pf->offset_loaded, &os->link_xon_tx,
2693 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2694 pf->offset_loaded, &os->link_xoff_tx,
2696 for (i = 0; i < 8; i++) {
2697 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2699 &os->priority_xon_tx[i],
2700 &ns->priority_xon_tx[i]);
2701 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2703 &os->priority_xoff_tx[i],
2704 &ns->priority_xoff_tx[i]);
2705 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2707 &os->priority_xon_2_xoff[i],
2708 &ns->priority_xon_2_xoff[i]);
2710 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2711 I40E_GLPRT_PRC64L(hw->port),
2712 pf->offset_loaded, &os->rx_size_64,
2714 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2715 I40E_GLPRT_PRC127L(hw->port),
2716 pf->offset_loaded, &os->rx_size_127,
2718 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2719 I40E_GLPRT_PRC255L(hw->port),
2720 pf->offset_loaded, &os->rx_size_255,
2722 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2723 I40E_GLPRT_PRC511L(hw->port),
2724 pf->offset_loaded, &os->rx_size_511,
2726 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2727 I40E_GLPRT_PRC1023L(hw->port),
2728 pf->offset_loaded, &os->rx_size_1023,
2730 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2731 I40E_GLPRT_PRC1522L(hw->port),
2732 pf->offset_loaded, &os->rx_size_1522,
2734 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2735 I40E_GLPRT_PRC9522L(hw->port),
2736 pf->offset_loaded, &os->rx_size_big,
2738 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2739 pf->offset_loaded, &os->rx_undersize,
2741 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2742 pf->offset_loaded, &os->rx_fragments,
2744 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2745 pf->offset_loaded, &os->rx_oversize,
2747 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2748 pf->offset_loaded, &os->rx_jabber,
2750 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2751 I40E_GLPRT_PTC64L(hw->port),
2752 pf->offset_loaded, &os->tx_size_64,
2754 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2755 I40E_GLPRT_PTC127L(hw->port),
2756 pf->offset_loaded, &os->tx_size_127,
2758 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2759 I40E_GLPRT_PTC255L(hw->port),
2760 pf->offset_loaded, &os->tx_size_255,
2762 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2763 I40E_GLPRT_PTC511L(hw->port),
2764 pf->offset_loaded, &os->tx_size_511,
2766 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2767 I40E_GLPRT_PTC1023L(hw->port),
2768 pf->offset_loaded, &os->tx_size_1023,
2770 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2771 I40E_GLPRT_PTC1522L(hw->port),
2772 pf->offset_loaded, &os->tx_size_1522,
2774 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2775 I40E_GLPRT_PTC9522L(hw->port),
2776 pf->offset_loaded, &os->tx_size_big,
2778 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2780 &os->fd_sb_match, &ns->fd_sb_match);
2781 /* GLPRT_MSPDC not supported */
2782 /* GLPRT_XEC not supported */
2784 pf->offset_loaded = true;
2787 i40e_update_vsi_stats(pf->main_vsi);
2790 /* Get all statistics of a port */
2792 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2794 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2795 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2796 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2799 /* call read registers - updates values, now write them to struct */
2800 i40e_read_stats_registers(pf, hw);
2802 stats->ipackets = ns->eth.rx_unicast +
2803 ns->eth.rx_multicast +
2804 ns->eth.rx_broadcast -
2805 ns->eth.rx_discards -
2806 pf->main_vsi->eth_stats.rx_discards;
2807 stats->opackets = ns->eth.tx_unicast +
2808 ns->eth.tx_multicast +
2809 ns->eth.tx_broadcast;
2810 stats->ibytes = ns->eth.rx_bytes;
2811 stats->obytes = ns->eth.tx_bytes;
2812 stats->oerrors = ns->eth.tx_errors +
2813 pf->main_vsi->eth_stats.tx_errors;
2816 stats->imissed = ns->eth.rx_discards +
2817 pf->main_vsi->eth_stats.rx_discards;
2818 stats->ierrors = ns->crc_errors +
2819 ns->rx_length_errors + ns->rx_undersize +
2820 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2822 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2823 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
2824 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
2825 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
2826 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
2827 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
2828 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2829 ns->eth.rx_unknown_protocol);
2830 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
2831 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
2832 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
2833 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
2834 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
2835 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
2837 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
2838 ns->tx_dropped_link_down);
2839 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
2840 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
2842 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
2843 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
2844 ns->mac_local_faults);
2845 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
2846 ns->mac_remote_faults);
2847 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
2848 ns->rx_length_errors);
2849 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
2850 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
2851 for (i = 0; i < 8; i++) {
2852 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
2853 i, ns->priority_xon_rx[i]);
2854 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
2855 i, ns->priority_xoff_rx[i]);
2857 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
2858 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
2859 for (i = 0; i < 8; i++) {
2860 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
2861 i, ns->priority_xon_tx[i]);
2862 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
2863 i, ns->priority_xoff_tx[i]);
2864 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
2865 i, ns->priority_xon_2_xoff[i]);
2867 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
2868 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
2869 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
2870 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
2871 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
2872 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
2873 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
2874 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
2875 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
2876 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
2877 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
2878 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
2879 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
2880 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
2881 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
2882 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
2883 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
2884 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
2885 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2886 ns->mac_short_packet_dropped);
2887 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
2888 ns->checksum_error);
2889 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
2890 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2894 /* Reset the statistics */
2896 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2898 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2899 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2901 /* Mark PF and VSI stats to update the offset, aka "reset" */
2902 pf->offset_loaded = false;
2904 pf->main_vsi->offset_loaded = false;
2906 /* read the stats, reading current register values into offset */
2907 i40e_read_stats_registers(pf, hw);
2911 i40e_xstats_calc_num(void)
2913 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2914 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2915 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2918 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2919 struct rte_eth_xstat_name *xstats_names,
2920 __rte_unused unsigned limit)
2925 if (xstats_names == NULL)
2926 return i40e_xstats_calc_num();
2928 /* Note: limit checked in rte_eth_xstats_names() */
2930 /* Get stats from i40e_eth_stats struct */
2931 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2932 snprintf(xstats_names[count].name,
2933 sizeof(xstats_names[count].name),
2934 "%s", rte_i40e_stats_strings[i].name);
2938 /* Get individiual stats from i40e_hw_port struct */
2939 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2940 snprintf(xstats_names[count].name,
2941 sizeof(xstats_names[count].name),
2942 "%s", rte_i40e_hw_port_strings[i].name);
2946 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2947 for (prio = 0; prio < 8; prio++) {
2948 snprintf(xstats_names[count].name,
2949 sizeof(xstats_names[count].name),
2950 "rx_priority%u_%s", prio,
2951 rte_i40e_rxq_prio_strings[i].name);
2956 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2957 for (prio = 0; prio < 8; prio++) {
2958 snprintf(xstats_names[count].name,
2959 sizeof(xstats_names[count].name),
2960 "tx_priority%u_%s", prio,
2961 rte_i40e_txq_prio_strings[i].name);
2969 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2972 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2973 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2974 unsigned i, count, prio;
2975 struct i40e_hw_port_stats *hw_stats = &pf->stats;
2977 count = i40e_xstats_calc_num();
2981 i40e_read_stats_registers(pf, hw);
2988 /* Get stats from i40e_eth_stats struct */
2989 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2990 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2991 rte_i40e_stats_strings[i].offset);
2992 xstats[count].id = count;
2996 /* Get individiual stats from i40e_hw_port struct */
2997 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2998 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2999 rte_i40e_hw_port_strings[i].offset);
3000 xstats[count].id = count;
3004 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3005 for (prio = 0; prio < 8; prio++) {
3006 xstats[count].value =
3007 *(uint64_t *)(((char *)hw_stats) +
3008 rte_i40e_rxq_prio_strings[i].offset +
3009 (sizeof(uint64_t) * prio));
3010 xstats[count].id = count;
3015 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3016 for (prio = 0; prio < 8; prio++) {
3017 xstats[count].value =
3018 *(uint64_t *)(((char *)hw_stats) +
3019 rte_i40e_txq_prio_strings[i].offset +
3020 (sizeof(uint64_t) * prio));
3021 xstats[count].id = count;
3030 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
3031 __rte_unused uint16_t queue_id,
3032 __rte_unused uint8_t stat_idx,
3033 __rte_unused uint8_t is_rx)
3035 PMD_INIT_FUNC_TRACE();
3041 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3043 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3049 full_ver = hw->nvm.oem_ver;
3050 ver = (u8)(full_ver >> 24);
3051 build = (u16)((full_ver >> 8) & 0xffff);
3052 patch = (u8)(full_ver & 0xff);
3054 ret = snprintf(fw_version, fw_size,
3055 "%d.%d%d 0x%08x %d.%d.%d",
3056 ((hw->nvm.version >> 12) & 0xf),
3057 ((hw->nvm.version >> 4) & 0xff),
3058 (hw->nvm.version & 0xf), hw->nvm.eetrack,
3061 ret += 1; /* add the size of '\0' */
3062 if (fw_size < (u32)ret)
3069 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3071 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3072 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3073 struct i40e_vsi *vsi = pf->main_vsi;
3074 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3076 dev_info->pci_dev = pci_dev;
3077 dev_info->max_rx_queues = vsi->nb_qps;
3078 dev_info->max_tx_queues = vsi->nb_qps;
3079 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3080 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3081 dev_info->max_mac_addrs = vsi->max_macaddrs;
3082 dev_info->max_vfs = pci_dev->max_vfs;
3083 dev_info->rx_offload_capa =
3084 DEV_RX_OFFLOAD_VLAN_STRIP |
3085 DEV_RX_OFFLOAD_QINQ_STRIP |
3086 DEV_RX_OFFLOAD_IPV4_CKSUM |
3087 DEV_RX_OFFLOAD_UDP_CKSUM |
3088 DEV_RX_OFFLOAD_TCP_CKSUM;
3089 dev_info->tx_offload_capa =
3090 DEV_TX_OFFLOAD_VLAN_INSERT |
3091 DEV_TX_OFFLOAD_QINQ_INSERT |
3092 DEV_TX_OFFLOAD_IPV4_CKSUM |
3093 DEV_TX_OFFLOAD_UDP_CKSUM |
3094 DEV_TX_OFFLOAD_TCP_CKSUM |
3095 DEV_TX_OFFLOAD_SCTP_CKSUM |
3096 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3097 DEV_TX_OFFLOAD_TCP_TSO |
3098 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3099 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3100 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3101 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
3102 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3104 dev_info->reta_size = pf->hash_lut_size;
3105 dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3107 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3109 .pthresh = I40E_DEFAULT_RX_PTHRESH,
3110 .hthresh = I40E_DEFAULT_RX_HTHRESH,
3111 .wthresh = I40E_DEFAULT_RX_WTHRESH,
3113 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3117 dev_info->default_txconf = (struct rte_eth_txconf) {
3119 .pthresh = I40E_DEFAULT_TX_PTHRESH,
3120 .hthresh = I40E_DEFAULT_TX_HTHRESH,
3121 .wthresh = I40E_DEFAULT_TX_WTHRESH,
3123 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3124 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3125 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3126 ETH_TXQ_FLAGS_NOOFFLOADS,
3129 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3130 .nb_max = I40E_MAX_RING_DESC,
3131 .nb_min = I40E_MIN_RING_DESC,
3132 .nb_align = I40E_ALIGN_RING_DESC,
3135 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3136 .nb_max = I40E_MAX_RING_DESC,
3137 .nb_min = I40E_MIN_RING_DESC,
3138 .nb_align = I40E_ALIGN_RING_DESC,
3139 .nb_seg_max = I40E_TX_MAX_SEG,
3140 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3143 if (pf->flags & I40E_FLAG_VMDQ) {
3144 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3145 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3146 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3147 pf->max_nb_vmdq_vsi;
3148 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3149 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3150 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3153 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
3155 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3156 else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
3158 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3161 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3165 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3167 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3168 struct i40e_vsi *vsi = pf->main_vsi;
3169 PMD_INIT_FUNC_TRACE();
3172 return i40e_vsi_add_vlan(vsi, vlan_id);
3174 return i40e_vsi_delete_vlan(vsi, vlan_id);
3178 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3179 enum rte_vlan_type vlan_type,
3180 uint16_t tpid, int qinq)
3182 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3185 uint16_t reg_id = 3;
3189 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3193 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3195 if (ret != I40E_SUCCESS) {
3197 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3202 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3205 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3206 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3207 if (reg_r == reg_w) {
3208 PMD_DRV_LOG(DEBUG, "No need to write");
3212 ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3214 if (ret != I40E_SUCCESS) {
3216 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3221 "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3228 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3229 enum rte_vlan_type vlan_type,
3232 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3233 int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
3236 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3237 vlan_type != ETH_VLAN_TYPE_OUTER) ||
3238 (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3240 "Unsupported vlan type.");
3243 /* 802.1ad frames ability is added in NVM API 1.7*/
3244 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3246 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3247 hw->first_tag = rte_cpu_to_le_16(tpid);
3248 else if (vlan_type == ETH_VLAN_TYPE_INNER)
3249 hw->second_tag = rte_cpu_to_le_16(tpid);
3251 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3252 hw->second_tag = rte_cpu_to_le_16(tpid);
3254 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3255 if (ret != I40E_SUCCESS) {
3257 "Set switch config failed aq_err: %d",
3258 hw->aq.asq_last_status);
3262 /* If NVM API < 1.7, keep the register setting */
3263 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3270 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3272 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3273 struct i40e_vsi *vsi = pf->main_vsi;
3275 if (mask & ETH_VLAN_FILTER_MASK) {
3276 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3277 i40e_vsi_config_vlan_filter(vsi, TRUE);
3279 i40e_vsi_config_vlan_filter(vsi, FALSE);
3282 if (mask & ETH_VLAN_STRIP_MASK) {
3283 /* Enable or disable VLAN stripping */
3284 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3285 i40e_vsi_config_vlan_stripping(vsi, TRUE);
3287 i40e_vsi_config_vlan_stripping(vsi, FALSE);
3290 if (mask & ETH_VLAN_EXTEND_MASK) {
3291 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3292 i40e_vsi_config_double_vlan(vsi, TRUE);
3293 /* Set global registers with default ethertype. */
3294 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3296 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3300 i40e_vsi_config_double_vlan(vsi, FALSE);
3307 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3308 __rte_unused uint16_t queue,
3309 __rte_unused int on)
3311 PMD_INIT_FUNC_TRACE();
3315 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3317 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3318 struct i40e_vsi *vsi = pf->main_vsi;
3319 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3320 struct i40e_vsi_vlan_pvid_info info;
3322 memset(&info, 0, sizeof(info));
3325 info.config.pvid = pvid;
3327 info.config.reject.tagged =
3328 data->dev_conf.txmode.hw_vlan_reject_tagged;
3329 info.config.reject.untagged =
3330 data->dev_conf.txmode.hw_vlan_reject_untagged;
3333 return i40e_vsi_vlan_pvid_set(vsi, &info);
3337 i40e_dev_led_on(struct rte_eth_dev *dev)
3339 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3340 uint32_t mode = i40e_led_get(hw);
3343 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3349 i40e_dev_led_off(struct rte_eth_dev *dev)
3351 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3352 uint32_t mode = i40e_led_get(hw);
3355 i40e_led_set(hw, 0, false);
3361 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3363 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3364 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3366 fc_conf->pause_time = pf->fc_conf.pause_time;
3368 /* read out from register, in case they are modified by other port */
3369 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3370 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3371 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3372 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3374 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3375 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3377 /* Return current mode according to actual setting*/
3378 switch (hw->fc.current_mode) {
3380 fc_conf->mode = RTE_FC_FULL;
3382 case I40E_FC_TX_PAUSE:
3383 fc_conf->mode = RTE_FC_TX_PAUSE;
3385 case I40E_FC_RX_PAUSE:
3386 fc_conf->mode = RTE_FC_RX_PAUSE;
3390 fc_conf->mode = RTE_FC_NONE;
3397 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3399 uint32_t mflcn_reg, fctrl_reg, reg;
3400 uint32_t max_high_water;
3401 uint8_t i, aq_failure;
3405 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3406 [RTE_FC_NONE] = I40E_FC_NONE,
3407 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3408 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3409 [RTE_FC_FULL] = I40E_FC_FULL
3412 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3414 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3415 if ((fc_conf->high_water > max_high_water) ||
3416 (fc_conf->high_water < fc_conf->low_water)) {
3418 "Invalid high/low water setup value in KB, High_water must be <= %d.",
3423 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3424 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3425 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3427 pf->fc_conf.pause_time = fc_conf->pause_time;
3428 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3429 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3431 PMD_INIT_FUNC_TRACE();
3433 /* All the link flow control related enable/disable register
3434 * configuration is handle by the F/W
3436 err = i40e_set_fc(hw, &aq_failure, true);
3440 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3441 /* Configure flow control refresh threshold,
3442 * the value for stat_tx_pause_refresh_timer[8]
3443 * is used for global pause operation.
3447 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3448 pf->fc_conf.pause_time);
3450 /* configure the timer value included in transmitted pause
3452 * the value for stat_tx_pause_quanta[8] is used for global
3455 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3456 pf->fc_conf.pause_time);
3458 fctrl_reg = I40E_READ_REG(hw,
3459 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3461 if (fc_conf->mac_ctrl_frame_fwd != 0)
3462 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3464 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3466 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3469 /* Configure pause time (2 TCs per register) */
3470 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3471 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3472 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3474 /* Configure flow control refresh threshold value */
3475 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3476 pf->fc_conf.pause_time / 2);
3478 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3480 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3481 *depending on configuration
3483 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3484 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3485 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3487 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3488 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3491 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3494 /* config the water marker both based on the packets and bytes */
3495 I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3496 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3497 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3498 I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3499 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3500 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3501 I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3502 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3504 I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3505 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3508 I40E_WRITE_FLUSH(hw);
3514 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3515 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3517 PMD_INIT_FUNC_TRACE();
3522 /* Add a MAC address, and update filters */
3524 i40e_macaddr_add(struct rte_eth_dev *dev,
3525 struct ether_addr *mac_addr,
3526 __rte_unused uint32_t index,
3529 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3530 struct i40e_mac_filter_info mac_filter;
3531 struct i40e_vsi *vsi;
3534 /* If VMDQ not enabled or configured, return */
3535 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3536 !pf->nb_cfg_vmdq_vsi)) {
3537 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3538 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3543 if (pool > pf->nb_cfg_vmdq_vsi) {
3544 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3545 pool, pf->nb_cfg_vmdq_vsi);
3549 rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3550 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3551 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3553 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3558 vsi = pf->vmdq[pool - 1].vsi;
3560 ret = i40e_vsi_add_mac(vsi, &mac_filter);
3561 if (ret != I40E_SUCCESS) {
3562 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3568 /* Remove a MAC address, and update filters */
3570 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3572 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3573 struct i40e_vsi *vsi;
3574 struct rte_eth_dev_data *data = dev->data;
3575 struct ether_addr *macaddr;
3580 macaddr = &(data->mac_addrs[index]);
3582 pool_sel = dev->data->mac_pool_sel[index];
3584 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3585 if (pool_sel & (1ULL << i)) {
3589 /* No VMDQ pool enabled or configured */
3590 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3591 (i > pf->nb_cfg_vmdq_vsi)) {
3593 "No VMDQ pool enabled/configured");
3596 vsi = pf->vmdq[i - 1].vsi;
3598 ret = i40e_vsi_delete_mac(vsi, macaddr);
3601 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3608 /* Set perfect match or hash match of MAC and VLAN for a VF */
3610 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3611 struct rte_eth_mac_filter *filter,
3615 struct i40e_mac_filter_info mac_filter;
3616 struct ether_addr old_mac;
3617 struct ether_addr *new_mac;
3618 struct i40e_pf_vf *vf = NULL;
3623 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3626 hw = I40E_PF_TO_HW(pf);
3628 if (filter == NULL) {
3629 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3633 new_mac = &filter->mac_addr;
3635 if (is_zero_ether_addr(new_mac)) {
3636 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3640 vf_id = filter->dst_id;
3642 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3643 PMD_DRV_LOG(ERR, "Invalid argument.");
3646 vf = &pf->vfs[vf_id];
3648 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3649 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3654 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3655 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3657 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3660 mac_filter.filter_type = filter->filter_type;
3661 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3662 if (ret != I40E_SUCCESS) {
3663 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3666 ether_addr_copy(new_mac, &pf->dev_addr);
3668 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3670 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3671 if (ret != I40E_SUCCESS) {
3672 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3676 /* Clear device address as it has been removed */
3677 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3678 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3684 /* MAC filter handle */
3686 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3689 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3690 struct rte_eth_mac_filter *filter;
3691 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3692 int ret = I40E_NOT_SUPPORTED;
3694 filter = (struct rte_eth_mac_filter *)(arg);
3696 switch (filter_op) {
3697 case RTE_ETH_FILTER_NOP:
3700 case RTE_ETH_FILTER_ADD:
3701 i40e_pf_disable_irq0(hw);
3703 ret = i40e_vf_mac_filter_set(pf, filter, 1);
3704 i40e_pf_enable_irq0(hw);
3706 case RTE_ETH_FILTER_DELETE:
3707 i40e_pf_disable_irq0(hw);
3709 ret = i40e_vf_mac_filter_set(pf, filter, 0);
3710 i40e_pf_enable_irq0(hw);
3713 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3714 ret = I40E_ERR_PARAM;
3722 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3724 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3725 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3732 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3733 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3736 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3740 uint32_t *lut_dw = (uint32_t *)lut;
3741 uint16_t i, lut_size_dw = lut_size / 4;
3743 if (vsi->type == I40E_VSI_SRIOV) {
3744 for (i = 0; i <= lut_size_dw; i++) {
3745 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
3746 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
3749 for (i = 0; i < lut_size_dw; i++)
3750 lut_dw[i] = I40E_READ_REG(hw,
3759 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3768 pf = I40E_VSI_TO_PF(vsi);
3769 hw = I40E_VSI_TO_HW(vsi);
3771 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3772 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3775 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3779 uint32_t *lut_dw = (uint32_t *)lut;
3780 uint16_t i, lut_size_dw = lut_size / 4;
3782 if (vsi->type == I40E_VSI_SRIOV) {
3783 for (i = 0; i < lut_size_dw; i++)
3786 I40E_VFQF_HLUT1(i, vsi->user_param),
3789 for (i = 0; i < lut_size_dw; i++)
3790 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
3793 I40E_WRITE_FLUSH(hw);
3800 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3801 struct rte_eth_rss_reta_entry64 *reta_conf,
3804 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3805 uint16_t i, lut_size = pf->hash_lut_size;
3806 uint16_t idx, shift;
3810 if (reta_size != lut_size ||
3811 reta_size > ETH_RSS_RETA_SIZE_512) {
3813 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3814 reta_size, lut_size);
3818 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3820 PMD_DRV_LOG(ERR, "No memory can be allocated");
3823 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3826 for (i = 0; i < reta_size; i++) {
3827 idx = i / RTE_RETA_GROUP_SIZE;
3828 shift = i % RTE_RETA_GROUP_SIZE;
3829 if (reta_conf[idx].mask & (1ULL << shift))
3830 lut[i] = reta_conf[idx].reta[shift];
3832 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3841 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3842 struct rte_eth_rss_reta_entry64 *reta_conf,
3845 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3846 uint16_t i, lut_size = pf->hash_lut_size;
3847 uint16_t idx, shift;
3851 if (reta_size != lut_size ||
3852 reta_size > ETH_RSS_RETA_SIZE_512) {
3854 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3855 reta_size, lut_size);
3859 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3861 PMD_DRV_LOG(ERR, "No memory can be allocated");
3865 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3868 for (i = 0; i < reta_size; i++) {
3869 idx = i / RTE_RETA_GROUP_SIZE;
3870 shift = i % RTE_RETA_GROUP_SIZE;
3871 if (reta_conf[idx].mask & (1ULL << shift))
3872 reta_conf[idx].reta[shift] = lut[i];
3882 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3883 * @hw: pointer to the HW structure
3884 * @mem: pointer to mem struct to fill out
3885 * @size: size of memory requested
3886 * @alignment: what to align the allocation to
3888 enum i40e_status_code
3889 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3890 struct i40e_dma_mem *mem,
3894 const struct rte_memzone *mz = NULL;
3895 char z_name[RTE_MEMZONE_NAMESIZE];
3898 return I40E_ERR_PARAM;
3900 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3901 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3902 alignment, RTE_PGSIZE_2M);
3904 return I40E_ERR_NO_MEMORY;
3909 mem->zone = (const void *)mz;
3911 "memzone %s allocated with physical address: %"PRIu64,
3914 return I40E_SUCCESS;
3918 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3919 * @hw: pointer to the HW structure
3920 * @mem: ptr to mem struct to free
3922 enum i40e_status_code
3923 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3924 struct i40e_dma_mem *mem)
3927 return I40E_ERR_PARAM;
3930 "memzone %s to be freed with physical address: %"PRIu64,
3931 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3932 rte_memzone_free((const struct rte_memzone *)mem->zone);
3937 return I40E_SUCCESS;
3941 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3942 * @hw: pointer to the HW structure
3943 * @mem: pointer to mem struct to fill out
3944 * @size: size of memory requested
3946 enum i40e_status_code
3947 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3948 struct i40e_virt_mem *mem,
3952 return I40E_ERR_PARAM;
3955 mem->va = rte_zmalloc("i40e", size, 0);
3958 return I40E_SUCCESS;
3960 return I40E_ERR_NO_MEMORY;
3964 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3965 * @hw: pointer to the HW structure
3966 * @mem: pointer to mem struct to free
3968 enum i40e_status_code
3969 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3970 struct i40e_virt_mem *mem)
3973 return I40E_ERR_PARAM;
3978 return I40E_SUCCESS;
3982 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3984 rte_spinlock_init(&sp->spinlock);
3988 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3990 rte_spinlock_lock(&sp->spinlock);
3994 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3996 rte_spinlock_unlock(&sp->spinlock);
4000 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4006 * Get the hardware capabilities, which will be parsed
4007 * and saved into struct i40e_hw.
4010 i40e_get_cap(struct i40e_hw *hw)
4012 struct i40e_aqc_list_capabilities_element_resp *buf;
4013 uint16_t len, size = 0;
4016 /* Calculate a huge enough buff for saving response data temporarily */
4017 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4018 I40E_MAX_CAP_ELE_NUM;
4019 buf = rte_zmalloc("i40e", len, 0);
4021 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4022 return I40E_ERR_NO_MEMORY;
4025 /* Get, parse the capabilities and save it to hw */
4026 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4027 i40e_aqc_opc_list_func_capabilities, NULL);
4028 if (ret != I40E_SUCCESS)
4029 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4031 /* Free the temporary buffer after being used */
4037 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4
4038 #define QUEUE_NUM_PER_VF_ARG "queue-num-per-vf"
4039 RTE_PMD_REGISTER_PARAM_STRING(net_i40e, QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16");
4041 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4049 pf = (struct i40e_pf *)opaque;
4053 num = strtoul(value, &end, 0);
4054 if (errno != 0 || end == value || *end != 0) {
4055 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4056 "kept the value = %hu", value, pf->vf_nb_qp_max);
4060 if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4061 pf->vf_nb_qp_max = (uint16_t)num;
4063 /* here return 0 to make next valid same argument work */
4064 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4065 "power of 2 and equal or less than 16 !, Now it is "
4066 "kept the value = %hu", num, pf->vf_nb_qp_max);
4071 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4073 static const char * const valid_keys[] = {QUEUE_NUM_PER_VF_ARG, NULL};
4074 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4075 struct rte_kvargs *kvlist;
4077 /* set default queue number per VF as 4 */
4078 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4080 if (dev->device->devargs == NULL)
4083 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4087 if (rte_kvargs_count(kvlist, QUEUE_NUM_PER_VF_ARG) > 1)
4088 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4089 "the first invalid or last valid one is used !",
4090 QUEUE_NUM_PER_VF_ARG);
4092 rte_kvargs_process(kvlist, QUEUE_NUM_PER_VF_ARG,
4093 i40e_pf_parse_vf_queue_number_handler, pf);
4095 rte_kvargs_free(kvlist);
4101 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4103 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4104 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4105 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4106 uint16_t qp_count = 0, vsi_count = 0;
4108 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4109 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4113 i40e_pf_config_vf_rxq_number(dev);
4115 /* Add the parameter init for LFC */
4116 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4117 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4118 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4120 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4121 pf->max_num_vsi = hw->func_caps.num_vsis;
4122 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4123 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4125 /* FDir queue/VSI allocation */
4126 pf->fdir_qp_offset = 0;
4127 if (hw->func_caps.fd) {
4128 pf->flags |= I40E_FLAG_FDIR;
4129 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4131 pf->fdir_nb_qps = 0;
4133 qp_count += pf->fdir_nb_qps;
4136 /* LAN queue/VSI allocation */
4137 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4138 if (!hw->func_caps.rss) {
4141 pf->flags |= I40E_FLAG_RSS;
4142 if (hw->mac.type == I40E_MAC_X722)
4143 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4144 pf->lan_nb_qps = pf->lan_nb_qp_max;
4146 qp_count += pf->lan_nb_qps;
4149 /* VF queue/VSI allocation */
4150 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4151 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4152 pf->flags |= I40E_FLAG_SRIOV;
4153 pf->vf_nb_qps = pf->vf_nb_qp_max;
4154 pf->vf_num = pci_dev->max_vfs;
4156 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4157 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4162 qp_count += pf->vf_nb_qps * pf->vf_num;
4163 vsi_count += pf->vf_num;
4165 /* VMDq queue/VSI allocation */
4166 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4167 pf->vmdq_nb_qps = 0;
4168 pf->max_nb_vmdq_vsi = 0;
4169 if (hw->func_caps.vmdq) {
4170 if (qp_count < hw->func_caps.num_tx_qp &&
4171 vsi_count < hw->func_caps.num_vsis) {
4172 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4173 qp_count) / pf->vmdq_nb_qp_max;
4175 /* Limit the maximum number of VMDq vsi to the maximum
4176 * ethdev can support
4178 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4179 hw->func_caps.num_vsis - vsi_count);
4180 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4182 if (pf->max_nb_vmdq_vsi) {
4183 pf->flags |= I40E_FLAG_VMDQ;
4184 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4186 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4187 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4188 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4191 "No enough queues left for VMDq");
4194 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4197 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4198 vsi_count += pf->max_nb_vmdq_vsi;
4200 if (hw->func_caps.dcb)
4201 pf->flags |= I40E_FLAG_DCB;
4203 if (qp_count > hw->func_caps.num_tx_qp) {
4205 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4206 qp_count, hw->func_caps.num_tx_qp);
4209 if (vsi_count > hw->func_caps.num_vsis) {
4211 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4212 vsi_count, hw->func_caps.num_vsis);
4220 i40e_pf_get_switch_config(struct i40e_pf *pf)
4222 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4223 struct i40e_aqc_get_switch_config_resp *switch_config;
4224 struct i40e_aqc_switch_config_element_resp *element;
4225 uint16_t start_seid = 0, num_reported;
4228 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4229 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4230 if (!switch_config) {
4231 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4235 /* Get the switch configurations */
4236 ret = i40e_aq_get_switch_config(hw, switch_config,
4237 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4238 if (ret != I40E_SUCCESS) {
4239 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4242 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4243 if (num_reported != 1) { /* The number should be 1 */
4244 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4248 /* Parse the switch configuration elements */
4249 element = &(switch_config->element[0]);
4250 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4251 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4252 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4254 PMD_DRV_LOG(INFO, "Unknown element type");
4257 rte_free(switch_config);
4263 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4266 struct pool_entry *entry;
4268 if (pool == NULL || num == 0)
4271 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4272 if (entry == NULL) {
4273 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4277 /* queue heap initialize */
4278 pool->num_free = num;
4279 pool->num_alloc = 0;
4281 LIST_INIT(&pool->alloc_list);
4282 LIST_INIT(&pool->free_list);
4284 /* Initialize element */
4288 LIST_INSERT_HEAD(&pool->free_list, entry, next);
4293 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4295 struct pool_entry *entry, *next_entry;
4300 for (entry = LIST_FIRST(&pool->alloc_list);
4301 entry && (next_entry = LIST_NEXT(entry, next), 1);
4302 entry = next_entry) {
4303 LIST_REMOVE(entry, next);
4307 for (entry = LIST_FIRST(&pool->free_list);
4308 entry && (next_entry = LIST_NEXT(entry, next), 1);
4309 entry = next_entry) {
4310 LIST_REMOVE(entry, next);
4315 pool->num_alloc = 0;
4317 LIST_INIT(&pool->alloc_list);
4318 LIST_INIT(&pool->free_list);
4322 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4325 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4326 uint32_t pool_offset;
4330 PMD_DRV_LOG(ERR, "Invalid parameter");
4334 pool_offset = base - pool->base;
4335 /* Lookup in alloc list */
4336 LIST_FOREACH(entry, &pool->alloc_list, next) {
4337 if (entry->base == pool_offset) {
4338 valid_entry = entry;
4339 LIST_REMOVE(entry, next);
4344 /* Not find, return */
4345 if (valid_entry == NULL) {
4346 PMD_DRV_LOG(ERR, "Failed to find entry");
4351 * Found it, move it to free list and try to merge.
4352 * In order to make merge easier, always sort it by qbase.
4353 * Find adjacent prev and last entries.
4356 LIST_FOREACH(entry, &pool->free_list, next) {
4357 if (entry->base > valid_entry->base) {
4365 /* Try to merge with next one*/
4367 /* Merge with next one */
4368 if (valid_entry->base + valid_entry->len == next->base) {
4369 next->base = valid_entry->base;
4370 next->len += valid_entry->len;
4371 rte_free(valid_entry);
4378 /* Merge with previous one */
4379 if (prev->base + prev->len == valid_entry->base) {
4380 prev->len += valid_entry->len;
4381 /* If it merge with next one, remove next node */
4383 LIST_REMOVE(valid_entry, next);
4384 rte_free(valid_entry);
4386 rte_free(valid_entry);
4392 /* Not find any entry to merge, insert */
4395 LIST_INSERT_AFTER(prev, valid_entry, next);
4396 else if (next != NULL)
4397 LIST_INSERT_BEFORE(next, valid_entry, next);
4398 else /* It's empty list, insert to head */
4399 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4402 pool->num_free += valid_entry->len;
4403 pool->num_alloc -= valid_entry->len;
4409 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4412 struct pool_entry *entry, *valid_entry;
4414 if (pool == NULL || num == 0) {
4415 PMD_DRV_LOG(ERR, "Invalid parameter");
4419 if (pool->num_free < num) {
4420 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4421 num, pool->num_free);
4426 /* Lookup in free list and find most fit one */
4427 LIST_FOREACH(entry, &pool->free_list, next) {
4428 if (entry->len >= num) {
4430 if (entry->len == num) {
4431 valid_entry = entry;
4434 if (valid_entry == NULL || valid_entry->len > entry->len)
4435 valid_entry = entry;
4439 /* Not find one to satisfy the request, return */
4440 if (valid_entry == NULL) {
4441 PMD_DRV_LOG(ERR, "No valid entry found");
4445 * The entry have equal queue number as requested,
4446 * remove it from alloc_list.
4448 if (valid_entry->len == num) {
4449 LIST_REMOVE(valid_entry, next);
4452 * The entry have more numbers than requested,
4453 * create a new entry for alloc_list and minus its
4454 * queue base and number in free_list.
4456 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4457 if (entry == NULL) {
4459 "Failed to allocate memory for resource pool");
4462 entry->base = valid_entry->base;
4464 valid_entry->base += num;
4465 valid_entry->len -= num;
4466 valid_entry = entry;
4469 /* Insert it into alloc list, not sorted */
4470 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4472 pool->num_free -= valid_entry->len;
4473 pool->num_alloc += valid_entry->len;
4475 return valid_entry->base + pool->base;
4479 * bitmap_is_subset - Check whether src2 is subset of src1
4482 bitmap_is_subset(uint8_t src1, uint8_t src2)
4484 return !((src1 ^ src2) & src2);
4487 static enum i40e_status_code
4488 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4490 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4492 /* If DCB is not supported, only default TC is supported */
4493 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4494 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4495 return I40E_NOT_SUPPORTED;
4498 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4500 "Enabled TC map 0x%x not applicable to HW support 0x%x",
4501 hw->func_caps.enabled_tcmap, enabled_tcmap);
4502 return I40E_NOT_SUPPORTED;
4504 return I40E_SUCCESS;
4508 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4509 struct i40e_vsi_vlan_pvid_info *info)
4512 struct i40e_vsi_context ctxt;
4513 uint8_t vlan_flags = 0;
4516 if (vsi == NULL || info == NULL) {
4517 PMD_DRV_LOG(ERR, "invalid parameters");
4518 return I40E_ERR_PARAM;
4522 vsi->info.pvid = info->config.pvid;
4524 * If insert pvid is enabled, only tagged pkts are
4525 * allowed to be sent out.
4527 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4528 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4531 if (info->config.reject.tagged == 0)
4532 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4534 if (info->config.reject.untagged == 0)
4535 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4537 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4538 I40E_AQ_VSI_PVLAN_MODE_MASK);
4539 vsi->info.port_vlan_flags |= vlan_flags;
4540 vsi->info.valid_sections =
4541 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4542 memset(&ctxt, 0, sizeof(ctxt));
4543 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4544 ctxt.seid = vsi->seid;
4546 hw = I40E_VSI_TO_HW(vsi);
4547 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4548 if (ret != I40E_SUCCESS)
4549 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4555 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4557 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4559 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4561 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4562 if (ret != I40E_SUCCESS)
4566 PMD_DRV_LOG(ERR, "seid not valid");
4570 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4571 tc_bw_data.tc_valid_bits = enabled_tcmap;
4572 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4573 tc_bw_data.tc_bw_credits[i] =
4574 (enabled_tcmap & (1 << i)) ? 1 : 0;
4576 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4577 if (ret != I40E_SUCCESS) {
4578 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4582 rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4583 sizeof(vsi->info.qs_handle));
4584 return I40E_SUCCESS;
4587 static enum i40e_status_code
4588 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4589 struct i40e_aqc_vsi_properties_data *info,
4590 uint8_t enabled_tcmap)
4592 enum i40e_status_code ret;
4593 int i, total_tc = 0;
4594 uint16_t qpnum_per_tc, bsf, qp_idx;
4596 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4597 if (ret != I40E_SUCCESS)
4600 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4601 if (enabled_tcmap & (1 << i))
4605 vsi->enabled_tc = enabled_tcmap;
4607 /* Number of queues per enabled TC */
4608 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4609 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4610 bsf = rte_bsf32(qpnum_per_tc);
4612 /* Adjust the queue number to actual queues that can be applied */
4613 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4614 vsi->nb_qps = qpnum_per_tc * total_tc;
4617 * Configure TC and queue mapping parameters, for enabled TC,
4618 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4619 * default queue will serve it.
4622 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4623 if (vsi->enabled_tc & (1 << i)) {
4624 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4625 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4626 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4627 qp_idx += qpnum_per_tc;
4629 info->tc_mapping[i] = 0;
4632 /* Associate queue number with VSI */
4633 if (vsi->type == I40E_VSI_SRIOV) {
4634 info->mapping_flags |=
4635 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4636 for (i = 0; i < vsi->nb_qps; i++)
4637 info->queue_mapping[i] =
4638 rte_cpu_to_le_16(vsi->base_queue + i);
4640 info->mapping_flags |=
4641 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4642 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4644 info->valid_sections |=
4645 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4647 return I40E_SUCCESS;
4651 i40e_veb_release(struct i40e_veb *veb)
4653 struct i40e_vsi *vsi;
4659 if (!TAILQ_EMPTY(&veb->head)) {
4660 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4663 /* associate_vsi field is NULL for floating VEB */
4664 if (veb->associate_vsi != NULL) {
4665 vsi = veb->associate_vsi;
4666 hw = I40E_VSI_TO_HW(vsi);
4668 vsi->uplink_seid = veb->uplink_seid;
4671 veb->associate_pf->main_vsi->floating_veb = NULL;
4672 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4675 i40e_aq_delete_element(hw, veb->seid, NULL);
4677 return I40E_SUCCESS;
4681 static struct i40e_veb *
4682 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4684 struct i40e_veb *veb;
4690 "veb setup failed, associated PF shouldn't null");
4693 hw = I40E_PF_TO_HW(pf);
4695 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4697 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4701 veb->associate_vsi = vsi;
4702 veb->associate_pf = pf;
4703 TAILQ_INIT(&veb->head);
4704 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4706 /* create floating veb if vsi is NULL */
4708 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4709 I40E_DEFAULT_TCMAP, false,
4710 &veb->seid, false, NULL);
4712 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4713 true, &veb->seid, false, NULL);
4716 if (ret != I40E_SUCCESS) {
4717 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4718 hw->aq.asq_last_status);
4721 veb->enabled_tc = I40E_DEFAULT_TCMAP;
4723 /* get statistics index */
4724 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4725 &veb->stats_idx, NULL, NULL, NULL);
4726 if (ret != I40E_SUCCESS) {
4727 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4728 hw->aq.asq_last_status);
4731 /* Get VEB bandwidth, to be implemented */
4732 /* Now associated vsi binding to the VEB, set uplink to this VEB */
4734 vsi->uplink_seid = veb->seid;
4743 i40e_vsi_release(struct i40e_vsi *vsi)
4747 struct i40e_vsi_list *vsi_list;
4750 struct i40e_mac_filter *f;
4751 uint16_t user_param;
4754 return I40E_SUCCESS;
4759 user_param = vsi->user_param;
4761 pf = I40E_VSI_TO_PF(vsi);
4762 hw = I40E_VSI_TO_HW(vsi);
4764 /* VSI has child to attach, release child first */
4766 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4767 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4770 i40e_veb_release(vsi->veb);
4773 if (vsi->floating_veb) {
4774 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4775 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4780 /* Remove all macvlan filters of the VSI */
4781 i40e_vsi_remove_all_macvlan_filter(vsi);
4782 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4785 if (vsi->type != I40E_VSI_MAIN &&
4786 ((vsi->type != I40E_VSI_SRIOV) ||
4787 !pf->floating_veb_list[user_param])) {
4788 /* Remove vsi from parent's sibling list */
4789 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4790 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4791 return I40E_ERR_PARAM;
4793 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4794 &vsi->sib_vsi_list, list);
4796 /* Remove all switch element of the VSI */
4797 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4798 if (ret != I40E_SUCCESS)
4799 PMD_DRV_LOG(ERR, "Failed to delete element");
4802 if ((vsi->type == I40E_VSI_SRIOV) &&
4803 pf->floating_veb_list[user_param]) {
4804 /* Remove vsi from parent's sibling list */
4805 if (vsi->parent_vsi == NULL ||
4806 vsi->parent_vsi->floating_veb == NULL) {
4807 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4808 return I40E_ERR_PARAM;
4810 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4811 &vsi->sib_vsi_list, list);
4813 /* Remove all switch element of the VSI */
4814 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4815 if (ret != I40E_SUCCESS)
4816 PMD_DRV_LOG(ERR, "Failed to delete element");
4819 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4821 if (vsi->type != I40E_VSI_SRIOV)
4822 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4825 return I40E_SUCCESS;
4829 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4831 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4832 struct i40e_aqc_remove_macvlan_element_data def_filter;
4833 struct i40e_mac_filter_info filter;
4836 if (vsi->type != I40E_VSI_MAIN)
4837 return I40E_ERR_CONFIG;
4838 memset(&def_filter, 0, sizeof(def_filter));
4839 rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4841 def_filter.vlan_tag = 0;
4842 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4843 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4844 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4845 if (ret != I40E_SUCCESS) {
4846 struct i40e_mac_filter *f;
4847 struct ether_addr *mac;
4850 "Cannot remove the default macvlan filter");
4851 /* It needs to add the permanent mac into mac list */
4852 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4854 PMD_DRV_LOG(ERR, "failed to allocate memory");
4855 return I40E_ERR_NO_MEMORY;
4857 mac = &f->mac_info.mac_addr;
4858 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4860 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4861 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4866 rte_memcpy(&filter.mac_addr,
4867 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4868 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4869 return i40e_vsi_add_mac(vsi, &filter);
4873 * i40e_vsi_get_bw_config - Query VSI BW Information
4874 * @vsi: the VSI to be queried
4876 * Returns 0 on success, negative value on failure
4878 static enum i40e_status_code
4879 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4881 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4882 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4883 struct i40e_hw *hw = &vsi->adapter->hw;
4888 memset(&bw_config, 0, sizeof(bw_config));
4889 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4890 if (ret != I40E_SUCCESS) {
4891 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4892 hw->aq.asq_last_status);
4896 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4897 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4898 &ets_sla_config, NULL);
4899 if (ret != I40E_SUCCESS) {
4901 "VSI failed to get TC bandwdith configuration %u",
4902 hw->aq.asq_last_status);
4906 /* store and print out BW info */
4907 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4908 vsi->bw_info.bw_max = bw_config.max_bw;
4909 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4910 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4911 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4912 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4914 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4915 vsi->bw_info.bw_ets_share_credits[i] =
4916 ets_sla_config.share_credits[i];
4917 vsi->bw_info.bw_ets_credits[i] =
4918 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4919 /* 4 bits per TC, 4th bit is reserved */
4920 vsi->bw_info.bw_ets_max[i] =
4921 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4922 RTE_LEN2MASK(3, uint8_t));
4923 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4924 vsi->bw_info.bw_ets_share_credits[i]);
4925 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4926 vsi->bw_info.bw_ets_credits[i]);
4927 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4928 vsi->bw_info.bw_ets_max[i]);
4931 return I40E_SUCCESS;
4934 /* i40e_enable_pf_lb
4935 * @pf: pointer to the pf structure
4937 * allow loopback on pf
4940 i40e_enable_pf_lb(struct i40e_pf *pf)
4942 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4943 struct i40e_vsi_context ctxt;
4946 /* Use the FW API if FW >= v5.0 */
4947 if (hw->aq.fw_maj_ver < 5) {
4948 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4952 memset(&ctxt, 0, sizeof(ctxt));
4953 ctxt.seid = pf->main_vsi_seid;
4954 ctxt.pf_num = hw->pf_id;
4955 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4957 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4958 ret, hw->aq.asq_last_status);
4961 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4962 ctxt.info.valid_sections =
4963 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4964 ctxt.info.switch_id |=
4965 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4967 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4969 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4970 hw->aq.asq_last_status);
4975 i40e_vsi_setup(struct i40e_pf *pf,
4976 enum i40e_vsi_type type,
4977 struct i40e_vsi *uplink_vsi,
4978 uint16_t user_param)
4980 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4981 struct i40e_vsi *vsi;
4982 struct i40e_mac_filter_info filter;
4984 struct i40e_vsi_context ctxt;
4985 struct ether_addr broadcast =
4986 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4988 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4989 uplink_vsi == NULL) {
4991 "VSI setup failed, VSI link shouldn't be NULL");
4995 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4997 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5002 * 1.type is not MAIN and uplink vsi is not NULL
5003 * If uplink vsi didn't setup VEB, create one first under veb field
5004 * 2.type is SRIOV and the uplink is NULL
5005 * If floating VEB is NULL, create one veb under floating veb field
5008 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5009 uplink_vsi->veb == NULL) {
5010 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5012 if (uplink_vsi->veb == NULL) {
5013 PMD_DRV_LOG(ERR, "VEB setup failed");
5016 /* set ALLOWLOOPBACk on pf, when veb is created */
5017 i40e_enable_pf_lb(pf);
5020 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5021 pf->main_vsi->floating_veb == NULL) {
5022 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5024 if (pf->main_vsi->floating_veb == NULL) {
5025 PMD_DRV_LOG(ERR, "VEB setup failed");
5030 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5032 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5035 TAILQ_INIT(&vsi->mac_list);
5037 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5038 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5039 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5040 vsi->user_param = user_param;
5041 vsi->vlan_anti_spoof_on = 0;
5042 vsi->vlan_filter_on = 0;
5043 /* Allocate queues */
5044 switch (vsi->type) {
5045 case I40E_VSI_MAIN :
5046 vsi->nb_qps = pf->lan_nb_qps;
5048 case I40E_VSI_SRIOV :
5049 vsi->nb_qps = pf->vf_nb_qps;
5051 case I40E_VSI_VMDQ2:
5052 vsi->nb_qps = pf->vmdq_nb_qps;
5055 vsi->nb_qps = pf->fdir_nb_qps;
5061 * The filter status descriptor is reported in rx queue 0,
5062 * while the tx queue for fdir filter programming has no
5063 * such constraints, can be non-zero queues.
5064 * To simplify it, choose FDIR vsi use queue 0 pair.
5065 * To make sure it will use queue 0 pair, queue allocation
5066 * need be done before this function is called
5068 if (type != I40E_VSI_FDIR) {
5069 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5071 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5075 vsi->base_queue = ret;
5077 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5079 /* VF has MSIX interrupt in VF range, don't allocate here */
5080 if (type == I40E_VSI_MAIN) {
5081 ret = i40e_res_pool_alloc(&pf->msix_pool,
5082 RTE_MIN(vsi->nb_qps,
5083 RTE_MAX_RXTX_INTR_VEC_ID));
5085 PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
5087 goto fail_queue_alloc;
5089 vsi->msix_intr = ret;
5090 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
5091 } else if (type != I40E_VSI_SRIOV) {
5092 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5094 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5095 goto fail_queue_alloc;
5097 vsi->msix_intr = ret;
5105 if (type == I40E_VSI_MAIN) {
5106 /* For main VSI, no need to add since it's default one */
5107 vsi->uplink_seid = pf->mac_seid;
5108 vsi->seid = pf->main_vsi_seid;
5109 /* Bind queues with specific MSIX interrupt */
5111 * Needs 2 interrupt at least, one for misc cause which will
5112 * enabled from OS side, Another for queues binding the
5113 * interrupt from device side only.
5116 /* Get default VSI parameters from hardware */
5117 memset(&ctxt, 0, sizeof(ctxt));
5118 ctxt.seid = vsi->seid;
5119 ctxt.pf_num = hw->pf_id;
5120 ctxt.uplink_seid = vsi->uplink_seid;
5122 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5123 if (ret != I40E_SUCCESS) {
5124 PMD_DRV_LOG(ERR, "Failed to get VSI params");
5125 goto fail_msix_alloc;
5127 rte_memcpy(&vsi->info, &ctxt.info,
5128 sizeof(struct i40e_aqc_vsi_properties_data));
5129 vsi->vsi_id = ctxt.vsi_number;
5130 vsi->info.valid_sections = 0;
5132 /* Configure tc, enabled TC0 only */
5133 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5135 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5136 goto fail_msix_alloc;
5139 /* TC, queue mapping */
5140 memset(&ctxt, 0, sizeof(ctxt));
5141 vsi->info.valid_sections |=
5142 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5143 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5144 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5145 rte_memcpy(&ctxt.info, &vsi->info,
5146 sizeof(struct i40e_aqc_vsi_properties_data));
5147 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5148 I40E_DEFAULT_TCMAP);
5149 if (ret != I40E_SUCCESS) {
5151 "Failed to configure TC queue mapping");
5152 goto fail_msix_alloc;
5154 ctxt.seid = vsi->seid;
5155 ctxt.pf_num = hw->pf_id;
5156 ctxt.uplink_seid = vsi->uplink_seid;
5159 /* Update VSI parameters */
5160 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5161 if (ret != I40E_SUCCESS) {
5162 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5163 goto fail_msix_alloc;
5166 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5167 sizeof(vsi->info.tc_mapping));
5168 rte_memcpy(&vsi->info.queue_mapping,
5169 &ctxt.info.queue_mapping,
5170 sizeof(vsi->info.queue_mapping));
5171 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5172 vsi->info.valid_sections = 0;
5174 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5178 * Updating default filter settings are necessary to prevent
5179 * reception of tagged packets.
5180 * Some old firmware configurations load a default macvlan
5181 * filter which accepts both tagged and untagged packets.
5182 * The updating is to use a normal filter instead if needed.
5183 * For NVM 4.2.2 or after, the updating is not needed anymore.
5184 * The firmware with correct configurations load the default
5185 * macvlan filter which is expected and cannot be removed.
5187 i40e_update_default_filter_setting(vsi);
5188 i40e_config_qinq(hw, vsi);
5189 } else if (type == I40E_VSI_SRIOV) {
5190 memset(&ctxt, 0, sizeof(ctxt));
5192 * For other VSI, the uplink_seid equals to uplink VSI's
5193 * uplink_seid since they share same VEB
5195 if (uplink_vsi == NULL)
5196 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5198 vsi->uplink_seid = uplink_vsi->uplink_seid;
5199 ctxt.pf_num = hw->pf_id;
5200 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5201 ctxt.uplink_seid = vsi->uplink_seid;
5202 ctxt.connection_type = 0x1;
5203 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5205 /* Use the VEB configuration if FW >= v5.0 */
5206 if (hw->aq.fw_maj_ver >= 5) {
5207 /* Configure switch ID */
5208 ctxt.info.valid_sections |=
5209 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5210 ctxt.info.switch_id =
5211 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5214 /* Configure port/vlan */
5215 ctxt.info.valid_sections |=
5216 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5217 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5218 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5219 hw->func_caps.enabled_tcmap);
5220 if (ret != I40E_SUCCESS) {
5222 "Failed to configure TC queue mapping");
5223 goto fail_msix_alloc;
5226 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5227 ctxt.info.valid_sections |=
5228 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5230 * Since VSI is not created yet, only configure parameter,
5231 * will add vsi below.
5234 i40e_config_qinq(hw, vsi);
5235 } else if (type == I40E_VSI_VMDQ2) {
5236 memset(&ctxt, 0, sizeof(ctxt));
5238 * For other VSI, the uplink_seid equals to uplink VSI's
5239 * uplink_seid since they share same VEB
5241 vsi->uplink_seid = uplink_vsi->uplink_seid;
5242 ctxt.pf_num = hw->pf_id;
5244 ctxt.uplink_seid = vsi->uplink_seid;
5245 ctxt.connection_type = 0x1;
5246 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5248 ctxt.info.valid_sections |=
5249 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5250 /* user_param carries flag to enable loop back */
5252 ctxt.info.switch_id =
5253 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5254 ctxt.info.switch_id |=
5255 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5258 /* Configure port/vlan */
5259 ctxt.info.valid_sections |=
5260 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5261 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5262 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5263 I40E_DEFAULT_TCMAP);
5264 if (ret != I40E_SUCCESS) {
5266 "Failed to configure TC queue mapping");
5267 goto fail_msix_alloc;
5269 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5270 ctxt.info.valid_sections |=
5271 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5272 } else if (type == I40E_VSI_FDIR) {
5273 memset(&ctxt, 0, sizeof(ctxt));
5274 vsi->uplink_seid = uplink_vsi->uplink_seid;
5275 ctxt.pf_num = hw->pf_id;
5277 ctxt.uplink_seid = vsi->uplink_seid;
5278 ctxt.connection_type = 0x1; /* regular data port */
5279 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5280 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5281 I40E_DEFAULT_TCMAP);
5282 if (ret != I40E_SUCCESS) {
5284 "Failed to configure TC queue mapping.");
5285 goto fail_msix_alloc;
5287 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5288 ctxt.info.valid_sections |=
5289 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5291 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5292 goto fail_msix_alloc;
5295 if (vsi->type != I40E_VSI_MAIN) {
5296 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5297 if (ret != I40E_SUCCESS) {
5298 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5299 hw->aq.asq_last_status);
5300 goto fail_msix_alloc;
5302 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5303 vsi->info.valid_sections = 0;
5304 vsi->seid = ctxt.seid;
5305 vsi->vsi_id = ctxt.vsi_number;
5306 vsi->sib_vsi_list.vsi = vsi;
5307 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5308 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5309 &vsi->sib_vsi_list, list);
5311 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5312 &vsi->sib_vsi_list, list);
5316 /* MAC/VLAN configuration */
5317 rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5318 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5320 ret = i40e_vsi_add_mac(vsi, &filter);
5321 if (ret != I40E_SUCCESS) {
5322 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5323 goto fail_msix_alloc;
5326 /* Get VSI BW information */
5327 i40e_vsi_get_bw_config(vsi);
5330 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5332 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5338 /* Configure vlan filter on or off */
5340 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5343 struct i40e_mac_filter *f;
5345 struct i40e_mac_filter_info *mac_filter;
5346 enum rte_mac_filter_type desired_filter;
5347 int ret = I40E_SUCCESS;
5350 /* Filter to match MAC and VLAN */
5351 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5353 /* Filter to match only MAC */
5354 desired_filter = RTE_MAC_PERFECT_MATCH;
5359 mac_filter = rte_zmalloc("mac_filter_info_data",
5360 num * sizeof(*mac_filter), 0);
5361 if (mac_filter == NULL) {
5362 PMD_DRV_LOG(ERR, "failed to allocate memory");
5363 return I40E_ERR_NO_MEMORY;
5368 /* Remove all existing mac */
5369 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5370 mac_filter[i] = f->mac_info;
5371 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5373 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5374 on ? "enable" : "disable");
5380 /* Override with new filter */
5381 for (i = 0; i < num; i++) {
5382 mac_filter[i].filter_type = desired_filter;
5383 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5385 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5386 on ? "enable" : "disable");
5392 rte_free(mac_filter);
5396 /* Configure vlan stripping on or off */
5398 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5400 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5401 struct i40e_vsi_context ctxt;
5403 int ret = I40E_SUCCESS;
5405 /* Check if it has been already on or off */
5406 if (vsi->info.valid_sections &
5407 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5409 if ((vsi->info.port_vlan_flags &
5410 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5411 return 0; /* already on */
5413 if ((vsi->info.port_vlan_flags &
5414 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5415 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5416 return 0; /* already off */
5421 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5423 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5424 vsi->info.valid_sections =
5425 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5426 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5427 vsi->info.port_vlan_flags |= vlan_flags;
5428 ctxt.seid = vsi->seid;
5429 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5430 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5432 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5433 on ? "enable" : "disable");
5439 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5441 struct rte_eth_dev_data *data = dev->data;
5445 /* Apply vlan offload setting */
5446 mask = ETH_VLAN_STRIP_MASK |
5447 ETH_VLAN_FILTER_MASK |
5448 ETH_VLAN_EXTEND_MASK;
5449 ret = i40e_vlan_offload_set(dev, mask);
5451 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5455 /* Apply pvid setting */
5456 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5457 data->dev_conf.txmode.hw_vlan_insert_pvid);
5459 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5465 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5467 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5469 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5473 i40e_update_flow_control(struct i40e_hw *hw)
5475 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5476 struct i40e_link_status link_status;
5477 uint32_t rxfc = 0, txfc = 0, reg;
5481 memset(&link_status, 0, sizeof(link_status));
5482 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5483 if (ret != I40E_SUCCESS) {
5484 PMD_DRV_LOG(ERR, "Failed to get link status information");
5485 goto write_reg; /* Disable flow control */
5488 an_info = hw->phy.link_info.an_info;
5489 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5490 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5491 ret = I40E_ERR_NOT_READY;
5492 goto write_reg; /* Disable flow control */
5495 * If link auto negotiation is enabled, flow control needs to
5496 * be configured according to it
5498 switch (an_info & I40E_LINK_PAUSE_RXTX) {
5499 case I40E_LINK_PAUSE_RXTX:
5502 hw->fc.current_mode = I40E_FC_FULL;
5504 case I40E_AQ_LINK_PAUSE_RX:
5506 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5508 case I40E_AQ_LINK_PAUSE_TX:
5510 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5513 hw->fc.current_mode = I40E_FC_NONE;
5518 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5519 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5520 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5521 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5522 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5523 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5530 i40e_pf_setup(struct i40e_pf *pf)
5532 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5533 struct i40e_filter_control_settings settings;
5534 struct i40e_vsi *vsi;
5537 /* Clear all stats counters */
5538 pf->offset_loaded = FALSE;
5539 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5540 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5541 memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5542 memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5544 ret = i40e_pf_get_switch_config(pf);
5545 if (ret != I40E_SUCCESS) {
5546 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5549 if (pf->flags & I40E_FLAG_FDIR) {
5550 /* make queue allocated first, let FDIR use queue pair 0*/
5551 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5552 if (ret != I40E_FDIR_QUEUE_ID) {
5554 "queue allocation fails for FDIR: ret =%d",
5556 pf->flags &= ~I40E_FLAG_FDIR;
5559 /* main VSI setup */
5560 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5562 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5563 return I40E_ERR_NOT_READY;
5567 /* Configure filter control */
5568 memset(&settings, 0, sizeof(settings));
5569 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5570 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5571 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5572 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5574 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5575 hw->func_caps.rss_table_size);
5576 return I40E_ERR_PARAM;
5578 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5579 hw->func_caps.rss_table_size);
5580 pf->hash_lut_size = hw->func_caps.rss_table_size;
5582 /* Enable ethtype and macvlan filters */
5583 settings.enable_ethtype = TRUE;
5584 settings.enable_macvlan = TRUE;
5585 ret = i40e_set_filter_control(hw, &settings);
5587 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5590 /* Update flow control according to the auto negotiation */
5591 i40e_update_flow_control(hw);
5593 return I40E_SUCCESS;
5597 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5603 * Set or clear TX Queue Disable flags,
5604 * which is required by hardware.
5606 i40e_pre_tx_queue_cfg(hw, q_idx, on);
5607 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5609 /* Wait until the request is finished */
5610 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5611 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5612 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5613 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5614 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5620 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5621 return I40E_SUCCESS; /* already on, skip next steps */
5623 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5624 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5626 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5627 return I40E_SUCCESS; /* already off, skip next steps */
5628 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5630 /* Write the register */
5631 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5632 /* Check the result */
5633 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5634 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5635 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5637 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5638 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5641 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5642 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5646 /* Check if it is timeout */
5647 if (j >= I40E_CHK_Q_ENA_COUNT) {
5648 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5649 (on ? "enable" : "disable"), q_idx);
5650 return I40E_ERR_TIMEOUT;
5653 return I40E_SUCCESS;
5656 /* Swith on or off the tx queues */
5658 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5660 struct rte_eth_dev_data *dev_data = pf->dev_data;
5661 struct i40e_tx_queue *txq;
5662 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5666 for (i = 0; i < dev_data->nb_tx_queues; i++) {
5667 txq = dev_data->tx_queues[i];
5668 /* Don't operate the queue if not configured or
5669 * if starting only per queue */
5670 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5673 ret = i40e_dev_tx_queue_start(dev, i);
5675 ret = i40e_dev_tx_queue_stop(dev, i);
5676 if ( ret != I40E_SUCCESS)
5680 return I40E_SUCCESS;
5684 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5689 /* Wait until the request is finished */
5690 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5691 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5692 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5693 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5694 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5699 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5700 return I40E_SUCCESS; /* Already on, skip next steps */
5701 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5703 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5704 return I40E_SUCCESS; /* Already off, skip next steps */
5705 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5708 /* Write the register */
5709 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5710 /* Check the result */
5711 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5712 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5713 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5715 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5716 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5719 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5720 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5725 /* Check if it is timeout */
5726 if (j >= I40E_CHK_Q_ENA_COUNT) {
5727 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5728 (on ? "enable" : "disable"), q_idx);
5729 return I40E_ERR_TIMEOUT;
5732 return I40E_SUCCESS;
5734 /* Switch on or off the rx queues */
5736 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5738 struct rte_eth_dev_data *dev_data = pf->dev_data;
5739 struct i40e_rx_queue *rxq;
5740 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5744 for (i = 0; i < dev_data->nb_rx_queues; i++) {
5745 rxq = dev_data->rx_queues[i];
5746 /* Don't operate the queue if not configured or
5747 * if starting only per queue */
5748 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5751 ret = i40e_dev_rx_queue_start(dev, i);
5753 ret = i40e_dev_rx_queue_stop(dev, i);
5754 if (ret != I40E_SUCCESS)
5758 return I40E_SUCCESS;
5761 /* Switch on or off all the rx/tx queues */
5763 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5768 /* enable rx queues before enabling tx queues */
5769 ret = i40e_dev_switch_rx_queues(pf, on);
5771 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5774 ret = i40e_dev_switch_tx_queues(pf, on);
5776 /* Stop tx queues before stopping rx queues */
5777 ret = i40e_dev_switch_tx_queues(pf, on);
5779 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5782 ret = i40e_dev_switch_rx_queues(pf, on);
5788 /* Initialize VSI for TX */
5790 i40e_dev_tx_init(struct i40e_pf *pf)
5792 struct rte_eth_dev_data *data = pf->dev_data;
5794 uint32_t ret = I40E_SUCCESS;
5795 struct i40e_tx_queue *txq;
5797 for (i = 0; i < data->nb_tx_queues; i++) {
5798 txq = data->tx_queues[i];
5799 if (!txq || !txq->q_set)
5801 ret = i40e_tx_queue_init(txq);
5802 if (ret != I40E_SUCCESS)
5805 if (ret == I40E_SUCCESS)
5806 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5812 /* Initialize VSI for RX */
5814 i40e_dev_rx_init(struct i40e_pf *pf)
5816 struct rte_eth_dev_data *data = pf->dev_data;
5817 int ret = I40E_SUCCESS;
5819 struct i40e_rx_queue *rxq;
5821 i40e_pf_config_mq_rx(pf);
5822 for (i = 0; i < data->nb_rx_queues; i++) {
5823 rxq = data->rx_queues[i];
5824 if (!rxq || !rxq->q_set)
5827 ret = i40e_rx_queue_init(rxq);
5828 if (ret != I40E_SUCCESS) {
5830 "Failed to do RX queue initialization");
5834 if (ret == I40E_SUCCESS)
5835 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5842 i40e_dev_rxtx_init(struct i40e_pf *pf)
5846 err = i40e_dev_tx_init(pf);
5848 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5851 err = i40e_dev_rx_init(pf);
5853 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5861 i40e_vmdq_setup(struct rte_eth_dev *dev)
5863 struct rte_eth_conf *conf = &dev->data->dev_conf;
5864 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5865 int i, err, conf_vsis, j, loop;
5866 struct i40e_vsi *vsi;
5867 struct i40e_vmdq_info *vmdq_info;
5868 struct rte_eth_vmdq_rx_conf *vmdq_conf;
5869 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5872 * Disable interrupt to avoid message from VF. Furthermore, it will
5873 * avoid race condition in VSI creation/destroy.
5875 i40e_pf_disable_irq0(hw);
5877 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5878 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5882 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5883 if (conf_vsis > pf->max_nb_vmdq_vsi) {
5884 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5885 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5886 pf->max_nb_vmdq_vsi);
5890 if (pf->vmdq != NULL) {
5891 PMD_INIT_LOG(INFO, "VMDQ already configured");
5895 pf->vmdq = rte_zmalloc("vmdq_info_struct",
5896 sizeof(*vmdq_info) * conf_vsis, 0);
5898 if (pf->vmdq == NULL) {
5899 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5903 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5905 /* Create VMDQ VSI */
5906 for (i = 0; i < conf_vsis; i++) {
5907 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5908 vmdq_conf->enable_loop_back);
5910 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5914 vmdq_info = &pf->vmdq[i];
5916 vmdq_info->vsi = vsi;
5918 pf->nb_cfg_vmdq_vsi = conf_vsis;
5920 /* Configure Vlan */
5921 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5922 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5923 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5924 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5925 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5926 vmdq_conf->pool_map[i].vlan_id, j);
5928 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5929 vmdq_conf->pool_map[i].vlan_id);
5931 PMD_INIT_LOG(ERR, "Failed to add vlan");
5939 i40e_pf_enable_irq0(hw);
5944 for (i = 0; i < conf_vsis; i++)
5945 if (pf->vmdq[i].vsi == NULL)
5948 i40e_vsi_release(pf->vmdq[i].vsi);
5952 i40e_pf_enable_irq0(hw);
5957 i40e_stat_update_32(struct i40e_hw *hw,
5965 new_data = (uint64_t)I40E_READ_REG(hw, reg);
5969 if (new_data >= *offset)
5970 *stat = (uint64_t)(new_data - *offset);
5972 *stat = (uint64_t)((new_data +
5973 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5977 i40e_stat_update_48(struct i40e_hw *hw,
5986 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5987 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5988 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5993 if (new_data >= *offset)
5994 *stat = new_data - *offset;
5996 *stat = (uint64_t)((new_data +
5997 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5999 *stat &= I40E_48_BIT_MASK;
6004 i40e_pf_disable_irq0(struct i40e_hw *hw)
6006 /* Disable all interrupt types */
6007 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
6008 I40E_WRITE_FLUSH(hw);
6013 i40e_pf_enable_irq0(struct i40e_hw *hw)
6015 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6016 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6017 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6018 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6019 I40E_WRITE_FLUSH(hw);
6023 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6025 /* read pending request and disable first */
6026 i40e_pf_disable_irq0(hw);
6027 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6028 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6029 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6032 /* Link no queues with irq0 */
6033 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6034 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6038 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6040 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6041 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6044 uint32_t index, offset, val;
6049 * Try to find which VF trigger a reset, use absolute VF id to access
6050 * since the reg is global register.
6052 for (i = 0; i < pf->vf_num; i++) {
6053 abs_vf_id = hw->func_caps.vf_base_id + i;
6054 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6055 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6056 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6057 /* VFR event occurred */
6058 if (val & (0x1 << offset)) {
6061 /* Clear the event first */
6062 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6064 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6066 * Only notify a VF reset event occurred,
6067 * don't trigger another SW reset
6069 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6070 if (ret != I40E_SUCCESS)
6071 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6077 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6079 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6082 for (i = 0; i < pf->vf_num; i++)
6083 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6087 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6089 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6090 struct i40e_arq_event_info info;
6091 uint16_t pending, opcode;
6094 info.buf_len = I40E_AQ_BUF_SZ;
6095 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6096 if (!info.msg_buf) {
6097 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6103 ret = i40e_clean_arq_element(hw, &info, &pending);
6105 if (ret != I40E_SUCCESS) {
6107 "Failed to read msg from AdminQ, aq_err: %u",
6108 hw->aq.asq_last_status);
6111 opcode = rte_le_to_cpu_16(info.desc.opcode);
6114 case i40e_aqc_opc_send_msg_to_pf:
6115 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6116 i40e_pf_host_handle_vf_msg(dev,
6117 rte_le_to_cpu_16(info.desc.retval),
6118 rte_le_to_cpu_32(info.desc.cookie_high),
6119 rte_le_to_cpu_32(info.desc.cookie_low),
6123 case i40e_aqc_opc_get_link_status:
6124 ret = i40e_dev_link_update(dev, 0);
6126 _rte_eth_dev_callback_process(dev,
6127 RTE_ETH_EVENT_INTR_LSC, NULL);
6130 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6135 rte_free(info.msg_buf);
6139 * Interrupt handler triggered by NIC for handling
6140 * specific interrupt.
6143 * Pointer to interrupt handle.
6145 * The address of parameter (struct rte_eth_dev *) regsitered before.
6151 i40e_dev_interrupt_handler(void *param)
6153 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6154 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6157 /* Disable interrupt */
6158 i40e_pf_disable_irq0(hw);
6160 /* read out interrupt causes */
6161 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6163 /* No interrupt event indicated */
6164 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6165 PMD_DRV_LOG(INFO, "No interrupt event");
6168 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6169 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6170 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6171 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6172 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6173 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6174 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6175 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6176 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6177 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6178 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6179 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6180 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6181 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6183 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6184 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6185 i40e_dev_handle_vfr_event(dev);
6187 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6188 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6189 i40e_dev_handle_aq_msg(dev);
6193 /* Enable interrupt */
6194 i40e_pf_enable_irq0(hw);
6195 rte_intr_enable(dev->intr_handle);
6199 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6200 struct i40e_macvlan_filter *filter,
6203 int ele_num, ele_buff_size;
6204 int num, actual_num, i;
6206 int ret = I40E_SUCCESS;
6207 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6208 struct i40e_aqc_add_macvlan_element_data *req_list;
6210 if (filter == NULL || total == 0)
6211 return I40E_ERR_PARAM;
6212 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6213 ele_buff_size = hw->aq.asq_buf_size;
6215 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6216 if (req_list == NULL) {
6217 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6218 return I40E_ERR_NO_MEMORY;
6223 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6224 memset(req_list, 0, ele_buff_size);
6226 for (i = 0; i < actual_num; i++) {
6227 rte_memcpy(req_list[i].mac_addr,
6228 &filter[num + i].macaddr, ETH_ADDR_LEN);
6229 req_list[i].vlan_tag =
6230 rte_cpu_to_le_16(filter[num + i].vlan_id);
6232 switch (filter[num + i].filter_type) {
6233 case RTE_MAC_PERFECT_MATCH:
6234 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6235 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6237 case RTE_MACVLAN_PERFECT_MATCH:
6238 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6240 case RTE_MAC_HASH_MATCH:
6241 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6242 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6244 case RTE_MACVLAN_HASH_MATCH:
6245 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6248 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6249 ret = I40E_ERR_PARAM;
6253 req_list[i].queue_number = 0;
6255 req_list[i].flags = rte_cpu_to_le_16(flags);
6258 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6260 if (ret != I40E_SUCCESS) {
6261 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6265 } while (num < total);
6273 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6274 struct i40e_macvlan_filter *filter,
6277 int ele_num, ele_buff_size;
6278 int num, actual_num, i;
6280 int ret = I40E_SUCCESS;
6281 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6282 struct i40e_aqc_remove_macvlan_element_data *req_list;
6284 if (filter == NULL || total == 0)
6285 return I40E_ERR_PARAM;
6287 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6288 ele_buff_size = hw->aq.asq_buf_size;
6290 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6291 if (req_list == NULL) {
6292 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6293 return I40E_ERR_NO_MEMORY;
6298 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6299 memset(req_list, 0, ele_buff_size);
6301 for (i = 0; i < actual_num; i++) {
6302 rte_memcpy(req_list[i].mac_addr,
6303 &filter[num + i].macaddr, ETH_ADDR_LEN);
6304 req_list[i].vlan_tag =
6305 rte_cpu_to_le_16(filter[num + i].vlan_id);
6307 switch (filter[num + i].filter_type) {
6308 case RTE_MAC_PERFECT_MATCH:
6309 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6310 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6312 case RTE_MACVLAN_PERFECT_MATCH:
6313 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6315 case RTE_MAC_HASH_MATCH:
6316 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6317 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6319 case RTE_MACVLAN_HASH_MATCH:
6320 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6323 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6324 ret = I40E_ERR_PARAM;
6327 req_list[i].flags = rte_cpu_to_le_16(flags);
6330 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6332 if (ret != I40E_SUCCESS) {
6333 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6337 } while (num < total);
6344 /* Find out specific MAC filter */
6345 static struct i40e_mac_filter *
6346 i40e_find_mac_filter(struct i40e_vsi *vsi,
6347 struct ether_addr *macaddr)
6349 struct i40e_mac_filter *f;
6351 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6352 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6360 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6363 uint32_t vid_idx, vid_bit;
6365 if (vlan_id > ETH_VLAN_ID_MAX)
6368 vid_idx = I40E_VFTA_IDX(vlan_id);
6369 vid_bit = I40E_VFTA_BIT(vlan_id);
6371 if (vsi->vfta[vid_idx] & vid_bit)
6378 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6379 uint16_t vlan_id, bool on)
6381 uint32_t vid_idx, vid_bit;
6383 vid_idx = I40E_VFTA_IDX(vlan_id);
6384 vid_bit = I40E_VFTA_BIT(vlan_id);
6387 vsi->vfta[vid_idx] |= vid_bit;
6389 vsi->vfta[vid_idx] &= ~vid_bit;
6393 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6394 uint16_t vlan_id, bool on)
6396 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6397 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6400 if (vlan_id > ETH_VLAN_ID_MAX)
6403 i40e_store_vlan_filter(vsi, vlan_id, on);
6405 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6408 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6411 ret = i40e_aq_add_vlan(hw, vsi->seid,
6412 &vlan_data, 1, NULL);
6413 if (ret != I40E_SUCCESS)
6414 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6416 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6417 &vlan_data, 1, NULL);
6418 if (ret != I40E_SUCCESS)
6420 "Failed to remove vlan filter");
6425 * Find all vlan options for specific mac addr,
6426 * return with actual vlan found.
6429 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6430 struct i40e_macvlan_filter *mv_f,
6431 int num, struct ether_addr *addr)
6437 * Not to use i40e_find_vlan_filter to decrease the loop time,
6438 * although the code looks complex.
6440 if (num < vsi->vlan_num)
6441 return I40E_ERR_PARAM;
6444 for (j = 0; j < I40E_VFTA_SIZE; j++) {
6446 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6447 if (vsi->vfta[j] & (1 << k)) {
6450 "vlan number doesn't match");
6451 return I40E_ERR_PARAM;
6453 rte_memcpy(&mv_f[i].macaddr,
6454 addr, ETH_ADDR_LEN);
6456 j * I40E_UINT32_BIT_SIZE + k;
6462 return I40E_SUCCESS;
6466 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6467 struct i40e_macvlan_filter *mv_f,
6472 struct i40e_mac_filter *f;
6474 if (num < vsi->mac_num)
6475 return I40E_ERR_PARAM;
6477 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6479 PMD_DRV_LOG(ERR, "buffer number not match");
6480 return I40E_ERR_PARAM;
6482 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6484 mv_f[i].vlan_id = vlan;
6485 mv_f[i].filter_type = f->mac_info.filter_type;
6489 return I40E_SUCCESS;
6493 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6496 struct i40e_mac_filter *f;
6497 struct i40e_macvlan_filter *mv_f;
6498 int ret = I40E_SUCCESS;
6500 if (vsi == NULL || vsi->mac_num == 0)
6501 return I40E_ERR_PARAM;
6503 /* Case that no vlan is set */
6504 if (vsi->vlan_num == 0)
6507 num = vsi->mac_num * vsi->vlan_num;
6509 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6511 PMD_DRV_LOG(ERR, "failed to allocate memory");
6512 return I40E_ERR_NO_MEMORY;
6516 if (vsi->vlan_num == 0) {
6517 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6518 rte_memcpy(&mv_f[i].macaddr,
6519 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6520 mv_f[i].filter_type = f->mac_info.filter_type;
6521 mv_f[i].vlan_id = 0;
6525 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6526 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6527 vsi->vlan_num, &f->mac_info.mac_addr);
6528 if (ret != I40E_SUCCESS)
6530 for (j = i; j < i + vsi->vlan_num; j++)
6531 mv_f[j].filter_type = f->mac_info.filter_type;
6536 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6544 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6546 struct i40e_macvlan_filter *mv_f;
6548 int ret = I40E_SUCCESS;
6550 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6551 return I40E_ERR_PARAM;
6553 /* If it's already set, just return */
6554 if (i40e_find_vlan_filter(vsi,vlan))
6555 return I40E_SUCCESS;
6557 mac_num = vsi->mac_num;
6560 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6561 return I40E_ERR_PARAM;
6564 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6567 PMD_DRV_LOG(ERR, "failed to allocate memory");
6568 return I40E_ERR_NO_MEMORY;
6571 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6573 if (ret != I40E_SUCCESS)
6576 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6578 if (ret != I40E_SUCCESS)
6581 i40e_set_vlan_filter(vsi, vlan, 1);
6591 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6593 struct i40e_macvlan_filter *mv_f;
6595 int ret = I40E_SUCCESS;
6598 * Vlan 0 is the generic filter for untagged packets
6599 * and can't be removed.
6601 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6602 return I40E_ERR_PARAM;
6604 /* If can't find it, just return */
6605 if (!i40e_find_vlan_filter(vsi, vlan))
6606 return I40E_ERR_PARAM;
6608 mac_num = vsi->mac_num;
6611 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6612 return I40E_ERR_PARAM;
6615 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6618 PMD_DRV_LOG(ERR, "failed to allocate memory");
6619 return I40E_ERR_NO_MEMORY;
6622 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6624 if (ret != I40E_SUCCESS)
6627 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6629 if (ret != I40E_SUCCESS)
6632 /* This is last vlan to remove, replace all mac filter with vlan 0 */
6633 if (vsi->vlan_num == 1) {
6634 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6635 if (ret != I40E_SUCCESS)
6638 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6639 if (ret != I40E_SUCCESS)
6643 i40e_set_vlan_filter(vsi, vlan, 0);
6653 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6655 struct i40e_mac_filter *f;
6656 struct i40e_macvlan_filter *mv_f;
6657 int i, vlan_num = 0;
6658 int ret = I40E_SUCCESS;
6660 /* If it's add and we've config it, return */
6661 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6663 return I40E_SUCCESS;
6664 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6665 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6668 * If vlan_num is 0, that's the first time to add mac,
6669 * set mask for vlan_id 0.
6671 if (vsi->vlan_num == 0) {
6672 i40e_set_vlan_filter(vsi, 0, 1);
6675 vlan_num = vsi->vlan_num;
6676 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6677 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6680 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6682 PMD_DRV_LOG(ERR, "failed to allocate memory");
6683 return I40E_ERR_NO_MEMORY;
6686 for (i = 0; i < vlan_num; i++) {
6687 mv_f[i].filter_type = mac_filter->filter_type;
6688 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6692 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6693 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6694 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6695 &mac_filter->mac_addr);
6696 if (ret != I40E_SUCCESS)
6700 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6701 if (ret != I40E_SUCCESS)
6704 /* Add the mac addr into mac list */
6705 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6707 PMD_DRV_LOG(ERR, "failed to allocate memory");
6708 ret = I40E_ERR_NO_MEMORY;
6711 rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6713 f->mac_info.filter_type = mac_filter->filter_type;
6714 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6725 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6727 struct i40e_mac_filter *f;
6728 struct i40e_macvlan_filter *mv_f;
6730 enum rte_mac_filter_type filter_type;
6731 int ret = I40E_SUCCESS;
6733 /* Can't find it, return an error */
6734 f = i40e_find_mac_filter(vsi, addr);
6736 return I40E_ERR_PARAM;
6738 vlan_num = vsi->vlan_num;
6739 filter_type = f->mac_info.filter_type;
6740 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6741 filter_type == RTE_MACVLAN_HASH_MATCH) {
6742 if (vlan_num == 0) {
6743 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6744 return I40E_ERR_PARAM;
6746 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6747 filter_type == RTE_MAC_HASH_MATCH)
6750 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6752 PMD_DRV_LOG(ERR, "failed to allocate memory");
6753 return I40E_ERR_NO_MEMORY;
6756 for (i = 0; i < vlan_num; i++) {
6757 mv_f[i].filter_type = filter_type;
6758 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6761 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6762 filter_type == RTE_MACVLAN_HASH_MATCH) {
6763 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6764 if (ret != I40E_SUCCESS)
6768 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6769 if (ret != I40E_SUCCESS)
6772 /* Remove the mac addr into mac list */
6773 TAILQ_REMOVE(&vsi->mac_list, f, next);
6783 /* Configure hash enable flags for RSS */
6785 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
6793 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6794 if (flags & (1ULL << i))
6795 hena |= adapter->pctypes_tbl[i];
6801 /* Parse the hash enable flags */
6803 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
6805 uint64_t rss_hf = 0;
6811 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6812 if (flags & adapter->pctypes_tbl[i])
6813 rss_hf |= (1ULL << i);
6820 i40e_pf_disable_rss(struct i40e_pf *pf)
6822 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6824 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
6825 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
6826 I40E_WRITE_FLUSH(hw);
6830 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6832 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6833 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6834 uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
6835 I40E_VFQF_HKEY_MAX_INDEX :
6836 I40E_PFQF_HKEY_MAX_INDEX;
6839 if (!key || key_len == 0) {
6840 PMD_DRV_LOG(DEBUG, "No key to be configured");
6842 } else if (key_len != (key_idx + 1) *
6844 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6848 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6849 struct i40e_aqc_get_set_rss_key_data *key_dw =
6850 (struct i40e_aqc_get_set_rss_key_data *)key;
6852 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6854 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6856 uint32_t *hash_key = (uint32_t *)key;
6859 if (vsi->type == I40E_VSI_SRIOV) {
6860 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
6863 I40E_VFQF_HKEY1(i, vsi->user_param),
6867 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6868 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
6871 I40E_WRITE_FLUSH(hw);
6878 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6880 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6881 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6885 if (!key || !key_len)
6888 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6889 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6890 (struct i40e_aqc_get_set_rss_key_data *)key);
6892 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6896 uint32_t *key_dw = (uint32_t *)key;
6899 if (vsi->type == I40E_VSI_SRIOV) {
6900 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
6901 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
6902 key_dw[i] = i40e_read_rx_ctl(hw, reg);
6904 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
6907 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
6908 reg = I40E_PFQF_HKEY(i);
6909 key_dw[i] = i40e_read_rx_ctl(hw, reg);
6911 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6919 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6921 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6925 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6926 rss_conf->rss_key_len);
6930 hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
6931 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6932 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6933 I40E_WRITE_FLUSH(hw);
6939 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6940 struct rte_eth_rss_conf *rss_conf)
6942 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6943 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6944 uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
6947 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6948 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6950 if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
6951 if (rss_hf != 0) /* Enable RSS */
6953 return 0; /* Nothing to do */
6956 if (rss_hf == 0) /* Disable RSS */
6959 return i40e_hw_rss_hash_set(pf, rss_conf);
6963 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6964 struct rte_eth_rss_conf *rss_conf)
6966 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6967 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6970 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6971 &rss_conf->rss_key_len);
6973 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6974 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6975 rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
6981 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6983 switch (filter_type) {
6984 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6985 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6987 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6988 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6990 case RTE_TUNNEL_FILTER_IMAC_TENID:
6991 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6993 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6994 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6996 case ETH_TUNNEL_FILTER_IMAC:
6997 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6999 case ETH_TUNNEL_FILTER_OIP:
7000 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7002 case ETH_TUNNEL_FILTER_IIP:
7003 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7006 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7013 /* Convert tunnel filter structure */
7015 i40e_tunnel_filter_convert(
7016 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
7017 struct i40e_tunnel_filter *tunnel_filter)
7019 ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
7020 (struct ether_addr *)&tunnel_filter->input.outer_mac);
7021 ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
7022 (struct ether_addr *)&tunnel_filter->input.inner_mac);
7023 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7024 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7025 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7026 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7027 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7029 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7030 tunnel_filter->input.flags = cld_filter->element.flags;
7031 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7032 tunnel_filter->queue = cld_filter->element.queue_number;
7033 rte_memcpy(tunnel_filter->input.general_fields,
7034 cld_filter->general_fields,
7035 sizeof(cld_filter->general_fields));
7040 /* Check if there exists the tunnel filter */
7041 struct i40e_tunnel_filter *
7042 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7043 const struct i40e_tunnel_filter_input *input)
7047 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7051 return tunnel_rule->hash_map[ret];
7054 /* Add a tunnel filter into the SW list */
7056 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7057 struct i40e_tunnel_filter *tunnel_filter)
7059 struct i40e_tunnel_rule *rule = &pf->tunnel;
7062 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7065 "Failed to insert tunnel filter to hash table %d!",
7069 rule->hash_map[ret] = tunnel_filter;
7071 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7076 /* Delete a tunnel filter from the SW list */
7078 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7079 struct i40e_tunnel_filter_input *input)
7081 struct i40e_tunnel_rule *rule = &pf->tunnel;
7082 struct i40e_tunnel_filter *tunnel_filter;
7085 ret = rte_hash_del_key(rule->hash_table, input);
7088 "Failed to delete tunnel filter to hash table %d!",
7092 tunnel_filter = rule->hash_map[ret];
7093 rule->hash_map[ret] = NULL;
7095 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7096 rte_free(tunnel_filter);
7102 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7103 struct rte_eth_tunnel_filter_conf *tunnel_filter,
7107 uint32_t ipv4_addr, ipv4_addr_le;
7108 uint8_t i, tun_type = 0;
7109 /* internal varialbe to convert ipv6 byte order */
7110 uint32_t convert_ipv6[4];
7112 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7113 struct i40e_vsi *vsi = pf->main_vsi;
7114 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7115 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7116 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7117 struct i40e_tunnel_filter *tunnel, *node;
7118 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7120 cld_filter = rte_zmalloc("tunnel_filter",
7121 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7124 if (NULL == cld_filter) {
7125 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7128 pfilter = cld_filter;
7130 ether_addr_copy(&tunnel_filter->outer_mac,
7131 (struct ether_addr *)&pfilter->element.outer_mac);
7132 ether_addr_copy(&tunnel_filter->inner_mac,
7133 (struct ether_addr *)&pfilter->element.inner_mac);
7135 pfilter->element.inner_vlan =
7136 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7137 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7138 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7139 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7140 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7141 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7143 sizeof(pfilter->element.ipaddr.v4.data));
7145 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7146 for (i = 0; i < 4; i++) {
7148 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7150 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7152 sizeof(pfilter->element.ipaddr.v6.data));
7155 /* check tunneled type */
7156 switch (tunnel_filter->tunnel_type) {
7157 case RTE_TUNNEL_TYPE_VXLAN:
7158 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7160 case RTE_TUNNEL_TYPE_NVGRE:
7161 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7163 case RTE_TUNNEL_TYPE_IP_IN_GRE:
7164 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7167 /* Other tunnel types is not supported. */
7168 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7169 rte_free(cld_filter);
7173 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7174 &pfilter->element.flags);
7176 rte_free(cld_filter);
7180 pfilter->element.flags |= rte_cpu_to_le_16(
7181 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7182 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7183 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7184 pfilter->element.queue_number =
7185 rte_cpu_to_le_16(tunnel_filter->queue_id);
7187 /* Check if there is the filter in SW list */
7188 memset(&check_filter, 0, sizeof(check_filter));
7189 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7190 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7192 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7196 if (!add && !node) {
7197 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7202 ret = i40e_aq_add_cloud_filters(hw,
7203 vsi->seid, &cld_filter->element, 1);
7205 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7208 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7209 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7210 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7212 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7213 &cld_filter->element, 1);
7215 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7218 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7221 rte_free(cld_filter);
7225 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7226 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
7227 #define I40E_TR_GENEVE_KEY_MASK 0x8
7228 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
7229 #define I40E_TR_GRE_KEY_MASK 0x400
7230 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
7231 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
7234 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7236 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7237 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7238 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7239 enum i40e_status_code status = I40E_SUCCESS;
7241 memset(&filter_replace, 0,
7242 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7243 memset(&filter_replace_buf, 0,
7244 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7246 /* create L1 filter */
7247 filter_replace.old_filter_type =
7248 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7249 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7250 filter_replace.tr_bit = 0;
7252 /* Prepare the buffer, 3 entries */
7253 filter_replace_buf.data[0] =
7254 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7255 filter_replace_buf.data[0] |=
7256 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7257 filter_replace_buf.data[2] = 0xFF;
7258 filter_replace_buf.data[3] = 0xFF;
7259 filter_replace_buf.data[4] =
7260 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7261 filter_replace_buf.data[4] |=
7262 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7263 filter_replace_buf.data[7] = 0xF0;
7264 filter_replace_buf.data[8]
7265 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7266 filter_replace_buf.data[8] |=
7267 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7268 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7269 I40E_TR_GENEVE_KEY_MASK |
7270 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7271 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7272 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7273 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7275 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7276 &filter_replace_buf);
7281 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7283 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7284 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7285 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7286 enum i40e_status_code status = I40E_SUCCESS;
7289 memset(&filter_replace, 0,
7290 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7291 memset(&filter_replace_buf, 0,
7292 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7293 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7294 I40E_AQC_MIRROR_CLOUD_FILTER;
7295 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7296 filter_replace.new_filter_type =
7297 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7298 /* Prepare the buffer, 2 entries */
7299 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7300 filter_replace_buf.data[0] |=
7301 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7302 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7303 filter_replace_buf.data[4] |=
7304 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7305 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7306 &filter_replace_buf);
7311 memset(&filter_replace, 0,
7312 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7313 memset(&filter_replace_buf, 0,
7314 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7316 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7317 I40E_AQC_MIRROR_CLOUD_FILTER;
7318 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7319 filter_replace.new_filter_type =
7320 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7321 /* Prepare the buffer, 2 entries */
7322 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7323 filter_replace_buf.data[0] |=
7324 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7325 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7326 filter_replace_buf.data[4] |=
7327 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7329 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7330 &filter_replace_buf);
7334 static enum i40e_status_code
7335 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7337 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7338 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7339 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7340 enum i40e_status_code status = I40E_SUCCESS;
7343 memset(&filter_replace, 0,
7344 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7345 memset(&filter_replace_buf, 0,
7346 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7347 /* create L1 filter */
7348 filter_replace.old_filter_type =
7349 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7350 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7351 filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7352 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7353 /* Prepare the buffer, 2 entries */
7354 filter_replace_buf.data[0] =
7355 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7356 filter_replace_buf.data[0] |=
7357 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7358 filter_replace_buf.data[2] = 0xFF;
7359 filter_replace_buf.data[3] = 0xFF;
7360 filter_replace_buf.data[4] =
7361 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7362 filter_replace_buf.data[4] |=
7363 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7364 filter_replace_buf.data[6] = 0xFF;
7365 filter_replace_buf.data[7] = 0xFF;
7366 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7367 &filter_replace_buf);
7372 memset(&filter_replace, 0,
7373 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7374 memset(&filter_replace_buf, 0,
7375 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7376 /* create L1 filter */
7377 filter_replace.old_filter_type =
7378 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
7379 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
7380 filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
7381 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7382 /* Prepare the buffer, 2 entries */
7383 filter_replace_buf.data[0] =
7384 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7385 filter_replace_buf.data[0] |=
7386 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7387 filter_replace_buf.data[2] = 0xFF;
7388 filter_replace_buf.data[3] = 0xFF;
7389 filter_replace_buf.data[4] =
7390 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7391 filter_replace_buf.data[4] |=
7392 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7393 filter_replace_buf.data[6] = 0xFF;
7394 filter_replace_buf.data[7] = 0xFF;
7396 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7397 &filter_replace_buf);
7402 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
7404 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7405 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7406 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7407 enum i40e_status_code status = I40E_SUCCESS;
7410 memset(&filter_replace, 0,
7411 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7412 memset(&filter_replace_buf, 0,
7413 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7414 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7415 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7416 filter_replace.new_filter_type =
7417 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7418 /* Prepare the buffer, 2 entries */
7419 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
7420 filter_replace_buf.data[0] |=
7421 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7422 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7423 filter_replace_buf.data[4] |=
7424 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7425 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7426 &filter_replace_buf);
7431 memset(&filter_replace, 0,
7432 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7433 memset(&filter_replace_buf, 0,
7434 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7435 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7436 filter_replace.old_filter_type =
7437 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7438 filter_replace.new_filter_type =
7439 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7440 /* Prepare the buffer, 2 entries */
7441 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
7442 filter_replace_buf.data[0] |=
7443 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7444 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7445 filter_replace_buf.data[4] |=
7446 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7448 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7449 &filter_replace_buf);
7454 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7455 struct i40e_tunnel_filter_conf *tunnel_filter,
7459 uint32_t ipv4_addr, ipv4_addr_le;
7460 uint8_t i, tun_type = 0;
7461 /* internal variable to convert ipv6 byte order */
7462 uint32_t convert_ipv6[4];
7464 struct i40e_pf_vf *vf = NULL;
7465 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7466 struct i40e_vsi *vsi;
7467 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7468 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7469 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7470 struct i40e_tunnel_filter *tunnel, *node;
7471 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7473 bool big_buffer = 0;
7475 cld_filter = rte_zmalloc("tunnel_filter",
7476 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7479 if (cld_filter == NULL) {
7480 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7483 pfilter = cld_filter;
7485 ether_addr_copy(&tunnel_filter->outer_mac,
7486 (struct ether_addr *)&pfilter->element.outer_mac);
7487 ether_addr_copy(&tunnel_filter->inner_mac,
7488 (struct ether_addr *)&pfilter->element.inner_mac);
7490 pfilter->element.inner_vlan =
7491 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7492 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7493 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7494 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7495 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7496 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7498 sizeof(pfilter->element.ipaddr.v4.data));
7500 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7501 for (i = 0; i < 4; i++) {
7503 rte_cpu_to_le_32(rte_be_to_cpu_32(
7504 tunnel_filter->ip_addr.ipv6_addr[i]));
7506 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7508 sizeof(pfilter->element.ipaddr.v6.data));
7511 /* check tunneled type */
7512 switch (tunnel_filter->tunnel_type) {
7513 case I40E_TUNNEL_TYPE_VXLAN:
7514 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7516 case I40E_TUNNEL_TYPE_NVGRE:
7517 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7519 case I40E_TUNNEL_TYPE_IP_IN_GRE:
7520 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7522 case I40E_TUNNEL_TYPE_MPLSoUDP:
7523 if (!pf->mpls_replace_flag) {
7524 i40e_replace_mpls_l1_filter(pf);
7525 i40e_replace_mpls_cloud_filter(pf);
7526 pf->mpls_replace_flag = 1;
7528 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7529 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7531 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7532 (teid_le & 0xF) << 12;
7533 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7536 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
7538 case I40E_TUNNEL_TYPE_MPLSoGRE:
7539 if (!pf->mpls_replace_flag) {
7540 i40e_replace_mpls_l1_filter(pf);
7541 i40e_replace_mpls_cloud_filter(pf);
7542 pf->mpls_replace_flag = 1;
7544 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7545 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7547 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7548 (teid_le & 0xF) << 12;
7549 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7552 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
7554 case I40E_TUNNEL_TYPE_GTPC:
7555 if (!pf->gtp_replace_flag) {
7556 i40e_replace_gtp_l1_filter(pf);
7557 i40e_replace_gtp_cloud_filter(pf);
7558 pf->gtp_replace_flag = 1;
7560 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7561 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
7562 (teid_le >> 16) & 0xFFFF;
7563 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
7565 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
7569 case I40E_TUNNEL_TYPE_GTPU:
7570 if (!pf->gtp_replace_flag) {
7571 i40e_replace_gtp_l1_filter(pf);
7572 i40e_replace_gtp_cloud_filter(pf);
7573 pf->gtp_replace_flag = 1;
7575 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7576 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
7577 (teid_le >> 16) & 0xFFFF;
7578 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
7580 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
7584 case I40E_TUNNEL_TYPE_QINQ:
7585 if (!pf->qinq_replace_flag) {
7586 ret = i40e_cloud_filter_qinq_create(pf);
7589 "QinQ tunnel filter already created.");
7590 pf->qinq_replace_flag = 1;
7592 /* Add in the General fields the values of
7593 * the Outer and Inner VLAN
7594 * Big Buffer should be set, see changes in
7595 * i40e_aq_add_cloud_filters
7597 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7598 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7602 /* Other tunnel types is not supported. */
7603 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7604 rte_free(cld_filter);
7608 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7609 pfilter->element.flags =
7610 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7611 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7612 pfilter->element.flags =
7613 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7614 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
7615 pfilter->element.flags =
7616 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7617 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
7618 pfilter->element.flags =
7619 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7620 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7621 pfilter->element.flags |=
7622 I40E_AQC_ADD_CLOUD_FILTER_0X10;
7624 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7625 &pfilter->element.flags);
7627 rte_free(cld_filter);
7632 pfilter->element.flags |= rte_cpu_to_le_16(
7633 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7634 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7635 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7636 pfilter->element.queue_number =
7637 rte_cpu_to_le_16(tunnel_filter->queue_id);
7639 if (!tunnel_filter->is_to_vf)
7642 if (tunnel_filter->vf_id >= pf->vf_num) {
7643 PMD_DRV_LOG(ERR, "Invalid argument.");
7646 vf = &pf->vfs[tunnel_filter->vf_id];
7650 /* Check if there is the filter in SW list */
7651 memset(&check_filter, 0, sizeof(check_filter));
7652 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7653 check_filter.is_to_vf = tunnel_filter->is_to_vf;
7654 check_filter.vf_id = tunnel_filter->vf_id;
7655 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7657 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7661 if (!add && !node) {
7662 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7668 ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7669 vsi->seid, cld_filter, 1);
7671 ret = i40e_aq_add_cloud_filters(hw,
7672 vsi->seid, &cld_filter->element, 1);
7674 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7677 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7678 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7679 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7682 ret = i40e_aq_remove_cloud_filters_big_buffer(
7683 hw, vsi->seid, cld_filter, 1);
7685 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7686 &cld_filter->element, 1);
7688 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7691 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7694 rte_free(cld_filter);
7699 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7703 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7704 if (pf->vxlan_ports[i] == port)
7712 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7716 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7718 idx = i40e_get_vxlan_port_idx(pf, port);
7720 /* Check if port already exists */
7722 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7726 /* Now check if there is space to add the new port */
7727 idx = i40e_get_vxlan_port_idx(pf, 0);
7730 "Maximum number of UDP ports reached, not adding port %d",
7735 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7738 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7742 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7745 /* New port: add it and mark its index in the bitmap */
7746 pf->vxlan_ports[idx] = port;
7747 pf->vxlan_bitmap |= (1 << idx);
7749 if (!(pf->flags & I40E_FLAG_VXLAN))
7750 pf->flags |= I40E_FLAG_VXLAN;
7756 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7759 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7761 if (!(pf->flags & I40E_FLAG_VXLAN)) {
7762 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7766 idx = i40e_get_vxlan_port_idx(pf, port);
7769 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7773 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7774 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7778 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7781 pf->vxlan_ports[idx] = 0;
7782 pf->vxlan_bitmap &= ~(1 << idx);
7784 if (!pf->vxlan_bitmap)
7785 pf->flags &= ~I40E_FLAG_VXLAN;
7790 /* Add UDP tunneling port */
7792 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7793 struct rte_eth_udp_tunnel *udp_tunnel)
7796 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7798 if (udp_tunnel == NULL)
7801 switch (udp_tunnel->prot_type) {
7802 case RTE_TUNNEL_TYPE_VXLAN:
7803 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7806 case RTE_TUNNEL_TYPE_GENEVE:
7807 case RTE_TUNNEL_TYPE_TEREDO:
7808 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7813 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7821 /* Remove UDP tunneling port */
7823 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7824 struct rte_eth_udp_tunnel *udp_tunnel)
7827 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7829 if (udp_tunnel == NULL)
7832 switch (udp_tunnel->prot_type) {
7833 case RTE_TUNNEL_TYPE_VXLAN:
7834 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7836 case RTE_TUNNEL_TYPE_GENEVE:
7837 case RTE_TUNNEL_TYPE_TEREDO:
7838 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7842 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7850 /* Calculate the maximum number of contiguous PF queues that are configured */
7852 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7854 struct rte_eth_dev_data *data = pf->dev_data;
7856 struct i40e_rx_queue *rxq;
7859 for (i = 0; i < pf->lan_nb_qps; i++) {
7860 rxq = data->rx_queues[i];
7861 if (rxq && rxq->q_set)
7872 i40e_pf_config_rss(struct i40e_pf *pf)
7874 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7875 struct rte_eth_rss_conf rss_conf;
7876 uint32_t i, lut = 0;
7880 * If both VMDQ and RSS enabled, not all of PF queues are configured.
7881 * It's necessary to calculate the actual PF queues that are configured.
7883 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7884 num = i40e_pf_calc_configured_queues_num(pf);
7886 num = pf->dev_data->nb_rx_queues;
7888 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7889 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7893 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7897 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7900 lut = (lut << 8) | (j & ((0x1 <<
7901 hw->func_caps.rss_table_entry_width) - 1));
7903 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7906 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7907 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
7908 i40e_pf_disable_rss(pf);
7911 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7912 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7913 /* Random default keys */
7914 static uint32_t rss_key_default[] = {0x6b793944,
7915 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7916 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7917 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7919 rss_conf.rss_key = (uint8_t *)rss_key_default;
7920 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7924 return i40e_hw_rss_hash_set(pf, &rss_conf);
7928 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7929 struct rte_eth_tunnel_filter_conf *filter)
7931 if (pf == NULL || filter == NULL) {
7932 PMD_DRV_LOG(ERR, "Invalid parameter");
7936 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7937 PMD_DRV_LOG(ERR, "Invalid queue ID");
7941 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7942 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7946 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7947 (is_zero_ether_addr(&filter->outer_mac))) {
7948 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7952 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7953 (is_zero_ether_addr(&filter->inner_mac))) {
7954 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7961 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7962 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
7964 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7969 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7970 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7973 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7974 } else if (len == 4) {
7975 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7977 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7982 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7989 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7990 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7996 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8003 switch (cfg->cfg_type) {
8004 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8005 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8008 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8016 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8017 enum rte_filter_op filter_op,
8020 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8021 int ret = I40E_ERR_PARAM;
8023 switch (filter_op) {
8024 case RTE_ETH_FILTER_SET:
8025 ret = i40e_dev_global_config_set(hw,
8026 (struct rte_eth_global_cfg *)arg);
8029 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8037 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8038 enum rte_filter_op filter_op,
8041 struct rte_eth_tunnel_filter_conf *filter;
8042 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8043 int ret = I40E_SUCCESS;
8045 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8047 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8048 return I40E_ERR_PARAM;
8050 switch (filter_op) {
8051 case RTE_ETH_FILTER_NOP:
8052 if (!(pf->flags & I40E_FLAG_VXLAN))
8053 ret = I40E_NOT_SUPPORTED;
8055 case RTE_ETH_FILTER_ADD:
8056 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8058 case RTE_ETH_FILTER_DELETE:
8059 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8062 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8063 ret = I40E_ERR_PARAM;
8071 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8074 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8077 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8078 ret = i40e_pf_config_rss(pf);
8080 i40e_pf_disable_rss(pf);
8085 /* Get the symmetric hash enable configurations per port */
8087 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8089 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8091 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8094 /* Set the symmetric hash enable configurations per port */
8096 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8098 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8101 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8103 "Symmetric hash has already been enabled");
8106 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8108 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8110 "Symmetric hash has already been disabled");
8113 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8115 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8116 I40E_WRITE_FLUSH(hw);
8120 * Get global configurations of hash function type and symmetric hash enable
8121 * per flow type (pctype). Note that global configuration means it affects all
8122 * the ports on the same NIC.
8125 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8126 struct rte_eth_hash_global_conf *g_cfg)
8128 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8132 memset(g_cfg, 0, sizeof(*g_cfg));
8133 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8134 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8135 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8137 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8138 PMD_DRV_LOG(DEBUG, "Hash function is %s",
8139 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8142 * We work only with lowest 32 bits which is not correct, but to work
8143 * properly the valid_bit_mask size should be increased up to 64 bits
8144 * and this will brake ABI. This modification will be done in next
8147 g_cfg->valid_bit_mask[0] = (uint32_t)adapter->flow_types_mask;
8149 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT32_BIT; i++) {
8150 if (!adapter->pctypes_tbl[i])
8152 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8153 j < I40E_FILTER_PCTYPE_MAX; j++) {
8154 if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8155 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8156 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8157 g_cfg->sym_hash_enable_mask[0] |=
8168 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8169 const struct rte_eth_hash_global_conf *g_cfg)
8172 uint32_t mask0, i40e_mask = adapter->flow_types_mask;
8174 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8175 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8176 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8177 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8183 * As i40e supports less than 32 flow types, only first 32 bits need to
8186 mask0 = g_cfg->valid_bit_mask[0];
8187 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8189 /* Check if any unsupported flow type configured */
8190 if ((mask0 | i40e_mask) ^ i40e_mask)
8193 if (g_cfg->valid_bit_mask[i])
8201 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8207 * Set global configurations of hash function type and symmetric hash enable
8208 * per flow type (pctype). Note any modifying global configuration will affect
8209 * all the ports on the same NIC.
8212 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8213 struct rte_eth_hash_global_conf *g_cfg)
8215 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8220 * We work only with lowest 32 bits which is not correct, but to work
8221 * properly the valid_bit_mask size should be increased up to 64 bits
8222 * and this will brake ABI. This modification will be done in next
8225 uint32_t mask0 = g_cfg->valid_bit_mask[0] &
8226 (uint32_t)adapter->flow_types_mask;
8228 /* Check the input parameters */
8229 ret = i40e_hash_global_config_check(adapter, g_cfg);
8233 for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT32_BIT; i++) {
8234 if (mask0 & (1UL << i)) {
8235 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
8236 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8238 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8239 j < I40E_FILTER_PCTYPE_MAX; j++) {
8240 if (adapter->pctypes_tbl[i] & (1ULL << j))
8241 i40e_write_rx_ctl(hw,
8248 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8249 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8251 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8253 "Hash function already set to Toeplitz");
8256 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8257 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8259 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8261 "Hash function already set to Simple XOR");
8264 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8266 /* Use the default, and keep it as it is */
8269 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
8272 I40E_WRITE_FLUSH(hw);
8278 * Valid input sets for hash and flow director filters per PCTYPE
8281 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8282 enum rte_filter_type filter)
8286 static const uint64_t valid_hash_inset_table[] = {
8287 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8288 I40E_INSET_DMAC | I40E_INSET_SMAC |
8289 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8290 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8291 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8292 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8293 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8294 I40E_INSET_FLEX_PAYLOAD,
8295 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8296 I40E_INSET_DMAC | I40E_INSET_SMAC |
8297 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8298 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8299 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8300 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8301 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8302 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8303 I40E_INSET_FLEX_PAYLOAD,
8304 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8305 I40E_INSET_DMAC | I40E_INSET_SMAC |
8306 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8307 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8308 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8309 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8310 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8311 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8312 I40E_INSET_FLEX_PAYLOAD,
8313 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8314 I40E_INSET_DMAC | I40E_INSET_SMAC |
8315 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8316 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8317 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8318 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8319 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8320 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8321 I40E_INSET_FLEX_PAYLOAD,
8322 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8323 I40E_INSET_DMAC | I40E_INSET_SMAC |
8324 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8325 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8326 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8327 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8328 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8329 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8330 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8331 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8332 I40E_INSET_DMAC | I40E_INSET_SMAC |
8333 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8334 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8335 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8336 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8337 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8338 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8339 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8340 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8341 I40E_INSET_DMAC | I40E_INSET_SMAC |
8342 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8343 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8344 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8345 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8346 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8347 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8348 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8349 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8350 I40E_INSET_DMAC | I40E_INSET_SMAC |
8351 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8352 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8353 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8354 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8355 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8356 I40E_INSET_FLEX_PAYLOAD,
8357 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8358 I40E_INSET_DMAC | I40E_INSET_SMAC |
8359 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8360 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8361 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8362 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8363 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8364 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8365 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8366 I40E_INSET_DMAC | I40E_INSET_SMAC |
8367 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8368 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8369 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8370 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8371 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8372 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8373 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8374 I40E_INSET_DMAC | I40E_INSET_SMAC |
8375 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8376 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8377 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8378 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8379 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8380 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8381 I40E_INSET_FLEX_PAYLOAD,
8382 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8383 I40E_INSET_DMAC | I40E_INSET_SMAC |
8384 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8385 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8386 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8387 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8388 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8389 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8390 I40E_INSET_FLEX_PAYLOAD,
8391 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8392 I40E_INSET_DMAC | I40E_INSET_SMAC |
8393 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8394 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8395 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8396 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8397 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8398 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8399 I40E_INSET_FLEX_PAYLOAD,
8400 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8401 I40E_INSET_DMAC | I40E_INSET_SMAC |
8402 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8403 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8404 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8405 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8406 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8407 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8408 I40E_INSET_FLEX_PAYLOAD,
8409 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8410 I40E_INSET_DMAC | I40E_INSET_SMAC |
8411 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8412 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8413 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8414 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8415 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8416 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8417 I40E_INSET_FLEX_PAYLOAD,
8418 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8419 I40E_INSET_DMAC | I40E_INSET_SMAC |
8420 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8421 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8422 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8423 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8424 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8425 I40E_INSET_FLEX_PAYLOAD,
8426 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8427 I40E_INSET_DMAC | I40E_INSET_SMAC |
8428 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8429 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8430 I40E_INSET_FLEX_PAYLOAD,
8434 * Flow director supports only fields defined in
8435 * union rte_eth_fdir_flow.
8437 static const uint64_t valid_fdir_inset_table[] = {
8438 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8439 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8440 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8441 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8442 I40E_INSET_IPV4_TTL,
8443 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8444 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8445 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8446 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8447 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8448 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8449 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8450 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8451 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8452 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8453 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8454 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8455 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8456 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8457 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8458 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8459 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8460 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8461 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8462 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8463 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8464 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8465 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8466 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8467 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8468 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8469 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8470 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8471 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8472 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8474 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8475 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8476 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8477 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8478 I40E_INSET_IPV4_TTL,
8479 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8480 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8481 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8482 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8483 I40E_INSET_IPV6_HOP_LIMIT,
8484 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8485 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8486 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8487 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8488 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8489 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8490 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8491 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8492 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8493 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8494 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8495 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8496 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8497 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8498 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8499 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8500 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8501 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8502 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8503 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8504 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8505 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8506 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8507 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8508 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8509 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8510 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8511 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8512 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8513 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8515 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8516 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8517 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8518 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8519 I40E_INSET_IPV6_HOP_LIMIT,
8520 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8521 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8522 I40E_INSET_LAST_ETHER_TYPE,
8525 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8527 if (filter == RTE_ETH_FILTER_HASH)
8528 valid = valid_hash_inset_table[pctype];
8530 valid = valid_fdir_inset_table[pctype];
8536 * Validate if the input set is allowed for a specific PCTYPE
8539 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8540 enum rte_filter_type filter, uint64_t inset)
8544 valid = i40e_get_valid_input_set(pctype, filter);
8545 if (inset & (~valid))
8551 /* default input set fields combination per pctype */
8553 i40e_get_default_input_set(uint16_t pctype)
8555 static const uint64_t default_inset_table[] = {
8556 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8557 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8558 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8559 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8560 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8561 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8562 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8563 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8564 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8565 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8566 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8567 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8568 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8569 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8570 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8571 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8572 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8573 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8574 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8575 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8577 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8578 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8579 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8580 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8581 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8582 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8583 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8584 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8585 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8586 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8587 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8588 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8589 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8590 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8591 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8592 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8593 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8594 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8595 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8596 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8597 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8598 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8600 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8601 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8602 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8603 I40E_INSET_LAST_ETHER_TYPE,
8606 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8609 return default_inset_table[pctype];
8613 * Parse the input set from index to logical bit masks
8616 i40e_parse_input_set(uint64_t *inset,
8617 enum i40e_filter_pctype pctype,
8618 enum rte_eth_input_set_field *field,
8624 static const struct {
8625 enum rte_eth_input_set_field field;
8627 } inset_convert_table[] = {
8628 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8629 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8630 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8631 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8632 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8633 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8634 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8635 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8636 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8637 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8638 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8639 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8640 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8641 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8642 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8643 I40E_INSET_IPV6_NEXT_HDR},
8644 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8645 I40E_INSET_IPV6_HOP_LIMIT},
8646 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8647 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8648 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8649 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8650 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8651 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8652 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8653 I40E_INSET_SCTP_VT},
8654 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8655 I40E_INSET_TUNNEL_DMAC},
8656 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8657 I40E_INSET_VLAN_TUNNEL},
8658 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8659 I40E_INSET_TUNNEL_ID},
8660 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8661 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8662 I40E_INSET_FLEX_PAYLOAD_W1},
8663 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8664 I40E_INSET_FLEX_PAYLOAD_W2},
8665 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8666 I40E_INSET_FLEX_PAYLOAD_W3},
8667 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8668 I40E_INSET_FLEX_PAYLOAD_W4},
8669 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8670 I40E_INSET_FLEX_PAYLOAD_W5},
8671 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8672 I40E_INSET_FLEX_PAYLOAD_W6},
8673 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8674 I40E_INSET_FLEX_PAYLOAD_W7},
8675 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8676 I40E_INSET_FLEX_PAYLOAD_W8},
8679 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8682 /* Only one item allowed for default or all */
8684 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8685 *inset = i40e_get_default_input_set(pctype);
8687 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8688 *inset = I40E_INSET_NONE;
8693 for (i = 0, *inset = 0; i < size; i++) {
8694 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8695 if (field[i] == inset_convert_table[j].field) {
8696 *inset |= inset_convert_table[j].inset;
8701 /* It contains unsupported input set, return immediately */
8702 if (j == RTE_DIM(inset_convert_table))
8710 * Translate the input set from bit masks to register aware bit masks
8714 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8724 static const struct inset_map inset_map_common[] = {
8725 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8726 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8727 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8728 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8729 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8730 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8731 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8732 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8733 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8734 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8735 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8736 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8737 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8738 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8739 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8740 {I40E_INSET_TUNNEL_DMAC,
8741 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8742 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8743 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8744 {I40E_INSET_TUNNEL_SRC_PORT,
8745 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8746 {I40E_INSET_TUNNEL_DST_PORT,
8747 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8748 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8749 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8750 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8751 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8752 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8753 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8754 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8755 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8756 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8759 /* some different registers map in x722*/
8760 static const struct inset_map inset_map_diff_x722[] = {
8761 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8762 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8763 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8764 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8767 static const struct inset_map inset_map_diff_not_x722[] = {
8768 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8769 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8770 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8771 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8777 /* Translate input set to register aware inset */
8778 if (type == I40E_MAC_X722) {
8779 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8780 if (input & inset_map_diff_x722[i].inset)
8781 val |= inset_map_diff_x722[i].inset_reg;
8784 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8785 if (input & inset_map_diff_not_x722[i].inset)
8786 val |= inset_map_diff_not_x722[i].inset_reg;
8790 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8791 if (input & inset_map_common[i].inset)
8792 val |= inset_map_common[i].inset_reg;
8799 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8802 uint64_t inset_need_mask = inset;
8804 static const struct {
8807 } inset_mask_map[] = {
8808 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8809 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8810 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8811 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8812 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8813 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8814 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8815 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8818 if (!inset || !mask || !nb_elem)
8821 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8822 /* Clear the inset bit, if no MASK is required,
8823 * for example proto + ttl
8825 if ((inset & inset_mask_map[i].inset) ==
8826 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8827 inset_need_mask &= ~inset_mask_map[i].inset;
8828 if (!inset_need_mask)
8831 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8832 if ((inset_need_mask & inset_mask_map[i].inset) ==
8833 inset_mask_map[i].inset) {
8834 if (idx >= nb_elem) {
8835 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8838 mask[idx] = inset_mask_map[i].mask;
8847 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8849 uint32_t reg = i40e_read_rx_ctl(hw, addr);
8851 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8853 i40e_write_rx_ctl(hw, addr, val);
8854 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8855 (uint32_t)i40e_read_rx_ctl(hw, addr));
8859 i40e_filter_input_set_init(struct i40e_pf *pf)
8861 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8862 enum i40e_filter_pctype pctype;
8863 uint64_t input_set, inset_reg;
8864 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8868 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8869 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8870 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
8872 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
8875 input_set = i40e_get_default_input_set(pctype);
8877 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8878 I40E_INSET_MASK_NUM_REG);
8881 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8884 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8885 (uint32_t)(inset_reg & UINT32_MAX));
8886 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8887 (uint32_t)((inset_reg >>
8888 I40E_32_BIT_WIDTH) & UINT32_MAX));
8889 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8890 (uint32_t)(inset_reg & UINT32_MAX));
8891 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8892 (uint32_t)((inset_reg >>
8893 I40E_32_BIT_WIDTH) & UINT32_MAX));
8895 for (i = 0; i < num; i++) {
8896 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8898 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8901 /*clear unused mask registers of the pctype */
8902 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8903 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8905 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8908 I40E_WRITE_FLUSH(hw);
8910 /* store the default input set */
8911 pf->hash_input_set[pctype] = input_set;
8912 pf->fdir.input_set[pctype] = input_set;
8917 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8918 struct rte_eth_input_set_conf *conf)
8920 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8921 enum i40e_filter_pctype pctype;
8922 uint64_t input_set, inset_reg = 0;
8923 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8927 PMD_DRV_LOG(ERR, "Invalid pointer");
8930 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8931 conf->op != RTE_ETH_INPUT_SET_ADD) {
8932 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8936 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
8937 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
8938 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8942 if (hw->mac.type == I40E_MAC_X722) {
8943 /* get translated pctype value in fd pctype register */
8944 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8945 I40E_GLQF_FD_PCTYPES((int)pctype));
8948 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8951 PMD_DRV_LOG(ERR, "Failed to parse input set");
8955 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8956 /* get inset value in register */
8957 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8958 inset_reg <<= I40E_32_BIT_WIDTH;
8959 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8960 input_set |= pf->hash_input_set[pctype];
8962 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8963 I40E_INSET_MASK_NUM_REG);
8967 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8969 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8970 (uint32_t)(inset_reg & UINT32_MAX));
8971 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8972 (uint32_t)((inset_reg >>
8973 I40E_32_BIT_WIDTH) & UINT32_MAX));
8975 for (i = 0; i < num; i++)
8976 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8978 /*clear unused mask registers of the pctype */
8979 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8980 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8982 I40E_WRITE_FLUSH(hw);
8984 pf->hash_input_set[pctype] = input_set;
8989 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8990 struct rte_eth_input_set_conf *conf)
8992 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8993 enum i40e_filter_pctype pctype;
8994 uint64_t input_set, inset_reg = 0;
8995 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8999 PMD_DRV_LOG(ERR, "Invalid pointer");
9002 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9003 conf->op != RTE_ETH_INPUT_SET_ADD) {
9004 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9008 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9010 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9011 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9015 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9018 PMD_DRV_LOG(ERR, "Failed to parse input set");
9022 /* get inset value in register */
9023 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9024 inset_reg <<= I40E_32_BIT_WIDTH;
9025 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9027 /* Can not change the inset reg for flex payload for fdir,
9028 * it is done by writing I40E_PRTQF_FD_FLXINSET
9029 * in i40e_set_flex_mask_on_pctype.
9031 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9032 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9034 input_set |= pf->fdir.input_set[pctype];
9035 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9036 I40E_INSET_MASK_NUM_REG);
9040 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9042 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9043 (uint32_t)(inset_reg & UINT32_MAX));
9044 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9045 (uint32_t)((inset_reg >>
9046 I40E_32_BIT_WIDTH) & UINT32_MAX));
9048 for (i = 0; i < num; i++)
9049 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
9051 /*clear unused mask registers of the pctype */
9052 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9053 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
9055 I40E_WRITE_FLUSH(hw);
9057 pf->fdir.input_set[pctype] = input_set;
9062 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9067 PMD_DRV_LOG(ERR, "Invalid pointer");
9071 switch (info->info_type) {
9072 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9073 i40e_get_symmetric_hash_enable_per_port(hw,
9074 &(info->info.enable));
9076 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9077 ret = i40e_get_hash_filter_global_config(hw,
9078 &(info->info.global_conf));
9081 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9091 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9096 PMD_DRV_LOG(ERR, "Invalid pointer");
9100 switch (info->info_type) {
9101 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9102 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9104 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9105 ret = i40e_set_hash_filter_global_config(hw,
9106 &(info->info.global_conf));
9108 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9109 ret = i40e_hash_filter_inset_select(hw,
9110 &(info->info.input_set_conf));
9114 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9123 /* Operations for hash function */
9125 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9126 enum rte_filter_op filter_op,
9129 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9132 switch (filter_op) {
9133 case RTE_ETH_FILTER_NOP:
9135 case RTE_ETH_FILTER_GET:
9136 ret = i40e_hash_filter_get(hw,
9137 (struct rte_eth_hash_filter_info *)arg);
9139 case RTE_ETH_FILTER_SET:
9140 ret = i40e_hash_filter_set(hw,
9141 (struct rte_eth_hash_filter_info *)arg);
9144 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9153 /* Convert ethertype filter structure */
9155 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9156 struct i40e_ethertype_filter *filter)
9158 rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
9159 filter->input.ether_type = input->ether_type;
9160 filter->flags = input->flags;
9161 filter->queue = input->queue;
9166 /* Check if there exists the ehtertype filter */
9167 struct i40e_ethertype_filter *
9168 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9169 const struct i40e_ethertype_filter_input *input)
9173 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9177 return ethertype_rule->hash_map[ret];
9180 /* Add ethertype filter in SW list */
9182 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9183 struct i40e_ethertype_filter *filter)
9185 struct i40e_ethertype_rule *rule = &pf->ethertype;
9188 ret = rte_hash_add_key(rule->hash_table, &filter->input);
9191 "Failed to insert ethertype filter"
9192 " to hash table %d!",
9196 rule->hash_map[ret] = filter;
9198 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9203 /* Delete ethertype filter in SW list */
9205 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9206 struct i40e_ethertype_filter_input *input)
9208 struct i40e_ethertype_rule *rule = &pf->ethertype;
9209 struct i40e_ethertype_filter *filter;
9212 ret = rte_hash_del_key(rule->hash_table, input);
9215 "Failed to delete ethertype filter"
9216 " to hash table %d!",
9220 filter = rule->hash_map[ret];
9221 rule->hash_map[ret] = NULL;
9223 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9230 * Configure ethertype filter, which can director packet by filtering
9231 * with mac address and ether_type or only ether_type
9234 i40e_ethertype_filter_set(struct i40e_pf *pf,
9235 struct rte_eth_ethertype_filter *filter,
9238 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9239 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9240 struct i40e_ethertype_filter *ethertype_filter, *node;
9241 struct i40e_ethertype_filter check_filter;
9242 struct i40e_control_filter_stats stats;
9246 if (filter->queue >= pf->dev_data->nb_rx_queues) {
9247 PMD_DRV_LOG(ERR, "Invalid queue ID");
9250 if (filter->ether_type == ETHER_TYPE_IPv4 ||
9251 filter->ether_type == ETHER_TYPE_IPv6) {
9253 "unsupported ether_type(0x%04x) in control packet filter.",
9254 filter->ether_type);
9257 if (filter->ether_type == ETHER_TYPE_VLAN)
9258 PMD_DRV_LOG(WARNING,
9259 "filter vlan ether_type in first tag is not supported.");
9261 /* Check if there is the filter in SW list */
9262 memset(&check_filter, 0, sizeof(check_filter));
9263 i40e_ethertype_filter_convert(filter, &check_filter);
9264 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9265 &check_filter.input);
9267 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9271 if (!add && !node) {
9272 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9276 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9277 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9278 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9279 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9280 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9282 memset(&stats, 0, sizeof(stats));
9283 ret = i40e_aq_add_rem_control_packet_filter(hw,
9284 filter->mac_addr.addr_bytes,
9285 filter->ether_type, flags,
9287 filter->queue, add, &stats, NULL);
9290 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9291 ret, stats.mac_etype_used, stats.etype_used,
9292 stats.mac_etype_free, stats.etype_free);
9296 /* Add or delete a filter in SW list */
9298 ethertype_filter = rte_zmalloc("ethertype_filter",
9299 sizeof(*ethertype_filter), 0);
9300 rte_memcpy(ethertype_filter, &check_filter,
9301 sizeof(check_filter));
9302 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9304 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9311 * Handle operations for ethertype filter.
9314 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9315 enum rte_filter_op filter_op,
9318 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9321 if (filter_op == RTE_ETH_FILTER_NOP)
9325 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9330 switch (filter_op) {
9331 case RTE_ETH_FILTER_ADD:
9332 ret = i40e_ethertype_filter_set(pf,
9333 (struct rte_eth_ethertype_filter *)arg,
9336 case RTE_ETH_FILTER_DELETE:
9337 ret = i40e_ethertype_filter_set(pf,
9338 (struct rte_eth_ethertype_filter *)arg,
9342 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9350 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9351 enum rte_filter_type filter_type,
9352 enum rte_filter_op filter_op,
9360 switch (filter_type) {
9361 case RTE_ETH_FILTER_NONE:
9362 /* For global configuration */
9363 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9365 case RTE_ETH_FILTER_HASH:
9366 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9368 case RTE_ETH_FILTER_MACVLAN:
9369 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9371 case RTE_ETH_FILTER_ETHERTYPE:
9372 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9374 case RTE_ETH_FILTER_TUNNEL:
9375 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9377 case RTE_ETH_FILTER_FDIR:
9378 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9380 case RTE_ETH_FILTER_GENERIC:
9381 if (filter_op != RTE_ETH_FILTER_GET)
9383 *(const void **)arg = &i40e_flow_ops;
9386 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9396 * Check and enable Extended Tag.
9397 * Enabling Extended Tag is important for 40G performance.
9400 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9402 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9406 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9409 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9413 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9414 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9419 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9422 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9426 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9427 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9430 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9431 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9434 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9441 * As some registers wouldn't be reset unless a global hardware reset,
9442 * hardware initialization is needed to put those registers into an
9443 * expected initial state.
9446 i40e_hw_init(struct rte_eth_dev *dev)
9448 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9450 i40e_enable_extended_tag(dev);
9452 /* clear the PF Queue Filter control register */
9453 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9455 /* Disable symmetric hash per port */
9456 i40e_set_symmetric_hash_enable_per_port(hw, 0);
9460 * For X722 it is possible to have multiple pctypes mapped to the same flowtype
9461 * however this function will return only one highest pctype index,
9462 * which is not quite correct. This is known problem of i40e driver
9463 * and needs to be fixed later.
9465 enum i40e_filter_pctype
9466 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
9469 uint64_t pctype_mask;
9471 if (flow_type < I40E_FLOW_TYPE_MAX) {
9472 pctype_mask = adapter->pctypes_tbl[flow_type];
9473 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
9474 if (pctype_mask & (1ULL << i))
9475 return (enum i40e_filter_pctype)i;
9478 return I40E_FILTER_PCTYPE_INVALID;
9482 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
9483 enum i40e_filter_pctype pctype)
9486 uint64_t pctype_mask = 1ULL << pctype;
9488 for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
9490 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
9494 return RTE_ETH_FLOW_UNKNOWN;
9498 * On X710, performance number is far from the expectation on recent firmware
9499 * versions; on XL710, performance number is also far from the expectation on
9500 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9501 * mode is enabled and port MAC address is equal to the packet destination MAC
9502 * address. The fix for this issue may not be integrated in the following
9503 * firmware version. So the workaround in software driver is needed. It needs
9504 * to modify the initial values of 3 internal only registers for both X710 and
9505 * XL710. Note that the values for X710 or XL710 could be different, and the
9506 * workaround can be removed when it is fixed in firmware in the future.
9509 /* For both X710 and XL710 */
9510 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1 0x10000200
9511 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x203F0200
9512 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
9514 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9515 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
9518 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9519 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9522 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
9524 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
9525 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
9528 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9530 enum i40e_status_code status;
9531 struct i40e_aq_get_phy_abilities_resp phy_ab;
9535 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9539 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
9542 rte_delay_us(100000);
9544 status = i40e_aq_get_phy_capabilities(hw, false,
9545 true, &phy_ab, NULL);
9553 i40e_configure_registers(struct i40e_hw *hw)
9559 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9560 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9561 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9567 for (i = 0; i < RTE_DIM(reg_table); i++) {
9568 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9569 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9571 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9572 else /* For X710/XL710/XXV710 */
9573 if (hw->aq.fw_maj_ver < 6)
9575 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
9578 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
9581 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9582 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9584 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9585 else /* For X710/XL710/XXV710 */
9587 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9590 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9591 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9592 I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9594 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9597 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9600 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9603 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9607 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9608 reg_table[i].addr, reg);
9609 if (reg == reg_table[i].val)
9612 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9613 reg_table[i].val, NULL);
9616 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9617 reg_table[i].val, reg_table[i].addr);
9620 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9621 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9625 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
9626 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
9627 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
9628 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9630 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9635 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9636 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9640 /* Configure for double VLAN RX stripping */
9641 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9642 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9643 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9644 ret = i40e_aq_debug_write_register(hw,
9645 I40E_VSI_TSR(vsi->vsi_id),
9648 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9650 return I40E_ERR_CONFIG;
9654 /* Configure for double VLAN TX insertion */
9655 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9656 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9657 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9658 ret = i40e_aq_debug_write_register(hw,
9659 I40E_VSI_L2TAGSTXVALID(
9660 vsi->vsi_id), reg, NULL);
9663 "Failed to update VSI_L2TAGSTXVALID[%d]",
9665 return I40E_ERR_CONFIG;
9673 * i40e_aq_add_mirror_rule
9674 * @hw: pointer to the hardware structure
9675 * @seid: VEB seid to add mirror rule to
9676 * @dst_id: destination vsi seid
9677 * @entries: Buffer which contains the entities to be mirrored
9678 * @count: number of entities contained in the buffer
9679 * @rule_id:the rule_id of the rule to be added
9681 * Add a mirror rule for a given veb.
9684 static enum i40e_status_code
9685 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9686 uint16_t seid, uint16_t dst_id,
9687 uint16_t rule_type, uint16_t *entries,
9688 uint16_t count, uint16_t *rule_id)
9690 struct i40e_aq_desc desc;
9691 struct i40e_aqc_add_delete_mirror_rule cmd;
9692 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9693 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9696 enum i40e_status_code status;
9698 i40e_fill_default_direct_cmd_desc(&desc,
9699 i40e_aqc_opc_add_mirror_rule);
9700 memset(&cmd, 0, sizeof(cmd));
9702 buff_len = sizeof(uint16_t) * count;
9703 desc.datalen = rte_cpu_to_le_16(buff_len);
9705 desc.flags |= rte_cpu_to_le_16(
9706 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9707 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9708 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9709 cmd.num_entries = rte_cpu_to_le_16(count);
9710 cmd.seid = rte_cpu_to_le_16(seid);
9711 cmd.destination = rte_cpu_to_le_16(dst_id);
9713 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9714 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9716 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9717 hw->aq.asq_last_status, resp->rule_id,
9718 resp->mirror_rules_used, resp->mirror_rules_free);
9719 *rule_id = rte_le_to_cpu_16(resp->rule_id);
9725 * i40e_aq_del_mirror_rule
9726 * @hw: pointer to the hardware structure
9727 * @seid: VEB seid to add mirror rule to
9728 * @entries: Buffer which contains the entities to be mirrored
9729 * @count: number of entities contained in the buffer
9730 * @rule_id:the rule_id of the rule to be delete
9732 * Delete a mirror rule for a given veb.
9735 static enum i40e_status_code
9736 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9737 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9738 uint16_t count, uint16_t rule_id)
9740 struct i40e_aq_desc desc;
9741 struct i40e_aqc_add_delete_mirror_rule cmd;
9742 uint16_t buff_len = 0;
9743 enum i40e_status_code status;
9746 i40e_fill_default_direct_cmd_desc(&desc,
9747 i40e_aqc_opc_delete_mirror_rule);
9748 memset(&cmd, 0, sizeof(cmd));
9749 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9750 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9752 cmd.num_entries = count;
9753 buff_len = sizeof(uint16_t) * count;
9754 desc.datalen = rte_cpu_to_le_16(buff_len);
9755 buff = (void *)entries;
9757 /* rule id is filled in destination field for deleting mirror rule */
9758 cmd.destination = rte_cpu_to_le_16(rule_id);
9760 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9761 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9762 cmd.seid = rte_cpu_to_le_16(seid);
9764 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9765 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9771 * i40e_mirror_rule_set
9772 * @dev: pointer to the hardware structure
9773 * @mirror_conf: mirror rule info
9774 * @sw_id: mirror rule's sw_id
9775 * @on: enable/disable
9777 * set a mirror rule.
9781 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9782 struct rte_eth_mirror_conf *mirror_conf,
9783 uint8_t sw_id, uint8_t on)
9785 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9786 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9787 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9788 struct i40e_mirror_rule *parent = NULL;
9789 uint16_t seid, dst_seid, rule_id;
9793 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9795 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9797 "mirror rule can not be configured without veb or vfs.");
9800 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9801 PMD_DRV_LOG(ERR, "mirror table is full.");
9804 if (mirror_conf->dst_pool > pf->vf_num) {
9805 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9806 mirror_conf->dst_pool);
9810 seid = pf->main_vsi->veb->seid;
9812 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9813 if (sw_id <= it->index) {
9819 if (mirr_rule && sw_id == mirr_rule->index) {
9821 PMD_DRV_LOG(ERR, "mirror rule exists.");
9824 ret = i40e_aq_del_mirror_rule(hw, seid,
9825 mirr_rule->rule_type,
9827 mirr_rule->num_entries, mirr_rule->id);
9830 "failed to remove mirror rule: ret = %d, aq_err = %d.",
9831 ret, hw->aq.asq_last_status);
9834 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9835 rte_free(mirr_rule);
9836 pf->nb_mirror_rule--;
9840 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9844 mirr_rule = rte_zmalloc("i40e_mirror_rule",
9845 sizeof(struct i40e_mirror_rule) , 0);
9847 PMD_DRV_LOG(ERR, "failed to allocate memory");
9848 return I40E_ERR_NO_MEMORY;
9850 switch (mirror_conf->rule_type) {
9851 case ETH_MIRROR_VLAN:
9852 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9853 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9854 mirr_rule->entries[j] =
9855 mirror_conf->vlan.vlan_id[i];
9860 PMD_DRV_LOG(ERR, "vlan is not specified.");
9861 rte_free(mirr_rule);
9864 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9866 case ETH_MIRROR_VIRTUAL_POOL_UP:
9867 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9868 /* check if the specified pool bit is out of range */
9869 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9870 PMD_DRV_LOG(ERR, "pool mask is out of range.");
9871 rte_free(mirr_rule);
9874 for (i = 0, j = 0; i < pf->vf_num; i++) {
9875 if (mirror_conf->pool_mask & (1ULL << i)) {
9876 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9880 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9881 /* add pf vsi to entries */
9882 mirr_rule->entries[j] = pf->main_vsi_seid;
9886 PMD_DRV_LOG(ERR, "pool is not specified.");
9887 rte_free(mirr_rule);
9890 /* egress and ingress in aq commands means from switch but not port */
9891 mirr_rule->rule_type =
9892 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9893 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9894 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9896 case ETH_MIRROR_UPLINK_PORT:
9897 /* egress and ingress in aq commands means from switch but not port*/
9898 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9900 case ETH_MIRROR_DOWNLINK_PORT:
9901 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9904 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9905 mirror_conf->rule_type);
9906 rte_free(mirr_rule);
9910 /* If the dst_pool is equal to vf_num, consider it as PF */
9911 if (mirror_conf->dst_pool == pf->vf_num)
9912 dst_seid = pf->main_vsi_seid;
9914 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9916 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9917 mirr_rule->rule_type, mirr_rule->entries,
9921 "failed to add mirror rule: ret = %d, aq_err = %d.",
9922 ret, hw->aq.asq_last_status);
9923 rte_free(mirr_rule);
9927 mirr_rule->index = sw_id;
9928 mirr_rule->num_entries = j;
9929 mirr_rule->id = rule_id;
9930 mirr_rule->dst_vsi_seid = dst_seid;
9933 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9935 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9937 pf->nb_mirror_rule++;
9942 * i40e_mirror_rule_reset
9943 * @dev: pointer to the device
9944 * @sw_id: mirror rule's sw_id
9946 * reset a mirror rule.
9950 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9952 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9953 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9954 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9958 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9960 seid = pf->main_vsi->veb->seid;
9962 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9963 if (sw_id == it->index) {
9969 ret = i40e_aq_del_mirror_rule(hw, seid,
9970 mirr_rule->rule_type,
9972 mirr_rule->num_entries, mirr_rule->id);
9975 "failed to remove mirror rule: status = %d, aq_err = %d.",
9976 ret, hw->aq.asq_last_status);
9979 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9980 rte_free(mirr_rule);
9981 pf->nb_mirror_rule--;
9983 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9990 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9992 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9993 uint64_t systim_cycles;
9995 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9996 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9999 return systim_cycles;
10003 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10005 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10006 uint64_t rx_tstamp;
10008 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10009 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10016 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10018 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10019 uint64_t tx_tstamp;
10021 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10022 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10029 i40e_start_timecounters(struct rte_eth_dev *dev)
10031 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10032 struct i40e_adapter *adapter =
10033 (struct i40e_adapter *)dev->data->dev_private;
10034 struct rte_eth_link link;
10035 uint32_t tsync_inc_l;
10036 uint32_t tsync_inc_h;
10038 /* Get current link speed. */
10039 memset(&link, 0, sizeof(link));
10040 i40e_dev_link_update(dev, 1);
10041 rte_i40e_dev_atomic_read_link_status(dev, &link);
10043 switch (link.link_speed) {
10044 case ETH_SPEED_NUM_40G:
10045 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10046 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10048 case ETH_SPEED_NUM_10G:
10049 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10050 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10052 case ETH_SPEED_NUM_1G:
10053 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10054 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10061 /* Set the timesync increment value. */
10062 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10063 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10065 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10066 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10067 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10069 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10070 adapter->systime_tc.cc_shift = 0;
10071 adapter->systime_tc.nsec_mask = 0;
10073 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10074 adapter->rx_tstamp_tc.cc_shift = 0;
10075 adapter->rx_tstamp_tc.nsec_mask = 0;
10077 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10078 adapter->tx_tstamp_tc.cc_shift = 0;
10079 adapter->tx_tstamp_tc.nsec_mask = 0;
10083 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10085 struct i40e_adapter *adapter =
10086 (struct i40e_adapter *)dev->data->dev_private;
10088 adapter->systime_tc.nsec += delta;
10089 adapter->rx_tstamp_tc.nsec += delta;
10090 adapter->tx_tstamp_tc.nsec += delta;
10096 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10099 struct i40e_adapter *adapter =
10100 (struct i40e_adapter *)dev->data->dev_private;
10102 ns = rte_timespec_to_ns(ts);
10104 /* Set the timecounters to a new value. */
10105 adapter->systime_tc.nsec = ns;
10106 adapter->rx_tstamp_tc.nsec = ns;
10107 adapter->tx_tstamp_tc.nsec = ns;
10113 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10115 uint64_t ns, systime_cycles;
10116 struct i40e_adapter *adapter =
10117 (struct i40e_adapter *)dev->data->dev_private;
10119 systime_cycles = i40e_read_systime_cyclecounter(dev);
10120 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10121 *ts = rte_ns_to_timespec(ns);
10127 i40e_timesync_enable(struct rte_eth_dev *dev)
10129 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10130 uint32_t tsync_ctl_l;
10131 uint32_t tsync_ctl_h;
10133 /* Stop the timesync system time. */
10134 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10135 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10136 /* Reset the timesync system time value. */
10137 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10138 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10140 i40e_start_timecounters(dev);
10142 /* Clear timesync registers. */
10143 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10144 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10145 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10146 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10147 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10148 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10150 /* Enable timestamping of PTP packets. */
10151 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10152 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10154 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10155 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10156 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10158 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10159 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10165 i40e_timesync_disable(struct rte_eth_dev *dev)
10167 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10168 uint32_t tsync_ctl_l;
10169 uint32_t tsync_ctl_h;
10171 /* Disable timestamping of transmitted PTP packets. */
10172 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10173 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10175 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10176 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10178 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10179 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10181 /* Reset the timesync increment value. */
10182 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10183 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10189 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10190 struct timespec *timestamp, uint32_t flags)
10192 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10193 struct i40e_adapter *adapter =
10194 (struct i40e_adapter *)dev->data->dev_private;
10196 uint32_t sync_status;
10197 uint32_t index = flags & 0x03;
10198 uint64_t rx_tstamp_cycles;
10201 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10202 if ((sync_status & (1 << index)) == 0)
10205 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10206 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10207 *timestamp = rte_ns_to_timespec(ns);
10213 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10214 struct timespec *timestamp)
10216 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10217 struct i40e_adapter *adapter =
10218 (struct i40e_adapter *)dev->data->dev_private;
10220 uint32_t sync_status;
10221 uint64_t tx_tstamp_cycles;
10224 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10225 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10228 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10229 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10230 *timestamp = rte_ns_to_timespec(ns);
10236 * i40e_parse_dcb_configure - parse dcb configure from user
10237 * @dev: the device being configured
10238 * @dcb_cfg: pointer of the result of parse
10239 * @*tc_map: bit map of enabled traffic classes
10241 * Returns 0 on success, negative value on failure
10244 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10245 struct i40e_dcbx_config *dcb_cfg,
10248 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10249 uint8_t i, tc_bw, bw_lf;
10251 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10253 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10254 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10255 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10259 /* assume each tc has the same bw */
10260 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10261 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10262 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10263 /* to ensure the sum of tcbw is equal to 100 */
10264 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10265 for (i = 0; i < bw_lf; i++)
10266 dcb_cfg->etscfg.tcbwtable[i]++;
10268 /* assume each tc has the same Transmission Selection Algorithm */
10269 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10270 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10272 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10273 dcb_cfg->etscfg.prioritytable[i] =
10274 dcb_rx_conf->dcb_tc[i];
10276 /* FW needs one App to configure HW */
10277 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10278 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10279 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10280 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10282 if (dcb_rx_conf->nb_tcs == 0)
10283 *tc_map = 1; /* tc0 only */
10285 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10287 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10288 dcb_cfg->pfc.willing = 0;
10289 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10290 dcb_cfg->pfc.pfcenable = *tc_map;
10296 static enum i40e_status_code
10297 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10298 struct i40e_aqc_vsi_properties_data *info,
10299 uint8_t enabled_tcmap)
10301 enum i40e_status_code ret;
10302 int i, total_tc = 0;
10303 uint16_t qpnum_per_tc, bsf, qp_idx;
10304 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10305 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10306 uint16_t used_queues;
10308 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10309 if (ret != I40E_SUCCESS)
10312 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10313 if (enabled_tcmap & (1 << i))
10318 vsi->enabled_tc = enabled_tcmap;
10320 /* different VSI has different queues assigned */
10321 if (vsi->type == I40E_VSI_MAIN)
10322 used_queues = dev_data->nb_rx_queues -
10323 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10324 else if (vsi->type == I40E_VSI_VMDQ2)
10325 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10327 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10328 return I40E_ERR_NO_AVAILABLE_VSI;
10331 qpnum_per_tc = used_queues / total_tc;
10332 /* Number of queues per enabled TC */
10333 if (qpnum_per_tc == 0) {
10334 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10335 return I40E_ERR_INVALID_QP_ID;
10337 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10338 I40E_MAX_Q_PER_TC);
10339 bsf = rte_bsf32(qpnum_per_tc);
10342 * Configure TC and queue mapping parameters, for enabled TC,
10343 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10344 * default queue will serve it.
10347 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10348 if (vsi->enabled_tc & (1 << i)) {
10349 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10350 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10351 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10352 qp_idx += qpnum_per_tc;
10354 info->tc_mapping[i] = 0;
10357 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10358 if (vsi->type == I40E_VSI_SRIOV) {
10359 info->mapping_flags |=
10360 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10361 for (i = 0; i < vsi->nb_qps; i++)
10362 info->queue_mapping[i] =
10363 rte_cpu_to_le_16(vsi->base_queue + i);
10365 info->mapping_flags |=
10366 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10367 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10369 info->valid_sections |=
10370 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10372 return I40E_SUCCESS;
10376 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10377 * @veb: VEB to be configured
10378 * @tc_map: enabled TC bitmap
10380 * Returns 0 on success, negative value on failure
10382 static enum i40e_status_code
10383 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10385 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10386 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10387 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10388 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10389 enum i40e_status_code ret = I40E_SUCCESS;
10393 /* Check if enabled_tc is same as existing or new TCs */
10394 if (veb->enabled_tc == tc_map)
10397 /* configure tc bandwidth */
10398 memset(&veb_bw, 0, sizeof(veb_bw));
10399 veb_bw.tc_valid_bits = tc_map;
10400 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10401 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10402 if (tc_map & BIT_ULL(i))
10403 veb_bw.tc_bw_share_credits[i] = 1;
10405 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10409 "AQ command Config switch_comp BW allocation per TC failed = %d",
10410 hw->aq.asq_last_status);
10414 memset(&ets_query, 0, sizeof(ets_query));
10415 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10417 if (ret != I40E_SUCCESS) {
10419 "Failed to get switch_comp ETS configuration %u",
10420 hw->aq.asq_last_status);
10423 memset(&bw_query, 0, sizeof(bw_query));
10424 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10426 if (ret != I40E_SUCCESS) {
10428 "Failed to get switch_comp bandwidth configuration %u",
10429 hw->aq.asq_last_status);
10433 /* store and print out BW info */
10434 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10435 veb->bw_info.bw_max = ets_query.tc_bw_max;
10436 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10437 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10438 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10439 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10440 I40E_16_BIT_WIDTH);
10441 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10442 veb->bw_info.bw_ets_share_credits[i] =
10443 bw_query.tc_bw_share_credits[i];
10444 veb->bw_info.bw_ets_credits[i] =
10445 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10446 /* 4 bits per TC, 4th bit is reserved */
10447 veb->bw_info.bw_ets_max[i] =
10448 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10449 RTE_LEN2MASK(3, uint8_t));
10450 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10451 veb->bw_info.bw_ets_share_credits[i]);
10452 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10453 veb->bw_info.bw_ets_credits[i]);
10454 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10455 veb->bw_info.bw_ets_max[i]);
10458 veb->enabled_tc = tc_map;
10465 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10466 * @vsi: VSI to be configured
10467 * @tc_map: enabled TC bitmap
10469 * Returns 0 on success, negative value on failure
10471 static enum i40e_status_code
10472 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10474 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10475 struct i40e_vsi_context ctxt;
10476 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10477 enum i40e_status_code ret = I40E_SUCCESS;
10480 /* Check if enabled_tc is same as existing or new TCs */
10481 if (vsi->enabled_tc == tc_map)
10484 /* configure tc bandwidth */
10485 memset(&bw_data, 0, sizeof(bw_data));
10486 bw_data.tc_valid_bits = tc_map;
10487 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10488 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10489 if (tc_map & BIT_ULL(i))
10490 bw_data.tc_bw_credits[i] = 1;
10492 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10495 "AQ command Config VSI BW allocation per TC failed = %d",
10496 hw->aq.asq_last_status);
10499 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10500 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10502 /* Update Queue Pairs Mapping for currently enabled UPs */
10503 ctxt.seid = vsi->seid;
10504 ctxt.pf_num = hw->pf_id;
10506 ctxt.uplink_seid = vsi->uplink_seid;
10507 ctxt.info = vsi->info;
10509 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10513 /* Update the VSI after updating the VSI queue-mapping information */
10514 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10516 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10517 hw->aq.asq_last_status);
10520 /* update the local VSI info with updated queue map */
10521 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10522 sizeof(vsi->info.tc_mapping));
10523 rte_memcpy(&vsi->info.queue_mapping,
10524 &ctxt.info.queue_mapping,
10525 sizeof(vsi->info.queue_mapping));
10526 vsi->info.mapping_flags = ctxt.info.mapping_flags;
10527 vsi->info.valid_sections = 0;
10529 /* query and update current VSI BW information */
10530 ret = i40e_vsi_get_bw_config(vsi);
10533 "Failed updating vsi bw info, err %s aq_err %s",
10534 i40e_stat_str(hw, ret),
10535 i40e_aq_str(hw, hw->aq.asq_last_status));
10539 vsi->enabled_tc = tc_map;
10546 * i40e_dcb_hw_configure - program the dcb setting to hw
10547 * @pf: pf the configuration is taken on
10548 * @new_cfg: new configuration
10549 * @tc_map: enabled TC bitmap
10551 * Returns 0 on success, negative value on failure
10553 static enum i40e_status_code
10554 i40e_dcb_hw_configure(struct i40e_pf *pf,
10555 struct i40e_dcbx_config *new_cfg,
10558 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10559 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10560 struct i40e_vsi *main_vsi = pf->main_vsi;
10561 struct i40e_vsi_list *vsi_list;
10562 enum i40e_status_code ret;
10566 /* Use the FW API if FW > v4.4*/
10567 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10568 (hw->aq.fw_maj_ver >= 5))) {
10570 "FW < v4.4, can not use FW LLDP API to configure DCB");
10571 return I40E_ERR_FIRMWARE_API_VERSION;
10574 /* Check if need reconfiguration */
10575 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10576 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10577 return I40E_SUCCESS;
10580 /* Copy the new config to the current config */
10581 *old_cfg = *new_cfg;
10582 old_cfg->etsrec = old_cfg->etscfg;
10583 ret = i40e_set_dcb_config(hw);
10585 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10586 i40e_stat_str(hw, ret),
10587 i40e_aq_str(hw, hw->aq.asq_last_status));
10590 /* set receive Arbiter to RR mode and ETS scheme by default */
10591 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10592 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10593 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
10594 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10595 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10596 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10597 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10598 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10599 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10600 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10601 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10602 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10603 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10605 /* get local mib to check whether it is configured correctly */
10607 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10608 /* Get Local DCB Config */
10609 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10610 &hw->local_dcbx_config);
10612 /* if Veb is created, need to update TC of it at first */
10613 if (main_vsi->veb) {
10614 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10616 PMD_INIT_LOG(WARNING,
10617 "Failed configuring TC for VEB seid=%d",
10618 main_vsi->veb->seid);
10620 /* Update each VSI */
10621 i40e_vsi_config_tc(main_vsi, tc_map);
10622 if (main_vsi->veb) {
10623 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10624 /* Beside main VSI and VMDQ VSIs, only enable default
10625 * TC for other VSIs
10627 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10628 ret = i40e_vsi_config_tc(vsi_list->vsi,
10631 ret = i40e_vsi_config_tc(vsi_list->vsi,
10632 I40E_DEFAULT_TCMAP);
10634 PMD_INIT_LOG(WARNING,
10635 "Failed configuring TC for VSI seid=%d",
10636 vsi_list->vsi->seid);
10640 return I40E_SUCCESS;
10644 * i40e_dcb_init_configure - initial dcb config
10645 * @dev: device being configured
10646 * @sw_dcb: indicate whether dcb is sw configured or hw offload
10648 * Returns 0 on success, negative value on failure
10651 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10653 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10654 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10657 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10658 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10662 /* DCB initialization:
10663 * Update DCB configuration from the Firmware and configure
10664 * LLDP MIB change event.
10666 if (sw_dcb == TRUE) {
10667 ret = i40e_init_dcb(hw);
10668 /* If lldp agent is stopped, the return value from
10669 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10670 * adminq status. Otherwise, it should return success.
10672 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10673 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10674 memset(&hw->local_dcbx_config, 0,
10675 sizeof(struct i40e_dcbx_config));
10676 /* set dcb default configuration */
10677 hw->local_dcbx_config.etscfg.willing = 0;
10678 hw->local_dcbx_config.etscfg.maxtcs = 0;
10679 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10680 hw->local_dcbx_config.etscfg.tsatable[0] =
10682 /* all UPs mapping to TC0 */
10683 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10684 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10685 hw->local_dcbx_config.etsrec =
10686 hw->local_dcbx_config.etscfg;
10687 hw->local_dcbx_config.pfc.willing = 0;
10688 hw->local_dcbx_config.pfc.pfccap =
10689 I40E_MAX_TRAFFIC_CLASS;
10690 /* FW needs one App to configure HW */
10691 hw->local_dcbx_config.numapps = 1;
10692 hw->local_dcbx_config.app[0].selector =
10693 I40E_APP_SEL_ETHTYPE;
10694 hw->local_dcbx_config.app[0].priority = 3;
10695 hw->local_dcbx_config.app[0].protocolid =
10696 I40E_APP_PROTOID_FCOE;
10697 ret = i40e_set_dcb_config(hw);
10700 "default dcb config fails. err = %d, aq_err = %d.",
10701 ret, hw->aq.asq_last_status);
10706 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10707 ret, hw->aq.asq_last_status);
10711 ret = i40e_aq_start_lldp(hw, NULL);
10712 if (ret != I40E_SUCCESS)
10713 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10715 ret = i40e_init_dcb(hw);
10717 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10719 "HW doesn't support DCBX offload.");
10724 "DCBX configuration failed, err = %d, aq_err = %d.",
10725 ret, hw->aq.asq_last_status);
10733 * i40e_dcb_setup - setup dcb related config
10734 * @dev: device being configured
10736 * Returns 0 on success, negative value on failure
10739 i40e_dcb_setup(struct rte_eth_dev *dev)
10741 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10742 struct i40e_dcbx_config dcb_cfg;
10743 uint8_t tc_map = 0;
10746 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10747 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10751 if (pf->vf_num != 0)
10752 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10754 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10756 PMD_INIT_LOG(ERR, "invalid dcb config");
10759 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10761 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10769 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10770 struct rte_eth_dcb_info *dcb_info)
10772 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10773 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10774 struct i40e_vsi *vsi = pf->main_vsi;
10775 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10776 uint16_t bsf, tc_mapping;
10779 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10780 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10782 dcb_info->nb_tcs = 1;
10783 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10784 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10785 for (i = 0; i < dcb_info->nb_tcs; i++)
10786 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10788 /* get queue mapping if vmdq is disabled */
10789 if (!pf->nb_cfg_vmdq_vsi) {
10790 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10791 if (!(vsi->enabled_tc & (1 << i)))
10793 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10794 dcb_info->tc_queue.tc_rxq[j][i].base =
10795 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10796 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10797 dcb_info->tc_queue.tc_txq[j][i].base =
10798 dcb_info->tc_queue.tc_rxq[j][i].base;
10799 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10800 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10801 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10802 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10803 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10808 /* get queue mapping if vmdq is enabled */
10810 vsi = pf->vmdq[j].vsi;
10811 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10812 if (!(vsi->enabled_tc & (1 << i)))
10814 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10815 dcb_info->tc_queue.tc_rxq[j][i].base =
10816 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10817 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10818 dcb_info->tc_queue.tc_txq[j][i].base =
10819 dcb_info->tc_queue.tc_rxq[j][i].base;
10820 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10821 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10822 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10823 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10824 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10827 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10832 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10834 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10835 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10836 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10837 uint16_t interval =
10838 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL, 1);
10839 uint16_t msix_intr;
10841 msix_intr = intr_handle->intr_vec[queue_id];
10842 if (msix_intr == I40E_MISC_VEC_ID)
10843 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10844 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10845 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10846 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10848 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10851 I40E_PFINT_DYN_CTLN(msix_intr -
10852 I40E_RX_VEC_START),
10853 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10854 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10855 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10857 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10859 I40E_WRITE_FLUSH(hw);
10860 rte_intr_enable(&pci_dev->intr_handle);
10866 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10868 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10869 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10870 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10871 uint16_t msix_intr;
10873 msix_intr = intr_handle->intr_vec[queue_id];
10874 if (msix_intr == I40E_MISC_VEC_ID)
10875 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10878 I40E_PFINT_DYN_CTLN(msix_intr -
10879 I40E_RX_VEC_START),
10881 I40E_WRITE_FLUSH(hw);
10886 static int i40e_get_regs(struct rte_eth_dev *dev,
10887 struct rte_dev_reg_info *regs)
10889 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10890 uint32_t *ptr_data = regs->data;
10891 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10892 const struct i40e_reg_info *reg_info;
10894 if (ptr_data == NULL) {
10895 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10896 regs->width = sizeof(uint32_t);
10900 /* The first few registers have to be read using AQ operations */
10902 while (i40e_regs_adminq[reg_idx].name) {
10903 reg_info = &i40e_regs_adminq[reg_idx++];
10904 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10906 arr_idx2 <= reg_info->count2;
10908 reg_offset = arr_idx * reg_info->stride1 +
10909 arr_idx2 * reg_info->stride2;
10910 reg_offset += reg_info->base_addr;
10911 ptr_data[reg_offset >> 2] =
10912 i40e_read_rx_ctl(hw, reg_offset);
10916 /* The remaining registers can be read using primitives */
10918 while (i40e_regs_others[reg_idx].name) {
10919 reg_info = &i40e_regs_others[reg_idx++];
10920 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10922 arr_idx2 <= reg_info->count2;
10924 reg_offset = arr_idx * reg_info->stride1 +
10925 arr_idx2 * reg_info->stride2;
10926 reg_offset += reg_info->base_addr;
10927 ptr_data[reg_offset >> 2] =
10928 I40E_READ_REG(hw, reg_offset);
10935 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10937 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10939 /* Convert word count to byte count */
10940 return hw->nvm.sr_size << 1;
10943 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10944 struct rte_dev_eeprom_info *eeprom)
10946 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10947 uint16_t *data = eeprom->data;
10948 uint16_t offset, length, cnt_words;
10951 offset = eeprom->offset >> 1;
10952 length = eeprom->length >> 1;
10953 cnt_words = length;
10955 if (offset > hw->nvm.sr_size ||
10956 offset + length > hw->nvm.sr_size) {
10957 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10961 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10963 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10964 if (ret_code != I40E_SUCCESS || cnt_words != length) {
10965 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10972 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10973 struct ether_addr *mac_addr)
10975 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10976 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10977 struct i40e_vsi *vsi = pf->main_vsi;
10978 struct i40e_mac_filter_info mac_filter;
10979 struct i40e_mac_filter *f;
10982 if (!is_valid_assigned_ether_addr(mac_addr)) {
10983 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10987 TAILQ_FOREACH(f, &vsi->mac_list, next) {
10988 if (is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
10993 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
10997 mac_filter = f->mac_info;
10998 ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
10999 if (ret != I40E_SUCCESS) {
11000 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11003 memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11004 ret = i40e_vsi_add_mac(vsi, &mac_filter);
11005 if (ret != I40E_SUCCESS) {
11006 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11009 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11011 /* Flags: 0x3 updates port address */
11012 i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
11016 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
11018 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11019 struct rte_eth_dev_data *dev_data = pf->dev_data;
11020 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
11023 /* check if mtu is within the allowed range */
11024 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
11027 /* mtu setting is forbidden if port is start */
11028 if (dev_data->dev_started) {
11029 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
11030 dev_data->port_id);
11034 if (frame_size > ETHER_MAX_LEN)
11035 dev_data->dev_conf.rxmode.jumbo_frame = 1;
11037 dev_data->dev_conf.rxmode.jumbo_frame = 0;
11039 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
11044 /* Restore ethertype filter */
11046 i40e_ethertype_filter_restore(struct i40e_pf *pf)
11048 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11049 struct i40e_ethertype_filter_list
11050 *ethertype_list = &pf->ethertype.ethertype_list;
11051 struct i40e_ethertype_filter *f;
11052 struct i40e_control_filter_stats stats;
11055 TAILQ_FOREACH(f, ethertype_list, rules) {
11057 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
11058 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
11059 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
11060 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
11061 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
11063 memset(&stats, 0, sizeof(stats));
11064 i40e_aq_add_rem_control_packet_filter(hw,
11065 f->input.mac_addr.addr_bytes,
11066 f->input.ether_type,
11067 flags, pf->main_vsi->seid,
11068 f->queue, 1, &stats, NULL);
11070 PMD_DRV_LOG(INFO, "Ethertype filter:"
11071 " mac_etype_used = %u, etype_used = %u,"
11072 " mac_etype_free = %u, etype_free = %u",
11073 stats.mac_etype_used, stats.etype_used,
11074 stats.mac_etype_free, stats.etype_free);
11077 /* Restore tunnel filter */
11079 i40e_tunnel_filter_restore(struct i40e_pf *pf)
11081 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11082 struct i40e_vsi *vsi;
11083 struct i40e_pf_vf *vf;
11084 struct i40e_tunnel_filter_list
11085 *tunnel_list = &pf->tunnel.tunnel_list;
11086 struct i40e_tunnel_filter *f;
11087 struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
11088 bool big_buffer = 0;
11090 TAILQ_FOREACH(f, tunnel_list, rules) {
11092 vsi = pf->main_vsi;
11094 vf = &pf->vfs[f->vf_id];
11097 memset(&cld_filter, 0, sizeof(cld_filter));
11098 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
11099 (struct ether_addr *)&cld_filter.element.outer_mac);
11100 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
11101 (struct ether_addr *)&cld_filter.element.inner_mac);
11102 cld_filter.element.inner_vlan = f->input.inner_vlan;
11103 cld_filter.element.flags = f->input.flags;
11104 cld_filter.element.tenant_id = f->input.tenant_id;
11105 cld_filter.element.queue_number = f->queue;
11106 rte_memcpy(cld_filter.general_fields,
11107 f->input.general_fields,
11108 sizeof(f->input.general_fields));
11110 if (((f->input.flags &
11111 I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
11112 I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
11114 I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
11115 I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
11117 I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
11118 I40E_AQC_ADD_CLOUD_FILTER_0X10))
11122 i40e_aq_add_cloud_filters_big_buffer(hw,
11123 vsi->seid, &cld_filter, 1);
11125 i40e_aq_add_cloud_filters(hw, vsi->seid,
11126 &cld_filter.element, 1);
11130 /* Restore rss filter */
11132 i40e_rss_filter_restore(struct i40e_pf *pf)
11134 struct i40e_rte_flow_rss_conf *conf =
11137 i40e_config_rss_filter(pf, conf, TRUE);
11141 i40e_filter_restore(struct i40e_pf *pf)
11143 i40e_ethertype_filter_restore(pf);
11144 i40e_tunnel_filter_restore(pf);
11145 i40e_fdir_filter_restore(pf);
11146 i40e_rss_filter_restore(pf);
11150 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
11152 if (strcmp(dev->device->driver->name, drv->driver.name))
11159 is_i40e_supported(struct rte_eth_dev *dev)
11161 return is_device_supported(dev, &rte_i40e_pmd);
11164 struct i40e_customized_pctype*
11165 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
11169 for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
11170 if (pf->customized_pctype[i].index == index)
11171 return &pf->customized_pctype[i];
11177 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
11178 uint32_t pkg_size, uint32_t proto_num,
11179 struct rte_pmd_i40e_proto_info *proto)
11181 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11182 uint32_t pctype_num;
11183 struct rte_pmd_i40e_ptype_info *pctype;
11184 uint32_t buff_size;
11185 struct i40e_customized_pctype *new_pctype = NULL;
11187 uint8_t pctype_value;
11192 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11193 (uint8_t *)&pctype_num, sizeof(pctype_num),
11194 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
11196 PMD_DRV_LOG(ERR, "Failed to get pctype number");
11200 PMD_DRV_LOG(INFO, "No new pctype added");
11204 buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
11205 pctype = rte_zmalloc("new_pctype", buff_size, 0);
11207 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11210 /* get information about new pctype list */
11211 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11212 (uint8_t *)pctype, buff_size,
11213 RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
11215 PMD_DRV_LOG(ERR, "Failed to get pctype list");
11220 /* Update customized pctype. */
11221 for (i = 0; i < pctype_num; i++) {
11222 pctype_value = pctype[i].ptype_id;
11223 memset(name, 0, sizeof(name));
11224 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11225 proto_id = pctype[i].protocols[j];
11226 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11228 for (n = 0; n < proto_num; n++) {
11229 if (proto[n].proto_id != proto_id)
11231 strcat(name, proto[n].name);
11236 name[strlen(name) - 1] = '\0';
11237 if (!strcmp(name, "GTPC"))
11239 i40e_find_customized_pctype(pf,
11240 I40E_CUSTOMIZED_GTPC);
11241 else if (!strcmp(name, "GTPU_IPV4"))
11243 i40e_find_customized_pctype(pf,
11244 I40E_CUSTOMIZED_GTPU_IPV4);
11245 else if (!strcmp(name, "GTPU_IPV6"))
11247 i40e_find_customized_pctype(pf,
11248 I40E_CUSTOMIZED_GTPU_IPV6);
11249 else if (!strcmp(name, "GTPU"))
11251 i40e_find_customized_pctype(pf,
11252 I40E_CUSTOMIZED_GTPU);
11254 new_pctype->pctype = pctype_value;
11255 new_pctype->valid = true;
11264 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
11265 uint32_t pkg_size, uint32_t proto_num,
11266 struct rte_pmd_i40e_proto_info *proto)
11268 struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
11269 uint16_t port_id = dev->data->port_id;
11270 uint32_t ptype_num;
11271 struct rte_pmd_i40e_ptype_info *ptype;
11272 uint32_t buff_size;
11274 char name[RTE_PMD_I40E_DDP_NAME_SIZE];
11279 /* get information about new ptype num */
11280 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11281 (uint8_t *)&ptype_num, sizeof(ptype_num),
11282 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
11284 PMD_DRV_LOG(ERR, "Failed to get ptype number");
11288 PMD_DRV_LOG(INFO, "No new ptype added");
11292 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
11293 ptype = rte_zmalloc("new_ptype", buff_size, 0);
11295 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11299 /* get information about new ptype list */
11300 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11301 (uint8_t *)ptype, buff_size,
11302 RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
11304 PMD_DRV_LOG(ERR, "Failed to get ptype list");
11309 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
11310 ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
11311 if (!ptype_mapping) {
11312 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11317 /* Update ptype mapping table. */
11318 for (i = 0; i < ptype_num; i++) {
11319 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
11320 ptype_mapping[i].sw_ptype = 0;
11322 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11323 proto_id = ptype[i].protocols[j];
11324 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11326 for (n = 0; n < proto_num; n++) {
11327 if (proto[n].proto_id != proto_id)
11329 memset(name, 0, sizeof(name));
11330 strcpy(name, proto[n].name);
11331 if (!strncmp(name, "PPPOE", 5))
11332 ptype_mapping[i].sw_ptype |=
11333 RTE_PTYPE_L2_ETHER_PPPOE;
11334 else if (!strncmp(name, "OIPV4", 5)) {
11335 ptype_mapping[i].sw_ptype |=
11336 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11338 } else if (!strncmp(name, "IPV4", 4) &&
11340 ptype_mapping[i].sw_ptype |=
11341 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11342 else if (!strncmp(name, "IPV4FRAG", 8) &&
11344 ptype_mapping[i].sw_ptype |=
11345 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11346 ptype_mapping[i].sw_ptype |=
11347 RTE_PTYPE_INNER_L4_FRAG;
11348 } else if (!strncmp(name, "IPV4", 4) &&
11350 ptype_mapping[i].sw_ptype |=
11351 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11352 else if (!strncmp(name, "OIPV6", 5)) {
11353 ptype_mapping[i].sw_ptype |=
11354 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11356 } else if (!strncmp(name, "IPV6", 4) &&
11358 ptype_mapping[i].sw_ptype |=
11359 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11360 else if (!strncmp(name, "IPV6FRAG", 8) &&
11362 ptype_mapping[i].sw_ptype |=
11363 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11364 ptype_mapping[i].sw_ptype |=
11365 RTE_PTYPE_INNER_L4_FRAG;
11366 } else if (!strncmp(name, "IPV6", 4) &&
11368 ptype_mapping[i].sw_ptype |=
11369 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11370 else if (!strncmp(name, "UDP", 3) && !in_tunnel)
11371 ptype_mapping[i].sw_ptype |=
11373 else if (!strncmp(name, "UDP", 3) && in_tunnel)
11374 ptype_mapping[i].sw_ptype |=
11375 RTE_PTYPE_INNER_L4_UDP;
11376 else if (!strncmp(name, "TCP", 3) && !in_tunnel)
11377 ptype_mapping[i].sw_ptype |=
11379 else if (!strncmp(name, "TCP", 3) && in_tunnel)
11380 ptype_mapping[i].sw_ptype |=
11381 RTE_PTYPE_INNER_L4_TCP;
11382 else if (!strncmp(name, "SCTP", 4) &&
11384 ptype_mapping[i].sw_ptype |=
11386 else if (!strncmp(name, "SCTP", 4) && in_tunnel)
11387 ptype_mapping[i].sw_ptype |=
11388 RTE_PTYPE_INNER_L4_SCTP;
11389 else if ((!strncmp(name, "ICMP", 4) ||
11390 !strncmp(name, "ICMPV6", 6)) &&
11392 ptype_mapping[i].sw_ptype |=
11394 else if ((!strncmp(name, "ICMP", 4) ||
11395 !strncmp(name, "ICMPV6", 6)) &&
11397 ptype_mapping[i].sw_ptype |=
11398 RTE_PTYPE_INNER_L4_ICMP;
11399 else if (!strncmp(name, "GTPC", 4)) {
11400 ptype_mapping[i].sw_ptype |=
11401 RTE_PTYPE_TUNNEL_GTPC;
11403 } else if (!strncmp(name, "GTPU", 4)) {
11404 ptype_mapping[i].sw_ptype |=
11405 RTE_PTYPE_TUNNEL_GTPU;
11407 } else if (!strncmp(name, "GRENAT", 6)) {
11408 ptype_mapping[i].sw_ptype |=
11409 RTE_PTYPE_TUNNEL_GRENAT;
11411 } else if (!strncmp(name, "L2TPv2CTL", 9)) {
11412 ptype_mapping[i].sw_ptype |=
11413 RTE_PTYPE_TUNNEL_L2TP;
11422 ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
11425 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
11427 rte_free(ptype_mapping);
11433 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
11436 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11437 uint32_t proto_num;
11438 struct rte_pmd_i40e_proto_info *proto;
11439 uint32_t buff_size;
11443 /* get information about protocol number */
11444 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11445 (uint8_t *)&proto_num, sizeof(proto_num),
11446 RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
11448 PMD_DRV_LOG(ERR, "Failed to get protocol number");
11452 PMD_DRV_LOG(INFO, "No new protocol added");
11456 buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
11457 proto = rte_zmalloc("new_proto", buff_size, 0);
11459 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11463 /* get information about protocol list */
11464 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11465 (uint8_t *)proto, buff_size,
11466 RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
11468 PMD_DRV_LOG(ERR, "Failed to get protocol list");
11473 /* Check if GTP is supported. */
11474 for (i = 0; i < proto_num; i++) {
11475 if (!strncmp(proto[i].name, "GTP", 3)) {
11476 pf->gtp_support = true;
11481 /* Update customized pctype info */
11482 ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
11485 PMD_DRV_LOG(INFO, "No pctype is updated.");
11487 /* Update customized ptype info */
11488 ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
11491 PMD_DRV_LOG(INFO, "No ptype is updated.");
11496 /* Create a QinQ cloud filter
11498 * The Fortville NIC has limited resources for tunnel filters,
11499 * so we can only reuse existing filters.
11501 * In step 1 we define which Field Vector fields can be used for
11503 * As we do not have the inner tag defined as a field,
11504 * we have to define it first, by reusing one of L1 entries.
11506 * In step 2 we are replacing one of existing filter types with
11507 * a new one for QinQ.
11508 * As we reusing L1 and replacing L2, some of the default filter
11509 * types will disappear,which depends on L1 and L2 entries we reuse.
11511 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
11513 * 1. Create L1 filter of outer vlan (12b) which will be in use
11514 * later when we define the cloud filter.
11515 * a. Valid_flags.replace_cloud = 0
11516 * b. Old_filter = 10 (Stag_Inner_Vlan)
11517 * c. New_filter = 0x10
11518 * d. TR bit = 0xff (optional, not used here)
11519 * e. Buffer – 2 entries:
11520 * i. Byte 0 = 8 (outer vlan FV index).
11522 * Byte 2-3 = 0x0fff
11523 * ii. Byte 0 = 37 (inner vlan FV index).
11525 * Byte 2-3 = 0x0fff
11528 * 2. Create cloud filter using two L1 filters entries: stag and
11529 * new filter(outer vlan+ inner vlan)
11530 * a. Valid_flags.replace_cloud = 1
11531 * b. Old_filter = 1 (instead of outer IP)
11532 * c. New_filter = 0x10
11533 * d. Buffer – 2 entries:
11534 * i. Byte 0 = 0x80 | 7 (valid | Stag).
11535 * Byte 1-3 = 0 (rsv)
11536 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
11537 * Byte 9-11 = 0 (rsv)
11540 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
11542 int ret = -ENOTSUP;
11543 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
11544 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
11545 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11548 memset(&filter_replace, 0,
11549 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11550 memset(&filter_replace_buf, 0,
11551 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11553 /* create L1 filter */
11554 filter_replace.old_filter_type =
11555 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
11556 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11557 filter_replace.tr_bit = 0;
11559 /* Prepare the buffer, 2 entries */
11560 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
11561 filter_replace_buf.data[0] |=
11562 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11563 /* Field Vector 12b mask */
11564 filter_replace_buf.data[2] = 0xff;
11565 filter_replace_buf.data[3] = 0x0f;
11566 filter_replace_buf.data[4] =
11567 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
11568 filter_replace_buf.data[4] |=
11569 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11570 /* Field Vector 12b mask */
11571 filter_replace_buf.data[6] = 0xff;
11572 filter_replace_buf.data[7] = 0x0f;
11573 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11574 &filter_replace_buf);
11575 if (ret != I40E_SUCCESS)
11578 /* Apply the second L2 cloud filter */
11579 memset(&filter_replace, 0,
11580 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11581 memset(&filter_replace_buf, 0,
11582 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11584 /* create L2 filter, input for L2 filter will be L1 filter */
11585 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
11586 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
11587 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11589 /* Prepare the buffer, 2 entries */
11590 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
11591 filter_replace_buf.data[0] |=
11592 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11593 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11594 filter_replace_buf.data[4] |=
11595 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11596 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11597 &filter_replace_buf);
11602 i40e_config_rss_filter(struct i40e_pf *pf,
11603 struct i40e_rte_flow_rss_conf *conf, bool add)
11605 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11606 uint32_t i, lut = 0;
11608 struct rte_eth_rss_conf rss_conf = conf->rss_conf;
11609 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
11612 if (memcmp(conf, rss_info,
11613 sizeof(struct i40e_rte_flow_rss_conf)) == 0) {
11614 i40e_pf_disable_rss(pf);
11615 memset(rss_info, 0,
11616 sizeof(struct i40e_rte_flow_rss_conf));
11625 /* If both VMDQ and RSS enabled, not all of PF queues are configured.
11626 * It's necessary to calculate the actual PF queues that are configured.
11628 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
11629 num = i40e_pf_calc_configured_queues_num(pf);
11631 num = pf->dev_data->nb_rx_queues;
11633 num = RTE_MIN(num, conf->num);
11634 PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
11638 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS");
11642 /* Fill in redirection table */
11643 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
11646 lut = (lut << 8) | (conf->queue[j] & ((0x1 <<
11647 hw->func_caps.rss_table_entry_width) - 1));
11649 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
11652 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
11653 i40e_pf_disable_rss(pf);
11656 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
11657 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
11658 /* Random default keys */
11659 static uint32_t rss_key_default[] = {0x6b793944,
11660 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
11661 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
11662 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
11664 rss_conf.rss_key = (uint8_t *)rss_key_default;
11665 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
11669 return i40e_hw_rss_hash_set(pf, &rss_conf);
11671 rte_memcpy(rss_info,
11672 conf, sizeof(struct i40e_rte_flow_rss_conf));
11677 RTE_INIT(i40e_init_log);
11679 i40e_init_log(void)
11681 i40e_logtype_init = rte_log_register("pmd.i40e.init");
11682 if (i40e_logtype_init >= 0)
11683 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
11684 i40e_logtype_driver = rte_log_register("pmd.i40e.driver");
11685 if (i40e_logtype_driver >= 0)
11686 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);