1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
14 #include <rte_common.h>
16 #include <rte_string_fns.h>
18 #include <rte_bus_pci.h>
19 #include <rte_ether.h>
20 #include <rte_ethdev_driver.h>
21 #include <rte_ethdev_pci.h>
22 #include <rte_memzone.h>
23 #include <rte_malloc.h>
24 #include <rte_memcpy.h>
25 #include <rte_alarm.h>
27 #include <rte_tailq.h>
28 #include <rte_hash_crc.h>
30 #include "i40e_logs.h"
31 #include "base/i40e_prototype.h"
32 #include "base/i40e_adminq_cmd.h"
33 #include "base/i40e_type.h"
34 #include "base/i40e_register.h"
35 #include "base/i40e_dcb.h"
36 #include "i40e_ethdev.h"
37 #include "i40e_rxtx.h"
39 #include "i40e_regs.h"
40 #include "rte_pmd_i40e.h"
42 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
43 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
44 #define ETH_I40E_SUPPORT_MULTI_DRIVER "support-multi-driver"
45 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG "queue-num-per-vf"
46 #define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec"
47 #define ETH_I40E_VF_MSG_CFG "vf_msg_cfg"
49 #define I40E_CLEAR_PXE_WAIT_MS 200
51 /* Maximun number of capability elements */
52 #define I40E_MAX_CAP_ELE_NUM 128
54 /* Wait count and interval */
55 #define I40E_CHK_Q_ENA_COUNT 1000
56 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
58 /* Maximun number of VSI */
59 #define I40E_MAX_NUM_VSIS (384UL)
61 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
63 /* Flow control default timer */
64 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
66 /* Flow control enable fwd bit */
67 #define I40E_PRTMAC_FWD_CTRL 0x00000001
69 /* Receive Packet Buffer size */
70 #define I40E_RXPBSIZE (968 * 1024)
73 #define I40E_KILOSHIFT 10
75 /* Flow control default high water */
76 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
78 /* Flow control default low water */
79 #define I40E_DEFAULT_LOW_WATER (0xF2000 >> I40E_KILOSHIFT)
81 /* Receive Average Packet Size in Byte*/
82 #define I40E_PACKET_AVERAGE_SIZE 128
84 /* Mask of PF interrupt causes */
85 #define I40E_PFINT_ICR0_ENA_MASK ( \
86 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
87 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
88 I40E_PFINT_ICR0_ENA_GRST_MASK | \
89 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
90 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
91 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
92 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
93 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
94 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
96 #define I40E_FLOW_TYPES ( \
97 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
98 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
99 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
100 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
101 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
102 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
103 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
104 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
105 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
106 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
107 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
109 /* Additional timesync values. */
110 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
111 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
112 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
113 #define I40E_PRTTSYN_TSYNENA 0x80000000
114 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
115 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
118 * Below are values for writing un-exposed registers suggested
121 /* Destination MAC address */
122 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
123 /* Source MAC address */
124 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
125 /* Outer (S-Tag) VLAN tag in the outer L2 header */
126 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
127 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
128 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
129 /* Single VLAN tag in the inner L2 header */
130 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
131 /* Source IPv4 address */
132 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
133 /* Destination IPv4 address */
134 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
135 /* Source IPv4 address for X722 */
136 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
137 /* Destination IPv4 address for X722 */
138 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
139 /* IPv4 Protocol for X722 */
140 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
141 /* IPv4 Time to Live for X722 */
142 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
143 /* IPv4 Type of Service (TOS) */
144 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
146 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
147 /* IPv4 Time to Live */
148 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
149 /* Source IPv6 address */
150 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
151 /* Destination IPv6 address */
152 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
153 /* IPv6 Traffic Class (TC) */
154 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
155 /* IPv6 Next Header */
156 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
158 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
160 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
161 /* Destination L4 port */
162 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
163 /* SCTP verification tag */
164 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
165 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
166 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
167 /* Source port of tunneling UDP */
168 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
169 /* Destination port of tunneling UDP */
170 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
171 /* UDP Tunneling ID, NVGRE/GRE key */
172 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
173 /* Last ether type */
174 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
175 /* Tunneling outer destination IPv4 address */
176 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
177 /* Tunneling outer destination IPv6 address */
178 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
179 /* 1st word of flex payload */
180 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
181 /* 2nd word of flex payload */
182 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
183 /* 3rd word of flex payload */
184 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
185 /* 4th word of flex payload */
186 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
187 /* 5th word of flex payload */
188 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
189 /* 6th word of flex payload */
190 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
191 /* 7th word of flex payload */
192 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
193 /* 8th word of flex payload */
194 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
195 /* all 8 words flex payload */
196 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
197 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
199 #define I40E_TRANSLATE_INSET 0
200 #define I40E_TRANSLATE_REG 1
202 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
203 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
204 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
205 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
206 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
207 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
209 /* PCI offset for querying capability */
210 #define PCI_DEV_CAP_REG 0xA4
211 /* PCI offset for enabling/disabling Extended Tag */
212 #define PCI_DEV_CTRL_REG 0xA8
213 /* Bit mask of Extended Tag capability */
214 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
215 /* Bit shift of Extended Tag enable/disable */
216 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
217 /* Bit mask of Extended Tag enable/disable */
218 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
220 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
221 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
222 static int i40e_dev_configure(struct rte_eth_dev *dev);
223 static int i40e_dev_start(struct rte_eth_dev *dev);
224 static void i40e_dev_stop(struct rte_eth_dev *dev);
225 static void i40e_dev_close(struct rte_eth_dev *dev);
226 static int i40e_dev_reset(struct rte_eth_dev *dev);
227 static int i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
228 static int i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
229 static int i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
230 static int i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
231 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
232 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
233 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
234 struct rte_eth_stats *stats);
235 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
236 struct rte_eth_xstat *xstats, unsigned n);
237 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
238 struct rte_eth_xstat_name *xstats_names,
240 static int i40e_dev_stats_reset(struct rte_eth_dev *dev);
241 static int i40e_fw_version_get(struct rte_eth_dev *dev,
242 char *fw_version, size_t fw_size);
243 static int i40e_dev_info_get(struct rte_eth_dev *dev,
244 struct rte_eth_dev_info *dev_info);
245 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
248 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
249 enum rte_vlan_type vlan_type,
251 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
252 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
255 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
256 static int i40e_dev_led_on(struct rte_eth_dev *dev);
257 static int i40e_dev_led_off(struct rte_eth_dev *dev);
258 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
259 struct rte_eth_fc_conf *fc_conf);
260 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
261 struct rte_eth_fc_conf *fc_conf);
262 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
263 struct rte_eth_pfc_conf *pfc_conf);
264 static int i40e_macaddr_add(struct rte_eth_dev *dev,
265 struct rte_ether_addr *mac_addr,
268 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
269 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
270 struct rte_eth_rss_reta_entry64 *reta_conf,
272 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
273 struct rte_eth_rss_reta_entry64 *reta_conf,
276 static int i40e_get_cap(struct i40e_hw *hw);
277 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
278 static int i40e_pf_setup(struct i40e_pf *pf);
279 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
280 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
281 static int i40e_dcb_setup(struct rte_eth_dev *dev);
282 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
283 bool offset_loaded, uint64_t *offset, uint64_t *stat);
284 static void i40e_stat_update_48(struct i40e_hw *hw,
290 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
291 static void i40e_dev_interrupt_handler(void *param);
292 static void i40e_dev_alarm_handler(void *param);
293 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
294 uint32_t base, uint32_t num);
295 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
296 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
298 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
300 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
301 static int i40e_veb_release(struct i40e_veb *veb);
302 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
303 struct i40e_vsi *vsi);
304 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
305 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
306 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
307 struct i40e_macvlan_filter *mv_f,
310 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
311 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
312 struct rte_eth_rss_conf *rss_conf);
313 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
314 struct rte_eth_rss_conf *rss_conf);
315 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
316 struct rte_eth_udp_tunnel *udp_tunnel);
317 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
318 struct rte_eth_udp_tunnel *udp_tunnel);
319 static void i40e_filter_input_set_init(struct i40e_pf *pf);
320 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
321 enum rte_filter_op filter_op,
323 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
324 enum rte_filter_type filter_type,
325 enum rte_filter_op filter_op,
327 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
328 struct rte_eth_dcb_info *dcb_info);
329 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
330 static void i40e_configure_registers(struct i40e_hw *hw);
331 static void i40e_hw_init(struct rte_eth_dev *dev);
332 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
333 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
339 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
340 struct rte_eth_mirror_conf *mirror_conf,
341 uint8_t sw_id, uint8_t on);
342 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
344 static int i40e_timesync_enable(struct rte_eth_dev *dev);
345 static int i40e_timesync_disable(struct rte_eth_dev *dev);
346 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
347 struct timespec *timestamp,
349 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
350 struct timespec *timestamp);
351 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
353 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
355 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
356 struct timespec *timestamp);
357 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
358 const struct timespec *timestamp);
360 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
362 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
365 static int i40e_get_regs(struct rte_eth_dev *dev,
366 struct rte_dev_reg_info *regs);
368 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
370 static int i40e_get_eeprom(struct rte_eth_dev *dev,
371 struct rte_dev_eeprom_info *eeprom);
373 static int i40e_get_module_info(struct rte_eth_dev *dev,
374 struct rte_eth_dev_module_info *modinfo);
375 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
376 struct rte_dev_eeprom_info *info);
378 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
379 struct rte_ether_addr *mac_addr);
381 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
383 static int i40e_ethertype_filter_convert(
384 const struct rte_eth_ethertype_filter *input,
385 struct i40e_ethertype_filter *filter);
386 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
387 struct i40e_ethertype_filter *filter);
389 static int i40e_tunnel_filter_convert(
390 struct i40e_aqc_cloud_filters_element_bb *cld_filter,
391 struct i40e_tunnel_filter *tunnel_filter);
392 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
393 struct i40e_tunnel_filter *tunnel_filter);
394 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
396 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
397 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
398 static void i40e_filter_restore(struct i40e_pf *pf);
399 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
401 int i40e_logtype_init;
402 int i40e_logtype_driver;
403 #ifdef RTE_LIBRTE_I40E_DEBUG_RX
406 #ifdef RTE_LIBRTE_I40E_DEBUG_TX
409 #ifdef RTE_LIBRTE_I40E_DEBUG_TX_FREE
410 int i40e_logtype_tx_free;
413 static const char *const valid_keys[] = {
414 ETH_I40E_FLOATING_VEB_ARG,
415 ETH_I40E_FLOATING_VEB_LIST_ARG,
416 ETH_I40E_SUPPORT_MULTI_DRIVER,
417 ETH_I40E_QUEUE_NUM_PER_VF_ARG,
418 ETH_I40E_USE_LATEST_VEC,
422 static const struct rte_pci_id pci_id_i40e_map[] = {
423 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
424 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
425 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
426 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
427 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
428 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
429 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
430 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
431 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
432 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
433 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
434 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
435 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
436 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
437 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
438 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
439 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
440 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
441 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
442 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
443 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X710_N3000) },
444 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_XXV710_N3000) },
445 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_BC) },
446 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_B) },
447 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_SFP) },
448 { .vendor_id = 0, /* sentinel */ },
451 static const struct eth_dev_ops i40e_eth_dev_ops = {
452 .dev_configure = i40e_dev_configure,
453 .dev_start = i40e_dev_start,
454 .dev_stop = i40e_dev_stop,
455 .dev_close = i40e_dev_close,
456 .dev_reset = i40e_dev_reset,
457 .promiscuous_enable = i40e_dev_promiscuous_enable,
458 .promiscuous_disable = i40e_dev_promiscuous_disable,
459 .allmulticast_enable = i40e_dev_allmulticast_enable,
460 .allmulticast_disable = i40e_dev_allmulticast_disable,
461 .dev_set_link_up = i40e_dev_set_link_up,
462 .dev_set_link_down = i40e_dev_set_link_down,
463 .link_update = i40e_dev_link_update,
464 .stats_get = i40e_dev_stats_get,
465 .xstats_get = i40e_dev_xstats_get,
466 .xstats_get_names = i40e_dev_xstats_get_names,
467 .stats_reset = i40e_dev_stats_reset,
468 .xstats_reset = i40e_dev_stats_reset,
469 .fw_version_get = i40e_fw_version_get,
470 .dev_infos_get = i40e_dev_info_get,
471 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
472 .vlan_filter_set = i40e_vlan_filter_set,
473 .vlan_tpid_set = i40e_vlan_tpid_set,
474 .vlan_offload_set = i40e_vlan_offload_set,
475 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
476 .vlan_pvid_set = i40e_vlan_pvid_set,
477 .rx_queue_start = i40e_dev_rx_queue_start,
478 .rx_queue_stop = i40e_dev_rx_queue_stop,
479 .tx_queue_start = i40e_dev_tx_queue_start,
480 .tx_queue_stop = i40e_dev_tx_queue_stop,
481 .rx_queue_setup = i40e_dev_rx_queue_setup,
482 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
483 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
484 .rx_queue_release = i40e_dev_rx_queue_release,
485 .rx_queue_count = i40e_dev_rx_queue_count,
486 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
487 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
488 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
489 .tx_queue_setup = i40e_dev_tx_queue_setup,
490 .tx_queue_release = i40e_dev_tx_queue_release,
491 .dev_led_on = i40e_dev_led_on,
492 .dev_led_off = i40e_dev_led_off,
493 .flow_ctrl_get = i40e_flow_ctrl_get,
494 .flow_ctrl_set = i40e_flow_ctrl_set,
495 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
496 .mac_addr_add = i40e_macaddr_add,
497 .mac_addr_remove = i40e_macaddr_remove,
498 .reta_update = i40e_dev_rss_reta_update,
499 .reta_query = i40e_dev_rss_reta_query,
500 .rss_hash_update = i40e_dev_rss_hash_update,
501 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
502 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
503 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
504 .filter_ctrl = i40e_dev_filter_ctrl,
505 .rxq_info_get = i40e_rxq_info_get,
506 .txq_info_get = i40e_txq_info_get,
507 .rx_burst_mode_get = i40e_rx_burst_mode_get,
508 .tx_burst_mode_get = i40e_tx_burst_mode_get,
509 .mirror_rule_set = i40e_mirror_rule_set,
510 .mirror_rule_reset = i40e_mirror_rule_reset,
511 .timesync_enable = i40e_timesync_enable,
512 .timesync_disable = i40e_timesync_disable,
513 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
514 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
515 .get_dcb_info = i40e_dev_get_dcb_info,
516 .timesync_adjust_time = i40e_timesync_adjust_time,
517 .timesync_read_time = i40e_timesync_read_time,
518 .timesync_write_time = i40e_timesync_write_time,
519 .get_reg = i40e_get_regs,
520 .get_eeprom_length = i40e_get_eeprom_length,
521 .get_eeprom = i40e_get_eeprom,
522 .get_module_info = i40e_get_module_info,
523 .get_module_eeprom = i40e_get_module_eeprom,
524 .mac_addr_set = i40e_set_default_mac_addr,
525 .mtu_set = i40e_dev_mtu_set,
526 .tm_ops_get = i40e_tm_ops_get,
529 /* store statistics names and its offset in stats structure */
530 struct rte_i40e_xstats_name_off {
531 char name[RTE_ETH_XSTATS_NAME_SIZE];
535 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
536 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
537 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
538 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
539 {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
540 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
541 rx_unknown_protocol)},
542 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
543 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
544 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
545 {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
548 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
549 sizeof(rte_i40e_stats_strings[0]))
551 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
552 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
553 tx_dropped_link_down)},
554 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
555 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
557 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
558 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
560 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
562 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
564 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
565 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
566 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
567 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
568 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
569 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
571 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
573 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
575 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
577 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
579 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
581 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
583 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
585 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
586 mac_short_packet_dropped)},
587 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
589 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
590 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
591 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
593 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
595 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
597 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
599 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
601 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
603 {"rx_flow_director_atr_match_packets",
604 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
605 {"rx_flow_director_sb_match_packets",
606 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
607 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
609 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
611 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
613 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
617 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
618 sizeof(rte_i40e_hw_port_strings[0]))
620 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
621 {"xon_packets", offsetof(struct i40e_hw_port_stats,
623 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
627 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
628 sizeof(rte_i40e_rxq_prio_strings[0]))
630 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
631 {"xon_packets", offsetof(struct i40e_hw_port_stats,
633 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
635 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
636 priority_xon_2_xoff)},
639 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
640 sizeof(rte_i40e_txq_prio_strings[0]))
643 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
644 struct rte_pci_device *pci_dev)
646 char name[RTE_ETH_NAME_MAX_LEN];
647 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
650 if (pci_dev->device.devargs) {
651 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
657 retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
658 sizeof(struct i40e_adapter),
659 eth_dev_pci_specific_init, pci_dev,
660 eth_i40e_dev_init, NULL);
662 if (retval || eth_da.nb_representor_ports < 1)
665 /* probe VF representor ports */
666 struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
667 pci_dev->device.name);
669 if (pf_ethdev == NULL)
672 for (i = 0; i < eth_da.nb_representor_ports; i++) {
673 struct i40e_vf_representor representor = {
674 .vf_id = eth_da.representor_ports[i],
675 .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
676 pf_ethdev->data->dev_private)->switch_domain_id,
677 .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
678 pf_ethdev->data->dev_private)
681 /* representor port net_bdf_port */
682 snprintf(name, sizeof(name), "net_%s_representor_%d",
683 pci_dev->device.name, eth_da.representor_ports[i]);
685 retval = rte_eth_dev_create(&pci_dev->device, name,
686 sizeof(struct i40e_vf_representor), NULL, NULL,
687 i40e_vf_representor_init, &representor);
690 PMD_DRV_LOG(ERR, "failed to create i40e vf "
691 "representor %s.", name);
697 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
699 struct rte_eth_dev *ethdev;
701 ethdev = rte_eth_dev_allocated(pci_dev->device.name);
705 if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
706 return rte_eth_dev_pci_generic_remove(pci_dev,
707 i40e_vf_representor_uninit);
709 return rte_eth_dev_pci_generic_remove(pci_dev,
710 eth_i40e_dev_uninit);
713 static struct rte_pci_driver rte_i40e_pmd = {
714 .id_table = pci_id_i40e_map,
715 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
716 .probe = eth_i40e_pci_probe,
717 .remove = eth_i40e_pci_remove,
721 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
724 uint32_t ori_reg_val;
725 struct rte_eth_dev *dev;
727 ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
728 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
729 i40e_write_rx_ctl(hw, reg_addr, reg_val);
730 if (ori_reg_val != reg_val)
732 "i40e device %s changed global register [0x%08x]."
733 " original: 0x%08x, new: 0x%08x",
734 dev->device->name, reg_addr, ori_reg_val, reg_val);
737 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
738 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
739 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
741 #ifndef I40E_GLQF_ORT
742 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
744 #ifndef I40E_GLQF_PIT
745 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
747 #ifndef I40E_GLQF_L3_MAP
748 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
751 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
754 * Initialize registers for parsing packet type of QinQ
755 * This should be removed from code once proper
756 * configuration API is added to avoid configuration conflicts
757 * between ports of the same device.
759 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
760 I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
763 static inline void i40e_config_automask(struct i40e_pf *pf)
765 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
768 /* INTENA flag is not auto-cleared for interrupt */
769 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
770 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
771 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
773 /* If support multi-driver, PF will use INT0. */
774 if (!pf->support_multi_driver)
775 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
777 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
780 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
783 * Add a ethertype filter to drop all flow control frames transmitted
787 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
789 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
790 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
791 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
792 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
795 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
796 I40E_FLOW_CONTROL_ETHERTYPE, flags,
797 pf->main_vsi_seid, 0,
801 "Failed to add filter to drop flow control frames from VSIs.");
805 floating_veb_list_handler(__rte_unused const char *key,
806 const char *floating_veb_value,
810 unsigned int count = 0;
813 bool *vf_floating_veb = opaque;
815 while (isblank(*floating_veb_value))
816 floating_veb_value++;
818 /* Reset floating VEB configuration for VFs */
819 for (idx = 0; idx < I40E_MAX_VF; idx++)
820 vf_floating_veb[idx] = false;
824 while (isblank(*floating_veb_value))
825 floating_veb_value++;
826 if (*floating_veb_value == '\0')
829 idx = strtoul(floating_veb_value, &end, 10);
830 if (errno || end == NULL)
832 while (isblank(*end))
836 } else if ((*end == ';') || (*end == '\0')) {
838 if (min == I40E_MAX_VF)
840 if (max >= I40E_MAX_VF)
841 max = I40E_MAX_VF - 1;
842 for (idx = min; idx <= max; idx++) {
843 vf_floating_veb[idx] = true;
850 floating_veb_value = end + 1;
851 } while (*end != '\0');
860 config_vf_floating_veb(struct rte_devargs *devargs,
861 uint16_t floating_veb,
862 bool *vf_floating_veb)
864 struct rte_kvargs *kvlist;
866 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
870 /* All the VFs attach to the floating VEB by default
871 * when the floating VEB is enabled.
873 for (i = 0; i < I40E_MAX_VF; i++)
874 vf_floating_veb[i] = true;
879 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
883 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
884 rte_kvargs_free(kvlist);
887 /* When the floating_veb_list parameter exists, all the VFs
888 * will attach to the legacy VEB firstly, then configure VFs
889 * to the floating VEB according to the floating_veb_list.
891 if (rte_kvargs_process(kvlist, floating_veb_list,
892 floating_veb_list_handler,
893 vf_floating_veb) < 0) {
894 rte_kvargs_free(kvlist);
897 rte_kvargs_free(kvlist);
901 i40e_check_floating_handler(__rte_unused const char *key,
903 __rte_unused void *opaque)
905 if (strcmp(value, "1"))
912 is_floating_veb_supported(struct rte_devargs *devargs)
914 struct rte_kvargs *kvlist;
915 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
920 kvlist = rte_kvargs_parse(devargs->args, valid_keys);
924 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
925 rte_kvargs_free(kvlist);
928 /* Floating VEB is enabled when there's key-value:
929 * enable_floating_veb=1
931 if (rte_kvargs_process(kvlist, floating_veb_key,
932 i40e_check_floating_handler, NULL) < 0) {
933 rte_kvargs_free(kvlist);
936 rte_kvargs_free(kvlist);
942 config_floating_veb(struct rte_eth_dev *dev)
944 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
945 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
946 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
948 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
950 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
952 is_floating_veb_supported(pci_dev->device.devargs);
953 config_vf_floating_veb(pci_dev->device.devargs,
955 pf->floating_veb_list);
957 pf->floating_veb = false;
961 #define I40E_L2_TAGS_S_TAG_SHIFT 1
962 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
965 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
967 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
968 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
969 char ethertype_hash_name[RTE_HASH_NAMESIZE];
972 struct rte_hash_parameters ethertype_hash_params = {
973 .name = ethertype_hash_name,
974 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
975 .key_len = sizeof(struct i40e_ethertype_filter_input),
976 .hash_func = rte_hash_crc,
977 .hash_func_init_val = 0,
978 .socket_id = rte_socket_id(),
981 /* Initialize ethertype filter rule list and hash */
982 TAILQ_INIT(ðertype_rule->ethertype_list);
983 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
984 "ethertype_%s", dev->device->name);
985 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
986 if (!ethertype_rule->hash_table) {
987 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
990 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
991 sizeof(struct i40e_ethertype_filter *) *
992 I40E_MAX_ETHERTYPE_FILTER_NUM,
994 if (!ethertype_rule->hash_map) {
996 "Failed to allocate memory for ethertype hash map!");
998 goto err_ethertype_hash_map_alloc;
1003 err_ethertype_hash_map_alloc:
1004 rte_hash_free(ethertype_rule->hash_table);
1010 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
1012 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1013 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
1014 char tunnel_hash_name[RTE_HASH_NAMESIZE];
1017 struct rte_hash_parameters tunnel_hash_params = {
1018 .name = tunnel_hash_name,
1019 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1020 .key_len = sizeof(struct i40e_tunnel_filter_input),
1021 .hash_func = rte_hash_crc,
1022 .hash_func_init_val = 0,
1023 .socket_id = rte_socket_id(),
1026 /* Initialize tunnel filter rule list and hash */
1027 TAILQ_INIT(&tunnel_rule->tunnel_list);
1028 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1029 "tunnel_%s", dev->device->name);
1030 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1031 if (!tunnel_rule->hash_table) {
1032 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1035 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1036 sizeof(struct i40e_tunnel_filter *) *
1037 I40E_MAX_TUNNEL_FILTER_NUM,
1039 if (!tunnel_rule->hash_map) {
1041 "Failed to allocate memory for tunnel hash map!");
1043 goto err_tunnel_hash_map_alloc;
1048 err_tunnel_hash_map_alloc:
1049 rte_hash_free(tunnel_rule->hash_table);
1055 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1057 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1058 struct i40e_fdir_info *fdir_info = &pf->fdir;
1059 char fdir_hash_name[RTE_HASH_NAMESIZE];
1062 struct rte_hash_parameters fdir_hash_params = {
1063 .name = fdir_hash_name,
1064 .entries = I40E_MAX_FDIR_FILTER_NUM,
1065 .key_len = sizeof(struct i40e_fdir_input),
1066 .hash_func = rte_hash_crc,
1067 .hash_func_init_val = 0,
1068 .socket_id = rte_socket_id(),
1071 /* Initialize flow director filter rule list and hash */
1072 TAILQ_INIT(&fdir_info->fdir_list);
1073 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1074 "fdir_%s", dev->device->name);
1075 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1076 if (!fdir_info->hash_table) {
1077 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1080 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1081 sizeof(struct i40e_fdir_filter *) *
1082 I40E_MAX_FDIR_FILTER_NUM,
1084 if (!fdir_info->hash_map) {
1086 "Failed to allocate memory for fdir hash map!");
1088 goto err_fdir_hash_map_alloc;
1092 err_fdir_hash_map_alloc:
1093 rte_hash_free(fdir_info->hash_table);
1099 i40e_init_customized_info(struct i40e_pf *pf)
1103 /* Initialize customized pctype */
1104 for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1105 pf->customized_pctype[i].index = i;
1106 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1107 pf->customized_pctype[i].valid = false;
1110 pf->gtp_support = false;
1114 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1116 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1117 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1118 struct i40e_queue_regions *info = &pf->queue_region;
1121 for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1122 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1124 memset(info, 0, sizeof(struct i40e_queue_regions));
1128 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1133 unsigned long support_multi_driver;
1136 pf = (struct i40e_pf *)opaque;
1139 support_multi_driver = strtoul(value, &end, 10);
1140 if (errno != 0 || end == value || *end != 0) {
1141 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1145 if (support_multi_driver == 1 || support_multi_driver == 0)
1146 pf->support_multi_driver = (bool)support_multi_driver;
1148 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1149 "enable global configuration by default."
1150 ETH_I40E_SUPPORT_MULTI_DRIVER);
1155 i40e_support_multi_driver(struct rte_eth_dev *dev)
1157 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1158 struct rte_kvargs *kvlist;
1161 /* Enable global configuration by default */
1162 pf->support_multi_driver = false;
1164 if (!dev->device->devargs)
1167 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1171 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1172 if (!kvargs_count) {
1173 rte_kvargs_free(kvlist);
1177 if (kvargs_count > 1)
1178 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1179 "the first invalid or last valid one is used !",
1180 ETH_I40E_SUPPORT_MULTI_DRIVER);
1182 if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1183 i40e_parse_multi_drv_handler, pf) < 0) {
1184 rte_kvargs_free(kvlist);
1188 rte_kvargs_free(kvlist);
1193 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1194 uint32_t reg_addr, uint64_t reg_val,
1195 struct i40e_asq_cmd_details *cmd_details)
1197 uint64_t ori_reg_val;
1198 struct rte_eth_dev *dev;
1201 ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1202 if (ret != I40E_SUCCESS) {
1204 "Fail to debug read from 0x%08x",
1208 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1210 if (ori_reg_val != reg_val)
1211 PMD_DRV_LOG(WARNING,
1212 "i40e device %s changed global register [0x%08x]."
1213 " original: 0x%"PRIx64", after: 0x%"PRIx64,
1214 dev->device->name, reg_addr, ori_reg_val, reg_val);
1216 return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1220 i40e_parse_latest_vec_handler(__rte_unused const char *key,
1224 struct i40e_adapter *ad = opaque;
1227 use_latest_vec = atoi(value);
1229 if (use_latest_vec != 0 && use_latest_vec != 1)
1230 PMD_DRV_LOG(WARNING, "Value should be 0 or 1, set it as 1!");
1232 ad->use_latest_vec = (uint8_t)use_latest_vec;
1238 i40e_use_latest_vec(struct rte_eth_dev *dev)
1240 struct i40e_adapter *ad =
1241 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1242 struct rte_kvargs *kvlist;
1245 ad->use_latest_vec = false;
1247 if (!dev->device->devargs)
1250 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1254 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_USE_LATEST_VEC);
1255 if (!kvargs_count) {
1256 rte_kvargs_free(kvlist);
1260 if (kvargs_count > 1)
1261 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1262 "the first invalid or last valid one is used !",
1263 ETH_I40E_USE_LATEST_VEC);
1265 if (rte_kvargs_process(kvlist, ETH_I40E_USE_LATEST_VEC,
1266 i40e_parse_latest_vec_handler, ad) < 0) {
1267 rte_kvargs_free(kvlist);
1271 rte_kvargs_free(kvlist);
1276 read_vf_msg_config(__rte_unused const char *key,
1280 struct i40e_vf_msg_cfg *cfg = opaque;
1282 if (sscanf(value, "%u@%u:%u", &cfg->max_msg, &cfg->period,
1283 &cfg->ignore_second) != 3) {
1284 memset(cfg, 0, sizeof(*cfg));
1285 PMD_DRV_LOG(ERR, "format error! example: "
1286 "%s=60@120:180", ETH_I40E_VF_MSG_CFG);
1291 * If the message validation function been enabled, the 'period'
1292 * and 'ignore_second' must greater than 0.
1294 if (cfg->max_msg && (!cfg->period || !cfg->ignore_second)) {
1295 memset(cfg, 0, sizeof(*cfg));
1296 PMD_DRV_LOG(ERR, "%s error! the second and third"
1297 " number must be greater than 0!",
1298 ETH_I40E_VF_MSG_CFG);
1306 i40e_parse_vf_msg_config(struct rte_eth_dev *dev,
1307 struct i40e_vf_msg_cfg *msg_cfg)
1309 struct rte_kvargs *kvlist;
1313 memset(msg_cfg, 0, sizeof(*msg_cfg));
1315 if (!dev->device->devargs)
1318 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1322 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_VF_MSG_CFG);
1326 if (kvargs_count > 1) {
1327 PMD_DRV_LOG(ERR, "More than one argument \"%s\"!",
1328 ETH_I40E_VF_MSG_CFG);
1333 if (rte_kvargs_process(kvlist, ETH_I40E_VF_MSG_CFG,
1334 read_vf_msg_config, msg_cfg) < 0)
1338 rte_kvargs_free(kvlist);
1342 #define I40E_ALARM_INTERVAL 50000 /* us */
1345 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1347 struct rte_pci_device *pci_dev;
1348 struct rte_intr_handle *intr_handle;
1349 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1350 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1351 struct i40e_vsi *vsi;
1354 uint8_t aq_fail = 0;
1356 PMD_INIT_FUNC_TRACE();
1358 dev->dev_ops = &i40e_eth_dev_ops;
1359 dev->rx_pkt_burst = i40e_recv_pkts;
1360 dev->tx_pkt_burst = i40e_xmit_pkts;
1361 dev->tx_pkt_prepare = i40e_prep_pkts;
1363 /* for secondary processes, we don't initialise any further as primary
1364 * has already done this work. Only check we don't need a different
1366 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1367 i40e_set_rx_function(dev);
1368 i40e_set_tx_function(dev);
1371 i40e_set_default_ptype_table(dev);
1372 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1373 intr_handle = &pci_dev->intr_handle;
1375 rte_eth_copy_pci_info(dev, pci_dev);
1377 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1378 pf->adapter->eth_dev = dev;
1379 pf->dev_data = dev->data;
1381 hw->back = I40E_PF_TO_ADAPTER(pf);
1382 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1385 "Hardware is not available, as address is NULL");
1389 hw->vendor_id = pci_dev->id.vendor_id;
1390 hw->device_id = pci_dev->id.device_id;
1391 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1392 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1393 hw->bus.device = pci_dev->addr.devid;
1394 hw->bus.func = pci_dev->addr.function;
1395 hw->adapter_stopped = 0;
1396 hw->adapter_closed = 0;
1398 /* Init switch device pointer */
1399 hw->switch_dev = NULL;
1402 * Switch Tag value should not be identical to either the First Tag
1403 * or Second Tag values. So set something other than common Ethertype
1404 * for internal switching.
1406 hw->switch_tag = 0xffff;
1408 val = I40E_READ_REG(hw, I40E_GL_FWSTS);
1409 if (val & I40E_GL_FWSTS_FWS1B_MASK) {
1410 PMD_INIT_LOG(ERR, "\nERROR: "
1411 "Firmware recovery mode detected. Limiting functionality.\n"
1412 "Refer to the Intel(R) Ethernet Adapters and Devices "
1413 "User Guide for details on firmware recovery mode.");
1417 i40e_parse_vf_msg_config(dev, &pf->vf_msg_cfg);
1418 /* Check if need to support multi-driver */
1419 i40e_support_multi_driver(dev);
1420 /* Check if users want the latest supported vec path */
1421 i40e_use_latest_vec(dev);
1423 /* Make sure all is clean before doing PF reset */
1426 /* Reset here to make sure all is clean for each PF */
1427 ret = i40e_pf_reset(hw);
1429 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1433 /* Initialize the shared code (base driver) */
1434 ret = i40e_init_shared_code(hw);
1436 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1440 /* Initialize the parameters for adminq */
1441 i40e_init_adminq_parameter(hw);
1442 ret = i40e_init_adminq(hw);
1443 if (ret != I40E_SUCCESS) {
1444 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1447 /* Firmware of SFP x722 does not support adminq option */
1448 if (hw->device_id == I40E_DEV_ID_SFP_X722)
1449 hw->flags &= ~I40E_HW_FLAG_802_1AD_CAPABLE;
1451 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1452 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1453 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1454 ((hw->nvm.version >> 12) & 0xf),
1455 ((hw->nvm.version >> 4) & 0xff),
1456 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1458 /* Initialize the hardware */
1461 i40e_config_automask(pf);
1463 i40e_set_default_pctype_table(dev);
1466 * To work around the NVM issue, initialize registers
1467 * for packet type of QinQ by software.
1468 * It should be removed once issues are fixed in NVM.
1470 if (!pf->support_multi_driver)
1471 i40e_GLQF_reg_init(hw);
1473 /* Initialize the input set for filters (hash and fd) to default value */
1474 i40e_filter_input_set_init(pf);
1476 /* initialise the L3_MAP register */
1477 if (!pf->support_multi_driver) {
1478 ret = i40e_aq_debug_write_global_register(hw,
1479 I40E_GLQF_L3_MAP(40),
1482 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1485 "Global register 0x%08x is changed with 0x28",
1486 I40E_GLQF_L3_MAP(40));
1489 /* Need the special FW version to support floating VEB */
1490 config_floating_veb(dev);
1491 /* Clear PXE mode */
1492 i40e_clear_pxe_mode(hw);
1493 i40e_dev_sync_phy_type(hw);
1496 * On X710, performance number is far from the expectation on recent
1497 * firmware versions. The fix for this issue may not be integrated in
1498 * the following firmware version. So the workaround in software driver
1499 * is needed. It needs to modify the initial values of 3 internal only
1500 * registers. Note that the workaround can be removed when it is fixed
1501 * in firmware in the future.
1503 i40e_configure_registers(hw);
1505 /* Get hw capabilities */
1506 ret = i40e_get_cap(hw);
1507 if (ret != I40E_SUCCESS) {
1508 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1509 goto err_get_capabilities;
1512 /* Initialize parameters for PF */
1513 ret = i40e_pf_parameter_init(dev);
1515 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1516 goto err_parameter_init;
1519 /* Initialize the queue management */
1520 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1522 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1523 goto err_qp_pool_init;
1525 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1526 hw->func_caps.num_msix_vectors - 1);
1528 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1529 goto err_msix_pool_init;
1532 /* Initialize lan hmc */
1533 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1534 hw->func_caps.num_rx_qp, 0, 0);
1535 if (ret != I40E_SUCCESS) {
1536 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1537 goto err_init_lan_hmc;
1540 /* Configure lan hmc */
1541 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1542 if (ret != I40E_SUCCESS) {
1543 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1544 goto err_configure_lan_hmc;
1547 /* Get and check the mac address */
1548 i40e_get_mac_addr(hw, hw->mac.addr);
1549 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1550 PMD_INIT_LOG(ERR, "mac address is not valid");
1552 goto err_get_mac_addr;
1554 /* Copy the permanent MAC address */
1555 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1556 (struct rte_ether_addr *)hw->mac.perm_addr);
1558 /* Disable flow control */
1559 hw->fc.requested_mode = I40E_FC_NONE;
1560 i40e_set_fc(hw, &aq_fail, TRUE);
1562 /* Set the global registers with default ether type value */
1563 if (!pf->support_multi_driver) {
1564 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1565 RTE_ETHER_TYPE_VLAN);
1566 if (ret != I40E_SUCCESS) {
1568 "Failed to set the default outer "
1570 goto err_setup_pf_switch;
1574 /* PF setup, which includes VSI setup */
1575 ret = i40e_pf_setup(pf);
1577 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1578 goto err_setup_pf_switch;
1583 /* Disable double vlan by default */
1584 i40e_vsi_config_double_vlan(vsi, FALSE);
1586 /* Disable S-TAG identification when floating_veb is disabled */
1587 if (!pf->floating_veb) {
1588 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1589 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1590 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1591 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1595 if (!vsi->max_macaddrs)
1596 len = RTE_ETHER_ADDR_LEN;
1598 len = RTE_ETHER_ADDR_LEN * vsi->max_macaddrs;
1600 /* Should be after VSI initialized */
1601 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1602 if (!dev->data->mac_addrs) {
1604 "Failed to allocated memory for storing mac address");
1607 rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1608 &dev->data->mac_addrs[0]);
1610 /* Pass the information to the rte_eth_dev_close() that it should also
1611 * release the private port resources.
1613 dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1615 /* Init dcb to sw mode by default */
1616 ret = i40e_dcb_init_configure(dev, TRUE);
1617 if (ret != I40E_SUCCESS) {
1618 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1619 pf->flags &= ~I40E_FLAG_DCB;
1621 /* Update HW struct after DCB configuration */
1624 /* initialize pf host driver to setup SRIOV resource if applicable */
1625 i40e_pf_host_init(dev);
1627 /* register callback func to eal lib */
1628 rte_intr_callback_register(intr_handle,
1629 i40e_dev_interrupt_handler, dev);
1631 /* configure and enable device interrupt */
1632 i40e_pf_config_irq0(hw, TRUE);
1633 i40e_pf_enable_irq0(hw);
1635 /* enable uio intr after callback register */
1636 rte_intr_enable(intr_handle);
1638 /* By default disable flexible payload in global configuration */
1639 if (!pf->support_multi_driver)
1640 i40e_flex_payload_reg_set_default(hw);
1643 * Add an ethertype filter to drop all flow control frames transmitted
1644 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1647 i40e_add_tx_flow_control_drop_filter(pf);
1649 /* Set the max frame size to 0x2600 by default,
1650 * in case other drivers changed the default value.
1652 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, false, 0, NULL);
1654 /* initialize mirror rule list */
1655 TAILQ_INIT(&pf->mirror_list);
1657 /* initialize Traffic Manager configuration */
1658 i40e_tm_conf_init(dev);
1660 /* Initialize customized information */
1661 i40e_init_customized_info(pf);
1663 ret = i40e_init_ethtype_filter_list(dev);
1665 goto err_init_ethtype_filter_list;
1666 ret = i40e_init_tunnel_filter_list(dev);
1668 goto err_init_tunnel_filter_list;
1669 ret = i40e_init_fdir_filter_list(dev);
1671 goto err_init_fdir_filter_list;
1673 /* initialize queue region configuration */
1674 i40e_init_queue_region_conf(dev);
1676 /* initialize rss configuration from rte_flow */
1677 memset(&pf->rss_info, 0,
1678 sizeof(struct i40e_rte_flow_rss_conf));
1680 /* reset all stats of the device, including pf and main vsi */
1681 i40e_dev_stats_reset(dev);
1685 err_init_fdir_filter_list:
1686 rte_free(pf->tunnel.hash_table);
1687 rte_free(pf->tunnel.hash_map);
1688 err_init_tunnel_filter_list:
1689 rte_free(pf->ethertype.hash_table);
1690 rte_free(pf->ethertype.hash_map);
1691 err_init_ethtype_filter_list:
1692 rte_free(dev->data->mac_addrs);
1693 dev->data->mac_addrs = NULL;
1695 i40e_vsi_release(pf->main_vsi);
1696 err_setup_pf_switch:
1698 err_configure_lan_hmc:
1699 (void)i40e_shutdown_lan_hmc(hw);
1701 i40e_res_pool_destroy(&pf->msix_pool);
1703 i40e_res_pool_destroy(&pf->qp_pool);
1706 err_get_capabilities:
1707 (void)i40e_shutdown_adminq(hw);
1713 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1715 struct i40e_ethertype_filter *p_ethertype;
1716 struct i40e_ethertype_rule *ethertype_rule;
1718 ethertype_rule = &pf->ethertype;
1719 /* Remove all ethertype filter rules and hash */
1720 if (ethertype_rule->hash_map)
1721 rte_free(ethertype_rule->hash_map);
1722 if (ethertype_rule->hash_table)
1723 rte_hash_free(ethertype_rule->hash_table);
1725 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1726 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1727 p_ethertype, rules);
1728 rte_free(p_ethertype);
1733 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1735 struct i40e_tunnel_filter *p_tunnel;
1736 struct i40e_tunnel_rule *tunnel_rule;
1738 tunnel_rule = &pf->tunnel;
1739 /* Remove all tunnel director rules and hash */
1740 if (tunnel_rule->hash_map)
1741 rte_free(tunnel_rule->hash_map);
1742 if (tunnel_rule->hash_table)
1743 rte_hash_free(tunnel_rule->hash_table);
1745 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1746 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1752 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1754 struct i40e_fdir_filter *p_fdir;
1755 struct i40e_fdir_info *fdir_info;
1757 fdir_info = &pf->fdir;
1758 /* Remove all flow director rules and hash */
1759 if (fdir_info->hash_map)
1760 rte_free(fdir_info->hash_map);
1761 if (fdir_info->hash_table)
1762 rte_hash_free(fdir_info->hash_table);
1764 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1765 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1770 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1773 * Disable by default flexible payload
1774 * for corresponding L2/L3/L4 layers.
1776 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1777 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1778 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1782 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1786 PMD_INIT_FUNC_TRACE();
1788 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1791 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1793 if (hw->adapter_closed == 0)
1794 i40e_dev_close(dev);
1800 i40e_dev_configure(struct rte_eth_dev *dev)
1802 struct i40e_adapter *ad =
1803 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1804 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1805 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1806 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1809 ret = i40e_dev_sync_phy_type(hw);
1813 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1814 * bulk allocation or vector Rx preconditions we will reset it.
1816 ad->rx_bulk_alloc_allowed = true;
1817 ad->rx_vec_allowed = true;
1818 ad->tx_simple_allowed = true;
1819 ad->tx_vec_allowed = true;
1821 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1822 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1824 /* Only legacy filter API needs the following fdir config. So when the
1825 * legacy filter API is deprecated, the following codes should also be
1828 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1829 ret = i40e_fdir_setup(pf);
1830 if (ret != I40E_SUCCESS) {
1831 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1834 ret = i40e_fdir_configure(dev);
1836 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1840 i40e_fdir_teardown(pf);
1842 ret = i40e_dev_init_vlan(dev);
1847 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1848 * RSS setting have different requirements.
1849 * General PMD driver call sequence are NIC init, configure,
1850 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1851 * will try to lookup the VSI that specific queue belongs to if VMDQ
1852 * applicable. So, VMDQ setting has to be done before
1853 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1854 * For RSS setting, it will try to calculate actual configured RX queue
1855 * number, which will be available after rx_queue_setup(). dev_start()
1856 * function is good to place RSS setup.
1858 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1859 ret = i40e_vmdq_setup(dev);
1864 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1865 ret = i40e_dcb_setup(dev);
1867 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1872 TAILQ_INIT(&pf->flow_list);
1877 /* need to release vmdq resource if exists */
1878 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1879 i40e_vsi_release(pf->vmdq[i].vsi);
1880 pf->vmdq[i].vsi = NULL;
1885 /* Need to release fdir resource if exists.
1886 * Only legacy filter API needs the following fdir config. So when the
1887 * legacy filter API is deprecated, the following code should also be
1890 i40e_fdir_teardown(pf);
1895 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1897 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1898 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1899 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1900 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1901 uint16_t msix_vect = vsi->msix_intr;
1904 for (i = 0; i < vsi->nb_qps; i++) {
1905 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1906 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1910 if (vsi->type != I40E_VSI_SRIOV) {
1911 if (!rte_intr_allow_others(intr_handle)) {
1912 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1913 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1915 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1918 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1919 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1921 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1926 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1927 vsi->user_param + (msix_vect - 1);
1929 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1930 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1932 I40E_WRITE_FLUSH(hw);
1936 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1937 int base_queue, int nb_queue,
1942 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1943 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1945 /* Bind all RX queues to allocated MSIX interrupt */
1946 for (i = 0; i < nb_queue; i++) {
1947 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1948 itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1949 ((base_queue + i + 1) <<
1950 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1951 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1952 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1954 if (i == nb_queue - 1)
1955 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1956 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1959 /* Write first RX queue to Link list register as the head element */
1960 if (vsi->type != I40E_VSI_SRIOV) {
1962 i40e_calc_itr_interval(1, pf->support_multi_driver);
1964 if (msix_vect == I40E_MISC_VEC_ID) {
1965 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1967 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1969 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1971 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1974 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1976 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1978 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1980 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1987 if (msix_vect == I40E_MISC_VEC_ID) {
1989 I40E_VPINT_LNKLST0(vsi->user_param),
1991 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1993 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1995 /* num_msix_vectors_vf needs to minus irq0 */
1996 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1997 vsi->user_param + (msix_vect - 1);
1999 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
2001 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
2003 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2007 I40E_WRITE_FLUSH(hw);
2011 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
2013 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2014 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2015 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2016 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2017 uint16_t msix_vect = vsi->msix_intr;
2018 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2019 uint16_t queue_idx = 0;
2023 for (i = 0; i < vsi->nb_qps; i++) {
2024 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
2025 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2028 /* VF bind interrupt */
2029 if (vsi->type == I40E_VSI_SRIOV) {
2030 __vsi_queues_bind_intr(vsi, msix_vect,
2031 vsi->base_queue, vsi->nb_qps,
2036 /* PF & VMDq bind interrupt */
2037 if (rte_intr_dp_is_en(intr_handle)) {
2038 if (vsi->type == I40E_VSI_MAIN) {
2041 } else if (vsi->type == I40E_VSI_VMDQ2) {
2042 struct i40e_vsi *main_vsi =
2043 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2044 queue_idx = vsi->base_queue - main_vsi->nb_qps;
2049 for (i = 0; i < vsi->nb_used_qps; i++) {
2051 if (!rte_intr_allow_others(intr_handle))
2052 /* allow to share MISC_VEC_ID */
2053 msix_vect = I40E_MISC_VEC_ID;
2055 /* no enough msix_vect, map all to one */
2056 __vsi_queues_bind_intr(vsi, msix_vect,
2057 vsi->base_queue + i,
2058 vsi->nb_used_qps - i,
2060 for (; !!record && i < vsi->nb_used_qps; i++)
2061 intr_handle->intr_vec[queue_idx + i] =
2065 /* 1:1 queue/msix_vect mapping */
2066 __vsi_queues_bind_intr(vsi, msix_vect,
2067 vsi->base_queue + i, 1,
2070 intr_handle->intr_vec[queue_idx + i] = msix_vect;
2078 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2080 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2081 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2082 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2083 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2084 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2085 uint16_t msix_intr, i;
2087 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2088 for (i = 0; i < vsi->nb_msix; i++) {
2089 msix_intr = vsi->msix_intr + i;
2090 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2091 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2092 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2093 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2096 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2097 I40E_PFINT_DYN_CTL0_INTENA_MASK |
2098 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2099 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2101 I40E_WRITE_FLUSH(hw);
2105 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2107 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2108 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2109 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2110 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2111 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2112 uint16_t msix_intr, i;
2114 if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2115 for (i = 0; i < vsi->nb_msix; i++) {
2116 msix_intr = vsi->msix_intr + i;
2117 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2118 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2121 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2122 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2124 I40E_WRITE_FLUSH(hw);
2127 static inline uint8_t
2128 i40e_parse_link_speeds(uint16_t link_speeds)
2130 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2132 if (link_speeds & ETH_LINK_SPEED_40G)
2133 link_speed |= I40E_LINK_SPEED_40GB;
2134 if (link_speeds & ETH_LINK_SPEED_25G)
2135 link_speed |= I40E_LINK_SPEED_25GB;
2136 if (link_speeds & ETH_LINK_SPEED_20G)
2137 link_speed |= I40E_LINK_SPEED_20GB;
2138 if (link_speeds & ETH_LINK_SPEED_10G)
2139 link_speed |= I40E_LINK_SPEED_10GB;
2140 if (link_speeds & ETH_LINK_SPEED_1G)
2141 link_speed |= I40E_LINK_SPEED_1GB;
2142 if (link_speeds & ETH_LINK_SPEED_100M)
2143 link_speed |= I40E_LINK_SPEED_100MB;
2149 i40e_phy_conf_link(struct i40e_hw *hw,
2151 uint8_t force_speed,
2154 enum i40e_status_code status;
2155 struct i40e_aq_get_phy_abilities_resp phy_ab;
2156 struct i40e_aq_set_phy_config phy_conf;
2157 enum i40e_aq_phy_type cnt;
2158 uint8_t avail_speed;
2159 uint32_t phy_type_mask = 0;
2161 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2162 I40E_AQ_PHY_FLAG_PAUSE_RX |
2163 I40E_AQ_PHY_FLAG_PAUSE_RX |
2164 I40E_AQ_PHY_FLAG_LOW_POWER;
2167 /* To get phy capabilities of available speeds. */
2168 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2171 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2175 avail_speed = phy_ab.link_speed;
2177 /* To get the current phy config. */
2178 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2181 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2186 /* If link needs to go up and it is in autoneg mode the speed is OK,
2187 * no need to set up again.
2189 if (is_up && phy_ab.phy_type != 0 &&
2190 abilities & I40E_AQ_PHY_AN_ENABLED &&
2191 phy_ab.link_speed != 0)
2192 return I40E_SUCCESS;
2194 memset(&phy_conf, 0, sizeof(phy_conf));
2196 /* bits 0-2 use the values from get_phy_abilities_resp */
2198 abilities |= phy_ab.abilities & mask;
2200 phy_conf.abilities = abilities;
2202 /* If link needs to go up, but the force speed is not supported,
2203 * Warn users and config the default available speeds.
2205 if (is_up && !(force_speed & avail_speed)) {
2206 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2207 phy_conf.link_speed = avail_speed;
2209 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2212 /* PHY type mask needs to include each type except PHY type extension */
2213 for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2214 phy_type_mask |= 1 << cnt;
2216 /* use get_phy_abilities_resp value for the rest */
2217 phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2218 phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2219 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2220 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2221 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2222 phy_conf.eee_capability = phy_ab.eee_capability;
2223 phy_conf.eeer = phy_ab.eeer_val;
2224 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2226 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2227 phy_ab.abilities, phy_ab.link_speed);
2228 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
2229 phy_conf.abilities, phy_conf.link_speed);
2231 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2235 return I40E_SUCCESS;
2239 i40e_apply_link_speed(struct rte_eth_dev *dev)
2242 uint8_t abilities = 0;
2243 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2244 struct rte_eth_conf *conf = &dev->data->dev_conf;
2246 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2247 I40E_AQ_PHY_LINK_ENABLED;
2249 if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2250 conf->link_speeds = ETH_LINK_SPEED_40G |
2251 ETH_LINK_SPEED_25G |
2252 ETH_LINK_SPEED_20G |
2253 ETH_LINK_SPEED_10G |
2255 ETH_LINK_SPEED_100M;
2257 abilities |= I40E_AQ_PHY_AN_ENABLED;
2259 abilities &= ~I40E_AQ_PHY_AN_ENABLED;
2261 speed = i40e_parse_link_speeds(conf->link_speeds);
2263 return i40e_phy_conf_link(hw, abilities, speed, true);
2267 i40e_dev_start(struct rte_eth_dev *dev)
2269 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2270 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2271 struct i40e_vsi *main_vsi = pf->main_vsi;
2273 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2274 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2275 uint32_t intr_vector = 0;
2276 struct i40e_vsi *vsi;
2278 hw->adapter_stopped = 0;
2280 rte_intr_disable(intr_handle);
2282 if ((rte_intr_cap_multiple(intr_handle) ||
2283 !RTE_ETH_DEV_SRIOV(dev).active) &&
2284 dev->data->dev_conf.intr_conf.rxq != 0) {
2285 intr_vector = dev->data->nb_rx_queues;
2286 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2291 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2292 intr_handle->intr_vec =
2293 rte_zmalloc("intr_vec",
2294 dev->data->nb_rx_queues * sizeof(int),
2296 if (!intr_handle->intr_vec) {
2298 "Failed to allocate %d rx_queues intr_vec",
2299 dev->data->nb_rx_queues);
2304 /* Initialize VSI */
2305 ret = i40e_dev_rxtx_init(pf);
2306 if (ret != I40E_SUCCESS) {
2307 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2311 /* Map queues with MSIX interrupt */
2312 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2313 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2314 i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2315 i40e_vsi_enable_queues_intr(main_vsi);
2317 /* Map VMDQ VSI queues with MSIX interrupt */
2318 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2319 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2320 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2321 I40E_ITR_INDEX_DEFAULT);
2322 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2325 /* enable FDIR MSIX interrupt */
2326 if (pf->fdir.fdir_vsi) {
2327 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2328 I40E_ITR_INDEX_NONE);
2329 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2332 /* Enable all queues which have been configured */
2333 ret = i40e_dev_switch_queues(pf, TRUE);
2334 if (ret != I40E_SUCCESS) {
2335 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2339 /* Enable receiving broadcast packets */
2340 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2341 if (ret != I40E_SUCCESS)
2342 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2344 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2345 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2347 if (ret != I40E_SUCCESS)
2348 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2351 /* Enable the VLAN promiscuous mode. */
2353 for (i = 0; i < pf->vf_num; i++) {
2354 vsi = pf->vfs[i].vsi;
2355 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2360 /* Enable mac loopback mode */
2361 if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2362 dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2363 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2364 if (ret != I40E_SUCCESS) {
2365 PMD_DRV_LOG(ERR, "fail to set loopback link");
2370 /* Apply link configure */
2371 ret = i40e_apply_link_speed(dev);
2372 if (I40E_SUCCESS != ret) {
2373 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2377 if (!rte_intr_allow_others(intr_handle)) {
2378 rte_intr_callback_unregister(intr_handle,
2379 i40e_dev_interrupt_handler,
2381 /* configure and enable device interrupt */
2382 i40e_pf_config_irq0(hw, FALSE);
2383 i40e_pf_enable_irq0(hw);
2385 if (dev->data->dev_conf.intr_conf.lsc != 0)
2387 "lsc won't enable because of no intr multiplex");
2389 ret = i40e_aq_set_phy_int_mask(hw,
2390 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2391 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2392 I40E_AQ_EVENT_MEDIA_NA), NULL);
2393 if (ret != I40E_SUCCESS)
2394 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2396 /* Call get_link_info aq commond to enable/disable LSE */
2397 i40e_dev_link_update(dev, 0);
2400 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2401 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2402 i40e_dev_alarm_handler, dev);
2404 /* enable uio intr after callback register */
2405 rte_intr_enable(intr_handle);
2408 i40e_filter_restore(pf);
2410 if (pf->tm_conf.root && !pf->tm_conf.committed)
2411 PMD_DRV_LOG(WARNING,
2412 "please call hierarchy_commit() "
2413 "before starting the port");
2415 return I40E_SUCCESS;
2418 i40e_dev_switch_queues(pf, FALSE);
2419 i40e_dev_clear_queues(dev);
2425 i40e_dev_stop(struct rte_eth_dev *dev)
2427 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2428 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2429 struct i40e_vsi *main_vsi = pf->main_vsi;
2430 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2431 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2434 if (hw->adapter_stopped == 1)
2437 if (dev->data->dev_conf.intr_conf.rxq == 0) {
2438 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2439 rte_intr_enable(intr_handle);
2442 /* Disable all queues */
2443 i40e_dev_switch_queues(pf, FALSE);
2445 /* un-map queues with interrupt registers */
2446 i40e_vsi_disable_queues_intr(main_vsi);
2447 i40e_vsi_queues_unbind_intr(main_vsi);
2449 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2450 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2451 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2454 if (pf->fdir.fdir_vsi) {
2455 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2456 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2458 /* Clear all queues and release memory */
2459 i40e_dev_clear_queues(dev);
2462 i40e_dev_set_link_down(dev);
2464 if (!rte_intr_allow_others(intr_handle))
2465 /* resume to the default handler */
2466 rte_intr_callback_register(intr_handle,
2467 i40e_dev_interrupt_handler,
2470 /* Clean datapath event and queue/vec mapping */
2471 rte_intr_efd_disable(intr_handle);
2472 if (intr_handle->intr_vec) {
2473 rte_free(intr_handle->intr_vec);
2474 intr_handle->intr_vec = NULL;
2477 /* reset hierarchy commit */
2478 pf->tm_conf.committed = false;
2480 hw->adapter_stopped = 1;
2482 pf->adapter->rss_reta_updated = 0;
2486 i40e_dev_close(struct rte_eth_dev *dev)
2488 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2489 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2490 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2491 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2492 struct i40e_mirror_rule *p_mirror;
2493 struct i40e_filter_control_settings settings;
2494 struct rte_flow *p_flow;
2498 uint8_t aq_fail = 0;
2501 PMD_INIT_FUNC_TRACE();
2503 ret = rte_eth_switch_domain_free(pf->switch_domain_id);
2505 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
2510 /* Remove all mirror rules */
2511 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2512 ret = i40e_aq_del_mirror_rule(hw,
2513 pf->main_vsi->veb->seid,
2514 p_mirror->rule_type,
2516 p_mirror->num_entries,
2519 PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2520 "status = %d, aq_err = %d.", ret,
2521 hw->aq.asq_last_status);
2523 /* remove mirror software resource anyway */
2524 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2526 pf->nb_mirror_rule--;
2529 i40e_dev_free_queues(dev);
2531 /* Disable interrupt */
2532 i40e_pf_disable_irq0(hw);
2533 rte_intr_disable(intr_handle);
2536 * Only legacy filter API needs the following fdir config. So when the
2537 * legacy filter API is deprecated, the following code should also be
2540 i40e_fdir_teardown(pf);
2542 /* shutdown and destroy the HMC */
2543 i40e_shutdown_lan_hmc(hw);
2545 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2546 i40e_vsi_release(pf->vmdq[i].vsi);
2547 pf->vmdq[i].vsi = NULL;
2552 /* release all the existing VSIs and VEBs */
2553 i40e_vsi_release(pf->main_vsi);
2555 /* shutdown the adminq */
2556 i40e_aq_queue_shutdown(hw, true);
2557 i40e_shutdown_adminq(hw);
2559 i40e_res_pool_destroy(&pf->qp_pool);
2560 i40e_res_pool_destroy(&pf->msix_pool);
2562 /* Disable flexible payload in global configuration */
2563 if (!pf->support_multi_driver)
2564 i40e_flex_payload_reg_set_default(hw);
2566 /* force a PF reset to clean anything leftover */
2567 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2568 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2569 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2570 I40E_WRITE_FLUSH(hw);
2572 dev->dev_ops = NULL;
2573 dev->rx_pkt_burst = NULL;
2574 dev->tx_pkt_burst = NULL;
2576 /* Clear PXE mode */
2577 i40e_clear_pxe_mode(hw);
2579 /* Unconfigure filter control */
2580 memset(&settings, 0, sizeof(settings));
2581 ret = i40e_set_filter_control(hw, &settings);
2583 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
2586 /* Disable flow control */
2587 hw->fc.requested_mode = I40E_FC_NONE;
2588 i40e_set_fc(hw, &aq_fail, TRUE);
2590 /* uninitialize pf host driver */
2591 i40e_pf_host_uninit(dev);
2594 ret = rte_intr_callback_unregister(intr_handle,
2595 i40e_dev_interrupt_handler, dev);
2596 if (ret >= 0 || ret == -ENOENT) {
2598 } else if (ret != -EAGAIN) {
2600 "intr callback unregister failed: %d",
2603 i40e_msec_delay(500);
2604 } while (retries++ < 5);
2606 i40e_rm_ethtype_filter_list(pf);
2607 i40e_rm_tunnel_filter_list(pf);
2608 i40e_rm_fdir_filter_list(pf);
2610 /* Remove all flows */
2611 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
2612 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
2616 /* Remove all Traffic Manager configuration */
2617 i40e_tm_conf_uninit(dev);
2619 hw->adapter_closed = 1;
2623 * Reset PF device only to re-initialize resources in PMD layer
2626 i40e_dev_reset(struct rte_eth_dev *dev)
2630 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2631 * its VF to make them align with it. The detailed notification
2632 * mechanism is PMD specific. As to i40e PF, it is rather complex.
2633 * To avoid unexpected behavior in VF, currently reset of PF with
2634 * SR-IOV activation is not supported. It might be supported later.
2636 if (dev->data->sriov.active)
2639 ret = eth_i40e_dev_uninit(dev);
2643 ret = eth_i40e_dev_init(dev, NULL);
2649 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2651 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2652 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2653 struct i40e_vsi *vsi = pf->main_vsi;
2656 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2658 if (status != I40E_SUCCESS) {
2659 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2663 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2665 if (status != I40E_SUCCESS) {
2666 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2667 /* Rollback unicast promiscuous mode */
2668 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2677 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2679 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2680 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2681 struct i40e_vsi *vsi = pf->main_vsi;
2684 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2686 if (status != I40E_SUCCESS) {
2687 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2691 /* must remain in all_multicast mode */
2692 if (dev->data->all_multicast == 1)
2695 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2697 if (status != I40E_SUCCESS) {
2698 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2699 /* Rollback unicast promiscuous mode */
2700 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2709 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2711 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2712 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2713 struct i40e_vsi *vsi = pf->main_vsi;
2716 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2717 if (ret != I40E_SUCCESS) {
2718 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2726 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2728 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2729 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2730 struct i40e_vsi *vsi = pf->main_vsi;
2733 if (dev->data->promiscuous == 1)
2734 return 0; /* must remain in all_multicast mode */
2736 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2737 vsi->seid, FALSE, NULL);
2738 if (ret != I40E_SUCCESS) {
2739 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2747 * Set device link up.
2750 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2752 /* re-apply link speed setting */
2753 return i40e_apply_link_speed(dev);
2757 * Set device link down.
2760 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2762 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2763 uint8_t abilities = 0;
2764 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2766 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2767 return i40e_phy_conf_link(hw, abilities, speed, false);
2770 static __rte_always_inline void
2771 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2773 /* Link status registers and values*/
2774 #define I40E_PRTMAC_LINKSTA 0x001E2420
2775 #define I40E_REG_LINK_UP 0x40000080
2776 #define I40E_PRTMAC_MACC 0x001E24E0
2777 #define I40E_REG_MACC_25GB 0x00020000
2778 #define I40E_REG_SPEED_MASK 0x38000000
2779 #define I40E_REG_SPEED_0 0x00000000
2780 #define I40E_REG_SPEED_1 0x08000000
2781 #define I40E_REG_SPEED_2 0x10000000
2782 #define I40E_REG_SPEED_3 0x18000000
2783 #define I40E_REG_SPEED_4 0x20000000
2784 uint32_t link_speed;
2787 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2788 link_speed = reg_val & I40E_REG_SPEED_MASK;
2789 reg_val &= I40E_REG_LINK_UP;
2790 link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2792 if (unlikely(link->link_status == 0))
2795 /* Parse the link status */
2796 switch (link_speed) {
2797 case I40E_REG_SPEED_0:
2798 link->link_speed = ETH_SPEED_NUM_100M;
2800 case I40E_REG_SPEED_1:
2801 link->link_speed = ETH_SPEED_NUM_1G;
2803 case I40E_REG_SPEED_2:
2804 if (hw->mac.type == I40E_MAC_X722)
2805 link->link_speed = ETH_SPEED_NUM_2_5G;
2807 link->link_speed = ETH_SPEED_NUM_10G;
2809 case I40E_REG_SPEED_3:
2810 if (hw->mac.type == I40E_MAC_X722) {
2811 link->link_speed = ETH_SPEED_NUM_5G;
2813 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2815 if (reg_val & I40E_REG_MACC_25GB)
2816 link->link_speed = ETH_SPEED_NUM_25G;
2818 link->link_speed = ETH_SPEED_NUM_40G;
2821 case I40E_REG_SPEED_4:
2822 if (hw->mac.type == I40E_MAC_X722)
2823 link->link_speed = ETH_SPEED_NUM_10G;
2825 link->link_speed = ETH_SPEED_NUM_20G;
2828 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2833 static __rte_always_inline void
2834 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2835 bool enable_lse, int wait_to_complete)
2837 #define CHECK_INTERVAL 100 /* 100ms */
2838 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2839 uint32_t rep_cnt = MAX_REPEAT_TIME;
2840 struct i40e_link_status link_status;
2843 memset(&link_status, 0, sizeof(link_status));
2846 memset(&link_status, 0, sizeof(link_status));
2848 /* Get link status information from hardware */
2849 status = i40e_aq_get_link_info(hw, enable_lse,
2850 &link_status, NULL);
2851 if (unlikely(status != I40E_SUCCESS)) {
2852 link->link_speed = ETH_SPEED_NUM_NONE;
2853 link->link_duplex = ETH_LINK_FULL_DUPLEX;
2854 PMD_DRV_LOG(ERR, "Failed to get link info");
2858 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2859 if (!wait_to_complete || link->link_status)
2862 rte_delay_ms(CHECK_INTERVAL);
2863 } while (--rep_cnt);
2865 /* Parse the link status */
2866 switch (link_status.link_speed) {
2867 case I40E_LINK_SPEED_100MB:
2868 link->link_speed = ETH_SPEED_NUM_100M;
2870 case I40E_LINK_SPEED_1GB:
2871 link->link_speed = ETH_SPEED_NUM_1G;
2873 case I40E_LINK_SPEED_10GB:
2874 link->link_speed = ETH_SPEED_NUM_10G;
2876 case I40E_LINK_SPEED_20GB:
2877 link->link_speed = ETH_SPEED_NUM_20G;
2879 case I40E_LINK_SPEED_25GB:
2880 link->link_speed = ETH_SPEED_NUM_25G;
2882 case I40E_LINK_SPEED_40GB:
2883 link->link_speed = ETH_SPEED_NUM_40G;
2886 link->link_speed = ETH_SPEED_NUM_NONE;
2892 i40e_dev_link_update(struct rte_eth_dev *dev,
2893 int wait_to_complete)
2895 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2896 struct rte_eth_link link;
2897 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2900 memset(&link, 0, sizeof(link));
2902 /* i40e uses full duplex only */
2903 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2904 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2905 ETH_LINK_SPEED_FIXED);
2907 if (!wait_to_complete && !enable_lse)
2908 update_link_reg(hw, &link);
2910 update_link_aq(hw, &link, enable_lse, wait_to_complete);
2913 rte_eth_linkstatus_get(hw->switch_dev, &link);
2915 ret = rte_eth_linkstatus_set(dev, &link);
2916 i40e_notify_all_vfs_link_status(dev);
2921 /* Get all the statistics of a VSI */
2923 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2925 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2926 struct i40e_eth_stats *nes = &vsi->eth_stats;
2927 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2928 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2930 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2931 vsi->offset_loaded, &oes->rx_bytes,
2933 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2934 vsi->offset_loaded, &oes->rx_unicast,
2936 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2937 vsi->offset_loaded, &oes->rx_multicast,
2938 &nes->rx_multicast);
2939 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2940 vsi->offset_loaded, &oes->rx_broadcast,
2941 &nes->rx_broadcast);
2942 /* exclude CRC bytes */
2943 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2944 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
2946 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2947 &oes->rx_discards, &nes->rx_discards);
2948 /* GLV_REPC not supported */
2949 /* GLV_RMPC not supported */
2950 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2951 &oes->rx_unknown_protocol,
2952 &nes->rx_unknown_protocol);
2953 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2954 vsi->offset_loaded, &oes->tx_bytes,
2956 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2957 vsi->offset_loaded, &oes->tx_unicast,
2959 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2960 vsi->offset_loaded, &oes->tx_multicast,
2961 &nes->tx_multicast);
2962 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2963 vsi->offset_loaded, &oes->tx_broadcast,
2964 &nes->tx_broadcast);
2965 /* GLV_TDPC not supported */
2966 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2967 &oes->tx_errors, &nes->tx_errors);
2968 vsi->offset_loaded = true;
2970 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2972 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2973 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2974 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2975 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2976 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2977 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2978 nes->rx_unknown_protocol);
2979 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2980 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2981 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2982 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2983 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2984 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2985 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2990 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2993 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2994 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2996 /* Get rx/tx bytes of internal transfer packets */
2997 i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2998 I40E_GLV_GORCL(hw->port),
3000 &pf->internal_stats_offset.rx_bytes,
3001 &pf->internal_stats.rx_bytes);
3003 i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
3004 I40E_GLV_GOTCL(hw->port),
3006 &pf->internal_stats_offset.tx_bytes,
3007 &pf->internal_stats.tx_bytes);
3008 /* Get total internal rx packet count */
3009 i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
3010 I40E_GLV_UPRCL(hw->port),
3012 &pf->internal_stats_offset.rx_unicast,
3013 &pf->internal_stats.rx_unicast);
3014 i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
3015 I40E_GLV_MPRCL(hw->port),
3017 &pf->internal_stats_offset.rx_multicast,
3018 &pf->internal_stats.rx_multicast);
3019 i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
3020 I40E_GLV_BPRCL(hw->port),
3022 &pf->internal_stats_offset.rx_broadcast,
3023 &pf->internal_stats.rx_broadcast);
3024 /* Get total internal tx packet count */
3025 i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
3026 I40E_GLV_UPTCL(hw->port),
3028 &pf->internal_stats_offset.tx_unicast,
3029 &pf->internal_stats.tx_unicast);
3030 i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
3031 I40E_GLV_MPTCL(hw->port),
3033 &pf->internal_stats_offset.tx_multicast,
3034 &pf->internal_stats.tx_multicast);
3035 i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
3036 I40E_GLV_BPTCL(hw->port),
3038 &pf->internal_stats_offset.tx_broadcast,
3039 &pf->internal_stats.tx_broadcast);
3041 /* exclude CRC size */
3042 pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
3043 pf->internal_stats.rx_multicast +
3044 pf->internal_stats.rx_broadcast) * RTE_ETHER_CRC_LEN;
3046 /* Get statistics of struct i40e_eth_stats */
3047 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
3048 I40E_GLPRT_GORCL(hw->port),
3049 pf->offset_loaded, &os->eth.rx_bytes,
3051 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
3052 I40E_GLPRT_UPRCL(hw->port),
3053 pf->offset_loaded, &os->eth.rx_unicast,
3054 &ns->eth.rx_unicast);
3055 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
3056 I40E_GLPRT_MPRCL(hw->port),
3057 pf->offset_loaded, &os->eth.rx_multicast,
3058 &ns->eth.rx_multicast);
3059 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
3060 I40E_GLPRT_BPRCL(hw->port),
3061 pf->offset_loaded, &os->eth.rx_broadcast,
3062 &ns->eth.rx_broadcast);
3063 /* Workaround: CRC size should not be included in byte statistics,
3064 * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
3067 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
3068 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
3070 /* exclude internal rx bytes
3071 * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
3072 * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
3074 * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
3076 if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
3077 ns->eth.rx_bytes = 0;
3079 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
3081 if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
3082 ns->eth.rx_unicast = 0;
3084 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
3086 if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
3087 ns->eth.rx_multicast = 0;
3089 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
3091 if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
3092 ns->eth.rx_broadcast = 0;
3094 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
3096 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
3097 pf->offset_loaded, &os->eth.rx_discards,
3098 &ns->eth.rx_discards);
3099 /* GLPRT_REPC not supported */
3100 /* GLPRT_RMPC not supported */
3101 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
3103 &os->eth.rx_unknown_protocol,
3104 &ns->eth.rx_unknown_protocol);
3105 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
3106 I40E_GLPRT_GOTCL(hw->port),
3107 pf->offset_loaded, &os->eth.tx_bytes,
3109 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
3110 I40E_GLPRT_UPTCL(hw->port),
3111 pf->offset_loaded, &os->eth.tx_unicast,
3112 &ns->eth.tx_unicast);
3113 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
3114 I40E_GLPRT_MPTCL(hw->port),
3115 pf->offset_loaded, &os->eth.tx_multicast,
3116 &ns->eth.tx_multicast);
3117 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
3118 I40E_GLPRT_BPTCL(hw->port),
3119 pf->offset_loaded, &os->eth.tx_broadcast,
3120 &ns->eth.tx_broadcast);
3121 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3122 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3124 /* exclude internal tx bytes
3125 * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
3126 * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
3128 * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
3130 if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
3131 ns->eth.tx_bytes = 0;
3133 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3135 if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3136 ns->eth.tx_unicast = 0;
3138 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3140 if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3141 ns->eth.tx_multicast = 0;
3143 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3145 if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3146 ns->eth.tx_broadcast = 0;
3148 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3150 /* GLPRT_TEPC not supported */
3152 /* additional port specific stats */
3153 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3154 pf->offset_loaded, &os->tx_dropped_link_down,
3155 &ns->tx_dropped_link_down);
3156 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3157 pf->offset_loaded, &os->crc_errors,
3159 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3160 pf->offset_loaded, &os->illegal_bytes,
3161 &ns->illegal_bytes);
3162 /* GLPRT_ERRBC not supported */
3163 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3164 pf->offset_loaded, &os->mac_local_faults,
3165 &ns->mac_local_faults);
3166 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3167 pf->offset_loaded, &os->mac_remote_faults,
3168 &ns->mac_remote_faults);
3169 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3170 pf->offset_loaded, &os->rx_length_errors,
3171 &ns->rx_length_errors);
3172 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3173 pf->offset_loaded, &os->link_xon_rx,
3175 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3176 pf->offset_loaded, &os->link_xoff_rx,
3178 for (i = 0; i < 8; i++) {
3179 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3181 &os->priority_xon_rx[i],
3182 &ns->priority_xon_rx[i]);
3183 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3185 &os->priority_xoff_rx[i],
3186 &ns->priority_xoff_rx[i]);
3188 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3189 pf->offset_loaded, &os->link_xon_tx,
3191 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3192 pf->offset_loaded, &os->link_xoff_tx,
3194 for (i = 0; i < 8; i++) {
3195 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3197 &os->priority_xon_tx[i],
3198 &ns->priority_xon_tx[i]);
3199 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3201 &os->priority_xoff_tx[i],
3202 &ns->priority_xoff_tx[i]);
3203 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3205 &os->priority_xon_2_xoff[i],
3206 &ns->priority_xon_2_xoff[i]);
3208 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3209 I40E_GLPRT_PRC64L(hw->port),
3210 pf->offset_loaded, &os->rx_size_64,
3212 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3213 I40E_GLPRT_PRC127L(hw->port),
3214 pf->offset_loaded, &os->rx_size_127,
3216 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3217 I40E_GLPRT_PRC255L(hw->port),
3218 pf->offset_loaded, &os->rx_size_255,
3220 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3221 I40E_GLPRT_PRC511L(hw->port),
3222 pf->offset_loaded, &os->rx_size_511,
3224 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3225 I40E_GLPRT_PRC1023L(hw->port),
3226 pf->offset_loaded, &os->rx_size_1023,
3228 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3229 I40E_GLPRT_PRC1522L(hw->port),
3230 pf->offset_loaded, &os->rx_size_1522,
3232 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3233 I40E_GLPRT_PRC9522L(hw->port),
3234 pf->offset_loaded, &os->rx_size_big,
3236 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3237 pf->offset_loaded, &os->rx_undersize,
3239 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3240 pf->offset_loaded, &os->rx_fragments,
3242 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3243 pf->offset_loaded, &os->rx_oversize,
3245 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3246 pf->offset_loaded, &os->rx_jabber,
3248 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3249 I40E_GLPRT_PTC64L(hw->port),
3250 pf->offset_loaded, &os->tx_size_64,
3252 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3253 I40E_GLPRT_PTC127L(hw->port),
3254 pf->offset_loaded, &os->tx_size_127,
3256 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3257 I40E_GLPRT_PTC255L(hw->port),
3258 pf->offset_loaded, &os->tx_size_255,
3260 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3261 I40E_GLPRT_PTC511L(hw->port),
3262 pf->offset_loaded, &os->tx_size_511,
3264 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3265 I40E_GLPRT_PTC1023L(hw->port),
3266 pf->offset_loaded, &os->tx_size_1023,
3268 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3269 I40E_GLPRT_PTC1522L(hw->port),
3270 pf->offset_loaded, &os->tx_size_1522,
3272 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3273 I40E_GLPRT_PTC9522L(hw->port),
3274 pf->offset_loaded, &os->tx_size_big,
3276 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3278 &os->fd_sb_match, &ns->fd_sb_match);
3279 /* GLPRT_MSPDC not supported */
3280 /* GLPRT_XEC not supported */
3282 pf->offset_loaded = true;
3285 i40e_update_vsi_stats(pf->main_vsi);
3288 /* Get all statistics of a port */
3290 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3292 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3293 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3294 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3295 struct i40e_vsi *vsi;
3298 /* call read registers - updates values, now write them to struct */
3299 i40e_read_stats_registers(pf, hw);
3301 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3302 pf->main_vsi->eth_stats.rx_multicast +
3303 pf->main_vsi->eth_stats.rx_broadcast -
3304 pf->main_vsi->eth_stats.rx_discards;
3305 stats->opackets = ns->eth.tx_unicast +
3306 ns->eth.tx_multicast +
3307 ns->eth.tx_broadcast;
3308 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes;
3309 stats->obytes = ns->eth.tx_bytes;
3310 stats->oerrors = ns->eth.tx_errors +
3311 pf->main_vsi->eth_stats.tx_errors;
3314 stats->imissed = ns->eth.rx_discards +
3315 pf->main_vsi->eth_stats.rx_discards;
3316 stats->ierrors = ns->crc_errors +
3317 ns->rx_length_errors + ns->rx_undersize +
3318 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3321 for (i = 0; i < pf->vf_num; i++) {
3322 vsi = pf->vfs[i].vsi;
3323 i40e_update_vsi_stats(vsi);
3325 stats->ipackets += (vsi->eth_stats.rx_unicast +
3326 vsi->eth_stats.rx_multicast +
3327 vsi->eth_stats.rx_broadcast -
3328 vsi->eth_stats.rx_discards);
3329 stats->ibytes += vsi->eth_stats.rx_bytes;
3330 stats->oerrors += vsi->eth_stats.tx_errors;
3331 stats->imissed += vsi->eth_stats.rx_discards;
3335 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3336 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
3337 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
3338 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
3339 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
3340 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
3341 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3342 ns->eth.rx_unknown_protocol);
3343 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
3344 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
3345 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
3346 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
3347 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
3348 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
3350 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
3351 ns->tx_dropped_link_down);
3352 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
3353 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
3355 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
3356 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
3357 ns->mac_local_faults);
3358 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
3359 ns->mac_remote_faults);
3360 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
3361 ns->rx_length_errors);
3362 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
3363 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
3364 for (i = 0; i < 8; i++) {
3365 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
3366 i, ns->priority_xon_rx[i]);
3367 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
3368 i, ns->priority_xoff_rx[i]);
3370 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
3371 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
3372 for (i = 0; i < 8; i++) {
3373 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
3374 i, ns->priority_xon_tx[i]);
3375 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
3376 i, ns->priority_xoff_tx[i]);
3377 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
3378 i, ns->priority_xon_2_xoff[i]);
3380 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
3381 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
3382 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
3383 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
3384 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
3385 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
3386 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
3387 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
3388 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
3389 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
3390 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
3391 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
3392 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
3393 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
3394 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
3395 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
3396 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
3397 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
3398 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3399 ns->mac_short_packet_dropped);
3400 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
3401 ns->checksum_error);
3402 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
3403 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3407 /* Reset the statistics */
3409 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3411 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3412 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3414 /* Mark PF and VSI stats to update the offset, aka "reset" */
3415 pf->offset_loaded = false;
3417 pf->main_vsi->offset_loaded = false;
3419 /* read the stats, reading current register values into offset */
3420 i40e_read_stats_registers(pf, hw);
3426 i40e_xstats_calc_num(void)
3428 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3429 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3430 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3433 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3434 struct rte_eth_xstat_name *xstats_names,
3435 __rte_unused unsigned limit)
3440 if (xstats_names == NULL)
3441 return i40e_xstats_calc_num();
3443 /* Note: limit checked in rte_eth_xstats_names() */
3445 /* Get stats from i40e_eth_stats struct */
3446 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3447 strlcpy(xstats_names[count].name,
3448 rte_i40e_stats_strings[i].name,
3449 sizeof(xstats_names[count].name));
3453 /* Get individiual stats from i40e_hw_port struct */
3454 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3455 strlcpy(xstats_names[count].name,
3456 rte_i40e_hw_port_strings[i].name,
3457 sizeof(xstats_names[count].name));
3461 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3462 for (prio = 0; prio < 8; prio++) {
3463 snprintf(xstats_names[count].name,
3464 sizeof(xstats_names[count].name),
3465 "rx_priority%u_%s", prio,
3466 rte_i40e_rxq_prio_strings[i].name);
3471 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3472 for (prio = 0; prio < 8; prio++) {
3473 snprintf(xstats_names[count].name,
3474 sizeof(xstats_names[count].name),
3475 "tx_priority%u_%s", prio,
3476 rte_i40e_txq_prio_strings[i].name);
3484 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3487 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3488 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3489 unsigned i, count, prio;
3490 struct i40e_hw_port_stats *hw_stats = &pf->stats;
3492 count = i40e_xstats_calc_num();
3496 i40e_read_stats_registers(pf, hw);
3503 /* Get stats from i40e_eth_stats struct */
3504 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3505 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3506 rte_i40e_stats_strings[i].offset);
3507 xstats[count].id = count;
3511 /* Get individiual stats from i40e_hw_port struct */
3512 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3513 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3514 rte_i40e_hw_port_strings[i].offset);
3515 xstats[count].id = count;
3519 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3520 for (prio = 0; prio < 8; prio++) {
3521 xstats[count].value =
3522 *(uint64_t *)(((char *)hw_stats) +
3523 rte_i40e_rxq_prio_strings[i].offset +
3524 (sizeof(uint64_t) * prio));
3525 xstats[count].id = count;
3530 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3531 for (prio = 0; prio < 8; prio++) {
3532 xstats[count].value =
3533 *(uint64_t *)(((char *)hw_stats) +
3534 rte_i40e_txq_prio_strings[i].offset +
3535 (sizeof(uint64_t) * prio));
3536 xstats[count].id = count;
3545 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3547 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3553 full_ver = hw->nvm.oem_ver;
3554 ver = (u8)(full_ver >> 24);
3555 build = (u16)((full_ver >> 8) & 0xffff);
3556 patch = (u8)(full_ver & 0xff);
3558 ret = snprintf(fw_version, fw_size,
3559 "%d.%d%d 0x%08x %d.%d.%d",
3560 ((hw->nvm.version >> 12) & 0xf),
3561 ((hw->nvm.version >> 4) & 0xff),
3562 (hw->nvm.version & 0xf), hw->nvm.eetrack,
3565 ret += 1; /* add the size of '\0' */
3566 if (fw_size < (u32)ret)
3573 * When using NVM 6.01(for X710 XL710 XXV710)/3.33(for X722) or later,
3574 * the Rx data path does not hang if the FW LLDP is stopped.
3575 * return true if lldp need to stop
3576 * return false if we cannot disable the LLDP to avoid Rx data path blocking.
3579 i40e_need_stop_lldp(struct rte_eth_dev *dev)
3582 char ver_str[64] = {0};
3583 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3585 i40e_fw_version_get(dev, ver_str, 64);
3586 nvm_ver = atof(ver_str);
3587 if ((hw->mac.type == I40E_MAC_X722 ||
3588 hw->mac.type == I40E_MAC_X722_VF) &&
3589 ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(3.33 * 1000)))
3591 else if ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(6.01 * 1000))
3598 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3600 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3601 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3602 struct i40e_vsi *vsi = pf->main_vsi;
3603 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3605 dev_info->max_rx_queues = vsi->nb_qps;
3606 dev_info->max_tx_queues = vsi->nb_qps;
3607 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3608 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3609 dev_info->max_mac_addrs = vsi->max_macaddrs;
3610 dev_info->max_vfs = pci_dev->max_vfs;
3611 dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
3612 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3613 dev_info->rx_queue_offload_capa = 0;
3614 dev_info->rx_offload_capa =
3615 DEV_RX_OFFLOAD_VLAN_STRIP |
3616 DEV_RX_OFFLOAD_QINQ_STRIP |
3617 DEV_RX_OFFLOAD_IPV4_CKSUM |
3618 DEV_RX_OFFLOAD_UDP_CKSUM |
3619 DEV_RX_OFFLOAD_TCP_CKSUM |
3620 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3621 DEV_RX_OFFLOAD_KEEP_CRC |
3622 DEV_RX_OFFLOAD_SCATTER |
3623 DEV_RX_OFFLOAD_VLAN_EXTEND |
3624 DEV_RX_OFFLOAD_VLAN_FILTER |
3625 DEV_RX_OFFLOAD_JUMBO_FRAME |
3626 DEV_RX_OFFLOAD_RSS_HASH;
3628 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3629 dev_info->tx_offload_capa =
3630 DEV_TX_OFFLOAD_VLAN_INSERT |
3631 DEV_TX_OFFLOAD_QINQ_INSERT |
3632 DEV_TX_OFFLOAD_IPV4_CKSUM |
3633 DEV_TX_OFFLOAD_UDP_CKSUM |
3634 DEV_TX_OFFLOAD_TCP_CKSUM |
3635 DEV_TX_OFFLOAD_SCTP_CKSUM |
3636 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3637 DEV_TX_OFFLOAD_TCP_TSO |
3638 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3639 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3640 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3641 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3642 DEV_TX_OFFLOAD_MULTI_SEGS |
3643 dev_info->tx_queue_offload_capa;
3644 dev_info->dev_capa =
3645 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3646 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3648 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3650 dev_info->reta_size = pf->hash_lut_size;
3651 dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3653 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3655 .pthresh = I40E_DEFAULT_RX_PTHRESH,
3656 .hthresh = I40E_DEFAULT_RX_HTHRESH,
3657 .wthresh = I40E_DEFAULT_RX_WTHRESH,
3659 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3664 dev_info->default_txconf = (struct rte_eth_txconf) {
3666 .pthresh = I40E_DEFAULT_TX_PTHRESH,
3667 .hthresh = I40E_DEFAULT_TX_HTHRESH,
3668 .wthresh = I40E_DEFAULT_TX_WTHRESH,
3670 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3671 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3675 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3676 .nb_max = I40E_MAX_RING_DESC,
3677 .nb_min = I40E_MIN_RING_DESC,
3678 .nb_align = I40E_ALIGN_RING_DESC,
3681 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3682 .nb_max = I40E_MAX_RING_DESC,
3683 .nb_min = I40E_MIN_RING_DESC,
3684 .nb_align = I40E_ALIGN_RING_DESC,
3685 .nb_seg_max = I40E_TX_MAX_SEG,
3686 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3689 if (pf->flags & I40E_FLAG_VMDQ) {
3690 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3691 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3692 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3693 pf->max_nb_vmdq_vsi;
3694 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3695 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3696 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3699 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3701 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3702 dev_info->default_rxportconf.nb_queues = 2;
3703 dev_info->default_txportconf.nb_queues = 2;
3704 if (dev->data->nb_rx_queues == 1)
3705 dev_info->default_rxportconf.ring_size = 2048;
3707 dev_info->default_rxportconf.ring_size = 1024;
3708 if (dev->data->nb_tx_queues == 1)
3709 dev_info->default_txportconf.ring_size = 1024;
3711 dev_info->default_txportconf.ring_size = 512;
3713 } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3715 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3716 dev_info->default_rxportconf.nb_queues = 1;
3717 dev_info->default_txportconf.nb_queues = 1;
3718 dev_info->default_rxportconf.ring_size = 256;
3719 dev_info->default_txportconf.ring_size = 256;
3722 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3723 dev_info->default_rxportconf.nb_queues = 1;
3724 dev_info->default_txportconf.nb_queues = 1;
3725 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3726 dev_info->default_rxportconf.ring_size = 512;
3727 dev_info->default_txportconf.ring_size = 256;
3729 dev_info->default_rxportconf.ring_size = 256;
3730 dev_info->default_txportconf.ring_size = 256;
3733 dev_info->default_rxportconf.burst_size = 32;
3734 dev_info->default_txportconf.burst_size = 32;
3740 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3742 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3743 struct i40e_vsi *vsi = pf->main_vsi;
3744 PMD_INIT_FUNC_TRACE();
3747 return i40e_vsi_add_vlan(vsi, vlan_id);
3749 return i40e_vsi_delete_vlan(vsi, vlan_id);
3753 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3754 enum rte_vlan_type vlan_type,
3755 uint16_t tpid, int qinq)
3757 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3760 uint16_t reg_id = 3;
3764 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3768 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3770 if (ret != I40E_SUCCESS) {
3772 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3777 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3780 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3781 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3782 if (reg_r == reg_w) {
3783 PMD_DRV_LOG(DEBUG, "No need to write");
3787 ret = i40e_aq_debug_write_global_register(hw,
3788 I40E_GL_SWT_L2TAGCTRL(reg_id),
3790 if (ret != I40E_SUCCESS) {
3792 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3797 "Global register 0x%08x is changed with value 0x%08x",
3798 I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3804 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3805 enum rte_vlan_type vlan_type,
3808 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3809 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3810 int qinq = dev->data->dev_conf.rxmode.offloads &
3811 DEV_RX_OFFLOAD_VLAN_EXTEND;
3814 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3815 vlan_type != ETH_VLAN_TYPE_OUTER) ||
3816 (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3818 "Unsupported vlan type.");
3822 if (pf->support_multi_driver) {
3823 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3827 /* 802.1ad frames ability is added in NVM API 1.7*/
3828 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3830 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3831 hw->first_tag = rte_cpu_to_le_16(tpid);
3832 else if (vlan_type == ETH_VLAN_TYPE_INNER)
3833 hw->second_tag = rte_cpu_to_le_16(tpid);
3835 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3836 hw->second_tag = rte_cpu_to_le_16(tpid);
3838 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL);
3839 if (ret != I40E_SUCCESS) {
3841 "Set switch config failed aq_err: %d",
3842 hw->aq.asq_last_status);
3846 /* If NVM API < 1.7, keep the register setting */
3847 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3854 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3856 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3857 struct i40e_vsi *vsi = pf->main_vsi;
3858 struct rte_eth_rxmode *rxmode;
3860 if (mask & ETH_QINQ_STRIP_MASK) {
3861 PMD_DRV_LOG(ERR, "Strip qinq is not supported.");
3865 rxmode = &dev->data->dev_conf.rxmode;
3866 if (mask & ETH_VLAN_FILTER_MASK) {
3867 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3868 i40e_vsi_config_vlan_filter(vsi, TRUE);
3870 i40e_vsi_config_vlan_filter(vsi, FALSE);
3873 if (mask & ETH_VLAN_STRIP_MASK) {
3874 /* Enable or disable VLAN stripping */
3875 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3876 i40e_vsi_config_vlan_stripping(vsi, TRUE);
3878 i40e_vsi_config_vlan_stripping(vsi, FALSE);
3881 if (mask & ETH_VLAN_EXTEND_MASK) {
3882 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
3883 i40e_vsi_config_double_vlan(vsi, TRUE);
3884 /* Set global registers with default ethertype. */
3885 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3886 RTE_ETHER_TYPE_VLAN);
3887 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3888 RTE_ETHER_TYPE_VLAN);
3891 i40e_vsi_config_double_vlan(vsi, FALSE);
3898 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3899 __rte_unused uint16_t queue,
3900 __rte_unused int on)
3902 PMD_INIT_FUNC_TRACE();
3906 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3908 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3909 struct i40e_vsi *vsi = pf->main_vsi;
3910 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3911 struct i40e_vsi_vlan_pvid_info info;
3913 memset(&info, 0, sizeof(info));
3916 info.config.pvid = pvid;
3918 info.config.reject.tagged =
3919 data->dev_conf.txmode.hw_vlan_reject_tagged;
3920 info.config.reject.untagged =
3921 data->dev_conf.txmode.hw_vlan_reject_untagged;
3924 return i40e_vsi_vlan_pvid_set(vsi, &info);
3928 i40e_dev_led_on(struct rte_eth_dev *dev)
3930 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3931 uint32_t mode = i40e_led_get(hw);
3934 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3940 i40e_dev_led_off(struct rte_eth_dev *dev)
3942 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3943 uint32_t mode = i40e_led_get(hw);
3946 i40e_led_set(hw, 0, false);
3952 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3954 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3955 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3957 fc_conf->pause_time = pf->fc_conf.pause_time;
3959 /* read out from register, in case they are modified by other port */
3960 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3961 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3962 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3963 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3965 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3966 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3968 /* Return current mode according to actual setting*/
3969 switch (hw->fc.current_mode) {
3971 fc_conf->mode = RTE_FC_FULL;
3973 case I40E_FC_TX_PAUSE:
3974 fc_conf->mode = RTE_FC_TX_PAUSE;
3976 case I40E_FC_RX_PAUSE:
3977 fc_conf->mode = RTE_FC_RX_PAUSE;
3981 fc_conf->mode = RTE_FC_NONE;
3988 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3990 uint32_t mflcn_reg, fctrl_reg, reg;
3991 uint32_t max_high_water;
3992 uint8_t i, aq_failure;
3996 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3997 [RTE_FC_NONE] = I40E_FC_NONE,
3998 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3999 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
4000 [RTE_FC_FULL] = I40E_FC_FULL
4003 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
4005 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
4006 if ((fc_conf->high_water > max_high_water) ||
4007 (fc_conf->high_water < fc_conf->low_water)) {
4009 "Invalid high/low water setup value in KB, High_water must be <= %d.",
4014 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4015 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4016 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
4018 pf->fc_conf.pause_time = fc_conf->pause_time;
4019 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
4020 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
4022 PMD_INIT_FUNC_TRACE();
4024 /* All the link flow control related enable/disable register
4025 * configuration is handle by the F/W
4027 err = i40e_set_fc(hw, &aq_failure, true);
4031 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
4032 /* Configure flow control refresh threshold,
4033 * the value for stat_tx_pause_refresh_timer[8]
4034 * is used for global pause operation.
4038 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
4039 pf->fc_conf.pause_time);
4041 /* configure the timer value included in transmitted pause
4043 * the value for stat_tx_pause_quanta[8] is used for global
4046 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
4047 pf->fc_conf.pause_time);
4049 fctrl_reg = I40E_READ_REG(hw,
4050 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
4052 if (fc_conf->mac_ctrl_frame_fwd != 0)
4053 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
4055 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
4057 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
4060 /* Configure pause time (2 TCs per register) */
4061 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
4062 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
4063 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
4065 /* Configure flow control refresh threshold value */
4066 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
4067 pf->fc_conf.pause_time / 2);
4069 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4071 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
4072 *depending on configuration
4074 if (fc_conf->mac_ctrl_frame_fwd != 0) {
4075 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
4076 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
4078 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
4079 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
4082 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
4085 if (!pf->support_multi_driver) {
4086 /* config water marker both based on the packets and bytes */
4087 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
4088 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4089 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4090 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
4091 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4092 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4093 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
4094 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4096 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
4097 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4101 "Water marker configuration is not supported.");
4104 I40E_WRITE_FLUSH(hw);
4110 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
4111 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
4113 PMD_INIT_FUNC_TRACE();
4118 /* Add a MAC address, and update filters */
4120 i40e_macaddr_add(struct rte_eth_dev *dev,
4121 struct rte_ether_addr *mac_addr,
4122 __rte_unused uint32_t index,
4125 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4126 struct i40e_mac_filter_info mac_filter;
4127 struct i40e_vsi *vsi;
4128 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
4131 /* If VMDQ not enabled or configured, return */
4132 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
4133 !pf->nb_cfg_vmdq_vsi)) {
4134 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
4135 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
4140 if (pool > pf->nb_cfg_vmdq_vsi) {
4141 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
4142 pool, pf->nb_cfg_vmdq_vsi);
4146 rte_memcpy(&mac_filter.mac_addr, mac_addr, RTE_ETHER_ADDR_LEN);
4147 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4148 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4150 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
4155 vsi = pf->vmdq[pool - 1].vsi;
4157 ret = i40e_vsi_add_mac(vsi, &mac_filter);
4158 if (ret != I40E_SUCCESS) {
4159 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4165 /* Remove a MAC address, and update filters */
4167 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4169 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4170 struct i40e_vsi *vsi;
4171 struct rte_eth_dev_data *data = dev->data;
4172 struct rte_ether_addr *macaddr;
4177 macaddr = &(data->mac_addrs[index]);
4179 pool_sel = dev->data->mac_pool_sel[index];
4181 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4182 if (pool_sel & (1ULL << i)) {
4186 /* No VMDQ pool enabled or configured */
4187 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4188 (i > pf->nb_cfg_vmdq_vsi)) {
4190 "No VMDQ pool enabled/configured");
4193 vsi = pf->vmdq[i - 1].vsi;
4195 ret = i40e_vsi_delete_mac(vsi, macaddr);
4198 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4205 /* Set perfect match or hash match of MAC and VLAN for a VF */
4207 i40e_vf_mac_filter_set(struct i40e_pf *pf,
4208 struct rte_eth_mac_filter *filter,
4212 struct i40e_mac_filter_info mac_filter;
4213 struct rte_ether_addr old_mac;
4214 struct rte_ether_addr *new_mac;
4215 struct i40e_pf_vf *vf = NULL;
4220 PMD_DRV_LOG(ERR, "Invalid PF argument.");
4223 hw = I40E_PF_TO_HW(pf);
4225 if (filter == NULL) {
4226 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
4230 new_mac = &filter->mac_addr;
4232 if (rte_is_zero_ether_addr(new_mac)) {
4233 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
4237 vf_id = filter->dst_id;
4239 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
4240 PMD_DRV_LOG(ERR, "Invalid argument.");
4243 vf = &pf->vfs[vf_id];
4245 if (add && rte_is_same_ether_addr(new_mac, &pf->dev_addr)) {
4246 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
4251 rte_memcpy(&old_mac, hw->mac.addr, RTE_ETHER_ADDR_LEN);
4252 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
4253 RTE_ETHER_ADDR_LEN);
4254 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
4255 RTE_ETHER_ADDR_LEN);
4257 mac_filter.filter_type = filter->filter_type;
4258 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
4259 if (ret != I40E_SUCCESS) {
4260 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
4263 rte_ether_addr_copy(new_mac, &pf->dev_addr);
4265 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
4266 RTE_ETHER_ADDR_LEN);
4267 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
4268 if (ret != I40E_SUCCESS) {
4269 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
4273 /* Clear device address as it has been removed */
4274 if (rte_is_same_ether_addr(&pf->dev_addr, new_mac))
4275 memset(&pf->dev_addr, 0, sizeof(struct rte_ether_addr));
4281 /* MAC filter handle */
4283 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4286 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4287 struct rte_eth_mac_filter *filter;
4288 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4289 int ret = I40E_NOT_SUPPORTED;
4291 filter = (struct rte_eth_mac_filter *)(arg);
4293 switch (filter_op) {
4294 case RTE_ETH_FILTER_NOP:
4297 case RTE_ETH_FILTER_ADD:
4298 i40e_pf_disable_irq0(hw);
4300 ret = i40e_vf_mac_filter_set(pf, filter, 1);
4301 i40e_pf_enable_irq0(hw);
4303 case RTE_ETH_FILTER_DELETE:
4304 i40e_pf_disable_irq0(hw);
4306 ret = i40e_vf_mac_filter_set(pf, filter, 0);
4307 i40e_pf_enable_irq0(hw);
4310 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4311 ret = I40E_ERR_PARAM;
4319 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4321 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4322 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4329 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4330 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id,
4331 vsi->type != I40E_VSI_SRIOV,
4334 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4338 uint32_t *lut_dw = (uint32_t *)lut;
4339 uint16_t i, lut_size_dw = lut_size / 4;
4341 if (vsi->type == I40E_VSI_SRIOV) {
4342 for (i = 0; i <= lut_size_dw; i++) {
4343 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4344 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4347 for (i = 0; i < lut_size_dw; i++)
4348 lut_dw[i] = I40E_READ_REG(hw,
4357 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4366 pf = I40E_VSI_TO_PF(vsi);
4367 hw = I40E_VSI_TO_HW(vsi);
4369 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4370 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id,
4371 vsi->type != I40E_VSI_SRIOV,
4374 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4378 uint32_t *lut_dw = (uint32_t *)lut;
4379 uint16_t i, lut_size_dw = lut_size / 4;
4381 if (vsi->type == I40E_VSI_SRIOV) {
4382 for (i = 0; i < lut_size_dw; i++)
4385 I40E_VFQF_HLUT1(i, vsi->user_param),
4388 for (i = 0; i < lut_size_dw; i++)
4389 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4392 I40E_WRITE_FLUSH(hw);
4399 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4400 struct rte_eth_rss_reta_entry64 *reta_conf,
4403 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4404 uint16_t i, lut_size = pf->hash_lut_size;
4405 uint16_t idx, shift;
4409 if (reta_size != lut_size ||
4410 reta_size > ETH_RSS_RETA_SIZE_512) {
4412 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4413 reta_size, lut_size);
4417 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4419 PMD_DRV_LOG(ERR, "No memory can be allocated");
4422 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4425 for (i = 0; i < reta_size; i++) {
4426 idx = i / RTE_RETA_GROUP_SIZE;
4427 shift = i % RTE_RETA_GROUP_SIZE;
4428 if (reta_conf[idx].mask & (1ULL << shift))
4429 lut[i] = reta_conf[idx].reta[shift];
4431 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4433 pf->adapter->rss_reta_updated = 1;
4442 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4443 struct rte_eth_rss_reta_entry64 *reta_conf,
4446 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4447 uint16_t i, lut_size = pf->hash_lut_size;
4448 uint16_t idx, shift;
4452 if (reta_size != lut_size ||
4453 reta_size > ETH_RSS_RETA_SIZE_512) {
4455 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4456 reta_size, lut_size);
4460 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4462 PMD_DRV_LOG(ERR, "No memory can be allocated");
4466 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4469 for (i = 0; i < reta_size; i++) {
4470 idx = i / RTE_RETA_GROUP_SIZE;
4471 shift = i % RTE_RETA_GROUP_SIZE;
4472 if (reta_conf[idx].mask & (1ULL << shift))
4473 reta_conf[idx].reta[shift] = lut[i];
4483 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4484 * @hw: pointer to the HW structure
4485 * @mem: pointer to mem struct to fill out
4486 * @size: size of memory requested
4487 * @alignment: what to align the allocation to
4489 enum i40e_status_code
4490 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4491 struct i40e_dma_mem *mem,
4495 const struct rte_memzone *mz = NULL;
4496 char z_name[RTE_MEMZONE_NAMESIZE];
4499 return I40E_ERR_PARAM;
4501 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4502 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4503 RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4505 return I40E_ERR_NO_MEMORY;
4510 mem->zone = (const void *)mz;
4512 "memzone %s allocated with physical address: %"PRIu64,
4515 return I40E_SUCCESS;
4519 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4520 * @hw: pointer to the HW structure
4521 * @mem: ptr to mem struct to free
4523 enum i40e_status_code
4524 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4525 struct i40e_dma_mem *mem)
4528 return I40E_ERR_PARAM;
4531 "memzone %s to be freed with physical address: %"PRIu64,
4532 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4533 rte_memzone_free((const struct rte_memzone *)mem->zone);
4538 return I40E_SUCCESS;
4542 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4543 * @hw: pointer to the HW structure
4544 * @mem: pointer to mem struct to fill out
4545 * @size: size of memory requested
4547 enum i40e_status_code
4548 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4549 struct i40e_virt_mem *mem,
4553 return I40E_ERR_PARAM;
4556 mem->va = rte_zmalloc("i40e", size, 0);
4559 return I40E_SUCCESS;
4561 return I40E_ERR_NO_MEMORY;
4565 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4566 * @hw: pointer to the HW structure
4567 * @mem: pointer to mem struct to free
4569 enum i40e_status_code
4570 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4571 struct i40e_virt_mem *mem)
4574 return I40E_ERR_PARAM;
4579 return I40E_SUCCESS;
4583 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4585 rte_spinlock_init(&sp->spinlock);
4589 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4591 rte_spinlock_lock(&sp->spinlock);
4595 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4597 rte_spinlock_unlock(&sp->spinlock);
4601 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4607 * Get the hardware capabilities, which will be parsed
4608 * and saved into struct i40e_hw.
4611 i40e_get_cap(struct i40e_hw *hw)
4613 struct i40e_aqc_list_capabilities_element_resp *buf;
4614 uint16_t len, size = 0;
4617 /* Calculate a huge enough buff for saving response data temporarily */
4618 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4619 I40E_MAX_CAP_ELE_NUM;
4620 buf = rte_zmalloc("i40e", len, 0);
4622 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4623 return I40E_ERR_NO_MEMORY;
4626 /* Get, parse the capabilities and save it to hw */
4627 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4628 i40e_aqc_opc_list_func_capabilities, NULL);
4629 if (ret != I40E_SUCCESS)
4630 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4632 /* Free the temporary buffer after being used */
4638 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4
4640 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4648 pf = (struct i40e_pf *)opaque;
4652 num = strtoul(value, &end, 0);
4653 if (errno != 0 || end == value || *end != 0) {
4654 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4655 "kept the value = %hu", value, pf->vf_nb_qp_max);
4659 if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4660 pf->vf_nb_qp_max = (uint16_t)num;
4662 /* here return 0 to make next valid same argument work */
4663 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4664 "power of 2 and equal or less than 16 !, Now it is "
4665 "kept the value = %hu", num, pf->vf_nb_qp_max);
4670 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4672 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4673 struct rte_kvargs *kvlist;
4676 /* set default queue number per VF as 4 */
4677 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4679 if (dev->device->devargs == NULL)
4682 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4686 kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4687 if (!kvargs_count) {
4688 rte_kvargs_free(kvlist);
4692 if (kvargs_count > 1)
4693 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4694 "the first invalid or last valid one is used !",
4695 ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4697 rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4698 i40e_pf_parse_vf_queue_number_handler, pf);
4700 rte_kvargs_free(kvlist);
4706 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4708 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4709 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4710 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4711 uint16_t qp_count = 0, vsi_count = 0;
4713 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4714 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4718 i40e_pf_config_vf_rxq_number(dev);
4720 /* Add the parameter init for LFC */
4721 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4722 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4723 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4725 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4726 pf->max_num_vsi = hw->func_caps.num_vsis;
4727 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4728 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4730 /* FDir queue/VSI allocation */
4731 pf->fdir_qp_offset = 0;
4732 if (hw->func_caps.fd) {
4733 pf->flags |= I40E_FLAG_FDIR;
4734 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4736 pf->fdir_nb_qps = 0;
4738 qp_count += pf->fdir_nb_qps;
4741 /* LAN queue/VSI allocation */
4742 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4743 if (!hw->func_caps.rss) {
4746 pf->flags |= I40E_FLAG_RSS;
4747 if (hw->mac.type == I40E_MAC_X722)
4748 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4749 pf->lan_nb_qps = pf->lan_nb_qp_max;
4751 qp_count += pf->lan_nb_qps;
4754 /* VF queue/VSI allocation */
4755 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4756 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4757 pf->flags |= I40E_FLAG_SRIOV;
4758 pf->vf_nb_qps = pf->vf_nb_qp_max;
4759 pf->vf_num = pci_dev->max_vfs;
4761 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4762 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4767 qp_count += pf->vf_nb_qps * pf->vf_num;
4768 vsi_count += pf->vf_num;
4770 /* VMDq queue/VSI allocation */
4771 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4772 pf->vmdq_nb_qps = 0;
4773 pf->max_nb_vmdq_vsi = 0;
4774 if (hw->func_caps.vmdq) {
4775 if (qp_count < hw->func_caps.num_tx_qp &&
4776 vsi_count < hw->func_caps.num_vsis) {
4777 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4778 qp_count) / pf->vmdq_nb_qp_max;
4780 /* Limit the maximum number of VMDq vsi to the maximum
4781 * ethdev can support
4783 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4784 hw->func_caps.num_vsis - vsi_count);
4785 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4787 if (pf->max_nb_vmdq_vsi) {
4788 pf->flags |= I40E_FLAG_VMDQ;
4789 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4791 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4792 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4793 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4796 "No enough queues left for VMDq");
4799 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4802 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4803 vsi_count += pf->max_nb_vmdq_vsi;
4805 if (hw->func_caps.dcb)
4806 pf->flags |= I40E_FLAG_DCB;
4808 if (qp_count > hw->func_caps.num_tx_qp) {
4810 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4811 qp_count, hw->func_caps.num_tx_qp);
4814 if (vsi_count > hw->func_caps.num_vsis) {
4816 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4817 vsi_count, hw->func_caps.num_vsis);
4825 i40e_pf_get_switch_config(struct i40e_pf *pf)
4827 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4828 struct i40e_aqc_get_switch_config_resp *switch_config;
4829 struct i40e_aqc_switch_config_element_resp *element;
4830 uint16_t start_seid = 0, num_reported;
4833 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4834 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4835 if (!switch_config) {
4836 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4840 /* Get the switch configurations */
4841 ret = i40e_aq_get_switch_config(hw, switch_config,
4842 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4843 if (ret != I40E_SUCCESS) {
4844 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4847 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4848 if (num_reported != 1) { /* The number should be 1 */
4849 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4853 /* Parse the switch configuration elements */
4854 element = &(switch_config->element[0]);
4855 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4856 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4857 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4859 PMD_DRV_LOG(INFO, "Unknown element type");
4862 rte_free(switch_config);
4868 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4871 struct pool_entry *entry;
4873 if (pool == NULL || num == 0)
4876 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4877 if (entry == NULL) {
4878 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4882 /* queue heap initialize */
4883 pool->num_free = num;
4884 pool->num_alloc = 0;
4886 LIST_INIT(&pool->alloc_list);
4887 LIST_INIT(&pool->free_list);
4889 /* Initialize element */
4893 LIST_INSERT_HEAD(&pool->free_list, entry, next);
4898 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4900 struct pool_entry *entry, *next_entry;
4905 for (entry = LIST_FIRST(&pool->alloc_list);
4906 entry && (next_entry = LIST_NEXT(entry, next), 1);
4907 entry = next_entry) {
4908 LIST_REMOVE(entry, next);
4912 for (entry = LIST_FIRST(&pool->free_list);
4913 entry && (next_entry = LIST_NEXT(entry, next), 1);
4914 entry = next_entry) {
4915 LIST_REMOVE(entry, next);
4920 pool->num_alloc = 0;
4922 LIST_INIT(&pool->alloc_list);
4923 LIST_INIT(&pool->free_list);
4927 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4930 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4931 uint32_t pool_offset;
4935 PMD_DRV_LOG(ERR, "Invalid parameter");
4939 pool_offset = base - pool->base;
4940 /* Lookup in alloc list */
4941 LIST_FOREACH(entry, &pool->alloc_list, next) {
4942 if (entry->base == pool_offset) {
4943 valid_entry = entry;
4944 LIST_REMOVE(entry, next);
4949 /* Not find, return */
4950 if (valid_entry == NULL) {
4951 PMD_DRV_LOG(ERR, "Failed to find entry");
4956 * Found it, move it to free list and try to merge.
4957 * In order to make merge easier, always sort it by qbase.
4958 * Find adjacent prev and last entries.
4961 LIST_FOREACH(entry, &pool->free_list, next) {
4962 if (entry->base > valid_entry->base) {
4970 /* Try to merge with next one*/
4972 /* Merge with next one */
4973 if (valid_entry->base + valid_entry->len == next->base) {
4974 next->base = valid_entry->base;
4975 next->len += valid_entry->len;
4976 rte_free(valid_entry);
4983 /* Merge with previous one */
4984 if (prev->base + prev->len == valid_entry->base) {
4985 prev->len += valid_entry->len;
4986 /* If it merge with next one, remove next node */
4988 LIST_REMOVE(valid_entry, next);
4989 rte_free(valid_entry);
4991 rte_free(valid_entry);
4997 /* Not find any entry to merge, insert */
5000 LIST_INSERT_AFTER(prev, valid_entry, next);
5001 else if (next != NULL)
5002 LIST_INSERT_BEFORE(next, valid_entry, next);
5003 else /* It's empty list, insert to head */
5004 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
5007 pool->num_free += valid_entry->len;
5008 pool->num_alloc -= valid_entry->len;
5014 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
5017 struct pool_entry *entry, *valid_entry;
5019 if (pool == NULL || num == 0) {
5020 PMD_DRV_LOG(ERR, "Invalid parameter");
5024 if (pool->num_free < num) {
5025 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
5026 num, pool->num_free);
5031 /* Lookup in free list and find most fit one */
5032 LIST_FOREACH(entry, &pool->free_list, next) {
5033 if (entry->len >= num) {
5035 if (entry->len == num) {
5036 valid_entry = entry;
5039 if (valid_entry == NULL || valid_entry->len > entry->len)
5040 valid_entry = entry;
5044 /* Not find one to satisfy the request, return */
5045 if (valid_entry == NULL) {
5046 PMD_DRV_LOG(ERR, "No valid entry found");
5050 * The entry have equal queue number as requested,
5051 * remove it from alloc_list.
5053 if (valid_entry->len == num) {
5054 LIST_REMOVE(valid_entry, next);
5057 * The entry have more numbers than requested,
5058 * create a new entry for alloc_list and minus its
5059 * queue base and number in free_list.
5061 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
5062 if (entry == NULL) {
5064 "Failed to allocate memory for resource pool");
5067 entry->base = valid_entry->base;
5069 valid_entry->base += num;
5070 valid_entry->len -= num;
5071 valid_entry = entry;
5074 /* Insert it into alloc list, not sorted */
5075 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
5077 pool->num_free -= valid_entry->len;
5078 pool->num_alloc += valid_entry->len;
5080 return valid_entry->base + pool->base;
5084 * bitmap_is_subset - Check whether src2 is subset of src1
5087 bitmap_is_subset(uint8_t src1, uint8_t src2)
5089 return !((src1 ^ src2) & src2);
5092 static enum i40e_status_code
5093 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5095 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5097 /* If DCB is not supported, only default TC is supported */
5098 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
5099 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
5100 return I40E_NOT_SUPPORTED;
5103 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
5105 "Enabled TC map 0x%x not applicable to HW support 0x%x",
5106 hw->func_caps.enabled_tcmap, enabled_tcmap);
5107 return I40E_NOT_SUPPORTED;
5109 return I40E_SUCCESS;
5113 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
5114 struct i40e_vsi_vlan_pvid_info *info)
5117 struct i40e_vsi_context ctxt;
5118 uint8_t vlan_flags = 0;
5121 if (vsi == NULL || info == NULL) {
5122 PMD_DRV_LOG(ERR, "invalid parameters");
5123 return I40E_ERR_PARAM;
5127 vsi->info.pvid = info->config.pvid;
5129 * If insert pvid is enabled, only tagged pkts are
5130 * allowed to be sent out.
5132 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
5133 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5136 if (info->config.reject.tagged == 0)
5137 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5139 if (info->config.reject.untagged == 0)
5140 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
5142 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
5143 I40E_AQ_VSI_PVLAN_MODE_MASK);
5144 vsi->info.port_vlan_flags |= vlan_flags;
5145 vsi->info.valid_sections =
5146 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5147 memset(&ctxt, 0, sizeof(ctxt));
5148 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5149 ctxt.seid = vsi->seid;
5151 hw = I40E_VSI_TO_HW(vsi);
5152 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5153 if (ret != I40E_SUCCESS)
5154 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5160 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5162 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5164 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
5166 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5167 if (ret != I40E_SUCCESS)
5171 PMD_DRV_LOG(ERR, "seid not valid");
5175 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
5176 tc_bw_data.tc_valid_bits = enabled_tcmap;
5177 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5178 tc_bw_data.tc_bw_credits[i] =
5179 (enabled_tcmap & (1 << i)) ? 1 : 0;
5181 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5182 if (ret != I40E_SUCCESS) {
5183 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5187 rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5188 sizeof(vsi->info.qs_handle));
5189 return I40E_SUCCESS;
5192 static enum i40e_status_code
5193 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5194 struct i40e_aqc_vsi_properties_data *info,
5195 uint8_t enabled_tcmap)
5197 enum i40e_status_code ret;
5198 int i, total_tc = 0;
5199 uint16_t qpnum_per_tc, bsf, qp_idx;
5201 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5202 if (ret != I40E_SUCCESS)
5205 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5206 if (enabled_tcmap & (1 << i))
5210 vsi->enabled_tc = enabled_tcmap;
5212 /* Number of queues per enabled TC */
5213 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5214 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5215 bsf = rte_bsf32(qpnum_per_tc);
5217 /* Adjust the queue number to actual queues that can be applied */
5218 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5219 vsi->nb_qps = qpnum_per_tc * total_tc;
5222 * Configure TC and queue mapping parameters, for enabled TC,
5223 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5224 * default queue will serve it.
5227 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5228 if (vsi->enabled_tc & (1 << i)) {
5229 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5230 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5231 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5232 qp_idx += qpnum_per_tc;
5234 info->tc_mapping[i] = 0;
5237 /* Associate queue number with VSI */
5238 if (vsi->type == I40E_VSI_SRIOV) {
5239 info->mapping_flags |=
5240 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5241 for (i = 0; i < vsi->nb_qps; i++)
5242 info->queue_mapping[i] =
5243 rte_cpu_to_le_16(vsi->base_queue + i);
5245 info->mapping_flags |=
5246 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5247 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5249 info->valid_sections |=
5250 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5252 return I40E_SUCCESS;
5256 i40e_veb_release(struct i40e_veb *veb)
5258 struct i40e_vsi *vsi;
5264 if (!TAILQ_EMPTY(&veb->head)) {
5265 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5268 /* associate_vsi field is NULL for floating VEB */
5269 if (veb->associate_vsi != NULL) {
5270 vsi = veb->associate_vsi;
5271 hw = I40E_VSI_TO_HW(vsi);
5273 vsi->uplink_seid = veb->uplink_seid;
5276 veb->associate_pf->main_vsi->floating_veb = NULL;
5277 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5280 i40e_aq_delete_element(hw, veb->seid, NULL);
5282 return I40E_SUCCESS;
5286 static struct i40e_veb *
5287 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5289 struct i40e_veb *veb;
5295 "veb setup failed, associated PF shouldn't null");
5298 hw = I40E_PF_TO_HW(pf);
5300 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5302 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5306 veb->associate_vsi = vsi;
5307 veb->associate_pf = pf;
5308 TAILQ_INIT(&veb->head);
5309 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5311 /* create floating veb if vsi is NULL */
5313 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5314 I40E_DEFAULT_TCMAP, false,
5315 &veb->seid, false, NULL);
5317 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5318 true, &veb->seid, false, NULL);
5321 if (ret != I40E_SUCCESS) {
5322 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5323 hw->aq.asq_last_status);
5326 veb->enabled_tc = I40E_DEFAULT_TCMAP;
5328 /* get statistics index */
5329 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5330 &veb->stats_idx, NULL, NULL, NULL);
5331 if (ret != I40E_SUCCESS) {
5332 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5333 hw->aq.asq_last_status);
5336 /* Get VEB bandwidth, to be implemented */
5337 /* Now associated vsi binding to the VEB, set uplink to this VEB */
5339 vsi->uplink_seid = veb->seid;
5348 i40e_vsi_release(struct i40e_vsi *vsi)
5352 struct i40e_vsi_list *vsi_list;
5355 struct i40e_mac_filter *f;
5356 uint16_t user_param;
5359 return I40E_SUCCESS;
5364 user_param = vsi->user_param;
5366 pf = I40E_VSI_TO_PF(vsi);
5367 hw = I40E_VSI_TO_HW(vsi);
5369 /* VSI has child to attach, release child first */
5371 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5372 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5375 i40e_veb_release(vsi->veb);
5378 if (vsi->floating_veb) {
5379 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5380 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5385 /* Remove all macvlan filters of the VSI */
5386 i40e_vsi_remove_all_macvlan_filter(vsi);
5387 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5390 if (vsi->type != I40E_VSI_MAIN &&
5391 ((vsi->type != I40E_VSI_SRIOV) ||
5392 !pf->floating_veb_list[user_param])) {
5393 /* Remove vsi from parent's sibling list */
5394 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5395 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5396 return I40E_ERR_PARAM;
5398 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5399 &vsi->sib_vsi_list, list);
5401 /* Remove all switch element of the VSI */
5402 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5403 if (ret != I40E_SUCCESS)
5404 PMD_DRV_LOG(ERR, "Failed to delete element");
5407 if ((vsi->type == I40E_VSI_SRIOV) &&
5408 pf->floating_veb_list[user_param]) {
5409 /* Remove vsi from parent's sibling list */
5410 if (vsi->parent_vsi == NULL ||
5411 vsi->parent_vsi->floating_veb == NULL) {
5412 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5413 return I40E_ERR_PARAM;
5415 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5416 &vsi->sib_vsi_list, list);
5418 /* Remove all switch element of the VSI */
5419 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5420 if (ret != I40E_SUCCESS)
5421 PMD_DRV_LOG(ERR, "Failed to delete element");
5424 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5426 if (vsi->type != I40E_VSI_SRIOV)
5427 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5430 return I40E_SUCCESS;
5434 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5436 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5437 struct i40e_aqc_remove_macvlan_element_data def_filter;
5438 struct i40e_mac_filter_info filter;
5441 if (vsi->type != I40E_VSI_MAIN)
5442 return I40E_ERR_CONFIG;
5443 memset(&def_filter, 0, sizeof(def_filter));
5444 rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5446 def_filter.vlan_tag = 0;
5447 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5448 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5449 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5450 if (ret != I40E_SUCCESS) {
5451 struct i40e_mac_filter *f;
5452 struct rte_ether_addr *mac;
5455 "Cannot remove the default macvlan filter");
5456 /* It needs to add the permanent mac into mac list */
5457 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5459 PMD_DRV_LOG(ERR, "failed to allocate memory");
5460 return I40E_ERR_NO_MEMORY;
5462 mac = &f->mac_info.mac_addr;
5463 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5465 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5466 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5471 rte_memcpy(&filter.mac_addr,
5472 (struct rte_ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5473 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5474 return i40e_vsi_add_mac(vsi, &filter);
5478 * i40e_vsi_get_bw_config - Query VSI BW Information
5479 * @vsi: the VSI to be queried
5481 * Returns 0 on success, negative value on failure
5483 static enum i40e_status_code
5484 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5486 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5487 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5488 struct i40e_hw *hw = &vsi->adapter->hw;
5493 memset(&bw_config, 0, sizeof(bw_config));
5494 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5495 if (ret != I40E_SUCCESS) {
5496 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5497 hw->aq.asq_last_status);
5501 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5502 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5503 &ets_sla_config, NULL);
5504 if (ret != I40E_SUCCESS) {
5506 "VSI failed to get TC bandwdith configuration %u",
5507 hw->aq.asq_last_status);
5511 /* store and print out BW info */
5512 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5513 vsi->bw_info.bw_max = bw_config.max_bw;
5514 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5515 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5516 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5517 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5519 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5520 vsi->bw_info.bw_ets_share_credits[i] =
5521 ets_sla_config.share_credits[i];
5522 vsi->bw_info.bw_ets_credits[i] =
5523 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5524 /* 4 bits per TC, 4th bit is reserved */
5525 vsi->bw_info.bw_ets_max[i] =
5526 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5527 RTE_LEN2MASK(3, uint8_t));
5528 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5529 vsi->bw_info.bw_ets_share_credits[i]);
5530 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5531 vsi->bw_info.bw_ets_credits[i]);
5532 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5533 vsi->bw_info.bw_ets_max[i]);
5536 return I40E_SUCCESS;
5539 /* i40e_enable_pf_lb
5540 * @pf: pointer to the pf structure
5542 * allow loopback on pf
5545 i40e_enable_pf_lb(struct i40e_pf *pf)
5547 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5548 struct i40e_vsi_context ctxt;
5551 /* Use the FW API if FW >= v5.0 */
5552 if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
5553 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5557 memset(&ctxt, 0, sizeof(ctxt));
5558 ctxt.seid = pf->main_vsi_seid;
5559 ctxt.pf_num = hw->pf_id;
5560 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5562 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5563 ret, hw->aq.asq_last_status);
5566 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5567 ctxt.info.valid_sections =
5568 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5569 ctxt.info.switch_id |=
5570 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5572 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5574 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5575 hw->aq.asq_last_status);
5580 i40e_vsi_setup(struct i40e_pf *pf,
5581 enum i40e_vsi_type type,
5582 struct i40e_vsi *uplink_vsi,
5583 uint16_t user_param)
5585 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5586 struct i40e_vsi *vsi;
5587 struct i40e_mac_filter_info filter;
5589 struct i40e_vsi_context ctxt;
5590 struct rte_ether_addr broadcast =
5591 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5593 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5594 uplink_vsi == NULL) {
5596 "VSI setup failed, VSI link shouldn't be NULL");
5600 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5602 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5607 * 1.type is not MAIN and uplink vsi is not NULL
5608 * If uplink vsi didn't setup VEB, create one first under veb field
5609 * 2.type is SRIOV and the uplink is NULL
5610 * If floating VEB is NULL, create one veb under floating veb field
5613 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5614 uplink_vsi->veb == NULL) {
5615 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5617 if (uplink_vsi->veb == NULL) {
5618 PMD_DRV_LOG(ERR, "VEB setup failed");
5621 /* set ALLOWLOOPBACk on pf, when veb is created */
5622 i40e_enable_pf_lb(pf);
5625 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5626 pf->main_vsi->floating_veb == NULL) {
5627 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5629 if (pf->main_vsi->floating_veb == NULL) {
5630 PMD_DRV_LOG(ERR, "VEB setup failed");
5635 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5637 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5640 TAILQ_INIT(&vsi->mac_list);
5642 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5643 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5644 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5645 vsi->user_param = user_param;
5646 vsi->vlan_anti_spoof_on = 0;
5647 vsi->vlan_filter_on = 0;
5648 /* Allocate queues */
5649 switch (vsi->type) {
5650 case I40E_VSI_MAIN :
5651 vsi->nb_qps = pf->lan_nb_qps;
5653 case I40E_VSI_SRIOV :
5654 vsi->nb_qps = pf->vf_nb_qps;
5656 case I40E_VSI_VMDQ2:
5657 vsi->nb_qps = pf->vmdq_nb_qps;
5660 vsi->nb_qps = pf->fdir_nb_qps;
5666 * The filter status descriptor is reported in rx queue 0,
5667 * while the tx queue for fdir filter programming has no
5668 * such constraints, can be non-zero queues.
5669 * To simplify it, choose FDIR vsi use queue 0 pair.
5670 * To make sure it will use queue 0 pair, queue allocation
5671 * need be done before this function is called
5673 if (type != I40E_VSI_FDIR) {
5674 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5676 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5680 vsi->base_queue = ret;
5682 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5684 /* VF has MSIX interrupt in VF range, don't allocate here */
5685 if (type == I40E_VSI_MAIN) {
5686 if (pf->support_multi_driver) {
5687 /* If support multi-driver, need to use INT0 instead of
5688 * allocating from msix pool. The Msix pool is init from
5689 * INT1, so it's OK just set msix_intr to 0 and nb_msix
5690 * to 1 without calling i40e_res_pool_alloc.
5695 ret = i40e_res_pool_alloc(&pf->msix_pool,
5696 RTE_MIN(vsi->nb_qps,
5697 RTE_MAX_RXTX_INTR_VEC_ID));
5700 "VSI MAIN %d get heap failed %d",
5702 goto fail_queue_alloc;
5704 vsi->msix_intr = ret;
5705 vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5706 RTE_MAX_RXTX_INTR_VEC_ID);
5708 } else if (type != I40E_VSI_SRIOV) {
5709 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5711 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5712 goto fail_queue_alloc;
5714 vsi->msix_intr = ret;
5722 if (type == I40E_VSI_MAIN) {
5723 /* For main VSI, no need to add since it's default one */
5724 vsi->uplink_seid = pf->mac_seid;
5725 vsi->seid = pf->main_vsi_seid;
5726 /* Bind queues with specific MSIX interrupt */
5728 * Needs 2 interrupt at least, one for misc cause which will
5729 * enabled from OS side, Another for queues binding the
5730 * interrupt from device side only.
5733 /* Get default VSI parameters from hardware */
5734 memset(&ctxt, 0, sizeof(ctxt));
5735 ctxt.seid = vsi->seid;
5736 ctxt.pf_num = hw->pf_id;
5737 ctxt.uplink_seid = vsi->uplink_seid;
5739 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5740 if (ret != I40E_SUCCESS) {
5741 PMD_DRV_LOG(ERR, "Failed to get VSI params");
5742 goto fail_msix_alloc;
5744 rte_memcpy(&vsi->info, &ctxt.info,
5745 sizeof(struct i40e_aqc_vsi_properties_data));
5746 vsi->vsi_id = ctxt.vsi_number;
5747 vsi->info.valid_sections = 0;
5749 /* Configure tc, enabled TC0 only */
5750 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5752 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5753 goto fail_msix_alloc;
5756 /* TC, queue mapping */
5757 memset(&ctxt, 0, sizeof(ctxt));
5758 vsi->info.valid_sections |=
5759 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5760 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5761 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5762 rte_memcpy(&ctxt.info, &vsi->info,
5763 sizeof(struct i40e_aqc_vsi_properties_data));
5764 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5765 I40E_DEFAULT_TCMAP);
5766 if (ret != I40E_SUCCESS) {
5768 "Failed to configure TC queue mapping");
5769 goto fail_msix_alloc;
5771 ctxt.seid = vsi->seid;
5772 ctxt.pf_num = hw->pf_id;
5773 ctxt.uplink_seid = vsi->uplink_seid;
5776 /* Update VSI parameters */
5777 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5778 if (ret != I40E_SUCCESS) {
5779 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5780 goto fail_msix_alloc;
5783 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5784 sizeof(vsi->info.tc_mapping));
5785 rte_memcpy(&vsi->info.queue_mapping,
5786 &ctxt.info.queue_mapping,
5787 sizeof(vsi->info.queue_mapping));
5788 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5789 vsi->info.valid_sections = 0;
5791 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5795 * Updating default filter settings are necessary to prevent
5796 * reception of tagged packets.
5797 * Some old firmware configurations load a default macvlan
5798 * filter which accepts both tagged and untagged packets.
5799 * The updating is to use a normal filter instead if needed.
5800 * For NVM 4.2.2 or after, the updating is not needed anymore.
5801 * The firmware with correct configurations load the default
5802 * macvlan filter which is expected and cannot be removed.
5804 i40e_update_default_filter_setting(vsi);
5805 i40e_config_qinq(hw, vsi);
5806 } else if (type == I40E_VSI_SRIOV) {
5807 memset(&ctxt, 0, sizeof(ctxt));
5809 * For other VSI, the uplink_seid equals to uplink VSI's
5810 * uplink_seid since they share same VEB
5812 if (uplink_vsi == NULL)
5813 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5815 vsi->uplink_seid = uplink_vsi->uplink_seid;
5816 ctxt.pf_num = hw->pf_id;
5817 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5818 ctxt.uplink_seid = vsi->uplink_seid;
5819 ctxt.connection_type = 0x1;
5820 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5822 /* Use the VEB configuration if FW >= v5.0 */
5823 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
5824 /* Configure switch ID */
5825 ctxt.info.valid_sections |=
5826 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5827 ctxt.info.switch_id =
5828 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5831 /* Configure port/vlan */
5832 ctxt.info.valid_sections |=
5833 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5834 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5835 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5836 hw->func_caps.enabled_tcmap);
5837 if (ret != I40E_SUCCESS) {
5839 "Failed to configure TC queue mapping");
5840 goto fail_msix_alloc;
5843 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5844 ctxt.info.valid_sections |=
5845 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5847 * Since VSI is not created yet, only configure parameter,
5848 * will add vsi below.
5851 i40e_config_qinq(hw, vsi);
5852 } else if (type == I40E_VSI_VMDQ2) {
5853 memset(&ctxt, 0, sizeof(ctxt));
5855 * For other VSI, the uplink_seid equals to uplink VSI's
5856 * uplink_seid since they share same VEB
5858 vsi->uplink_seid = uplink_vsi->uplink_seid;
5859 ctxt.pf_num = hw->pf_id;
5861 ctxt.uplink_seid = vsi->uplink_seid;
5862 ctxt.connection_type = 0x1;
5863 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5865 ctxt.info.valid_sections |=
5866 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5867 /* user_param carries flag to enable loop back */
5869 ctxt.info.switch_id =
5870 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5871 ctxt.info.switch_id |=
5872 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5875 /* Configure port/vlan */
5876 ctxt.info.valid_sections |=
5877 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5878 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5879 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5880 I40E_DEFAULT_TCMAP);
5881 if (ret != I40E_SUCCESS) {
5883 "Failed to configure TC queue mapping");
5884 goto fail_msix_alloc;
5886 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5887 ctxt.info.valid_sections |=
5888 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5889 } else if (type == I40E_VSI_FDIR) {
5890 memset(&ctxt, 0, sizeof(ctxt));
5891 vsi->uplink_seid = uplink_vsi->uplink_seid;
5892 ctxt.pf_num = hw->pf_id;
5894 ctxt.uplink_seid = vsi->uplink_seid;
5895 ctxt.connection_type = 0x1; /* regular data port */
5896 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5897 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5898 I40E_DEFAULT_TCMAP);
5899 if (ret != I40E_SUCCESS) {
5901 "Failed to configure TC queue mapping.");
5902 goto fail_msix_alloc;
5904 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5905 ctxt.info.valid_sections |=
5906 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5908 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5909 goto fail_msix_alloc;
5912 if (vsi->type != I40E_VSI_MAIN) {
5913 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5914 if (ret != I40E_SUCCESS) {
5915 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5916 hw->aq.asq_last_status);
5917 goto fail_msix_alloc;
5919 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5920 vsi->info.valid_sections = 0;
5921 vsi->seid = ctxt.seid;
5922 vsi->vsi_id = ctxt.vsi_number;
5923 vsi->sib_vsi_list.vsi = vsi;
5924 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5925 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5926 &vsi->sib_vsi_list, list);
5928 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5929 &vsi->sib_vsi_list, list);
5933 /* MAC/VLAN configuration */
5934 rte_memcpy(&filter.mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
5935 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5937 ret = i40e_vsi_add_mac(vsi, &filter);
5938 if (ret != I40E_SUCCESS) {
5939 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5940 goto fail_msix_alloc;
5943 /* Get VSI BW information */
5944 i40e_vsi_get_bw_config(vsi);
5947 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5949 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5955 /* Configure vlan filter on or off */
5957 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5960 struct i40e_mac_filter *f;
5962 struct i40e_mac_filter_info *mac_filter;
5963 enum rte_mac_filter_type desired_filter;
5964 int ret = I40E_SUCCESS;
5967 /* Filter to match MAC and VLAN */
5968 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5970 /* Filter to match only MAC */
5971 desired_filter = RTE_MAC_PERFECT_MATCH;
5976 mac_filter = rte_zmalloc("mac_filter_info_data",
5977 num * sizeof(*mac_filter), 0);
5978 if (mac_filter == NULL) {
5979 PMD_DRV_LOG(ERR, "failed to allocate memory");
5980 return I40E_ERR_NO_MEMORY;
5985 /* Remove all existing mac */
5986 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5987 mac_filter[i] = f->mac_info;
5988 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5990 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5991 on ? "enable" : "disable");
5997 /* Override with new filter */
5998 for (i = 0; i < num; i++) {
5999 mac_filter[i].filter_type = desired_filter;
6000 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
6002 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6003 on ? "enable" : "disable");
6009 rte_free(mac_filter);
6013 /* Configure vlan stripping on or off */
6015 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
6017 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6018 struct i40e_vsi_context ctxt;
6020 int ret = I40E_SUCCESS;
6022 /* Check if it has been already on or off */
6023 if (vsi->info.valid_sections &
6024 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
6026 if ((vsi->info.port_vlan_flags &
6027 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
6028 return 0; /* already on */
6030 if ((vsi->info.port_vlan_flags &
6031 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
6032 I40E_AQ_VSI_PVLAN_EMOD_MASK)
6033 return 0; /* already off */
6038 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
6040 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
6041 vsi->info.valid_sections =
6042 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
6043 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
6044 vsi->info.port_vlan_flags |= vlan_flags;
6045 ctxt.seid = vsi->seid;
6046 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
6047 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6049 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
6050 on ? "enable" : "disable");
6056 i40e_dev_init_vlan(struct rte_eth_dev *dev)
6058 struct rte_eth_dev_data *data = dev->data;
6062 /* Apply vlan offload setting */
6063 mask = ETH_VLAN_STRIP_MASK |
6064 ETH_VLAN_FILTER_MASK |
6065 ETH_VLAN_EXTEND_MASK;
6066 ret = i40e_vlan_offload_set(dev, mask);
6068 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
6072 /* Apply pvid setting */
6073 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
6074 data->dev_conf.txmode.hw_vlan_insert_pvid);
6076 PMD_DRV_LOG(INFO, "Failed to update VSI params");
6082 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
6084 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6086 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
6090 i40e_update_flow_control(struct i40e_hw *hw)
6092 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
6093 struct i40e_link_status link_status;
6094 uint32_t rxfc = 0, txfc = 0, reg;
6098 memset(&link_status, 0, sizeof(link_status));
6099 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
6100 if (ret != I40E_SUCCESS) {
6101 PMD_DRV_LOG(ERR, "Failed to get link status information");
6102 goto write_reg; /* Disable flow control */
6105 an_info = hw->phy.link_info.an_info;
6106 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
6107 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
6108 ret = I40E_ERR_NOT_READY;
6109 goto write_reg; /* Disable flow control */
6112 * If link auto negotiation is enabled, flow control needs to
6113 * be configured according to it
6115 switch (an_info & I40E_LINK_PAUSE_RXTX) {
6116 case I40E_LINK_PAUSE_RXTX:
6119 hw->fc.current_mode = I40E_FC_FULL;
6121 case I40E_AQ_LINK_PAUSE_RX:
6123 hw->fc.current_mode = I40E_FC_RX_PAUSE;
6125 case I40E_AQ_LINK_PAUSE_TX:
6127 hw->fc.current_mode = I40E_FC_TX_PAUSE;
6130 hw->fc.current_mode = I40E_FC_NONE;
6135 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
6136 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
6137 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
6138 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
6139 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
6140 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
6147 i40e_pf_setup(struct i40e_pf *pf)
6149 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6150 struct i40e_filter_control_settings settings;
6151 struct i40e_vsi *vsi;
6154 /* Clear all stats counters */
6155 pf->offset_loaded = FALSE;
6156 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
6157 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
6158 memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
6159 memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
6161 ret = i40e_pf_get_switch_config(pf);
6162 if (ret != I40E_SUCCESS) {
6163 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
6167 ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
6169 PMD_INIT_LOG(WARNING,
6170 "failed to allocate switch domain for device %d", ret);
6172 if (pf->flags & I40E_FLAG_FDIR) {
6173 /* make queue allocated first, let FDIR use queue pair 0*/
6174 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
6175 if (ret != I40E_FDIR_QUEUE_ID) {
6177 "queue allocation fails for FDIR: ret =%d",
6179 pf->flags &= ~I40E_FLAG_FDIR;
6182 /* main VSI setup */
6183 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6185 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6186 return I40E_ERR_NOT_READY;
6190 /* Configure filter control */
6191 memset(&settings, 0, sizeof(settings));
6192 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
6193 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6194 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
6195 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6197 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6198 hw->func_caps.rss_table_size);
6199 return I40E_ERR_PARAM;
6201 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6202 hw->func_caps.rss_table_size);
6203 pf->hash_lut_size = hw->func_caps.rss_table_size;
6205 /* Enable ethtype and macvlan filters */
6206 settings.enable_ethtype = TRUE;
6207 settings.enable_macvlan = TRUE;
6208 ret = i40e_set_filter_control(hw, &settings);
6210 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6213 /* Update flow control according to the auto negotiation */
6214 i40e_update_flow_control(hw);
6216 return I40E_SUCCESS;
6220 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6226 * Set or clear TX Queue Disable flags,
6227 * which is required by hardware.
6229 i40e_pre_tx_queue_cfg(hw, q_idx, on);
6230 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6232 /* Wait until the request is finished */
6233 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6234 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6235 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6236 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6237 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6243 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6244 return I40E_SUCCESS; /* already on, skip next steps */
6246 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6247 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6249 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6250 return I40E_SUCCESS; /* already off, skip next steps */
6251 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6253 /* Write the register */
6254 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6255 /* Check the result */
6256 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6257 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6258 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6260 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6261 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6264 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6265 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6269 /* Check if it is timeout */
6270 if (j >= I40E_CHK_Q_ENA_COUNT) {
6271 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6272 (on ? "enable" : "disable"), q_idx);
6273 return I40E_ERR_TIMEOUT;
6276 return I40E_SUCCESS;
6279 /* Swith on or off the tx queues */
6281 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
6283 struct rte_eth_dev_data *dev_data = pf->dev_data;
6284 struct i40e_tx_queue *txq;
6285 struct rte_eth_dev *dev = pf->adapter->eth_dev;
6289 for (i = 0; i < dev_data->nb_tx_queues; i++) {
6290 txq = dev_data->tx_queues[i];
6291 /* Don't operate the queue if not configured or
6292 * if starting only per queue */
6293 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
6296 ret = i40e_dev_tx_queue_start(dev, i);
6298 ret = i40e_dev_tx_queue_stop(dev, i);
6299 if ( ret != I40E_SUCCESS)
6303 return I40E_SUCCESS;
6307 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6312 /* Wait until the request is finished */
6313 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6314 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6315 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6316 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6317 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6322 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6323 return I40E_SUCCESS; /* Already on, skip next steps */
6324 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6326 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6327 return I40E_SUCCESS; /* Already off, skip next steps */
6328 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6331 /* Write the register */
6332 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6333 /* Check the result */
6334 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6335 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6336 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6338 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6339 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6342 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6343 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6348 /* Check if it is timeout */
6349 if (j >= I40E_CHK_Q_ENA_COUNT) {
6350 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6351 (on ? "enable" : "disable"), q_idx);
6352 return I40E_ERR_TIMEOUT;
6355 return I40E_SUCCESS;
6357 /* Switch on or off the rx queues */
6359 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
6361 struct rte_eth_dev_data *dev_data = pf->dev_data;
6362 struct i40e_rx_queue *rxq;
6363 struct rte_eth_dev *dev = pf->adapter->eth_dev;
6367 for (i = 0; i < dev_data->nb_rx_queues; i++) {
6368 rxq = dev_data->rx_queues[i];
6369 /* Don't operate the queue if not configured or
6370 * if starting only per queue */
6371 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
6374 ret = i40e_dev_rx_queue_start(dev, i);
6376 ret = i40e_dev_rx_queue_stop(dev, i);
6377 if (ret != I40E_SUCCESS)
6381 return I40E_SUCCESS;
6384 /* Switch on or off all the rx/tx queues */
6386 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
6391 /* enable rx queues before enabling tx queues */
6392 ret = i40e_dev_switch_rx_queues(pf, on);
6394 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
6397 ret = i40e_dev_switch_tx_queues(pf, on);
6399 /* Stop tx queues before stopping rx queues */
6400 ret = i40e_dev_switch_tx_queues(pf, on);
6402 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
6405 ret = i40e_dev_switch_rx_queues(pf, on);
6411 /* Initialize VSI for TX */
6413 i40e_dev_tx_init(struct i40e_pf *pf)
6415 struct rte_eth_dev_data *data = pf->dev_data;
6417 uint32_t ret = I40E_SUCCESS;
6418 struct i40e_tx_queue *txq;
6420 for (i = 0; i < data->nb_tx_queues; i++) {
6421 txq = data->tx_queues[i];
6422 if (!txq || !txq->q_set)
6424 ret = i40e_tx_queue_init(txq);
6425 if (ret != I40E_SUCCESS)
6428 if (ret == I40E_SUCCESS)
6429 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6435 /* Initialize VSI for RX */
6437 i40e_dev_rx_init(struct i40e_pf *pf)
6439 struct rte_eth_dev_data *data = pf->dev_data;
6440 int ret = I40E_SUCCESS;
6442 struct i40e_rx_queue *rxq;
6444 i40e_pf_config_mq_rx(pf);
6445 for (i = 0; i < data->nb_rx_queues; i++) {
6446 rxq = data->rx_queues[i];
6447 if (!rxq || !rxq->q_set)
6450 ret = i40e_rx_queue_init(rxq);
6451 if (ret != I40E_SUCCESS) {
6453 "Failed to do RX queue initialization");
6457 if (ret == I40E_SUCCESS)
6458 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6465 i40e_dev_rxtx_init(struct i40e_pf *pf)
6469 err = i40e_dev_tx_init(pf);
6471 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6474 err = i40e_dev_rx_init(pf);
6476 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6484 i40e_vmdq_setup(struct rte_eth_dev *dev)
6486 struct rte_eth_conf *conf = &dev->data->dev_conf;
6487 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6488 int i, err, conf_vsis, j, loop;
6489 struct i40e_vsi *vsi;
6490 struct i40e_vmdq_info *vmdq_info;
6491 struct rte_eth_vmdq_rx_conf *vmdq_conf;
6492 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6495 * Disable interrupt to avoid message from VF. Furthermore, it will
6496 * avoid race condition in VSI creation/destroy.
6498 i40e_pf_disable_irq0(hw);
6500 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6501 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6505 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6506 if (conf_vsis > pf->max_nb_vmdq_vsi) {
6507 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6508 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6509 pf->max_nb_vmdq_vsi);
6513 if (pf->vmdq != NULL) {
6514 PMD_INIT_LOG(INFO, "VMDQ already configured");
6518 pf->vmdq = rte_zmalloc("vmdq_info_struct",
6519 sizeof(*vmdq_info) * conf_vsis, 0);
6521 if (pf->vmdq == NULL) {
6522 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6526 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6528 /* Create VMDQ VSI */
6529 for (i = 0; i < conf_vsis; i++) {
6530 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6531 vmdq_conf->enable_loop_back);
6533 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6537 vmdq_info = &pf->vmdq[i];
6539 vmdq_info->vsi = vsi;
6541 pf->nb_cfg_vmdq_vsi = conf_vsis;
6543 /* Configure Vlan */
6544 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6545 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6546 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6547 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6548 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6549 vmdq_conf->pool_map[i].vlan_id, j);
6551 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6552 vmdq_conf->pool_map[i].vlan_id);
6554 PMD_INIT_LOG(ERR, "Failed to add vlan");
6562 i40e_pf_enable_irq0(hw);
6567 for (i = 0; i < conf_vsis; i++)
6568 if (pf->vmdq[i].vsi == NULL)
6571 i40e_vsi_release(pf->vmdq[i].vsi);
6575 i40e_pf_enable_irq0(hw);
6580 i40e_stat_update_32(struct i40e_hw *hw,
6588 new_data = (uint64_t)I40E_READ_REG(hw, reg);
6592 if (new_data >= *offset)
6593 *stat = (uint64_t)(new_data - *offset);
6595 *stat = (uint64_t)((new_data +
6596 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6600 i40e_stat_update_48(struct i40e_hw *hw,
6609 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6610 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6611 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6616 if (new_data >= *offset)
6617 *stat = new_data - *offset;
6619 *stat = (uint64_t)((new_data +
6620 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6622 *stat &= I40E_48_BIT_MASK;
6627 i40e_pf_disable_irq0(struct i40e_hw *hw)
6629 /* Disable all interrupt types */
6630 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6631 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6632 I40E_WRITE_FLUSH(hw);
6637 i40e_pf_enable_irq0(struct i40e_hw *hw)
6639 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6640 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6641 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6642 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6643 I40E_WRITE_FLUSH(hw);
6647 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6649 /* read pending request and disable first */
6650 i40e_pf_disable_irq0(hw);
6651 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6652 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6653 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6656 /* Link no queues with irq0 */
6657 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6658 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6662 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6664 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6665 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6668 uint32_t index, offset, val;
6673 * Try to find which VF trigger a reset, use absolute VF id to access
6674 * since the reg is global register.
6676 for (i = 0; i < pf->vf_num; i++) {
6677 abs_vf_id = hw->func_caps.vf_base_id + i;
6678 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6679 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6680 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6681 /* VFR event occurred */
6682 if (val & (0x1 << offset)) {
6685 /* Clear the event first */
6686 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6688 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6690 * Only notify a VF reset event occurred,
6691 * don't trigger another SW reset
6693 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6694 if (ret != I40E_SUCCESS)
6695 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6701 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6703 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6706 for (i = 0; i < pf->vf_num; i++)
6707 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6711 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6713 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6714 struct i40e_arq_event_info info;
6715 uint16_t pending, opcode;
6718 info.buf_len = I40E_AQ_BUF_SZ;
6719 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6720 if (!info.msg_buf) {
6721 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6727 ret = i40e_clean_arq_element(hw, &info, &pending);
6729 if (ret != I40E_SUCCESS) {
6731 "Failed to read msg from AdminQ, aq_err: %u",
6732 hw->aq.asq_last_status);
6735 opcode = rte_le_to_cpu_16(info.desc.opcode);
6738 case i40e_aqc_opc_send_msg_to_pf:
6739 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6740 i40e_pf_host_handle_vf_msg(dev,
6741 rte_le_to_cpu_16(info.desc.retval),
6742 rte_le_to_cpu_32(info.desc.cookie_high),
6743 rte_le_to_cpu_32(info.desc.cookie_low),
6747 case i40e_aqc_opc_get_link_status:
6748 ret = i40e_dev_link_update(dev, 0);
6750 _rte_eth_dev_callback_process(dev,
6751 RTE_ETH_EVENT_INTR_LSC, NULL);
6754 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6759 rte_free(info.msg_buf);
6763 * Interrupt handler triggered by NIC for handling
6764 * specific interrupt.
6767 * Pointer to interrupt handle.
6769 * The address of parameter (struct rte_eth_dev *) regsitered before.
6775 i40e_dev_interrupt_handler(void *param)
6777 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6778 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6781 /* Disable interrupt */
6782 i40e_pf_disable_irq0(hw);
6784 /* read out interrupt causes */
6785 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6787 /* No interrupt event indicated */
6788 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6789 PMD_DRV_LOG(INFO, "No interrupt event");
6792 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6793 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6794 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6795 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6796 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6797 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6798 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6799 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6800 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6801 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6802 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6803 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6804 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6805 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6807 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6808 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6809 i40e_dev_handle_vfr_event(dev);
6811 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6812 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6813 i40e_dev_handle_aq_msg(dev);
6817 /* Enable interrupt */
6818 i40e_pf_enable_irq0(hw);
6822 i40e_dev_alarm_handler(void *param)
6824 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6825 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6828 /* Disable interrupt */
6829 i40e_pf_disable_irq0(hw);
6831 /* read out interrupt causes */
6832 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6834 /* No interrupt event indicated */
6835 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
6837 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6838 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6839 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6840 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6841 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6842 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6843 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6844 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6845 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6846 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6847 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6848 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6849 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6850 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6852 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6853 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6854 i40e_dev_handle_vfr_event(dev);
6856 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6857 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6858 i40e_dev_handle_aq_msg(dev);
6862 /* Enable interrupt */
6863 i40e_pf_enable_irq0(hw);
6864 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
6865 i40e_dev_alarm_handler, dev);
6869 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6870 struct i40e_macvlan_filter *filter,
6873 int ele_num, ele_buff_size;
6874 int num, actual_num, i;
6876 int ret = I40E_SUCCESS;
6877 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6878 struct i40e_aqc_add_macvlan_element_data *req_list;
6880 if (filter == NULL || total == 0)
6881 return I40E_ERR_PARAM;
6882 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6883 ele_buff_size = hw->aq.asq_buf_size;
6885 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6886 if (req_list == NULL) {
6887 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6888 return I40E_ERR_NO_MEMORY;
6893 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6894 memset(req_list, 0, ele_buff_size);
6896 for (i = 0; i < actual_num; i++) {
6897 rte_memcpy(req_list[i].mac_addr,
6898 &filter[num + i].macaddr, ETH_ADDR_LEN);
6899 req_list[i].vlan_tag =
6900 rte_cpu_to_le_16(filter[num + i].vlan_id);
6902 switch (filter[num + i].filter_type) {
6903 case RTE_MAC_PERFECT_MATCH:
6904 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6905 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6907 case RTE_MACVLAN_PERFECT_MATCH:
6908 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6910 case RTE_MAC_HASH_MATCH:
6911 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6912 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6914 case RTE_MACVLAN_HASH_MATCH:
6915 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6918 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6919 ret = I40E_ERR_PARAM;
6923 req_list[i].queue_number = 0;
6925 req_list[i].flags = rte_cpu_to_le_16(flags);
6928 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6930 if (ret != I40E_SUCCESS) {
6931 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6935 } while (num < total);
6943 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6944 struct i40e_macvlan_filter *filter,
6947 int ele_num, ele_buff_size;
6948 int num, actual_num, i;
6950 int ret = I40E_SUCCESS;
6951 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6952 struct i40e_aqc_remove_macvlan_element_data *req_list;
6954 if (filter == NULL || total == 0)
6955 return I40E_ERR_PARAM;
6957 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6958 ele_buff_size = hw->aq.asq_buf_size;
6960 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6961 if (req_list == NULL) {
6962 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6963 return I40E_ERR_NO_MEMORY;
6968 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6969 memset(req_list, 0, ele_buff_size);
6971 for (i = 0; i < actual_num; i++) {
6972 rte_memcpy(req_list[i].mac_addr,
6973 &filter[num + i].macaddr, ETH_ADDR_LEN);
6974 req_list[i].vlan_tag =
6975 rte_cpu_to_le_16(filter[num + i].vlan_id);
6977 switch (filter[num + i].filter_type) {
6978 case RTE_MAC_PERFECT_MATCH:
6979 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6980 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6982 case RTE_MACVLAN_PERFECT_MATCH:
6983 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6985 case RTE_MAC_HASH_MATCH:
6986 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6987 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6989 case RTE_MACVLAN_HASH_MATCH:
6990 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6993 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6994 ret = I40E_ERR_PARAM;
6997 req_list[i].flags = rte_cpu_to_le_16(flags);
7000 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
7002 if (ret != I40E_SUCCESS) {
7003 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
7007 } while (num < total);
7014 /* Find out specific MAC filter */
7015 static struct i40e_mac_filter *
7016 i40e_find_mac_filter(struct i40e_vsi *vsi,
7017 struct rte_ether_addr *macaddr)
7019 struct i40e_mac_filter *f;
7021 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7022 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
7030 i40e_find_vlan_filter(struct i40e_vsi *vsi,
7033 uint32_t vid_idx, vid_bit;
7035 if (vlan_id > ETH_VLAN_ID_MAX)
7038 vid_idx = I40E_VFTA_IDX(vlan_id);
7039 vid_bit = I40E_VFTA_BIT(vlan_id);
7041 if (vsi->vfta[vid_idx] & vid_bit)
7048 i40e_store_vlan_filter(struct i40e_vsi *vsi,
7049 uint16_t vlan_id, bool on)
7051 uint32_t vid_idx, vid_bit;
7053 vid_idx = I40E_VFTA_IDX(vlan_id);
7054 vid_bit = I40E_VFTA_BIT(vlan_id);
7057 vsi->vfta[vid_idx] |= vid_bit;
7059 vsi->vfta[vid_idx] &= ~vid_bit;
7063 i40e_set_vlan_filter(struct i40e_vsi *vsi,
7064 uint16_t vlan_id, bool on)
7066 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7067 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
7070 if (vlan_id > ETH_VLAN_ID_MAX)
7073 i40e_store_vlan_filter(vsi, vlan_id, on);
7075 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
7078 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
7081 ret = i40e_aq_add_vlan(hw, vsi->seid,
7082 &vlan_data, 1, NULL);
7083 if (ret != I40E_SUCCESS)
7084 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
7086 ret = i40e_aq_remove_vlan(hw, vsi->seid,
7087 &vlan_data, 1, NULL);
7088 if (ret != I40E_SUCCESS)
7090 "Failed to remove vlan filter");
7095 * Find all vlan options for specific mac addr,
7096 * return with actual vlan found.
7099 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
7100 struct i40e_macvlan_filter *mv_f,
7101 int num, struct rte_ether_addr *addr)
7107 * Not to use i40e_find_vlan_filter to decrease the loop time,
7108 * although the code looks complex.
7110 if (num < vsi->vlan_num)
7111 return I40E_ERR_PARAM;
7114 for (j = 0; j < I40E_VFTA_SIZE; j++) {
7116 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
7117 if (vsi->vfta[j] & (1 << k)) {
7120 "vlan number doesn't match");
7121 return I40E_ERR_PARAM;
7123 rte_memcpy(&mv_f[i].macaddr,
7124 addr, ETH_ADDR_LEN);
7126 j * I40E_UINT32_BIT_SIZE + k;
7132 return I40E_SUCCESS;
7136 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
7137 struct i40e_macvlan_filter *mv_f,
7142 struct i40e_mac_filter *f;
7144 if (num < vsi->mac_num)
7145 return I40E_ERR_PARAM;
7147 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7149 PMD_DRV_LOG(ERR, "buffer number not match");
7150 return I40E_ERR_PARAM;
7152 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7154 mv_f[i].vlan_id = vlan;
7155 mv_f[i].filter_type = f->mac_info.filter_type;
7159 return I40E_SUCCESS;
7163 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
7166 struct i40e_mac_filter *f;
7167 struct i40e_macvlan_filter *mv_f;
7168 int ret = I40E_SUCCESS;
7170 if (vsi == NULL || vsi->mac_num == 0)
7171 return I40E_ERR_PARAM;
7173 /* Case that no vlan is set */
7174 if (vsi->vlan_num == 0)
7177 num = vsi->mac_num * vsi->vlan_num;
7179 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7181 PMD_DRV_LOG(ERR, "failed to allocate memory");
7182 return I40E_ERR_NO_MEMORY;
7186 if (vsi->vlan_num == 0) {
7187 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7188 rte_memcpy(&mv_f[i].macaddr,
7189 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7190 mv_f[i].filter_type = f->mac_info.filter_type;
7191 mv_f[i].vlan_id = 0;
7195 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7196 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7197 vsi->vlan_num, &f->mac_info.mac_addr);
7198 if (ret != I40E_SUCCESS)
7200 for (j = i; j < i + vsi->vlan_num; j++)
7201 mv_f[j].filter_type = f->mac_info.filter_type;
7206 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7214 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7216 struct i40e_macvlan_filter *mv_f;
7218 int ret = I40E_SUCCESS;
7220 if (!vsi || vlan > RTE_ETHER_MAX_VLAN_ID)
7221 return I40E_ERR_PARAM;
7223 /* If it's already set, just return */
7224 if (i40e_find_vlan_filter(vsi,vlan))
7225 return I40E_SUCCESS;
7227 mac_num = vsi->mac_num;
7230 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7231 return I40E_ERR_PARAM;
7234 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7237 PMD_DRV_LOG(ERR, "failed to allocate memory");
7238 return I40E_ERR_NO_MEMORY;
7241 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7243 if (ret != I40E_SUCCESS)
7246 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7248 if (ret != I40E_SUCCESS)
7251 i40e_set_vlan_filter(vsi, vlan, 1);
7261 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7263 struct i40e_macvlan_filter *mv_f;
7265 int ret = I40E_SUCCESS;
7268 * Vlan 0 is the generic filter for untagged packets
7269 * and can't be removed.
7271 if (!vsi || vlan == 0 || vlan > RTE_ETHER_MAX_VLAN_ID)
7272 return I40E_ERR_PARAM;
7274 /* If can't find it, just return */
7275 if (!i40e_find_vlan_filter(vsi, vlan))
7276 return I40E_ERR_PARAM;
7278 mac_num = vsi->mac_num;
7281 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7282 return I40E_ERR_PARAM;
7285 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7288 PMD_DRV_LOG(ERR, "failed to allocate memory");
7289 return I40E_ERR_NO_MEMORY;
7292 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7294 if (ret != I40E_SUCCESS)
7297 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7299 if (ret != I40E_SUCCESS)
7302 /* This is last vlan to remove, replace all mac filter with vlan 0 */
7303 if (vsi->vlan_num == 1) {
7304 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7305 if (ret != I40E_SUCCESS)
7308 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7309 if (ret != I40E_SUCCESS)
7313 i40e_set_vlan_filter(vsi, vlan, 0);
7323 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7325 struct i40e_mac_filter *f;
7326 struct i40e_macvlan_filter *mv_f;
7327 int i, vlan_num = 0;
7328 int ret = I40E_SUCCESS;
7330 /* If it's add and we've config it, return */
7331 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7333 return I40E_SUCCESS;
7334 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
7335 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
7338 * If vlan_num is 0, that's the first time to add mac,
7339 * set mask for vlan_id 0.
7341 if (vsi->vlan_num == 0) {
7342 i40e_set_vlan_filter(vsi, 0, 1);
7345 vlan_num = vsi->vlan_num;
7346 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
7347 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
7350 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7352 PMD_DRV_LOG(ERR, "failed to allocate memory");
7353 return I40E_ERR_NO_MEMORY;
7356 for (i = 0; i < vlan_num; i++) {
7357 mv_f[i].filter_type = mac_filter->filter_type;
7358 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7362 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7363 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
7364 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7365 &mac_filter->mac_addr);
7366 if (ret != I40E_SUCCESS)
7370 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7371 if (ret != I40E_SUCCESS)
7374 /* Add the mac addr into mac list */
7375 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7377 PMD_DRV_LOG(ERR, "failed to allocate memory");
7378 ret = I40E_ERR_NO_MEMORY;
7381 rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7383 f->mac_info.filter_type = mac_filter->filter_type;
7384 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7395 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr)
7397 struct i40e_mac_filter *f;
7398 struct i40e_macvlan_filter *mv_f;
7400 enum rte_mac_filter_type filter_type;
7401 int ret = I40E_SUCCESS;
7403 /* Can't find it, return an error */
7404 f = i40e_find_mac_filter(vsi, addr);
7406 return I40E_ERR_PARAM;
7408 vlan_num = vsi->vlan_num;
7409 filter_type = f->mac_info.filter_type;
7410 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7411 filter_type == RTE_MACVLAN_HASH_MATCH) {
7412 if (vlan_num == 0) {
7413 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7414 return I40E_ERR_PARAM;
7416 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7417 filter_type == RTE_MAC_HASH_MATCH)
7420 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7422 PMD_DRV_LOG(ERR, "failed to allocate memory");
7423 return I40E_ERR_NO_MEMORY;
7426 for (i = 0; i < vlan_num; i++) {
7427 mv_f[i].filter_type = filter_type;
7428 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7431 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7432 filter_type == RTE_MACVLAN_HASH_MATCH) {
7433 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7434 if (ret != I40E_SUCCESS)
7438 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7439 if (ret != I40E_SUCCESS)
7442 /* Remove the mac addr into mac list */
7443 TAILQ_REMOVE(&vsi->mac_list, f, next);
7453 /* Configure hash enable flags for RSS */
7455 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7463 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7464 if (flags & (1ULL << i))
7465 hena |= adapter->pctypes_tbl[i];
7471 /* Parse the hash enable flags */
7473 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7475 uint64_t rss_hf = 0;
7481 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7482 if (flags & adapter->pctypes_tbl[i])
7483 rss_hf |= (1ULL << i);
7490 i40e_pf_disable_rss(struct i40e_pf *pf)
7492 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7494 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7495 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7496 I40E_WRITE_FLUSH(hw);
7500 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7502 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7503 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7504 uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7505 I40E_VFQF_HKEY_MAX_INDEX :
7506 I40E_PFQF_HKEY_MAX_INDEX;
7509 if (!key || key_len == 0) {
7510 PMD_DRV_LOG(DEBUG, "No key to be configured");
7512 } else if (key_len != (key_idx + 1) *
7514 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7518 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7519 struct i40e_aqc_get_set_rss_key_data *key_dw =
7520 (struct i40e_aqc_get_set_rss_key_data *)key;
7522 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7524 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7526 uint32_t *hash_key = (uint32_t *)key;
7529 if (vsi->type == I40E_VSI_SRIOV) {
7530 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7533 I40E_VFQF_HKEY1(i, vsi->user_param),
7537 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7538 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7541 I40E_WRITE_FLUSH(hw);
7548 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7550 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7551 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7555 if (!key || !key_len)
7558 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7559 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7560 (struct i40e_aqc_get_set_rss_key_data *)key);
7562 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7566 uint32_t *key_dw = (uint32_t *)key;
7569 if (vsi->type == I40E_VSI_SRIOV) {
7570 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7571 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7572 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7574 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7577 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7578 reg = I40E_PFQF_HKEY(i);
7579 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7581 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7589 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7591 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7595 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7596 rss_conf->rss_key_len);
7600 hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7601 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7602 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7603 I40E_WRITE_FLUSH(hw);
7609 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7610 struct rte_eth_rss_conf *rss_conf)
7612 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7613 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7614 uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7617 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7618 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7620 if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7621 if (rss_hf != 0) /* Enable RSS */
7623 return 0; /* Nothing to do */
7626 if (rss_hf == 0) /* Disable RSS */
7629 return i40e_hw_rss_hash_set(pf, rss_conf);
7633 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7634 struct rte_eth_rss_conf *rss_conf)
7636 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7637 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7644 ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7645 &rss_conf->rss_key_len);
7649 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7650 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7651 rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7657 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7659 switch (filter_type) {
7660 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7661 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7663 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7664 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7666 case RTE_TUNNEL_FILTER_IMAC_TENID:
7667 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7669 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7670 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7672 case ETH_TUNNEL_FILTER_IMAC:
7673 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7675 case ETH_TUNNEL_FILTER_OIP:
7676 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7678 case ETH_TUNNEL_FILTER_IIP:
7679 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7682 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7689 /* Convert tunnel filter structure */
7691 i40e_tunnel_filter_convert(
7692 struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7693 struct i40e_tunnel_filter *tunnel_filter)
7695 rte_ether_addr_copy((struct rte_ether_addr *)
7696 &cld_filter->element.outer_mac,
7697 (struct rte_ether_addr *)&tunnel_filter->input.outer_mac);
7698 rte_ether_addr_copy((struct rte_ether_addr *)
7699 &cld_filter->element.inner_mac,
7700 (struct rte_ether_addr *)&tunnel_filter->input.inner_mac);
7701 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7702 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7703 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7704 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7705 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7707 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7708 tunnel_filter->input.flags = cld_filter->element.flags;
7709 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7710 tunnel_filter->queue = cld_filter->element.queue_number;
7711 rte_memcpy(tunnel_filter->input.general_fields,
7712 cld_filter->general_fields,
7713 sizeof(cld_filter->general_fields));
7718 /* Check if there exists the tunnel filter */
7719 struct i40e_tunnel_filter *
7720 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7721 const struct i40e_tunnel_filter_input *input)
7725 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7729 return tunnel_rule->hash_map[ret];
7732 /* Add a tunnel filter into the SW list */
7734 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7735 struct i40e_tunnel_filter *tunnel_filter)
7737 struct i40e_tunnel_rule *rule = &pf->tunnel;
7740 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7743 "Failed to insert tunnel filter to hash table %d!",
7747 rule->hash_map[ret] = tunnel_filter;
7749 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7754 /* Delete a tunnel filter from the SW list */
7756 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7757 struct i40e_tunnel_filter_input *input)
7759 struct i40e_tunnel_rule *rule = &pf->tunnel;
7760 struct i40e_tunnel_filter *tunnel_filter;
7763 ret = rte_hash_del_key(rule->hash_table, input);
7766 "Failed to delete tunnel filter to hash table %d!",
7770 tunnel_filter = rule->hash_map[ret];
7771 rule->hash_map[ret] = NULL;
7773 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7774 rte_free(tunnel_filter);
7780 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7781 struct rte_eth_tunnel_filter_conf *tunnel_filter,
7785 uint32_t ipv4_addr, ipv4_addr_le;
7786 uint8_t i, tun_type = 0;
7787 /* internal varialbe to convert ipv6 byte order */
7788 uint32_t convert_ipv6[4];
7790 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7791 struct i40e_vsi *vsi = pf->main_vsi;
7792 struct i40e_aqc_cloud_filters_element_bb *cld_filter;
7793 struct i40e_aqc_cloud_filters_element_bb *pfilter;
7794 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7795 struct i40e_tunnel_filter *tunnel, *node;
7796 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7798 cld_filter = rte_zmalloc("tunnel_filter",
7799 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7802 if (NULL == cld_filter) {
7803 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7806 pfilter = cld_filter;
7808 rte_ether_addr_copy(&tunnel_filter->outer_mac,
7809 (struct rte_ether_addr *)&pfilter->element.outer_mac);
7810 rte_ether_addr_copy(&tunnel_filter->inner_mac,
7811 (struct rte_ether_addr *)&pfilter->element.inner_mac);
7813 pfilter->element.inner_vlan =
7814 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7815 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7816 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7817 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7818 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7819 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7821 sizeof(pfilter->element.ipaddr.v4.data));
7823 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7824 for (i = 0; i < 4; i++) {
7826 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7828 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7830 sizeof(pfilter->element.ipaddr.v6.data));
7833 /* check tunneled type */
7834 switch (tunnel_filter->tunnel_type) {
7835 case RTE_TUNNEL_TYPE_VXLAN:
7836 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7838 case RTE_TUNNEL_TYPE_NVGRE:
7839 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7841 case RTE_TUNNEL_TYPE_IP_IN_GRE:
7842 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7844 case RTE_TUNNEL_TYPE_VXLAN_GPE:
7845 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE;
7848 /* Other tunnel types is not supported. */
7849 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7850 rte_free(cld_filter);
7854 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7855 &pfilter->element.flags);
7857 rte_free(cld_filter);
7861 pfilter->element.flags |= rte_cpu_to_le_16(
7862 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7863 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7864 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7865 pfilter->element.queue_number =
7866 rte_cpu_to_le_16(tunnel_filter->queue_id);
7868 /* Check if there is the filter in SW list */
7869 memset(&check_filter, 0, sizeof(check_filter));
7870 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7871 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7873 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7874 rte_free(cld_filter);
7878 if (!add && !node) {
7879 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7880 rte_free(cld_filter);
7885 ret = i40e_aq_add_cloud_filters(hw,
7886 vsi->seid, &cld_filter->element, 1);
7888 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7889 rte_free(cld_filter);
7892 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7893 if (tunnel == NULL) {
7894 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7895 rte_free(cld_filter);
7899 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7900 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7904 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
7905 &cld_filter->element, 1);
7907 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7908 rte_free(cld_filter);
7911 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7914 rte_free(cld_filter);
7918 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7919 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
7920 #define I40E_TR_GENEVE_KEY_MASK 0x8
7921 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
7922 #define I40E_TR_GRE_KEY_MASK 0x400
7923 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
7924 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
7927 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7929 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7930 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7931 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7932 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7933 enum i40e_status_code status = I40E_SUCCESS;
7935 if (pf->support_multi_driver) {
7936 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7937 return I40E_NOT_SUPPORTED;
7940 memset(&filter_replace, 0,
7941 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7942 memset(&filter_replace_buf, 0,
7943 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7945 /* create L1 filter */
7946 filter_replace.old_filter_type =
7947 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7948 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7949 filter_replace.tr_bit = 0;
7951 /* Prepare the buffer, 3 entries */
7952 filter_replace_buf.data[0] =
7953 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7954 filter_replace_buf.data[0] |=
7955 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7956 filter_replace_buf.data[2] = 0xFF;
7957 filter_replace_buf.data[3] = 0xFF;
7958 filter_replace_buf.data[4] =
7959 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7960 filter_replace_buf.data[4] |=
7961 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7962 filter_replace_buf.data[7] = 0xF0;
7963 filter_replace_buf.data[8]
7964 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7965 filter_replace_buf.data[8] |=
7966 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7967 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7968 I40E_TR_GENEVE_KEY_MASK |
7969 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7970 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7971 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7972 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7974 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7975 &filter_replace_buf);
7976 if (!status && (filter_replace.old_filter_type !=
7977 filter_replace.new_filter_type))
7978 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7979 " original: 0x%x, new: 0x%x",
7981 filter_replace.old_filter_type,
7982 filter_replace.new_filter_type);
7988 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7990 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7991 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7992 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7993 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7994 enum i40e_status_code status = I40E_SUCCESS;
7996 if (pf->support_multi_driver) {
7997 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7998 return I40E_NOT_SUPPORTED;
8002 memset(&filter_replace, 0,
8003 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8004 memset(&filter_replace_buf, 0,
8005 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8006 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
8007 I40E_AQC_MIRROR_CLOUD_FILTER;
8008 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
8009 filter_replace.new_filter_type =
8010 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8011 /* Prepare the buffer, 2 entries */
8012 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8013 filter_replace_buf.data[0] |=
8014 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8015 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8016 filter_replace_buf.data[4] |=
8017 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8018 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8019 &filter_replace_buf);
8022 if (filter_replace.old_filter_type !=
8023 filter_replace.new_filter_type)
8024 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8025 " original: 0x%x, new: 0x%x",
8027 filter_replace.old_filter_type,
8028 filter_replace.new_filter_type);
8031 memset(&filter_replace, 0,
8032 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8033 memset(&filter_replace_buf, 0,
8034 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8036 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
8037 I40E_AQC_MIRROR_CLOUD_FILTER;
8038 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
8039 filter_replace.new_filter_type =
8040 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8041 /* Prepare the buffer, 2 entries */
8042 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8043 filter_replace_buf.data[0] |=
8044 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8045 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8046 filter_replace_buf.data[4] |=
8047 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8049 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8050 &filter_replace_buf);
8051 if (!status && (filter_replace.old_filter_type !=
8052 filter_replace.new_filter_type))
8053 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8054 " original: 0x%x, new: 0x%x",
8056 filter_replace.old_filter_type,
8057 filter_replace.new_filter_type);
8062 static enum i40e_status_code
8063 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
8065 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8066 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8067 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8068 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8069 enum i40e_status_code status = I40E_SUCCESS;
8071 if (pf->support_multi_driver) {
8072 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8073 return I40E_NOT_SUPPORTED;
8077 memset(&filter_replace, 0,
8078 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8079 memset(&filter_replace_buf, 0,
8080 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8081 /* create L1 filter */
8082 filter_replace.old_filter_type =
8083 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
8084 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
8085 filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
8086 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8087 /* Prepare the buffer, 2 entries */
8088 filter_replace_buf.data[0] =
8089 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8090 filter_replace_buf.data[0] |=
8091 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8092 filter_replace_buf.data[2] = 0xFF;
8093 filter_replace_buf.data[3] = 0xFF;
8094 filter_replace_buf.data[4] =
8095 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8096 filter_replace_buf.data[4] |=
8097 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8098 filter_replace_buf.data[6] = 0xFF;
8099 filter_replace_buf.data[7] = 0xFF;
8100 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8101 &filter_replace_buf);
8104 if (filter_replace.old_filter_type !=
8105 filter_replace.new_filter_type)
8106 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8107 " original: 0x%x, new: 0x%x",
8109 filter_replace.old_filter_type,
8110 filter_replace.new_filter_type);
8113 memset(&filter_replace, 0,
8114 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8115 memset(&filter_replace_buf, 0,
8116 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8117 /* create L1 filter */
8118 filter_replace.old_filter_type =
8119 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8120 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
8121 filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
8122 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8123 /* Prepare the buffer, 2 entries */
8124 filter_replace_buf.data[0] =
8125 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8126 filter_replace_buf.data[0] |=
8127 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8128 filter_replace_buf.data[2] = 0xFF;
8129 filter_replace_buf.data[3] = 0xFF;
8130 filter_replace_buf.data[4] =
8131 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8132 filter_replace_buf.data[4] |=
8133 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8134 filter_replace_buf.data[6] = 0xFF;
8135 filter_replace_buf.data[7] = 0xFF;
8137 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8138 &filter_replace_buf);
8139 if (!status && (filter_replace.old_filter_type !=
8140 filter_replace.new_filter_type))
8141 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8142 " original: 0x%x, new: 0x%x",
8144 filter_replace.old_filter_type,
8145 filter_replace.new_filter_type);
8151 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
8153 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
8154 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
8155 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8156 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8157 enum i40e_status_code status = I40E_SUCCESS;
8159 if (pf->support_multi_driver) {
8160 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8161 return I40E_NOT_SUPPORTED;
8165 memset(&filter_replace, 0,
8166 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8167 memset(&filter_replace_buf, 0,
8168 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8169 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8170 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
8171 filter_replace.new_filter_type =
8172 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8173 /* Prepare the buffer, 2 entries */
8174 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
8175 filter_replace_buf.data[0] |=
8176 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8177 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8178 filter_replace_buf.data[4] |=
8179 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8180 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8181 &filter_replace_buf);
8184 if (filter_replace.old_filter_type !=
8185 filter_replace.new_filter_type)
8186 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8187 " original: 0x%x, new: 0x%x",
8189 filter_replace.old_filter_type,
8190 filter_replace.new_filter_type);
8193 memset(&filter_replace, 0,
8194 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8195 memset(&filter_replace_buf, 0,
8196 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8197 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8198 filter_replace.old_filter_type =
8199 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8200 filter_replace.new_filter_type =
8201 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8202 /* Prepare the buffer, 2 entries */
8203 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8204 filter_replace_buf.data[0] |=
8205 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8206 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8207 filter_replace_buf.data[4] |=
8208 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8210 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8211 &filter_replace_buf);
8212 if (!status && (filter_replace.old_filter_type !=
8213 filter_replace.new_filter_type))
8214 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8215 " original: 0x%x, new: 0x%x",
8217 filter_replace.old_filter_type,
8218 filter_replace.new_filter_type);
8224 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8225 struct i40e_tunnel_filter_conf *tunnel_filter,
8229 uint32_t ipv4_addr, ipv4_addr_le;
8230 uint8_t i, tun_type = 0;
8231 /* internal variable to convert ipv6 byte order */
8232 uint32_t convert_ipv6[4];
8234 struct i40e_pf_vf *vf = NULL;
8235 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8236 struct i40e_vsi *vsi;
8237 struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8238 struct i40e_aqc_cloud_filters_element_bb *pfilter;
8239 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8240 struct i40e_tunnel_filter *tunnel, *node;
8241 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8243 bool big_buffer = 0;
8245 cld_filter = rte_zmalloc("tunnel_filter",
8246 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8249 if (cld_filter == NULL) {
8250 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8253 pfilter = cld_filter;
8255 rte_ether_addr_copy(&tunnel_filter->outer_mac,
8256 (struct rte_ether_addr *)&pfilter->element.outer_mac);
8257 rte_ether_addr_copy(&tunnel_filter->inner_mac,
8258 (struct rte_ether_addr *)&pfilter->element.inner_mac);
8260 pfilter->element.inner_vlan =
8261 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8262 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8263 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8264 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8265 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8266 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8268 sizeof(pfilter->element.ipaddr.v4.data));
8270 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8271 for (i = 0; i < 4; i++) {
8273 rte_cpu_to_le_32(rte_be_to_cpu_32(
8274 tunnel_filter->ip_addr.ipv6_addr[i]));
8276 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8278 sizeof(pfilter->element.ipaddr.v6.data));
8281 /* check tunneled type */
8282 switch (tunnel_filter->tunnel_type) {
8283 case I40E_TUNNEL_TYPE_VXLAN:
8284 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8286 case I40E_TUNNEL_TYPE_NVGRE:
8287 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8289 case I40E_TUNNEL_TYPE_IP_IN_GRE:
8290 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8292 case I40E_TUNNEL_TYPE_MPLSoUDP:
8293 if (!pf->mpls_replace_flag) {
8294 i40e_replace_mpls_l1_filter(pf);
8295 i40e_replace_mpls_cloud_filter(pf);
8296 pf->mpls_replace_flag = 1;
8298 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8299 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8301 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8302 (teid_le & 0xF) << 12;
8303 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8306 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8308 case I40E_TUNNEL_TYPE_MPLSoGRE:
8309 if (!pf->mpls_replace_flag) {
8310 i40e_replace_mpls_l1_filter(pf);
8311 i40e_replace_mpls_cloud_filter(pf);
8312 pf->mpls_replace_flag = 1;
8314 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8315 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8317 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8318 (teid_le & 0xF) << 12;
8319 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8322 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8324 case I40E_TUNNEL_TYPE_GTPC:
8325 if (!pf->gtp_replace_flag) {
8326 i40e_replace_gtp_l1_filter(pf);
8327 i40e_replace_gtp_cloud_filter(pf);
8328 pf->gtp_replace_flag = 1;
8330 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8331 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8332 (teid_le >> 16) & 0xFFFF;
8333 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8335 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8339 case I40E_TUNNEL_TYPE_GTPU:
8340 if (!pf->gtp_replace_flag) {
8341 i40e_replace_gtp_l1_filter(pf);
8342 i40e_replace_gtp_cloud_filter(pf);
8343 pf->gtp_replace_flag = 1;
8345 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8346 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8347 (teid_le >> 16) & 0xFFFF;
8348 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8350 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8354 case I40E_TUNNEL_TYPE_QINQ:
8355 if (!pf->qinq_replace_flag) {
8356 ret = i40e_cloud_filter_qinq_create(pf);
8359 "QinQ tunnel filter already created.");
8360 pf->qinq_replace_flag = 1;
8362 /* Add in the General fields the values of
8363 * the Outer and Inner VLAN
8364 * Big Buffer should be set, see changes in
8365 * i40e_aq_add_cloud_filters
8367 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8368 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8372 /* Other tunnel types is not supported. */
8373 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8374 rte_free(cld_filter);
8378 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8379 pfilter->element.flags =
8380 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8381 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8382 pfilter->element.flags =
8383 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8384 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8385 pfilter->element.flags =
8386 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8387 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8388 pfilter->element.flags =
8389 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8390 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8391 pfilter->element.flags |=
8392 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8394 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8395 &pfilter->element.flags);
8397 rte_free(cld_filter);
8402 pfilter->element.flags |= rte_cpu_to_le_16(
8403 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8404 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8405 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8406 pfilter->element.queue_number =
8407 rte_cpu_to_le_16(tunnel_filter->queue_id);
8409 if (!tunnel_filter->is_to_vf)
8412 if (tunnel_filter->vf_id >= pf->vf_num) {
8413 PMD_DRV_LOG(ERR, "Invalid argument.");
8414 rte_free(cld_filter);
8417 vf = &pf->vfs[tunnel_filter->vf_id];
8421 /* Check if there is the filter in SW list */
8422 memset(&check_filter, 0, sizeof(check_filter));
8423 i40e_tunnel_filter_convert(cld_filter, &check_filter);
8424 check_filter.is_to_vf = tunnel_filter->is_to_vf;
8425 check_filter.vf_id = tunnel_filter->vf_id;
8426 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8428 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8429 rte_free(cld_filter);
8433 if (!add && !node) {
8434 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8435 rte_free(cld_filter);
8441 ret = i40e_aq_add_cloud_filters_bb(hw,
8442 vsi->seid, cld_filter, 1);
8444 ret = i40e_aq_add_cloud_filters(hw,
8445 vsi->seid, &cld_filter->element, 1);
8447 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8448 rte_free(cld_filter);
8451 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8452 if (tunnel == NULL) {
8453 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8454 rte_free(cld_filter);
8458 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8459 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8464 ret = i40e_aq_rem_cloud_filters_bb(
8465 hw, vsi->seid, cld_filter, 1);
8467 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8468 &cld_filter->element, 1);
8470 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8471 rte_free(cld_filter);
8474 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8477 rte_free(cld_filter);
8482 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8486 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8487 if (pf->vxlan_ports[i] == port)
8495 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port, int udp_type)
8498 uint8_t filter_idx = 0;
8499 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8501 idx = i40e_get_vxlan_port_idx(pf, port);
8503 /* Check if port already exists */
8505 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8509 /* Now check if there is space to add the new port */
8510 idx = i40e_get_vxlan_port_idx(pf, 0);
8513 "Maximum number of UDP ports reached, not adding port %d",
8518 ret = i40e_aq_add_udp_tunnel(hw, port, udp_type,
8521 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8525 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8528 /* New port: add it and mark its index in the bitmap */
8529 pf->vxlan_ports[idx] = port;
8530 pf->vxlan_bitmap |= (1 << idx);
8532 if (!(pf->flags & I40E_FLAG_VXLAN))
8533 pf->flags |= I40E_FLAG_VXLAN;
8539 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8542 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8544 if (!(pf->flags & I40E_FLAG_VXLAN)) {
8545 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8549 idx = i40e_get_vxlan_port_idx(pf, port);
8552 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8556 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8557 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8561 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8564 pf->vxlan_ports[idx] = 0;
8565 pf->vxlan_bitmap &= ~(1 << idx);
8567 if (!pf->vxlan_bitmap)
8568 pf->flags &= ~I40E_FLAG_VXLAN;
8573 /* Add UDP tunneling port */
8575 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8576 struct rte_eth_udp_tunnel *udp_tunnel)
8579 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8581 if (udp_tunnel == NULL)
8584 switch (udp_tunnel->prot_type) {
8585 case RTE_TUNNEL_TYPE_VXLAN:
8586 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8587 I40E_AQC_TUNNEL_TYPE_VXLAN);
8589 case RTE_TUNNEL_TYPE_VXLAN_GPE:
8590 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8591 I40E_AQC_TUNNEL_TYPE_VXLAN_GPE);
8593 case RTE_TUNNEL_TYPE_GENEVE:
8594 case RTE_TUNNEL_TYPE_TEREDO:
8595 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8600 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8608 /* Remove UDP tunneling port */
8610 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8611 struct rte_eth_udp_tunnel *udp_tunnel)
8614 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8616 if (udp_tunnel == NULL)
8619 switch (udp_tunnel->prot_type) {
8620 case RTE_TUNNEL_TYPE_VXLAN:
8621 case RTE_TUNNEL_TYPE_VXLAN_GPE:
8622 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8624 case RTE_TUNNEL_TYPE_GENEVE:
8625 case RTE_TUNNEL_TYPE_TEREDO:
8626 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8630 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8638 /* Calculate the maximum number of contiguous PF queues that are configured */
8640 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8642 struct rte_eth_dev_data *data = pf->dev_data;
8644 struct i40e_rx_queue *rxq;
8647 for (i = 0; i < pf->lan_nb_qps; i++) {
8648 rxq = data->rx_queues[i];
8649 if (rxq && rxq->q_set)
8660 i40e_pf_config_rss(struct i40e_pf *pf)
8662 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8663 struct rte_eth_rss_conf rss_conf;
8664 uint32_t i, lut = 0;
8668 * If both VMDQ and RSS enabled, not all of PF queues are configured.
8669 * It's necessary to calculate the actual PF queues that are configured.
8671 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8672 num = i40e_pf_calc_configured_queues_num(pf);
8674 num = pf->dev_data->nb_rx_queues;
8676 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8677 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8681 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
8685 if (pf->adapter->rss_reta_updated == 0) {
8686 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8689 lut = (lut << 8) | (j & ((0x1 <<
8690 hw->func_caps.rss_table_entry_width) - 1));
8692 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2),
8697 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8698 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8699 i40e_pf_disable_rss(pf);
8702 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8703 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8704 /* Random default keys */
8705 static uint32_t rss_key_default[] = {0x6b793944,
8706 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8707 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8708 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8710 rss_conf.rss_key = (uint8_t *)rss_key_default;
8711 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8715 return i40e_hw_rss_hash_set(pf, &rss_conf);
8719 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8720 struct rte_eth_tunnel_filter_conf *filter)
8722 if (pf == NULL || filter == NULL) {
8723 PMD_DRV_LOG(ERR, "Invalid parameter");
8727 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8728 PMD_DRV_LOG(ERR, "Invalid queue ID");
8732 if (filter->inner_vlan > RTE_ETHER_MAX_VLAN_ID) {
8733 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8737 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8738 (rte_is_zero_ether_addr(&filter->outer_mac))) {
8739 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8743 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8744 (rte_is_zero_ether_addr(&filter->inner_mac))) {
8745 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8752 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8753 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
8755 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8757 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8761 if (pf->support_multi_driver) {
8762 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8766 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8767 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8770 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8771 } else if (len == 4) {
8772 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8774 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8779 ret = i40e_aq_debug_write_global_register(hw,
8780 I40E_GL_PRS_FVBM(2),
8784 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8785 "with value 0x%08x",
8786 I40E_GL_PRS_FVBM(2), reg);
8790 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8791 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8797 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8804 switch (cfg->cfg_type) {
8805 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8806 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8809 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8817 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8818 enum rte_filter_op filter_op,
8821 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8822 int ret = I40E_ERR_PARAM;
8824 switch (filter_op) {
8825 case RTE_ETH_FILTER_SET:
8826 ret = i40e_dev_global_config_set(hw,
8827 (struct rte_eth_global_cfg *)arg);
8830 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8838 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8839 enum rte_filter_op filter_op,
8842 struct rte_eth_tunnel_filter_conf *filter;
8843 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8844 int ret = I40E_SUCCESS;
8846 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8848 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8849 return I40E_ERR_PARAM;
8851 switch (filter_op) {
8852 case RTE_ETH_FILTER_NOP:
8853 if (!(pf->flags & I40E_FLAG_VXLAN))
8854 ret = I40E_NOT_SUPPORTED;
8856 case RTE_ETH_FILTER_ADD:
8857 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8859 case RTE_ETH_FILTER_DELETE:
8860 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8863 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8864 ret = I40E_ERR_PARAM;
8872 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8875 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8878 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8879 ret = i40e_pf_config_rss(pf);
8881 i40e_pf_disable_rss(pf);
8886 /* Get the symmetric hash enable configurations per port */
8888 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8890 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8892 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8895 /* Set the symmetric hash enable configurations per port */
8897 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8899 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8902 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8904 "Symmetric hash has already been enabled");
8907 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8909 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8911 "Symmetric hash has already been disabled");
8914 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8916 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8917 I40E_WRITE_FLUSH(hw);
8921 * Get global configurations of hash function type and symmetric hash enable
8922 * per flow type (pctype). Note that global configuration means it affects all
8923 * the ports on the same NIC.
8926 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8927 struct rte_eth_hash_global_conf *g_cfg)
8929 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8933 memset(g_cfg, 0, sizeof(*g_cfg));
8934 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8935 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8936 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8938 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8939 PMD_DRV_LOG(DEBUG, "Hash function is %s",
8940 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8943 * As i40e supports less than 64 flow types, only first 64 bits need to
8946 for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8947 g_cfg->valid_bit_mask[i] = 0ULL;
8948 g_cfg->sym_hash_enable_mask[i] = 0ULL;
8951 g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
8953 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
8954 if (!adapter->pctypes_tbl[i])
8956 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8957 j < I40E_FILTER_PCTYPE_MAX; j++) {
8958 if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8959 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8960 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8961 g_cfg->sym_hash_enable_mask[0] |=
8972 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8973 const struct rte_eth_hash_global_conf *g_cfg)
8976 uint64_t mask0, i40e_mask = adapter->flow_types_mask;
8978 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8979 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8980 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8981 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8987 * As i40e supports less than 64 flow types, only first 64 bits need to
8990 mask0 = g_cfg->valid_bit_mask[0];
8991 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8993 /* Check if any unsupported flow type configured */
8994 if ((mask0 | i40e_mask) ^ i40e_mask)
8997 if (g_cfg->valid_bit_mask[i])
9005 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
9011 * Set global configurations of hash function type and symmetric hash enable
9012 * per flow type (pctype). Note any modifying global configuration will affect
9013 * all the ports on the same NIC.
9016 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
9017 struct rte_eth_hash_global_conf *g_cfg)
9019 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
9020 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9024 uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
9026 if (pf->support_multi_driver) {
9027 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
9031 /* Check the input parameters */
9032 ret = i40e_hash_global_config_check(adapter, g_cfg);
9037 * As i40e supports less than 64 flow types, only first 64 bits need to
9040 for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
9041 if (mask0 & (1UL << i)) {
9042 reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
9043 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
9045 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
9046 j < I40E_FILTER_PCTYPE_MAX; j++) {
9047 if (adapter->pctypes_tbl[i] & (1ULL << j))
9048 i40e_write_global_rx_ctl(hw,
9055 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
9056 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
9058 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
9060 "Hash function already set to Toeplitz");
9063 reg |= I40E_GLQF_CTL_HTOEP_MASK;
9064 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
9066 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
9068 "Hash function already set to Simple XOR");
9071 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
9073 /* Use the default, and keep it as it is */
9076 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
9079 I40E_WRITE_FLUSH(hw);
9085 * Valid input sets for hash and flow director filters per PCTYPE
9088 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
9089 enum rte_filter_type filter)
9093 static const uint64_t valid_hash_inset_table[] = {
9094 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9095 I40E_INSET_DMAC | I40E_INSET_SMAC |
9096 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9097 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
9098 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
9099 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9100 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9101 I40E_INSET_FLEX_PAYLOAD,
9102 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9103 I40E_INSET_DMAC | I40E_INSET_SMAC |
9104 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9105 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9106 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9107 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9108 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9109 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9110 I40E_INSET_FLEX_PAYLOAD,
9111 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9112 I40E_INSET_DMAC | I40E_INSET_SMAC |
9113 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9114 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9115 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9116 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9117 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9118 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9119 I40E_INSET_FLEX_PAYLOAD,
9120 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9121 I40E_INSET_DMAC | I40E_INSET_SMAC |
9122 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9123 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9124 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9125 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9126 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9127 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9128 I40E_INSET_FLEX_PAYLOAD,
9129 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9130 I40E_INSET_DMAC | I40E_INSET_SMAC |
9131 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9132 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9133 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9134 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9135 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9136 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9137 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9138 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9139 I40E_INSET_DMAC | I40E_INSET_SMAC |
9140 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9141 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9142 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9143 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9144 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9145 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9146 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9147 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9148 I40E_INSET_DMAC | I40E_INSET_SMAC |
9149 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9150 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9151 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9152 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9153 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9154 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9155 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
9156 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9157 I40E_INSET_DMAC | I40E_INSET_SMAC |
9158 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9159 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9160 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9161 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9162 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9163 I40E_INSET_FLEX_PAYLOAD,
9164 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9165 I40E_INSET_DMAC | I40E_INSET_SMAC |
9166 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9167 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9168 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9169 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
9170 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
9171 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
9172 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9173 I40E_INSET_DMAC | I40E_INSET_SMAC |
9174 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9175 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9176 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9177 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9178 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9179 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
9180 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9181 I40E_INSET_DMAC | I40E_INSET_SMAC |
9182 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9183 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9184 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9185 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9186 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9187 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9188 I40E_INSET_FLEX_PAYLOAD,
9189 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9190 I40E_INSET_DMAC | I40E_INSET_SMAC |
9191 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9192 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9193 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9194 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9195 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9196 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9197 I40E_INSET_FLEX_PAYLOAD,
9198 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9199 I40E_INSET_DMAC | I40E_INSET_SMAC |
9200 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9201 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9202 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9203 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9204 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9205 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9206 I40E_INSET_FLEX_PAYLOAD,
9207 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9208 I40E_INSET_DMAC | I40E_INSET_SMAC |
9209 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9210 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9211 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9212 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9213 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9214 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9215 I40E_INSET_FLEX_PAYLOAD,
9216 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9217 I40E_INSET_DMAC | I40E_INSET_SMAC |
9218 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9219 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9220 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9221 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9222 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9223 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9224 I40E_INSET_FLEX_PAYLOAD,
9225 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9226 I40E_INSET_DMAC | I40E_INSET_SMAC |
9227 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9228 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9229 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9230 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9231 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9232 I40E_INSET_FLEX_PAYLOAD,
9233 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9234 I40E_INSET_DMAC | I40E_INSET_SMAC |
9235 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9236 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9237 I40E_INSET_FLEX_PAYLOAD,
9241 * Flow director supports only fields defined in
9242 * union rte_eth_fdir_flow.
9244 static const uint64_t valid_fdir_inset_table[] = {
9245 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9246 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9247 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9248 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9249 I40E_INSET_IPV4_TTL,
9250 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9251 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9252 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9253 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9254 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9255 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9256 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9257 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9258 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9259 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9260 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9261 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9262 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9263 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9264 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9265 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9266 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9267 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9268 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9269 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9270 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9271 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9272 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9273 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9274 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9275 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9276 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9277 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9278 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9279 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9281 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9282 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9283 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9284 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9285 I40E_INSET_IPV4_TTL,
9286 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9287 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9288 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9289 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9290 I40E_INSET_IPV6_HOP_LIMIT,
9291 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9292 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9293 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9294 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9295 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9296 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9297 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9298 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9299 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9300 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9301 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9302 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9303 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9304 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9305 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9306 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9307 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9308 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9309 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9310 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9311 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9312 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9313 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9314 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9315 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9316 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9317 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9318 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9319 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9320 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9322 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9323 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9324 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9325 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9326 I40E_INSET_IPV6_HOP_LIMIT,
9327 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9328 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9329 I40E_INSET_LAST_ETHER_TYPE,
9332 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9334 if (filter == RTE_ETH_FILTER_HASH)
9335 valid = valid_hash_inset_table[pctype];
9337 valid = valid_fdir_inset_table[pctype];
9343 * Validate if the input set is allowed for a specific PCTYPE
9346 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9347 enum rte_filter_type filter, uint64_t inset)
9351 valid = i40e_get_valid_input_set(pctype, filter);
9352 if (inset & (~valid))
9358 /* default input set fields combination per pctype */
9360 i40e_get_default_input_set(uint16_t pctype)
9362 static const uint64_t default_inset_table[] = {
9363 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9364 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9365 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9366 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9367 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9368 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9369 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9370 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9371 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9372 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9373 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9374 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9375 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9376 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9377 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9378 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9379 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9380 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9381 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9382 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9384 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9385 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9386 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9387 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9388 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9389 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9390 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9391 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9392 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9393 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9394 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9395 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9396 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9397 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9398 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9399 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9400 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9401 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9402 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9403 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9404 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9405 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9407 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9408 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9409 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9410 I40E_INSET_LAST_ETHER_TYPE,
9413 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9416 return default_inset_table[pctype];
9420 * Parse the input set from index to logical bit masks
9423 i40e_parse_input_set(uint64_t *inset,
9424 enum i40e_filter_pctype pctype,
9425 enum rte_eth_input_set_field *field,
9431 static const struct {
9432 enum rte_eth_input_set_field field;
9434 } inset_convert_table[] = {
9435 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9436 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9437 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9438 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9439 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9440 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9441 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9442 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9443 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9444 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9445 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9446 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9447 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9448 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9449 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9450 I40E_INSET_IPV6_NEXT_HDR},
9451 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9452 I40E_INSET_IPV6_HOP_LIMIT},
9453 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9454 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9455 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9456 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9457 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9458 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9459 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9460 I40E_INSET_SCTP_VT},
9461 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9462 I40E_INSET_TUNNEL_DMAC},
9463 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9464 I40E_INSET_VLAN_TUNNEL},
9465 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9466 I40E_INSET_TUNNEL_ID},
9467 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9468 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9469 I40E_INSET_FLEX_PAYLOAD_W1},
9470 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9471 I40E_INSET_FLEX_PAYLOAD_W2},
9472 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9473 I40E_INSET_FLEX_PAYLOAD_W3},
9474 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9475 I40E_INSET_FLEX_PAYLOAD_W4},
9476 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9477 I40E_INSET_FLEX_PAYLOAD_W5},
9478 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9479 I40E_INSET_FLEX_PAYLOAD_W6},
9480 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9481 I40E_INSET_FLEX_PAYLOAD_W7},
9482 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9483 I40E_INSET_FLEX_PAYLOAD_W8},
9486 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9489 /* Only one item allowed for default or all */
9491 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9492 *inset = i40e_get_default_input_set(pctype);
9494 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9495 *inset = I40E_INSET_NONE;
9500 for (i = 0, *inset = 0; i < size; i++) {
9501 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9502 if (field[i] == inset_convert_table[j].field) {
9503 *inset |= inset_convert_table[j].inset;
9508 /* It contains unsupported input set, return immediately */
9509 if (j == RTE_DIM(inset_convert_table))
9517 * Translate the input set from bit masks to register aware bit masks
9521 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9531 static const struct inset_map inset_map_common[] = {
9532 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9533 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9534 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9535 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9536 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9537 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9538 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9539 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9540 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9541 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9542 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9543 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9544 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9545 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9546 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9547 {I40E_INSET_TUNNEL_DMAC,
9548 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9549 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9550 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9551 {I40E_INSET_TUNNEL_SRC_PORT,
9552 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9553 {I40E_INSET_TUNNEL_DST_PORT,
9554 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9555 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9556 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9557 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9558 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9559 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9560 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9561 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9562 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9563 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9566 /* some different registers map in x722*/
9567 static const struct inset_map inset_map_diff_x722[] = {
9568 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9569 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9570 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9571 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9574 static const struct inset_map inset_map_diff_not_x722[] = {
9575 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9576 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9577 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9578 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9584 /* Translate input set to register aware inset */
9585 if (type == I40E_MAC_X722) {
9586 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9587 if (input & inset_map_diff_x722[i].inset)
9588 val |= inset_map_diff_x722[i].inset_reg;
9591 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9592 if (input & inset_map_diff_not_x722[i].inset)
9593 val |= inset_map_diff_not_x722[i].inset_reg;
9597 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9598 if (input & inset_map_common[i].inset)
9599 val |= inset_map_common[i].inset_reg;
9606 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9609 uint64_t inset_need_mask = inset;
9611 static const struct {
9614 } inset_mask_map[] = {
9615 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9616 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9617 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9618 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9619 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9620 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9621 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9622 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9625 if (!inset || !mask || !nb_elem)
9628 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9629 /* Clear the inset bit, if no MASK is required,
9630 * for example proto + ttl
9632 if ((inset & inset_mask_map[i].inset) ==
9633 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9634 inset_need_mask &= ~inset_mask_map[i].inset;
9635 if (!inset_need_mask)
9638 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9639 if ((inset_need_mask & inset_mask_map[i].inset) ==
9640 inset_mask_map[i].inset) {
9641 if (idx >= nb_elem) {
9642 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9645 mask[idx] = inset_mask_map[i].mask;
9654 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9656 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9658 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9660 i40e_write_rx_ctl(hw, addr, val);
9661 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9662 (uint32_t)i40e_read_rx_ctl(hw, addr));
9666 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9668 uint32_t reg = i40e_read_rx_ctl(hw, addr);
9669 struct rte_eth_dev *dev;
9671 dev = ((struct i40e_adapter *)hw->back)->eth_dev;
9673 i40e_write_rx_ctl(hw, addr, val);
9674 PMD_DRV_LOG(WARNING,
9675 "i40e device %s changed global register [0x%08x]."
9676 " original: 0x%08x, new: 0x%08x",
9677 dev->device->name, addr, reg,
9678 (uint32_t)i40e_read_rx_ctl(hw, addr));
9683 i40e_filter_input_set_init(struct i40e_pf *pf)
9685 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9686 enum i40e_filter_pctype pctype;
9687 uint64_t input_set, inset_reg;
9688 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9692 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9693 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9694 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9696 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9699 input_set = i40e_get_default_input_set(pctype);
9701 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9702 I40E_INSET_MASK_NUM_REG);
9705 if (pf->support_multi_driver && num > 0) {
9706 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9709 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9712 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9713 (uint32_t)(inset_reg & UINT32_MAX));
9714 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9715 (uint32_t)((inset_reg >>
9716 I40E_32_BIT_WIDTH) & UINT32_MAX));
9717 if (!pf->support_multi_driver) {
9718 i40e_check_write_global_reg(hw,
9719 I40E_GLQF_HASH_INSET(0, pctype),
9720 (uint32_t)(inset_reg & UINT32_MAX));
9721 i40e_check_write_global_reg(hw,
9722 I40E_GLQF_HASH_INSET(1, pctype),
9723 (uint32_t)((inset_reg >>
9724 I40E_32_BIT_WIDTH) & UINT32_MAX));
9726 for (i = 0; i < num; i++) {
9727 i40e_check_write_global_reg(hw,
9728 I40E_GLQF_FD_MSK(i, pctype),
9730 i40e_check_write_global_reg(hw,
9731 I40E_GLQF_HASH_MSK(i, pctype),
9734 /*clear unused mask registers of the pctype */
9735 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9736 i40e_check_write_global_reg(hw,
9737 I40E_GLQF_FD_MSK(i, pctype),
9739 i40e_check_write_global_reg(hw,
9740 I40E_GLQF_HASH_MSK(i, pctype),
9744 PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9746 I40E_WRITE_FLUSH(hw);
9748 /* store the default input set */
9749 if (!pf->support_multi_driver)
9750 pf->hash_input_set[pctype] = input_set;
9751 pf->fdir.input_set[pctype] = input_set;
9756 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9757 struct rte_eth_input_set_conf *conf)
9759 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9760 enum i40e_filter_pctype pctype;
9761 uint64_t input_set, inset_reg = 0;
9762 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9766 PMD_DRV_LOG(ERR, "Invalid pointer");
9769 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9770 conf->op != RTE_ETH_INPUT_SET_ADD) {
9771 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9775 if (pf->support_multi_driver) {
9776 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9780 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9781 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9782 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9786 if (hw->mac.type == I40E_MAC_X722) {
9787 /* get translated pctype value in fd pctype register */
9788 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9789 I40E_GLQF_FD_PCTYPES((int)pctype));
9792 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9795 PMD_DRV_LOG(ERR, "Failed to parse input set");
9799 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9800 /* get inset value in register */
9801 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9802 inset_reg <<= I40E_32_BIT_WIDTH;
9803 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9804 input_set |= pf->hash_input_set[pctype];
9806 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9807 I40E_INSET_MASK_NUM_REG);
9811 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9813 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9814 (uint32_t)(inset_reg & UINT32_MAX));
9815 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9816 (uint32_t)((inset_reg >>
9817 I40E_32_BIT_WIDTH) & UINT32_MAX));
9819 for (i = 0; i < num; i++)
9820 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9822 /*clear unused mask registers of the pctype */
9823 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9824 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9826 I40E_WRITE_FLUSH(hw);
9828 pf->hash_input_set[pctype] = input_set;
9833 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9834 struct rte_eth_input_set_conf *conf)
9836 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9837 enum i40e_filter_pctype pctype;
9838 uint64_t input_set, inset_reg = 0;
9839 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9843 PMD_DRV_LOG(ERR, "Invalid pointer");
9846 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9847 conf->op != RTE_ETH_INPUT_SET_ADD) {
9848 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9852 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9854 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9855 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9859 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9862 PMD_DRV_LOG(ERR, "Failed to parse input set");
9866 /* get inset value in register */
9867 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9868 inset_reg <<= I40E_32_BIT_WIDTH;
9869 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9871 /* Can not change the inset reg for flex payload for fdir,
9872 * it is done by writing I40E_PRTQF_FD_FLXINSET
9873 * in i40e_set_flex_mask_on_pctype.
9875 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9876 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9878 input_set |= pf->fdir.input_set[pctype];
9879 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9880 I40E_INSET_MASK_NUM_REG);
9883 if (pf->support_multi_driver && num > 0) {
9884 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9888 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9890 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9891 (uint32_t)(inset_reg & UINT32_MAX));
9892 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9893 (uint32_t)((inset_reg >>
9894 I40E_32_BIT_WIDTH) & UINT32_MAX));
9896 if (!pf->support_multi_driver) {
9897 for (i = 0; i < num; i++)
9898 i40e_check_write_global_reg(hw,
9899 I40E_GLQF_FD_MSK(i, pctype),
9901 /*clear unused mask registers of the pctype */
9902 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9903 i40e_check_write_global_reg(hw,
9904 I40E_GLQF_FD_MSK(i, pctype),
9907 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9909 I40E_WRITE_FLUSH(hw);
9911 pf->fdir.input_set[pctype] = input_set;
9916 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9921 PMD_DRV_LOG(ERR, "Invalid pointer");
9925 switch (info->info_type) {
9926 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9927 i40e_get_symmetric_hash_enable_per_port(hw,
9928 &(info->info.enable));
9930 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9931 ret = i40e_get_hash_filter_global_config(hw,
9932 &(info->info.global_conf));
9935 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9945 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9950 PMD_DRV_LOG(ERR, "Invalid pointer");
9954 switch (info->info_type) {
9955 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9956 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9958 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9959 ret = i40e_set_hash_filter_global_config(hw,
9960 &(info->info.global_conf));
9962 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9963 ret = i40e_hash_filter_inset_select(hw,
9964 &(info->info.input_set_conf));
9968 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9977 /* Operations for hash function */
9979 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9980 enum rte_filter_op filter_op,
9983 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9986 switch (filter_op) {
9987 case RTE_ETH_FILTER_NOP:
9989 case RTE_ETH_FILTER_GET:
9990 ret = i40e_hash_filter_get(hw,
9991 (struct rte_eth_hash_filter_info *)arg);
9993 case RTE_ETH_FILTER_SET:
9994 ret = i40e_hash_filter_set(hw,
9995 (struct rte_eth_hash_filter_info *)arg);
9998 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
10007 /* Convert ethertype filter structure */
10009 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
10010 struct i40e_ethertype_filter *filter)
10012 rte_memcpy(&filter->input.mac_addr, &input->mac_addr,
10013 RTE_ETHER_ADDR_LEN);
10014 filter->input.ether_type = input->ether_type;
10015 filter->flags = input->flags;
10016 filter->queue = input->queue;
10021 /* Check if there exists the ehtertype filter */
10022 struct i40e_ethertype_filter *
10023 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
10024 const struct i40e_ethertype_filter_input *input)
10028 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
10032 return ethertype_rule->hash_map[ret];
10035 /* Add ethertype filter in SW list */
10037 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
10038 struct i40e_ethertype_filter *filter)
10040 struct i40e_ethertype_rule *rule = &pf->ethertype;
10043 ret = rte_hash_add_key(rule->hash_table, &filter->input);
10046 "Failed to insert ethertype filter"
10047 " to hash table %d!",
10051 rule->hash_map[ret] = filter;
10053 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
10058 /* Delete ethertype filter in SW list */
10060 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
10061 struct i40e_ethertype_filter_input *input)
10063 struct i40e_ethertype_rule *rule = &pf->ethertype;
10064 struct i40e_ethertype_filter *filter;
10067 ret = rte_hash_del_key(rule->hash_table, input);
10070 "Failed to delete ethertype filter"
10071 " to hash table %d!",
10075 filter = rule->hash_map[ret];
10076 rule->hash_map[ret] = NULL;
10078 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
10085 * Configure ethertype filter, which can director packet by filtering
10086 * with mac address and ether_type or only ether_type
10089 i40e_ethertype_filter_set(struct i40e_pf *pf,
10090 struct rte_eth_ethertype_filter *filter,
10093 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10094 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
10095 struct i40e_ethertype_filter *ethertype_filter, *node;
10096 struct i40e_ethertype_filter check_filter;
10097 struct i40e_control_filter_stats stats;
10098 uint16_t flags = 0;
10101 if (filter->queue >= pf->dev_data->nb_rx_queues) {
10102 PMD_DRV_LOG(ERR, "Invalid queue ID");
10105 if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
10106 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
10108 "unsupported ether_type(0x%04x) in control packet filter.",
10109 filter->ether_type);
10112 if (filter->ether_type == RTE_ETHER_TYPE_VLAN)
10113 PMD_DRV_LOG(WARNING,
10114 "filter vlan ether_type in first tag is not supported.");
10116 /* Check if there is the filter in SW list */
10117 memset(&check_filter, 0, sizeof(check_filter));
10118 i40e_ethertype_filter_convert(filter, &check_filter);
10119 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
10120 &check_filter.input);
10122 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
10126 if (!add && !node) {
10127 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
10131 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
10132 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10133 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
10134 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10135 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10137 memset(&stats, 0, sizeof(stats));
10138 ret = i40e_aq_add_rem_control_packet_filter(hw,
10139 filter->mac_addr.addr_bytes,
10140 filter->ether_type, flags,
10141 pf->main_vsi->seid,
10142 filter->queue, add, &stats, NULL);
10145 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
10146 ret, stats.mac_etype_used, stats.etype_used,
10147 stats.mac_etype_free, stats.etype_free);
10151 /* Add or delete a filter in SW list */
10153 ethertype_filter = rte_zmalloc("ethertype_filter",
10154 sizeof(*ethertype_filter), 0);
10155 if (ethertype_filter == NULL) {
10156 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
10160 rte_memcpy(ethertype_filter, &check_filter,
10161 sizeof(check_filter));
10162 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
10164 rte_free(ethertype_filter);
10166 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
10173 * Handle operations for ethertype filter.
10176 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
10177 enum rte_filter_op filter_op,
10180 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10183 if (filter_op == RTE_ETH_FILTER_NOP)
10187 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
10192 switch (filter_op) {
10193 case RTE_ETH_FILTER_ADD:
10194 ret = i40e_ethertype_filter_set(pf,
10195 (struct rte_eth_ethertype_filter *)arg,
10198 case RTE_ETH_FILTER_DELETE:
10199 ret = i40e_ethertype_filter_set(pf,
10200 (struct rte_eth_ethertype_filter *)arg,
10204 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
10212 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
10213 enum rte_filter_type filter_type,
10214 enum rte_filter_op filter_op,
10222 switch (filter_type) {
10223 case RTE_ETH_FILTER_NONE:
10224 /* For global configuration */
10225 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
10227 case RTE_ETH_FILTER_HASH:
10228 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
10230 case RTE_ETH_FILTER_MACVLAN:
10231 ret = i40e_mac_filter_handle(dev, filter_op, arg);
10233 case RTE_ETH_FILTER_ETHERTYPE:
10234 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
10236 case RTE_ETH_FILTER_TUNNEL:
10237 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
10239 case RTE_ETH_FILTER_FDIR:
10240 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
10242 case RTE_ETH_FILTER_GENERIC:
10243 if (filter_op != RTE_ETH_FILTER_GET)
10245 *(const void **)arg = &i40e_flow_ops;
10248 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
10258 * Check and enable Extended Tag.
10259 * Enabling Extended Tag is important for 40G performance.
10262 i40e_enable_extended_tag(struct rte_eth_dev *dev)
10264 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10268 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10271 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10275 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
10276 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
10281 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10284 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10288 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
10289 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
10292 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
10293 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
10296 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
10303 * As some registers wouldn't be reset unless a global hardware reset,
10304 * hardware initialization is needed to put those registers into an
10305 * expected initial state.
10308 i40e_hw_init(struct rte_eth_dev *dev)
10310 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10312 i40e_enable_extended_tag(dev);
10314 /* clear the PF Queue Filter control register */
10315 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
10317 /* Disable symmetric hash per port */
10318 i40e_set_symmetric_hash_enable_per_port(hw, 0);
10322 * For X722 it is possible to have multiple pctypes mapped to the same flowtype
10323 * however this function will return only one highest pctype index,
10324 * which is not quite correct. This is known problem of i40e driver
10325 * and needs to be fixed later.
10327 enum i40e_filter_pctype
10328 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
10331 uint64_t pctype_mask;
10333 if (flow_type < I40E_FLOW_TYPE_MAX) {
10334 pctype_mask = adapter->pctypes_tbl[flow_type];
10335 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
10336 if (pctype_mask & (1ULL << i))
10337 return (enum i40e_filter_pctype)i;
10340 return I40E_FILTER_PCTYPE_INVALID;
10344 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
10345 enum i40e_filter_pctype pctype)
10348 uint64_t pctype_mask = 1ULL << pctype;
10350 for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
10352 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
10356 return RTE_ETH_FLOW_UNKNOWN;
10360 * On X710, performance number is far from the expectation on recent firmware
10361 * versions; on XL710, performance number is also far from the expectation on
10362 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10363 * mode is enabled and port MAC address is equal to the packet destination MAC
10364 * address. The fix for this issue may not be integrated in the following
10365 * firmware version. So the workaround in software driver is needed. It needs
10366 * to modify the initial values of 3 internal only registers for both X710 and
10367 * XL710. Note that the values for X710 or XL710 could be different, and the
10368 * workaround can be removed when it is fixed in firmware in the future.
10371 /* For both X710 and XL710 */
10372 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1 0x10000200
10373 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x203F0200
10374 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
10376 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10377 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
10380 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10381 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10384 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
10386 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
10387 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
10390 * GL_SWR_PM_UP_THR:
10391 * The value is not impacted from the link speed, its value is set according
10392 * to the total number of ports for a better pipe-monitor configuration.
10395 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10397 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10398 .device_id = (dev), \
10399 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10401 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10402 .device_id = (dev), \
10403 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10405 static const struct {
10406 uint16_t device_id;
10408 } swr_pm_table[] = {
10409 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10410 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10411 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10412 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10414 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10415 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10416 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10417 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10418 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10419 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10420 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10424 if (value == NULL) {
10425 PMD_DRV_LOG(ERR, "value is NULL");
10429 for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10430 if (hw->device_id == swr_pm_table[i].device_id) {
10431 *value = swr_pm_table[i].val;
10433 PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10435 hw->device_id, *value);
10444 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10446 enum i40e_status_code status;
10447 struct i40e_aq_get_phy_abilities_resp phy_ab;
10448 int ret = -ENOTSUP;
10451 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10455 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10458 rte_delay_us(100000);
10460 status = i40e_aq_get_phy_capabilities(hw, false,
10461 true, &phy_ab, NULL);
10469 i40e_configure_registers(struct i40e_hw *hw)
10475 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10476 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10477 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10483 for (i = 0; i < RTE_DIM(reg_table); i++) {
10484 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10485 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10487 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10488 else /* For X710/XL710/XXV710 */
10489 if (hw->aq.fw_maj_ver < 6)
10491 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10494 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10497 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10498 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10500 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10501 else /* For X710/XL710/XXV710 */
10503 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10506 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10509 if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10510 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10511 "GL_SWR_PM_UP_THR value fixup",
10516 reg_table[i].val = cfg_val;
10519 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10522 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10523 reg_table[i].addr);
10526 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10527 reg_table[i].addr, reg);
10528 if (reg == reg_table[i].val)
10531 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10532 reg_table[i].val, NULL);
10535 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10536 reg_table[i].val, reg_table[i].addr);
10539 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10540 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10544 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
10545 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
10546 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
10547 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10549 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10554 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10555 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10559 /* Configure for double VLAN RX stripping */
10560 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10561 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10562 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10563 ret = i40e_aq_debug_write_register(hw,
10564 I40E_VSI_TSR(vsi->vsi_id),
10567 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10569 return I40E_ERR_CONFIG;
10573 /* Configure for double VLAN TX insertion */
10574 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10575 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10576 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10577 ret = i40e_aq_debug_write_register(hw,
10578 I40E_VSI_L2TAGSTXVALID(
10579 vsi->vsi_id), reg, NULL);
10582 "Failed to update VSI_L2TAGSTXVALID[%d]",
10584 return I40E_ERR_CONFIG;
10592 * i40e_aq_add_mirror_rule
10593 * @hw: pointer to the hardware structure
10594 * @seid: VEB seid to add mirror rule to
10595 * @dst_id: destination vsi seid
10596 * @entries: Buffer which contains the entities to be mirrored
10597 * @count: number of entities contained in the buffer
10598 * @rule_id:the rule_id of the rule to be added
10600 * Add a mirror rule for a given veb.
10603 static enum i40e_status_code
10604 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10605 uint16_t seid, uint16_t dst_id,
10606 uint16_t rule_type, uint16_t *entries,
10607 uint16_t count, uint16_t *rule_id)
10609 struct i40e_aq_desc desc;
10610 struct i40e_aqc_add_delete_mirror_rule cmd;
10611 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10612 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10615 enum i40e_status_code status;
10617 i40e_fill_default_direct_cmd_desc(&desc,
10618 i40e_aqc_opc_add_mirror_rule);
10619 memset(&cmd, 0, sizeof(cmd));
10621 buff_len = sizeof(uint16_t) * count;
10622 desc.datalen = rte_cpu_to_le_16(buff_len);
10624 desc.flags |= rte_cpu_to_le_16(
10625 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10626 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10627 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10628 cmd.num_entries = rte_cpu_to_le_16(count);
10629 cmd.seid = rte_cpu_to_le_16(seid);
10630 cmd.destination = rte_cpu_to_le_16(dst_id);
10632 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10633 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10635 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10636 hw->aq.asq_last_status, resp->rule_id,
10637 resp->mirror_rules_used, resp->mirror_rules_free);
10638 *rule_id = rte_le_to_cpu_16(resp->rule_id);
10644 * i40e_aq_del_mirror_rule
10645 * @hw: pointer to the hardware structure
10646 * @seid: VEB seid to add mirror rule to
10647 * @entries: Buffer which contains the entities to be mirrored
10648 * @count: number of entities contained in the buffer
10649 * @rule_id:the rule_id of the rule to be delete
10651 * Delete a mirror rule for a given veb.
10654 static enum i40e_status_code
10655 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10656 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10657 uint16_t count, uint16_t rule_id)
10659 struct i40e_aq_desc desc;
10660 struct i40e_aqc_add_delete_mirror_rule cmd;
10661 uint16_t buff_len = 0;
10662 enum i40e_status_code status;
10665 i40e_fill_default_direct_cmd_desc(&desc,
10666 i40e_aqc_opc_delete_mirror_rule);
10667 memset(&cmd, 0, sizeof(cmd));
10668 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10669 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10671 cmd.num_entries = count;
10672 buff_len = sizeof(uint16_t) * count;
10673 desc.datalen = rte_cpu_to_le_16(buff_len);
10674 buff = (void *)entries;
10676 /* rule id is filled in destination field for deleting mirror rule */
10677 cmd.destination = rte_cpu_to_le_16(rule_id);
10679 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10680 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10681 cmd.seid = rte_cpu_to_le_16(seid);
10683 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10684 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10690 * i40e_mirror_rule_set
10691 * @dev: pointer to the hardware structure
10692 * @mirror_conf: mirror rule info
10693 * @sw_id: mirror rule's sw_id
10694 * @on: enable/disable
10696 * set a mirror rule.
10700 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10701 struct rte_eth_mirror_conf *mirror_conf,
10702 uint8_t sw_id, uint8_t on)
10704 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10705 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10706 struct i40e_mirror_rule *it, *mirr_rule = NULL;
10707 struct i40e_mirror_rule *parent = NULL;
10708 uint16_t seid, dst_seid, rule_id;
10712 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10714 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10716 "mirror rule can not be configured without veb or vfs.");
10719 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10720 PMD_DRV_LOG(ERR, "mirror table is full.");
10723 if (mirror_conf->dst_pool > pf->vf_num) {
10724 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10725 mirror_conf->dst_pool);
10729 seid = pf->main_vsi->veb->seid;
10731 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10732 if (sw_id <= it->index) {
10738 if (mirr_rule && sw_id == mirr_rule->index) {
10740 PMD_DRV_LOG(ERR, "mirror rule exists.");
10743 ret = i40e_aq_del_mirror_rule(hw, seid,
10744 mirr_rule->rule_type,
10745 mirr_rule->entries,
10746 mirr_rule->num_entries, mirr_rule->id);
10749 "failed to remove mirror rule: ret = %d, aq_err = %d.",
10750 ret, hw->aq.asq_last_status);
10753 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10754 rte_free(mirr_rule);
10755 pf->nb_mirror_rule--;
10759 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10763 mirr_rule = rte_zmalloc("i40e_mirror_rule",
10764 sizeof(struct i40e_mirror_rule) , 0);
10766 PMD_DRV_LOG(ERR, "failed to allocate memory");
10767 return I40E_ERR_NO_MEMORY;
10769 switch (mirror_conf->rule_type) {
10770 case ETH_MIRROR_VLAN:
10771 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10772 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10773 mirr_rule->entries[j] =
10774 mirror_conf->vlan.vlan_id[i];
10779 PMD_DRV_LOG(ERR, "vlan is not specified.");
10780 rte_free(mirr_rule);
10783 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10785 case ETH_MIRROR_VIRTUAL_POOL_UP:
10786 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10787 /* check if the specified pool bit is out of range */
10788 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10789 PMD_DRV_LOG(ERR, "pool mask is out of range.");
10790 rte_free(mirr_rule);
10793 for (i = 0, j = 0; i < pf->vf_num; i++) {
10794 if (mirror_conf->pool_mask & (1ULL << i)) {
10795 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10799 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10800 /* add pf vsi to entries */
10801 mirr_rule->entries[j] = pf->main_vsi_seid;
10805 PMD_DRV_LOG(ERR, "pool is not specified.");
10806 rte_free(mirr_rule);
10809 /* egress and ingress in aq commands means from switch but not port */
10810 mirr_rule->rule_type =
10811 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10812 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10813 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10815 case ETH_MIRROR_UPLINK_PORT:
10816 /* egress and ingress in aq commands means from switch but not port*/
10817 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10819 case ETH_MIRROR_DOWNLINK_PORT:
10820 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10823 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10824 mirror_conf->rule_type);
10825 rte_free(mirr_rule);
10829 /* If the dst_pool is equal to vf_num, consider it as PF */
10830 if (mirror_conf->dst_pool == pf->vf_num)
10831 dst_seid = pf->main_vsi_seid;
10833 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10835 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10836 mirr_rule->rule_type, mirr_rule->entries,
10840 "failed to add mirror rule: ret = %d, aq_err = %d.",
10841 ret, hw->aq.asq_last_status);
10842 rte_free(mirr_rule);
10846 mirr_rule->index = sw_id;
10847 mirr_rule->num_entries = j;
10848 mirr_rule->id = rule_id;
10849 mirr_rule->dst_vsi_seid = dst_seid;
10852 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10854 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10856 pf->nb_mirror_rule++;
10861 * i40e_mirror_rule_reset
10862 * @dev: pointer to the device
10863 * @sw_id: mirror rule's sw_id
10865 * reset a mirror rule.
10869 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10871 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10872 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10873 struct i40e_mirror_rule *it, *mirr_rule = NULL;
10877 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10879 seid = pf->main_vsi->veb->seid;
10881 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10882 if (sw_id == it->index) {
10888 ret = i40e_aq_del_mirror_rule(hw, seid,
10889 mirr_rule->rule_type,
10890 mirr_rule->entries,
10891 mirr_rule->num_entries, mirr_rule->id);
10894 "failed to remove mirror rule: status = %d, aq_err = %d.",
10895 ret, hw->aq.asq_last_status);
10898 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10899 rte_free(mirr_rule);
10900 pf->nb_mirror_rule--;
10902 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10909 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10911 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10912 uint64_t systim_cycles;
10914 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10915 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10918 return systim_cycles;
10922 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10924 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10925 uint64_t rx_tstamp;
10927 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10928 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10935 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10937 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10938 uint64_t tx_tstamp;
10940 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10941 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10948 i40e_start_timecounters(struct rte_eth_dev *dev)
10950 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10951 struct i40e_adapter *adapter = dev->data->dev_private;
10952 struct rte_eth_link link;
10953 uint32_t tsync_inc_l;
10954 uint32_t tsync_inc_h;
10956 /* Get current link speed. */
10957 i40e_dev_link_update(dev, 1);
10958 rte_eth_linkstatus_get(dev, &link);
10960 switch (link.link_speed) {
10961 case ETH_SPEED_NUM_40G:
10962 case ETH_SPEED_NUM_25G:
10963 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10964 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10966 case ETH_SPEED_NUM_10G:
10967 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10968 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10970 case ETH_SPEED_NUM_1G:
10971 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10972 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10979 /* Set the timesync increment value. */
10980 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10981 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10983 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10984 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10985 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10987 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10988 adapter->systime_tc.cc_shift = 0;
10989 adapter->systime_tc.nsec_mask = 0;
10991 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10992 adapter->rx_tstamp_tc.cc_shift = 0;
10993 adapter->rx_tstamp_tc.nsec_mask = 0;
10995 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10996 adapter->tx_tstamp_tc.cc_shift = 0;
10997 adapter->tx_tstamp_tc.nsec_mask = 0;
11001 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
11003 struct i40e_adapter *adapter = dev->data->dev_private;
11005 adapter->systime_tc.nsec += delta;
11006 adapter->rx_tstamp_tc.nsec += delta;
11007 adapter->tx_tstamp_tc.nsec += delta;
11013 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
11016 struct i40e_adapter *adapter = dev->data->dev_private;
11018 ns = rte_timespec_to_ns(ts);
11020 /* Set the timecounters to a new value. */
11021 adapter->systime_tc.nsec = ns;
11022 adapter->rx_tstamp_tc.nsec = ns;
11023 adapter->tx_tstamp_tc.nsec = ns;
11029 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
11031 uint64_t ns, systime_cycles;
11032 struct i40e_adapter *adapter = dev->data->dev_private;
11034 systime_cycles = i40e_read_systime_cyclecounter(dev);
11035 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
11036 *ts = rte_ns_to_timespec(ns);
11042 i40e_timesync_enable(struct rte_eth_dev *dev)
11044 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11045 uint32_t tsync_ctl_l;
11046 uint32_t tsync_ctl_h;
11048 /* Stop the timesync system time. */
11049 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
11050 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11051 /* Reset the timesync system time value. */
11052 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
11053 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
11055 i40e_start_timecounters(dev);
11057 /* Clear timesync registers. */
11058 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11059 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
11060 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
11061 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
11062 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
11063 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
11065 /* Enable timestamping of PTP packets. */
11066 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
11067 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
11069 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
11070 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
11071 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
11073 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
11074 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
11080 i40e_timesync_disable(struct rte_eth_dev *dev)
11082 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11083 uint32_t tsync_ctl_l;
11084 uint32_t tsync_ctl_h;
11086 /* Disable timestamping of transmitted PTP packets. */
11087 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
11088 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
11090 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
11091 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
11093 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
11094 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
11096 /* Reset the timesync increment value. */
11097 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
11098 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11104 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
11105 struct timespec *timestamp, uint32_t flags)
11107 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11108 struct i40e_adapter *adapter = dev->data->dev_private;
11109 uint32_t sync_status;
11110 uint32_t index = flags & 0x03;
11111 uint64_t rx_tstamp_cycles;
11114 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
11115 if ((sync_status & (1 << index)) == 0)
11118 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
11119 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
11120 *timestamp = rte_ns_to_timespec(ns);
11126 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
11127 struct timespec *timestamp)
11129 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11130 struct i40e_adapter *adapter = dev->data->dev_private;
11131 uint32_t sync_status;
11132 uint64_t tx_tstamp_cycles;
11135 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11136 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
11139 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
11140 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
11141 *timestamp = rte_ns_to_timespec(ns);
11147 * i40e_parse_dcb_configure - parse dcb configure from user
11148 * @dev: the device being configured
11149 * @dcb_cfg: pointer of the result of parse
11150 * @*tc_map: bit map of enabled traffic classes
11152 * Returns 0 on success, negative value on failure
11155 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
11156 struct i40e_dcbx_config *dcb_cfg,
11159 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
11160 uint8_t i, tc_bw, bw_lf;
11162 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
11164 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
11165 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
11166 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
11170 /* assume each tc has the same bw */
11171 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
11172 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11173 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
11174 /* to ensure the sum of tcbw is equal to 100 */
11175 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
11176 for (i = 0; i < bw_lf; i++)
11177 dcb_cfg->etscfg.tcbwtable[i]++;
11179 /* assume each tc has the same Transmission Selection Algorithm */
11180 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11181 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
11183 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11184 dcb_cfg->etscfg.prioritytable[i] =
11185 dcb_rx_conf->dcb_tc[i];
11187 /* FW needs one App to configure HW */
11188 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
11189 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
11190 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
11191 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
11193 if (dcb_rx_conf->nb_tcs == 0)
11194 *tc_map = 1; /* tc0 only */
11196 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
11198 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
11199 dcb_cfg->pfc.willing = 0;
11200 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
11201 dcb_cfg->pfc.pfcenable = *tc_map;
11207 static enum i40e_status_code
11208 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
11209 struct i40e_aqc_vsi_properties_data *info,
11210 uint8_t enabled_tcmap)
11212 enum i40e_status_code ret;
11213 int i, total_tc = 0;
11214 uint16_t qpnum_per_tc, bsf, qp_idx;
11215 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
11216 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
11217 uint16_t used_queues;
11219 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
11220 if (ret != I40E_SUCCESS)
11223 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11224 if (enabled_tcmap & (1 << i))
11229 vsi->enabled_tc = enabled_tcmap;
11231 /* different VSI has different queues assigned */
11232 if (vsi->type == I40E_VSI_MAIN)
11233 used_queues = dev_data->nb_rx_queues -
11234 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11235 else if (vsi->type == I40E_VSI_VMDQ2)
11236 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11238 PMD_INIT_LOG(ERR, "unsupported VSI type.");
11239 return I40E_ERR_NO_AVAILABLE_VSI;
11242 qpnum_per_tc = used_queues / total_tc;
11243 /* Number of queues per enabled TC */
11244 if (qpnum_per_tc == 0) {
11245 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
11246 return I40E_ERR_INVALID_QP_ID;
11248 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
11249 I40E_MAX_Q_PER_TC);
11250 bsf = rte_bsf32(qpnum_per_tc);
11253 * Configure TC and queue mapping parameters, for enabled TC,
11254 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
11255 * default queue will serve it.
11258 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11259 if (vsi->enabled_tc & (1 << i)) {
11260 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
11261 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
11262 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
11263 qp_idx += qpnum_per_tc;
11265 info->tc_mapping[i] = 0;
11268 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
11269 if (vsi->type == I40E_VSI_SRIOV) {
11270 info->mapping_flags |=
11271 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
11272 for (i = 0; i < vsi->nb_qps; i++)
11273 info->queue_mapping[i] =
11274 rte_cpu_to_le_16(vsi->base_queue + i);
11276 info->mapping_flags |=
11277 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
11278 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
11280 info->valid_sections |=
11281 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
11283 return I40E_SUCCESS;
11287 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
11288 * @veb: VEB to be configured
11289 * @tc_map: enabled TC bitmap
11291 * Returns 0 on success, negative value on failure
11293 static enum i40e_status_code
11294 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
11296 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
11297 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
11298 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
11299 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
11300 enum i40e_status_code ret = I40E_SUCCESS;
11304 /* Check if enabled_tc is same as existing or new TCs */
11305 if (veb->enabled_tc == tc_map)
11308 /* configure tc bandwidth */
11309 memset(&veb_bw, 0, sizeof(veb_bw));
11310 veb_bw.tc_valid_bits = tc_map;
11311 /* Enable ETS TCs with equal BW Share for now across all VSIs */
11312 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11313 if (tc_map & BIT_ULL(i))
11314 veb_bw.tc_bw_share_credits[i] = 1;
11316 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
11320 "AQ command Config switch_comp BW allocation per TC failed = %d",
11321 hw->aq.asq_last_status);
11325 memset(&ets_query, 0, sizeof(ets_query));
11326 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
11328 if (ret != I40E_SUCCESS) {
11330 "Failed to get switch_comp ETS configuration %u",
11331 hw->aq.asq_last_status);
11334 memset(&bw_query, 0, sizeof(bw_query));
11335 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
11337 if (ret != I40E_SUCCESS) {
11339 "Failed to get switch_comp bandwidth configuration %u",
11340 hw->aq.asq_last_status);
11344 /* store and print out BW info */
11345 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
11346 veb->bw_info.bw_max = ets_query.tc_bw_max;
11347 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
11348 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
11349 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
11350 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
11351 I40E_16_BIT_WIDTH);
11352 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11353 veb->bw_info.bw_ets_share_credits[i] =
11354 bw_query.tc_bw_share_credits[i];
11355 veb->bw_info.bw_ets_credits[i] =
11356 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
11357 /* 4 bits per TC, 4th bit is reserved */
11358 veb->bw_info.bw_ets_max[i] =
11359 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
11360 RTE_LEN2MASK(3, uint8_t));
11361 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
11362 veb->bw_info.bw_ets_share_credits[i]);
11363 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11364 veb->bw_info.bw_ets_credits[i]);
11365 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11366 veb->bw_info.bw_ets_max[i]);
11369 veb->enabled_tc = tc_map;
11376 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11377 * @vsi: VSI to be configured
11378 * @tc_map: enabled TC bitmap
11380 * Returns 0 on success, negative value on failure
11382 static enum i40e_status_code
11383 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11385 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11386 struct i40e_vsi_context ctxt;
11387 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11388 enum i40e_status_code ret = I40E_SUCCESS;
11391 /* Check if enabled_tc is same as existing or new TCs */
11392 if (vsi->enabled_tc == tc_map)
11395 /* configure tc bandwidth */
11396 memset(&bw_data, 0, sizeof(bw_data));
11397 bw_data.tc_valid_bits = tc_map;
11398 /* Enable ETS TCs with equal BW Share for now across all VSIs */
11399 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11400 if (tc_map & BIT_ULL(i))
11401 bw_data.tc_bw_credits[i] = 1;
11403 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11406 "AQ command Config VSI BW allocation per TC failed = %d",
11407 hw->aq.asq_last_status);
11410 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11411 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11413 /* Update Queue Pairs Mapping for currently enabled UPs */
11414 ctxt.seid = vsi->seid;
11415 ctxt.pf_num = hw->pf_id;
11417 ctxt.uplink_seid = vsi->uplink_seid;
11418 ctxt.info = vsi->info;
11420 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11424 /* Update the VSI after updating the VSI queue-mapping information */
11425 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11427 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11428 hw->aq.asq_last_status);
11431 /* update the local VSI info with updated queue map */
11432 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11433 sizeof(vsi->info.tc_mapping));
11434 rte_memcpy(&vsi->info.queue_mapping,
11435 &ctxt.info.queue_mapping,
11436 sizeof(vsi->info.queue_mapping));
11437 vsi->info.mapping_flags = ctxt.info.mapping_flags;
11438 vsi->info.valid_sections = 0;
11440 /* query and update current VSI BW information */
11441 ret = i40e_vsi_get_bw_config(vsi);
11444 "Failed updating vsi bw info, err %s aq_err %s",
11445 i40e_stat_str(hw, ret),
11446 i40e_aq_str(hw, hw->aq.asq_last_status));
11450 vsi->enabled_tc = tc_map;
11457 * i40e_dcb_hw_configure - program the dcb setting to hw
11458 * @pf: pf the configuration is taken on
11459 * @new_cfg: new configuration
11460 * @tc_map: enabled TC bitmap
11462 * Returns 0 on success, negative value on failure
11464 static enum i40e_status_code
11465 i40e_dcb_hw_configure(struct i40e_pf *pf,
11466 struct i40e_dcbx_config *new_cfg,
11469 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11470 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11471 struct i40e_vsi *main_vsi = pf->main_vsi;
11472 struct i40e_vsi_list *vsi_list;
11473 enum i40e_status_code ret;
11477 /* Use the FW API if FW > v4.4*/
11478 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11479 (hw->aq.fw_maj_ver >= 5))) {
11481 "FW < v4.4, can not use FW LLDP API to configure DCB");
11482 return I40E_ERR_FIRMWARE_API_VERSION;
11485 /* Check if need reconfiguration */
11486 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11487 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11488 return I40E_SUCCESS;
11491 /* Copy the new config to the current config */
11492 *old_cfg = *new_cfg;
11493 old_cfg->etsrec = old_cfg->etscfg;
11494 ret = i40e_set_dcb_config(hw);
11496 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11497 i40e_stat_str(hw, ret),
11498 i40e_aq_str(hw, hw->aq.asq_last_status));
11501 /* set receive Arbiter to RR mode and ETS scheme by default */
11502 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11503 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11504 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
11505 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11506 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11507 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11508 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11509 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11510 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11511 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11512 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11513 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11514 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11516 /* get local mib to check whether it is configured correctly */
11518 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11519 /* Get Local DCB Config */
11520 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11521 &hw->local_dcbx_config);
11523 /* if Veb is created, need to update TC of it at first */
11524 if (main_vsi->veb) {
11525 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11527 PMD_INIT_LOG(WARNING,
11528 "Failed configuring TC for VEB seid=%d",
11529 main_vsi->veb->seid);
11531 /* Update each VSI */
11532 i40e_vsi_config_tc(main_vsi, tc_map);
11533 if (main_vsi->veb) {
11534 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11535 /* Beside main VSI and VMDQ VSIs, only enable default
11536 * TC for other VSIs
11538 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11539 ret = i40e_vsi_config_tc(vsi_list->vsi,
11542 ret = i40e_vsi_config_tc(vsi_list->vsi,
11543 I40E_DEFAULT_TCMAP);
11545 PMD_INIT_LOG(WARNING,
11546 "Failed configuring TC for VSI seid=%d",
11547 vsi_list->vsi->seid);
11551 return I40E_SUCCESS;
11555 * i40e_dcb_init_configure - initial dcb config
11556 * @dev: device being configured
11557 * @sw_dcb: indicate whether dcb is sw configured or hw offload
11559 * Returns 0 on success, negative value on failure
11562 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11564 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11565 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11568 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11569 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11573 /* DCB initialization:
11574 * Update DCB configuration from the Firmware and configure
11575 * LLDP MIB change event.
11577 if (sw_dcb == TRUE) {
11578 if (i40e_need_stop_lldp(dev)) {
11579 ret = i40e_aq_stop_lldp(hw, TRUE, TRUE, NULL);
11580 if (ret != I40E_SUCCESS)
11581 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
11584 ret = i40e_init_dcb(hw, true);
11585 /* If lldp agent is stopped, the return value from
11586 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11587 * adminq status. Otherwise, it should return success.
11589 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11590 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11591 memset(&hw->local_dcbx_config, 0,
11592 sizeof(struct i40e_dcbx_config));
11593 /* set dcb default configuration */
11594 hw->local_dcbx_config.etscfg.willing = 0;
11595 hw->local_dcbx_config.etscfg.maxtcs = 0;
11596 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11597 hw->local_dcbx_config.etscfg.tsatable[0] =
11599 /* all UPs mapping to TC0 */
11600 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11601 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11602 hw->local_dcbx_config.etsrec =
11603 hw->local_dcbx_config.etscfg;
11604 hw->local_dcbx_config.pfc.willing = 0;
11605 hw->local_dcbx_config.pfc.pfccap =
11606 I40E_MAX_TRAFFIC_CLASS;
11607 /* FW needs one App to configure HW */
11608 hw->local_dcbx_config.numapps = 1;
11609 hw->local_dcbx_config.app[0].selector =
11610 I40E_APP_SEL_ETHTYPE;
11611 hw->local_dcbx_config.app[0].priority = 3;
11612 hw->local_dcbx_config.app[0].protocolid =
11613 I40E_APP_PROTOID_FCOE;
11614 ret = i40e_set_dcb_config(hw);
11617 "default dcb config fails. err = %d, aq_err = %d.",
11618 ret, hw->aq.asq_last_status);
11623 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11624 ret, hw->aq.asq_last_status);
11628 ret = i40e_aq_start_lldp(hw, true, NULL);
11629 if (ret != I40E_SUCCESS)
11630 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11632 ret = i40e_init_dcb(hw, true);
11634 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11636 "HW doesn't support DCBX offload.");
11641 "DCBX configuration failed, err = %d, aq_err = %d.",
11642 ret, hw->aq.asq_last_status);
11650 * i40e_dcb_setup - setup dcb related config
11651 * @dev: device being configured
11653 * Returns 0 on success, negative value on failure
11656 i40e_dcb_setup(struct rte_eth_dev *dev)
11658 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11659 struct i40e_dcbx_config dcb_cfg;
11660 uint8_t tc_map = 0;
11663 if ((pf->flags & I40E_FLAG_DCB) == 0) {
11664 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11668 if (pf->vf_num != 0)
11669 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11671 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11673 PMD_INIT_LOG(ERR, "invalid dcb config");
11676 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11678 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11686 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11687 struct rte_eth_dcb_info *dcb_info)
11689 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11690 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11691 struct i40e_vsi *vsi = pf->main_vsi;
11692 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11693 uint16_t bsf, tc_mapping;
11696 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11697 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11699 dcb_info->nb_tcs = 1;
11700 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11701 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11702 for (i = 0; i < dcb_info->nb_tcs; i++)
11703 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11705 /* get queue mapping if vmdq is disabled */
11706 if (!pf->nb_cfg_vmdq_vsi) {
11707 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11708 if (!(vsi->enabled_tc & (1 << i)))
11710 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11711 dcb_info->tc_queue.tc_rxq[j][i].base =
11712 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11713 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11714 dcb_info->tc_queue.tc_txq[j][i].base =
11715 dcb_info->tc_queue.tc_rxq[j][i].base;
11716 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11717 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11718 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11719 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11720 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11725 /* get queue mapping if vmdq is enabled */
11727 vsi = pf->vmdq[j].vsi;
11728 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11729 if (!(vsi->enabled_tc & (1 << i)))
11731 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11732 dcb_info->tc_queue.tc_rxq[j][i].base =
11733 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11734 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11735 dcb_info->tc_queue.tc_txq[j][i].base =
11736 dcb_info->tc_queue.tc_rxq[j][i].base;
11737 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11738 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11739 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11740 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11741 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11744 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11749 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11751 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11752 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11753 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11754 uint16_t msix_intr;
11756 msix_intr = intr_handle->intr_vec[queue_id];
11757 if (msix_intr == I40E_MISC_VEC_ID)
11758 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11759 I40E_PFINT_DYN_CTL0_INTENA_MASK |
11760 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11761 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11764 I40E_PFINT_DYN_CTLN(msix_intr -
11765 I40E_RX_VEC_START),
11766 I40E_PFINT_DYN_CTLN_INTENA_MASK |
11767 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11768 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11770 I40E_WRITE_FLUSH(hw);
11771 rte_intr_ack(&pci_dev->intr_handle);
11777 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11779 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11780 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11781 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11782 uint16_t msix_intr;
11784 msix_intr = intr_handle->intr_vec[queue_id];
11785 if (msix_intr == I40E_MISC_VEC_ID)
11786 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11787 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11790 I40E_PFINT_DYN_CTLN(msix_intr -
11791 I40E_RX_VEC_START),
11792 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11793 I40E_WRITE_FLUSH(hw);
11799 * This function is used to check if the register is valid.
11800 * Below is the valid registers list for X722 only:
11804 * 0x208e00--0x209000
11805 * 0x20be00--0x20c000
11806 * 0x263c00--0x264000
11807 * 0x265c00--0x266000
11809 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset)
11811 if ((type != I40E_MAC_X722) &&
11812 ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) ||
11813 (reg_offset >= 0x38700 && reg_offset <= 0x38a00) ||
11814 (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) ||
11815 (reg_offset >= 0x208e00 && reg_offset <= 0x209000) ||
11816 (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) ||
11817 (reg_offset >= 0x263c00 && reg_offset <= 0x264000) ||
11818 (reg_offset >= 0x265c00 && reg_offset <= 0x266000)))
11824 static int i40e_get_regs(struct rte_eth_dev *dev,
11825 struct rte_dev_reg_info *regs)
11827 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11828 uint32_t *ptr_data = regs->data;
11829 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11830 const struct i40e_reg_info *reg_info;
11832 if (ptr_data == NULL) {
11833 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11834 regs->width = sizeof(uint32_t);
11838 /* The first few registers have to be read using AQ operations */
11840 while (i40e_regs_adminq[reg_idx].name) {
11841 reg_info = &i40e_regs_adminq[reg_idx++];
11842 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11844 arr_idx2 <= reg_info->count2;
11846 reg_offset = arr_idx * reg_info->stride1 +
11847 arr_idx2 * reg_info->stride2;
11848 reg_offset += reg_info->base_addr;
11849 ptr_data[reg_offset >> 2] =
11850 i40e_read_rx_ctl(hw, reg_offset);
11854 /* The remaining registers can be read using primitives */
11856 while (i40e_regs_others[reg_idx].name) {
11857 reg_info = &i40e_regs_others[reg_idx++];
11858 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11860 arr_idx2 <= reg_info->count2;
11862 reg_offset = arr_idx * reg_info->stride1 +
11863 arr_idx2 * reg_info->stride2;
11864 reg_offset += reg_info->base_addr;
11865 if (!i40e_valid_regs(hw->mac.type, reg_offset))
11866 ptr_data[reg_offset >> 2] = 0;
11868 ptr_data[reg_offset >> 2] =
11869 I40E_READ_REG(hw, reg_offset);
11876 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11878 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11880 /* Convert word count to byte count */
11881 return hw->nvm.sr_size << 1;
11884 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11885 struct rte_dev_eeprom_info *eeprom)
11887 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11888 uint16_t *data = eeprom->data;
11889 uint16_t offset, length, cnt_words;
11892 offset = eeprom->offset >> 1;
11893 length = eeprom->length >> 1;
11894 cnt_words = length;
11896 if (offset > hw->nvm.sr_size ||
11897 offset + length > hw->nvm.sr_size) {
11898 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11902 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11904 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11905 if (ret_code != I40E_SUCCESS || cnt_words != length) {
11906 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11913 static int i40e_get_module_info(struct rte_eth_dev *dev,
11914 struct rte_eth_dev_module_info *modinfo)
11916 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11917 uint32_t sff8472_comp = 0;
11918 uint32_t sff8472_swap = 0;
11919 uint32_t sff8636_rev = 0;
11920 i40e_status status;
11923 /* Check if firmware supports reading module EEPROM. */
11924 if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
11926 "Module EEPROM memory read not supported. "
11927 "Please update the NVM image.\n");
11931 status = i40e_update_link_info(hw);
11935 if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
11937 "Cannot read module EEPROM memory. "
11938 "No module connected.\n");
11942 type = hw->phy.link_info.module_type[0];
11945 case I40E_MODULE_TYPE_SFP:
11946 status = i40e_aq_get_phy_register(hw,
11947 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11948 I40E_I2C_EEPROM_DEV_ADDR, 1,
11949 I40E_MODULE_SFF_8472_COMP,
11950 &sff8472_comp, NULL);
11954 status = i40e_aq_get_phy_register(hw,
11955 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11956 I40E_I2C_EEPROM_DEV_ADDR, 1,
11957 I40E_MODULE_SFF_8472_SWAP,
11958 &sff8472_swap, NULL);
11962 /* Check if the module requires address swap to access
11963 * the other EEPROM memory page.
11965 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
11966 PMD_DRV_LOG(WARNING,
11967 "Module address swap to access "
11968 "page 0xA2 is not supported.\n");
11969 modinfo->type = RTE_ETH_MODULE_SFF_8079;
11970 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11971 } else if (sff8472_comp == 0x00) {
11972 /* Module is not SFF-8472 compliant */
11973 modinfo->type = RTE_ETH_MODULE_SFF_8079;
11974 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11976 modinfo->type = RTE_ETH_MODULE_SFF_8472;
11977 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
11980 case I40E_MODULE_TYPE_QSFP_PLUS:
11981 /* Read from memory page 0. */
11982 status = i40e_aq_get_phy_register(hw,
11983 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11985 I40E_MODULE_REVISION_ADDR,
11986 &sff8636_rev, NULL);
11989 /* Determine revision compliance byte */
11990 if (sff8636_rev > 0x02) {
11991 /* Module is SFF-8636 compliant */
11992 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11993 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11995 modinfo->type = RTE_ETH_MODULE_SFF_8436;
11996 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11999 case I40E_MODULE_TYPE_QSFP28:
12000 modinfo->type = RTE_ETH_MODULE_SFF_8636;
12001 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12004 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
12010 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
12011 struct rte_dev_eeprom_info *info)
12013 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12014 bool is_sfp = false;
12015 i40e_status status;
12017 uint32_t value = 0;
12020 if (!info || !info->length || !info->data)
12023 if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
12027 for (i = 0; i < info->length; i++) {
12028 u32 offset = i + info->offset;
12029 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
12031 /* Check if we need to access the other memory page */
12033 if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
12034 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
12035 addr = I40E_I2C_EEPROM_DEV_ADDR2;
12038 while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
12039 /* Compute memory page number and offset. */
12040 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
12044 status = i40e_aq_get_phy_register(hw,
12045 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12046 addr, offset, 1, &value, NULL);
12049 data[i] = (uint8_t)value;
12054 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
12055 struct rte_ether_addr *mac_addr)
12057 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12058 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12059 struct i40e_vsi *vsi = pf->main_vsi;
12060 struct i40e_mac_filter_info mac_filter;
12061 struct i40e_mac_filter *f;
12064 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
12065 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
12069 TAILQ_FOREACH(f, &vsi->mac_list, next) {
12070 if (rte_is_same_ether_addr(&pf->dev_addr,
12071 &f->mac_info.mac_addr))
12076 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
12080 mac_filter = f->mac_info;
12081 ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
12082 if (ret != I40E_SUCCESS) {
12083 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
12086 memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
12087 ret = i40e_vsi_add_mac(vsi, &mac_filter);
12088 if (ret != I40E_SUCCESS) {
12089 PMD_DRV_LOG(ERR, "Failed to add mac filter");
12092 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
12094 ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
12095 mac_addr->addr_bytes, NULL);
12096 if (ret != I40E_SUCCESS) {
12097 PMD_DRV_LOG(ERR, "Failed to change mac");
12105 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
12107 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12108 struct rte_eth_dev_data *dev_data = pf->dev_data;
12109 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
12112 /* check if mtu is within the allowed range */
12113 if (mtu < RTE_ETHER_MIN_MTU || frame_size > I40E_FRAME_SIZE_MAX)
12116 /* mtu setting is forbidden if port is start */
12117 if (dev_data->dev_started) {
12118 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
12119 dev_data->port_id);
12123 if (frame_size > RTE_ETHER_MAX_LEN)
12124 dev_data->dev_conf.rxmode.offloads |=
12125 DEV_RX_OFFLOAD_JUMBO_FRAME;
12127 dev_data->dev_conf.rxmode.offloads &=
12128 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
12130 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
12135 /* Restore ethertype filter */
12137 i40e_ethertype_filter_restore(struct i40e_pf *pf)
12139 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12140 struct i40e_ethertype_filter_list
12141 *ethertype_list = &pf->ethertype.ethertype_list;
12142 struct i40e_ethertype_filter *f;
12143 struct i40e_control_filter_stats stats;
12146 TAILQ_FOREACH(f, ethertype_list, rules) {
12148 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
12149 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
12150 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
12151 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
12152 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
12154 memset(&stats, 0, sizeof(stats));
12155 i40e_aq_add_rem_control_packet_filter(hw,
12156 f->input.mac_addr.addr_bytes,
12157 f->input.ether_type,
12158 flags, pf->main_vsi->seid,
12159 f->queue, 1, &stats, NULL);
12161 PMD_DRV_LOG(INFO, "Ethertype filter:"
12162 " mac_etype_used = %u, etype_used = %u,"
12163 " mac_etype_free = %u, etype_free = %u",
12164 stats.mac_etype_used, stats.etype_used,
12165 stats.mac_etype_free, stats.etype_free);
12168 /* Restore tunnel filter */
12170 i40e_tunnel_filter_restore(struct i40e_pf *pf)
12172 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12173 struct i40e_vsi *vsi;
12174 struct i40e_pf_vf *vf;
12175 struct i40e_tunnel_filter_list
12176 *tunnel_list = &pf->tunnel.tunnel_list;
12177 struct i40e_tunnel_filter *f;
12178 struct i40e_aqc_cloud_filters_element_bb cld_filter;
12179 bool big_buffer = 0;
12181 TAILQ_FOREACH(f, tunnel_list, rules) {
12183 vsi = pf->main_vsi;
12185 vf = &pf->vfs[f->vf_id];
12188 memset(&cld_filter, 0, sizeof(cld_filter));
12189 rte_ether_addr_copy((struct rte_ether_addr *)
12190 &f->input.outer_mac,
12191 (struct rte_ether_addr *)&cld_filter.element.outer_mac);
12192 rte_ether_addr_copy((struct rte_ether_addr *)
12193 &f->input.inner_mac,
12194 (struct rte_ether_addr *)&cld_filter.element.inner_mac);
12195 cld_filter.element.inner_vlan = f->input.inner_vlan;
12196 cld_filter.element.flags = f->input.flags;
12197 cld_filter.element.tenant_id = f->input.tenant_id;
12198 cld_filter.element.queue_number = f->queue;
12199 rte_memcpy(cld_filter.general_fields,
12200 f->input.general_fields,
12201 sizeof(f->input.general_fields));
12203 if (((f->input.flags &
12204 I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
12205 I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
12207 I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
12208 I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
12210 I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
12211 I40E_AQC_ADD_CLOUD_FILTER_0X10))
12215 i40e_aq_add_cloud_filters_bb(hw,
12216 vsi->seid, &cld_filter, 1);
12218 i40e_aq_add_cloud_filters(hw, vsi->seid,
12219 &cld_filter.element, 1);
12223 /* Restore rss filter */
12225 i40e_rss_filter_restore(struct i40e_pf *pf)
12227 struct i40e_rte_flow_rss_conf *conf =
12229 if (conf->conf.queue_num)
12230 i40e_config_rss_filter(pf, conf, TRUE);
12234 i40e_filter_restore(struct i40e_pf *pf)
12236 i40e_ethertype_filter_restore(pf);
12237 i40e_tunnel_filter_restore(pf);
12238 i40e_fdir_filter_restore(pf);
12239 i40e_rss_filter_restore(pf);
12243 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
12245 if (strcmp(dev->device->driver->name, drv->driver.name))
12252 is_i40e_supported(struct rte_eth_dev *dev)
12254 return is_device_supported(dev, &rte_i40e_pmd);
12257 struct i40e_customized_pctype*
12258 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
12262 for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
12263 if (pf->customized_pctype[i].index == index)
12264 return &pf->customized_pctype[i];
12270 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
12271 uint32_t pkg_size, uint32_t proto_num,
12272 struct rte_pmd_i40e_proto_info *proto,
12273 enum rte_pmd_i40e_package_op op)
12275 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12276 uint32_t pctype_num;
12277 struct rte_pmd_i40e_ptype_info *pctype;
12278 uint32_t buff_size;
12279 struct i40e_customized_pctype *new_pctype = NULL;
12281 uint8_t pctype_value;
12286 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12287 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12288 PMD_DRV_LOG(ERR, "Unsupported operation.");
12292 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12293 (uint8_t *)&pctype_num, sizeof(pctype_num),
12294 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
12296 PMD_DRV_LOG(ERR, "Failed to get pctype number");
12300 PMD_DRV_LOG(INFO, "No new pctype added");
12304 buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
12305 pctype = rte_zmalloc("new_pctype", buff_size, 0);
12307 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12310 /* get information about new pctype list */
12311 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12312 (uint8_t *)pctype, buff_size,
12313 RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
12315 PMD_DRV_LOG(ERR, "Failed to get pctype list");
12320 /* Update customized pctype. */
12321 for (i = 0; i < pctype_num; i++) {
12322 pctype_value = pctype[i].ptype_id;
12323 memset(name, 0, sizeof(name));
12324 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12325 proto_id = pctype[i].protocols[j];
12326 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12328 for (n = 0; n < proto_num; n++) {
12329 if (proto[n].proto_id != proto_id)
12331 strlcat(name, proto[n].name, sizeof(name));
12332 strlcat(name, "_", sizeof(name));
12336 name[strlen(name) - 1] = '\0';
12337 if (!strcmp(name, "GTPC"))
12339 i40e_find_customized_pctype(pf,
12340 I40E_CUSTOMIZED_GTPC);
12341 else if (!strcmp(name, "GTPU_IPV4"))
12343 i40e_find_customized_pctype(pf,
12344 I40E_CUSTOMIZED_GTPU_IPV4);
12345 else if (!strcmp(name, "GTPU_IPV6"))
12347 i40e_find_customized_pctype(pf,
12348 I40E_CUSTOMIZED_GTPU_IPV6);
12349 else if (!strcmp(name, "GTPU"))
12351 i40e_find_customized_pctype(pf,
12352 I40E_CUSTOMIZED_GTPU);
12353 else if (!strcmp(name, "IPV4_L2TPV3"))
12355 i40e_find_customized_pctype(pf,
12356 I40E_CUSTOMIZED_IPV4_L2TPV3);
12357 else if (!strcmp(name, "IPV6_L2TPV3"))
12359 i40e_find_customized_pctype(pf,
12360 I40E_CUSTOMIZED_IPV6_L2TPV3);
12362 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12363 new_pctype->pctype = pctype_value;
12364 new_pctype->valid = true;
12366 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
12367 new_pctype->valid = false;
12377 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
12378 uint32_t pkg_size, uint32_t proto_num,
12379 struct rte_pmd_i40e_proto_info *proto,
12380 enum rte_pmd_i40e_package_op op)
12382 struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
12383 uint16_t port_id = dev->data->port_id;
12384 uint32_t ptype_num;
12385 struct rte_pmd_i40e_ptype_info *ptype;
12386 uint32_t buff_size;
12388 char name[RTE_PMD_I40E_DDP_NAME_SIZE];
12393 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12394 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12395 PMD_DRV_LOG(ERR, "Unsupported operation.");
12399 if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
12400 rte_pmd_i40e_ptype_mapping_reset(port_id);
12404 /* get information about new ptype num */
12405 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12406 (uint8_t *)&ptype_num, sizeof(ptype_num),
12407 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12409 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12413 PMD_DRV_LOG(INFO, "No new ptype added");
12417 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12418 ptype = rte_zmalloc("new_ptype", buff_size, 0);
12420 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12424 /* get information about new ptype list */
12425 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12426 (uint8_t *)ptype, buff_size,
12427 RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12429 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12434 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12435 ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12436 if (!ptype_mapping) {
12437 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12442 /* Update ptype mapping table. */
12443 for (i = 0; i < ptype_num; i++) {
12444 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12445 ptype_mapping[i].sw_ptype = 0;
12447 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12448 proto_id = ptype[i].protocols[j];
12449 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12451 for (n = 0; n < proto_num; n++) {
12452 if (proto[n].proto_id != proto_id)
12454 memset(name, 0, sizeof(name));
12455 strcpy(name, proto[n].name);
12456 if (!strncasecmp(name, "PPPOE", 5))
12457 ptype_mapping[i].sw_ptype |=
12458 RTE_PTYPE_L2_ETHER_PPPOE;
12459 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12461 ptype_mapping[i].sw_ptype |=
12462 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12463 ptype_mapping[i].sw_ptype |=
12465 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12467 ptype_mapping[i].sw_ptype |=
12468 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12469 ptype_mapping[i].sw_ptype |=
12470 RTE_PTYPE_INNER_L4_FRAG;
12471 } else if (!strncasecmp(name, "OIPV4", 5)) {
12472 ptype_mapping[i].sw_ptype |=
12473 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12475 } else if (!strncasecmp(name, "IPV4", 4) &&
12477 ptype_mapping[i].sw_ptype |=
12478 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12479 else if (!strncasecmp(name, "IPV4", 4) &&
12481 ptype_mapping[i].sw_ptype |=
12482 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12483 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12485 ptype_mapping[i].sw_ptype |=
12486 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12487 ptype_mapping[i].sw_ptype |=
12489 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12491 ptype_mapping[i].sw_ptype |=
12492 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12493 ptype_mapping[i].sw_ptype |=
12494 RTE_PTYPE_INNER_L4_FRAG;
12495 } else if (!strncasecmp(name, "OIPV6", 5)) {
12496 ptype_mapping[i].sw_ptype |=
12497 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12499 } else if (!strncasecmp(name, "IPV6", 4) &&
12501 ptype_mapping[i].sw_ptype |=
12502 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12503 else if (!strncasecmp(name, "IPV6", 4) &&
12505 ptype_mapping[i].sw_ptype |=
12506 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12507 else if (!strncasecmp(name, "UDP", 3) &&
12509 ptype_mapping[i].sw_ptype |=
12511 else if (!strncasecmp(name, "UDP", 3) &&
12513 ptype_mapping[i].sw_ptype |=
12514 RTE_PTYPE_INNER_L4_UDP;
12515 else if (!strncasecmp(name, "TCP", 3) &&
12517 ptype_mapping[i].sw_ptype |=
12519 else if (!strncasecmp(name, "TCP", 3) &&
12521 ptype_mapping[i].sw_ptype |=
12522 RTE_PTYPE_INNER_L4_TCP;
12523 else if (!strncasecmp(name, "SCTP", 4) &&
12525 ptype_mapping[i].sw_ptype |=
12527 else if (!strncasecmp(name, "SCTP", 4) &&
12529 ptype_mapping[i].sw_ptype |=
12530 RTE_PTYPE_INNER_L4_SCTP;
12531 else if ((!strncasecmp(name, "ICMP", 4) ||
12532 !strncasecmp(name, "ICMPV6", 6)) &&
12534 ptype_mapping[i].sw_ptype |=
12536 else if ((!strncasecmp(name, "ICMP", 4) ||
12537 !strncasecmp(name, "ICMPV6", 6)) &&
12539 ptype_mapping[i].sw_ptype |=
12540 RTE_PTYPE_INNER_L4_ICMP;
12541 else if (!strncasecmp(name, "GTPC", 4)) {
12542 ptype_mapping[i].sw_ptype |=
12543 RTE_PTYPE_TUNNEL_GTPC;
12545 } else if (!strncasecmp(name, "GTPU", 4)) {
12546 ptype_mapping[i].sw_ptype |=
12547 RTE_PTYPE_TUNNEL_GTPU;
12549 } else if (!strncasecmp(name, "GRENAT", 6)) {
12550 ptype_mapping[i].sw_ptype |=
12551 RTE_PTYPE_TUNNEL_GRENAT;
12553 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12554 !strncasecmp(name, "L2TPV2", 6) ||
12555 !strncasecmp(name, "L2TPV3", 6)) {
12556 ptype_mapping[i].sw_ptype |=
12557 RTE_PTYPE_TUNNEL_L2TP;
12566 ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12569 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
12571 rte_free(ptype_mapping);
12577 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12578 uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12580 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12581 uint32_t proto_num;
12582 struct rte_pmd_i40e_proto_info *proto;
12583 uint32_t buff_size;
12587 if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12588 op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12589 PMD_DRV_LOG(ERR, "Unsupported operation.");
12593 /* get information about protocol number */
12594 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12595 (uint8_t *)&proto_num, sizeof(proto_num),
12596 RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12598 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12602 PMD_DRV_LOG(INFO, "No new protocol added");
12606 buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12607 proto = rte_zmalloc("new_proto", buff_size, 0);
12609 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12613 /* get information about protocol list */
12614 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12615 (uint8_t *)proto, buff_size,
12616 RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12618 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12623 /* Check if GTP is supported. */
12624 for (i = 0; i < proto_num; i++) {
12625 if (!strncmp(proto[i].name, "GTP", 3)) {
12626 if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12627 pf->gtp_support = true;
12629 pf->gtp_support = false;
12634 /* Update customized pctype info */
12635 ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12636 proto_num, proto, op);
12638 PMD_DRV_LOG(INFO, "No pctype is updated.");
12640 /* Update customized ptype info */
12641 ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12642 proto_num, proto, op);
12644 PMD_DRV_LOG(INFO, "No ptype is updated.");
12649 /* Create a QinQ cloud filter
12651 * The Fortville NIC has limited resources for tunnel filters,
12652 * so we can only reuse existing filters.
12654 * In step 1 we define which Field Vector fields can be used for
12656 * As we do not have the inner tag defined as a field,
12657 * we have to define it first, by reusing one of L1 entries.
12659 * In step 2 we are replacing one of existing filter types with
12660 * a new one for QinQ.
12661 * As we reusing L1 and replacing L2, some of the default filter
12662 * types will disappear,which depends on L1 and L2 entries we reuse.
12664 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12666 * 1. Create L1 filter of outer vlan (12b) which will be in use
12667 * later when we define the cloud filter.
12668 * a. Valid_flags.replace_cloud = 0
12669 * b. Old_filter = 10 (Stag_Inner_Vlan)
12670 * c. New_filter = 0x10
12671 * d. TR bit = 0xff (optional, not used here)
12672 * e. Buffer – 2 entries:
12673 * i. Byte 0 = 8 (outer vlan FV index).
12675 * Byte 2-3 = 0x0fff
12676 * ii. Byte 0 = 37 (inner vlan FV index).
12678 * Byte 2-3 = 0x0fff
12681 * 2. Create cloud filter using two L1 filters entries: stag and
12682 * new filter(outer vlan+ inner vlan)
12683 * a. Valid_flags.replace_cloud = 1
12684 * b. Old_filter = 1 (instead of outer IP)
12685 * c. New_filter = 0x10
12686 * d. Buffer – 2 entries:
12687 * i. Byte 0 = 0x80 | 7 (valid | Stag).
12688 * Byte 1-3 = 0 (rsv)
12689 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12690 * Byte 9-11 = 0 (rsv)
12693 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12695 int ret = -ENOTSUP;
12696 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
12697 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
12698 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12699 struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
12701 if (pf->support_multi_driver) {
12702 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12707 memset(&filter_replace, 0,
12708 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12709 memset(&filter_replace_buf, 0,
12710 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12712 /* create L1 filter */
12713 filter_replace.old_filter_type =
12714 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12715 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12716 filter_replace.tr_bit = 0;
12718 /* Prepare the buffer, 2 entries */
12719 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12720 filter_replace_buf.data[0] |=
12721 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12722 /* Field Vector 12b mask */
12723 filter_replace_buf.data[2] = 0xff;
12724 filter_replace_buf.data[3] = 0x0f;
12725 filter_replace_buf.data[4] =
12726 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12727 filter_replace_buf.data[4] |=
12728 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12729 /* Field Vector 12b mask */
12730 filter_replace_buf.data[6] = 0xff;
12731 filter_replace_buf.data[7] = 0x0f;
12732 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12733 &filter_replace_buf);
12734 if (ret != I40E_SUCCESS)
12737 if (filter_replace.old_filter_type !=
12738 filter_replace.new_filter_type)
12739 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
12740 " original: 0x%x, new: 0x%x",
12742 filter_replace.old_filter_type,
12743 filter_replace.new_filter_type);
12745 /* Apply the second L2 cloud filter */
12746 memset(&filter_replace, 0,
12747 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12748 memset(&filter_replace_buf, 0,
12749 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12751 /* create L2 filter, input for L2 filter will be L1 filter */
12752 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12753 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12754 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12756 /* Prepare the buffer, 2 entries */
12757 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12758 filter_replace_buf.data[0] |=
12759 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12760 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12761 filter_replace_buf.data[4] |=
12762 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12763 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12764 &filter_replace_buf);
12765 if (!ret && (filter_replace.old_filter_type !=
12766 filter_replace.new_filter_type))
12767 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
12768 " original: 0x%x, new: 0x%x",
12770 filter_replace.old_filter_type,
12771 filter_replace.new_filter_type);
12777 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
12778 const struct rte_flow_action_rss *in)
12780 if (in->key_len > RTE_DIM(out->key) ||
12781 in->queue_num > RTE_DIM(out->queue))
12783 if (!in->key && in->key_len)
12785 out->conf = (struct rte_flow_action_rss){
12787 .level = in->level,
12788 .types = in->types,
12789 .key_len = in->key_len,
12790 .queue_num = in->queue_num,
12791 .queue = memcpy(out->queue, in->queue,
12792 sizeof(*in->queue) * in->queue_num),
12795 out->conf.key = memcpy(out->key, in->key, in->key_len);
12800 i40e_action_rss_same(const struct rte_flow_action_rss *comp,
12801 const struct rte_flow_action_rss *with)
12803 return (comp->func == with->func &&
12804 comp->level == with->level &&
12805 comp->types == with->types &&
12806 comp->key_len == with->key_len &&
12807 comp->queue_num == with->queue_num &&
12808 !memcmp(comp->key, with->key, with->key_len) &&
12809 !memcmp(comp->queue, with->queue,
12810 sizeof(*with->queue) * with->queue_num));
12814 i40e_config_rss_filter(struct i40e_pf *pf,
12815 struct i40e_rte_flow_rss_conf *conf, bool add)
12817 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12818 uint32_t i, lut = 0;
12820 struct rte_eth_rss_conf rss_conf = {
12821 .rss_key = conf->conf.key_len ?
12822 (void *)(uintptr_t)conf->conf.key : NULL,
12823 .rss_key_len = conf->conf.key_len,
12824 .rss_hf = conf->conf.types,
12826 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
12829 if (i40e_action_rss_same(&rss_info->conf, &conf->conf)) {
12830 i40e_pf_disable_rss(pf);
12831 memset(rss_info, 0,
12832 sizeof(struct i40e_rte_flow_rss_conf));
12838 /* If both VMDQ and RSS enabled, not all of PF queues are configured.
12839 * It's necessary to calculate the actual PF queues that are configured.
12841 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
12842 num = i40e_pf_calc_configured_queues_num(pf);
12844 num = pf->dev_data->nb_rx_queues;
12846 num = RTE_MIN(num, conf->conf.queue_num);
12847 PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
12851 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS");
12855 /* Fill in redirection table */
12856 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
12859 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
12860 hw->func_caps.rss_table_entry_width) - 1));
12862 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
12865 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
12866 i40e_pf_disable_rss(pf);
12869 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
12870 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
12871 /* Random default keys */
12872 static uint32_t rss_key_default[] = {0x6b793944,
12873 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
12874 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
12875 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
12877 rss_conf.rss_key = (uint8_t *)rss_key_default;
12878 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
12881 "No valid RSS key config for i40e, using default\n");
12884 i40e_hw_rss_hash_set(pf, &rss_conf);
12886 if (i40e_rss_conf_init(rss_info, &conf->conf))
12892 RTE_INIT(i40e_init_log)
12894 i40e_logtype_init = rte_log_register("pmd.net.i40e.init");
12895 if (i40e_logtype_init >= 0)
12896 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
12897 i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver");
12898 if (i40e_logtype_driver >= 0)
12899 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
12901 #ifdef RTE_LIBRTE_I40E_DEBUG_RX
12902 i40e_logtype_rx = rte_log_register("pmd.net.i40e.rx");
12903 if (i40e_logtype_rx >= 0)
12904 rte_log_set_level(i40e_logtype_rx, RTE_LOG_DEBUG);
12907 #ifdef RTE_LIBRTE_I40E_DEBUG_TX
12908 i40e_logtype_tx = rte_log_register("pmd.net.i40e.tx");
12909 if (i40e_logtype_tx >= 0)
12910 rte_log_set_level(i40e_logtype_tx, RTE_LOG_DEBUG);
12913 #ifdef RTE_LIBRTE_I40E_DEBUG_TX_FREE
12914 i40e_logtype_tx_free = rte_log_register("pmd.net.i40e.tx_free");
12915 if (i40e_logtype_tx_free >= 0)
12916 rte_log_set_level(i40e_logtype_tx_free, RTE_LOG_DEBUG);
12920 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12921 ETH_I40E_FLOATING_VEB_ARG "=1"
12922 ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
12923 ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12924 ETH_I40E_SUPPORT_MULTI_DRIVER "=1"
12925 ETH_I40E_USE_LATEST_VEC "=0|1");