drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <assert.h>
  43
  44 #include <rte_string_fns.h>
  45 #include <rte_pci.h>
  46 #include <rte_ether.h>
  47 #include <rte_ethdev.h>
  48 #include <rte_memzone.h>
  49 #include <rte_malloc.h>
  50 #include <rte_memcpy.h>
  51 #include <rte_alarm.h>
  52 #include <rte_dev.h>
  53 #include <rte_eth_ctrl.h>
  54
  55 #include "i40e_logs.h"
  56 #include "base/i40e_prototype.h"
  57 #include "base/i40e_adminq_cmd.h"
  58 #include "base/i40e_type.h"
  59 #include "base/i40e_register.h"
  60 #include "base/i40e_dcb.h"
  61 #include "i40e_ethdev.h"
  62 #include "i40e_rxtx.h"
  63 #include "i40e_pf.h"
  64 #include "i40e_regs.h"
  65
  66 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  67 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  68
  69 #define I40E_CLEAR_PXE_WAIT_MS     200
  70
  71 /* Maximun number of capability elements */
  72 #define I40E_MAX_CAP_ELE_NUM       128
  73
  74 /* Wait count and inteval */
  75 #define I40E_CHK_Q_ENA_COUNT       1000
  76 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  77
  78 /* Maximun number of VSI */
  79 #define I40E_MAX_NUM_VSIS          (384UL)
  80
  81 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  82
  83 /* Flow control default timer */
  84 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  85
  86 /* Flow control default high water */
  87 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  88
  89 /* Flow control default low water */
  90 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  91
  92 /* Flow control enable fwd bit */
  93 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  94
  95 /* Receive Packet Buffer size */
  96 #define I40E_RXPBSIZE (968 * 1024)
  97
  98 /* Kilobytes shift */
  99 #define I40E_KILOSHIFT 10
 100
 101 /* Receive Average Packet Size in Byte*/
 102 #define I40E_PACKET_AVERAGE_SIZE 128
 103
 104 /* Mask of PF interrupt causes */
 105 #define I40E_PFINT_ICR0_ENA_MASK ( \
 106                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 107                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 108                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 109                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 110                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 111                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
 112                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 113                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 114                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 115                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 116
 117 #define I40E_FLOW_TYPES ( \
 118         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 119         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 123         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 128         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 129
 130 /* Additional timesync values. */
 131 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 132 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 133 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 134 #define I40E_PRTTSYN_TSYNENA     0x80000000
 135 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 136 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 137
 138 #define I40E_MAX_PERCENT            100
 139 #define I40E_DEFAULT_DCB_APP_NUM    1
 140 #define I40E_DEFAULT_DCB_APP_PRIO   3
 141
 142 #define I40E_INSET_NONE            0x00000000000000000ULL
 143
 144 /* bit0 ~ bit 7 */
 145 #define I40E_INSET_DMAC            0x0000000000000001ULL
 146 #define I40E_INSET_SMAC            0x0000000000000002ULL
 147 #define I40E_INSET_VLAN_OUTER      0x0000000000000004ULL
 148 #define I40E_INSET_VLAN_INNER      0x0000000000000008ULL
 149 #define I40E_INSET_VLAN_TUNNEL     0x0000000000000010ULL
 150
 151 /* bit 8 ~ bit 15 */
 152 #define I40E_INSET_IPV4_SRC        0x0000000000000100ULL
 153 #define I40E_INSET_IPV4_DST        0x0000000000000200ULL
 154 #define I40E_INSET_IPV6_SRC        0x0000000000000400ULL
 155 #define I40E_INSET_IPV6_DST        0x0000000000000800ULL
 156 #define I40E_INSET_SRC_PORT        0x0000000000001000ULL
 157 #define I40E_INSET_DST_PORT        0x0000000000002000ULL
 158 #define I40E_INSET_SCTP_VT         0x0000000000004000ULL
 159
 160 /* bit 16 ~ bit 31 */
 161 #define I40E_INSET_IPV4_TOS        0x0000000000010000ULL
 162 #define I40E_INSET_IPV4_PROTO      0x0000000000020000ULL
 163 #define I40E_INSET_IPV4_TTL        0x0000000000040000ULL
 164 #define I40E_INSET_IPV6_TC         0x0000000000080000ULL
 165 #define I40E_INSET_IPV6_FLOW       0x0000000000100000ULL
 166 #define I40E_INSET_IPV6_NEXT_HDR   0x0000000000200000ULL
 167 #define I40E_INSET_IPV6_HOP_LIMIT  0x0000000000400000ULL
 168 #define I40E_INSET_TCP_FLAGS       0x0000000000800000ULL
 169
 170 /* bit 32 ~ bit 47, tunnel fields */
 171 #define I40E_INSET_TUNNEL_IPV4_DST       0x0000000100000000ULL
 172 #define I40E_INSET_TUNNEL_IPV6_DST       0x0000000200000000ULL
 173 #define I40E_INSET_TUNNEL_DMAC           0x0000000400000000ULL
 174 #define I40E_INSET_TUNNEL_SRC_PORT       0x0000000800000000ULL
 175 #define I40E_INSET_TUNNEL_DST_PORT       0x0000001000000000ULL
 176 #define I40E_INSET_TUNNEL_ID             0x0000002000000000ULL
 177
 178 /* bit 48 ~ bit 55 */
 179 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
 180
 181 /* bit 56 ~ bit 63, Flex Payload */
 182 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
 183 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
 184 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
 185 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
 186 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
 187 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
 188 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
 189 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
 190 #define I40E_INSET_FLEX_PAYLOAD \
 191         (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
 192         I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
 193         I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
 194         I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
 195
 196 /**
 197  * Below are values for writing un-exposed registers suggested
 198  * by silicon experts
 199  */
 200 /* Destination MAC address */
 201 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 202 /* Source MAC address */
 203 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 204 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 205 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0200000000000000ULL
 206 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 207 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 208 /* Single VLAN tag in the inner L2 header */
 209 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 210 /* Source IPv4 address */
 211 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 212 /* Destination IPv4 address */
 213 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 214 /* IPv4 Type of Service (TOS) */
 215 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 216 /* IPv4 Protocol */
 217 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 218 /* IPv4 Time to Live */
 219 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 220 /* Source IPv6 address */
 221 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 222 /* Destination IPv6 address */
 223 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 224 /* IPv6 Traffic Class (TC) */
 225 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 226 /* IPv6 Next Header */
 227 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 228 /* IPv6 Hop Limit */
 229 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 230 /* Source L4 port */
 231 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 232 /* Destination L4 port */
 233 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 234 /* SCTP verification tag */
 235 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 236 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 237 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 238 /* Source port of tunneling UDP */
 239 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 240 /* Destination port of tunneling UDP */
 241 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 242 /* UDP Tunneling ID, NVGRE/GRE key */
 243 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 244 /* Last ether type */
 245 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 246 /* Tunneling outer destination IPv4 address */
 247 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 248 /* Tunneling outer destination IPv6 address */
 249 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 250 /* 1st word of flex payload */
 251 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 252 /* 2nd word of flex payload */
 253 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 254 /* 3rd word of flex payload */
 255 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 256 /* 4th word of flex payload */
 257 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 258 /* 5th word of flex payload */
 259 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 260 /* 6th word of flex payload */
 261 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 262 /* 7th word of flex payload */
 263 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 264 /* 8th word of flex payload */
 265 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 266 /* all 8 words flex payload */
 267 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 268 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 269
 270 #define I40E_TRANSLATE_INSET 0
 271 #define I40E_TRANSLATE_REG   1
 272
 273 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 274 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 275 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 276 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 277 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 278 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 279
 280 #define I40E_GL_SWT_L2TAGCTRL(_i)             (0x001C0A70 + ((_i) * 4))
 281 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
 282 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK  \
 283         I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
 284
 285 /* PCI offset for querying capability */
 286 #define PCI_DEV_CAP_REG            0xA4
 287 /* PCI offset for enabling/disabling Extended Tag */
 288 #define PCI_DEV_CTRL_REG           0xA8
 289 /* Bit mask of Extended Tag capability */
 290 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 291 /* Bit shift of Extended Tag enable/disable */
 292 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 293 /* Bit mask of Extended Tag enable/disable */
 294 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 295
 296 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 297 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 298 static int i40e_dev_configure(struct rte_eth_dev *dev);
 299 static int i40e_dev_start(struct rte_eth_dev *dev);
 300 static void i40e_dev_stop(struct rte_eth_dev *dev);
 301 static void i40e_dev_close(struct rte_eth_dev *dev);
 302 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 303 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 304 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 305 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 306 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 307 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 308 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 309                                struct rte_eth_stats *stats);
 310 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 311                                struct rte_eth_xstat *xstats, unsigned n);
 312 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 313                                      struct rte_eth_xstat_name *xstats_names,
 314                                      unsigned limit);
 315 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 316 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 317                                             uint16_t queue_id,
 318                                             uint8_t stat_idx,
 319                                             uint8_t is_rx);
 320 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 321                               struct rte_eth_dev_info *dev_info);
 322 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 323                                 uint16_t vlan_id,
 324                                 int on);
 325 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 326                               enum rte_vlan_type vlan_type,
 327                               uint16_t tpid);
 328 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 329 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 330                                       uint16_t queue,
 331                                       int on);
 332 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 333 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 334 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 335 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 336                               struct rte_eth_fc_conf *fc_conf);
 337 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 338                               struct rte_eth_fc_conf *fc_conf);
 339 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 340                                        struct rte_eth_pfc_conf *pfc_conf);
 341 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 342                           struct ether_addr *mac_addr,
 343                           uint32_t index,
 344                           uint32_t pool);
 345 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 346 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 347                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 348                                     uint16_t reta_size);
 349 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 350                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 351                                    uint16_t reta_size);
 352
 353 static int i40e_get_cap(struct i40e_hw *hw);
 354 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 355 static int i40e_pf_setup(struct i40e_pf *pf);
 356 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 357 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 358 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 359 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 360 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 361                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 362 static void i40e_stat_update_48(struct i40e_hw *hw,
 363                                uint32_t hireg,
 364                                uint32_t loreg,
 365                                bool offset_loaded,
 366                                uint64_t *offset,
 367                                uint64_t *stat);
 368 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 369 static void i40e_dev_interrupt_handler(
 370                 __rte_unused struct rte_intr_handle *handle, void *param);
 371 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 372                                 uint32_t base, uint32_t num);
 373 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 374 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 375                         uint32_t base);
 376 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 377                         uint16_t num);
 378 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 379 static int i40e_veb_release(struct i40e_veb *veb);
 380 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 381                                                 struct i40e_vsi *vsi);
 382 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 383 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 384 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 385                                              struct i40e_macvlan_filter *mv_f,
 386                                              int num,
 387                                              struct ether_addr *addr);
 388 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 389                                              struct i40e_macvlan_filter *mv_f,
 390                                              int num,
 391                                              uint16_t vlan);
 392 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 393 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 394                                     struct rte_eth_rss_conf *rss_conf);
 395 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 396                                       struct rte_eth_rss_conf *rss_conf);
 397 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 398                                         struct rte_eth_udp_tunnel *udp_tunnel);
 399 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 400                                         struct rte_eth_udp_tunnel *udp_tunnel);
 401 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 402 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 403                         struct rte_eth_ethertype_filter *filter,
 404                         bool add);
 405 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 406                                 enum rte_filter_op filter_op,
 407                                 void *arg);
 408 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 409                                 enum rte_filter_type filter_type,
 410                                 enum rte_filter_op filter_op,
 411                                 void *arg);
 412 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 413                                   struct rte_eth_dcb_info *dcb_info);
 414 static void i40e_configure_registers(struct i40e_hw *hw);
 415 static void i40e_hw_init(struct rte_eth_dev *dev);
 416 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 417 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 418                         struct rte_eth_mirror_conf *mirror_conf,
 419                         uint8_t sw_id, uint8_t on);
 420 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 421
 422 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 423 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 424 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 425                                            struct timespec *timestamp,
 426                                            uint32_t flags);
 427 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 428                                            struct timespec *timestamp);
 429 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 430
 431 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 432
 433 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 434                                    struct timespec *timestamp);
 435 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 436                                     const struct timespec *timestamp);
 437
 438 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 439                                          uint16_t queue_id);
 440 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 441                                           uint16_t queue_id);
 442
 443 static int i40e_get_regs(struct rte_eth_dev *dev,
 444                          struct rte_dev_reg_info *regs);
 445
 446 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 447
 448 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 449                            struct rte_dev_eeprom_info *eeprom);
 450
 451 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 452                                       struct ether_addr *mac_addr);
 453
 454 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 455
 456 static const struct rte_pci_id pci_id_i40e_map[] = {
 457 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 458 #include "rte_pci_dev_ids.h"
 459 { .vendor_id = 0, /* sentinel */ },
 460 };
 461
 462 static const struct eth_dev_ops i40e_eth_dev_ops = {
 463         .dev_configure                = i40e_dev_configure,
 464         .dev_start                    = i40e_dev_start,
 465         .dev_stop                     = i40e_dev_stop,
 466         .dev_close                    = i40e_dev_close,
 467         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 468         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 469         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 470         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 471         .dev_set_link_up              = i40e_dev_set_link_up,
 472         .dev_set_link_down            = i40e_dev_set_link_down,
 473         .link_update                  = i40e_dev_link_update,
 474         .stats_get                    = i40e_dev_stats_get,
 475         .xstats_get                   = i40e_dev_xstats_get,
 476         .xstats_get_names             = i40e_dev_xstats_get_names,
 477         .stats_reset                  = i40e_dev_stats_reset,
 478         .xstats_reset                 = i40e_dev_stats_reset,
 479         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 480         .dev_infos_get                = i40e_dev_info_get,
 481         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 482         .vlan_filter_set              = i40e_vlan_filter_set,
 483         .vlan_tpid_set                = i40e_vlan_tpid_set,
 484         .vlan_offload_set             = i40e_vlan_offload_set,
 485         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 486         .vlan_pvid_set                = i40e_vlan_pvid_set,
 487         .rx_queue_start               = i40e_dev_rx_queue_start,
 488         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 489         .tx_queue_start               = i40e_dev_tx_queue_start,
 490         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 491         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 492         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 493         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 494         .rx_queue_release             = i40e_dev_rx_queue_release,
 495         .rx_queue_count               = i40e_dev_rx_queue_count,
 496         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 497         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 498         .tx_queue_release             = i40e_dev_tx_queue_release,
 499         .dev_led_on                   = i40e_dev_led_on,
 500         .dev_led_off                  = i40e_dev_led_off,
 501         .flow_ctrl_get                = i40e_flow_ctrl_get,
 502         .flow_ctrl_set                = i40e_flow_ctrl_set,
 503         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 504         .mac_addr_add                 = i40e_macaddr_add,
 505         .mac_addr_remove              = i40e_macaddr_remove,
 506         .reta_update                  = i40e_dev_rss_reta_update,
 507         .reta_query                   = i40e_dev_rss_reta_query,
 508         .rss_hash_update              = i40e_dev_rss_hash_update,
 509         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 510         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 511         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 512         .filter_ctrl                  = i40e_dev_filter_ctrl,
 513         .rxq_info_get                 = i40e_rxq_info_get,
 514         .txq_info_get                 = i40e_txq_info_get,
 515         .mirror_rule_set              = i40e_mirror_rule_set,
 516         .mirror_rule_reset            = i40e_mirror_rule_reset,
 517         .timesync_enable              = i40e_timesync_enable,
 518         .timesync_disable             = i40e_timesync_disable,
 519         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 520         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 521         .get_dcb_info                 = i40e_dev_get_dcb_info,
 522         .timesync_adjust_time         = i40e_timesync_adjust_time,
 523         .timesync_read_time           = i40e_timesync_read_time,
 524         .timesync_write_time          = i40e_timesync_write_time,
 525         .get_reg                      = i40e_get_regs,
 526         .get_eeprom_length            = i40e_get_eeprom_length,
 527         .get_eeprom                   = i40e_get_eeprom,
 528         .mac_addr_set                 = i40e_set_default_mac_addr,
 529         .mtu_set                      = i40e_dev_mtu_set,
 530 };
 531
 532 /* store statistics names and its offset in stats structure */
 533 struct rte_i40e_xstats_name_off {
 534         char name[RTE_ETH_XSTATS_NAME_SIZE];
 535         unsigned offset;
 536 };
 537
 538 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 539         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 540         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 541         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 542         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 543         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 544                 rx_unknown_protocol)},
 545         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 546         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 547         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 548         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 549 };
 550
 551 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 552                 sizeof(rte_i40e_stats_strings[0]))
 553
 554 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 555         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 556                 tx_dropped_link_down)},
 557         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 558         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 559                 illegal_bytes)},
 560         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 561         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 562                 mac_local_faults)},
 563         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 564                 mac_remote_faults)},
 565         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 566                 rx_length_errors)},
 567         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 568         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 569         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 570         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 571         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 572         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 573                 rx_size_127)},
 574         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 575                 rx_size_255)},
 576         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 577                 rx_size_511)},
 578         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 579                 rx_size_1023)},
 580         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 581                 rx_size_1522)},
 582         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 583                 rx_size_big)},
 584         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 585                 rx_undersize)},
 586         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 587                 rx_oversize)},
 588         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 589                 mac_short_packet_dropped)},
 590         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 591                 rx_fragments)},
 592         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 593         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 594         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 595                 tx_size_127)},
 596         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 597                 tx_size_255)},
 598         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 599                 tx_size_511)},
 600         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 601                 tx_size_1023)},
 602         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 603                 tx_size_1522)},
 604         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 605                 tx_size_big)},
 606         {"rx_flow_director_atr_match_packets",
 607                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 608         {"rx_flow_director_sb_match_packets",
 609                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 610         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 611                 tx_lpi_status)},
 612         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 613                 rx_lpi_status)},
 614         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 615                 tx_lpi_count)},
 616         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 617                 rx_lpi_count)},
 618 };
 619
 620 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 621                 sizeof(rte_i40e_hw_port_strings[0]))
 622
 623 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 624         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 625                 priority_xon_rx)},
 626         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 627                 priority_xoff_rx)},
 628 };
 629
 630 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 631                 sizeof(rte_i40e_rxq_prio_strings[0]))
 632
 633 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 634         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 635                 priority_xon_tx)},
 636         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 637                 priority_xoff_tx)},
 638         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 639                 priority_xon_2_xoff)},
 640 };
 641
 642 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 643                 sizeof(rte_i40e_txq_prio_strings[0]))
 644
 645 static struct eth_driver rte_i40e_pmd = {
 646         .pci_drv = {
 647                 .name = "rte_i40e_pmd",
 648                 .id_table = pci_id_i40e_map,
 649                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 650                         RTE_PCI_DRV_DETACHABLE,
 651         },
 652         .eth_dev_init = eth_i40e_dev_init,
 653         .eth_dev_uninit = eth_i40e_dev_uninit,
 654         .dev_private_size = sizeof(struct i40e_adapter),
 655 };
 656
 657 static inline int
 658 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 659                                      struct rte_eth_link *link)
 660 {
 661         struct rte_eth_link *dst = link;
 662         struct rte_eth_link *src = &(dev->data->dev_link);
 663
 664         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 665                                         *(uint64_t *)src) == 0)
 666                 return -1;
 667
 668         return 0;
 669 }
 670
 671 static inline int
 672 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 673                                       struct rte_eth_link *link)
 674 {
 675         struct rte_eth_link *dst = &(dev->data->dev_link);
 676         struct rte_eth_link *src = link;
 677
 678         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 679                                         *(uint64_t *)src) == 0)
 680                 return -1;
 681
 682         return 0;
 683 }
 684
 685 /*
 686  * Driver initialization routine.
 687  * Invoked once at EAL init time.
 688  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 689  */
 690 static int
 691 rte_i40e_pmd_init(const char *name __rte_unused,
 692                   const char *params __rte_unused)
 693 {
 694         PMD_INIT_FUNC_TRACE();
 695         rte_eth_driver_register(&rte_i40e_pmd);
 696
 697         return 0;
 698 }
 699
 700 static struct rte_driver rte_i40e_driver = {
 701         .type = PMD_PDEV,
 702         .init = rte_i40e_pmd_init,
 703 };
 704
 705 PMD_REGISTER_DRIVER(rte_i40e_driver, i40e);
 706 DRIVER_REGISTER_PCI_TABLE(i40e, pci_id_i40e_map);
 707
 708 /*
 709  * Initialize registers for flexible payload, which should be set by NVM.
 710  * This should be removed from code once it is fixed in NVM.
 711  */
 712 #ifndef I40E_GLQF_ORT
 713 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 714 #endif
 715 #ifndef I40E_GLQF_PIT
 716 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 717 #endif
 718
 719 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 720 {
 721         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 722         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 723         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 724         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 725         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 726         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 727         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 728         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 729         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 730         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 731
 732         /* GLQF_PIT Registers */
 733         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 734         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 735 }
 736
 737 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 738
 739 /*
 740  * Add a ethertype filter to drop all flow control frames transmitted
 741  * from VSIs.
 742 */
 743 static void
 744 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 745 {
 746         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 747         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 748                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 749                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 750         int ret;
 751
 752         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 753                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 754                                 pf->main_vsi_seid, 0,
 755                                 TRUE, NULL, NULL);
 756         if (ret)
 757                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 758                                   " frames from VSIs.");
 759 }
 760
 761 static int
 762 floating_veb_list_handler(__rte_unused const char *key,
 763                           const char *floating_veb_value,
 764                           void *opaque)
 765 {
 766         int idx = 0;
 767         unsigned int count = 0;
 768         char *end = NULL;
 769         int min, max;
 770         bool *vf_floating_veb = opaque;
 771
 772         while (isblank(*floating_veb_value))
 773                 floating_veb_value++;
 774
 775         /* Reset floating VEB configuration for VFs */
 776         for (idx = 0; idx < I40E_MAX_VF; idx++)
 777                 vf_floating_veb[idx] = false;
 778
 779         min = I40E_MAX_VF;
 780         do {
 781                 while (isblank(*floating_veb_value))
 782                         floating_veb_value++;
 783                 if (*floating_veb_value == '\0')
 784                         return -1;
 785                 errno = 0;
 786                 idx = strtoul(floating_veb_value, &end, 10);
 787                 if (errno || end == NULL)
 788                         return -1;
 789                 while (isblank(*end))
 790                         end++;
 791                 if (*end == '-') {
 792                         min = idx;
 793                 } else if ((*end == ';') || (*end == '\0')) {
 794                         max = idx;
 795                         if (min == I40E_MAX_VF)
 796                                 min = idx;
 797                         if (max >= I40E_MAX_VF)
 798                                 max = I40E_MAX_VF - 1;
 799                         for (idx = min; idx <= max; idx++) {
 800                                 vf_floating_veb[idx] = true;
 801                                 count++;
 802                         }
 803                         min = I40E_MAX_VF;
 804                 } else {
 805                         return -1;
 806                 }
 807                 floating_veb_value = end + 1;
 808         } while (*end != '\0');
 809
 810         if (count == 0)
 811                 return -1;
 812
 813         return 0;
 814 }
 815
 816 static void
 817 config_vf_floating_veb(struct rte_devargs *devargs,
 818                        uint16_t floating_veb,
 819                        bool *vf_floating_veb)
 820 {
 821         struct rte_kvargs *kvlist;
 822         int i;
 823         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 824
 825         if (!floating_veb)
 826                 return;
 827         /* All the VFs attach to the floating VEB by default
 828          * when the floating VEB is enabled.
 829          */
 830         for (i = 0; i < I40E_MAX_VF; i++)
 831                 vf_floating_veb[i] = true;
 832
 833         if (devargs == NULL)
 834                 return;
 835
 836         kvlist = rte_kvargs_parse(devargs->args, NULL);
 837         if (kvlist == NULL)
 838                 return;
 839
 840         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 841                 rte_kvargs_free(kvlist);
 842                 return;
 843         }
 844         /* When the floating_veb_list parameter exists, all the VFs
 845          * will attach to the legacy VEB firstly, then configure VFs
 846          * to the floating VEB according to the floating_veb_list.
 847          */
 848         if (rte_kvargs_process(kvlist, floating_veb_list,
 849                                floating_veb_list_handler,
 850                                vf_floating_veb) < 0) {
 851                 rte_kvargs_free(kvlist);
 852                 return;
 853         }
 854         rte_kvargs_free(kvlist);
 855 }
 856
 857 static int
 858 i40e_check_floating_handler(__rte_unused const char *key,
 859                             const char *value,
 860                             __rte_unused void *opaque)
 861 {
 862         if (strcmp(value, "1"))
 863                 return -1;
 864
 865         return 0;
 866 }
 867
 868 static int
 869 is_floating_veb_supported(struct rte_devargs *devargs)
 870 {
 871         struct rte_kvargs *kvlist;
 872         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 873
 874         if (devargs == NULL)
 875                 return 0;
 876
 877         kvlist = rte_kvargs_parse(devargs->args, NULL);
 878         if (kvlist == NULL)
 879                 return 0;
 880
 881         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 882                 rte_kvargs_free(kvlist);
 883                 return 0;
 884         }
 885         /* Floating VEB is enabled when there's key-value:
 886          * enable_floating_veb=1
 887          */
 888         if (rte_kvargs_process(kvlist, floating_veb_key,
 889                                i40e_check_floating_handler, NULL) < 0) {
 890                 rte_kvargs_free(kvlist);
 891                 return 0;
 892         }
 893         rte_kvargs_free(kvlist);
 894
 895         return 1;
 896 }
 897
 898 static void
 899 config_floating_veb(struct rte_eth_dev *dev)
 900 {
 901         struct rte_pci_device *pci_dev = dev->pci_dev;
 902         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 903         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 904
 905         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 906
 907         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 908                 pf->floating_veb = is_floating_veb_supported(pci_dev->devargs);
 909                 config_vf_floating_veb(pci_dev->devargs, pf->floating_veb,
 910                                        pf->floating_veb_list);
 911         } else {
 912                 pf->floating_veb = false;
 913         }
 914 }
 915
 916 static int
 917 eth_i40e_dev_init(struct rte_eth_dev *dev)
 918 {
 919         struct rte_pci_device *pci_dev;
 920         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 921         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 922         struct i40e_vsi *vsi;
 923         int ret;
 924         uint32_t len;
 925         uint8_t aq_fail = 0;
 926
 927         PMD_INIT_FUNC_TRACE();
 928
 929         dev->dev_ops = &i40e_eth_dev_ops;
 930         dev->rx_pkt_burst = i40e_recv_pkts;
 931         dev->tx_pkt_burst = i40e_xmit_pkts;
 932
 933         /* for secondary processes, we don't initialise any further as primary
 934          * has already done this work. Only check we don't need a different
 935          * RX function */
 936         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 937                 i40e_set_rx_function(dev);
 938                 i40e_set_tx_function(dev);
 939                 return 0;
 940         }
 941         pci_dev = dev->pci_dev;
 942
 943         rte_eth_copy_pci_info(dev, pci_dev);
 944
 945         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 946         pf->adapter->eth_dev = dev;
 947         pf->dev_data = dev->data;
 948
 949         hw->back = I40E_PF_TO_ADAPTER(pf);
 950         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 951         if (!hw->hw_addr) {
 952                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 953                              "as address is NULL");
 954                 return -ENODEV;
 955         }
 956
 957         hw->vendor_id = pci_dev->id.vendor_id;
 958         hw->device_id = pci_dev->id.device_id;
 959         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 960         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 961         hw->bus.device = pci_dev->addr.devid;
 962         hw->bus.func = pci_dev->addr.function;
 963         hw->adapter_stopped = 0;
 964
 965         /* Make sure all is clean before doing PF reset */
 966         i40e_clear_hw(hw);
 967
 968         /* Initialize the hardware */
 969         i40e_hw_init(dev);
 970
 971         /* Reset here to make sure all is clean for each PF */
 972         ret = i40e_pf_reset(hw);
 973         if (ret) {
 974                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 975                 return ret;
 976         }
 977
 978         /* Initialize the shared code (base driver) */
 979         ret = i40e_init_shared_code(hw);
 980         if (ret) {
 981                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 982                 return ret;
 983         }
 984
 985         /*
 986          * To work around the NVM issue,initialize registers
 987          * for flexible payload by software.
 988          * It should be removed once issues are fixed in NVM.
 989          */
 990         i40e_flex_payload_reg_init(hw);
 991
 992         /* Initialize the input set for filters (hash and fd) to default value */
 993         i40e_filter_input_set_init(pf);
 994
 995         /* Initialize the parameters for adminq */
 996         i40e_init_adminq_parameter(hw);
 997         ret = i40e_init_adminq(hw);
 998         if (ret != I40E_SUCCESS) {
 999                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1000                 return -EIO;
1001         }
1002         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1003                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1004                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1005                      ((hw->nvm.version >> 12) & 0xf),
1006                      ((hw->nvm.version >> 4) & 0xff),
1007                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1008
1009         /* Need the special FW version to support floating VEB */
1010         config_floating_veb(dev);
1011         /* Clear PXE mode */
1012         i40e_clear_pxe_mode(hw);
1013
1014         /*
1015          * On X710, performance number is far from the expectation on recent
1016          * firmware versions. The fix for this issue may not be integrated in
1017          * the following firmware version. So the workaround in software driver
1018          * is needed. It needs to modify the initial values of 3 internal only
1019          * registers. Note that the workaround can be removed when it is fixed
1020          * in firmware in the future.
1021          */
1022         i40e_configure_registers(hw);
1023
1024         /* Get hw capabilities */
1025         ret = i40e_get_cap(hw);
1026         if (ret != I40E_SUCCESS) {
1027                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1028                 goto err_get_capabilities;
1029         }
1030
1031         /* Initialize parameters for PF */
1032         ret = i40e_pf_parameter_init(dev);
1033         if (ret != 0) {
1034                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1035                 goto err_parameter_init;
1036         }
1037
1038         /* Initialize the queue management */
1039         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1040         if (ret < 0) {
1041                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1042                 goto err_qp_pool_init;
1043         }
1044         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1045                                 hw->func_caps.num_msix_vectors - 1);
1046         if (ret < 0) {
1047                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1048                 goto err_msix_pool_init;
1049         }
1050
1051         /* Initialize lan hmc */
1052         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1053                                 hw->func_caps.num_rx_qp, 0, 0);
1054         if (ret != I40E_SUCCESS) {
1055                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1056                 goto err_init_lan_hmc;
1057         }
1058
1059         /* Configure lan hmc */
1060         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1061         if (ret != I40E_SUCCESS) {
1062                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1063                 goto err_configure_lan_hmc;
1064         }
1065
1066         /* Get and check the mac address */
1067         i40e_get_mac_addr(hw, hw->mac.addr);
1068         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1069                 PMD_INIT_LOG(ERR, "mac address is not valid");
1070                 ret = -EIO;
1071                 goto err_get_mac_addr;
1072         }
1073         /* Copy the permanent MAC address */
1074         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1075                         (struct ether_addr *) hw->mac.perm_addr);
1076
1077         /* Disable flow control */
1078         hw->fc.requested_mode = I40E_FC_NONE;
1079         i40e_set_fc(hw, &aq_fail, TRUE);
1080
1081         /* Set the global registers with default ether type value */
1082         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1083         if (ret != I40E_SUCCESS) {
1084                 PMD_INIT_LOG(ERR, "Failed to set the default outer "
1085                              "VLAN ether type");
1086                 goto err_setup_pf_switch;
1087         }
1088
1089         /* PF setup, which includes VSI setup */
1090         ret = i40e_pf_setup(pf);
1091         if (ret) {
1092                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1093                 goto err_setup_pf_switch;
1094         }
1095
1096         /* reset all stats of the device, including pf and main vsi */
1097         i40e_dev_stats_reset(dev);
1098
1099         vsi = pf->main_vsi;
1100
1101         /* Disable double vlan by default */
1102         i40e_vsi_config_double_vlan(vsi, FALSE);
1103
1104         if (!vsi->max_macaddrs)
1105                 len = ETHER_ADDR_LEN;
1106         else
1107                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1108
1109         /* Should be after VSI initialized */
1110         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1111         if (!dev->data->mac_addrs) {
1112                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
1113                                         "for storing mac address");
1114                 goto err_mac_alloc;
1115         }
1116         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1117                                         &dev->data->mac_addrs[0]);
1118
1119         /* initialize pf host driver to setup SRIOV resource if applicable */
1120         i40e_pf_host_init(dev);
1121
1122         /* register callback func to eal lib */
1123         rte_intr_callback_register(&(pci_dev->intr_handle),
1124                 i40e_dev_interrupt_handler, (void *)dev);
1125
1126         /* configure and enable device interrupt */
1127         i40e_pf_config_irq0(hw, TRUE);
1128         i40e_pf_enable_irq0(hw);
1129
1130         /* enable uio intr after callback register */
1131         rte_intr_enable(&(pci_dev->intr_handle));
1132         /*
1133          * Add an ethertype filter to drop all flow control frames transmitted
1134          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1135          * frames to wire.
1136          */
1137         i40e_add_tx_flow_control_drop_filter(pf);
1138
1139         /* Set the max frame size to 0x2600 by default,
1140          * in case other drivers changed the default value.
1141          */
1142         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1143
1144         /* initialize mirror rule list */
1145         TAILQ_INIT(&pf->mirror_list);
1146
1147         /* Init dcb to sw mode by default */
1148         ret = i40e_dcb_init_configure(dev, TRUE);
1149         if (ret != I40E_SUCCESS) {
1150                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1151                 pf->flags &= ~I40E_FLAG_DCB;
1152         }
1153
1154         return 0;
1155
1156 err_mac_alloc:
1157         i40e_vsi_release(pf->main_vsi);
1158 err_setup_pf_switch:
1159 err_get_mac_addr:
1160 err_configure_lan_hmc:
1161         (void)i40e_shutdown_lan_hmc(hw);
1162 err_init_lan_hmc:
1163         i40e_res_pool_destroy(&pf->msix_pool);
1164 err_msix_pool_init:
1165         i40e_res_pool_destroy(&pf->qp_pool);
1166 err_qp_pool_init:
1167 err_parameter_init:
1168 err_get_capabilities:
1169         (void)i40e_shutdown_adminq(hw);
1170
1171         return ret;
1172 }
1173
1174 static int
1175 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1176 {
1177         struct rte_pci_device *pci_dev;
1178         struct i40e_hw *hw;
1179         struct i40e_filter_control_settings settings;
1180         int ret;
1181         uint8_t aq_fail = 0;
1182
1183         PMD_INIT_FUNC_TRACE();
1184
1185         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1186                 return 0;
1187
1188         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1189         pci_dev = dev->pci_dev;
1190
1191         if (hw->adapter_stopped == 0)
1192                 i40e_dev_close(dev);
1193
1194         dev->dev_ops = NULL;
1195         dev->rx_pkt_burst = NULL;
1196         dev->tx_pkt_burst = NULL;
1197
1198         /* Disable LLDP */
1199         ret = i40e_aq_stop_lldp(hw, true, NULL);
1200         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
1201                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
1202
1203         /* Clear PXE mode */
1204         i40e_clear_pxe_mode(hw);
1205
1206         /* Unconfigure filter control */
1207         memset(&settings, 0, sizeof(settings));
1208         ret = i40e_set_filter_control(hw, &settings);
1209         if (ret)
1210                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1211                                         ret);
1212
1213         /* Disable flow control */
1214         hw->fc.requested_mode = I40E_FC_NONE;
1215         i40e_set_fc(hw, &aq_fail, TRUE);
1216
1217         /* uninitialize pf host driver */
1218         i40e_pf_host_uninit(dev);
1219
1220         rte_free(dev->data->mac_addrs);
1221         dev->data->mac_addrs = NULL;
1222
1223         /* disable uio intr before callback unregister */
1224         rte_intr_disable(&(pci_dev->intr_handle));
1225
1226         /* register callback func to eal lib */
1227         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1228                 i40e_dev_interrupt_handler, (void *)dev);
1229
1230         return 0;
1231 }
1232
1233 static int
1234 i40e_dev_configure(struct rte_eth_dev *dev)
1235 {
1236         struct i40e_adapter *ad =
1237                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1238         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1239         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1240         int i, ret;
1241
1242         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1243          * bulk allocation or vector Rx preconditions we will reset it.
1244          */
1245         ad->rx_bulk_alloc_allowed = true;
1246         ad->rx_vec_allowed = true;
1247         ad->tx_simple_allowed = true;
1248         ad->tx_vec_allowed = true;
1249
1250         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1251                 ret = i40e_fdir_setup(pf);
1252                 if (ret != I40E_SUCCESS) {
1253                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1254                         return -ENOTSUP;
1255                 }
1256                 ret = i40e_fdir_configure(dev);
1257                 if (ret < 0) {
1258                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1259                         goto err;
1260                 }
1261         } else
1262                 i40e_fdir_teardown(pf);
1263
1264         ret = i40e_dev_init_vlan(dev);
1265         if (ret < 0)
1266                 goto err;
1267
1268         /* VMDQ setup.
1269          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1270          *  RSS setting have different requirements.
1271          *  General PMD driver call sequence are NIC init, configure,
1272          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1273          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1274          *  applicable. So, VMDQ setting has to be done before
1275          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1276          *  For RSS setting, it will try to calculate actual configured RX queue
1277          *  number, which will be available after rx_queue_setup(). dev_start()
1278          *  function is good to place RSS setup.
1279          */
1280         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1281                 ret = i40e_vmdq_setup(dev);
1282                 if (ret)
1283                         goto err;
1284         }
1285
1286         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1287                 ret = i40e_dcb_setup(dev);
1288                 if (ret) {
1289                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1290                         goto err_dcb;
1291                 }
1292         }
1293
1294         return 0;
1295
1296 err_dcb:
1297         /* need to release vmdq resource if exists */
1298         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1299                 i40e_vsi_release(pf->vmdq[i].vsi);
1300                 pf->vmdq[i].vsi = NULL;
1301         }
1302         rte_free(pf->vmdq);
1303         pf->vmdq = NULL;
1304 err:
1305         /* need to release fdir resource if exists */
1306         i40e_fdir_teardown(pf);
1307         return ret;
1308 }
1309
1310 void
1311 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1312 {
1313         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1314         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1315         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1316         uint16_t msix_vect = vsi->msix_intr;
1317         uint16_t i;
1318
1319         for (i = 0; i < vsi->nb_qps; i++) {
1320                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1321                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1322                 rte_wmb();
1323         }
1324
1325         if (vsi->type != I40E_VSI_SRIOV) {
1326                 if (!rte_intr_allow_others(intr_handle)) {
1327                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1328                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1329                         I40E_WRITE_REG(hw,
1330                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1331                                        0);
1332                 } else {
1333                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1334                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1335                         I40E_WRITE_REG(hw,
1336                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1337                                                        msix_vect - 1), 0);
1338                 }
1339         } else {
1340                 uint32_t reg;
1341                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1342                         vsi->user_param + (msix_vect - 1);
1343
1344                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1345                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1346         }
1347         I40E_WRITE_FLUSH(hw);
1348 }
1349
1350 static void
1351 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1352                        int base_queue, int nb_queue)
1353 {
1354         int i;
1355         uint32_t val;
1356         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1357
1358         /* Bind all RX queues to allocated MSIX interrupt */
1359         for (i = 0; i < nb_queue; i++) {
1360                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1361                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1362                         ((base_queue + i + 1) <<
1363                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1364                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1365                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1366
1367                 if (i == nb_queue - 1)
1368                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1369                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1370         }
1371
1372         /* Write first RX queue to Link list register as the head element */
1373         if (vsi->type != I40E_VSI_SRIOV) {
1374                 uint16_t interval =
1375                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1376
1377                 if (msix_vect == I40E_MISC_VEC_ID) {
1378                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1379                                        (base_queue <<
1380                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1381                                        (0x0 <<
1382                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1383                         I40E_WRITE_REG(hw,
1384                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1385                                        interval);
1386                 } else {
1387                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1388                                        (base_queue <<
1389                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1390                                        (0x0 <<
1391                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1392                         I40E_WRITE_REG(hw,
1393                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1394                                                        msix_vect - 1),
1395                                        interval);
1396                 }
1397         } else {
1398                 uint32_t reg;
1399
1400                 if (msix_vect == I40E_MISC_VEC_ID) {
1401                         I40E_WRITE_REG(hw,
1402                                        I40E_VPINT_LNKLST0(vsi->user_param),
1403                                        (base_queue <<
1404                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1405                                        (0x0 <<
1406                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1407                 } else {
1408                         /* num_msix_vectors_vf needs to minus irq0 */
1409                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1410                                 vsi->user_param + (msix_vect - 1);
1411
1412                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1413                                        (base_queue <<
1414                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1415                                        (0x0 <<
1416                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1417                 }
1418         }
1419
1420         I40E_WRITE_FLUSH(hw);
1421 }
1422
1423 void
1424 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1425 {
1426         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1427         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1428         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1429         uint16_t msix_vect = vsi->msix_intr;
1430         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1431         uint16_t queue_idx = 0;
1432         int record = 0;
1433         uint32_t val;
1434         int i;
1435
1436         for (i = 0; i < vsi->nb_qps; i++) {
1437                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1438                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1439         }
1440
1441         /* INTENA flag is not auto-cleared for interrupt */
1442         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1443         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1444                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1445                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1446         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1447
1448         /* VF bind interrupt */
1449         if (vsi->type == I40E_VSI_SRIOV) {
1450                 __vsi_queues_bind_intr(vsi, msix_vect,
1451                                        vsi->base_queue, vsi->nb_qps);
1452                 return;
1453         }
1454
1455         /* PF & VMDq bind interrupt */
1456         if (rte_intr_dp_is_en(intr_handle)) {
1457                 if (vsi->type == I40E_VSI_MAIN) {
1458                         queue_idx = 0;
1459                         record = 1;
1460                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1461                         struct i40e_vsi *main_vsi =
1462                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1463                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1464                         record = 1;
1465                 }
1466         }
1467
1468         for (i = 0; i < vsi->nb_used_qps; i++) {
1469                 if (nb_msix <= 1) {
1470                         if (!rte_intr_allow_others(intr_handle))
1471                                 /* allow to share MISC_VEC_ID */
1472                                 msix_vect = I40E_MISC_VEC_ID;
1473
1474                         /* no enough msix_vect, map all to one */
1475                         __vsi_queues_bind_intr(vsi, msix_vect,
1476                                                vsi->base_queue + i,
1477                                                vsi->nb_used_qps - i);
1478                         for (; !!record && i < vsi->nb_used_qps; i++)
1479                                 intr_handle->intr_vec[queue_idx + i] =
1480                                         msix_vect;
1481                         break;
1482                 }
1483                 /* 1:1 queue/msix_vect mapping */
1484                 __vsi_queues_bind_intr(vsi, msix_vect,
1485                                        vsi->base_queue + i, 1);
1486                 if (!!record)
1487                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1488
1489                 msix_vect++;
1490                 nb_msix--;
1491         }
1492 }
1493
1494 static void
1495 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1496 {
1497         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1498         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1499         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1500         uint16_t interval = i40e_calc_itr_interval(\
1501                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1502         uint16_t msix_intr, i;
1503
1504         if (rte_intr_allow_others(intr_handle))
1505                 for (i = 0; i < vsi->nb_msix; i++) {
1506                         msix_intr = vsi->msix_intr + i;
1507                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1508                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1509                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1510                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1511                                 (interval <<
1512                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1513                 }
1514         else
1515                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1516                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1517                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1518                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1519                                (interval <<
1520                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1521
1522         I40E_WRITE_FLUSH(hw);
1523 }
1524
1525 static void
1526 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1527 {
1528         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1529         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1530         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1531         uint16_t msix_intr, i;
1532
1533         if (rte_intr_allow_others(intr_handle))
1534                 for (i = 0; i < vsi->nb_msix; i++) {
1535                         msix_intr = vsi->msix_intr + i;
1536                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1537                                        0);
1538                 }
1539         else
1540                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1541
1542         I40E_WRITE_FLUSH(hw);
1543 }
1544
1545 static inline uint8_t
1546 i40e_parse_link_speeds(uint16_t link_speeds)
1547 {
1548         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1549
1550         if (link_speeds & ETH_LINK_SPEED_40G)
1551                 link_speed |= I40E_LINK_SPEED_40GB;
1552         if (link_speeds & ETH_LINK_SPEED_20G)
1553                 link_speed |= I40E_LINK_SPEED_20GB;
1554         if (link_speeds & ETH_LINK_SPEED_10G)
1555                 link_speed |= I40E_LINK_SPEED_10GB;
1556         if (link_speeds & ETH_LINK_SPEED_1G)
1557                 link_speed |= I40E_LINK_SPEED_1GB;
1558         if (link_speeds & ETH_LINK_SPEED_100M)
1559                 link_speed |= I40E_LINK_SPEED_100MB;
1560
1561         return link_speed;
1562 }
1563
1564 static int
1565 i40e_phy_conf_link(struct i40e_hw *hw,
1566                    uint8_t abilities,
1567                    uint8_t force_speed)
1568 {
1569         enum i40e_status_code status;
1570         struct i40e_aq_get_phy_abilities_resp phy_ab;
1571         struct i40e_aq_set_phy_config phy_conf;
1572         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1573                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1574                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1575                         I40E_AQ_PHY_FLAG_LOW_POWER;
1576         const uint8_t advt = I40E_LINK_SPEED_40GB |
1577                         I40E_LINK_SPEED_10GB |
1578                         I40E_LINK_SPEED_1GB |
1579                         I40E_LINK_SPEED_100MB;
1580         int ret = -ENOTSUP;
1581
1582
1583         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1584                                               NULL);
1585         if (status)
1586                 return ret;
1587
1588         memset(&phy_conf, 0, sizeof(phy_conf));
1589
1590         /* bits 0-2 use the values from get_phy_abilities_resp */
1591         abilities &= ~mask;
1592         abilities |= phy_ab.abilities & mask;
1593
1594         /* update ablities and speed */
1595         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1596                 phy_conf.link_speed = advt;
1597         else
1598                 phy_conf.link_speed = force_speed;
1599
1600         phy_conf.abilities = abilities;
1601
1602         /* use get_phy_abilities_resp value for the rest */
1603         phy_conf.phy_type = phy_ab.phy_type;
1604         phy_conf.eee_capability = phy_ab.eee_capability;
1605         phy_conf.eeer = phy_ab.eeer_val;
1606         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1607
1608         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1609                     phy_ab.abilities, phy_ab.link_speed);
1610         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1611                     phy_conf.abilities, phy_conf.link_speed);
1612
1613         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1614         if (status)
1615                 return ret;
1616
1617         return I40E_SUCCESS;
1618 }
1619
1620 static int
1621 i40e_apply_link_speed(struct rte_eth_dev *dev)
1622 {
1623         uint8_t speed;
1624         uint8_t abilities = 0;
1625         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1626         struct rte_eth_conf *conf = &dev->data->dev_conf;
1627
1628         speed = i40e_parse_link_speeds(conf->link_speeds);
1629         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1630         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1631                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1632         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1633
1634         /* Skip changing speed on 40G interfaces, FW does not support */
1635         if (i40e_is_40G_device(hw->device_id)) {
1636                 speed =  I40E_LINK_SPEED_UNKNOWN;
1637                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1638         }
1639
1640         return i40e_phy_conf_link(hw, abilities, speed);
1641 }
1642
1643 static int
1644 i40e_dev_start(struct rte_eth_dev *dev)
1645 {
1646         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1647         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1648         struct i40e_vsi *main_vsi = pf->main_vsi;
1649         int ret, i;
1650         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1651         uint32_t intr_vector = 0;
1652
1653         hw->adapter_stopped = 0;
1654
1655         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1656                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1657                              dev->data->port_id);
1658                 return -EINVAL;
1659         }
1660
1661         rte_intr_disable(intr_handle);
1662
1663         if ((rte_intr_cap_multiple(intr_handle) ||
1664              !RTE_ETH_DEV_SRIOV(dev).active) &&
1665             dev->data->dev_conf.intr_conf.rxq != 0) {
1666                 intr_vector = dev->data->nb_rx_queues;
1667                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1668                         return -1;
1669         }
1670
1671         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1672                 intr_handle->intr_vec =
1673                         rte_zmalloc("intr_vec",
1674                                     dev->data->nb_rx_queues * sizeof(int),
1675                                     0);
1676                 if (!intr_handle->intr_vec) {
1677                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1678                                      " intr_vec\n", dev->data->nb_rx_queues);
1679                         return -ENOMEM;
1680                 }
1681         }
1682
1683         /* Initialize VSI */
1684         ret = i40e_dev_rxtx_init(pf);
1685         if (ret != I40E_SUCCESS) {
1686                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1687                 goto err_up;
1688         }
1689
1690         /* Map queues with MSIX interrupt */
1691         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1692                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1693         i40e_vsi_queues_bind_intr(main_vsi);
1694         i40e_vsi_enable_queues_intr(main_vsi);
1695
1696         /* Map VMDQ VSI queues with MSIX interrupt */
1697         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1698                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1699                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1700                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1701         }
1702
1703         /* enable FDIR MSIX interrupt */
1704         if (pf->fdir.fdir_vsi) {
1705                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1706                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1707         }
1708
1709         /* Enable all queues which have been configured */
1710         ret = i40e_dev_switch_queues(pf, TRUE);
1711         if (ret != I40E_SUCCESS) {
1712                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1713                 goto err_up;
1714         }
1715
1716         /* Enable receiving broadcast packets */
1717         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1718         if (ret != I40E_SUCCESS)
1719                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1720
1721         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1722                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1723                                                 true, NULL);
1724                 if (ret != I40E_SUCCESS)
1725                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1726         }
1727
1728         /* Apply link configure */
1729         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1730                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1731                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_40G)) {
1732                 PMD_DRV_LOG(ERR, "Invalid link setting");
1733                 goto err_up;
1734         }
1735         ret = i40e_apply_link_speed(dev);
1736         if (I40E_SUCCESS != ret) {
1737                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1738                 goto err_up;
1739         }
1740
1741         if (!rte_intr_allow_others(intr_handle)) {
1742                 rte_intr_callback_unregister(intr_handle,
1743                                              i40e_dev_interrupt_handler,
1744                                              (void *)dev);
1745                 /* configure and enable device interrupt */
1746                 i40e_pf_config_irq0(hw, FALSE);
1747                 i40e_pf_enable_irq0(hw);
1748
1749                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1750                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1751                                      " no intr multiplex\n");
1752         }
1753
1754         /* enable uio intr after callback register */
1755         rte_intr_enable(intr_handle);
1756
1757         return I40E_SUCCESS;
1758
1759 err_up:
1760         i40e_dev_switch_queues(pf, FALSE);
1761         i40e_dev_clear_queues(dev);
1762
1763         return ret;
1764 }
1765
1766 static void
1767 i40e_dev_stop(struct rte_eth_dev *dev)
1768 {
1769         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1770         struct i40e_vsi *main_vsi = pf->main_vsi;
1771         struct i40e_mirror_rule *p_mirror;
1772         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1773         int i;
1774
1775         /* Disable all queues */
1776         i40e_dev_switch_queues(pf, FALSE);
1777
1778         /* un-map queues with interrupt registers */
1779         i40e_vsi_disable_queues_intr(main_vsi);
1780         i40e_vsi_queues_unbind_intr(main_vsi);
1781
1782         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1783                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1784                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1785         }
1786
1787         if (pf->fdir.fdir_vsi) {
1788                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1789                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1790         }
1791         /* Clear all queues and release memory */
1792         i40e_dev_clear_queues(dev);
1793
1794         /* Set link down */
1795         i40e_dev_set_link_down(dev);
1796
1797         /* Remove all mirror rules */
1798         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1799                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1800                 rte_free(p_mirror);
1801         }
1802         pf->nb_mirror_rule = 0;
1803
1804         if (!rte_intr_allow_others(intr_handle))
1805                 /* resume to the default handler */
1806                 rte_intr_callback_register(intr_handle,
1807                                            i40e_dev_interrupt_handler,
1808                                            (void *)dev);
1809
1810         /* Clean datapath event and queue/vec mapping */
1811         rte_intr_efd_disable(intr_handle);
1812         if (intr_handle->intr_vec) {
1813                 rte_free(intr_handle->intr_vec);
1814                 intr_handle->intr_vec = NULL;
1815         }
1816 }
1817
1818 static void
1819 i40e_dev_close(struct rte_eth_dev *dev)
1820 {
1821         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1822         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1823         uint32_t reg;
1824         int i;
1825
1826         PMD_INIT_FUNC_TRACE();
1827
1828         i40e_dev_stop(dev);
1829         hw->adapter_stopped = 1;
1830         i40e_dev_free_queues(dev);
1831
1832         /* Disable interrupt */
1833         i40e_pf_disable_irq0(hw);
1834         rte_intr_disable(&(dev->pci_dev->intr_handle));
1835
1836         /* shutdown and destroy the HMC */
1837         i40e_shutdown_lan_hmc(hw);
1838
1839         /* release all the existing VSIs and VEBs */
1840         i40e_fdir_teardown(pf);
1841         i40e_vsi_release(pf->main_vsi);
1842
1843         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1844                 i40e_vsi_release(pf->vmdq[i].vsi);
1845                 pf->vmdq[i].vsi = NULL;
1846         }
1847
1848         rte_free(pf->vmdq);
1849         pf->vmdq = NULL;
1850
1851         /* shutdown the adminq */
1852         i40e_aq_queue_shutdown(hw, true);
1853         i40e_shutdown_adminq(hw);
1854
1855         i40e_res_pool_destroy(&pf->qp_pool);
1856         i40e_res_pool_destroy(&pf->msix_pool);
1857
1858         /* force a PF reset to clean anything leftover */
1859         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1860         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1861                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1862         I40E_WRITE_FLUSH(hw);
1863 }
1864
1865 static void
1866 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1867 {
1868         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1869         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1870         struct i40e_vsi *vsi = pf->main_vsi;
1871         int status;
1872
1873         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1874                                                      true, NULL, true);
1875         if (status != I40E_SUCCESS)
1876                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1877
1878         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1879                                                         TRUE, NULL);
1880         if (status != I40E_SUCCESS)
1881                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1882
1883 }
1884
1885 static void
1886 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1887 {
1888         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1889         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1890         struct i40e_vsi *vsi = pf->main_vsi;
1891         int status;
1892
1893         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1894                                                      false, NULL, true);
1895         if (status != I40E_SUCCESS)
1896                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1897
1898         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1899                                                         false, NULL);
1900         if (status != I40E_SUCCESS)
1901                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1902 }
1903
1904 static void
1905 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1906 {
1907         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1908         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1909         struct i40e_vsi *vsi = pf->main_vsi;
1910         int ret;
1911
1912         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1913         if (ret != I40E_SUCCESS)
1914                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1915 }
1916
1917 static void
1918 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1919 {
1920         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1921         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1922         struct i40e_vsi *vsi = pf->main_vsi;
1923         int ret;
1924
1925         if (dev->data->promiscuous == 1)
1926                 return; /* must remain in all_multicast mode */
1927
1928         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1929                                 vsi->seid, FALSE, NULL);
1930         if (ret != I40E_SUCCESS)
1931                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1932 }
1933
1934 /*
1935  * Set device link up.
1936  */
1937 static int
1938 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1939 {
1940         /* re-apply link speed setting */
1941         return i40e_apply_link_speed(dev);
1942 }
1943
1944 /*
1945  * Set device link down.
1946  */
1947 static int
1948 i40e_dev_set_link_down(struct rte_eth_dev *dev)
1949 {
1950         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1951         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1952         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1953
1954         return i40e_phy_conf_link(hw, abilities, speed);
1955 }
1956
1957 int
1958 i40e_dev_link_update(struct rte_eth_dev *dev,
1959                      int wait_to_complete)
1960 {
1961 #define CHECK_INTERVAL 100  /* 100ms */
1962 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
1963         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1964         struct i40e_link_status link_status;
1965         struct rte_eth_link link, old;
1966         int status;
1967         unsigned rep_cnt = MAX_REPEAT_TIME;
1968
1969         memset(&link, 0, sizeof(link));
1970         memset(&old, 0, sizeof(old));
1971         memset(&link_status, 0, sizeof(link_status));
1972         rte_i40e_dev_atomic_read_link_status(dev, &old);
1973
1974         do {
1975                 /* Get link status information from hardware */
1976                 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1977                 if (status != I40E_SUCCESS) {
1978                         link.link_speed = ETH_SPEED_NUM_100M;
1979                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1980                         PMD_DRV_LOG(ERR, "Failed to get link info");
1981                         goto out;
1982                 }
1983
1984                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1985                 if (!wait_to_complete)
1986                         break;
1987
1988                 rte_delay_ms(CHECK_INTERVAL);
1989         } while (!link.link_status && rep_cnt--);
1990
1991         if (!link.link_status)
1992                 goto out;
1993
1994         /* i40e uses full duplex only */
1995         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1996
1997         /* Parse the link status */
1998         switch (link_status.link_speed) {
1999         case I40E_LINK_SPEED_100MB:
2000                 link.link_speed = ETH_SPEED_NUM_100M;
2001                 break;
2002         case I40E_LINK_SPEED_1GB:
2003                 link.link_speed = ETH_SPEED_NUM_1G;
2004                 break;
2005         case I40E_LINK_SPEED_10GB:
2006                 link.link_speed = ETH_SPEED_NUM_10G;
2007                 break;
2008         case I40E_LINK_SPEED_20GB:
2009                 link.link_speed = ETH_SPEED_NUM_20G;
2010                 break;
2011         case I40E_LINK_SPEED_40GB:
2012                 link.link_speed = ETH_SPEED_NUM_40G;
2013                 break;
2014         default:
2015                 link.link_speed = ETH_SPEED_NUM_100M;
2016                 break;
2017         }
2018
2019         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2020                         ETH_LINK_SPEED_FIXED);
2021
2022 out:
2023         rte_i40e_dev_atomic_write_link_status(dev, &link);
2024         if (link.link_status == old.link_status)
2025                 return -1;
2026
2027         return 0;
2028 }
2029
2030 /* Get all the statistics of a VSI */
2031 void
2032 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2033 {
2034         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2035         struct i40e_eth_stats *nes = &vsi->eth_stats;
2036         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2037         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2038
2039         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2040                             vsi->offset_loaded, &oes->rx_bytes,
2041                             &nes->rx_bytes);
2042         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2043                             vsi->offset_loaded, &oes->rx_unicast,
2044                             &nes->rx_unicast);
2045         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2046                             vsi->offset_loaded, &oes->rx_multicast,
2047                             &nes->rx_multicast);
2048         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2049                             vsi->offset_loaded, &oes->rx_broadcast,
2050                             &nes->rx_broadcast);
2051         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2052                             &oes->rx_discards, &nes->rx_discards);
2053         /* GLV_REPC not supported */
2054         /* GLV_RMPC not supported */
2055         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2056                             &oes->rx_unknown_protocol,
2057                             &nes->rx_unknown_protocol);
2058         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2059                             vsi->offset_loaded, &oes->tx_bytes,
2060                             &nes->tx_bytes);
2061         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2062                             vsi->offset_loaded, &oes->tx_unicast,
2063                             &nes->tx_unicast);
2064         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2065                             vsi->offset_loaded, &oes->tx_multicast,
2066                             &nes->tx_multicast);
2067         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2068                             vsi->offset_loaded,  &oes->tx_broadcast,
2069                             &nes->tx_broadcast);
2070         /* GLV_TDPC not supported */
2071         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2072                             &oes->tx_errors, &nes->tx_errors);
2073         vsi->offset_loaded = true;
2074
2075         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2076                     vsi->vsi_id);
2077         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2078         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2079         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2080         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2081         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2082         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2083                     nes->rx_unknown_protocol);
2084         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2085         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2086         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2087         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2088         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2089         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2090         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2091                     vsi->vsi_id);
2092 }
2093
2094 static void
2095 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2096 {
2097         unsigned int i;
2098         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2099         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2100
2101         /* Get statistics of struct i40e_eth_stats */
2102         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2103                             I40E_GLPRT_GORCL(hw->port),
2104                             pf->offset_loaded, &os->eth.rx_bytes,
2105                             &ns->eth.rx_bytes);
2106         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2107                             I40E_GLPRT_UPRCL(hw->port),
2108                             pf->offset_loaded, &os->eth.rx_unicast,
2109                             &ns->eth.rx_unicast);
2110         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2111                             I40E_GLPRT_MPRCL(hw->port),
2112                             pf->offset_loaded, &os->eth.rx_multicast,
2113                             &ns->eth.rx_multicast);
2114         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2115                             I40E_GLPRT_BPRCL(hw->port),
2116                             pf->offset_loaded, &os->eth.rx_broadcast,
2117                             &ns->eth.rx_broadcast);
2118         /* Workaround: CRC size should not be included in byte statistics,
2119          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2120          */
2121         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2122                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2123
2124         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2125                             pf->offset_loaded, &os->eth.rx_discards,
2126                             &ns->eth.rx_discards);
2127         /* GLPRT_REPC not supported */
2128         /* GLPRT_RMPC not supported */
2129         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2130                             pf->offset_loaded,
2131                             &os->eth.rx_unknown_protocol,
2132                             &ns->eth.rx_unknown_protocol);
2133         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2134                             I40E_GLPRT_GOTCL(hw->port),
2135                             pf->offset_loaded, &os->eth.tx_bytes,
2136                             &ns->eth.tx_bytes);
2137         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2138                             I40E_GLPRT_UPTCL(hw->port),
2139                             pf->offset_loaded, &os->eth.tx_unicast,
2140                             &ns->eth.tx_unicast);
2141         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2142                             I40E_GLPRT_MPTCL(hw->port),
2143                             pf->offset_loaded, &os->eth.tx_multicast,
2144                             &ns->eth.tx_multicast);
2145         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2146                             I40E_GLPRT_BPTCL(hw->port),
2147                             pf->offset_loaded, &os->eth.tx_broadcast,
2148                             &ns->eth.tx_broadcast);
2149         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2150                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2151         /* GLPRT_TEPC not supported */
2152
2153         /* additional port specific stats */
2154         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2155                             pf->offset_loaded, &os->tx_dropped_link_down,
2156                             &ns->tx_dropped_link_down);
2157         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2158                             pf->offset_loaded, &os->crc_errors,
2159                             &ns->crc_errors);
2160         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2161                             pf->offset_loaded, &os->illegal_bytes,
2162                             &ns->illegal_bytes);
2163         /* GLPRT_ERRBC not supported */
2164         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2165                             pf->offset_loaded, &os->mac_local_faults,
2166                             &ns->mac_local_faults);
2167         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2168                             pf->offset_loaded, &os->mac_remote_faults,
2169                             &ns->mac_remote_faults);
2170         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2171                             pf->offset_loaded, &os->rx_length_errors,
2172                             &ns->rx_length_errors);
2173         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2174                             pf->offset_loaded, &os->link_xon_rx,
2175                             &ns->link_xon_rx);
2176         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2177                             pf->offset_loaded, &os->link_xoff_rx,
2178                             &ns->link_xoff_rx);
2179         for (i = 0; i < 8; i++) {
2180                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2181                                     pf->offset_loaded,
2182                                     &os->priority_xon_rx[i],
2183                                     &ns->priority_xon_rx[i]);
2184                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2185                                     pf->offset_loaded,
2186                                     &os->priority_xoff_rx[i],
2187                                     &ns->priority_xoff_rx[i]);
2188         }
2189         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2190                             pf->offset_loaded, &os->link_xon_tx,
2191                             &ns->link_xon_tx);
2192         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2193                             pf->offset_loaded, &os->link_xoff_tx,
2194                             &ns->link_xoff_tx);
2195         for (i = 0; i < 8; i++) {
2196                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2197                                     pf->offset_loaded,
2198                                     &os->priority_xon_tx[i],
2199                                     &ns->priority_xon_tx[i]);
2200                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2201                                     pf->offset_loaded,
2202                                     &os->priority_xoff_tx[i],
2203                                     &ns->priority_xoff_tx[i]);
2204                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2205                                     pf->offset_loaded,
2206                                     &os->priority_xon_2_xoff[i],
2207                                     &ns->priority_xon_2_xoff[i]);
2208         }
2209         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2210                             I40E_GLPRT_PRC64L(hw->port),
2211                             pf->offset_loaded, &os->rx_size_64,
2212                             &ns->rx_size_64);
2213         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2214                             I40E_GLPRT_PRC127L(hw->port),
2215                             pf->offset_loaded, &os->rx_size_127,
2216                             &ns->rx_size_127);
2217         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2218                             I40E_GLPRT_PRC255L(hw->port),
2219                             pf->offset_loaded, &os->rx_size_255,
2220                             &ns->rx_size_255);
2221         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2222                             I40E_GLPRT_PRC511L(hw->port),
2223                             pf->offset_loaded, &os->rx_size_511,
2224                             &ns->rx_size_511);
2225         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2226                             I40E_GLPRT_PRC1023L(hw->port),
2227                             pf->offset_loaded, &os->rx_size_1023,
2228                             &ns->rx_size_1023);
2229         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2230                             I40E_GLPRT_PRC1522L(hw->port),
2231                             pf->offset_loaded, &os->rx_size_1522,
2232                             &ns->rx_size_1522);
2233         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2234                             I40E_GLPRT_PRC9522L(hw->port),
2235                             pf->offset_loaded, &os->rx_size_big,
2236                             &ns->rx_size_big);
2237         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2238                             pf->offset_loaded, &os->rx_undersize,
2239                             &ns->rx_undersize);
2240         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2241                             pf->offset_loaded, &os->rx_fragments,
2242                             &ns->rx_fragments);
2243         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2244                             pf->offset_loaded, &os->rx_oversize,
2245                             &ns->rx_oversize);
2246         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2247                             pf->offset_loaded, &os->rx_jabber,
2248                             &ns->rx_jabber);
2249         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2250                             I40E_GLPRT_PTC64L(hw->port),
2251                             pf->offset_loaded, &os->tx_size_64,
2252                             &ns->tx_size_64);
2253         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2254                             I40E_GLPRT_PTC127L(hw->port),
2255                             pf->offset_loaded, &os->tx_size_127,
2256                             &ns->tx_size_127);
2257         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2258                             I40E_GLPRT_PTC255L(hw->port),
2259                             pf->offset_loaded, &os->tx_size_255,
2260                             &ns->tx_size_255);
2261         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2262                             I40E_GLPRT_PTC511L(hw->port),
2263                             pf->offset_loaded, &os->tx_size_511,
2264                             &ns->tx_size_511);
2265         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2266                             I40E_GLPRT_PTC1023L(hw->port),
2267                             pf->offset_loaded, &os->tx_size_1023,
2268                             &ns->tx_size_1023);
2269         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2270                             I40E_GLPRT_PTC1522L(hw->port),
2271                             pf->offset_loaded, &os->tx_size_1522,
2272                             &ns->tx_size_1522);
2273         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2274                             I40E_GLPRT_PTC9522L(hw->port),
2275                             pf->offset_loaded, &os->tx_size_big,
2276                             &ns->tx_size_big);
2277         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2278                            pf->offset_loaded,
2279                            &os->fd_sb_match, &ns->fd_sb_match);
2280         /* GLPRT_MSPDC not supported */
2281         /* GLPRT_XEC not supported */
2282
2283         pf->offset_loaded = true;
2284
2285         if (pf->main_vsi)
2286                 i40e_update_vsi_stats(pf->main_vsi);
2287 }
2288
2289 /* Get all statistics of a port */
2290 static void
2291 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2292 {
2293         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2294         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2295         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2296         unsigned i;
2297
2298         /* call read registers - updates values, now write them to struct */
2299         i40e_read_stats_registers(pf, hw);
2300
2301         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2302                         pf->main_vsi->eth_stats.rx_multicast +
2303                         pf->main_vsi->eth_stats.rx_broadcast -
2304                         pf->main_vsi->eth_stats.rx_discards;
2305         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2306                         pf->main_vsi->eth_stats.tx_multicast +
2307                         pf->main_vsi->eth_stats.tx_broadcast;
2308         stats->ibytes   = ns->eth.rx_bytes;
2309         stats->obytes   = ns->eth.tx_bytes;
2310         stats->oerrors  = ns->eth.tx_errors +
2311                         pf->main_vsi->eth_stats.tx_errors;
2312
2313         /* Rx Errors */
2314         stats->imissed  = ns->eth.rx_discards +
2315                         pf->main_vsi->eth_stats.rx_discards;
2316         stats->ierrors  = ns->crc_errors +
2317                         ns->rx_length_errors + ns->rx_undersize +
2318                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2319
2320         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2321         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2322         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2323         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2324         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2325         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2326         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2327                     ns->eth.rx_unknown_protocol);
2328         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2329         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2330         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2331         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2332         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2333         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2334
2335         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2336                     ns->tx_dropped_link_down);
2337         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2338         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2339                     ns->illegal_bytes);
2340         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2341         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2342                     ns->mac_local_faults);
2343         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2344                     ns->mac_remote_faults);
2345         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2346                     ns->rx_length_errors);
2347         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2348         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2349         for (i = 0; i < 8; i++) {
2350                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2351                                 i, ns->priority_xon_rx[i]);
2352                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2353                                 i, ns->priority_xoff_rx[i]);
2354         }
2355         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2356         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2357         for (i = 0; i < 8; i++) {
2358                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2359                                 i, ns->priority_xon_tx[i]);
2360                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2361                                 i, ns->priority_xoff_tx[i]);
2362                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2363                                 i, ns->priority_xon_2_xoff[i]);
2364         }
2365         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2366         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2367         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2368         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2369         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2370         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2371         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2372         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2373         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2374         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2375         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2376         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2377         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2378         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2379         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2380         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2381         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2382         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2383         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2384                         ns->mac_short_packet_dropped);
2385         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2386                     ns->checksum_error);
2387         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2388         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2389 }
2390
2391 /* Reset the statistics */
2392 static void
2393 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2394 {
2395         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2396         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2397
2398         /* Mark PF and VSI stats to update the offset, aka "reset" */
2399         pf->offset_loaded = false;
2400         if (pf->main_vsi)
2401                 pf->main_vsi->offset_loaded = false;
2402
2403         /* read the stats, reading current register values into offset */
2404         i40e_read_stats_registers(pf, hw);
2405 }
2406
2407 static uint32_t
2408 i40e_xstats_calc_num(void)
2409 {
2410         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2411                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2412                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2413 }
2414
2415 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2416                                      struct rte_eth_xstat_name *xstats_names,
2417                                      __rte_unused unsigned limit)
2418 {
2419         unsigned count = 0;
2420         unsigned i, prio;
2421
2422         if (xstats_names == NULL)
2423                 return i40e_xstats_calc_num();
2424
2425         /* Note: limit checked in rte_eth_xstats_names() */
2426
2427         /* Get stats from i40e_eth_stats struct */
2428         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2429                 snprintf(xstats_names[count].name,
2430                          sizeof(xstats_names[count].name),
2431                          "%s", rte_i40e_stats_strings[i].name);
2432                 count++;
2433         }
2434
2435         /* Get individiual stats from i40e_hw_port struct */
2436         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2437                 snprintf(xstats_names[count].name,
2438                         sizeof(xstats_names[count].name),
2439                          "%s", rte_i40e_hw_port_strings[i].name);
2440                 count++;
2441         }
2442
2443         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2444                 for (prio = 0; prio < 8; prio++) {
2445                         snprintf(xstats_names[count].name,
2446                                  sizeof(xstats_names[count].name),
2447                                  "rx_priority%u_%s", prio,
2448                                  rte_i40e_rxq_prio_strings[i].name);
2449                         count++;
2450                 }
2451         }
2452
2453         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2454                 for (prio = 0; prio < 8; prio++) {
2455                         snprintf(xstats_names[count].name,
2456                                  sizeof(xstats_names[count].name),
2457                                  "tx_priority%u_%s", prio,
2458                                  rte_i40e_txq_prio_strings[i].name);
2459                         count++;
2460                 }
2461         }
2462         return count;
2463 }
2464
2465 static int
2466 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2467                     unsigned n)
2468 {
2469         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2470         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2471         unsigned i, count, prio;
2472         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2473
2474         count = i40e_xstats_calc_num();
2475         if (n < count)
2476                 return count;
2477
2478         i40e_read_stats_registers(pf, hw);
2479
2480         if (xstats == NULL)
2481                 return 0;
2482
2483         count = 0;
2484
2485         /* Get stats from i40e_eth_stats struct */
2486         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2487                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2488                         rte_i40e_stats_strings[i].offset);
2489                 count++;
2490         }
2491
2492         /* Get individiual stats from i40e_hw_port struct */
2493         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2494                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2495                         rte_i40e_hw_port_strings[i].offset);
2496                 count++;
2497         }
2498
2499         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2500                 for (prio = 0; prio < 8; prio++) {
2501                         xstats[count].value =
2502                                 *(uint64_t *)(((char *)hw_stats) +
2503                                 rte_i40e_rxq_prio_strings[i].offset +
2504                                 (sizeof(uint64_t) * prio));
2505                         count++;
2506                 }
2507         }
2508
2509         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2510                 for (prio = 0; prio < 8; prio++) {
2511                         xstats[count].value =
2512                                 *(uint64_t *)(((char *)hw_stats) +
2513                                 rte_i40e_txq_prio_strings[i].offset +
2514                                 (sizeof(uint64_t) * prio));
2515                         count++;
2516                 }
2517         }
2518
2519         return count;
2520 }
2521
2522 static int
2523 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2524                                  __rte_unused uint16_t queue_id,
2525                                  __rte_unused uint8_t stat_idx,
2526                                  __rte_unused uint8_t is_rx)
2527 {
2528         PMD_INIT_FUNC_TRACE();
2529
2530         return -ENOSYS;
2531 }
2532
2533 static void
2534 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2535 {
2536         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2537         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2538         struct i40e_vsi *vsi = pf->main_vsi;
2539
2540         dev_info->max_rx_queues = vsi->nb_qps;
2541         dev_info->max_tx_queues = vsi->nb_qps;
2542         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2543         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2544         dev_info->max_mac_addrs = vsi->max_macaddrs;
2545         dev_info->max_vfs = dev->pci_dev->max_vfs;
2546         dev_info->rx_offload_capa =
2547                 DEV_RX_OFFLOAD_VLAN_STRIP |
2548                 DEV_RX_OFFLOAD_QINQ_STRIP |
2549                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2550                 DEV_RX_OFFLOAD_UDP_CKSUM |
2551                 DEV_RX_OFFLOAD_TCP_CKSUM;
2552         dev_info->tx_offload_capa =
2553                 DEV_TX_OFFLOAD_VLAN_INSERT |
2554                 DEV_TX_OFFLOAD_QINQ_INSERT |
2555                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2556                 DEV_TX_OFFLOAD_UDP_CKSUM |
2557                 DEV_TX_OFFLOAD_TCP_CKSUM |
2558                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2559                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2560                 DEV_TX_OFFLOAD_TCP_TSO;
2561         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2562                                                 sizeof(uint32_t);
2563         dev_info->reta_size = pf->hash_lut_size;
2564         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2565
2566         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2567                 .rx_thresh = {
2568                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2569                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2570                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2571                 },
2572                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2573                 .rx_drop_en = 0,
2574         };
2575
2576         dev_info->default_txconf = (struct rte_eth_txconf) {
2577                 .tx_thresh = {
2578                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2579                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2580                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2581                 },
2582                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2583                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2584                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2585                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2586         };
2587
2588         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2589                 .nb_max = I40E_MAX_RING_DESC,
2590                 .nb_min = I40E_MIN_RING_DESC,
2591                 .nb_align = I40E_ALIGN_RING_DESC,
2592         };
2593
2594         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2595                 .nb_max = I40E_MAX_RING_DESC,
2596                 .nb_min = I40E_MIN_RING_DESC,
2597                 .nb_align = I40E_ALIGN_RING_DESC,
2598         };
2599
2600         if (pf->flags & I40E_FLAG_VMDQ) {
2601                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2602                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2603                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2604                                                 pf->max_nb_vmdq_vsi;
2605                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2606                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2607                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2608         }
2609
2610         if (i40e_is_40G_device(hw->device_id))
2611                 /* For XL710 */
2612                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2613         else
2614                 /* For X710 */
2615                 dev_info->speed_capa = ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G;
2616 }
2617
2618 static int
2619 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2620 {
2621         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2622         struct i40e_vsi *vsi = pf->main_vsi;
2623         PMD_INIT_FUNC_TRACE();
2624
2625         if (on)
2626                 return i40e_vsi_add_vlan(vsi, vlan_id);
2627         else
2628                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2629 }
2630
2631 static int
2632 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2633                    enum rte_vlan_type vlan_type,
2634                    uint16_t tpid)
2635 {
2636         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2637         uint64_t reg_r = 0, reg_w = 0;
2638         uint16_t reg_id = 0;
2639         int ret = 0;
2640         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2641
2642         switch (vlan_type) {
2643         case ETH_VLAN_TYPE_OUTER:
2644                 if (qinq)
2645                         reg_id = 2;
2646                 else
2647                         reg_id = 3;
2648                 break;
2649         case ETH_VLAN_TYPE_INNER:
2650                 if (qinq)
2651                         reg_id = 3;
2652                 else {
2653                         ret = -EINVAL;
2654                         PMD_DRV_LOG(ERR,
2655                                 "Unsupported vlan type in single vlan.\n");
2656                         return ret;
2657                 }
2658                 break;
2659         default:
2660                 ret = -EINVAL;
2661                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2662                 return ret;
2663         }
2664         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2665                                           &reg_r, NULL);
2666         if (ret != I40E_SUCCESS) {
2667                 PMD_DRV_LOG(ERR, "Fail to debug read from "
2668                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2669                 ret = -EIO;
2670                 return ret;
2671         }
2672         PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2673                     "0x%08"PRIx64"", reg_id, reg_r);
2674
2675         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2676         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2677         if (reg_r == reg_w) {
2678                 ret = 0;
2679                 PMD_DRV_LOG(DEBUG, "No need to write");
2680                 return ret;
2681         }
2682
2683         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2684                                            reg_w, NULL);
2685         if (ret != I40E_SUCCESS) {
2686                 ret = -EIO;
2687                 PMD_DRV_LOG(ERR, "Fail to debug write to "
2688                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2689                 return ret;
2690         }
2691         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2692                     "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2693
2694         return ret;
2695 }
2696
2697 static void
2698 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2699 {
2700         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2701         struct i40e_vsi *vsi = pf->main_vsi;
2702
2703         if (mask & ETH_VLAN_FILTER_MASK) {
2704                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2705                         i40e_vsi_config_vlan_filter(vsi, TRUE);
2706                 else
2707                         i40e_vsi_config_vlan_filter(vsi, FALSE);
2708         }
2709
2710         if (mask & ETH_VLAN_STRIP_MASK) {
2711                 /* Enable or disable VLAN stripping */
2712                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2713                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
2714                 else
2715                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
2716         }
2717
2718         if (mask & ETH_VLAN_EXTEND_MASK) {
2719                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
2720                         i40e_vsi_config_double_vlan(vsi, TRUE);
2721                         /* Set global registers with default ether type value */
2722                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
2723                                            ETHER_TYPE_VLAN);
2724                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
2725                                            ETHER_TYPE_VLAN);
2726                 }
2727                 else
2728                         i40e_vsi_config_double_vlan(vsi, FALSE);
2729         }
2730 }
2731
2732 static void
2733 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2734                           __rte_unused uint16_t queue,
2735                           __rte_unused int on)
2736 {
2737         PMD_INIT_FUNC_TRACE();
2738 }
2739
2740 static int
2741 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2742 {
2743         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2744         struct i40e_vsi *vsi = pf->main_vsi;
2745         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2746         struct i40e_vsi_vlan_pvid_info info;
2747
2748         memset(&info, 0, sizeof(info));
2749         info.on = on;
2750         if (info.on)
2751                 info.config.pvid = pvid;
2752         else {
2753                 info.config.reject.tagged =
2754                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
2755                 info.config.reject.untagged =
2756                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
2757         }
2758
2759         return i40e_vsi_vlan_pvid_set(vsi, &info);
2760 }
2761
2762 static int
2763 i40e_dev_led_on(struct rte_eth_dev *dev)
2764 {
2765         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2766         uint32_t mode = i40e_led_get(hw);
2767
2768         if (mode == 0)
2769                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2770
2771         return 0;
2772 }
2773
2774 static int
2775 i40e_dev_led_off(struct rte_eth_dev *dev)
2776 {
2777         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2778         uint32_t mode = i40e_led_get(hw);
2779
2780         if (mode != 0)
2781                 i40e_led_set(hw, 0, false);
2782
2783         return 0;
2784 }
2785
2786 static int
2787 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2788 {
2789         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2790         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2791
2792         fc_conf->pause_time = pf->fc_conf.pause_time;
2793         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2794         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2795
2796          /* Return current mode according to actual setting*/
2797         switch (hw->fc.current_mode) {
2798         case I40E_FC_FULL:
2799                 fc_conf->mode = RTE_FC_FULL;
2800                 break;
2801         case I40E_FC_TX_PAUSE:
2802                 fc_conf->mode = RTE_FC_TX_PAUSE;
2803                 break;
2804         case I40E_FC_RX_PAUSE:
2805                 fc_conf->mode = RTE_FC_RX_PAUSE;
2806                 break;
2807         case I40E_FC_NONE:
2808         default:
2809                 fc_conf->mode = RTE_FC_NONE;
2810         };
2811
2812         return 0;
2813 }
2814
2815 static int
2816 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2817 {
2818         uint32_t mflcn_reg, fctrl_reg, reg;
2819         uint32_t max_high_water;
2820         uint8_t i, aq_failure;
2821         int err;
2822         struct i40e_hw *hw;
2823         struct i40e_pf *pf;
2824         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2825                 [RTE_FC_NONE] = I40E_FC_NONE,
2826                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2827                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2828                 [RTE_FC_FULL] = I40E_FC_FULL
2829         };
2830
2831         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2832
2833         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2834         if ((fc_conf->high_water > max_high_water) ||
2835                         (fc_conf->high_water < fc_conf->low_water)) {
2836                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2837                         "High_water must <= %d.", max_high_water);
2838                 return -EINVAL;
2839         }
2840
2841         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2842         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2843         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2844
2845         pf->fc_conf.pause_time = fc_conf->pause_time;
2846         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2847         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2848
2849         PMD_INIT_FUNC_TRACE();
2850
2851         /* All the link flow control related enable/disable register
2852          * configuration is handle by the F/W
2853          */
2854         err = i40e_set_fc(hw, &aq_failure, true);
2855         if (err < 0)
2856                 return -ENOSYS;
2857
2858         if (i40e_is_40G_device(hw->device_id)) {
2859                 /* Configure flow control refresh threshold,
2860                  * the value for stat_tx_pause_refresh_timer[8]
2861                  * is used for global pause operation.
2862                  */
2863
2864                 I40E_WRITE_REG(hw,
2865                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2866                                pf->fc_conf.pause_time);
2867
2868                 /* configure the timer value included in transmitted pause
2869                  * frame,
2870                  * the value for stat_tx_pause_quanta[8] is used for global
2871                  * pause operation
2872                  */
2873                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2874                                pf->fc_conf.pause_time);
2875
2876                 fctrl_reg = I40E_READ_REG(hw,
2877                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2878
2879                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2880                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2881                 else
2882                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2883
2884                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2885                                fctrl_reg);
2886         } else {
2887                 /* Configure pause time (2 TCs per register) */
2888                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2889                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2890                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2891
2892                 /* Configure flow control refresh threshold value */
2893                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2894                                pf->fc_conf.pause_time / 2);
2895
2896                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2897
2898                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2899                  *depending on configuration
2900                  */
2901                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2902                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2903                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2904                 } else {
2905                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2906                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2907                 }
2908
2909                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2910         }
2911
2912         /* config the water marker both based on the packets and bytes */
2913         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2914                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2915                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2916         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2917                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2918                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2919         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2920                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2921                        << I40E_KILOSHIFT);
2922         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2923                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2924                        << I40E_KILOSHIFT);
2925
2926         I40E_WRITE_FLUSH(hw);
2927
2928         return 0;
2929 }
2930
2931 static int
2932 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2933                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2934 {
2935         PMD_INIT_FUNC_TRACE();
2936
2937         return -ENOSYS;
2938 }
2939
2940 /* Add a MAC address, and update filters */
2941 static void
2942 i40e_macaddr_add(struct rte_eth_dev *dev,
2943                  struct ether_addr *mac_addr,
2944                  __rte_unused uint32_t index,
2945                  uint32_t pool)
2946 {
2947         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2948         struct i40e_mac_filter_info mac_filter;
2949         struct i40e_vsi *vsi;
2950         int ret;
2951
2952         /* If VMDQ not enabled or configured, return */
2953         if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
2954                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2955                         pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
2956                         pool);
2957                 return;
2958         }
2959
2960         if (pool > pf->nb_cfg_vmdq_vsi) {
2961                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2962                                 pool, pf->nb_cfg_vmdq_vsi);
2963                 return;
2964         }
2965
2966         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2967         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2968                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2969         else
2970                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
2971
2972         if (pool == 0)
2973                 vsi = pf->main_vsi;
2974         else
2975                 vsi = pf->vmdq[pool - 1].vsi;
2976
2977         ret = i40e_vsi_add_mac(vsi, &mac_filter);
2978         if (ret != I40E_SUCCESS) {
2979                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2980                 return;
2981         }
2982 }
2983
2984 /* Remove a MAC address, and update filters */
2985 static void
2986 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2987 {
2988         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2989         struct i40e_vsi *vsi;
2990         struct rte_eth_dev_data *data = dev->data;
2991         struct ether_addr *macaddr;
2992         int ret;
2993         uint32_t i;
2994         uint64_t pool_sel;
2995
2996         macaddr = &(data->mac_addrs[index]);
2997
2998         pool_sel = dev->data->mac_pool_sel[index];
2999
3000         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3001                 if (pool_sel & (1ULL << i)) {
3002                         if (i == 0)
3003                                 vsi = pf->main_vsi;
3004                         else {
3005                                 /* No VMDQ pool enabled or configured */
3006                                 if (!(pf->flags | I40E_FLAG_VMDQ) ||
3007                                         (i > pf->nb_cfg_vmdq_vsi)) {
3008                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
3009                                                         "/configured");
3010                                         return;
3011                                 }
3012                                 vsi = pf->vmdq[i - 1].vsi;
3013                         }
3014                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3015
3016                         if (ret) {
3017                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3018                                 return;
3019                         }
3020                 }
3021         }
3022 }
3023
3024 /* Set perfect match or hash match of MAC and VLAN for a VF */
3025 static int
3026 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3027                  struct rte_eth_mac_filter *filter,
3028                  bool add)
3029 {
3030         struct i40e_hw *hw;
3031         struct i40e_mac_filter_info mac_filter;
3032         struct ether_addr old_mac;
3033         struct ether_addr *new_mac;
3034         struct i40e_pf_vf *vf = NULL;
3035         uint16_t vf_id;
3036         int ret;
3037
3038         if (pf == NULL) {
3039                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3040                 return -EINVAL;
3041         }
3042         hw = I40E_PF_TO_HW(pf);
3043
3044         if (filter == NULL) {
3045                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3046                 return -EINVAL;
3047         }
3048
3049         new_mac = &filter->mac_addr;
3050
3051         if (is_zero_ether_addr(new_mac)) {
3052                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3053                 return -EINVAL;
3054         }
3055
3056         vf_id = filter->dst_id;
3057
3058         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3059                 PMD_DRV_LOG(ERR, "Invalid argument.");
3060                 return -EINVAL;
3061         }
3062         vf = &pf->vfs[vf_id];
3063
3064         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3065                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3066                 return -EINVAL;
3067         }
3068
3069         if (add) {
3070                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3071                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3072                                 ETHER_ADDR_LEN);
3073                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3074                                  ETHER_ADDR_LEN);
3075
3076                 mac_filter.filter_type = filter->filter_type;
3077                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3078                 if (ret != I40E_SUCCESS) {
3079                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3080                         return -1;
3081                 }
3082                 ether_addr_copy(new_mac, &pf->dev_addr);
3083         } else {
3084                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3085                                 ETHER_ADDR_LEN);
3086                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3087                 if (ret != I40E_SUCCESS) {
3088                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3089                         return -1;
3090                 }
3091
3092                 /* Clear device address as it has been removed */
3093                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3094                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3095         }
3096
3097         return 0;
3098 }
3099
3100 /* MAC filter handle */
3101 static int
3102 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3103                 void *arg)
3104 {
3105         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3106         struct rte_eth_mac_filter *filter;
3107         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3108         int ret = I40E_NOT_SUPPORTED;
3109
3110         filter = (struct rte_eth_mac_filter *)(arg);
3111
3112         switch (filter_op) {
3113         case RTE_ETH_FILTER_NOP:
3114                 ret = I40E_SUCCESS;
3115                 break;
3116         case RTE_ETH_FILTER_ADD:
3117                 i40e_pf_disable_irq0(hw);
3118                 if (filter->is_vf)
3119                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3120                 i40e_pf_enable_irq0(hw);
3121                 break;
3122         case RTE_ETH_FILTER_DELETE:
3123                 i40e_pf_disable_irq0(hw);
3124                 if (filter->is_vf)
3125                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3126                 i40e_pf_enable_irq0(hw);
3127                 break;
3128         default:
3129                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3130                 ret = I40E_ERR_PARAM;
3131                 break;
3132         }
3133
3134         return ret;
3135 }
3136
3137 static int
3138 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3139 {
3140         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3141         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3142         int ret;
3143
3144         if (!lut)
3145                 return -EINVAL;
3146
3147         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3148                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3149                                           lut, lut_size);
3150                 if (ret) {
3151                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3152                         return ret;
3153                 }
3154         } else {
3155                 uint32_t *lut_dw = (uint32_t *)lut;
3156                 uint16_t i, lut_size_dw = lut_size / 4;
3157
3158                 for (i = 0; i < lut_size_dw; i++)
3159                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3160         }
3161
3162         return 0;
3163 }
3164
3165 static int
3166 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3167 {
3168         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3169         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3170         int ret;
3171
3172         if (!vsi || !lut)
3173                 return -EINVAL;
3174
3175         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3176                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3177                                           lut, lut_size);
3178                 if (ret) {
3179                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3180                         return ret;
3181                 }
3182         } else {
3183                 uint32_t *lut_dw = (uint32_t *)lut;
3184                 uint16_t i, lut_size_dw = lut_size / 4;
3185
3186                 for (i = 0; i < lut_size_dw; i++)
3187                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3188                 I40E_WRITE_FLUSH(hw);
3189         }
3190
3191         return 0;
3192 }
3193
3194 static int
3195 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3196                          struct rte_eth_rss_reta_entry64 *reta_conf,
3197                          uint16_t reta_size)
3198 {
3199         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3200         uint16_t i, lut_size = pf->hash_lut_size;
3201         uint16_t idx, shift;
3202         uint8_t *lut;
3203         int ret;
3204
3205         if (reta_size != lut_size ||
3206                 reta_size > ETH_RSS_RETA_SIZE_512) {
3207                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3208                         "(%d) doesn't match the number hardware can supported "
3209                                         "(%d)\n", reta_size, lut_size);
3210                 return -EINVAL;
3211         }
3212
3213         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3214         if (!lut) {
3215                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3216                 return -ENOMEM;
3217         }
3218         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3219         if (ret)
3220                 goto out;
3221         for (i = 0; i < reta_size; i++) {
3222                 idx = i / RTE_RETA_GROUP_SIZE;
3223                 shift = i % RTE_RETA_GROUP_SIZE;
3224                 if (reta_conf[idx].mask & (1ULL << shift))
3225                         lut[i] = reta_conf[idx].reta[shift];
3226         }
3227         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3228
3229 out:
3230         rte_free(lut);
3231
3232         return ret;
3233 }
3234
3235 static int
3236 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3237                         struct rte_eth_rss_reta_entry64 *reta_conf,
3238                         uint16_t reta_size)
3239 {
3240         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3241         uint16_t i, lut_size = pf->hash_lut_size;
3242         uint16_t idx, shift;
3243         uint8_t *lut;
3244         int ret;
3245
3246         if (reta_size != lut_size ||
3247                 reta_size > ETH_RSS_RETA_SIZE_512) {
3248                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3249                         "(%d) doesn't match the number hardware can supported "
3250                                         "(%d)\n", reta_size, lut_size);
3251                 return -EINVAL;
3252         }
3253
3254         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3255         if (!lut) {
3256                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3257                 return -ENOMEM;
3258         }
3259
3260         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3261         if (ret)
3262                 goto out;
3263         for (i = 0; i < reta_size; i++) {
3264                 idx = i / RTE_RETA_GROUP_SIZE;
3265                 shift = i % RTE_RETA_GROUP_SIZE;
3266                 if (reta_conf[idx].mask & (1ULL << shift))
3267                         reta_conf[idx].reta[shift] = lut[i];
3268         }
3269
3270 out:
3271         rte_free(lut);
3272
3273         return ret;
3274 }
3275
3276 /**
3277  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3278  * @hw:   pointer to the HW structure
3279  * @mem:  pointer to mem struct to fill out
3280  * @size: size of memory requested
3281  * @alignment: what to align the allocation to
3282  **/
3283 enum i40e_status_code
3284 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3285                         struct i40e_dma_mem *mem,
3286                         u64 size,
3287                         u32 alignment)
3288 {
3289         const struct rte_memzone *mz = NULL;
3290         char z_name[RTE_MEMZONE_NAMESIZE];
3291
3292         if (!mem)
3293                 return I40E_ERR_PARAM;
3294
3295         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3296         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3297                                          alignment, RTE_PGSIZE_2M);
3298         if (!mz)
3299                 return I40E_ERR_NO_MEMORY;
3300
3301         mem->size = size;
3302         mem->va = mz->addr;
3303         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3304         mem->zone = (const void *)mz;
3305         PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3306                     "%"PRIu64, mz->name, mem->pa);
3307
3308         return I40E_SUCCESS;
3309 }
3310
3311 /**
3312  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3313  * @hw:   pointer to the HW structure
3314  * @mem:  ptr to mem struct to free
3315  **/
3316 enum i40e_status_code
3317 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3318                     struct i40e_dma_mem *mem)
3319 {
3320         if (!mem)
3321                 return I40E_ERR_PARAM;
3322
3323         PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3324                     "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3325                     mem->pa);
3326         rte_memzone_free((const struct rte_memzone *)mem->zone);
3327         mem->zone = NULL;
3328         mem->va = NULL;
3329         mem->pa = (u64)0;
3330
3331         return I40E_SUCCESS;
3332 }
3333
3334 /**
3335  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3336  * @hw:   pointer to the HW structure
3337  * @mem:  pointer to mem struct to fill out
3338  * @size: size of memory requested
3339  **/
3340 enum i40e_status_code
3341 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3342                          struct i40e_virt_mem *mem,
3343                          u32 size)
3344 {
3345         if (!mem)
3346                 return I40E_ERR_PARAM;
3347
3348         mem->size = size;
3349         mem->va = rte_zmalloc("i40e", size, 0);
3350
3351         if (mem->va)
3352                 return I40E_SUCCESS;
3353         else
3354                 return I40E_ERR_NO_MEMORY;
3355 }
3356
3357 /**
3358  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3359  * @hw:   pointer to the HW structure
3360  * @mem:  pointer to mem struct to free
3361  **/
3362 enum i40e_status_code
3363 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3364                      struct i40e_virt_mem *mem)
3365 {
3366         if (!mem)
3367                 return I40E_ERR_PARAM;
3368
3369         rte_free(mem->va);
3370         mem->va = NULL;
3371
3372         return I40E_SUCCESS;
3373 }
3374
3375 void
3376 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3377 {
3378         rte_spinlock_init(&sp->spinlock);
3379 }
3380
3381 void
3382 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3383 {
3384         rte_spinlock_lock(&sp->spinlock);
3385 }
3386
3387 void
3388 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3389 {
3390         rte_spinlock_unlock(&sp->spinlock);
3391 }
3392
3393 void
3394 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3395 {
3396         return;
3397 }
3398
3399 /**
3400  * Get the hardware capabilities, which will be parsed
3401  * and saved into struct i40e_hw.
3402  */
3403 static int
3404 i40e_get_cap(struct i40e_hw *hw)
3405 {
3406         struct i40e_aqc_list_capabilities_element_resp *buf;
3407         uint16_t len, size = 0;
3408         int ret;
3409
3410         /* Calculate a huge enough buff for saving response data temporarily */
3411         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3412                                                 I40E_MAX_CAP_ELE_NUM;
3413         buf = rte_zmalloc("i40e", len, 0);
3414         if (!buf) {
3415                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3416                 return I40E_ERR_NO_MEMORY;
3417         }
3418
3419         /* Get, parse the capabilities and save it to hw */
3420         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3421                         i40e_aqc_opc_list_func_capabilities, NULL);
3422         if (ret != I40E_SUCCESS)
3423                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3424
3425         /* Free the temporary buffer after being used */
3426         rte_free(buf);
3427
3428         return ret;
3429 }
3430
3431 static int
3432 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3433 {
3434         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3435         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3436         uint16_t qp_count = 0, vsi_count = 0;
3437
3438         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3439                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3440                 return -EINVAL;
3441         }
3442         /* Add the parameter init for LFC */
3443         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3444         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3445         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3446
3447         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3448         pf->max_num_vsi = hw->func_caps.num_vsis;
3449         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3450         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3451         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3452
3453         /* FDir queue/VSI allocation */
3454         pf->fdir_qp_offset = 0;
3455         if (hw->func_caps.fd) {
3456                 pf->flags |= I40E_FLAG_FDIR;
3457                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3458         } else {
3459                 pf->fdir_nb_qps = 0;
3460         }
3461         qp_count += pf->fdir_nb_qps;
3462         vsi_count += 1;
3463
3464         /* LAN queue/VSI allocation */
3465         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3466         if (!hw->func_caps.rss) {
3467                 pf->lan_nb_qps = 1;
3468         } else {
3469                 pf->flags |= I40E_FLAG_RSS;
3470                 if (hw->mac.type == I40E_MAC_X722)
3471                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3472                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3473         }
3474         qp_count += pf->lan_nb_qps;
3475         vsi_count += 1;
3476
3477         /* VF queue/VSI allocation */
3478         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3479         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3480                 pf->flags |= I40E_FLAG_SRIOV;
3481                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3482                 pf->vf_num = dev->pci_dev->max_vfs;
3483                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3484                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3485                             pf->vf_nb_qps * pf->vf_num);
3486         } else {
3487                 pf->vf_nb_qps = 0;
3488                 pf->vf_num = 0;
3489         }
3490         qp_count += pf->vf_nb_qps * pf->vf_num;
3491         vsi_count += pf->vf_num;
3492
3493         /* VMDq queue/VSI allocation */
3494         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3495         pf->vmdq_nb_qps = 0;
3496         pf->max_nb_vmdq_vsi = 0;
3497         if (hw->func_caps.vmdq) {
3498                 if (qp_count < hw->func_caps.num_tx_qp &&
3499                         vsi_count < hw->func_caps.num_vsis) {
3500                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3501                                 qp_count) / pf->vmdq_nb_qp_max;
3502
3503                         /* Limit the maximum number of VMDq vsi to the maximum
3504                          * ethdev can support
3505                          */
3506                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3507                                 hw->func_caps.num_vsis - vsi_count);
3508                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3509                                 ETH_64_POOLS);
3510                         if (pf->max_nb_vmdq_vsi) {
3511                                 pf->flags |= I40E_FLAG_VMDQ;
3512                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3513                                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3514                                             "per VMDQ VSI, in total %u queues",
3515                                             pf->max_nb_vmdq_vsi,
3516                                             pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3517                                             pf->max_nb_vmdq_vsi);
3518                         } else {
3519                                 PMD_DRV_LOG(INFO, "No enough queues left for "
3520                                             "VMDq");
3521                         }
3522                 } else {
3523                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3524                 }
3525         }
3526         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3527         vsi_count += pf->max_nb_vmdq_vsi;
3528
3529         if (hw->func_caps.dcb)
3530                 pf->flags |= I40E_FLAG_DCB;
3531
3532         if (qp_count > hw->func_caps.num_tx_qp) {
3533                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3534                             "the hardware maximum %u", qp_count,
3535                             hw->func_caps.num_tx_qp);
3536                 return -EINVAL;
3537         }
3538         if (vsi_count > hw->func_caps.num_vsis) {
3539                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3540                             "the hardware maximum %u", vsi_count,
3541                             hw->func_caps.num_vsis);
3542                 return -EINVAL;
3543         }
3544
3545         return 0;
3546 }
3547
3548 static int
3549 i40e_pf_get_switch_config(struct i40e_pf *pf)
3550 {
3551         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3552         struct i40e_aqc_get_switch_config_resp *switch_config;
3553         struct i40e_aqc_switch_config_element_resp *element;
3554         uint16_t start_seid = 0, num_reported;
3555         int ret;
3556
3557         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3558                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3559         if (!switch_config) {
3560                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3561                 return -ENOMEM;
3562         }
3563
3564         /* Get the switch configurations */
3565         ret = i40e_aq_get_switch_config(hw, switch_config,
3566                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3567         if (ret != I40E_SUCCESS) {
3568                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3569                 goto fail;
3570         }
3571         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3572         if (num_reported != 1) { /* The number should be 1 */
3573                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3574                 goto fail;
3575         }
3576
3577         /* Parse the switch configuration elements */
3578         element = &(switch_config->element[0]);
3579         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3580                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3581                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3582         } else
3583                 PMD_DRV_LOG(INFO, "Unknown element type");
3584
3585 fail:
3586         rte_free(switch_config);
3587
3588         return ret;
3589 }
3590
3591 static int
3592 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3593                         uint32_t num)
3594 {
3595         struct pool_entry *entry;
3596
3597         if (pool == NULL || num == 0)
3598                 return -EINVAL;
3599
3600         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3601         if (entry == NULL) {
3602                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3603                 return -ENOMEM;
3604         }
3605
3606         /* queue heap initialize */
3607         pool->num_free = num;
3608         pool->num_alloc = 0;
3609         pool->base = base;
3610         LIST_INIT(&pool->alloc_list);
3611         LIST_INIT(&pool->free_list);
3612
3613         /* Initialize element  */
3614         entry->base = 0;
3615         entry->len = num;
3616
3617         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3618         return 0;
3619 }
3620
3621 static void
3622 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3623 {
3624         struct pool_entry *entry, *next_entry;
3625
3626         if (pool == NULL)
3627                 return;
3628
3629         for (entry = LIST_FIRST(&pool->alloc_list);
3630                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3631                         entry = next_entry) {
3632                 LIST_REMOVE(entry, next);
3633                 rte_free(entry);
3634         }
3635
3636         for (entry = LIST_FIRST(&pool->free_list);
3637                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3638                         entry = next_entry) {
3639                 LIST_REMOVE(entry, next);
3640                 rte_free(entry);
3641         }
3642
3643         pool->num_free = 0;
3644         pool->num_alloc = 0;
3645         pool->base = 0;
3646         LIST_INIT(&pool->alloc_list);
3647         LIST_INIT(&pool->free_list);
3648 }
3649
3650 static int
3651 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3652                        uint32_t base)
3653 {
3654         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3655         uint32_t pool_offset;
3656         int insert;
3657
3658         if (pool == NULL) {
3659                 PMD_DRV_LOG(ERR, "Invalid parameter");
3660                 return -EINVAL;
3661         }
3662
3663         pool_offset = base - pool->base;
3664         /* Lookup in alloc list */
3665         LIST_FOREACH(entry, &pool->alloc_list, next) {
3666                 if (entry->base == pool_offset) {
3667                         valid_entry = entry;
3668                         LIST_REMOVE(entry, next);
3669                         break;
3670                 }
3671         }
3672
3673         /* Not find, return */
3674         if (valid_entry == NULL) {
3675                 PMD_DRV_LOG(ERR, "Failed to find entry");
3676                 return -EINVAL;
3677         }
3678
3679         /**
3680          * Found it, move it to free list  and try to merge.
3681          * In order to make merge easier, always sort it by qbase.
3682          * Find adjacent prev and last entries.
3683          */
3684         prev = next = NULL;
3685         LIST_FOREACH(entry, &pool->free_list, next) {
3686                 if (entry->base > valid_entry->base) {
3687                         next = entry;
3688                         break;
3689                 }
3690                 prev = entry;
3691         }
3692
3693         insert = 0;
3694         /* Try to merge with next one*/
3695         if (next != NULL) {
3696                 /* Merge with next one */
3697                 if (valid_entry->base + valid_entry->len == next->base) {
3698                         next->base = valid_entry->base;
3699                         next->len += valid_entry->len;
3700                         rte_free(valid_entry);
3701                         valid_entry = next;
3702                         insert = 1;
3703                 }
3704         }
3705
3706         if (prev != NULL) {
3707                 /* Merge with previous one */
3708                 if (prev->base + prev->len == valid_entry->base) {
3709                         prev->len += valid_entry->len;
3710                         /* If it merge with next one, remove next node */
3711                         if (insert == 1) {
3712                                 LIST_REMOVE(valid_entry, next);
3713                                 rte_free(valid_entry);
3714                         } else {
3715                                 rte_free(valid_entry);
3716                                 insert = 1;
3717                         }
3718                 }
3719         }
3720
3721         /* Not find any entry to merge, insert */
3722         if (insert == 0) {
3723                 if (prev != NULL)
3724                         LIST_INSERT_AFTER(prev, valid_entry, next);
3725                 else if (next != NULL)
3726                         LIST_INSERT_BEFORE(next, valid_entry, next);
3727                 else /* It's empty list, insert to head */
3728                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3729         }
3730
3731         pool->num_free += valid_entry->len;
3732         pool->num_alloc -= valid_entry->len;
3733
3734         return 0;
3735 }
3736
3737 static int
3738 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3739                        uint16_t num)
3740 {
3741         struct pool_entry *entry, *valid_entry;
3742
3743         if (pool == NULL || num == 0) {
3744                 PMD_DRV_LOG(ERR, "Invalid parameter");
3745                 return -EINVAL;
3746         }
3747
3748         if (pool->num_free < num) {
3749                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3750                             num, pool->num_free);
3751                 return -ENOMEM;
3752         }
3753
3754         valid_entry = NULL;
3755         /* Lookup  in free list and find most fit one */
3756         LIST_FOREACH(entry, &pool->free_list, next) {
3757                 if (entry->len >= num) {
3758                         /* Find best one */
3759                         if (entry->len == num) {
3760                                 valid_entry = entry;
3761                                 break;
3762                         }
3763                         if (valid_entry == NULL || valid_entry->len > entry->len)
3764                                 valid_entry = entry;
3765                 }
3766         }
3767
3768         /* Not find one to satisfy the request, return */
3769         if (valid_entry == NULL) {
3770                 PMD_DRV_LOG(ERR, "No valid entry found");
3771                 return -ENOMEM;
3772         }
3773         /**
3774          * The entry have equal queue number as requested,
3775          * remove it from alloc_list.
3776          */
3777         if (valid_entry->len == num) {
3778                 LIST_REMOVE(valid_entry, next);
3779         } else {
3780                 /**
3781                  * The entry have more numbers than requested,
3782                  * create a new entry for alloc_list and minus its
3783                  * queue base and number in free_list.
3784                  */
3785                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3786                 if (entry == NULL) {
3787                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3788                                     "resource pool");
3789                         return -ENOMEM;
3790                 }
3791                 entry->base = valid_entry->base;
3792                 entry->len = num;
3793                 valid_entry->base += num;
3794                 valid_entry->len -= num;
3795                 valid_entry = entry;
3796         }
3797
3798         /* Insert it into alloc list, not sorted */
3799         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3800
3801         pool->num_free -= valid_entry->len;
3802         pool->num_alloc += valid_entry->len;
3803
3804         return valid_entry->base + pool->base;
3805 }
3806
3807 /**
3808  * bitmap_is_subset - Check whether src2 is subset of src1
3809  **/
3810 static inline int
3811 bitmap_is_subset(uint8_t src1, uint8_t src2)
3812 {
3813         return !((src1 ^ src2) & src2);
3814 }
3815
3816 static enum i40e_status_code
3817 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3818 {
3819         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3820
3821         /* If DCB is not supported, only default TC is supported */
3822         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3823                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3824                 return I40E_NOT_SUPPORTED;
3825         }
3826
3827         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3828                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3829                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
3830                             enabled_tcmap);
3831                 return I40E_NOT_SUPPORTED;
3832         }
3833         return I40E_SUCCESS;
3834 }
3835
3836 int
3837 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3838                                 struct i40e_vsi_vlan_pvid_info *info)
3839 {
3840         struct i40e_hw *hw;
3841         struct i40e_vsi_context ctxt;
3842         uint8_t vlan_flags = 0;
3843         int ret;
3844
3845         if (vsi == NULL || info == NULL) {
3846                 PMD_DRV_LOG(ERR, "invalid parameters");
3847                 return I40E_ERR_PARAM;
3848         }
3849
3850         if (info->on) {
3851                 vsi->info.pvid = info->config.pvid;
3852                 /**
3853                  * If insert pvid is enabled, only tagged pkts are
3854                  * allowed to be sent out.
3855                  */
3856                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3857                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3858         } else {
3859                 vsi->info.pvid = 0;
3860                 if (info->config.reject.tagged == 0)
3861                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3862
3863                 if (info->config.reject.untagged == 0)
3864                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3865         }
3866         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3867                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
3868         vsi->info.port_vlan_flags |= vlan_flags;
3869         vsi->info.valid_sections =
3870                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3871         memset(&ctxt, 0, sizeof(ctxt));
3872         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3873         ctxt.seid = vsi->seid;
3874
3875         hw = I40E_VSI_TO_HW(vsi);
3876         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3877         if (ret != I40E_SUCCESS)
3878                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3879
3880         return ret;
3881 }
3882
3883 static int
3884 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3885 {
3886         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3887         int i, ret;
3888         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3889
3890         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3891         if (ret != I40E_SUCCESS)
3892                 return ret;
3893
3894         if (!vsi->seid) {
3895                 PMD_DRV_LOG(ERR, "seid not valid");
3896                 return -EINVAL;
3897         }
3898
3899         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3900         tc_bw_data.tc_valid_bits = enabled_tcmap;
3901         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3902                 tc_bw_data.tc_bw_credits[i] =
3903                         (enabled_tcmap & (1 << i)) ? 1 : 0;
3904
3905         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3906         if (ret != I40E_SUCCESS) {
3907                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3908                 return ret;
3909         }
3910
3911         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3912                                         sizeof(vsi->info.qs_handle));
3913         return I40E_SUCCESS;
3914 }
3915
3916 static enum i40e_status_code
3917 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3918                                  struct i40e_aqc_vsi_properties_data *info,
3919                                  uint8_t enabled_tcmap)
3920 {
3921         enum i40e_status_code ret;
3922         int i, total_tc = 0;
3923         uint16_t qpnum_per_tc, bsf, qp_idx;
3924
3925         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3926         if (ret != I40E_SUCCESS)
3927                 return ret;
3928
3929         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3930                 if (enabled_tcmap & (1 << i))
3931                         total_tc++;
3932         vsi->enabled_tc = enabled_tcmap;
3933
3934         /* Number of queues per enabled TC */
3935         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3936         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3937         bsf = rte_bsf32(qpnum_per_tc);
3938
3939         /* Adjust the queue number to actual queues that can be applied */
3940         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3941                 vsi->nb_qps = qpnum_per_tc * total_tc;
3942
3943         /**
3944          * Configure TC and queue mapping parameters, for enabled TC,
3945          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3946          * default queue will serve it.
3947          */
3948         qp_idx = 0;
3949         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3950                 if (vsi->enabled_tc & (1 << i)) {
3951                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3952                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3953                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
3954                         qp_idx += qpnum_per_tc;
3955                 } else
3956                         info->tc_mapping[i] = 0;
3957         }
3958
3959         /* Associate queue number with VSI */
3960         if (vsi->type == I40E_VSI_SRIOV) {
3961                 info->mapping_flags |=
3962                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
3963                 for (i = 0; i < vsi->nb_qps; i++)
3964                         info->queue_mapping[i] =
3965                                 rte_cpu_to_le_16(vsi->base_queue + i);
3966         } else {
3967                 info->mapping_flags |=
3968                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
3969                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
3970         }
3971         info->valid_sections |=
3972                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
3973
3974         return I40E_SUCCESS;
3975 }
3976
3977 static int
3978 i40e_veb_release(struct i40e_veb *veb)
3979 {
3980         struct i40e_vsi *vsi;
3981         struct i40e_hw *hw;
3982
3983         if (veb == NULL)
3984                 return -EINVAL;
3985
3986         if (!TAILQ_EMPTY(&veb->head)) {
3987                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
3988                 return -EACCES;
3989         }
3990         /* associate_vsi field is NULL for floating VEB */
3991         if (veb->associate_vsi != NULL) {
3992                 vsi = veb->associate_vsi;
3993                 hw = I40E_VSI_TO_HW(vsi);
3994
3995                 vsi->uplink_seid = veb->uplink_seid;
3996                 vsi->veb = NULL;
3997         } else {
3998                 veb->associate_pf->main_vsi->floating_veb = NULL;
3999                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4000         }
4001
4002         i40e_aq_delete_element(hw, veb->seid, NULL);
4003         rte_free(veb);
4004         return I40E_SUCCESS;
4005 }
4006
4007 /* Setup a veb */
4008 static struct i40e_veb *
4009 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4010 {
4011         struct i40e_veb *veb;
4012         int ret;
4013         struct i40e_hw *hw;
4014
4015         if (pf == NULL) {
4016                 PMD_DRV_LOG(ERR,
4017                             "veb setup failed, associated PF shouldn't null");
4018                 return NULL;
4019         }
4020         hw = I40E_PF_TO_HW(pf);
4021
4022         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4023         if (!veb) {
4024                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4025                 goto fail;
4026         }
4027
4028         veb->associate_vsi = vsi;
4029         veb->associate_pf = pf;
4030         TAILQ_INIT(&veb->head);
4031         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4032
4033         /* create floating veb if vsi is NULL */
4034         if (vsi != NULL) {
4035                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4036                                       I40E_DEFAULT_TCMAP, false,
4037                                       &veb->seid, false, NULL);
4038         } else {
4039                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4040                                       true, &veb->seid, false, NULL);
4041         }
4042
4043         if (ret != I40E_SUCCESS) {
4044                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4045                             hw->aq.asq_last_status);
4046                 goto fail;
4047         }
4048
4049         /* get statistics index */
4050         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4051                                 &veb->stats_idx, NULL, NULL, NULL);
4052         if (ret != I40E_SUCCESS) {
4053                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
4054                             hw->aq.asq_last_status);
4055                 goto fail;
4056         }
4057         /* Get VEB bandwidth, to be implemented */
4058         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4059         if (vsi)
4060                 vsi->uplink_seid = veb->seid;
4061
4062         return veb;
4063 fail:
4064         rte_free(veb);
4065         return NULL;
4066 }
4067
4068 int
4069 i40e_vsi_release(struct i40e_vsi *vsi)
4070 {
4071         struct i40e_pf *pf;
4072         struct i40e_hw *hw;
4073         struct i40e_vsi_list *vsi_list;
4074         int ret;
4075         struct i40e_mac_filter *f;
4076         uint16_t user_param = vsi->user_param;
4077
4078         if (!vsi)
4079                 return I40E_SUCCESS;
4080
4081         pf = I40E_VSI_TO_PF(vsi);
4082         hw = I40E_VSI_TO_HW(vsi);
4083
4084         /* VSI has child to attach, release child first */
4085         if (vsi->veb) {
4086                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
4087                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4088                                 return -1;
4089                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
4090                 }
4091                 i40e_veb_release(vsi->veb);
4092         }
4093
4094         if (vsi->floating_veb) {
4095                 TAILQ_FOREACH(vsi_list, &vsi->floating_veb->head, list) {
4096                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4097                                 return -1;
4098                         TAILQ_REMOVE(&vsi->floating_veb->head, vsi_list, list);
4099                 }
4100         }
4101
4102         /* Remove all macvlan filters of the VSI */
4103         i40e_vsi_remove_all_macvlan_filter(vsi);
4104         TAILQ_FOREACH(f, &vsi->mac_list, next)
4105                 rte_free(f);
4106
4107         if (vsi->type != I40E_VSI_MAIN &&
4108             ((vsi->type != I40E_VSI_SRIOV) ||
4109             !pf->floating_veb_list[user_param])) {
4110                 /* Remove vsi from parent's sibling list */
4111                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4112                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4113                         return I40E_ERR_PARAM;
4114                 }
4115                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4116                                 &vsi->sib_vsi_list, list);
4117
4118                 /* Remove all switch element of the VSI */
4119                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4120                 if (ret != I40E_SUCCESS)
4121                         PMD_DRV_LOG(ERR, "Failed to delete element");
4122         }
4123
4124         if ((vsi->type == I40E_VSI_SRIOV) &&
4125             pf->floating_veb_list[user_param]) {
4126                 /* Remove vsi from parent's sibling list */
4127                 if (vsi->parent_vsi == NULL ||
4128                     vsi->parent_vsi->floating_veb == NULL) {
4129                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4130                         return I40E_ERR_PARAM;
4131                 }
4132                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4133                              &vsi->sib_vsi_list, list);
4134
4135                 /* Remove all switch element of the VSI */
4136                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4137                 if (ret != I40E_SUCCESS)
4138                         PMD_DRV_LOG(ERR, "Failed to delete element");
4139         }
4140
4141         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4142
4143         if (vsi->type != I40E_VSI_SRIOV)
4144                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4145         rte_free(vsi);
4146
4147         return I40E_SUCCESS;
4148 }
4149
4150 static int
4151 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4152 {
4153         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4154         struct i40e_aqc_remove_macvlan_element_data def_filter;
4155         struct i40e_mac_filter_info filter;
4156         int ret;
4157
4158         if (vsi->type != I40E_VSI_MAIN)
4159                 return I40E_ERR_CONFIG;
4160         memset(&def_filter, 0, sizeof(def_filter));
4161         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4162                                         ETH_ADDR_LEN);
4163         def_filter.vlan_tag = 0;
4164         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4165                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4166         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4167         if (ret != I40E_SUCCESS) {
4168                 struct i40e_mac_filter *f;
4169                 struct ether_addr *mac;
4170
4171                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
4172                             "macvlan filter");
4173                 /* It needs to add the permanent mac into mac list */
4174                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4175                 if (f == NULL) {
4176                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4177                         return I40E_ERR_NO_MEMORY;
4178                 }
4179                 mac = &f->mac_info.mac_addr;
4180                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4181                                 ETH_ADDR_LEN);
4182                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4183                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4184                 vsi->mac_num++;
4185
4186                 return ret;
4187         }
4188         (void)rte_memcpy(&filter.mac_addr,
4189                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4190         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4191         return i40e_vsi_add_mac(vsi, &filter);
4192 }
4193
4194 /*
4195  * i40e_vsi_get_bw_config - Query VSI BW Information
4196  * @vsi: the VSI to be queried
4197  *
4198  * Returns 0 on success, negative value on failure
4199  */
4200 static enum i40e_status_code
4201 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4202 {
4203         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4204         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4205         struct i40e_hw *hw = &vsi->adapter->hw;
4206         i40e_status ret;
4207         int i;
4208         uint32_t bw_max;
4209
4210         memset(&bw_config, 0, sizeof(bw_config));
4211         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4212         if (ret != I40E_SUCCESS) {
4213                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4214                             hw->aq.asq_last_status);
4215                 return ret;
4216         }
4217
4218         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4219         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4220                                         &ets_sla_config, NULL);
4221         if (ret != I40E_SUCCESS) {
4222                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
4223                             "configuration %u", hw->aq.asq_last_status);
4224                 return ret;
4225         }
4226
4227         /* store and print out BW info */
4228         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4229         vsi->bw_info.bw_max = bw_config.max_bw;
4230         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4231         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4232         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4233                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4234                      I40E_16_BIT_WIDTH);
4235         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4236                 vsi->bw_info.bw_ets_share_credits[i] =
4237                                 ets_sla_config.share_credits[i];
4238                 vsi->bw_info.bw_ets_credits[i] =
4239                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4240                 /* 4 bits per TC, 4th bit is reserved */
4241                 vsi->bw_info.bw_ets_max[i] =
4242                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4243                                   RTE_LEN2MASK(3, uint8_t));
4244                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4245                             vsi->bw_info.bw_ets_share_credits[i]);
4246                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4247                             vsi->bw_info.bw_ets_credits[i]);
4248                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4249                             vsi->bw_info.bw_ets_max[i]);
4250         }
4251
4252         return I40E_SUCCESS;
4253 }
4254
4255 /* i40e_enable_pf_lb
4256  * @pf: pointer to the pf structure
4257  *
4258  * allow loopback on pf
4259  */
4260 static inline void
4261 i40e_enable_pf_lb(struct i40e_pf *pf)
4262 {
4263         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4264         struct i40e_vsi_context ctxt;
4265         int ret;
4266
4267         /* Use the FW API if FW >= v5.0 */
4268         if (hw->aq.fw_maj_ver < 5) {
4269                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4270                 return;
4271         }
4272
4273         memset(&ctxt, 0, sizeof(ctxt));
4274         ctxt.seid = pf->main_vsi_seid;
4275         ctxt.pf_num = hw->pf_id;
4276         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4277         if (ret) {
4278                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4279                             ret, hw->aq.asq_last_status);
4280                 return;
4281         }
4282         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4283         ctxt.info.valid_sections =
4284                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4285         ctxt.info.switch_id |=
4286                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4287
4288         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4289         if (ret)
4290                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
4291                             hw->aq.asq_last_status);
4292 }
4293
4294 /* Setup a VSI */
4295 struct i40e_vsi *
4296 i40e_vsi_setup(struct i40e_pf *pf,
4297                enum i40e_vsi_type type,
4298                struct i40e_vsi *uplink_vsi,
4299                uint16_t user_param)
4300 {
4301         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4302         struct i40e_vsi *vsi;
4303         struct i40e_mac_filter_info filter;
4304         int ret;
4305         struct i40e_vsi_context ctxt;
4306         struct ether_addr broadcast =
4307                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4308
4309         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4310             uplink_vsi == NULL) {
4311                 PMD_DRV_LOG(ERR, "VSI setup failed, "
4312                             "VSI link shouldn't be NULL");
4313                 return NULL;
4314         }
4315
4316         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4317                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
4318                             "uplink VSI should be NULL");
4319                 return NULL;
4320         }
4321
4322         /* two situations
4323          * 1.type is not MAIN and uplink vsi is not NULL
4324          * If uplink vsi didn't setup VEB, create one first under veb field
4325          * 2.type is SRIOV and the uplink is NULL
4326          * If floating VEB is NULL, create one veb under floating veb field
4327          */
4328
4329         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4330             uplink_vsi->veb == NULL) {
4331                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4332
4333                 if (uplink_vsi->veb == NULL) {
4334                         PMD_DRV_LOG(ERR, "VEB setup failed");
4335                         return NULL;
4336                 }
4337                 /* set ALLOWLOOPBACk on pf, when veb is created */
4338                 i40e_enable_pf_lb(pf);
4339         }
4340
4341         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4342             pf->main_vsi->floating_veb == NULL) {
4343                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4344
4345                 if (pf->main_vsi->floating_veb == NULL) {
4346                         PMD_DRV_LOG(ERR, "VEB setup failed");
4347                         return NULL;
4348                 }
4349         }
4350
4351         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4352         if (!vsi) {
4353                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4354                 return NULL;
4355         }
4356         TAILQ_INIT(&vsi->mac_list);
4357         vsi->type = type;
4358         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4359         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4360         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4361         vsi->user_param = user_param;
4362         /* Allocate queues */
4363         switch (vsi->type) {
4364         case I40E_VSI_MAIN  :
4365                 vsi->nb_qps = pf->lan_nb_qps;
4366                 break;
4367         case I40E_VSI_SRIOV :
4368                 vsi->nb_qps = pf->vf_nb_qps;
4369                 break;
4370         case I40E_VSI_VMDQ2:
4371                 vsi->nb_qps = pf->vmdq_nb_qps;
4372                 break;
4373         case I40E_VSI_FDIR:
4374                 vsi->nb_qps = pf->fdir_nb_qps;
4375                 break;
4376         default:
4377                 goto fail_mem;
4378         }
4379         /*
4380          * The filter status descriptor is reported in rx queue 0,
4381          * while the tx queue for fdir filter programming has no
4382          * such constraints, can be non-zero queues.
4383          * To simplify it, choose FDIR vsi use queue 0 pair.
4384          * To make sure it will use queue 0 pair, queue allocation
4385          * need be done before this function is called
4386          */
4387         if (type != I40E_VSI_FDIR) {
4388                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4389                         if (ret < 0) {
4390                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4391                                                 vsi->seid, ret);
4392                                 goto fail_mem;
4393                         }
4394                         vsi->base_queue = ret;
4395         } else
4396                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4397
4398         /* VF has MSIX interrupt in VF range, don't allocate here */
4399         if (type == I40E_VSI_MAIN) {
4400                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4401                                           RTE_MIN(vsi->nb_qps,
4402                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4403                 if (ret < 0) {
4404                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4405                                     vsi->seid, ret);
4406                         goto fail_queue_alloc;
4407                 }
4408                 vsi->msix_intr = ret;
4409                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4410         } else if (type != I40E_VSI_SRIOV) {
4411                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4412                 if (ret < 0) {
4413                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4414                         goto fail_queue_alloc;
4415                 }
4416                 vsi->msix_intr = ret;
4417                 vsi->nb_msix = 1;
4418         } else {
4419                 vsi->msix_intr = 0;
4420                 vsi->nb_msix = 0;
4421         }
4422
4423         /* Add VSI */
4424         if (type == I40E_VSI_MAIN) {
4425                 /* For main VSI, no need to add since it's default one */
4426                 vsi->uplink_seid = pf->mac_seid;
4427                 vsi->seid = pf->main_vsi_seid;
4428                 /* Bind queues with specific MSIX interrupt */
4429                 /**
4430                  * Needs 2 interrupt at least, one for misc cause which will
4431                  * enabled from OS side, Another for queues binding the
4432                  * interrupt from device side only.
4433                  */
4434
4435                 /* Get default VSI parameters from hardware */
4436                 memset(&ctxt, 0, sizeof(ctxt));
4437                 ctxt.seid = vsi->seid;
4438                 ctxt.pf_num = hw->pf_id;
4439                 ctxt.uplink_seid = vsi->uplink_seid;
4440                 ctxt.vf_num = 0;
4441                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4442                 if (ret != I40E_SUCCESS) {
4443                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4444                         goto fail_msix_alloc;
4445                 }
4446                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4447                         sizeof(struct i40e_aqc_vsi_properties_data));
4448                 vsi->vsi_id = ctxt.vsi_number;
4449                 vsi->info.valid_sections = 0;
4450
4451                 /* Configure tc, enabled TC0 only */
4452                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4453                         I40E_SUCCESS) {
4454                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4455                         goto fail_msix_alloc;
4456                 }
4457
4458                 /* TC, queue mapping */
4459                 memset(&ctxt, 0, sizeof(ctxt));
4460                 vsi->info.valid_sections |=
4461                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4462                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4463                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4464                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4465                         sizeof(struct i40e_aqc_vsi_properties_data));
4466                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4467                                                 I40E_DEFAULT_TCMAP);
4468                 if (ret != I40E_SUCCESS) {
4469                         PMD_DRV_LOG(ERR, "Failed to configure "
4470                                     "TC queue mapping");
4471                         goto fail_msix_alloc;
4472                 }
4473                 ctxt.seid = vsi->seid;
4474                 ctxt.pf_num = hw->pf_id;
4475                 ctxt.uplink_seid = vsi->uplink_seid;
4476                 ctxt.vf_num = 0;
4477
4478                 /* Update VSI parameters */
4479                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4480                 if (ret != I40E_SUCCESS) {
4481                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4482                         goto fail_msix_alloc;
4483                 }
4484
4485                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4486                                                 sizeof(vsi->info.tc_mapping));
4487                 (void)rte_memcpy(&vsi->info.queue_mapping,
4488                                 &ctxt.info.queue_mapping,
4489                         sizeof(vsi->info.queue_mapping));
4490                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4491                 vsi->info.valid_sections = 0;
4492
4493                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4494                                 ETH_ADDR_LEN);
4495
4496                 /**
4497                  * Updating default filter settings are necessary to prevent
4498                  * reception of tagged packets.
4499                  * Some old firmware configurations load a default macvlan
4500                  * filter which accepts both tagged and untagged packets.
4501                  * The updating is to use a normal filter instead if needed.
4502                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4503                  * The firmware with correct configurations load the default
4504                  * macvlan filter which is expected and cannot be removed.
4505                  */
4506                 i40e_update_default_filter_setting(vsi);
4507                 i40e_config_qinq(hw, vsi);
4508         } else if (type == I40E_VSI_SRIOV) {
4509                 memset(&ctxt, 0, sizeof(ctxt));
4510                 /**
4511                  * For other VSI, the uplink_seid equals to uplink VSI's
4512                  * uplink_seid since they share same VEB
4513                  */
4514                 if (uplink_vsi == NULL)
4515                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4516                 else
4517                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4518                 ctxt.pf_num = hw->pf_id;
4519                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4520                 ctxt.uplink_seid = vsi->uplink_seid;
4521                 ctxt.connection_type = 0x1;
4522                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4523
4524                 /* Use the VEB configuration if FW >= v5.0 */
4525                 if (hw->aq.fw_maj_ver >= 5) {
4526                         /* Configure switch ID */
4527                         ctxt.info.valid_sections |=
4528                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4529                         ctxt.info.switch_id =
4530                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4531                 }
4532
4533                 /* Configure port/vlan */
4534                 ctxt.info.valid_sections |=
4535                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4536                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4537                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4538                                                 I40E_DEFAULT_TCMAP);
4539                 if (ret != I40E_SUCCESS) {
4540                         PMD_DRV_LOG(ERR, "Failed to configure "
4541                                     "TC queue mapping");
4542                         goto fail_msix_alloc;
4543                 }
4544                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4545                 ctxt.info.valid_sections |=
4546                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4547                 /**
4548                  * Since VSI is not created yet, only configure parameter,
4549                  * will add vsi below.
4550                  */
4551
4552                 i40e_config_qinq(hw, vsi);
4553         } else if (type == I40E_VSI_VMDQ2) {
4554                 memset(&ctxt, 0, sizeof(ctxt));
4555                 /*
4556                  * For other VSI, the uplink_seid equals to uplink VSI's
4557                  * uplink_seid since they share same VEB
4558                  */
4559                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4560                 ctxt.pf_num = hw->pf_id;
4561                 ctxt.vf_num = 0;
4562                 ctxt.uplink_seid = vsi->uplink_seid;
4563                 ctxt.connection_type = 0x1;
4564                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4565
4566                 ctxt.info.valid_sections |=
4567                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4568                 /* user_param carries flag to enable loop back */
4569                 if (user_param) {
4570                         ctxt.info.switch_id =
4571                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4572                         ctxt.info.switch_id |=
4573                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4574                 }
4575
4576                 /* Configure port/vlan */
4577                 ctxt.info.valid_sections |=
4578                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4579                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4580                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4581                                                 I40E_DEFAULT_TCMAP);
4582                 if (ret != I40E_SUCCESS) {
4583                         PMD_DRV_LOG(ERR, "Failed to configure "
4584                                         "TC queue mapping");
4585                         goto fail_msix_alloc;
4586                 }
4587                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4588                 ctxt.info.valid_sections |=
4589                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4590         } else if (type == I40E_VSI_FDIR) {
4591                 memset(&ctxt, 0, sizeof(ctxt));
4592                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4593                 ctxt.pf_num = hw->pf_id;
4594                 ctxt.vf_num = 0;
4595                 ctxt.uplink_seid = vsi->uplink_seid;
4596                 ctxt.connection_type = 0x1;     /* regular data port */
4597                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4598                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4599                                                 I40E_DEFAULT_TCMAP);
4600                 if (ret != I40E_SUCCESS) {
4601                         PMD_DRV_LOG(ERR, "Failed to configure "
4602                                         "TC queue mapping.");
4603                         goto fail_msix_alloc;
4604                 }
4605                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4606                 ctxt.info.valid_sections |=
4607                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4608         } else {
4609                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4610                 goto fail_msix_alloc;
4611         }
4612
4613         if (vsi->type != I40E_VSI_MAIN) {
4614                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4615                 if (ret != I40E_SUCCESS) {
4616                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4617                                     hw->aq.asq_last_status);
4618                         goto fail_msix_alloc;
4619                 }
4620                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4621                 vsi->info.valid_sections = 0;
4622                 vsi->seid = ctxt.seid;
4623                 vsi->vsi_id = ctxt.vsi_number;
4624                 vsi->sib_vsi_list.vsi = vsi;
4625                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4626                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4627                                           &vsi->sib_vsi_list, list);
4628                 } else {
4629                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4630                                           &vsi->sib_vsi_list, list);
4631                 }
4632         }
4633
4634         /* MAC/VLAN configuration */
4635         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4636         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4637
4638         ret = i40e_vsi_add_mac(vsi, &filter);
4639         if (ret != I40E_SUCCESS) {
4640                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4641                 goto fail_msix_alloc;
4642         }
4643
4644         /* Get VSI BW information */
4645         i40e_vsi_get_bw_config(vsi);
4646         return vsi;
4647 fail_msix_alloc:
4648         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4649 fail_queue_alloc:
4650         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4651 fail_mem:
4652         rte_free(vsi);
4653         return NULL;
4654 }
4655
4656 /* Configure vlan filter on or off */
4657 int
4658 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4659 {
4660         int i, num;
4661         struct i40e_mac_filter *f;
4662         struct i40e_mac_filter_info *mac_filter;
4663         enum rte_mac_filter_type desired_filter;
4664         int ret = I40E_SUCCESS;
4665
4666         if (on) {
4667                 /* Filter to match MAC and VLAN */
4668                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4669         } else {
4670                 /* Filter to match only MAC */
4671                 desired_filter = RTE_MAC_PERFECT_MATCH;
4672         }
4673
4674         num = vsi->mac_num;
4675
4676         mac_filter = rte_zmalloc("mac_filter_info_data",
4677                                  num * sizeof(*mac_filter), 0);
4678         if (mac_filter == NULL) {
4679                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4680                 return I40E_ERR_NO_MEMORY;
4681         }
4682
4683         i = 0;
4684
4685         /* Remove all existing mac */
4686         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4687                 mac_filter[i] = f->mac_info;
4688                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4689                 if (ret) {
4690                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4691                                     on ? "enable" : "disable");
4692                         goto DONE;
4693                 }
4694                 i++;
4695         }
4696
4697         /* Override with new filter */
4698         for (i = 0; i < num; i++) {
4699                 mac_filter[i].filter_type = desired_filter;
4700                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4701                 if (ret) {
4702                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4703                                     on ? "enable" : "disable");
4704                         goto DONE;
4705                 }
4706         }
4707
4708 DONE:
4709         rte_free(mac_filter);
4710         return ret;
4711 }
4712
4713 /* Configure vlan stripping on or off */
4714 int
4715 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4716 {
4717         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4718         struct i40e_vsi_context ctxt;
4719         uint8_t vlan_flags;
4720         int ret = I40E_SUCCESS;
4721
4722         /* Check if it has been already on or off */
4723         if (vsi->info.valid_sections &
4724                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4725                 if (on) {
4726                         if ((vsi->info.port_vlan_flags &
4727                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4728                                 return 0; /* already on */
4729                 } else {
4730                         if ((vsi->info.port_vlan_flags &
4731                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4732                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4733                                 return 0; /* already off */
4734                 }
4735         }
4736
4737         if (on)
4738                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4739         else
4740                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4741         vsi->info.valid_sections =
4742                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4743         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4744         vsi->info.port_vlan_flags |= vlan_flags;
4745         ctxt.seid = vsi->seid;
4746         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4747         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4748         if (ret)
4749                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4750                             on ? "enable" : "disable");
4751
4752         return ret;
4753 }
4754
4755 static int
4756 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4757 {
4758         struct rte_eth_dev_data *data = dev->data;
4759         int ret;
4760         int mask = 0;
4761
4762         /* Apply vlan offload setting */
4763         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
4764         i40e_vlan_offload_set(dev, mask);
4765
4766         /* Apply double-vlan setting, not implemented yet */
4767
4768         /* Apply pvid setting */
4769         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4770                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
4771         if (ret)
4772                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4773
4774         return ret;
4775 }
4776
4777 static int
4778 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4779 {
4780         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4781
4782         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4783 }
4784
4785 static int
4786 i40e_update_flow_control(struct i40e_hw *hw)
4787 {
4788 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4789         struct i40e_link_status link_status;
4790         uint32_t rxfc = 0, txfc = 0, reg;
4791         uint8_t an_info;
4792         int ret;
4793
4794         memset(&link_status, 0, sizeof(link_status));
4795         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4796         if (ret != I40E_SUCCESS) {
4797                 PMD_DRV_LOG(ERR, "Failed to get link status information");
4798                 goto write_reg; /* Disable flow control */
4799         }
4800
4801         an_info = hw->phy.link_info.an_info;
4802         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4803                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4804                 ret = I40E_ERR_NOT_READY;
4805                 goto write_reg; /* Disable flow control */
4806         }
4807         /**
4808          * If link auto negotiation is enabled, flow control needs to
4809          * be configured according to it
4810          */
4811         switch (an_info & I40E_LINK_PAUSE_RXTX) {
4812         case I40E_LINK_PAUSE_RXTX:
4813                 rxfc = 1;
4814                 txfc = 1;
4815                 hw->fc.current_mode = I40E_FC_FULL;
4816                 break;
4817         case I40E_AQ_LINK_PAUSE_RX:
4818                 rxfc = 1;
4819                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4820                 break;
4821         case I40E_AQ_LINK_PAUSE_TX:
4822                 txfc = 1;
4823                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4824                 break;
4825         default:
4826                 hw->fc.current_mode = I40E_FC_NONE;
4827                 break;
4828         }
4829
4830 write_reg:
4831         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4832                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4833         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4834         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4835         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4836         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4837
4838         return ret;
4839 }
4840
4841 /* PF setup */
4842 static int
4843 i40e_pf_setup(struct i40e_pf *pf)
4844 {
4845         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4846         struct i40e_filter_control_settings settings;
4847         struct i40e_vsi *vsi;
4848         int ret;
4849
4850         /* Clear all stats counters */
4851         pf->offset_loaded = FALSE;
4852         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4853         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4854
4855         ret = i40e_pf_get_switch_config(pf);
4856         if (ret != I40E_SUCCESS) {
4857                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4858                 return ret;
4859         }
4860         if (pf->flags & I40E_FLAG_FDIR) {
4861                 /* make queue allocated first, let FDIR use queue pair 0*/
4862                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4863                 if (ret != I40E_FDIR_QUEUE_ID) {
4864                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4865                                     " ret =%d", ret);
4866                         pf->flags &= ~I40E_FLAG_FDIR;
4867                 }
4868         }
4869         /*  main VSI setup */
4870         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4871         if (!vsi) {
4872                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4873                 return I40E_ERR_NOT_READY;
4874         }
4875         pf->main_vsi = vsi;
4876
4877         /* Configure filter control */
4878         memset(&settings, 0, sizeof(settings));
4879         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4880                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4881         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4882                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4883         else {
4884                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4885                                                 hw->func_caps.rss_table_size);
4886                 return I40E_ERR_PARAM;
4887         }
4888         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4889                         "size: %u\n", hw->func_caps.rss_table_size);
4890         pf->hash_lut_size = hw->func_caps.rss_table_size;
4891
4892         /* Enable ethtype and macvlan filters */
4893         settings.enable_ethtype = TRUE;
4894         settings.enable_macvlan = TRUE;
4895         ret = i40e_set_filter_control(hw, &settings);
4896         if (ret)
4897                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4898                                                                 ret);
4899
4900         /* Update flow control according to the auto negotiation */
4901         i40e_update_flow_control(hw);
4902
4903         return I40E_SUCCESS;
4904 }
4905
4906 int
4907 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4908 {
4909         uint32_t reg;
4910         uint16_t j;
4911
4912         /**
4913          * Set or clear TX Queue Disable flags,
4914          * which is required by hardware.
4915          */
4916         i40e_pre_tx_queue_cfg(hw, q_idx, on);
4917         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4918
4919         /* Wait until the request is finished */
4920         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4921                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4922                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4923                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4924                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4925                                                         & 0x1))) {
4926                         break;
4927                 }
4928         }
4929         if (on) {
4930                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4931                         return I40E_SUCCESS; /* already on, skip next steps */
4932
4933                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4934                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4935         } else {
4936                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4937                         return I40E_SUCCESS; /* already off, skip next steps */
4938                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4939         }
4940         /* Write the register */
4941         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4942         /* Check the result */
4943         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4944                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4945                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4946                 if (on) {
4947                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4948                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
4949                                 break;
4950                 } else {
4951                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4952                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4953                                 break;
4954                 }
4955         }
4956         /* Check if it is timeout */
4957         if (j >= I40E_CHK_Q_ENA_COUNT) {
4958                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
4959                             (on ? "enable" : "disable"), q_idx);
4960                 return I40E_ERR_TIMEOUT;
4961         }
4962
4963         return I40E_SUCCESS;
4964 }
4965
4966 /* Swith on or off the tx queues */
4967 static int
4968 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
4969 {
4970         struct rte_eth_dev_data *dev_data = pf->dev_data;
4971         struct i40e_tx_queue *txq;
4972         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4973         uint16_t i;
4974         int ret;
4975
4976         for (i = 0; i < dev_data->nb_tx_queues; i++) {
4977                 txq = dev_data->tx_queues[i];
4978                 /* Don't operate the queue if not configured or
4979                  * if starting only per queue */
4980                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
4981                         continue;
4982                 if (on)
4983                         ret = i40e_dev_tx_queue_start(dev, i);
4984                 else
4985                         ret = i40e_dev_tx_queue_stop(dev, i);
4986                 if ( ret != I40E_SUCCESS)
4987                         return ret;
4988         }
4989
4990         return I40E_SUCCESS;
4991 }
4992
4993 int
4994 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4995 {
4996         uint32_t reg;
4997         uint16_t j;
4998
4999         /* Wait until the request is finished */
5000         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5001                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5002                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5003                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5004                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5005                         break;
5006         }
5007
5008         if (on) {
5009                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5010                         return I40E_SUCCESS; /* Already on, skip next steps */
5011                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5012         } else {
5013                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5014                         return I40E_SUCCESS; /* Already off, skip next steps */
5015                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5016         }
5017
5018         /* Write the register */
5019         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5020         /* Check the result */
5021         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5022                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5023                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5024                 if (on) {
5025                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5026                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5027                                 break;
5028                 } else {
5029                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5030                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5031                                 break;
5032                 }
5033         }
5034
5035         /* Check if it is timeout */
5036         if (j >= I40E_CHK_Q_ENA_COUNT) {
5037                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5038                             (on ? "enable" : "disable"), q_idx);
5039                 return I40E_ERR_TIMEOUT;
5040         }
5041
5042         return I40E_SUCCESS;
5043 }
5044 /* Switch on or off the rx queues */
5045 static int
5046 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5047 {
5048         struct rte_eth_dev_data *dev_data = pf->dev_data;
5049         struct i40e_rx_queue *rxq;
5050         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5051         uint16_t i;
5052         int ret;
5053
5054         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5055                 rxq = dev_data->rx_queues[i];
5056                 /* Don't operate the queue if not configured or
5057                  * if starting only per queue */
5058                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5059                         continue;
5060                 if (on)
5061                         ret = i40e_dev_rx_queue_start(dev, i);
5062                 else
5063                         ret = i40e_dev_rx_queue_stop(dev, i);
5064                 if (ret != I40E_SUCCESS)
5065                         return ret;
5066         }
5067
5068         return I40E_SUCCESS;
5069 }
5070
5071 /* Switch on or off all the rx/tx queues */
5072 int
5073 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5074 {
5075         int ret;
5076
5077         if (on) {
5078                 /* enable rx queues before enabling tx queues */
5079                 ret = i40e_dev_switch_rx_queues(pf, on);
5080                 if (ret) {
5081                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5082                         return ret;
5083                 }
5084                 ret = i40e_dev_switch_tx_queues(pf, on);
5085         } else {
5086                 /* Stop tx queues before stopping rx queues */
5087                 ret = i40e_dev_switch_tx_queues(pf, on);
5088                 if (ret) {
5089                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5090                         return ret;
5091                 }
5092                 ret = i40e_dev_switch_rx_queues(pf, on);
5093         }
5094
5095         return ret;
5096 }
5097
5098 /* Initialize VSI for TX */
5099 static int
5100 i40e_dev_tx_init(struct i40e_pf *pf)
5101 {
5102         struct rte_eth_dev_data *data = pf->dev_data;
5103         uint16_t i;
5104         uint32_t ret = I40E_SUCCESS;
5105         struct i40e_tx_queue *txq;
5106
5107         for (i = 0; i < data->nb_tx_queues; i++) {
5108                 txq = data->tx_queues[i];
5109                 if (!txq || !txq->q_set)
5110                         continue;
5111                 ret = i40e_tx_queue_init(txq);
5112                 if (ret != I40E_SUCCESS)
5113                         break;
5114         }
5115         if (ret == I40E_SUCCESS)
5116                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5117                                      ->eth_dev);
5118
5119         return ret;
5120 }
5121
5122 /* Initialize VSI for RX */
5123 static int
5124 i40e_dev_rx_init(struct i40e_pf *pf)
5125 {
5126         struct rte_eth_dev_data *data = pf->dev_data;
5127         int ret = I40E_SUCCESS;
5128         uint16_t i;
5129         struct i40e_rx_queue *rxq;
5130
5131         i40e_pf_config_mq_rx(pf);
5132         for (i = 0; i < data->nb_rx_queues; i++) {
5133                 rxq = data->rx_queues[i];
5134                 if (!rxq || !rxq->q_set)
5135                         continue;
5136
5137                 ret = i40e_rx_queue_init(rxq);
5138                 if (ret != I40E_SUCCESS) {
5139                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
5140                                     "initialization");
5141                         break;
5142                 }
5143         }
5144         if (ret == I40E_SUCCESS)
5145                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5146                                      ->eth_dev);
5147
5148         return ret;
5149 }
5150
5151 static int
5152 i40e_dev_rxtx_init(struct i40e_pf *pf)
5153 {
5154         int err;
5155
5156         err = i40e_dev_tx_init(pf);
5157         if (err) {
5158                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5159                 return err;
5160         }
5161         err = i40e_dev_rx_init(pf);
5162         if (err) {
5163                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5164                 return err;
5165         }
5166
5167         return err;
5168 }
5169
5170 static int
5171 i40e_vmdq_setup(struct rte_eth_dev *dev)
5172 {
5173         struct rte_eth_conf *conf = &dev->data->dev_conf;
5174         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5175         int i, err, conf_vsis, j, loop;
5176         struct i40e_vsi *vsi;
5177         struct i40e_vmdq_info *vmdq_info;
5178         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5179         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5180
5181         /*
5182          * Disable interrupt to avoid message from VF. Furthermore, it will
5183          * avoid race condition in VSI creation/destroy.
5184          */
5185         i40e_pf_disable_irq0(hw);
5186
5187         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5188                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5189                 return -ENOTSUP;
5190         }
5191
5192         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5193         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5194                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5195                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5196                         pf->max_nb_vmdq_vsi);
5197                 return -ENOTSUP;
5198         }
5199
5200         if (pf->vmdq != NULL) {
5201                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5202                 return 0;
5203         }
5204
5205         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5206                                 sizeof(*vmdq_info) * conf_vsis, 0);
5207
5208         if (pf->vmdq == NULL) {
5209                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5210                 return -ENOMEM;
5211         }
5212
5213         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5214
5215         /* Create VMDQ VSI */
5216         for (i = 0; i < conf_vsis; i++) {
5217                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5218                                 vmdq_conf->enable_loop_back);
5219                 if (vsi == NULL) {
5220                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5221                         err = -1;
5222                         goto err_vsi_setup;
5223                 }
5224                 vmdq_info = &pf->vmdq[i];
5225                 vmdq_info->pf = pf;
5226                 vmdq_info->vsi = vsi;
5227         }
5228         pf->nb_cfg_vmdq_vsi = conf_vsis;
5229
5230         /* Configure Vlan */
5231         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5232         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5233                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5234                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5235                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5236                                         vmdq_conf->pool_map[i].vlan_id, j);
5237
5238                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5239                                                 vmdq_conf->pool_map[i].vlan_id);
5240                                 if (err) {
5241                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5242                                         err = -1;
5243                                         goto err_vsi_setup;
5244                                 }
5245                         }
5246                 }
5247         }
5248
5249         i40e_pf_enable_irq0(hw);
5250
5251         return 0;
5252
5253 err_vsi_setup:
5254         for (i = 0; i < conf_vsis; i++)
5255                 if (pf->vmdq[i].vsi == NULL)
5256                         break;
5257                 else
5258                         i40e_vsi_release(pf->vmdq[i].vsi);
5259
5260         rte_free(pf->vmdq);
5261         pf->vmdq = NULL;
5262         i40e_pf_enable_irq0(hw);
5263         return err;
5264 }
5265
5266 static void
5267 i40e_stat_update_32(struct i40e_hw *hw,
5268                    uint32_t reg,
5269                    bool offset_loaded,
5270                    uint64_t *offset,
5271                    uint64_t *stat)
5272 {
5273         uint64_t new_data;
5274
5275         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5276         if (!offset_loaded)
5277                 *offset = new_data;
5278
5279         if (new_data >= *offset)
5280                 *stat = (uint64_t)(new_data - *offset);
5281         else
5282                 *stat = (uint64_t)((new_data +
5283                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5284 }
5285
5286 static void
5287 i40e_stat_update_48(struct i40e_hw *hw,
5288                    uint32_t hireg,
5289                    uint32_t loreg,
5290                    bool offset_loaded,
5291                    uint64_t *offset,
5292                    uint64_t *stat)
5293 {
5294         uint64_t new_data;
5295
5296         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5297         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5298                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5299
5300         if (!offset_loaded)
5301                 *offset = new_data;
5302
5303         if (new_data >= *offset)
5304                 *stat = new_data - *offset;
5305         else
5306                 *stat = (uint64_t)((new_data +
5307                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5308
5309         *stat &= I40E_48_BIT_MASK;
5310 }
5311
5312 /* Disable IRQ0 */
5313 void
5314 i40e_pf_disable_irq0(struct i40e_hw *hw)
5315 {
5316         /* Disable all interrupt types */
5317         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5318         I40E_WRITE_FLUSH(hw);
5319 }
5320
5321 /* Enable IRQ0 */
5322 void
5323 i40e_pf_enable_irq0(struct i40e_hw *hw)
5324 {
5325         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5326                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5327                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5328                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5329         I40E_WRITE_FLUSH(hw);
5330 }
5331
5332 static void
5333 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5334 {
5335         /* read pending request and disable first */
5336         i40e_pf_disable_irq0(hw);
5337         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5338         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5339                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5340
5341         if (no_queue)
5342                 /* Link no queues with irq0 */
5343                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5344                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5345 }
5346
5347 static void
5348 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5349 {
5350         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5351         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5352         int i;
5353         uint16_t abs_vf_id;
5354         uint32_t index, offset, val;
5355
5356         if (!pf->vfs)
5357                 return;
5358         /**
5359          * Try to find which VF trigger a reset, use absolute VF id to access
5360          * since the reg is global register.
5361          */
5362         for (i = 0; i < pf->vf_num; i++) {
5363                 abs_vf_id = hw->func_caps.vf_base_id + i;
5364                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5365                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5366                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5367                 /* VFR event occured */
5368                 if (val & (0x1 << offset)) {
5369                         int ret;
5370
5371                         /* Clear the event first */
5372                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5373                                                         (0x1 << offset));
5374                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5375                         /**
5376                          * Only notify a VF reset event occured,
5377                          * don't trigger another SW reset
5378                          */
5379                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5380                         if (ret != I40E_SUCCESS)
5381                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5382                 }
5383         }
5384 }
5385
5386 static void
5387 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5388 {
5389         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5390         struct i40e_arq_event_info info;
5391         uint16_t pending, opcode;
5392         int ret;
5393
5394         info.buf_len = I40E_AQ_BUF_SZ;
5395         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5396         if (!info.msg_buf) {
5397                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5398                 return;
5399         }
5400
5401         pending = 1;
5402         while (pending) {
5403                 ret = i40e_clean_arq_element(hw, &info, &pending);
5404
5405                 if (ret != I40E_SUCCESS) {
5406                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5407                                     "aq_err: %u", hw->aq.asq_last_status);
5408                         break;
5409                 }
5410                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5411
5412                 switch (opcode) {
5413                 case i40e_aqc_opc_send_msg_to_pf:
5414                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5415                         i40e_pf_host_handle_vf_msg(dev,
5416                                         rte_le_to_cpu_16(info.desc.retval),
5417                                         rte_le_to_cpu_32(info.desc.cookie_high),
5418                                         rte_le_to_cpu_32(info.desc.cookie_low),
5419                                         info.msg_buf,
5420                                         info.msg_len);
5421                         break;
5422                 default:
5423                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5424                                     opcode);
5425                         break;
5426                 }
5427         }
5428         rte_free(info.msg_buf);
5429 }
5430
5431 /*
5432  * Interrupt handler is registered as the alarm callback for handling LSC
5433  * interrupt in a definite of time, in order to wait the NIC into a stable
5434  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
5435  * no need for link down interrupt.
5436  */
5437 static void
5438 i40e_dev_interrupt_delayed_handler(void *param)
5439 {
5440         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5441         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5442         uint32_t icr0;
5443
5444         /* read interrupt causes again */
5445         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5446
5447 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5448         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5449                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
5450         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5451                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
5452         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5453                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
5454         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5455                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
5456         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5457                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
5458                                                                 "state\n");
5459         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5460                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
5461         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5462                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
5463 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5464
5465         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5466                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
5467                 i40e_dev_handle_vfr_event(dev);
5468         }
5469         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5470                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
5471                 i40e_dev_handle_aq_msg(dev);
5472         }
5473
5474         /* handle the link up interrupt in an alarm callback */
5475         i40e_dev_link_update(dev, 0);
5476         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
5477
5478         i40e_pf_enable_irq0(hw);
5479         rte_intr_enable(&(dev->pci_dev->intr_handle));
5480 }
5481
5482 /**
5483  * Interrupt handler triggered by NIC  for handling
5484  * specific interrupt.
5485  *
5486  * @param handle
5487  *  Pointer to interrupt handle.
5488  * @param param
5489  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5490  *
5491  * @return
5492  *  void
5493  */
5494 static void
5495 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
5496                            void *param)
5497 {
5498         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5499         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5500         uint32_t icr0;
5501
5502         /* Disable interrupt */
5503         i40e_pf_disable_irq0(hw);
5504
5505         /* read out interrupt causes */
5506         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5507
5508         /* No interrupt event indicated */
5509         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5510                 PMD_DRV_LOG(INFO, "No interrupt event");
5511                 goto done;
5512         }
5513 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5514         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5515                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5516         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5517                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5518         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5519                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5520         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5521                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5522         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5523                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5524         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5525                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5526         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5527                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5528 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5529
5530         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5531                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5532                 i40e_dev_handle_vfr_event(dev);
5533         }
5534         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5535                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5536                 i40e_dev_handle_aq_msg(dev);
5537         }
5538
5539         /* Link Status Change interrupt */
5540         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
5541 #define I40E_US_PER_SECOND 1000000
5542                 struct rte_eth_link link;
5543
5544                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
5545                 memset(&link, 0, sizeof(link));
5546                 rte_i40e_dev_atomic_read_link_status(dev, &link);
5547                 i40e_dev_link_update(dev, 0);
5548
5549                 /*
5550                  * For link up interrupt, it needs to wait 1 second to let the
5551                  * hardware be a stable state. Otherwise several consecutive
5552                  * interrupts can be observed.
5553                  * For link down interrupt, no need to wait.
5554                  */
5555                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
5556                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
5557                         return;
5558                 else
5559                         _rte_eth_dev_callback_process(dev,
5560                                 RTE_ETH_EVENT_INTR_LSC);
5561         }
5562
5563 done:
5564         /* Enable interrupt */
5565         i40e_pf_enable_irq0(hw);
5566         rte_intr_enable(&(dev->pci_dev->intr_handle));
5567 }
5568
5569 static int
5570 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5571                          struct i40e_macvlan_filter *filter,
5572                          int total)
5573 {
5574         int ele_num, ele_buff_size;
5575         int num, actual_num, i;
5576         uint16_t flags;
5577         int ret = I40E_SUCCESS;
5578         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5579         struct i40e_aqc_add_macvlan_element_data *req_list;
5580
5581         if (filter == NULL  || total == 0)
5582                 return I40E_ERR_PARAM;
5583         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5584         ele_buff_size = hw->aq.asq_buf_size;
5585
5586         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5587         if (req_list == NULL) {
5588                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5589                 return I40E_ERR_NO_MEMORY;
5590         }
5591
5592         num = 0;
5593         do {
5594                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5595                 memset(req_list, 0, ele_buff_size);
5596
5597                 for (i = 0; i < actual_num; i++) {
5598                         (void)rte_memcpy(req_list[i].mac_addr,
5599                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5600                         req_list[i].vlan_tag =
5601                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5602
5603                         switch (filter[num + i].filter_type) {
5604                         case RTE_MAC_PERFECT_MATCH:
5605                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5606                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5607                                 break;
5608                         case RTE_MACVLAN_PERFECT_MATCH:
5609                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5610                                 break;
5611                         case RTE_MAC_HASH_MATCH:
5612                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5613                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5614                                 break;
5615                         case RTE_MACVLAN_HASH_MATCH:
5616                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5617                                 break;
5618                         default:
5619                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5620                                 ret = I40E_ERR_PARAM;
5621                                 goto DONE;
5622                         }
5623
5624                         req_list[i].queue_number = 0;
5625
5626                         req_list[i].flags = rte_cpu_to_le_16(flags);
5627                 }
5628
5629                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5630                                                 actual_num, NULL);
5631                 if (ret != I40E_SUCCESS) {
5632                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5633                         goto DONE;
5634                 }
5635                 num += actual_num;
5636         } while (num < total);
5637
5638 DONE:
5639         rte_free(req_list);
5640         return ret;
5641 }
5642
5643 static int
5644 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5645                             struct i40e_macvlan_filter *filter,
5646                             int total)
5647 {
5648         int ele_num, ele_buff_size;
5649         int num, actual_num, i;
5650         uint16_t flags;
5651         int ret = I40E_SUCCESS;
5652         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5653         struct i40e_aqc_remove_macvlan_element_data *req_list;
5654
5655         if (filter == NULL  || total == 0)
5656                 return I40E_ERR_PARAM;
5657
5658         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5659         ele_buff_size = hw->aq.asq_buf_size;
5660
5661         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5662         if (req_list == NULL) {
5663                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5664                 return I40E_ERR_NO_MEMORY;
5665         }
5666
5667         num = 0;
5668         do {
5669                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5670                 memset(req_list, 0, ele_buff_size);
5671
5672                 for (i = 0; i < actual_num; i++) {
5673                         (void)rte_memcpy(req_list[i].mac_addr,
5674                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5675                         req_list[i].vlan_tag =
5676                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5677
5678                         switch (filter[num + i].filter_type) {
5679                         case RTE_MAC_PERFECT_MATCH:
5680                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5681                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5682                                 break;
5683                         case RTE_MACVLAN_PERFECT_MATCH:
5684                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5685                                 break;
5686                         case RTE_MAC_HASH_MATCH:
5687                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5688                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5689                                 break;
5690                         case RTE_MACVLAN_HASH_MATCH:
5691                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5692                                 break;
5693                         default:
5694                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5695                                 ret = I40E_ERR_PARAM;
5696                                 goto DONE;
5697                         }
5698                         req_list[i].flags = rte_cpu_to_le_16(flags);
5699                 }
5700
5701                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5702                                                 actual_num, NULL);
5703                 if (ret != I40E_SUCCESS) {
5704                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5705                         goto DONE;
5706                 }
5707                 num += actual_num;
5708         } while (num < total);
5709
5710 DONE:
5711         rte_free(req_list);
5712         return ret;
5713 }
5714
5715 /* Find out specific MAC filter */
5716 static struct i40e_mac_filter *
5717 i40e_find_mac_filter(struct i40e_vsi *vsi,
5718                          struct ether_addr *macaddr)
5719 {
5720         struct i40e_mac_filter *f;
5721
5722         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5723                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5724                         return f;
5725         }
5726
5727         return NULL;
5728 }
5729
5730 static bool
5731 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5732                          uint16_t vlan_id)
5733 {
5734         uint32_t vid_idx, vid_bit;
5735
5736         if (vlan_id > ETH_VLAN_ID_MAX)
5737                 return 0;
5738
5739         vid_idx = I40E_VFTA_IDX(vlan_id);
5740         vid_bit = I40E_VFTA_BIT(vlan_id);
5741
5742         if (vsi->vfta[vid_idx] & vid_bit)
5743                 return 1;
5744         else
5745                 return 0;
5746 }
5747
5748 static void
5749 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5750                          uint16_t vlan_id, bool on)
5751 {
5752         uint32_t vid_idx, vid_bit;
5753
5754         if (vlan_id > ETH_VLAN_ID_MAX)
5755                 return;
5756
5757         vid_idx = I40E_VFTA_IDX(vlan_id);
5758         vid_bit = I40E_VFTA_BIT(vlan_id);
5759
5760         if (on)
5761                 vsi->vfta[vid_idx] |= vid_bit;
5762         else
5763                 vsi->vfta[vid_idx] &= ~vid_bit;
5764 }
5765
5766 /**
5767  * Find all vlan options for specific mac addr,
5768  * return with actual vlan found.
5769  */
5770 static inline int
5771 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5772                            struct i40e_macvlan_filter *mv_f,
5773                            int num, struct ether_addr *addr)
5774 {
5775         int i;
5776         uint32_t j, k;
5777
5778         /**
5779          * Not to use i40e_find_vlan_filter to decrease the loop time,
5780          * although the code looks complex.
5781           */
5782         if (num < vsi->vlan_num)
5783                 return I40E_ERR_PARAM;
5784
5785         i = 0;
5786         for (j = 0; j < I40E_VFTA_SIZE; j++) {
5787                 if (vsi->vfta[j]) {
5788                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5789                                 if (vsi->vfta[j] & (1 << k)) {
5790                                         if (i > num - 1) {
5791                                                 PMD_DRV_LOG(ERR, "vlan number "
5792                                                             "not match");
5793                                                 return I40E_ERR_PARAM;
5794                                         }
5795                                         (void)rte_memcpy(&mv_f[i].macaddr,
5796                                                         addr, ETH_ADDR_LEN);
5797                                         mv_f[i].vlan_id =
5798                                                 j * I40E_UINT32_BIT_SIZE + k;
5799                                         i++;
5800                                 }
5801                         }
5802                 }
5803         }
5804         return I40E_SUCCESS;
5805 }
5806
5807 static inline int
5808 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5809                            struct i40e_macvlan_filter *mv_f,
5810                            int num,
5811                            uint16_t vlan)
5812 {
5813         int i = 0;
5814         struct i40e_mac_filter *f;
5815
5816         if (num < vsi->mac_num)
5817                 return I40E_ERR_PARAM;
5818
5819         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5820                 if (i > num - 1) {
5821                         PMD_DRV_LOG(ERR, "buffer number not match");
5822                         return I40E_ERR_PARAM;
5823                 }
5824                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5825                                 ETH_ADDR_LEN);
5826                 mv_f[i].vlan_id = vlan;
5827                 mv_f[i].filter_type = f->mac_info.filter_type;
5828                 i++;
5829         }
5830
5831         return I40E_SUCCESS;
5832 }
5833
5834 static int
5835 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5836 {
5837         int i, num;
5838         struct i40e_mac_filter *f;
5839         struct i40e_macvlan_filter *mv_f;
5840         int ret = I40E_SUCCESS;
5841
5842         if (vsi == NULL || vsi->mac_num == 0)
5843                 return I40E_ERR_PARAM;
5844
5845         /* Case that no vlan is set */
5846         if (vsi->vlan_num == 0)
5847                 num = vsi->mac_num;
5848         else
5849                 num = vsi->mac_num * vsi->vlan_num;
5850
5851         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5852         if (mv_f == NULL) {
5853                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5854                 return I40E_ERR_NO_MEMORY;
5855         }
5856
5857         i = 0;
5858         if (vsi->vlan_num == 0) {
5859                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5860                         (void)rte_memcpy(&mv_f[i].macaddr,
5861                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5862                         mv_f[i].vlan_id = 0;
5863                         i++;
5864                 }
5865         } else {
5866                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5867                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5868                                         vsi->vlan_num, &f->mac_info.mac_addr);
5869                         if (ret != I40E_SUCCESS)
5870                                 goto DONE;
5871                         i += vsi->vlan_num;
5872                 }
5873         }
5874
5875         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5876 DONE:
5877         rte_free(mv_f);
5878
5879         return ret;
5880 }
5881
5882 int
5883 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5884 {
5885         struct i40e_macvlan_filter *mv_f;
5886         int mac_num;
5887         int ret = I40E_SUCCESS;
5888
5889         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5890                 return I40E_ERR_PARAM;
5891
5892         /* If it's already set, just return */
5893         if (i40e_find_vlan_filter(vsi,vlan))
5894                 return I40E_SUCCESS;
5895
5896         mac_num = vsi->mac_num;
5897
5898         if (mac_num == 0) {
5899                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5900                 return I40E_ERR_PARAM;
5901         }
5902
5903         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5904
5905         if (mv_f == NULL) {
5906                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5907                 return I40E_ERR_NO_MEMORY;
5908         }
5909
5910         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5911
5912         if (ret != I40E_SUCCESS)
5913                 goto DONE;
5914
5915         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5916
5917         if (ret != I40E_SUCCESS)
5918                 goto DONE;
5919
5920         i40e_set_vlan_filter(vsi, vlan, 1);
5921
5922         vsi->vlan_num++;
5923         ret = I40E_SUCCESS;
5924 DONE:
5925         rte_free(mv_f);
5926         return ret;
5927 }
5928
5929 int
5930 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5931 {
5932         struct i40e_macvlan_filter *mv_f;
5933         int mac_num;
5934         int ret = I40E_SUCCESS;
5935
5936         /**
5937          * Vlan 0 is the generic filter for untagged packets
5938          * and can't be removed.
5939          */
5940         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5941                 return I40E_ERR_PARAM;
5942
5943         /* If can't find it, just return */
5944         if (!i40e_find_vlan_filter(vsi, vlan))
5945                 return I40E_ERR_PARAM;
5946
5947         mac_num = vsi->mac_num;
5948
5949         if (mac_num == 0) {
5950                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5951                 return I40E_ERR_PARAM;
5952         }
5953
5954         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5955
5956         if (mv_f == NULL) {
5957                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5958                 return I40E_ERR_NO_MEMORY;
5959         }
5960
5961         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5962
5963         if (ret != I40E_SUCCESS)
5964                 goto DONE;
5965
5966         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
5967
5968         if (ret != I40E_SUCCESS)
5969                 goto DONE;
5970
5971         /* This is last vlan to remove, replace all mac filter with vlan 0 */
5972         if (vsi->vlan_num == 1) {
5973                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
5974                 if (ret != I40E_SUCCESS)
5975                         goto DONE;
5976
5977                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5978                 if (ret != I40E_SUCCESS)
5979                         goto DONE;
5980         }
5981
5982         i40e_set_vlan_filter(vsi, vlan, 0);
5983
5984         vsi->vlan_num--;
5985         ret = I40E_SUCCESS;
5986 DONE:
5987         rte_free(mv_f);
5988         return ret;
5989 }
5990
5991 int
5992 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
5993 {
5994         struct i40e_mac_filter *f;
5995         struct i40e_macvlan_filter *mv_f;
5996         int i, vlan_num = 0;
5997         int ret = I40E_SUCCESS;
5998
5999         /* If it's add and we've config it, return */
6000         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6001         if (f != NULL)
6002                 return I40E_SUCCESS;
6003         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6004                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6005
6006                 /**
6007                  * If vlan_num is 0, that's the first time to add mac,
6008                  * set mask for vlan_id 0.
6009                  */
6010                 if (vsi->vlan_num == 0) {
6011                         i40e_set_vlan_filter(vsi, 0, 1);
6012                         vsi->vlan_num = 1;
6013                 }
6014                 vlan_num = vsi->vlan_num;
6015         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6016                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6017                 vlan_num = 1;
6018
6019         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6020         if (mv_f == NULL) {
6021                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6022                 return I40E_ERR_NO_MEMORY;
6023         }
6024
6025         for (i = 0; i < vlan_num; i++) {
6026                 mv_f[i].filter_type = mac_filter->filter_type;
6027                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6028                                 ETH_ADDR_LEN);
6029         }
6030
6031         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6032                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6033                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6034                                         &mac_filter->mac_addr);
6035                 if (ret != I40E_SUCCESS)
6036                         goto DONE;
6037         }
6038
6039         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6040         if (ret != I40E_SUCCESS)
6041                 goto DONE;
6042
6043         /* Add the mac addr into mac list */
6044         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6045         if (f == NULL) {
6046                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6047                 ret = I40E_ERR_NO_MEMORY;
6048                 goto DONE;
6049         }
6050         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6051                         ETH_ADDR_LEN);
6052         f->mac_info.filter_type = mac_filter->filter_type;
6053         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6054         vsi->mac_num++;
6055
6056         ret = I40E_SUCCESS;
6057 DONE:
6058         rte_free(mv_f);
6059
6060         return ret;
6061 }
6062
6063 int
6064 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6065 {
6066         struct i40e_mac_filter *f;
6067         struct i40e_macvlan_filter *mv_f;
6068         int i, vlan_num;
6069         enum rte_mac_filter_type filter_type;
6070         int ret = I40E_SUCCESS;
6071
6072         /* Can't find it, return an error */
6073         f = i40e_find_mac_filter(vsi, addr);
6074         if (f == NULL)
6075                 return I40E_ERR_PARAM;
6076
6077         vlan_num = vsi->vlan_num;
6078         filter_type = f->mac_info.filter_type;
6079         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6080                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6081                 if (vlan_num == 0) {
6082                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
6083                         return I40E_ERR_PARAM;
6084                 }
6085         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6086                         filter_type == RTE_MAC_HASH_MATCH)
6087                 vlan_num = 1;
6088
6089         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6090         if (mv_f == NULL) {
6091                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6092                 return I40E_ERR_NO_MEMORY;
6093         }
6094
6095         for (i = 0; i < vlan_num; i++) {
6096                 mv_f[i].filter_type = filter_type;
6097                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6098                                 ETH_ADDR_LEN);
6099         }
6100         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6101                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6102                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6103                 if (ret != I40E_SUCCESS)
6104                         goto DONE;
6105         }
6106
6107         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6108         if (ret != I40E_SUCCESS)
6109                 goto DONE;
6110
6111         /* Remove the mac addr into mac list */
6112         TAILQ_REMOVE(&vsi->mac_list, f, next);
6113         rte_free(f);
6114         vsi->mac_num--;
6115
6116         ret = I40E_SUCCESS;
6117 DONE:
6118         rte_free(mv_f);
6119         return ret;
6120 }
6121
6122 /* Configure hash enable flags for RSS */
6123 uint64_t
6124 i40e_config_hena(uint64_t flags)
6125 {
6126         uint64_t hena = 0;
6127
6128         if (!flags)
6129                 return hena;
6130
6131         if (flags & ETH_RSS_FRAG_IPV4)
6132                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6133         if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
6134                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6135         if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
6136                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6137         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6138                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6139         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6140                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6141         if (flags & ETH_RSS_FRAG_IPV6)
6142                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6143         if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
6144                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6145         if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
6146                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6147         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6148                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6149         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6150                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6151         if (flags & ETH_RSS_L2_PAYLOAD)
6152                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6153
6154         return hena;
6155 }
6156
6157 /* Parse the hash enable flags */
6158 uint64_t
6159 i40e_parse_hena(uint64_t flags)
6160 {
6161         uint64_t rss_hf = 0;
6162
6163         if (!flags)
6164                 return rss_hf;
6165         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6166                 rss_hf |= ETH_RSS_FRAG_IPV4;
6167         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6168                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6169         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6170                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6171         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6172                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6173         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6174                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6175         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6176                 rss_hf |= ETH_RSS_FRAG_IPV6;
6177         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6178                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6179         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6180                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6181         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6182                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6183         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6184                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6185         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6186                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6187
6188         return rss_hf;
6189 }
6190
6191 /* Disable RSS */
6192 static void
6193 i40e_pf_disable_rss(struct i40e_pf *pf)
6194 {
6195         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6196         uint64_t hena;
6197
6198         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6199         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6200         hena &= ~I40E_RSS_HENA_ALL;
6201         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6202         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6203         I40E_WRITE_FLUSH(hw);
6204 }
6205
6206 static int
6207 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6208 {
6209         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6210         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6211         int ret = 0;
6212
6213         if (!key || key_len == 0) {
6214                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6215                 return 0;
6216         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6217                 sizeof(uint32_t)) {
6218                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6219                 return -EINVAL;
6220         }
6221
6222         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6223                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6224                         (struct i40e_aqc_get_set_rss_key_data *)key;
6225
6226                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6227                 if (ret)
6228                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
6229                                      "via AQ");
6230         } else {
6231                 uint32_t *hash_key = (uint32_t *)key;
6232                 uint16_t i;
6233
6234                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6235                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6236                 I40E_WRITE_FLUSH(hw);
6237         }
6238
6239         return ret;
6240 }
6241
6242 static int
6243 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6244 {
6245         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6246         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6247         int ret;
6248
6249         if (!key || !key_len)
6250                 return -EINVAL;
6251
6252         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6253                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6254                         (struct i40e_aqc_get_set_rss_key_data *)key);
6255                 if (ret) {
6256                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6257                         return ret;
6258                 }
6259         } else {
6260                 uint32_t *key_dw = (uint32_t *)key;
6261                 uint16_t i;
6262
6263                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6264                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6265         }
6266         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6267
6268         return 0;
6269 }
6270
6271 static int
6272 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6273 {
6274         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6275         uint64_t rss_hf;
6276         uint64_t hena;
6277         int ret;
6278
6279         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6280                                rss_conf->rss_key_len);
6281         if (ret)
6282                 return ret;
6283
6284         rss_hf = rss_conf->rss_hf;
6285         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6286         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6287         hena &= ~I40E_RSS_HENA_ALL;
6288         hena |= i40e_config_hena(rss_hf);
6289         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6290         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6291         I40E_WRITE_FLUSH(hw);
6292
6293         return 0;
6294 }
6295
6296 static int
6297 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6298                          struct rte_eth_rss_conf *rss_conf)
6299 {
6300         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6301         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6302         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6303         uint64_t hena;
6304
6305         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6306         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6307         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
6308                 if (rss_hf != 0) /* Enable RSS */
6309                         return -EINVAL;
6310                 return 0; /* Nothing to do */
6311         }
6312         /* RSS enabled */
6313         if (rss_hf == 0) /* Disable RSS */
6314                 return -EINVAL;
6315
6316         return i40e_hw_rss_hash_set(pf, rss_conf);
6317 }
6318
6319 static int
6320 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6321                            struct rte_eth_rss_conf *rss_conf)
6322 {
6323         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6324         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6325         uint64_t hena;
6326
6327         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6328                          &rss_conf->rss_key_len);
6329
6330         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6331         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6332         rss_conf->rss_hf = i40e_parse_hena(hena);
6333
6334         return 0;
6335 }
6336
6337 static int
6338 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6339 {
6340         switch (filter_type) {
6341         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6342                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6343                 break;
6344         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6345                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6346                 break;
6347         case RTE_TUNNEL_FILTER_IMAC_TENID:
6348                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6349                 break;
6350         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6351                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6352                 break;
6353         case ETH_TUNNEL_FILTER_IMAC:
6354                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6355                 break;
6356         case ETH_TUNNEL_FILTER_OIP:
6357                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6358                 break;
6359         case ETH_TUNNEL_FILTER_IIP:
6360                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6361                 break;
6362         default:
6363                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6364                 return -EINVAL;
6365         }
6366
6367         return 0;
6368 }
6369
6370 static int
6371 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6372                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6373                         uint8_t add)
6374 {
6375         uint16_t ip_type;
6376         uint32_t ipv4_addr;
6377         uint8_t i, tun_type = 0;
6378         /* internal varialbe to convert ipv6 byte order */
6379         uint32_t convert_ipv6[4];
6380         int val, ret = 0;
6381         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6382         struct i40e_vsi *vsi = pf->main_vsi;
6383         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
6384         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
6385
6386         cld_filter = rte_zmalloc("tunnel_filter",
6387                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6388                 0);
6389
6390         if (NULL == cld_filter) {
6391                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6392                 return -EINVAL;
6393         }
6394         pfilter = cld_filter;
6395
6396         ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6397         ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6398
6399         pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6400         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6401                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6402                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6403                 rte_memcpy(&pfilter->ipaddr.v4.data,
6404                                 &rte_cpu_to_le_32(ipv4_addr),
6405                                 sizeof(pfilter->ipaddr.v4.data));
6406         } else {
6407                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6408                 for (i = 0; i < 4; i++) {
6409                         convert_ipv6[i] =
6410                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6411                 }
6412                 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6413                                 sizeof(pfilter->ipaddr.v6.data));
6414         }
6415
6416         /* check tunneled type */
6417         switch (tunnel_filter->tunnel_type) {
6418         case RTE_TUNNEL_TYPE_VXLAN:
6419                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6420                 break;
6421         case RTE_TUNNEL_TYPE_NVGRE:
6422                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6423                 break;
6424         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6425                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6426                 break;
6427         default:
6428                 /* Other tunnel types is not supported. */
6429                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6430                 rte_free(cld_filter);
6431                 return -EINVAL;
6432         }
6433
6434         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6435                                                 &pfilter->flags);
6436         if (val < 0) {
6437                 rte_free(cld_filter);
6438                 return -EINVAL;
6439         }
6440
6441         pfilter->flags |= rte_cpu_to_le_16(
6442                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6443                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6444         pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6445         pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6446
6447         if (add)
6448                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6449         else
6450                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6451                                                 cld_filter, 1);
6452
6453         rte_free(cld_filter);
6454         return ret;
6455 }
6456
6457 static int
6458 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6459 {
6460         uint8_t i;
6461
6462         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6463                 if (pf->vxlan_ports[i] == port)
6464                         return i;
6465         }
6466
6467         return -1;
6468 }
6469
6470 static int
6471 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6472 {
6473         int  idx, ret;
6474         uint8_t filter_idx;
6475         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6476
6477         idx = i40e_get_vxlan_port_idx(pf, port);
6478
6479         /* Check if port already exists */
6480         if (idx >= 0) {
6481                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6482                 return -EINVAL;
6483         }
6484
6485         /* Now check if there is space to add the new port */
6486         idx = i40e_get_vxlan_port_idx(pf, 0);
6487         if (idx < 0) {
6488                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6489                         "not adding port %d", port);
6490                 return -ENOSPC;
6491         }
6492
6493         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6494                                         &filter_idx, NULL);
6495         if (ret < 0) {
6496                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6497                 return -1;
6498         }
6499
6500         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6501                          port,  filter_idx);
6502
6503         /* New port: add it and mark its index in the bitmap */
6504         pf->vxlan_ports[idx] = port;
6505         pf->vxlan_bitmap |= (1 << idx);
6506
6507         if (!(pf->flags & I40E_FLAG_VXLAN))
6508                 pf->flags |= I40E_FLAG_VXLAN;
6509
6510         return 0;
6511 }
6512
6513 static int
6514 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6515 {
6516         int idx;
6517         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6518
6519         if (!(pf->flags & I40E_FLAG_VXLAN)) {
6520                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6521                 return -EINVAL;
6522         }
6523
6524         idx = i40e_get_vxlan_port_idx(pf, port);
6525
6526         if (idx < 0) {
6527                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6528                 return -EINVAL;
6529         }
6530
6531         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6532                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6533                 return -1;
6534         }
6535
6536         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6537                         port, idx);
6538
6539         pf->vxlan_ports[idx] = 0;
6540         pf->vxlan_bitmap &= ~(1 << idx);
6541
6542         if (!pf->vxlan_bitmap)
6543                 pf->flags &= ~I40E_FLAG_VXLAN;
6544
6545         return 0;
6546 }
6547
6548 /* Add UDP tunneling port */
6549 static int
6550 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6551                              struct rte_eth_udp_tunnel *udp_tunnel)
6552 {
6553         int ret = 0;
6554         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6555
6556         if (udp_tunnel == NULL)
6557                 return -EINVAL;
6558
6559         switch (udp_tunnel->prot_type) {
6560         case RTE_TUNNEL_TYPE_VXLAN:
6561                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6562                 break;
6563
6564         case RTE_TUNNEL_TYPE_GENEVE:
6565         case RTE_TUNNEL_TYPE_TEREDO:
6566                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6567                 ret = -1;
6568                 break;
6569
6570         default:
6571                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6572                 ret = -1;
6573                 break;
6574         }
6575
6576         return ret;
6577 }
6578
6579 /* Remove UDP tunneling port */
6580 static int
6581 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6582                              struct rte_eth_udp_tunnel *udp_tunnel)
6583 {
6584         int ret = 0;
6585         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6586
6587         if (udp_tunnel == NULL)
6588                 return -EINVAL;
6589
6590         switch (udp_tunnel->prot_type) {
6591         case RTE_TUNNEL_TYPE_VXLAN:
6592                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6593                 break;
6594         case RTE_TUNNEL_TYPE_GENEVE:
6595         case RTE_TUNNEL_TYPE_TEREDO:
6596                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6597                 ret = -1;
6598                 break;
6599         default:
6600                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6601                 ret = -1;
6602                 break;
6603         }
6604
6605         return ret;
6606 }
6607
6608 /* Calculate the maximum number of contiguous PF queues that are configured */
6609 static int
6610 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6611 {
6612         struct rte_eth_dev_data *data = pf->dev_data;
6613         int i, num;
6614         struct i40e_rx_queue *rxq;
6615
6616         num = 0;
6617         for (i = 0; i < pf->lan_nb_qps; i++) {
6618                 rxq = data->rx_queues[i];
6619                 if (rxq && rxq->q_set)
6620                         num++;
6621                 else
6622                         break;
6623         }
6624
6625         return num;
6626 }
6627
6628 /* Configure RSS */
6629 static int
6630 i40e_pf_config_rss(struct i40e_pf *pf)
6631 {
6632         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6633         struct rte_eth_rss_conf rss_conf;
6634         uint32_t i, lut = 0;
6635         uint16_t j, num;
6636
6637         /*
6638          * If both VMDQ and RSS enabled, not all of PF queues are configured.
6639          * It's necessary to calulate the actual PF queues that are configured.
6640          */
6641         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6642                 num = i40e_pf_calc_configured_queues_num(pf);
6643         else
6644                 num = pf->dev_data->nb_rx_queues;
6645
6646         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6647         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6648                         num);
6649
6650         if (num == 0) {
6651                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6652                 return -ENOTSUP;
6653         }
6654
6655         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6656                 if (j == num)
6657                         j = 0;
6658                 lut = (lut << 8) | (j & ((0x1 <<
6659                         hw->func_caps.rss_table_entry_width) - 1));
6660                 if ((i & 3) == 3)
6661                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6662         }
6663
6664         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6665         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6666                 i40e_pf_disable_rss(pf);
6667                 return 0;
6668         }
6669         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6670                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6671                 /* Random default keys */
6672                 static uint32_t rss_key_default[] = {0x6b793944,
6673                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6674                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6675                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6676
6677                 rss_conf.rss_key = (uint8_t *)rss_key_default;
6678                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6679                                                         sizeof(uint32_t);
6680         }
6681
6682         return i40e_hw_rss_hash_set(pf, &rss_conf);
6683 }
6684
6685 static int
6686 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6687                                struct rte_eth_tunnel_filter_conf *filter)
6688 {
6689         if (pf == NULL || filter == NULL) {
6690                 PMD_DRV_LOG(ERR, "Invalid parameter");
6691                 return -EINVAL;
6692         }
6693
6694         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6695                 PMD_DRV_LOG(ERR, "Invalid queue ID");
6696                 return -EINVAL;
6697         }
6698
6699         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6700                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6701                 return -EINVAL;
6702         }
6703
6704         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6705                 (is_zero_ether_addr(&filter->outer_mac))) {
6706                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6707                 return -EINVAL;
6708         }
6709
6710         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6711                 (is_zero_ether_addr(&filter->inner_mac))) {
6712                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6713                 return -EINVAL;
6714         }
6715
6716         return 0;
6717 }
6718
6719 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6720 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
6721 static int
6722 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6723 {
6724         uint32_t val, reg;
6725         int ret = -EINVAL;
6726
6727         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6728         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6729
6730         if (len == 3) {
6731                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6732         } else if (len == 4) {
6733                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6734         } else {
6735                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6736                 return ret;
6737         }
6738
6739         if (reg != val) {
6740                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6741                                                    reg, NULL);
6742                 if (ret != 0)
6743                         return ret;
6744         } else {
6745                 ret = 0;
6746         }
6747         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6748                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6749
6750         return ret;
6751 }
6752
6753 static int
6754 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6755 {
6756         int ret = -EINVAL;
6757
6758         if (!hw || !cfg)
6759                 return -EINVAL;
6760
6761         switch (cfg->cfg_type) {
6762         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6763                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6764                 break;
6765         default:
6766                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6767                 break;
6768         }
6769
6770         return ret;
6771 }
6772
6773 static int
6774 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6775                                enum rte_filter_op filter_op,
6776                                void *arg)
6777 {
6778         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6779         int ret = I40E_ERR_PARAM;
6780
6781         switch (filter_op) {
6782         case RTE_ETH_FILTER_SET:
6783                 ret = i40e_dev_global_config_set(hw,
6784                         (struct rte_eth_global_cfg *)arg);
6785                 break;
6786         default:
6787                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6788                 break;
6789         }
6790
6791         return ret;
6792 }
6793
6794 static int
6795 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6796                           enum rte_filter_op filter_op,
6797                           void *arg)
6798 {
6799         struct rte_eth_tunnel_filter_conf *filter;
6800         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6801         int ret = I40E_SUCCESS;
6802
6803         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6804
6805         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6806                 return I40E_ERR_PARAM;
6807
6808         switch (filter_op) {
6809         case RTE_ETH_FILTER_NOP:
6810                 if (!(pf->flags & I40E_FLAG_VXLAN))
6811                         ret = I40E_NOT_SUPPORTED;
6812                 break;
6813         case RTE_ETH_FILTER_ADD:
6814                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6815                 break;
6816         case RTE_ETH_FILTER_DELETE:
6817                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6818                 break;
6819         default:
6820                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6821                 ret = I40E_ERR_PARAM;
6822                 break;
6823         }
6824
6825         return ret;
6826 }
6827
6828 static int
6829 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6830 {
6831         int ret = 0;
6832         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6833
6834         /* RSS setup */
6835         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6836                 ret = i40e_pf_config_rss(pf);
6837         else
6838                 i40e_pf_disable_rss(pf);
6839
6840         return ret;
6841 }
6842
6843 /* Get the symmetric hash enable configurations per port */
6844 static void
6845 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6846 {
6847         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6848
6849         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6850 }
6851
6852 /* Set the symmetric hash enable configurations per port */
6853 static void
6854 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6855 {
6856         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6857
6858         if (enable > 0) {
6859                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6860                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6861                                                         "been enabled");
6862                         return;
6863                 }
6864                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6865         } else {
6866                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6867                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6868                                                         "been disabled");
6869                         return;
6870                 }
6871                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6872         }
6873         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
6874         I40E_WRITE_FLUSH(hw);
6875 }
6876
6877 /*
6878  * Get global configurations of hash function type and symmetric hash enable
6879  * per flow type (pctype). Note that global configuration means it affects all
6880  * the ports on the same NIC.
6881  */
6882 static int
6883 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6884                                    struct rte_eth_hash_global_conf *g_cfg)
6885 {
6886         uint32_t reg, mask = I40E_FLOW_TYPES;
6887         uint16_t i;
6888         enum i40e_filter_pctype pctype;
6889
6890         memset(g_cfg, 0, sizeof(*g_cfg));
6891         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6892         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6893                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6894         else
6895                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6896         PMD_DRV_LOG(DEBUG, "Hash function is %s",
6897                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6898
6899         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6900                 if (!(mask & (1UL << i)))
6901                         continue;
6902                 mask &= ~(1UL << i);
6903                 /* Bit set indicats the coresponding flow type is supported */
6904                 g_cfg->valid_bit_mask[0] |= (1UL << i);
6905                 pctype = i40e_flowtype_to_pctype(i);
6906                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
6907                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
6908                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
6909         }
6910
6911         return 0;
6912 }
6913
6914 static int
6915 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
6916 {
6917         uint32_t i;
6918         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
6919
6920         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
6921                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
6922                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
6923                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
6924                                                 g_cfg->hash_func);
6925                 return -EINVAL;
6926         }
6927
6928         /*
6929          * As i40e supports less than 32 flow types, only first 32 bits need to
6930          * be checked.
6931          */
6932         mask0 = g_cfg->valid_bit_mask[0];
6933         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
6934                 if (i == 0) {
6935                         /* Check if any unsupported flow type configured */
6936                         if ((mask0 | i40e_mask) ^ i40e_mask)
6937                                 goto mask_err;
6938                 } else {
6939                         if (g_cfg->valid_bit_mask[i])
6940                                 goto mask_err;
6941                 }
6942         }
6943
6944         return 0;
6945
6946 mask_err:
6947         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
6948
6949         return -EINVAL;
6950 }
6951
6952 /*
6953  * Set global configurations of hash function type and symmetric hash enable
6954  * per flow type (pctype). Note any modifying global configuration will affect
6955  * all the ports on the same NIC.
6956  */
6957 static int
6958 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
6959                                    struct rte_eth_hash_global_conf *g_cfg)
6960 {
6961         int ret;
6962         uint16_t i;
6963         uint32_t reg;
6964         uint32_t mask0 = g_cfg->valid_bit_mask[0];
6965         enum i40e_filter_pctype pctype;
6966
6967         /* Check the input parameters */
6968         ret = i40e_hash_global_config_check(g_cfg);
6969         if (ret < 0)
6970                 return ret;
6971
6972         for (i = 0; mask0 && i < UINT32_BIT; i++) {
6973                 if (!(mask0 & (1UL << i)))
6974                         continue;
6975                 mask0 &= ~(1UL << i);
6976                 pctype = i40e_flowtype_to_pctype(i);
6977                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
6978                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
6979                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
6980         }
6981
6982         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6983         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
6984                 /* Toeplitz */
6985                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
6986                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
6987                                                                 "Toeplitz");
6988                         goto out;
6989                 }
6990                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
6991         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
6992                 /* Simple XOR */
6993                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
6994                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
6995                                                         "Simple XOR");
6996                         goto out;
6997                 }
6998                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
6999         } else
7000                 /* Use the default, and keep it as it is */
7001                 goto out;
7002
7003         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7004
7005 out:
7006         I40E_WRITE_FLUSH(hw);
7007
7008         return 0;
7009 }
7010
7011 /**
7012  * Valid input sets for hash and flow director filters per PCTYPE
7013  */
7014 static uint64_t
7015 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7016                 enum rte_filter_type filter)
7017 {
7018         uint64_t valid;
7019
7020         static const uint64_t valid_hash_inset_table[] = {
7021                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7022                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7023                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7024                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7025                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7026                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7027                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7028                         I40E_INSET_FLEX_PAYLOAD,
7029                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7030                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7031                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7032                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7033                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7034                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7035                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7036                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7037                         I40E_INSET_FLEX_PAYLOAD,
7038                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7039                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7040                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7041                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7042                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7043                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7044                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7045                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7046                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7047                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7048                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7049                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7050                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7051                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7052                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7053                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7054                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7055                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7056                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7057                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7058                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7059                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7060                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7061                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7062                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7063                         I40E_INSET_FLEX_PAYLOAD,
7064                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7065                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7066                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7067                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7068                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7069                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7070                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7071                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7072                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7073                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7074                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7075                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7076                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7077                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7078                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7079                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7080                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7081                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7082                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7083                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7084                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7085                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7086                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7087                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7088                         I40E_INSET_FLEX_PAYLOAD,
7089                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7090                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7091                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7092                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7093                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7094                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7095                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7096                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7097                         I40E_INSET_FLEX_PAYLOAD,
7098                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7099                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7100                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7101                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7102                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7103                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7104                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7105                         I40E_INSET_FLEX_PAYLOAD,
7106                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7107                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7108                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7109                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7110                         I40E_INSET_FLEX_PAYLOAD,
7111         };
7112
7113         /**
7114          * Flow director supports only fields defined in
7115          * union rte_eth_fdir_flow.
7116          */
7117         static const uint64_t valid_fdir_inset_table[] = {
7118                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7119                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7120                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7121                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7122                 I40E_INSET_IPV4_TTL,
7123                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7124                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7125                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7126                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7127                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7128                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7129                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7130                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7131                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7132                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7133                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7134                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7135                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7136                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7137                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7138                 I40E_INSET_SCTP_VT,
7139                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7140                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7141                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7142                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7143                 I40E_INSET_IPV4_TTL,
7144                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7145                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7146                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7147                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7148                 I40E_INSET_IPV6_HOP_LIMIT,
7149                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7150                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7151                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7152                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7153                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7154                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7155                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7156                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7157                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7158                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7159                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7160                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7161                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7162                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7163                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7164                 I40E_INSET_SCTP_VT,
7165                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7166                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7167                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7168                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7169                 I40E_INSET_IPV6_HOP_LIMIT,
7170                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7171                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7172                 I40E_INSET_LAST_ETHER_TYPE,
7173         };
7174
7175         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7176                 return 0;
7177         if (filter == RTE_ETH_FILTER_HASH)
7178                 valid = valid_hash_inset_table[pctype];
7179         else
7180                 valid = valid_fdir_inset_table[pctype];
7181
7182         return valid;
7183 }
7184
7185 /**
7186  * Validate if the input set is allowed for a specific PCTYPE
7187  */
7188 static int
7189 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7190                 enum rte_filter_type filter, uint64_t inset)
7191 {
7192         uint64_t valid;
7193
7194         valid = i40e_get_valid_input_set(pctype, filter);
7195         if (inset & (~valid))
7196                 return -EINVAL;
7197
7198         return 0;
7199 }
7200
7201 /* default input set fields combination per pctype */
7202 static uint64_t
7203 i40e_get_default_input_set(uint16_t pctype)
7204 {
7205         static const uint64_t default_inset_table[] = {
7206                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7207                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7208                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7209                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7210                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7211                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7212                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7213                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7214                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7215                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7216                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7217                         I40E_INSET_SCTP_VT,
7218                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7219                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7220                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7221                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7222                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7223                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7224                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7225                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7226                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7227                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7228                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7229                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7230                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7231                         I40E_INSET_SCTP_VT,
7232                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7233                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7234                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7235                         I40E_INSET_LAST_ETHER_TYPE,
7236         };
7237
7238         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7239                 return 0;
7240
7241         return default_inset_table[pctype];
7242 }
7243
7244 /**
7245  * Parse the input set from index to logical bit masks
7246  */
7247 static int
7248 i40e_parse_input_set(uint64_t *inset,
7249                      enum i40e_filter_pctype pctype,
7250                      enum rte_eth_input_set_field *field,
7251                      uint16_t size)
7252 {
7253         uint16_t i, j;
7254         int ret = -EINVAL;
7255
7256         static const struct {
7257                 enum rte_eth_input_set_field field;
7258                 uint64_t inset;
7259         } inset_convert_table[] = {
7260                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7261                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7262                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7263                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7264                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7265                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7266                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7267                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7268                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7269                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7270                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7271                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7272                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7273                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7274                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7275                         I40E_INSET_IPV6_NEXT_HDR},
7276                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7277                         I40E_INSET_IPV6_HOP_LIMIT},
7278                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7279                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7280                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7281                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7282                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7283                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7284                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7285                         I40E_INSET_SCTP_VT},
7286                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7287                         I40E_INSET_TUNNEL_DMAC},
7288                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7289                         I40E_INSET_VLAN_TUNNEL},
7290                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7291                         I40E_INSET_TUNNEL_ID},
7292                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7293                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7294                         I40E_INSET_FLEX_PAYLOAD_W1},
7295                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7296                         I40E_INSET_FLEX_PAYLOAD_W2},
7297                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7298                         I40E_INSET_FLEX_PAYLOAD_W3},
7299                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7300                         I40E_INSET_FLEX_PAYLOAD_W4},
7301                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7302                         I40E_INSET_FLEX_PAYLOAD_W5},
7303                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7304                         I40E_INSET_FLEX_PAYLOAD_W6},
7305                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7306                         I40E_INSET_FLEX_PAYLOAD_W7},
7307                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7308                         I40E_INSET_FLEX_PAYLOAD_W8},
7309         };
7310
7311         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7312                 return ret;
7313
7314         /* Only one item allowed for default or all */
7315         if (size == 1) {
7316                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7317                         *inset = i40e_get_default_input_set(pctype);
7318                         return 0;
7319                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7320                         *inset = I40E_INSET_NONE;
7321                         return 0;
7322                 }
7323         }
7324
7325         for (i = 0, *inset = 0; i < size; i++) {
7326                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7327                         if (field[i] == inset_convert_table[j].field) {
7328                                 *inset |= inset_convert_table[j].inset;
7329                                 break;
7330                         }
7331                 }
7332
7333                 /* It contains unsupported input set, return immediately */
7334                 if (j == RTE_DIM(inset_convert_table))
7335                         return ret;
7336         }
7337
7338         return 0;
7339 }
7340
7341 /**
7342  * Translate the input set from bit masks to register aware bit masks
7343  * and vice versa
7344  */
7345 static uint64_t
7346 i40e_translate_input_set_reg(uint64_t input)
7347 {
7348         uint64_t val = 0;
7349         uint16_t i;
7350
7351         static const struct {
7352                 uint64_t inset;
7353                 uint64_t inset_reg;
7354         } inset_map[] = {
7355                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7356                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7357                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7358                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7359                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7360                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7361                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7362                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7363                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7364                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7365                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7366                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7367                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7368                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7369                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7370                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7371                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7372                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7373                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7374                 {I40E_INSET_TUNNEL_DMAC,
7375                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7376                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7377                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7378                 {I40E_INSET_TUNNEL_SRC_PORT,
7379                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7380                 {I40E_INSET_TUNNEL_DST_PORT,
7381                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7382                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7383                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7384                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7385                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7386                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7387                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7388                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7389                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7390                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7391         };
7392
7393         if (input == 0)
7394                 return val;
7395
7396         /* Translate input set to register aware inset */
7397         for (i = 0; i < RTE_DIM(inset_map); i++) {
7398                 if (input & inset_map[i].inset)
7399                         val |= inset_map[i].inset_reg;
7400         }
7401
7402         return val;
7403 }
7404
7405 static int
7406 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7407 {
7408         uint8_t i, idx = 0;
7409         uint64_t inset_need_mask = inset;
7410
7411         static const struct {
7412                 uint64_t inset;
7413                 uint32_t mask;
7414         } inset_mask_map[] = {
7415                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7416                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7417                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7418                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7419                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7420                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7421                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7422                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7423         };
7424
7425         if (!inset || !mask || !nb_elem)
7426                 return 0;
7427
7428         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7429                 /* Clear the inset bit, if no MASK is required,
7430                  * for example proto + ttl
7431                  */
7432                 if ((inset & inset_mask_map[i].inset) ==
7433                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
7434                         inset_need_mask &= ~inset_mask_map[i].inset;
7435                 if (!inset_need_mask)
7436                         return 0;
7437         }
7438         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7439                 if ((inset_need_mask & inset_mask_map[i].inset) ==
7440                     inset_mask_map[i].inset) {
7441                         if (idx >= nb_elem) {
7442                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
7443                                 return -EINVAL;
7444                         }
7445                         mask[idx] = inset_mask_map[i].mask;
7446                         idx++;
7447                 }
7448         }
7449
7450         return idx;
7451 }
7452
7453 static void
7454 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7455 {
7456         uint32_t reg = i40e_read_rx_ctl(hw, addr);
7457
7458         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7459         if (reg != val)
7460                 i40e_write_rx_ctl(hw, addr, val);
7461         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7462                     (uint32_t)i40e_read_rx_ctl(hw, addr));
7463 }
7464
7465 static void
7466 i40e_filter_input_set_init(struct i40e_pf *pf)
7467 {
7468         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7469         enum i40e_filter_pctype pctype;
7470         uint64_t input_set, inset_reg;
7471         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7472         int num, i;
7473
7474         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
7475              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
7476                 if (!I40E_VALID_PCTYPE(pctype))
7477                         continue;
7478                 input_set = i40e_get_default_input_set(pctype);
7479
7480                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7481                                                    I40E_INSET_MASK_NUM_REG);
7482                 if (num < 0)
7483                         return;
7484                 inset_reg = i40e_translate_input_set_reg(input_set);
7485
7486                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7487                                       (uint32_t)(inset_reg & UINT32_MAX));
7488                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7489                                      (uint32_t)((inset_reg >>
7490                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7491                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7492                                       (uint32_t)(inset_reg & UINT32_MAX));
7493                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7494                                      (uint32_t)((inset_reg >>
7495                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7496
7497                 for (i = 0; i < num; i++) {
7498                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7499                                              mask_reg[i]);
7500                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7501                                              mask_reg[i]);
7502                 }
7503                 /*clear unused mask registers of the pctype */
7504                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
7505                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7506                                              0);
7507                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7508                                              0);
7509                 }
7510                 I40E_WRITE_FLUSH(hw);
7511
7512                 /* store the default input set */
7513                 pf->hash_input_set[pctype] = input_set;
7514                 pf->fdir.input_set[pctype] = input_set;
7515         }
7516 }
7517
7518 int
7519 i40e_hash_filter_inset_select(struct i40e_hw *hw,
7520                          struct rte_eth_input_set_conf *conf)
7521 {
7522         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
7523         enum i40e_filter_pctype pctype;
7524         uint64_t input_set, inset_reg = 0;
7525         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7526         int ret, i, num;
7527
7528         if (!conf) {
7529                 PMD_DRV_LOG(ERR, "Invalid pointer");
7530                 return -EFAULT;
7531         }
7532         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7533             conf->op != RTE_ETH_INPUT_SET_ADD) {
7534                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7535                 return -EINVAL;
7536         }
7537
7538         pctype = i40e_flowtype_to_pctype(conf->flow_type);
7539         if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
7540                 PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
7541                             conf->flow_type);
7542                 return -EINVAL;
7543         }
7544
7545         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7546                                    conf->inset_size);
7547         if (ret) {
7548                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7549                 return -EINVAL;
7550         }
7551         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
7552                                     input_set) != 0) {
7553                 PMD_DRV_LOG(ERR, "Invalid input set");
7554                 return -EINVAL;
7555         }
7556         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
7557                 /* get inset value in register */
7558                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
7559                 inset_reg <<= I40E_32_BIT_WIDTH;
7560                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
7561                 input_set |= pf->hash_input_set[pctype];
7562         }
7563         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7564                                            I40E_INSET_MASK_NUM_REG);
7565         if (num < 0)
7566                 return -EINVAL;
7567
7568         inset_reg |= i40e_translate_input_set_reg(input_set);
7569
7570         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7571                               (uint32_t)(inset_reg & UINT32_MAX));
7572         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7573                              (uint32_t)((inset_reg >>
7574                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7575
7576         for (i = 0; i < num; i++)
7577                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7578                                      mask_reg[i]);
7579         /*clear unused mask registers of the pctype */
7580         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7581                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7582                                      0);
7583         I40E_WRITE_FLUSH(hw);
7584
7585         pf->hash_input_set[pctype] = input_set;
7586         return 0;
7587 }
7588
7589 int
7590 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
7591                          struct rte_eth_input_set_conf *conf)
7592 {
7593         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7594         enum i40e_filter_pctype pctype;
7595         uint64_t input_set, inset_reg = 0;
7596         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7597         int ret, i, num;
7598
7599         if (!hw || !conf) {
7600                 PMD_DRV_LOG(ERR, "Invalid pointer");
7601                 return -EFAULT;
7602         }
7603         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7604             conf->op != RTE_ETH_INPUT_SET_ADD) {
7605                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7606                 return -EINVAL;
7607         }
7608
7609         pctype = i40e_flowtype_to_pctype(conf->flow_type);
7610         if (pctype == 0 || pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD) {
7611                 PMD_DRV_LOG(ERR, "Not supported flow type (%u)",
7612                             conf->flow_type);
7613                 return -EINVAL;
7614         }
7615         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7616                                    conf->inset_size);
7617         if (ret) {
7618                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7619                 return -EINVAL;
7620         }
7621         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
7622                                     input_set) != 0) {
7623                 PMD_DRV_LOG(ERR, "Invalid input set");
7624                 return -EINVAL;
7625         }
7626
7627         /* get inset value in register */
7628         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
7629         inset_reg <<= I40E_32_BIT_WIDTH;
7630         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
7631
7632         /* Can not change the inset reg for flex payload for fdir,
7633          * it is done by writing I40E_PRTQF_FD_FLXINSET
7634          * in i40e_set_flex_mask_on_pctype.
7635          */
7636         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
7637                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
7638         else
7639                 input_set |= pf->fdir.input_set[pctype];
7640         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7641                                            I40E_INSET_MASK_NUM_REG);
7642         if (num < 0)
7643                 return -EINVAL;
7644
7645         inset_reg |= i40e_translate_input_set_reg(input_set);
7646
7647         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7648                               (uint32_t)(inset_reg & UINT32_MAX));
7649         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7650                              (uint32_t)((inset_reg >>
7651                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7652
7653         for (i = 0; i < num; i++)
7654                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7655                                      mask_reg[i]);
7656         /*clear unused mask registers of the pctype */
7657         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7658                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7659                                      0);
7660         I40E_WRITE_FLUSH(hw);
7661
7662         pf->fdir.input_set[pctype] = input_set;
7663         return 0;
7664 }
7665
7666 static int
7667 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7668 {
7669         int ret = 0;
7670
7671         if (!hw || !info) {
7672                 PMD_DRV_LOG(ERR, "Invalid pointer");
7673                 return -EFAULT;
7674         }
7675
7676         switch (info->info_type) {
7677         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7678                 i40e_get_symmetric_hash_enable_per_port(hw,
7679                                         &(info->info.enable));
7680                 break;
7681         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7682                 ret = i40e_get_hash_filter_global_config(hw,
7683                                 &(info->info.global_conf));
7684                 break;
7685         default:
7686                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7687                                                         info->info_type);
7688                 ret = -EINVAL;
7689                 break;
7690         }
7691
7692         return ret;
7693 }
7694
7695 static int
7696 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7697 {
7698         int ret = 0;
7699
7700         if (!hw || !info) {
7701                 PMD_DRV_LOG(ERR, "Invalid pointer");
7702                 return -EFAULT;
7703         }
7704
7705         switch (info->info_type) {
7706         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7707                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7708                 break;
7709         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7710                 ret = i40e_set_hash_filter_global_config(hw,
7711                                 &(info->info.global_conf));
7712                 break;
7713         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7714                 ret = i40e_hash_filter_inset_select(hw,
7715                                                &(info->info.input_set_conf));
7716                 break;
7717
7718         default:
7719                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7720                                                         info->info_type);
7721                 ret = -EINVAL;
7722                 break;
7723         }
7724
7725         return ret;
7726 }
7727
7728 /* Operations for hash function */
7729 static int
7730 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
7731                       enum rte_filter_op filter_op,
7732                       void *arg)
7733 {
7734         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7735         int ret = 0;
7736
7737         switch (filter_op) {
7738         case RTE_ETH_FILTER_NOP:
7739                 break;
7740         case RTE_ETH_FILTER_GET:
7741                 ret = i40e_hash_filter_get(hw,
7742                         (struct rte_eth_hash_filter_info *)arg);
7743                 break;
7744         case RTE_ETH_FILTER_SET:
7745                 ret = i40e_hash_filter_set(hw,
7746                         (struct rte_eth_hash_filter_info *)arg);
7747                 break;
7748         default:
7749                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
7750                                                                 filter_op);
7751                 ret = -ENOTSUP;
7752                 break;
7753         }
7754
7755         return ret;
7756 }
7757
7758 /*
7759  * Configure ethertype filter, which can director packet by filtering
7760  * with mac address and ether_type or only ether_type
7761  */
7762 static int
7763 i40e_ethertype_filter_set(struct i40e_pf *pf,
7764                         struct rte_eth_ethertype_filter *filter,
7765                         bool add)
7766 {
7767         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7768         struct i40e_control_filter_stats stats;
7769         uint16_t flags = 0;
7770         int ret;
7771
7772         if (filter->queue >= pf->dev_data->nb_rx_queues) {
7773                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7774                 return -EINVAL;
7775         }
7776         if (filter->ether_type == ETHER_TYPE_IPv4 ||
7777                 filter->ether_type == ETHER_TYPE_IPv6) {
7778                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
7779                         " control packet filter.", filter->ether_type);
7780                 return -EINVAL;
7781         }
7782         if (filter->ether_type == ETHER_TYPE_VLAN)
7783                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
7784                         " not supported.");
7785
7786         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
7787                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
7788         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
7789                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
7790         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
7791
7792         memset(&stats, 0, sizeof(stats));
7793         ret = i40e_aq_add_rem_control_packet_filter(hw,
7794                         filter->mac_addr.addr_bytes,
7795                         filter->ether_type, flags,
7796                         pf->main_vsi->seid,
7797                         filter->queue, add, &stats, NULL);
7798
7799         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
7800                          " mac_etype_used = %u, etype_used = %u,"
7801                          " mac_etype_free = %u, etype_free = %u\n",
7802                          ret, stats.mac_etype_used, stats.etype_used,
7803                          stats.mac_etype_free, stats.etype_free);
7804         if (ret < 0)
7805                 return -ENOSYS;
7806         return 0;
7807 }
7808
7809 /*
7810  * Handle operations for ethertype filter.
7811  */
7812 static int
7813 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
7814                                 enum rte_filter_op filter_op,
7815                                 void *arg)
7816 {
7817         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7818         int ret = 0;
7819
7820         if (filter_op == RTE_ETH_FILTER_NOP)
7821                 return ret;
7822
7823         if (arg == NULL) {
7824                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
7825                             filter_op);
7826                 return -EINVAL;
7827         }
7828
7829         switch (filter_op) {
7830         case RTE_ETH_FILTER_ADD:
7831                 ret = i40e_ethertype_filter_set(pf,
7832                         (struct rte_eth_ethertype_filter *)arg,
7833                         TRUE);
7834                 break;
7835         case RTE_ETH_FILTER_DELETE:
7836                 ret = i40e_ethertype_filter_set(pf,
7837                         (struct rte_eth_ethertype_filter *)arg,
7838                         FALSE);
7839                 break;
7840         default:
7841                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
7842                 ret = -ENOSYS;
7843                 break;
7844         }
7845         return ret;
7846 }
7847
7848 static int
7849 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
7850                      enum rte_filter_type filter_type,
7851                      enum rte_filter_op filter_op,
7852                      void *arg)
7853 {
7854         int ret = 0;
7855
7856         if (dev == NULL)
7857                 return -EINVAL;
7858
7859         switch (filter_type) {
7860         case RTE_ETH_FILTER_NONE:
7861                 /* For global configuration */
7862                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
7863                 break;
7864         case RTE_ETH_FILTER_HASH:
7865                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
7866                 break;
7867         case RTE_ETH_FILTER_MACVLAN:
7868                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
7869                 break;
7870         case RTE_ETH_FILTER_ETHERTYPE:
7871                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
7872                 break;
7873         case RTE_ETH_FILTER_TUNNEL:
7874                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
7875                 break;
7876         case RTE_ETH_FILTER_FDIR:
7877                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
7878                 break;
7879         default:
7880                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
7881                                                         filter_type);
7882                 ret = -EINVAL;
7883                 break;
7884         }
7885
7886         return ret;
7887 }
7888
7889 /*
7890  * Check and enable Extended Tag.
7891  * Enabling Extended Tag is important for 40G performance.
7892  */
7893 static void
7894 i40e_enable_extended_tag(struct rte_eth_dev *dev)
7895 {
7896         uint32_t buf = 0;
7897         int ret;
7898
7899         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7900                                       PCI_DEV_CAP_REG);
7901         if (ret < 0) {
7902                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7903                             PCI_DEV_CAP_REG);
7904                 return;
7905         }
7906         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
7907                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
7908                 return;
7909         }
7910
7911         buf = 0;
7912         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
7913                                       PCI_DEV_CTRL_REG);
7914         if (ret < 0) {
7915                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
7916                             PCI_DEV_CTRL_REG);
7917                 return;
7918         }
7919         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
7920                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
7921                 return;
7922         }
7923         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
7924         ret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf),
7925                                        PCI_DEV_CTRL_REG);
7926         if (ret < 0) {
7927                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
7928                             PCI_DEV_CTRL_REG);
7929                 return;
7930         }
7931 }
7932
7933 /*
7934  * As some registers wouldn't be reset unless a global hardware reset,
7935  * hardware initialization is needed to put those registers into an
7936  * expected initial state.
7937  */
7938 static void
7939 i40e_hw_init(struct rte_eth_dev *dev)
7940 {
7941         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7942
7943         i40e_enable_extended_tag(dev);
7944
7945         /* clear the PF Queue Filter control register */
7946         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
7947
7948         /* Disable symmetric hash per port */
7949         i40e_set_symmetric_hash_enable_per_port(hw, 0);
7950 }
7951
7952 enum i40e_filter_pctype
7953 i40e_flowtype_to_pctype(uint16_t flow_type)
7954 {
7955         static const enum i40e_filter_pctype pctype_table[] = {
7956                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
7957                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
7958                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
7959                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
7960                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
7961                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
7962                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
7963                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
7964                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
7965                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
7966                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
7967                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
7968                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
7969                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
7970                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
7971                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
7972                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
7973                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
7974                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
7975         };
7976
7977         return pctype_table[flow_type];
7978 }
7979
7980 uint16_t
7981 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
7982 {
7983         static const uint16_t flowtype_table[] = {
7984                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
7985                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7986                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
7987                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7988                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
7989                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7990                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
7991                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7992                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
7993                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
7994                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7995                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
7996                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7997                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
7998                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7999                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8000                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8001                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8002                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8003         };
8004
8005         return flowtype_table[pctype];
8006 }
8007
8008 /*
8009  * On X710, performance number is far from the expectation on recent firmware
8010  * versions; on XL710, performance number is also far from the expectation on
8011  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8012  * mode is enabled and port MAC address is equal to the packet destination MAC
8013  * address. The fix for this issue may not be integrated in the following
8014  * firmware version. So the workaround in software driver is needed. It needs
8015  * to modify the initial values of 3 internal only registers for both X710 and
8016  * XL710. Note that the values for X710 or XL710 could be different, and the
8017  * workaround can be removed when it is fixed in firmware in the future.
8018  */
8019
8020 /* For both X710 and XL710 */
8021 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
8022 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
8023
8024 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8025 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
8026
8027 /* For X710 */
8028 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
8029 /* For XL710 */
8030 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
8031 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
8032
8033 static void
8034 i40e_configure_registers(struct i40e_hw *hw)
8035 {
8036         static struct {
8037                 uint32_t addr;
8038                 uint64_t val;
8039         } reg_table[] = {
8040                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
8041                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
8042                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8043         };
8044         uint64_t reg;
8045         uint32_t i;
8046         int ret;
8047
8048         for (i = 0; i < RTE_DIM(reg_table); i++) {
8049                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8050                         if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
8051                                 reg_table[i].val =
8052                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
8053                         else /* For X710 */
8054                                 reg_table[i].val =
8055                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
8056                 }
8057
8058                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8059                                                         &reg, NULL);
8060                 if (ret < 0) {
8061                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8062                                                         reg_table[i].addr);
8063                         break;
8064                 }
8065                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8066                                                 reg_table[i].addr, reg);
8067                 if (reg == reg_table[i].val)
8068                         continue;
8069
8070                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
8071                                                 reg_table[i].val, NULL);
8072                 if (ret < 0) {
8073                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
8074                                 "address of 0x%"PRIx32, reg_table[i].val,
8075                                                         reg_table[i].addr);
8076                         break;
8077                 }
8078                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
8079                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
8080         }
8081 }
8082
8083 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
8084 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
8085 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
8086 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
8087 static int
8088 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
8089 {
8090         uint32_t reg;
8091         int ret;
8092
8093         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
8094                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
8095                 return -EINVAL;
8096         }
8097
8098         /* Configure for double VLAN RX stripping */
8099         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
8100         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
8101                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
8102                 ret = i40e_aq_debug_write_register(hw,
8103                                                    I40E_VSI_TSR(vsi->vsi_id),
8104                                                    reg, NULL);
8105                 if (ret < 0) {
8106                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
8107                                     vsi->vsi_id);
8108                         return I40E_ERR_CONFIG;
8109                 }
8110         }
8111
8112         /* Configure for double VLAN TX insertion */
8113         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
8114         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
8115                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
8116                 ret = i40e_aq_debug_write_register(hw,
8117                                                    I40E_VSI_L2TAGSTXVALID(
8118                                                    vsi->vsi_id), reg, NULL);
8119                 if (ret < 0) {
8120                         PMD_DRV_LOG(ERR, "Failed to update "
8121                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
8122                         return I40E_ERR_CONFIG;
8123                 }
8124         }
8125
8126         return 0;
8127 }
8128
8129 /**
8130  * i40e_aq_add_mirror_rule
8131  * @hw: pointer to the hardware structure
8132  * @seid: VEB seid to add mirror rule to
8133  * @dst_id: destination vsi seid
8134  * @entries: Buffer which contains the entities to be mirrored
8135  * @count: number of entities contained in the buffer
8136  * @rule_id:the rule_id of the rule to be added
8137  *
8138  * Add a mirror rule for a given veb.
8139  *
8140  **/
8141 static enum i40e_status_code
8142 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
8143                         uint16_t seid, uint16_t dst_id,
8144                         uint16_t rule_type, uint16_t *entries,
8145                         uint16_t count, uint16_t *rule_id)
8146 {
8147         struct i40e_aq_desc desc;
8148         struct i40e_aqc_add_delete_mirror_rule cmd;
8149         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8150                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8151                 &desc.params.raw;
8152         uint16_t buff_len;
8153         enum i40e_status_code status;
8154
8155         i40e_fill_default_direct_cmd_desc(&desc,
8156                                           i40e_aqc_opc_add_mirror_rule);
8157         memset(&cmd, 0, sizeof(cmd));
8158
8159         buff_len = sizeof(uint16_t) * count;
8160         desc.datalen = rte_cpu_to_le_16(buff_len);
8161         if (buff_len > 0)
8162                 desc.flags |= rte_cpu_to_le_16(
8163                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8164         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8165                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8166         cmd.num_entries = rte_cpu_to_le_16(count);
8167         cmd.seid = rte_cpu_to_le_16(seid);
8168         cmd.destination = rte_cpu_to_le_16(dst_id);
8169
8170         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8171         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8172         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
8173                          "rule_id = %u"
8174                          " mirror_rules_used = %u, mirror_rules_free = %u,",
8175                          hw->aq.asq_last_status, resp->rule_id,
8176                          resp->mirror_rules_used, resp->mirror_rules_free);
8177         *rule_id = rte_le_to_cpu_16(resp->rule_id);
8178
8179         return status;
8180 }
8181
8182 /**
8183  * i40e_aq_del_mirror_rule
8184  * @hw: pointer to the hardware structure
8185  * @seid: VEB seid to add mirror rule to
8186  * @entries: Buffer which contains the entities to be mirrored
8187  * @count: number of entities contained in the buffer
8188  * @rule_id:the rule_id of the rule to be delete
8189  *
8190  * Delete a mirror rule for a given veb.
8191  *
8192  **/
8193 static enum i40e_status_code
8194 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8195                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8196                 uint16_t count, uint16_t rule_id)
8197 {
8198         struct i40e_aq_desc desc;
8199         struct i40e_aqc_add_delete_mirror_rule cmd;
8200         uint16_t buff_len = 0;
8201         enum i40e_status_code status;
8202         void *buff = NULL;
8203
8204         i40e_fill_default_direct_cmd_desc(&desc,
8205                                           i40e_aqc_opc_delete_mirror_rule);
8206         memset(&cmd, 0, sizeof(cmd));
8207         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8208                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8209                                                           I40E_AQ_FLAG_RD));
8210                 cmd.num_entries = count;
8211                 buff_len = sizeof(uint16_t) * count;
8212                 desc.datalen = rte_cpu_to_le_16(buff_len);
8213                 buff = (void *)entries;
8214         } else
8215                 /* rule id is filled in destination field for deleting mirror rule */
8216                 cmd.destination = rte_cpu_to_le_16(rule_id);
8217
8218         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8219                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8220         cmd.seid = rte_cpu_to_le_16(seid);
8221
8222         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8223         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
8224
8225         return status;
8226 }
8227
8228 /**
8229  * i40e_mirror_rule_set
8230  * @dev: pointer to the hardware structure
8231  * @mirror_conf: mirror rule info
8232  * @sw_id: mirror rule's sw_id
8233  * @on: enable/disable
8234  *
8235  * set a mirror rule.
8236  *
8237  **/
8238 static int
8239 i40e_mirror_rule_set(struct rte_eth_dev *dev,
8240                         struct rte_eth_mirror_conf *mirror_conf,
8241                         uint8_t sw_id, uint8_t on)
8242 {
8243         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8244         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8245         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8246         struct i40e_mirror_rule *parent = NULL;
8247         uint16_t seid, dst_seid, rule_id;
8248         uint16_t i, j = 0;
8249         int ret;
8250
8251         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
8252
8253         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
8254                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
8255                         " without veb or vfs.");
8256                 return -ENOSYS;
8257         }
8258         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
8259                 PMD_DRV_LOG(ERR, "mirror table is full.");
8260                 return -ENOSPC;
8261         }
8262         if (mirror_conf->dst_pool > pf->vf_num) {
8263                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
8264                                  mirror_conf->dst_pool);
8265                 return -EINVAL;
8266         }
8267
8268         seid = pf->main_vsi->veb->seid;
8269
8270         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8271                 if (sw_id <= it->index) {
8272                         mirr_rule = it;
8273                         break;
8274                 }
8275                 parent = it;
8276         }
8277         if (mirr_rule && sw_id == mirr_rule->index) {
8278                 if (on) {
8279                         PMD_DRV_LOG(ERR, "mirror rule exists.");
8280                         return -EEXIST;
8281                 } else {
8282                         ret = i40e_aq_del_mirror_rule(hw, seid,
8283                                         mirr_rule->rule_type,
8284                                         mirr_rule->entries,
8285                                         mirr_rule->num_entries, mirr_rule->id);
8286                         if (ret < 0) {
8287                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8288                                                    " ret = %d, aq_err = %d.",
8289                                                    ret, hw->aq.asq_last_status);
8290                                 return -ENOSYS;
8291                         }
8292                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8293                         rte_free(mirr_rule);
8294                         pf->nb_mirror_rule--;
8295                         return 0;
8296                 }
8297         } else if (!on) {
8298                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8299                 return -ENOENT;
8300         }
8301
8302         mirr_rule = rte_zmalloc("i40e_mirror_rule",
8303                                 sizeof(struct i40e_mirror_rule) , 0);
8304         if (!mirr_rule) {
8305                 PMD_DRV_LOG(ERR, "failed to allocate memory");
8306                 return I40E_ERR_NO_MEMORY;
8307         }
8308         switch (mirror_conf->rule_type) {
8309         case ETH_MIRROR_VLAN:
8310                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
8311                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
8312                                 mirr_rule->entries[j] =
8313                                         mirror_conf->vlan.vlan_id[i];
8314                                 j++;
8315                         }
8316                 }
8317                 if (j == 0) {
8318                         PMD_DRV_LOG(ERR, "vlan is not specified.");
8319                         rte_free(mirr_rule);
8320                         return -EINVAL;
8321                 }
8322                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
8323                 break;
8324         case ETH_MIRROR_VIRTUAL_POOL_UP:
8325         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
8326                 /* check if the specified pool bit is out of range */
8327                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
8328                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
8329                         rte_free(mirr_rule);
8330                         return -EINVAL;
8331                 }
8332                 for (i = 0, j = 0; i < pf->vf_num; i++) {
8333                         if (mirror_conf->pool_mask & (1ULL << i)) {
8334                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
8335                                 j++;
8336                         }
8337                 }
8338                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
8339                         /* add pf vsi to entries */
8340                         mirr_rule->entries[j] = pf->main_vsi_seid;
8341                         j++;
8342                 }
8343                 if (j == 0) {
8344                         PMD_DRV_LOG(ERR, "pool is not specified.");
8345                         rte_free(mirr_rule);
8346                         return -EINVAL;
8347                 }
8348                 /* egress and ingress in aq commands means from switch but not port */
8349                 mirr_rule->rule_type =
8350                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
8351                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
8352                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
8353                 break;
8354         case ETH_MIRROR_UPLINK_PORT:
8355                 /* egress and ingress in aq commands means from switch but not port*/
8356                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
8357                 break;
8358         case ETH_MIRROR_DOWNLINK_PORT:
8359                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
8360                 break;
8361         default:
8362                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
8363                         mirror_conf->rule_type);
8364                 rte_free(mirr_rule);
8365                 return -EINVAL;
8366         }
8367
8368         /* If the dst_pool is equal to vf_num, consider it as PF */
8369         if (mirror_conf->dst_pool == pf->vf_num)
8370                 dst_seid = pf->main_vsi_seid;
8371         else
8372                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
8373
8374         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
8375                                       mirr_rule->rule_type, mirr_rule->entries,
8376                                       j, &rule_id);
8377         if (ret < 0) {
8378                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
8379                                    " ret = %d, aq_err = %d.",
8380                                    ret, hw->aq.asq_last_status);
8381                 rte_free(mirr_rule);
8382                 return -ENOSYS;
8383         }
8384
8385         mirr_rule->index = sw_id;
8386         mirr_rule->num_entries = j;
8387         mirr_rule->id = rule_id;
8388         mirr_rule->dst_vsi_seid = dst_seid;
8389
8390         if (parent)
8391                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
8392         else
8393                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
8394
8395         pf->nb_mirror_rule++;
8396         return 0;
8397 }
8398
8399 /**
8400  * i40e_mirror_rule_reset
8401  * @dev: pointer to the device
8402  * @sw_id: mirror rule's sw_id
8403  *
8404  * reset a mirror rule.
8405  *
8406  **/
8407 static int
8408 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
8409 {
8410         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8411         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8412         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8413         uint16_t seid;
8414         int ret;
8415
8416         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
8417
8418         seid = pf->main_vsi->veb->seid;
8419
8420         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8421                 if (sw_id == it->index) {
8422                         mirr_rule = it;
8423                         break;
8424                 }
8425         }
8426         if (mirr_rule) {
8427                 ret = i40e_aq_del_mirror_rule(hw, seid,
8428                                 mirr_rule->rule_type,
8429                                 mirr_rule->entries,
8430                                 mirr_rule->num_entries, mirr_rule->id);
8431                 if (ret < 0) {
8432                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8433                                            " status = %d, aq_err = %d.",
8434                                            ret, hw->aq.asq_last_status);
8435                         return -ENOSYS;
8436                 }
8437                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8438                 rte_free(mirr_rule);
8439                 pf->nb_mirror_rule--;
8440         } else {
8441                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8442                 return -ENOENT;
8443         }
8444         return 0;
8445 }
8446
8447 static uint64_t
8448 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
8449 {
8450         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8451         uint64_t systim_cycles;
8452
8453         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
8454         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
8455                         << 32;
8456
8457         return systim_cycles;
8458 }
8459
8460 static uint64_t
8461 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
8462 {
8463         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8464         uint64_t rx_tstamp;
8465
8466         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
8467         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
8468                         << 32;
8469
8470         return rx_tstamp;
8471 }
8472
8473 static uint64_t
8474 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
8475 {
8476         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8477         uint64_t tx_tstamp;
8478
8479         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
8480         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
8481                         << 32;
8482
8483         return tx_tstamp;
8484 }
8485
8486 static void
8487 i40e_start_timecounters(struct rte_eth_dev *dev)
8488 {
8489         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8490         struct i40e_adapter *adapter =
8491                         (struct i40e_adapter *)dev->data->dev_private;
8492         struct rte_eth_link link;
8493         uint32_t tsync_inc_l;
8494         uint32_t tsync_inc_h;
8495
8496         /* Get current link speed. */
8497         memset(&link, 0, sizeof(link));
8498         i40e_dev_link_update(dev, 1);
8499         rte_i40e_dev_atomic_read_link_status(dev, &link);
8500
8501         switch (link.link_speed) {
8502         case ETH_SPEED_NUM_40G:
8503                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
8504                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
8505                 break;
8506         case ETH_SPEED_NUM_10G:
8507                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
8508                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
8509                 break;
8510         case ETH_SPEED_NUM_1G:
8511                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
8512                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
8513                 break;
8514         default:
8515                 tsync_inc_l = 0x0;
8516                 tsync_inc_h = 0x0;
8517         }
8518
8519         /* Set the timesync increment value. */
8520         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
8521         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
8522
8523         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
8524         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8525         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8526
8527         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8528         adapter->systime_tc.cc_shift = 0;
8529         adapter->systime_tc.nsec_mask = 0;
8530
8531         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8532         adapter->rx_tstamp_tc.cc_shift = 0;
8533         adapter->rx_tstamp_tc.nsec_mask = 0;
8534
8535         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8536         adapter->tx_tstamp_tc.cc_shift = 0;
8537         adapter->tx_tstamp_tc.nsec_mask = 0;
8538 }
8539
8540 static int
8541 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
8542 {
8543         struct i40e_adapter *adapter =
8544                         (struct i40e_adapter *)dev->data->dev_private;
8545
8546         adapter->systime_tc.nsec += delta;
8547         adapter->rx_tstamp_tc.nsec += delta;
8548         adapter->tx_tstamp_tc.nsec += delta;
8549
8550         return 0;
8551 }
8552
8553 static int
8554 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
8555 {
8556         uint64_t ns;
8557         struct i40e_adapter *adapter =
8558                         (struct i40e_adapter *)dev->data->dev_private;
8559
8560         ns = rte_timespec_to_ns(ts);
8561
8562         /* Set the timecounters to a new value. */
8563         adapter->systime_tc.nsec = ns;
8564         adapter->rx_tstamp_tc.nsec = ns;
8565         adapter->tx_tstamp_tc.nsec = ns;
8566
8567         return 0;
8568 }
8569
8570 static int
8571 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
8572 {
8573         uint64_t ns, systime_cycles;
8574         struct i40e_adapter *adapter =
8575                         (struct i40e_adapter *)dev->data->dev_private;
8576
8577         systime_cycles = i40e_read_systime_cyclecounter(dev);
8578         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
8579         *ts = rte_ns_to_timespec(ns);
8580
8581         return 0;
8582 }
8583
8584 static int
8585 i40e_timesync_enable(struct rte_eth_dev *dev)
8586 {
8587         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8588         uint32_t tsync_ctl_l;
8589         uint32_t tsync_ctl_h;
8590
8591         /* Stop the timesync system time. */
8592         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8593         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8594         /* Reset the timesync system time value. */
8595         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
8596         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
8597
8598         i40e_start_timecounters(dev);
8599
8600         /* Clear timesync registers. */
8601         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8602         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
8603         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
8604         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
8605         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
8606         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
8607
8608         /* Enable timestamping of PTP packets. */
8609         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8610         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
8611
8612         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8613         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
8614         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
8615
8616         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8617         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8618
8619         return 0;
8620 }
8621
8622 static int
8623 i40e_timesync_disable(struct rte_eth_dev *dev)
8624 {
8625         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8626         uint32_t tsync_ctl_l;
8627         uint32_t tsync_ctl_h;
8628
8629         /* Disable timestamping of transmitted PTP packets. */
8630         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8631         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
8632
8633         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8634         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
8635
8636         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8637         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8638
8639         /* Reset the timesync increment value. */
8640         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8641         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8642
8643         return 0;
8644 }
8645
8646 static int
8647 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
8648                                 struct timespec *timestamp, uint32_t flags)
8649 {
8650         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8651         struct i40e_adapter *adapter =
8652                 (struct i40e_adapter *)dev->data->dev_private;
8653
8654         uint32_t sync_status;
8655         uint32_t index = flags & 0x03;
8656         uint64_t rx_tstamp_cycles;
8657         uint64_t ns;
8658
8659         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
8660         if ((sync_status & (1 << index)) == 0)
8661                 return -EINVAL;
8662
8663         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
8664         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
8665         *timestamp = rte_ns_to_timespec(ns);
8666
8667         return 0;
8668 }
8669
8670 static int
8671 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
8672                                 struct timespec *timestamp)
8673 {
8674         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8675         struct i40e_adapter *adapter =
8676                 (struct i40e_adapter *)dev->data->dev_private;
8677
8678         uint32_t sync_status;
8679         uint64_t tx_tstamp_cycles;
8680         uint64_t ns;
8681
8682         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8683         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
8684                 return -EINVAL;
8685
8686         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
8687         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
8688         *timestamp = rte_ns_to_timespec(ns);
8689
8690         return 0;
8691 }
8692
8693 /*
8694  * i40e_parse_dcb_configure - parse dcb configure from user
8695  * @dev: the device being configured
8696  * @dcb_cfg: pointer of the result of parse
8697  * @*tc_map: bit map of enabled traffic classes
8698  *
8699  * Returns 0 on success, negative value on failure
8700  */
8701 static int
8702 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
8703                          struct i40e_dcbx_config *dcb_cfg,
8704                          uint8_t *tc_map)
8705 {
8706         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
8707         uint8_t i, tc_bw, bw_lf;
8708
8709         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
8710
8711         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
8712         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
8713                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
8714                 return -EINVAL;
8715         }
8716
8717         /* assume each tc has the same bw */
8718         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
8719         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8720                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
8721         /* to ensure the sum of tcbw is equal to 100 */
8722         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
8723         for (i = 0; i < bw_lf; i++)
8724                 dcb_cfg->etscfg.tcbwtable[i]++;
8725
8726         /* assume each tc has the same Transmission Selection Algorithm */
8727         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
8728                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
8729
8730         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
8731                 dcb_cfg->etscfg.prioritytable[i] =
8732                                 dcb_rx_conf->dcb_tc[i];
8733
8734         /* FW needs one App to configure HW */
8735         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
8736         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
8737         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
8738         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
8739
8740         if (dcb_rx_conf->nb_tcs == 0)
8741                 *tc_map = 1; /* tc0 only */
8742         else
8743                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
8744
8745         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
8746                 dcb_cfg->pfc.willing = 0;
8747                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
8748                 dcb_cfg->pfc.pfcenable = *tc_map;
8749         }
8750         return 0;
8751 }
8752
8753
8754 static enum i40e_status_code
8755 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
8756                               struct i40e_aqc_vsi_properties_data *info,
8757                               uint8_t enabled_tcmap)
8758 {
8759         enum i40e_status_code ret;
8760         int i, total_tc = 0;
8761         uint16_t qpnum_per_tc, bsf, qp_idx;
8762         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
8763         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
8764         uint16_t used_queues;
8765
8766         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
8767         if (ret != I40E_SUCCESS)
8768                 return ret;
8769
8770         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8771                 if (enabled_tcmap & (1 << i))
8772                         total_tc++;
8773         }
8774         if (total_tc == 0)
8775                 total_tc = 1;
8776         vsi->enabled_tc = enabled_tcmap;
8777
8778         /* different VSI has different queues assigned */
8779         if (vsi->type == I40E_VSI_MAIN)
8780                 used_queues = dev_data->nb_rx_queues -
8781                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8782         else if (vsi->type == I40E_VSI_VMDQ2)
8783                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
8784         else {
8785                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
8786                 return I40E_ERR_NO_AVAILABLE_VSI;
8787         }
8788
8789         qpnum_per_tc = used_queues / total_tc;
8790         /* Number of queues per enabled TC */
8791         if (qpnum_per_tc == 0) {
8792                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
8793                 return I40E_ERR_INVALID_QP_ID;
8794         }
8795         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
8796                                 I40E_MAX_Q_PER_TC);
8797         bsf = rte_bsf32(qpnum_per_tc);
8798
8799         /**
8800          * Configure TC and queue mapping parameters, for enabled TC,
8801          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
8802          * default queue will serve it.
8803          */
8804         qp_idx = 0;
8805         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8806                 if (vsi->enabled_tc & (1 << i)) {
8807                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
8808                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
8809                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
8810                         qp_idx += qpnum_per_tc;
8811                 } else
8812                         info->tc_mapping[i] = 0;
8813         }
8814
8815         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
8816         if (vsi->type == I40E_VSI_SRIOV) {
8817                 info->mapping_flags |=
8818                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
8819                 for (i = 0; i < vsi->nb_qps; i++)
8820                         info->queue_mapping[i] =
8821                                 rte_cpu_to_le_16(vsi->base_queue + i);
8822         } else {
8823                 info->mapping_flags |=
8824                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
8825                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
8826         }
8827         info->valid_sections |=
8828                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
8829
8830         return I40E_SUCCESS;
8831 }
8832
8833 /*
8834  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
8835  * @veb: VEB to be configured
8836  * @tc_map: enabled TC bitmap
8837  *
8838  * Returns 0 on success, negative value on failure
8839  */
8840 static enum i40e_status_code
8841 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
8842 {
8843         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
8844         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
8845         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
8846         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
8847         enum i40e_status_code ret = I40E_SUCCESS;
8848         int i;
8849         uint32_t bw_max;
8850
8851         /* Check if enabled_tc is same as existing or new TCs */
8852         if (veb->enabled_tc == tc_map)
8853                 return ret;
8854
8855         /* configure tc bandwidth */
8856         memset(&veb_bw, 0, sizeof(veb_bw));
8857         veb_bw.tc_valid_bits = tc_map;
8858         /* Enable ETS TCs with equal BW Share for now across all VSIs */
8859         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8860                 if (tc_map & BIT_ULL(i))
8861                         veb_bw.tc_bw_share_credits[i] = 1;
8862         }
8863         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
8864                                                    &veb_bw, NULL);
8865         if (ret) {
8866                 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
8867                                   " per TC failed = %d",
8868                                   hw->aq.asq_last_status);
8869                 return ret;
8870         }
8871
8872         memset(&ets_query, 0, sizeof(ets_query));
8873         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
8874                                                    &ets_query, NULL);
8875         if (ret != I40E_SUCCESS) {
8876                 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
8877                                  " configuration %u", hw->aq.asq_last_status);
8878                 return ret;
8879         }
8880         memset(&bw_query, 0, sizeof(bw_query));
8881         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
8882                                                   &bw_query, NULL);
8883         if (ret != I40E_SUCCESS) {
8884                 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
8885                                  " configuration %u", hw->aq.asq_last_status);
8886                 return ret;
8887         }
8888
8889         /* store and print out BW info */
8890         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
8891         veb->bw_info.bw_max = ets_query.tc_bw_max;
8892         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
8893         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
8894         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
8895                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
8896                      I40E_16_BIT_WIDTH);
8897         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8898                 veb->bw_info.bw_ets_share_credits[i] =
8899                                 bw_query.tc_bw_share_credits[i];
8900                 veb->bw_info.bw_ets_credits[i] =
8901                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
8902                 /* 4 bits per TC, 4th bit is reserved */
8903                 veb->bw_info.bw_ets_max[i] =
8904                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
8905                                   RTE_LEN2MASK(3, uint8_t));
8906                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
8907                             veb->bw_info.bw_ets_share_credits[i]);
8908                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
8909                             veb->bw_info.bw_ets_credits[i]);
8910                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
8911                             veb->bw_info.bw_ets_max[i]);
8912         }
8913
8914         veb->enabled_tc = tc_map;
8915
8916         return ret;
8917 }
8918
8919
8920 /*
8921  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
8922  * @vsi: VSI to be configured
8923  * @tc_map: enabled TC bitmap
8924  *
8925  * Returns 0 on success, negative value on failure
8926  */
8927 static enum i40e_status_code
8928 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
8929 {
8930         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
8931         struct i40e_vsi_context ctxt;
8932         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
8933         enum i40e_status_code ret = I40E_SUCCESS;
8934         int i;
8935
8936         /* Check if enabled_tc is same as existing or new TCs */
8937         if (vsi->enabled_tc == tc_map)
8938                 return ret;
8939
8940         /* configure tc bandwidth */
8941         memset(&bw_data, 0, sizeof(bw_data));
8942         bw_data.tc_valid_bits = tc_map;
8943         /* Enable ETS TCs with equal BW Share for now across all VSIs */
8944         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
8945                 if (tc_map & BIT_ULL(i))
8946                         bw_data.tc_bw_credits[i] = 1;
8947         }
8948         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
8949         if (ret) {
8950                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
8951                         " per TC failed = %d",
8952                         hw->aq.asq_last_status);
8953                 goto out;
8954         }
8955         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
8956                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
8957
8958         /* Update Queue Pairs Mapping for currently enabled UPs */
8959         ctxt.seid = vsi->seid;
8960         ctxt.pf_num = hw->pf_id;
8961         ctxt.vf_num = 0;
8962         ctxt.uplink_seid = vsi->uplink_seid;
8963         ctxt.info = vsi->info;
8964         i40e_get_cap(hw);
8965         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
8966         if (ret)
8967                 goto out;
8968
8969         /* Update the VSI after updating the VSI queue-mapping information */
8970         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8971         if (ret) {
8972                 PMD_INIT_LOG(ERR, "Failed to configure "
8973                             "TC queue mapping = %d",
8974                             hw->aq.asq_last_status);
8975                 goto out;
8976         }
8977         /* update the local VSI info with updated queue map */
8978         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
8979                                         sizeof(vsi->info.tc_mapping));
8980         (void)rte_memcpy(&vsi->info.queue_mapping,
8981                         &ctxt.info.queue_mapping,
8982                 sizeof(vsi->info.queue_mapping));
8983         vsi->info.mapping_flags = ctxt.info.mapping_flags;
8984         vsi->info.valid_sections = 0;
8985
8986         /* query and update current VSI BW information */
8987         ret = i40e_vsi_get_bw_config(vsi);
8988         if (ret) {
8989                 PMD_INIT_LOG(ERR,
8990                          "Failed updating vsi bw info, err %s aq_err %s",
8991                          i40e_stat_str(hw, ret),
8992                          i40e_aq_str(hw, hw->aq.asq_last_status));
8993                 goto out;
8994         }
8995
8996         vsi->enabled_tc = tc_map;
8997
8998 out:
8999         return ret;
9000 }
9001
9002 /*
9003  * i40e_dcb_hw_configure - program the dcb setting to hw
9004  * @pf: pf the configuration is taken on
9005  * @new_cfg: new configuration
9006  * @tc_map: enabled TC bitmap
9007  *
9008  * Returns 0 on success, negative value on failure
9009  */
9010 static enum i40e_status_code
9011 i40e_dcb_hw_configure(struct i40e_pf *pf,
9012                       struct i40e_dcbx_config *new_cfg,
9013                       uint8_t tc_map)
9014 {
9015         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9016         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9017         struct i40e_vsi *main_vsi = pf->main_vsi;
9018         struct i40e_vsi_list *vsi_list;
9019         enum i40e_status_code ret;
9020         int i;
9021         uint32_t val;
9022
9023         /* Use the FW API if FW > v4.4*/
9024         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9025               (hw->aq.fw_maj_ver >= 5))) {
9026                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
9027                                   " to configure DCB");
9028                 return I40E_ERR_FIRMWARE_API_VERSION;
9029         }
9030
9031         /* Check if need reconfiguration */
9032         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9033                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9034                 return I40E_SUCCESS;
9035         }
9036
9037         /* Copy the new config to the current config */
9038         *old_cfg = *new_cfg;
9039         old_cfg->etsrec = old_cfg->etscfg;
9040         ret = i40e_set_dcb_config(hw);
9041         if (ret) {
9042                 PMD_INIT_LOG(ERR,
9043                          "Set DCB Config failed, err %s aq_err %s\n",
9044                          i40e_stat_str(hw, ret),
9045                          i40e_aq_str(hw, hw->aq.asq_last_status));
9046                 return ret;
9047         }
9048         /* set receive Arbiter to RR mode and ETS scheme by default */
9049         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9050                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9051                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
9052                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9053                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9054                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9055                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9056                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9057                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9058                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9059                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9060                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9061                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9062         }
9063         /* get local mib to check whether it is configured correctly */
9064         /* IEEE mode */
9065         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9066         /* Get Local DCB Config */
9067         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9068                                      &hw->local_dcbx_config);
9069
9070         /* if Veb is created, need to update TC of it at first */
9071         if (main_vsi->veb) {
9072                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
9073                 if (ret)
9074                         PMD_INIT_LOG(WARNING,
9075                                  "Failed configuring TC for VEB seid=%d\n",
9076                                  main_vsi->veb->seid);
9077         }
9078         /* Update each VSI */
9079         i40e_vsi_config_tc(main_vsi, tc_map);
9080         if (main_vsi->veb) {
9081                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
9082                         /* Beside main VSI and VMDQ VSIs, only enable default
9083                          * TC for other VSIs
9084                          */
9085                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
9086                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9087                                                          tc_map);
9088                         else
9089                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9090                                                          I40E_DEFAULT_TCMAP);
9091                         if (ret)
9092                                 PMD_INIT_LOG(WARNING,
9093                                          "Failed configuring TC for VSI seid=%d\n",
9094                                          vsi_list->vsi->seid);
9095                         /* continue */
9096                 }
9097         }
9098         return I40E_SUCCESS;
9099 }
9100
9101 /*
9102  * i40e_dcb_init_configure - initial dcb config
9103  * @dev: device being configured
9104  * @sw_dcb: indicate whether dcb is sw configured or hw offload
9105  *
9106  * Returns 0 on success, negative value on failure
9107  */
9108 static int
9109 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
9110 {
9111         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9112         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9113         int ret = 0;
9114
9115         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9116                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9117                 return -ENOTSUP;
9118         }
9119
9120         /* DCB initialization:
9121          * Update DCB configuration from the Firmware and configure
9122          * LLDP MIB change event.
9123          */
9124         if (sw_dcb == TRUE) {
9125                 ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
9126                 if (ret != I40E_SUCCESS)
9127                         PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
9128
9129                 ret = i40e_init_dcb(hw);
9130                 /* if sw_dcb, lldp agent is stopped, the return from
9131                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
9132                  * adminq status.
9133                  */
9134                 if (ret != I40E_SUCCESS &&
9135                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM) {
9136                         memset(&hw->local_dcbx_config, 0,
9137                                 sizeof(struct i40e_dcbx_config));
9138                         /* set dcb default configuration */
9139                         hw->local_dcbx_config.etscfg.willing = 0;
9140                         hw->local_dcbx_config.etscfg.maxtcs = 0;
9141                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
9142                         hw->local_dcbx_config.etscfg.tsatable[0] =
9143                                                 I40E_IEEE_TSA_ETS;
9144                         hw->local_dcbx_config.etsrec =
9145                                 hw->local_dcbx_config.etscfg;
9146                         hw->local_dcbx_config.pfc.willing = 0;
9147                         hw->local_dcbx_config.pfc.pfccap =
9148                                                 I40E_MAX_TRAFFIC_CLASS;
9149                         /* FW needs one App to configure HW */
9150                         hw->local_dcbx_config.numapps = 1;
9151                         hw->local_dcbx_config.app[0].selector =
9152                                                 I40E_APP_SEL_ETHTYPE;
9153                         hw->local_dcbx_config.app[0].priority = 3;
9154                         hw->local_dcbx_config.app[0].protocolid =
9155                                                 I40E_APP_PROTOID_FCOE;
9156                         ret = i40e_set_dcb_config(hw);
9157                         if (ret) {
9158                                 PMD_INIT_LOG(ERR, "default dcb config fails."
9159                                         " err = %d, aq_err = %d.", ret,
9160                                           hw->aq.asq_last_status);
9161                                 return -ENOSYS;
9162                         }
9163                 } else {
9164                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9165                                           " aq_err = %d.", ret,
9166                                           hw->aq.asq_last_status);
9167                         return -ENOTSUP;
9168                 }
9169         } else {
9170                 ret = i40e_aq_start_lldp(hw, NULL);
9171                 if (ret != I40E_SUCCESS)
9172                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9173
9174                 ret = i40e_init_dcb(hw);
9175                 if (!ret) {
9176                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9177                                 PMD_INIT_LOG(ERR, "HW doesn't support"
9178                                                   " DCBX offload.");
9179                                 return -ENOTSUP;
9180                         }
9181                 } else {
9182                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9183                                           " aq_err = %d.", ret,
9184                                           hw->aq.asq_last_status);
9185                         return -ENOTSUP;
9186                 }
9187         }
9188         return 0;
9189 }
9190
9191 /*
9192  * i40e_dcb_setup - setup dcb related config
9193  * @dev: device being configured
9194  *
9195  * Returns 0 on success, negative value on failure
9196  */
9197 static int
9198 i40e_dcb_setup(struct rte_eth_dev *dev)
9199 {
9200         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9201         struct i40e_dcbx_config dcb_cfg;
9202         uint8_t tc_map = 0;
9203         int ret = 0;
9204
9205         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9206                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9207                 return -ENOTSUP;
9208         }
9209
9210         if (pf->vf_num != 0)
9211                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9212
9213         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9214         if (ret) {
9215                 PMD_INIT_LOG(ERR, "invalid dcb config");
9216                 return -EINVAL;
9217         }
9218         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9219         if (ret) {
9220                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
9221                 return -ENOSYS;
9222         }
9223
9224         return 0;
9225 }
9226
9227 static int
9228 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
9229                       struct rte_eth_dcb_info *dcb_info)
9230 {
9231         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9232         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9233         struct i40e_vsi *vsi = pf->main_vsi;
9234         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
9235         uint16_t bsf, tc_mapping;
9236         int i, j = 0;
9237
9238         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
9239                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
9240         else
9241                 dcb_info->nb_tcs = 1;
9242         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9243                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
9244         for (i = 0; i < dcb_info->nb_tcs; i++)
9245                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
9246
9247         /* get queue mapping if vmdq is disabled */
9248         if (!pf->nb_cfg_vmdq_vsi) {
9249                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9250                         if (!(vsi->enabled_tc & (1 << i)))
9251                                 continue;
9252                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9253                         dcb_info->tc_queue.tc_rxq[j][i].base =
9254                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9255                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9256                         dcb_info->tc_queue.tc_txq[j][i].base =
9257                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9258                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9259                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9260                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9261                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9262                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9263                 }
9264                 return 0;
9265         }
9266
9267         /* get queue mapping if vmdq is enabled */
9268         do {
9269                 vsi = pf->vmdq[j].vsi;
9270                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9271                         if (!(vsi->enabled_tc & (1 << i)))
9272                                 continue;
9273                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9274                         dcb_info->tc_queue.tc_rxq[j][i].base =
9275                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9276                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9277                         dcb_info->tc_queue.tc_txq[j][i].base =
9278                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9279                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9280                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9281                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9282                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9283                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9284                 }
9285                 j++;
9286         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
9287         return 0;
9288 }
9289
9290 static int
9291 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
9292 {
9293         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9294         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9295         uint16_t interval =
9296                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
9297         uint16_t msix_intr;
9298
9299         msix_intr = intr_handle->intr_vec[queue_id];
9300         if (msix_intr == I40E_MISC_VEC_ID)
9301                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
9302                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9303                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9304                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9305                                (interval <<
9306                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9307         else
9308                 I40E_WRITE_REG(hw,
9309                                I40E_PFINT_DYN_CTLN(msix_intr -
9310                                                    I40E_RX_VEC_START),
9311                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9312                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9313                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9314                                (interval <<
9315                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9316
9317         I40E_WRITE_FLUSH(hw);
9318         rte_intr_enable(&dev->pci_dev->intr_handle);
9319
9320         return 0;
9321 }
9322
9323 static int
9324 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
9325 {
9326         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9327         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9328         uint16_t msix_intr;
9329
9330         msix_intr = intr_handle->intr_vec[queue_id];
9331         if (msix_intr == I40E_MISC_VEC_ID)
9332                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
9333         else
9334                 I40E_WRITE_REG(hw,
9335                                I40E_PFINT_DYN_CTLN(msix_intr -
9336                                                    I40E_RX_VEC_START),
9337                                0);
9338         I40E_WRITE_FLUSH(hw);
9339
9340         return 0;
9341 }
9342
9343 static int i40e_get_regs(struct rte_eth_dev *dev,
9344                          struct rte_dev_reg_info *regs)
9345 {
9346         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9347         uint32_t *ptr_data = regs->data;
9348         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
9349         const struct i40e_reg_info *reg_info;
9350
9351         if (ptr_data == NULL) {
9352                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
9353                 regs->width = sizeof(uint32_t);
9354                 return 0;
9355         }
9356
9357         /* The first few registers have to be read using AQ operations */
9358         reg_idx = 0;
9359         while (i40e_regs_adminq[reg_idx].name) {
9360                 reg_info = &i40e_regs_adminq[reg_idx++];
9361                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9362                         for (arr_idx2 = 0;
9363                                         arr_idx2 <= reg_info->count2;
9364                                         arr_idx2++) {
9365                                 reg_offset = arr_idx * reg_info->stride1 +
9366                                         arr_idx2 * reg_info->stride2;
9367                                 reg_offset += reg_info->base_addr;
9368                                 ptr_data[reg_offset >> 2] =
9369                                         i40e_read_rx_ctl(hw, reg_offset);
9370                         }
9371         }
9372
9373         /* The remaining registers can be read using primitives */
9374         reg_idx = 0;
9375         while (i40e_regs_others[reg_idx].name) {
9376                 reg_info = &i40e_regs_others[reg_idx++];
9377                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9378                         for (arr_idx2 = 0;
9379                                         arr_idx2 <= reg_info->count2;
9380                                         arr_idx2++) {
9381                                 reg_offset = arr_idx * reg_info->stride1 +
9382                                         arr_idx2 * reg_info->stride2;
9383                                 reg_offset += reg_info->base_addr;
9384                                 ptr_data[reg_offset >> 2] =
9385                                         I40E_READ_REG(hw, reg_offset);
9386                         }
9387         }
9388
9389         return 0;
9390 }
9391
9392 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
9393 {
9394         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9395
9396         /* Convert word count to byte count */
9397         return hw->nvm.sr_size << 1;
9398 }
9399
9400 static int i40e_get_eeprom(struct rte_eth_dev *dev,
9401                            struct rte_dev_eeprom_info *eeprom)
9402 {
9403         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9404         uint16_t *data = eeprom->data;
9405         uint16_t offset, length, cnt_words;
9406         int ret_code;
9407
9408         offset = eeprom->offset >> 1;
9409         length = eeprom->length >> 1;
9410         cnt_words = length;
9411
9412         if (offset > hw->nvm.sr_size ||
9413                 offset + length > hw->nvm.sr_size) {
9414                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
9415                 return -EINVAL;
9416         }
9417
9418         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
9419
9420         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
9421         if (ret_code != I40E_SUCCESS || cnt_words != length) {
9422                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
9423                 return -EIO;
9424         }
9425
9426         return 0;
9427 }
9428
9429 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
9430                                       struct ether_addr *mac_addr)
9431 {
9432         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9433
9434         if (!is_valid_assigned_ether_addr(mac_addr)) {
9435                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
9436                 return;
9437         }
9438
9439         /* Flags: 0x3 updates port address */
9440         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
9441 }
9442
9443 static int
9444 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
9445 {
9446         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9447         struct rte_eth_dev_data *dev_data = pf->dev_data;
9448         uint32_t frame_size = mtu + ETHER_HDR_LEN
9449                               + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
9450         int ret = 0;
9451
9452         /* check if mtu is within the allowed range */
9453         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
9454                 return -EINVAL;
9455
9456         /* mtu setting is forbidden if port is start */
9457         if (dev_data->dev_started) {
9458                 PMD_DRV_LOG(ERR,
9459                             "port %d must be stopped before configuration\n",
9460                             dev_data->port_id);
9461                 return -EBUSY;
9462         }
9463
9464         if (frame_size > ETHER_MAX_LEN)
9465                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
9466         else
9467                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
9468
9469         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
9470
9471         return ret;
9472 }