drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53 #include <rte_tailq.h>
  54
  55 #include "i40e_logs.h"
  56 #include "base/i40e_prototype.h"
  57 #include "base/i40e_adminq_cmd.h"
  58 #include "base/i40e_type.h"
  59 #include "base/i40e_register.h"
  60 #include "base/i40e_dcb.h"
  61 #include "i40e_ethdev.h"
  62 #include "i40e_rxtx.h"
  63 #include "i40e_pf.h"
  64 #include "i40e_regs.h"
  65
  66 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  67 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  68
  69 #define I40E_CLEAR_PXE_WAIT_MS     200
  70
  71 /* Maximun number of capability elements */
  72 #define I40E_MAX_CAP_ELE_NUM       128
  73
  74 /* Wait count and inteval */
  75 #define I40E_CHK_Q_ENA_COUNT       1000
  76 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  77
  78 /* Maximun number of VSI */
  79 #define I40E_MAX_NUM_VSIS          (384UL)
  80
  81 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  82
  83 /* Flow control default timer */
  84 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  85
  86 /* Flow control default high water */
  87 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  88
  89 /* Flow control default low water */
  90 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  91
  92 /* Flow control enable fwd bit */
  93 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  94
  95 /* Receive Packet Buffer size */
  96 #define I40E_RXPBSIZE (968 * 1024)
  97
  98 /* Kilobytes shift */
  99 #define I40E_KILOSHIFT 10
 100
 101 /* Receive Average Packet Size in Byte*/
 102 #define I40E_PACKET_AVERAGE_SIZE 128
 103
 104 /* Mask of PF interrupt causes */
 105 #define I40E_PFINT_ICR0_ENA_MASK ( \
 106                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 107                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 108                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 109                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 110                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 111                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
 112                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 113                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 114                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 115                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 116
 117 #define I40E_FLOW_TYPES ( \
 118         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 119         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 123         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 128         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 129
 130 /* Additional timesync values. */
 131 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 132 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 133 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 134 #define I40E_PRTTSYN_TSYNENA     0x80000000
 135 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 136 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 137
 138 #define I40E_MAX_PERCENT            100
 139 #define I40E_DEFAULT_DCB_APP_NUM    1
 140 #define I40E_DEFAULT_DCB_APP_PRIO   3
 141
 142 #define I40E_INSET_NONE            0x00000000000000000ULL
 143
 144 /* bit0 ~ bit 7 */
 145 #define I40E_INSET_DMAC            0x0000000000000001ULL
 146 #define I40E_INSET_SMAC            0x0000000000000002ULL
 147 #define I40E_INSET_VLAN_OUTER      0x0000000000000004ULL
 148 #define I40E_INSET_VLAN_INNER      0x0000000000000008ULL
 149 #define I40E_INSET_VLAN_TUNNEL     0x0000000000000010ULL
 150
 151 /* bit 8 ~ bit 15 */
 152 #define I40E_INSET_IPV4_SRC        0x0000000000000100ULL
 153 #define I40E_INSET_IPV4_DST        0x0000000000000200ULL
 154 #define I40E_INSET_IPV6_SRC        0x0000000000000400ULL
 155 #define I40E_INSET_IPV6_DST        0x0000000000000800ULL
 156 #define I40E_INSET_SRC_PORT        0x0000000000001000ULL
 157 #define I40E_INSET_DST_PORT        0x0000000000002000ULL
 158 #define I40E_INSET_SCTP_VT         0x0000000000004000ULL
 159
 160 /* bit 16 ~ bit 31 */
 161 #define I40E_INSET_IPV4_TOS        0x0000000000010000ULL
 162 #define I40E_INSET_IPV4_PROTO      0x0000000000020000ULL
 163 #define I40E_INSET_IPV4_TTL        0x0000000000040000ULL
 164 #define I40E_INSET_IPV6_TC         0x0000000000080000ULL
 165 #define I40E_INSET_IPV6_FLOW       0x0000000000100000ULL
 166 #define I40E_INSET_IPV6_NEXT_HDR   0x0000000000200000ULL
 167 #define I40E_INSET_IPV6_HOP_LIMIT  0x0000000000400000ULL
 168 #define I40E_INSET_TCP_FLAGS       0x0000000000800000ULL
 169
 170 /* bit 32 ~ bit 47, tunnel fields */
 171 #define I40E_INSET_TUNNEL_IPV4_DST       0x0000000100000000ULL
 172 #define I40E_INSET_TUNNEL_IPV6_DST       0x0000000200000000ULL
 173 #define I40E_INSET_TUNNEL_DMAC           0x0000000400000000ULL
 174 #define I40E_INSET_TUNNEL_SRC_PORT       0x0000000800000000ULL
 175 #define I40E_INSET_TUNNEL_DST_PORT       0x0000001000000000ULL
 176 #define I40E_INSET_TUNNEL_ID             0x0000002000000000ULL
 177
 178 /* bit 48 ~ bit 55 */
 179 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
 180
 181 /* bit 56 ~ bit 63, Flex Payload */
 182 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
 183 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
 184 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
 185 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
 186 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
 187 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
 188 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
 189 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
 190 #define I40E_INSET_FLEX_PAYLOAD \
 191         (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
 192         I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
 193         I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
 194         I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
 195
 196 /**
 197  * Below are values for writing un-exposed registers suggested
 198  * by silicon experts
 199  */
 200 /* Destination MAC address */
 201 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 202 /* Source MAC address */
 203 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 204 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 205 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 206 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 207 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 208 /* Single VLAN tag in the inner L2 header */
 209 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 210 /* Source IPv4 address */
 211 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 212 /* Destination IPv4 address */
 213 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 214 /* Source IPv4 address for X722 */
 215 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 216 /* Destination IPv4 address for X722 */
 217 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 218 /* IPv4 Protocol for X722 */
 219 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 220 /* IPv4 Time to Live for X722 */
 221 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 222 /* IPv4 Type of Service (TOS) */
 223 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 224 /* IPv4 Protocol */
 225 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 226 /* IPv4 Time to Live */
 227 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 228 /* Source IPv6 address */
 229 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 230 /* Destination IPv6 address */
 231 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 232 /* IPv6 Traffic Class (TC) */
 233 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 234 /* IPv6 Next Header */
 235 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 236 /* IPv6 Hop Limit */
 237 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 238 /* Source L4 port */
 239 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 240 /* Destination L4 port */
 241 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 242 /* SCTP verification tag */
 243 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 244 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 245 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 246 /* Source port of tunneling UDP */
 247 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 248 /* Destination port of tunneling UDP */
 249 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 250 /* UDP Tunneling ID, NVGRE/GRE key */
 251 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 252 /* Last ether type */
 253 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 254 /* Tunneling outer destination IPv4 address */
 255 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 256 /* Tunneling outer destination IPv6 address */
 257 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 258 /* 1st word of flex payload */
 259 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 260 /* 2nd word of flex payload */
 261 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 262 /* 3rd word of flex payload */
 263 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 264 /* 4th word of flex payload */
 265 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 266 /* 5th word of flex payload */
 267 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 268 /* 6th word of flex payload */
 269 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 270 /* 7th word of flex payload */
 271 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 272 /* 8th word of flex payload */
 273 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 274 /* all 8 words flex payload */
 275 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 276 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 277
 278 #define I40E_TRANSLATE_INSET 0
 279 #define I40E_TRANSLATE_REG   1
 280
 281 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 282 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 283 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 284 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 285 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 286 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 287
 288 #define I40E_GL_SWT_L2TAGCTRL(_i)             (0x001C0A70 + ((_i) * 4))
 289 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
 290 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK  \
 291         I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
 292
 293 /* PCI offset for querying capability */
 294 #define PCI_DEV_CAP_REG            0xA4
 295 /* PCI offset for enabling/disabling Extended Tag */
 296 #define PCI_DEV_CTRL_REG           0xA8
 297 /* Bit mask of Extended Tag capability */
 298 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 299 /* Bit shift of Extended Tag enable/disable */
 300 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 301 /* Bit mask of Extended Tag enable/disable */
 302 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 303
 304 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 305 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 306 static int i40e_dev_configure(struct rte_eth_dev *dev);
 307 static int i40e_dev_start(struct rte_eth_dev *dev);
 308 static void i40e_dev_stop(struct rte_eth_dev *dev);
 309 static void i40e_dev_close(struct rte_eth_dev *dev);
 310 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 311 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 312 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 313 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 314 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 315 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 316 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 317                                struct rte_eth_stats *stats);
 318 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 319                                struct rte_eth_xstat *xstats, unsigned n);
 320 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 321                                      struct rte_eth_xstat_name *xstats_names,
 322                                      unsigned limit);
 323 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 324 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 325                                             uint16_t queue_id,
 326                                             uint8_t stat_idx,
 327                                             uint8_t is_rx);
 328 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 329                               struct rte_eth_dev_info *dev_info);
 330 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 331                                 uint16_t vlan_id,
 332                                 int on);
 333 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 334                               enum rte_vlan_type vlan_type,
 335                               uint16_t tpid);
 336 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 337 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 338                                       uint16_t queue,
 339                                       int on);
 340 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 341 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 342 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 343 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 344                               struct rte_eth_fc_conf *fc_conf);
 345 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 346                               struct rte_eth_fc_conf *fc_conf);
 347 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 348                                        struct rte_eth_pfc_conf *pfc_conf);
 349 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 350                           struct ether_addr *mac_addr,
 351                           uint32_t index,
 352                           uint32_t pool);
 353 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 354 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 355                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 356                                     uint16_t reta_size);
 357 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 358                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 359                                    uint16_t reta_size);
 360
 361 static int i40e_get_cap(struct i40e_hw *hw);
 362 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 363 static int i40e_pf_setup(struct i40e_pf *pf);
 364 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 365 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 366 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 367 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 368 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 369                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 370 static void i40e_stat_update_48(struct i40e_hw *hw,
 371                                uint32_t hireg,
 372                                uint32_t loreg,
 373                                bool offset_loaded,
 374                                uint64_t *offset,
 375                                uint64_t *stat);
 376 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 377 static void i40e_dev_interrupt_handler(
 378                 __rte_unused struct rte_intr_handle *handle, void *param);
 379 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 380                                 uint32_t base, uint32_t num);
 381 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 382 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 383                         uint32_t base);
 384 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 385                         uint16_t num);
 386 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 387 static int i40e_veb_release(struct i40e_veb *veb);
 388 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 389                                                 struct i40e_vsi *vsi);
 390 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 391 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 392 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 393                                              struct i40e_macvlan_filter *mv_f,
 394                                              int num,
 395                                              struct ether_addr *addr);
 396 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 397                                              struct i40e_macvlan_filter *mv_f,
 398                                              int num,
 399                                              uint16_t vlan);
 400 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 401 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 402                                     struct rte_eth_rss_conf *rss_conf);
 403 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 404                                       struct rte_eth_rss_conf *rss_conf);
 405 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 406                                         struct rte_eth_udp_tunnel *udp_tunnel);
 407 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 408                                         struct rte_eth_udp_tunnel *udp_tunnel);
 409 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 410 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 411                         struct rte_eth_ethertype_filter *filter,
 412                         bool add);
 413 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 414                                 enum rte_filter_op filter_op,
 415                                 void *arg);
 416 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 417                                 enum rte_filter_type filter_type,
 418                                 enum rte_filter_op filter_op,
 419                                 void *arg);
 420 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 421                                   struct rte_eth_dcb_info *dcb_info);
 422 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 423 static void i40e_configure_registers(struct i40e_hw *hw);
 424 static void i40e_hw_init(struct rte_eth_dev *dev);
 425 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 426 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 427                         struct rte_eth_mirror_conf *mirror_conf,
 428                         uint8_t sw_id, uint8_t on);
 429 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 430
 431 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 432 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 433 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 434                                            struct timespec *timestamp,
 435                                            uint32_t flags);
 436 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 437                                            struct timespec *timestamp);
 438 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 439
 440 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 441
 442 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 443                                    struct timespec *timestamp);
 444 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 445                                     const struct timespec *timestamp);
 446
 447 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 448                                          uint16_t queue_id);
 449 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 450                                           uint16_t queue_id);
 451
 452 static int i40e_get_regs(struct rte_eth_dev *dev,
 453                          struct rte_dev_reg_info *regs);
 454
 455 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 456
 457 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 458                            struct rte_dev_eeprom_info *eeprom);
 459
 460 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 461                                       struct ether_addr *mac_addr);
 462
 463 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 464
 465 static const struct rte_pci_id pci_id_i40e_map[] = {
 466         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 467         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 468         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 469         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 470         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 471         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 472         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 473         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 474         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 475         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 476         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 477         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 478         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 479         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 480         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 481         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 482         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 483         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 484         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 485         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 486         { .vendor_id = 0, /* sentinel */ },
 487 };
 488
 489 static const struct eth_dev_ops i40e_eth_dev_ops = {
 490         .dev_configure                = i40e_dev_configure,
 491         .dev_start                    = i40e_dev_start,
 492         .dev_stop                     = i40e_dev_stop,
 493         .dev_close                    = i40e_dev_close,
 494         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 495         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 496         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 497         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 498         .dev_set_link_up              = i40e_dev_set_link_up,
 499         .dev_set_link_down            = i40e_dev_set_link_down,
 500         .link_update                  = i40e_dev_link_update,
 501         .stats_get                    = i40e_dev_stats_get,
 502         .xstats_get                   = i40e_dev_xstats_get,
 503         .xstats_get_names             = i40e_dev_xstats_get_names,
 504         .stats_reset                  = i40e_dev_stats_reset,
 505         .xstats_reset                 = i40e_dev_stats_reset,
 506         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 507         .dev_infos_get                = i40e_dev_info_get,
 508         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 509         .vlan_filter_set              = i40e_vlan_filter_set,
 510         .vlan_tpid_set                = i40e_vlan_tpid_set,
 511         .vlan_offload_set             = i40e_vlan_offload_set,
 512         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 513         .vlan_pvid_set                = i40e_vlan_pvid_set,
 514         .rx_queue_start               = i40e_dev_rx_queue_start,
 515         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 516         .tx_queue_start               = i40e_dev_tx_queue_start,
 517         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 518         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 519         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 520         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 521         .rx_queue_release             = i40e_dev_rx_queue_release,
 522         .rx_queue_count               = i40e_dev_rx_queue_count,
 523         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 524         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 525         .tx_queue_release             = i40e_dev_tx_queue_release,
 526         .dev_led_on                   = i40e_dev_led_on,
 527         .dev_led_off                  = i40e_dev_led_off,
 528         .flow_ctrl_get                = i40e_flow_ctrl_get,
 529         .flow_ctrl_set                = i40e_flow_ctrl_set,
 530         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 531         .mac_addr_add                 = i40e_macaddr_add,
 532         .mac_addr_remove              = i40e_macaddr_remove,
 533         .reta_update                  = i40e_dev_rss_reta_update,
 534         .reta_query                   = i40e_dev_rss_reta_query,
 535         .rss_hash_update              = i40e_dev_rss_hash_update,
 536         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 537         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 538         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 539         .filter_ctrl                  = i40e_dev_filter_ctrl,
 540         .rxq_info_get                 = i40e_rxq_info_get,
 541         .txq_info_get                 = i40e_txq_info_get,
 542         .mirror_rule_set              = i40e_mirror_rule_set,
 543         .mirror_rule_reset            = i40e_mirror_rule_reset,
 544         .timesync_enable              = i40e_timesync_enable,
 545         .timesync_disable             = i40e_timesync_disable,
 546         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 547         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 548         .get_dcb_info                 = i40e_dev_get_dcb_info,
 549         .timesync_adjust_time         = i40e_timesync_adjust_time,
 550         .timesync_read_time           = i40e_timesync_read_time,
 551         .timesync_write_time          = i40e_timesync_write_time,
 552         .get_reg                      = i40e_get_regs,
 553         .get_eeprom_length            = i40e_get_eeprom_length,
 554         .get_eeprom                   = i40e_get_eeprom,
 555         .mac_addr_set                 = i40e_set_default_mac_addr,
 556         .mtu_set                      = i40e_dev_mtu_set,
 557 };
 558
 559 /* store statistics names and its offset in stats structure */
 560 struct rte_i40e_xstats_name_off {
 561         char name[RTE_ETH_XSTATS_NAME_SIZE];
 562         unsigned offset;
 563 };
 564
 565 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 566         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 567         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 568         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 569         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 570         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 571                 rx_unknown_protocol)},
 572         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 573         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 574         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 575         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 576 };
 577
 578 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 579                 sizeof(rte_i40e_stats_strings[0]))
 580
 581 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 582         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 583                 tx_dropped_link_down)},
 584         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 585         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 586                 illegal_bytes)},
 587         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 588         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 589                 mac_local_faults)},
 590         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 591                 mac_remote_faults)},
 592         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 593                 rx_length_errors)},
 594         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 595         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 596         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 597         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 598         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 599         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 600                 rx_size_127)},
 601         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 602                 rx_size_255)},
 603         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 604                 rx_size_511)},
 605         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 606                 rx_size_1023)},
 607         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 608                 rx_size_1522)},
 609         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 610                 rx_size_big)},
 611         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 612                 rx_undersize)},
 613         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 614                 rx_oversize)},
 615         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 616                 mac_short_packet_dropped)},
 617         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 618                 rx_fragments)},
 619         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 620         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 621         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 622                 tx_size_127)},
 623         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 624                 tx_size_255)},
 625         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 626                 tx_size_511)},
 627         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 628                 tx_size_1023)},
 629         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 630                 tx_size_1522)},
 631         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 632                 tx_size_big)},
 633         {"rx_flow_director_atr_match_packets",
 634                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 635         {"rx_flow_director_sb_match_packets",
 636                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 637         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 638                 tx_lpi_status)},
 639         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 640                 rx_lpi_status)},
 641         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 642                 tx_lpi_count)},
 643         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 644                 rx_lpi_count)},
 645 };
 646
 647 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 648                 sizeof(rte_i40e_hw_port_strings[0]))
 649
 650 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 651         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 652                 priority_xon_rx)},
 653         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 654                 priority_xoff_rx)},
 655 };
 656
 657 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 658                 sizeof(rte_i40e_rxq_prio_strings[0]))
 659
 660 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 661         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 662                 priority_xon_tx)},
 663         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 664                 priority_xoff_tx)},
 665         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 666                 priority_xon_2_xoff)},
 667 };
 668
 669 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 670                 sizeof(rte_i40e_txq_prio_strings[0]))
 671
 672 static struct eth_driver rte_i40e_pmd = {
 673         .pci_drv = {
 674                 .id_table = pci_id_i40e_map,
 675                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 676                         RTE_PCI_DRV_DETACHABLE,
 677                 .probe = rte_eth_dev_pci_probe,
 678                 .remove = rte_eth_dev_pci_remove,
 679         },
 680         .eth_dev_init = eth_i40e_dev_init,
 681         .eth_dev_uninit = eth_i40e_dev_uninit,
 682         .dev_private_size = sizeof(struct i40e_adapter),
 683 };
 684
 685 static inline int
 686 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 687                                      struct rte_eth_link *link)
 688 {
 689         struct rte_eth_link *dst = link;
 690         struct rte_eth_link *src = &(dev->data->dev_link);
 691
 692         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 693                                         *(uint64_t *)src) == 0)
 694                 return -1;
 695
 696         return 0;
 697 }
 698
 699 static inline int
 700 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 701                                       struct rte_eth_link *link)
 702 {
 703         struct rte_eth_link *dst = &(dev->data->dev_link);
 704         struct rte_eth_link *src = link;
 705
 706         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 707                                         *(uint64_t *)src) == 0)
 708                 return -1;
 709
 710         return 0;
 711 }
 712
 713 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
 714 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 715
 716 #ifndef I40E_GLQF_ORT
 717 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 718 #endif
 719 #ifndef I40E_GLQF_PIT
 720 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 721 #endif
 722
 723 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 724 {
 725         /*
 726          * Initialize registers for flexible payload, which should be set by NVM.
 727          * This should be removed from code once it is fixed in NVM.
 728          */
 729         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 730         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 731         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 732         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 733         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 734         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 735         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 736         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 737         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 738         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 739         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 740         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 741
 742         /* Initialize registers for parsing packet type of QinQ */
 743         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 744         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 745 }
 746
 747 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 748
 749 /*
 750  * Add a ethertype filter to drop all flow control frames transmitted
 751  * from VSIs.
 752 */
 753 static void
 754 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 755 {
 756         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 757         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 758                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 759                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 760         int ret;
 761
 762         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 763                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 764                                 pf->main_vsi_seid, 0,
 765                                 TRUE, NULL, NULL);
 766         if (ret)
 767                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 768                                   " frames from VSIs.");
 769 }
 770
 771 static int
 772 floating_veb_list_handler(__rte_unused const char *key,
 773                           const char *floating_veb_value,
 774                           void *opaque)
 775 {
 776         int idx = 0;
 777         unsigned int count = 0;
 778         char *end = NULL;
 779         int min, max;
 780         bool *vf_floating_veb = opaque;
 781
 782         while (isblank(*floating_veb_value))
 783                 floating_veb_value++;
 784
 785         /* Reset floating VEB configuration for VFs */
 786         for (idx = 0; idx < I40E_MAX_VF; idx++)
 787                 vf_floating_veb[idx] = false;
 788
 789         min = I40E_MAX_VF;
 790         do {
 791                 while (isblank(*floating_veb_value))
 792                         floating_veb_value++;
 793                 if (*floating_veb_value == '\0')
 794                         return -1;
 795                 errno = 0;
 796                 idx = strtoul(floating_veb_value, &end, 10);
 797                 if (errno || end == NULL)
 798                         return -1;
 799                 while (isblank(*end))
 800                         end++;
 801                 if (*end == '-') {
 802                         min = idx;
 803                 } else if ((*end == ';') || (*end == '\0')) {
 804                         max = idx;
 805                         if (min == I40E_MAX_VF)
 806                                 min = idx;
 807                         if (max >= I40E_MAX_VF)
 808                                 max = I40E_MAX_VF - 1;
 809                         for (idx = min; idx <= max; idx++) {
 810                                 vf_floating_veb[idx] = true;
 811                                 count++;
 812                         }
 813                         min = I40E_MAX_VF;
 814                 } else {
 815                         return -1;
 816                 }
 817                 floating_veb_value = end + 1;
 818         } while (*end != '\0');
 819
 820         if (count == 0)
 821                 return -1;
 822
 823         return 0;
 824 }
 825
 826 static void
 827 config_vf_floating_veb(struct rte_devargs *devargs,
 828                        uint16_t floating_veb,
 829                        bool *vf_floating_veb)
 830 {
 831         struct rte_kvargs *kvlist;
 832         int i;
 833         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 834
 835         if (!floating_veb)
 836                 return;
 837         /* All the VFs attach to the floating VEB by default
 838          * when the floating VEB is enabled.
 839          */
 840         for (i = 0; i < I40E_MAX_VF; i++)
 841                 vf_floating_veb[i] = true;
 842
 843         if (devargs == NULL)
 844                 return;
 845
 846         kvlist = rte_kvargs_parse(devargs->args, NULL);
 847         if (kvlist == NULL)
 848                 return;
 849
 850         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 851                 rte_kvargs_free(kvlist);
 852                 return;
 853         }
 854         /* When the floating_veb_list parameter exists, all the VFs
 855          * will attach to the legacy VEB firstly, then configure VFs
 856          * to the floating VEB according to the floating_veb_list.
 857          */
 858         if (rte_kvargs_process(kvlist, floating_veb_list,
 859                                floating_veb_list_handler,
 860                                vf_floating_veb) < 0) {
 861                 rte_kvargs_free(kvlist);
 862                 return;
 863         }
 864         rte_kvargs_free(kvlist);
 865 }
 866
 867 static int
 868 i40e_check_floating_handler(__rte_unused const char *key,
 869                             const char *value,
 870                             __rte_unused void *opaque)
 871 {
 872         if (strcmp(value, "1"))
 873                 return -1;
 874
 875         return 0;
 876 }
 877
 878 static int
 879 is_floating_veb_supported(struct rte_devargs *devargs)
 880 {
 881         struct rte_kvargs *kvlist;
 882         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 883
 884         if (devargs == NULL)
 885                 return 0;
 886
 887         kvlist = rte_kvargs_parse(devargs->args, NULL);
 888         if (kvlist == NULL)
 889                 return 0;
 890
 891         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 892                 rte_kvargs_free(kvlist);
 893                 return 0;
 894         }
 895         /* Floating VEB is enabled when there's key-value:
 896          * enable_floating_veb=1
 897          */
 898         if (rte_kvargs_process(kvlist, floating_veb_key,
 899                                i40e_check_floating_handler, NULL) < 0) {
 900                 rte_kvargs_free(kvlist);
 901                 return 0;
 902         }
 903         rte_kvargs_free(kvlist);
 904
 905         return 1;
 906 }
 907
 908 static void
 909 config_floating_veb(struct rte_eth_dev *dev)
 910 {
 911         struct rte_pci_device *pci_dev = dev->pci_dev;
 912         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 913         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 914
 915         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 916
 917         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 918                 pf->floating_veb =
 919                         is_floating_veb_supported(pci_dev->device.devargs);
 920                 config_vf_floating_veb(pci_dev->device.devargs,
 921                                        pf->floating_veb,
 922                                        pf->floating_veb_list);
 923         } else {
 924                 pf->floating_veb = false;
 925         }
 926 }
 927
 928 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 929 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 930
 931 static int
 932 eth_i40e_dev_init(struct rte_eth_dev *dev)
 933 {
 934         struct rte_pci_device *pci_dev;
 935         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 936         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 937         struct i40e_vsi *vsi;
 938         int ret;
 939         uint32_t len;
 940         uint8_t aq_fail = 0;
 941
 942         PMD_INIT_FUNC_TRACE();
 943
 944         dev->dev_ops = &i40e_eth_dev_ops;
 945         dev->rx_pkt_burst = i40e_recv_pkts;
 946         dev->tx_pkt_burst = i40e_xmit_pkts;
 947
 948         /* for secondary processes, we don't initialise any further as primary
 949          * has already done this work. Only check we don't need a different
 950          * RX function */
 951         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 952                 i40e_set_rx_function(dev);
 953                 i40e_set_tx_function(dev);
 954                 return 0;
 955         }
 956         pci_dev = dev->pci_dev;
 957
 958         rte_eth_copy_pci_info(dev, pci_dev);
 959
 960         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 961         pf->adapter->eth_dev = dev;
 962         pf->dev_data = dev->data;
 963
 964         hw->back = I40E_PF_TO_ADAPTER(pf);
 965         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 966         if (!hw->hw_addr) {
 967                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 968                              "as address is NULL");
 969                 return -ENODEV;
 970         }
 971
 972         hw->vendor_id = pci_dev->id.vendor_id;
 973         hw->device_id = pci_dev->id.device_id;
 974         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 975         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 976         hw->bus.device = pci_dev->addr.devid;
 977         hw->bus.func = pci_dev->addr.function;
 978         hw->adapter_stopped = 0;
 979
 980         /* Make sure all is clean before doing PF reset */
 981         i40e_clear_hw(hw);
 982
 983         /* Initialize the hardware */
 984         i40e_hw_init(dev);
 985
 986         /* Reset here to make sure all is clean for each PF */
 987         ret = i40e_pf_reset(hw);
 988         if (ret) {
 989                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 990                 return ret;
 991         }
 992
 993         /* Initialize the shared code (base driver) */
 994         ret = i40e_init_shared_code(hw);
 995         if (ret) {
 996                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 997                 return ret;
 998         }
 999
1000         /*
1001          * To work around the NVM issue, initialize registers
1002          * for flexible payload and packet type of QinQ by
1003          * software. It should be removed once issues are fixed
1004          * in NVM.
1005          */
1006         i40e_GLQF_reg_init(hw);
1007
1008         /* Initialize the input set for filters (hash and fd) to default value */
1009         i40e_filter_input_set_init(pf);
1010
1011         /* Initialize the parameters for adminq */
1012         i40e_init_adminq_parameter(hw);
1013         ret = i40e_init_adminq(hw);
1014         if (ret != I40E_SUCCESS) {
1015                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1016                 return -EIO;
1017         }
1018         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1019                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1020                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1021                      ((hw->nvm.version >> 12) & 0xf),
1022                      ((hw->nvm.version >> 4) & 0xff),
1023                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1024
1025         /* Need the special FW version to support floating VEB */
1026         config_floating_veb(dev);
1027         /* Clear PXE mode */
1028         i40e_clear_pxe_mode(hw);
1029         ret = i40e_dev_sync_phy_type(hw);
1030         if (ret) {
1031                 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1032                 goto err_sync_phy_type;
1033         }
1034         /*
1035          * On X710, performance number is far from the expectation on recent
1036          * firmware versions. The fix for this issue may not be integrated in
1037          * the following firmware version. So the workaround in software driver
1038          * is needed. It needs to modify the initial values of 3 internal only
1039          * registers. Note that the workaround can be removed when it is fixed
1040          * in firmware in the future.
1041          */
1042         i40e_configure_registers(hw);
1043
1044         /* Get hw capabilities */
1045         ret = i40e_get_cap(hw);
1046         if (ret != I40E_SUCCESS) {
1047                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1048                 goto err_get_capabilities;
1049         }
1050
1051         /* Initialize parameters for PF */
1052         ret = i40e_pf_parameter_init(dev);
1053         if (ret != 0) {
1054                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1055                 goto err_parameter_init;
1056         }
1057
1058         /* Initialize the queue management */
1059         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1060         if (ret < 0) {
1061                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1062                 goto err_qp_pool_init;
1063         }
1064         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1065                                 hw->func_caps.num_msix_vectors - 1);
1066         if (ret < 0) {
1067                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1068                 goto err_msix_pool_init;
1069         }
1070
1071         /* Initialize lan hmc */
1072         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1073                                 hw->func_caps.num_rx_qp, 0, 0);
1074         if (ret != I40E_SUCCESS) {
1075                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1076                 goto err_init_lan_hmc;
1077         }
1078
1079         /* Configure lan hmc */
1080         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1081         if (ret != I40E_SUCCESS) {
1082                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1083                 goto err_configure_lan_hmc;
1084         }
1085
1086         /* Get and check the mac address */
1087         i40e_get_mac_addr(hw, hw->mac.addr);
1088         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1089                 PMD_INIT_LOG(ERR, "mac address is not valid");
1090                 ret = -EIO;
1091                 goto err_get_mac_addr;
1092         }
1093         /* Copy the permanent MAC address */
1094         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1095                         (struct ether_addr *) hw->mac.perm_addr);
1096
1097         /* Disable flow control */
1098         hw->fc.requested_mode = I40E_FC_NONE;
1099         i40e_set_fc(hw, &aq_fail, TRUE);
1100
1101         /* Set the global registers with default ether type value */
1102         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1103         if (ret != I40E_SUCCESS) {
1104                 PMD_INIT_LOG(ERR, "Failed to set the default outer "
1105                              "VLAN ether type");
1106                 goto err_setup_pf_switch;
1107         }
1108
1109         /* PF setup, which includes VSI setup */
1110         ret = i40e_pf_setup(pf);
1111         if (ret) {
1112                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1113                 goto err_setup_pf_switch;
1114         }
1115
1116         /* reset all stats of the device, including pf and main vsi */
1117         i40e_dev_stats_reset(dev);
1118
1119         vsi = pf->main_vsi;
1120
1121         /* Disable double vlan by default */
1122         i40e_vsi_config_double_vlan(vsi, FALSE);
1123
1124         /* Disable S-TAG identification when floating_veb is disabled */
1125         if (!pf->floating_veb) {
1126                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1127                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1128                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1129                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1130                 }
1131         }
1132
1133         if (!vsi->max_macaddrs)
1134                 len = ETHER_ADDR_LEN;
1135         else
1136                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1137
1138         /* Should be after VSI initialized */
1139         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1140         if (!dev->data->mac_addrs) {
1141                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
1142                                         "for storing mac address");
1143                 goto err_mac_alloc;
1144         }
1145         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1146                                         &dev->data->mac_addrs[0]);
1147
1148         /* initialize pf host driver to setup SRIOV resource if applicable */
1149         i40e_pf_host_init(dev);
1150
1151         /* register callback func to eal lib */
1152         rte_intr_callback_register(&(pci_dev->intr_handle),
1153                 i40e_dev_interrupt_handler, (void *)dev);
1154
1155         /* configure and enable device interrupt */
1156         i40e_pf_config_irq0(hw, TRUE);
1157         i40e_pf_enable_irq0(hw);
1158
1159         /* enable uio intr after callback register */
1160         rte_intr_enable(&(pci_dev->intr_handle));
1161         /*
1162          * Add an ethertype filter to drop all flow control frames transmitted
1163          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1164          * frames to wire.
1165          */
1166         i40e_add_tx_flow_control_drop_filter(pf);
1167
1168         /* Set the max frame size to 0x2600 by default,
1169          * in case other drivers changed the default value.
1170          */
1171         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1172
1173         /* initialize mirror rule list */
1174         TAILQ_INIT(&pf->mirror_list);
1175
1176         /* Init dcb to sw mode by default */
1177         ret = i40e_dcb_init_configure(dev, TRUE);
1178         if (ret != I40E_SUCCESS) {
1179                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1180                 pf->flags &= ~I40E_FLAG_DCB;
1181         }
1182
1183         return 0;
1184
1185 err_mac_alloc:
1186         i40e_vsi_release(pf->main_vsi);
1187 err_setup_pf_switch:
1188 err_get_mac_addr:
1189 err_configure_lan_hmc:
1190         (void)i40e_shutdown_lan_hmc(hw);
1191 err_init_lan_hmc:
1192         i40e_res_pool_destroy(&pf->msix_pool);
1193 err_msix_pool_init:
1194         i40e_res_pool_destroy(&pf->qp_pool);
1195 err_qp_pool_init:
1196 err_parameter_init:
1197 err_get_capabilities:
1198 err_sync_phy_type:
1199         (void)i40e_shutdown_adminq(hw);
1200
1201         return ret;
1202 }
1203
1204 static int
1205 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1206 {
1207         struct rte_pci_device *pci_dev;
1208         struct i40e_hw *hw;
1209         struct i40e_filter_control_settings settings;
1210         int ret;
1211         uint8_t aq_fail = 0;
1212
1213         PMD_INIT_FUNC_TRACE();
1214
1215         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1216                 return 0;
1217
1218         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1219         pci_dev = dev->pci_dev;
1220
1221         if (hw->adapter_stopped == 0)
1222                 i40e_dev_close(dev);
1223
1224         dev->dev_ops = NULL;
1225         dev->rx_pkt_burst = NULL;
1226         dev->tx_pkt_burst = NULL;
1227
1228         /* Clear PXE mode */
1229         i40e_clear_pxe_mode(hw);
1230
1231         /* Unconfigure filter control */
1232         memset(&settings, 0, sizeof(settings));
1233         ret = i40e_set_filter_control(hw, &settings);
1234         if (ret)
1235                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1236                                         ret);
1237
1238         /* Disable flow control */
1239         hw->fc.requested_mode = I40E_FC_NONE;
1240         i40e_set_fc(hw, &aq_fail, TRUE);
1241
1242         /* uninitialize pf host driver */
1243         i40e_pf_host_uninit(dev);
1244
1245         rte_free(dev->data->mac_addrs);
1246         dev->data->mac_addrs = NULL;
1247
1248         /* disable uio intr before callback unregister */
1249         rte_intr_disable(&(pci_dev->intr_handle));
1250
1251         /* register callback func to eal lib */
1252         rte_intr_callback_unregister(&(pci_dev->intr_handle),
1253                 i40e_dev_interrupt_handler, (void *)dev);
1254
1255         return 0;
1256 }
1257
1258 static int
1259 i40e_dev_configure(struct rte_eth_dev *dev)
1260 {
1261         struct i40e_adapter *ad =
1262                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1263         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1264         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1265         int i, ret;
1266
1267         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1268          * bulk allocation or vector Rx preconditions we will reset it.
1269          */
1270         ad->rx_bulk_alloc_allowed = true;
1271         ad->rx_vec_allowed = true;
1272         ad->tx_simple_allowed = true;
1273         ad->tx_vec_allowed = true;
1274
1275         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1276                 ret = i40e_fdir_setup(pf);
1277                 if (ret != I40E_SUCCESS) {
1278                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1279                         return -ENOTSUP;
1280                 }
1281                 ret = i40e_fdir_configure(dev);
1282                 if (ret < 0) {
1283                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1284                         goto err;
1285                 }
1286         } else
1287                 i40e_fdir_teardown(pf);
1288
1289         ret = i40e_dev_init_vlan(dev);
1290         if (ret < 0)
1291                 goto err;
1292
1293         /* VMDQ setup.
1294          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1295          *  RSS setting have different requirements.
1296          *  General PMD driver call sequence are NIC init, configure,
1297          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1298          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1299          *  applicable. So, VMDQ setting has to be done before
1300          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1301          *  For RSS setting, it will try to calculate actual configured RX queue
1302          *  number, which will be available after rx_queue_setup(). dev_start()
1303          *  function is good to place RSS setup.
1304          */
1305         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1306                 ret = i40e_vmdq_setup(dev);
1307                 if (ret)
1308                         goto err;
1309         }
1310
1311         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1312                 ret = i40e_dcb_setup(dev);
1313                 if (ret) {
1314                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1315                         goto err_dcb;
1316                 }
1317         }
1318
1319         return 0;
1320
1321 err_dcb:
1322         /* need to release vmdq resource if exists */
1323         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1324                 i40e_vsi_release(pf->vmdq[i].vsi);
1325                 pf->vmdq[i].vsi = NULL;
1326         }
1327         rte_free(pf->vmdq);
1328         pf->vmdq = NULL;
1329 err:
1330         /* need to release fdir resource if exists */
1331         i40e_fdir_teardown(pf);
1332         return ret;
1333 }
1334
1335 void
1336 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1337 {
1338         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1339         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1340         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1341         uint16_t msix_vect = vsi->msix_intr;
1342         uint16_t i;
1343
1344         for (i = 0; i < vsi->nb_qps; i++) {
1345                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1346                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1347                 rte_wmb();
1348         }
1349
1350         if (vsi->type != I40E_VSI_SRIOV) {
1351                 if (!rte_intr_allow_others(intr_handle)) {
1352                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1353                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1354                         I40E_WRITE_REG(hw,
1355                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1356                                        0);
1357                 } else {
1358                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1359                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1360                         I40E_WRITE_REG(hw,
1361                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1362                                                        msix_vect - 1), 0);
1363                 }
1364         } else {
1365                 uint32_t reg;
1366                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1367                         vsi->user_param + (msix_vect - 1);
1368
1369                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1370                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1371         }
1372         I40E_WRITE_FLUSH(hw);
1373 }
1374
1375 static void
1376 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1377                        int base_queue, int nb_queue)
1378 {
1379         int i;
1380         uint32_t val;
1381         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1382
1383         /* Bind all RX queues to allocated MSIX interrupt */
1384         for (i = 0; i < nb_queue; i++) {
1385                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1386                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1387                         ((base_queue + i + 1) <<
1388                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1389                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1390                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1391
1392                 if (i == nb_queue - 1)
1393                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1394                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1395         }
1396
1397         /* Write first RX queue to Link list register as the head element */
1398         if (vsi->type != I40E_VSI_SRIOV) {
1399                 uint16_t interval =
1400                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1401
1402                 if (msix_vect == I40E_MISC_VEC_ID) {
1403                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1404                                        (base_queue <<
1405                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1406                                        (0x0 <<
1407                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1408                         I40E_WRITE_REG(hw,
1409                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1410                                        interval);
1411                 } else {
1412                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1413                                        (base_queue <<
1414                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1415                                        (0x0 <<
1416                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1417                         I40E_WRITE_REG(hw,
1418                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1419                                                        msix_vect - 1),
1420                                        interval);
1421                 }
1422         } else {
1423                 uint32_t reg;
1424
1425                 if (msix_vect == I40E_MISC_VEC_ID) {
1426                         I40E_WRITE_REG(hw,
1427                                        I40E_VPINT_LNKLST0(vsi->user_param),
1428                                        (base_queue <<
1429                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1430                                        (0x0 <<
1431                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1432                 } else {
1433                         /* num_msix_vectors_vf needs to minus irq0 */
1434                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1435                                 vsi->user_param + (msix_vect - 1);
1436
1437                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1438                                        (base_queue <<
1439                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1440                                        (0x0 <<
1441                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1442                 }
1443         }
1444
1445         I40E_WRITE_FLUSH(hw);
1446 }
1447
1448 void
1449 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1450 {
1451         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1452         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1453         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1454         uint16_t msix_vect = vsi->msix_intr;
1455         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1456         uint16_t queue_idx = 0;
1457         int record = 0;
1458         uint32_t val;
1459         int i;
1460
1461         for (i = 0; i < vsi->nb_qps; i++) {
1462                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1463                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1464         }
1465
1466         /* INTENA flag is not auto-cleared for interrupt */
1467         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1468         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1469                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1470                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1471         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1472
1473         /* VF bind interrupt */
1474         if (vsi->type == I40E_VSI_SRIOV) {
1475                 __vsi_queues_bind_intr(vsi, msix_vect,
1476                                        vsi->base_queue, vsi->nb_qps);
1477                 return;
1478         }
1479
1480         /* PF & VMDq bind interrupt */
1481         if (rte_intr_dp_is_en(intr_handle)) {
1482                 if (vsi->type == I40E_VSI_MAIN) {
1483                         queue_idx = 0;
1484                         record = 1;
1485                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1486                         struct i40e_vsi *main_vsi =
1487                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1488                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1489                         record = 1;
1490                 }
1491         }
1492
1493         for (i = 0; i < vsi->nb_used_qps; i++) {
1494                 if (nb_msix <= 1) {
1495                         if (!rte_intr_allow_others(intr_handle))
1496                                 /* allow to share MISC_VEC_ID */
1497                                 msix_vect = I40E_MISC_VEC_ID;
1498
1499                         /* no enough msix_vect, map all to one */
1500                         __vsi_queues_bind_intr(vsi, msix_vect,
1501                                                vsi->base_queue + i,
1502                                                vsi->nb_used_qps - i);
1503                         for (; !!record && i < vsi->nb_used_qps; i++)
1504                                 intr_handle->intr_vec[queue_idx + i] =
1505                                         msix_vect;
1506                         break;
1507                 }
1508                 /* 1:1 queue/msix_vect mapping */
1509                 __vsi_queues_bind_intr(vsi, msix_vect,
1510                                        vsi->base_queue + i, 1);
1511                 if (!!record)
1512                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1513
1514                 msix_vect++;
1515                 nb_msix--;
1516         }
1517 }
1518
1519 static void
1520 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1521 {
1522         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1523         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1524         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1525         uint16_t interval = i40e_calc_itr_interval(\
1526                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1527         uint16_t msix_intr, i;
1528
1529         if (rte_intr_allow_others(intr_handle))
1530                 for (i = 0; i < vsi->nb_msix; i++) {
1531                         msix_intr = vsi->msix_intr + i;
1532                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1533                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1534                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1535                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1536                                 (interval <<
1537                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1538                 }
1539         else
1540                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1541                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1542                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1543                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1544                                (interval <<
1545                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1546
1547         I40E_WRITE_FLUSH(hw);
1548 }
1549
1550 static void
1551 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1552 {
1553         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1554         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1555         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1556         uint16_t msix_intr, i;
1557
1558         if (rte_intr_allow_others(intr_handle))
1559                 for (i = 0; i < vsi->nb_msix; i++) {
1560                         msix_intr = vsi->msix_intr + i;
1561                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1562                                        0);
1563                 }
1564         else
1565                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1566
1567         I40E_WRITE_FLUSH(hw);
1568 }
1569
1570 static inline uint8_t
1571 i40e_parse_link_speeds(uint16_t link_speeds)
1572 {
1573         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1574
1575         if (link_speeds & ETH_LINK_SPEED_40G)
1576                 link_speed |= I40E_LINK_SPEED_40GB;
1577         if (link_speeds & ETH_LINK_SPEED_25G)
1578                 link_speed |= I40E_LINK_SPEED_25GB;
1579         if (link_speeds & ETH_LINK_SPEED_20G)
1580                 link_speed |= I40E_LINK_SPEED_20GB;
1581         if (link_speeds & ETH_LINK_SPEED_10G)
1582                 link_speed |= I40E_LINK_SPEED_10GB;
1583         if (link_speeds & ETH_LINK_SPEED_1G)
1584                 link_speed |= I40E_LINK_SPEED_1GB;
1585         if (link_speeds & ETH_LINK_SPEED_100M)
1586                 link_speed |= I40E_LINK_SPEED_100MB;
1587
1588         return link_speed;
1589 }
1590
1591 static int
1592 i40e_phy_conf_link(struct i40e_hw *hw,
1593                    uint8_t abilities,
1594                    uint8_t force_speed)
1595 {
1596         enum i40e_status_code status;
1597         struct i40e_aq_get_phy_abilities_resp phy_ab;
1598         struct i40e_aq_set_phy_config phy_conf;
1599         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1600                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1601                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1602                         I40E_AQ_PHY_FLAG_LOW_POWER;
1603         const uint8_t advt = I40E_LINK_SPEED_40GB |
1604                         I40E_LINK_SPEED_25GB |
1605                         I40E_LINK_SPEED_10GB |
1606                         I40E_LINK_SPEED_1GB |
1607                         I40E_LINK_SPEED_100MB;
1608         int ret = -ENOTSUP;
1609
1610
1611         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1612                                               NULL);
1613         if (status)
1614                 return ret;
1615
1616         memset(&phy_conf, 0, sizeof(phy_conf));
1617
1618         /* bits 0-2 use the values from get_phy_abilities_resp */
1619         abilities &= ~mask;
1620         abilities |= phy_ab.abilities & mask;
1621
1622         /* update ablities and speed */
1623         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1624                 phy_conf.link_speed = advt;
1625         else
1626                 phy_conf.link_speed = force_speed;
1627
1628         phy_conf.abilities = abilities;
1629
1630         /* use get_phy_abilities_resp value for the rest */
1631         phy_conf.phy_type = phy_ab.phy_type;
1632         phy_conf.eee_capability = phy_ab.eee_capability;
1633         phy_conf.eeer = phy_ab.eeer_val;
1634         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1635
1636         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1637                     phy_ab.abilities, phy_ab.link_speed);
1638         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1639                     phy_conf.abilities, phy_conf.link_speed);
1640
1641         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1642         if (status)
1643                 return ret;
1644
1645         return I40E_SUCCESS;
1646 }
1647
1648 static int
1649 i40e_apply_link_speed(struct rte_eth_dev *dev)
1650 {
1651         uint8_t speed;
1652         uint8_t abilities = 0;
1653         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1654         struct rte_eth_conf *conf = &dev->data->dev_conf;
1655
1656         speed = i40e_parse_link_speeds(conf->link_speeds);
1657         if (!I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
1658                 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1659         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1660                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1661         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1662
1663         /* Skip changing speed on 40G interfaces, FW does not support */
1664         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1665                 speed =  I40E_LINK_SPEED_UNKNOWN;
1666                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1667         }
1668
1669         return i40e_phy_conf_link(hw, abilities, speed);
1670 }
1671
1672 static int
1673 i40e_dev_start(struct rte_eth_dev *dev)
1674 {
1675         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1676         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1677         struct i40e_vsi *main_vsi = pf->main_vsi;
1678         int ret, i;
1679         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1680         uint32_t intr_vector = 0;
1681
1682         hw->adapter_stopped = 0;
1683
1684         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1685                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1686                              dev->data->port_id);
1687                 return -EINVAL;
1688         }
1689
1690         rte_intr_disable(intr_handle);
1691
1692         if ((rte_intr_cap_multiple(intr_handle) ||
1693              !RTE_ETH_DEV_SRIOV(dev).active) &&
1694             dev->data->dev_conf.intr_conf.rxq != 0) {
1695                 intr_vector = dev->data->nb_rx_queues;
1696                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1697                         return -1;
1698         }
1699
1700         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1701                 intr_handle->intr_vec =
1702                         rte_zmalloc("intr_vec",
1703                                     dev->data->nb_rx_queues * sizeof(int),
1704                                     0);
1705                 if (!intr_handle->intr_vec) {
1706                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1707                                      " intr_vec\n", dev->data->nb_rx_queues);
1708                         return -ENOMEM;
1709                 }
1710         }
1711
1712         /* Initialize VSI */
1713         ret = i40e_dev_rxtx_init(pf);
1714         if (ret != I40E_SUCCESS) {
1715                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1716                 goto err_up;
1717         }
1718
1719         /* Map queues with MSIX interrupt */
1720         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1721                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1722         i40e_vsi_queues_bind_intr(main_vsi);
1723         i40e_vsi_enable_queues_intr(main_vsi);
1724
1725         /* Map VMDQ VSI queues with MSIX interrupt */
1726         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1727                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1728                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1729                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1730         }
1731
1732         /* enable FDIR MSIX interrupt */
1733         if (pf->fdir.fdir_vsi) {
1734                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1735                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1736         }
1737
1738         /* Enable all queues which have been configured */
1739         ret = i40e_dev_switch_queues(pf, TRUE);
1740         if (ret != I40E_SUCCESS) {
1741                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1742                 goto err_up;
1743         }
1744
1745         /* Enable receiving broadcast packets */
1746         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1747         if (ret != I40E_SUCCESS)
1748                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1749
1750         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1751                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1752                                                 true, NULL);
1753                 if (ret != I40E_SUCCESS)
1754                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1755         }
1756
1757         /* Apply link configure */
1758         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
1759                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
1760                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
1761                                 ETH_LINK_SPEED_40G)) {
1762                 PMD_DRV_LOG(ERR, "Invalid link setting");
1763                 goto err_up;
1764         }
1765         ret = i40e_apply_link_speed(dev);
1766         if (I40E_SUCCESS != ret) {
1767                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1768                 goto err_up;
1769         }
1770
1771         if (!rte_intr_allow_others(intr_handle)) {
1772                 rte_intr_callback_unregister(intr_handle,
1773                                              i40e_dev_interrupt_handler,
1774                                              (void *)dev);
1775                 /* configure and enable device interrupt */
1776                 i40e_pf_config_irq0(hw, FALSE);
1777                 i40e_pf_enable_irq0(hw);
1778
1779                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1780                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1781                                      " no intr multiplex\n");
1782         }
1783
1784         /* enable uio intr after callback register */
1785         rte_intr_enable(intr_handle);
1786
1787         return I40E_SUCCESS;
1788
1789 err_up:
1790         i40e_dev_switch_queues(pf, FALSE);
1791         i40e_dev_clear_queues(dev);
1792
1793         return ret;
1794 }
1795
1796 static void
1797 i40e_dev_stop(struct rte_eth_dev *dev)
1798 {
1799         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1800         struct i40e_vsi *main_vsi = pf->main_vsi;
1801         struct i40e_mirror_rule *p_mirror;
1802         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
1803         int i;
1804
1805         /* Disable all queues */
1806         i40e_dev_switch_queues(pf, FALSE);
1807
1808         /* un-map queues with interrupt registers */
1809         i40e_vsi_disable_queues_intr(main_vsi);
1810         i40e_vsi_queues_unbind_intr(main_vsi);
1811
1812         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1813                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1814                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1815         }
1816
1817         if (pf->fdir.fdir_vsi) {
1818                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
1819                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
1820         }
1821         /* Clear all queues and release memory */
1822         i40e_dev_clear_queues(dev);
1823
1824         /* Set link down */
1825         i40e_dev_set_link_down(dev);
1826
1827         /* Remove all mirror rules */
1828         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1829                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1830                 rte_free(p_mirror);
1831         }
1832         pf->nb_mirror_rule = 0;
1833
1834         if (!rte_intr_allow_others(intr_handle))
1835                 /* resume to the default handler */
1836                 rte_intr_callback_register(intr_handle,
1837                                            i40e_dev_interrupt_handler,
1838                                            (void *)dev);
1839
1840         /* Clean datapath event and queue/vec mapping */
1841         rte_intr_efd_disable(intr_handle);
1842         if (intr_handle->intr_vec) {
1843                 rte_free(intr_handle->intr_vec);
1844                 intr_handle->intr_vec = NULL;
1845         }
1846 }
1847
1848 static void
1849 i40e_dev_close(struct rte_eth_dev *dev)
1850 {
1851         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1852         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1853         uint32_t reg;
1854         int i;
1855
1856         PMD_INIT_FUNC_TRACE();
1857
1858         i40e_dev_stop(dev);
1859         hw->adapter_stopped = 1;
1860         i40e_dev_free_queues(dev);
1861
1862         /* Disable interrupt */
1863         i40e_pf_disable_irq0(hw);
1864         rte_intr_disable(&(dev->pci_dev->intr_handle));
1865
1866         /* shutdown and destroy the HMC */
1867         i40e_shutdown_lan_hmc(hw);
1868
1869         /* release all the existing VSIs and VEBs */
1870         i40e_fdir_teardown(pf);
1871         i40e_vsi_release(pf->main_vsi);
1872
1873         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1874                 i40e_vsi_release(pf->vmdq[i].vsi);
1875                 pf->vmdq[i].vsi = NULL;
1876         }
1877
1878         rte_free(pf->vmdq);
1879         pf->vmdq = NULL;
1880
1881         /* shutdown the adminq */
1882         i40e_aq_queue_shutdown(hw, true);
1883         i40e_shutdown_adminq(hw);
1884
1885         i40e_res_pool_destroy(&pf->qp_pool);
1886         i40e_res_pool_destroy(&pf->msix_pool);
1887
1888         /* force a PF reset to clean anything leftover */
1889         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1890         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1891                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1892         I40E_WRITE_FLUSH(hw);
1893 }
1894
1895 static void
1896 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1897 {
1898         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1899         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1900         struct i40e_vsi *vsi = pf->main_vsi;
1901         int status;
1902
1903         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1904                                                      true, NULL, true);
1905         if (status != I40E_SUCCESS)
1906                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1907
1908         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1909                                                         TRUE, NULL);
1910         if (status != I40E_SUCCESS)
1911                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1912
1913 }
1914
1915 static void
1916 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1917 {
1918         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1919         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1920         struct i40e_vsi *vsi = pf->main_vsi;
1921         int status;
1922
1923         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1924                                                      false, NULL, true);
1925         if (status != I40E_SUCCESS)
1926                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1927
1928         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1929                                                         false, NULL);
1930         if (status != I40E_SUCCESS)
1931                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1932 }
1933
1934 static void
1935 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1936 {
1937         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1938         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1939         struct i40e_vsi *vsi = pf->main_vsi;
1940         int ret;
1941
1942         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1943         if (ret != I40E_SUCCESS)
1944                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1945 }
1946
1947 static void
1948 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1949 {
1950         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1951         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1952         struct i40e_vsi *vsi = pf->main_vsi;
1953         int ret;
1954
1955         if (dev->data->promiscuous == 1)
1956                 return; /* must remain in all_multicast mode */
1957
1958         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1959                                 vsi->seid, FALSE, NULL);
1960         if (ret != I40E_SUCCESS)
1961                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1962 }
1963
1964 /*
1965  * Set device link up.
1966  */
1967 static int
1968 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1969 {
1970         /* re-apply link speed setting */
1971         return i40e_apply_link_speed(dev);
1972 }
1973
1974 /*
1975  * Set device link down.
1976  */
1977 static int
1978 i40e_dev_set_link_down(struct rte_eth_dev *dev)
1979 {
1980         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1981         uint8_t abilities = 0;
1982         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1983
1984         if (!I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
1985                 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1986         return i40e_phy_conf_link(hw, abilities, speed);
1987 }
1988
1989 int
1990 i40e_dev_link_update(struct rte_eth_dev *dev,
1991                      int wait_to_complete)
1992 {
1993 #define CHECK_INTERVAL 100  /* 100ms */
1994 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
1995         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1996         struct i40e_link_status link_status;
1997         struct rte_eth_link link, old;
1998         int status;
1999         unsigned rep_cnt = MAX_REPEAT_TIME;
2000
2001         memset(&link, 0, sizeof(link));
2002         memset(&old, 0, sizeof(old));
2003         memset(&link_status, 0, sizeof(link_status));
2004         rte_i40e_dev_atomic_read_link_status(dev, &old);
2005
2006         do {
2007                 /* Get link status information from hardware */
2008                 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
2009                 if (status != I40E_SUCCESS) {
2010                         link.link_speed = ETH_SPEED_NUM_100M;
2011                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2012                         PMD_DRV_LOG(ERR, "Failed to get link info");
2013                         goto out;
2014                 }
2015
2016                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2017                 if (!wait_to_complete)
2018                         break;
2019
2020                 rte_delay_ms(CHECK_INTERVAL);
2021         } while (!link.link_status && rep_cnt--);
2022
2023         if (!link.link_status)
2024                 goto out;
2025
2026         /* i40e uses full duplex only */
2027         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2028
2029         /* Parse the link status */
2030         switch (link_status.link_speed) {
2031         case I40E_LINK_SPEED_100MB:
2032                 link.link_speed = ETH_SPEED_NUM_100M;
2033                 break;
2034         case I40E_LINK_SPEED_1GB:
2035                 link.link_speed = ETH_SPEED_NUM_1G;
2036                 break;
2037         case I40E_LINK_SPEED_10GB:
2038                 link.link_speed = ETH_SPEED_NUM_10G;
2039                 break;
2040         case I40E_LINK_SPEED_20GB:
2041                 link.link_speed = ETH_SPEED_NUM_20G;
2042                 break;
2043         case I40E_LINK_SPEED_25GB:
2044                 link.link_speed = ETH_SPEED_NUM_25G;
2045                 break;
2046         case I40E_LINK_SPEED_40GB:
2047                 link.link_speed = ETH_SPEED_NUM_40G;
2048                 break;
2049         default:
2050                 link.link_speed = ETH_SPEED_NUM_100M;
2051                 break;
2052         }
2053
2054         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2055                         ETH_LINK_SPEED_FIXED);
2056
2057 out:
2058         rte_i40e_dev_atomic_write_link_status(dev, &link);
2059         if (link.link_status == old.link_status)
2060                 return -1;
2061
2062         return 0;
2063 }
2064
2065 /* Get all the statistics of a VSI */
2066 void
2067 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2068 {
2069         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2070         struct i40e_eth_stats *nes = &vsi->eth_stats;
2071         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2072         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2073
2074         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2075                             vsi->offset_loaded, &oes->rx_bytes,
2076                             &nes->rx_bytes);
2077         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2078                             vsi->offset_loaded, &oes->rx_unicast,
2079                             &nes->rx_unicast);
2080         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2081                             vsi->offset_loaded, &oes->rx_multicast,
2082                             &nes->rx_multicast);
2083         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2084                             vsi->offset_loaded, &oes->rx_broadcast,
2085                             &nes->rx_broadcast);
2086         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2087                             &oes->rx_discards, &nes->rx_discards);
2088         /* GLV_REPC not supported */
2089         /* GLV_RMPC not supported */
2090         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2091                             &oes->rx_unknown_protocol,
2092                             &nes->rx_unknown_protocol);
2093         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2094                             vsi->offset_loaded, &oes->tx_bytes,
2095                             &nes->tx_bytes);
2096         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2097                             vsi->offset_loaded, &oes->tx_unicast,
2098                             &nes->tx_unicast);
2099         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2100                             vsi->offset_loaded, &oes->tx_multicast,
2101                             &nes->tx_multicast);
2102         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2103                             vsi->offset_loaded,  &oes->tx_broadcast,
2104                             &nes->tx_broadcast);
2105         /* GLV_TDPC not supported */
2106         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2107                             &oes->tx_errors, &nes->tx_errors);
2108         vsi->offset_loaded = true;
2109
2110         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2111                     vsi->vsi_id);
2112         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2113         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2114         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2115         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2116         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2117         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2118                     nes->rx_unknown_protocol);
2119         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2120         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2121         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2122         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2123         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2124         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2125         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2126                     vsi->vsi_id);
2127 }
2128
2129 static void
2130 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2131 {
2132         unsigned int i;
2133         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2134         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2135
2136         /* Get statistics of struct i40e_eth_stats */
2137         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2138                             I40E_GLPRT_GORCL(hw->port),
2139                             pf->offset_loaded, &os->eth.rx_bytes,
2140                             &ns->eth.rx_bytes);
2141         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2142                             I40E_GLPRT_UPRCL(hw->port),
2143                             pf->offset_loaded, &os->eth.rx_unicast,
2144                             &ns->eth.rx_unicast);
2145         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2146                             I40E_GLPRT_MPRCL(hw->port),
2147                             pf->offset_loaded, &os->eth.rx_multicast,
2148                             &ns->eth.rx_multicast);
2149         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2150                             I40E_GLPRT_BPRCL(hw->port),
2151                             pf->offset_loaded, &os->eth.rx_broadcast,
2152                             &ns->eth.rx_broadcast);
2153         /* Workaround: CRC size should not be included in byte statistics,
2154          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2155          */
2156         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2157                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2158
2159         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2160                             pf->offset_loaded, &os->eth.rx_discards,
2161                             &ns->eth.rx_discards);
2162         /* GLPRT_REPC not supported */
2163         /* GLPRT_RMPC not supported */
2164         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2165                             pf->offset_loaded,
2166                             &os->eth.rx_unknown_protocol,
2167                             &ns->eth.rx_unknown_protocol);
2168         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2169                             I40E_GLPRT_GOTCL(hw->port),
2170                             pf->offset_loaded, &os->eth.tx_bytes,
2171                             &ns->eth.tx_bytes);
2172         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2173                             I40E_GLPRT_UPTCL(hw->port),
2174                             pf->offset_loaded, &os->eth.tx_unicast,
2175                             &ns->eth.tx_unicast);
2176         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2177                             I40E_GLPRT_MPTCL(hw->port),
2178                             pf->offset_loaded, &os->eth.tx_multicast,
2179                             &ns->eth.tx_multicast);
2180         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2181                             I40E_GLPRT_BPTCL(hw->port),
2182                             pf->offset_loaded, &os->eth.tx_broadcast,
2183                             &ns->eth.tx_broadcast);
2184         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2185                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2186         /* GLPRT_TEPC not supported */
2187
2188         /* additional port specific stats */
2189         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2190                             pf->offset_loaded, &os->tx_dropped_link_down,
2191                             &ns->tx_dropped_link_down);
2192         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2193                             pf->offset_loaded, &os->crc_errors,
2194                             &ns->crc_errors);
2195         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2196                             pf->offset_loaded, &os->illegal_bytes,
2197                             &ns->illegal_bytes);
2198         /* GLPRT_ERRBC not supported */
2199         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2200                             pf->offset_loaded, &os->mac_local_faults,
2201                             &ns->mac_local_faults);
2202         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2203                             pf->offset_loaded, &os->mac_remote_faults,
2204                             &ns->mac_remote_faults);
2205         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2206                             pf->offset_loaded, &os->rx_length_errors,
2207                             &ns->rx_length_errors);
2208         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2209                             pf->offset_loaded, &os->link_xon_rx,
2210                             &ns->link_xon_rx);
2211         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2212                             pf->offset_loaded, &os->link_xoff_rx,
2213                             &ns->link_xoff_rx);
2214         for (i = 0; i < 8; i++) {
2215                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2216                                     pf->offset_loaded,
2217                                     &os->priority_xon_rx[i],
2218                                     &ns->priority_xon_rx[i]);
2219                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2220                                     pf->offset_loaded,
2221                                     &os->priority_xoff_rx[i],
2222                                     &ns->priority_xoff_rx[i]);
2223         }
2224         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2225                             pf->offset_loaded, &os->link_xon_tx,
2226                             &ns->link_xon_tx);
2227         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2228                             pf->offset_loaded, &os->link_xoff_tx,
2229                             &ns->link_xoff_tx);
2230         for (i = 0; i < 8; i++) {
2231                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2232                                     pf->offset_loaded,
2233                                     &os->priority_xon_tx[i],
2234                                     &ns->priority_xon_tx[i]);
2235                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2236                                     pf->offset_loaded,
2237                                     &os->priority_xoff_tx[i],
2238                                     &ns->priority_xoff_tx[i]);
2239                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2240                                     pf->offset_loaded,
2241                                     &os->priority_xon_2_xoff[i],
2242                                     &ns->priority_xon_2_xoff[i]);
2243         }
2244         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2245                             I40E_GLPRT_PRC64L(hw->port),
2246                             pf->offset_loaded, &os->rx_size_64,
2247                             &ns->rx_size_64);
2248         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2249                             I40E_GLPRT_PRC127L(hw->port),
2250                             pf->offset_loaded, &os->rx_size_127,
2251                             &ns->rx_size_127);
2252         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2253                             I40E_GLPRT_PRC255L(hw->port),
2254                             pf->offset_loaded, &os->rx_size_255,
2255                             &ns->rx_size_255);
2256         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2257                             I40E_GLPRT_PRC511L(hw->port),
2258                             pf->offset_loaded, &os->rx_size_511,
2259                             &ns->rx_size_511);
2260         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2261                             I40E_GLPRT_PRC1023L(hw->port),
2262                             pf->offset_loaded, &os->rx_size_1023,
2263                             &ns->rx_size_1023);
2264         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2265                             I40E_GLPRT_PRC1522L(hw->port),
2266                             pf->offset_loaded, &os->rx_size_1522,
2267                             &ns->rx_size_1522);
2268         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2269                             I40E_GLPRT_PRC9522L(hw->port),
2270                             pf->offset_loaded, &os->rx_size_big,
2271                             &ns->rx_size_big);
2272         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2273                             pf->offset_loaded, &os->rx_undersize,
2274                             &ns->rx_undersize);
2275         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2276                             pf->offset_loaded, &os->rx_fragments,
2277                             &ns->rx_fragments);
2278         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2279                             pf->offset_loaded, &os->rx_oversize,
2280                             &ns->rx_oversize);
2281         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2282                             pf->offset_loaded, &os->rx_jabber,
2283                             &ns->rx_jabber);
2284         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2285                             I40E_GLPRT_PTC64L(hw->port),
2286                             pf->offset_loaded, &os->tx_size_64,
2287                             &ns->tx_size_64);
2288         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2289                             I40E_GLPRT_PTC127L(hw->port),
2290                             pf->offset_loaded, &os->tx_size_127,
2291                             &ns->tx_size_127);
2292         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2293                             I40E_GLPRT_PTC255L(hw->port),
2294                             pf->offset_loaded, &os->tx_size_255,
2295                             &ns->tx_size_255);
2296         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2297                             I40E_GLPRT_PTC511L(hw->port),
2298                             pf->offset_loaded, &os->tx_size_511,
2299                             &ns->tx_size_511);
2300         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2301                             I40E_GLPRT_PTC1023L(hw->port),
2302                             pf->offset_loaded, &os->tx_size_1023,
2303                             &ns->tx_size_1023);
2304         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2305                             I40E_GLPRT_PTC1522L(hw->port),
2306                             pf->offset_loaded, &os->tx_size_1522,
2307                             &ns->tx_size_1522);
2308         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2309                             I40E_GLPRT_PTC9522L(hw->port),
2310                             pf->offset_loaded, &os->tx_size_big,
2311                             &ns->tx_size_big);
2312         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2313                            pf->offset_loaded,
2314                            &os->fd_sb_match, &ns->fd_sb_match);
2315         /* GLPRT_MSPDC not supported */
2316         /* GLPRT_XEC not supported */
2317
2318         pf->offset_loaded = true;
2319
2320         if (pf->main_vsi)
2321                 i40e_update_vsi_stats(pf->main_vsi);
2322 }
2323
2324 /* Get all statistics of a port */
2325 static void
2326 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2327 {
2328         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2329         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2330         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2331         unsigned i;
2332
2333         /* call read registers - updates values, now write them to struct */
2334         i40e_read_stats_registers(pf, hw);
2335
2336         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2337                         pf->main_vsi->eth_stats.rx_multicast +
2338                         pf->main_vsi->eth_stats.rx_broadcast -
2339                         pf->main_vsi->eth_stats.rx_discards;
2340         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2341                         pf->main_vsi->eth_stats.tx_multicast +
2342                         pf->main_vsi->eth_stats.tx_broadcast;
2343         stats->ibytes   = ns->eth.rx_bytes;
2344         stats->obytes   = ns->eth.tx_bytes;
2345         stats->oerrors  = ns->eth.tx_errors +
2346                         pf->main_vsi->eth_stats.tx_errors;
2347
2348         /* Rx Errors */
2349         stats->imissed  = ns->eth.rx_discards +
2350                         pf->main_vsi->eth_stats.rx_discards;
2351         stats->ierrors  = ns->crc_errors +
2352                         ns->rx_length_errors + ns->rx_undersize +
2353                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2354
2355         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2356         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2357         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2358         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2359         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2360         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2361         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2362                     ns->eth.rx_unknown_protocol);
2363         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2364         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2365         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2366         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2367         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2368         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2369
2370         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2371                     ns->tx_dropped_link_down);
2372         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2373         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2374                     ns->illegal_bytes);
2375         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2376         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2377                     ns->mac_local_faults);
2378         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2379                     ns->mac_remote_faults);
2380         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2381                     ns->rx_length_errors);
2382         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2383         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2384         for (i = 0; i < 8; i++) {
2385                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2386                                 i, ns->priority_xon_rx[i]);
2387                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2388                                 i, ns->priority_xoff_rx[i]);
2389         }
2390         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2391         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2392         for (i = 0; i < 8; i++) {
2393                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2394                                 i, ns->priority_xon_tx[i]);
2395                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2396                                 i, ns->priority_xoff_tx[i]);
2397                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2398                                 i, ns->priority_xon_2_xoff[i]);
2399         }
2400         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2401         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2402         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2403         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2404         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2405         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2406         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2407         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2408         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2409         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2410         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2411         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2412         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2413         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2414         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2415         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2416         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2417         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2418         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2419                         ns->mac_short_packet_dropped);
2420         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2421                     ns->checksum_error);
2422         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2423         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2424 }
2425
2426 /* Reset the statistics */
2427 static void
2428 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2429 {
2430         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2431         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2432
2433         /* Mark PF and VSI stats to update the offset, aka "reset" */
2434         pf->offset_loaded = false;
2435         if (pf->main_vsi)
2436                 pf->main_vsi->offset_loaded = false;
2437
2438         /* read the stats, reading current register values into offset */
2439         i40e_read_stats_registers(pf, hw);
2440 }
2441
2442 static uint32_t
2443 i40e_xstats_calc_num(void)
2444 {
2445         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2446                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2447                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2448 }
2449
2450 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2451                                      struct rte_eth_xstat_name *xstats_names,
2452                                      __rte_unused unsigned limit)
2453 {
2454         unsigned count = 0;
2455         unsigned i, prio;
2456
2457         if (xstats_names == NULL)
2458                 return i40e_xstats_calc_num();
2459
2460         /* Note: limit checked in rte_eth_xstats_names() */
2461
2462         /* Get stats from i40e_eth_stats struct */
2463         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2464                 snprintf(xstats_names[count].name,
2465                          sizeof(xstats_names[count].name),
2466                          "%s", rte_i40e_stats_strings[i].name);
2467                 count++;
2468         }
2469
2470         /* Get individiual stats from i40e_hw_port struct */
2471         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2472                 snprintf(xstats_names[count].name,
2473                         sizeof(xstats_names[count].name),
2474                          "%s", rte_i40e_hw_port_strings[i].name);
2475                 count++;
2476         }
2477
2478         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2479                 for (prio = 0; prio < 8; prio++) {
2480                         snprintf(xstats_names[count].name,
2481                                  sizeof(xstats_names[count].name),
2482                                  "rx_priority%u_%s", prio,
2483                                  rte_i40e_rxq_prio_strings[i].name);
2484                         count++;
2485                 }
2486         }
2487
2488         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2489                 for (prio = 0; prio < 8; prio++) {
2490                         snprintf(xstats_names[count].name,
2491                                  sizeof(xstats_names[count].name),
2492                                  "tx_priority%u_%s", prio,
2493                                  rte_i40e_txq_prio_strings[i].name);
2494                         count++;
2495                 }
2496         }
2497         return count;
2498 }
2499
2500 static int
2501 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2502                     unsigned n)
2503 {
2504         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2505         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2506         unsigned i, count, prio;
2507         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2508
2509         count = i40e_xstats_calc_num();
2510         if (n < count)
2511                 return count;
2512
2513         i40e_read_stats_registers(pf, hw);
2514
2515         if (xstats == NULL)
2516                 return 0;
2517
2518         count = 0;
2519
2520         /* Get stats from i40e_eth_stats struct */
2521         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2522                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2523                         rte_i40e_stats_strings[i].offset);
2524                 count++;
2525         }
2526
2527         /* Get individiual stats from i40e_hw_port struct */
2528         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2529                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2530                         rte_i40e_hw_port_strings[i].offset);
2531                 count++;
2532         }
2533
2534         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2535                 for (prio = 0; prio < 8; prio++) {
2536                         xstats[count].value =
2537                                 *(uint64_t *)(((char *)hw_stats) +
2538                                 rte_i40e_rxq_prio_strings[i].offset +
2539                                 (sizeof(uint64_t) * prio));
2540                         count++;
2541                 }
2542         }
2543
2544         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2545                 for (prio = 0; prio < 8; prio++) {
2546                         xstats[count].value =
2547                                 *(uint64_t *)(((char *)hw_stats) +
2548                                 rte_i40e_txq_prio_strings[i].offset +
2549                                 (sizeof(uint64_t) * prio));
2550                         count++;
2551                 }
2552         }
2553
2554         return count;
2555 }
2556
2557 static int
2558 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2559                                  __rte_unused uint16_t queue_id,
2560                                  __rte_unused uint8_t stat_idx,
2561                                  __rte_unused uint8_t is_rx)
2562 {
2563         PMD_INIT_FUNC_TRACE();
2564
2565         return -ENOSYS;
2566 }
2567
2568 static void
2569 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2570 {
2571         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2572         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2573         struct i40e_vsi *vsi = pf->main_vsi;
2574
2575         dev_info->max_rx_queues = vsi->nb_qps;
2576         dev_info->max_tx_queues = vsi->nb_qps;
2577         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2578         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2579         dev_info->max_mac_addrs = vsi->max_macaddrs;
2580         dev_info->max_vfs = dev->pci_dev->max_vfs;
2581         dev_info->rx_offload_capa =
2582                 DEV_RX_OFFLOAD_VLAN_STRIP |
2583                 DEV_RX_OFFLOAD_QINQ_STRIP |
2584                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2585                 DEV_RX_OFFLOAD_UDP_CKSUM |
2586                 DEV_RX_OFFLOAD_TCP_CKSUM;
2587         dev_info->tx_offload_capa =
2588                 DEV_TX_OFFLOAD_VLAN_INSERT |
2589                 DEV_TX_OFFLOAD_QINQ_INSERT |
2590                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2591                 DEV_TX_OFFLOAD_UDP_CKSUM |
2592                 DEV_TX_OFFLOAD_TCP_CKSUM |
2593                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2594                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2595                 DEV_TX_OFFLOAD_TCP_TSO |
2596                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2597                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2598                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2599                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2600         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2601                                                 sizeof(uint32_t);
2602         dev_info->reta_size = pf->hash_lut_size;
2603         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2604
2605         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2606                 .rx_thresh = {
2607                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2608                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2609                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2610                 },
2611                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2612                 .rx_drop_en = 0,
2613         };
2614
2615         dev_info->default_txconf = (struct rte_eth_txconf) {
2616                 .tx_thresh = {
2617                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2618                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2619                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2620                 },
2621                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2622                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2623                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2624                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2625         };
2626
2627         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2628                 .nb_max = I40E_MAX_RING_DESC,
2629                 .nb_min = I40E_MIN_RING_DESC,
2630                 .nb_align = I40E_ALIGN_RING_DESC,
2631         };
2632
2633         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2634                 .nb_max = I40E_MAX_RING_DESC,
2635                 .nb_min = I40E_MIN_RING_DESC,
2636                 .nb_align = I40E_ALIGN_RING_DESC,
2637         };
2638
2639         if (pf->flags & I40E_FLAG_VMDQ) {
2640                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2641                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2642                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2643                                                 pf->max_nb_vmdq_vsi;
2644                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2645                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2646                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2647         }
2648
2649         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2650                 /* For XL710 */
2651                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2652         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2653                 /* For XXV710 */
2654                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2655         else
2656                 /* For X710 */
2657                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2658 }
2659
2660 static int
2661 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2662 {
2663         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2664         struct i40e_vsi *vsi = pf->main_vsi;
2665         PMD_INIT_FUNC_TRACE();
2666
2667         if (on)
2668                 return i40e_vsi_add_vlan(vsi, vlan_id);
2669         else
2670                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2671 }
2672
2673 static int
2674 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2675                    enum rte_vlan_type vlan_type,
2676                    uint16_t tpid)
2677 {
2678         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2679         uint64_t reg_r = 0, reg_w = 0;
2680         uint16_t reg_id = 0;
2681         int ret = 0;
2682         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2683
2684         switch (vlan_type) {
2685         case ETH_VLAN_TYPE_OUTER:
2686                 if (qinq)
2687                         reg_id = 2;
2688                 else
2689                         reg_id = 3;
2690                 break;
2691         case ETH_VLAN_TYPE_INNER:
2692                 if (qinq)
2693                         reg_id = 3;
2694                 else {
2695                         ret = -EINVAL;
2696                         PMD_DRV_LOG(ERR,
2697                                 "Unsupported vlan type in single vlan.\n");
2698                         return ret;
2699                 }
2700                 break;
2701         default:
2702                 ret = -EINVAL;
2703                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2704                 return ret;
2705         }
2706         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2707                                           &reg_r, NULL);
2708         if (ret != I40E_SUCCESS) {
2709                 PMD_DRV_LOG(ERR, "Fail to debug read from "
2710                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2711                 ret = -EIO;
2712                 return ret;
2713         }
2714         PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
2715                     "0x%08"PRIx64"", reg_id, reg_r);
2716
2717         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
2718         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
2719         if (reg_r == reg_w) {
2720                 ret = 0;
2721                 PMD_DRV_LOG(DEBUG, "No need to write");
2722                 return ret;
2723         }
2724
2725         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
2726                                            reg_w, NULL);
2727         if (ret != I40E_SUCCESS) {
2728                 ret = -EIO;
2729                 PMD_DRV_LOG(ERR, "Fail to debug write to "
2730                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
2731                 return ret;
2732         }
2733         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2734                     "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2735
2736         return ret;
2737 }
2738
2739 static void
2740 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2741 {
2742         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2743         struct i40e_vsi *vsi = pf->main_vsi;
2744
2745         if (mask & ETH_VLAN_FILTER_MASK) {
2746                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
2747                         i40e_vsi_config_vlan_filter(vsi, TRUE);
2748                 else
2749                         i40e_vsi_config_vlan_filter(vsi, FALSE);
2750         }
2751
2752         if (mask & ETH_VLAN_STRIP_MASK) {
2753                 /* Enable or disable VLAN stripping */
2754                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
2755                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
2756                 else
2757                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
2758         }
2759
2760         if (mask & ETH_VLAN_EXTEND_MASK) {
2761                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
2762                         i40e_vsi_config_double_vlan(vsi, TRUE);
2763                         /* Set global registers with default ether type value */
2764                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
2765                                            ETHER_TYPE_VLAN);
2766                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
2767                                            ETHER_TYPE_VLAN);
2768                 }
2769                 else
2770                         i40e_vsi_config_double_vlan(vsi, FALSE);
2771         }
2772 }
2773
2774 static void
2775 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
2776                           __rte_unused uint16_t queue,
2777                           __rte_unused int on)
2778 {
2779         PMD_INIT_FUNC_TRACE();
2780 }
2781
2782 static int
2783 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
2784 {
2785         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2786         struct i40e_vsi *vsi = pf->main_vsi;
2787         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
2788         struct i40e_vsi_vlan_pvid_info info;
2789
2790         memset(&info, 0, sizeof(info));
2791         info.on = on;
2792         if (info.on)
2793                 info.config.pvid = pvid;
2794         else {
2795                 info.config.reject.tagged =
2796                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
2797                 info.config.reject.untagged =
2798                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
2799         }
2800
2801         return i40e_vsi_vlan_pvid_set(vsi, &info);
2802 }
2803
2804 static int
2805 i40e_dev_led_on(struct rte_eth_dev *dev)
2806 {
2807         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2808         uint32_t mode = i40e_led_get(hw);
2809
2810         if (mode == 0)
2811                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
2812
2813         return 0;
2814 }
2815
2816 static int
2817 i40e_dev_led_off(struct rte_eth_dev *dev)
2818 {
2819         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2820         uint32_t mode = i40e_led_get(hw);
2821
2822         if (mode != 0)
2823                 i40e_led_set(hw, 0, false);
2824
2825         return 0;
2826 }
2827
2828 static int
2829 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2830 {
2831         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2832         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2833
2834         fc_conf->pause_time = pf->fc_conf.pause_time;
2835         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
2836         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
2837
2838          /* Return current mode according to actual setting*/
2839         switch (hw->fc.current_mode) {
2840         case I40E_FC_FULL:
2841                 fc_conf->mode = RTE_FC_FULL;
2842                 break;
2843         case I40E_FC_TX_PAUSE:
2844                 fc_conf->mode = RTE_FC_TX_PAUSE;
2845                 break;
2846         case I40E_FC_RX_PAUSE:
2847                 fc_conf->mode = RTE_FC_RX_PAUSE;
2848                 break;
2849         case I40E_FC_NONE:
2850         default:
2851                 fc_conf->mode = RTE_FC_NONE;
2852         };
2853
2854         return 0;
2855 }
2856
2857 static int
2858 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2859 {
2860         uint32_t mflcn_reg, fctrl_reg, reg;
2861         uint32_t max_high_water;
2862         uint8_t i, aq_failure;
2863         int err;
2864         struct i40e_hw *hw;
2865         struct i40e_pf *pf;
2866         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
2867                 [RTE_FC_NONE] = I40E_FC_NONE,
2868                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
2869                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
2870                 [RTE_FC_FULL] = I40E_FC_FULL
2871         };
2872
2873         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
2874
2875         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
2876         if ((fc_conf->high_water > max_high_water) ||
2877                         (fc_conf->high_water < fc_conf->low_water)) {
2878                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
2879                         "High_water must <= %d.", max_high_water);
2880                 return -EINVAL;
2881         }
2882
2883         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2884         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2885         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
2886
2887         pf->fc_conf.pause_time = fc_conf->pause_time;
2888         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
2889         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
2890
2891         PMD_INIT_FUNC_TRACE();
2892
2893         /* All the link flow control related enable/disable register
2894          * configuration is handle by the F/W
2895          */
2896         err = i40e_set_fc(hw, &aq_failure, true);
2897         if (err < 0)
2898                 return -ENOSYS;
2899
2900         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
2901                 /* Configure flow control refresh threshold,
2902                  * the value for stat_tx_pause_refresh_timer[8]
2903                  * is used for global pause operation.
2904                  */
2905
2906                 I40E_WRITE_REG(hw,
2907                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
2908                                pf->fc_conf.pause_time);
2909
2910                 /* configure the timer value included in transmitted pause
2911                  * frame,
2912                  * the value for stat_tx_pause_quanta[8] is used for global
2913                  * pause operation
2914                  */
2915                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
2916                                pf->fc_conf.pause_time);
2917
2918                 fctrl_reg = I40E_READ_REG(hw,
2919                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
2920
2921                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2922                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
2923                 else
2924                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
2925
2926                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
2927                                fctrl_reg);
2928         } else {
2929                 /* Configure pause time (2 TCs per register) */
2930                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
2931                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
2932                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
2933
2934                 /* Configure flow control refresh threshold value */
2935                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
2936                                pf->fc_conf.pause_time / 2);
2937
2938                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
2939
2940                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
2941                  *depending on configuration
2942                  */
2943                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
2944                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
2945                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
2946                 } else {
2947                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
2948                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
2949                 }
2950
2951                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
2952         }
2953
2954         /* config the water marker both based on the packets and bytes */
2955         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
2956                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2957                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2958         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
2959                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2960                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
2961         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
2962                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
2963                        << I40E_KILOSHIFT);
2964         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
2965                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
2966                        << I40E_KILOSHIFT);
2967
2968         I40E_WRITE_FLUSH(hw);
2969
2970         return 0;
2971 }
2972
2973 static int
2974 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
2975                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
2976 {
2977         PMD_INIT_FUNC_TRACE();
2978
2979         return -ENOSYS;
2980 }
2981
2982 /* Add a MAC address, and update filters */
2983 static void
2984 i40e_macaddr_add(struct rte_eth_dev *dev,
2985                  struct ether_addr *mac_addr,
2986                  __rte_unused uint32_t index,
2987                  uint32_t pool)
2988 {
2989         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2990         struct i40e_mac_filter_info mac_filter;
2991         struct i40e_vsi *vsi;
2992         int ret;
2993
2994         /* If VMDQ not enabled or configured, return */
2995         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
2996                           !pf->nb_cfg_vmdq_vsi)) {
2997                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2998                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
2999                         pool);
3000                 return;
3001         }
3002
3003         if (pool > pf->nb_cfg_vmdq_vsi) {
3004                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3005                                 pool, pf->nb_cfg_vmdq_vsi);
3006                 return;
3007         }
3008
3009         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3010         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3011                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3012         else
3013                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3014
3015         if (pool == 0)
3016                 vsi = pf->main_vsi;
3017         else
3018                 vsi = pf->vmdq[pool - 1].vsi;
3019
3020         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3021         if (ret != I40E_SUCCESS) {
3022                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3023                 return;
3024         }
3025 }
3026
3027 /* Remove a MAC address, and update filters */
3028 static void
3029 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3030 {
3031         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3032         struct i40e_vsi *vsi;
3033         struct rte_eth_dev_data *data = dev->data;
3034         struct ether_addr *macaddr;
3035         int ret;
3036         uint32_t i;
3037         uint64_t pool_sel;
3038
3039         macaddr = &(data->mac_addrs[index]);
3040
3041         pool_sel = dev->data->mac_pool_sel[index];
3042
3043         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3044                 if (pool_sel & (1ULL << i)) {
3045                         if (i == 0)
3046                                 vsi = pf->main_vsi;
3047                         else {
3048                                 /* No VMDQ pool enabled or configured */
3049                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3050                                         (i > pf->nb_cfg_vmdq_vsi)) {
3051                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
3052                                                         "/configured");
3053                                         return;
3054                                 }
3055                                 vsi = pf->vmdq[i - 1].vsi;
3056                         }
3057                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3058
3059                         if (ret) {
3060                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3061                                 return;
3062                         }
3063                 }
3064         }
3065 }
3066
3067 /* Set perfect match or hash match of MAC and VLAN for a VF */
3068 static int
3069 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3070                  struct rte_eth_mac_filter *filter,
3071                  bool add)
3072 {
3073         struct i40e_hw *hw;
3074         struct i40e_mac_filter_info mac_filter;
3075         struct ether_addr old_mac;
3076         struct ether_addr *new_mac;
3077         struct i40e_pf_vf *vf = NULL;
3078         uint16_t vf_id;
3079         int ret;
3080
3081         if (pf == NULL) {
3082                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3083                 return -EINVAL;
3084         }
3085         hw = I40E_PF_TO_HW(pf);
3086
3087         if (filter == NULL) {
3088                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3089                 return -EINVAL;
3090         }
3091
3092         new_mac = &filter->mac_addr;
3093
3094         if (is_zero_ether_addr(new_mac)) {
3095                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3096                 return -EINVAL;
3097         }
3098
3099         vf_id = filter->dst_id;
3100
3101         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3102                 PMD_DRV_LOG(ERR, "Invalid argument.");
3103                 return -EINVAL;
3104         }
3105         vf = &pf->vfs[vf_id];
3106
3107         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3108                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3109                 return -EINVAL;
3110         }
3111
3112         if (add) {
3113                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3114                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3115                                 ETHER_ADDR_LEN);
3116                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3117                                  ETHER_ADDR_LEN);
3118
3119                 mac_filter.filter_type = filter->filter_type;
3120                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3121                 if (ret != I40E_SUCCESS) {
3122                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3123                         return -1;
3124                 }
3125                 ether_addr_copy(new_mac, &pf->dev_addr);
3126         } else {
3127                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3128                                 ETHER_ADDR_LEN);
3129                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3130                 if (ret != I40E_SUCCESS) {
3131                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3132                         return -1;
3133                 }
3134
3135                 /* Clear device address as it has been removed */
3136                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3137                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3138         }
3139
3140         return 0;
3141 }
3142
3143 /* MAC filter handle */
3144 static int
3145 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3146                 void *arg)
3147 {
3148         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3149         struct rte_eth_mac_filter *filter;
3150         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3151         int ret = I40E_NOT_SUPPORTED;
3152
3153         filter = (struct rte_eth_mac_filter *)(arg);
3154
3155         switch (filter_op) {
3156         case RTE_ETH_FILTER_NOP:
3157                 ret = I40E_SUCCESS;
3158                 break;
3159         case RTE_ETH_FILTER_ADD:
3160                 i40e_pf_disable_irq0(hw);
3161                 if (filter->is_vf)
3162                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3163                 i40e_pf_enable_irq0(hw);
3164                 break;
3165         case RTE_ETH_FILTER_DELETE:
3166                 i40e_pf_disable_irq0(hw);
3167                 if (filter->is_vf)
3168                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3169                 i40e_pf_enable_irq0(hw);
3170                 break;
3171         default:
3172                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3173                 ret = I40E_ERR_PARAM;
3174                 break;
3175         }
3176
3177         return ret;
3178 }
3179
3180 static int
3181 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3182 {
3183         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3184         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3185         int ret;
3186
3187         if (!lut)
3188                 return -EINVAL;
3189
3190         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3191                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3192                                           lut, lut_size);
3193                 if (ret) {
3194                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3195                         return ret;
3196                 }
3197         } else {
3198                 uint32_t *lut_dw = (uint32_t *)lut;
3199                 uint16_t i, lut_size_dw = lut_size / 4;
3200
3201                 for (i = 0; i < lut_size_dw; i++)
3202                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3203         }
3204
3205         return 0;
3206 }
3207
3208 static int
3209 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3210 {
3211         struct i40e_pf *pf;
3212         struct i40e_hw *hw;
3213         int ret;
3214
3215         if (!vsi || !lut)
3216                 return -EINVAL;
3217
3218         pf = I40E_VSI_TO_PF(vsi);
3219         hw = I40E_VSI_TO_HW(vsi);
3220
3221         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3222                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3223                                           lut, lut_size);
3224                 if (ret) {
3225                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3226                         return ret;
3227                 }
3228         } else {
3229                 uint32_t *lut_dw = (uint32_t *)lut;
3230                 uint16_t i, lut_size_dw = lut_size / 4;
3231
3232                 for (i = 0; i < lut_size_dw; i++)
3233                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3234                 I40E_WRITE_FLUSH(hw);
3235         }
3236
3237         return 0;
3238 }
3239
3240 static int
3241 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3242                          struct rte_eth_rss_reta_entry64 *reta_conf,
3243                          uint16_t reta_size)
3244 {
3245         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3246         uint16_t i, lut_size = pf->hash_lut_size;
3247         uint16_t idx, shift;
3248         uint8_t *lut;
3249         int ret;
3250
3251         if (reta_size != lut_size ||
3252                 reta_size > ETH_RSS_RETA_SIZE_512) {
3253                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3254                         "(%d) doesn't match the number hardware can supported "
3255                                         "(%d)\n", reta_size, lut_size);
3256                 return -EINVAL;
3257         }
3258
3259         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3260         if (!lut) {
3261                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3262                 return -ENOMEM;
3263         }
3264         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3265         if (ret)
3266                 goto out;
3267         for (i = 0; i < reta_size; i++) {
3268                 idx = i / RTE_RETA_GROUP_SIZE;
3269                 shift = i % RTE_RETA_GROUP_SIZE;
3270                 if (reta_conf[idx].mask & (1ULL << shift))
3271                         lut[i] = reta_conf[idx].reta[shift];
3272         }
3273         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3274
3275 out:
3276         rte_free(lut);
3277
3278         return ret;
3279 }
3280
3281 static int
3282 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3283                         struct rte_eth_rss_reta_entry64 *reta_conf,
3284                         uint16_t reta_size)
3285 {
3286         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3287         uint16_t i, lut_size = pf->hash_lut_size;
3288         uint16_t idx, shift;
3289         uint8_t *lut;
3290         int ret;
3291
3292         if (reta_size != lut_size ||
3293                 reta_size > ETH_RSS_RETA_SIZE_512) {
3294                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3295                         "(%d) doesn't match the number hardware can supported "
3296                                         "(%d)\n", reta_size, lut_size);
3297                 return -EINVAL;
3298         }
3299
3300         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3301         if (!lut) {
3302                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3303                 return -ENOMEM;
3304         }
3305
3306         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3307         if (ret)
3308                 goto out;
3309         for (i = 0; i < reta_size; i++) {
3310                 idx = i / RTE_RETA_GROUP_SIZE;
3311                 shift = i % RTE_RETA_GROUP_SIZE;
3312                 if (reta_conf[idx].mask & (1ULL << shift))
3313                         reta_conf[idx].reta[shift] = lut[i];
3314         }
3315
3316 out:
3317         rte_free(lut);
3318
3319         return ret;
3320 }
3321
3322 /**
3323  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3324  * @hw:   pointer to the HW structure
3325  * @mem:  pointer to mem struct to fill out
3326  * @size: size of memory requested
3327  * @alignment: what to align the allocation to
3328  **/
3329 enum i40e_status_code
3330 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3331                         struct i40e_dma_mem *mem,
3332                         u64 size,
3333                         u32 alignment)
3334 {
3335         const struct rte_memzone *mz = NULL;
3336         char z_name[RTE_MEMZONE_NAMESIZE];
3337
3338         if (!mem)
3339                 return I40E_ERR_PARAM;
3340
3341         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3342         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3343                                          alignment, RTE_PGSIZE_2M);
3344         if (!mz)
3345                 return I40E_ERR_NO_MEMORY;
3346
3347         mem->size = size;
3348         mem->va = mz->addr;
3349         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3350         mem->zone = (const void *)mz;
3351         PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3352                     "%"PRIu64, mz->name, mem->pa);
3353
3354         return I40E_SUCCESS;
3355 }
3356
3357 /**
3358  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3359  * @hw:   pointer to the HW structure
3360  * @mem:  ptr to mem struct to free
3361  **/
3362 enum i40e_status_code
3363 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3364                     struct i40e_dma_mem *mem)
3365 {
3366         if (!mem)
3367                 return I40E_ERR_PARAM;
3368
3369         PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3370                     "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3371                     mem->pa);
3372         rte_memzone_free((const struct rte_memzone *)mem->zone);
3373         mem->zone = NULL;
3374         mem->va = NULL;
3375         mem->pa = (u64)0;
3376
3377         return I40E_SUCCESS;
3378 }
3379
3380 /**
3381  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3382  * @hw:   pointer to the HW structure
3383  * @mem:  pointer to mem struct to fill out
3384  * @size: size of memory requested
3385  **/
3386 enum i40e_status_code
3387 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3388                          struct i40e_virt_mem *mem,
3389                          u32 size)
3390 {
3391         if (!mem)
3392                 return I40E_ERR_PARAM;
3393
3394         mem->size = size;
3395         mem->va = rte_zmalloc("i40e", size, 0);
3396
3397         if (mem->va)
3398                 return I40E_SUCCESS;
3399         else
3400                 return I40E_ERR_NO_MEMORY;
3401 }
3402
3403 /**
3404  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3405  * @hw:   pointer to the HW structure
3406  * @mem:  pointer to mem struct to free
3407  **/
3408 enum i40e_status_code
3409 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3410                      struct i40e_virt_mem *mem)
3411 {
3412         if (!mem)
3413                 return I40E_ERR_PARAM;
3414
3415         rte_free(mem->va);
3416         mem->va = NULL;
3417
3418         return I40E_SUCCESS;
3419 }
3420
3421 void
3422 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3423 {
3424         rte_spinlock_init(&sp->spinlock);
3425 }
3426
3427 void
3428 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3429 {
3430         rte_spinlock_lock(&sp->spinlock);
3431 }
3432
3433 void
3434 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3435 {
3436         rte_spinlock_unlock(&sp->spinlock);
3437 }
3438
3439 void
3440 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3441 {
3442         return;
3443 }
3444
3445 /**
3446  * Get the hardware capabilities, which will be parsed
3447  * and saved into struct i40e_hw.
3448  */
3449 static int
3450 i40e_get_cap(struct i40e_hw *hw)
3451 {
3452         struct i40e_aqc_list_capabilities_element_resp *buf;
3453         uint16_t len, size = 0;
3454         int ret;
3455
3456         /* Calculate a huge enough buff for saving response data temporarily */
3457         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3458                                                 I40E_MAX_CAP_ELE_NUM;
3459         buf = rte_zmalloc("i40e", len, 0);
3460         if (!buf) {
3461                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3462                 return I40E_ERR_NO_MEMORY;
3463         }
3464
3465         /* Get, parse the capabilities and save it to hw */
3466         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3467                         i40e_aqc_opc_list_func_capabilities, NULL);
3468         if (ret != I40E_SUCCESS)
3469                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3470
3471         /* Free the temporary buffer after being used */
3472         rte_free(buf);
3473
3474         return ret;
3475 }
3476
3477 static int
3478 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3479 {
3480         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3481         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3482         uint16_t qp_count = 0, vsi_count = 0;
3483
3484         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3485                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3486                 return -EINVAL;
3487         }
3488         /* Add the parameter init for LFC */
3489         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3490         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3491         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3492
3493         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3494         pf->max_num_vsi = hw->func_caps.num_vsis;
3495         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3496         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3497         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3498
3499         /* FDir queue/VSI allocation */
3500         pf->fdir_qp_offset = 0;
3501         if (hw->func_caps.fd) {
3502                 pf->flags |= I40E_FLAG_FDIR;
3503                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3504         } else {
3505                 pf->fdir_nb_qps = 0;
3506         }
3507         qp_count += pf->fdir_nb_qps;
3508         vsi_count += 1;
3509
3510         /* LAN queue/VSI allocation */
3511         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3512         if (!hw->func_caps.rss) {
3513                 pf->lan_nb_qps = 1;
3514         } else {
3515                 pf->flags |= I40E_FLAG_RSS;
3516                 if (hw->mac.type == I40E_MAC_X722)
3517                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3518                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3519         }
3520         qp_count += pf->lan_nb_qps;
3521         vsi_count += 1;
3522
3523         /* VF queue/VSI allocation */
3524         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3525         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
3526                 pf->flags |= I40E_FLAG_SRIOV;
3527                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3528                 pf->vf_num = dev->pci_dev->max_vfs;
3529                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3530                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3531                             pf->vf_nb_qps * pf->vf_num);
3532         } else {
3533                 pf->vf_nb_qps = 0;
3534                 pf->vf_num = 0;
3535         }
3536         qp_count += pf->vf_nb_qps * pf->vf_num;
3537         vsi_count += pf->vf_num;
3538
3539         /* VMDq queue/VSI allocation */
3540         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3541         pf->vmdq_nb_qps = 0;
3542         pf->max_nb_vmdq_vsi = 0;
3543         if (hw->func_caps.vmdq) {
3544                 if (qp_count < hw->func_caps.num_tx_qp &&
3545                         vsi_count < hw->func_caps.num_vsis) {
3546                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3547                                 qp_count) / pf->vmdq_nb_qp_max;
3548
3549                         /* Limit the maximum number of VMDq vsi to the maximum
3550                          * ethdev can support
3551                          */
3552                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3553                                 hw->func_caps.num_vsis - vsi_count);
3554                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3555                                 ETH_64_POOLS);
3556                         if (pf->max_nb_vmdq_vsi) {
3557                                 pf->flags |= I40E_FLAG_VMDQ;
3558                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3559                                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3560                                             "per VMDQ VSI, in total %u queues",
3561                                             pf->max_nb_vmdq_vsi,
3562                                             pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3563                                             pf->max_nb_vmdq_vsi);
3564                         } else {
3565                                 PMD_DRV_LOG(INFO, "No enough queues left for "
3566                                             "VMDq");
3567                         }
3568                 } else {
3569                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3570                 }
3571         }
3572         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3573         vsi_count += pf->max_nb_vmdq_vsi;
3574
3575         if (hw->func_caps.dcb)
3576                 pf->flags |= I40E_FLAG_DCB;
3577
3578         if (qp_count > hw->func_caps.num_tx_qp) {
3579                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3580                             "the hardware maximum %u", qp_count,
3581                             hw->func_caps.num_tx_qp);
3582                 return -EINVAL;
3583         }
3584         if (vsi_count > hw->func_caps.num_vsis) {
3585                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3586                             "the hardware maximum %u", vsi_count,
3587                             hw->func_caps.num_vsis);
3588                 return -EINVAL;
3589         }
3590
3591         return 0;
3592 }
3593
3594 static int
3595 i40e_pf_get_switch_config(struct i40e_pf *pf)
3596 {
3597         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3598         struct i40e_aqc_get_switch_config_resp *switch_config;
3599         struct i40e_aqc_switch_config_element_resp *element;
3600         uint16_t start_seid = 0, num_reported;
3601         int ret;
3602
3603         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3604                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3605         if (!switch_config) {
3606                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3607                 return -ENOMEM;
3608         }
3609
3610         /* Get the switch configurations */
3611         ret = i40e_aq_get_switch_config(hw, switch_config,
3612                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3613         if (ret != I40E_SUCCESS) {
3614                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3615                 goto fail;
3616         }
3617         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3618         if (num_reported != 1) { /* The number should be 1 */
3619                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3620                 goto fail;
3621         }
3622
3623         /* Parse the switch configuration elements */
3624         element = &(switch_config->element[0]);
3625         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3626                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3627                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3628         } else
3629                 PMD_DRV_LOG(INFO, "Unknown element type");
3630
3631 fail:
3632         rte_free(switch_config);
3633
3634         return ret;
3635 }
3636
3637 static int
3638 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3639                         uint32_t num)
3640 {
3641         struct pool_entry *entry;
3642
3643         if (pool == NULL || num == 0)
3644                 return -EINVAL;
3645
3646         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3647         if (entry == NULL) {
3648                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3649                 return -ENOMEM;
3650         }
3651
3652         /* queue heap initialize */
3653         pool->num_free = num;
3654         pool->num_alloc = 0;
3655         pool->base = base;
3656         LIST_INIT(&pool->alloc_list);
3657         LIST_INIT(&pool->free_list);
3658
3659         /* Initialize element  */
3660         entry->base = 0;
3661         entry->len = num;
3662
3663         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3664         return 0;
3665 }
3666
3667 static void
3668 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3669 {
3670         struct pool_entry *entry, *next_entry;
3671
3672         if (pool == NULL)
3673                 return;
3674
3675         for (entry = LIST_FIRST(&pool->alloc_list);
3676                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3677                         entry = next_entry) {
3678                 LIST_REMOVE(entry, next);
3679                 rte_free(entry);
3680         }
3681
3682         for (entry = LIST_FIRST(&pool->free_list);
3683                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3684                         entry = next_entry) {
3685                 LIST_REMOVE(entry, next);
3686                 rte_free(entry);
3687         }
3688
3689         pool->num_free = 0;
3690         pool->num_alloc = 0;
3691         pool->base = 0;
3692         LIST_INIT(&pool->alloc_list);
3693         LIST_INIT(&pool->free_list);
3694 }
3695
3696 static int
3697 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3698                        uint32_t base)
3699 {
3700         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3701         uint32_t pool_offset;
3702         int insert;
3703
3704         if (pool == NULL) {
3705                 PMD_DRV_LOG(ERR, "Invalid parameter");
3706                 return -EINVAL;
3707         }
3708
3709         pool_offset = base - pool->base;
3710         /* Lookup in alloc list */
3711         LIST_FOREACH(entry, &pool->alloc_list, next) {
3712                 if (entry->base == pool_offset) {
3713                         valid_entry = entry;
3714                         LIST_REMOVE(entry, next);
3715                         break;
3716                 }
3717         }
3718
3719         /* Not find, return */
3720         if (valid_entry == NULL) {
3721                 PMD_DRV_LOG(ERR, "Failed to find entry");
3722                 return -EINVAL;
3723         }
3724
3725         /**
3726          * Found it, move it to free list  and try to merge.
3727          * In order to make merge easier, always sort it by qbase.
3728          * Find adjacent prev and last entries.
3729          */
3730         prev = next = NULL;
3731         LIST_FOREACH(entry, &pool->free_list, next) {
3732                 if (entry->base > valid_entry->base) {
3733                         next = entry;
3734                         break;
3735                 }
3736                 prev = entry;
3737         }
3738
3739         insert = 0;
3740         /* Try to merge with next one*/
3741         if (next != NULL) {
3742                 /* Merge with next one */
3743                 if (valid_entry->base + valid_entry->len == next->base) {
3744                         next->base = valid_entry->base;
3745                         next->len += valid_entry->len;
3746                         rte_free(valid_entry);
3747                         valid_entry = next;
3748                         insert = 1;
3749                 }
3750         }
3751
3752         if (prev != NULL) {
3753                 /* Merge with previous one */
3754                 if (prev->base + prev->len == valid_entry->base) {
3755                         prev->len += valid_entry->len;
3756                         /* If it merge with next one, remove next node */
3757                         if (insert == 1) {
3758                                 LIST_REMOVE(valid_entry, next);
3759                                 rte_free(valid_entry);
3760                         } else {
3761                                 rte_free(valid_entry);
3762                                 insert = 1;
3763                         }
3764                 }
3765         }
3766
3767         /* Not find any entry to merge, insert */
3768         if (insert == 0) {
3769                 if (prev != NULL)
3770                         LIST_INSERT_AFTER(prev, valid_entry, next);
3771                 else if (next != NULL)
3772                         LIST_INSERT_BEFORE(next, valid_entry, next);
3773                 else /* It's empty list, insert to head */
3774                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
3775         }
3776
3777         pool->num_free += valid_entry->len;
3778         pool->num_alloc -= valid_entry->len;
3779
3780         return 0;
3781 }
3782
3783 static int
3784 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
3785                        uint16_t num)
3786 {
3787         struct pool_entry *entry, *valid_entry;
3788
3789         if (pool == NULL || num == 0) {
3790                 PMD_DRV_LOG(ERR, "Invalid parameter");
3791                 return -EINVAL;
3792         }
3793
3794         if (pool->num_free < num) {
3795                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
3796                             num, pool->num_free);
3797                 return -ENOMEM;
3798         }
3799
3800         valid_entry = NULL;
3801         /* Lookup  in free list and find most fit one */
3802         LIST_FOREACH(entry, &pool->free_list, next) {
3803                 if (entry->len >= num) {
3804                         /* Find best one */
3805                         if (entry->len == num) {
3806                                 valid_entry = entry;
3807                                 break;
3808                         }
3809                         if (valid_entry == NULL || valid_entry->len > entry->len)
3810                                 valid_entry = entry;
3811                 }
3812         }
3813
3814         /* Not find one to satisfy the request, return */
3815         if (valid_entry == NULL) {
3816                 PMD_DRV_LOG(ERR, "No valid entry found");
3817                 return -ENOMEM;
3818         }
3819         /**
3820          * The entry have equal queue number as requested,
3821          * remove it from alloc_list.
3822          */
3823         if (valid_entry->len == num) {
3824                 LIST_REMOVE(valid_entry, next);
3825         } else {
3826                 /**
3827                  * The entry have more numbers than requested,
3828                  * create a new entry for alloc_list and minus its
3829                  * queue base and number in free_list.
3830                  */
3831                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
3832                 if (entry == NULL) {
3833                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3834                                     "resource pool");
3835                         return -ENOMEM;
3836                 }
3837                 entry->base = valid_entry->base;
3838                 entry->len = num;
3839                 valid_entry->base += num;
3840                 valid_entry->len -= num;
3841                 valid_entry = entry;
3842         }
3843
3844         /* Insert it into alloc list, not sorted */
3845         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
3846
3847         pool->num_free -= valid_entry->len;
3848         pool->num_alloc += valid_entry->len;
3849
3850         return valid_entry->base + pool->base;
3851 }
3852
3853 /**
3854  * bitmap_is_subset - Check whether src2 is subset of src1
3855  **/
3856 static inline int
3857 bitmap_is_subset(uint8_t src1, uint8_t src2)
3858 {
3859         return !((src1 ^ src2) & src2);
3860 }
3861
3862 static enum i40e_status_code
3863 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3864 {
3865         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3866
3867         /* If DCB is not supported, only default TC is supported */
3868         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
3869                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
3870                 return I40E_NOT_SUPPORTED;
3871         }
3872
3873         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
3874                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
3875                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
3876                             enabled_tcmap);
3877                 return I40E_NOT_SUPPORTED;
3878         }
3879         return I40E_SUCCESS;
3880 }
3881
3882 int
3883 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
3884                                 struct i40e_vsi_vlan_pvid_info *info)
3885 {
3886         struct i40e_hw *hw;
3887         struct i40e_vsi_context ctxt;
3888         uint8_t vlan_flags = 0;
3889         int ret;
3890
3891         if (vsi == NULL || info == NULL) {
3892                 PMD_DRV_LOG(ERR, "invalid parameters");
3893                 return I40E_ERR_PARAM;
3894         }
3895
3896         if (info->on) {
3897                 vsi->info.pvid = info->config.pvid;
3898                 /**
3899                  * If insert pvid is enabled, only tagged pkts are
3900                  * allowed to be sent out.
3901                  */
3902                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
3903                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3904         } else {
3905                 vsi->info.pvid = 0;
3906                 if (info->config.reject.tagged == 0)
3907                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
3908
3909                 if (info->config.reject.untagged == 0)
3910                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
3911         }
3912         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
3913                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
3914         vsi->info.port_vlan_flags |= vlan_flags;
3915         vsi->info.valid_sections =
3916                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3917         memset(&ctxt, 0, sizeof(ctxt));
3918         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3919         ctxt.seid = vsi->seid;
3920
3921         hw = I40E_VSI_TO_HW(vsi);
3922         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3923         if (ret != I40E_SUCCESS)
3924                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
3925
3926         return ret;
3927 }
3928
3929 static int
3930 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
3931 {
3932         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3933         int i, ret;
3934         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
3935
3936         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3937         if (ret != I40E_SUCCESS)
3938                 return ret;
3939
3940         if (!vsi->seid) {
3941                 PMD_DRV_LOG(ERR, "seid not valid");
3942                 return -EINVAL;
3943         }
3944
3945         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
3946         tc_bw_data.tc_valid_bits = enabled_tcmap;
3947         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3948                 tc_bw_data.tc_bw_credits[i] =
3949                         (enabled_tcmap & (1 << i)) ? 1 : 0;
3950
3951         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
3952         if (ret != I40E_SUCCESS) {
3953                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
3954                 return ret;
3955         }
3956
3957         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
3958                                         sizeof(vsi->info.qs_handle));
3959         return I40E_SUCCESS;
3960 }
3961
3962 static enum i40e_status_code
3963 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
3964                                  struct i40e_aqc_vsi_properties_data *info,
3965                                  uint8_t enabled_tcmap)
3966 {
3967         enum i40e_status_code ret;
3968         int i, total_tc = 0;
3969         uint16_t qpnum_per_tc, bsf, qp_idx;
3970
3971         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
3972         if (ret != I40E_SUCCESS)
3973                 return ret;
3974
3975         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
3976                 if (enabled_tcmap & (1 << i))
3977                         total_tc++;
3978         vsi->enabled_tc = enabled_tcmap;
3979
3980         /* Number of queues per enabled TC */
3981         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
3982         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
3983         bsf = rte_bsf32(qpnum_per_tc);
3984
3985         /* Adjust the queue number to actual queues that can be applied */
3986         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
3987                 vsi->nb_qps = qpnum_per_tc * total_tc;
3988
3989         /**
3990          * Configure TC and queue mapping parameters, for enabled TC,
3991          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
3992          * default queue will serve it.
3993          */
3994         qp_idx = 0;
3995         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3996                 if (vsi->enabled_tc & (1 << i)) {
3997                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
3998                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
3999                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4000                         qp_idx += qpnum_per_tc;
4001                 } else
4002                         info->tc_mapping[i] = 0;
4003         }
4004
4005         /* Associate queue number with VSI */
4006         if (vsi->type == I40E_VSI_SRIOV) {
4007                 info->mapping_flags |=
4008                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4009                 for (i = 0; i < vsi->nb_qps; i++)
4010                         info->queue_mapping[i] =
4011                                 rte_cpu_to_le_16(vsi->base_queue + i);
4012         } else {
4013                 info->mapping_flags |=
4014                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4015                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4016         }
4017         info->valid_sections |=
4018                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4019
4020         return I40E_SUCCESS;
4021 }
4022
4023 static int
4024 i40e_veb_release(struct i40e_veb *veb)
4025 {
4026         struct i40e_vsi *vsi;
4027         struct i40e_hw *hw;
4028
4029         if (veb == NULL)
4030                 return -EINVAL;
4031
4032         if (!TAILQ_EMPTY(&veb->head)) {
4033                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4034                 return -EACCES;
4035         }
4036         /* associate_vsi field is NULL for floating VEB */
4037         if (veb->associate_vsi != NULL) {
4038                 vsi = veb->associate_vsi;
4039                 hw = I40E_VSI_TO_HW(vsi);
4040
4041                 vsi->uplink_seid = veb->uplink_seid;
4042                 vsi->veb = NULL;
4043         } else {
4044                 veb->associate_pf->main_vsi->floating_veb = NULL;
4045                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4046         }
4047
4048         i40e_aq_delete_element(hw, veb->seid, NULL);
4049         rte_free(veb);
4050         return I40E_SUCCESS;
4051 }
4052
4053 /* Setup a veb */
4054 static struct i40e_veb *
4055 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4056 {
4057         struct i40e_veb *veb;
4058         int ret;
4059         struct i40e_hw *hw;
4060
4061         if (pf == NULL) {
4062                 PMD_DRV_LOG(ERR,
4063                             "veb setup failed, associated PF shouldn't null");
4064                 return NULL;
4065         }
4066         hw = I40E_PF_TO_HW(pf);
4067
4068         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4069         if (!veb) {
4070                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4071                 goto fail;
4072         }
4073
4074         veb->associate_vsi = vsi;
4075         veb->associate_pf = pf;
4076         TAILQ_INIT(&veb->head);
4077         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4078
4079         /* create floating veb if vsi is NULL */
4080         if (vsi != NULL) {
4081                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4082                                       I40E_DEFAULT_TCMAP, false,
4083                                       &veb->seid, false, NULL);
4084         } else {
4085                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4086                                       true, &veb->seid, false, NULL);
4087         }
4088
4089         if (ret != I40E_SUCCESS) {
4090                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4091                             hw->aq.asq_last_status);
4092                 goto fail;
4093         }
4094
4095         /* get statistics index */
4096         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4097                                 &veb->stats_idx, NULL, NULL, NULL);
4098         if (ret != I40E_SUCCESS) {
4099                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
4100                             hw->aq.asq_last_status);
4101                 goto fail;
4102         }
4103         /* Get VEB bandwidth, to be implemented */
4104         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4105         if (vsi)
4106                 vsi->uplink_seid = veb->seid;
4107
4108         return veb;
4109 fail:
4110         rte_free(veb);
4111         return NULL;
4112 }
4113
4114 int
4115 i40e_vsi_release(struct i40e_vsi *vsi)
4116 {
4117         struct i40e_pf *pf;
4118         struct i40e_hw *hw;
4119         struct i40e_vsi_list *vsi_list;
4120         void *temp;
4121         int ret;
4122         struct i40e_mac_filter *f;
4123         uint16_t user_param;
4124
4125         if (!vsi)
4126                 return I40E_SUCCESS;
4127
4128         user_param = vsi->user_param;
4129
4130         pf = I40E_VSI_TO_PF(vsi);
4131         hw = I40E_VSI_TO_HW(vsi);
4132
4133         /* VSI has child to attach, release child first */
4134         if (vsi->veb) {
4135                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4136                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4137                                 return -1;
4138                 }
4139                 i40e_veb_release(vsi->veb);
4140         }
4141
4142         if (vsi->floating_veb) {
4143                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4144                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4145                                 return -1;
4146                 }
4147         }
4148
4149         /* Remove all macvlan filters of the VSI */
4150         i40e_vsi_remove_all_macvlan_filter(vsi);
4151         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4152                 rte_free(f);
4153
4154         if (vsi->type != I40E_VSI_MAIN &&
4155             ((vsi->type != I40E_VSI_SRIOV) ||
4156             !pf->floating_veb_list[user_param])) {
4157                 /* Remove vsi from parent's sibling list */
4158                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4159                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4160                         return I40E_ERR_PARAM;
4161                 }
4162                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4163                                 &vsi->sib_vsi_list, list);
4164
4165                 /* Remove all switch element of the VSI */
4166                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4167                 if (ret != I40E_SUCCESS)
4168                         PMD_DRV_LOG(ERR, "Failed to delete element");
4169         }
4170
4171         if ((vsi->type == I40E_VSI_SRIOV) &&
4172             pf->floating_veb_list[user_param]) {
4173                 /* Remove vsi from parent's sibling list */
4174                 if (vsi->parent_vsi == NULL ||
4175                     vsi->parent_vsi->floating_veb == NULL) {
4176                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4177                         return I40E_ERR_PARAM;
4178                 }
4179                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4180                              &vsi->sib_vsi_list, list);
4181
4182                 /* Remove all switch element of the VSI */
4183                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4184                 if (ret != I40E_SUCCESS)
4185                         PMD_DRV_LOG(ERR, "Failed to delete element");
4186         }
4187
4188         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4189
4190         if (vsi->type != I40E_VSI_SRIOV)
4191                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4192         rte_free(vsi);
4193
4194         return I40E_SUCCESS;
4195 }
4196
4197 static int
4198 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4199 {
4200         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4201         struct i40e_aqc_remove_macvlan_element_data def_filter;
4202         struct i40e_mac_filter_info filter;
4203         int ret;
4204
4205         if (vsi->type != I40E_VSI_MAIN)
4206                 return I40E_ERR_CONFIG;
4207         memset(&def_filter, 0, sizeof(def_filter));
4208         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4209                                         ETH_ADDR_LEN);
4210         def_filter.vlan_tag = 0;
4211         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4212                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4213         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4214         if (ret != I40E_SUCCESS) {
4215                 struct i40e_mac_filter *f;
4216                 struct ether_addr *mac;
4217
4218                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
4219                             "macvlan filter");
4220                 /* It needs to add the permanent mac into mac list */
4221                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4222                 if (f == NULL) {
4223                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4224                         return I40E_ERR_NO_MEMORY;
4225                 }
4226                 mac = &f->mac_info.mac_addr;
4227                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4228                                 ETH_ADDR_LEN);
4229                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4230                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4231                 vsi->mac_num++;
4232
4233                 return ret;
4234         }
4235         (void)rte_memcpy(&filter.mac_addr,
4236                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4237         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4238         return i40e_vsi_add_mac(vsi, &filter);
4239 }
4240
4241 /*
4242  * i40e_vsi_get_bw_config - Query VSI BW Information
4243  * @vsi: the VSI to be queried
4244  *
4245  * Returns 0 on success, negative value on failure
4246  */
4247 static enum i40e_status_code
4248 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4249 {
4250         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4251         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4252         struct i40e_hw *hw = &vsi->adapter->hw;
4253         i40e_status ret;
4254         int i;
4255         uint32_t bw_max;
4256
4257         memset(&bw_config, 0, sizeof(bw_config));
4258         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4259         if (ret != I40E_SUCCESS) {
4260                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4261                             hw->aq.asq_last_status);
4262                 return ret;
4263         }
4264
4265         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4266         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4267                                         &ets_sla_config, NULL);
4268         if (ret != I40E_SUCCESS) {
4269                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
4270                             "configuration %u", hw->aq.asq_last_status);
4271                 return ret;
4272         }
4273
4274         /* store and print out BW info */
4275         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4276         vsi->bw_info.bw_max = bw_config.max_bw;
4277         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4278         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4279         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4280                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4281                      I40E_16_BIT_WIDTH);
4282         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4283                 vsi->bw_info.bw_ets_share_credits[i] =
4284                                 ets_sla_config.share_credits[i];
4285                 vsi->bw_info.bw_ets_credits[i] =
4286                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4287                 /* 4 bits per TC, 4th bit is reserved */
4288                 vsi->bw_info.bw_ets_max[i] =
4289                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4290                                   RTE_LEN2MASK(3, uint8_t));
4291                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4292                             vsi->bw_info.bw_ets_share_credits[i]);
4293                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4294                             vsi->bw_info.bw_ets_credits[i]);
4295                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4296                             vsi->bw_info.bw_ets_max[i]);
4297         }
4298
4299         return I40E_SUCCESS;
4300 }
4301
4302 /* i40e_enable_pf_lb
4303  * @pf: pointer to the pf structure
4304  *
4305  * allow loopback on pf
4306  */
4307 static inline void
4308 i40e_enable_pf_lb(struct i40e_pf *pf)
4309 {
4310         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4311         struct i40e_vsi_context ctxt;
4312         int ret;
4313
4314         /* Use the FW API if FW >= v5.0 */
4315         if (hw->aq.fw_maj_ver < 5) {
4316                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4317                 return;
4318         }
4319
4320         memset(&ctxt, 0, sizeof(ctxt));
4321         ctxt.seid = pf->main_vsi_seid;
4322         ctxt.pf_num = hw->pf_id;
4323         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4324         if (ret) {
4325                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4326                             ret, hw->aq.asq_last_status);
4327                 return;
4328         }
4329         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4330         ctxt.info.valid_sections =
4331                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4332         ctxt.info.switch_id |=
4333                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4334
4335         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4336         if (ret)
4337                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
4338                             hw->aq.asq_last_status);
4339 }
4340
4341 /* Setup a VSI */
4342 struct i40e_vsi *
4343 i40e_vsi_setup(struct i40e_pf *pf,
4344                enum i40e_vsi_type type,
4345                struct i40e_vsi *uplink_vsi,
4346                uint16_t user_param)
4347 {
4348         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4349         struct i40e_vsi *vsi;
4350         struct i40e_mac_filter_info filter;
4351         int ret;
4352         struct i40e_vsi_context ctxt;
4353         struct ether_addr broadcast =
4354                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4355
4356         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4357             uplink_vsi == NULL) {
4358                 PMD_DRV_LOG(ERR, "VSI setup failed, "
4359                             "VSI link shouldn't be NULL");
4360                 return NULL;
4361         }
4362
4363         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4364                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
4365                             "uplink VSI should be NULL");
4366                 return NULL;
4367         }
4368
4369         /* two situations
4370          * 1.type is not MAIN and uplink vsi is not NULL
4371          * If uplink vsi didn't setup VEB, create one first under veb field
4372          * 2.type is SRIOV and the uplink is NULL
4373          * If floating VEB is NULL, create one veb under floating veb field
4374          */
4375
4376         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4377             uplink_vsi->veb == NULL) {
4378                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4379
4380                 if (uplink_vsi->veb == NULL) {
4381                         PMD_DRV_LOG(ERR, "VEB setup failed");
4382                         return NULL;
4383                 }
4384                 /* set ALLOWLOOPBACk on pf, when veb is created */
4385                 i40e_enable_pf_lb(pf);
4386         }
4387
4388         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4389             pf->main_vsi->floating_veb == NULL) {
4390                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4391
4392                 if (pf->main_vsi->floating_veb == NULL) {
4393                         PMD_DRV_LOG(ERR, "VEB setup failed");
4394                         return NULL;
4395                 }
4396         }
4397
4398         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4399         if (!vsi) {
4400                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4401                 return NULL;
4402         }
4403         TAILQ_INIT(&vsi->mac_list);
4404         vsi->type = type;
4405         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4406         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4407         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4408         vsi->user_param = user_param;
4409         /* Allocate queues */
4410         switch (vsi->type) {
4411         case I40E_VSI_MAIN  :
4412                 vsi->nb_qps = pf->lan_nb_qps;
4413                 break;
4414         case I40E_VSI_SRIOV :
4415                 vsi->nb_qps = pf->vf_nb_qps;
4416                 break;
4417         case I40E_VSI_VMDQ2:
4418                 vsi->nb_qps = pf->vmdq_nb_qps;
4419                 break;
4420         case I40E_VSI_FDIR:
4421                 vsi->nb_qps = pf->fdir_nb_qps;
4422                 break;
4423         default:
4424                 goto fail_mem;
4425         }
4426         /*
4427          * The filter status descriptor is reported in rx queue 0,
4428          * while the tx queue for fdir filter programming has no
4429          * such constraints, can be non-zero queues.
4430          * To simplify it, choose FDIR vsi use queue 0 pair.
4431          * To make sure it will use queue 0 pair, queue allocation
4432          * need be done before this function is called
4433          */
4434         if (type != I40E_VSI_FDIR) {
4435                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4436                         if (ret < 0) {
4437                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4438                                                 vsi->seid, ret);
4439                                 goto fail_mem;
4440                         }
4441                         vsi->base_queue = ret;
4442         } else
4443                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4444
4445         /* VF has MSIX interrupt in VF range, don't allocate here */
4446         if (type == I40E_VSI_MAIN) {
4447                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4448                                           RTE_MIN(vsi->nb_qps,
4449                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4450                 if (ret < 0) {
4451                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4452                                     vsi->seid, ret);
4453                         goto fail_queue_alloc;
4454                 }
4455                 vsi->msix_intr = ret;
4456                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4457         } else if (type != I40E_VSI_SRIOV) {
4458                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4459                 if (ret < 0) {
4460                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4461                         goto fail_queue_alloc;
4462                 }
4463                 vsi->msix_intr = ret;
4464                 vsi->nb_msix = 1;
4465         } else {
4466                 vsi->msix_intr = 0;
4467                 vsi->nb_msix = 0;
4468         }
4469
4470         /* Add VSI */
4471         if (type == I40E_VSI_MAIN) {
4472                 /* For main VSI, no need to add since it's default one */
4473                 vsi->uplink_seid = pf->mac_seid;
4474                 vsi->seid = pf->main_vsi_seid;
4475                 /* Bind queues with specific MSIX interrupt */
4476                 /**
4477                  * Needs 2 interrupt at least, one for misc cause which will
4478                  * enabled from OS side, Another for queues binding the
4479                  * interrupt from device side only.
4480                  */
4481
4482                 /* Get default VSI parameters from hardware */
4483                 memset(&ctxt, 0, sizeof(ctxt));
4484                 ctxt.seid = vsi->seid;
4485                 ctxt.pf_num = hw->pf_id;
4486                 ctxt.uplink_seid = vsi->uplink_seid;
4487                 ctxt.vf_num = 0;
4488                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4489                 if (ret != I40E_SUCCESS) {
4490                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4491                         goto fail_msix_alloc;
4492                 }
4493                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4494                         sizeof(struct i40e_aqc_vsi_properties_data));
4495                 vsi->vsi_id = ctxt.vsi_number;
4496                 vsi->info.valid_sections = 0;
4497
4498                 /* Configure tc, enabled TC0 only */
4499                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4500                         I40E_SUCCESS) {
4501                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4502                         goto fail_msix_alloc;
4503                 }
4504
4505                 /* TC, queue mapping */
4506                 memset(&ctxt, 0, sizeof(ctxt));
4507                 vsi->info.valid_sections |=
4508                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4509                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4510                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4511                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4512                         sizeof(struct i40e_aqc_vsi_properties_data));
4513                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4514                                                 I40E_DEFAULT_TCMAP);
4515                 if (ret != I40E_SUCCESS) {
4516                         PMD_DRV_LOG(ERR, "Failed to configure "
4517                                     "TC queue mapping");
4518                         goto fail_msix_alloc;
4519                 }
4520                 ctxt.seid = vsi->seid;
4521                 ctxt.pf_num = hw->pf_id;
4522                 ctxt.uplink_seid = vsi->uplink_seid;
4523                 ctxt.vf_num = 0;
4524
4525                 /* Update VSI parameters */
4526                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4527                 if (ret != I40E_SUCCESS) {
4528                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4529                         goto fail_msix_alloc;
4530                 }
4531
4532                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4533                                                 sizeof(vsi->info.tc_mapping));
4534                 (void)rte_memcpy(&vsi->info.queue_mapping,
4535                                 &ctxt.info.queue_mapping,
4536                         sizeof(vsi->info.queue_mapping));
4537                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4538                 vsi->info.valid_sections = 0;
4539
4540                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4541                                 ETH_ADDR_LEN);
4542
4543                 /**
4544                  * Updating default filter settings are necessary to prevent
4545                  * reception of tagged packets.
4546                  * Some old firmware configurations load a default macvlan
4547                  * filter which accepts both tagged and untagged packets.
4548                  * The updating is to use a normal filter instead if needed.
4549                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4550                  * The firmware with correct configurations load the default
4551                  * macvlan filter which is expected and cannot be removed.
4552                  */
4553                 i40e_update_default_filter_setting(vsi);
4554                 i40e_config_qinq(hw, vsi);
4555         } else if (type == I40E_VSI_SRIOV) {
4556                 memset(&ctxt, 0, sizeof(ctxt));
4557                 /**
4558                  * For other VSI, the uplink_seid equals to uplink VSI's
4559                  * uplink_seid since they share same VEB
4560                  */
4561                 if (uplink_vsi == NULL)
4562                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4563                 else
4564                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4565                 ctxt.pf_num = hw->pf_id;
4566                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4567                 ctxt.uplink_seid = vsi->uplink_seid;
4568                 ctxt.connection_type = 0x1;
4569                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4570
4571                 /* Use the VEB configuration if FW >= v5.0 */
4572                 if (hw->aq.fw_maj_ver >= 5) {
4573                         /* Configure switch ID */
4574                         ctxt.info.valid_sections |=
4575                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4576                         ctxt.info.switch_id =
4577                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4578                 }
4579
4580                 /* Configure port/vlan */
4581                 ctxt.info.valid_sections |=
4582                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4583                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4584                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4585                                                 I40E_DEFAULT_TCMAP);
4586                 if (ret != I40E_SUCCESS) {
4587                         PMD_DRV_LOG(ERR, "Failed to configure "
4588                                     "TC queue mapping");
4589                         goto fail_msix_alloc;
4590                 }
4591                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4592                 ctxt.info.valid_sections |=
4593                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4594                 /**
4595                  * Since VSI is not created yet, only configure parameter,
4596                  * will add vsi below.
4597                  */
4598
4599                 i40e_config_qinq(hw, vsi);
4600         } else if (type == I40E_VSI_VMDQ2) {
4601                 memset(&ctxt, 0, sizeof(ctxt));
4602                 /*
4603                  * For other VSI, the uplink_seid equals to uplink VSI's
4604                  * uplink_seid since they share same VEB
4605                  */
4606                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4607                 ctxt.pf_num = hw->pf_id;
4608                 ctxt.vf_num = 0;
4609                 ctxt.uplink_seid = vsi->uplink_seid;
4610                 ctxt.connection_type = 0x1;
4611                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4612
4613                 ctxt.info.valid_sections |=
4614                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4615                 /* user_param carries flag to enable loop back */
4616                 if (user_param) {
4617                         ctxt.info.switch_id =
4618                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4619                         ctxt.info.switch_id |=
4620                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4621                 }
4622
4623                 /* Configure port/vlan */
4624                 ctxt.info.valid_sections |=
4625                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4626                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4627                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4628                                                 I40E_DEFAULT_TCMAP);
4629                 if (ret != I40E_SUCCESS) {
4630                         PMD_DRV_LOG(ERR, "Failed to configure "
4631                                         "TC queue mapping");
4632                         goto fail_msix_alloc;
4633                 }
4634                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4635                 ctxt.info.valid_sections |=
4636                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4637         } else if (type == I40E_VSI_FDIR) {
4638                 memset(&ctxt, 0, sizeof(ctxt));
4639                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4640                 ctxt.pf_num = hw->pf_id;
4641                 ctxt.vf_num = 0;
4642                 ctxt.uplink_seid = vsi->uplink_seid;
4643                 ctxt.connection_type = 0x1;     /* regular data port */
4644                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4645                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4646                                                 I40E_DEFAULT_TCMAP);
4647                 if (ret != I40E_SUCCESS) {
4648                         PMD_DRV_LOG(ERR, "Failed to configure "
4649                                         "TC queue mapping.");
4650                         goto fail_msix_alloc;
4651                 }
4652                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4653                 ctxt.info.valid_sections |=
4654                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4655         } else {
4656                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4657                 goto fail_msix_alloc;
4658         }
4659
4660         if (vsi->type != I40E_VSI_MAIN) {
4661                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4662                 if (ret != I40E_SUCCESS) {
4663                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4664                                     hw->aq.asq_last_status);
4665                         goto fail_msix_alloc;
4666                 }
4667                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4668                 vsi->info.valid_sections = 0;
4669                 vsi->seid = ctxt.seid;
4670                 vsi->vsi_id = ctxt.vsi_number;
4671                 vsi->sib_vsi_list.vsi = vsi;
4672                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4673                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4674                                           &vsi->sib_vsi_list, list);
4675                 } else {
4676                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4677                                           &vsi->sib_vsi_list, list);
4678                 }
4679         }
4680
4681         /* MAC/VLAN configuration */
4682         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4683         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4684
4685         ret = i40e_vsi_add_mac(vsi, &filter);
4686         if (ret != I40E_SUCCESS) {
4687                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4688                 goto fail_msix_alloc;
4689         }
4690
4691         /* Get VSI BW information */
4692         i40e_vsi_get_bw_config(vsi);
4693         return vsi;
4694 fail_msix_alloc:
4695         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4696 fail_queue_alloc:
4697         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4698 fail_mem:
4699         rte_free(vsi);
4700         return NULL;
4701 }
4702
4703 /* Configure vlan filter on or off */
4704 int
4705 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
4706 {
4707         int i, num;
4708         struct i40e_mac_filter *f;
4709         void *temp;
4710         struct i40e_mac_filter_info *mac_filter;
4711         enum rte_mac_filter_type desired_filter;
4712         int ret = I40E_SUCCESS;
4713
4714         if (on) {
4715                 /* Filter to match MAC and VLAN */
4716                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
4717         } else {
4718                 /* Filter to match only MAC */
4719                 desired_filter = RTE_MAC_PERFECT_MATCH;
4720         }
4721
4722         num = vsi->mac_num;
4723
4724         mac_filter = rte_zmalloc("mac_filter_info_data",
4725                                  num * sizeof(*mac_filter), 0);
4726         if (mac_filter == NULL) {
4727                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4728                 return I40E_ERR_NO_MEMORY;
4729         }
4730
4731         i = 0;
4732
4733         /* Remove all existing mac */
4734         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
4735                 mac_filter[i] = f->mac_info;
4736                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
4737                 if (ret) {
4738                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4739                                     on ? "enable" : "disable");
4740                         goto DONE;
4741                 }
4742                 i++;
4743         }
4744
4745         /* Override with new filter */
4746         for (i = 0; i < num; i++) {
4747                 mac_filter[i].filter_type = desired_filter;
4748                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
4749                 if (ret) {
4750                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
4751                                     on ? "enable" : "disable");
4752                         goto DONE;
4753                 }
4754         }
4755
4756 DONE:
4757         rte_free(mac_filter);
4758         return ret;
4759 }
4760
4761 /* Configure vlan stripping on or off */
4762 int
4763 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
4764 {
4765         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4766         struct i40e_vsi_context ctxt;
4767         uint8_t vlan_flags;
4768         int ret = I40E_SUCCESS;
4769
4770         /* Check if it has been already on or off */
4771         if (vsi->info.valid_sections &
4772                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
4773                 if (on) {
4774                         if ((vsi->info.port_vlan_flags &
4775                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
4776                                 return 0; /* already on */
4777                 } else {
4778                         if ((vsi->info.port_vlan_flags &
4779                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
4780                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
4781                                 return 0; /* already off */
4782                 }
4783         }
4784
4785         if (on)
4786                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4787         else
4788                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
4789         vsi->info.valid_sections =
4790                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4791         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
4792         vsi->info.port_vlan_flags |= vlan_flags;
4793         ctxt.seid = vsi->seid;
4794         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4795         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4796         if (ret)
4797                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
4798                             on ? "enable" : "disable");
4799
4800         return ret;
4801 }
4802
4803 static int
4804 i40e_dev_init_vlan(struct rte_eth_dev *dev)
4805 {
4806         struct rte_eth_dev_data *data = dev->data;
4807         int ret;
4808         int mask = 0;
4809
4810         /* Apply vlan offload setting */
4811         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
4812         i40e_vlan_offload_set(dev, mask);
4813
4814         /* Apply double-vlan setting, not implemented yet */
4815
4816         /* Apply pvid setting */
4817         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
4818                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
4819         if (ret)
4820                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
4821
4822         return ret;
4823 }
4824
4825 static int
4826 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
4827 {
4828         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4829
4830         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
4831 }
4832
4833 static int
4834 i40e_update_flow_control(struct i40e_hw *hw)
4835 {
4836 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
4837         struct i40e_link_status link_status;
4838         uint32_t rxfc = 0, txfc = 0, reg;
4839         uint8_t an_info;
4840         int ret;
4841
4842         memset(&link_status, 0, sizeof(link_status));
4843         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
4844         if (ret != I40E_SUCCESS) {
4845                 PMD_DRV_LOG(ERR, "Failed to get link status information");
4846                 goto write_reg; /* Disable flow control */
4847         }
4848
4849         an_info = hw->phy.link_info.an_info;
4850         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
4851                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
4852                 ret = I40E_ERR_NOT_READY;
4853                 goto write_reg; /* Disable flow control */
4854         }
4855         /**
4856          * If link auto negotiation is enabled, flow control needs to
4857          * be configured according to it
4858          */
4859         switch (an_info & I40E_LINK_PAUSE_RXTX) {
4860         case I40E_LINK_PAUSE_RXTX:
4861                 rxfc = 1;
4862                 txfc = 1;
4863                 hw->fc.current_mode = I40E_FC_FULL;
4864                 break;
4865         case I40E_AQ_LINK_PAUSE_RX:
4866                 rxfc = 1;
4867                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
4868                 break;
4869         case I40E_AQ_LINK_PAUSE_TX:
4870                 txfc = 1;
4871                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
4872                 break;
4873         default:
4874                 hw->fc.current_mode = I40E_FC_NONE;
4875                 break;
4876         }
4877
4878 write_reg:
4879         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
4880                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
4881         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4882         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
4883         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
4884         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
4885
4886         return ret;
4887 }
4888
4889 /* PF setup */
4890 static int
4891 i40e_pf_setup(struct i40e_pf *pf)
4892 {
4893         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4894         struct i40e_filter_control_settings settings;
4895         struct i40e_vsi *vsi;
4896         int ret;
4897
4898         /* Clear all stats counters */
4899         pf->offset_loaded = FALSE;
4900         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
4901         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
4902
4903         ret = i40e_pf_get_switch_config(pf);
4904         if (ret != I40E_SUCCESS) {
4905                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
4906                 return ret;
4907         }
4908         if (pf->flags & I40E_FLAG_FDIR) {
4909                 /* make queue allocated first, let FDIR use queue pair 0*/
4910                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
4911                 if (ret != I40E_FDIR_QUEUE_ID) {
4912                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
4913                                     " ret =%d", ret);
4914                         pf->flags &= ~I40E_FLAG_FDIR;
4915                 }
4916         }
4917         /*  main VSI setup */
4918         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
4919         if (!vsi) {
4920                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
4921                 return I40E_ERR_NOT_READY;
4922         }
4923         pf->main_vsi = vsi;
4924
4925         /* Configure filter control */
4926         memset(&settings, 0, sizeof(settings));
4927         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
4928                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
4929         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
4930                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
4931         else {
4932                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
4933                                                 hw->func_caps.rss_table_size);
4934                 return I40E_ERR_PARAM;
4935         }
4936         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
4937                         "size: %u\n", hw->func_caps.rss_table_size);
4938         pf->hash_lut_size = hw->func_caps.rss_table_size;
4939
4940         /* Enable ethtype and macvlan filters */
4941         settings.enable_ethtype = TRUE;
4942         settings.enable_macvlan = TRUE;
4943         ret = i40e_set_filter_control(hw, &settings);
4944         if (ret)
4945                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
4946                                                                 ret);
4947
4948         /* Update flow control according to the auto negotiation */
4949         i40e_update_flow_control(hw);
4950
4951         return I40E_SUCCESS;
4952 }
4953
4954 int
4955 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
4956 {
4957         uint32_t reg;
4958         uint16_t j;
4959
4960         /**
4961          * Set or clear TX Queue Disable flags,
4962          * which is required by hardware.
4963          */
4964         i40e_pre_tx_queue_cfg(hw, q_idx, on);
4965         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
4966
4967         /* Wait until the request is finished */
4968         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4969                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4970                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4971                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
4972                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
4973                                                         & 0x1))) {
4974                         break;
4975                 }
4976         }
4977         if (on) {
4978                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
4979                         return I40E_SUCCESS; /* already on, skip next steps */
4980
4981                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
4982                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4983         } else {
4984                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
4985                         return I40E_SUCCESS; /* already off, skip next steps */
4986                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4987         }
4988         /* Write the register */
4989         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
4990         /* Check the result */
4991         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
4992                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
4993                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
4994                 if (on) {
4995                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
4996                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
4997                                 break;
4998                 } else {
4999                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5000                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5001                                 break;
5002                 }
5003         }
5004         /* Check if it is timeout */
5005         if (j >= I40E_CHK_Q_ENA_COUNT) {
5006                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5007                             (on ? "enable" : "disable"), q_idx);
5008                 return I40E_ERR_TIMEOUT;
5009         }
5010
5011         return I40E_SUCCESS;
5012 }
5013
5014 /* Swith on or off the tx queues */
5015 static int
5016 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5017 {
5018         struct rte_eth_dev_data *dev_data = pf->dev_data;
5019         struct i40e_tx_queue *txq;
5020         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5021         uint16_t i;
5022         int ret;
5023
5024         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5025                 txq = dev_data->tx_queues[i];
5026                 /* Don't operate the queue if not configured or
5027                  * if starting only per queue */
5028                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5029                         continue;
5030                 if (on)
5031                         ret = i40e_dev_tx_queue_start(dev, i);
5032                 else
5033                         ret = i40e_dev_tx_queue_stop(dev, i);
5034                 if ( ret != I40E_SUCCESS)
5035                         return ret;
5036         }
5037
5038         return I40E_SUCCESS;
5039 }
5040
5041 int
5042 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5043 {
5044         uint32_t reg;
5045         uint16_t j;
5046
5047         /* Wait until the request is finished */
5048         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5049                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5050                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5051                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5052                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5053                         break;
5054         }
5055
5056         if (on) {
5057                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5058                         return I40E_SUCCESS; /* Already on, skip next steps */
5059                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5060         } else {
5061                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5062                         return I40E_SUCCESS; /* Already off, skip next steps */
5063                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5064         }
5065
5066         /* Write the register */
5067         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5068         /* Check the result */
5069         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5070                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5071                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5072                 if (on) {
5073                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5074                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5075                                 break;
5076                 } else {
5077                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5078                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5079                                 break;
5080                 }
5081         }
5082
5083         /* Check if it is timeout */
5084         if (j >= I40E_CHK_Q_ENA_COUNT) {
5085                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5086                             (on ? "enable" : "disable"), q_idx);
5087                 return I40E_ERR_TIMEOUT;
5088         }
5089
5090         return I40E_SUCCESS;
5091 }
5092 /* Switch on or off the rx queues */
5093 static int
5094 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5095 {
5096         struct rte_eth_dev_data *dev_data = pf->dev_data;
5097         struct i40e_rx_queue *rxq;
5098         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5099         uint16_t i;
5100         int ret;
5101
5102         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5103                 rxq = dev_data->rx_queues[i];
5104                 /* Don't operate the queue if not configured or
5105                  * if starting only per queue */
5106                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5107                         continue;
5108                 if (on)
5109                         ret = i40e_dev_rx_queue_start(dev, i);
5110                 else
5111                         ret = i40e_dev_rx_queue_stop(dev, i);
5112                 if (ret != I40E_SUCCESS)
5113                         return ret;
5114         }
5115
5116         return I40E_SUCCESS;
5117 }
5118
5119 /* Switch on or off all the rx/tx queues */
5120 int
5121 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5122 {
5123         int ret;
5124
5125         if (on) {
5126                 /* enable rx queues before enabling tx queues */
5127                 ret = i40e_dev_switch_rx_queues(pf, on);
5128                 if (ret) {
5129                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5130                         return ret;
5131                 }
5132                 ret = i40e_dev_switch_tx_queues(pf, on);
5133         } else {
5134                 /* Stop tx queues before stopping rx queues */
5135                 ret = i40e_dev_switch_tx_queues(pf, on);
5136                 if (ret) {
5137                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5138                         return ret;
5139                 }
5140                 ret = i40e_dev_switch_rx_queues(pf, on);
5141         }
5142
5143         return ret;
5144 }
5145
5146 /* Initialize VSI for TX */
5147 static int
5148 i40e_dev_tx_init(struct i40e_pf *pf)
5149 {
5150         struct rte_eth_dev_data *data = pf->dev_data;
5151         uint16_t i;
5152         uint32_t ret = I40E_SUCCESS;
5153         struct i40e_tx_queue *txq;
5154
5155         for (i = 0; i < data->nb_tx_queues; i++) {
5156                 txq = data->tx_queues[i];
5157                 if (!txq || !txq->q_set)
5158                         continue;
5159                 ret = i40e_tx_queue_init(txq);
5160                 if (ret != I40E_SUCCESS)
5161                         break;
5162         }
5163         if (ret == I40E_SUCCESS)
5164                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5165                                      ->eth_dev);
5166
5167         return ret;
5168 }
5169
5170 /* Initialize VSI for RX */
5171 static int
5172 i40e_dev_rx_init(struct i40e_pf *pf)
5173 {
5174         struct rte_eth_dev_data *data = pf->dev_data;
5175         int ret = I40E_SUCCESS;
5176         uint16_t i;
5177         struct i40e_rx_queue *rxq;
5178
5179         i40e_pf_config_mq_rx(pf);
5180         for (i = 0; i < data->nb_rx_queues; i++) {
5181                 rxq = data->rx_queues[i];
5182                 if (!rxq || !rxq->q_set)
5183                         continue;
5184
5185                 ret = i40e_rx_queue_init(rxq);
5186                 if (ret != I40E_SUCCESS) {
5187                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
5188                                     "initialization");
5189                         break;
5190                 }
5191         }
5192         if (ret == I40E_SUCCESS)
5193                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5194                                      ->eth_dev);
5195
5196         return ret;
5197 }
5198
5199 static int
5200 i40e_dev_rxtx_init(struct i40e_pf *pf)
5201 {
5202         int err;
5203
5204         err = i40e_dev_tx_init(pf);
5205         if (err) {
5206                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5207                 return err;
5208         }
5209         err = i40e_dev_rx_init(pf);
5210         if (err) {
5211                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5212                 return err;
5213         }
5214
5215         return err;
5216 }
5217
5218 static int
5219 i40e_vmdq_setup(struct rte_eth_dev *dev)
5220 {
5221         struct rte_eth_conf *conf = &dev->data->dev_conf;
5222         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5223         int i, err, conf_vsis, j, loop;
5224         struct i40e_vsi *vsi;
5225         struct i40e_vmdq_info *vmdq_info;
5226         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5227         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5228
5229         /*
5230          * Disable interrupt to avoid message from VF. Furthermore, it will
5231          * avoid race condition in VSI creation/destroy.
5232          */
5233         i40e_pf_disable_irq0(hw);
5234
5235         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5236                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5237                 return -ENOTSUP;
5238         }
5239
5240         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5241         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5242                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5243                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5244                         pf->max_nb_vmdq_vsi);
5245                 return -ENOTSUP;
5246         }
5247
5248         if (pf->vmdq != NULL) {
5249                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5250                 return 0;
5251         }
5252
5253         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5254                                 sizeof(*vmdq_info) * conf_vsis, 0);
5255
5256         if (pf->vmdq == NULL) {
5257                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5258                 return -ENOMEM;
5259         }
5260
5261         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5262
5263         /* Create VMDQ VSI */
5264         for (i = 0; i < conf_vsis; i++) {
5265                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5266                                 vmdq_conf->enable_loop_back);
5267                 if (vsi == NULL) {
5268                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5269                         err = -1;
5270                         goto err_vsi_setup;
5271                 }
5272                 vmdq_info = &pf->vmdq[i];
5273                 vmdq_info->pf = pf;
5274                 vmdq_info->vsi = vsi;
5275         }
5276         pf->nb_cfg_vmdq_vsi = conf_vsis;
5277
5278         /* Configure Vlan */
5279         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5280         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5281                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5282                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5283                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5284                                         vmdq_conf->pool_map[i].vlan_id, j);
5285
5286                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5287                                                 vmdq_conf->pool_map[i].vlan_id);
5288                                 if (err) {
5289                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5290                                         err = -1;
5291                                         goto err_vsi_setup;
5292                                 }
5293                         }
5294                 }
5295         }
5296
5297         i40e_pf_enable_irq0(hw);
5298
5299         return 0;
5300
5301 err_vsi_setup:
5302         for (i = 0; i < conf_vsis; i++)
5303                 if (pf->vmdq[i].vsi == NULL)
5304                         break;
5305                 else
5306                         i40e_vsi_release(pf->vmdq[i].vsi);
5307
5308         rte_free(pf->vmdq);
5309         pf->vmdq = NULL;
5310         i40e_pf_enable_irq0(hw);
5311         return err;
5312 }
5313
5314 static void
5315 i40e_stat_update_32(struct i40e_hw *hw,
5316                    uint32_t reg,
5317                    bool offset_loaded,
5318                    uint64_t *offset,
5319                    uint64_t *stat)
5320 {
5321         uint64_t new_data;
5322
5323         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5324         if (!offset_loaded)
5325                 *offset = new_data;
5326
5327         if (new_data >= *offset)
5328                 *stat = (uint64_t)(new_data - *offset);
5329         else
5330                 *stat = (uint64_t)((new_data +
5331                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5332 }
5333
5334 static void
5335 i40e_stat_update_48(struct i40e_hw *hw,
5336                    uint32_t hireg,
5337                    uint32_t loreg,
5338                    bool offset_loaded,
5339                    uint64_t *offset,
5340                    uint64_t *stat)
5341 {
5342         uint64_t new_data;
5343
5344         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5345         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5346                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5347
5348         if (!offset_loaded)
5349                 *offset = new_data;
5350
5351         if (new_data >= *offset)
5352                 *stat = new_data - *offset;
5353         else
5354                 *stat = (uint64_t)((new_data +
5355                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5356
5357         *stat &= I40E_48_BIT_MASK;
5358 }
5359
5360 /* Disable IRQ0 */
5361 void
5362 i40e_pf_disable_irq0(struct i40e_hw *hw)
5363 {
5364         /* Disable all interrupt types */
5365         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5366         I40E_WRITE_FLUSH(hw);
5367 }
5368
5369 /* Enable IRQ0 */
5370 void
5371 i40e_pf_enable_irq0(struct i40e_hw *hw)
5372 {
5373         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5374                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5375                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5376                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5377         I40E_WRITE_FLUSH(hw);
5378 }
5379
5380 static void
5381 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5382 {
5383         /* read pending request and disable first */
5384         i40e_pf_disable_irq0(hw);
5385         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5386         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5387                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5388
5389         if (no_queue)
5390                 /* Link no queues with irq0 */
5391                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5392                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5393 }
5394
5395 static void
5396 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5397 {
5398         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5399         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5400         int i;
5401         uint16_t abs_vf_id;
5402         uint32_t index, offset, val;
5403
5404         if (!pf->vfs)
5405                 return;
5406         /**
5407          * Try to find which VF trigger a reset, use absolute VF id to access
5408          * since the reg is global register.
5409          */
5410         for (i = 0; i < pf->vf_num; i++) {
5411                 abs_vf_id = hw->func_caps.vf_base_id + i;
5412                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5413                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5414                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5415                 /* VFR event occured */
5416                 if (val & (0x1 << offset)) {
5417                         int ret;
5418
5419                         /* Clear the event first */
5420                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5421                                                         (0x1 << offset));
5422                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5423                         /**
5424                          * Only notify a VF reset event occured,
5425                          * don't trigger another SW reset
5426                          */
5427                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5428                         if (ret != I40E_SUCCESS)
5429                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5430                 }
5431         }
5432 }
5433
5434 static void
5435 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5436 {
5437         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5438         struct i40e_arq_event_info info;
5439         uint16_t pending, opcode;
5440         int ret;
5441
5442         info.buf_len = I40E_AQ_BUF_SZ;
5443         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5444         if (!info.msg_buf) {
5445                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5446                 return;
5447         }
5448
5449         pending = 1;
5450         while (pending) {
5451                 ret = i40e_clean_arq_element(hw, &info, &pending);
5452
5453                 if (ret != I40E_SUCCESS) {
5454                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5455                                     "aq_err: %u", hw->aq.asq_last_status);
5456                         break;
5457                 }
5458                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5459
5460                 switch (opcode) {
5461                 case i40e_aqc_opc_send_msg_to_pf:
5462                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5463                         i40e_pf_host_handle_vf_msg(dev,
5464                                         rte_le_to_cpu_16(info.desc.retval),
5465                                         rte_le_to_cpu_32(info.desc.cookie_high),
5466                                         rte_le_to_cpu_32(info.desc.cookie_low),
5467                                         info.msg_buf,
5468                                         info.msg_len);
5469                         break;
5470                 default:
5471                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5472                                     opcode);
5473                         break;
5474                 }
5475         }
5476         rte_free(info.msg_buf);
5477 }
5478
5479 /*
5480  * Interrupt handler is registered as the alarm callback for handling LSC
5481  * interrupt in a definite of time, in order to wait the NIC into a stable
5482  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
5483  * no need for link down interrupt.
5484  */
5485 static void
5486 i40e_dev_interrupt_delayed_handler(void *param)
5487 {
5488         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5489         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5490         uint32_t icr0;
5491
5492         /* read interrupt causes again */
5493         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5494
5495 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5496         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5497                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
5498         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5499                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
5500         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5501                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
5502         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5503                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
5504         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5505                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
5506                                                                 "state\n");
5507         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5508                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
5509         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5510                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
5511 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5512
5513         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5514                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
5515                 i40e_dev_handle_vfr_event(dev);
5516         }
5517         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5518                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
5519                 i40e_dev_handle_aq_msg(dev);
5520         }
5521
5522         /* handle the link up interrupt in an alarm callback */
5523         i40e_dev_link_update(dev, 0);
5524         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
5525
5526         i40e_pf_enable_irq0(hw);
5527         rte_intr_enable(&(dev->pci_dev->intr_handle));
5528 }
5529
5530 /**
5531  * Interrupt handler triggered by NIC  for handling
5532  * specific interrupt.
5533  *
5534  * @param handle
5535  *  Pointer to interrupt handle.
5536  * @param param
5537  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5538  *
5539  * @return
5540  *  void
5541  */
5542 static void
5543 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
5544                            void *param)
5545 {
5546         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5547         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5548         uint32_t icr0;
5549
5550         /* Disable interrupt */
5551         i40e_pf_disable_irq0(hw);
5552
5553         /* read out interrupt causes */
5554         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5555
5556         /* No interrupt event indicated */
5557         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5558                 PMD_DRV_LOG(INFO, "No interrupt event");
5559                 goto done;
5560         }
5561 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5562         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5563                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5564         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5565                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5566         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5567                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5568         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5569                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5570         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5571                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5572         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5573                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5574         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5575                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5576 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5577
5578         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5579                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5580                 i40e_dev_handle_vfr_event(dev);
5581         }
5582         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5583                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5584                 i40e_dev_handle_aq_msg(dev);
5585         }
5586
5587         /* Link Status Change interrupt */
5588         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
5589 #define I40E_US_PER_SECOND 1000000
5590                 struct rte_eth_link link;
5591
5592                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
5593                 memset(&link, 0, sizeof(link));
5594                 rte_i40e_dev_atomic_read_link_status(dev, &link);
5595                 i40e_dev_link_update(dev, 0);
5596
5597                 /*
5598                  * For link up interrupt, it needs to wait 1 second to let the
5599                  * hardware be a stable state. Otherwise several consecutive
5600                  * interrupts can be observed.
5601                  * For link down interrupt, no need to wait.
5602                  */
5603                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
5604                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
5605                         return;
5606                 else
5607                         _rte_eth_dev_callback_process(dev,
5608                                 RTE_ETH_EVENT_INTR_LSC, NULL);
5609         }
5610
5611 done:
5612         /* Enable interrupt */
5613         i40e_pf_enable_irq0(hw);
5614         rte_intr_enable(&(dev->pci_dev->intr_handle));
5615 }
5616
5617 static int
5618 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5619                          struct i40e_macvlan_filter *filter,
5620                          int total)
5621 {
5622         int ele_num, ele_buff_size;
5623         int num, actual_num, i;
5624         uint16_t flags;
5625         int ret = I40E_SUCCESS;
5626         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5627         struct i40e_aqc_add_macvlan_element_data *req_list;
5628
5629         if (filter == NULL  || total == 0)
5630                 return I40E_ERR_PARAM;
5631         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5632         ele_buff_size = hw->aq.asq_buf_size;
5633
5634         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5635         if (req_list == NULL) {
5636                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5637                 return I40E_ERR_NO_MEMORY;
5638         }
5639
5640         num = 0;
5641         do {
5642                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5643                 memset(req_list, 0, ele_buff_size);
5644
5645                 for (i = 0; i < actual_num; i++) {
5646                         (void)rte_memcpy(req_list[i].mac_addr,
5647                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5648                         req_list[i].vlan_tag =
5649                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5650
5651                         switch (filter[num + i].filter_type) {
5652                         case RTE_MAC_PERFECT_MATCH:
5653                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5654                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5655                                 break;
5656                         case RTE_MACVLAN_PERFECT_MATCH:
5657                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5658                                 break;
5659                         case RTE_MAC_HASH_MATCH:
5660                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5661                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5662                                 break;
5663                         case RTE_MACVLAN_HASH_MATCH:
5664                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5665                                 break;
5666                         default:
5667                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5668                                 ret = I40E_ERR_PARAM;
5669                                 goto DONE;
5670                         }
5671
5672                         req_list[i].queue_number = 0;
5673
5674                         req_list[i].flags = rte_cpu_to_le_16(flags);
5675                 }
5676
5677                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5678                                                 actual_num, NULL);
5679                 if (ret != I40E_SUCCESS) {
5680                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5681                         goto DONE;
5682                 }
5683                 num += actual_num;
5684         } while (num < total);
5685
5686 DONE:
5687         rte_free(req_list);
5688         return ret;
5689 }
5690
5691 static int
5692 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5693                             struct i40e_macvlan_filter *filter,
5694                             int total)
5695 {
5696         int ele_num, ele_buff_size;
5697         int num, actual_num, i;
5698         uint16_t flags;
5699         int ret = I40E_SUCCESS;
5700         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5701         struct i40e_aqc_remove_macvlan_element_data *req_list;
5702
5703         if (filter == NULL  || total == 0)
5704                 return I40E_ERR_PARAM;
5705
5706         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5707         ele_buff_size = hw->aq.asq_buf_size;
5708
5709         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5710         if (req_list == NULL) {
5711                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5712                 return I40E_ERR_NO_MEMORY;
5713         }
5714
5715         num = 0;
5716         do {
5717                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5718                 memset(req_list, 0, ele_buff_size);
5719
5720                 for (i = 0; i < actual_num; i++) {
5721                         (void)rte_memcpy(req_list[i].mac_addr,
5722                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5723                         req_list[i].vlan_tag =
5724                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5725
5726                         switch (filter[num + i].filter_type) {
5727                         case RTE_MAC_PERFECT_MATCH:
5728                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5729                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5730                                 break;
5731                         case RTE_MACVLAN_PERFECT_MATCH:
5732                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5733                                 break;
5734                         case RTE_MAC_HASH_MATCH:
5735                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5736                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5737                                 break;
5738                         case RTE_MACVLAN_HASH_MATCH:
5739                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5740                                 break;
5741                         default:
5742                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5743                                 ret = I40E_ERR_PARAM;
5744                                 goto DONE;
5745                         }
5746                         req_list[i].flags = rte_cpu_to_le_16(flags);
5747                 }
5748
5749                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5750                                                 actual_num, NULL);
5751                 if (ret != I40E_SUCCESS) {
5752                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5753                         goto DONE;
5754                 }
5755                 num += actual_num;
5756         } while (num < total);
5757
5758 DONE:
5759         rte_free(req_list);
5760         return ret;
5761 }
5762
5763 /* Find out specific MAC filter */
5764 static struct i40e_mac_filter *
5765 i40e_find_mac_filter(struct i40e_vsi *vsi,
5766                          struct ether_addr *macaddr)
5767 {
5768         struct i40e_mac_filter *f;
5769
5770         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5771                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
5772                         return f;
5773         }
5774
5775         return NULL;
5776 }
5777
5778 static bool
5779 i40e_find_vlan_filter(struct i40e_vsi *vsi,
5780                          uint16_t vlan_id)
5781 {
5782         uint32_t vid_idx, vid_bit;
5783
5784         if (vlan_id > ETH_VLAN_ID_MAX)
5785                 return 0;
5786
5787         vid_idx = I40E_VFTA_IDX(vlan_id);
5788         vid_bit = I40E_VFTA_BIT(vlan_id);
5789
5790         if (vsi->vfta[vid_idx] & vid_bit)
5791                 return 1;
5792         else
5793                 return 0;
5794 }
5795
5796 static void
5797 i40e_set_vlan_filter(struct i40e_vsi *vsi,
5798                          uint16_t vlan_id, bool on)
5799 {
5800         uint32_t vid_idx, vid_bit;
5801
5802         if (vlan_id > ETH_VLAN_ID_MAX)
5803                 return;
5804
5805         vid_idx = I40E_VFTA_IDX(vlan_id);
5806         vid_bit = I40E_VFTA_BIT(vlan_id);
5807
5808         if (on)
5809                 vsi->vfta[vid_idx] |= vid_bit;
5810         else
5811                 vsi->vfta[vid_idx] &= ~vid_bit;
5812 }
5813
5814 /**
5815  * Find all vlan options for specific mac addr,
5816  * return with actual vlan found.
5817  */
5818 static inline int
5819 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
5820                            struct i40e_macvlan_filter *mv_f,
5821                            int num, struct ether_addr *addr)
5822 {
5823         int i;
5824         uint32_t j, k;
5825
5826         /**
5827          * Not to use i40e_find_vlan_filter to decrease the loop time,
5828          * although the code looks complex.
5829           */
5830         if (num < vsi->vlan_num)
5831                 return I40E_ERR_PARAM;
5832
5833         i = 0;
5834         for (j = 0; j < I40E_VFTA_SIZE; j++) {
5835                 if (vsi->vfta[j]) {
5836                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
5837                                 if (vsi->vfta[j] & (1 << k)) {
5838                                         if (i > num - 1) {
5839                                                 PMD_DRV_LOG(ERR, "vlan number "
5840                                                             "not match");
5841                                                 return I40E_ERR_PARAM;
5842                                         }
5843                                         (void)rte_memcpy(&mv_f[i].macaddr,
5844                                                         addr, ETH_ADDR_LEN);
5845                                         mv_f[i].vlan_id =
5846                                                 j * I40E_UINT32_BIT_SIZE + k;
5847                                         i++;
5848                                 }
5849                         }
5850                 }
5851         }
5852         return I40E_SUCCESS;
5853 }
5854
5855 static inline int
5856 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
5857                            struct i40e_macvlan_filter *mv_f,
5858                            int num,
5859                            uint16_t vlan)
5860 {
5861         int i = 0;
5862         struct i40e_mac_filter *f;
5863
5864         if (num < vsi->mac_num)
5865                 return I40E_ERR_PARAM;
5866
5867         TAILQ_FOREACH(f, &vsi->mac_list, next) {
5868                 if (i > num - 1) {
5869                         PMD_DRV_LOG(ERR, "buffer number not match");
5870                         return I40E_ERR_PARAM;
5871                 }
5872                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
5873                                 ETH_ADDR_LEN);
5874                 mv_f[i].vlan_id = vlan;
5875                 mv_f[i].filter_type = f->mac_info.filter_type;
5876                 i++;
5877         }
5878
5879         return I40E_SUCCESS;
5880 }
5881
5882 static int
5883 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
5884 {
5885         int i, num;
5886         struct i40e_mac_filter *f;
5887         struct i40e_macvlan_filter *mv_f;
5888         int ret = I40E_SUCCESS;
5889
5890         if (vsi == NULL || vsi->mac_num == 0)
5891                 return I40E_ERR_PARAM;
5892
5893         /* Case that no vlan is set */
5894         if (vsi->vlan_num == 0)
5895                 num = vsi->mac_num;
5896         else
5897                 num = vsi->mac_num * vsi->vlan_num;
5898
5899         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
5900         if (mv_f == NULL) {
5901                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5902                 return I40E_ERR_NO_MEMORY;
5903         }
5904
5905         i = 0;
5906         if (vsi->vlan_num == 0) {
5907                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5908                         (void)rte_memcpy(&mv_f[i].macaddr,
5909                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
5910                         mv_f[i].vlan_id = 0;
5911                         i++;
5912                 }
5913         } else {
5914                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
5915                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
5916                                         vsi->vlan_num, &f->mac_info.mac_addr);
5917                         if (ret != I40E_SUCCESS)
5918                                 goto DONE;
5919                         i += vsi->vlan_num;
5920                 }
5921         }
5922
5923         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
5924 DONE:
5925         rte_free(mv_f);
5926
5927         return ret;
5928 }
5929
5930 int
5931 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5932 {
5933         struct i40e_macvlan_filter *mv_f;
5934         int mac_num;
5935         int ret = I40E_SUCCESS;
5936
5937         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
5938                 return I40E_ERR_PARAM;
5939
5940         /* If it's already set, just return */
5941         if (i40e_find_vlan_filter(vsi,vlan))
5942                 return I40E_SUCCESS;
5943
5944         mac_num = vsi->mac_num;
5945
5946         if (mac_num == 0) {
5947                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5948                 return I40E_ERR_PARAM;
5949         }
5950
5951         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
5952
5953         if (mv_f == NULL) {
5954                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5955                 return I40E_ERR_NO_MEMORY;
5956         }
5957
5958         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
5959
5960         if (ret != I40E_SUCCESS)
5961                 goto DONE;
5962
5963         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
5964
5965         if (ret != I40E_SUCCESS)
5966                 goto DONE;
5967
5968         i40e_set_vlan_filter(vsi, vlan, 1);
5969
5970         vsi->vlan_num++;
5971         ret = I40E_SUCCESS;
5972 DONE:
5973         rte_free(mv_f);
5974         return ret;
5975 }
5976
5977 int
5978 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
5979 {
5980         struct i40e_macvlan_filter *mv_f;
5981         int mac_num;
5982         int ret = I40E_SUCCESS;
5983
5984         /**
5985          * Vlan 0 is the generic filter for untagged packets
5986          * and can't be removed.
5987          */
5988         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
5989                 return I40E_ERR_PARAM;
5990
5991         /* If can't find it, just return */
5992         if (!i40e_find_vlan_filter(vsi, vlan))
5993                 return I40E_ERR_PARAM;
5994
5995         mac_num = vsi->mac_num;
5996
5997         if (mac_num == 0) {
5998                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
5999                 return I40E_ERR_PARAM;
6000         }
6001
6002         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6003
6004         if (mv_f == NULL) {
6005                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6006                 return I40E_ERR_NO_MEMORY;
6007         }
6008
6009         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6010
6011         if (ret != I40E_SUCCESS)
6012                 goto DONE;
6013
6014         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6015
6016         if (ret != I40E_SUCCESS)
6017                 goto DONE;
6018
6019         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6020         if (vsi->vlan_num == 1) {
6021                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6022                 if (ret != I40E_SUCCESS)
6023                         goto DONE;
6024
6025                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6026                 if (ret != I40E_SUCCESS)
6027                         goto DONE;
6028         }
6029
6030         i40e_set_vlan_filter(vsi, vlan, 0);
6031
6032         vsi->vlan_num--;
6033         ret = I40E_SUCCESS;
6034 DONE:
6035         rte_free(mv_f);
6036         return ret;
6037 }
6038
6039 int
6040 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6041 {
6042         struct i40e_mac_filter *f;
6043         struct i40e_macvlan_filter *mv_f;
6044         int i, vlan_num = 0;
6045         int ret = I40E_SUCCESS;
6046
6047         /* If it's add and we've config it, return */
6048         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6049         if (f != NULL)
6050                 return I40E_SUCCESS;
6051         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6052                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6053
6054                 /**
6055                  * If vlan_num is 0, that's the first time to add mac,
6056                  * set mask for vlan_id 0.
6057                  */
6058                 if (vsi->vlan_num == 0) {
6059                         i40e_set_vlan_filter(vsi, 0, 1);
6060                         vsi->vlan_num = 1;
6061                 }
6062                 vlan_num = vsi->vlan_num;
6063         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6064                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6065                 vlan_num = 1;
6066
6067         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6068         if (mv_f == NULL) {
6069                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6070                 return I40E_ERR_NO_MEMORY;
6071         }
6072
6073         for (i = 0; i < vlan_num; i++) {
6074                 mv_f[i].filter_type = mac_filter->filter_type;
6075                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6076                                 ETH_ADDR_LEN);
6077         }
6078
6079         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6080                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6081                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6082                                         &mac_filter->mac_addr);
6083                 if (ret != I40E_SUCCESS)
6084                         goto DONE;
6085         }
6086
6087         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6088         if (ret != I40E_SUCCESS)
6089                 goto DONE;
6090
6091         /* Add the mac addr into mac list */
6092         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6093         if (f == NULL) {
6094                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6095                 ret = I40E_ERR_NO_MEMORY;
6096                 goto DONE;
6097         }
6098         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6099                         ETH_ADDR_LEN);
6100         f->mac_info.filter_type = mac_filter->filter_type;
6101         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6102         vsi->mac_num++;
6103
6104         ret = I40E_SUCCESS;
6105 DONE:
6106         rte_free(mv_f);
6107
6108         return ret;
6109 }
6110
6111 int
6112 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6113 {
6114         struct i40e_mac_filter *f;
6115         struct i40e_macvlan_filter *mv_f;
6116         int i, vlan_num;
6117         enum rte_mac_filter_type filter_type;
6118         int ret = I40E_SUCCESS;
6119
6120         /* Can't find it, return an error */
6121         f = i40e_find_mac_filter(vsi, addr);
6122         if (f == NULL)
6123                 return I40E_ERR_PARAM;
6124
6125         vlan_num = vsi->vlan_num;
6126         filter_type = f->mac_info.filter_type;
6127         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6128                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6129                 if (vlan_num == 0) {
6130                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
6131                         return I40E_ERR_PARAM;
6132                 }
6133         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6134                         filter_type == RTE_MAC_HASH_MATCH)
6135                 vlan_num = 1;
6136
6137         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6138         if (mv_f == NULL) {
6139                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6140                 return I40E_ERR_NO_MEMORY;
6141         }
6142
6143         for (i = 0; i < vlan_num; i++) {
6144                 mv_f[i].filter_type = filter_type;
6145                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6146                                 ETH_ADDR_LEN);
6147         }
6148         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6149                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6150                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6151                 if (ret != I40E_SUCCESS)
6152                         goto DONE;
6153         }
6154
6155         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6156         if (ret != I40E_SUCCESS)
6157                 goto DONE;
6158
6159         /* Remove the mac addr into mac list */
6160         TAILQ_REMOVE(&vsi->mac_list, f, next);
6161         rte_free(f);
6162         vsi->mac_num--;
6163
6164         ret = I40E_SUCCESS;
6165 DONE:
6166         rte_free(mv_f);
6167         return ret;
6168 }
6169
6170 /* Configure hash enable flags for RSS */
6171 uint64_t
6172 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6173 {
6174         uint64_t hena = 0;
6175
6176         if (!flags)
6177                 return hena;
6178
6179         if (flags & ETH_RSS_FRAG_IPV4)
6180                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6181         if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6182                 if (type == I40E_MAC_X722) {
6183                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6184                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6185                 } else
6186                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6187         }
6188         if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6189                 if (type == I40E_MAC_X722) {
6190                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6191                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6192                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6193                 } else
6194                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6195         }
6196         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6197                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6198         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6199                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6200         if (flags & ETH_RSS_FRAG_IPV6)
6201                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6202         if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6203                 if (type == I40E_MAC_X722) {
6204                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6205                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6206                 } else
6207                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6208         }
6209         if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6210                 if (type == I40E_MAC_X722) {
6211                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6212                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6213                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6214                 } else
6215                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6216         }
6217         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6218                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6219         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6220                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6221         if (flags & ETH_RSS_L2_PAYLOAD)
6222                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6223
6224         return hena;
6225 }
6226
6227 /* Parse the hash enable flags */
6228 uint64_t
6229 i40e_parse_hena(uint64_t flags)
6230 {
6231         uint64_t rss_hf = 0;
6232
6233         if (!flags)
6234                 return rss_hf;
6235         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6236                 rss_hf |= ETH_RSS_FRAG_IPV4;
6237         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6238                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6239 #ifdef X722_SUPPORT
6240         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6241                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6242 #endif
6243         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6244                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6245 #ifdef X722_SUPPORT
6246         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6247                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6248         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6249                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6250 #endif
6251         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6252                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6253         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6254                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6255         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6256                 rss_hf |= ETH_RSS_FRAG_IPV6;
6257         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6258                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6259 #ifdef X722_SUPPORT
6260         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6261                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6262 #endif
6263         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6264                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6265 #ifdef X722_SUPPORT
6266         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6267                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6268         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6269                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6270 #endif
6271         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6272                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6273         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6274                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6275         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6276                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6277
6278         return rss_hf;
6279 }
6280
6281 /* Disable RSS */
6282 static void
6283 i40e_pf_disable_rss(struct i40e_pf *pf)
6284 {
6285         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6286         uint64_t hena;
6287
6288         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6289         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6290         if (hw->mac.type == I40E_MAC_X722)
6291                 hena &= ~I40E_RSS_HENA_ALL_X722;
6292         else
6293                 hena &= ~I40E_RSS_HENA_ALL;
6294         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6295         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6296         I40E_WRITE_FLUSH(hw);
6297 }
6298
6299 static int
6300 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6301 {
6302         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6303         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6304         int ret = 0;
6305
6306         if (!key || key_len == 0) {
6307                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6308                 return 0;
6309         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6310                 sizeof(uint32_t)) {
6311                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6312                 return -EINVAL;
6313         }
6314
6315         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6316                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6317                         (struct i40e_aqc_get_set_rss_key_data *)key;
6318
6319                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6320                 if (ret)
6321                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
6322                                      "via AQ");
6323         } else {
6324                 uint32_t *hash_key = (uint32_t *)key;
6325                 uint16_t i;
6326
6327                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6328                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6329                 I40E_WRITE_FLUSH(hw);
6330         }
6331
6332         return ret;
6333 }
6334
6335 static int
6336 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6337 {
6338         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6339         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6340         int ret;
6341
6342         if (!key || !key_len)
6343                 return -EINVAL;
6344
6345         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6346                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6347                         (struct i40e_aqc_get_set_rss_key_data *)key);
6348                 if (ret) {
6349                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6350                         return ret;
6351                 }
6352         } else {
6353                 uint32_t *key_dw = (uint32_t *)key;
6354                 uint16_t i;
6355
6356                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6357                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6358         }
6359         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6360
6361         return 0;
6362 }
6363
6364 static int
6365 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6366 {
6367         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6368         uint64_t rss_hf;
6369         uint64_t hena;
6370         int ret;
6371
6372         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6373                                rss_conf->rss_key_len);
6374         if (ret)
6375                 return ret;
6376
6377         rss_hf = rss_conf->rss_hf;
6378         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6379         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6380         if (hw->mac.type == I40E_MAC_X722)
6381                 hena &= ~I40E_RSS_HENA_ALL_X722;
6382         else
6383                 hena &= ~I40E_RSS_HENA_ALL;
6384         hena |= i40e_config_hena(rss_hf, hw->mac.type);
6385         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6386         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6387         I40E_WRITE_FLUSH(hw);
6388
6389         return 0;
6390 }
6391
6392 static int
6393 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6394                          struct rte_eth_rss_conf *rss_conf)
6395 {
6396         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6397         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6398         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6399         uint64_t hena;
6400
6401         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6402         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6403         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6404                  ? I40E_RSS_HENA_ALL_X722
6405                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6406                 if (rss_hf != 0) /* Enable RSS */
6407                         return -EINVAL;
6408                 return 0; /* Nothing to do */
6409         }
6410         /* RSS enabled */
6411         if (rss_hf == 0) /* Disable RSS */
6412                 return -EINVAL;
6413
6414         return i40e_hw_rss_hash_set(pf, rss_conf);
6415 }
6416
6417 static int
6418 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6419                            struct rte_eth_rss_conf *rss_conf)
6420 {
6421         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6422         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6423         uint64_t hena;
6424
6425         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6426                          &rss_conf->rss_key_len);
6427
6428         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6429         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6430         rss_conf->rss_hf = i40e_parse_hena(hena);
6431
6432         return 0;
6433 }
6434
6435 static int
6436 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6437 {
6438         switch (filter_type) {
6439         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6440                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6441                 break;
6442         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6443                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6444                 break;
6445         case RTE_TUNNEL_FILTER_IMAC_TENID:
6446                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6447                 break;
6448         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6449                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6450                 break;
6451         case ETH_TUNNEL_FILTER_IMAC:
6452                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6453                 break;
6454         case ETH_TUNNEL_FILTER_OIP:
6455                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6456                 break;
6457         case ETH_TUNNEL_FILTER_IIP:
6458                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6459                 break;
6460         default:
6461                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6462                 return -EINVAL;
6463         }
6464
6465         return 0;
6466 }
6467
6468 static int
6469 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6470                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6471                         uint8_t add)
6472 {
6473         uint16_t ip_type;
6474         uint32_t ipv4_addr;
6475         uint8_t i, tun_type = 0;
6476         /* internal varialbe to convert ipv6 byte order */
6477         uint32_t convert_ipv6[4];
6478         int val, ret = 0;
6479         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6480         struct i40e_vsi *vsi = pf->main_vsi;
6481         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
6482         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
6483
6484         cld_filter = rte_zmalloc("tunnel_filter",
6485                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6486                 0);
6487
6488         if (NULL == cld_filter) {
6489                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6490                 return -EINVAL;
6491         }
6492         pfilter = cld_filter;
6493
6494         ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6495         ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6496
6497         pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6498         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6499                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6500                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6501                 rte_memcpy(&pfilter->ipaddr.v4.data,
6502                                 &rte_cpu_to_le_32(ipv4_addr),
6503                                 sizeof(pfilter->ipaddr.v4.data));
6504         } else {
6505                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6506                 for (i = 0; i < 4; i++) {
6507                         convert_ipv6[i] =
6508                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6509                 }
6510                 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6511                                 sizeof(pfilter->ipaddr.v6.data));
6512         }
6513
6514         /* check tunneled type */
6515         switch (tunnel_filter->tunnel_type) {
6516         case RTE_TUNNEL_TYPE_VXLAN:
6517                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6518                 break;
6519         case RTE_TUNNEL_TYPE_NVGRE:
6520                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6521                 break;
6522         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6523                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6524                 break;
6525         default:
6526                 /* Other tunnel types is not supported. */
6527                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6528                 rte_free(cld_filter);
6529                 return -EINVAL;
6530         }
6531
6532         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6533                                                 &pfilter->flags);
6534         if (val < 0) {
6535                 rte_free(cld_filter);
6536                 return -EINVAL;
6537         }
6538
6539         pfilter->flags |= rte_cpu_to_le_16(
6540                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6541                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6542         pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6543         pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6544
6545         if (add)
6546                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6547         else
6548                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6549                                                 cld_filter, 1);
6550
6551         rte_free(cld_filter);
6552         return ret;
6553 }
6554
6555 static int
6556 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6557 {
6558         uint8_t i;
6559
6560         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6561                 if (pf->vxlan_ports[i] == port)
6562                         return i;
6563         }
6564
6565         return -1;
6566 }
6567
6568 static int
6569 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6570 {
6571         int  idx, ret;
6572         uint8_t filter_idx;
6573         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6574
6575         idx = i40e_get_vxlan_port_idx(pf, port);
6576
6577         /* Check if port already exists */
6578         if (idx >= 0) {
6579                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6580                 return -EINVAL;
6581         }
6582
6583         /* Now check if there is space to add the new port */
6584         idx = i40e_get_vxlan_port_idx(pf, 0);
6585         if (idx < 0) {
6586                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6587                         "not adding port %d", port);
6588                 return -ENOSPC;
6589         }
6590
6591         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6592                                         &filter_idx, NULL);
6593         if (ret < 0) {
6594                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6595                 return -1;
6596         }
6597
6598         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6599                          port,  filter_idx);
6600
6601         /* New port: add it and mark its index in the bitmap */
6602         pf->vxlan_ports[idx] = port;
6603         pf->vxlan_bitmap |= (1 << idx);
6604
6605         if (!(pf->flags & I40E_FLAG_VXLAN))
6606                 pf->flags |= I40E_FLAG_VXLAN;
6607
6608         return 0;
6609 }
6610
6611 static int
6612 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6613 {
6614         int idx;
6615         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6616
6617         if (!(pf->flags & I40E_FLAG_VXLAN)) {
6618                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6619                 return -EINVAL;
6620         }
6621
6622         idx = i40e_get_vxlan_port_idx(pf, port);
6623
6624         if (idx < 0) {
6625                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6626                 return -EINVAL;
6627         }
6628
6629         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6630                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6631                 return -1;
6632         }
6633
6634         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6635                         port, idx);
6636
6637         pf->vxlan_ports[idx] = 0;
6638         pf->vxlan_bitmap &= ~(1 << idx);
6639
6640         if (!pf->vxlan_bitmap)
6641                 pf->flags &= ~I40E_FLAG_VXLAN;
6642
6643         return 0;
6644 }
6645
6646 /* Add UDP tunneling port */
6647 static int
6648 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6649                              struct rte_eth_udp_tunnel *udp_tunnel)
6650 {
6651         int ret = 0;
6652         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6653
6654         if (udp_tunnel == NULL)
6655                 return -EINVAL;
6656
6657         switch (udp_tunnel->prot_type) {
6658         case RTE_TUNNEL_TYPE_VXLAN:
6659                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
6660                 break;
6661
6662         case RTE_TUNNEL_TYPE_GENEVE:
6663         case RTE_TUNNEL_TYPE_TEREDO:
6664                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6665                 ret = -1;
6666                 break;
6667
6668         default:
6669                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6670                 ret = -1;
6671                 break;
6672         }
6673
6674         return ret;
6675 }
6676
6677 /* Remove UDP tunneling port */
6678 static int
6679 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
6680                              struct rte_eth_udp_tunnel *udp_tunnel)
6681 {
6682         int ret = 0;
6683         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6684
6685         if (udp_tunnel == NULL)
6686                 return -EINVAL;
6687
6688         switch (udp_tunnel->prot_type) {
6689         case RTE_TUNNEL_TYPE_VXLAN:
6690                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
6691                 break;
6692         case RTE_TUNNEL_TYPE_GENEVE:
6693         case RTE_TUNNEL_TYPE_TEREDO:
6694                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
6695                 ret = -1;
6696                 break;
6697         default:
6698                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
6699                 ret = -1;
6700                 break;
6701         }
6702
6703         return ret;
6704 }
6705
6706 /* Calculate the maximum number of contiguous PF queues that are configured */
6707 static int
6708 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
6709 {
6710         struct rte_eth_dev_data *data = pf->dev_data;
6711         int i, num;
6712         struct i40e_rx_queue *rxq;
6713
6714         num = 0;
6715         for (i = 0; i < pf->lan_nb_qps; i++) {
6716                 rxq = data->rx_queues[i];
6717                 if (rxq && rxq->q_set)
6718                         num++;
6719                 else
6720                         break;
6721         }
6722
6723         return num;
6724 }
6725
6726 /* Configure RSS */
6727 static int
6728 i40e_pf_config_rss(struct i40e_pf *pf)
6729 {
6730         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6731         struct rte_eth_rss_conf rss_conf;
6732         uint32_t i, lut = 0;
6733         uint16_t j, num;
6734
6735         /*
6736          * If both VMDQ and RSS enabled, not all of PF queues are configured.
6737          * It's necessary to calulate the actual PF queues that are configured.
6738          */
6739         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
6740                 num = i40e_pf_calc_configured_queues_num(pf);
6741         else
6742                 num = pf->dev_data->nb_rx_queues;
6743
6744         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
6745         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
6746                         num);
6747
6748         if (num == 0) {
6749                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
6750                 return -ENOTSUP;
6751         }
6752
6753         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
6754                 if (j == num)
6755                         j = 0;
6756                 lut = (lut << 8) | (j & ((0x1 <<
6757                         hw->func_caps.rss_table_entry_width) - 1));
6758                 if ((i & 3) == 3)
6759                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
6760         }
6761
6762         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
6763         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
6764                 i40e_pf_disable_rss(pf);
6765                 return 0;
6766         }
6767         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
6768                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
6769                 /* Random default keys */
6770                 static uint32_t rss_key_default[] = {0x6b793944,
6771                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
6772                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
6773                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
6774
6775                 rss_conf.rss_key = (uint8_t *)rss_key_default;
6776                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6777                                                         sizeof(uint32_t);
6778         }
6779
6780         return i40e_hw_rss_hash_set(pf, &rss_conf);
6781 }
6782
6783 static int
6784 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
6785                                struct rte_eth_tunnel_filter_conf *filter)
6786 {
6787         if (pf == NULL || filter == NULL) {
6788                 PMD_DRV_LOG(ERR, "Invalid parameter");
6789                 return -EINVAL;
6790         }
6791
6792         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
6793                 PMD_DRV_LOG(ERR, "Invalid queue ID");
6794                 return -EINVAL;
6795         }
6796
6797         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
6798                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
6799                 return -EINVAL;
6800         }
6801
6802         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
6803                 (is_zero_ether_addr(&filter->outer_mac))) {
6804                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
6805                 return -EINVAL;
6806         }
6807
6808         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
6809                 (is_zero_ether_addr(&filter->inner_mac))) {
6810                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
6811                 return -EINVAL;
6812         }
6813
6814         return 0;
6815 }
6816
6817 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
6818 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
6819 static int
6820 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
6821 {
6822         uint32_t val, reg;
6823         int ret = -EINVAL;
6824
6825         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
6826         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
6827
6828         if (len == 3) {
6829                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
6830         } else if (len == 4) {
6831                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
6832         } else {
6833                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
6834                 return ret;
6835         }
6836
6837         if (reg != val) {
6838                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
6839                                                    reg, NULL);
6840                 if (ret != 0)
6841                         return ret;
6842         } else {
6843                 ret = 0;
6844         }
6845         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
6846                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
6847
6848         return ret;
6849 }
6850
6851 static int
6852 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
6853 {
6854         int ret = -EINVAL;
6855
6856         if (!hw || !cfg)
6857                 return -EINVAL;
6858
6859         switch (cfg->cfg_type) {
6860         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
6861                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
6862                 break;
6863         default:
6864                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
6865                 break;
6866         }
6867
6868         return ret;
6869 }
6870
6871 static int
6872 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
6873                                enum rte_filter_op filter_op,
6874                                void *arg)
6875 {
6876         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6877         int ret = I40E_ERR_PARAM;
6878
6879         switch (filter_op) {
6880         case RTE_ETH_FILTER_SET:
6881                 ret = i40e_dev_global_config_set(hw,
6882                         (struct rte_eth_global_cfg *)arg);
6883                 break;
6884         default:
6885                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6886                 break;
6887         }
6888
6889         return ret;
6890 }
6891
6892 static int
6893 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
6894                           enum rte_filter_op filter_op,
6895                           void *arg)
6896 {
6897         struct rte_eth_tunnel_filter_conf *filter;
6898         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6899         int ret = I40E_SUCCESS;
6900
6901         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
6902
6903         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
6904                 return I40E_ERR_PARAM;
6905
6906         switch (filter_op) {
6907         case RTE_ETH_FILTER_NOP:
6908                 if (!(pf->flags & I40E_FLAG_VXLAN))
6909                         ret = I40E_NOT_SUPPORTED;
6910                 break;
6911         case RTE_ETH_FILTER_ADD:
6912                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
6913                 break;
6914         case RTE_ETH_FILTER_DELETE:
6915                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
6916                 break;
6917         default:
6918                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
6919                 ret = I40E_ERR_PARAM;
6920                 break;
6921         }
6922
6923         return ret;
6924 }
6925
6926 static int
6927 i40e_pf_config_mq_rx(struct i40e_pf *pf)
6928 {
6929         int ret = 0;
6930         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
6931
6932         /* RSS setup */
6933         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
6934                 ret = i40e_pf_config_rss(pf);
6935         else
6936                 i40e_pf_disable_rss(pf);
6937
6938         return ret;
6939 }
6940
6941 /* Get the symmetric hash enable configurations per port */
6942 static void
6943 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
6944 {
6945         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6946
6947         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
6948 }
6949
6950 /* Set the symmetric hash enable configurations per port */
6951 static void
6952 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
6953 {
6954         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
6955
6956         if (enable > 0) {
6957                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
6958                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6959                                                         "been enabled");
6960                         return;
6961                 }
6962                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6963         } else {
6964                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
6965                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
6966                                                         "been disabled");
6967                         return;
6968                 }
6969                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
6970         }
6971         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
6972         I40E_WRITE_FLUSH(hw);
6973 }
6974
6975 /*
6976  * Get global configurations of hash function type and symmetric hash enable
6977  * per flow type (pctype). Note that global configuration means it affects all
6978  * the ports on the same NIC.
6979  */
6980 static int
6981 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
6982                                    struct rte_eth_hash_global_conf *g_cfg)
6983 {
6984         uint32_t reg, mask = I40E_FLOW_TYPES;
6985         uint16_t i;
6986         enum i40e_filter_pctype pctype;
6987
6988         memset(g_cfg, 0, sizeof(*g_cfg));
6989         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
6990         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
6991                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
6992         else
6993                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
6994         PMD_DRV_LOG(DEBUG, "Hash function is %s",
6995                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
6996
6997         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
6998                 if (!(mask & (1UL << i)))
6999                         continue;
7000                 mask &= ~(1UL << i);
7001                 /* Bit set indicats the coresponding flow type is supported */
7002                 g_cfg->valid_bit_mask[0] |= (1UL << i);
7003                 /* if flowtype is invalid, continue */
7004                 if (!I40E_VALID_FLOW(i))
7005                         continue;
7006                 pctype = i40e_flowtype_to_pctype(i);
7007                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7008                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7009                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7010         }
7011
7012         return 0;
7013 }
7014
7015 static int
7016 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7017 {
7018         uint32_t i;
7019         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7020
7021         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7022                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7023                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7024                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7025                                                 g_cfg->hash_func);
7026                 return -EINVAL;
7027         }
7028
7029         /*
7030          * As i40e supports less than 32 flow types, only first 32 bits need to
7031          * be checked.
7032          */
7033         mask0 = g_cfg->valid_bit_mask[0];
7034         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7035                 if (i == 0) {
7036                         /* Check if any unsupported flow type configured */
7037                         if ((mask0 | i40e_mask) ^ i40e_mask)
7038                                 goto mask_err;
7039                 } else {
7040                         if (g_cfg->valid_bit_mask[i])
7041                                 goto mask_err;
7042                 }
7043         }
7044
7045         return 0;
7046
7047 mask_err:
7048         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7049
7050         return -EINVAL;
7051 }
7052
7053 /*
7054  * Set global configurations of hash function type and symmetric hash enable
7055  * per flow type (pctype). Note any modifying global configuration will affect
7056  * all the ports on the same NIC.
7057  */
7058 static int
7059 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7060                                    struct rte_eth_hash_global_conf *g_cfg)
7061 {
7062         int ret;
7063         uint16_t i;
7064         uint32_t reg;
7065         uint32_t mask0 = g_cfg->valid_bit_mask[0];
7066         enum i40e_filter_pctype pctype;
7067
7068         /* Check the input parameters */
7069         ret = i40e_hash_global_config_check(g_cfg);
7070         if (ret < 0)
7071                 return ret;
7072
7073         for (i = 0; mask0 && i < UINT32_BIT; i++) {
7074                 if (!(mask0 & (1UL << i)))
7075                         continue;
7076                 mask0 &= ~(1UL << i);
7077                 /* if flowtype is invalid, continue */
7078                 if (!I40E_VALID_FLOW(i))
7079                         continue;
7080                 pctype = i40e_flowtype_to_pctype(i);
7081                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7082                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7083                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7084         }
7085
7086         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7087         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7088                 /* Toeplitz */
7089                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7090                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7091                                                                 "Toeplitz");
7092                         goto out;
7093                 }
7094                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7095         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7096                 /* Simple XOR */
7097                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7098                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7099                                                         "Simple XOR");
7100                         goto out;
7101                 }
7102                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7103         } else
7104                 /* Use the default, and keep it as it is */
7105                 goto out;
7106
7107         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7108
7109 out:
7110         I40E_WRITE_FLUSH(hw);
7111
7112         return 0;
7113 }
7114
7115 /**
7116  * Valid input sets for hash and flow director filters per PCTYPE
7117  */
7118 static uint64_t
7119 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7120                 enum rte_filter_type filter)
7121 {
7122         uint64_t valid;
7123
7124         static const uint64_t valid_hash_inset_table[] = {
7125                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7126                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7127                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7128                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7129                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7130                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7131                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7132                         I40E_INSET_FLEX_PAYLOAD,
7133                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7134                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7135                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7136                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7137                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7138                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7139                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7140                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7141                         I40E_INSET_FLEX_PAYLOAD,
7142 #ifdef X722_SUPPORT
7143                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7144                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7145                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7146                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7147                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7148                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7149                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7150                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7151                         I40E_INSET_FLEX_PAYLOAD,
7152                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7153                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7154                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7155                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7156                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7157                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7158                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7159                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7160                         I40E_INSET_FLEX_PAYLOAD,
7161 #endif
7162                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7163                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7164                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7165                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7166                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7167                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7168                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7169                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7170                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7171 #ifdef X722_SUPPORT
7172                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7173                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7174                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7175                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7176                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7177                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7178                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7179                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7180                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7181 #endif
7182                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7183                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7184                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7185                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7186                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7187                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7188                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7189                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7190                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7191                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7192                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7193                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7194                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7195                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7196                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7197                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7198                         I40E_INSET_FLEX_PAYLOAD,
7199                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7200                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7201                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7202                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7203                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7204                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7205                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7206                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7207                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7208                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7209                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7210                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7211                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7212                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7213                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7214                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7215 #ifdef X722_SUPPORT
7216                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7217                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7218                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7219                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7220                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7221                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7222                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7223                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7224                         I40E_INSET_FLEX_PAYLOAD,
7225                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7226                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7227                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7228                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7229                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7230                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7231                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7232                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7233                         I40E_INSET_FLEX_PAYLOAD,
7234 #endif
7235                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7236                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7237                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7238                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7239                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7240                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7241                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7242                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7243                         I40E_INSET_FLEX_PAYLOAD,
7244 #ifdef X722_SUPPORT
7245                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7246                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7247                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7248                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7249                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7250                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7251                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7252                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7253                         I40E_INSET_FLEX_PAYLOAD,
7254 #endif
7255                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7256                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7257                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7258                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7259                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7260                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7261                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7262                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7263                         I40E_INSET_FLEX_PAYLOAD,
7264                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7265                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7266                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7267                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7268                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7269                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7270                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7271                         I40E_INSET_FLEX_PAYLOAD,
7272                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7273                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7274                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7275                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7276                         I40E_INSET_FLEX_PAYLOAD,
7277         };
7278
7279         /**
7280          * Flow director supports only fields defined in
7281          * union rte_eth_fdir_flow.
7282          */
7283         static const uint64_t valid_fdir_inset_table[] = {
7284                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7285                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7286                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7287                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7288                 I40E_INSET_IPV4_TTL,
7289                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7290                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7291                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7292                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7293                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7294 #ifdef X722_SUPPORT
7295                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7296                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7297                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7298                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7299                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7300                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7301                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7302                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7303                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7304                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7305 #endif
7306                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7307                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7308                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7309                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7310                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7311 #ifdef X722_SUPPORT
7312                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7313                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7314                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7315                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7316                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7317 #endif
7318                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7319                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7320                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7321                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7322                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7323                 I40E_INSET_SCTP_VT,
7324                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7325                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7326                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7327                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7328                 I40E_INSET_IPV4_TTL,
7329                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7330                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7331                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7332                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7333                 I40E_INSET_IPV6_HOP_LIMIT,
7334                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7335                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7336                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7337                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7338                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7339 #ifdef X722_SUPPORT
7340                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7341                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7342                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7343                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7344                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7345                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7346                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7347                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7348                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7349                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7350 #endif
7351                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7352                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7353                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7354                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7355                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7356 #ifdef X722_SUPPORT
7357                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7358                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7359                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7360                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7361                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7362 #endif
7363                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7364                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7365                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7366                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7367                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7368                 I40E_INSET_SCTP_VT,
7369                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7370                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7371                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7372                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7373                 I40E_INSET_IPV6_HOP_LIMIT,
7374                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7375                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7376                 I40E_INSET_LAST_ETHER_TYPE,
7377         };
7378
7379         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7380                 return 0;
7381         if (filter == RTE_ETH_FILTER_HASH)
7382                 valid = valid_hash_inset_table[pctype];
7383         else
7384                 valid = valid_fdir_inset_table[pctype];
7385
7386         return valid;
7387 }
7388
7389 /**
7390  * Validate if the input set is allowed for a specific PCTYPE
7391  */
7392 static int
7393 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7394                 enum rte_filter_type filter, uint64_t inset)
7395 {
7396         uint64_t valid;
7397
7398         valid = i40e_get_valid_input_set(pctype, filter);
7399         if (inset & (~valid))
7400                 return -EINVAL;
7401
7402         return 0;
7403 }
7404
7405 /* default input set fields combination per pctype */
7406 static uint64_t
7407 i40e_get_default_input_set(uint16_t pctype)
7408 {
7409         static const uint64_t default_inset_table[] = {
7410                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7411                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7412                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7413                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7414                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7415 #ifdef X722_SUPPORT
7416                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7417                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7418                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7419                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7420                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7421                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7422 #endif
7423                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7424                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7425                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7426 #ifdef X722_SUPPORT
7427                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7428                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7429                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7430 #endif
7431                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7432                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7433                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7434                         I40E_INSET_SCTP_VT,
7435                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7436                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7437                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7438                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7439                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7440                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7441                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7442 #ifdef X722_SUPPORT
7443                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7444                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7445                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7446                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7447                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7448                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7449 #endif
7450                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7451                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7452                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7453 #ifdef X722_SUPPORT
7454                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7455                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7456                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7457 #endif
7458                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7459                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7460                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7461                         I40E_INSET_SCTP_VT,
7462                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7463                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7464                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7465                         I40E_INSET_LAST_ETHER_TYPE,
7466         };
7467
7468         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7469                 return 0;
7470
7471         return default_inset_table[pctype];
7472 }
7473
7474 /**
7475  * Parse the input set from index to logical bit masks
7476  */
7477 static int
7478 i40e_parse_input_set(uint64_t *inset,
7479                      enum i40e_filter_pctype pctype,
7480                      enum rte_eth_input_set_field *field,
7481                      uint16_t size)
7482 {
7483         uint16_t i, j;
7484         int ret = -EINVAL;
7485
7486         static const struct {
7487                 enum rte_eth_input_set_field field;
7488                 uint64_t inset;
7489         } inset_convert_table[] = {
7490                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7491                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7492                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7493                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7494                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7495                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7496                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7497                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7498                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7499                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7500                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7501                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7502                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7503                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7504                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7505                         I40E_INSET_IPV6_NEXT_HDR},
7506                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7507                         I40E_INSET_IPV6_HOP_LIMIT},
7508                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7509                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7510                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7511                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7512                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7513                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7514                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7515                         I40E_INSET_SCTP_VT},
7516                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7517                         I40E_INSET_TUNNEL_DMAC},
7518                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7519                         I40E_INSET_VLAN_TUNNEL},
7520                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7521                         I40E_INSET_TUNNEL_ID},
7522                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7523                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7524                         I40E_INSET_FLEX_PAYLOAD_W1},
7525                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7526                         I40E_INSET_FLEX_PAYLOAD_W2},
7527                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7528                         I40E_INSET_FLEX_PAYLOAD_W3},
7529                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7530                         I40E_INSET_FLEX_PAYLOAD_W4},
7531                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7532                         I40E_INSET_FLEX_PAYLOAD_W5},
7533                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7534                         I40E_INSET_FLEX_PAYLOAD_W6},
7535                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7536                         I40E_INSET_FLEX_PAYLOAD_W7},
7537                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7538                         I40E_INSET_FLEX_PAYLOAD_W8},
7539         };
7540
7541         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7542                 return ret;
7543
7544         /* Only one item allowed for default or all */
7545         if (size == 1) {
7546                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7547                         *inset = i40e_get_default_input_set(pctype);
7548                         return 0;
7549                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7550                         *inset = I40E_INSET_NONE;
7551                         return 0;
7552                 }
7553         }
7554
7555         for (i = 0, *inset = 0; i < size; i++) {
7556                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7557                         if (field[i] == inset_convert_table[j].field) {
7558                                 *inset |= inset_convert_table[j].inset;
7559                                 break;
7560                         }
7561                 }
7562
7563                 /* It contains unsupported input set, return immediately */
7564                 if (j == RTE_DIM(inset_convert_table))
7565                         return ret;
7566         }
7567
7568         return 0;
7569 }
7570
7571 /**
7572  * Translate the input set from bit masks to register aware bit masks
7573  * and vice versa
7574  */
7575 static uint64_t
7576 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
7577 {
7578         uint64_t val = 0;
7579         uint16_t i;
7580
7581         struct inset_map {
7582                 uint64_t inset;
7583                 uint64_t inset_reg;
7584         };
7585
7586         static const struct inset_map inset_map_common[] = {
7587                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7588                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7589                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7590                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7591                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7592                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7593                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7594                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7595                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7596                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7597                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7598                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7599                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7600                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7601                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7602                 {I40E_INSET_TUNNEL_DMAC,
7603                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7604                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7605                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7606                 {I40E_INSET_TUNNEL_SRC_PORT,
7607                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7608                 {I40E_INSET_TUNNEL_DST_PORT,
7609                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7610                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7611                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7612                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7613                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7614                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7615                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7616                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7617                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7618                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7619         };
7620
7621     /* some different registers map in x722*/
7622         static const struct inset_map inset_map_diff_x722[] = {
7623                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
7624                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
7625                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
7626                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
7627         };
7628
7629         static const struct inset_map inset_map_diff_not_x722[] = {
7630                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7631                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7632                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7633                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7634         };
7635
7636         if (input == 0)
7637                 return val;
7638
7639         /* Translate input set to register aware inset */
7640         if (type == I40E_MAC_X722) {
7641                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
7642                         if (input & inset_map_diff_x722[i].inset)
7643                                 val |= inset_map_diff_x722[i].inset_reg;
7644                 }
7645         } else {
7646                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
7647                         if (input & inset_map_diff_not_x722[i].inset)
7648                                 val |= inset_map_diff_not_x722[i].inset_reg;
7649                 }
7650         }
7651
7652         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
7653                 if (input & inset_map_common[i].inset)
7654                         val |= inset_map_common[i].inset_reg;
7655         }
7656
7657         return val;
7658 }
7659
7660 static int
7661 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7662 {
7663         uint8_t i, idx = 0;
7664         uint64_t inset_need_mask = inset;
7665
7666         static const struct {
7667                 uint64_t inset;
7668                 uint32_t mask;
7669         } inset_mask_map[] = {
7670                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7671                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7672                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7673                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7674                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7675                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7676                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7677                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
7678         };
7679
7680         if (!inset || !mask || !nb_elem)
7681                 return 0;
7682
7683         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7684                 /* Clear the inset bit, if no MASK is required,
7685                  * for example proto + ttl
7686                  */
7687                 if ((inset & inset_mask_map[i].inset) ==
7688                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
7689                         inset_need_mask &= ~inset_mask_map[i].inset;
7690                 if (!inset_need_mask)
7691                         return 0;
7692         }
7693         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
7694                 if ((inset_need_mask & inset_mask_map[i].inset) ==
7695                     inset_mask_map[i].inset) {
7696                         if (idx >= nb_elem) {
7697                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
7698                                 return -EINVAL;
7699                         }
7700                         mask[idx] = inset_mask_map[i].mask;
7701                         idx++;
7702                 }
7703         }
7704
7705         return idx;
7706 }
7707
7708 static void
7709 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
7710 {
7711         uint32_t reg = i40e_read_rx_ctl(hw, addr);
7712
7713         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
7714         if (reg != val)
7715                 i40e_write_rx_ctl(hw, addr, val);
7716         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
7717                     (uint32_t)i40e_read_rx_ctl(hw, addr));
7718 }
7719
7720 static void
7721 i40e_filter_input_set_init(struct i40e_pf *pf)
7722 {
7723         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7724         enum i40e_filter_pctype pctype;
7725         uint64_t input_set, inset_reg;
7726         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7727         int num, i;
7728
7729         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
7730              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
7731                 if (hw->mac.type == I40E_MAC_X722) {
7732                         if (!I40E_VALID_PCTYPE_X722(pctype))
7733                                 continue;
7734                 } else {
7735                         if (!I40E_VALID_PCTYPE(pctype))
7736                                 continue;
7737                 }
7738
7739                 input_set = i40e_get_default_input_set(pctype);
7740
7741                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7742                                                    I40E_INSET_MASK_NUM_REG);
7743                 if (num < 0)
7744                         return;
7745                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
7746                                         input_set);
7747
7748                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7749                                       (uint32_t)(inset_reg & UINT32_MAX));
7750                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7751                                      (uint32_t)((inset_reg >>
7752                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7753                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7754                                       (uint32_t)(inset_reg & UINT32_MAX));
7755                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7756                                      (uint32_t)((inset_reg >>
7757                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
7758
7759                 for (i = 0; i < num; i++) {
7760                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7761                                              mask_reg[i]);
7762                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7763                                              mask_reg[i]);
7764                 }
7765                 /*clear unused mask registers of the pctype */
7766                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
7767                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7768                                              0);
7769                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7770                                              0);
7771                 }
7772                 I40E_WRITE_FLUSH(hw);
7773
7774                 /* store the default input set */
7775                 pf->hash_input_set[pctype] = input_set;
7776                 pf->fdir.input_set[pctype] = input_set;
7777         }
7778 }
7779
7780 int
7781 i40e_hash_filter_inset_select(struct i40e_hw *hw,
7782                          struct rte_eth_input_set_conf *conf)
7783 {
7784         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
7785         enum i40e_filter_pctype pctype;
7786         uint64_t input_set, inset_reg = 0;
7787         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7788         int ret, i, num;
7789
7790         if (!conf) {
7791                 PMD_DRV_LOG(ERR, "Invalid pointer");
7792                 return -EFAULT;
7793         }
7794         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7795             conf->op != RTE_ETH_INPUT_SET_ADD) {
7796                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7797                 return -EINVAL;
7798         }
7799
7800         if (!I40E_VALID_FLOW(conf->flow_type)) {
7801                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
7802                 return -EINVAL;
7803         }
7804
7805         if (hw->mac.type == I40E_MAC_X722) {
7806                 /* get translated pctype value in fd pctype register */
7807                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
7808                         I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
7809                         conf->flow_type)));
7810         } else
7811                 pctype = i40e_flowtype_to_pctype(conf->flow_type);
7812
7813         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7814                                    conf->inset_size);
7815         if (ret) {
7816                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7817                 return -EINVAL;
7818         }
7819         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
7820                                     input_set) != 0) {
7821                 PMD_DRV_LOG(ERR, "Invalid input set");
7822                 return -EINVAL;
7823         }
7824         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
7825                 /* get inset value in register */
7826                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
7827                 inset_reg <<= I40E_32_BIT_WIDTH;
7828                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
7829                 input_set |= pf->hash_input_set[pctype];
7830         }
7831         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7832                                            I40E_INSET_MASK_NUM_REG);
7833         if (num < 0)
7834                 return -EINVAL;
7835
7836         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
7837
7838         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
7839                               (uint32_t)(inset_reg & UINT32_MAX));
7840         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
7841                              (uint32_t)((inset_reg >>
7842                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7843
7844         for (i = 0; i < num; i++)
7845                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7846                                      mask_reg[i]);
7847         /*clear unused mask registers of the pctype */
7848         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7849                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
7850                                      0);
7851         I40E_WRITE_FLUSH(hw);
7852
7853         pf->hash_input_set[pctype] = input_set;
7854         return 0;
7855 }
7856
7857 int
7858 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
7859                          struct rte_eth_input_set_conf *conf)
7860 {
7861         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7862         enum i40e_filter_pctype pctype;
7863         uint64_t input_set, inset_reg = 0;
7864         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
7865         int ret, i, num;
7866
7867         if (!hw || !conf) {
7868                 PMD_DRV_LOG(ERR, "Invalid pointer");
7869                 return -EFAULT;
7870         }
7871         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
7872             conf->op != RTE_ETH_INPUT_SET_ADD) {
7873                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
7874                 return -EINVAL;
7875         }
7876
7877         if (!I40E_VALID_FLOW(conf->flow_type)) {
7878                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
7879                 return -EINVAL;
7880         }
7881
7882         pctype = i40e_flowtype_to_pctype(conf->flow_type);
7883
7884         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
7885                                    conf->inset_size);
7886         if (ret) {
7887                 PMD_DRV_LOG(ERR, "Failed to parse input set");
7888                 return -EINVAL;
7889         }
7890         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
7891                                     input_set) != 0) {
7892                 PMD_DRV_LOG(ERR, "Invalid input set");
7893                 return -EINVAL;
7894         }
7895
7896         /* get inset value in register */
7897         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
7898         inset_reg <<= I40E_32_BIT_WIDTH;
7899         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
7900
7901         /* Can not change the inset reg for flex payload for fdir,
7902          * it is done by writing I40E_PRTQF_FD_FLXINSET
7903          * in i40e_set_flex_mask_on_pctype.
7904          */
7905         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
7906                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
7907         else
7908                 input_set |= pf->fdir.input_set[pctype];
7909         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
7910                                            I40E_INSET_MASK_NUM_REG);
7911         if (num < 0)
7912                 return -EINVAL;
7913
7914         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
7915
7916         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
7917                               (uint32_t)(inset_reg & UINT32_MAX));
7918         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
7919                              (uint32_t)((inset_reg >>
7920                              I40E_32_BIT_WIDTH) & UINT32_MAX));
7921
7922         for (i = 0; i < num; i++)
7923                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7924                                      mask_reg[i]);
7925         /*clear unused mask registers of the pctype */
7926         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
7927                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
7928                                      0);
7929         I40E_WRITE_FLUSH(hw);
7930
7931         pf->fdir.input_set[pctype] = input_set;
7932         return 0;
7933 }
7934
7935 static int
7936 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7937 {
7938         int ret = 0;
7939
7940         if (!hw || !info) {
7941                 PMD_DRV_LOG(ERR, "Invalid pointer");
7942                 return -EFAULT;
7943         }
7944
7945         switch (info->info_type) {
7946         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7947                 i40e_get_symmetric_hash_enable_per_port(hw,
7948                                         &(info->info.enable));
7949                 break;
7950         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7951                 ret = i40e_get_hash_filter_global_config(hw,
7952                                 &(info->info.global_conf));
7953                 break;
7954         default:
7955                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7956                                                         info->info_type);
7957                 ret = -EINVAL;
7958                 break;
7959         }
7960
7961         return ret;
7962 }
7963
7964 static int
7965 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
7966 {
7967         int ret = 0;
7968
7969         if (!hw || !info) {
7970                 PMD_DRV_LOG(ERR, "Invalid pointer");
7971                 return -EFAULT;
7972         }
7973
7974         switch (info->info_type) {
7975         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
7976                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
7977                 break;
7978         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
7979                 ret = i40e_set_hash_filter_global_config(hw,
7980                                 &(info->info.global_conf));
7981                 break;
7982         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
7983                 ret = i40e_hash_filter_inset_select(hw,
7984                                                &(info->info.input_set_conf));
7985                 break;
7986
7987         default:
7988                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
7989                                                         info->info_type);
7990                 ret = -EINVAL;
7991                 break;
7992         }
7993
7994         return ret;
7995 }
7996
7997 /* Operations for hash function */
7998 static int
7999 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8000                       enum rte_filter_op filter_op,
8001                       void *arg)
8002 {
8003         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8004         int ret = 0;
8005
8006         switch (filter_op) {
8007         case RTE_ETH_FILTER_NOP:
8008                 break;
8009         case RTE_ETH_FILTER_GET:
8010                 ret = i40e_hash_filter_get(hw,
8011                         (struct rte_eth_hash_filter_info *)arg);
8012                 break;
8013         case RTE_ETH_FILTER_SET:
8014                 ret = i40e_hash_filter_set(hw,
8015                         (struct rte_eth_hash_filter_info *)arg);
8016                 break;
8017         default:
8018                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8019                                                                 filter_op);
8020                 ret = -ENOTSUP;
8021                 break;
8022         }
8023
8024         return ret;
8025 }
8026
8027 /*
8028  * Configure ethertype filter, which can director packet by filtering
8029  * with mac address and ether_type or only ether_type
8030  */
8031 static int
8032 i40e_ethertype_filter_set(struct i40e_pf *pf,
8033                         struct rte_eth_ethertype_filter *filter,
8034                         bool add)
8035 {
8036         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8037         struct i40e_control_filter_stats stats;
8038         uint16_t flags = 0;
8039         int ret;
8040
8041         if (filter->queue >= pf->dev_data->nb_rx_queues) {
8042                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8043                 return -EINVAL;
8044         }
8045         if (filter->ether_type == ETHER_TYPE_IPv4 ||
8046                 filter->ether_type == ETHER_TYPE_IPv6) {
8047                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
8048                         " control packet filter.", filter->ether_type);
8049                 return -EINVAL;
8050         }
8051         if (filter->ether_type == ETHER_TYPE_VLAN)
8052                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
8053                         " not supported.");
8054
8055         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8056                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8057         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8058                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8059         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8060
8061         memset(&stats, 0, sizeof(stats));
8062         ret = i40e_aq_add_rem_control_packet_filter(hw,
8063                         filter->mac_addr.addr_bytes,
8064                         filter->ether_type, flags,
8065                         pf->main_vsi->seid,
8066                         filter->queue, add, &stats, NULL);
8067
8068         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
8069                          " mac_etype_used = %u, etype_used = %u,"
8070                          " mac_etype_free = %u, etype_free = %u\n",
8071                          ret, stats.mac_etype_used, stats.etype_used,
8072                          stats.mac_etype_free, stats.etype_free);
8073         if (ret < 0)
8074                 return -ENOSYS;
8075         return 0;
8076 }
8077
8078 /*
8079  * Handle operations for ethertype filter.
8080  */
8081 static int
8082 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8083                                 enum rte_filter_op filter_op,
8084                                 void *arg)
8085 {
8086         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8087         int ret = 0;
8088
8089         if (filter_op == RTE_ETH_FILTER_NOP)
8090                 return ret;
8091
8092         if (arg == NULL) {
8093                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8094                             filter_op);
8095                 return -EINVAL;
8096         }
8097
8098         switch (filter_op) {
8099         case RTE_ETH_FILTER_ADD:
8100                 ret = i40e_ethertype_filter_set(pf,
8101                         (struct rte_eth_ethertype_filter *)arg,
8102                         TRUE);
8103                 break;
8104         case RTE_ETH_FILTER_DELETE:
8105                 ret = i40e_ethertype_filter_set(pf,
8106                         (struct rte_eth_ethertype_filter *)arg,
8107                         FALSE);
8108                 break;
8109         default:
8110                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
8111                 ret = -ENOSYS;
8112                 break;
8113         }
8114         return ret;
8115 }
8116
8117 static int
8118 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8119                      enum rte_filter_type filter_type,
8120                      enum rte_filter_op filter_op,
8121                      void *arg)
8122 {
8123         int ret = 0;
8124
8125         if (dev == NULL)
8126                 return -EINVAL;
8127
8128         switch (filter_type) {
8129         case RTE_ETH_FILTER_NONE:
8130                 /* For global configuration */
8131                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8132                 break;
8133         case RTE_ETH_FILTER_HASH:
8134                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8135                 break;
8136         case RTE_ETH_FILTER_MACVLAN:
8137                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8138                 break;
8139         case RTE_ETH_FILTER_ETHERTYPE:
8140                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8141                 break;
8142         case RTE_ETH_FILTER_TUNNEL:
8143                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8144                 break;
8145         case RTE_ETH_FILTER_FDIR:
8146                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8147                 break;
8148         default:
8149                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8150                                                         filter_type);
8151                 ret = -EINVAL;
8152                 break;
8153         }
8154
8155         return ret;
8156 }
8157
8158 /*
8159  * Check and enable Extended Tag.
8160  * Enabling Extended Tag is important for 40G performance.
8161  */
8162 static void
8163 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8164 {
8165         uint32_t buf = 0;
8166         int ret;
8167
8168         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
8169                                       PCI_DEV_CAP_REG);
8170         if (ret < 0) {
8171                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8172                             PCI_DEV_CAP_REG);
8173                 return;
8174         }
8175         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
8176                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
8177                 return;
8178         }
8179
8180         buf = 0;
8181         ret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),
8182                                       PCI_DEV_CTRL_REG);
8183         if (ret < 0) {
8184                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8185                             PCI_DEV_CTRL_REG);
8186                 return;
8187         }
8188         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
8189                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
8190                 return;
8191         }
8192         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
8193         ret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf),
8194                                        PCI_DEV_CTRL_REG);
8195         if (ret < 0) {
8196                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
8197                             PCI_DEV_CTRL_REG);
8198                 return;
8199         }
8200 }
8201
8202 /*
8203  * As some registers wouldn't be reset unless a global hardware reset,
8204  * hardware initialization is needed to put those registers into an
8205  * expected initial state.
8206  */
8207 static void
8208 i40e_hw_init(struct rte_eth_dev *dev)
8209 {
8210         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8211
8212         i40e_enable_extended_tag(dev);
8213
8214         /* clear the PF Queue Filter control register */
8215         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
8216
8217         /* Disable symmetric hash per port */
8218         i40e_set_symmetric_hash_enable_per_port(hw, 0);
8219 }
8220
8221 enum i40e_filter_pctype
8222 i40e_flowtype_to_pctype(uint16_t flow_type)
8223 {
8224         static const enum i40e_filter_pctype pctype_table[] = {
8225                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
8226                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
8227                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
8228                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
8229                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
8230                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
8231                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
8232                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
8233                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
8234                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
8235                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
8236                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
8237                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
8238                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
8239                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
8240                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
8241                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
8242                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
8243                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
8244         };
8245
8246         return pctype_table[flow_type];
8247 }
8248
8249 uint16_t
8250 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
8251 {
8252         static const uint16_t flowtype_table[] = {
8253                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
8254                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8255                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8256 #ifdef X722_SUPPORT
8257                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8258                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8259                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8260                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8261 #endif
8262                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8263                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8264 #ifdef X722_SUPPORT
8265                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8266                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8267 #endif
8268                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8269                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
8270                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8271                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
8272                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
8273                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8274                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8275 #ifdef X722_SUPPORT
8276                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8277                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8278                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8279                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8280 #endif
8281                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8282                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8283 #ifdef X722_SUPPORT
8284                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8285                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8286 #endif
8287                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8288                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8289                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8290                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8291                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8292         };
8293
8294         return flowtype_table[pctype];
8295 }
8296
8297 /*
8298  * On X710, performance number is far from the expectation on recent firmware
8299  * versions; on XL710, performance number is also far from the expectation on
8300  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8301  * mode is enabled and port MAC address is equal to the packet destination MAC
8302  * address. The fix for this issue may not be integrated in the following
8303  * firmware version. So the workaround in software driver is needed. It needs
8304  * to modify the initial values of 3 internal only registers for both X710 and
8305  * XL710. Note that the values for X710 or XL710 could be different, and the
8306  * workaround can be removed when it is fixed in firmware in the future.
8307  */
8308
8309 /* For both X710 and XL710 */
8310 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
8311 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
8312
8313 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8314 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
8315
8316 /* For X710 */
8317 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
8318 /* For XL710 */
8319 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
8320 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
8321
8322 static int
8323 i40e_dev_sync_phy_type(struct i40e_hw *hw)
8324 {
8325         enum i40e_status_code status;
8326         struct i40e_aq_get_phy_abilities_resp phy_ab;
8327         int ret = -ENOTSUP;
8328
8329         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
8330                                               NULL);
8331
8332         if (status)
8333                 return ret;
8334
8335         return 0;
8336 }
8337
8338
8339 static void
8340 i40e_configure_registers(struct i40e_hw *hw)
8341 {
8342         static struct {
8343                 uint32_t addr;
8344                 uint64_t val;
8345         } reg_table[] = {
8346                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
8347                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
8348                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8349         };
8350         uint64_t reg;
8351         uint32_t i;
8352         int ret;
8353
8354         for (i = 0; i < RTE_DIM(reg_table); i++) {
8355                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8356                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
8357                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
8358                                 reg_table[i].val =
8359                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
8360                         else /* For X710 */
8361                                 reg_table[i].val =
8362                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
8363                 }
8364
8365                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8366                                                         &reg, NULL);
8367                 if (ret < 0) {
8368                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8369                                                         reg_table[i].addr);
8370                         break;
8371                 }
8372                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8373                                                 reg_table[i].addr, reg);
8374                 if (reg == reg_table[i].val)
8375                         continue;
8376
8377                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
8378                                                 reg_table[i].val, NULL);
8379                 if (ret < 0) {
8380                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
8381                                 "address of 0x%"PRIx32, reg_table[i].val,
8382                                                         reg_table[i].addr);
8383                         break;
8384                 }
8385                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
8386                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
8387         }
8388 }
8389
8390 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
8391 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
8392 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
8393 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
8394 static int
8395 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
8396 {
8397         uint32_t reg;
8398         int ret;
8399
8400         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
8401                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
8402                 return -EINVAL;
8403         }
8404
8405         /* Configure for double VLAN RX stripping */
8406         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
8407         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
8408                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
8409                 ret = i40e_aq_debug_write_register(hw,
8410                                                    I40E_VSI_TSR(vsi->vsi_id),
8411                                                    reg, NULL);
8412                 if (ret < 0) {
8413                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
8414                                     vsi->vsi_id);
8415                         return I40E_ERR_CONFIG;
8416                 }
8417         }
8418
8419         /* Configure for double VLAN TX insertion */
8420         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
8421         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
8422                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
8423                 ret = i40e_aq_debug_write_register(hw,
8424                                                    I40E_VSI_L2TAGSTXVALID(
8425                                                    vsi->vsi_id), reg, NULL);
8426                 if (ret < 0) {
8427                         PMD_DRV_LOG(ERR, "Failed to update "
8428                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
8429                         return I40E_ERR_CONFIG;
8430                 }
8431         }
8432
8433         return 0;
8434 }
8435
8436 /**
8437  * i40e_aq_add_mirror_rule
8438  * @hw: pointer to the hardware structure
8439  * @seid: VEB seid to add mirror rule to
8440  * @dst_id: destination vsi seid
8441  * @entries: Buffer which contains the entities to be mirrored
8442  * @count: number of entities contained in the buffer
8443  * @rule_id:the rule_id of the rule to be added
8444  *
8445  * Add a mirror rule for a given veb.
8446  *
8447  **/
8448 static enum i40e_status_code
8449 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
8450                         uint16_t seid, uint16_t dst_id,
8451                         uint16_t rule_type, uint16_t *entries,
8452                         uint16_t count, uint16_t *rule_id)
8453 {
8454         struct i40e_aq_desc desc;
8455         struct i40e_aqc_add_delete_mirror_rule cmd;
8456         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8457                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8458                 &desc.params.raw;
8459         uint16_t buff_len;
8460         enum i40e_status_code status;
8461
8462         i40e_fill_default_direct_cmd_desc(&desc,
8463                                           i40e_aqc_opc_add_mirror_rule);
8464         memset(&cmd, 0, sizeof(cmd));
8465
8466         buff_len = sizeof(uint16_t) * count;
8467         desc.datalen = rte_cpu_to_le_16(buff_len);
8468         if (buff_len > 0)
8469                 desc.flags |= rte_cpu_to_le_16(
8470                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8471         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8472                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8473         cmd.num_entries = rte_cpu_to_le_16(count);
8474         cmd.seid = rte_cpu_to_le_16(seid);
8475         cmd.destination = rte_cpu_to_le_16(dst_id);
8476
8477         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8478         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8479         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
8480                          "rule_id = %u"
8481                          " mirror_rules_used = %u, mirror_rules_free = %u,",
8482                          hw->aq.asq_last_status, resp->rule_id,
8483                          resp->mirror_rules_used, resp->mirror_rules_free);
8484         *rule_id = rte_le_to_cpu_16(resp->rule_id);
8485
8486         return status;
8487 }
8488
8489 /**
8490  * i40e_aq_del_mirror_rule
8491  * @hw: pointer to the hardware structure
8492  * @seid: VEB seid to add mirror rule to
8493  * @entries: Buffer which contains the entities to be mirrored
8494  * @count: number of entities contained in the buffer
8495  * @rule_id:the rule_id of the rule to be delete
8496  *
8497  * Delete a mirror rule for a given veb.
8498  *
8499  **/
8500 static enum i40e_status_code
8501 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8502                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8503                 uint16_t count, uint16_t rule_id)
8504 {
8505         struct i40e_aq_desc desc;
8506         struct i40e_aqc_add_delete_mirror_rule cmd;
8507         uint16_t buff_len = 0;
8508         enum i40e_status_code status;
8509         void *buff = NULL;
8510
8511         i40e_fill_default_direct_cmd_desc(&desc,
8512                                           i40e_aqc_opc_delete_mirror_rule);
8513         memset(&cmd, 0, sizeof(cmd));
8514         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8515                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8516                                                           I40E_AQ_FLAG_RD));
8517                 cmd.num_entries = count;
8518                 buff_len = sizeof(uint16_t) * count;
8519                 desc.datalen = rte_cpu_to_le_16(buff_len);
8520                 buff = (void *)entries;
8521         } else
8522                 /* rule id is filled in destination field for deleting mirror rule */
8523                 cmd.destination = rte_cpu_to_le_16(rule_id);
8524
8525         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8526                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8527         cmd.seid = rte_cpu_to_le_16(seid);
8528
8529         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8530         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
8531
8532         return status;
8533 }
8534
8535 /**
8536  * i40e_mirror_rule_set
8537  * @dev: pointer to the hardware structure
8538  * @mirror_conf: mirror rule info
8539  * @sw_id: mirror rule's sw_id
8540  * @on: enable/disable
8541  *
8542  * set a mirror rule.
8543  *
8544  **/
8545 static int
8546 i40e_mirror_rule_set(struct rte_eth_dev *dev,
8547                         struct rte_eth_mirror_conf *mirror_conf,
8548                         uint8_t sw_id, uint8_t on)
8549 {
8550         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8551         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8552         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8553         struct i40e_mirror_rule *parent = NULL;
8554         uint16_t seid, dst_seid, rule_id;
8555         uint16_t i, j = 0;
8556         int ret;
8557
8558         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
8559
8560         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
8561                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
8562                         " without veb or vfs.");
8563                 return -ENOSYS;
8564         }
8565         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
8566                 PMD_DRV_LOG(ERR, "mirror table is full.");
8567                 return -ENOSPC;
8568         }
8569         if (mirror_conf->dst_pool > pf->vf_num) {
8570                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
8571                                  mirror_conf->dst_pool);
8572                 return -EINVAL;
8573         }
8574
8575         seid = pf->main_vsi->veb->seid;
8576
8577         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8578                 if (sw_id <= it->index) {
8579                         mirr_rule = it;
8580                         break;
8581                 }
8582                 parent = it;
8583         }
8584         if (mirr_rule && sw_id == mirr_rule->index) {
8585                 if (on) {
8586                         PMD_DRV_LOG(ERR, "mirror rule exists.");
8587                         return -EEXIST;
8588                 } else {
8589                         ret = i40e_aq_del_mirror_rule(hw, seid,
8590                                         mirr_rule->rule_type,
8591                                         mirr_rule->entries,
8592                                         mirr_rule->num_entries, mirr_rule->id);
8593                         if (ret < 0) {
8594                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8595                                                    " ret = %d, aq_err = %d.",
8596                                                    ret, hw->aq.asq_last_status);
8597                                 return -ENOSYS;
8598                         }
8599                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8600                         rte_free(mirr_rule);
8601                         pf->nb_mirror_rule--;
8602                         return 0;
8603                 }
8604         } else if (!on) {
8605                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8606                 return -ENOENT;
8607         }
8608
8609         mirr_rule = rte_zmalloc("i40e_mirror_rule",
8610                                 sizeof(struct i40e_mirror_rule) , 0);
8611         if (!mirr_rule) {
8612                 PMD_DRV_LOG(ERR, "failed to allocate memory");
8613                 return I40E_ERR_NO_MEMORY;
8614         }
8615         switch (mirror_conf->rule_type) {
8616         case ETH_MIRROR_VLAN:
8617                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
8618                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
8619                                 mirr_rule->entries[j] =
8620                                         mirror_conf->vlan.vlan_id[i];
8621                                 j++;
8622                         }
8623                 }
8624                 if (j == 0) {
8625                         PMD_DRV_LOG(ERR, "vlan is not specified.");
8626                         rte_free(mirr_rule);
8627                         return -EINVAL;
8628                 }
8629                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
8630                 break;
8631         case ETH_MIRROR_VIRTUAL_POOL_UP:
8632         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
8633                 /* check if the specified pool bit is out of range */
8634                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
8635                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
8636                         rte_free(mirr_rule);
8637                         return -EINVAL;
8638                 }
8639                 for (i = 0, j = 0; i < pf->vf_num; i++) {
8640                         if (mirror_conf->pool_mask & (1ULL << i)) {
8641                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
8642                                 j++;
8643                         }
8644                 }
8645                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
8646                         /* add pf vsi to entries */
8647                         mirr_rule->entries[j] = pf->main_vsi_seid;
8648                         j++;
8649                 }
8650                 if (j == 0) {
8651                         PMD_DRV_LOG(ERR, "pool is not specified.");
8652                         rte_free(mirr_rule);
8653                         return -EINVAL;
8654                 }
8655                 /* egress and ingress in aq commands means from switch but not port */
8656                 mirr_rule->rule_type =
8657                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
8658                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
8659                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
8660                 break;
8661         case ETH_MIRROR_UPLINK_PORT:
8662                 /* egress and ingress in aq commands means from switch but not port*/
8663                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
8664                 break;
8665         case ETH_MIRROR_DOWNLINK_PORT:
8666                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
8667                 break;
8668         default:
8669                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
8670                         mirror_conf->rule_type);
8671                 rte_free(mirr_rule);
8672                 return -EINVAL;
8673         }
8674
8675         /* If the dst_pool is equal to vf_num, consider it as PF */
8676         if (mirror_conf->dst_pool == pf->vf_num)
8677                 dst_seid = pf->main_vsi_seid;
8678         else
8679                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
8680
8681         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
8682                                       mirr_rule->rule_type, mirr_rule->entries,
8683                                       j, &rule_id);
8684         if (ret < 0) {
8685                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
8686                                    " ret = %d, aq_err = %d.",
8687                                    ret, hw->aq.asq_last_status);
8688                 rte_free(mirr_rule);
8689                 return -ENOSYS;
8690         }
8691
8692         mirr_rule->index = sw_id;
8693         mirr_rule->num_entries = j;
8694         mirr_rule->id = rule_id;
8695         mirr_rule->dst_vsi_seid = dst_seid;
8696
8697         if (parent)
8698                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
8699         else
8700                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
8701
8702         pf->nb_mirror_rule++;
8703         return 0;
8704 }
8705
8706 /**
8707  * i40e_mirror_rule_reset
8708  * @dev: pointer to the device
8709  * @sw_id: mirror rule's sw_id
8710  *
8711  * reset a mirror rule.
8712  *
8713  **/
8714 static int
8715 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
8716 {
8717         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8718         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8719         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8720         uint16_t seid;
8721         int ret;
8722
8723         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
8724
8725         seid = pf->main_vsi->veb->seid;
8726
8727         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8728                 if (sw_id == it->index) {
8729                         mirr_rule = it;
8730                         break;
8731                 }
8732         }
8733         if (mirr_rule) {
8734                 ret = i40e_aq_del_mirror_rule(hw, seid,
8735                                 mirr_rule->rule_type,
8736                                 mirr_rule->entries,
8737                                 mirr_rule->num_entries, mirr_rule->id);
8738                 if (ret < 0) {
8739                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
8740                                            " status = %d, aq_err = %d.",
8741                                            ret, hw->aq.asq_last_status);
8742                         return -ENOSYS;
8743                 }
8744                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
8745                 rte_free(mirr_rule);
8746                 pf->nb_mirror_rule--;
8747         } else {
8748                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
8749                 return -ENOENT;
8750         }
8751         return 0;
8752 }
8753
8754 static uint64_t
8755 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
8756 {
8757         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8758         uint64_t systim_cycles;
8759
8760         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
8761         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
8762                         << 32;
8763
8764         return systim_cycles;
8765 }
8766
8767 static uint64_t
8768 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
8769 {
8770         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8771         uint64_t rx_tstamp;
8772
8773         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
8774         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
8775                         << 32;
8776
8777         return rx_tstamp;
8778 }
8779
8780 static uint64_t
8781 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
8782 {
8783         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8784         uint64_t tx_tstamp;
8785
8786         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
8787         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
8788                         << 32;
8789
8790         return tx_tstamp;
8791 }
8792
8793 static void
8794 i40e_start_timecounters(struct rte_eth_dev *dev)
8795 {
8796         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8797         struct i40e_adapter *adapter =
8798                         (struct i40e_adapter *)dev->data->dev_private;
8799         struct rte_eth_link link;
8800         uint32_t tsync_inc_l;
8801         uint32_t tsync_inc_h;
8802
8803         /* Get current link speed. */
8804         memset(&link, 0, sizeof(link));
8805         i40e_dev_link_update(dev, 1);
8806         rte_i40e_dev_atomic_read_link_status(dev, &link);
8807
8808         switch (link.link_speed) {
8809         case ETH_SPEED_NUM_40G:
8810                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
8811                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
8812                 break;
8813         case ETH_SPEED_NUM_10G:
8814                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
8815                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
8816                 break;
8817         case ETH_SPEED_NUM_1G:
8818                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
8819                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
8820                 break;
8821         default:
8822                 tsync_inc_l = 0x0;
8823                 tsync_inc_h = 0x0;
8824         }
8825
8826         /* Set the timesync increment value. */
8827         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
8828         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
8829
8830         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
8831         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8832         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
8833
8834         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8835         adapter->systime_tc.cc_shift = 0;
8836         adapter->systime_tc.nsec_mask = 0;
8837
8838         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8839         adapter->rx_tstamp_tc.cc_shift = 0;
8840         adapter->rx_tstamp_tc.nsec_mask = 0;
8841
8842         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
8843         adapter->tx_tstamp_tc.cc_shift = 0;
8844         adapter->tx_tstamp_tc.nsec_mask = 0;
8845 }
8846
8847 static int
8848 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
8849 {
8850         struct i40e_adapter *adapter =
8851                         (struct i40e_adapter *)dev->data->dev_private;
8852
8853         adapter->systime_tc.nsec += delta;
8854         adapter->rx_tstamp_tc.nsec += delta;
8855         adapter->tx_tstamp_tc.nsec += delta;
8856
8857         return 0;
8858 }
8859
8860 static int
8861 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
8862 {
8863         uint64_t ns;
8864         struct i40e_adapter *adapter =
8865                         (struct i40e_adapter *)dev->data->dev_private;
8866
8867         ns = rte_timespec_to_ns(ts);
8868
8869         /* Set the timecounters to a new value. */
8870         adapter->systime_tc.nsec = ns;
8871         adapter->rx_tstamp_tc.nsec = ns;
8872         adapter->tx_tstamp_tc.nsec = ns;
8873
8874         return 0;
8875 }
8876
8877 static int
8878 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
8879 {
8880         uint64_t ns, systime_cycles;
8881         struct i40e_adapter *adapter =
8882                         (struct i40e_adapter *)dev->data->dev_private;
8883
8884         systime_cycles = i40e_read_systime_cyclecounter(dev);
8885         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
8886         *ts = rte_ns_to_timespec(ns);
8887
8888         return 0;
8889 }
8890
8891 static int
8892 i40e_timesync_enable(struct rte_eth_dev *dev)
8893 {
8894         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8895         uint32_t tsync_ctl_l;
8896         uint32_t tsync_ctl_h;
8897
8898         /* Stop the timesync system time. */
8899         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8900         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8901         /* Reset the timesync system time value. */
8902         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
8903         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
8904
8905         i40e_start_timecounters(dev);
8906
8907         /* Clear timesync registers. */
8908         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8909         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
8910         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
8911         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
8912         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
8913         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
8914
8915         /* Enable timestamping of PTP packets. */
8916         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8917         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
8918
8919         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8920         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
8921         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
8922
8923         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8924         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8925
8926         return 0;
8927 }
8928
8929 static int
8930 i40e_timesync_disable(struct rte_eth_dev *dev)
8931 {
8932         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8933         uint32_t tsync_ctl_l;
8934         uint32_t tsync_ctl_h;
8935
8936         /* Disable timestamping of transmitted PTP packets. */
8937         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
8938         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
8939
8940         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
8941         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
8942
8943         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
8944         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
8945
8946         /* Reset the timesync increment value. */
8947         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
8948         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
8949
8950         return 0;
8951 }
8952
8953 static int
8954 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
8955                                 struct timespec *timestamp, uint32_t flags)
8956 {
8957         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8958         struct i40e_adapter *adapter =
8959                 (struct i40e_adapter *)dev->data->dev_private;
8960
8961         uint32_t sync_status;
8962         uint32_t index = flags & 0x03;
8963         uint64_t rx_tstamp_cycles;
8964         uint64_t ns;
8965
8966         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
8967         if ((sync_status & (1 << index)) == 0)
8968                 return -EINVAL;
8969
8970         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
8971         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
8972         *timestamp = rte_ns_to_timespec(ns);
8973
8974         return 0;
8975 }
8976
8977 static int
8978 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
8979                                 struct timespec *timestamp)
8980 {
8981         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8982         struct i40e_adapter *adapter =
8983                 (struct i40e_adapter *)dev->data->dev_private;
8984
8985         uint32_t sync_status;
8986         uint64_t tx_tstamp_cycles;
8987         uint64_t ns;
8988
8989         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
8990         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
8991                 return -EINVAL;
8992
8993         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
8994         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
8995         *timestamp = rte_ns_to_timespec(ns);
8996
8997         return 0;
8998 }
8999
9000 /*
9001  * i40e_parse_dcb_configure - parse dcb configure from user
9002  * @dev: the device being configured
9003  * @dcb_cfg: pointer of the result of parse
9004  * @*tc_map: bit map of enabled traffic classes
9005  *
9006  * Returns 0 on success, negative value on failure
9007  */
9008 static int
9009 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9010                          struct i40e_dcbx_config *dcb_cfg,
9011                          uint8_t *tc_map)
9012 {
9013         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9014         uint8_t i, tc_bw, bw_lf;
9015
9016         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9017
9018         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9019         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9020                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9021                 return -EINVAL;
9022         }
9023
9024         /* assume each tc has the same bw */
9025         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9026         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9027                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9028         /* to ensure the sum of tcbw is equal to 100 */
9029         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9030         for (i = 0; i < bw_lf; i++)
9031                 dcb_cfg->etscfg.tcbwtable[i]++;
9032
9033         /* assume each tc has the same Transmission Selection Algorithm */
9034         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9035                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9036
9037         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9038                 dcb_cfg->etscfg.prioritytable[i] =
9039                                 dcb_rx_conf->dcb_tc[i];
9040
9041         /* FW needs one App to configure HW */
9042         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9043         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9044         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9045         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9046
9047         if (dcb_rx_conf->nb_tcs == 0)
9048                 *tc_map = 1; /* tc0 only */
9049         else
9050                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9051
9052         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9053                 dcb_cfg->pfc.willing = 0;
9054                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9055                 dcb_cfg->pfc.pfcenable = *tc_map;
9056         }
9057         return 0;
9058 }
9059
9060
9061 static enum i40e_status_code
9062 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9063                               struct i40e_aqc_vsi_properties_data *info,
9064                               uint8_t enabled_tcmap)
9065 {
9066         enum i40e_status_code ret;
9067         int i, total_tc = 0;
9068         uint16_t qpnum_per_tc, bsf, qp_idx;
9069         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9070         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9071         uint16_t used_queues;
9072
9073         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9074         if (ret != I40E_SUCCESS)
9075                 return ret;
9076
9077         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9078                 if (enabled_tcmap & (1 << i))
9079                         total_tc++;
9080         }
9081         if (total_tc == 0)
9082                 total_tc = 1;
9083         vsi->enabled_tc = enabled_tcmap;
9084
9085         /* different VSI has different queues assigned */
9086         if (vsi->type == I40E_VSI_MAIN)
9087                 used_queues = dev_data->nb_rx_queues -
9088                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9089         else if (vsi->type == I40E_VSI_VMDQ2)
9090                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9091         else {
9092                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9093                 return I40E_ERR_NO_AVAILABLE_VSI;
9094         }
9095
9096         qpnum_per_tc = used_queues / total_tc;
9097         /* Number of queues per enabled TC */
9098         if (qpnum_per_tc == 0) {
9099                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9100                 return I40E_ERR_INVALID_QP_ID;
9101         }
9102         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9103                                 I40E_MAX_Q_PER_TC);
9104         bsf = rte_bsf32(qpnum_per_tc);
9105
9106         /**
9107          * Configure TC and queue mapping parameters, for enabled TC,
9108          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9109          * default queue will serve it.
9110          */
9111         qp_idx = 0;
9112         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9113                 if (vsi->enabled_tc & (1 << i)) {
9114                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9115                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9116                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9117                         qp_idx += qpnum_per_tc;
9118                 } else
9119                         info->tc_mapping[i] = 0;
9120         }
9121
9122         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9123         if (vsi->type == I40E_VSI_SRIOV) {
9124                 info->mapping_flags |=
9125                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9126                 for (i = 0; i < vsi->nb_qps; i++)
9127                         info->queue_mapping[i] =
9128                                 rte_cpu_to_le_16(vsi->base_queue + i);
9129         } else {
9130                 info->mapping_flags |=
9131                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9132                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9133         }
9134         info->valid_sections |=
9135                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9136
9137         return I40E_SUCCESS;
9138 }
9139
9140 /*
9141  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9142  * @veb: VEB to be configured
9143  * @tc_map: enabled TC bitmap
9144  *
9145  * Returns 0 on success, negative value on failure
9146  */
9147 static enum i40e_status_code
9148 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9149 {
9150         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9151         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9152         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9153         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9154         enum i40e_status_code ret = I40E_SUCCESS;
9155         int i;
9156         uint32_t bw_max;
9157
9158         /* Check if enabled_tc is same as existing or new TCs */
9159         if (veb->enabled_tc == tc_map)
9160                 return ret;
9161
9162         /* configure tc bandwidth */
9163         memset(&veb_bw, 0, sizeof(veb_bw));
9164         veb_bw.tc_valid_bits = tc_map;
9165         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9166         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9167                 if (tc_map & BIT_ULL(i))
9168                         veb_bw.tc_bw_share_credits[i] = 1;
9169         }
9170         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
9171                                                    &veb_bw, NULL);
9172         if (ret) {
9173                 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
9174                                   " per TC failed = %d",
9175                                   hw->aq.asq_last_status);
9176                 return ret;
9177         }
9178
9179         memset(&ets_query, 0, sizeof(ets_query));
9180         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9181                                                    &ets_query, NULL);
9182         if (ret != I40E_SUCCESS) {
9183                 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
9184                                  " configuration %u", hw->aq.asq_last_status);
9185                 return ret;
9186         }
9187         memset(&bw_query, 0, sizeof(bw_query));
9188         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9189                                                   &bw_query, NULL);
9190         if (ret != I40E_SUCCESS) {
9191                 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
9192                                  " configuration %u", hw->aq.asq_last_status);
9193                 return ret;
9194         }
9195
9196         /* store and print out BW info */
9197         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
9198         veb->bw_info.bw_max = ets_query.tc_bw_max;
9199         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
9200         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
9201         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
9202                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
9203                      I40E_16_BIT_WIDTH);
9204         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9205                 veb->bw_info.bw_ets_share_credits[i] =
9206                                 bw_query.tc_bw_share_credits[i];
9207                 veb->bw_info.bw_ets_credits[i] =
9208                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
9209                 /* 4 bits per TC, 4th bit is reserved */
9210                 veb->bw_info.bw_ets_max[i] =
9211                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
9212                                   RTE_LEN2MASK(3, uint8_t));
9213                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
9214                             veb->bw_info.bw_ets_share_credits[i]);
9215                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
9216                             veb->bw_info.bw_ets_credits[i]);
9217                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
9218                             veb->bw_info.bw_ets_max[i]);
9219         }
9220
9221         veb->enabled_tc = tc_map;
9222
9223         return ret;
9224 }
9225
9226
9227 /*
9228  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
9229  * @vsi: VSI to be configured
9230  * @tc_map: enabled TC bitmap
9231  *
9232  * Returns 0 on success, negative value on failure
9233  */
9234 static enum i40e_status_code
9235 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
9236 {
9237         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
9238         struct i40e_vsi_context ctxt;
9239         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
9240         enum i40e_status_code ret = I40E_SUCCESS;
9241         int i;
9242
9243         /* Check if enabled_tc is same as existing or new TCs */
9244         if (vsi->enabled_tc == tc_map)
9245                 return ret;
9246
9247         /* configure tc bandwidth */
9248         memset(&bw_data, 0, sizeof(bw_data));
9249         bw_data.tc_valid_bits = tc_map;
9250         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9251         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9252                 if (tc_map & BIT_ULL(i))
9253                         bw_data.tc_bw_credits[i] = 1;
9254         }
9255         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
9256         if (ret) {
9257                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
9258                         " per TC failed = %d",
9259                         hw->aq.asq_last_status);
9260                 goto out;
9261         }
9262         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
9263                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
9264
9265         /* Update Queue Pairs Mapping for currently enabled UPs */
9266         ctxt.seid = vsi->seid;
9267         ctxt.pf_num = hw->pf_id;
9268         ctxt.vf_num = 0;
9269         ctxt.uplink_seid = vsi->uplink_seid;
9270         ctxt.info = vsi->info;
9271         i40e_get_cap(hw);
9272         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
9273         if (ret)
9274                 goto out;
9275
9276         /* Update the VSI after updating the VSI queue-mapping information */
9277         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9278         if (ret) {
9279                 PMD_INIT_LOG(ERR, "Failed to configure "
9280                             "TC queue mapping = %d",
9281                             hw->aq.asq_last_status);
9282                 goto out;
9283         }
9284         /* update the local VSI info with updated queue map */
9285         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
9286                                         sizeof(vsi->info.tc_mapping));
9287         (void)rte_memcpy(&vsi->info.queue_mapping,
9288                         &ctxt.info.queue_mapping,
9289                 sizeof(vsi->info.queue_mapping));
9290         vsi->info.mapping_flags = ctxt.info.mapping_flags;
9291         vsi->info.valid_sections = 0;
9292
9293         /* query and update current VSI BW information */
9294         ret = i40e_vsi_get_bw_config(vsi);
9295         if (ret) {
9296                 PMD_INIT_LOG(ERR,
9297                          "Failed updating vsi bw info, err %s aq_err %s",
9298                          i40e_stat_str(hw, ret),
9299                          i40e_aq_str(hw, hw->aq.asq_last_status));
9300                 goto out;
9301         }
9302
9303         vsi->enabled_tc = tc_map;
9304
9305 out:
9306         return ret;
9307 }
9308
9309 /*
9310  * i40e_dcb_hw_configure - program the dcb setting to hw
9311  * @pf: pf the configuration is taken on
9312  * @new_cfg: new configuration
9313  * @tc_map: enabled TC bitmap
9314  *
9315  * Returns 0 on success, negative value on failure
9316  */
9317 static enum i40e_status_code
9318 i40e_dcb_hw_configure(struct i40e_pf *pf,
9319                       struct i40e_dcbx_config *new_cfg,
9320                       uint8_t tc_map)
9321 {
9322         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9323         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9324         struct i40e_vsi *main_vsi = pf->main_vsi;
9325         struct i40e_vsi_list *vsi_list;
9326         enum i40e_status_code ret;
9327         int i;
9328         uint32_t val;
9329
9330         /* Use the FW API if FW > v4.4*/
9331         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9332               (hw->aq.fw_maj_ver >= 5))) {
9333                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
9334                                   " to configure DCB");
9335                 return I40E_ERR_FIRMWARE_API_VERSION;
9336         }
9337
9338         /* Check if need reconfiguration */
9339         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9340                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9341                 return I40E_SUCCESS;
9342         }
9343
9344         /* Copy the new config to the current config */
9345         *old_cfg = *new_cfg;
9346         old_cfg->etsrec = old_cfg->etscfg;
9347         ret = i40e_set_dcb_config(hw);
9348         if (ret) {
9349                 PMD_INIT_LOG(ERR,
9350                          "Set DCB Config failed, err %s aq_err %s\n",
9351                          i40e_stat_str(hw, ret),
9352                          i40e_aq_str(hw, hw->aq.asq_last_status));
9353                 return ret;
9354         }
9355         /* set receive Arbiter to RR mode and ETS scheme by default */
9356         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9357                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9358                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
9359                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9360                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9361                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9362                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9363                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9364                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9365                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9366                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9367                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9368                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9369         }
9370         /* get local mib to check whether it is configured correctly */
9371         /* IEEE mode */
9372         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9373         /* Get Local DCB Config */
9374         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9375                                      &hw->local_dcbx_config);
9376
9377         /* if Veb is created, need to update TC of it at first */
9378         if (main_vsi->veb) {
9379                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
9380                 if (ret)
9381                         PMD_INIT_LOG(WARNING,
9382                                  "Failed configuring TC for VEB seid=%d\n",
9383                                  main_vsi->veb->seid);
9384         }
9385         /* Update each VSI */
9386         i40e_vsi_config_tc(main_vsi, tc_map);
9387         if (main_vsi->veb) {
9388                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
9389                         /* Beside main VSI and VMDQ VSIs, only enable default
9390                          * TC for other VSIs
9391                          */
9392                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
9393                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9394                                                          tc_map);
9395                         else
9396                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9397                                                          I40E_DEFAULT_TCMAP);
9398                         if (ret)
9399                                 PMD_INIT_LOG(WARNING,
9400                                          "Failed configuring TC for VSI seid=%d\n",
9401                                          vsi_list->vsi->seid);
9402                         /* continue */
9403                 }
9404         }
9405         return I40E_SUCCESS;
9406 }
9407
9408 /*
9409  * i40e_dcb_init_configure - initial dcb config
9410  * @dev: device being configured
9411  * @sw_dcb: indicate whether dcb is sw configured or hw offload
9412  *
9413  * Returns 0 on success, negative value on failure
9414  */
9415 static int
9416 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
9417 {
9418         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9419         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9420         int ret = 0;
9421
9422         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9423                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9424                 return -ENOTSUP;
9425         }
9426
9427         /* DCB initialization:
9428          * Update DCB configuration from the Firmware and configure
9429          * LLDP MIB change event.
9430          */
9431         if (sw_dcb == TRUE) {
9432                 ret = i40e_init_dcb(hw);
9433                 /* If lldp agent is stopped, the return value from
9434                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
9435                  * adminq status. Otherwise, it should return success.
9436                  */
9437                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
9438                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
9439                         memset(&hw->local_dcbx_config, 0,
9440                                 sizeof(struct i40e_dcbx_config));
9441                         /* set dcb default configuration */
9442                         hw->local_dcbx_config.etscfg.willing = 0;
9443                         hw->local_dcbx_config.etscfg.maxtcs = 0;
9444                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
9445                         hw->local_dcbx_config.etscfg.tsatable[0] =
9446                                                 I40E_IEEE_TSA_ETS;
9447                         hw->local_dcbx_config.etsrec =
9448                                 hw->local_dcbx_config.etscfg;
9449                         hw->local_dcbx_config.pfc.willing = 0;
9450                         hw->local_dcbx_config.pfc.pfccap =
9451                                                 I40E_MAX_TRAFFIC_CLASS;
9452                         /* FW needs one App to configure HW */
9453                         hw->local_dcbx_config.numapps = 1;
9454                         hw->local_dcbx_config.app[0].selector =
9455                                                 I40E_APP_SEL_ETHTYPE;
9456                         hw->local_dcbx_config.app[0].priority = 3;
9457                         hw->local_dcbx_config.app[0].protocolid =
9458                                                 I40E_APP_PROTOID_FCOE;
9459                         ret = i40e_set_dcb_config(hw);
9460                         if (ret) {
9461                                 PMD_INIT_LOG(ERR, "default dcb config fails."
9462                                         " err = %d, aq_err = %d.", ret,
9463                                           hw->aq.asq_last_status);
9464                                 return -ENOSYS;
9465                         }
9466                 } else {
9467                         PMD_INIT_LOG(ERR, "DCB initialization in FW fails,"
9468                                           " err = %d, aq_err = %d.", ret,
9469                                           hw->aq.asq_last_status);
9470                         return -ENOTSUP;
9471                 }
9472         } else {
9473                 ret = i40e_aq_start_lldp(hw, NULL);
9474                 if (ret != I40E_SUCCESS)
9475                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9476
9477                 ret = i40e_init_dcb(hw);
9478                 if (!ret) {
9479                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9480                                 PMD_INIT_LOG(ERR, "HW doesn't support"
9481                                                   " DCBX offload.");
9482                                 return -ENOTSUP;
9483                         }
9484                 } else {
9485                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9486                                           " aq_err = %d.", ret,
9487                                           hw->aq.asq_last_status);
9488                         return -ENOTSUP;
9489                 }
9490         }
9491         return 0;
9492 }
9493
9494 /*
9495  * i40e_dcb_setup - setup dcb related config
9496  * @dev: device being configured
9497  *
9498  * Returns 0 on success, negative value on failure
9499  */
9500 static int
9501 i40e_dcb_setup(struct rte_eth_dev *dev)
9502 {
9503         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9504         struct i40e_dcbx_config dcb_cfg;
9505         uint8_t tc_map = 0;
9506         int ret = 0;
9507
9508         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9509                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9510                 return -ENOTSUP;
9511         }
9512
9513         if (pf->vf_num != 0)
9514                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9515
9516         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9517         if (ret) {
9518                 PMD_INIT_LOG(ERR, "invalid dcb config");
9519                 return -EINVAL;
9520         }
9521         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9522         if (ret) {
9523                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
9524                 return -ENOSYS;
9525         }
9526
9527         return 0;
9528 }
9529
9530 static int
9531 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
9532                       struct rte_eth_dcb_info *dcb_info)
9533 {
9534         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9535         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9536         struct i40e_vsi *vsi = pf->main_vsi;
9537         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
9538         uint16_t bsf, tc_mapping;
9539         int i, j = 0;
9540
9541         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
9542                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
9543         else
9544                 dcb_info->nb_tcs = 1;
9545         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9546                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
9547         for (i = 0; i < dcb_info->nb_tcs; i++)
9548                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
9549
9550         /* get queue mapping if vmdq is disabled */
9551         if (!pf->nb_cfg_vmdq_vsi) {
9552                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9553                         if (!(vsi->enabled_tc & (1 << i)))
9554                                 continue;
9555                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9556                         dcb_info->tc_queue.tc_rxq[j][i].base =
9557                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9558                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9559                         dcb_info->tc_queue.tc_txq[j][i].base =
9560                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9561                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9562                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9563                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9564                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9565                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9566                 }
9567                 return 0;
9568         }
9569
9570         /* get queue mapping if vmdq is enabled */
9571         do {
9572                 vsi = pf->vmdq[j].vsi;
9573                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9574                         if (!(vsi->enabled_tc & (1 << i)))
9575                                 continue;
9576                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9577                         dcb_info->tc_queue.tc_rxq[j][i].base =
9578                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9579                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9580                         dcb_info->tc_queue.tc_txq[j][i].base =
9581                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9582                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9583                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9584                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9585                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9586                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9587                 }
9588                 j++;
9589         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
9590         return 0;
9591 }
9592
9593 static int
9594 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
9595 {
9596         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9597         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9598         uint16_t interval =
9599                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
9600         uint16_t msix_intr;
9601
9602         msix_intr = intr_handle->intr_vec[queue_id];
9603         if (msix_intr == I40E_MISC_VEC_ID)
9604                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
9605                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9606                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9607                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9608                                (interval <<
9609                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9610         else
9611                 I40E_WRITE_REG(hw,
9612                                I40E_PFINT_DYN_CTLN(msix_intr -
9613                                                    I40E_RX_VEC_START),
9614                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
9615                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
9616                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
9617                                (interval <<
9618                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
9619
9620         I40E_WRITE_FLUSH(hw);
9621         rte_intr_enable(&dev->pci_dev->intr_handle);
9622
9623         return 0;
9624 }
9625
9626 static int
9627 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
9628 {
9629         struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
9630         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9631         uint16_t msix_intr;
9632
9633         msix_intr = intr_handle->intr_vec[queue_id];
9634         if (msix_intr == I40E_MISC_VEC_ID)
9635                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
9636         else
9637                 I40E_WRITE_REG(hw,
9638                                I40E_PFINT_DYN_CTLN(msix_intr -
9639                                                    I40E_RX_VEC_START),
9640                                0);
9641         I40E_WRITE_FLUSH(hw);
9642
9643         return 0;
9644 }
9645
9646 static int i40e_get_regs(struct rte_eth_dev *dev,
9647                          struct rte_dev_reg_info *regs)
9648 {
9649         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9650         uint32_t *ptr_data = regs->data;
9651         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
9652         const struct i40e_reg_info *reg_info;
9653
9654         if (ptr_data == NULL) {
9655                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
9656                 regs->width = sizeof(uint32_t);
9657                 return 0;
9658         }
9659
9660         /* The first few registers have to be read using AQ operations */
9661         reg_idx = 0;
9662         while (i40e_regs_adminq[reg_idx].name) {
9663                 reg_info = &i40e_regs_adminq[reg_idx++];
9664                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9665                         for (arr_idx2 = 0;
9666                                         arr_idx2 <= reg_info->count2;
9667                                         arr_idx2++) {
9668                                 reg_offset = arr_idx * reg_info->stride1 +
9669                                         arr_idx2 * reg_info->stride2;
9670                                 reg_offset += reg_info->base_addr;
9671                                 ptr_data[reg_offset >> 2] =
9672                                         i40e_read_rx_ctl(hw, reg_offset);
9673                         }
9674         }
9675
9676         /* The remaining registers can be read using primitives */
9677         reg_idx = 0;
9678         while (i40e_regs_others[reg_idx].name) {
9679                 reg_info = &i40e_regs_others[reg_idx++];
9680                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
9681                         for (arr_idx2 = 0;
9682                                         arr_idx2 <= reg_info->count2;
9683                                         arr_idx2++) {
9684                                 reg_offset = arr_idx * reg_info->stride1 +
9685                                         arr_idx2 * reg_info->stride2;
9686                                 reg_offset += reg_info->base_addr;
9687                                 ptr_data[reg_offset >> 2] =
9688                                         I40E_READ_REG(hw, reg_offset);
9689                         }
9690         }
9691
9692         return 0;
9693 }
9694
9695 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
9696 {
9697         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9698
9699         /* Convert word count to byte count */
9700         return hw->nvm.sr_size << 1;
9701 }
9702
9703 static int i40e_get_eeprom(struct rte_eth_dev *dev,
9704                            struct rte_dev_eeprom_info *eeprom)
9705 {
9706         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9707         uint16_t *data = eeprom->data;
9708         uint16_t offset, length, cnt_words;
9709         int ret_code;
9710
9711         offset = eeprom->offset >> 1;
9712         length = eeprom->length >> 1;
9713         cnt_words = length;
9714
9715         if (offset > hw->nvm.sr_size ||
9716                 offset + length > hw->nvm.sr_size) {
9717                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
9718                 return -EINVAL;
9719         }
9720
9721         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
9722
9723         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
9724         if (ret_code != I40E_SUCCESS || cnt_words != length) {
9725                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
9726                 return -EIO;
9727         }
9728
9729         return 0;
9730 }
9731
9732 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
9733                                       struct ether_addr *mac_addr)
9734 {
9735         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9736
9737         if (!is_valid_assigned_ether_addr(mac_addr)) {
9738                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
9739                 return;
9740         }
9741
9742         /* Flags: 0x3 updates port address */
9743         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
9744 }
9745
9746 static int
9747 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
9748 {
9749         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9750         struct rte_eth_dev_data *dev_data = pf->dev_data;
9751         uint32_t frame_size = mtu + ETHER_HDR_LEN
9752                               + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
9753         int ret = 0;
9754
9755         /* check if mtu is within the allowed range */
9756         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
9757                 return -EINVAL;
9758
9759         /* mtu setting is forbidden if port is start */
9760         if (dev_data->dev_started) {
9761                 PMD_DRV_LOG(ERR,
9762                             "port %d must be stopped before configuration\n",
9763                             dev_data->port_id);
9764                 return -EBUSY;
9765         }
9766
9767         if (frame_size > ETHER_MAX_LEN)
9768                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
9769         else
9770                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
9771
9772         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
9773
9774         return ret;
9775 }