drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <errno.h>
  36 #include <stdint.h>
  37 #include <string.h>
  38 #include <unistd.h>
  39 #include <stdarg.h>
  40 #include <inttypes.h>
  41 #include <assert.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53 #include <rte_tailq.h>
  54 #include <rte_hash_crc.h>
  55
  56 #include "i40e_logs.h"
  57 #include "base/i40e_prototype.h"
  58 #include "base/i40e_adminq_cmd.h"
  59 #include "base/i40e_type.h"
  60 #include "base/i40e_register.h"
  61 #include "base/i40e_dcb.h"
  62 #include "i40e_ethdev.h"
  63 #include "i40e_rxtx.h"
  64 #include "i40e_pf.h"
  65 #include "i40e_regs.h"
  66
  67 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  68 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  69
  70 #define I40E_CLEAR_PXE_WAIT_MS     200
  71
  72 /* Maximun number of capability elements */
  73 #define I40E_MAX_CAP_ELE_NUM       128
  74
  75 /* Wait count and inteval */
  76 #define I40E_CHK_Q_ENA_COUNT       1000
  77 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  78
  79 /* Maximun number of VSI */
  80 #define I40E_MAX_NUM_VSIS          (384UL)
  81
  82 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  83
  84 /* Flow control default timer */
  85 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  86
  87 /* Flow control default high water */
  88 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  89
  90 /* Flow control default low water */
  91 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  92
  93 /* Flow control enable fwd bit */
  94 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  95
  96 /* Receive Packet Buffer size */
  97 #define I40E_RXPBSIZE (968 * 1024)
  98
  99 /* Kilobytes shift */
 100 #define I40E_KILOSHIFT 10
 101
 102 /* Receive Average Packet Size in Byte*/
 103 #define I40E_PACKET_AVERAGE_SIZE 128
 104
 105 /* Mask of PF interrupt causes */
 106 #define I40E_PFINT_ICR0_ENA_MASK ( \
 107                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 108                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 109                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 110                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 111                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 112                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 113                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 114                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 115                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 116
 117 #define I40E_FLOW_TYPES ( \
 118         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 119         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 123         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 124         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 128         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 129
 130 /* Additional timesync values. */
 131 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 132 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 133 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 134 #define I40E_PRTTSYN_TSYNENA     0x80000000
 135 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 136 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 137
 138 #define I40E_MAX_PERCENT            100
 139 #define I40E_DEFAULT_DCB_APP_NUM    1
 140 #define I40E_DEFAULT_DCB_APP_PRIO   3
 141
 142 #define I40E_INSET_NONE            0x00000000000000000ULL
 143
 144 /* bit0 ~ bit 7 */
 145 #define I40E_INSET_DMAC            0x0000000000000001ULL
 146 #define I40E_INSET_SMAC            0x0000000000000002ULL
 147 #define I40E_INSET_VLAN_OUTER      0x0000000000000004ULL
 148 #define I40E_INSET_VLAN_INNER      0x0000000000000008ULL
 149 #define I40E_INSET_VLAN_TUNNEL     0x0000000000000010ULL
 150
 151 /* bit 8 ~ bit 15 */
 152 #define I40E_INSET_IPV4_SRC        0x0000000000000100ULL
 153 #define I40E_INSET_IPV4_DST        0x0000000000000200ULL
 154 #define I40E_INSET_IPV6_SRC        0x0000000000000400ULL
 155 #define I40E_INSET_IPV6_DST        0x0000000000000800ULL
 156 #define I40E_INSET_SRC_PORT        0x0000000000001000ULL
 157 #define I40E_INSET_DST_PORT        0x0000000000002000ULL
 158 #define I40E_INSET_SCTP_VT         0x0000000000004000ULL
 159
 160 /* bit 16 ~ bit 31 */
 161 #define I40E_INSET_IPV4_TOS        0x0000000000010000ULL
 162 #define I40E_INSET_IPV4_PROTO      0x0000000000020000ULL
 163 #define I40E_INSET_IPV4_TTL        0x0000000000040000ULL
 164 #define I40E_INSET_IPV6_TC         0x0000000000080000ULL
 165 #define I40E_INSET_IPV6_FLOW       0x0000000000100000ULL
 166 #define I40E_INSET_IPV6_NEXT_HDR   0x0000000000200000ULL
 167 #define I40E_INSET_IPV6_HOP_LIMIT  0x0000000000400000ULL
 168 #define I40E_INSET_TCP_FLAGS       0x0000000000800000ULL
 169
 170 /* bit 32 ~ bit 47, tunnel fields */
 171 #define I40E_INSET_TUNNEL_IPV4_DST       0x0000000100000000ULL
 172 #define I40E_INSET_TUNNEL_IPV6_DST       0x0000000200000000ULL
 173 #define I40E_INSET_TUNNEL_DMAC           0x0000000400000000ULL
 174 #define I40E_INSET_TUNNEL_SRC_PORT       0x0000000800000000ULL
 175 #define I40E_INSET_TUNNEL_DST_PORT       0x0000001000000000ULL
 176 #define I40E_INSET_TUNNEL_ID             0x0000002000000000ULL
 177
 178 /* bit 48 ~ bit 55 */
 179 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
 180
 181 /* bit 56 ~ bit 63, Flex Payload */
 182 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
 183 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
 184 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
 185 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
 186 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
 187 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
 188 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
 189 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
 190 #define I40E_INSET_FLEX_PAYLOAD \
 191         (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
 192         I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
 193         I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
 194         I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
 195
 196 /**
 197  * Below are values for writing un-exposed registers suggested
 198  * by silicon experts
 199  */
 200 /* Destination MAC address */
 201 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 202 /* Source MAC address */
 203 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 204 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 205 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 206 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 207 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 208 /* Single VLAN tag in the inner L2 header */
 209 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 210 /* Source IPv4 address */
 211 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 212 /* Destination IPv4 address */
 213 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 214 /* Source IPv4 address for X722 */
 215 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 216 /* Destination IPv4 address for X722 */
 217 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 218 /* IPv4 Protocol for X722 */
 219 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 220 /* IPv4 Time to Live for X722 */
 221 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 222 /* IPv4 Type of Service (TOS) */
 223 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 224 /* IPv4 Protocol */
 225 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 226 /* IPv4 Time to Live */
 227 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 228 /* Source IPv6 address */
 229 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 230 /* Destination IPv6 address */
 231 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 232 /* IPv6 Traffic Class (TC) */
 233 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 234 /* IPv6 Next Header */
 235 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 236 /* IPv6 Hop Limit */
 237 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 238 /* Source L4 port */
 239 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 240 /* Destination L4 port */
 241 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 242 /* SCTP verification tag */
 243 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 244 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 245 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 246 /* Source port of tunneling UDP */
 247 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 248 /* Destination port of tunneling UDP */
 249 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 250 /* UDP Tunneling ID, NVGRE/GRE key */
 251 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 252 /* Last ether type */
 253 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 254 /* Tunneling outer destination IPv4 address */
 255 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 256 /* Tunneling outer destination IPv6 address */
 257 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 258 /* 1st word of flex payload */
 259 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 260 /* 2nd word of flex payload */
 261 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 262 /* 3rd word of flex payload */
 263 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 264 /* 4th word of flex payload */
 265 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 266 /* 5th word of flex payload */
 267 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 268 /* 6th word of flex payload */
 269 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 270 /* 7th word of flex payload */
 271 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 272 /* 8th word of flex payload */
 273 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 274 /* all 8 words flex payload */
 275 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 276 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 277
 278 #define I40E_TRANSLATE_INSET 0
 279 #define I40E_TRANSLATE_REG   1
 280
 281 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 282 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 283 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 284 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 285 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 286 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 287
 288 #define I40E_GL_SWT_L2TAGCTRL(_i)             (0x001C0A70 + ((_i) * 4))
 289 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
 290 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK  \
 291         I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
 292
 293 /* PCI offset for querying capability */
 294 #define PCI_DEV_CAP_REG            0xA4
 295 /* PCI offset for enabling/disabling Extended Tag */
 296 #define PCI_DEV_CTRL_REG           0xA8
 297 /* Bit mask of Extended Tag capability */
 298 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 299 /* Bit shift of Extended Tag enable/disable */
 300 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 301 /* Bit mask of Extended Tag enable/disable */
 302 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 303
 304 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 305 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 306 static int i40e_dev_configure(struct rte_eth_dev *dev);
 307 static int i40e_dev_start(struct rte_eth_dev *dev);
 308 static void i40e_dev_stop(struct rte_eth_dev *dev);
 309 static void i40e_dev_close(struct rte_eth_dev *dev);
 310 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 311 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 312 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 313 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 314 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 315 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 316 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 317                                struct rte_eth_stats *stats);
 318 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 319                                struct rte_eth_xstat *xstats, unsigned n);
 320 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 321                                      struct rte_eth_xstat_name *xstats_names,
 322                                      unsigned limit);
 323 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 324 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 325                                             uint16_t queue_id,
 326                                             uint8_t stat_idx,
 327                                             uint8_t is_rx);
 328 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 329                                 char *fw_version, size_t fw_size);
 330 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 331                               struct rte_eth_dev_info *dev_info);
 332 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 333                                 uint16_t vlan_id,
 334                                 int on);
 335 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 336                               enum rte_vlan_type vlan_type,
 337                               uint16_t tpid);
 338 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 339 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 340                                       uint16_t queue,
 341                                       int on);
 342 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 343 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 344 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 345 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 346                               struct rte_eth_fc_conf *fc_conf);
 347 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 348                               struct rte_eth_fc_conf *fc_conf);
 349 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 350                                        struct rte_eth_pfc_conf *pfc_conf);
 351 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 352                           struct ether_addr *mac_addr,
 353                           uint32_t index,
 354                           uint32_t pool);
 355 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 356 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 357                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 358                                     uint16_t reta_size);
 359 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 360                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 361                                    uint16_t reta_size);
 362
 363 static int i40e_get_cap(struct i40e_hw *hw);
 364 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 365 static int i40e_pf_setup(struct i40e_pf *pf);
 366 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 367 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 368 static int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
 369 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 370 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 371                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 372 static void i40e_stat_update_48(struct i40e_hw *hw,
 373                                uint32_t hireg,
 374                                uint32_t loreg,
 375                                bool offset_loaded,
 376                                uint64_t *offset,
 377                                uint64_t *stat);
 378 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 379 static void i40e_dev_interrupt_handler(struct rte_intr_handle *handle,
 380                                        void *param);
 381 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 382                                 uint32_t base, uint32_t num);
 383 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 384 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 385                         uint32_t base);
 386 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 387                         uint16_t num);
 388 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 389 static int i40e_veb_release(struct i40e_veb *veb);
 390 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 391                                                 struct i40e_vsi *vsi);
 392 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 393 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 394 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 395                                              struct i40e_macvlan_filter *mv_f,
 396                                              int num,
 397                                              struct ether_addr *addr);
 398 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 399                                              struct i40e_macvlan_filter *mv_f,
 400                                              int num,
 401                                              uint16_t vlan);
 402 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 403 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 404                                     struct rte_eth_rss_conf *rss_conf);
 405 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 406                                       struct rte_eth_rss_conf *rss_conf);
 407 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 408                                         struct rte_eth_udp_tunnel *udp_tunnel);
 409 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 410                                         struct rte_eth_udp_tunnel *udp_tunnel);
 411 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 412 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 413                         struct rte_eth_ethertype_filter *filter,
 414                         bool add);
 415 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 416                                 enum rte_filter_op filter_op,
 417                                 void *arg);
 418 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 419                                 enum rte_filter_type filter_type,
 420                                 enum rte_filter_op filter_op,
 421                                 void *arg);
 422 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 423                                   struct rte_eth_dcb_info *dcb_info);
 424 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 425 static void i40e_configure_registers(struct i40e_hw *hw);
 426 static void i40e_hw_init(struct rte_eth_dev *dev);
 427 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 428 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 429                         struct rte_eth_mirror_conf *mirror_conf,
 430                         uint8_t sw_id, uint8_t on);
 431 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 432
 433 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 434 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 435 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 436                                            struct timespec *timestamp,
 437                                            uint32_t flags);
 438 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 439                                            struct timespec *timestamp);
 440 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 441
 442 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 443
 444 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 445                                    struct timespec *timestamp);
 446 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 447                                     const struct timespec *timestamp);
 448
 449 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 450                                          uint16_t queue_id);
 451 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 452                                           uint16_t queue_id);
 453
 454 static int i40e_get_regs(struct rte_eth_dev *dev,
 455                          struct rte_dev_reg_info *regs);
 456
 457 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 458
 459 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 460                            struct rte_dev_eeprom_info *eeprom);
 461
 462 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 463                                       struct ether_addr *mac_addr);
 464
 465 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 466
 467 static int i40e_ethertype_filter_convert(
 468         const struct rte_eth_ethertype_filter *input,
 469         struct i40e_ethertype_filter *filter);
 470 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 471                                    struct i40e_ethertype_filter *filter);
 472
 473 static int i40e_tunnel_filter_convert(
 474         struct i40e_aqc_add_remove_cloud_filters_element_data *cld_filter,
 475         struct i40e_tunnel_filter *tunnel_filter);
 476 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 477                                 struct i40e_tunnel_filter *tunnel_filter);
 478
 479 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 480 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 481 static void i40e_filter_restore(struct i40e_pf *pf);
 482
 483 static const struct rte_pci_id pci_id_i40e_map[] = {
 484         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 485         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 486         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 487         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 488         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 489         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 490         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 491         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 492         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 493         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 494         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 495         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 496         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 497         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 498         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 499         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 500         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 501         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 502         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 503         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 504         { .vendor_id = 0, /* sentinel */ },
 505 };
 506
 507 static const struct eth_dev_ops i40e_eth_dev_ops = {
 508         .dev_configure                = i40e_dev_configure,
 509         .dev_start                    = i40e_dev_start,
 510         .dev_stop                     = i40e_dev_stop,
 511         .dev_close                    = i40e_dev_close,
 512         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 513         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 514         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 515         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 516         .dev_set_link_up              = i40e_dev_set_link_up,
 517         .dev_set_link_down            = i40e_dev_set_link_down,
 518         .link_update                  = i40e_dev_link_update,
 519         .stats_get                    = i40e_dev_stats_get,
 520         .xstats_get                   = i40e_dev_xstats_get,
 521         .xstats_get_names             = i40e_dev_xstats_get_names,
 522         .stats_reset                  = i40e_dev_stats_reset,
 523         .xstats_reset                 = i40e_dev_stats_reset,
 524         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 525         .fw_version_get               = i40e_fw_version_get,
 526         .dev_infos_get                = i40e_dev_info_get,
 527         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 528         .vlan_filter_set              = i40e_vlan_filter_set,
 529         .vlan_tpid_set                = i40e_vlan_tpid_set,
 530         .vlan_offload_set             = i40e_vlan_offload_set,
 531         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 532         .vlan_pvid_set                = i40e_vlan_pvid_set,
 533         .rx_queue_start               = i40e_dev_rx_queue_start,
 534         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 535         .tx_queue_start               = i40e_dev_tx_queue_start,
 536         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 537         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 538         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 539         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 540         .rx_queue_release             = i40e_dev_rx_queue_release,
 541         .rx_queue_count               = i40e_dev_rx_queue_count,
 542         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 543         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 544         .tx_queue_release             = i40e_dev_tx_queue_release,
 545         .dev_led_on                   = i40e_dev_led_on,
 546         .dev_led_off                  = i40e_dev_led_off,
 547         .flow_ctrl_get                = i40e_flow_ctrl_get,
 548         .flow_ctrl_set                = i40e_flow_ctrl_set,
 549         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 550         .mac_addr_add                 = i40e_macaddr_add,
 551         .mac_addr_remove              = i40e_macaddr_remove,
 552         .reta_update                  = i40e_dev_rss_reta_update,
 553         .reta_query                   = i40e_dev_rss_reta_query,
 554         .rss_hash_update              = i40e_dev_rss_hash_update,
 555         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 556         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 557         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 558         .filter_ctrl                  = i40e_dev_filter_ctrl,
 559         .rxq_info_get                 = i40e_rxq_info_get,
 560         .txq_info_get                 = i40e_txq_info_get,
 561         .mirror_rule_set              = i40e_mirror_rule_set,
 562         .mirror_rule_reset            = i40e_mirror_rule_reset,
 563         .timesync_enable              = i40e_timesync_enable,
 564         .timesync_disable             = i40e_timesync_disable,
 565         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 566         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 567         .get_dcb_info                 = i40e_dev_get_dcb_info,
 568         .timesync_adjust_time         = i40e_timesync_adjust_time,
 569         .timesync_read_time           = i40e_timesync_read_time,
 570         .timesync_write_time          = i40e_timesync_write_time,
 571         .get_reg                      = i40e_get_regs,
 572         .get_eeprom_length            = i40e_get_eeprom_length,
 573         .get_eeprom                   = i40e_get_eeprom,
 574         .mac_addr_set                 = i40e_set_default_mac_addr,
 575         .mtu_set                      = i40e_dev_mtu_set,
 576 };
 577
 578 /* store statistics names and its offset in stats structure */
 579 struct rte_i40e_xstats_name_off {
 580         char name[RTE_ETH_XSTATS_NAME_SIZE];
 581         unsigned offset;
 582 };
 583
 584 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 585         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 586         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 587         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 588         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 589         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 590                 rx_unknown_protocol)},
 591         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 592         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 593         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 594         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 595 };
 596
 597 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 598                 sizeof(rte_i40e_stats_strings[0]))
 599
 600 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 601         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 602                 tx_dropped_link_down)},
 603         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 604         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 605                 illegal_bytes)},
 606         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 607         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 608                 mac_local_faults)},
 609         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 610                 mac_remote_faults)},
 611         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 612                 rx_length_errors)},
 613         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 614         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 615         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 616         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 617         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 618         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 619                 rx_size_127)},
 620         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 621                 rx_size_255)},
 622         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 623                 rx_size_511)},
 624         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 625                 rx_size_1023)},
 626         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 627                 rx_size_1522)},
 628         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 629                 rx_size_big)},
 630         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 631                 rx_undersize)},
 632         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 633                 rx_oversize)},
 634         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 635                 mac_short_packet_dropped)},
 636         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 637                 rx_fragments)},
 638         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 639         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 640         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 641                 tx_size_127)},
 642         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 643                 tx_size_255)},
 644         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 645                 tx_size_511)},
 646         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 647                 tx_size_1023)},
 648         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 649                 tx_size_1522)},
 650         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 651                 tx_size_big)},
 652         {"rx_flow_director_atr_match_packets",
 653                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 654         {"rx_flow_director_sb_match_packets",
 655                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 656         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 657                 tx_lpi_status)},
 658         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 659                 rx_lpi_status)},
 660         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 661                 tx_lpi_count)},
 662         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 663                 rx_lpi_count)},
 664 };
 665
 666 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 667                 sizeof(rte_i40e_hw_port_strings[0]))
 668
 669 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 670         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 671                 priority_xon_rx)},
 672         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 673                 priority_xoff_rx)},
 674 };
 675
 676 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 677                 sizeof(rte_i40e_rxq_prio_strings[0]))
 678
 679 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 680         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 681                 priority_xon_tx)},
 682         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 683                 priority_xoff_tx)},
 684         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 685                 priority_xon_2_xoff)},
 686 };
 687
 688 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 689                 sizeof(rte_i40e_txq_prio_strings[0]))
 690
 691 static struct eth_driver rte_i40e_pmd = {
 692         .pci_drv = {
 693                 .id_table = pci_id_i40e_map,
 694                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 695                 .probe = rte_eth_dev_pci_probe,
 696                 .remove = rte_eth_dev_pci_remove,
 697         },
 698         .eth_dev_init = eth_i40e_dev_init,
 699         .eth_dev_uninit = eth_i40e_dev_uninit,
 700         .dev_private_size = sizeof(struct i40e_adapter),
 701 };
 702
 703 static inline int
 704 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 705                                      struct rte_eth_link *link)
 706 {
 707         struct rte_eth_link *dst = link;
 708         struct rte_eth_link *src = &(dev->data->dev_link);
 709
 710         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 711                                         *(uint64_t *)src) == 0)
 712                 return -1;
 713
 714         return 0;
 715 }
 716
 717 static inline int
 718 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 719                                       struct rte_eth_link *link)
 720 {
 721         struct rte_eth_link *dst = &(dev->data->dev_link);
 722         struct rte_eth_link *src = link;
 723
 724         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 725                                         *(uint64_t *)src) == 0)
 726                 return -1;
 727
 728         return 0;
 729 }
 730
 731 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd.pci_drv);
 732 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 733 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio");
 734
 735 #ifndef I40E_GLQF_ORT
 736 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 737 #endif
 738 #ifndef I40E_GLQF_PIT
 739 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 740 #endif
 741
 742 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 743 {
 744         /*
 745          * Initialize registers for flexible payload, which should be set by NVM.
 746          * This should be removed from code once it is fixed in NVM.
 747          */
 748         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 749         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 750         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 751         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 752         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 753         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 754         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 755         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 756         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 757         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 758         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 759         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 760
 761         /* Initialize registers for parsing packet type of QinQ */
 762         I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 763         I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 764 }
 765
 766 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 767
 768 /*
 769  * Add a ethertype filter to drop all flow control frames transmitted
 770  * from VSIs.
 771 */
 772 static void
 773 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 774 {
 775         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 776         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 777                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 778                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 779         int ret;
 780
 781         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 782                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 783                                 pf->main_vsi_seid, 0,
 784                                 TRUE, NULL, NULL);
 785         if (ret)
 786                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 787                                   " frames from VSIs.");
 788 }
 789
 790 static int
 791 floating_veb_list_handler(__rte_unused const char *key,
 792                           const char *floating_veb_value,
 793                           void *opaque)
 794 {
 795         int idx = 0;
 796         unsigned int count = 0;
 797         char *end = NULL;
 798         int min, max;
 799         bool *vf_floating_veb = opaque;
 800
 801         while (isblank(*floating_veb_value))
 802                 floating_veb_value++;
 803
 804         /* Reset floating VEB configuration for VFs */
 805         for (idx = 0; idx < I40E_MAX_VF; idx++)
 806                 vf_floating_veb[idx] = false;
 807
 808         min = I40E_MAX_VF;
 809         do {
 810                 while (isblank(*floating_veb_value))
 811                         floating_veb_value++;
 812                 if (*floating_veb_value == '\0')
 813                         return -1;
 814                 errno = 0;
 815                 idx = strtoul(floating_veb_value, &end, 10);
 816                 if (errno || end == NULL)
 817                         return -1;
 818                 while (isblank(*end))
 819                         end++;
 820                 if (*end == '-') {
 821                         min = idx;
 822                 } else if ((*end == ';') || (*end == '\0')) {
 823                         max = idx;
 824                         if (min == I40E_MAX_VF)
 825                                 min = idx;
 826                         if (max >= I40E_MAX_VF)
 827                                 max = I40E_MAX_VF - 1;
 828                         for (idx = min; idx <= max; idx++) {
 829                                 vf_floating_veb[idx] = true;
 830                                 count++;
 831                         }
 832                         min = I40E_MAX_VF;
 833                 } else {
 834                         return -1;
 835                 }
 836                 floating_veb_value = end + 1;
 837         } while (*end != '\0');
 838
 839         if (count == 0)
 840                 return -1;
 841
 842         return 0;
 843 }
 844
 845 static void
 846 config_vf_floating_veb(struct rte_devargs *devargs,
 847                        uint16_t floating_veb,
 848                        bool *vf_floating_veb)
 849 {
 850         struct rte_kvargs *kvlist;
 851         int i;
 852         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 853
 854         if (!floating_veb)
 855                 return;
 856         /* All the VFs attach to the floating VEB by default
 857          * when the floating VEB is enabled.
 858          */
 859         for (i = 0; i < I40E_MAX_VF; i++)
 860                 vf_floating_veb[i] = true;
 861
 862         if (devargs == NULL)
 863                 return;
 864
 865         kvlist = rte_kvargs_parse(devargs->args, NULL);
 866         if (kvlist == NULL)
 867                 return;
 868
 869         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 870                 rte_kvargs_free(kvlist);
 871                 return;
 872         }
 873         /* When the floating_veb_list parameter exists, all the VFs
 874          * will attach to the legacy VEB firstly, then configure VFs
 875          * to the floating VEB according to the floating_veb_list.
 876          */
 877         if (rte_kvargs_process(kvlist, floating_veb_list,
 878                                floating_veb_list_handler,
 879                                vf_floating_veb) < 0) {
 880                 rte_kvargs_free(kvlist);
 881                 return;
 882         }
 883         rte_kvargs_free(kvlist);
 884 }
 885
 886 static int
 887 i40e_check_floating_handler(__rte_unused const char *key,
 888                             const char *value,
 889                             __rte_unused void *opaque)
 890 {
 891         if (strcmp(value, "1"))
 892                 return -1;
 893
 894         return 0;
 895 }
 896
 897 static int
 898 is_floating_veb_supported(struct rte_devargs *devargs)
 899 {
 900         struct rte_kvargs *kvlist;
 901         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 902
 903         if (devargs == NULL)
 904                 return 0;
 905
 906         kvlist = rte_kvargs_parse(devargs->args, NULL);
 907         if (kvlist == NULL)
 908                 return 0;
 909
 910         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 911                 rte_kvargs_free(kvlist);
 912                 return 0;
 913         }
 914         /* Floating VEB is enabled when there's key-value:
 915          * enable_floating_veb=1
 916          */
 917         if (rte_kvargs_process(kvlist, floating_veb_key,
 918                                i40e_check_floating_handler, NULL) < 0) {
 919                 rte_kvargs_free(kvlist);
 920                 return 0;
 921         }
 922         rte_kvargs_free(kvlist);
 923
 924         return 1;
 925 }
 926
 927 static void
 928 config_floating_veb(struct rte_eth_dev *dev)
 929 {
 930         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
 931         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 932         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 933
 934         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 935
 936         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 937                 pf->floating_veb =
 938                         is_floating_veb_supported(pci_dev->device.devargs);
 939                 config_vf_floating_veb(pci_dev->device.devargs,
 940                                        pf->floating_veb,
 941                                        pf->floating_veb_list);
 942         } else {
 943                 pf->floating_veb = false;
 944         }
 945 }
 946
 947 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 948 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 949
 950 static int
 951 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 952 {
 953         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 954         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 955         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 956         int ret;
 957
 958         struct rte_hash_parameters ethertype_hash_params = {
 959                 .name = ethertype_hash_name,
 960                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 961                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 962                 .hash_func = rte_hash_crc,
 963         };
 964
 965         /* Initialize ethertype filter rule list and hash */
 966         TAILQ_INIT(&ethertype_rule->ethertype_list);
 967         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 968                  "ethertype_%s", dev->data->name);
 969         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 970         if (!ethertype_rule->hash_table) {
 971                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 972                 return -EINVAL;
 973         }
 974         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 975                                        sizeof(struct i40e_ethertype_filter *) *
 976                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 977                                        0);
 978         if (!ethertype_rule->hash_map) {
 979                 PMD_INIT_LOG(ERR,
 980                              "Failed to allocate memory for ethertype hash map!");
 981                 ret = -ENOMEM;
 982                 goto err_ethertype_hash_map_alloc;
 983         }
 984
 985         return 0;
 986
 987 err_ethertype_hash_map_alloc:
 988         rte_hash_free(ethertype_rule->hash_table);
 989
 990         return ret;
 991 }
 992
 993 static int
 994 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 995 {
 996         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 997         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 998         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 999         int ret;
1000
1001         struct rte_hash_parameters tunnel_hash_params = {
1002                 .name = tunnel_hash_name,
1003                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1004                 .key_len = sizeof(struct i40e_tunnel_filter_input),
1005                 .hash_func = rte_hash_crc,
1006         };
1007
1008         /* Initialize tunnel filter rule list and hash */
1009         TAILQ_INIT(&tunnel_rule->tunnel_list);
1010         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1011                  "tunnel_%s", dev->data->name);
1012         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1013         if (!tunnel_rule->hash_table) {
1014                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1015                 return -EINVAL;
1016         }
1017         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1018                                     sizeof(struct i40e_tunnel_filter *) *
1019                                     I40E_MAX_TUNNEL_FILTER_NUM,
1020                                     0);
1021         if (!tunnel_rule->hash_map) {
1022                 PMD_INIT_LOG(ERR,
1023                              "Failed to allocate memory for tunnel hash map!");
1024                 ret = -ENOMEM;
1025                 goto err_tunnel_hash_map_alloc;
1026         }
1027
1028         return 0;
1029
1030 err_tunnel_hash_map_alloc:
1031         rte_hash_free(tunnel_rule->hash_table);
1032
1033         return ret;
1034 }
1035
1036 static int
1037 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1038 {
1039         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1040         struct i40e_fdir_info *fdir_info = &pf->fdir;
1041         char fdir_hash_name[RTE_HASH_NAMESIZE];
1042         int ret;
1043
1044         struct rte_hash_parameters fdir_hash_params = {
1045                 .name = fdir_hash_name,
1046                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1047                 .key_len = sizeof(struct rte_eth_fdir_input),
1048                 .hash_func = rte_hash_crc,
1049         };
1050
1051         /* Initialize flow director filter rule list and hash */
1052         TAILQ_INIT(&fdir_info->fdir_list);
1053         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1054                  "fdir_%s", dev->data->name);
1055         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1056         if (!fdir_info->hash_table) {
1057                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1058                 return -EINVAL;
1059         }
1060         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1061                                           sizeof(struct i40e_fdir_filter *) *
1062                                           I40E_MAX_FDIR_FILTER_NUM,
1063                                           0);
1064         if (!fdir_info->hash_map) {
1065                 PMD_INIT_LOG(ERR,
1066                              "Failed to allocate memory for fdir hash map!");
1067                 ret = -ENOMEM;
1068                 goto err_fdir_hash_map_alloc;
1069         }
1070         return 0;
1071
1072 err_fdir_hash_map_alloc:
1073         rte_hash_free(fdir_info->hash_table);
1074
1075         return ret;
1076 }
1077
1078 static int
1079 eth_i40e_dev_init(struct rte_eth_dev *dev)
1080 {
1081         struct rte_pci_device *pci_dev;
1082         struct rte_intr_handle *intr_handle;
1083         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1084         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1085         struct i40e_vsi *vsi;
1086         int ret;
1087         uint32_t len;
1088         uint8_t aq_fail = 0;
1089
1090         PMD_INIT_FUNC_TRACE();
1091
1092         dev->dev_ops = &i40e_eth_dev_ops;
1093         dev->rx_pkt_burst = i40e_recv_pkts;
1094         dev->tx_pkt_burst = i40e_xmit_pkts;
1095         dev->tx_pkt_prepare = i40e_prep_pkts;
1096
1097         /* for secondary processes, we don't initialise any further as primary
1098          * has already done this work. Only check we don't need a different
1099          * RX function */
1100         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1101                 i40e_set_rx_function(dev);
1102                 i40e_set_tx_function(dev);
1103                 return 0;
1104         }
1105         pci_dev = I40E_DEV_TO_PCI(dev);
1106         intr_handle = &pci_dev->intr_handle;
1107
1108         rte_eth_copy_pci_info(dev, pci_dev);
1109         dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
1110
1111         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1112         pf->adapter->eth_dev = dev;
1113         pf->dev_data = dev->data;
1114
1115         hw->back = I40E_PF_TO_ADAPTER(pf);
1116         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1117         if (!hw->hw_addr) {
1118                 PMD_INIT_LOG(ERR, "Hardware is not available, "
1119                              "as address is NULL");
1120                 return -ENODEV;
1121         }
1122
1123         hw->vendor_id = pci_dev->id.vendor_id;
1124         hw->device_id = pci_dev->id.device_id;
1125         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1126         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1127         hw->bus.device = pci_dev->addr.devid;
1128         hw->bus.func = pci_dev->addr.function;
1129         hw->adapter_stopped = 0;
1130
1131         /* Make sure all is clean before doing PF reset */
1132         i40e_clear_hw(hw);
1133
1134         /* Initialize the hardware */
1135         i40e_hw_init(dev);
1136
1137         /* Reset here to make sure all is clean for each PF */
1138         ret = i40e_pf_reset(hw);
1139         if (ret) {
1140                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1141                 return ret;
1142         }
1143
1144         /* Initialize the shared code (base driver) */
1145         ret = i40e_init_shared_code(hw);
1146         if (ret) {
1147                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1148                 return ret;
1149         }
1150
1151         /*
1152          * To work around the NVM issue, initialize registers
1153          * for flexible payload and packet type of QinQ by
1154          * software. It should be removed once issues are fixed
1155          * in NVM.
1156          */
1157         i40e_GLQF_reg_init(hw);
1158
1159         /* Initialize the input set for filters (hash and fd) to default value */
1160         i40e_filter_input_set_init(pf);
1161
1162         /* Initialize the parameters for adminq */
1163         i40e_init_adminq_parameter(hw);
1164         ret = i40e_init_adminq(hw);
1165         if (ret != I40E_SUCCESS) {
1166                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1167                 return -EIO;
1168         }
1169         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1170                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1171                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1172                      ((hw->nvm.version >> 12) & 0xf),
1173                      ((hw->nvm.version >> 4) & 0xff),
1174                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1175
1176         /* Need the special FW version to support floating VEB */
1177         config_floating_veb(dev);
1178         /* Clear PXE mode */
1179         i40e_clear_pxe_mode(hw);
1180         ret = i40e_dev_sync_phy_type(hw);
1181         if (ret) {
1182                 PMD_INIT_LOG(ERR, "Failed to sync phy type: %d", ret);
1183                 goto err_sync_phy_type;
1184         }
1185         /*
1186          * On X710, performance number is far from the expectation on recent
1187          * firmware versions. The fix for this issue may not be integrated in
1188          * the following firmware version. So the workaround in software driver
1189          * is needed. It needs to modify the initial values of 3 internal only
1190          * registers. Note that the workaround can be removed when it is fixed
1191          * in firmware in the future.
1192          */
1193         i40e_configure_registers(hw);
1194
1195         /* Get hw capabilities */
1196         ret = i40e_get_cap(hw);
1197         if (ret != I40E_SUCCESS) {
1198                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1199                 goto err_get_capabilities;
1200         }
1201
1202         /* Initialize parameters for PF */
1203         ret = i40e_pf_parameter_init(dev);
1204         if (ret != 0) {
1205                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1206                 goto err_parameter_init;
1207         }
1208
1209         /* Initialize the queue management */
1210         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1211         if (ret < 0) {
1212                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1213                 goto err_qp_pool_init;
1214         }
1215         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1216                                 hw->func_caps.num_msix_vectors - 1);
1217         if (ret < 0) {
1218                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1219                 goto err_msix_pool_init;
1220         }
1221
1222         /* Initialize lan hmc */
1223         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1224                                 hw->func_caps.num_rx_qp, 0, 0);
1225         if (ret != I40E_SUCCESS) {
1226                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1227                 goto err_init_lan_hmc;
1228         }
1229
1230         /* Configure lan hmc */
1231         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1232         if (ret != I40E_SUCCESS) {
1233                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1234                 goto err_configure_lan_hmc;
1235         }
1236
1237         /* Get and check the mac address */
1238         i40e_get_mac_addr(hw, hw->mac.addr);
1239         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1240                 PMD_INIT_LOG(ERR, "mac address is not valid");
1241                 ret = -EIO;
1242                 goto err_get_mac_addr;
1243         }
1244         /* Copy the permanent MAC address */
1245         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1246                         (struct ether_addr *) hw->mac.perm_addr);
1247
1248         /* Disable flow control */
1249         hw->fc.requested_mode = I40E_FC_NONE;
1250         i40e_set_fc(hw, &aq_fail, TRUE);
1251
1252         /* Set the global registers with default ether type value */
1253         ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1254         if (ret != I40E_SUCCESS) {
1255                 PMD_INIT_LOG(ERR, "Failed to set the default outer "
1256                              "VLAN ether type");
1257                 goto err_setup_pf_switch;
1258         }
1259
1260         /* PF setup, which includes VSI setup */
1261         ret = i40e_pf_setup(pf);
1262         if (ret) {
1263                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1264                 goto err_setup_pf_switch;
1265         }
1266
1267         /* reset all stats of the device, including pf and main vsi */
1268         i40e_dev_stats_reset(dev);
1269
1270         vsi = pf->main_vsi;
1271
1272         /* Disable double vlan by default */
1273         i40e_vsi_config_double_vlan(vsi, FALSE);
1274
1275         /* Disable S-TAG identification when floating_veb is disabled */
1276         if (!pf->floating_veb) {
1277                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1278                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1279                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1280                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1281                 }
1282         }
1283
1284         if (!vsi->max_macaddrs)
1285                 len = ETHER_ADDR_LEN;
1286         else
1287                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1288
1289         /* Should be after VSI initialized */
1290         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1291         if (!dev->data->mac_addrs) {
1292                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
1293                                         "for storing mac address");
1294                 goto err_mac_alloc;
1295         }
1296         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1297                                         &dev->data->mac_addrs[0]);
1298
1299         /* initialize pf host driver to setup SRIOV resource if applicable */
1300         i40e_pf_host_init(dev);
1301
1302         /* register callback func to eal lib */
1303         rte_intr_callback_register(intr_handle,
1304                                    i40e_dev_interrupt_handler, dev);
1305
1306         /* configure and enable device interrupt */
1307         i40e_pf_config_irq0(hw, TRUE);
1308         i40e_pf_enable_irq0(hw);
1309
1310         /* enable uio intr after callback register */
1311         rte_intr_enable(intr_handle);
1312         /*
1313          * Add an ethertype filter to drop all flow control frames transmitted
1314          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1315          * frames to wire.
1316          */
1317         i40e_add_tx_flow_control_drop_filter(pf);
1318
1319         /* Set the max frame size to 0x2600 by default,
1320          * in case other drivers changed the default value.
1321          */
1322         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1323
1324         /* initialize mirror rule list */
1325         TAILQ_INIT(&pf->mirror_list);
1326
1327         /* Init dcb to sw mode by default */
1328         ret = i40e_dcb_init_configure(dev, TRUE);
1329         if (ret != I40E_SUCCESS) {
1330                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1331                 pf->flags &= ~I40E_FLAG_DCB;
1332         }
1333
1334         ret = i40e_init_ethtype_filter_list(dev);
1335         if (ret < 0)
1336                 goto err_init_ethtype_filter_list;
1337         ret = i40e_init_tunnel_filter_list(dev);
1338         if (ret < 0)
1339                 goto err_init_tunnel_filter_list;
1340         ret = i40e_init_fdir_filter_list(dev);
1341         if (ret < 0)
1342                 goto err_init_fdir_filter_list;
1343
1344         return 0;
1345
1346 err_init_fdir_filter_list:
1347         rte_free(pf->tunnel.hash_table);
1348         rte_free(pf->tunnel.hash_map);
1349 err_init_tunnel_filter_list:
1350         rte_free(pf->ethertype.hash_table);
1351         rte_free(pf->ethertype.hash_map);
1352 err_init_ethtype_filter_list:
1353         rte_free(dev->data->mac_addrs);
1354 err_mac_alloc:
1355         i40e_vsi_release(pf->main_vsi);
1356 err_setup_pf_switch:
1357 err_get_mac_addr:
1358 err_configure_lan_hmc:
1359         (void)i40e_shutdown_lan_hmc(hw);
1360 err_init_lan_hmc:
1361         i40e_res_pool_destroy(&pf->msix_pool);
1362 err_msix_pool_init:
1363         i40e_res_pool_destroy(&pf->qp_pool);
1364 err_qp_pool_init:
1365 err_parameter_init:
1366 err_get_capabilities:
1367 err_sync_phy_type:
1368         (void)i40e_shutdown_adminq(hw);
1369
1370         return ret;
1371 }
1372
1373 static void
1374 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1375 {
1376         struct i40e_ethertype_filter *p_ethertype;
1377         struct i40e_ethertype_rule *ethertype_rule;
1378
1379         ethertype_rule = &pf->ethertype;
1380         /* Remove all ethertype filter rules and hash */
1381         if (ethertype_rule->hash_map)
1382                 rte_free(ethertype_rule->hash_map);
1383         if (ethertype_rule->hash_table)
1384                 rte_hash_free(ethertype_rule->hash_table);
1385
1386         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1387                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1388                              p_ethertype, rules);
1389                 rte_free(p_ethertype);
1390         }
1391 }
1392
1393 static void
1394 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1395 {
1396         struct i40e_tunnel_filter *p_tunnel;
1397         struct i40e_tunnel_rule *tunnel_rule;
1398
1399         tunnel_rule = &pf->tunnel;
1400         /* Remove all tunnel director rules and hash */
1401         if (tunnel_rule->hash_map)
1402                 rte_free(tunnel_rule->hash_map);
1403         if (tunnel_rule->hash_table)
1404                 rte_hash_free(tunnel_rule->hash_table);
1405
1406         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1407                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1408                 rte_free(p_tunnel);
1409         }
1410 }
1411
1412 static void
1413 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1414 {
1415         struct i40e_fdir_filter *p_fdir;
1416         struct i40e_fdir_info *fdir_info;
1417
1418         fdir_info = &pf->fdir;
1419         /* Remove all flow director rules and hash */
1420         if (fdir_info->hash_map)
1421                 rte_free(fdir_info->hash_map);
1422         if (fdir_info->hash_table)
1423                 rte_hash_free(fdir_info->hash_table);
1424
1425         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1426                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1427                 rte_free(p_fdir);
1428         }
1429 }
1430
1431 static int
1432 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1433 {
1434         struct i40e_pf *pf;
1435         struct rte_pci_device *pci_dev;
1436         struct rte_intr_handle *intr_handle;
1437         struct i40e_hw *hw;
1438         struct i40e_filter_control_settings settings;
1439         int ret;
1440         uint8_t aq_fail = 0;
1441
1442         PMD_INIT_FUNC_TRACE();
1443
1444         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1445                 return 0;
1446
1447         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1448         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1449         pci_dev = I40E_DEV_TO_PCI(dev);
1450         intr_handle = &pci_dev->intr_handle;
1451
1452         if (hw->adapter_stopped == 0)
1453                 i40e_dev_close(dev);
1454
1455         dev->dev_ops = NULL;
1456         dev->rx_pkt_burst = NULL;
1457         dev->tx_pkt_burst = NULL;
1458
1459         /* Clear PXE mode */
1460         i40e_clear_pxe_mode(hw);
1461
1462         /* Unconfigure filter control */
1463         memset(&settings, 0, sizeof(settings));
1464         ret = i40e_set_filter_control(hw, &settings);
1465         if (ret)
1466                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1467                                         ret);
1468
1469         /* Disable flow control */
1470         hw->fc.requested_mode = I40E_FC_NONE;
1471         i40e_set_fc(hw, &aq_fail, TRUE);
1472
1473         /* uninitialize pf host driver */
1474         i40e_pf_host_uninit(dev);
1475
1476         rte_free(dev->data->mac_addrs);
1477         dev->data->mac_addrs = NULL;
1478
1479         /* disable uio intr before callback unregister */
1480         rte_intr_disable(intr_handle);
1481
1482         /* register callback func to eal lib */
1483         rte_intr_callback_unregister(intr_handle,
1484                                      i40e_dev_interrupt_handler, dev);
1485
1486         i40e_rm_ethtype_filter_list(pf);
1487         i40e_rm_tunnel_filter_list(pf);
1488         i40e_rm_fdir_filter_list(pf);
1489
1490         return 0;
1491 }
1492
1493 static int
1494 i40e_dev_configure(struct rte_eth_dev *dev)
1495 {
1496         struct i40e_adapter *ad =
1497                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1498         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1499         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1500         int i, ret;
1501
1502         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1503          * bulk allocation or vector Rx preconditions we will reset it.
1504          */
1505         ad->rx_bulk_alloc_allowed = true;
1506         ad->rx_vec_allowed = true;
1507         ad->tx_simple_allowed = true;
1508         ad->tx_vec_allowed = true;
1509
1510         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1511                 ret = i40e_fdir_setup(pf);
1512                 if (ret != I40E_SUCCESS) {
1513                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1514                         return -ENOTSUP;
1515                 }
1516                 ret = i40e_fdir_configure(dev);
1517                 if (ret < 0) {
1518                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1519                         goto err;
1520                 }
1521         } else
1522                 i40e_fdir_teardown(pf);
1523
1524         ret = i40e_dev_init_vlan(dev);
1525         if (ret < 0)
1526                 goto err;
1527
1528         /* VMDQ setup.
1529          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1530          *  RSS setting have different requirements.
1531          *  General PMD driver call sequence are NIC init, configure,
1532          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1533          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1534          *  applicable. So, VMDQ setting has to be done before
1535          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1536          *  For RSS setting, it will try to calculate actual configured RX queue
1537          *  number, which will be available after rx_queue_setup(). dev_start()
1538          *  function is good to place RSS setup.
1539          */
1540         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1541                 ret = i40e_vmdq_setup(dev);
1542                 if (ret)
1543                         goto err;
1544         }
1545
1546         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1547                 ret = i40e_dcb_setup(dev);
1548                 if (ret) {
1549                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1550                         goto err_dcb;
1551                 }
1552         }
1553
1554         return 0;
1555
1556 err_dcb:
1557         /* need to release vmdq resource if exists */
1558         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1559                 i40e_vsi_release(pf->vmdq[i].vsi);
1560                 pf->vmdq[i].vsi = NULL;
1561         }
1562         rte_free(pf->vmdq);
1563         pf->vmdq = NULL;
1564 err:
1565         /* need to release fdir resource if exists */
1566         i40e_fdir_teardown(pf);
1567         return ret;
1568 }
1569
1570 void
1571 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1572 {
1573         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1574         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1575         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1576         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1577         uint16_t msix_vect = vsi->msix_intr;
1578         uint16_t i;
1579
1580         for (i = 0; i < vsi->nb_qps; i++) {
1581                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1582                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1583                 rte_wmb();
1584         }
1585
1586         if (vsi->type != I40E_VSI_SRIOV) {
1587                 if (!rte_intr_allow_others(intr_handle)) {
1588                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1589                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1590                         I40E_WRITE_REG(hw,
1591                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1592                                        0);
1593                 } else {
1594                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1595                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1596                         I40E_WRITE_REG(hw,
1597                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1598                                                        msix_vect - 1), 0);
1599                 }
1600         } else {
1601                 uint32_t reg;
1602                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1603                         vsi->user_param + (msix_vect - 1);
1604
1605                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1606                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1607         }
1608         I40E_WRITE_FLUSH(hw);
1609 }
1610
1611 static void
1612 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1613                        int base_queue, int nb_queue)
1614 {
1615         int i;
1616         uint32_t val;
1617         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1618
1619         /* Bind all RX queues to allocated MSIX interrupt */
1620         for (i = 0; i < nb_queue; i++) {
1621                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1622                         I40E_QINT_RQCTL_ITR_INDX_MASK |
1623                         ((base_queue + i + 1) <<
1624                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1625                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1626                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1627
1628                 if (i == nb_queue - 1)
1629                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1630                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1631         }
1632
1633         /* Write first RX queue to Link list register as the head element */
1634         if (vsi->type != I40E_VSI_SRIOV) {
1635                 uint16_t interval =
1636                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1637
1638                 if (msix_vect == I40E_MISC_VEC_ID) {
1639                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1640                                        (base_queue <<
1641                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1642                                        (0x0 <<
1643                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1644                         I40E_WRITE_REG(hw,
1645                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1646                                        interval);
1647                 } else {
1648                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1649                                        (base_queue <<
1650                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1651                                        (0x0 <<
1652                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1653                         I40E_WRITE_REG(hw,
1654                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1655                                                        msix_vect - 1),
1656                                        interval);
1657                 }
1658         } else {
1659                 uint32_t reg;
1660
1661                 if (msix_vect == I40E_MISC_VEC_ID) {
1662                         I40E_WRITE_REG(hw,
1663                                        I40E_VPINT_LNKLST0(vsi->user_param),
1664                                        (base_queue <<
1665                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1666                                        (0x0 <<
1667                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1668                 } else {
1669                         /* num_msix_vectors_vf needs to minus irq0 */
1670                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1671                                 vsi->user_param + (msix_vect - 1);
1672
1673                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1674                                        (base_queue <<
1675                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1676                                        (0x0 <<
1677                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1678                 }
1679         }
1680
1681         I40E_WRITE_FLUSH(hw);
1682 }
1683
1684 void
1685 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
1686 {
1687         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1688         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1689         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1690         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1691         uint16_t msix_vect = vsi->msix_intr;
1692         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1693         uint16_t queue_idx = 0;
1694         int record = 0;
1695         uint32_t val;
1696         int i;
1697
1698         for (i = 0; i < vsi->nb_qps; i++) {
1699                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1700                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1701         }
1702
1703         /* INTENA flag is not auto-cleared for interrupt */
1704         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1705         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1706                 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1707                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1708         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1709
1710         /* VF bind interrupt */
1711         if (vsi->type == I40E_VSI_SRIOV) {
1712                 __vsi_queues_bind_intr(vsi, msix_vect,
1713                                        vsi->base_queue, vsi->nb_qps);
1714                 return;
1715         }
1716
1717         /* PF & VMDq bind interrupt */
1718         if (rte_intr_dp_is_en(intr_handle)) {
1719                 if (vsi->type == I40E_VSI_MAIN) {
1720                         queue_idx = 0;
1721                         record = 1;
1722                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1723                         struct i40e_vsi *main_vsi =
1724                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1725                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1726                         record = 1;
1727                 }
1728         }
1729
1730         for (i = 0; i < vsi->nb_used_qps; i++) {
1731                 if (nb_msix <= 1) {
1732                         if (!rte_intr_allow_others(intr_handle))
1733                                 /* allow to share MISC_VEC_ID */
1734                                 msix_vect = I40E_MISC_VEC_ID;
1735
1736                         /* no enough msix_vect, map all to one */
1737                         __vsi_queues_bind_intr(vsi, msix_vect,
1738                                                vsi->base_queue + i,
1739                                                vsi->nb_used_qps - i);
1740                         for (; !!record && i < vsi->nb_used_qps; i++)
1741                                 intr_handle->intr_vec[queue_idx + i] =
1742                                         msix_vect;
1743                         break;
1744                 }
1745                 /* 1:1 queue/msix_vect mapping */
1746                 __vsi_queues_bind_intr(vsi, msix_vect,
1747                                        vsi->base_queue + i, 1);
1748                 if (!!record)
1749                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1750
1751                 msix_vect++;
1752                 nb_msix--;
1753         }
1754 }
1755
1756 static void
1757 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1758 {
1759         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1760         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1761         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1762         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1763         uint16_t interval = i40e_calc_itr_interval(\
1764                 RTE_LIBRTE_I40E_ITR_INTERVAL);
1765         uint16_t msix_intr, i;
1766
1767         if (rte_intr_allow_others(intr_handle))
1768                 for (i = 0; i < vsi->nb_msix; i++) {
1769                         msix_intr = vsi->msix_intr + i;
1770                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1771                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1772                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1773                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1774                                 (interval <<
1775                                  I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1776                 }
1777         else
1778                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1779                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1780                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1781                                (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1782                                (interval <<
1783                                 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1784
1785         I40E_WRITE_FLUSH(hw);
1786 }
1787
1788 static void
1789 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1790 {
1791         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1792         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1793         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1794         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1795         uint16_t msix_intr, i;
1796
1797         if (rte_intr_allow_others(intr_handle))
1798                 for (i = 0; i < vsi->nb_msix; i++) {
1799                         msix_intr = vsi->msix_intr + i;
1800                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1801                                        0);
1802                 }
1803         else
1804                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1805
1806         I40E_WRITE_FLUSH(hw);
1807 }
1808
1809 static inline uint8_t
1810 i40e_parse_link_speeds(uint16_t link_speeds)
1811 {
1812         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1813
1814         if (link_speeds & ETH_LINK_SPEED_40G)
1815                 link_speed |= I40E_LINK_SPEED_40GB;
1816         if (link_speeds & ETH_LINK_SPEED_25G)
1817                 link_speed |= I40E_LINK_SPEED_25GB;
1818         if (link_speeds & ETH_LINK_SPEED_20G)
1819                 link_speed |= I40E_LINK_SPEED_20GB;
1820         if (link_speeds & ETH_LINK_SPEED_10G)
1821                 link_speed |= I40E_LINK_SPEED_10GB;
1822         if (link_speeds & ETH_LINK_SPEED_1G)
1823                 link_speed |= I40E_LINK_SPEED_1GB;
1824         if (link_speeds & ETH_LINK_SPEED_100M)
1825                 link_speed |= I40E_LINK_SPEED_100MB;
1826
1827         return link_speed;
1828 }
1829
1830 static int
1831 i40e_phy_conf_link(struct i40e_hw *hw,
1832                    uint8_t abilities,
1833                    uint8_t force_speed)
1834 {
1835         enum i40e_status_code status;
1836         struct i40e_aq_get_phy_abilities_resp phy_ab;
1837         struct i40e_aq_set_phy_config phy_conf;
1838         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1839                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1840                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1841                         I40E_AQ_PHY_FLAG_LOW_POWER;
1842         const uint8_t advt = I40E_LINK_SPEED_40GB |
1843                         I40E_LINK_SPEED_25GB |
1844                         I40E_LINK_SPEED_10GB |
1845                         I40E_LINK_SPEED_1GB |
1846                         I40E_LINK_SPEED_100MB;
1847         int ret = -ENOTSUP;
1848
1849
1850         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1851                                               NULL);
1852         if (status)
1853                 return ret;
1854
1855         memset(&phy_conf, 0, sizeof(phy_conf));
1856
1857         /* bits 0-2 use the values from get_phy_abilities_resp */
1858         abilities &= ~mask;
1859         abilities |= phy_ab.abilities & mask;
1860
1861         /* update ablities and speed */
1862         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1863                 phy_conf.link_speed = advt;
1864         else
1865                 phy_conf.link_speed = force_speed;
1866
1867         phy_conf.abilities = abilities;
1868
1869         /* use get_phy_abilities_resp value for the rest */
1870         phy_conf.phy_type = phy_ab.phy_type;
1871         phy_conf.phy_type_ext = phy_ab.phy_type_ext;
1872         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1873         phy_conf.eee_capability = phy_ab.eee_capability;
1874         phy_conf.eeer = phy_ab.eeer_val;
1875         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1876
1877         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1878                     phy_ab.abilities, phy_ab.link_speed);
1879         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
1880                     phy_conf.abilities, phy_conf.link_speed);
1881
1882         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1883         if (status)
1884                 return ret;
1885
1886         return I40E_SUCCESS;
1887 }
1888
1889 static int
1890 i40e_apply_link_speed(struct rte_eth_dev *dev)
1891 {
1892         uint8_t speed;
1893         uint8_t abilities = 0;
1894         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1895         struct rte_eth_conf *conf = &dev->data->dev_conf;
1896
1897         speed = i40e_parse_link_speeds(conf->link_speeds);
1898         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1899         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1900                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1901         abilities |= I40E_AQ_PHY_LINK_ENABLED;
1902
1903         /* Skip changing speed on 40G interfaces, FW does not support */
1904         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
1905                 speed =  I40E_LINK_SPEED_UNKNOWN;
1906                 abilities |= I40E_AQ_PHY_AN_ENABLED;
1907         }
1908
1909         return i40e_phy_conf_link(hw, abilities, speed);
1910 }
1911
1912 static int
1913 i40e_dev_start(struct rte_eth_dev *dev)
1914 {
1915         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1916         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1917         struct i40e_vsi *main_vsi = pf->main_vsi;
1918         int ret, i;
1919         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1920         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1921         uint32_t intr_vector = 0;
1922
1923         hw->adapter_stopped = 0;
1924
1925         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1926                 PMD_INIT_LOG(ERR, "Invalid link_speeds for port %hhu; autonegotiation disabled",
1927                              dev->data->port_id);
1928                 return -EINVAL;
1929         }
1930
1931         rte_intr_disable(intr_handle);
1932
1933         if ((rte_intr_cap_multiple(intr_handle) ||
1934              !RTE_ETH_DEV_SRIOV(dev).active) &&
1935             dev->data->dev_conf.intr_conf.rxq != 0) {
1936                 intr_vector = dev->data->nb_rx_queues;
1937                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1938                         return -1;
1939         }
1940
1941         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1942                 intr_handle->intr_vec =
1943                         rte_zmalloc("intr_vec",
1944                                     dev->data->nb_rx_queues * sizeof(int),
1945                                     0);
1946                 if (!intr_handle->intr_vec) {
1947                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1948                                      " intr_vec\n", dev->data->nb_rx_queues);
1949                         return -ENOMEM;
1950                 }
1951         }
1952
1953         /* Initialize VSI */
1954         ret = i40e_dev_rxtx_init(pf);
1955         if (ret != I40E_SUCCESS) {
1956                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1957                 goto err_up;
1958         }
1959
1960         /* Map queues with MSIX interrupt */
1961         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1962                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1963         i40e_vsi_queues_bind_intr(main_vsi);
1964         i40e_vsi_enable_queues_intr(main_vsi);
1965
1966         /* Map VMDQ VSI queues with MSIX interrupt */
1967         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1968                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1969                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1970                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1971         }
1972
1973         /* enable FDIR MSIX interrupt */
1974         if (pf->fdir.fdir_vsi) {
1975                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1976                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1977         }
1978
1979         /* Enable all queues which have been configured */
1980         ret = i40e_dev_switch_queues(pf, TRUE);
1981         if (ret != I40E_SUCCESS) {
1982                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1983                 goto err_up;
1984         }
1985
1986         /* Enable receiving broadcast packets */
1987         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1988         if (ret != I40E_SUCCESS)
1989                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1990
1991         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1992                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1993                                                 true, NULL);
1994                 if (ret != I40E_SUCCESS)
1995                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1996         }
1997
1998         /* Apply link configure */
1999         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
2000                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
2001                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
2002                                 ETH_LINK_SPEED_40G)) {
2003                 PMD_DRV_LOG(ERR, "Invalid link setting");
2004                 goto err_up;
2005         }
2006         ret = i40e_apply_link_speed(dev);
2007         if (I40E_SUCCESS != ret) {
2008                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2009                 goto err_up;
2010         }
2011
2012         if (!rte_intr_allow_others(intr_handle)) {
2013                 rte_intr_callback_unregister(intr_handle,
2014                                              i40e_dev_interrupt_handler,
2015                                              (void *)dev);
2016                 /* configure and enable device interrupt */
2017                 i40e_pf_config_irq0(hw, FALSE);
2018                 i40e_pf_enable_irq0(hw);
2019
2020                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2021                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
2022                                      " no intr multiplex\n");
2023         } else if (dev->data->dev_conf.intr_conf.lsc != 0) {
2024                 ret = i40e_aq_set_phy_int_mask(hw,
2025                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2026                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2027                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2028                 if (ret != I40E_SUCCESS)
2029                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2030
2031                 /* Call get_link_info aq commond to enable LSE */
2032                 i40e_dev_link_update(dev, 0);
2033         }
2034
2035         /* enable uio intr after callback register */
2036         rte_intr_enable(intr_handle);
2037
2038         i40e_filter_restore(pf);
2039
2040         return I40E_SUCCESS;
2041
2042 err_up:
2043         i40e_dev_switch_queues(pf, FALSE);
2044         i40e_dev_clear_queues(dev);
2045
2046         return ret;
2047 }
2048
2049 static void
2050 i40e_dev_stop(struct rte_eth_dev *dev)
2051 {
2052         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2053         struct i40e_vsi *main_vsi = pf->main_vsi;
2054         struct i40e_mirror_rule *p_mirror;
2055         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2056         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2057         int i;
2058
2059         /* Disable all queues */
2060         i40e_dev_switch_queues(pf, FALSE);
2061
2062         /* un-map queues with interrupt registers */
2063         i40e_vsi_disable_queues_intr(main_vsi);
2064         i40e_vsi_queues_unbind_intr(main_vsi);
2065
2066         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2067                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2068                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2069         }
2070
2071         if (pf->fdir.fdir_vsi) {
2072                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2073                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2074         }
2075         /* Clear all queues and release memory */
2076         i40e_dev_clear_queues(dev);
2077
2078         /* Set link down */
2079         i40e_dev_set_link_down(dev);
2080
2081         /* Remove all mirror rules */
2082         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2083                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2084                 rte_free(p_mirror);
2085         }
2086         pf->nb_mirror_rule = 0;
2087
2088         if (!rte_intr_allow_others(intr_handle))
2089                 /* resume to the default handler */
2090                 rte_intr_callback_register(intr_handle,
2091                                            i40e_dev_interrupt_handler,
2092                                            (void *)dev);
2093
2094         /* Clean datapath event and queue/vec mapping */
2095         rte_intr_efd_disable(intr_handle);
2096         if (intr_handle->intr_vec) {
2097                 rte_free(intr_handle->intr_vec);
2098                 intr_handle->intr_vec = NULL;
2099         }
2100 }
2101
2102 static void
2103 i40e_dev_close(struct rte_eth_dev *dev)
2104 {
2105         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2106         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2107         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2108         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2109         uint32_t reg;
2110         int i;
2111
2112         PMD_INIT_FUNC_TRACE();
2113
2114         i40e_dev_stop(dev);
2115         hw->adapter_stopped = 1;
2116         i40e_dev_free_queues(dev);
2117
2118         /* Disable interrupt */
2119         i40e_pf_disable_irq0(hw);
2120         rte_intr_disable(intr_handle);
2121
2122         /* shutdown and destroy the HMC */
2123         i40e_shutdown_lan_hmc(hw);
2124
2125         /* release all the existing VSIs and VEBs */
2126         i40e_fdir_teardown(pf);
2127         i40e_vsi_release(pf->main_vsi);
2128
2129         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2130                 i40e_vsi_release(pf->vmdq[i].vsi);
2131                 pf->vmdq[i].vsi = NULL;
2132         }
2133
2134         rte_free(pf->vmdq);
2135         pf->vmdq = NULL;
2136
2137         /* shutdown the adminq */
2138         i40e_aq_queue_shutdown(hw, true);
2139         i40e_shutdown_adminq(hw);
2140
2141         i40e_res_pool_destroy(&pf->qp_pool);
2142         i40e_res_pool_destroy(&pf->msix_pool);
2143
2144         /* force a PF reset to clean anything leftover */
2145         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2146         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2147                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2148         I40E_WRITE_FLUSH(hw);
2149 }
2150
2151 static void
2152 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2153 {
2154         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2155         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2156         struct i40e_vsi *vsi = pf->main_vsi;
2157         int status;
2158
2159         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2160                                                      true, NULL, true);
2161         if (status != I40E_SUCCESS)
2162                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2163
2164         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2165                                                         TRUE, NULL);
2166         if (status != I40E_SUCCESS)
2167                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2168
2169 }
2170
2171 static void
2172 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2173 {
2174         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2175         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2176         struct i40e_vsi *vsi = pf->main_vsi;
2177         int status;
2178
2179         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2180                                                      false, NULL, true);
2181         if (status != I40E_SUCCESS)
2182                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2183
2184         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2185                                                         false, NULL);
2186         if (status != I40E_SUCCESS)
2187                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2188 }
2189
2190 static void
2191 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2192 {
2193         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2194         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2195         struct i40e_vsi *vsi = pf->main_vsi;
2196         int ret;
2197
2198         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2199         if (ret != I40E_SUCCESS)
2200                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2201 }
2202
2203 static void
2204 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2205 {
2206         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2207         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2208         struct i40e_vsi *vsi = pf->main_vsi;
2209         int ret;
2210
2211         if (dev->data->promiscuous == 1)
2212                 return; /* must remain in all_multicast mode */
2213
2214         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2215                                 vsi->seid, FALSE, NULL);
2216         if (ret != I40E_SUCCESS)
2217                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2218 }
2219
2220 /*
2221  * Set device link up.
2222  */
2223 static int
2224 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2225 {
2226         /* re-apply link speed setting */
2227         return i40e_apply_link_speed(dev);
2228 }
2229
2230 /*
2231  * Set device link down.
2232  */
2233 static int
2234 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2235 {
2236         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2237         uint8_t abilities = 0;
2238         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2239
2240         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2241         return i40e_phy_conf_link(hw, abilities, speed);
2242 }
2243
2244 int
2245 i40e_dev_link_update(struct rte_eth_dev *dev,
2246                      int wait_to_complete)
2247 {
2248 #define CHECK_INTERVAL 100  /* 100ms */
2249 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2250         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2251         struct i40e_link_status link_status;
2252         struct rte_eth_link link, old;
2253         int status;
2254         unsigned rep_cnt = MAX_REPEAT_TIME;
2255         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2256
2257         memset(&link, 0, sizeof(link));
2258         memset(&old, 0, sizeof(old));
2259         memset(&link_status, 0, sizeof(link_status));
2260         rte_i40e_dev_atomic_read_link_status(dev, &old);
2261
2262         do {
2263                 /* Get link status information from hardware */
2264                 status = i40e_aq_get_link_info(hw, enable_lse,
2265                                                 &link_status, NULL);
2266                 if (status != I40E_SUCCESS) {
2267                         link.link_speed = ETH_SPEED_NUM_100M;
2268                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2269                         PMD_DRV_LOG(ERR, "Failed to get link info");
2270                         goto out;
2271                 }
2272
2273                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2274                 if (!wait_to_complete)
2275                         break;
2276
2277                 rte_delay_ms(CHECK_INTERVAL);
2278         } while (!link.link_status && rep_cnt--);
2279
2280         if (!link.link_status)
2281                 goto out;
2282
2283         /* i40e uses full duplex only */
2284         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2285
2286         /* Parse the link status */
2287         switch (link_status.link_speed) {
2288         case I40E_LINK_SPEED_100MB:
2289                 link.link_speed = ETH_SPEED_NUM_100M;
2290                 break;
2291         case I40E_LINK_SPEED_1GB:
2292                 link.link_speed = ETH_SPEED_NUM_1G;
2293                 break;
2294         case I40E_LINK_SPEED_10GB:
2295                 link.link_speed = ETH_SPEED_NUM_10G;
2296                 break;
2297         case I40E_LINK_SPEED_20GB:
2298                 link.link_speed = ETH_SPEED_NUM_20G;
2299                 break;
2300         case I40E_LINK_SPEED_25GB:
2301                 link.link_speed = ETH_SPEED_NUM_25G;
2302                 break;
2303         case I40E_LINK_SPEED_40GB:
2304                 link.link_speed = ETH_SPEED_NUM_40G;
2305                 break;
2306         default:
2307                 link.link_speed = ETH_SPEED_NUM_100M;
2308                 break;
2309         }
2310
2311         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2312                         ETH_LINK_SPEED_FIXED);
2313
2314 out:
2315         rte_i40e_dev_atomic_write_link_status(dev, &link);
2316         if (link.link_status == old.link_status)
2317                 return -1;
2318
2319         return 0;
2320 }
2321
2322 /* Get all the statistics of a VSI */
2323 void
2324 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2325 {
2326         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2327         struct i40e_eth_stats *nes = &vsi->eth_stats;
2328         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2329         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2330
2331         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2332                             vsi->offset_loaded, &oes->rx_bytes,
2333                             &nes->rx_bytes);
2334         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2335                             vsi->offset_loaded, &oes->rx_unicast,
2336                             &nes->rx_unicast);
2337         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2338                             vsi->offset_loaded, &oes->rx_multicast,
2339                             &nes->rx_multicast);
2340         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2341                             vsi->offset_loaded, &oes->rx_broadcast,
2342                             &nes->rx_broadcast);
2343         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2344                             &oes->rx_discards, &nes->rx_discards);
2345         /* GLV_REPC not supported */
2346         /* GLV_RMPC not supported */
2347         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2348                             &oes->rx_unknown_protocol,
2349                             &nes->rx_unknown_protocol);
2350         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2351                             vsi->offset_loaded, &oes->tx_bytes,
2352                             &nes->tx_bytes);
2353         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2354                             vsi->offset_loaded, &oes->tx_unicast,
2355                             &nes->tx_unicast);
2356         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2357                             vsi->offset_loaded, &oes->tx_multicast,
2358                             &nes->tx_multicast);
2359         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2360                             vsi->offset_loaded,  &oes->tx_broadcast,
2361                             &nes->tx_broadcast);
2362         /* GLV_TDPC not supported */
2363         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2364                             &oes->tx_errors, &nes->tx_errors);
2365         vsi->offset_loaded = true;
2366
2367         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2368                     vsi->vsi_id);
2369         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2370         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2371         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2372         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2373         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2374         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2375                     nes->rx_unknown_protocol);
2376         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2377         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2378         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2379         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2380         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2381         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2382         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2383                     vsi->vsi_id);
2384 }
2385
2386 static void
2387 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2388 {
2389         unsigned int i;
2390         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2391         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2392
2393         /* Get statistics of struct i40e_eth_stats */
2394         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2395                             I40E_GLPRT_GORCL(hw->port),
2396                             pf->offset_loaded, &os->eth.rx_bytes,
2397                             &ns->eth.rx_bytes);
2398         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2399                             I40E_GLPRT_UPRCL(hw->port),
2400                             pf->offset_loaded, &os->eth.rx_unicast,
2401                             &ns->eth.rx_unicast);
2402         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2403                             I40E_GLPRT_MPRCL(hw->port),
2404                             pf->offset_loaded, &os->eth.rx_multicast,
2405                             &ns->eth.rx_multicast);
2406         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2407                             I40E_GLPRT_BPRCL(hw->port),
2408                             pf->offset_loaded, &os->eth.rx_broadcast,
2409                             &ns->eth.rx_broadcast);
2410         /* Workaround: CRC size should not be included in byte statistics,
2411          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2412          */
2413         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2414                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2415
2416         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2417                             pf->offset_loaded, &os->eth.rx_discards,
2418                             &ns->eth.rx_discards);
2419         /* GLPRT_REPC not supported */
2420         /* GLPRT_RMPC not supported */
2421         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2422                             pf->offset_loaded,
2423                             &os->eth.rx_unknown_protocol,
2424                             &ns->eth.rx_unknown_protocol);
2425         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2426                             I40E_GLPRT_GOTCL(hw->port),
2427                             pf->offset_loaded, &os->eth.tx_bytes,
2428                             &ns->eth.tx_bytes);
2429         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2430                             I40E_GLPRT_UPTCL(hw->port),
2431                             pf->offset_loaded, &os->eth.tx_unicast,
2432                             &ns->eth.tx_unicast);
2433         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2434                             I40E_GLPRT_MPTCL(hw->port),
2435                             pf->offset_loaded, &os->eth.tx_multicast,
2436                             &ns->eth.tx_multicast);
2437         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2438                             I40E_GLPRT_BPTCL(hw->port),
2439                             pf->offset_loaded, &os->eth.tx_broadcast,
2440                             &ns->eth.tx_broadcast);
2441         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2442                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2443         /* GLPRT_TEPC not supported */
2444
2445         /* additional port specific stats */
2446         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2447                             pf->offset_loaded, &os->tx_dropped_link_down,
2448                             &ns->tx_dropped_link_down);
2449         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2450                             pf->offset_loaded, &os->crc_errors,
2451                             &ns->crc_errors);
2452         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2453                             pf->offset_loaded, &os->illegal_bytes,
2454                             &ns->illegal_bytes);
2455         /* GLPRT_ERRBC not supported */
2456         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2457                             pf->offset_loaded, &os->mac_local_faults,
2458                             &ns->mac_local_faults);
2459         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2460                             pf->offset_loaded, &os->mac_remote_faults,
2461                             &ns->mac_remote_faults);
2462         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2463                             pf->offset_loaded, &os->rx_length_errors,
2464                             &ns->rx_length_errors);
2465         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2466                             pf->offset_loaded, &os->link_xon_rx,
2467                             &ns->link_xon_rx);
2468         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2469                             pf->offset_loaded, &os->link_xoff_rx,
2470                             &ns->link_xoff_rx);
2471         for (i = 0; i < 8; i++) {
2472                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2473                                     pf->offset_loaded,
2474                                     &os->priority_xon_rx[i],
2475                                     &ns->priority_xon_rx[i]);
2476                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2477                                     pf->offset_loaded,
2478                                     &os->priority_xoff_rx[i],
2479                                     &ns->priority_xoff_rx[i]);
2480         }
2481         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2482                             pf->offset_loaded, &os->link_xon_tx,
2483                             &ns->link_xon_tx);
2484         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2485                             pf->offset_loaded, &os->link_xoff_tx,
2486                             &ns->link_xoff_tx);
2487         for (i = 0; i < 8; i++) {
2488                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2489                                     pf->offset_loaded,
2490                                     &os->priority_xon_tx[i],
2491                                     &ns->priority_xon_tx[i]);
2492                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2493                                     pf->offset_loaded,
2494                                     &os->priority_xoff_tx[i],
2495                                     &ns->priority_xoff_tx[i]);
2496                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2497                                     pf->offset_loaded,
2498                                     &os->priority_xon_2_xoff[i],
2499                                     &ns->priority_xon_2_xoff[i]);
2500         }
2501         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2502                             I40E_GLPRT_PRC64L(hw->port),
2503                             pf->offset_loaded, &os->rx_size_64,
2504                             &ns->rx_size_64);
2505         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2506                             I40E_GLPRT_PRC127L(hw->port),
2507                             pf->offset_loaded, &os->rx_size_127,
2508                             &ns->rx_size_127);
2509         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2510                             I40E_GLPRT_PRC255L(hw->port),
2511                             pf->offset_loaded, &os->rx_size_255,
2512                             &ns->rx_size_255);
2513         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2514                             I40E_GLPRT_PRC511L(hw->port),
2515                             pf->offset_loaded, &os->rx_size_511,
2516                             &ns->rx_size_511);
2517         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2518                             I40E_GLPRT_PRC1023L(hw->port),
2519                             pf->offset_loaded, &os->rx_size_1023,
2520                             &ns->rx_size_1023);
2521         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2522                             I40E_GLPRT_PRC1522L(hw->port),
2523                             pf->offset_loaded, &os->rx_size_1522,
2524                             &ns->rx_size_1522);
2525         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2526                             I40E_GLPRT_PRC9522L(hw->port),
2527                             pf->offset_loaded, &os->rx_size_big,
2528                             &ns->rx_size_big);
2529         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2530                             pf->offset_loaded, &os->rx_undersize,
2531                             &ns->rx_undersize);
2532         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2533                             pf->offset_loaded, &os->rx_fragments,
2534                             &ns->rx_fragments);
2535         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2536                             pf->offset_loaded, &os->rx_oversize,
2537                             &ns->rx_oversize);
2538         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2539                             pf->offset_loaded, &os->rx_jabber,
2540                             &ns->rx_jabber);
2541         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2542                             I40E_GLPRT_PTC64L(hw->port),
2543                             pf->offset_loaded, &os->tx_size_64,
2544                             &ns->tx_size_64);
2545         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2546                             I40E_GLPRT_PTC127L(hw->port),
2547                             pf->offset_loaded, &os->tx_size_127,
2548                             &ns->tx_size_127);
2549         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2550                             I40E_GLPRT_PTC255L(hw->port),
2551                             pf->offset_loaded, &os->tx_size_255,
2552                             &ns->tx_size_255);
2553         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2554                             I40E_GLPRT_PTC511L(hw->port),
2555                             pf->offset_loaded, &os->tx_size_511,
2556                             &ns->tx_size_511);
2557         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2558                             I40E_GLPRT_PTC1023L(hw->port),
2559                             pf->offset_loaded, &os->tx_size_1023,
2560                             &ns->tx_size_1023);
2561         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2562                             I40E_GLPRT_PTC1522L(hw->port),
2563                             pf->offset_loaded, &os->tx_size_1522,
2564                             &ns->tx_size_1522);
2565         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2566                             I40E_GLPRT_PTC9522L(hw->port),
2567                             pf->offset_loaded, &os->tx_size_big,
2568                             &ns->tx_size_big);
2569         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2570                            pf->offset_loaded,
2571                            &os->fd_sb_match, &ns->fd_sb_match);
2572         /* GLPRT_MSPDC not supported */
2573         /* GLPRT_XEC not supported */
2574
2575         pf->offset_loaded = true;
2576
2577         if (pf->main_vsi)
2578                 i40e_update_vsi_stats(pf->main_vsi);
2579 }
2580
2581 /* Get all statistics of a port */
2582 static void
2583 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2584 {
2585         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2586         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2587         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2588         unsigned i;
2589
2590         /* call read registers - updates values, now write them to struct */
2591         i40e_read_stats_registers(pf, hw);
2592
2593         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
2594                         pf->main_vsi->eth_stats.rx_multicast +
2595                         pf->main_vsi->eth_stats.rx_broadcast -
2596                         pf->main_vsi->eth_stats.rx_discards;
2597         stats->opackets = pf->main_vsi->eth_stats.tx_unicast +
2598                         pf->main_vsi->eth_stats.tx_multicast +
2599                         pf->main_vsi->eth_stats.tx_broadcast;
2600         stats->ibytes   = ns->eth.rx_bytes;
2601         stats->obytes   = ns->eth.tx_bytes;
2602         stats->oerrors  = ns->eth.tx_errors +
2603                         pf->main_vsi->eth_stats.tx_errors;
2604
2605         /* Rx Errors */
2606         stats->imissed  = ns->eth.rx_discards +
2607                         pf->main_vsi->eth_stats.rx_discards;
2608         stats->ierrors  = ns->crc_errors +
2609                         ns->rx_length_errors + ns->rx_undersize +
2610                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2611
2612         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2613         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2614         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2615         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2616         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2617         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2618         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2619                     ns->eth.rx_unknown_protocol);
2620         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2621         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2622         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2623         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2624         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2625         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2626
2627         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2628                     ns->tx_dropped_link_down);
2629         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2630         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2631                     ns->illegal_bytes);
2632         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
2633         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
2634                     ns->mac_local_faults);
2635         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
2636                     ns->mac_remote_faults);
2637         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
2638                     ns->rx_length_errors);
2639         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
2640         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
2641         for (i = 0; i < 8; i++) {
2642                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
2643                                 i, ns->priority_xon_rx[i]);
2644                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
2645                                 i, ns->priority_xoff_rx[i]);
2646         }
2647         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
2648         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
2649         for (i = 0; i < 8; i++) {
2650                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
2651                                 i, ns->priority_xon_tx[i]);
2652                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
2653                                 i, ns->priority_xoff_tx[i]);
2654                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
2655                                 i, ns->priority_xon_2_xoff[i]);
2656         }
2657         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
2658         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
2659         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
2660         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
2661         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
2662         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
2663         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
2664         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
2665         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
2666         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
2667         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
2668         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
2669         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
2670         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
2671         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
2672         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
2673         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
2674         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
2675         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2676                         ns->mac_short_packet_dropped);
2677         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
2678                     ns->checksum_error);
2679         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
2680         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2681 }
2682
2683 /* Reset the statistics */
2684 static void
2685 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2686 {
2687         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2688         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2689
2690         /* Mark PF and VSI stats to update the offset, aka "reset" */
2691         pf->offset_loaded = false;
2692         if (pf->main_vsi)
2693                 pf->main_vsi->offset_loaded = false;
2694
2695         /* read the stats, reading current register values into offset */
2696         i40e_read_stats_registers(pf, hw);
2697 }
2698
2699 static uint32_t
2700 i40e_xstats_calc_num(void)
2701 {
2702         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2703                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2704                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2705 }
2706
2707 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2708                                      struct rte_eth_xstat_name *xstats_names,
2709                                      __rte_unused unsigned limit)
2710 {
2711         unsigned count = 0;
2712         unsigned i, prio;
2713
2714         if (xstats_names == NULL)
2715                 return i40e_xstats_calc_num();
2716
2717         /* Note: limit checked in rte_eth_xstats_names() */
2718
2719         /* Get stats from i40e_eth_stats struct */
2720         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2721                 snprintf(xstats_names[count].name,
2722                          sizeof(xstats_names[count].name),
2723                          "%s", rte_i40e_stats_strings[i].name);
2724                 count++;
2725         }
2726
2727         /* Get individiual stats from i40e_hw_port struct */
2728         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2729                 snprintf(xstats_names[count].name,
2730                         sizeof(xstats_names[count].name),
2731                          "%s", rte_i40e_hw_port_strings[i].name);
2732                 count++;
2733         }
2734
2735         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2736                 for (prio = 0; prio < 8; prio++) {
2737                         snprintf(xstats_names[count].name,
2738                                  sizeof(xstats_names[count].name),
2739                                  "rx_priority%u_%s", prio,
2740                                  rte_i40e_rxq_prio_strings[i].name);
2741                         count++;
2742                 }
2743         }
2744
2745         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2746                 for (prio = 0; prio < 8; prio++) {
2747                         snprintf(xstats_names[count].name,
2748                                  sizeof(xstats_names[count].name),
2749                                  "tx_priority%u_%s", prio,
2750                                  rte_i40e_txq_prio_strings[i].name);
2751                         count++;
2752                 }
2753         }
2754         return count;
2755 }
2756
2757 static int
2758 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2759                     unsigned n)
2760 {
2761         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2762         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2763         unsigned i, count, prio;
2764         struct i40e_hw_port_stats *hw_stats = &pf->stats;
2765
2766         count = i40e_xstats_calc_num();
2767         if (n < count)
2768                 return count;
2769
2770         i40e_read_stats_registers(pf, hw);
2771
2772         if (xstats == NULL)
2773                 return 0;
2774
2775         count = 0;
2776
2777         /* Get stats from i40e_eth_stats struct */
2778         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2779                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2780                         rte_i40e_stats_strings[i].offset);
2781                 xstats[count].id = count;
2782                 count++;
2783         }
2784
2785         /* Get individiual stats from i40e_hw_port struct */
2786         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2787                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2788                         rte_i40e_hw_port_strings[i].offset);
2789                 xstats[count].id = count;
2790                 count++;
2791         }
2792
2793         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2794                 for (prio = 0; prio < 8; prio++) {
2795                         xstats[count].value =
2796                                 *(uint64_t *)(((char *)hw_stats) +
2797                                 rte_i40e_rxq_prio_strings[i].offset +
2798                                 (sizeof(uint64_t) * prio));
2799                         xstats[count].id = count;
2800                         count++;
2801                 }
2802         }
2803
2804         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2805                 for (prio = 0; prio < 8; prio++) {
2806                         xstats[count].value =
2807                                 *(uint64_t *)(((char *)hw_stats) +
2808                                 rte_i40e_txq_prio_strings[i].offset +
2809                                 (sizeof(uint64_t) * prio));
2810                         xstats[count].id = count;
2811                         count++;
2812                 }
2813         }
2814
2815         return count;
2816 }
2817
2818 static int
2819 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2820                                  __rte_unused uint16_t queue_id,
2821                                  __rte_unused uint8_t stat_idx,
2822                                  __rte_unused uint8_t is_rx)
2823 {
2824         PMD_INIT_FUNC_TRACE();
2825
2826         return -ENOSYS;
2827 }
2828
2829 static int
2830 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2831 {
2832         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2833         u32 full_ver;
2834         u8 ver, patch;
2835         u16 build;
2836         int ret;
2837
2838         full_ver = hw->nvm.oem_ver;
2839         ver = (u8)(full_ver >> 24);
2840         build = (u16)((full_ver >> 8) & 0xffff);
2841         patch = (u8)(full_ver & 0xff);
2842
2843         ret = snprintf(fw_version, fw_size,
2844                  "%d.%d%d 0x%08x %d.%d.%d",
2845                  ((hw->nvm.version >> 12) & 0xf),
2846                  ((hw->nvm.version >> 4) & 0xff),
2847                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
2848                  ver, build, patch);
2849
2850         ret += 1; /* add the size of '\0' */
2851         if (fw_size < (u32)ret)
2852                 return ret;
2853         else
2854                 return 0;
2855 }
2856
2857 static void
2858 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2859 {
2860         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2861         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2862         struct i40e_vsi *vsi = pf->main_vsi;
2863         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2864
2865         dev_info->pci_dev = pci_dev;
2866         dev_info->max_rx_queues = vsi->nb_qps;
2867         dev_info->max_tx_queues = vsi->nb_qps;
2868         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2869         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2870         dev_info->max_mac_addrs = vsi->max_macaddrs;
2871         dev_info->max_vfs = pci_dev->max_vfs;
2872         dev_info->rx_offload_capa =
2873                 DEV_RX_OFFLOAD_VLAN_STRIP |
2874                 DEV_RX_OFFLOAD_QINQ_STRIP |
2875                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2876                 DEV_RX_OFFLOAD_UDP_CKSUM |
2877                 DEV_RX_OFFLOAD_TCP_CKSUM;
2878         dev_info->tx_offload_capa =
2879                 DEV_TX_OFFLOAD_VLAN_INSERT |
2880                 DEV_TX_OFFLOAD_QINQ_INSERT |
2881                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2882                 DEV_TX_OFFLOAD_UDP_CKSUM |
2883                 DEV_TX_OFFLOAD_TCP_CKSUM |
2884                 DEV_TX_OFFLOAD_SCTP_CKSUM |
2885                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2886                 DEV_TX_OFFLOAD_TCP_TSO |
2887                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
2888                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
2889                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
2890                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
2891         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
2892                                                 sizeof(uint32_t);
2893         dev_info->reta_size = pf->hash_lut_size;
2894         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2895
2896         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2897                 .rx_thresh = {
2898                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2899                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2900                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2901                 },
2902                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2903                 .rx_drop_en = 0,
2904         };
2905
2906         dev_info->default_txconf = (struct rte_eth_txconf) {
2907                 .tx_thresh = {
2908                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2909                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2910                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2911                 },
2912                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2913                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2914                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2915                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2916         };
2917
2918         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2919                 .nb_max = I40E_MAX_RING_DESC,
2920                 .nb_min = I40E_MIN_RING_DESC,
2921                 .nb_align = I40E_ALIGN_RING_DESC,
2922         };
2923
2924         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2925                 .nb_max = I40E_MAX_RING_DESC,
2926                 .nb_min = I40E_MIN_RING_DESC,
2927                 .nb_align = I40E_ALIGN_RING_DESC,
2928                 .nb_seg_max = I40E_TX_MAX_SEG,
2929                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
2930         };
2931
2932         if (pf->flags & I40E_FLAG_VMDQ) {
2933                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
2934                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
2935                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
2936                                                 pf->max_nb_vmdq_vsi;
2937                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
2938                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
2939                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
2940         }
2941
2942         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
2943                 /* For XL710 */
2944                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
2945         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
2946                 /* For XXV710 */
2947                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
2948         else
2949                 /* For X710 */
2950                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2951 }
2952
2953 static int
2954 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2955 {
2956         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2957         struct i40e_vsi *vsi = pf->main_vsi;
2958         PMD_INIT_FUNC_TRACE();
2959
2960         if (on)
2961                 return i40e_vsi_add_vlan(vsi, vlan_id);
2962         else
2963                 return i40e_vsi_delete_vlan(vsi, vlan_id);
2964 }
2965
2966 static int
2967 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
2968                    enum rte_vlan_type vlan_type,
2969                    uint16_t tpid)
2970 {
2971         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2972         uint64_t reg_r = 0, reg_w = 0;
2973         uint16_t reg_id = 0;
2974         int ret = 0;
2975         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
2976
2977         switch (vlan_type) {
2978         case ETH_VLAN_TYPE_OUTER:
2979                 if (qinq)
2980                         reg_id = 2;
2981                 else
2982                         reg_id = 3;
2983                 break;
2984         case ETH_VLAN_TYPE_INNER:
2985                 if (qinq)
2986                         reg_id = 3;
2987                 else {
2988                         ret = -EINVAL;
2989                         PMD_DRV_LOG(ERR,
2990                                 "Unsupported vlan type in single vlan.\n");
2991                         return ret;
2992                 }
2993                 break;
2994         default:
2995                 ret = -EINVAL;
2996                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2997                 return ret;
2998         }
2999         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3000                                           &reg_r, NULL);
3001         if (ret != I40E_SUCCESS) {
3002                 PMD_DRV_LOG(ERR, "Fail to debug read from "
3003                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
3004                 ret = -EIO;
3005                 return ret;
3006         }
3007         PMD_DRV_LOG(DEBUG, "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: "
3008                     "0x%08"PRIx64"", reg_id, reg_r);
3009
3010         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3011         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3012         if (reg_r == reg_w) {
3013                 ret = 0;
3014                 PMD_DRV_LOG(DEBUG, "No need to write");
3015                 return ret;
3016         }
3017
3018         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3019                                            reg_w, NULL);
3020         if (ret != I40E_SUCCESS) {
3021                 ret = -EIO;
3022                 PMD_DRV_LOG(ERR, "Fail to debug write to "
3023                             "I40E_GL_SWT_L2TAGCTRL[%d]", reg_id);
3024                 return ret;
3025         }
3026         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
3027                     "I40E_GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
3028
3029         return ret;
3030 }
3031
3032 static void
3033 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3034 {
3035         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3036         struct i40e_vsi *vsi = pf->main_vsi;
3037
3038         if (mask & ETH_VLAN_FILTER_MASK) {
3039                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3040                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3041                 else
3042                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3043         }
3044
3045         if (mask & ETH_VLAN_STRIP_MASK) {
3046                 /* Enable or disable VLAN stripping */
3047                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3048                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3049                 else
3050                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3051         }
3052
3053         if (mask & ETH_VLAN_EXTEND_MASK) {
3054                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3055                         i40e_vsi_config_double_vlan(vsi, TRUE);
3056                         /* Set global registers with default ether type value */
3057                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3058                                            ETHER_TYPE_VLAN);
3059                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3060                                            ETHER_TYPE_VLAN);
3061                 }
3062                 else
3063                         i40e_vsi_config_double_vlan(vsi, FALSE);
3064         }
3065 }
3066
3067 static void
3068 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3069                           __rte_unused uint16_t queue,
3070                           __rte_unused int on)
3071 {
3072         PMD_INIT_FUNC_TRACE();
3073 }
3074
3075 static int
3076 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3077 {
3078         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3079         struct i40e_vsi *vsi = pf->main_vsi;
3080         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3081         struct i40e_vsi_vlan_pvid_info info;
3082
3083         memset(&info, 0, sizeof(info));
3084         info.on = on;
3085         if (info.on)
3086                 info.config.pvid = pvid;
3087         else {
3088                 info.config.reject.tagged =
3089                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3090                 info.config.reject.untagged =
3091                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3092         }
3093
3094         return i40e_vsi_vlan_pvid_set(vsi, &info);
3095 }
3096
3097 static int
3098 i40e_dev_led_on(struct rte_eth_dev *dev)
3099 {
3100         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3101         uint32_t mode = i40e_led_get(hw);
3102
3103         if (mode == 0)
3104                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3105
3106         return 0;
3107 }
3108
3109 static int
3110 i40e_dev_led_off(struct rte_eth_dev *dev)
3111 {
3112         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3113         uint32_t mode = i40e_led_get(hw);
3114
3115         if (mode != 0)
3116                 i40e_led_set(hw, 0, false);
3117
3118         return 0;
3119 }
3120
3121 static int
3122 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3123 {
3124         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3125         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3126
3127         fc_conf->pause_time = pf->fc_conf.pause_time;
3128         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3129         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3130
3131          /* Return current mode according to actual setting*/
3132         switch (hw->fc.current_mode) {
3133         case I40E_FC_FULL:
3134                 fc_conf->mode = RTE_FC_FULL;
3135                 break;
3136         case I40E_FC_TX_PAUSE:
3137                 fc_conf->mode = RTE_FC_TX_PAUSE;
3138                 break;
3139         case I40E_FC_RX_PAUSE:
3140                 fc_conf->mode = RTE_FC_RX_PAUSE;
3141                 break;
3142         case I40E_FC_NONE:
3143         default:
3144                 fc_conf->mode = RTE_FC_NONE;
3145         };
3146
3147         return 0;
3148 }
3149
3150 static int
3151 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3152 {
3153         uint32_t mflcn_reg, fctrl_reg, reg;
3154         uint32_t max_high_water;
3155         uint8_t i, aq_failure;
3156         int err;
3157         struct i40e_hw *hw;
3158         struct i40e_pf *pf;
3159         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3160                 [RTE_FC_NONE] = I40E_FC_NONE,
3161                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3162                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3163                 [RTE_FC_FULL] = I40E_FC_FULL
3164         };
3165
3166         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3167
3168         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3169         if ((fc_conf->high_water > max_high_water) ||
3170                         (fc_conf->high_water < fc_conf->low_water)) {
3171                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
3172                         "High_water must <= %d.", max_high_water);
3173                 return -EINVAL;
3174         }
3175
3176         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3177         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3178         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3179
3180         pf->fc_conf.pause_time = fc_conf->pause_time;
3181         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3182         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3183
3184         PMD_INIT_FUNC_TRACE();
3185
3186         /* All the link flow control related enable/disable register
3187          * configuration is handle by the F/W
3188          */
3189         err = i40e_set_fc(hw, &aq_failure, true);
3190         if (err < 0)
3191                 return -ENOSYS;
3192
3193         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3194                 /* Configure flow control refresh threshold,
3195                  * the value for stat_tx_pause_refresh_timer[8]
3196                  * is used for global pause operation.
3197                  */
3198
3199                 I40E_WRITE_REG(hw,
3200                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3201                                pf->fc_conf.pause_time);
3202
3203                 /* configure the timer value included in transmitted pause
3204                  * frame,
3205                  * the value for stat_tx_pause_quanta[8] is used for global
3206                  * pause operation
3207                  */
3208                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3209                                pf->fc_conf.pause_time);
3210
3211                 fctrl_reg = I40E_READ_REG(hw,
3212                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3213
3214                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3215                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3216                 else
3217                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3218
3219                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3220                                fctrl_reg);
3221         } else {
3222                 /* Configure pause time (2 TCs per register) */
3223                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3224                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3225                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3226
3227                 /* Configure flow control refresh threshold value */
3228                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3229                                pf->fc_conf.pause_time / 2);
3230
3231                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3232
3233                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3234                  *depending on configuration
3235                  */
3236                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3237                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3238                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3239                 } else {
3240                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3241                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3242                 }
3243
3244                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3245         }
3246
3247         /* config the water marker both based on the packets and bytes */
3248         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3249                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3250                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3251         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3252                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3253                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3254         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3255                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3256                        << I40E_KILOSHIFT);
3257         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3258                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3259                        << I40E_KILOSHIFT);
3260
3261         I40E_WRITE_FLUSH(hw);
3262
3263         return 0;
3264 }
3265
3266 static int
3267 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3268                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3269 {
3270         PMD_INIT_FUNC_TRACE();
3271
3272         return -ENOSYS;
3273 }
3274
3275 /* Add a MAC address, and update filters */
3276 static void
3277 i40e_macaddr_add(struct rte_eth_dev *dev,
3278                  struct ether_addr *mac_addr,
3279                  __rte_unused uint32_t index,
3280                  uint32_t pool)
3281 {
3282         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3283         struct i40e_mac_filter_info mac_filter;
3284         struct i40e_vsi *vsi;
3285         int ret;
3286
3287         /* If VMDQ not enabled or configured, return */
3288         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3289                           !pf->nb_cfg_vmdq_vsi)) {
3290                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3291                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3292                         pool);
3293                 return;
3294         }
3295
3296         if (pool > pf->nb_cfg_vmdq_vsi) {
3297                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3298                                 pool, pf->nb_cfg_vmdq_vsi);
3299                 return;
3300         }
3301
3302         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3303         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3304                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3305         else
3306                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3307
3308         if (pool == 0)
3309                 vsi = pf->main_vsi;
3310         else
3311                 vsi = pf->vmdq[pool - 1].vsi;
3312
3313         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3314         if (ret != I40E_SUCCESS) {
3315                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3316                 return;
3317         }
3318 }
3319
3320 /* Remove a MAC address, and update filters */
3321 static void
3322 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3323 {
3324         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3325         struct i40e_vsi *vsi;
3326         struct rte_eth_dev_data *data = dev->data;
3327         struct ether_addr *macaddr;
3328         int ret;
3329         uint32_t i;
3330         uint64_t pool_sel;
3331
3332         macaddr = &(data->mac_addrs[index]);
3333
3334         pool_sel = dev->data->mac_pool_sel[index];
3335
3336         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3337                 if (pool_sel & (1ULL << i)) {
3338                         if (i == 0)
3339                                 vsi = pf->main_vsi;
3340                         else {
3341                                 /* No VMDQ pool enabled or configured */
3342                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3343                                         (i > pf->nb_cfg_vmdq_vsi)) {
3344                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
3345                                                         "/configured");
3346                                         return;
3347                                 }
3348                                 vsi = pf->vmdq[i - 1].vsi;
3349                         }
3350                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3351
3352                         if (ret) {
3353                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3354                                 return;
3355                         }
3356                 }
3357         }
3358 }
3359
3360 /* Set perfect match or hash match of MAC and VLAN for a VF */
3361 static int
3362 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3363                  struct rte_eth_mac_filter *filter,
3364                  bool add)
3365 {
3366         struct i40e_hw *hw;
3367         struct i40e_mac_filter_info mac_filter;
3368         struct ether_addr old_mac;
3369         struct ether_addr *new_mac;
3370         struct i40e_pf_vf *vf = NULL;
3371         uint16_t vf_id;
3372         int ret;
3373
3374         if (pf == NULL) {
3375                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3376                 return -EINVAL;
3377         }
3378         hw = I40E_PF_TO_HW(pf);
3379
3380         if (filter == NULL) {
3381                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3382                 return -EINVAL;
3383         }
3384
3385         new_mac = &filter->mac_addr;
3386
3387         if (is_zero_ether_addr(new_mac)) {
3388                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3389                 return -EINVAL;
3390         }
3391
3392         vf_id = filter->dst_id;
3393
3394         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3395                 PMD_DRV_LOG(ERR, "Invalid argument.");
3396                 return -EINVAL;
3397         }
3398         vf = &pf->vfs[vf_id];
3399
3400         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3401                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3402                 return -EINVAL;
3403         }
3404
3405         if (add) {
3406                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3407                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3408                                 ETHER_ADDR_LEN);
3409                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3410                                  ETHER_ADDR_LEN);
3411
3412                 mac_filter.filter_type = filter->filter_type;
3413                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3414                 if (ret != I40E_SUCCESS) {
3415                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3416                         return -1;
3417                 }
3418                 ether_addr_copy(new_mac, &pf->dev_addr);
3419         } else {
3420                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3421                                 ETHER_ADDR_LEN);
3422                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3423                 if (ret != I40E_SUCCESS) {
3424                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3425                         return -1;
3426                 }
3427
3428                 /* Clear device address as it has been removed */
3429                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3430                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3431         }
3432
3433         return 0;
3434 }
3435
3436 /* MAC filter handle */
3437 static int
3438 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3439                 void *arg)
3440 {
3441         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3442         struct rte_eth_mac_filter *filter;
3443         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3444         int ret = I40E_NOT_SUPPORTED;
3445
3446         filter = (struct rte_eth_mac_filter *)(arg);
3447
3448         switch (filter_op) {
3449         case RTE_ETH_FILTER_NOP:
3450                 ret = I40E_SUCCESS;
3451                 break;
3452         case RTE_ETH_FILTER_ADD:
3453                 i40e_pf_disable_irq0(hw);
3454                 if (filter->is_vf)
3455                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3456                 i40e_pf_enable_irq0(hw);
3457                 break;
3458         case RTE_ETH_FILTER_DELETE:
3459                 i40e_pf_disable_irq0(hw);
3460                 if (filter->is_vf)
3461                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3462                 i40e_pf_enable_irq0(hw);
3463                 break;
3464         default:
3465                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3466                 ret = I40E_ERR_PARAM;
3467                 break;
3468         }
3469
3470         return ret;
3471 }
3472
3473 static int
3474 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3475 {
3476         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3477         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3478         int ret;
3479
3480         if (!lut)
3481                 return -EINVAL;
3482
3483         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3484                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3485                                           lut, lut_size);
3486                 if (ret) {
3487                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3488                         return ret;
3489                 }
3490         } else {
3491                 uint32_t *lut_dw = (uint32_t *)lut;
3492                 uint16_t i, lut_size_dw = lut_size / 4;
3493
3494                 for (i = 0; i < lut_size_dw; i++)
3495                         lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3496         }
3497
3498         return 0;
3499 }
3500
3501 static int
3502 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3503 {
3504         struct i40e_pf *pf;
3505         struct i40e_hw *hw;
3506         int ret;
3507
3508         if (!vsi || !lut)
3509                 return -EINVAL;
3510
3511         pf = I40E_VSI_TO_PF(vsi);
3512         hw = I40E_VSI_TO_HW(vsi);
3513
3514         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3515                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3516                                           lut, lut_size);
3517                 if (ret) {
3518                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3519                         return ret;
3520                 }
3521         } else {
3522                 uint32_t *lut_dw = (uint32_t *)lut;
3523                 uint16_t i, lut_size_dw = lut_size / 4;
3524
3525                 for (i = 0; i < lut_size_dw; i++)
3526                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3527                 I40E_WRITE_FLUSH(hw);
3528         }
3529
3530         return 0;
3531 }
3532
3533 static int
3534 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3535                          struct rte_eth_rss_reta_entry64 *reta_conf,
3536                          uint16_t reta_size)
3537 {
3538         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3539         uint16_t i, lut_size = pf->hash_lut_size;
3540         uint16_t idx, shift;
3541         uint8_t *lut;
3542         int ret;
3543
3544         if (reta_size != lut_size ||
3545                 reta_size > ETH_RSS_RETA_SIZE_512) {
3546                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3547                         "(%d) doesn't match the number hardware can supported "
3548                                         "(%d)\n", reta_size, lut_size);
3549                 return -EINVAL;
3550         }
3551
3552         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3553         if (!lut) {
3554                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3555                 return -ENOMEM;
3556         }
3557         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3558         if (ret)
3559                 goto out;
3560         for (i = 0; i < reta_size; i++) {
3561                 idx = i / RTE_RETA_GROUP_SIZE;
3562                 shift = i % RTE_RETA_GROUP_SIZE;
3563                 if (reta_conf[idx].mask & (1ULL << shift))
3564                         lut[i] = reta_conf[idx].reta[shift];
3565         }
3566         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3567
3568 out:
3569         rte_free(lut);
3570
3571         return ret;
3572 }
3573
3574 static int
3575 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3576                         struct rte_eth_rss_reta_entry64 *reta_conf,
3577                         uint16_t reta_size)
3578 {
3579         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3580         uint16_t i, lut_size = pf->hash_lut_size;
3581         uint16_t idx, shift;
3582         uint8_t *lut;
3583         int ret;
3584
3585         if (reta_size != lut_size ||
3586                 reta_size > ETH_RSS_RETA_SIZE_512) {
3587                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3588                         "(%d) doesn't match the number hardware can supported "
3589                                         "(%d)\n", reta_size, lut_size);
3590                 return -EINVAL;
3591         }
3592
3593         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3594         if (!lut) {
3595                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3596                 return -ENOMEM;
3597         }
3598
3599         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3600         if (ret)
3601                 goto out;
3602         for (i = 0; i < reta_size; i++) {
3603                 idx = i / RTE_RETA_GROUP_SIZE;
3604                 shift = i % RTE_RETA_GROUP_SIZE;
3605                 if (reta_conf[idx].mask & (1ULL << shift))
3606                         reta_conf[idx].reta[shift] = lut[i];
3607         }
3608
3609 out:
3610         rte_free(lut);
3611
3612         return ret;
3613 }
3614
3615 /**
3616  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3617  * @hw:   pointer to the HW structure
3618  * @mem:  pointer to mem struct to fill out
3619  * @size: size of memory requested
3620  * @alignment: what to align the allocation to
3621  **/
3622 enum i40e_status_code
3623 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3624                         struct i40e_dma_mem *mem,
3625                         u64 size,
3626                         u32 alignment)
3627 {
3628         const struct rte_memzone *mz = NULL;
3629         char z_name[RTE_MEMZONE_NAMESIZE];
3630
3631         if (!mem)
3632                 return I40E_ERR_PARAM;
3633
3634         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3635         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3636                                          alignment, RTE_PGSIZE_2M);
3637         if (!mz)
3638                 return I40E_ERR_NO_MEMORY;
3639
3640         mem->size = size;
3641         mem->va = mz->addr;
3642         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
3643         mem->zone = (const void *)mz;
3644         PMD_DRV_LOG(DEBUG, "memzone %s allocated with physical address: "
3645                     "%"PRIu64, mz->name, mem->pa);
3646
3647         return I40E_SUCCESS;
3648 }
3649
3650 /**
3651  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3652  * @hw:   pointer to the HW structure
3653  * @mem:  ptr to mem struct to free
3654  **/
3655 enum i40e_status_code
3656 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3657                     struct i40e_dma_mem *mem)
3658 {
3659         if (!mem)
3660                 return I40E_ERR_PARAM;
3661
3662         PMD_DRV_LOG(DEBUG, "memzone %s to be freed with physical address: "
3663                     "%"PRIu64, ((const struct rte_memzone *)mem->zone)->name,
3664                     mem->pa);
3665         rte_memzone_free((const struct rte_memzone *)mem->zone);
3666         mem->zone = NULL;
3667         mem->va = NULL;
3668         mem->pa = (u64)0;
3669
3670         return I40E_SUCCESS;
3671 }
3672
3673 /**
3674  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3675  * @hw:   pointer to the HW structure
3676  * @mem:  pointer to mem struct to fill out
3677  * @size: size of memory requested
3678  **/
3679 enum i40e_status_code
3680 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3681                          struct i40e_virt_mem *mem,
3682                          u32 size)
3683 {
3684         if (!mem)
3685                 return I40E_ERR_PARAM;
3686
3687         mem->size = size;
3688         mem->va = rte_zmalloc("i40e", size, 0);
3689
3690         if (mem->va)
3691                 return I40E_SUCCESS;
3692         else
3693                 return I40E_ERR_NO_MEMORY;
3694 }
3695
3696 /**
3697  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3698  * @hw:   pointer to the HW structure
3699  * @mem:  pointer to mem struct to free
3700  **/
3701 enum i40e_status_code
3702 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3703                      struct i40e_virt_mem *mem)
3704 {
3705         if (!mem)
3706                 return I40E_ERR_PARAM;
3707
3708         rte_free(mem->va);
3709         mem->va = NULL;
3710
3711         return I40E_SUCCESS;
3712 }
3713
3714 void
3715 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3716 {
3717         rte_spinlock_init(&sp->spinlock);
3718 }
3719
3720 void
3721 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3722 {
3723         rte_spinlock_lock(&sp->spinlock);
3724 }
3725
3726 void
3727 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3728 {
3729         rte_spinlock_unlock(&sp->spinlock);
3730 }
3731
3732 void
3733 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3734 {
3735         return;
3736 }
3737
3738 /**
3739  * Get the hardware capabilities, which will be parsed
3740  * and saved into struct i40e_hw.
3741  */
3742 static int
3743 i40e_get_cap(struct i40e_hw *hw)
3744 {
3745         struct i40e_aqc_list_capabilities_element_resp *buf;
3746         uint16_t len, size = 0;
3747         int ret;
3748
3749         /* Calculate a huge enough buff for saving response data temporarily */
3750         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3751                                                 I40E_MAX_CAP_ELE_NUM;
3752         buf = rte_zmalloc("i40e", len, 0);
3753         if (!buf) {
3754                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3755                 return I40E_ERR_NO_MEMORY;
3756         }
3757
3758         /* Get, parse the capabilities and save it to hw */
3759         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3760                         i40e_aqc_opc_list_func_capabilities, NULL);
3761         if (ret != I40E_SUCCESS)
3762                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3763
3764         /* Free the temporary buffer after being used */
3765         rte_free(buf);
3766
3767         return ret;
3768 }
3769
3770 static int
3771 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3772 {
3773         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3774         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3775         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
3776         uint16_t qp_count = 0, vsi_count = 0;
3777
3778         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3779                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3780                 return -EINVAL;
3781         }
3782         /* Add the parameter init for LFC */
3783         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3784         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3785         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3786
3787         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3788         pf->max_num_vsi = hw->func_caps.num_vsis;
3789         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3790         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3791         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3792
3793         /* FDir queue/VSI allocation */
3794         pf->fdir_qp_offset = 0;
3795         if (hw->func_caps.fd) {
3796                 pf->flags |= I40E_FLAG_FDIR;
3797                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3798         } else {
3799                 pf->fdir_nb_qps = 0;
3800         }
3801         qp_count += pf->fdir_nb_qps;
3802         vsi_count += 1;
3803
3804         /* LAN queue/VSI allocation */
3805         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3806         if (!hw->func_caps.rss) {
3807                 pf->lan_nb_qps = 1;
3808         } else {
3809                 pf->flags |= I40E_FLAG_RSS;
3810                 if (hw->mac.type == I40E_MAC_X722)
3811                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3812                 pf->lan_nb_qps = pf->lan_nb_qp_max;
3813         }
3814         qp_count += pf->lan_nb_qps;
3815         vsi_count += 1;
3816
3817         /* VF queue/VSI allocation */
3818         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
3819         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
3820                 pf->flags |= I40E_FLAG_SRIOV;
3821                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3822                 pf->vf_num = pci_dev->max_vfs;
3823                 PMD_DRV_LOG(DEBUG, "%u VF VSIs, %u queues per VF VSI, "
3824                             "in total %u queues", pf->vf_num, pf->vf_nb_qps,
3825                             pf->vf_nb_qps * pf->vf_num);
3826         } else {
3827                 pf->vf_nb_qps = 0;
3828                 pf->vf_num = 0;
3829         }
3830         qp_count += pf->vf_nb_qps * pf->vf_num;
3831         vsi_count += pf->vf_num;
3832
3833         /* VMDq queue/VSI allocation */
3834         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
3835         pf->vmdq_nb_qps = 0;
3836         pf->max_nb_vmdq_vsi = 0;
3837         if (hw->func_caps.vmdq) {
3838                 if (qp_count < hw->func_caps.num_tx_qp &&
3839                         vsi_count < hw->func_caps.num_vsis) {
3840                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
3841                                 qp_count) / pf->vmdq_nb_qp_max;
3842
3843                         /* Limit the maximum number of VMDq vsi to the maximum
3844                          * ethdev can support
3845                          */
3846                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3847                                 hw->func_caps.num_vsis - vsi_count);
3848                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
3849                                 ETH_64_POOLS);
3850                         if (pf->max_nb_vmdq_vsi) {
3851                                 pf->flags |= I40E_FLAG_VMDQ;
3852                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
3853                                 PMD_DRV_LOG(DEBUG, "%u VMDQ VSIs, %u queues "
3854                                             "per VMDQ VSI, in total %u queues",
3855                                             pf->max_nb_vmdq_vsi,
3856                                             pf->vmdq_nb_qps, pf->vmdq_nb_qps *
3857                                             pf->max_nb_vmdq_vsi);
3858                         } else {
3859                                 PMD_DRV_LOG(INFO, "No enough queues left for "
3860                                             "VMDq");
3861                         }
3862                 } else {
3863                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
3864                 }
3865         }
3866         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
3867         vsi_count += pf->max_nb_vmdq_vsi;
3868
3869         if (hw->func_caps.dcb)
3870                 pf->flags |= I40E_FLAG_DCB;
3871
3872         if (qp_count > hw->func_caps.num_tx_qp) {
3873                 PMD_DRV_LOG(ERR, "Failed to allocate %u queues, which exceeds "
3874                             "the hardware maximum %u", qp_count,
3875                             hw->func_caps.num_tx_qp);
3876                 return -EINVAL;
3877         }
3878         if (vsi_count > hw->func_caps.num_vsis) {
3879                 PMD_DRV_LOG(ERR, "Failed to allocate %u VSIs, which exceeds "
3880                             "the hardware maximum %u", vsi_count,
3881                             hw->func_caps.num_vsis);
3882                 return -EINVAL;
3883         }
3884
3885         return 0;
3886 }
3887
3888 static int
3889 i40e_pf_get_switch_config(struct i40e_pf *pf)
3890 {
3891         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3892         struct i40e_aqc_get_switch_config_resp *switch_config;
3893         struct i40e_aqc_switch_config_element_resp *element;
3894         uint16_t start_seid = 0, num_reported;
3895         int ret;
3896
3897         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
3898                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
3899         if (!switch_config) {
3900                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
3901                 return -ENOMEM;
3902         }
3903
3904         /* Get the switch configurations */
3905         ret = i40e_aq_get_switch_config(hw, switch_config,
3906                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
3907         if (ret != I40E_SUCCESS) {
3908                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
3909                 goto fail;
3910         }
3911         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
3912         if (num_reported != 1) { /* The number should be 1 */
3913                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
3914                 goto fail;
3915         }
3916
3917         /* Parse the switch configuration elements */
3918         element = &(switch_config->element[0]);
3919         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
3920                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
3921                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
3922         } else
3923                 PMD_DRV_LOG(INFO, "Unknown element type");
3924
3925 fail:
3926         rte_free(switch_config);
3927
3928         return ret;
3929 }
3930
3931 static int
3932 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
3933                         uint32_t num)
3934 {
3935         struct pool_entry *entry;
3936
3937         if (pool == NULL || num == 0)
3938                 return -EINVAL;
3939
3940         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
3941         if (entry == NULL) {
3942                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
3943                 return -ENOMEM;
3944         }
3945
3946         /* queue heap initialize */
3947         pool->num_free = num;
3948         pool->num_alloc = 0;
3949         pool->base = base;
3950         LIST_INIT(&pool->alloc_list);
3951         LIST_INIT(&pool->free_list);
3952
3953         /* Initialize element  */
3954         entry->base = 0;
3955         entry->len = num;
3956
3957         LIST_INSERT_HEAD(&pool->free_list, entry, next);
3958         return 0;
3959 }
3960
3961 static void
3962 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
3963 {
3964         struct pool_entry *entry, *next_entry;
3965
3966         if (pool == NULL)
3967                 return;
3968
3969         for (entry = LIST_FIRST(&pool->alloc_list);
3970                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3971                         entry = next_entry) {
3972                 LIST_REMOVE(entry, next);
3973                 rte_free(entry);
3974         }
3975
3976         for (entry = LIST_FIRST(&pool->free_list);
3977                         entry && (next_entry = LIST_NEXT(entry, next), 1);
3978                         entry = next_entry) {
3979                 LIST_REMOVE(entry, next);
3980                 rte_free(entry);
3981         }
3982
3983         pool->num_free = 0;
3984         pool->num_alloc = 0;
3985         pool->base = 0;
3986         LIST_INIT(&pool->alloc_list);
3987         LIST_INIT(&pool->free_list);
3988 }
3989
3990 static int
3991 i40e_res_pool_free(struct i40e_res_pool_info *pool,
3992                        uint32_t base)
3993 {
3994         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
3995         uint32_t pool_offset;
3996         int insert;
3997
3998         if (pool == NULL) {
3999                 PMD_DRV_LOG(ERR, "Invalid parameter");
4000                 return -EINVAL;
4001         }
4002
4003         pool_offset = base - pool->base;
4004         /* Lookup in alloc list */
4005         LIST_FOREACH(entry, &pool->alloc_list, next) {
4006                 if (entry->base == pool_offset) {
4007                         valid_entry = entry;
4008                         LIST_REMOVE(entry, next);
4009                         break;
4010                 }
4011         }
4012
4013         /* Not find, return */
4014         if (valid_entry == NULL) {
4015                 PMD_DRV_LOG(ERR, "Failed to find entry");
4016                 return -EINVAL;
4017         }
4018
4019         /**
4020          * Found it, move it to free list  and try to merge.
4021          * In order to make merge easier, always sort it by qbase.
4022          * Find adjacent prev and last entries.
4023          */
4024         prev = next = NULL;
4025         LIST_FOREACH(entry, &pool->free_list, next) {
4026                 if (entry->base > valid_entry->base) {
4027                         next = entry;
4028                         break;
4029                 }
4030                 prev = entry;
4031         }
4032
4033         insert = 0;
4034         /* Try to merge with next one*/
4035         if (next != NULL) {
4036                 /* Merge with next one */
4037                 if (valid_entry->base + valid_entry->len == next->base) {
4038                         next->base = valid_entry->base;
4039                         next->len += valid_entry->len;
4040                         rte_free(valid_entry);
4041                         valid_entry = next;
4042                         insert = 1;
4043                 }
4044         }
4045
4046         if (prev != NULL) {
4047                 /* Merge with previous one */
4048                 if (prev->base + prev->len == valid_entry->base) {
4049                         prev->len += valid_entry->len;
4050                         /* If it merge with next one, remove next node */
4051                         if (insert == 1) {
4052                                 LIST_REMOVE(valid_entry, next);
4053                                 rte_free(valid_entry);
4054                         } else {
4055                                 rte_free(valid_entry);
4056                                 insert = 1;
4057                         }
4058                 }
4059         }
4060
4061         /* Not find any entry to merge, insert */
4062         if (insert == 0) {
4063                 if (prev != NULL)
4064                         LIST_INSERT_AFTER(prev, valid_entry, next);
4065                 else if (next != NULL)
4066                         LIST_INSERT_BEFORE(next, valid_entry, next);
4067                 else /* It's empty list, insert to head */
4068                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4069         }
4070
4071         pool->num_free += valid_entry->len;
4072         pool->num_alloc -= valid_entry->len;
4073
4074         return 0;
4075 }
4076
4077 static int
4078 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4079                        uint16_t num)
4080 {
4081         struct pool_entry *entry, *valid_entry;
4082
4083         if (pool == NULL || num == 0) {
4084                 PMD_DRV_LOG(ERR, "Invalid parameter");
4085                 return -EINVAL;
4086         }
4087
4088         if (pool->num_free < num) {
4089                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4090                             num, pool->num_free);
4091                 return -ENOMEM;
4092         }
4093
4094         valid_entry = NULL;
4095         /* Lookup  in free list and find most fit one */
4096         LIST_FOREACH(entry, &pool->free_list, next) {
4097                 if (entry->len >= num) {
4098                         /* Find best one */
4099                         if (entry->len == num) {
4100                                 valid_entry = entry;
4101                                 break;
4102                         }
4103                         if (valid_entry == NULL || valid_entry->len > entry->len)
4104                                 valid_entry = entry;
4105                 }
4106         }
4107
4108         /* Not find one to satisfy the request, return */
4109         if (valid_entry == NULL) {
4110                 PMD_DRV_LOG(ERR, "No valid entry found");
4111                 return -ENOMEM;
4112         }
4113         /**
4114          * The entry have equal queue number as requested,
4115          * remove it from alloc_list.
4116          */
4117         if (valid_entry->len == num) {
4118                 LIST_REMOVE(valid_entry, next);
4119         } else {
4120                 /**
4121                  * The entry have more numbers than requested,
4122                  * create a new entry for alloc_list and minus its
4123                  * queue base and number in free_list.
4124                  */
4125                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4126                 if (entry == NULL) {
4127                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
4128                                     "resource pool");
4129                         return -ENOMEM;
4130                 }
4131                 entry->base = valid_entry->base;
4132                 entry->len = num;
4133                 valid_entry->base += num;
4134                 valid_entry->len -= num;
4135                 valid_entry = entry;
4136         }
4137
4138         /* Insert it into alloc list, not sorted */
4139         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4140
4141         pool->num_free -= valid_entry->len;
4142         pool->num_alloc += valid_entry->len;
4143
4144         return valid_entry->base + pool->base;
4145 }
4146
4147 /**
4148  * bitmap_is_subset - Check whether src2 is subset of src1
4149  **/
4150 static inline int
4151 bitmap_is_subset(uint8_t src1, uint8_t src2)
4152 {
4153         return !((src1 ^ src2) & src2);
4154 }
4155
4156 static enum i40e_status_code
4157 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4158 {
4159         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4160
4161         /* If DCB is not supported, only default TC is supported */
4162         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4163                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4164                 return I40E_NOT_SUPPORTED;
4165         }
4166
4167         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4168                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
4169                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
4170                             enabled_tcmap);
4171                 return I40E_NOT_SUPPORTED;
4172         }
4173         return I40E_SUCCESS;
4174 }
4175
4176 int
4177 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4178                                 struct i40e_vsi_vlan_pvid_info *info)
4179 {
4180         struct i40e_hw *hw;
4181         struct i40e_vsi_context ctxt;
4182         uint8_t vlan_flags = 0;
4183         int ret;
4184
4185         if (vsi == NULL || info == NULL) {
4186                 PMD_DRV_LOG(ERR, "invalid parameters");
4187                 return I40E_ERR_PARAM;
4188         }
4189
4190         if (info->on) {
4191                 vsi->info.pvid = info->config.pvid;
4192                 /**
4193                  * If insert pvid is enabled, only tagged pkts are
4194                  * allowed to be sent out.
4195                  */
4196                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4197                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4198         } else {
4199                 vsi->info.pvid = 0;
4200                 if (info->config.reject.tagged == 0)
4201                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4202
4203                 if (info->config.reject.untagged == 0)
4204                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4205         }
4206         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4207                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4208         vsi->info.port_vlan_flags |= vlan_flags;
4209         vsi->info.valid_sections =
4210                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4211         memset(&ctxt, 0, sizeof(ctxt));
4212         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4213         ctxt.seid = vsi->seid;
4214
4215         hw = I40E_VSI_TO_HW(vsi);
4216         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4217         if (ret != I40E_SUCCESS)
4218                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4219
4220         return ret;
4221 }
4222
4223 static int
4224 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4225 {
4226         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4227         int i, ret;
4228         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4229
4230         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4231         if (ret != I40E_SUCCESS)
4232                 return ret;
4233
4234         if (!vsi->seid) {
4235                 PMD_DRV_LOG(ERR, "seid not valid");
4236                 return -EINVAL;
4237         }
4238
4239         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4240         tc_bw_data.tc_valid_bits = enabled_tcmap;
4241         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4242                 tc_bw_data.tc_bw_credits[i] =
4243                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4244
4245         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4246         if (ret != I40E_SUCCESS) {
4247                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4248                 return ret;
4249         }
4250
4251         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4252                                         sizeof(vsi->info.qs_handle));
4253         return I40E_SUCCESS;
4254 }
4255
4256 static enum i40e_status_code
4257 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4258                                  struct i40e_aqc_vsi_properties_data *info,
4259                                  uint8_t enabled_tcmap)
4260 {
4261         enum i40e_status_code ret;
4262         int i, total_tc = 0;
4263         uint16_t qpnum_per_tc, bsf, qp_idx;
4264
4265         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4266         if (ret != I40E_SUCCESS)
4267                 return ret;
4268
4269         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4270                 if (enabled_tcmap & (1 << i))
4271                         total_tc++;
4272         vsi->enabled_tc = enabled_tcmap;
4273
4274         /* Number of queues per enabled TC */
4275         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4276         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4277         bsf = rte_bsf32(qpnum_per_tc);
4278
4279         /* Adjust the queue number to actual queues that can be applied */
4280         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4281                 vsi->nb_qps = qpnum_per_tc * total_tc;
4282
4283         /**
4284          * Configure TC and queue mapping parameters, for enabled TC,
4285          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4286          * default queue will serve it.
4287          */
4288         qp_idx = 0;
4289         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4290                 if (vsi->enabled_tc & (1 << i)) {
4291                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4292                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4293                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4294                         qp_idx += qpnum_per_tc;
4295                 } else
4296                         info->tc_mapping[i] = 0;
4297         }
4298
4299         /* Associate queue number with VSI */
4300         if (vsi->type == I40E_VSI_SRIOV) {
4301                 info->mapping_flags |=
4302                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4303                 for (i = 0; i < vsi->nb_qps; i++)
4304                         info->queue_mapping[i] =
4305                                 rte_cpu_to_le_16(vsi->base_queue + i);
4306         } else {
4307                 info->mapping_flags |=
4308                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4309                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4310         }
4311         info->valid_sections |=
4312                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4313
4314         return I40E_SUCCESS;
4315 }
4316
4317 static int
4318 i40e_veb_release(struct i40e_veb *veb)
4319 {
4320         struct i40e_vsi *vsi;
4321         struct i40e_hw *hw;
4322
4323         if (veb == NULL)
4324                 return -EINVAL;
4325
4326         if (!TAILQ_EMPTY(&veb->head)) {
4327                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4328                 return -EACCES;
4329         }
4330         /* associate_vsi field is NULL for floating VEB */
4331         if (veb->associate_vsi != NULL) {
4332                 vsi = veb->associate_vsi;
4333                 hw = I40E_VSI_TO_HW(vsi);
4334
4335                 vsi->uplink_seid = veb->uplink_seid;
4336                 vsi->veb = NULL;
4337         } else {
4338                 veb->associate_pf->main_vsi->floating_veb = NULL;
4339                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4340         }
4341
4342         i40e_aq_delete_element(hw, veb->seid, NULL);
4343         rte_free(veb);
4344         return I40E_SUCCESS;
4345 }
4346
4347 /* Setup a veb */
4348 static struct i40e_veb *
4349 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4350 {
4351         struct i40e_veb *veb;
4352         int ret;
4353         struct i40e_hw *hw;
4354
4355         if (pf == NULL) {
4356                 PMD_DRV_LOG(ERR,
4357                             "veb setup failed, associated PF shouldn't null");
4358                 return NULL;
4359         }
4360         hw = I40E_PF_TO_HW(pf);
4361
4362         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4363         if (!veb) {
4364                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4365                 goto fail;
4366         }
4367
4368         veb->associate_vsi = vsi;
4369         veb->associate_pf = pf;
4370         TAILQ_INIT(&veb->head);
4371         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4372
4373         /* create floating veb if vsi is NULL */
4374         if (vsi != NULL) {
4375                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4376                                       I40E_DEFAULT_TCMAP, false,
4377                                       &veb->seid, false, NULL);
4378         } else {
4379                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4380                                       true, &veb->seid, false, NULL);
4381         }
4382
4383         if (ret != I40E_SUCCESS) {
4384                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4385                             hw->aq.asq_last_status);
4386                 goto fail;
4387         }
4388
4389         /* get statistics index */
4390         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4391                                 &veb->stats_idx, NULL, NULL, NULL);
4392         if (ret != I40E_SUCCESS) {
4393                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4394                             hw->aq.asq_last_status);
4395                 goto fail;
4396         }
4397         /* Get VEB bandwidth, to be implemented */
4398         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4399         if (vsi)
4400                 vsi->uplink_seid = veb->seid;
4401
4402         return veb;
4403 fail:
4404         rte_free(veb);
4405         return NULL;
4406 }
4407
4408 int
4409 i40e_vsi_release(struct i40e_vsi *vsi)
4410 {
4411         struct i40e_pf *pf;
4412         struct i40e_hw *hw;
4413         struct i40e_vsi_list *vsi_list;
4414         void *temp;
4415         int ret;
4416         struct i40e_mac_filter *f;
4417         uint16_t user_param;
4418
4419         if (!vsi)
4420                 return I40E_SUCCESS;
4421
4422         user_param = vsi->user_param;
4423
4424         pf = I40E_VSI_TO_PF(vsi);
4425         hw = I40E_VSI_TO_HW(vsi);
4426
4427         /* VSI has child to attach, release child first */
4428         if (vsi->veb) {
4429                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4430                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4431                                 return -1;
4432                 }
4433                 i40e_veb_release(vsi->veb);
4434         }
4435
4436         if (vsi->floating_veb) {
4437                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4438                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4439                                 return -1;
4440                 }
4441         }
4442
4443         /* Remove all macvlan filters of the VSI */
4444         i40e_vsi_remove_all_macvlan_filter(vsi);
4445         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4446                 rte_free(f);
4447
4448         if (vsi->type != I40E_VSI_MAIN &&
4449             ((vsi->type != I40E_VSI_SRIOV) ||
4450             !pf->floating_veb_list[user_param])) {
4451                 /* Remove vsi from parent's sibling list */
4452                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4453                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4454                         return I40E_ERR_PARAM;
4455                 }
4456                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4457                                 &vsi->sib_vsi_list, list);
4458
4459                 /* Remove all switch element of the VSI */
4460                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4461                 if (ret != I40E_SUCCESS)
4462                         PMD_DRV_LOG(ERR, "Failed to delete element");
4463         }
4464
4465         if ((vsi->type == I40E_VSI_SRIOV) &&
4466             pf->floating_veb_list[user_param]) {
4467                 /* Remove vsi from parent's sibling list */
4468                 if (vsi->parent_vsi == NULL ||
4469                     vsi->parent_vsi->floating_veb == NULL) {
4470                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4471                         return I40E_ERR_PARAM;
4472                 }
4473                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4474                              &vsi->sib_vsi_list, list);
4475
4476                 /* Remove all switch element of the VSI */
4477                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4478                 if (ret != I40E_SUCCESS)
4479                         PMD_DRV_LOG(ERR, "Failed to delete element");
4480         }
4481
4482         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4483
4484         if (vsi->type != I40E_VSI_SRIOV)
4485                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4486         rte_free(vsi);
4487
4488         return I40E_SUCCESS;
4489 }
4490
4491 static int
4492 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4493 {
4494         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4495         struct i40e_aqc_remove_macvlan_element_data def_filter;
4496         struct i40e_mac_filter_info filter;
4497         int ret;
4498
4499         if (vsi->type != I40E_VSI_MAIN)
4500                 return I40E_ERR_CONFIG;
4501         memset(&def_filter, 0, sizeof(def_filter));
4502         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4503                                         ETH_ADDR_LEN);
4504         def_filter.vlan_tag = 0;
4505         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4506                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4507         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4508         if (ret != I40E_SUCCESS) {
4509                 struct i40e_mac_filter *f;
4510                 struct ether_addr *mac;
4511
4512                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
4513                             "macvlan filter");
4514                 /* It needs to add the permanent mac into mac list */
4515                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4516                 if (f == NULL) {
4517                         PMD_DRV_LOG(ERR, "failed to allocate memory");
4518                         return I40E_ERR_NO_MEMORY;
4519                 }
4520                 mac = &f->mac_info.mac_addr;
4521                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4522                                 ETH_ADDR_LEN);
4523                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4524                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4525                 vsi->mac_num++;
4526
4527                 return ret;
4528         }
4529         (void)rte_memcpy(&filter.mac_addr,
4530                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4531         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4532         return i40e_vsi_add_mac(vsi, &filter);
4533 }
4534
4535 /*
4536  * i40e_vsi_get_bw_config - Query VSI BW Information
4537  * @vsi: the VSI to be queried
4538  *
4539  * Returns 0 on success, negative value on failure
4540  */
4541 static enum i40e_status_code
4542 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4543 {
4544         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4545         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4546         struct i40e_hw *hw = &vsi->adapter->hw;
4547         i40e_status ret;
4548         int i;
4549         uint32_t bw_max;
4550
4551         memset(&bw_config, 0, sizeof(bw_config));
4552         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4553         if (ret != I40E_SUCCESS) {
4554                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4555                             hw->aq.asq_last_status);
4556                 return ret;
4557         }
4558
4559         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4560         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4561                                         &ets_sla_config, NULL);
4562         if (ret != I40E_SUCCESS) {
4563                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
4564                             "configuration %u", hw->aq.asq_last_status);
4565                 return ret;
4566         }
4567
4568         /* store and print out BW info */
4569         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4570         vsi->bw_info.bw_max = bw_config.max_bw;
4571         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4572         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4573         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4574                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4575                      I40E_16_BIT_WIDTH);
4576         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4577                 vsi->bw_info.bw_ets_share_credits[i] =
4578                                 ets_sla_config.share_credits[i];
4579                 vsi->bw_info.bw_ets_credits[i] =
4580                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4581                 /* 4 bits per TC, 4th bit is reserved */
4582                 vsi->bw_info.bw_ets_max[i] =
4583                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4584                                   RTE_LEN2MASK(3, uint8_t));
4585                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4586                             vsi->bw_info.bw_ets_share_credits[i]);
4587                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4588                             vsi->bw_info.bw_ets_credits[i]);
4589                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4590                             vsi->bw_info.bw_ets_max[i]);
4591         }
4592
4593         return I40E_SUCCESS;
4594 }
4595
4596 /* i40e_enable_pf_lb
4597  * @pf: pointer to the pf structure
4598  *
4599  * allow loopback on pf
4600  */
4601 static inline void
4602 i40e_enable_pf_lb(struct i40e_pf *pf)
4603 {
4604         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4605         struct i40e_vsi_context ctxt;
4606         int ret;
4607
4608         /* Use the FW API if FW >= v5.0 */
4609         if (hw->aq.fw_maj_ver < 5) {
4610                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4611                 return;
4612         }
4613
4614         memset(&ctxt, 0, sizeof(ctxt));
4615         ctxt.seid = pf->main_vsi_seid;
4616         ctxt.pf_num = hw->pf_id;
4617         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4618         if (ret) {
4619                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4620                             ret, hw->aq.asq_last_status);
4621                 return;
4622         }
4623         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4624         ctxt.info.valid_sections =
4625                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4626         ctxt.info.switch_id |=
4627                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4628
4629         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4630         if (ret)
4631                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d\n",
4632                             hw->aq.asq_last_status);
4633 }
4634
4635 /* Setup a VSI */
4636 struct i40e_vsi *
4637 i40e_vsi_setup(struct i40e_pf *pf,
4638                enum i40e_vsi_type type,
4639                struct i40e_vsi *uplink_vsi,
4640                uint16_t user_param)
4641 {
4642         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4643         struct i40e_vsi *vsi;
4644         struct i40e_mac_filter_info filter;
4645         int ret;
4646         struct i40e_vsi_context ctxt;
4647         struct ether_addr broadcast =
4648                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4649
4650         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4651             uplink_vsi == NULL) {
4652                 PMD_DRV_LOG(ERR, "VSI setup failed, "
4653                             "VSI link shouldn't be NULL");
4654                 return NULL;
4655         }
4656
4657         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4658                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
4659                             "uplink VSI should be NULL");
4660                 return NULL;
4661         }
4662
4663         /* two situations
4664          * 1.type is not MAIN and uplink vsi is not NULL
4665          * If uplink vsi didn't setup VEB, create one first under veb field
4666          * 2.type is SRIOV and the uplink is NULL
4667          * If floating VEB is NULL, create one veb under floating veb field
4668          */
4669
4670         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4671             uplink_vsi->veb == NULL) {
4672                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4673
4674                 if (uplink_vsi->veb == NULL) {
4675                         PMD_DRV_LOG(ERR, "VEB setup failed");
4676                         return NULL;
4677                 }
4678                 /* set ALLOWLOOPBACk on pf, when veb is created */
4679                 i40e_enable_pf_lb(pf);
4680         }
4681
4682         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4683             pf->main_vsi->floating_veb == NULL) {
4684                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4685
4686                 if (pf->main_vsi->floating_veb == NULL) {
4687                         PMD_DRV_LOG(ERR, "VEB setup failed");
4688                         return NULL;
4689                 }
4690         }
4691
4692         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4693         if (!vsi) {
4694                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4695                 return NULL;
4696         }
4697         TAILQ_INIT(&vsi->mac_list);
4698         vsi->type = type;
4699         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4700         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4701         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4702         vsi->user_param = user_param;
4703         /* Allocate queues */
4704         switch (vsi->type) {
4705         case I40E_VSI_MAIN  :
4706                 vsi->nb_qps = pf->lan_nb_qps;
4707                 break;
4708         case I40E_VSI_SRIOV :
4709                 vsi->nb_qps = pf->vf_nb_qps;
4710                 break;
4711         case I40E_VSI_VMDQ2:
4712                 vsi->nb_qps = pf->vmdq_nb_qps;
4713                 break;
4714         case I40E_VSI_FDIR:
4715                 vsi->nb_qps = pf->fdir_nb_qps;
4716                 break;
4717         default:
4718                 goto fail_mem;
4719         }
4720         /*
4721          * The filter status descriptor is reported in rx queue 0,
4722          * while the tx queue for fdir filter programming has no
4723          * such constraints, can be non-zero queues.
4724          * To simplify it, choose FDIR vsi use queue 0 pair.
4725          * To make sure it will use queue 0 pair, queue allocation
4726          * need be done before this function is called
4727          */
4728         if (type != I40E_VSI_FDIR) {
4729                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4730                         if (ret < 0) {
4731                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4732                                                 vsi->seid, ret);
4733                                 goto fail_mem;
4734                         }
4735                         vsi->base_queue = ret;
4736         } else
4737                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4738
4739         /* VF has MSIX interrupt in VF range, don't allocate here */
4740         if (type == I40E_VSI_MAIN) {
4741                 ret = i40e_res_pool_alloc(&pf->msix_pool,
4742                                           RTE_MIN(vsi->nb_qps,
4743                                                   RTE_MAX_RXTX_INTR_VEC_ID));
4744                 if (ret < 0) {
4745                         PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4746                                     vsi->seid, ret);
4747                         goto fail_queue_alloc;
4748                 }
4749                 vsi->msix_intr = ret;
4750                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4751         } else if (type != I40E_VSI_SRIOV) {
4752                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4753                 if (ret < 0) {
4754                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4755                         goto fail_queue_alloc;
4756                 }
4757                 vsi->msix_intr = ret;
4758                 vsi->nb_msix = 1;
4759         } else {
4760                 vsi->msix_intr = 0;
4761                 vsi->nb_msix = 0;
4762         }
4763
4764         /* Add VSI */
4765         if (type == I40E_VSI_MAIN) {
4766                 /* For main VSI, no need to add since it's default one */
4767                 vsi->uplink_seid = pf->mac_seid;
4768                 vsi->seid = pf->main_vsi_seid;
4769                 /* Bind queues with specific MSIX interrupt */
4770                 /**
4771                  * Needs 2 interrupt at least, one for misc cause which will
4772                  * enabled from OS side, Another for queues binding the
4773                  * interrupt from device side only.
4774                  */
4775
4776                 /* Get default VSI parameters from hardware */
4777                 memset(&ctxt, 0, sizeof(ctxt));
4778                 ctxt.seid = vsi->seid;
4779                 ctxt.pf_num = hw->pf_id;
4780                 ctxt.uplink_seid = vsi->uplink_seid;
4781                 ctxt.vf_num = 0;
4782                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4783                 if (ret != I40E_SUCCESS) {
4784                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
4785                         goto fail_msix_alloc;
4786                 }
4787                 (void)rte_memcpy(&vsi->info, &ctxt.info,
4788                         sizeof(struct i40e_aqc_vsi_properties_data));
4789                 vsi->vsi_id = ctxt.vsi_number;
4790                 vsi->info.valid_sections = 0;
4791
4792                 /* Configure tc, enabled TC0 only */
4793                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4794                         I40E_SUCCESS) {
4795                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4796                         goto fail_msix_alloc;
4797                 }
4798
4799                 /* TC, queue mapping */
4800                 memset(&ctxt, 0, sizeof(ctxt));
4801                 vsi->info.valid_sections |=
4802                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4803                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4804                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4805                 (void)rte_memcpy(&ctxt.info, &vsi->info,
4806                         sizeof(struct i40e_aqc_vsi_properties_data));
4807                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4808                                                 I40E_DEFAULT_TCMAP);
4809                 if (ret != I40E_SUCCESS) {
4810                         PMD_DRV_LOG(ERR, "Failed to configure "
4811                                     "TC queue mapping");
4812                         goto fail_msix_alloc;
4813                 }
4814                 ctxt.seid = vsi->seid;
4815                 ctxt.pf_num = hw->pf_id;
4816                 ctxt.uplink_seid = vsi->uplink_seid;
4817                 ctxt.vf_num = 0;
4818
4819                 /* Update VSI parameters */
4820                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4821                 if (ret != I40E_SUCCESS) {
4822                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
4823                         goto fail_msix_alloc;
4824                 }
4825
4826                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
4827                                                 sizeof(vsi->info.tc_mapping));
4828                 (void)rte_memcpy(&vsi->info.queue_mapping,
4829                                 &ctxt.info.queue_mapping,
4830                         sizeof(vsi->info.queue_mapping));
4831                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
4832                 vsi->info.valid_sections = 0;
4833
4834                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
4835                                 ETH_ADDR_LEN);
4836
4837                 /**
4838                  * Updating default filter settings are necessary to prevent
4839                  * reception of tagged packets.
4840                  * Some old firmware configurations load a default macvlan
4841                  * filter which accepts both tagged and untagged packets.
4842                  * The updating is to use a normal filter instead if needed.
4843                  * For NVM 4.2.2 or after, the updating is not needed anymore.
4844                  * The firmware with correct configurations load the default
4845                  * macvlan filter which is expected and cannot be removed.
4846                  */
4847                 i40e_update_default_filter_setting(vsi);
4848                 i40e_config_qinq(hw, vsi);
4849         } else if (type == I40E_VSI_SRIOV) {
4850                 memset(&ctxt, 0, sizeof(ctxt));
4851                 /**
4852                  * For other VSI, the uplink_seid equals to uplink VSI's
4853                  * uplink_seid since they share same VEB
4854                  */
4855                 if (uplink_vsi == NULL)
4856                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
4857                 else
4858                         vsi->uplink_seid = uplink_vsi->uplink_seid;
4859                 ctxt.pf_num = hw->pf_id;
4860                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
4861                 ctxt.uplink_seid = vsi->uplink_seid;
4862                 ctxt.connection_type = 0x1;
4863                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
4864
4865                 /* Use the VEB configuration if FW >= v5.0 */
4866                 if (hw->aq.fw_maj_ver >= 5) {
4867                         /* Configure switch ID */
4868                         ctxt.info.valid_sections |=
4869                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4870                         ctxt.info.switch_id =
4871                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4872                 }
4873
4874                 /* Configure port/vlan */
4875                 ctxt.info.valid_sections |=
4876                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4877                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4878                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4879                                                 I40E_DEFAULT_TCMAP);
4880                 if (ret != I40E_SUCCESS) {
4881                         PMD_DRV_LOG(ERR, "Failed to configure "
4882                                     "TC queue mapping");
4883                         goto fail_msix_alloc;
4884                 }
4885                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4886                 ctxt.info.valid_sections |=
4887                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4888                 /**
4889                  * Since VSI is not created yet, only configure parameter,
4890                  * will add vsi below.
4891                  */
4892
4893                 i40e_config_qinq(hw, vsi);
4894         } else if (type == I40E_VSI_VMDQ2) {
4895                 memset(&ctxt, 0, sizeof(ctxt));
4896                 /*
4897                  * For other VSI, the uplink_seid equals to uplink VSI's
4898                  * uplink_seid since they share same VEB
4899                  */
4900                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4901                 ctxt.pf_num = hw->pf_id;
4902                 ctxt.vf_num = 0;
4903                 ctxt.uplink_seid = vsi->uplink_seid;
4904                 ctxt.connection_type = 0x1;
4905                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
4906
4907                 ctxt.info.valid_sections |=
4908                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4909                 /* user_param carries flag to enable loop back */
4910                 if (user_param) {
4911                         ctxt.info.switch_id =
4912                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
4913                         ctxt.info.switch_id |=
4914                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4915                 }
4916
4917                 /* Configure port/vlan */
4918                 ctxt.info.valid_sections |=
4919                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4920                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
4921                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4922                                                 I40E_DEFAULT_TCMAP);
4923                 if (ret != I40E_SUCCESS) {
4924                         PMD_DRV_LOG(ERR, "Failed to configure "
4925                                         "TC queue mapping");
4926                         goto fail_msix_alloc;
4927                 }
4928                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4929                 ctxt.info.valid_sections |=
4930                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4931         } else if (type == I40E_VSI_FDIR) {
4932                 memset(&ctxt, 0, sizeof(ctxt));
4933                 vsi->uplink_seid = uplink_vsi->uplink_seid;
4934                 ctxt.pf_num = hw->pf_id;
4935                 ctxt.vf_num = 0;
4936                 ctxt.uplink_seid = vsi->uplink_seid;
4937                 ctxt.connection_type = 0x1;     /* regular data port */
4938                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4939                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
4940                                                 I40E_DEFAULT_TCMAP);
4941                 if (ret != I40E_SUCCESS) {
4942                         PMD_DRV_LOG(ERR, "Failed to configure "
4943                                         "TC queue mapping.");
4944                         goto fail_msix_alloc;
4945                 }
4946                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
4947                 ctxt.info.valid_sections |=
4948                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
4949         } else {
4950                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
4951                 goto fail_msix_alloc;
4952         }
4953
4954         if (vsi->type != I40E_VSI_MAIN) {
4955                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
4956                 if (ret != I40E_SUCCESS) {
4957                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
4958                                     hw->aq.asq_last_status);
4959                         goto fail_msix_alloc;
4960                 }
4961                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
4962                 vsi->info.valid_sections = 0;
4963                 vsi->seid = ctxt.seid;
4964                 vsi->vsi_id = ctxt.vsi_number;
4965                 vsi->sib_vsi_list.vsi = vsi;
4966                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
4967                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
4968                                           &vsi->sib_vsi_list, list);
4969                 } else {
4970                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
4971                                           &vsi->sib_vsi_list, list);
4972                 }
4973         }
4974
4975         /* MAC/VLAN configuration */
4976         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
4977         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4978
4979         ret = i40e_vsi_add_mac(vsi, &filter);
4980         if (ret != I40E_SUCCESS) {
4981                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4982                 goto fail_msix_alloc;
4983         }
4984
4985         /* Get VSI BW information */
4986         i40e_vsi_get_bw_config(vsi);
4987         return vsi;
4988 fail_msix_alloc:
4989         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
4990 fail_queue_alloc:
4991         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
4992 fail_mem:
4993         rte_free(vsi);
4994         return NULL;
4995 }
4996
4997 /* Configure vlan filter on or off */
4998 int
4999 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5000 {
5001         int i, num;
5002         struct i40e_mac_filter *f;
5003         void *temp;
5004         struct i40e_mac_filter_info *mac_filter;
5005         enum rte_mac_filter_type desired_filter;
5006         int ret = I40E_SUCCESS;
5007
5008         if (on) {
5009                 /* Filter to match MAC and VLAN */
5010                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5011         } else {
5012                 /* Filter to match only MAC */
5013                 desired_filter = RTE_MAC_PERFECT_MATCH;
5014         }
5015
5016         num = vsi->mac_num;
5017
5018         mac_filter = rte_zmalloc("mac_filter_info_data",
5019                                  num * sizeof(*mac_filter), 0);
5020         if (mac_filter == NULL) {
5021                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5022                 return I40E_ERR_NO_MEMORY;
5023         }
5024
5025         i = 0;
5026
5027         /* Remove all existing mac */
5028         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5029                 mac_filter[i] = f->mac_info;
5030                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5031                 if (ret) {
5032                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5033                                     on ? "enable" : "disable");
5034                         goto DONE;
5035                 }
5036                 i++;
5037         }
5038
5039         /* Override with new filter */
5040         for (i = 0; i < num; i++) {
5041                 mac_filter[i].filter_type = desired_filter;
5042                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5043                 if (ret) {
5044                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5045                                     on ? "enable" : "disable");
5046                         goto DONE;
5047                 }
5048         }
5049
5050 DONE:
5051         rte_free(mac_filter);
5052         return ret;
5053 }
5054
5055 /* Configure vlan stripping on or off */
5056 int
5057 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5058 {
5059         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5060         struct i40e_vsi_context ctxt;
5061         uint8_t vlan_flags;
5062         int ret = I40E_SUCCESS;
5063
5064         /* Check if it has been already on or off */
5065         if (vsi->info.valid_sections &
5066                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5067                 if (on) {
5068                         if ((vsi->info.port_vlan_flags &
5069                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5070                                 return 0; /* already on */
5071                 } else {
5072                         if ((vsi->info.port_vlan_flags &
5073                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5074                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5075                                 return 0; /* already off */
5076                 }
5077         }
5078
5079         if (on)
5080                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5081         else
5082                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5083         vsi->info.valid_sections =
5084                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5085         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5086         vsi->info.port_vlan_flags |= vlan_flags;
5087         ctxt.seid = vsi->seid;
5088         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5089         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5090         if (ret)
5091                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5092                             on ? "enable" : "disable");
5093
5094         return ret;
5095 }
5096
5097 static int
5098 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5099 {
5100         struct rte_eth_dev_data *data = dev->data;
5101         int ret;
5102         int mask = 0;
5103
5104         /* Apply vlan offload setting */
5105         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK;
5106         i40e_vlan_offload_set(dev, mask);
5107
5108         /* Apply double-vlan setting, not implemented yet */
5109
5110         /* Apply pvid setting */
5111         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5112                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5113         if (ret)
5114                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5115
5116         return ret;
5117 }
5118
5119 static int
5120 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5121 {
5122         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5123
5124         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5125 }
5126
5127 static int
5128 i40e_update_flow_control(struct i40e_hw *hw)
5129 {
5130 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5131         struct i40e_link_status link_status;
5132         uint32_t rxfc = 0, txfc = 0, reg;
5133         uint8_t an_info;
5134         int ret;
5135
5136         memset(&link_status, 0, sizeof(link_status));
5137         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5138         if (ret != I40E_SUCCESS) {
5139                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5140                 goto write_reg; /* Disable flow control */
5141         }
5142
5143         an_info = hw->phy.link_info.an_info;
5144         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5145                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5146                 ret = I40E_ERR_NOT_READY;
5147                 goto write_reg; /* Disable flow control */
5148         }
5149         /**
5150          * If link auto negotiation is enabled, flow control needs to
5151          * be configured according to it
5152          */
5153         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5154         case I40E_LINK_PAUSE_RXTX:
5155                 rxfc = 1;
5156                 txfc = 1;
5157                 hw->fc.current_mode = I40E_FC_FULL;
5158                 break;
5159         case I40E_AQ_LINK_PAUSE_RX:
5160                 rxfc = 1;
5161                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5162                 break;
5163         case I40E_AQ_LINK_PAUSE_TX:
5164                 txfc = 1;
5165                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5166                 break;
5167         default:
5168                 hw->fc.current_mode = I40E_FC_NONE;
5169                 break;
5170         }
5171
5172 write_reg:
5173         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5174                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5175         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5176         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5177         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5178         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5179
5180         return ret;
5181 }
5182
5183 /* PF setup */
5184 static int
5185 i40e_pf_setup(struct i40e_pf *pf)
5186 {
5187         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5188         struct i40e_filter_control_settings settings;
5189         struct i40e_vsi *vsi;
5190         int ret;
5191
5192         /* Clear all stats counters */
5193         pf->offset_loaded = FALSE;
5194         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5195         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5196
5197         ret = i40e_pf_get_switch_config(pf);
5198         if (ret != I40E_SUCCESS) {
5199                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5200                 return ret;
5201         }
5202         if (pf->flags & I40E_FLAG_FDIR) {
5203                 /* make queue allocated first, let FDIR use queue pair 0*/
5204                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5205                 if (ret != I40E_FDIR_QUEUE_ID) {
5206                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
5207                                     " ret =%d", ret);
5208                         pf->flags &= ~I40E_FLAG_FDIR;
5209                 }
5210         }
5211         /*  main VSI setup */
5212         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5213         if (!vsi) {
5214                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5215                 return I40E_ERR_NOT_READY;
5216         }
5217         pf->main_vsi = vsi;
5218
5219         /* Configure filter control */
5220         memset(&settings, 0, sizeof(settings));
5221         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5222                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5223         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5224                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5225         else {
5226                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
5227                                                 hw->func_caps.rss_table_size);
5228                 return I40E_ERR_PARAM;
5229         }
5230         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
5231                         "size: %u\n", hw->func_caps.rss_table_size);
5232         pf->hash_lut_size = hw->func_caps.rss_table_size;
5233
5234         /* Enable ethtype and macvlan filters */
5235         settings.enable_ethtype = TRUE;
5236         settings.enable_macvlan = TRUE;
5237         ret = i40e_set_filter_control(hw, &settings);
5238         if (ret)
5239                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5240                                                                 ret);
5241
5242         /* Update flow control according to the auto negotiation */
5243         i40e_update_flow_control(hw);
5244
5245         return I40E_SUCCESS;
5246 }
5247
5248 int
5249 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5250 {
5251         uint32_t reg;
5252         uint16_t j;
5253
5254         /**
5255          * Set or clear TX Queue Disable flags,
5256          * which is required by hardware.
5257          */
5258         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5259         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5260
5261         /* Wait until the request is finished */
5262         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5263                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5264                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5265                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5266                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5267                                                         & 0x1))) {
5268                         break;
5269                 }
5270         }
5271         if (on) {
5272                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5273                         return I40E_SUCCESS; /* already on, skip next steps */
5274
5275                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5276                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5277         } else {
5278                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5279                         return I40E_SUCCESS; /* already off, skip next steps */
5280                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5281         }
5282         /* Write the register */
5283         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5284         /* Check the result */
5285         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5286                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5287                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5288                 if (on) {
5289                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5290                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5291                                 break;
5292                 } else {
5293                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5294                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5295                                 break;
5296                 }
5297         }
5298         /* Check if it is timeout */
5299         if (j >= I40E_CHK_Q_ENA_COUNT) {
5300                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5301                             (on ? "enable" : "disable"), q_idx);
5302                 return I40E_ERR_TIMEOUT;
5303         }
5304
5305         return I40E_SUCCESS;
5306 }
5307
5308 /* Swith on or off the tx queues */
5309 static int
5310 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5311 {
5312         struct rte_eth_dev_data *dev_data = pf->dev_data;
5313         struct i40e_tx_queue *txq;
5314         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5315         uint16_t i;
5316         int ret;
5317
5318         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5319                 txq = dev_data->tx_queues[i];
5320                 /* Don't operate the queue if not configured or
5321                  * if starting only per queue */
5322                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5323                         continue;
5324                 if (on)
5325                         ret = i40e_dev_tx_queue_start(dev, i);
5326                 else
5327                         ret = i40e_dev_tx_queue_stop(dev, i);
5328                 if ( ret != I40E_SUCCESS)
5329                         return ret;
5330         }
5331
5332         return I40E_SUCCESS;
5333 }
5334
5335 int
5336 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5337 {
5338         uint32_t reg;
5339         uint16_t j;
5340
5341         /* Wait until the request is finished */
5342         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5343                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5344                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5345                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5346                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5347                         break;
5348         }
5349
5350         if (on) {
5351                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5352                         return I40E_SUCCESS; /* Already on, skip next steps */
5353                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5354         } else {
5355                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5356                         return I40E_SUCCESS; /* Already off, skip next steps */
5357                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5358         }
5359
5360         /* Write the register */
5361         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5362         /* Check the result */
5363         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5364                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5365                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5366                 if (on) {
5367                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5368                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5369                                 break;
5370                 } else {
5371                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5372                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5373                                 break;
5374                 }
5375         }
5376
5377         /* Check if it is timeout */
5378         if (j >= I40E_CHK_Q_ENA_COUNT) {
5379                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5380                             (on ? "enable" : "disable"), q_idx);
5381                 return I40E_ERR_TIMEOUT;
5382         }
5383
5384         return I40E_SUCCESS;
5385 }
5386 /* Switch on or off the rx queues */
5387 static int
5388 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5389 {
5390         struct rte_eth_dev_data *dev_data = pf->dev_data;
5391         struct i40e_rx_queue *rxq;
5392         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5393         uint16_t i;
5394         int ret;
5395
5396         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5397                 rxq = dev_data->rx_queues[i];
5398                 /* Don't operate the queue if not configured or
5399                  * if starting only per queue */
5400                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5401                         continue;
5402                 if (on)
5403                         ret = i40e_dev_rx_queue_start(dev, i);
5404                 else
5405                         ret = i40e_dev_rx_queue_stop(dev, i);
5406                 if (ret != I40E_SUCCESS)
5407                         return ret;
5408         }
5409
5410         return I40E_SUCCESS;
5411 }
5412
5413 /* Switch on or off all the rx/tx queues */
5414 int
5415 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5416 {
5417         int ret;
5418
5419         if (on) {
5420                 /* enable rx queues before enabling tx queues */
5421                 ret = i40e_dev_switch_rx_queues(pf, on);
5422                 if (ret) {
5423                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5424                         return ret;
5425                 }
5426                 ret = i40e_dev_switch_tx_queues(pf, on);
5427         } else {
5428                 /* Stop tx queues before stopping rx queues */
5429                 ret = i40e_dev_switch_tx_queues(pf, on);
5430                 if (ret) {
5431                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5432                         return ret;
5433                 }
5434                 ret = i40e_dev_switch_rx_queues(pf, on);
5435         }
5436
5437         return ret;
5438 }
5439
5440 /* Initialize VSI for TX */
5441 static int
5442 i40e_dev_tx_init(struct i40e_pf *pf)
5443 {
5444         struct rte_eth_dev_data *data = pf->dev_data;
5445         uint16_t i;
5446         uint32_t ret = I40E_SUCCESS;
5447         struct i40e_tx_queue *txq;
5448
5449         for (i = 0; i < data->nb_tx_queues; i++) {
5450                 txq = data->tx_queues[i];
5451                 if (!txq || !txq->q_set)
5452                         continue;
5453                 ret = i40e_tx_queue_init(txq);
5454                 if (ret != I40E_SUCCESS)
5455                         break;
5456         }
5457         if (ret == I40E_SUCCESS)
5458                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5459                                      ->eth_dev);
5460
5461         return ret;
5462 }
5463
5464 /* Initialize VSI for RX */
5465 static int
5466 i40e_dev_rx_init(struct i40e_pf *pf)
5467 {
5468         struct rte_eth_dev_data *data = pf->dev_data;
5469         int ret = I40E_SUCCESS;
5470         uint16_t i;
5471         struct i40e_rx_queue *rxq;
5472
5473         i40e_pf_config_mq_rx(pf);
5474         for (i = 0; i < data->nb_rx_queues; i++) {
5475                 rxq = data->rx_queues[i];
5476                 if (!rxq || !rxq->q_set)
5477                         continue;
5478
5479                 ret = i40e_rx_queue_init(rxq);
5480                 if (ret != I40E_SUCCESS) {
5481                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
5482                                     "initialization");
5483                         break;
5484                 }
5485         }
5486         if (ret == I40E_SUCCESS)
5487                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5488                                      ->eth_dev);
5489
5490         return ret;
5491 }
5492
5493 static int
5494 i40e_dev_rxtx_init(struct i40e_pf *pf)
5495 {
5496         int err;
5497
5498         err = i40e_dev_tx_init(pf);
5499         if (err) {
5500                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5501                 return err;
5502         }
5503         err = i40e_dev_rx_init(pf);
5504         if (err) {
5505                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5506                 return err;
5507         }
5508
5509         return err;
5510 }
5511
5512 static int
5513 i40e_vmdq_setup(struct rte_eth_dev *dev)
5514 {
5515         struct rte_eth_conf *conf = &dev->data->dev_conf;
5516         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5517         int i, err, conf_vsis, j, loop;
5518         struct i40e_vsi *vsi;
5519         struct i40e_vmdq_info *vmdq_info;
5520         struct rte_eth_vmdq_rx_conf *vmdq_conf;
5521         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5522
5523         /*
5524          * Disable interrupt to avoid message from VF. Furthermore, it will
5525          * avoid race condition in VSI creation/destroy.
5526          */
5527         i40e_pf_disable_irq0(hw);
5528
5529         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5530                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5531                 return -ENOTSUP;
5532         }
5533
5534         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5535         if (conf_vsis > pf->max_nb_vmdq_vsi) {
5536                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5537                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5538                         pf->max_nb_vmdq_vsi);
5539                 return -ENOTSUP;
5540         }
5541
5542         if (pf->vmdq != NULL) {
5543                 PMD_INIT_LOG(INFO, "VMDQ already configured");
5544                 return 0;
5545         }
5546
5547         pf->vmdq = rte_zmalloc("vmdq_info_struct",
5548                                 sizeof(*vmdq_info) * conf_vsis, 0);
5549
5550         if (pf->vmdq == NULL) {
5551                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5552                 return -ENOMEM;
5553         }
5554
5555         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5556
5557         /* Create VMDQ VSI */
5558         for (i = 0; i < conf_vsis; i++) {
5559                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5560                                 vmdq_conf->enable_loop_back);
5561                 if (vsi == NULL) {
5562                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5563                         err = -1;
5564                         goto err_vsi_setup;
5565                 }
5566                 vmdq_info = &pf->vmdq[i];
5567                 vmdq_info->pf = pf;
5568                 vmdq_info->vsi = vsi;
5569         }
5570         pf->nb_cfg_vmdq_vsi = conf_vsis;
5571
5572         /* Configure Vlan */
5573         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5574         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5575                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5576                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5577                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5578                                         vmdq_conf->pool_map[i].vlan_id, j);
5579
5580                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5581                                                 vmdq_conf->pool_map[i].vlan_id);
5582                                 if (err) {
5583                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
5584                                         err = -1;
5585                                         goto err_vsi_setup;
5586                                 }
5587                         }
5588                 }
5589         }
5590
5591         i40e_pf_enable_irq0(hw);
5592
5593         return 0;
5594
5595 err_vsi_setup:
5596         for (i = 0; i < conf_vsis; i++)
5597                 if (pf->vmdq[i].vsi == NULL)
5598                         break;
5599                 else
5600                         i40e_vsi_release(pf->vmdq[i].vsi);
5601
5602         rte_free(pf->vmdq);
5603         pf->vmdq = NULL;
5604         i40e_pf_enable_irq0(hw);
5605         return err;
5606 }
5607
5608 static void
5609 i40e_stat_update_32(struct i40e_hw *hw,
5610                    uint32_t reg,
5611                    bool offset_loaded,
5612                    uint64_t *offset,
5613                    uint64_t *stat)
5614 {
5615         uint64_t new_data;
5616
5617         new_data = (uint64_t)I40E_READ_REG(hw, reg);
5618         if (!offset_loaded)
5619                 *offset = new_data;
5620
5621         if (new_data >= *offset)
5622                 *stat = (uint64_t)(new_data - *offset);
5623         else
5624                 *stat = (uint64_t)((new_data +
5625                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5626 }
5627
5628 static void
5629 i40e_stat_update_48(struct i40e_hw *hw,
5630                    uint32_t hireg,
5631                    uint32_t loreg,
5632                    bool offset_loaded,
5633                    uint64_t *offset,
5634                    uint64_t *stat)
5635 {
5636         uint64_t new_data;
5637
5638         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5639         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5640                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5641
5642         if (!offset_loaded)
5643                 *offset = new_data;
5644
5645         if (new_data >= *offset)
5646                 *stat = new_data - *offset;
5647         else
5648                 *stat = (uint64_t)((new_data +
5649                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5650
5651         *stat &= I40E_48_BIT_MASK;
5652 }
5653
5654 /* Disable IRQ0 */
5655 void
5656 i40e_pf_disable_irq0(struct i40e_hw *hw)
5657 {
5658         /* Disable all interrupt types */
5659         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5660         I40E_WRITE_FLUSH(hw);
5661 }
5662
5663 /* Enable IRQ0 */
5664 void
5665 i40e_pf_enable_irq0(struct i40e_hw *hw)
5666 {
5667         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5668                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5669                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5670                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5671         I40E_WRITE_FLUSH(hw);
5672 }
5673
5674 static void
5675 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5676 {
5677         /* read pending request and disable first */
5678         i40e_pf_disable_irq0(hw);
5679         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5680         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5681                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5682
5683         if (no_queue)
5684                 /* Link no queues with irq0 */
5685                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5686                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5687 }
5688
5689 static void
5690 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5691 {
5692         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5693         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5694         int i;
5695         uint16_t abs_vf_id;
5696         uint32_t index, offset, val;
5697
5698         if (!pf->vfs)
5699                 return;
5700         /**
5701          * Try to find which VF trigger a reset, use absolute VF id to access
5702          * since the reg is global register.
5703          */
5704         for (i = 0; i < pf->vf_num; i++) {
5705                 abs_vf_id = hw->func_caps.vf_base_id + i;
5706                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5707                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5708                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5709                 /* VFR event occured */
5710                 if (val & (0x1 << offset)) {
5711                         int ret;
5712
5713                         /* Clear the event first */
5714                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5715                                                         (0x1 << offset));
5716                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
5717                         /**
5718                          * Only notify a VF reset event occured,
5719                          * don't trigger another SW reset
5720                          */
5721                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5722                         if (ret != I40E_SUCCESS)
5723                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5724                 }
5725         }
5726 }
5727
5728 static void
5729 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5730 {
5731         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5732         struct i40e_virtchnl_pf_event event;
5733         int i;
5734
5735         event.event = I40E_VIRTCHNL_EVENT_LINK_CHANGE;
5736         event.event_data.link_event.link_status =
5737                 dev->data->dev_link.link_status;
5738         event.event_data.link_event.link_speed =
5739                 (enum i40e_aq_link_speed)dev->data->dev_link.link_speed;
5740
5741         for (i = 0; i < pf->vf_num; i++)
5742                 i40e_pf_host_send_msg_to_vf(&pf->vfs[i], I40E_VIRTCHNL_OP_EVENT,
5743                                 I40E_SUCCESS, (uint8_t *)&event, sizeof(event));
5744 }
5745
5746 static void
5747 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5748 {
5749         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5750         struct i40e_arq_event_info info;
5751         uint16_t pending, opcode;
5752         int ret;
5753
5754         info.buf_len = I40E_AQ_BUF_SZ;
5755         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5756         if (!info.msg_buf) {
5757                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5758                 return;
5759         }
5760
5761         pending = 1;
5762         while (pending) {
5763                 ret = i40e_clean_arq_element(hw, &info, &pending);
5764
5765                 if (ret != I40E_SUCCESS) {
5766                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
5767                                     "aq_err: %u", hw->aq.asq_last_status);
5768                         break;
5769                 }
5770                 opcode = rte_le_to_cpu_16(info.desc.opcode);
5771
5772                 switch (opcode) {
5773                 case i40e_aqc_opc_send_msg_to_pf:
5774                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5775                         i40e_pf_host_handle_vf_msg(dev,
5776                                         rte_le_to_cpu_16(info.desc.retval),
5777                                         rte_le_to_cpu_32(info.desc.cookie_high),
5778                                         rte_le_to_cpu_32(info.desc.cookie_low),
5779                                         info.msg_buf,
5780                                         info.msg_len);
5781                         break;
5782                 case i40e_aqc_opc_get_link_status:
5783                         ret = i40e_dev_link_update(dev, 0);
5784                         if (!ret) {
5785                                 i40e_notify_all_vfs_link_status(dev);
5786                                 _rte_eth_dev_callback_process(dev,
5787                                         RTE_ETH_EVENT_INTR_LSC, NULL);
5788                         }
5789                         break;
5790                 default:
5791                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
5792                                     opcode);
5793                         break;
5794                 }
5795         }
5796         rte_free(info.msg_buf);
5797 }
5798
5799 /**
5800  * Interrupt handler triggered by NIC  for handling
5801  * specific interrupt.
5802  *
5803  * @param handle
5804  *  Pointer to interrupt handle.
5805  * @param param
5806  *  The address of parameter (struct rte_eth_dev *) regsitered before.
5807  *
5808  * @return
5809  *  void
5810  */
5811 static void
5812 i40e_dev_interrupt_handler(struct rte_intr_handle *intr_handle,
5813                            void *param)
5814 {
5815         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
5816         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5817         uint32_t icr0;
5818
5819         /* Disable interrupt */
5820         i40e_pf_disable_irq0(hw);
5821
5822         /* read out interrupt causes */
5823         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
5824
5825         /* No interrupt event indicated */
5826         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
5827                 PMD_DRV_LOG(INFO, "No interrupt event");
5828                 goto done;
5829         }
5830 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
5831         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
5832                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
5833         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
5834                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
5835         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
5836                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
5837         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
5838                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
5839         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
5840                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
5841         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
5842                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
5843         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
5844                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
5845 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
5846
5847         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
5848                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
5849                 i40e_dev_handle_vfr_event(dev);
5850         }
5851         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
5852                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
5853                 i40e_dev_handle_aq_msg(dev);
5854         }
5855
5856 done:
5857         /* Enable interrupt */
5858         i40e_pf_enable_irq0(hw);
5859         rte_intr_enable(intr_handle);
5860 }
5861
5862 static int
5863 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
5864                          struct i40e_macvlan_filter *filter,
5865                          int total)
5866 {
5867         int ele_num, ele_buff_size;
5868         int num, actual_num, i;
5869         uint16_t flags;
5870         int ret = I40E_SUCCESS;
5871         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5872         struct i40e_aqc_add_macvlan_element_data *req_list;
5873
5874         if (filter == NULL  || total == 0)
5875                 return I40E_ERR_PARAM;
5876         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5877         ele_buff_size = hw->aq.asq_buf_size;
5878
5879         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
5880         if (req_list == NULL) {
5881                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5882                 return I40E_ERR_NO_MEMORY;
5883         }
5884
5885         num = 0;
5886         do {
5887                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5888                 memset(req_list, 0, ele_buff_size);
5889
5890                 for (i = 0; i < actual_num; i++) {
5891                         (void)rte_memcpy(req_list[i].mac_addr,
5892                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5893                         req_list[i].vlan_tag =
5894                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5895
5896                         switch (filter[num + i].filter_type) {
5897                         case RTE_MAC_PERFECT_MATCH:
5898                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
5899                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5900                                 break;
5901                         case RTE_MACVLAN_PERFECT_MATCH:
5902                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
5903                                 break;
5904                         case RTE_MAC_HASH_MATCH:
5905                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
5906                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
5907                                 break;
5908                         case RTE_MACVLAN_HASH_MATCH:
5909                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
5910                                 break;
5911                         default:
5912                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
5913                                 ret = I40E_ERR_PARAM;
5914                                 goto DONE;
5915                         }
5916
5917                         req_list[i].queue_number = 0;
5918
5919                         req_list[i].flags = rte_cpu_to_le_16(flags);
5920                 }
5921
5922                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
5923                                                 actual_num, NULL);
5924                 if (ret != I40E_SUCCESS) {
5925                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
5926                         goto DONE;
5927                 }
5928                 num += actual_num;
5929         } while (num < total);
5930
5931 DONE:
5932         rte_free(req_list);
5933         return ret;
5934 }
5935
5936 static int
5937 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
5938                             struct i40e_macvlan_filter *filter,
5939                             int total)
5940 {
5941         int ele_num, ele_buff_size;
5942         int num, actual_num, i;
5943         uint16_t flags;
5944         int ret = I40E_SUCCESS;
5945         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5946         struct i40e_aqc_remove_macvlan_element_data *req_list;
5947
5948         if (filter == NULL  || total == 0)
5949                 return I40E_ERR_PARAM;
5950
5951         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
5952         ele_buff_size = hw->aq.asq_buf_size;
5953
5954         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
5955         if (req_list == NULL) {
5956                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
5957                 return I40E_ERR_NO_MEMORY;
5958         }
5959
5960         num = 0;
5961         do {
5962                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
5963                 memset(req_list, 0, ele_buff_size);
5964
5965                 for (i = 0; i < actual_num; i++) {
5966                         (void)rte_memcpy(req_list[i].mac_addr,
5967                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
5968                         req_list[i].vlan_tag =
5969                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
5970
5971                         switch (filter[num + i].filter_type) {
5972                         case RTE_MAC_PERFECT_MATCH:
5973                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5974                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5975                                 break;
5976                         case RTE_MACVLAN_PERFECT_MATCH:
5977                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
5978                                 break;
5979                         case RTE_MAC_HASH_MATCH:
5980                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
5981                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5982                                 break;
5983                         case RTE_MACVLAN_HASH_MATCH:
5984                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
5985                                 break;
5986                         default:
5987                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
5988                                 ret = I40E_ERR_PARAM;
5989                                 goto DONE;
5990                         }
5991                         req_list[i].flags = rte_cpu_to_le_16(flags);
5992                 }
5993
5994                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
5995                                                 actual_num, NULL);
5996                 if (ret != I40E_SUCCESS) {
5997                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
5998                         goto DONE;
5999                 }
6000                 num += actual_num;
6001         } while (num < total);
6002
6003 DONE:
6004         rte_free(req_list);
6005         return ret;
6006 }
6007
6008 /* Find out specific MAC filter */
6009 static struct i40e_mac_filter *
6010 i40e_find_mac_filter(struct i40e_vsi *vsi,
6011                          struct ether_addr *macaddr)
6012 {
6013         struct i40e_mac_filter *f;
6014
6015         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6016                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6017                         return f;
6018         }
6019
6020         return NULL;
6021 }
6022
6023 static bool
6024 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6025                          uint16_t vlan_id)
6026 {
6027         uint32_t vid_idx, vid_bit;
6028
6029         if (vlan_id > ETH_VLAN_ID_MAX)
6030                 return 0;
6031
6032         vid_idx = I40E_VFTA_IDX(vlan_id);
6033         vid_bit = I40E_VFTA_BIT(vlan_id);
6034
6035         if (vsi->vfta[vid_idx] & vid_bit)
6036                 return 1;
6037         else
6038                 return 0;
6039 }
6040
6041 static void
6042 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6043                          uint16_t vlan_id, bool on)
6044 {
6045         uint32_t vid_idx, vid_bit;
6046
6047         if (vlan_id > ETH_VLAN_ID_MAX)
6048                 return;
6049
6050         vid_idx = I40E_VFTA_IDX(vlan_id);
6051         vid_bit = I40E_VFTA_BIT(vlan_id);
6052
6053         if (on)
6054                 vsi->vfta[vid_idx] |= vid_bit;
6055         else
6056                 vsi->vfta[vid_idx] &= ~vid_bit;
6057 }
6058
6059 /**
6060  * Find all vlan options for specific mac addr,
6061  * return with actual vlan found.
6062  */
6063 static inline int
6064 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6065                            struct i40e_macvlan_filter *mv_f,
6066                            int num, struct ether_addr *addr)
6067 {
6068         int i;
6069         uint32_t j, k;
6070
6071         /**
6072          * Not to use i40e_find_vlan_filter to decrease the loop time,
6073          * although the code looks complex.
6074           */
6075         if (num < vsi->vlan_num)
6076                 return I40E_ERR_PARAM;
6077
6078         i = 0;
6079         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6080                 if (vsi->vfta[j]) {
6081                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6082                                 if (vsi->vfta[j] & (1 << k)) {
6083                                         if (i > num - 1) {
6084                                                 PMD_DRV_LOG(ERR, "vlan number "
6085                                                             "not match");
6086                                                 return I40E_ERR_PARAM;
6087                                         }
6088                                         (void)rte_memcpy(&mv_f[i].macaddr,
6089                                                         addr, ETH_ADDR_LEN);
6090                                         mv_f[i].vlan_id =
6091                                                 j * I40E_UINT32_BIT_SIZE + k;
6092                                         i++;
6093                                 }
6094                         }
6095                 }
6096         }
6097         return I40E_SUCCESS;
6098 }
6099
6100 static inline int
6101 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6102                            struct i40e_macvlan_filter *mv_f,
6103                            int num,
6104                            uint16_t vlan)
6105 {
6106         int i = 0;
6107         struct i40e_mac_filter *f;
6108
6109         if (num < vsi->mac_num)
6110                 return I40E_ERR_PARAM;
6111
6112         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6113                 if (i > num - 1) {
6114                         PMD_DRV_LOG(ERR, "buffer number not match");
6115                         return I40E_ERR_PARAM;
6116                 }
6117                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6118                                 ETH_ADDR_LEN);
6119                 mv_f[i].vlan_id = vlan;
6120                 mv_f[i].filter_type = f->mac_info.filter_type;
6121                 i++;
6122         }
6123
6124         return I40E_SUCCESS;
6125 }
6126
6127 static int
6128 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6129 {
6130         int i, num;
6131         struct i40e_mac_filter *f;
6132         struct i40e_macvlan_filter *mv_f;
6133         int ret = I40E_SUCCESS;
6134
6135         if (vsi == NULL || vsi->mac_num == 0)
6136                 return I40E_ERR_PARAM;
6137
6138         /* Case that no vlan is set */
6139         if (vsi->vlan_num == 0)
6140                 num = vsi->mac_num;
6141         else
6142                 num = vsi->mac_num * vsi->vlan_num;
6143
6144         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6145         if (mv_f == NULL) {
6146                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6147                 return I40E_ERR_NO_MEMORY;
6148         }
6149
6150         i = 0;
6151         if (vsi->vlan_num == 0) {
6152                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6153                         (void)rte_memcpy(&mv_f[i].macaddr,
6154                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6155                         mv_f[i].vlan_id = 0;
6156                         i++;
6157                 }
6158         } else {
6159                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6160                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6161                                         vsi->vlan_num, &f->mac_info.mac_addr);
6162                         if (ret != I40E_SUCCESS)
6163                                 goto DONE;
6164                         i += vsi->vlan_num;
6165                 }
6166         }
6167
6168         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6169 DONE:
6170         rte_free(mv_f);
6171
6172         return ret;
6173 }
6174
6175 int
6176 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6177 {
6178         struct i40e_macvlan_filter *mv_f;
6179         int mac_num;
6180         int ret = I40E_SUCCESS;
6181
6182         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6183                 return I40E_ERR_PARAM;
6184
6185         /* If it's already set, just return */
6186         if (i40e_find_vlan_filter(vsi,vlan))
6187                 return I40E_SUCCESS;
6188
6189         mac_num = vsi->mac_num;
6190
6191         if (mac_num == 0) {
6192                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6193                 return I40E_ERR_PARAM;
6194         }
6195
6196         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6197
6198         if (mv_f == NULL) {
6199                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6200                 return I40E_ERR_NO_MEMORY;
6201         }
6202
6203         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6204
6205         if (ret != I40E_SUCCESS)
6206                 goto DONE;
6207
6208         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6209
6210         if (ret != I40E_SUCCESS)
6211                 goto DONE;
6212
6213         i40e_set_vlan_filter(vsi, vlan, 1);
6214
6215         vsi->vlan_num++;
6216         ret = I40E_SUCCESS;
6217 DONE:
6218         rte_free(mv_f);
6219         return ret;
6220 }
6221
6222 int
6223 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6224 {
6225         struct i40e_macvlan_filter *mv_f;
6226         int mac_num;
6227         int ret = I40E_SUCCESS;
6228
6229         /**
6230          * Vlan 0 is the generic filter for untagged packets
6231          * and can't be removed.
6232          */
6233         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6234                 return I40E_ERR_PARAM;
6235
6236         /* If can't find it, just return */
6237         if (!i40e_find_vlan_filter(vsi, vlan))
6238                 return I40E_ERR_PARAM;
6239
6240         mac_num = vsi->mac_num;
6241
6242         if (mac_num == 0) {
6243                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6244                 return I40E_ERR_PARAM;
6245         }
6246
6247         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6248
6249         if (mv_f == NULL) {
6250                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6251                 return I40E_ERR_NO_MEMORY;
6252         }
6253
6254         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6255
6256         if (ret != I40E_SUCCESS)
6257                 goto DONE;
6258
6259         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6260
6261         if (ret != I40E_SUCCESS)
6262                 goto DONE;
6263
6264         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6265         if (vsi->vlan_num == 1) {
6266                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6267                 if (ret != I40E_SUCCESS)
6268                         goto DONE;
6269
6270                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6271                 if (ret != I40E_SUCCESS)
6272                         goto DONE;
6273         }
6274
6275         i40e_set_vlan_filter(vsi, vlan, 0);
6276
6277         vsi->vlan_num--;
6278         ret = I40E_SUCCESS;
6279 DONE:
6280         rte_free(mv_f);
6281         return ret;
6282 }
6283
6284 int
6285 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6286 {
6287         struct i40e_mac_filter *f;
6288         struct i40e_macvlan_filter *mv_f;
6289         int i, vlan_num = 0;
6290         int ret = I40E_SUCCESS;
6291
6292         /* If it's add and we've config it, return */
6293         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6294         if (f != NULL)
6295                 return I40E_SUCCESS;
6296         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6297                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6298
6299                 /**
6300                  * If vlan_num is 0, that's the first time to add mac,
6301                  * set mask for vlan_id 0.
6302                  */
6303                 if (vsi->vlan_num == 0) {
6304                         i40e_set_vlan_filter(vsi, 0, 1);
6305                         vsi->vlan_num = 1;
6306                 }
6307                 vlan_num = vsi->vlan_num;
6308         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6309                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6310                 vlan_num = 1;
6311
6312         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6313         if (mv_f == NULL) {
6314                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6315                 return I40E_ERR_NO_MEMORY;
6316         }
6317
6318         for (i = 0; i < vlan_num; i++) {
6319                 mv_f[i].filter_type = mac_filter->filter_type;
6320                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6321                                 ETH_ADDR_LEN);
6322         }
6323
6324         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6325                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6326                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6327                                         &mac_filter->mac_addr);
6328                 if (ret != I40E_SUCCESS)
6329                         goto DONE;
6330         }
6331
6332         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6333         if (ret != I40E_SUCCESS)
6334                 goto DONE;
6335
6336         /* Add the mac addr into mac list */
6337         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6338         if (f == NULL) {
6339                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6340                 ret = I40E_ERR_NO_MEMORY;
6341                 goto DONE;
6342         }
6343         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6344                         ETH_ADDR_LEN);
6345         f->mac_info.filter_type = mac_filter->filter_type;
6346         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6347         vsi->mac_num++;
6348
6349         ret = I40E_SUCCESS;
6350 DONE:
6351         rte_free(mv_f);
6352
6353         return ret;
6354 }
6355
6356 int
6357 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6358 {
6359         struct i40e_mac_filter *f;
6360         struct i40e_macvlan_filter *mv_f;
6361         int i, vlan_num;
6362         enum rte_mac_filter_type filter_type;
6363         int ret = I40E_SUCCESS;
6364
6365         /* Can't find it, return an error */
6366         f = i40e_find_mac_filter(vsi, addr);
6367         if (f == NULL)
6368                 return I40E_ERR_PARAM;
6369
6370         vlan_num = vsi->vlan_num;
6371         filter_type = f->mac_info.filter_type;
6372         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6373                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6374                 if (vlan_num == 0) {
6375                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
6376                         return I40E_ERR_PARAM;
6377                 }
6378         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6379                         filter_type == RTE_MAC_HASH_MATCH)
6380                 vlan_num = 1;
6381
6382         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6383         if (mv_f == NULL) {
6384                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6385                 return I40E_ERR_NO_MEMORY;
6386         }
6387
6388         for (i = 0; i < vlan_num; i++) {
6389                 mv_f[i].filter_type = filter_type;
6390                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6391                                 ETH_ADDR_LEN);
6392         }
6393         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6394                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6395                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6396                 if (ret != I40E_SUCCESS)
6397                         goto DONE;
6398         }
6399
6400         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6401         if (ret != I40E_SUCCESS)
6402                 goto DONE;
6403
6404         /* Remove the mac addr into mac list */
6405         TAILQ_REMOVE(&vsi->mac_list, f, next);
6406         rte_free(f);
6407         vsi->mac_num--;
6408
6409         ret = I40E_SUCCESS;
6410 DONE:
6411         rte_free(mv_f);
6412         return ret;
6413 }
6414
6415 /* Configure hash enable flags for RSS */
6416 uint64_t
6417 i40e_config_hena(uint64_t flags, enum i40e_mac_type type)
6418 {
6419         uint64_t hena = 0;
6420
6421         if (!flags)
6422                 return hena;
6423
6424         if (flags & ETH_RSS_FRAG_IPV4)
6425                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
6426         if (flags & ETH_RSS_NONFRAG_IPV4_TCP) {
6427                 if (type == I40E_MAC_X722) {
6428                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |
6429                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
6430                 } else
6431                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
6432         }
6433         if (flags & ETH_RSS_NONFRAG_IPV4_UDP) {
6434                 if (type == I40E_MAC_X722) {
6435                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |
6436                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) |
6437                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
6438                 } else
6439                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
6440         }
6441         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
6442                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
6443         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
6444                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
6445         if (flags & ETH_RSS_FRAG_IPV6)
6446                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
6447         if (flags & ETH_RSS_NONFRAG_IPV6_TCP) {
6448                 if (type == I40E_MAC_X722) {
6449                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |
6450                          (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
6451                 } else
6452                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
6453         }
6454         if (flags & ETH_RSS_NONFRAG_IPV6_UDP) {
6455                 if (type == I40E_MAC_X722) {
6456                         hena |= (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |
6457                          (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) |
6458                          (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
6459                 } else
6460                         hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
6461         }
6462         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
6463                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
6464         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
6465                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
6466         if (flags & ETH_RSS_L2_PAYLOAD)
6467                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
6468
6469         return hena;
6470 }
6471
6472 /* Parse the hash enable flags */
6473 uint64_t
6474 i40e_parse_hena(uint64_t flags)
6475 {
6476         uint64_t rss_hf = 0;
6477
6478         if (!flags)
6479                 return rss_hf;
6480         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
6481                 rss_hf |= ETH_RSS_FRAG_IPV4;
6482         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
6483                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6484         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK))
6485                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
6486         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
6487                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6488         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP))
6489                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6490         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP))
6491                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
6492         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
6493                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
6494         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
6495                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
6496         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
6497                 rss_hf |= ETH_RSS_FRAG_IPV6;
6498         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
6499                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6500         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
6501                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
6502         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
6503                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6504         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP))
6505                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6506         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
6507                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
6508         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
6509                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
6510         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
6511                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
6512         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
6513                 rss_hf |= ETH_RSS_L2_PAYLOAD;
6514
6515         return rss_hf;
6516 }
6517
6518 /* Disable RSS */
6519 static void
6520 i40e_pf_disable_rss(struct i40e_pf *pf)
6521 {
6522         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6523         uint64_t hena;
6524
6525         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6526         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6527         if (hw->mac.type == I40E_MAC_X722)
6528                 hena &= ~I40E_RSS_HENA_ALL_X722;
6529         else
6530                 hena &= ~I40E_RSS_HENA_ALL;
6531         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6532         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6533         I40E_WRITE_FLUSH(hw);
6534 }
6535
6536 static int
6537 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6538 {
6539         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6540         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6541         int ret = 0;
6542
6543         if (!key || key_len == 0) {
6544                 PMD_DRV_LOG(DEBUG, "No key to be configured");
6545                 return 0;
6546         } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6547                 sizeof(uint32_t)) {
6548                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6549                 return -EINVAL;
6550         }
6551
6552         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6553                 struct i40e_aqc_get_set_rss_key_data *key_dw =
6554                         (struct i40e_aqc_get_set_rss_key_data *)key;
6555
6556                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6557                 if (ret)
6558                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
6559                                      "via AQ");
6560         } else {
6561                 uint32_t *hash_key = (uint32_t *)key;
6562                 uint16_t i;
6563
6564                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6565                         i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6566                 I40E_WRITE_FLUSH(hw);
6567         }
6568
6569         return ret;
6570 }
6571
6572 static int
6573 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6574 {
6575         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6576         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6577         int ret;
6578
6579         if (!key || !key_len)
6580                 return -EINVAL;
6581
6582         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6583                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6584                         (struct i40e_aqc_get_set_rss_key_data *)key);
6585                 if (ret) {
6586                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6587                         return ret;
6588                 }
6589         } else {
6590                 uint32_t *key_dw = (uint32_t *)key;
6591                 uint16_t i;
6592
6593                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6594                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6595         }
6596         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6597
6598         return 0;
6599 }
6600
6601 static int
6602 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6603 {
6604         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6605         uint64_t rss_hf;
6606         uint64_t hena;
6607         int ret;
6608
6609         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6610                                rss_conf->rss_key_len);
6611         if (ret)
6612                 return ret;
6613
6614         rss_hf = rss_conf->rss_hf;
6615         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6616         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6617         if (hw->mac.type == I40E_MAC_X722)
6618                 hena &= ~I40E_RSS_HENA_ALL_X722;
6619         else
6620                 hena &= ~I40E_RSS_HENA_ALL;
6621         hena |= i40e_config_hena(rss_hf, hw->mac.type);
6622         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6623         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6624         I40E_WRITE_FLUSH(hw);
6625
6626         return 0;
6627 }
6628
6629 static int
6630 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6631                          struct rte_eth_rss_conf *rss_conf)
6632 {
6633         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6634         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6635         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
6636         uint64_t hena;
6637
6638         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6639         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6640         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
6641                  ? I40E_RSS_HENA_ALL_X722
6642                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
6643                 if (rss_hf != 0) /* Enable RSS */
6644                         return -EINVAL;
6645                 return 0; /* Nothing to do */
6646         }
6647         /* RSS enabled */
6648         if (rss_hf == 0) /* Disable RSS */
6649                 return -EINVAL;
6650
6651         return i40e_hw_rss_hash_set(pf, rss_conf);
6652 }
6653
6654 static int
6655 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6656                            struct rte_eth_rss_conf *rss_conf)
6657 {
6658         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6659         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6660         uint64_t hena;
6661
6662         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6663                          &rss_conf->rss_key_len);
6664
6665         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6666         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6667         rss_conf->rss_hf = i40e_parse_hena(hena);
6668
6669         return 0;
6670 }
6671
6672 static int
6673 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6674 {
6675         switch (filter_type) {
6676         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6677                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6678                 break;
6679         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6680                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6681                 break;
6682         case RTE_TUNNEL_FILTER_IMAC_TENID:
6683                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6684                 break;
6685         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6686                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6687                 break;
6688         case ETH_TUNNEL_FILTER_IMAC:
6689                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6690                 break;
6691         case ETH_TUNNEL_FILTER_OIP:
6692                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6693                 break;
6694         case ETH_TUNNEL_FILTER_IIP:
6695                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6696                 break;
6697         default:
6698                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6699                 return -EINVAL;
6700         }
6701
6702         return 0;
6703 }
6704
6705 /* Convert tunnel filter structure */
6706 static int
6707 i40e_tunnel_filter_convert(struct i40e_aqc_add_remove_cloud_filters_element_data
6708                            *cld_filter,
6709                            struct i40e_tunnel_filter *tunnel_filter)
6710 {
6711         ether_addr_copy((struct ether_addr *)&cld_filter->outer_mac,
6712                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
6713         ether_addr_copy((struct ether_addr *)&cld_filter->inner_mac,
6714                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
6715         tunnel_filter->input.inner_vlan = cld_filter->inner_vlan;
6716         tunnel_filter->input.flags = cld_filter->flags;
6717         tunnel_filter->input.tenant_id = cld_filter->tenant_id;
6718         tunnel_filter->queue = cld_filter->queue_number;
6719
6720         return 0;
6721 }
6722
6723 /* Check if there exists the tunnel filter */
6724 struct i40e_tunnel_filter *
6725 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6726                              const struct i40e_tunnel_filter_input *input)
6727 {
6728         int ret;
6729
6730         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6731         if (ret < 0)
6732                 return NULL;
6733
6734         return tunnel_rule->hash_map[ret];
6735 }
6736
6737 /* Add a tunnel filter into the SW list */
6738 static int
6739 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6740                              struct i40e_tunnel_filter *tunnel_filter)
6741 {
6742         struct i40e_tunnel_rule *rule = &pf->tunnel;
6743         int ret;
6744
6745         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6746         if (ret < 0) {
6747                 PMD_DRV_LOG(ERR,
6748                             "Failed to insert tunnel filter to hash table %d!",
6749                             ret);
6750                 return ret;
6751         }
6752         rule->hash_map[ret] = tunnel_filter;
6753
6754         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6755
6756         return 0;
6757 }
6758
6759 /* Delete a tunnel filter from the SW list */
6760 int
6761 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6762                           struct i40e_tunnel_filter_input *input)
6763 {
6764         struct i40e_tunnel_rule *rule = &pf->tunnel;
6765         struct i40e_tunnel_filter *tunnel_filter;
6766         int ret;
6767
6768         ret = rte_hash_del_key(rule->hash_table, input);
6769         if (ret < 0) {
6770                 PMD_DRV_LOG(ERR,
6771                             "Failed to delete tunnel filter to hash table %d!",
6772                             ret);
6773                 return ret;
6774         }
6775         tunnel_filter = rule->hash_map[ret];
6776         rule->hash_map[ret] = NULL;
6777
6778         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6779         rte_free(tunnel_filter);
6780
6781         return 0;
6782 }
6783
6784 static int
6785 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6786                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
6787                         uint8_t add)
6788 {
6789         uint16_t ip_type;
6790         uint32_t ipv4_addr;
6791         uint8_t i, tun_type = 0;
6792         /* internal varialbe to convert ipv6 byte order */
6793         uint32_t convert_ipv6[4];
6794         int val, ret = 0;
6795         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6796         struct i40e_vsi *vsi = pf->main_vsi;
6797         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
6798         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
6799         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6800         struct i40e_tunnel_filter *tunnel, *node;
6801         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6802
6803         cld_filter = rte_zmalloc("tunnel_filter",
6804                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
6805                 0);
6806
6807         if (NULL == cld_filter) {
6808                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6809                 return -EINVAL;
6810         }
6811         pfilter = cld_filter;
6812
6813         ether_addr_copy(&tunnel_filter->outer_mac, (struct ether_addr*)&pfilter->outer_mac);
6814         ether_addr_copy(&tunnel_filter->inner_mac, (struct ether_addr*)&pfilter->inner_mac);
6815
6816         pfilter->inner_vlan = rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6817         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6818                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6819                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6820                 rte_memcpy(&pfilter->ipaddr.v4.data,
6821                                 &rte_cpu_to_le_32(ipv4_addr),
6822                                 sizeof(pfilter->ipaddr.v4.data));
6823         } else {
6824                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6825                 for (i = 0; i < 4; i++) {
6826                         convert_ipv6[i] =
6827                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6828                 }
6829                 rte_memcpy(&pfilter->ipaddr.v6.data, &convert_ipv6,
6830                                 sizeof(pfilter->ipaddr.v6.data));
6831         }
6832
6833         /* check tunneled type */
6834         switch (tunnel_filter->tunnel_type) {
6835         case RTE_TUNNEL_TYPE_VXLAN:
6836                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6837                 break;
6838         case RTE_TUNNEL_TYPE_NVGRE:
6839                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6840                 break;
6841         case RTE_TUNNEL_TYPE_IP_IN_GRE:
6842                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6843                 break;
6844         default:
6845                 /* Other tunnel types is not supported. */
6846                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6847                 rte_free(cld_filter);
6848                 return -EINVAL;
6849         }
6850
6851         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
6852                                                 &pfilter->flags);
6853         if (val < 0) {
6854                 rte_free(cld_filter);
6855                 return -EINVAL;
6856         }
6857
6858         pfilter->flags |= rte_cpu_to_le_16(
6859                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
6860                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
6861         pfilter->tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
6862         pfilter->queue_number = rte_cpu_to_le_16(tunnel_filter->queue_id);
6863
6864         /* Check if there is the filter in SW list */
6865         memset(&check_filter, 0, sizeof(check_filter));
6866         i40e_tunnel_filter_convert(cld_filter, &check_filter);
6867         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
6868         if (add && node) {
6869                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
6870                 return -EINVAL;
6871         }
6872
6873         if (!add && !node) {
6874                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
6875                 return -EINVAL;
6876         }
6877
6878         if (add) {
6879                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
6880                 if (ret < 0) {
6881                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
6882                         return ret;
6883                 }
6884                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
6885                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
6886                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
6887         } else {
6888                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
6889                                                    cld_filter, 1);
6890                 if (ret < 0) {
6891                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
6892                         return ret;
6893                 }
6894                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
6895         }
6896
6897         rte_free(cld_filter);
6898         return ret;
6899 }
6900
6901 static int
6902 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
6903 {
6904         uint8_t i;
6905
6906         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6907                 if (pf->vxlan_ports[i] == port)
6908                         return i;
6909         }
6910
6911         return -1;
6912 }
6913
6914 static int
6915 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
6916 {
6917         int  idx, ret;
6918         uint8_t filter_idx;
6919         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6920
6921         idx = i40e_get_vxlan_port_idx(pf, port);
6922
6923         /* Check if port already exists */
6924         if (idx >= 0) {
6925                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
6926                 return -EINVAL;
6927         }
6928
6929         /* Now check if there is space to add the new port */
6930         idx = i40e_get_vxlan_port_idx(pf, 0);
6931         if (idx < 0) {
6932                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
6933                         "not adding port %d", port);
6934                 return -ENOSPC;
6935         }
6936
6937         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
6938                                         &filter_idx, NULL);
6939         if (ret < 0) {
6940                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
6941                 return -1;
6942         }
6943
6944         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
6945                          port,  filter_idx);
6946
6947         /* New port: add it and mark its index in the bitmap */
6948         pf->vxlan_ports[idx] = port;
6949         pf->vxlan_bitmap |= (1 << idx);
6950
6951         if (!(pf->flags & I40E_FLAG_VXLAN))
6952                 pf->flags |= I40E_FLAG_VXLAN;
6953
6954         return 0;
6955 }
6956
6957 static int
6958 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
6959 {
6960         int idx;
6961         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6962
6963         if (!(pf->flags & I40E_FLAG_VXLAN)) {
6964                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
6965                 return -EINVAL;
6966         }
6967
6968         idx = i40e_get_vxlan_port_idx(pf, port);
6969
6970         if (idx < 0) {
6971                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
6972                 return -EINVAL;
6973         }
6974
6975         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
6976                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
6977                 return -1;
6978         }
6979
6980         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
6981                         port, idx);
6982
6983         pf->vxlan_ports[idx] = 0;
6984         pf->vxlan_bitmap &= ~(1 << idx);
6985
6986         if (!pf->vxlan_bitmap)
6987                 pf->flags &= ~I40E_FLAG_VXLAN;
6988
6989         return 0;
6990 }
6991
6992 /* Add UDP tunneling port */
6993 static int
6994 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
6995                              struct rte_eth_udp_tunnel *udp_tunnel)
6996 {
6997         int ret = 0;
6998         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6999
7000         if (udp_tunnel == NULL)
7001                 return -EINVAL;
7002
7003         switch (udp_tunnel->prot_type) {
7004         case RTE_TUNNEL_TYPE_VXLAN:
7005                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7006                 break;
7007
7008         case RTE_TUNNEL_TYPE_GENEVE:
7009         case RTE_TUNNEL_TYPE_TEREDO:
7010                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7011                 ret = -1;
7012                 break;
7013
7014         default:
7015                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7016                 ret = -1;
7017                 break;
7018         }
7019
7020         return ret;
7021 }
7022
7023 /* Remove UDP tunneling port */
7024 static int
7025 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7026                              struct rte_eth_udp_tunnel *udp_tunnel)
7027 {
7028         int ret = 0;
7029         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7030
7031         if (udp_tunnel == NULL)
7032                 return -EINVAL;
7033
7034         switch (udp_tunnel->prot_type) {
7035         case RTE_TUNNEL_TYPE_VXLAN:
7036                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7037                 break;
7038         case RTE_TUNNEL_TYPE_GENEVE:
7039         case RTE_TUNNEL_TYPE_TEREDO:
7040                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7041                 ret = -1;
7042                 break;
7043         default:
7044                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7045                 ret = -1;
7046                 break;
7047         }
7048
7049         return ret;
7050 }
7051
7052 /* Calculate the maximum number of contiguous PF queues that are configured */
7053 static int
7054 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7055 {
7056         struct rte_eth_dev_data *data = pf->dev_data;
7057         int i, num;
7058         struct i40e_rx_queue *rxq;
7059
7060         num = 0;
7061         for (i = 0; i < pf->lan_nb_qps; i++) {
7062                 rxq = data->rx_queues[i];
7063                 if (rxq && rxq->q_set)
7064                         num++;
7065                 else
7066                         break;
7067         }
7068
7069         return num;
7070 }
7071
7072 /* Configure RSS */
7073 static int
7074 i40e_pf_config_rss(struct i40e_pf *pf)
7075 {
7076         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7077         struct rte_eth_rss_conf rss_conf;
7078         uint32_t i, lut = 0;
7079         uint16_t j, num;
7080
7081         /*
7082          * If both VMDQ and RSS enabled, not all of PF queues are configured.
7083          * It's necessary to calulate the actual PF queues that are configured.
7084          */
7085         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7086                 num = i40e_pf_calc_configured_queues_num(pf);
7087         else
7088                 num = pf->dev_data->nb_rx_queues;
7089
7090         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7091         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7092                         num);
7093
7094         if (num == 0) {
7095                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7096                 return -ENOTSUP;
7097         }
7098
7099         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7100                 if (j == num)
7101                         j = 0;
7102                 lut = (lut << 8) | (j & ((0x1 <<
7103                         hw->func_caps.rss_table_entry_width) - 1));
7104                 if ((i & 3) == 3)
7105                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7106         }
7107
7108         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7109         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
7110                 i40e_pf_disable_rss(pf);
7111                 return 0;
7112         }
7113         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7114                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7115                 /* Random default keys */
7116                 static uint32_t rss_key_default[] = {0x6b793944,
7117                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7118                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7119                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7120
7121                 rss_conf.rss_key = (uint8_t *)rss_key_default;
7122                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7123                                                         sizeof(uint32_t);
7124         }
7125
7126         return i40e_hw_rss_hash_set(pf, &rss_conf);
7127 }
7128
7129 static int
7130 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7131                                struct rte_eth_tunnel_filter_conf *filter)
7132 {
7133         if (pf == NULL || filter == NULL) {
7134                 PMD_DRV_LOG(ERR, "Invalid parameter");
7135                 return -EINVAL;
7136         }
7137
7138         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7139                 PMD_DRV_LOG(ERR, "Invalid queue ID");
7140                 return -EINVAL;
7141         }
7142
7143         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7144                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7145                 return -EINVAL;
7146         }
7147
7148         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7149                 (is_zero_ether_addr(&filter->outer_mac))) {
7150                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7151                 return -EINVAL;
7152         }
7153
7154         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7155                 (is_zero_ether_addr(&filter->inner_mac))) {
7156                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7157                 return -EINVAL;
7158         }
7159
7160         return 0;
7161 }
7162
7163 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7164 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
7165 static int
7166 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7167 {
7168         uint32_t val, reg;
7169         int ret = -EINVAL;
7170
7171         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7172         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x\n", val);
7173
7174         if (len == 3) {
7175                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7176         } else if (len == 4) {
7177                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7178         } else {
7179                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7180                 return ret;
7181         }
7182
7183         if (reg != val) {
7184                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7185                                                    reg, NULL);
7186                 if (ret != 0)
7187                         return ret;
7188         } else {
7189                 ret = 0;
7190         }
7191         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x\n",
7192                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7193
7194         return ret;
7195 }
7196
7197 static int
7198 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7199 {
7200         int ret = -EINVAL;
7201
7202         if (!hw || !cfg)
7203                 return -EINVAL;
7204
7205         switch (cfg->cfg_type) {
7206         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7207                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7208                 break;
7209         default:
7210                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7211                 break;
7212         }
7213
7214         return ret;
7215 }
7216
7217 static int
7218 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7219                                enum rte_filter_op filter_op,
7220                                void *arg)
7221 {
7222         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7223         int ret = I40E_ERR_PARAM;
7224
7225         switch (filter_op) {
7226         case RTE_ETH_FILTER_SET:
7227                 ret = i40e_dev_global_config_set(hw,
7228                         (struct rte_eth_global_cfg *)arg);
7229                 break;
7230         default:
7231                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7232                 break;
7233         }
7234
7235         return ret;
7236 }
7237
7238 static int
7239 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7240                           enum rte_filter_op filter_op,
7241                           void *arg)
7242 {
7243         struct rte_eth_tunnel_filter_conf *filter;
7244         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7245         int ret = I40E_SUCCESS;
7246
7247         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7248
7249         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7250                 return I40E_ERR_PARAM;
7251
7252         switch (filter_op) {
7253         case RTE_ETH_FILTER_NOP:
7254                 if (!(pf->flags & I40E_FLAG_VXLAN))
7255                         ret = I40E_NOT_SUPPORTED;
7256                 break;
7257         case RTE_ETH_FILTER_ADD:
7258                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7259                 break;
7260         case RTE_ETH_FILTER_DELETE:
7261                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7262                 break;
7263         default:
7264                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7265                 ret = I40E_ERR_PARAM;
7266                 break;
7267         }
7268
7269         return ret;
7270 }
7271
7272 static int
7273 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7274 {
7275         int ret = 0;
7276         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7277
7278         /* RSS setup */
7279         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7280                 ret = i40e_pf_config_rss(pf);
7281         else
7282                 i40e_pf_disable_rss(pf);
7283
7284         return ret;
7285 }
7286
7287 /* Get the symmetric hash enable configurations per port */
7288 static void
7289 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7290 {
7291         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7292
7293         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7294 }
7295
7296 /* Set the symmetric hash enable configurations per port */
7297 static void
7298 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7299 {
7300         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7301
7302         if (enable > 0) {
7303                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7304                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
7305                                                         "been enabled");
7306                         return;
7307                 }
7308                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7309         } else {
7310                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7311                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
7312                                                         "been disabled");
7313                         return;
7314                 }
7315                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7316         }
7317         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7318         I40E_WRITE_FLUSH(hw);
7319 }
7320
7321 /*
7322  * Get global configurations of hash function type and symmetric hash enable
7323  * per flow type (pctype). Note that global configuration means it affects all
7324  * the ports on the same NIC.
7325  */
7326 static int
7327 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7328                                    struct rte_eth_hash_global_conf *g_cfg)
7329 {
7330         uint32_t reg, mask = I40E_FLOW_TYPES;
7331         uint16_t i;
7332         enum i40e_filter_pctype pctype;
7333
7334         memset(g_cfg, 0, sizeof(*g_cfg));
7335         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7336         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7337                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7338         else
7339                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7340         PMD_DRV_LOG(DEBUG, "Hash function is %s",
7341                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7342
7343         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
7344                 if (!(mask & (1UL << i)))
7345                         continue;
7346                 mask &= ~(1UL << i);
7347                 /* Bit set indicats the coresponding flow type is supported */
7348                 g_cfg->valid_bit_mask[0] |= (1UL << i);
7349                 /* if flowtype is invalid, continue */
7350                 if (!I40E_VALID_FLOW(i))
7351                         continue;
7352                 pctype = i40e_flowtype_to_pctype(i);
7353                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(pctype));
7354                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
7355                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
7356         }
7357
7358         return 0;
7359 }
7360
7361 static int
7362 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
7363 {
7364         uint32_t i;
7365         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
7366
7367         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
7368                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
7369                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
7370                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
7371                                                 g_cfg->hash_func);
7372                 return -EINVAL;
7373         }
7374
7375         /*
7376          * As i40e supports less than 32 flow types, only first 32 bits need to
7377          * be checked.
7378          */
7379         mask0 = g_cfg->valid_bit_mask[0];
7380         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
7381                 if (i == 0) {
7382                         /* Check if any unsupported flow type configured */
7383                         if ((mask0 | i40e_mask) ^ i40e_mask)
7384                                 goto mask_err;
7385                 } else {
7386                         if (g_cfg->valid_bit_mask[i])
7387                                 goto mask_err;
7388                 }
7389         }
7390
7391         return 0;
7392
7393 mask_err:
7394         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
7395
7396         return -EINVAL;
7397 }
7398
7399 /*
7400  * Set global configurations of hash function type and symmetric hash enable
7401  * per flow type (pctype). Note any modifying global configuration will affect
7402  * all the ports on the same NIC.
7403  */
7404 static int
7405 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
7406                                    struct rte_eth_hash_global_conf *g_cfg)
7407 {
7408         int ret;
7409         uint16_t i;
7410         uint32_t reg;
7411         uint32_t mask0 = g_cfg->valid_bit_mask[0];
7412         enum i40e_filter_pctype pctype;
7413
7414         /* Check the input parameters */
7415         ret = i40e_hash_global_config_check(g_cfg);
7416         if (ret < 0)
7417                 return ret;
7418
7419         for (i = 0; mask0 && i < UINT32_BIT; i++) {
7420                 if (!(mask0 & (1UL << i)))
7421                         continue;
7422                 mask0 &= ~(1UL << i);
7423                 /* if flowtype is invalid, continue */
7424                 if (!I40E_VALID_FLOW(i))
7425                         continue;
7426                 pctype = i40e_flowtype_to_pctype(i);
7427                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
7428                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
7429                 i40e_write_rx_ctl(hw, I40E_GLQF_HSYM(pctype), reg);
7430         }
7431
7432         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7433         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
7434                 /* Toeplitz */
7435                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
7436                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7437                                                                 "Toeplitz");
7438                         goto out;
7439                 }
7440                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
7441         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
7442                 /* Simple XOR */
7443                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
7444                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
7445                                                         "Simple XOR");
7446                         goto out;
7447                 }
7448                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
7449         } else
7450                 /* Use the default, and keep it as it is */
7451                 goto out;
7452
7453         i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
7454
7455 out:
7456         I40E_WRITE_FLUSH(hw);
7457
7458         return 0;
7459 }
7460
7461 /**
7462  * Valid input sets for hash and flow director filters per PCTYPE
7463  */
7464 static uint64_t
7465 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
7466                 enum rte_filter_type filter)
7467 {
7468         uint64_t valid;
7469
7470         static const uint64_t valid_hash_inset_table[] = {
7471                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7472                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7473                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7474                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
7475                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
7476                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7477                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7478                         I40E_INSET_FLEX_PAYLOAD,
7479                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7480                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7481                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7482                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7483                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7484                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7485                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7486                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7487                         I40E_INSET_FLEX_PAYLOAD,
7488                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7489                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7490                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7491                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7492                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7493                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7494                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7495                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7496                         I40E_INSET_FLEX_PAYLOAD,
7497                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7498                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7499                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7500                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7501                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7502                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7503                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7504                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7505                         I40E_INSET_FLEX_PAYLOAD,
7506                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7507                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7508                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7509                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7510                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7511                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7512                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7513                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7514                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7515                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7516                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7517                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7518                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7519                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7520                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7521                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7522                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7523                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
7524                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7525                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7526                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7527                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7528                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7529                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7530                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7531                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7532                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
7533                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7534                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7535                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7536                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
7537                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
7538                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
7539                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7540                         I40E_INSET_FLEX_PAYLOAD,
7541                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7542                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7543                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7544                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7545                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7546                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
7547                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
7548                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
7549                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7550                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7551                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7552                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7553                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7554                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7555                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7556                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
7557                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7558                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7559                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7560                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7561                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7562                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7563                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7564                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7565                         I40E_INSET_FLEX_PAYLOAD,
7566                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7567                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7568                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7569                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7570                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7571                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7572                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7573                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7574                         I40E_INSET_FLEX_PAYLOAD,
7575                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7576                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7577                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7578                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7579                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7580                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7581                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7582                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7583                         I40E_INSET_FLEX_PAYLOAD,
7584                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7585                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7586                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7587                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7588                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7589                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7590                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7591                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
7592                         I40E_INSET_FLEX_PAYLOAD,
7593                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7594                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7595                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7596                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7597                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7598                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7599                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
7600                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
7601                         I40E_INSET_FLEX_PAYLOAD,
7602                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7603                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7604                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7605                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
7606                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
7607                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
7608                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
7609                         I40E_INSET_FLEX_PAYLOAD,
7610                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7611                         I40E_INSET_DMAC | I40E_INSET_SMAC |
7612                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7613                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
7614                         I40E_INSET_FLEX_PAYLOAD,
7615         };
7616
7617         /**
7618          * Flow director supports only fields defined in
7619          * union rte_eth_fdir_flow.
7620          */
7621         static const uint64_t valid_fdir_inset_table[] = {
7622                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7623                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7624                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7625                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7626                 I40E_INSET_IPV4_TTL,
7627                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7628                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7629                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7630                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7631                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7632                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7633                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7634                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7635                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7636                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7637                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7638                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7639                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7640                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7641                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7642                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7643                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7644                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7645                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7646                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7647                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7648                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7649                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7650                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7651                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7652                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7653                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7654                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7655                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
7656                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7657                 I40E_INSET_SCTP_VT,
7658                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7659                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7660                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7661                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
7662                 I40E_INSET_IPV4_TTL,
7663                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7664                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7665                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7666                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7667                 I40E_INSET_IPV6_HOP_LIMIT,
7668                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7669                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7670                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7671                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7672                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7673                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7674                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7675                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7676                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7677                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7678                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7679                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7680                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7681                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7682                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7683                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7684                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7685                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7686                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7687                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7688                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7689                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7690                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7691                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7692                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7693                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7694                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7695                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7696                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
7697                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7698                 I40E_INSET_SCTP_VT,
7699                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7700                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7701                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7702                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
7703                 I40E_INSET_IPV6_HOP_LIMIT,
7704                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7705                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
7706                 I40E_INSET_LAST_ETHER_TYPE,
7707         };
7708
7709         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7710                 return 0;
7711         if (filter == RTE_ETH_FILTER_HASH)
7712                 valid = valid_hash_inset_table[pctype];
7713         else
7714                 valid = valid_fdir_inset_table[pctype];
7715
7716         return valid;
7717 }
7718
7719 /**
7720  * Validate if the input set is allowed for a specific PCTYPE
7721  */
7722 static int
7723 i40e_validate_input_set(enum i40e_filter_pctype pctype,
7724                 enum rte_filter_type filter, uint64_t inset)
7725 {
7726         uint64_t valid;
7727
7728         valid = i40e_get_valid_input_set(pctype, filter);
7729         if (inset & (~valid))
7730                 return -EINVAL;
7731
7732         return 0;
7733 }
7734
7735 /* default input set fields combination per pctype */
7736 static uint64_t
7737 i40e_get_default_input_set(uint16_t pctype)
7738 {
7739         static const uint64_t default_inset_table[] = {
7740                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
7741                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7742                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
7743                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7744                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7745                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
7746                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7747                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7748                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
7749                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7750                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7751                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
7752                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7753                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7754                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
7755                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7756                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7757                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
7758                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
7759                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7760                         I40E_INSET_SCTP_VT,
7761                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
7762                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
7763                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
7764                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7765                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
7766                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7767                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7768                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
7769                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7770                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7771                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
7772                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7773                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7774                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
7775                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7776                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7777                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
7778                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7779                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
7780                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
7781                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
7782                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
7783                         I40E_INSET_SCTP_VT,
7784                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
7785                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
7786                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
7787                         I40E_INSET_LAST_ETHER_TYPE,
7788         };
7789
7790         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
7791                 return 0;
7792
7793         return default_inset_table[pctype];
7794 }
7795
7796 /**
7797  * Parse the input set from index to logical bit masks
7798  */
7799 static int
7800 i40e_parse_input_set(uint64_t *inset,
7801                      enum i40e_filter_pctype pctype,
7802                      enum rte_eth_input_set_field *field,
7803                      uint16_t size)
7804 {
7805         uint16_t i, j;
7806         int ret = -EINVAL;
7807
7808         static const struct {
7809                 enum rte_eth_input_set_field field;
7810                 uint64_t inset;
7811         } inset_convert_table[] = {
7812                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
7813                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
7814                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
7815                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
7816                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
7817                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
7818                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
7819                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
7820                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
7821                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
7822                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
7823                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
7824                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
7825                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
7826                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
7827                         I40E_INSET_IPV6_NEXT_HDR},
7828                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
7829                         I40E_INSET_IPV6_HOP_LIMIT},
7830                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
7831                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
7832                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
7833                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
7834                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
7835                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
7836                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
7837                         I40E_INSET_SCTP_VT},
7838                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
7839                         I40E_INSET_TUNNEL_DMAC},
7840                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
7841                         I40E_INSET_VLAN_TUNNEL},
7842                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
7843                         I40E_INSET_TUNNEL_ID},
7844                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
7845                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
7846                         I40E_INSET_FLEX_PAYLOAD_W1},
7847                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
7848                         I40E_INSET_FLEX_PAYLOAD_W2},
7849                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
7850                         I40E_INSET_FLEX_PAYLOAD_W3},
7851                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
7852                         I40E_INSET_FLEX_PAYLOAD_W4},
7853                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
7854                         I40E_INSET_FLEX_PAYLOAD_W5},
7855                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
7856                         I40E_INSET_FLEX_PAYLOAD_W6},
7857                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
7858                         I40E_INSET_FLEX_PAYLOAD_W7},
7859                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
7860                         I40E_INSET_FLEX_PAYLOAD_W8},
7861         };
7862
7863         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
7864                 return ret;
7865
7866         /* Only one item allowed for default or all */
7867         if (size == 1) {
7868                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
7869                         *inset = i40e_get_default_input_set(pctype);
7870                         return 0;
7871                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
7872                         *inset = I40E_INSET_NONE;
7873                         return 0;
7874                 }
7875         }
7876
7877         for (i = 0, *inset = 0; i < size; i++) {
7878                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
7879                         if (field[i] == inset_convert_table[j].field) {
7880                                 *inset |= inset_convert_table[j].inset;
7881                                 break;
7882                         }
7883                 }
7884
7885                 /* It contains unsupported input set, return immediately */
7886                 if (j == RTE_DIM(inset_convert_table))
7887                         return ret;
7888         }
7889
7890         return 0;
7891 }
7892
7893 /**
7894  * Translate the input set from bit masks to register aware bit masks
7895  * and vice versa
7896  */
7897 static uint64_t
7898 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
7899 {
7900         uint64_t val = 0;
7901         uint16_t i;
7902
7903         struct inset_map {
7904                 uint64_t inset;
7905                 uint64_t inset_reg;
7906         };
7907
7908         static const struct inset_map inset_map_common[] = {
7909                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
7910                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
7911                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
7912                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
7913                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
7914                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
7915                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
7916                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
7917                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
7918                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
7919                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
7920                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
7921                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
7922                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
7923                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
7924                 {I40E_INSET_TUNNEL_DMAC,
7925                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
7926                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
7927                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
7928                 {I40E_INSET_TUNNEL_SRC_PORT,
7929                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
7930                 {I40E_INSET_TUNNEL_DST_PORT,
7931                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
7932                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
7933                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
7934                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
7935                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
7936                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
7937                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
7938                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
7939                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
7940                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
7941         };
7942
7943     /* some different registers map in x722*/
7944         static const struct inset_map inset_map_diff_x722[] = {
7945                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
7946                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
7947                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
7948                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
7949         };
7950
7951         static const struct inset_map inset_map_diff_not_x722[] = {
7952                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
7953                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
7954                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
7955                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
7956         };
7957
7958         if (input == 0)
7959                 return val;
7960
7961         /* Translate input set to register aware inset */
7962         if (type == I40E_MAC_X722) {
7963                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
7964                         if (input & inset_map_diff_x722[i].inset)
7965                                 val |= inset_map_diff_x722[i].inset_reg;
7966                 }
7967         } else {
7968                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
7969                         if (input & inset_map_diff_not_x722[i].inset)
7970                                 val |= inset_map_diff_not_x722[i].inset_reg;
7971                 }
7972         }
7973
7974         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
7975                 if (input & inset_map_common[i].inset)
7976                         val |= inset_map_common[i].inset_reg;
7977         }
7978
7979         return val;
7980 }
7981
7982 static int
7983 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
7984 {
7985         uint8_t i, idx = 0;
7986         uint64_t inset_need_mask = inset;
7987
7988         static const struct {
7989                 uint64_t inset;
7990                 uint32_t mask;
7991         } inset_mask_map[] = {
7992                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
7993                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
7994                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
7995                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
7996                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
7997                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
7998                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
7999                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8000         };
8001
8002         if (!inset || !mask || !nb_elem)
8003                 return 0;
8004
8005         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8006                 /* Clear the inset bit, if no MASK is required,
8007                  * for example proto + ttl
8008                  */
8009                 if ((inset & inset_mask_map[i].inset) ==
8010                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8011                         inset_need_mask &= ~inset_mask_map[i].inset;
8012                 if (!inset_need_mask)
8013                         return 0;
8014         }
8015         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8016                 if ((inset_need_mask & inset_mask_map[i].inset) ==
8017                     inset_mask_map[i].inset) {
8018                         if (idx >= nb_elem) {
8019                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8020                                 return -EINVAL;
8021                         }
8022                         mask[idx] = inset_mask_map[i].mask;
8023                         idx++;
8024                 }
8025         }
8026
8027         return idx;
8028 }
8029
8030 static void
8031 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8032 {
8033         uint32_t reg = i40e_read_rx_ctl(hw, addr);
8034
8035         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x\n", addr, reg);
8036         if (reg != val)
8037                 i40e_write_rx_ctl(hw, addr, val);
8038         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x\n", addr,
8039                     (uint32_t)i40e_read_rx_ctl(hw, addr));
8040 }
8041
8042 static void
8043 i40e_filter_input_set_init(struct i40e_pf *pf)
8044 {
8045         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8046         enum i40e_filter_pctype pctype;
8047         uint64_t input_set, inset_reg;
8048         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8049         int num, i;
8050
8051         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8052              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8053                 if (hw->mac.type == I40E_MAC_X722) {
8054                         if (!I40E_VALID_PCTYPE_X722(pctype))
8055                                 continue;
8056                 } else {
8057                         if (!I40E_VALID_PCTYPE(pctype))
8058                                 continue;
8059                 }
8060
8061                 input_set = i40e_get_default_input_set(pctype);
8062
8063                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8064                                                    I40E_INSET_MASK_NUM_REG);
8065                 if (num < 0)
8066                         return;
8067                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8068                                         input_set);
8069
8070                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8071                                       (uint32_t)(inset_reg & UINT32_MAX));
8072                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8073                                      (uint32_t)((inset_reg >>
8074                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8075                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8076                                       (uint32_t)(inset_reg & UINT32_MAX));
8077                 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8078                                      (uint32_t)((inset_reg >>
8079                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
8080
8081                 for (i = 0; i < num; i++) {
8082                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8083                                              mask_reg[i]);
8084                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8085                                              mask_reg[i]);
8086                 }
8087                 /*clear unused mask registers of the pctype */
8088                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8089                         i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8090                                              0);
8091                         i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8092                                              0);
8093                 }
8094                 I40E_WRITE_FLUSH(hw);
8095
8096                 /* store the default input set */
8097                 pf->hash_input_set[pctype] = input_set;
8098                 pf->fdir.input_set[pctype] = input_set;
8099         }
8100 }
8101
8102 int
8103 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8104                          struct rte_eth_input_set_conf *conf)
8105 {
8106         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8107         enum i40e_filter_pctype pctype;
8108         uint64_t input_set, inset_reg = 0;
8109         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8110         int ret, i, num;
8111
8112         if (!conf) {
8113                 PMD_DRV_LOG(ERR, "Invalid pointer");
8114                 return -EFAULT;
8115         }
8116         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8117             conf->op != RTE_ETH_INPUT_SET_ADD) {
8118                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8119                 return -EINVAL;
8120         }
8121
8122         if (!I40E_VALID_FLOW(conf->flow_type)) {
8123                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8124                 return -EINVAL;
8125         }
8126
8127         if (hw->mac.type == I40E_MAC_X722) {
8128                 /* get translated pctype value in fd pctype register */
8129                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8130                         I40E_GLQF_FD_PCTYPES((int)i40e_flowtype_to_pctype(
8131                         conf->flow_type)));
8132         } else
8133                 pctype = i40e_flowtype_to_pctype(conf->flow_type);
8134
8135         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8136                                    conf->inset_size);
8137         if (ret) {
8138                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8139                 return -EINVAL;
8140         }
8141         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_HASH,
8142                                     input_set) != 0) {
8143                 PMD_DRV_LOG(ERR, "Invalid input set");
8144                 return -EINVAL;
8145         }
8146         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8147                 /* get inset value in register */
8148                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8149                 inset_reg <<= I40E_32_BIT_WIDTH;
8150                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8151                 input_set |= pf->hash_input_set[pctype];
8152         }
8153         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8154                                            I40E_INSET_MASK_NUM_REG);
8155         if (num < 0)
8156                 return -EINVAL;
8157
8158         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8159
8160         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8161                               (uint32_t)(inset_reg & UINT32_MAX));
8162         i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8163                              (uint32_t)((inset_reg >>
8164                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8165
8166         for (i = 0; i < num; i++)
8167                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8168                                      mask_reg[i]);
8169         /*clear unused mask registers of the pctype */
8170         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8171                 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8172                                      0);
8173         I40E_WRITE_FLUSH(hw);
8174
8175         pf->hash_input_set[pctype] = input_set;
8176         return 0;
8177 }
8178
8179 int
8180 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8181                          struct rte_eth_input_set_conf *conf)
8182 {
8183         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8184         enum i40e_filter_pctype pctype;
8185         uint64_t input_set, inset_reg = 0;
8186         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8187         int ret, i, num;
8188
8189         if (!hw || !conf) {
8190                 PMD_DRV_LOG(ERR, "Invalid pointer");
8191                 return -EFAULT;
8192         }
8193         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8194             conf->op != RTE_ETH_INPUT_SET_ADD) {
8195                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8196                 return -EINVAL;
8197         }
8198
8199         if (!I40E_VALID_FLOW(conf->flow_type)) {
8200                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8201                 return -EINVAL;
8202         }
8203
8204         pctype = i40e_flowtype_to_pctype(conf->flow_type);
8205
8206         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8207                                    conf->inset_size);
8208         if (ret) {
8209                 PMD_DRV_LOG(ERR, "Failed to parse input set");
8210                 return -EINVAL;
8211         }
8212         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
8213                                     input_set) != 0) {
8214                 PMD_DRV_LOG(ERR, "Invalid input set");
8215                 return -EINVAL;
8216         }
8217
8218         /* get inset value in register */
8219         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8220         inset_reg <<= I40E_32_BIT_WIDTH;
8221         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8222
8223         /* Can not change the inset reg for flex payload for fdir,
8224          * it is done by writing I40E_PRTQF_FD_FLXINSET
8225          * in i40e_set_flex_mask_on_pctype.
8226          */
8227         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8228                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8229         else
8230                 input_set |= pf->fdir.input_set[pctype];
8231         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8232                                            I40E_INSET_MASK_NUM_REG);
8233         if (num < 0)
8234                 return -EINVAL;
8235
8236         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8237
8238         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8239                               (uint32_t)(inset_reg & UINT32_MAX));
8240         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8241                              (uint32_t)((inset_reg >>
8242                              I40E_32_BIT_WIDTH) & UINT32_MAX));
8243
8244         for (i = 0; i < num; i++)
8245                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8246                                      mask_reg[i]);
8247         /*clear unused mask registers of the pctype */
8248         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8249                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8250                                      0);
8251         I40E_WRITE_FLUSH(hw);
8252
8253         pf->fdir.input_set[pctype] = input_set;
8254         return 0;
8255 }
8256
8257 static int
8258 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8259 {
8260         int ret = 0;
8261
8262         if (!hw || !info) {
8263                 PMD_DRV_LOG(ERR, "Invalid pointer");
8264                 return -EFAULT;
8265         }
8266
8267         switch (info->info_type) {
8268         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8269                 i40e_get_symmetric_hash_enable_per_port(hw,
8270                                         &(info->info.enable));
8271                 break;
8272         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8273                 ret = i40e_get_hash_filter_global_config(hw,
8274                                 &(info->info.global_conf));
8275                 break;
8276         default:
8277                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8278                                                         info->info_type);
8279                 ret = -EINVAL;
8280                 break;
8281         }
8282
8283         return ret;
8284 }
8285
8286 static int
8287 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8288 {
8289         int ret = 0;
8290
8291         if (!hw || !info) {
8292                 PMD_DRV_LOG(ERR, "Invalid pointer");
8293                 return -EFAULT;
8294         }
8295
8296         switch (info->info_type) {
8297         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8298                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8299                 break;
8300         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8301                 ret = i40e_set_hash_filter_global_config(hw,
8302                                 &(info->info.global_conf));
8303                 break;
8304         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8305                 ret = i40e_hash_filter_inset_select(hw,
8306                                                &(info->info.input_set_conf));
8307                 break;
8308
8309         default:
8310                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8311                                                         info->info_type);
8312                 ret = -EINVAL;
8313                 break;
8314         }
8315
8316         return ret;
8317 }
8318
8319 /* Operations for hash function */
8320 static int
8321 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8322                       enum rte_filter_op filter_op,
8323                       void *arg)
8324 {
8325         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8326         int ret = 0;
8327
8328         switch (filter_op) {
8329         case RTE_ETH_FILTER_NOP:
8330                 break;
8331         case RTE_ETH_FILTER_GET:
8332                 ret = i40e_hash_filter_get(hw,
8333                         (struct rte_eth_hash_filter_info *)arg);
8334                 break;
8335         case RTE_ETH_FILTER_SET:
8336                 ret = i40e_hash_filter_set(hw,
8337                         (struct rte_eth_hash_filter_info *)arg);
8338                 break;
8339         default:
8340                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8341                                                                 filter_op);
8342                 ret = -ENOTSUP;
8343                 break;
8344         }
8345
8346         return ret;
8347 }
8348
8349 /* Convert ethertype filter structure */
8350 static int
8351 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8352                               struct i40e_ethertype_filter *filter)
8353 {
8354         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8355         filter->input.ether_type = input->ether_type;
8356         filter->flags = input->flags;
8357         filter->queue = input->queue;
8358
8359         return 0;
8360 }
8361
8362 /* Check if there exists the ehtertype filter */
8363 struct i40e_ethertype_filter *
8364 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8365                                 const struct i40e_ethertype_filter_input *input)
8366 {
8367         int ret;
8368
8369         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
8370         if (ret < 0)
8371                 return NULL;
8372
8373         return ethertype_rule->hash_map[ret];
8374 }
8375
8376 /* Add ethertype filter in SW list */
8377 static int
8378 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
8379                                 struct i40e_ethertype_filter *filter)
8380 {
8381         struct i40e_ethertype_rule *rule = &pf->ethertype;
8382         int ret;
8383
8384         ret = rte_hash_add_key(rule->hash_table, &filter->input);
8385         if (ret < 0) {
8386                 PMD_DRV_LOG(ERR,
8387                             "Failed to insert ethertype filter"
8388                             " to hash table %d!",
8389                             ret);
8390                 return ret;
8391         }
8392         rule->hash_map[ret] = filter;
8393
8394         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
8395
8396         return 0;
8397 }
8398
8399 /* Delete ethertype filter in SW list */
8400 int
8401 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
8402                              struct i40e_ethertype_filter_input *input)
8403 {
8404         struct i40e_ethertype_rule *rule = &pf->ethertype;
8405         struct i40e_ethertype_filter *filter;
8406         int ret;
8407
8408         ret = rte_hash_del_key(rule->hash_table, input);
8409         if (ret < 0) {
8410                 PMD_DRV_LOG(ERR,
8411                             "Failed to delete ethertype filter"
8412                             " to hash table %d!",
8413                             ret);
8414                 return ret;
8415         }
8416         filter = rule->hash_map[ret];
8417         rule->hash_map[ret] = NULL;
8418
8419         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
8420         rte_free(filter);
8421
8422         return 0;
8423 }
8424
8425 /*
8426  * Configure ethertype filter, which can director packet by filtering
8427  * with mac address and ether_type or only ether_type
8428  */
8429 static int
8430 i40e_ethertype_filter_set(struct i40e_pf *pf,
8431                         struct rte_eth_ethertype_filter *filter,
8432                         bool add)
8433 {
8434         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8435         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
8436         struct i40e_ethertype_filter *ethertype_filter, *node;
8437         struct i40e_ethertype_filter check_filter;
8438         struct i40e_control_filter_stats stats;
8439         uint16_t flags = 0;
8440         int ret;
8441
8442         if (filter->queue >= pf->dev_data->nb_rx_queues) {
8443                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8444                 return -EINVAL;
8445         }
8446         if (filter->ether_type == ETHER_TYPE_IPv4 ||
8447                 filter->ether_type == ETHER_TYPE_IPv6) {
8448                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
8449                         " control packet filter.", filter->ether_type);
8450                 return -EINVAL;
8451         }
8452         if (filter->ether_type == ETHER_TYPE_VLAN)
8453                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
8454                         " not supported.");
8455
8456         /* Check if there is the filter in SW list */
8457         memset(&check_filter, 0, sizeof(check_filter));
8458         i40e_ethertype_filter_convert(filter, &check_filter);
8459         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
8460                                                &check_filter.input);
8461         if (add && node) {
8462                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
8463                 return -EINVAL;
8464         }
8465
8466         if (!add && !node) {
8467                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
8468                 return -EINVAL;
8469         }
8470
8471         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
8472                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
8473         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
8474                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
8475         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
8476
8477         memset(&stats, 0, sizeof(stats));
8478         ret = i40e_aq_add_rem_control_packet_filter(hw,
8479                         filter->mac_addr.addr_bytes,
8480                         filter->ether_type, flags,
8481                         pf->main_vsi->seid,
8482                         filter->queue, add, &stats, NULL);
8483
8484         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
8485                          " mac_etype_used = %u, etype_used = %u,"
8486                          " mac_etype_free = %u, etype_free = %u\n",
8487                          ret, stats.mac_etype_used, stats.etype_used,
8488                          stats.mac_etype_free, stats.etype_free);
8489         if (ret < 0)
8490                 return -ENOSYS;
8491
8492         /* Add or delete a filter in SW list */
8493         if (add) {
8494                 ethertype_filter = rte_zmalloc("ethertype_filter",
8495                                        sizeof(*ethertype_filter), 0);
8496                 rte_memcpy(ethertype_filter, &check_filter,
8497                            sizeof(check_filter));
8498                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
8499         } else {
8500                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
8501         }
8502
8503         return ret;
8504 }
8505
8506 /*
8507  * Handle operations for ethertype filter.
8508  */
8509 static int
8510 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
8511                                 enum rte_filter_op filter_op,
8512                                 void *arg)
8513 {
8514         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8515         int ret = 0;
8516
8517         if (filter_op == RTE_ETH_FILTER_NOP)
8518                 return ret;
8519
8520         if (arg == NULL) {
8521                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
8522                             filter_op);
8523                 return -EINVAL;
8524         }
8525
8526         switch (filter_op) {
8527         case RTE_ETH_FILTER_ADD:
8528                 ret = i40e_ethertype_filter_set(pf,
8529                         (struct rte_eth_ethertype_filter *)arg,
8530                         TRUE);
8531                 break;
8532         case RTE_ETH_FILTER_DELETE:
8533                 ret = i40e_ethertype_filter_set(pf,
8534                         (struct rte_eth_ethertype_filter *)arg,
8535                         FALSE);
8536                 break;
8537         default:
8538                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
8539                 ret = -ENOSYS;
8540                 break;
8541         }
8542         return ret;
8543 }
8544
8545 static int
8546 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
8547                      enum rte_filter_type filter_type,
8548                      enum rte_filter_op filter_op,
8549                      void *arg)
8550 {
8551         int ret = 0;
8552
8553         if (dev == NULL)
8554                 return -EINVAL;
8555
8556         switch (filter_type) {
8557         case RTE_ETH_FILTER_NONE:
8558                 /* For global configuration */
8559                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
8560                 break;
8561         case RTE_ETH_FILTER_HASH:
8562                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
8563                 break;
8564         case RTE_ETH_FILTER_MACVLAN:
8565                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
8566                 break;
8567         case RTE_ETH_FILTER_ETHERTYPE:
8568                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
8569                 break;
8570         case RTE_ETH_FILTER_TUNNEL:
8571                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
8572                 break;
8573         case RTE_ETH_FILTER_FDIR:
8574                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
8575                 break;
8576         default:
8577                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
8578                                                         filter_type);
8579                 ret = -EINVAL;
8580                 break;
8581         }
8582
8583         return ret;
8584 }
8585
8586 /*
8587  * Check and enable Extended Tag.
8588  * Enabling Extended Tag is important for 40G performance.
8589  */
8590 static void
8591 i40e_enable_extended_tag(struct rte_eth_dev *dev)
8592 {
8593         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
8594         uint32_t buf = 0;
8595         int ret;
8596
8597         ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8598                                       PCI_DEV_CAP_REG);
8599         if (ret < 0) {
8600                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8601                             PCI_DEV_CAP_REG);
8602                 return;
8603         }
8604         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
8605                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
8606                 return;
8607         }
8608
8609         buf = 0;
8610         ret = rte_eal_pci_read_config(pci_dev, &buf, sizeof(buf),
8611                                       PCI_DEV_CTRL_REG);
8612         if (ret < 0) {
8613                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
8614                             PCI_DEV_CTRL_REG);
8615                 return;
8616         }
8617         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
8618                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
8619                 return;
8620         }
8621         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
8622         ret = rte_eal_pci_write_config(pci_dev, &buf, sizeof(buf),
8623                                        PCI_DEV_CTRL_REG);
8624         if (ret < 0) {
8625                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
8626                             PCI_DEV_CTRL_REG);
8627                 return;
8628         }
8629 }
8630
8631 /*
8632  * As some registers wouldn't be reset unless a global hardware reset,
8633  * hardware initialization is needed to put those registers into an
8634  * expected initial state.
8635  */
8636 static void
8637 i40e_hw_init(struct rte_eth_dev *dev)
8638 {
8639         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8640
8641         i40e_enable_extended_tag(dev);
8642
8643         /* clear the PF Queue Filter control register */
8644         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
8645
8646         /* Disable symmetric hash per port */
8647         i40e_set_symmetric_hash_enable_per_port(hw, 0);
8648 }
8649
8650 enum i40e_filter_pctype
8651 i40e_flowtype_to_pctype(uint16_t flow_type)
8652 {
8653         static const enum i40e_filter_pctype pctype_table[] = {
8654                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
8655                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
8656                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
8657                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
8658                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
8659                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
8660                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
8661                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
8662                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
8663                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
8664                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
8665                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
8666                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
8667                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
8668                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
8669                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
8670                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
8671                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
8672                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
8673         };
8674
8675         return pctype_table[flow_type];
8676 }
8677
8678 uint16_t
8679 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
8680 {
8681         static const uint16_t flowtype_table[] = {
8682                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
8683                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8684                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8685                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8686                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8687                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8688                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
8689                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8690                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8691                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8692                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
8693                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8694                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
8695                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8696                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
8697                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
8698                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8699                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8700                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8701                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8702                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8703                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
8704                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8705                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8706                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8707                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
8708                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8709                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
8710                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8711                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
8712                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
8713         };
8714
8715         return flowtype_table[pctype];
8716 }
8717
8718 /*
8719  * On X710, performance number is far from the expectation on recent firmware
8720  * versions; on XL710, performance number is also far from the expectation on
8721  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
8722  * mode is enabled and port MAC address is equal to the packet destination MAC
8723  * address. The fix for this issue may not be integrated in the following
8724  * firmware version. So the workaround in software driver is needed. It needs
8725  * to modify the initial values of 3 internal only registers for both X710 and
8726  * XL710. Note that the values for X710 or XL710 could be different, and the
8727  * workaround can be removed when it is fixed in firmware in the future.
8728  */
8729
8730 /* For both X710 and XL710 */
8731 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
8732 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
8733
8734 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
8735 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
8736
8737 /* For X710 */
8738 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
8739 /* For XL710 */
8740 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
8741 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
8742
8743 static int
8744 i40e_dev_sync_phy_type(struct i40e_hw *hw)
8745 {
8746         enum i40e_status_code status;
8747         struct i40e_aq_get_phy_abilities_resp phy_ab;
8748         int ret = -ENOTSUP;
8749
8750         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
8751                                               NULL);
8752
8753         if (status)
8754                 return ret;
8755
8756         return 0;
8757 }
8758
8759
8760 static void
8761 i40e_configure_registers(struct i40e_hw *hw)
8762 {
8763         static struct {
8764                 uint32_t addr;
8765                 uint64_t val;
8766         } reg_table[] = {
8767                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
8768                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
8769                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
8770         };
8771         uint64_t reg;
8772         uint32_t i;
8773         int ret;
8774
8775         for (i = 0; i < RTE_DIM(reg_table); i++) {
8776                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
8777                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
8778                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
8779                                 reg_table[i].val =
8780                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
8781                         else /* For X710 */
8782                                 reg_table[i].val =
8783                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
8784                 }
8785
8786                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
8787                                                         &reg, NULL);
8788                 if (ret < 0) {
8789                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
8790                                                         reg_table[i].addr);
8791                         break;
8792                 }
8793                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
8794                                                 reg_table[i].addr, reg);
8795                 if (reg == reg_table[i].val)
8796                         continue;
8797
8798                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
8799                                                 reg_table[i].val, NULL);
8800                 if (ret < 0) {
8801                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
8802                                 "address of 0x%"PRIx32, reg_table[i].val,
8803                                                         reg_table[i].addr);
8804                         break;
8805                 }
8806                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
8807                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
8808         }
8809 }
8810
8811 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
8812 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
8813 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
8814 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
8815 static int
8816 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
8817 {
8818         uint32_t reg;
8819         int ret;
8820
8821         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
8822                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
8823                 return -EINVAL;
8824         }
8825
8826         /* Configure for double VLAN RX stripping */
8827         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
8828         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
8829                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
8830                 ret = i40e_aq_debug_write_register(hw,
8831                                                    I40E_VSI_TSR(vsi->vsi_id),
8832                                                    reg, NULL);
8833                 if (ret < 0) {
8834                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
8835                                     vsi->vsi_id);
8836                         return I40E_ERR_CONFIG;
8837                 }
8838         }
8839
8840         /* Configure for double VLAN TX insertion */
8841         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
8842         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
8843                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
8844                 ret = i40e_aq_debug_write_register(hw,
8845                                                    I40E_VSI_L2TAGSTXVALID(
8846                                                    vsi->vsi_id), reg, NULL);
8847                 if (ret < 0) {
8848                         PMD_DRV_LOG(ERR, "Failed to update "
8849                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
8850                         return I40E_ERR_CONFIG;
8851                 }
8852         }
8853
8854         return 0;
8855 }
8856
8857 /**
8858  * i40e_aq_add_mirror_rule
8859  * @hw: pointer to the hardware structure
8860  * @seid: VEB seid to add mirror rule to
8861  * @dst_id: destination vsi seid
8862  * @entries: Buffer which contains the entities to be mirrored
8863  * @count: number of entities contained in the buffer
8864  * @rule_id:the rule_id of the rule to be added
8865  *
8866  * Add a mirror rule for a given veb.
8867  *
8868  **/
8869 static enum i40e_status_code
8870 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
8871                         uint16_t seid, uint16_t dst_id,
8872                         uint16_t rule_type, uint16_t *entries,
8873                         uint16_t count, uint16_t *rule_id)
8874 {
8875         struct i40e_aq_desc desc;
8876         struct i40e_aqc_add_delete_mirror_rule cmd;
8877         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
8878                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
8879                 &desc.params.raw;
8880         uint16_t buff_len;
8881         enum i40e_status_code status;
8882
8883         i40e_fill_default_direct_cmd_desc(&desc,
8884                                           i40e_aqc_opc_add_mirror_rule);
8885         memset(&cmd, 0, sizeof(cmd));
8886
8887         buff_len = sizeof(uint16_t) * count;
8888         desc.datalen = rte_cpu_to_le_16(buff_len);
8889         if (buff_len > 0)
8890                 desc.flags |= rte_cpu_to_le_16(
8891                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
8892         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8893                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8894         cmd.num_entries = rte_cpu_to_le_16(count);
8895         cmd.seid = rte_cpu_to_le_16(seid);
8896         cmd.destination = rte_cpu_to_le_16(dst_id);
8897
8898         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8899         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
8900         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
8901                          "rule_id = %u"
8902                          " mirror_rules_used = %u, mirror_rules_free = %u,",
8903                          hw->aq.asq_last_status, resp->rule_id,
8904                          resp->mirror_rules_used, resp->mirror_rules_free);
8905         *rule_id = rte_le_to_cpu_16(resp->rule_id);
8906
8907         return status;
8908 }
8909
8910 /**
8911  * i40e_aq_del_mirror_rule
8912  * @hw: pointer to the hardware structure
8913  * @seid: VEB seid to add mirror rule to
8914  * @entries: Buffer which contains the entities to be mirrored
8915  * @count: number of entities contained in the buffer
8916  * @rule_id:the rule_id of the rule to be delete
8917  *
8918  * Delete a mirror rule for a given veb.
8919  *
8920  **/
8921 static enum i40e_status_code
8922 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
8923                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
8924                 uint16_t count, uint16_t rule_id)
8925 {
8926         struct i40e_aq_desc desc;
8927         struct i40e_aqc_add_delete_mirror_rule cmd;
8928         uint16_t buff_len = 0;
8929         enum i40e_status_code status;
8930         void *buff = NULL;
8931
8932         i40e_fill_default_direct_cmd_desc(&desc,
8933                                           i40e_aqc_opc_delete_mirror_rule);
8934         memset(&cmd, 0, sizeof(cmd));
8935         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
8936                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
8937                                                           I40E_AQ_FLAG_RD));
8938                 cmd.num_entries = count;
8939                 buff_len = sizeof(uint16_t) * count;
8940                 desc.datalen = rte_cpu_to_le_16(buff_len);
8941                 buff = (void *)entries;
8942         } else
8943                 /* rule id is filled in destination field for deleting mirror rule */
8944                 cmd.destination = rte_cpu_to_le_16(rule_id);
8945
8946         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
8947                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
8948         cmd.seid = rte_cpu_to_le_16(seid);
8949
8950         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
8951         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
8952
8953         return status;
8954 }
8955
8956 /**
8957  * i40e_mirror_rule_set
8958  * @dev: pointer to the hardware structure
8959  * @mirror_conf: mirror rule info
8960  * @sw_id: mirror rule's sw_id
8961  * @on: enable/disable
8962  *
8963  * set a mirror rule.
8964  *
8965  **/
8966 static int
8967 i40e_mirror_rule_set(struct rte_eth_dev *dev,
8968                         struct rte_eth_mirror_conf *mirror_conf,
8969                         uint8_t sw_id, uint8_t on)
8970 {
8971         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8972         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8973         struct i40e_mirror_rule *it, *mirr_rule = NULL;
8974         struct i40e_mirror_rule *parent = NULL;
8975         uint16_t seid, dst_seid, rule_id;
8976         uint16_t i, j = 0;
8977         int ret;
8978
8979         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
8980
8981         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
8982                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
8983                         " without veb or vfs.");
8984                 return -ENOSYS;
8985         }
8986         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
8987                 PMD_DRV_LOG(ERR, "mirror table is full.");
8988                 return -ENOSPC;
8989         }
8990         if (mirror_conf->dst_pool > pf->vf_num) {
8991                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
8992                                  mirror_conf->dst_pool);
8993                 return -EINVAL;
8994         }
8995
8996         seid = pf->main_vsi->veb->seid;
8997
8998         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
8999                 if (sw_id <= it->index) {
9000                         mirr_rule = it;
9001                         break;
9002                 }
9003                 parent = it;
9004         }
9005         if (mirr_rule && sw_id == mirr_rule->index) {
9006                 if (on) {
9007                         PMD_DRV_LOG(ERR, "mirror rule exists.");
9008                         return -EEXIST;
9009                 } else {
9010                         ret = i40e_aq_del_mirror_rule(hw, seid,
9011                                         mirr_rule->rule_type,
9012                                         mirr_rule->entries,
9013                                         mirr_rule->num_entries, mirr_rule->id);
9014                         if (ret < 0) {
9015                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
9016                                                    " ret = %d, aq_err = %d.",
9017                                                    ret, hw->aq.asq_last_status);
9018                                 return -ENOSYS;
9019                         }
9020                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9021                         rte_free(mirr_rule);
9022                         pf->nb_mirror_rule--;
9023                         return 0;
9024                 }
9025         } else if (!on) {
9026                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9027                 return -ENOENT;
9028         }
9029
9030         mirr_rule = rte_zmalloc("i40e_mirror_rule",
9031                                 sizeof(struct i40e_mirror_rule) , 0);
9032         if (!mirr_rule) {
9033                 PMD_DRV_LOG(ERR, "failed to allocate memory");
9034                 return I40E_ERR_NO_MEMORY;
9035         }
9036         switch (mirror_conf->rule_type) {
9037         case ETH_MIRROR_VLAN:
9038                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9039                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9040                                 mirr_rule->entries[j] =
9041                                         mirror_conf->vlan.vlan_id[i];
9042                                 j++;
9043                         }
9044                 }
9045                 if (j == 0) {
9046                         PMD_DRV_LOG(ERR, "vlan is not specified.");
9047                         rte_free(mirr_rule);
9048                         return -EINVAL;
9049                 }
9050                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9051                 break;
9052         case ETH_MIRROR_VIRTUAL_POOL_UP:
9053         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9054                 /* check if the specified pool bit is out of range */
9055                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9056                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
9057                         rte_free(mirr_rule);
9058                         return -EINVAL;
9059                 }
9060                 for (i = 0, j = 0; i < pf->vf_num; i++) {
9061                         if (mirror_conf->pool_mask & (1ULL << i)) {
9062                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9063                                 j++;
9064                         }
9065                 }
9066                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9067                         /* add pf vsi to entries */
9068                         mirr_rule->entries[j] = pf->main_vsi_seid;
9069                         j++;
9070                 }
9071                 if (j == 0) {
9072                         PMD_DRV_LOG(ERR, "pool is not specified.");
9073                         rte_free(mirr_rule);
9074                         return -EINVAL;
9075                 }
9076                 /* egress and ingress in aq commands means from switch but not port */
9077                 mirr_rule->rule_type =
9078                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9079                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9080                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9081                 break;
9082         case ETH_MIRROR_UPLINK_PORT:
9083                 /* egress and ingress in aq commands means from switch but not port*/
9084                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9085                 break;
9086         case ETH_MIRROR_DOWNLINK_PORT:
9087                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9088                 break;
9089         default:
9090                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9091                         mirror_conf->rule_type);
9092                 rte_free(mirr_rule);
9093                 return -EINVAL;
9094         }
9095
9096         /* If the dst_pool is equal to vf_num, consider it as PF */
9097         if (mirror_conf->dst_pool == pf->vf_num)
9098                 dst_seid = pf->main_vsi_seid;
9099         else
9100                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9101
9102         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9103                                       mirr_rule->rule_type, mirr_rule->entries,
9104                                       j, &rule_id);
9105         if (ret < 0) {
9106                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
9107                                    " ret = %d, aq_err = %d.",
9108                                    ret, hw->aq.asq_last_status);
9109                 rte_free(mirr_rule);
9110                 return -ENOSYS;
9111         }
9112
9113         mirr_rule->index = sw_id;
9114         mirr_rule->num_entries = j;
9115         mirr_rule->id = rule_id;
9116         mirr_rule->dst_vsi_seid = dst_seid;
9117
9118         if (parent)
9119                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9120         else
9121                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9122
9123         pf->nb_mirror_rule++;
9124         return 0;
9125 }
9126
9127 /**
9128  * i40e_mirror_rule_reset
9129  * @dev: pointer to the device
9130  * @sw_id: mirror rule's sw_id
9131  *
9132  * reset a mirror rule.
9133  *
9134  **/
9135 static int
9136 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9137 {
9138         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9139         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9140         struct i40e_mirror_rule *it, *mirr_rule = NULL;
9141         uint16_t seid;
9142         int ret;
9143
9144         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9145
9146         seid = pf->main_vsi->veb->seid;
9147
9148         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9149                 if (sw_id == it->index) {
9150                         mirr_rule = it;
9151                         break;
9152                 }
9153         }
9154         if (mirr_rule) {
9155                 ret = i40e_aq_del_mirror_rule(hw, seid,
9156                                 mirr_rule->rule_type,
9157                                 mirr_rule->entries,
9158                                 mirr_rule->num_entries, mirr_rule->id);
9159                 if (ret < 0) {
9160                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
9161                                            " status = %d, aq_err = %d.",
9162                                            ret, hw->aq.asq_last_status);
9163                         return -ENOSYS;
9164                 }
9165                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9166                 rte_free(mirr_rule);
9167                 pf->nb_mirror_rule--;
9168         } else {
9169                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9170                 return -ENOENT;
9171         }
9172         return 0;
9173 }
9174
9175 static uint64_t
9176 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9177 {
9178         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9179         uint64_t systim_cycles;
9180
9181         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9182         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9183                         << 32;
9184
9185         return systim_cycles;
9186 }
9187
9188 static uint64_t
9189 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9190 {
9191         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9192         uint64_t rx_tstamp;
9193
9194         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9195         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9196                         << 32;
9197
9198         return rx_tstamp;
9199 }
9200
9201 static uint64_t
9202 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9203 {
9204         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9205         uint64_t tx_tstamp;
9206
9207         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9208         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9209                         << 32;
9210
9211         return tx_tstamp;
9212 }
9213
9214 static void
9215 i40e_start_timecounters(struct rte_eth_dev *dev)
9216 {
9217         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9218         struct i40e_adapter *adapter =
9219                         (struct i40e_adapter *)dev->data->dev_private;
9220         struct rte_eth_link link;
9221         uint32_t tsync_inc_l;
9222         uint32_t tsync_inc_h;
9223
9224         /* Get current link speed. */
9225         memset(&link, 0, sizeof(link));
9226         i40e_dev_link_update(dev, 1);
9227         rte_i40e_dev_atomic_read_link_status(dev, &link);
9228
9229         switch (link.link_speed) {
9230         case ETH_SPEED_NUM_40G:
9231                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9232                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9233                 break;
9234         case ETH_SPEED_NUM_10G:
9235                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9236                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9237                 break;
9238         case ETH_SPEED_NUM_1G:
9239                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9240                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9241                 break;
9242         default:
9243                 tsync_inc_l = 0x0;
9244                 tsync_inc_h = 0x0;
9245         }
9246
9247         /* Set the timesync increment value. */
9248         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9249         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9250
9251         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9252         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9253         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9254
9255         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9256         adapter->systime_tc.cc_shift = 0;
9257         adapter->systime_tc.nsec_mask = 0;
9258
9259         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9260         adapter->rx_tstamp_tc.cc_shift = 0;
9261         adapter->rx_tstamp_tc.nsec_mask = 0;
9262
9263         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9264         adapter->tx_tstamp_tc.cc_shift = 0;
9265         adapter->tx_tstamp_tc.nsec_mask = 0;
9266 }
9267
9268 static int
9269 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9270 {
9271         struct i40e_adapter *adapter =
9272                         (struct i40e_adapter *)dev->data->dev_private;
9273
9274         adapter->systime_tc.nsec += delta;
9275         adapter->rx_tstamp_tc.nsec += delta;
9276         adapter->tx_tstamp_tc.nsec += delta;
9277
9278         return 0;
9279 }
9280
9281 static int
9282 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9283 {
9284         uint64_t ns;
9285         struct i40e_adapter *adapter =
9286                         (struct i40e_adapter *)dev->data->dev_private;
9287
9288         ns = rte_timespec_to_ns(ts);
9289
9290         /* Set the timecounters to a new value. */
9291         adapter->systime_tc.nsec = ns;
9292         adapter->rx_tstamp_tc.nsec = ns;
9293         adapter->tx_tstamp_tc.nsec = ns;
9294
9295         return 0;
9296 }
9297
9298 static int
9299 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9300 {
9301         uint64_t ns, systime_cycles;
9302         struct i40e_adapter *adapter =
9303                         (struct i40e_adapter *)dev->data->dev_private;
9304
9305         systime_cycles = i40e_read_systime_cyclecounter(dev);
9306         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9307         *ts = rte_ns_to_timespec(ns);
9308
9309         return 0;
9310 }
9311
9312 static int
9313 i40e_timesync_enable(struct rte_eth_dev *dev)
9314 {
9315         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9316         uint32_t tsync_ctl_l;
9317         uint32_t tsync_ctl_h;
9318
9319         /* Stop the timesync system time. */
9320         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9321         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9322         /* Reset the timesync system time value. */
9323         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9324         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9325
9326         i40e_start_timecounters(dev);
9327
9328         /* Clear timesync registers. */
9329         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9330         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9331         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9332         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9333         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9334         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9335
9336         /* Enable timestamping of PTP packets. */
9337         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9338         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9339
9340         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9341         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9342         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9343
9344         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9345         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9346
9347         return 0;
9348 }
9349
9350 static int
9351 i40e_timesync_disable(struct rte_eth_dev *dev)
9352 {
9353         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9354         uint32_t tsync_ctl_l;
9355         uint32_t tsync_ctl_h;
9356
9357         /* Disable timestamping of transmitted PTP packets. */
9358         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9359         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
9360
9361         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9362         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
9363
9364         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9365         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9366
9367         /* Reset the timesync increment value. */
9368         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9369         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9370
9371         return 0;
9372 }
9373
9374 static int
9375 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
9376                                 struct timespec *timestamp, uint32_t flags)
9377 {
9378         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9379         struct i40e_adapter *adapter =
9380                 (struct i40e_adapter *)dev->data->dev_private;
9381
9382         uint32_t sync_status;
9383         uint32_t index = flags & 0x03;
9384         uint64_t rx_tstamp_cycles;
9385         uint64_t ns;
9386
9387         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
9388         if ((sync_status & (1 << index)) == 0)
9389                 return -EINVAL;
9390
9391         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
9392         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
9393         *timestamp = rte_ns_to_timespec(ns);
9394
9395         return 0;
9396 }
9397
9398 static int
9399 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
9400                                 struct timespec *timestamp)
9401 {
9402         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9403         struct i40e_adapter *adapter =
9404                 (struct i40e_adapter *)dev->data->dev_private;
9405
9406         uint32_t sync_status;
9407         uint64_t tx_tstamp_cycles;
9408         uint64_t ns;
9409
9410         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9411         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
9412                 return -EINVAL;
9413
9414         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
9415         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
9416         *timestamp = rte_ns_to_timespec(ns);
9417
9418         return 0;
9419 }
9420
9421 /*
9422  * i40e_parse_dcb_configure - parse dcb configure from user
9423  * @dev: the device being configured
9424  * @dcb_cfg: pointer of the result of parse
9425  * @*tc_map: bit map of enabled traffic classes
9426  *
9427  * Returns 0 on success, negative value on failure
9428  */
9429 static int
9430 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
9431                          struct i40e_dcbx_config *dcb_cfg,
9432                          uint8_t *tc_map)
9433 {
9434         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
9435         uint8_t i, tc_bw, bw_lf;
9436
9437         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
9438
9439         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
9440         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
9441                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
9442                 return -EINVAL;
9443         }
9444
9445         /* assume each tc has the same bw */
9446         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
9447         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9448                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
9449         /* to ensure the sum of tcbw is equal to 100 */
9450         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
9451         for (i = 0; i < bw_lf; i++)
9452                 dcb_cfg->etscfg.tcbwtable[i]++;
9453
9454         /* assume each tc has the same Transmission Selection Algorithm */
9455         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
9456                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
9457
9458         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9459                 dcb_cfg->etscfg.prioritytable[i] =
9460                                 dcb_rx_conf->dcb_tc[i];
9461
9462         /* FW needs one App to configure HW */
9463         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
9464         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
9465         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
9466         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
9467
9468         if (dcb_rx_conf->nb_tcs == 0)
9469                 *tc_map = 1; /* tc0 only */
9470         else
9471                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
9472
9473         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
9474                 dcb_cfg->pfc.willing = 0;
9475                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
9476                 dcb_cfg->pfc.pfcenable = *tc_map;
9477         }
9478         return 0;
9479 }
9480
9481
9482 static enum i40e_status_code
9483 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
9484                               struct i40e_aqc_vsi_properties_data *info,
9485                               uint8_t enabled_tcmap)
9486 {
9487         enum i40e_status_code ret;
9488         int i, total_tc = 0;
9489         uint16_t qpnum_per_tc, bsf, qp_idx;
9490         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
9491         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
9492         uint16_t used_queues;
9493
9494         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
9495         if (ret != I40E_SUCCESS)
9496                 return ret;
9497
9498         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9499                 if (enabled_tcmap & (1 << i))
9500                         total_tc++;
9501         }
9502         if (total_tc == 0)
9503                 total_tc = 1;
9504         vsi->enabled_tc = enabled_tcmap;
9505
9506         /* different VSI has different queues assigned */
9507         if (vsi->type == I40E_VSI_MAIN)
9508                 used_queues = dev_data->nb_rx_queues -
9509                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9510         else if (vsi->type == I40E_VSI_VMDQ2)
9511                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
9512         else {
9513                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
9514                 return I40E_ERR_NO_AVAILABLE_VSI;
9515         }
9516
9517         qpnum_per_tc = used_queues / total_tc;
9518         /* Number of queues per enabled TC */
9519         if (qpnum_per_tc == 0) {
9520                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
9521                 return I40E_ERR_INVALID_QP_ID;
9522         }
9523         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
9524                                 I40E_MAX_Q_PER_TC);
9525         bsf = rte_bsf32(qpnum_per_tc);
9526
9527         /**
9528          * Configure TC and queue mapping parameters, for enabled TC,
9529          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
9530          * default queue will serve it.
9531          */
9532         qp_idx = 0;
9533         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9534                 if (vsi->enabled_tc & (1 << i)) {
9535                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
9536                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
9537                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
9538                         qp_idx += qpnum_per_tc;
9539                 } else
9540                         info->tc_mapping[i] = 0;
9541         }
9542
9543         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
9544         if (vsi->type == I40E_VSI_SRIOV) {
9545                 info->mapping_flags |=
9546                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
9547                 for (i = 0; i < vsi->nb_qps; i++)
9548                         info->queue_mapping[i] =
9549                                 rte_cpu_to_le_16(vsi->base_queue + i);
9550         } else {
9551                 info->mapping_flags |=
9552                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
9553                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
9554         }
9555         info->valid_sections |=
9556                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
9557
9558         return I40E_SUCCESS;
9559 }
9560
9561 /*
9562  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
9563  * @veb: VEB to be configured
9564  * @tc_map: enabled TC bitmap
9565  *
9566  * Returns 0 on success, negative value on failure
9567  */
9568 static enum i40e_status_code
9569 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
9570 {
9571         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
9572         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
9573         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
9574         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
9575         enum i40e_status_code ret = I40E_SUCCESS;
9576         int i;
9577         uint32_t bw_max;
9578
9579         /* Check if enabled_tc is same as existing or new TCs */
9580         if (veb->enabled_tc == tc_map)
9581                 return ret;
9582
9583         /* configure tc bandwidth */
9584         memset(&veb_bw, 0, sizeof(veb_bw));
9585         veb_bw.tc_valid_bits = tc_map;
9586         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9587         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9588                 if (tc_map & BIT_ULL(i))
9589                         veb_bw.tc_bw_share_credits[i] = 1;
9590         }
9591         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
9592                                                    &veb_bw, NULL);
9593         if (ret) {
9594                 PMD_INIT_LOG(ERR, "AQ command Config switch_comp BW allocation"
9595                                   " per TC failed = %d",
9596                                   hw->aq.asq_last_status);
9597                 return ret;
9598         }
9599
9600         memset(&ets_query, 0, sizeof(ets_query));
9601         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9602                                                    &ets_query, NULL);
9603         if (ret != I40E_SUCCESS) {
9604                 PMD_DRV_LOG(ERR, "Failed to get switch_comp ETS"
9605                                  " configuration %u", hw->aq.asq_last_status);
9606                 return ret;
9607         }
9608         memset(&bw_query, 0, sizeof(bw_query));
9609         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9610                                                   &bw_query, NULL);
9611         if (ret != I40E_SUCCESS) {
9612                 PMD_DRV_LOG(ERR, "Failed to get switch_comp bandwidth"
9613                                  " configuration %u", hw->aq.asq_last_status);
9614                 return ret;
9615         }
9616
9617         /* store and print out BW info */
9618         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
9619         veb->bw_info.bw_max = ets_query.tc_bw_max;
9620         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
9621         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
9622         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
9623                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
9624                      I40E_16_BIT_WIDTH);
9625         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9626                 veb->bw_info.bw_ets_share_credits[i] =
9627                                 bw_query.tc_bw_share_credits[i];
9628                 veb->bw_info.bw_ets_credits[i] =
9629                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
9630                 /* 4 bits per TC, 4th bit is reserved */
9631                 veb->bw_info.bw_ets_max[i] =
9632                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
9633                                   RTE_LEN2MASK(3, uint8_t));
9634                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
9635                             veb->bw_info.bw_ets_share_credits[i]);
9636                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
9637                             veb->bw_info.bw_ets_credits[i]);
9638                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
9639                             veb->bw_info.bw_ets_max[i]);
9640         }
9641
9642         veb->enabled_tc = tc_map;
9643
9644         return ret;
9645 }
9646
9647
9648 /*
9649  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
9650  * @vsi: VSI to be configured
9651  * @tc_map: enabled TC bitmap
9652  *
9653  * Returns 0 on success, negative value on failure
9654  */
9655 static enum i40e_status_code
9656 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
9657 {
9658         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
9659         struct i40e_vsi_context ctxt;
9660         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
9661         enum i40e_status_code ret = I40E_SUCCESS;
9662         int i;
9663
9664         /* Check if enabled_tc is same as existing or new TCs */
9665         if (vsi->enabled_tc == tc_map)
9666                 return ret;
9667
9668         /* configure tc bandwidth */
9669         memset(&bw_data, 0, sizeof(bw_data));
9670         bw_data.tc_valid_bits = tc_map;
9671         /* Enable ETS TCs with equal BW Share for now across all VSIs */
9672         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9673                 if (tc_map & BIT_ULL(i))
9674                         bw_data.tc_bw_credits[i] = 1;
9675         }
9676         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
9677         if (ret) {
9678                 PMD_INIT_LOG(ERR, "AQ command Config VSI BW allocation"
9679                         " per TC failed = %d",
9680                         hw->aq.asq_last_status);
9681                 goto out;
9682         }
9683         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
9684                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
9685
9686         /* Update Queue Pairs Mapping for currently enabled UPs */
9687         ctxt.seid = vsi->seid;
9688         ctxt.pf_num = hw->pf_id;
9689         ctxt.vf_num = 0;
9690         ctxt.uplink_seid = vsi->uplink_seid;
9691         ctxt.info = vsi->info;
9692         i40e_get_cap(hw);
9693         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
9694         if (ret)
9695                 goto out;
9696
9697         /* Update the VSI after updating the VSI queue-mapping information */
9698         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9699         if (ret) {
9700                 PMD_INIT_LOG(ERR, "Failed to configure "
9701                             "TC queue mapping = %d",
9702                             hw->aq.asq_last_status);
9703                 goto out;
9704         }
9705         /* update the local VSI info with updated queue map */
9706         (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
9707                                         sizeof(vsi->info.tc_mapping));
9708         (void)rte_memcpy(&vsi->info.queue_mapping,
9709                         &ctxt.info.queue_mapping,
9710                 sizeof(vsi->info.queue_mapping));
9711         vsi->info.mapping_flags = ctxt.info.mapping_flags;
9712         vsi->info.valid_sections = 0;
9713
9714         /* query and update current VSI BW information */
9715         ret = i40e_vsi_get_bw_config(vsi);
9716         if (ret) {
9717                 PMD_INIT_LOG(ERR,
9718                          "Failed updating vsi bw info, err %s aq_err %s",
9719                          i40e_stat_str(hw, ret),
9720                          i40e_aq_str(hw, hw->aq.asq_last_status));
9721                 goto out;
9722         }
9723
9724         vsi->enabled_tc = tc_map;
9725
9726 out:
9727         return ret;
9728 }
9729
9730 /*
9731  * i40e_dcb_hw_configure - program the dcb setting to hw
9732  * @pf: pf the configuration is taken on
9733  * @new_cfg: new configuration
9734  * @tc_map: enabled TC bitmap
9735  *
9736  * Returns 0 on success, negative value on failure
9737  */
9738 static enum i40e_status_code
9739 i40e_dcb_hw_configure(struct i40e_pf *pf,
9740                       struct i40e_dcbx_config *new_cfg,
9741                       uint8_t tc_map)
9742 {
9743         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9744         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
9745         struct i40e_vsi *main_vsi = pf->main_vsi;
9746         struct i40e_vsi_list *vsi_list;
9747         enum i40e_status_code ret;
9748         int i;
9749         uint32_t val;
9750
9751         /* Use the FW API if FW > v4.4*/
9752         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
9753               (hw->aq.fw_maj_ver >= 5))) {
9754                 PMD_INIT_LOG(ERR, "FW < v4.4, can not use FW LLDP API"
9755                                   " to configure DCB");
9756                 return I40E_ERR_FIRMWARE_API_VERSION;
9757         }
9758
9759         /* Check if need reconfiguration */
9760         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
9761                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
9762                 return I40E_SUCCESS;
9763         }
9764
9765         /* Copy the new config to the current config */
9766         *old_cfg = *new_cfg;
9767         old_cfg->etsrec = old_cfg->etscfg;
9768         ret = i40e_set_dcb_config(hw);
9769         if (ret) {
9770                 PMD_INIT_LOG(ERR,
9771                          "Set DCB Config failed, err %s aq_err %s\n",
9772                          i40e_stat_str(hw, ret),
9773                          i40e_aq_str(hw, hw->aq.asq_last_status));
9774                 return ret;
9775         }
9776         /* set receive Arbiter to RR mode and ETS scheme by default */
9777         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
9778                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
9779                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
9780                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
9781                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
9782                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
9783                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
9784                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
9785                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
9786                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
9787                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
9788                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
9789                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
9790         }
9791         /* get local mib to check whether it is configured correctly */
9792         /* IEEE mode */
9793         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
9794         /* Get Local DCB Config */
9795         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
9796                                      &hw->local_dcbx_config);
9797
9798         /* if Veb is created, need to update TC of it at first */
9799         if (main_vsi->veb) {
9800                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
9801                 if (ret)
9802                         PMD_INIT_LOG(WARNING,
9803                                  "Failed configuring TC for VEB seid=%d\n",
9804                                  main_vsi->veb->seid);
9805         }
9806         /* Update each VSI */
9807         i40e_vsi_config_tc(main_vsi, tc_map);
9808         if (main_vsi->veb) {
9809                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
9810                         /* Beside main VSI and VMDQ VSIs, only enable default
9811                          * TC for other VSIs
9812                          */
9813                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
9814                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9815                                                          tc_map);
9816                         else
9817                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
9818                                                          I40E_DEFAULT_TCMAP);
9819                         if (ret)
9820                                 PMD_INIT_LOG(WARNING,
9821                                          "Failed configuring TC for VSI seid=%d\n",
9822                                          vsi_list->vsi->seid);
9823                         /* continue */
9824                 }
9825         }
9826         return I40E_SUCCESS;
9827 }
9828
9829 /*
9830  * i40e_dcb_init_configure - initial dcb config
9831  * @dev: device being configured
9832  * @sw_dcb: indicate whether dcb is sw configured or hw offload
9833  *
9834  * Returns 0 on success, negative value on failure
9835  */
9836 static int
9837 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
9838 {
9839         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9840         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9841         int ret = 0;
9842
9843         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9844                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9845                 return -ENOTSUP;
9846         }
9847
9848         /* DCB initialization:
9849          * Update DCB configuration from the Firmware and configure
9850          * LLDP MIB change event.
9851          */
9852         if (sw_dcb == TRUE) {
9853                 ret = i40e_init_dcb(hw);
9854                 /* If lldp agent is stopped, the return value from
9855                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
9856                  * adminq status. Otherwise, it should return success.
9857                  */
9858                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
9859                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
9860                         memset(&hw->local_dcbx_config, 0,
9861                                 sizeof(struct i40e_dcbx_config));
9862                         /* set dcb default configuration */
9863                         hw->local_dcbx_config.etscfg.willing = 0;
9864                         hw->local_dcbx_config.etscfg.maxtcs = 0;
9865                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
9866                         hw->local_dcbx_config.etscfg.tsatable[0] =
9867                                                 I40E_IEEE_TSA_ETS;
9868                         hw->local_dcbx_config.etsrec =
9869                                 hw->local_dcbx_config.etscfg;
9870                         hw->local_dcbx_config.pfc.willing = 0;
9871                         hw->local_dcbx_config.pfc.pfccap =
9872                                                 I40E_MAX_TRAFFIC_CLASS;
9873                         /* FW needs one App to configure HW */
9874                         hw->local_dcbx_config.numapps = 1;
9875                         hw->local_dcbx_config.app[0].selector =
9876                                                 I40E_APP_SEL_ETHTYPE;
9877                         hw->local_dcbx_config.app[0].priority = 3;
9878                         hw->local_dcbx_config.app[0].protocolid =
9879                                                 I40E_APP_PROTOID_FCOE;
9880                         ret = i40e_set_dcb_config(hw);
9881                         if (ret) {
9882                                 PMD_INIT_LOG(ERR, "default dcb config fails."
9883                                         " err = %d, aq_err = %d.", ret,
9884                                           hw->aq.asq_last_status);
9885                                 return -ENOSYS;
9886                         }
9887                 } else {
9888                         PMD_INIT_LOG(ERR, "DCB initialization in FW fails,"
9889                                           " err = %d, aq_err = %d.", ret,
9890                                           hw->aq.asq_last_status);
9891                         return -ENOTSUP;
9892                 }
9893         } else {
9894                 ret = i40e_aq_start_lldp(hw, NULL);
9895                 if (ret != I40E_SUCCESS)
9896                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
9897
9898                 ret = i40e_init_dcb(hw);
9899                 if (!ret) {
9900                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
9901                                 PMD_INIT_LOG(ERR, "HW doesn't support"
9902                                                   " DCBX offload.");
9903                                 return -ENOTSUP;
9904                         }
9905                 } else {
9906                         PMD_INIT_LOG(ERR, "DCBX configuration failed, err = %d,"
9907                                           " aq_err = %d.", ret,
9908                                           hw->aq.asq_last_status);
9909                         return -ENOTSUP;
9910                 }
9911         }
9912         return 0;
9913 }
9914
9915 /*
9916  * i40e_dcb_setup - setup dcb related config
9917  * @dev: device being configured
9918  *
9919  * Returns 0 on success, negative value on failure
9920  */
9921 static int
9922 i40e_dcb_setup(struct rte_eth_dev *dev)
9923 {
9924         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9925         struct i40e_dcbx_config dcb_cfg;
9926         uint8_t tc_map = 0;
9927         int ret = 0;
9928
9929         if ((pf->flags & I40E_FLAG_DCB) == 0) {
9930                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
9931                 return -ENOTSUP;
9932         }
9933
9934         if (pf->vf_num != 0)
9935                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
9936
9937         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
9938         if (ret) {
9939                 PMD_INIT_LOG(ERR, "invalid dcb config");
9940                 return -EINVAL;
9941         }
9942         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
9943         if (ret) {
9944                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
9945                 return -ENOSYS;
9946         }
9947
9948         return 0;
9949 }
9950
9951 static int
9952 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
9953                       struct rte_eth_dcb_info *dcb_info)
9954 {
9955         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9956         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9957         struct i40e_vsi *vsi = pf->main_vsi;
9958         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
9959         uint16_t bsf, tc_mapping;
9960         int i, j = 0;
9961
9962         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
9963                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
9964         else
9965                 dcb_info->nb_tcs = 1;
9966         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
9967                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
9968         for (i = 0; i < dcb_info->nb_tcs; i++)
9969                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
9970
9971         /* get queue mapping if vmdq is disabled */
9972         if (!pf->nb_cfg_vmdq_vsi) {
9973                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9974                         if (!(vsi->enabled_tc & (1 << i)))
9975                                 continue;
9976                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9977                         dcb_info->tc_queue.tc_rxq[j][i].base =
9978                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
9979                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
9980                         dcb_info->tc_queue.tc_txq[j][i].base =
9981                                 dcb_info->tc_queue.tc_rxq[j][i].base;
9982                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
9983                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
9984                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
9985                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
9986                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
9987                 }
9988                 return 0;
9989         }
9990
9991         /* get queue mapping if vmdq is enabled */
9992         do {
9993                 vsi = pf->vmdq[j].vsi;
9994                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9995                         if (!(vsi->enabled_tc & (1 << i)))
9996                                 continue;
9997                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
9998                         dcb_info->tc_queue.tc_rxq[j][i].base =
9999                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10000                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10001                         dcb_info->tc_queue.tc_txq[j][i].base =
10002                                 dcb_info->tc_queue.tc_rxq[j][i].base;
10003                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10004                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10005                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10006                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10007                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10008                 }
10009                 j++;
10010         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10011         return 0;
10012 }
10013
10014 static int
10015 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10016 {
10017         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10018         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10019         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10020         uint16_t interval =
10021                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10022         uint16_t msix_intr;
10023
10024         msix_intr = intr_handle->intr_vec[queue_id];
10025         if (msix_intr == I40E_MISC_VEC_ID)
10026                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10027                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10028                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10029                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10030                                (interval <<
10031                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10032         else
10033                 I40E_WRITE_REG(hw,
10034                                I40E_PFINT_DYN_CTLN(msix_intr -
10035                                                    I40E_RX_VEC_START),
10036                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
10037                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10038                                (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10039                                (interval <<
10040                                 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10041
10042         I40E_WRITE_FLUSH(hw);
10043         rte_intr_enable(&pci_dev->intr_handle);
10044
10045         return 0;
10046 }
10047
10048 static int
10049 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10050 {
10051         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
10052         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10053         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10054         uint16_t msix_intr;
10055
10056         msix_intr = intr_handle->intr_vec[queue_id];
10057         if (msix_intr == I40E_MISC_VEC_ID)
10058                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10059         else
10060                 I40E_WRITE_REG(hw,
10061                                I40E_PFINT_DYN_CTLN(msix_intr -
10062                                                    I40E_RX_VEC_START),
10063                                0);
10064         I40E_WRITE_FLUSH(hw);
10065
10066         return 0;
10067 }
10068
10069 static int i40e_get_regs(struct rte_eth_dev *dev,
10070                          struct rte_dev_reg_info *regs)
10071 {
10072         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10073         uint32_t *ptr_data = regs->data;
10074         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10075         const struct i40e_reg_info *reg_info;
10076
10077         if (ptr_data == NULL) {
10078                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10079                 regs->width = sizeof(uint32_t);
10080                 return 0;
10081         }
10082
10083         /* The first few registers have to be read using AQ operations */
10084         reg_idx = 0;
10085         while (i40e_regs_adminq[reg_idx].name) {
10086                 reg_info = &i40e_regs_adminq[reg_idx++];
10087                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10088                         for (arr_idx2 = 0;
10089                                         arr_idx2 <= reg_info->count2;
10090                                         arr_idx2++) {
10091                                 reg_offset = arr_idx * reg_info->stride1 +
10092                                         arr_idx2 * reg_info->stride2;
10093                                 reg_offset += reg_info->base_addr;
10094                                 ptr_data[reg_offset >> 2] =
10095                                         i40e_read_rx_ctl(hw, reg_offset);
10096                         }
10097         }
10098
10099         /* The remaining registers can be read using primitives */
10100         reg_idx = 0;
10101         while (i40e_regs_others[reg_idx].name) {
10102                 reg_info = &i40e_regs_others[reg_idx++];
10103                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10104                         for (arr_idx2 = 0;
10105                                         arr_idx2 <= reg_info->count2;
10106                                         arr_idx2++) {
10107                                 reg_offset = arr_idx * reg_info->stride1 +
10108                                         arr_idx2 * reg_info->stride2;
10109                                 reg_offset += reg_info->base_addr;
10110                                 ptr_data[reg_offset >> 2] =
10111                                         I40E_READ_REG(hw, reg_offset);
10112                         }
10113         }
10114
10115         return 0;
10116 }
10117
10118 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10119 {
10120         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10121
10122         /* Convert word count to byte count */
10123         return hw->nvm.sr_size << 1;
10124 }
10125
10126 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10127                            struct rte_dev_eeprom_info *eeprom)
10128 {
10129         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10130         uint16_t *data = eeprom->data;
10131         uint16_t offset, length, cnt_words;
10132         int ret_code;
10133
10134         offset = eeprom->offset >> 1;
10135         length = eeprom->length >> 1;
10136         cnt_words = length;
10137
10138         if (offset > hw->nvm.sr_size ||
10139                 offset + length > hw->nvm.sr_size) {
10140                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10141                 return -EINVAL;
10142         }
10143
10144         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10145
10146         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10147         if (ret_code != I40E_SUCCESS || cnt_words != length) {
10148                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10149                 return -EIO;
10150         }
10151
10152         return 0;
10153 }
10154
10155 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10156                                       struct ether_addr *mac_addr)
10157 {
10158         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10159
10160         if (!is_valid_assigned_ether_addr(mac_addr)) {
10161                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10162                 return;
10163         }
10164
10165         /* Flags: 0x3 updates port address */
10166         i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10167 }
10168
10169 static int
10170 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10171 {
10172         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10173         struct rte_eth_dev_data *dev_data = pf->dev_data;
10174         uint32_t frame_size = mtu + ETHER_HDR_LEN
10175                               + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
10176         int ret = 0;
10177
10178         /* check if mtu is within the allowed range */
10179         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10180                 return -EINVAL;
10181
10182         /* mtu setting is forbidden if port is start */
10183         if (dev_data->dev_started) {
10184                 PMD_DRV_LOG(ERR,
10185                             "port %d must be stopped before configuration\n",
10186                             dev_data->port_id);
10187                 return -EBUSY;
10188         }
10189
10190         if (frame_size > ETHER_MAX_LEN)
10191                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10192         else
10193                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10194
10195         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10196
10197         return ret;
10198 }
10199
10200 /* Restore ethertype filter */
10201 static void
10202 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10203 {
10204         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10205         struct i40e_ethertype_filter_list
10206                 *ethertype_list = &pf->ethertype.ethertype_list;
10207         struct i40e_ethertype_filter *f;
10208         struct i40e_control_filter_stats stats;
10209         uint16_t flags;
10210
10211         TAILQ_FOREACH(f, ethertype_list, rules) {
10212                 flags = 0;
10213                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10214                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10215                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10216                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10217                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10218
10219                 memset(&stats, 0, sizeof(stats));
10220                 i40e_aq_add_rem_control_packet_filter(hw,
10221                                             f->input.mac_addr.addr_bytes,
10222                                             f->input.ether_type,
10223                                             flags, pf->main_vsi->seid,
10224                                             f->queue, 1, &stats, NULL);
10225         }
10226         PMD_DRV_LOG(INFO, "Ethertype filter:"
10227                     " mac_etype_used = %u, etype_used = %u,"
10228                     " mac_etype_free = %u, etype_free = %u\n",
10229                     stats.mac_etype_used, stats.etype_used,
10230                     stats.mac_etype_free, stats.etype_free);
10231 }
10232
10233 /* Restore tunnel filter */
10234 static void
10235 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10236 {
10237         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10238         struct i40e_vsi *vsi = pf->main_vsi;
10239         struct i40e_tunnel_filter_list
10240                 *tunnel_list = &pf->tunnel.tunnel_list;
10241         struct i40e_tunnel_filter *f;
10242         struct i40e_aqc_add_remove_cloud_filters_element_data cld_filter;
10243
10244         TAILQ_FOREACH(f, tunnel_list, rules) {
10245                 memset(&cld_filter, 0, sizeof(cld_filter));
10246                 rte_memcpy(&cld_filter, &f->input, sizeof(f->input));
10247                 cld_filter.queue_number = f->queue;
10248                 i40e_aq_add_cloud_filters(hw, vsi->seid, &cld_filter, 1);
10249         }
10250 }
10251
10252 static void
10253 i40e_filter_restore(struct i40e_pf *pf)
10254 {
10255         i40e_ethertype_filter_restore(pf);
10256         i40e_tunnel_filter_restore(pf);
10257         i40e_fdir_filter_restore(pf);
10258 }