1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
15 #include <rte_string_fns.h>
17 #include <rte_bus_pci.h>
18 #include <rte_ether.h>
19 #include <rte_ethdev_driver.h>
20 #include <rte_ethdev_pci.h>
21 #include <rte_memzone.h>
22 #include <rte_malloc.h>
23 #include <rte_memcpy.h>
24 #include <rte_alarm.h>
26 #include <rte_eth_ctrl.h>
27 #include <rte_tailq.h>
28 #include <rte_hash_crc.h>
30 #include "i40e_logs.h"
31 #include "base/i40e_prototype.h"
32 #include "base/i40e_adminq_cmd.h"
33 #include "base/i40e_type.h"
34 #include "base/i40e_register.h"
35 #include "base/i40e_dcb.h"
36 #include "base/i40e_diag.h"
37 #include "i40e_ethdev.h"
38 #include "i40e_rxtx.h"
40 #include "i40e_regs.h"
41 #include "rte_pmd_i40e.h"
43 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
44 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
46 #define I40E_CLEAR_PXE_WAIT_MS 200
48 /* Maximun number of capability elements */
49 #define I40E_MAX_CAP_ELE_NUM 128
51 /* Wait count and interval */
52 #define I40E_CHK_Q_ENA_COUNT 1000
53 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
55 /* Maximun number of VSI */
56 #define I40E_MAX_NUM_VSIS (384UL)
58 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
60 /* Flow control default timer */
61 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
63 /* Flow control enable fwd bit */
64 #define I40E_PRTMAC_FWD_CTRL 0x00000001
66 /* Receive Packet Buffer size */
67 #define I40E_RXPBSIZE (968 * 1024)
70 #define I40E_KILOSHIFT 10
72 /* Flow control default high water */
73 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
75 /* Flow control default low water */
76 #define I40E_DEFAULT_LOW_WATER (0xF2000 >> I40E_KILOSHIFT)
78 /* Receive Average Packet Size in Byte*/
79 #define I40E_PACKET_AVERAGE_SIZE 128
81 /* Mask of PF interrupt causes */
82 #define I40E_PFINT_ICR0_ENA_MASK ( \
83 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
84 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
85 I40E_PFINT_ICR0_ENA_GRST_MASK | \
86 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
87 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
88 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
89 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
90 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
91 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
93 #define I40E_FLOW_TYPES ( \
94 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
95 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
96 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
97 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
98 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
99 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
100 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
101 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
102 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
103 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
104 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
106 /* Additional timesync values. */
107 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
108 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
109 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
110 #define I40E_PRTTSYN_TSYNENA 0x80000000
111 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
112 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
115 * Below are values for writing un-exposed registers suggested
118 /* Destination MAC address */
119 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
120 /* Source MAC address */
121 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
122 /* Outer (S-Tag) VLAN tag in the outer L2 header */
123 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
124 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
125 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
126 /* Single VLAN tag in the inner L2 header */
127 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
128 /* Source IPv4 address */
129 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
130 /* Destination IPv4 address */
131 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
132 /* Source IPv4 address for X722 */
133 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
134 /* Destination IPv4 address for X722 */
135 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
136 /* IPv4 Protocol for X722 */
137 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
138 /* IPv4 Time to Live for X722 */
139 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
140 /* IPv4 Type of Service (TOS) */
141 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
143 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
144 /* IPv4 Time to Live */
145 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
146 /* Source IPv6 address */
147 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
148 /* Destination IPv6 address */
149 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
150 /* IPv6 Traffic Class (TC) */
151 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
152 /* IPv6 Next Header */
153 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
155 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
157 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
158 /* Destination L4 port */
159 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
160 /* SCTP verification tag */
161 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
162 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
163 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
164 /* Source port of tunneling UDP */
165 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
166 /* Destination port of tunneling UDP */
167 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
168 /* UDP Tunneling ID, NVGRE/GRE key */
169 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
170 /* Last ether type */
171 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
172 /* Tunneling outer destination IPv4 address */
173 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
174 /* Tunneling outer destination IPv6 address */
175 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
176 /* 1st word of flex payload */
177 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
178 /* 2nd word of flex payload */
179 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
180 /* 3rd word of flex payload */
181 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
182 /* 4th word of flex payload */
183 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
184 /* 5th word of flex payload */
185 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
186 /* 6th word of flex payload */
187 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
188 /* 7th word of flex payload */
189 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
190 /* 8th word of flex payload */
191 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
192 /* all 8 words flex payload */
193 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
194 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
196 #define I40E_TRANSLATE_INSET 0
197 #define I40E_TRANSLATE_REG 1
199 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
200 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
201 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
202 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
203 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
204 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
206 /* PCI offset for querying capability */
207 #define PCI_DEV_CAP_REG 0xA4
208 /* PCI offset for enabling/disabling Extended Tag */
209 #define PCI_DEV_CTRL_REG 0xA8
210 /* Bit mask of Extended Tag capability */
211 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
212 /* Bit shift of Extended Tag enable/disable */
213 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
214 /* Bit mask of Extended Tag enable/disable */
215 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
217 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
218 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
219 static int i40e_dev_configure(struct rte_eth_dev *dev);
220 static int i40e_dev_start(struct rte_eth_dev *dev);
221 static void i40e_dev_stop(struct rte_eth_dev *dev);
222 static void i40e_dev_close(struct rte_eth_dev *dev);
223 static int i40e_dev_reset(struct rte_eth_dev *dev);
224 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
225 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
226 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
227 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
228 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
229 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
230 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
231 struct rte_eth_stats *stats);
232 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
233 struct rte_eth_xstat *xstats, unsigned n);
234 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
235 struct rte_eth_xstat_name *xstats_names,
237 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
238 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
242 static int i40e_fw_version_get(struct rte_eth_dev *dev,
243 char *fw_version, size_t fw_size);
244 static void i40e_dev_info_get(struct rte_eth_dev *dev,
245 struct rte_eth_dev_info *dev_info);
246 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
249 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
250 enum rte_vlan_type vlan_type,
252 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
253 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
256 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
257 static int i40e_dev_led_on(struct rte_eth_dev *dev);
258 static int i40e_dev_led_off(struct rte_eth_dev *dev);
259 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
260 struct rte_eth_fc_conf *fc_conf);
261 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
262 struct rte_eth_fc_conf *fc_conf);
263 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
264 struct rte_eth_pfc_conf *pfc_conf);
265 static int i40e_macaddr_add(struct rte_eth_dev *dev,
266 struct ether_addr *mac_addr,
269 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
270 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
271 struct rte_eth_rss_reta_entry64 *reta_conf,
273 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
274 struct rte_eth_rss_reta_entry64 *reta_conf,
277 static int i40e_get_cap(struct i40e_hw *hw);
278 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
279 static int i40e_pf_setup(struct i40e_pf *pf);
280 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
281 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
282 static int i40e_dcb_setup(struct rte_eth_dev *dev);
283 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
284 bool offset_loaded, uint64_t *offset, uint64_t *stat);
285 static void i40e_stat_update_48(struct i40e_hw *hw,
291 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
292 static void i40e_dev_interrupt_handler(void *param);
293 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
294 uint32_t base, uint32_t num);
295 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
296 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
298 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
300 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
301 static int i40e_veb_release(struct i40e_veb *veb);
302 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
303 struct i40e_vsi *vsi);
304 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
305 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
306 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
307 struct i40e_macvlan_filter *mv_f,
310 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
311 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
312 struct rte_eth_rss_conf *rss_conf);
313 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
314 struct rte_eth_rss_conf *rss_conf);
315 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
316 struct rte_eth_udp_tunnel *udp_tunnel);
317 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
318 struct rte_eth_udp_tunnel *udp_tunnel);
319 static void i40e_filter_input_set_init(struct i40e_pf *pf);
320 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
321 enum rte_filter_op filter_op,
323 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
324 enum rte_filter_type filter_type,
325 enum rte_filter_op filter_op,
327 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
328 struct rte_eth_dcb_info *dcb_info);
329 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
330 static void i40e_configure_registers(struct i40e_hw *hw);
331 static void i40e_hw_init(struct rte_eth_dev *dev);
332 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
333 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
339 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
340 struct rte_eth_mirror_conf *mirror_conf,
341 uint8_t sw_id, uint8_t on);
342 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
344 static int i40e_timesync_enable(struct rte_eth_dev *dev);
345 static int i40e_timesync_disable(struct rte_eth_dev *dev);
346 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
347 struct timespec *timestamp,
349 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
350 struct timespec *timestamp);
351 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
353 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
355 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
356 struct timespec *timestamp);
357 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
358 const struct timespec *timestamp);
360 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
362 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
365 static int i40e_get_regs(struct rte_eth_dev *dev,
366 struct rte_dev_reg_info *regs);
368 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
370 static int i40e_get_eeprom(struct rte_eth_dev *dev,
371 struct rte_dev_eeprom_info *eeprom);
373 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
374 struct ether_addr *mac_addr);
376 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
378 static int i40e_ethertype_filter_convert(
379 const struct rte_eth_ethertype_filter *input,
380 struct i40e_ethertype_filter *filter);
381 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
382 struct i40e_ethertype_filter *filter);
384 static int i40e_tunnel_filter_convert(
385 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
386 struct i40e_tunnel_filter *tunnel_filter);
387 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
388 struct i40e_tunnel_filter *tunnel_filter);
389 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
391 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
392 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
393 static void i40e_filter_restore(struct i40e_pf *pf);
394 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
396 int i40e_logtype_init;
397 int i40e_logtype_driver;
399 static const struct rte_pci_id pci_id_i40e_map[] = {
400 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
401 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
402 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
403 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
404 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
405 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
406 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
407 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
408 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
409 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
410 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
411 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
412 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
413 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
414 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
415 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
416 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
417 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
418 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
419 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
420 { .vendor_id = 0, /* sentinel */ },
423 static const struct eth_dev_ops i40e_eth_dev_ops = {
424 .dev_configure = i40e_dev_configure,
425 .dev_start = i40e_dev_start,
426 .dev_stop = i40e_dev_stop,
427 .dev_close = i40e_dev_close,
428 .dev_reset = i40e_dev_reset,
429 .promiscuous_enable = i40e_dev_promiscuous_enable,
430 .promiscuous_disable = i40e_dev_promiscuous_disable,
431 .allmulticast_enable = i40e_dev_allmulticast_enable,
432 .allmulticast_disable = i40e_dev_allmulticast_disable,
433 .dev_set_link_up = i40e_dev_set_link_up,
434 .dev_set_link_down = i40e_dev_set_link_down,
435 .link_update = i40e_dev_link_update,
436 .stats_get = i40e_dev_stats_get,
437 .xstats_get = i40e_dev_xstats_get,
438 .xstats_get_names = i40e_dev_xstats_get_names,
439 .stats_reset = i40e_dev_stats_reset,
440 .xstats_reset = i40e_dev_stats_reset,
441 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
442 .fw_version_get = i40e_fw_version_get,
443 .dev_infos_get = i40e_dev_info_get,
444 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
445 .vlan_filter_set = i40e_vlan_filter_set,
446 .vlan_tpid_set = i40e_vlan_tpid_set,
447 .vlan_offload_set = i40e_vlan_offload_set,
448 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
449 .vlan_pvid_set = i40e_vlan_pvid_set,
450 .rx_queue_start = i40e_dev_rx_queue_start,
451 .rx_queue_stop = i40e_dev_rx_queue_stop,
452 .tx_queue_start = i40e_dev_tx_queue_start,
453 .tx_queue_stop = i40e_dev_tx_queue_stop,
454 .rx_queue_setup = i40e_dev_rx_queue_setup,
455 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
456 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
457 .rx_queue_release = i40e_dev_rx_queue_release,
458 .rx_queue_count = i40e_dev_rx_queue_count,
459 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
460 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
461 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
462 .tx_queue_setup = i40e_dev_tx_queue_setup,
463 .tx_queue_release = i40e_dev_tx_queue_release,
464 .dev_led_on = i40e_dev_led_on,
465 .dev_led_off = i40e_dev_led_off,
466 .flow_ctrl_get = i40e_flow_ctrl_get,
467 .flow_ctrl_set = i40e_flow_ctrl_set,
468 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
469 .mac_addr_add = i40e_macaddr_add,
470 .mac_addr_remove = i40e_macaddr_remove,
471 .reta_update = i40e_dev_rss_reta_update,
472 .reta_query = i40e_dev_rss_reta_query,
473 .rss_hash_update = i40e_dev_rss_hash_update,
474 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
475 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
476 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
477 .filter_ctrl = i40e_dev_filter_ctrl,
478 .rxq_info_get = i40e_rxq_info_get,
479 .txq_info_get = i40e_txq_info_get,
480 .mirror_rule_set = i40e_mirror_rule_set,
481 .mirror_rule_reset = i40e_mirror_rule_reset,
482 .timesync_enable = i40e_timesync_enable,
483 .timesync_disable = i40e_timesync_disable,
484 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
485 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
486 .get_dcb_info = i40e_dev_get_dcb_info,
487 .timesync_adjust_time = i40e_timesync_adjust_time,
488 .timesync_read_time = i40e_timesync_read_time,
489 .timesync_write_time = i40e_timesync_write_time,
490 .get_reg = i40e_get_regs,
491 .get_eeprom_length = i40e_get_eeprom_length,
492 .get_eeprom = i40e_get_eeprom,
493 .mac_addr_set = i40e_set_default_mac_addr,
494 .mtu_set = i40e_dev_mtu_set,
495 .tm_ops_get = i40e_tm_ops_get,
498 /* store statistics names and its offset in stats structure */
499 struct rte_i40e_xstats_name_off {
500 char name[RTE_ETH_XSTATS_NAME_SIZE];
504 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
505 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
506 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
507 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
508 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
509 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
510 rx_unknown_protocol)},
511 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
512 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
513 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
514 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
517 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
518 sizeof(rte_i40e_stats_strings[0]))
520 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
521 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
522 tx_dropped_link_down)},
523 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
524 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
526 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
527 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
529 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
531 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
533 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
534 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
535 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
536 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
537 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
538 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
540 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
542 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
544 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
546 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
548 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
550 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
552 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
554 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
555 mac_short_packet_dropped)},
556 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
558 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
559 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
560 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
562 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
564 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
566 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
568 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
570 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
572 {"rx_flow_director_atr_match_packets",
573 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
574 {"rx_flow_director_sb_match_packets",
575 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
576 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
578 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
580 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
582 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
586 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
587 sizeof(rte_i40e_hw_port_strings[0]))
589 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
590 {"xon_packets", offsetof(struct i40e_hw_port_stats,
592 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
596 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
597 sizeof(rte_i40e_rxq_prio_strings[0]))
599 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
600 {"xon_packets", offsetof(struct i40e_hw_port_stats,
602 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
604 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
605 priority_xon_2_xoff)},
608 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
609 sizeof(rte_i40e_txq_prio_strings[0]))
611 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
612 struct rte_pci_device *pci_dev)
614 return rte_eth_dev_pci_generic_probe(pci_dev,
615 sizeof(struct i40e_adapter), eth_i40e_dev_init);
618 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
620 return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
623 static struct rte_pci_driver rte_i40e_pmd = {
624 .id_table = pci_id_i40e_map,
625 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
626 RTE_PCI_DRV_IOVA_AS_VA,
627 .probe = eth_i40e_pci_probe,
628 .remove = eth_i40e_pci_remove,
632 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
633 struct rte_eth_link *link)
635 struct rte_eth_link *dst = link;
636 struct rte_eth_link *src = &(dev->data->dev_link);
638 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
639 *(uint64_t *)src) == 0)
646 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
647 struct rte_eth_link *link)
649 struct rte_eth_link *dst = &(dev->data->dev_link);
650 struct rte_eth_link *src = link;
652 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
653 *(uint64_t *)src) == 0)
659 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
660 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
661 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
663 #ifndef I40E_GLQF_ORT
664 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
666 #ifndef I40E_GLQF_PIT
667 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
669 #ifndef I40E_GLQF_L3_MAP
670 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
673 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
676 * Initialize registers for parsing packet type of QinQ
677 * This should be removed from code once proper
678 * configuration API is added to avoid configuration conflicts
679 * between ports of the same device.
681 I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
682 I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
683 i40e_global_cfg_warning(I40E_WARNING_QINQ_PARSER);
686 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
689 * Add a ethertype filter to drop all flow control frames transmitted
693 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
695 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
696 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
697 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
698 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
701 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
702 I40E_FLOW_CONTROL_ETHERTYPE, flags,
703 pf->main_vsi_seid, 0,
707 "Failed to add filter to drop flow control frames from VSIs.");
711 floating_veb_list_handler(__rte_unused const char *key,
712 const char *floating_veb_value,
716 unsigned int count = 0;
719 bool *vf_floating_veb = opaque;
721 while (isblank(*floating_veb_value))
722 floating_veb_value++;
724 /* Reset floating VEB configuration for VFs */
725 for (idx = 0; idx < I40E_MAX_VF; idx++)
726 vf_floating_veb[idx] = false;
730 while (isblank(*floating_veb_value))
731 floating_veb_value++;
732 if (*floating_veb_value == '\0')
735 idx = strtoul(floating_veb_value, &end, 10);
736 if (errno || end == NULL)
738 while (isblank(*end))
742 } else if ((*end == ';') || (*end == '\0')) {
744 if (min == I40E_MAX_VF)
746 if (max >= I40E_MAX_VF)
747 max = I40E_MAX_VF - 1;
748 for (idx = min; idx <= max; idx++) {
749 vf_floating_veb[idx] = true;
756 floating_veb_value = end + 1;
757 } while (*end != '\0');
766 config_vf_floating_veb(struct rte_devargs *devargs,
767 uint16_t floating_veb,
768 bool *vf_floating_veb)
770 struct rte_kvargs *kvlist;
772 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
776 /* All the VFs attach to the floating VEB by default
777 * when the floating VEB is enabled.
779 for (i = 0; i < I40E_MAX_VF; i++)
780 vf_floating_veb[i] = true;
785 kvlist = rte_kvargs_parse(devargs->args, NULL);
789 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
790 rte_kvargs_free(kvlist);
793 /* When the floating_veb_list parameter exists, all the VFs
794 * will attach to the legacy VEB firstly, then configure VFs
795 * to the floating VEB according to the floating_veb_list.
797 if (rte_kvargs_process(kvlist, floating_veb_list,
798 floating_veb_list_handler,
799 vf_floating_veb) < 0) {
800 rte_kvargs_free(kvlist);
803 rte_kvargs_free(kvlist);
807 i40e_check_floating_handler(__rte_unused const char *key,
809 __rte_unused void *opaque)
811 if (strcmp(value, "1"))
818 is_floating_veb_supported(struct rte_devargs *devargs)
820 struct rte_kvargs *kvlist;
821 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
826 kvlist = rte_kvargs_parse(devargs->args, NULL);
830 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
831 rte_kvargs_free(kvlist);
834 /* Floating VEB is enabled when there's key-value:
835 * enable_floating_veb=1
837 if (rte_kvargs_process(kvlist, floating_veb_key,
838 i40e_check_floating_handler, NULL) < 0) {
839 rte_kvargs_free(kvlist);
842 rte_kvargs_free(kvlist);
848 config_floating_veb(struct rte_eth_dev *dev)
850 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
851 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
852 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
854 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
856 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
858 is_floating_veb_supported(pci_dev->device.devargs);
859 config_vf_floating_veb(pci_dev->device.devargs,
861 pf->floating_veb_list);
863 pf->floating_veb = false;
867 #define I40E_L2_TAGS_S_TAG_SHIFT 1
868 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
871 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
873 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
874 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
875 char ethertype_hash_name[RTE_HASH_NAMESIZE];
878 struct rte_hash_parameters ethertype_hash_params = {
879 .name = ethertype_hash_name,
880 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
881 .key_len = sizeof(struct i40e_ethertype_filter_input),
882 .hash_func = rte_hash_crc,
883 .hash_func_init_val = 0,
884 .socket_id = rte_socket_id(),
887 /* Initialize ethertype filter rule list and hash */
888 TAILQ_INIT(ðertype_rule->ethertype_list);
889 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
890 "ethertype_%s", dev->device->name);
891 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
892 if (!ethertype_rule->hash_table) {
893 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
896 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
897 sizeof(struct i40e_ethertype_filter *) *
898 I40E_MAX_ETHERTYPE_FILTER_NUM,
900 if (!ethertype_rule->hash_map) {
902 "Failed to allocate memory for ethertype hash map!");
904 goto err_ethertype_hash_map_alloc;
909 err_ethertype_hash_map_alloc:
910 rte_hash_free(ethertype_rule->hash_table);
916 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
918 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
919 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
920 char tunnel_hash_name[RTE_HASH_NAMESIZE];
923 struct rte_hash_parameters tunnel_hash_params = {
924 .name = tunnel_hash_name,
925 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
926 .key_len = sizeof(struct i40e_tunnel_filter_input),
927 .hash_func = rte_hash_crc,
928 .hash_func_init_val = 0,
929 .socket_id = rte_socket_id(),
932 /* Initialize tunnel filter rule list and hash */
933 TAILQ_INIT(&tunnel_rule->tunnel_list);
934 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
935 "tunnel_%s", dev->device->name);
936 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
937 if (!tunnel_rule->hash_table) {
938 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
941 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
942 sizeof(struct i40e_tunnel_filter *) *
943 I40E_MAX_TUNNEL_FILTER_NUM,
945 if (!tunnel_rule->hash_map) {
947 "Failed to allocate memory for tunnel hash map!");
949 goto err_tunnel_hash_map_alloc;
954 err_tunnel_hash_map_alloc:
955 rte_hash_free(tunnel_rule->hash_table);
961 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
963 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
964 struct i40e_fdir_info *fdir_info = &pf->fdir;
965 char fdir_hash_name[RTE_HASH_NAMESIZE];
968 struct rte_hash_parameters fdir_hash_params = {
969 .name = fdir_hash_name,
970 .entries = I40E_MAX_FDIR_FILTER_NUM,
971 .key_len = sizeof(struct i40e_fdir_input),
972 .hash_func = rte_hash_crc,
973 .hash_func_init_val = 0,
974 .socket_id = rte_socket_id(),
977 /* Initialize flow director filter rule list and hash */
978 TAILQ_INIT(&fdir_info->fdir_list);
979 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
980 "fdir_%s", dev->device->name);
981 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
982 if (!fdir_info->hash_table) {
983 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
986 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
987 sizeof(struct i40e_fdir_filter *) *
988 I40E_MAX_FDIR_FILTER_NUM,
990 if (!fdir_info->hash_map) {
992 "Failed to allocate memory for fdir hash map!");
994 goto err_fdir_hash_map_alloc;
998 err_fdir_hash_map_alloc:
999 rte_hash_free(fdir_info->hash_table);
1005 i40e_init_customized_info(struct i40e_pf *pf)
1009 /* Initialize customized pctype */
1010 for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1011 pf->customized_pctype[i].index = i;
1012 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1013 pf->customized_pctype[i].valid = false;
1016 pf->gtp_support = false;
1020 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1022 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1023 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1024 struct i40e_queue_regions *info = &pf->queue_region;
1027 for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1028 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1030 memset(info, 0, sizeof(struct i40e_queue_regions));
1034 eth_i40e_dev_init(struct rte_eth_dev *dev)
1036 struct rte_pci_device *pci_dev;
1037 struct rte_intr_handle *intr_handle;
1038 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1039 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1040 struct i40e_vsi *vsi;
1043 uint8_t aq_fail = 0;
1045 PMD_INIT_FUNC_TRACE();
1047 dev->dev_ops = &i40e_eth_dev_ops;
1048 dev->rx_pkt_burst = i40e_recv_pkts;
1049 dev->tx_pkt_burst = i40e_xmit_pkts;
1050 dev->tx_pkt_prepare = i40e_prep_pkts;
1052 /* for secondary processes, we don't initialise any further as primary
1053 * has already done this work. Only check we don't need a different
1055 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1056 i40e_set_rx_function(dev);
1057 i40e_set_tx_function(dev);
1060 i40e_set_default_ptype_table(dev);
1061 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1062 intr_handle = &pci_dev->intr_handle;
1064 rte_eth_copy_pci_info(dev, pci_dev);
1066 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1067 pf->adapter->eth_dev = dev;
1068 pf->dev_data = dev->data;
1070 hw->back = I40E_PF_TO_ADAPTER(pf);
1071 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1074 "Hardware is not available, as address is NULL");
1078 hw->vendor_id = pci_dev->id.vendor_id;
1079 hw->device_id = pci_dev->id.device_id;
1080 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1081 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1082 hw->bus.device = pci_dev->addr.devid;
1083 hw->bus.func = pci_dev->addr.function;
1084 hw->adapter_stopped = 0;
1086 /* Make sure all is clean before doing PF reset */
1089 /* Initialize the hardware */
1092 /* Reset here to make sure all is clean for each PF */
1093 ret = i40e_pf_reset(hw);
1095 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1099 /* Initialize the shared code (base driver) */
1100 ret = i40e_init_shared_code(hw);
1102 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1106 i40e_set_default_pctype_table(dev);
1109 * To work around the NVM issue, initialize registers
1110 * for packet type of QinQ by software.
1111 * It should be removed once issues are fixed in NVM.
1113 i40e_GLQF_reg_init(hw);
1115 /* Initialize the input set for filters (hash and fd) to default value */
1116 i40e_filter_input_set_init(pf);
1118 /* Initialize the parameters for adminq */
1119 i40e_init_adminq_parameter(hw);
1120 ret = i40e_init_adminq(hw);
1121 if (ret != I40E_SUCCESS) {
1122 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1125 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1126 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1127 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1128 ((hw->nvm.version >> 12) & 0xf),
1129 ((hw->nvm.version >> 4) & 0xff),
1130 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1132 /* initialise the L3_MAP register */
1133 ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1136 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
1137 i40e_global_cfg_warning(I40E_WARNING_QINQ_CLOUD_FILTER);
1139 /* Need the special FW version to support floating VEB */
1140 config_floating_veb(dev);
1141 /* Clear PXE mode */
1142 i40e_clear_pxe_mode(hw);
1143 i40e_dev_sync_phy_type(hw);
1146 * On X710, performance number is far from the expectation on recent
1147 * firmware versions. The fix for this issue may not be integrated in
1148 * the following firmware version. So the workaround in software driver
1149 * is needed. It needs to modify the initial values of 3 internal only
1150 * registers. Note that the workaround can be removed when it is fixed
1151 * in firmware in the future.
1153 i40e_configure_registers(hw);
1155 /* Get hw capabilities */
1156 ret = i40e_get_cap(hw);
1157 if (ret != I40E_SUCCESS) {
1158 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1159 goto err_get_capabilities;
1162 /* Initialize parameters for PF */
1163 ret = i40e_pf_parameter_init(dev);
1165 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1166 goto err_parameter_init;
1169 /* Initialize the queue management */
1170 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1172 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1173 goto err_qp_pool_init;
1175 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1176 hw->func_caps.num_msix_vectors - 1);
1178 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1179 goto err_msix_pool_init;
1182 /* Initialize lan hmc */
1183 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1184 hw->func_caps.num_rx_qp, 0, 0);
1185 if (ret != I40E_SUCCESS) {
1186 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1187 goto err_init_lan_hmc;
1190 /* Configure lan hmc */
1191 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1192 if (ret != I40E_SUCCESS) {
1193 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1194 goto err_configure_lan_hmc;
1197 /* Get and check the mac address */
1198 i40e_get_mac_addr(hw, hw->mac.addr);
1199 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1200 PMD_INIT_LOG(ERR, "mac address is not valid");
1202 goto err_get_mac_addr;
1204 /* Copy the permanent MAC address */
1205 ether_addr_copy((struct ether_addr *) hw->mac.addr,
1206 (struct ether_addr *) hw->mac.perm_addr);
1208 /* Disable flow control */
1209 hw->fc.requested_mode = I40E_FC_NONE;
1210 i40e_set_fc(hw, &aq_fail, TRUE);
1212 /* Set the global registers with default ether type value */
1213 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1214 if (ret != I40E_SUCCESS) {
1216 "Failed to set the default outer VLAN ether type");
1217 goto err_setup_pf_switch;
1220 /* PF setup, which includes VSI setup */
1221 ret = i40e_pf_setup(pf);
1223 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1224 goto err_setup_pf_switch;
1227 /* reset all stats of the device, including pf and main vsi */
1228 i40e_dev_stats_reset(dev);
1232 /* Disable double vlan by default */
1233 i40e_vsi_config_double_vlan(vsi, FALSE);
1235 /* Disable S-TAG identification when floating_veb is disabled */
1236 if (!pf->floating_veb) {
1237 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1238 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1239 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1240 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1244 if (!vsi->max_macaddrs)
1245 len = ETHER_ADDR_LEN;
1247 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1249 /* Should be after VSI initialized */
1250 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1251 if (!dev->data->mac_addrs) {
1253 "Failed to allocated memory for storing mac address");
1256 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1257 &dev->data->mac_addrs[0]);
1259 /* Init dcb to sw mode by default */
1260 ret = i40e_dcb_init_configure(dev, TRUE);
1261 if (ret != I40E_SUCCESS) {
1262 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1263 pf->flags &= ~I40E_FLAG_DCB;
1265 /* Update HW struct after DCB configuration */
1268 /* initialize pf host driver to setup SRIOV resource if applicable */
1269 i40e_pf_host_init(dev);
1271 /* register callback func to eal lib */
1272 rte_intr_callback_register(intr_handle,
1273 i40e_dev_interrupt_handler, dev);
1275 /* configure and enable device interrupt */
1276 i40e_pf_config_irq0(hw, TRUE);
1277 i40e_pf_enable_irq0(hw);
1279 /* enable uio intr after callback register */
1280 rte_intr_enable(intr_handle);
1282 /* By default disable flexible payload in global configuration */
1283 i40e_flex_payload_reg_set_default(hw);
1286 * Add an ethertype filter to drop all flow control frames transmitted
1287 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1290 i40e_add_tx_flow_control_drop_filter(pf);
1292 /* Set the max frame size to 0x2600 by default,
1293 * in case other drivers changed the default value.
1295 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1297 /* initialize mirror rule list */
1298 TAILQ_INIT(&pf->mirror_list);
1300 /* initialize Traffic Manager configuration */
1301 i40e_tm_conf_init(dev);
1303 /* Initialize customized information */
1304 i40e_init_customized_info(pf);
1306 ret = i40e_init_ethtype_filter_list(dev);
1308 goto err_init_ethtype_filter_list;
1309 ret = i40e_init_tunnel_filter_list(dev);
1311 goto err_init_tunnel_filter_list;
1312 ret = i40e_init_fdir_filter_list(dev);
1314 goto err_init_fdir_filter_list;
1316 /* initialize queue region configuration */
1317 i40e_init_queue_region_conf(dev);
1319 /* initialize rss configuration from rte_flow */
1320 memset(&pf->rss_info, 0,
1321 sizeof(struct i40e_rte_flow_rss_conf));
1325 err_init_fdir_filter_list:
1326 rte_free(pf->tunnel.hash_table);
1327 rte_free(pf->tunnel.hash_map);
1328 err_init_tunnel_filter_list:
1329 rte_free(pf->ethertype.hash_table);
1330 rte_free(pf->ethertype.hash_map);
1331 err_init_ethtype_filter_list:
1332 rte_free(dev->data->mac_addrs);
1334 i40e_vsi_release(pf->main_vsi);
1335 err_setup_pf_switch:
1337 err_configure_lan_hmc:
1338 (void)i40e_shutdown_lan_hmc(hw);
1340 i40e_res_pool_destroy(&pf->msix_pool);
1342 i40e_res_pool_destroy(&pf->qp_pool);
1345 err_get_capabilities:
1346 (void)i40e_shutdown_adminq(hw);
1352 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1354 struct i40e_ethertype_filter *p_ethertype;
1355 struct i40e_ethertype_rule *ethertype_rule;
1357 ethertype_rule = &pf->ethertype;
1358 /* Remove all ethertype filter rules and hash */
1359 if (ethertype_rule->hash_map)
1360 rte_free(ethertype_rule->hash_map);
1361 if (ethertype_rule->hash_table)
1362 rte_hash_free(ethertype_rule->hash_table);
1364 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1365 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1366 p_ethertype, rules);
1367 rte_free(p_ethertype);
1372 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1374 struct i40e_tunnel_filter *p_tunnel;
1375 struct i40e_tunnel_rule *tunnel_rule;
1377 tunnel_rule = &pf->tunnel;
1378 /* Remove all tunnel director rules and hash */
1379 if (tunnel_rule->hash_map)
1380 rte_free(tunnel_rule->hash_map);
1381 if (tunnel_rule->hash_table)
1382 rte_hash_free(tunnel_rule->hash_table);
1384 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1385 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1391 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1393 struct i40e_fdir_filter *p_fdir;
1394 struct i40e_fdir_info *fdir_info;
1396 fdir_info = &pf->fdir;
1397 /* Remove all flow director rules and hash */
1398 if (fdir_info->hash_map)
1399 rte_free(fdir_info->hash_map);
1400 if (fdir_info->hash_table)
1401 rte_hash_free(fdir_info->hash_table);
1403 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1404 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1409 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1412 * Disable by default flexible payload
1413 * for corresponding L2/L3/L4 layers.
1415 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1416 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1417 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1418 i40e_global_cfg_warning(I40E_WARNING_DIS_FLX_PLD);
1422 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1425 struct rte_pci_device *pci_dev;
1426 struct rte_intr_handle *intr_handle;
1428 struct i40e_filter_control_settings settings;
1429 struct rte_flow *p_flow;
1431 uint8_t aq_fail = 0;
1433 PMD_INIT_FUNC_TRACE();
1435 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1438 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1439 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1440 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1441 intr_handle = &pci_dev->intr_handle;
1443 if (hw->adapter_stopped == 0)
1444 i40e_dev_close(dev);
1446 dev->dev_ops = NULL;
1447 dev->rx_pkt_burst = NULL;
1448 dev->tx_pkt_burst = NULL;
1450 /* Clear PXE mode */
1451 i40e_clear_pxe_mode(hw);
1453 /* Unconfigure filter control */
1454 memset(&settings, 0, sizeof(settings));
1455 ret = i40e_set_filter_control(hw, &settings);
1457 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1460 /* Disable flow control */
1461 hw->fc.requested_mode = I40E_FC_NONE;
1462 i40e_set_fc(hw, &aq_fail, TRUE);
1464 /* uninitialize pf host driver */
1465 i40e_pf_host_uninit(dev);
1467 rte_free(dev->data->mac_addrs);
1468 dev->data->mac_addrs = NULL;
1470 /* disable uio intr before callback unregister */
1471 rte_intr_disable(intr_handle);
1473 /* register callback func to eal lib */
1474 rte_intr_callback_unregister(intr_handle,
1475 i40e_dev_interrupt_handler, dev);
1477 i40e_rm_ethtype_filter_list(pf);
1478 i40e_rm_tunnel_filter_list(pf);
1479 i40e_rm_fdir_filter_list(pf);
1481 /* Remove all flows */
1482 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1483 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1487 /* Remove all Traffic Manager configuration */
1488 i40e_tm_conf_uninit(dev);
1494 i40e_dev_configure(struct rte_eth_dev *dev)
1496 struct i40e_adapter *ad =
1497 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1498 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1499 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1500 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1503 ret = i40e_dev_sync_phy_type(hw);
1507 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1508 * bulk allocation or vector Rx preconditions we will reset it.
1510 ad->rx_bulk_alloc_allowed = true;
1511 ad->rx_vec_allowed = true;
1512 ad->tx_simple_allowed = true;
1513 ad->tx_vec_allowed = true;
1515 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1516 ret = i40e_fdir_setup(pf);
1517 if (ret != I40E_SUCCESS) {
1518 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1521 ret = i40e_fdir_configure(dev);
1523 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1527 i40e_fdir_teardown(pf);
1529 ret = i40e_dev_init_vlan(dev);
1534 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1535 * RSS setting have different requirements.
1536 * General PMD driver call sequence are NIC init, configure,
1537 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1538 * will try to lookup the VSI that specific queue belongs to if VMDQ
1539 * applicable. So, VMDQ setting has to be done before
1540 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1541 * For RSS setting, it will try to calculate actual configured RX queue
1542 * number, which will be available after rx_queue_setup(). dev_start()
1543 * function is good to place RSS setup.
1545 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1546 ret = i40e_vmdq_setup(dev);
1551 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1552 ret = i40e_dcb_setup(dev);
1554 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1559 TAILQ_INIT(&pf->flow_list);
1564 /* need to release vmdq resource if exists */
1565 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1566 i40e_vsi_release(pf->vmdq[i].vsi);
1567 pf->vmdq[i].vsi = NULL;
1572 /* need to release fdir resource if exists */
1573 i40e_fdir_teardown(pf);
1578 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1580 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1581 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1582 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1583 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1584 uint16_t msix_vect = vsi->msix_intr;
1587 for (i = 0; i < vsi->nb_qps; i++) {
1588 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1589 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1593 if (vsi->type != I40E_VSI_SRIOV) {
1594 if (!rte_intr_allow_others(intr_handle)) {
1595 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1596 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1598 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1601 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1602 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1604 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1609 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1610 vsi->user_param + (msix_vect - 1);
1612 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1613 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1615 I40E_WRITE_FLUSH(hw);
1619 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1620 int base_queue, int nb_queue,
1625 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1627 /* Bind all RX queues to allocated MSIX interrupt */
1628 for (i = 0; i < nb_queue; i++) {
1629 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1630 itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1631 ((base_queue + i + 1) <<
1632 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1633 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1634 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1636 if (i == nb_queue - 1)
1637 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1638 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1641 /* Write first RX queue to Link list register as the head element */
1642 if (vsi->type != I40E_VSI_SRIOV) {
1644 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL, 1);
1646 if (msix_vect == I40E_MISC_VEC_ID) {
1647 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1649 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1651 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1653 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1656 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1658 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1660 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1662 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1669 if (msix_vect == I40E_MISC_VEC_ID) {
1671 I40E_VPINT_LNKLST0(vsi->user_param),
1673 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1675 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1677 /* num_msix_vectors_vf needs to minus irq0 */
1678 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1679 vsi->user_param + (msix_vect - 1);
1681 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1683 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1685 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1689 I40E_WRITE_FLUSH(hw);
1693 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1695 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1696 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1697 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1698 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1699 uint16_t msix_vect = vsi->msix_intr;
1700 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1701 uint16_t queue_idx = 0;
1706 for (i = 0; i < vsi->nb_qps; i++) {
1707 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1708 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1711 /* INTENA flag is not auto-cleared for interrupt */
1712 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1713 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1714 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1715 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1716 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1718 /* VF bind interrupt */
1719 if (vsi->type == I40E_VSI_SRIOV) {
1720 __vsi_queues_bind_intr(vsi, msix_vect,
1721 vsi->base_queue, vsi->nb_qps,
1726 /* PF & VMDq bind interrupt */
1727 if (rte_intr_dp_is_en(intr_handle)) {
1728 if (vsi->type == I40E_VSI_MAIN) {
1731 } else if (vsi->type == I40E_VSI_VMDQ2) {
1732 struct i40e_vsi *main_vsi =
1733 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1734 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1739 for (i = 0; i < vsi->nb_used_qps; i++) {
1741 if (!rte_intr_allow_others(intr_handle))
1742 /* allow to share MISC_VEC_ID */
1743 msix_vect = I40E_MISC_VEC_ID;
1745 /* no enough msix_vect, map all to one */
1746 __vsi_queues_bind_intr(vsi, msix_vect,
1747 vsi->base_queue + i,
1748 vsi->nb_used_qps - i,
1750 for (; !!record && i < vsi->nb_used_qps; i++)
1751 intr_handle->intr_vec[queue_idx + i] =
1755 /* 1:1 queue/msix_vect mapping */
1756 __vsi_queues_bind_intr(vsi, msix_vect,
1757 vsi->base_queue + i, 1,
1760 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1768 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1770 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1771 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1772 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1773 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1774 uint16_t interval = i40e_calc_itr_interval(\
1775 RTE_LIBRTE_I40E_ITR_INTERVAL, 1);
1776 uint16_t msix_intr, i;
1778 if (rte_intr_allow_others(intr_handle))
1779 for (i = 0; i < vsi->nb_msix; i++) {
1780 msix_intr = vsi->msix_intr + i;
1781 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1782 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1783 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1784 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1786 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1789 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1790 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1791 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1792 (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1794 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1796 I40E_WRITE_FLUSH(hw);
1800 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1802 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1803 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1804 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1805 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1806 uint16_t msix_intr, i;
1808 if (rte_intr_allow_others(intr_handle))
1809 for (i = 0; i < vsi->nb_msix; i++) {
1810 msix_intr = vsi->msix_intr + i;
1811 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1815 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1817 I40E_WRITE_FLUSH(hw);
1820 static inline uint8_t
1821 i40e_parse_link_speeds(uint16_t link_speeds)
1823 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1825 if (link_speeds & ETH_LINK_SPEED_40G)
1826 link_speed |= I40E_LINK_SPEED_40GB;
1827 if (link_speeds & ETH_LINK_SPEED_25G)
1828 link_speed |= I40E_LINK_SPEED_25GB;
1829 if (link_speeds & ETH_LINK_SPEED_20G)
1830 link_speed |= I40E_LINK_SPEED_20GB;
1831 if (link_speeds & ETH_LINK_SPEED_10G)
1832 link_speed |= I40E_LINK_SPEED_10GB;
1833 if (link_speeds & ETH_LINK_SPEED_1G)
1834 link_speed |= I40E_LINK_SPEED_1GB;
1835 if (link_speeds & ETH_LINK_SPEED_100M)
1836 link_speed |= I40E_LINK_SPEED_100MB;
1842 i40e_phy_conf_link(struct i40e_hw *hw,
1844 uint8_t force_speed,
1847 enum i40e_status_code status;
1848 struct i40e_aq_get_phy_abilities_resp phy_ab;
1849 struct i40e_aq_set_phy_config phy_conf;
1850 enum i40e_aq_phy_type cnt;
1851 uint32_t phy_type_mask = 0;
1853 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1854 I40E_AQ_PHY_FLAG_PAUSE_RX |
1855 I40E_AQ_PHY_FLAG_PAUSE_RX |
1856 I40E_AQ_PHY_FLAG_LOW_POWER;
1857 const uint8_t advt = I40E_LINK_SPEED_40GB |
1858 I40E_LINK_SPEED_25GB |
1859 I40E_LINK_SPEED_10GB |
1860 I40E_LINK_SPEED_1GB |
1861 I40E_LINK_SPEED_100MB;
1865 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1870 /* If link already up, no need to set up again */
1871 if (is_up && phy_ab.phy_type != 0)
1872 return I40E_SUCCESS;
1874 memset(&phy_conf, 0, sizeof(phy_conf));
1876 /* bits 0-2 use the values from get_phy_abilities_resp */
1878 abilities |= phy_ab.abilities & mask;
1880 /* update ablities and speed */
1881 if (abilities & I40E_AQ_PHY_AN_ENABLED)
1882 phy_conf.link_speed = advt;
1884 phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed;
1886 phy_conf.abilities = abilities;
1890 /* To enable link, phy_type mask needs to include each type */
1891 for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_MAX; cnt++)
1892 phy_type_mask |= 1 << cnt;
1894 /* use get_phy_abilities_resp value for the rest */
1895 phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
1896 phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
1897 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
1898 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
1899 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1900 phy_conf.eee_capability = phy_ab.eee_capability;
1901 phy_conf.eeer = phy_ab.eeer_val;
1902 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1904 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1905 phy_ab.abilities, phy_ab.link_speed);
1906 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
1907 phy_conf.abilities, phy_conf.link_speed);
1909 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1913 return I40E_SUCCESS;
1917 i40e_apply_link_speed(struct rte_eth_dev *dev)
1920 uint8_t abilities = 0;
1921 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1922 struct rte_eth_conf *conf = &dev->data->dev_conf;
1924 speed = i40e_parse_link_speeds(conf->link_speeds);
1925 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1926 if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1927 abilities |= I40E_AQ_PHY_AN_ENABLED;
1928 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1930 return i40e_phy_conf_link(hw, abilities, speed, true);
1934 i40e_dev_start(struct rte_eth_dev *dev)
1936 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1937 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1938 struct i40e_vsi *main_vsi = pf->main_vsi;
1940 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1941 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1942 uint32_t intr_vector = 0;
1943 struct i40e_vsi *vsi;
1945 hw->adapter_stopped = 0;
1947 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1949 "Invalid link_speeds for port %u, autonegotiation disabled",
1950 dev->data->port_id);
1954 rte_intr_disable(intr_handle);
1956 if ((rte_intr_cap_multiple(intr_handle) ||
1957 !RTE_ETH_DEV_SRIOV(dev).active) &&
1958 dev->data->dev_conf.intr_conf.rxq != 0) {
1959 intr_vector = dev->data->nb_rx_queues;
1960 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1965 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1966 intr_handle->intr_vec =
1967 rte_zmalloc("intr_vec",
1968 dev->data->nb_rx_queues * sizeof(int),
1970 if (!intr_handle->intr_vec) {
1972 "Failed to allocate %d rx_queues intr_vec",
1973 dev->data->nb_rx_queues);
1978 /* Initialize VSI */
1979 ret = i40e_dev_rxtx_init(pf);
1980 if (ret != I40E_SUCCESS) {
1981 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1985 /* Map queues with MSIX interrupt */
1986 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1987 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1988 i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
1989 i40e_vsi_enable_queues_intr(main_vsi);
1991 /* Map VMDQ VSI queues with MSIX interrupt */
1992 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1993 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1994 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
1995 I40E_ITR_INDEX_DEFAULT);
1996 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1999 /* enable FDIR MSIX interrupt */
2000 if (pf->fdir.fdir_vsi) {
2001 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2002 I40E_ITR_INDEX_NONE);
2003 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2006 /* Enable all queues which have been configured */
2007 ret = i40e_dev_switch_queues(pf, TRUE);
2009 if (ret != I40E_SUCCESS) {
2010 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2014 /* Enable receiving broadcast packets */
2015 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2016 if (ret != I40E_SUCCESS)
2017 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2019 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2020 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2022 if (ret != I40E_SUCCESS)
2023 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2026 /* Enable the VLAN promiscuous mode. */
2028 for (i = 0; i < pf->vf_num; i++) {
2029 vsi = pf->vfs[i].vsi;
2030 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2035 /* Enable mac loopback mode */
2036 if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2037 dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2038 ret = i40e_diag_set_loopback(hw, dev->data->dev_conf.lpbk_mode);
2039 if (ret != I40E_SUCCESS) {
2040 PMD_DRV_LOG(ERR, "fail to set loopback link");
2045 /* Apply link configure */
2046 if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
2047 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
2048 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
2049 ETH_LINK_SPEED_40G)) {
2050 PMD_DRV_LOG(ERR, "Invalid link setting");
2053 ret = i40e_apply_link_speed(dev);
2054 if (I40E_SUCCESS != ret) {
2055 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2059 if (!rte_intr_allow_others(intr_handle)) {
2060 rte_intr_callback_unregister(intr_handle,
2061 i40e_dev_interrupt_handler,
2063 /* configure and enable device interrupt */
2064 i40e_pf_config_irq0(hw, FALSE);
2065 i40e_pf_enable_irq0(hw);
2067 if (dev->data->dev_conf.intr_conf.lsc != 0)
2069 "lsc won't enable because of no intr multiplex");
2071 ret = i40e_aq_set_phy_int_mask(hw,
2072 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2073 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2074 I40E_AQ_EVENT_MEDIA_NA), NULL);
2075 if (ret != I40E_SUCCESS)
2076 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2078 /* Call get_link_info aq commond to enable/disable LSE */
2079 i40e_dev_link_update(dev, 0);
2082 /* enable uio intr after callback register */
2083 rte_intr_enable(intr_handle);
2085 i40e_filter_restore(pf);
2087 if (pf->tm_conf.root && !pf->tm_conf.committed)
2088 PMD_DRV_LOG(WARNING,
2089 "please call hierarchy_commit() "
2090 "before starting the port");
2092 return I40E_SUCCESS;
2095 i40e_dev_switch_queues(pf, FALSE);
2096 i40e_dev_clear_queues(dev);
2102 i40e_dev_stop(struct rte_eth_dev *dev)
2104 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2105 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2106 struct i40e_vsi *main_vsi = pf->main_vsi;
2107 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2108 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2111 if (hw->adapter_stopped == 1)
2113 /* Disable all queues */
2114 i40e_dev_switch_queues(pf, FALSE);
2116 /* un-map queues with interrupt registers */
2117 i40e_vsi_disable_queues_intr(main_vsi);
2118 i40e_vsi_queues_unbind_intr(main_vsi);
2120 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2121 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2122 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2125 if (pf->fdir.fdir_vsi) {
2126 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2127 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2129 /* Clear all queues and release memory */
2130 i40e_dev_clear_queues(dev);
2133 i40e_dev_set_link_down(dev);
2135 if (!rte_intr_allow_others(intr_handle))
2136 /* resume to the default handler */
2137 rte_intr_callback_register(intr_handle,
2138 i40e_dev_interrupt_handler,
2141 /* Clean datapath event and queue/vec mapping */
2142 rte_intr_efd_disable(intr_handle);
2143 if (intr_handle->intr_vec) {
2144 rte_free(intr_handle->intr_vec);
2145 intr_handle->intr_vec = NULL;
2148 /* reset hierarchy commit */
2149 pf->tm_conf.committed = false;
2151 hw->adapter_stopped = 1;
2155 i40e_dev_close(struct rte_eth_dev *dev)
2157 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2158 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2159 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2160 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2161 struct i40e_mirror_rule *p_mirror;
2166 PMD_INIT_FUNC_TRACE();
2170 /* Remove all mirror rules */
2171 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2172 ret = i40e_aq_del_mirror_rule(hw,
2173 pf->main_vsi->veb->seid,
2174 p_mirror->rule_type,
2176 p_mirror->num_entries,
2179 PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2180 "status = %d, aq_err = %d.", ret,
2181 hw->aq.asq_last_status);
2183 /* remove mirror software resource anyway */
2184 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2186 pf->nb_mirror_rule--;
2189 i40e_dev_free_queues(dev);
2191 /* Disable interrupt */
2192 i40e_pf_disable_irq0(hw);
2193 rte_intr_disable(intr_handle);
2195 /* shutdown and destroy the HMC */
2196 i40e_shutdown_lan_hmc(hw);
2198 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2199 i40e_vsi_release(pf->vmdq[i].vsi);
2200 pf->vmdq[i].vsi = NULL;
2205 /* release all the existing VSIs and VEBs */
2206 i40e_fdir_teardown(pf);
2207 i40e_vsi_release(pf->main_vsi);
2209 /* shutdown the adminq */
2210 i40e_aq_queue_shutdown(hw, true);
2211 i40e_shutdown_adminq(hw);
2213 i40e_res_pool_destroy(&pf->qp_pool);
2214 i40e_res_pool_destroy(&pf->msix_pool);
2216 /* Disable flexible payload in global configuration */
2217 i40e_flex_payload_reg_set_default(hw);
2219 /* force a PF reset to clean anything leftover */
2220 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2221 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2222 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2223 I40E_WRITE_FLUSH(hw);
2227 * Reset PF device only to re-initialize resources in PMD layer
2230 i40e_dev_reset(struct rte_eth_dev *dev)
2234 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2235 * its VF to make them align with it. The detailed notification
2236 * mechanism is PMD specific. As to i40e PF, it is rather complex.
2237 * To avoid unexpected behavior in VF, currently reset of PF with
2238 * SR-IOV activation is not supported. It might be supported later.
2240 if (dev->data->sriov.active)
2243 ret = eth_i40e_dev_uninit(dev);
2247 ret = eth_i40e_dev_init(dev);
2253 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2255 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2256 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2257 struct i40e_vsi *vsi = pf->main_vsi;
2260 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2262 if (status != I40E_SUCCESS)
2263 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2265 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2267 if (status != I40E_SUCCESS)
2268 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2273 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2275 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2276 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2277 struct i40e_vsi *vsi = pf->main_vsi;
2280 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2282 if (status != I40E_SUCCESS)
2283 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2285 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2287 if (status != I40E_SUCCESS)
2288 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2292 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2294 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2295 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2296 struct i40e_vsi *vsi = pf->main_vsi;
2299 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2300 if (ret != I40E_SUCCESS)
2301 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2305 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2307 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2308 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2309 struct i40e_vsi *vsi = pf->main_vsi;
2312 if (dev->data->promiscuous == 1)
2313 return; /* must remain in all_multicast mode */
2315 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2316 vsi->seid, FALSE, NULL);
2317 if (ret != I40E_SUCCESS)
2318 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2322 * Set device link up.
2325 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2327 /* re-apply link speed setting */
2328 return i40e_apply_link_speed(dev);
2332 * Set device link down.
2335 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2337 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2338 uint8_t abilities = 0;
2339 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2341 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2342 return i40e_phy_conf_link(hw, abilities, speed, false);
2346 i40e_dev_link_update(struct rte_eth_dev *dev,
2347 int wait_to_complete)
2349 #define CHECK_INTERVAL 100 /* 100ms */
2350 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2351 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2352 struct i40e_link_status link_status;
2353 struct rte_eth_link link, old;
2355 unsigned rep_cnt = MAX_REPEAT_TIME;
2356 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2358 memset(&link, 0, sizeof(link));
2359 memset(&old, 0, sizeof(old));
2360 memset(&link_status, 0, sizeof(link_status));
2361 rte_i40e_dev_atomic_read_link_status(dev, &old);
2364 /* Get link status information from hardware */
2365 status = i40e_aq_get_link_info(hw, enable_lse,
2366 &link_status, NULL);
2367 if (status != I40E_SUCCESS) {
2368 link.link_speed = ETH_SPEED_NUM_100M;
2369 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2370 PMD_DRV_LOG(ERR, "Failed to get link info");
2374 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2375 if (!wait_to_complete || link.link_status)
2378 rte_delay_ms(CHECK_INTERVAL);
2379 } while (--rep_cnt);
2381 if (!link.link_status)
2384 /* i40e uses full duplex only */
2385 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2387 /* Parse the link status */
2388 switch (link_status.link_speed) {
2389 case I40E_LINK_SPEED_100MB:
2390 link.link_speed = ETH_SPEED_NUM_100M;
2392 case I40E_LINK_SPEED_1GB:
2393 link.link_speed = ETH_SPEED_NUM_1G;
2395 case I40E_LINK_SPEED_10GB:
2396 link.link_speed = ETH_SPEED_NUM_10G;
2398 case I40E_LINK_SPEED_20GB:
2399 link.link_speed = ETH_SPEED_NUM_20G;
2401 case I40E_LINK_SPEED_25GB:
2402 link.link_speed = ETH_SPEED_NUM_25G;
2404 case I40E_LINK_SPEED_40GB:
2405 link.link_speed = ETH_SPEED_NUM_40G;
2408 link.link_speed = ETH_SPEED_NUM_100M;
2412 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2413 ETH_LINK_SPEED_FIXED);
2416 rte_i40e_dev_atomic_write_link_status(dev, &link);
2417 if (link.link_status == old.link_status)
2420 i40e_notify_all_vfs_link_status(dev);
2425 /* Get all the statistics of a VSI */
2427 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2429 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2430 struct i40e_eth_stats *nes = &vsi->eth_stats;
2431 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2432 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2434 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2435 vsi->offset_loaded, &oes->rx_bytes,
2437 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2438 vsi->offset_loaded, &oes->rx_unicast,
2440 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2441 vsi->offset_loaded, &oes->rx_multicast,
2442 &nes->rx_multicast);
2443 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2444 vsi->offset_loaded, &oes->rx_broadcast,
2445 &nes->rx_broadcast);
2446 /* exclude CRC bytes */
2447 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2448 nes->rx_broadcast) * ETHER_CRC_LEN;
2450 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2451 &oes->rx_discards, &nes->rx_discards);
2452 /* GLV_REPC not supported */
2453 /* GLV_RMPC not supported */
2454 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2455 &oes->rx_unknown_protocol,
2456 &nes->rx_unknown_protocol);
2457 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2458 vsi->offset_loaded, &oes->tx_bytes,
2460 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2461 vsi->offset_loaded, &oes->tx_unicast,
2463 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2464 vsi->offset_loaded, &oes->tx_multicast,
2465 &nes->tx_multicast);
2466 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2467 vsi->offset_loaded, &oes->tx_broadcast,
2468 &nes->tx_broadcast);
2469 /* GLV_TDPC not supported */
2470 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2471 &oes->tx_errors, &nes->tx_errors);
2472 vsi->offset_loaded = true;
2474 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2476 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2477 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2478 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2479 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2480 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2481 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2482 nes->rx_unknown_protocol);
2483 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2484 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2485 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2486 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2487 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2488 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2489 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2494 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2497 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2498 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2500 /* Get rx/tx bytes of internal transfer packets */
2501 i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2502 I40E_GLV_GORCL(hw->port),
2504 &pf->internal_stats_offset.rx_bytes,
2505 &pf->internal_stats.rx_bytes);
2507 i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2508 I40E_GLV_GOTCL(hw->port),
2510 &pf->internal_stats_offset.tx_bytes,
2511 &pf->internal_stats.tx_bytes);
2512 /* Get total internal rx packet count */
2513 i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2514 I40E_GLV_UPRCL(hw->port),
2516 &pf->internal_stats_offset.rx_unicast,
2517 &pf->internal_stats.rx_unicast);
2518 i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2519 I40E_GLV_MPRCL(hw->port),
2521 &pf->internal_stats_offset.rx_multicast,
2522 &pf->internal_stats.rx_multicast);
2523 i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2524 I40E_GLV_BPRCL(hw->port),
2526 &pf->internal_stats_offset.rx_broadcast,
2527 &pf->internal_stats.rx_broadcast);
2528 /* Get total internal tx packet count */
2529 i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
2530 I40E_GLV_UPTCL(hw->port),
2532 &pf->internal_stats_offset.tx_unicast,
2533 &pf->internal_stats.tx_unicast);
2534 i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
2535 I40E_GLV_MPTCL(hw->port),
2537 &pf->internal_stats_offset.tx_multicast,
2538 &pf->internal_stats.tx_multicast);
2539 i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
2540 I40E_GLV_BPTCL(hw->port),
2542 &pf->internal_stats_offset.tx_broadcast,
2543 &pf->internal_stats.tx_broadcast);
2545 /* exclude CRC size */
2546 pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2547 pf->internal_stats.rx_multicast +
2548 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2550 /* Get statistics of struct i40e_eth_stats */
2551 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2552 I40E_GLPRT_GORCL(hw->port),
2553 pf->offset_loaded, &os->eth.rx_bytes,
2555 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2556 I40E_GLPRT_UPRCL(hw->port),
2557 pf->offset_loaded, &os->eth.rx_unicast,
2558 &ns->eth.rx_unicast);
2559 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2560 I40E_GLPRT_MPRCL(hw->port),
2561 pf->offset_loaded, &os->eth.rx_multicast,
2562 &ns->eth.rx_multicast);
2563 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2564 I40E_GLPRT_BPRCL(hw->port),
2565 pf->offset_loaded, &os->eth.rx_broadcast,
2566 &ns->eth.rx_broadcast);
2567 /* Workaround: CRC size should not be included in byte statistics,
2568 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2570 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2571 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2573 /* exclude internal rx bytes
2574 * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2575 * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
2577 * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
2579 if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2580 ns->eth.rx_bytes = 0;
2582 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2584 if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
2585 ns->eth.rx_unicast = 0;
2587 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
2589 if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
2590 ns->eth.rx_multicast = 0;
2592 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
2594 if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
2595 ns->eth.rx_broadcast = 0;
2597 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
2599 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2600 pf->offset_loaded, &os->eth.rx_discards,
2601 &ns->eth.rx_discards);
2602 /* GLPRT_REPC not supported */
2603 /* GLPRT_RMPC not supported */
2604 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2606 &os->eth.rx_unknown_protocol,
2607 &ns->eth.rx_unknown_protocol);
2608 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2609 I40E_GLPRT_GOTCL(hw->port),
2610 pf->offset_loaded, &os->eth.tx_bytes,
2612 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2613 I40E_GLPRT_UPTCL(hw->port),
2614 pf->offset_loaded, &os->eth.tx_unicast,
2615 &ns->eth.tx_unicast);
2616 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2617 I40E_GLPRT_MPTCL(hw->port),
2618 pf->offset_loaded, &os->eth.tx_multicast,
2619 &ns->eth.tx_multicast);
2620 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2621 I40E_GLPRT_BPTCL(hw->port),
2622 pf->offset_loaded, &os->eth.tx_broadcast,
2623 &ns->eth.tx_broadcast);
2624 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2625 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2627 /* exclude internal tx bytes
2628 * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
2629 * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
2631 * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
2633 if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2634 ns->eth.tx_bytes = 0;
2636 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2638 if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
2639 ns->eth.tx_unicast = 0;
2641 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
2643 if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
2644 ns->eth.tx_multicast = 0;
2646 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
2648 if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
2649 ns->eth.tx_broadcast = 0;
2651 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
2653 /* GLPRT_TEPC not supported */
2655 /* additional port specific stats */
2656 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2657 pf->offset_loaded, &os->tx_dropped_link_down,
2658 &ns->tx_dropped_link_down);
2659 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2660 pf->offset_loaded, &os->crc_errors,
2662 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2663 pf->offset_loaded, &os->illegal_bytes,
2664 &ns->illegal_bytes);
2665 /* GLPRT_ERRBC not supported */
2666 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2667 pf->offset_loaded, &os->mac_local_faults,
2668 &ns->mac_local_faults);
2669 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2670 pf->offset_loaded, &os->mac_remote_faults,
2671 &ns->mac_remote_faults);
2672 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2673 pf->offset_loaded, &os->rx_length_errors,
2674 &ns->rx_length_errors);
2675 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2676 pf->offset_loaded, &os->link_xon_rx,
2678 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2679 pf->offset_loaded, &os->link_xoff_rx,
2681 for (i = 0; i < 8; i++) {
2682 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2684 &os->priority_xon_rx[i],
2685 &ns->priority_xon_rx[i]);
2686 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2688 &os->priority_xoff_rx[i],
2689 &ns->priority_xoff_rx[i]);
2691 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2692 pf->offset_loaded, &os->link_xon_tx,
2694 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2695 pf->offset_loaded, &os->link_xoff_tx,
2697 for (i = 0; i < 8; i++) {
2698 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2700 &os->priority_xon_tx[i],
2701 &ns->priority_xon_tx[i]);
2702 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2704 &os->priority_xoff_tx[i],
2705 &ns->priority_xoff_tx[i]);
2706 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2708 &os->priority_xon_2_xoff[i],
2709 &ns->priority_xon_2_xoff[i]);
2711 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2712 I40E_GLPRT_PRC64L(hw->port),
2713 pf->offset_loaded, &os->rx_size_64,
2715 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2716 I40E_GLPRT_PRC127L(hw->port),
2717 pf->offset_loaded, &os->rx_size_127,
2719 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2720 I40E_GLPRT_PRC255L(hw->port),
2721 pf->offset_loaded, &os->rx_size_255,
2723 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2724 I40E_GLPRT_PRC511L(hw->port),
2725 pf->offset_loaded, &os->rx_size_511,
2727 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2728 I40E_GLPRT_PRC1023L(hw->port),
2729 pf->offset_loaded, &os->rx_size_1023,
2731 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2732 I40E_GLPRT_PRC1522L(hw->port),
2733 pf->offset_loaded, &os->rx_size_1522,
2735 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2736 I40E_GLPRT_PRC9522L(hw->port),
2737 pf->offset_loaded, &os->rx_size_big,
2739 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2740 pf->offset_loaded, &os->rx_undersize,
2742 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2743 pf->offset_loaded, &os->rx_fragments,
2745 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2746 pf->offset_loaded, &os->rx_oversize,
2748 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2749 pf->offset_loaded, &os->rx_jabber,
2751 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2752 I40E_GLPRT_PTC64L(hw->port),
2753 pf->offset_loaded, &os->tx_size_64,
2755 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2756 I40E_GLPRT_PTC127L(hw->port),
2757 pf->offset_loaded, &os->tx_size_127,
2759 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2760 I40E_GLPRT_PTC255L(hw->port),
2761 pf->offset_loaded, &os->tx_size_255,
2763 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2764 I40E_GLPRT_PTC511L(hw->port),
2765 pf->offset_loaded, &os->tx_size_511,
2767 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2768 I40E_GLPRT_PTC1023L(hw->port),
2769 pf->offset_loaded, &os->tx_size_1023,
2771 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2772 I40E_GLPRT_PTC1522L(hw->port),
2773 pf->offset_loaded, &os->tx_size_1522,
2775 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2776 I40E_GLPRT_PTC9522L(hw->port),
2777 pf->offset_loaded, &os->tx_size_big,
2779 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2781 &os->fd_sb_match, &ns->fd_sb_match);
2782 /* GLPRT_MSPDC not supported */
2783 /* GLPRT_XEC not supported */
2785 pf->offset_loaded = true;
2788 i40e_update_vsi_stats(pf->main_vsi);
2791 /* Get all statistics of a port */
2793 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2795 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2796 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2797 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2800 /* call read registers - updates values, now write them to struct */
2801 i40e_read_stats_registers(pf, hw);
2803 stats->ipackets = ns->eth.rx_unicast +
2804 ns->eth.rx_multicast +
2805 ns->eth.rx_broadcast -
2806 ns->eth.rx_discards -
2807 pf->main_vsi->eth_stats.rx_discards;
2808 stats->opackets = ns->eth.tx_unicast +
2809 ns->eth.tx_multicast +
2810 ns->eth.tx_broadcast;
2811 stats->ibytes = ns->eth.rx_bytes;
2812 stats->obytes = ns->eth.tx_bytes;
2813 stats->oerrors = ns->eth.tx_errors +
2814 pf->main_vsi->eth_stats.tx_errors;
2817 stats->imissed = ns->eth.rx_discards +
2818 pf->main_vsi->eth_stats.rx_discards;
2819 stats->ierrors = ns->crc_errors +
2820 ns->rx_length_errors + ns->rx_undersize +
2821 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2823 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2824 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
2825 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
2826 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
2827 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
2828 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
2829 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2830 ns->eth.rx_unknown_protocol);
2831 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
2832 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
2833 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
2834 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
2835 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
2836 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
2838 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
2839 ns->tx_dropped_link_down);
2840 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
2841 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
2843 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
2844 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
2845 ns->mac_local_faults);
2846 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
2847 ns->mac_remote_faults);
2848 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
2849 ns->rx_length_errors);
2850 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
2851 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
2852 for (i = 0; i < 8; i++) {
2853 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
2854 i, ns->priority_xon_rx[i]);
2855 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
2856 i, ns->priority_xoff_rx[i]);
2858 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
2859 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
2860 for (i = 0; i < 8; i++) {
2861 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
2862 i, ns->priority_xon_tx[i]);
2863 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
2864 i, ns->priority_xoff_tx[i]);
2865 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
2866 i, ns->priority_xon_2_xoff[i]);
2868 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
2869 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
2870 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
2871 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
2872 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
2873 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
2874 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
2875 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
2876 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
2877 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
2878 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
2879 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
2880 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
2881 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
2882 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
2883 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
2884 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
2885 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
2886 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2887 ns->mac_short_packet_dropped);
2888 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
2889 ns->checksum_error);
2890 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
2891 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2895 /* Reset the statistics */
2897 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2899 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2900 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2902 /* Mark PF and VSI stats to update the offset, aka "reset" */
2903 pf->offset_loaded = false;
2905 pf->main_vsi->offset_loaded = false;
2907 /* read the stats, reading current register values into offset */
2908 i40e_read_stats_registers(pf, hw);
2912 i40e_xstats_calc_num(void)
2914 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2915 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2916 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2919 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2920 struct rte_eth_xstat_name *xstats_names,
2921 __rte_unused unsigned limit)
2926 if (xstats_names == NULL)
2927 return i40e_xstats_calc_num();
2929 /* Note: limit checked in rte_eth_xstats_names() */
2931 /* Get stats from i40e_eth_stats struct */
2932 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2933 snprintf(xstats_names[count].name,
2934 sizeof(xstats_names[count].name),
2935 "%s", rte_i40e_stats_strings[i].name);
2939 /* Get individiual stats from i40e_hw_port struct */
2940 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2941 snprintf(xstats_names[count].name,
2942 sizeof(xstats_names[count].name),
2943 "%s", rte_i40e_hw_port_strings[i].name);
2947 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2948 for (prio = 0; prio < 8; prio++) {
2949 snprintf(xstats_names[count].name,
2950 sizeof(xstats_names[count].name),
2951 "rx_priority%u_%s", prio,
2952 rte_i40e_rxq_prio_strings[i].name);
2957 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2958 for (prio = 0; prio < 8; prio++) {
2959 snprintf(xstats_names[count].name,
2960 sizeof(xstats_names[count].name),
2961 "tx_priority%u_%s", prio,
2962 rte_i40e_txq_prio_strings[i].name);
2970 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2973 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2974 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2975 unsigned i, count, prio;
2976 struct i40e_hw_port_stats *hw_stats = &pf->stats;
2978 count = i40e_xstats_calc_num();
2982 i40e_read_stats_registers(pf, hw);
2989 /* Get stats from i40e_eth_stats struct */
2990 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2991 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2992 rte_i40e_stats_strings[i].offset);
2993 xstats[count].id = count;
2997 /* Get individiual stats from i40e_hw_port struct */
2998 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2999 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3000 rte_i40e_hw_port_strings[i].offset);
3001 xstats[count].id = count;
3005 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3006 for (prio = 0; prio < 8; prio++) {
3007 xstats[count].value =
3008 *(uint64_t *)(((char *)hw_stats) +
3009 rte_i40e_rxq_prio_strings[i].offset +
3010 (sizeof(uint64_t) * prio));
3011 xstats[count].id = count;
3016 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3017 for (prio = 0; prio < 8; prio++) {
3018 xstats[count].value =
3019 *(uint64_t *)(((char *)hw_stats) +
3020 rte_i40e_txq_prio_strings[i].offset +
3021 (sizeof(uint64_t) * prio));
3022 xstats[count].id = count;
3031 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
3032 __rte_unused uint16_t queue_id,
3033 __rte_unused uint8_t stat_idx,
3034 __rte_unused uint8_t is_rx)
3036 PMD_INIT_FUNC_TRACE();
3042 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3044 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3050 full_ver = hw->nvm.oem_ver;
3051 ver = (u8)(full_ver >> 24);
3052 build = (u16)((full_ver >> 8) & 0xffff);
3053 patch = (u8)(full_ver & 0xff);
3055 ret = snprintf(fw_version, fw_size,
3056 "%d.%d%d 0x%08x %d.%d.%d",
3057 ((hw->nvm.version >> 12) & 0xf),
3058 ((hw->nvm.version >> 4) & 0xff),
3059 (hw->nvm.version & 0xf), hw->nvm.eetrack,
3062 ret += 1; /* add the size of '\0' */
3063 if (fw_size < (u32)ret)
3070 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3072 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3073 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3074 struct i40e_vsi *vsi = pf->main_vsi;
3075 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3077 dev_info->pci_dev = pci_dev;
3078 dev_info->max_rx_queues = vsi->nb_qps;
3079 dev_info->max_tx_queues = vsi->nb_qps;
3080 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3081 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3082 dev_info->max_mac_addrs = vsi->max_macaddrs;
3083 dev_info->max_vfs = pci_dev->max_vfs;
3084 dev_info->rx_offload_capa =
3085 DEV_RX_OFFLOAD_VLAN_STRIP |
3086 DEV_RX_OFFLOAD_QINQ_STRIP |
3087 DEV_RX_OFFLOAD_IPV4_CKSUM |
3088 DEV_RX_OFFLOAD_UDP_CKSUM |
3089 DEV_RX_OFFLOAD_TCP_CKSUM |
3090 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3091 DEV_RX_OFFLOAD_CRC_STRIP;
3092 dev_info->tx_offload_capa =
3093 DEV_TX_OFFLOAD_VLAN_INSERT |
3094 DEV_TX_OFFLOAD_QINQ_INSERT |
3095 DEV_TX_OFFLOAD_IPV4_CKSUM |
3096 DEV_TX_OFFLOAD_UDP_CKSUM |
3097 DEV_TX_OFFLOAD_TCP_CKSUM |
3098 DEV_TX_OFFLOAD_SCTP_CKSUM |
3099 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3100 DEV_TX_OFFLOAD_TCP_TSO |
3101 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3102 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3103 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3104 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
3105 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3107 dev_info->reta_size = pf->hash_lut_size;
3108 dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3110 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3112 .pthresh = I40E_DEFAULT_RX_PTHRESH,
3113 .hthresh = I40E_DEFAULT_RX_HTHRESH,
3114 .wthresh = I40E_DEFAULT_RX_WTHRESH,
3116 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3120 dev_info->default_txconf = (struct rte_eth_txconf) {
3122 .pthresh = I40E_DEFAULT_TX_PTHRESH,
3123 .hthresh = I40E_DEFAULT_TX_HTHRESH,
3124 .wthresh = I40E_DEFAULT_TX_WTHRESH,
3126 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3127 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3128 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3129 ETH_TXQ_FLAGS_NOOFFLOADS,
3132 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3133 .nb_max = I40E_MAX_RING_DESC,
3134 .nb_min = I40E_MIN_RING_DESC,
3135 .nb_align = I40E_ALIGN_RING_DESC,
3138 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3139 .nb_max = I40E_MAX_RING_DESC,
3140 .nb_min = I40E_MIN_RING_DESC,
3141 .nb_align = I40E_ALIGN_RING_DESC,
3142 .nb_seg_max = I40E_TX_MAX_SEG,
3143 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3146 if (pf->flags & I40E_FLAG_VMDQ) {
3147 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3148 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3149 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3150 pf->max_nb_vmdq_vsi;
3151 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3152 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3153 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3156 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
3158 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3159 else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
3161 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3164 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3168 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3170 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3171 struct i40e_vsi *vsi = pf->main_vsi;
3172 PMD_INIT_FUNC_TRACE();
3175 return i40e_vsi_add_vlan(vsi, vlan_id);
3177 return i40e_vsi_delete_vlan(vsi, vlan_id);
3181 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3182 enum rte_vlan_type vlan_type,
3183 uint16_t tpid, int qinq)
3185 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3188 uint16_t reg_id = 3;
3192 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3196 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3198 if (ret != I40E_SUCCESS) {
3200 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3205 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3208 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3209 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3210 if (reg_r == reg_w) {
3211 PMD_DRV_LOG(DEBUG, "No need to write");
3215 ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3217 if (ret != I40E_SUCCESS) {
3219 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3224 "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3231 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3232 enum rte_vlan_type vlan_type,
3235 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3236 int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
3239 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3240 vlan_type != ETH_VLAN_TYPE_OUTER) ||
3241 (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3243 "Unsupported vlan type.");
3246 /* 802.1ad frames ability is added in NVM API 1.7*/
3247 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3249 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3250 hw->first_tag = rte_cpu_to_le_16(tpid);
3251 else if (vlan_type == ETH_VLAN_TYPE_INNER)
3252 hw->second_tag = rte_cpu_to_le_16(tpid);
3254 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3255 hw->second_tag = rte_cpu_to_le_16(tpid);
3257 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3258 if (ret != I40E_SUCCESS) {
3260 "Set switch config failed aq_err: %d",
3261 hw->aq.asq_last_status);
3265 /* If NVM API < 1.7, keep the register setting */
3266 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3268 i40e_global_cfg_warning(I40E_WARNING_TPID);
3274 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3276 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3277 struct i40e_vsi *vsi = pf->main_vsi;
3279 if (mask & ETH_VLAN_FILTER_MASK) {
3280 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3281 i40e_vsi_config_vlan_filter(vsi, TRUE);
3283 i40e_vsi_config_vlan_filter(vsi, FALSE);
3286 if (mask & ETH_VLAN_STRIP_MASK) {
3287 /* Enable or disable VLAN stripping */
3288 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3289 i40e_vsi_config_vlan_stripping(vsi, TRUE);
3291 i40e_vsi_config_vlan_stripping(vsi, FALSE);
3294 if (mask & ETH_VLAN_EXTEND_MASK) {
3295 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3296 i40e_vsi_config_double_vlan(vsi, TRUE);
3297 /* Set global registers with default ethertype. */
3298 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3300 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3304 i40e_vsi_config_double_vlan(vsi, FALSE);
3311 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3312 __rte_unused uint16_t queue,
3313 __rte_unused int on)
3315 PMD_INIT_FUNC_TRACE();
3319 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3321 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3322 struct i40e_vsi *vsi = pf->main_vsi;
3323 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3324 struct i40e_vsi_vlan_pvid_info info;
3326 memset(&info, 0, sizeof(info));
3329 info.config.pvid = pvid;
3331 info.config.reject.tagged =
3332 data->dev_conf.txmode.hw_vlan_reject_tagged;
3333 info.config.reject.untagged =
3334 data->dev_conf.txmode.hw_vlan_reject_untagged;
3337 return i40e_vsi_vlan_pvid_set(vsi, &info);
3341 i40e_dev_led_on(struct rte_eth_dev *dev)
3343 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3344 uint32_t mode = i40e_led_get(hw);
3347 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3353 i40e_dev_led_off(struct rte_eth_dev *dev)
3355 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3356 uint32_t mode = i40e_led_get(hw);
3359 i40e_led_set(hw, 0, false);
3365 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3367 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3368 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3370 fc_conf->pause_time = pf->fc_conf.pause_time;
3372 /* read out from register, in case they are modified by other port */
3373 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3374 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3375 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3376 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3378 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3379 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3381 /* Return current mode according to actual setting*/
3382 switch (hw->fc.current_mode) {
3384 fc_conf->mode = RTE_FC_FULL;
3386 case I40E_FC_TX_PAUSE:
3387 fc_conf->mode = RTE_FC_TX_PAUSE;
3389 case I40E_FC_RX_PAUSE:
3390 fc_conf->mode = RTE_FC_RX_PAUSE;
3394 fc_conf->mode = RTE_FC_NONE;
3401 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3403 uint32_t mflcn_reg, fctrl_reg, reg;
3404 uint32_t max_high_water;
3405 uint8_t i, aq_failure;
3409 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3410 [RTE_FC_NONE] = I40E_FC_NONE,
3411 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3412 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3413 [RTE_FC_FULL] = I40E_FC_FULL
3416 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3418 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3419 if ((fc_conf->high_water > max_high_water) ||
3420 (fc_conf->high_water < fc_conf->low_water)) {
3422 "Invalid high/low water setup value in KB, High_water must be <= %d.",
3427 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3428 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3429 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3431 pf->fc_conf.pause_time = fc_conf->pause_time;
3432 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3433 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3435 PMD_INIT_FUNC_TRACE();
3437 /* All the link flow control related enable/disable register
3438 * configuration is handle by the F/W
3440 err = i40e_set_fc(hw, &aq_failure, true);
3444 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3445 /* Configure flow control refresh threshold,
3446 * the value for stat_tx_pause_refresh_timer[8]
3447 * is used for global pause operation.
3451 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3452 pf->fc_conf.pause_time);
3454 /* configure the timer value included in transmitted pause
3456 * the value for stat_tx_pause_quanta[8] is used for global
3459 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3460 pf->fc_conf.pause_time);
3462 fctrl_reg = I40E_READ_REG(hw,
3463 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3465 if (fc_conf->mac_ctrl_frame_fwd != 0)
3466 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3468 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3470 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3473 /* Configure pause time (2 TCs per register) */
3474 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3475 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3476 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3478 /* Configure flow control refresh threshold value */
3479 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3480 pf->fc_conf.pause_time / 2);
3482 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3484 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3485 *depending on configuration
3487 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3488 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3489 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3491 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3492 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3495 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3498 /* config the water marker both based on the packets and bytes */
3499 I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3500 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3501 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3502 I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3503 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3504 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3505 I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3506 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3508 I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3509 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3511 i40e_global_cfg_warning(I40E_WARNING_FLOW_CTL);
3513 I40E_WRITE_FLUSH(hw);
3519 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3520 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3522 PMD_INIT_FUNC_TRACE();
3527 /* Add a MAC address, and update filters */
3529 i40e_macaddr_add(struct rte_eth_dev *dev,
3530 struct ether_addr *mac_addr,
3531 __rte_unused uint32_t index,
3534 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3535 struct i40e_mac_filter_info mac_filter;
3536 struct i40e_vsi *vsi;
3539 /* If VMDQ not enabled or configured, return */
3540 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3541 !pf->nb_cfg_vmdq_vsi)) {
3542 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3543 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3548 if (pool > pf->nb_cfg_vmdq_vsi) {
3549 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3550 pool, pf->nb_cfg_vmdq_vsi);
3554 rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3555 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3556 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3558 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3563 vsi = pf->vmdq[pool - 1].vsi;
3565 ret = i40e_vsi_add_mac(vsi, &mac_filter);
3566 if (ret != I40E_SUCCESS) {
3567 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3573 /* Remove a MAC address, and update filters */
3575 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3577 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3578 struct i40e_vsi *vsi;
3579 struct rte_eth_dev_data *data = dev->data;
3580 struct ether_addr *macaddr;
3585 macaddr = &(data->mac_addrs[index]);
3587 pool_sel = dev->data->mac_pool_sel[index];
3589 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3590 if (pool_sel & (1ULL << i)) {
3594 /* No VMDQ pool enabled or configured */
3595 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3596 (i > pf->nb_cfg_vmdq_vsi)) {
3598 "No VMDQ pool enabled/configured");
3601 vsi = pf->vmdq[i - 1].vsi;
3603 ret = i40e_vsi_delete_mac(vsi, macaddr);
3606 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3613 /* Set perfect match or hash match of MAC and VLAN for a VF */
3615 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3616 struct rte_eth_mac_filter *filter,
3620 struct i40e_mac_filter_info mac_filter;
3621 struct ether_addr old_mac;
3622 struct ether_addr *new_mac;
3623 struct i40e_pf_vf *vf = NULL;
3628 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3631 hw = I40E_PF_TO_HW(pf);
3633 if (filter == NULL) {
3634 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3638 new_mac = &filter->mac_addr;
3640 if (is_zero_ether_addr(new_mac)) {
3641 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3645 vf_id = filter->dst_id;
3647 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3648 PMD_DRV_LOG(ERR, "Invalid argument.");
3651 vf = &pf->vfs[vf_id];
3653 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3654 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3659 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3660 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3662 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3665 mac_filter.filter_type = filter->filter_type;
3666 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3667 if (ret != I40E_SUCCESS) {
3668 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3671 ether_addr_copy(new_mac, &pf->dev_addr);
3673 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3675 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3676 if (ret != I40E_SUCCESS) {
3677 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3681 /* Clear device address as it has been removed */
3682 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3683 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3689 /* MAC filter handle */
3691 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3694 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3695 struct rte_eth_mac_filter *filter;
3696 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3697 int ret = I40E_NOT_SUPPORTED;
3699 filter = (struct rte_eth_mac_filter *)(arg);
3701 switch (filter_op) {
3702 case RTE_ETH_FILTER_NOP:
3705 case RTE_ETH_FILTER_ADD:
3706 i40e_pf_disable_irq0(hw);
3708 ret = i40e_vf_mac_filter_set(pf, filter, 1);
3709 i40e_pf_enable_irq0(hw);
3711 case RTE_ETH_FILTER_DELETE:
3712 i40e_pf_disable_irq0(hw);
3714 ret = i40e_vf_mac_filter_set(pf, filter, 0);
3715 i40e_pf_enable_irq0(hw);
3718 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3719 ret = I40E_ERR_PARAM;
3727 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3729 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3730 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3737 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3738 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3741 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3745 uint32_t *lut_dw = (uint32_t *)lut;
3746 uint16_t i, lut_size_dw = lut_size / 4;
3748 if (vsi->type == I40E_VSI_SRIOV) {
3749 for (i = 0; i <= lut_size_dw; i++) {
3750 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
3751 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
3754 for (i = 0; i < lut_size_dw; i++)
3755 lut_dw[i] = I40E_READ_REG(hw,
3764 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3773 pf = I40E_VSI_TO_PF(vsi);
3774 hw = I40E_VSI_TO_HW(vsi);
3776 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3777 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3780 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3784 uint32_t *lut_dw = (uint32_t *)lut;
3785 uint16_t i, lut_size_dw = lut_size / 4;
3787 if (vsi->type == I40E_VSI_SRIOV) {
3788 for (i = 0; i < lut_size_dw; i++)
3791 I40E_VFQF_HLUT1(i, vsi->user_param),
3794 for (i = 0; i < lut_size_dw; i++)
3795 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
3798 I40E_WRITE_FLUSH(hw);
3805 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3806 struct rte_eth_rss_reta_entry64 *reta_conf,
3809 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3810 uint16_t i, lut_size = pf->hash_lut_size;
3811 uint16_t idx, shift;
3815 if (reta_size != lut_size ||
3816 reta_size > ETH_RSS_RETA_SIZE_512) {
3818 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3819 reta_size, lut_size);
3823 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3825 PMD_DRV_LOG(ERR, "No memory can be allocated");
3828 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3831 for (i = 0; i < reta_size; i++) {
3832 idx = i / RTE_RETA_GROUP_SIZE;
3833 shift = i % RTE_RETA_GROUP_SIZE;
3834 if (reta_conf[idx].mask & (1ULL << shift))
3835 lut[i] = reta_conf[idx].reta[shift];
3837 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3846 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3847 struct rte_eth_rss_reta_entry64 *reta_conf,
3850 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3851 uint16_t i, lut_size = pf->hash_lut_size;
3852 uint16_t idx, shift;
3856 if (reta_size != lut_size ||
3857 reta_size > ETH_RSS_RETA_SIZE_512) {
3859 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3860 reta_size, lut_size);
3864 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3866 PMD_DRV_LOG(ERR, "No memory can be allocated");
3870 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3873 for (i = 0; i < reta_size; i++) {
3874 idx = i / RTE_RETA_GROUP_SIZE;
3875 shift = i % RTE_RETA_GROUP_SIZE;
3876 if (reta_conf[idx].mask & (1ULL << shift))
3877 reta_conf[idx].reta[shift] = lut[i];
3887 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3888 * @hw: pointer to the HW structure
3889 * @mem: pointer to mem struct to fill out
3890 * @size: size of memory requested
3891 * @alignment: what to align the allocation to
3893 enum i40e_status_code
3894 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3895 struct i40e_dma_mem *mem,
3899 const struct rte_memzone *mz = NULL;
3900 char z_name[RTE_MEMZONE_NAMESIZE];
3903 return I40E_ERR_PARAM;
3905 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3906 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3907 alignment, RTE_PGSIZE_2M);
3909 return I40E_ERR_NO_MEMORY;
3914 mem->zone = (const void *)mz;
3916 "memzone %s allocated with physical address: %"PRIu64,
3919 return I40E_SUCCESS;
3923 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3924 * @hw: pointer to the HW structure
3925 * @mem: ptr to mem struct to free
3927 enum i40e_status_code
3928 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3929 struct i40e_dma_mem *mem)
3932 return I40E_ERR_PARAM;
3935 "memzone %s to be freed with physical address: %"PRIu64,
3936 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3937 rte_memzone_free((const struct rte_memzone *)mem->zone);
3942 return I40E_SUCCESS;
3946 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3947 * @hw: pointer to the HW structure
3948 * @mem: pointer to mem struct to fill out
3949 * @size: size of memory requested
3951 enum i40e_status_code
3952 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3953 struct i40e_virt_mem *mem,
3957 return I40E_ERR_PARAM;
3960 mem->va = rte_zmalloc("i40e", size, 0);
3963 return I40E_SUCCESS;
3965 return I40E_ERR_NO_MEMORY;
3969 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3970 * @hw: pointer to the HW structure
3971 * @mem: pointer to mem struct to free
3973 enum i40e_status_code
3974 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3975 struct i40e_virt_mem *mem)
3978 return I40E_ERR_PARAM;
3983 return I40E_SUCCESS;
3987 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3989 rte_spinlock_init(&sp->spinlock);
3993 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3995 rte_spinlock_lock(&sp->spinlock);
3999 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4001 rte_spinlock_unlock(&sp->spinlock);
4005 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4011 * Get the hardware capabilities, which will be parsed
4012 * and saved into struct i40e_hw.
4015 i40e_get_cap(struct i40e_hw *hw)
4017 struct i40e_aqc_list_capabilities_element_resp *buf;
4018 uint16_t len, size = 0;
4021 /* Calculate a huge enough buff for saving response data temporarily */
4022 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4023 I40E_MAX_CAP_ELE_NUM;
4024 buf = rte_zmalloc("i40e", len, 0);
4026 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4027 return I40E_ERR_NO_MEMORY;
4030 /* Get, parse the capabilities and save it to hw */
4031 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4032 i40e_aqc_opc_list_func_capabilities, NULL);
4033 if (ret != I40E_SUCCESS)
4034 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4036 /* Free the temporary buffer after being used */
4042 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4
4043 #define QUEUE_NUM_PER_VF_ARG "queue-num-per-vf"
4044 RTE_PMD_REGISTER_PARAM_STRING(net_i40e, QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16");
4046 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4054 pf = (struct i40e_pf *)opaque;
4058 num = strtoul(value, &end, 0);
4059 if (errno != 0 || end == value || *end != 0) {
4060 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4061 "kept the value = %hu", value, pf->vf_nb_qp_max);
4065 if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4066 pf->vf_nb_qp_max = (uint16_t)num;
4068 /* here return 0 to make next valid same argument work */
4069 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4070 "power of 2 and equal or less than 16 !, Now it is "
4071 "kept the value = %hu", num, pf->vf_nb_qp_max);
4076 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4078 static const char * const valid_keys[] = {QUEUE_NUM_PER_VF_ARG, NULL};
4079 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4080 struct rte_kvargs *kvlist;
4082 /* set default queue number per VF as 4 */
4083 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4085 if (dev->device->devargs == NULL)
4088 kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4092 if (rte_kvargs_count(kvlist, QUEUE_NUM_PER_VF_ARG) > 1)
4093 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4094 "the first invalid or last valid one is used !",
4095 QUEUE_NUM_PER_VF_ARG);
4097 rte_kvargs_process(kvlist, QUEUE_NUM_PER_VF_ARG,
4098 i40e_pf_parse_vf_queue_number_handler, pf);
4100 rte_kvargs_free(kvlist);
4106 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4108 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4109 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4110 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4111 uint16_t qp_count = 0, vsi_count = 0;
4113 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4114 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4118 i40e_pf_config_vf_rxq_number(dev);
4120 /* Add the parameter init for LFC */
4121 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4122 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4123 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4125 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4126 pf->max_num_vsi = hw->func_caps.num_vsis;
4127 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4128 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4130 /* FDir queue/VSI allocation */
4131 pf->fdir_qp_offset = 0;
4132 if (hw->func_caps.fd) {
4133 pf->flags |= I40E_FLAG_FDIR;
4134 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4136 pf->fdir_nb_qps = 0;
4138 qp_count += pf->fdir_nb_qps;
4141 /* LAN queue/VSI allocation */
4142 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4143 if (!hw->func_caps.rss) {
4146 pf->flags |= I40E_FLAG_RSS;
4147 if (hw->mac.type == I40E_MAC_X722)
4148 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4149 pf->lan_nb_qps = pf->lan_nb_qp_max;
4151 qp_count += pf->lan_nb_qps;
4154 /* VF queue/VSI allocation */
4155 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4156 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4157 pf->flags |= I40E_FLAG_SRIOV;
4158 pf->vf_nb_qps = pf->vf_nb_qp_max;
4159 pf->vf_num = pci_dev->max_vfs;
4161 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4162 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4167 qp_count += pf->vf_nb_qps * pf->vf_num;
4168 vsi_count += pf->vf_num;
4170 /* VMDq queue/VSI allocation */
4171 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4172 pf->vmdq_nb_qps = 0;
4173 pf->max_nb_vmdq_vsi = 0;
4174 if (hw->func_caps.vmdq) {
4175 if (qp_count < hw->func_caps.num_tx_qp &&
4176 vsi_count < hw->func_caps.num_vsis) {
4177 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4178 qp_count) / pf->vmdq_nb_qp_max;
4180 /* Limit the maximum number of VMDq vsi to the maximum
4181 * ethdev can support
4183 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4184 hw->func_caps.num_vsis - vsi_count);
4185 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4187 if (pf->max_nb_vmdq_vsi) {
4188 pf->flags |= I40E_FLAG_VMDQ;
4189 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4191 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4192 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4193 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4196 "No enough queues left for VMDq");
4199 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4202 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4203 vsi_count += pf->max_nb_vmdq_vsi;
4205 if (hw->func_caps.dcb)
4206 pf->flags |= I40E_FLAG_DCB;
4208 if (qp_count > hw->func_caps.num_tx_qp) {
4210 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4211 qp_count, hw->func_caps.num_tx_qp);
4214 if (vsi_count > hw->func_caps.num_vsis) {
4216 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4217 vsi_count, hw->func_caps.num_vsis);
4225 i40e_pf_get_switch_config(struct i40e_pf *pf)
4227 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4228 struct i40e_aqc_get_switch_config_resp *switch_config;
4229 struct i40e_aqc_switch_config_element_resp *element;
4230 uint16_t start_seid = 0, num_reported;
4233 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4234 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4235 if (!switch_config) {
4236 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4240 /* Get the switch configurations */
4241 ret = i40e_aq_get_switch_config(hw, switch_config,
4242 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4243 if (ret != I40E_SUCCESS) {
4244 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4247 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4248 if (num_reported != 1) { /* The number should be 1 */
4249 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4253 /* Parse the switch configuration elements */
4254 element = &(switch_config->element[0]);
4255 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4256 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4257 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4259 PMD_DRV_LOG(INFO, "Unknown element type");
4262 rte_free(switch_config);
4268 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4271 struct pool_entry *entry;
4273 if (pool == NULL || num == 0)
4276 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4277 if (entry == NULL) {
4278 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4282 /* queue heap initialize */
4283 pool->num_free = num;
4284 pool->num_alloc = 0;
4286 LIST_INIT(&pool->alloc_list);
4287 LIST_INIT(&pool->free_list);
4289 /* Initialize element */
4293 LIST_INSERT_HEAD(&pool->free_list, entry, next);
4298 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4300 struct pool_entry *entry, *next_entry;
4305 for (entry = LIST_FIRST(&pool->alloc_list);
4306 entry && (next_entry = LIST_NEXT(entry, next), 1);
4307 entry = next_entry) {
4308 LIST_REMOVE(entry, next);
4312 for (entry = LIST_FIRST(&pool->free_list);
4313 entry && (next_entry = LIST_NEXT(entry, next), 1);
4314 entry = next_entry) {
4315 LIST_REMOVE(entry, next);
4320 pool->num_alloc = 0;
4322 LIST_INIT(&pool->alloc_list);
4323 LIST_INIT(&pool->free_list);
4327 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4330 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4331 uint32_t pool_offset;
4335 PMD_DRV_LOG(ERR, "Invalid parameter");
4339 pool_offset = base - pool->base;
4340 /* Lookup in alloc list */
4341 LIST_FOREACH(entry, &pool->alloc_list, next) {
4342 if (entry->base == pool_offset) {
4343 valid_entry = entry;
4344 LIST_REMOVE(entry, next);
4349 /* Not find, return */
4350 if (valid_entry == NULL) {
4351 PMD_DRV_LOG(ERR, "Failed to find entry");
4356 * Found it, move it to free list and try to merge.
4357 * In order to make merge easier, always sort it by qbase.
4358 * Find adjacent prev and last entries.
4361 LIST_FOREACH(entry, &pool->free_list, next) {
4362 if (entry->base > valid_entry->base) {
4370 /* Try to merge with next one*/
4372 /* Merge with next one */
4373 if (valid_entry->base + valid_entry->len == next->base) {
4374 next->base = valid_entry->base;
4375 next->len += valid_entry->len;
4376 rte_free(valid_entry);
4383 /* Merge with previous one */
4384 if (prev->base + prev->len == valid_entry->base) {
4385 prev->len += valid_entry->len;
4386 /* If it merge with next one, remove next node */
4388 LIST_REMOVE(valid_entry, next);
4389 rte_free(valid_entry);
4391 rte_free(valid_entry);
4397 /* Not find any entry to merge, insert */
4400 LIST_INSERT_AFTER(prev, valid_entry, next);
4401 else if (next != NULL)
4402 LIST_INSERT_BEFORE(next, valid_entry, next);
4403 else /* It's empty list, insert to head */
4404 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4407 pool->num_free += valid_entry->len;
4408 pool->num_alloc -= valid_entry->len;
4414 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4417 struct pool_entry *entry, *valid_entry;
4419 if (pool == NULL || num == 0) {
4420 PMD_DRV_LOG(ERR, "Invalid parameter");
4424 if (pool->num_free < num) {
4425 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4426 num, pool->num_free);
4431 /* Lookup in free list and find most fit one */
4432 LIST_FOREACH(entry, &pool->free_list, next) {
4433 if (entry->len >= num) {
4435 if (entry->len == num) {
4436 valid_entry = entry;
4439 if (valid_entry == NULL || valid_entry->len > entry->len)
4440 valid_entry = entry;
4444 /* Not find one to satisfy the request, return */
4445 if (valid_entry == NULL) {
4446 PMD_DRV_LOG(ERR, "No valid entry found");
4450 * The entry have equal queue number as requested,
4451 * remove it from alloc_list.
4453 if (valid_entry->len == num) {
4454 LIST_REMOVE(valid_entry, next);
4457 * The entry have more numbers than requested,
4458 * create a new entry for alloc_list and minus its
4459 * queue base and number in free_list.
4461 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4462 if (entry == NULL) {
4464 "Failed to allocate memory for resource pool");
4467 entry->base = valid_entry->base;
4469 valid_entry->base += num;
4470 valid_entry->len -= num;
4471 valid_entry = entry;
4474 /* Insert it into alloc list, not sorted */
4475 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4477 pool->num_free -= valid_entry->len;
4478 pool->num_alloc += valid_entry->len;
4480 return valid_entry->base + pool->base;
4484 * bitmap_is_subset - Check whether src2 is subset of src1
4487 bitmap_is_subset(uint8_t src1, uint8_t src2)
4489 return !((src1 ^ src2) & src2);
4492 static enum i40e_status_code
4493 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4495 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4497 /* If DCB is not supported, only default TC is supported */
4498 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4499 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4500 return I40E_NOT_SUPPORTED;
4503 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4505 "Enabled TC map 0x%x not applicable to HW support 0x%x",
4506 hw->func_caps.enabled_tcmap, enabled_tcmap);
4507 return I40E_NOT_SUPPORTED;
4509 return I40E_SUCCESS;
4513 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4514 struct i40e_vsi_vlan_pvid_info *info)
4517 struct i40e_vsi_context ctxt;
4518 uint8_t vlan_flags = 0;
4521 if (vsi == NULL || info == NULL) {
4522 PMD_DRV_LOG(ERR, "invalid parameters");
4523 return I40E_ERR_PARAM;
4527 vsi->info.pvid = info->config.pvid;
4529 * If insert pvid is enabled, only tagged pkts are
4530 * allowed to be sent out.
4532 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4533 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4536 if (info->config.reject.tagged == 0)
4537 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4539 if (info->config.reject.untagged == 0)
4540 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4542 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4543 I40E_AQ_VSI_PVLAN_MODE_MASK);
4544 vsi->info.port_vlan_flags |= vlan_flags;
4545 vsi->info.valid_sections =
4546 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4547 memset(&ctxt, 0, sizeof(ctxt));
4548 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4549 ctxt.seid = vsi->seid;
4551 hw = I40E_VSI_TO_HW(vsi);
4552 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4553 if (ret != I40E_SUCCESS)
4554 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4560 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4562 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4564 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4566 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4567 if (ret != I40E_SUCCESS)
4571 PMD_DRV_LOG(ERR, "seid not valid");
4575 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4576 tc_bw_data.tc_valid_bits = enabled_tcmap;
4577 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4578 tc_bw_data.tc_bw_credits[i] =
4579 (enabled_tcmap & (1 << i)) ? 1 : 0;
4581 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4582 if (ret != I40E_SUCCESS) {
4583 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4587 rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4588 sizeof(vsi->info.qs_handle));
4589 return I40E_SUCCESS;
4592 static enum i40e_status_code
4593 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4594 struct i40e_aqc_vsi_properties_data *info,
4595 uint8_t enabled_tcmap)
4597 enum i40e_status_code ret;
4598 int i, total_tc = 0;
4599 uint16_t qpnum_per_tc, bsf, qp_idx;
4601 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4602 if (ret != I40E_SUCCESS)
4605 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4606 if (enabled_tcmap & (1 << i))
4610 vsi->enabled_tc = enabled_tcmap;
4612 /* Number of queues per enabled TC */
4613 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4614 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4615 bsf = rte_bsf32(qpnum_per_tc);
4617 /* Adjust the queue number to actual queues that can be applied */
4618 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4619 vsi->nb_qps = qpnum_per_tc * total_tc;
4622 * Configure TC and queue mapping parameters, for enabled TC,
4623 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4624 * default queue will serve it.
4627 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4628 if (vsi->enabled_tc & (1 << i)) {
4629 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4630 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4631 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4632 qp_idx += qpnum_per_tc;
4634 info->tc_mapping[i] = 0;
4637 /* Associate queue number with VSI */
4638 if (vsi->type == I40E_VSI_SRIOV) {
4639 info->mapping_flags |=
4640 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4641 for (i = 0; i < vsi->nb_qps; i++)
4642 info->queue_mapping[i] =
4643 rte_cpu_to_le_16(vsi->base_queue + i);
4645 info->mapping_flags |=
4646 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4647 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4649 info->valid_sections |=
4650 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4652 return I40E_SUCCESS;
4656 i40e_veb_release(struct i40e_veb *veb)
4658 struct i40e_vsi *vsi;
4664 if (!TAILQ_EMPTY(&veb->head)) {
4665 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4668 /* associate_vsi field is NULL for floating VEB */
4669 if (veb->associate_vsi != NULL) {
4670 vsi = veb->associate_vsi;
4671 hw = I40E_VSI_TO_HW(vsi);
4673 vsi->uplink_seid = veb->uplink_seid;
4676 veb->associate_pf->main_vsi->floating_veb = NULL;
4677 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4680 i40e_aq_delete_element(hw, veb->seid, NULL);
4682 return I40E_SUCCESS;
4686 static struct i40e_veb *
4687 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4689 struct i40e_veb *veb;
4695 "veb setup failed, associated PF shouldn't null");
4698 hw = I40E_PF_TO_HW(pf);
4700 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4702 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4706 veb->associate_vsi = vsi;
4707 veb->associate_pf = pf;
4708 TAILQ_INIT(&veb->head);
4709 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4711 /* create floating veb if vsi is NULL */
4713 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4714 I40E_DEFAULT_TCMAP, false,
4715 &veb->seid, false, NULL);
4717 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4718 true, &veb->seid, false, NULL);
4721 if (ret != I40E_SUCCESS) {
4722 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4723 hw->aq.asq_last_status);
4726 veb->enabled_tc = I40E_DEFAULT_TCMAP;
4728 /* get statistics index */
4729 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4730 &veb->stats_idx, NULL, NULL, NULL);
4731 if (ret != I40E_SUCCESS) {
4732 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4733 hw->aq.asq_last_status);
4736 /* Get VEB bandwidth, to be implemented */
4737 /* Now associated vsi binding to the VEB, set uplink to this VEB */
4739 vsi->uplink_seid = veb->seid;
4748 i40e_vsi_release(struct i40e_vsi *vsi)
4752 struct i40e_vsi_list *vsi_list;
4755 struct i40e_mac_filter *f;
4756 uint16_t user_param;
4759 return I40E_SUCCESS;
4764 user_param = vsi->user_param;
4766 pf = I40E_VSI_TO_PF(vsi);
4767 hw = I40E_VSI_TO_HW(vsi);
4769 /* VSI has child to attach, release child first */
4771 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4772 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4775 i40e_veb_release(vsi->veb);
4778 if (vsi->floating_veb) {
4779 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4780 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4785 /* Remove all macvlan filters of the VSI */
4786 i40e_vsi_remove_all_macvlan_filter(vsi);
4787 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4790 if (vsi->type != I40E_VSI_MAIN &&
4791 ((vsi->type != I40E_VSI_SRIOV) ||
4792 !pf->floating_veb_list[user_param])) {
4793 /* Remove vsi from parent's sibling list */
4794 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4795 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4796 return I40E_ERR_PARAM;
4798 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4799 &vsi->sib_vsi_list, list);
4801 /* Remove all switch element of the VSI */
4802 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4803 if (ret != I40E_SUCCESS)
4804 PMD_DRV_LOG(ERR, "Failed to delete element");
4807 if ((vsi->type == I40E_VSI_SRIOV) &&
4808 pf->floating_veb_list[user_param]) {
4809 /* Remove vsi from parent's sibling list */
4810 if (vsi->parent_vsi == NULL ||
4811 vsi->parent_vsi->floating_veb == NULL) {
4812 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4813 return I40E_ERR_PARAM;
4815 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4816 &vsi->sib_vsi_list, list);
4818 /* Remove all switch element of the VSI */
4819 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4820 if (ret != I40E_SUCCESS)
4821 PMD_DRV_LOG(ERR, "Failed to delete element");
4824 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4826 if (vsi->type != I40E_VSI_SRIOV)
4827 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4830 return I40E_SUCCESS;
4834 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4836 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4837 struct i40e_aqc_remove_macvlan_element_data def_filter;
4838 struct i40e_mac_filter_info filter;
4841 if (vsi->type != I40E_VSI_MAIN)
4842 return I40E_ERR_CONFIG;
4843 memset(&def_filter, 0, sizeof(def_filter));
4844 rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4846 def_filter.vlan_tag = 0;
4847 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4848 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4849 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4850 if (ret != I40E_SUCCESS) {
4851 struct i40e_mac_filter *f;
4852 struct ether_addr *mac;
4855 "Cannot remove the default macvlan filter");
4856 /* It needs to add the permanent mac into mac list */
4857 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4859 PMD_DRV_LOG(ERR, "failed to allocate memory");
4860 return I40E_ERR_NO_MEMORY;
4862 mac = &f->mac_info.mac_addr;
4863 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4865 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4866 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4871 rte_memcpy(&filter.mac_addr,
4872 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4873 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4874 return i40e_vsi_add_mac(vsi, &filter);
4878 * i40e_vsi_get_bw_config - Query VSI BW Information
4879 * @vsi: the VSI to be queried
4881 * Returns 0 on success, negative value on failure
4883 static enum i40e_status_code
4884 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4886 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4887 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4888 struct i40e_hw *hw = &vsi->adapter->hw;
4893 memset(&bw_config, 0, sizeof(bw_config));
4894 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4895 if (ret != I40E_SUCCESS) {
4896 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4897 hw->aq.asq_last_status);
4901 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4902 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4903 &ets_sla_config, NULL);
4904 if (ret != I40E_SUCCESS) {
4906 "VSI failed to get TC bandwdith configuration %u",
4907 hw->aq.asq_last_status);
4911 /* store and print out BW info */
4912 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4913 vsi->bw_info.bw_max = bw_config.max_bw;
4914 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4915 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4916 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4917 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4919 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4920 vsi->bw_info.bw_ets_share_credits[i] =
4921 ets_sla_config.share_credits[i];
4922 vsi->bw_info.bw_ets_credits[i] =
4923 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4924 /* 4 bits per TC, 4th bit is reserved */
4925 vsi->bw_info.bw_ets_max[i] =
4926 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4927 RTE_LEN2MASK(3, uint8_t));
4928 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4929 vsi->bw_info.bw_ets_share_credits[i]);
4930 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4931 vsi->bw_info.bw_ets_credits[i]);
4932 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4933 vsi->bw_info.bw_ets_max[i]);
4936 return I40E_SUCCESS;
4939 /* i40e_enable_pf_lb
4940 * @pf: pointer to the pf structure
4942 * allow loopback on pf
4945 i40e_enable_pf_lb(struct i40e_pf *pf)
4947 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4948 struct i40e_vsi_context ctxt;
4951 /* Use the FW API if FW >= v5.0 */
4952 if (hw->aq.fw_maj_ver < 5) {
4953 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4957 memset(&ctxt, 0, sizeof(ctxt));
4958 ctxt.seid = pf->main_vsi_seid;
4959 ctxt.pf_num = hw->pf_id;
4960 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4962 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4963 ret, hw->aq.asq_last_status);
4966 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4967 ctxt.info.valid_sections =
4968 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4969 ctxt.info.switch_id |=
4970 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4972 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4974 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4975 hw->aq.asq_last_status);
4980 i40e_vsi_setup(struct i40e_pf *pf,
4981 enum i40e_vsi_type type,
4982 struct i40e_vsi *uplink_vsi,
4983 uint16_t user_param)
4985 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4986 struct i40e_vsi *vsi;
4987 struct i40e_mac_filter_info filter;
4989 struct i40e_vsi_context ctxt;
4990 struct ether_addr broadcast =
4991 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4993 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4994 uplink_vsi == NULL) {
4996 "VSI setup failed, VSI link shouldn't be NULL");
5000 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5002 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5007 * 1.type is not MAIN and uplink vsi is not NULL
5008 * If uplink vsi didn't setup VEB, create one first under veb field
5009 * 2.type is SRIOV and the uplink is NULL
5010 * If floating VEB is NULL, create one veb under floating veb field
5013 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5014 uplink_vsi->veb == NULL) {
5015 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5017 if (uplink_vsi->veb == NULL) {
5018 PMD_DRV_LOG(ERR, "VEB setup failed");
5021 /* set ALLOWLOOPBACk on pf, when veb is created */
5022 i40e_enable_pf_lb(pf);
5025 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5026 pf->main_vsi->floating_veb == NULL) {
5027 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5029 if (pf->main_vsi->floating_veb == NULL) {
5030 PMD_DRV_LOG(ERR, "VEB setup failed");
5035 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5037 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5040 TAILQ_INIT(&vsi->mac_list);
5042 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5043 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5044 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5045 vsi->user_param = user_param;
5046 vsi->vlan_anti_spoof_on = 0;
5047 vsi->vlan_filter_on = 0;
5048 /* Allocate queues */
5049 switch (vsi->type) {
5050 case I40E_VSI_MAIN :
5051 vsi->nb_qps = pf->lan_nb_qps;
5053 case I40E_VSI_SRIOV :
5054 vsi->nb_qps = pf->vf_nb_qps;
5056 case I40E_VSI_VMDQ2:
5057 vsi->nb_qps = pf->vmdq_nb_qps;
5060 vsi->nb_qps = pf->fdir_nb_qps;
5066 * The filter status descriptor is reported in rx queue 0,
5067 * while the tx queue for fdir filter programming has no
5068 * such constraints, can be non-zero queues.
5069 * To simplify it, choose FDIR vsi use queue 0 pair.
5070 * To make sure it will use queue 0 pair, queue allocation
5071 * need be done before this function is called
5073 if (type != I40E_VSI_FDIR) {
5074 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5076 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5080 vsi->base_queue = ret;
5082 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5084 /* VF has MSIX interrupt in VF range, don't allocate here */
5085 if (type == I40E_VSI_MAIN) {
5086 ret = i40e_res_pool_alloc(&pf->msix_pool,
5087 RTE_MIN(vsi->nb_qps,
5088 RTE_MAX_RXTX_INTR_VEC_ID));
5090 PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
5092 goto fail_queue_alloc;
5094 vsi->msix_intr = ret;
5095 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
5096 } else if (type != I40E_VSI_SRIOV) {
5097 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5099 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5100 goto fail_queue_alloc;
5102 vsi->msix_intr = ret;
5110 if (type == I40E_VSI_MAIN) {
5111 /* For main VSI, no need to add since it's default one */
5112 vsi->uplink_seid = pf->mac_seid;
5113 vsi->seid = pf->main_vsi_seid;
5114 /* Bind queues with specific MSIX interrupt */
5116 * Needs 2 interrupt at least, one for misc cause which will
5117 * enabled from OS side, Another for queues binding the
5118 * interrupt from device side only.
5121 /* Get default VSI parameters from hardware */
5122 memset(&ctxt, 0, sizeof(ctxt));
5123 ctxt.seid = vsi->seid;
5124 ctxt.pf_num = hw->pf_id;
5125 ctxt.uplink_seid = vsi->uplink_seid;
5127 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5128 if (ret != I40E_SUCCESS) {
5129 PMD_DRV_LOG(ERR, "Failed to get VSI params");
5130 goto fail_msix_alloc;
5132 rte_memcpy(&vsi->info, &ctxt.info,
5133 sizeof(struct i40e_aqc_vsi_properties_data));
5134 vsi->vsi_id = ctxt.vsi_number;
5135 vsi->info.valid_sections = 0;
5137 /* Configure tc, enabled TC0 only */
5138 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5140 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5141 goto fail_msix_alloc;
5144 /* TC, queue mapping */
5145 memset(&ctxt, 0, sizeof(ctxt));
5146 vsi->info.valid_sections |=
5147 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5148 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5149 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5150 rte_memcpy(&ctxt.info, &vsi->info,
5151 sizeof(struct i40e_aqc_vsi_properties_data));
5152 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5153 I40E_DEFAULT_TCMAP);
5154 if (ret != I40E_SUCCESS) {
5156 "Failed to configure TC queue mapping");
5157 goto fail_msix_alloc;
5159 ctxt.seid = vsi->seid;
5160 ctxt.pf_num = hw->pf_id;
5161 ctxt.uplink_seid = vsi->uplink_seid;
5164 /* Update VSI parameters */
5165 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5166 if (ret != I40E_SUCCESS) {
5167 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5168 goto fail_msix_alloc;
5171 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5172 sizeof(vsi->info.tc_mapping));
5173 rte_memcpy(&vsi->info.queue_mapping,
5174 &ctxt.info.queue_mapping,
5175 sizeof(vsi->info.queue_mapping));
5176 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5177 vsi->info.valid_sections = 0;
5179 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5183 * Updating default filter settings are necessary to prevent
5184 * reception of tagged packets.
5185 * Some old firmware configurations load a default macvlan
5186 * filter which accepts both tagged and untagged packets.
5187 * The updating is to use a normal filter instead if needed.
5188 * For NVM 4.2.2 or after, the updating is not needed anymore.
5189 * The firmware with correct configurations load the default
5190 * macvlan filter which is expected and cannot be removed.
5192 i40e_update_default_filter_setting(vsi);
5193 i40e_config_qinq(hw, vsi);
5194 } else if (type == I40E_VSI_SRIOV) {
5195 memset(&ctxt, 0, sizeof(ctxt));
5197 * For other VSI, the uplink_seid equals to uplink VSI's
5198 * uplink_seid since they share same VEB
5200 if (uplink_vsi == NULL)
5201 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5203 vsi->uplink_seid = uplink_vsi->uplink_seid;
5204 ctxt.pf_num = hw->pf_id;
5205 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5206 ctxt.uplink_seid = vsi->uplink_seid;
5207 ctxt.connection_type = 0x1;
5208 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5210 /* Use the VEB configuration if FW >= v5.0 */
5211 if (hw->aq.fw_maj_ver >= 5) {
5212 /* Configure switch ID */
5213 ctxt.info.valid_sections |=
5214 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5215 ctxt.info.switch_id =
5216 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5219 /* Configure port/vlan */
5220 ctxt.info.valid_sections |=
5221 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5222 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5223 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5224 hw->func_caps.enabled_tcmap);
5225 if (ret != I40E_SUCCESS) {
5227 "Failed to configure TC queue mapping");
5228 goto fail_msix_alloc;
5231 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5232 ctxt.info.valid_sections |=
5233 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5235 * Since VSI is not created yet, only configure parameter,
5236 * will add vsi below.
5239 i40e_config_qinq(hw, vsi);
5240 } else if (type == I40E_VSI_VMDQ2) {
5241 memset(&ctxt, 0, sizeof(ctxt));
5243 * For other VSI, the uplink_seid equals to uplink VSI's
5244 * uplink_seid since they share same VEB
5246 vsi->uplink_seid = uplink_vsi->uplink_seid;
5247 ctxt.pf_num = hw->pf_id;
5249 ctxt.uplink_seid = vsi->uplink_seid;
5250 ctxt.connection_type = 0x1;
5251 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5253 ctxt.info.valid_sections |=
5254 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5255 /* user_param carries flag to enable loop back */
5257 ctxt.info.switch_id =
5258 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5259 ctxt.info.switch_id |=
5260 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5263 /* Configure port/vlan */
5264 ctxt.info.valid_sections |=
5265 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5266 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5267 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5268 I40E_DEFAULT_TCMAP);
5269 if (ret != I40E_SUCCESS) {
5271 "Failed to configure TC queue mapping");
5272 goto fail_msix_alloc;
5274 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5275 ctxt.info.valid_sections |=
5276 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5277 } else if (type == I40E_VSI_FDIR) {
5278 memset(&ctxt, 0, sizeof(ctxt));
5279 vsi->uplink_seid = uplink_vsi->uplink_seid;
5280 ctxt.pf_num = hw->pf_id;
5282 ctxt.uplink_seid = vsi->uplink_seid;
5283 ctxt.connection_type = 0x1; /* regular data port */
5284 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5285 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5286 I40E_DEFAULT_TCMAP);
5287 if (ret != I40E_SUCCESS) {
5289 "Failed to configure TC queue mapping.");
5290 goto fail_msix_alloc;
5292 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5293 ctxt.info.valid_sections |=
5294 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5296 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5297 goto fail_msix_alloc;
5300 if (vsi->type != I40E_VSI_MAIN) {
5301 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5302 if (ret != I40E_SUCCESS) {
5303 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5304 hw->aq.asq_last_status);
5305 goto fail_msix_alloc;
5307 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5308 vsi->info.valid_sections = 0;
5309 vsi->seid = ctxt.seid;
5310 vsi->vsi_id = ctxt.vsi_number;
5311 vsi->sib_vsi_list.vsi = vsi;
5312 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5313 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5314 &vsi->sib_vsi_list, list);
5316 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5317 &vsi->sib_vsi_list, list);
5321 /* MAC/VLAN configuration */
5322 rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5323 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5325 ret = i40e_vsi_add_mac(vsi, &filter);
5326 if (ret != I40E_SUCCESS) {
5327 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5328 goto fail_msix_alloc;
5331 /* Get VSI BW information */
5332 i40e_vsi_get_bw_config(vsi);
5335 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5337 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5343 /* Configure vlan filter on or off */
5345 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5348 struct i40e_mac_filter *f;
5350 struct i40e_mac_filter_info *mac_filter;
5351 enum rte_mac_filter_type desired_filter;
5352 int ret = I40E_SUCCESS;
5355 /* Filter to match MAC and VLAN */
5356 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5358 /* Filter to match only MAC */
5359 desired_filter = RTE_MAC_PERFECT_MATCH;
5364 mac_filter = rte_zmalloc("mac_filter_info_data",
5365 num * sizeof(*mac_filter), 0);
5366 if (mac_filter == NULL) {
5367 PMD_DRV_LOG(ERR, "failed to allocate memory");
5368 return I40E_ERR_NO_MEMORY;
5373 /* Remove all existing mac */
5374 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5375 mac_filter[i] = f->mac_info;
5376 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5378 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5379 on ? "enable" : "disable");
5385 /* Override with new filter */
5386 for (i = 0; i < num; i++) {
5387 mac_filter[i].filter_type = desired_filter;
5388 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5390 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5391 on ? "enable" : "disable");
5397 rte_free(mac_filter);
5401 /* Configure vlan stripping on or off */
5403 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5405 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5406 struct i40e_vsi_context ctxt;
5408 int ret = I40E_SUCCESS;
5410 /* Check if it has been already on or off */
5411 if (vsi->info.valid_sections &
5412 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5414 if ((vsi->info.port_vlan_flags &
5415 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5416 return 0; /* already on */
5418 if ((vsi->info.port_vlan_flags &
5419 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5420 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5421 return 0; /* already off */
5426 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5428 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5429 vsi->info.valid_sections =
5430 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5431 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5432 vsi->info.port_vlan_flags |= vlan_flags;
5433 ctxt.seid = vsi->seid;
5434 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5435 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5437 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5438 on ? "enable" : "disable");
5444 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5446 struct rte_eth_dev_data *data = dev->data;
5450 /* Apply vlan offload setting */
5451 mask = ETH_VLAN_STRIP_MASK |
5452 ETH_VLAN_FILTER_MASK |
5453 ETH_VLAN_EXTEND_MASK;
5454 ret = i40e_vlan_offload_set(dev, mask);
5456 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5460 /* Apply pvid setting */
5461 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5462 data->dev_conf.txmode.hw_vlan_insert_pvid);
5464 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5470 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5472 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5474 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5478 i40e_update_flow_control(struct i40e_hw *hw)
5480 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5481 struct i40e_link_status link_status;
5482 uint32_t rxfc = 0, txfc = 0, reg;
5486 memset(&link_status, 0, sizeof(link_status));
5487 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5488 if (ret != I40E_SUCCESS) {
5489 PMD_DRV_LOG(ERR, "Failed to get link status information");
5490 goto write_reg; /* Disable flow control */
5493 an_info = hw->phy.link_info.an_info;
5494 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5495 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5496 ret = I40E_ERR_NOT_READY;
5497 goto write_reg; /* Disable flow control */
5500 * If link auto negotiation is enabled, flow control needs to
5501 * be configured according to it
5503 switch (an_info & I40E_LINK_PAUSE_RXTX) {
5504 case I40E_LINK_PAUSE_RXTX:
5507 hw->fc.current_mode = I40E_FC_FULL;
5509 case I40E_AQ_LINK_PAUSE_RX:
5511 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5513 case I40E_AQ_LINK_PAUSE_TX:
5515 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5518 hw->fc.current_mode = I40E_FC_NONE;
5523 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5524 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5525 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5526 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5527 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5528 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5535 i40e_pf_setup(struct i40e_pf *pf)
5537 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5538 struct i40e_filter_control_settings settings;
5539 struct i40e_vsi *vsi;
5542 /* Clear all stats counters */
5543 pf->offset_loaded = FALSE;
5544 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5545 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5546 memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5547 memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5549 ret = i40e_pf_get_switch_config(pf);
5550 if (ret != I40E_SUCCESS) {
5551 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5554 if (pf->flags & I40E_FLAG_FDIR) {
5555 /* make queue allocated first, let FDIR use queue pair 0*/
5556 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5557 if (ret != I40E_FDIR_QUEUE_ID) {
5559 "queue allocation fails for FDIR: ret =%d",
5561 pf->flags &= ~I40E_FLAG_FDIR;
5564 /* main VSI setup */
5565 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5567 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5568 return I40E_ERR_NOT_READY;
5572 /* Configure filter control */
5573 memset(&settings, 0, sizeof(settings));
5574 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5575 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5576 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5577 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5579 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5580 hw->func_caps.rss_table_size);
5581 return I40E_ERR_PARAM;
5583 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5584 hw->func_caps.rss_table_size);
5585 pf->hash_lut_size = hw->func_caps.rss_table_size;
5587 /* Enable ethtype and macvlan filters */
5588 settings.enable_ethtype = TRUE;
5589 settings.enable_macvlan = TRUE;
5590 ret = i40e_set_filter_control(hw, &settings);
5592 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5595 /* Update flow control according to the auto negotiation */
5596 i40e_update_flow_control(hw);
5598 return I40E_SUCCESS;
5602 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5608 * Set or clear TX Queue Disable flags,
5609 * which is required by hardware.
5611 i40e_pre_tx_queue_cfg(hw, q_idx, on);
5612 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5614 /* Wait until the request is finished */
5615 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5616 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5617 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5618 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5619 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5625 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5626 return I40E_SUCCESS; /* already on, skip next steps */
5628 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5629 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5631 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5632 return I40E_SUCCESS; /* already off, skip next steps */
5633 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5635 /* Write the register */
5636 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5637 /* Check the result */
5638 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5639 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5640 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5642 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5643 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5646 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5647 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5651 /* Check if it is timeout */
5652 if (j >= I40E_CHK_Q_ENA_COUNT) {
5653 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5654 (on ? "enable" : "disable"), q_idx);
5655 return I40E_ERR_TIMEOUT;
5658 return I40E_SUCCESS;
5661 /* Swith on or off the tx queues */
5663 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5665 struct rte_eth_dev_data *dev_data = pf->dev_data;
5666 struct i40e_tx_queue *txq;
5667 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5671 for (i = 0; i < dev_data->nb_tx_queues; i++) {
5672 txq = dev_data->tx_queues[i];
5673 /* Don't operate the queue if not configured or
5674 * if starting only per queue */
5675 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5678 ret = i40e_dev_tx_queue_start(dev, i);
5680 ret = i40e_dev_tx_queue_stop(dev, i);
5681 if ( ret != I40E_SUCCESS)
5685 return I40E_SUCCESS;
5689 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5694 /* Wait until the request is finished */
5695 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5696 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5697 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5698 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5699 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5704 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5705 return I40E_SUCCESS; /* Already on, skip next steps */
5706 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5708 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5709 return I40E_SUCCESS; /* Already off, skip next steps */
5710 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5713 /* Write the register */
5714 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5715 /* Check the result */
5716 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5717 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5718 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5720 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5721 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5724 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5725 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5730 /* Check if it is timeout */
5731 if (j >= I40E_CHK_Q_ENA_COUNT) {
5732 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5733 (on ? "enable" : "disable"), q_idx);
5734 return I40E_ERR_TIMEOUT;
5737 return I40E_SUCCESS;
5739 /* Switch on or off the rx queues */
5741 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5743 struct rte_eth_dev_data *dev_data = pf->dev_data;
5744 struct i40e_rx_queue *rxq;
5745 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5749 for (i = 0; i < dev_data->nb_rx_queues; i++) {
5750 rxq = dev_data->rx_queues[i];
5751 /* Don't operate the queue if not configured or
5752 * if starting only per queue */
5753 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5756 ret = i40e_dev_rx_queue_start(dev, i);
5758 ret = i40e_dev_rx_queue_stop(dev, i);
5759 if (ret != I40E_SUCCESS)
5763 return I40E_SUCCESS;
5766 /* Switch on or off all the rx/tx queues */
5768 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5773 /* enable rx queues before enabling tx queues */
5774 ret = i40e_dev_switch_rx_queues(pf, on);
5776 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5779 ret = i40e_dev_switch_tx_queues(pf, on);
5781 /* Stop tx queues before stopping rx queues */
5782 ret = i40e_dev_switch_tx_queues(pf, on);
5784 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5787 ret = i40e_dev_switch_rx_queues(pf, on);
5793 /* Initialize VSI for TX */
5795 i40e_dev_tx_init(struct i40e_pf *pf)
5797 struct rte_eth_dev_data *data = pf->dev_data;
5799 uint32_t ret = I40E_SUCCESS;
5800 struct i40e_tx_queue *txq;
5802 for (i = 0; i < data->nb_tx_queues; i++) {
5803 txq = data->tx_queues[i];
5804 if (!txq || !txq->q_set)
5806 ret = i40e_tx_queue_init(txq);
5807 if (ret != I40E_SUCCESS)
5810 if (ret == I40E_SUCCESS)
5811 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5817 /* Initialize VSI for RX */
5819 i40e_dev_rx_init(struct i40e_pf *pf)
5821 struct rte_eth_dev_data *data = pf->dev_data;
5822 int ret = I40E_SUCCESS;
5824 struct i40e_rx_queue *rxq;
5826 i40e_pf_config_mq_rx(pf);
5827 for (i = 0; i < data->nb_rx_queues; i++) {
5828 rxq = data->rx_queues[i];
5829 if (!rxq || !rxq->q_set)
5832 ret = i40e_rx_queue_init(rxq);
5833 if (ret != I40E_SUCCESS) {
5835 "Failed to do RX queue initialization");
5839 if (ret == I40E_SUCCESS)
5840 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5847 i40e_dev_rxtx_init(struct i40e_pf *pf)
5851 err = i40e_dev_tx_init(pf);
5853 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5856 err = i40e_dev_rx_init(pf);
5858 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5866 i40e_vmdq_setup(struct rte_eth_dev *dev)
5868 struct rte_eth_conf *conf = &dev->data->dev_conf;
5869 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5870 int i, err, conf_vsis, j, loop;
5871 struct i40e_vsi *vsi;
5872 struct i40e_vmdq_info *vmdq_info;
5873 struct rte_eth_vmdq_rx_conf *vmdq_conf;
5874 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5877 * Disable interrupt to avoid message from VF. Furthermore, it will
5878 * avoid race condition in VSI creation/destroy.
5880 i40e_pf_disable_irq0(hw);
5882 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5883 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5887 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5888 if (conf_vsis > pf->max_nb_vmdq_vsi) {
5889 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5890 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5891 pf->max_nb_vmdq_vsi);
5895 if (pf->vmdq != NULL) {
5896 PMD_INIT_LOG(INFO, "VMDQ already configured");
5900 pf->vmdq = rte_zmalloc("vmdq_info_struct",
5901 sizeof(*vmdq_info) * conf_vsis, 0);
5903 if (pf->vmdq == NULL) {
5904 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5908 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5910 /* Create VMDQ VSI */
5911 for (i = 0; i < conf_vsis; i++) {
5912 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5913 vmdq_conf->enable_loop_back);
5915 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5919 vmdq_info = &pf->vmdq[i];
5921 vmdq_info->vsi = vsi;
5923 pf->nb_cfg_vmdq_vsi = conf_vsis;
5925 /* Configure Vlan */
5926 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5927 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5928 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5929 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5930 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5931 vmdq_conf->pool_map[i].vlan_id, j);
5933 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5934 vmdq_conf->pool_map[i].vlan_id);
5936 PMD_INIT_LOG(ERR, "Failed to add vlan");
5944 i40e_pf_enable_irq0(hw);
5949 for (i = 0; i < conf_vsis; i++)
5950 if (pf->vmdq[i].vsi == NULL)
5953 i40e_vsi_release(pf->vmdq[i].vsi);
5957 i40e_pf_enable_irq0(hw);
5962 i40e_stat_update_32(struct i40e_hw *hw,
5970 new_data = (uint64_t)I40E_READ_REG(hw, reg);
5974 if (new_data >= *offset)
5975 *stat = (uint64_t)(new_data - *offset);
5977 *stat = (uint64_t)((new_data +
5978 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5982 i40e_stat_update_48(struct i40e_hw *hw,
5991 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5992 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5993 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5998 if (new_data >= *offset)
5999 *stat = new_data - *offset;
6001 *stat = (uint64_t)((new_data +
6002 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6004 *stat &= I40E_48_BIT_MASK;
6009 i40e_pf_disable_irq0(struct i40e_hw *hw)
6011 /* Disable all interrupt types */
6012 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
6013 I40E_WRITE_FLUSH(hw);
6018 i40e_pf_enable_irq0(struct i40e_hw *hw)
6020 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6021 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6022 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6023 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6024 I40E_WRITE_FLUSH(hw);
6028 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6030 /* read pending request and disable first */
6031 i40e_pf_disable_irq0(hw);
6032 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6033 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6034 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6037 /* Link no queues with irq0 */
6038 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6039 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6043 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6045 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6046 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6049 uint32_t index, offset, val;
6054 * Try to find which VF trigger a reset, use absolute VF id to access
6055 * since the reg is global register.
6057 for (i = 0; i < pf->vf_num; i++) {
6058 abs_vf_id = hw->func_caps.vf_base_id + i;
6059 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6060 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6061 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6062 /* VFR event occurred */
6063 if (val & (0x1 << offset)) {
6066 /* Clear the event first */
6067 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6069 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6071 * Only notify a VF reset event occurred,
6072 * don't trigger another SW reset
6074 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6075 if (ret != I40E_SUCCESS)
6076 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6082 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6084 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6087 for (i = 0; i < pf->vf_num; i++)
6088 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6092 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6094 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6095 struct i40e_arq_event_info info;
6096 uint16_t pending, opcode;
6099 info.buf_len = I40E_AQ_BUF_SZ;
6100 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6101 if (!info.msg_buf) {
6102 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6108 ret = i40e_clean_arq_element(hw, &info, &pending);
6110 if (ret != I40E_SUCCESS) {
6112 "Failed to read msg from AdminQ, aq_err: %u",
6113 hw->aq.asq_last_status);
6116 opcode = rte_le_to_cpu_16(info.desc.opcode);
6119 case i40e_aqc_opc_send_msg_to_pf:
6120 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6121 i40e_pf_host_handle_vf_msg(dev,
6122 rte_le_to_cpu_16(info.desc.retval),
6123 rte_le_to_cpu_32(info.desc.cookie_high),
6124 rte_le_to_cpu_32(info.desc.cookie_low),
6128 case i40e_aqc_opc_get_link_status:
6129 ret = i40e_dev_link_update(dev, 0);
6131 _rte_eth_dev_callback_process(dev,
6132 RTE_ETH_EVENT_INTR_LSC, NULL);
6135 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6140 rte_free(info.msg_buf);
6144 * Interrupt handler triggered by NIC for handling
6145 * specific interrupt.
6148 * Pointer to interrupt handle.
6150 * The address of parameter (struct rte_eth_dev *) regsitered before.
6156 i40e_dev_interrupt_handler(void *param)
6158 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6159 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6162 /* Disable interrupt */
6163 i40e_pf_disable_irq0(hw);
6165 /* read out interrupt causes */
6166 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6168 /* No interrupt event indicated */
6169 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6170 PMD_DRV_LOG(INFO, "No interrupt event");
6173 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6174 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6175 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6176 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6177 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6178 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6179 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6180 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6181 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6182 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6183 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6184 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6185 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6186 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6188 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6189 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6190 i40e_dev_handle_vfr_event(dev);
6192 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6193 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6194 i40e_dev_handle_aq_msg(dev);
6198 /* Enable interrupt */
6199 i40e_pf_enable_irq0(hw);
6200 rte_intr_enable(dev->intr_handle);
6204 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6205 struct i40e_macvlan_filter *filter,
6208 int ele_num, ele_buff_size;
6209 int num, actual_num, i;
6211 int ret = I40E_SUCCESS;
6212 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6213 struct i40e_aqc_add_macvlan_element_data *req_list;
6215 if (filter == NULL || total == 0)
6216 return I40E_ERR_PARAM;
6217 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6218 ele_buff_size = hw->aq.asq_buf_size;
6220 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6221 if (req_list == NULL) {
6222 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6223 return I40E_ERR_NO_MEMORY;
6228 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6229 memset(req_list, 0, ele_buff_size);
6231 for (i = 0; i < actual_num; i++) {
6232 rte_memcpy(req_list[i].mac_addr,
6233 &filter[num + i].macaddr, ETH_ADDR_LEN);
6234 req_list[i].vlan_tag =
6235 rte_cpu_to_le_16(filter[num + i].vlan_id);
6237 switch (filter[num + i].filter_type) {
6238 case RTE_MAC_PERFECT_MATCH:
6239 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6240 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6242 case RTE_MACVLAN_PERFECT_MATCH:
6243 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6245 case RTE_MAC_HASH_MATCH:
6246 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6247 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6249 case RTE_MACVLAN_HASH_MATCH:
6250 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6253 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6254 ret = I40E_ERR_PARAM;
6258 req_list[i].queue_number = 0;
6260 req_list[i].flags = rte_cpu_to_le_16(flags);
6263 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6265 if (ret != I40E_SUCCESS) {
6266 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6270 } while (num < total);
6278 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6279 struct i40e_macvlan_filter *filter,
6282 int ele_num, ele_buff_size;
6283 int num, actual_num, i;
6285 int ret = I40E_SUCCESS;
6286 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6287 struct i40e_aqc_remove_macvlan_element_data *req_list;
6289 if (filter == NULL || total == 0)
6290 return I40E_ERR_PARAM;
6292 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6293 ele_buff_size = hw->aq.asq_buf_size;
6295 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6296 if (req_list == NULL) {
6297 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6298 return I40E_ERR_NO_MEMORY;
6303 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6304 memset(req_list, 0, ele_buff_size);
6306 for (i = 0; i < actual_num; i++) {
6307 rte_memcpy(req_list[i].mac_addr,
6308 &filter[num + i].macaddr, ETH_ADDR_LEN);
6309 req_list[i].vlan_tag =
6310 rte_cpu_to_le_16(filter[num + i].vlan_id);
6312 switch (filter[num + i].filter_type) {
6313 case RTE_MAC_PERFECT_MATCH:
6314 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6315 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6317 case RTE_MACVLAN_PERFECT_MATCH:
6318 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6320 case RTE_MAC_HASH_MATCH:
6321 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6322 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6324 case RTE_MACVLAN_HASH_MATCH:
6325 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6328 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6329 ret = I40E_ERR_PARAM;
6332 req_list[i].flags = rte_cpu_to_le_16(flags);
6335 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6337 if (ret != I40E_SUCCESS) {
6338 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6342 } while (num < total);
6349 /* Find out specific MAC filter */
6350 static struct i40e_mac_filter *
6351 i40e_find_mac_filter(struct i40e_vsi *vsi,
6352 struct ether_addr *macaddr)
6354 struct i40e_mac_filter *f;
6356 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6357 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6365 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6368 uint32_t vid_idx, vid_bit;
6370 if (vlan_id > ETH_VLAN_ID_MAX)
6373 vid_idx = I40E_VFTA_IDX(vlan_id);
6374 vid_bit = I40E_VFTA_BIT(vlan_id);
6376 if (vsi->vfta[vid_idx] & vid_bit)
6383 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6384 uint16_t vlan_id, bool on)
6386 uint32_t vid_idx, vid_bit;
6388 vid_idx = I40E_VFTA_IDX(vlan_id);
6389 vid_bit = I40E_VFTA_BIT(vlan_id);
6392 vsi->vfta[vid_idx] |= vid_bit;
6394 vsi->vfta[vid_idx] &= ~vid_bit;
6398 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6399 uint16_t vlan_id, bool on)
6401 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6402 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6405 if (vlan_id > ETH_VLAN_ID_MAX)
6408 i40e_store_vlan_filter(vsi, vlan_id, on);
6410 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6413 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6416 ret = i40e_aq_add_vlan(hw, vsi->seid,
6417 &vlan_data, 1, NULL);
6418 if (ret != I40E_SUCCESS)
6419 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6421 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6422 &vlan_data, 1, NULL);
6423 if (ret != I40E_SUCCESS)
6425 "Failed to remove vlan filter");
6430 * Find all vlan options for specific mac addr,
6431 * return with actual vlan found.
6434 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6435 struct i40e_macvlan_filter *mv_f,
6436 int num, struct ether_addr *addr)
6442 * Not to use i40e_find_vlan_filter to decrease the loop time,
6443 * although the code looks complex.
6445 if (num < vsi->vlan_num)
6446 return I40E_ERR_PARAM;
6449 for (j = 0; j < I40E_VFTA_SIZE; j++) {
6451 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6452 if (vsi->vfta[j] & (1 << k)) {
6455 "vlan number doesn't match");
6456 return I40E_ERR_PARAM;
6458 rte_memcpy(&mv_f[i].macaddr,
6459 addr, ETH_ADDR_LEN);
6461 j * I40E_UINT32_BIT_SIZE + k;
6467 return I40E_SUCCESS;
6471 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6472 struct i40e_macvlan_filter *mv_f,
6477 struct i40e_mac_filter *f;
6479 if (num < vsi->mac_num)
6480 return I40E_ERR_PARAM;
6482 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6484 PMD_DRV_LOG(ERR, "buffer number not match");
6485 return I40E_ERR_PARAM;
6487 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6489 mv_f[i].vlan_id = vlan;
6490 mv_f[i].filter_type = f->mac_info.filter_type;
6494 return I40E_SUCCESS;
6498 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6501 struct i40e_mac_filter *f;
6502 struct i40e_macvlan_filter *mv_f;
6503 int ret = I40E_SUCCESS;
6505 if (vsi == NULL || vsi->mac_num == 0)
6506 return I40E_ERR_PARAM;
6508 /* Case that no vlan is set */
6509 if (vsi->vlan_num == 0)
6512 num = vsi->mac_num * vsi->vlan_num;
6514 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6516 PMD_DRV_LOG(ERR, "failed to allocate memory");
6517 return I40E_ERR_NO_MEMORY;
6521 if (vsi->vlan_num == 0) {
6522 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6523 rte_memcpy(&mv_f[i].macaddr,
6524 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6525 mv_f[i].filter_type = f->mac_info.filter_type;
6526 mv_f[i].vlan_id = 0;
6530 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6531 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6532 vsi->vlan_num, &f->mac_info.mac_addr);
6533 if (ret != I40E_SUCCESS)
6535 for (j = i; j < i + vsi->vlan_num; j++)
6536 mv_f[j].filter_type = f->mac_info.filter_type;
6541 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6549 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6551 struct i40e_macvlan_filter *mv_f;
6553 int ret = I40E_SUCCESS;
6555 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6556 return I40E_ERR_PARAM;
6558 /* If it's already set, just return */
6559 if (i40e_find_vlan_filter(vsi,vlan))
6560 return I40E_SUCCESS;
6562 mac_num = vsi->mac_num;
6565 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6566 return I40E_ERR_PARAM;
6569 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6572 PMD_DRV_LOG(ERR, "failed to allocate memory");
6573 return I40E_ERR_NO_MEMORY;
6576 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6578 if (ret != I40E_SUCCESS)
6581 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6583 if (ret != I40E_SUCCESS)
6586 i40e_set_vlan_filter(vsi, vlan, 1);
6596 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6598 struct i40e_macvlan_filter *mv_f;
6600 int ret = I40E_SUCCESS;
6603 * Vlan 0 is the generic filter for untagged packets
6604 * and can't be removed.
6606 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6607 return I40E_ERR_PARAM;
6609 /* If can't find it, just return */
6610 if (!i40e_find_vlan_filter(vsi, vlan))
6611 return I40E_ERR_PARAM;
6613 mac_num = vsi->mac_num;
6616 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6617 return I40E_ERR_PARAM;
6620 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6623 PMD_DRV_LOG(ERR, "failed to allocate memory");
6624 return I40E_ERR_NO_MEMORY;
6627 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6629 if (ret != I40E_SUCCESS)
6632 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6634 if (ret != I40E_SUCCESS)
6637 /* This is last vlan to remove, replace all mac filter with vlan 0 */
6638 if (vsi->vlan_num == 1) {
6639 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6640 if (ret != I40E_SUCCESS)
6643 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6644 if (ret != I40E_SUCCESS)
6648 i40e_set_vlan_filter(vsi, vlan, 0);
6658 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6660 struct i40e_mac_filter *f;
6661 struct i40e_macvlan_filter *mv_f;
6662 int i, vlan_num = 0;
6663 int ret = I40E_SUCCESS;
6665 /* If it's add and we've config it, return */
6666 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6668 return I40E_SUCCESS;
6669 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6670 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6673 * If vlan_num is 0, that's the first time to add mac,
6674 * set mask for vlan_id 0.
6676 if (vsi->vlan_num == 0) {
6677 i40e_set_vlan_filter(vsi, 0, 1);
6680 vlan_num = vsi->vlan_num;
6681 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6682 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6685 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6687 PMD_DRV_LOG(ERR, "failed to allocate memory");
6688 return I40E_ERR_NO_MEMORY;
6691 for (i = 0; i < vlan_num; i++) {
6692 mv_f[i].filter_type = mac_filter->filter_type;
6693 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6697 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6698 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6699 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6700 &mac_filter->mac_addr);
6701 if (ret != I40E_SUCCESS)
6705 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6706 if (ret != I40E_SUCCESS)
6709 /* Add the mac addr into mac list */
6710 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6712 PMD_DRV_LOG(ERR, "failed to allocate memory");
6713 ret = I40E_ERR_NO_MEMORY;
6716 rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6718 f->mac_info.filter_type = mac_filter->filter_type;
6719 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6730 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6732 struct i40e_mac_filter *f;
6733 struct i40e_macvlan_filter *mv_f;
6735 enum rte_mac_filter_type filter_type;
6736 int ret = I40E_SUCCESS;
6738 /* Can't find it, return an error */
6739 f = i40e_find_mac_filter(vsi, addr);
6741 return I40E_ERR_PARAM;
6743 vlan_num = vsi->vlan_num;
6744 filter_type = f->mac_info.filter_type;
6745 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6746 filter_type == RTE_MACVLAN_HASH_MATCH) {
6747 if (vlan_num == 0) {
6748 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6749 return I40E_ERR_PARAM;
6751 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6752 filter_type == RTE_MAC_HASH_MATCH)
6755 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6757 PMD_DRV_LOG(ERR, "failed to allocate memory");
6758 return I40E_ERR_NO_MEMORY;
6761 for (i = 0; i < vlan_num; i++) {
6762 mv_f[i].filter_type = filter_type;
6763 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6766 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6767 filter_type == RTE_MACVLAN_HASH_MATCH) {
6768 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6769 if (ret != I40E_SUCCESS)
6773 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6774 if (ret != I40E_SUCCESS)
6777 /* Remove the mac addr into mac list */
6778 TAILQ_REMOVE(&vsi->mac_list, f, next);
6788 /* Configure hash enable flags for RSS */
6790 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
6798 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6799 if (flags & (1ULL << i))
6800 hena |= adapter->pctypes_tbl[i];
6806 /* Parse the hash enable flags */
6808 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
6810 uint64_t rss_hf = 0;
6816 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6817 if (flags & adapter->pctypes_tbl[i])
6818 rss_hf |= (1ULL << i);
6825 i40e_pf_disable_rss(struct i40e_pf *pf)
6827 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6829 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
6830 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
6831 I40E_WRITE_FLUSH(hw);
6835 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6837 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6838 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6839 uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
6840 I40E_VFQF_HKEY_MAX_INDEX :
6841 I40E_PFQF_HKEY_MAX_INDEX;
6844 if (!key || key_len == 0) {
6845 PMD_DRV_LOG(DEBUG, "No key to be configured");
6847 } else if (key_len != (key_idx + 1) *
6849 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6853 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6854 struct i40e_aqc_get_set_rss_key_data *key_dw =
6855 (struct i40e_aqc_get_set_rss_key_data *)key;
6857 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6859 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6861 uint32_t *hash_key = (uint32_t *)key;
6864 if (vsi->type == I40E_VSI_SRIOV) {
6865 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
6868 I40E_VFQF_HKEY1(i, vsi->user_param),
6872 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6873 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
6876 I40E_WRITE_FLUSH(hw);
6883 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6885 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6886 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6890 if (!key || !key_len)
6893 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6894 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6895 (struct i40e_aqc_get_set_rss_key_data *)key);
6897 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6901 uint32_t *key_dw = (uint32_t *)key;
6904 if (vsi->type == I40E_VSI_SRIOV) {
6905 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
6906 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
6907 key_dw[i] = i40e_read_rx_ctl(hw, reg);
6909 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
6912 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
6913 reg = I40E_PFQF_HKEY(i);
6914 key_dw[i] = i40e_read_rx_ctl(hw, reg);
6916 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6924 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6926 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6930 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6931 rss_conf->rss_key_len);
6935 hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
6936 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6937 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6938 I40E_WRITE_FLUSH(hw);
6944 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6945 struct rte_eth_rss_conf *rss_conf)
6947 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6948 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6949 uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
6952 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6953 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6955 if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
6956 if (rss_hf != 0) /* Enable RSS */
6958 return 0; /* Nothing to do */
6961 if (rss_hf == 0) /* Disable RSS */
6964 return i40e_hw_rss_hash_set(pf, rss_conf);
6968 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6969 struct rte_eth_rss_conf *rss_conf)
6971 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6972 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6975 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6976 &rss_conf->rss_key_len);
6978 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6979 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6980 rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
6986 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6988 switch (filter_type) {
6989 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6990 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6992 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6993 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6995 case RTE_TUNNEL_FILTER_IMAC_TENID:
6996 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6998 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6999 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7001 case ETH_TUNNEL_FILTER_IMAC:
7002 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7004 case ETH_TUNNEL_FILTER_OIP:
7005 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7007 case ETH_TUNNEL_FILTER_IIP:
7008 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7011 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7018 /* Convert tunnel filter structure */
7020 i40e_tunnel_filter_convert(
7021 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
7022 struct i40e_tunnel_filter *tunnel_filter)
7024 ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
7025 (struct ether_addr *)&tunnel_filter->input.outer_mac);
7026 ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
7027 (struct ether_addr *)&tunnel_filter->input.inner_mac);
7028 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7029 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7030 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7031 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7032 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7034 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7035 tunnel_filter->input.flags = cld_filter->element.flags;
7036 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7037 tunnel_filter->queue = cld_filter->element.queue_number;
7038 rte_memcpy(tunnel_filter->input.general_fields,
7039 cld_filter->general_fields,
7040 sizeof(cld_filter->general_fields));
7045 /* Check if there exists the tunnel filter */
7046 struct i40e_tunnel_filter *
7047 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7048 const struct i40e_tunnel_filter_input *input)
7052 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7056 return tunnel_rule->hash_map[ret];
7059 /* Add a tunnel filter into the SW list */
7061 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7062 struct i40e_tunnel_filter *tunnel_filter)
7064 struct i40e_tunnel_rule *rule = &pf->tunnel;
7067 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7070 "Failed to insert tunnel filter to hash table %d!",
7074 rule->hash_map[ret] = tunnel_filter;
7076 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7081 /* Delete a tunnel filter from the SW list */
7083 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7084 struct i40e_tunnel_filter_input *input)
7086 struct i40e_tunnel_rule *rule = &pf->tunnel;
7087 struct i40e_tunnel_filter *tunnel_filter;
7090 ret = rte_hash_del_key(rule->hash_table, input);
7093 "Failed to delete tunnel filter to hash table %d!",
7097 tunnel_filter = rule->hash_map[ret];
7098 rule->hash_map[ret] = NULL;
7100 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7101 rte_free(tunnel_filter);
7107 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7108 struct rte_eth_tunnel_filter_conf *tunnel_filter,
7112 uint32_t ipv4_addr, ipv4_addr_le;
7113 uint8_t i, tun_type = 0;
7114 /* internal varialbe to convert ipv6 byte order */
7115 uint32_t convert_ipv6[4];
7117 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7118 struct i40e_vsi *vsi = pf->main_vsi;
7119 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7120 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7121 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7122 struct i40e_tunnel_filter *tunnel, *node;
7123 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7125 cld_filter = rte_zmalloc("tunnel_filter",
7126 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7129 if (NULL == cld_filter) {
7130 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7133 pfilter = cld_filter;
7135 ether_addr_copy(&tunnel_filter->outer_mac,
7136 (struct ether_addr *)&pfilter->element.outer_mac);
7137 ether_addr_copy(&tunnel_filter->inner_mac,
7138 (struct ether_addr *)&pfilter->element.inner_mac);
7140 pfilter->element.inner_vlan =
7141 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7142 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7143 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7144 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7145 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7146 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7148 sizeof(pfilter->element.ipaddr.v4.data));
7150 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7151 for (i = 0; i < 4; i++) {
7153 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7155 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7157 sizeof(pfilter->element.ipaddr.v6.data));
7160 /* check tunneled type */
7161 switch (tunnel_filter->tunnel_type) {
7162 case RTE_TUNNEL_TYPE_VXLAN:
7163 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7165 case RTE_TUNNEL_TYPE_NVGRE:
7166 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7168 case RTE_TUNNEL_TYPE_IP_IN_GRE:
7169 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7172 /* Other tunnel types is not supported. */
7173 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7174 rte_free(cld_filter);
7178 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7179 &pfilter->element.flags);
7181 rte_free(cld_filter);
7185 pfilter->element.flags |= rte_cpu_to_le_16(
7186 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7187 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7188 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7189 pfilter->element.queue_number =
7190 rte_cpu_to_le_16(tunnel_filter->queue_id);
7192 /* Check if there is the filter in SW list */
7193 memset(&check_filter, 0, sizeof(check_filter));
7194 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7195 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7197 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7198 rte_free(cld_filter);
7202 if (!add && !node) {
7203 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7204 rte_free(cld_filter);
7209 ret = i40e_aq_add_cloud_filters(hw,
7210 vsi->seid, &cld_filter->element, 1);
7212 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7213 rte_free(cld_filter);
7216 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7217 if (tunnel == NULL) {
7218 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7219 rte_free(cld_filter);
7223 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7224 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7228 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7229 &cld_filter->element, 1);
7231 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7232 rte_free(cld_filter);
7235 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7238 rte_free(cld_filter);
7242 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7243 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
7244 #define I40E_TR_GENEVE_KEY_MASK 0x8
7245 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
7246 #define I40E_TR_GRE_KEY_MASK 0x400
7247 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
7248 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
7251 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7253 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7254 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7255 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7256 enum i40e_status_code status = I40E_SUCCESS;
7258 memset(&filter_replace, 0,
7259 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7260 memset(&filter_replace_buf, 0,
7261 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7263 /* create L1 filter */
7264 filter_replace.old_filter_type =
7265 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7266 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7267 filter_replace.tr_bit = 0;
7269 /* Prepare the buffer, 3 entries */
7270 filter_replace_buf.data[0] =
7271 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7272 filter_replace_buf.data[0] |=
7273 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7274 filter_replace_buf.data[2] = 0xFF;
7275 filter_replace_buf.data[3] = 0xFF;
7276 filter_replace_buf.data[4] =
7277 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7278 filter_replace_buf.data[4] |=
7279 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7280 filter_replace_buf.data[7] = 0xF0;
7281 filter_replace_buf.data[8]
7282 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7283 filter_replace_buf.data[8] |=
7284 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7285 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7286 I40E_TR_GENEVE_KEY_MASK |
7287 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7288 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7289 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7290 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7292 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7293 &filter_replace_buf);
7295 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7300 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7302 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7303 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7304 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7305 enum i40e_status_code status = I40E_SUCCESS;
7308 memset(&filter_replace, 0,
7309 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7310 memset(&filter_replace_buf, 0,
7311 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7312 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7313 I40E_AQC_MIRROR_CLOUD_FILTER;
7314 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7315 filter_replace.new_filter_type =
7316 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7317 /* Prepare the buffer, 2 entries */
7318 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7319 filter_replace_buf.data[0] |=
7320 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7321 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7322 filter_replace_buf.data[4] |=
7323 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7324 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7325 &filter_replace_buf);
7330 memset(&filter_replace, 0,
7331 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7332 memset(&filter_replace_buf, 0,
7333 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7335 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7336 I40E_AQC_MIRROR_CLOUD_FILTER;
7337 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7338 filter_replace.new_filter_type =
7339 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7340 /* Prepare the buffer, 2 entries */
7341 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7342 filter_replace_buf.data[0] |=
7343 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7344 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7345 filter_replace_buf.data[4] |=
7346 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7348 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7349 &filter_replace_buf);
7351 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7355 static enum i40e_status_code
7356 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7358 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7359 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7360 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7361 enum i40e_status_code status = I40E_SUCCESS;
7364 memset(&filter_replace, 0,
7365 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7366 memset(&filter_replace_buf, 0,
7367 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7368 /* create L1 filter */
7369 filter_replace.old_filter_type =
7370 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7371 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7372 filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7373 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7374 /* Prepare the buffer, 2 entries */
7375 filter_replace_buf.data[0] =
7376 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7377 filter_replace_buf.data[0] |=
7378 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7379 filter_replace_buf.data[2] = 0xFF;
7380 filter_replace_buf.data[3] = 0xFF;
7381 filter_replace_buf.data[4] =
7382 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7383 filter_replace_buf.data[4] |=
7384 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7385 filter_replace_buf.data[6] = 0xFF;
7386 filter_replace_buf.data[7] = 0xFF;
7387 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7388 &filter_replace_buf);
7393 memset(&filter_replace, 0,
7394 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7395 memset(&filter_replace_buf, 0,
7396 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7397 /* create L1 filter */
7398 filter_replace.old_filter_type =
7399 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
7400 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
7401 filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
7402 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7403 /* Prepare the buffer, 2 entries */
7404 filter_replace_buf.data[0] =
7405 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7406 filter_replace_buf.data[0] |=
7407 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7408 filter_replace_buf.data[2] = 0xFF;
7409 filter_replace_buf.data[3] = 0xFF;
7410 filter_replace_buf.data[4] =
7411 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7412 filter_replace_buf.data[4] |=
7413 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7414 filter_replace_buf.data[6] = 0xFF;
7415 filter_replace_buf.data[7] = 0xFF;
7417 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7418 &filter_replace_buf);
7420 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7425 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
7427 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7428 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7429 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7430 enum i40e_status_code status = I40E_SUCCESS;
7433 memset(&filter_replace, 0,
7434 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7435 memset(&filter_replace_buf, 0,
7436 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7437 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7438 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7439 filter_replace.new_filter_type =
7440 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7441 /* Prepare the buffer, 2 entries */
7442 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
7443 filter_replace_buf.data[0] |=
7444 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7445 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7446 filter_replace_buf.data[4] |=
7447 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7448 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7449 &filter_replace_buf);
7454 memset(&filter_replace, 0,
7455 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7456 memset(&filter_replace_buf, 0,
7457 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7458 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7459 filter_replace.old_filter_type =
7460 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7461 filter_replace.new_filter_type =
7462 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7463 /* Prepare the buffer, 2 entries */
7464 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
7465 filter_replace_buf.data[0] |=
7466 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7467 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7468 filter_replace_buf.data[4] |=
7469 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7471 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7472 &filter_replace_buf);
7474 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7479 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7480 struct i40e_tunnel_filter_conf *tunnel_filter,
7484 uint32_t ipv4_addr, ipv4_addr_le;
7485 uint8_t i, tun_type = 0;
7486 /* internal variable to convert ipv6 byte order */
7487 uint32_t convert_ipv6[4];
7489 struct i40e_pf_vf *vf = NULL;
7490 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7491 struct i40e_vsi *vsi;
7492 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7493 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7494 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7495 struct i40e_tunnel_filter *tunnel, *node;
7496 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7498 bool big_buffer = 0;
7500 cld_filter = rte_zmalloc("tunnel_filter",
7501 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7504 if (cld_filter == NULL) {
7505 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7508 pfilter = cld_filter;
7510 ether_addr_copy(&tunnel_filter->outer_mac,
7511 (struct ether_addr *)&pfilter->element.outer_mac);
7512 ether_addr_copy(&tunnel_filter->inner_mac,
7513 (struct ether_addr *)&pfilter->element.inner_mac);
7515 pfilter->element.inner_vlan =
7516 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7517 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7518 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7519 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7520 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7521 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7523 sizeof(pfilter->element.ipaddr.v4.data));
7525 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7526 for (i = 0; i < 4; i++) {
7528 rte_cpu_to_le_32(rte_be_to_cpu_32(
7529 tunnel_filter->ip_addr.ipv6_addr[i]));
7531 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7533 sizeof(pfilter->element.ipaddr.v6.data));
7536 /* check tunneled type */
7537 switch (tunnel_filter->tunnel_type) {
7538 case I40E_TUNNEL_TYPE_VXLAN:
7539 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7541 case I40E_TUNNEL_TYPE_NVGRE:
7542 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7544 case I40E_TUNNEL_TYPE_IP_IN_GRE:
7545 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7547 case I40E_TUNNEL_TYPE_MPLSoUDP:
7548 if (!pf->mpls_replace_flag) {
7549 i40e_replace_mpls_l1_filter(pf);
7550 i40e_replace_mpls_cloud_filter(pf);
7551 pf->mpls_replace_flag = 1;
7553 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7554 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7556 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7557 (teid_le & 0xF) << 12;
7558 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7561 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
7563 case I40E_TUNNEL_TYPE_MPLSoGRE:
7564 if (!pf->mpls_replace_flag) {
7565 i40e_replace_mpls_l1_filter(pf);
7566 i40e_replace_mpls_cloud_filter(pf);
7567 pf->mpls_replace_flag = 1;
7569 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7570 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7572 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7573 (teid_le & 0xF) << 12;
7574 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7577 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
7579 case I40E_TUNNEL_TYPE_GTPC:
7580 if (!pf->gtp_replace_flag) {
7581 i40e_replace_gtp_l1_filter(pf);
7582 i40e_replace_gtp_cloud_filter(pf);
7583 pf->gtp_replace_flag = 1;
7585 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7586 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
7587 (teid_le >> 16) & 0xFFFF;
7588 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
7590 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
7594 case I40E_TUNNEL_TYPE_GTPU:
7595 if (!pf->gtp_replace_flag) {
7596 i40e_replace_gtp_l1_filter(pf);
7597 i40e_replace_gtp_cloud_filter(pf);
7598 pf->gtp_replace_flag = 1;
7600 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7601 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
7602 (teid_le >> 16) & 0xFFFF;
7603 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
7605 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
7609 case I40E_TUNNEL_TYPE_QINQ:
7610 if (!pf->qinq_replace_flag) {
7611 ret = i40e_cloud_filter_qinq_create(pf);
7614 "QinQ tunnel filter already created.");
7615 pf->qinq_replace_flag = 1;
7617 /* Add in the General fields the values of
7618 * the Outer and Inner VLAN
7619 * Big Buffer should be set, see changes in
7620 * i40e_aq_add_cloud_filters
7622 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7623 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7627 /* Other tunnel types is not supported. */
7628 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7629 rte_free(cld_filter);
7633 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7634 pfilter->element.flags =
7635 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7636 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7637 pfilter->element.flags =
7638 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7639 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
7640 pfilter->element.flags =
7641 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7642 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
7643 pfilter->element.flags =
7644 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7645 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7646 pfilter->element.flags |=
7647 I40E_AQC_ADD_CLOUD_FILTER_0X10;
7649 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7650 &pfilter->element.flags);
7652 rte_free(cld_filter);
7657 pfilter->element.flags |= rte_cpu_to_le_16(
7658 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7659 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7660 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7661 pfilter->element.queue_number =
7662 rte_cpu_to_le_16(tunnel_filter->queue_id);
7664 if (!tunnel_filter->is_to_vf)
7667 if (tunnel_filter->vf_id >= pf->vf_num) {
7668 PMD_DRV_LOG(ERR, "Invalid argument.");
7669 rte_free(cld_filter);
7672 vf = &pf->vfs[tunnel_filter->vf_id];
7676 /* Check if there is the filter in SW list */
7677 memset(&check_filter, 0, sizeof(check_filter));
7678 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7679 check_filter.is_to_vf = tunnel_filter->is_to_vf;
7680 check_filter.vf_id = tunnel_filter->vf_id;
7681 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7683 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7684 rte_free(cld_filter);
7688 if (!add && !node) {
7689 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7690 rte_free(cld_filter);
7696 ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7697 vsi->seid, cld_filter, 1);
7699 ret = i40e_aq_add_cloud_filters(hw,
7700 vsi->seid, &cld_filter->element, 1);
7702 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7703 rte_free(cld_filter);
7706 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7707 if (tunnel == NULL) {
7708 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7709 rte_free(cld_filter);
7713 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7714 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7719 ret = i40e_aq_remove_cloud_filters_big_buffer(
7720 hw, vsi->seid, cld_filter, 1);
7722 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7723 &cld_filter->element, 1);
7725 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7726 rte_free(cld_filter);
7729 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7732 rte_free(cld_filter);
7737 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7741 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7742 if (pf->vxlan_ports[i] == port)
7750 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7754 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7756 idx = i40e_get_vxlan_port_idx(pf, port);
7758 /* Check if port already exists */
7760 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7764 /* Now check if there is space to add the new port */
7765 idx = i40e_get_vxlan_port_idx(pf, 0);
7768 "Maximum number of UDP ports reached, not adding port %d",
7773 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7776 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7780 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7783 /* New port: add it and mark its index in the bitmap */
7784 pf->vxlan_ports[idx] = port;
7785 pf->vxlan_bitmap |= (1 << idx);
7787 if (!(pf->flags & I40E_FLAG_VXLAN))
7788 pf->flags |= I40E_FLAG_VXLAN;
7794 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7797 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7799 if (!(pf->flags & I40E_FLAG_VXLAN)) {
7800 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7804 idx = i40e_get_vxlan_port_idx(pf, port);
7807 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7811 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7812 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7816 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7819 pf->vxlan_ports[idx] = 0;
7820 pf->vxlan_bitmap &= ~(1 << idx);
7822 if (!pf->vxlan_bitmap)
7823 pf->flags &= ~I40E_FLAG_VXLAN;
7828 /* Add UDP tunneling port */
7830 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7831 struct rte_eth_udp_tunnel *udp_tunnel)
7834 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7836 if (udp_tunnel == NULL)
7839 switch (udp_tunnel->prot_type) {
7840 case RTE_TUNNEL_TYPE_VXLAN:
7841 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7844 case RTE_TUNNEL_TYPE_GENEVE:
7845 case RTE_TUNNEL_TYPE_TEREDO:
7846 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7851 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7859 /* Remove UDP tunneling port */
7861 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7862 struct rte_eth_udp_tunnel *udp_tunnel)
7865 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7867 if (udp_tunnel == NULL)
7870 switch (udp_tunnel->prot_type) {
7871 case RTE_TUNNEL_TYPE_VXLAN:
7872 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7874 case RTE_TUNNEL_TYPE_GENEVE:
7875 case RTE_TUNNEL_TYPE_TEREDO:
7876 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7880 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7888 /* Calculate the maximum number of contiguous PF queues that are configured */
7890 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7892 struct rte_eth_dev_data *data = pf->dev_data;
7894 struct i40e_rx_queue *rxq;
7897 for (i = 0; i < pf->lan_nb_qps; i++) {
7898 rxq = data->rx_queues[i];
7899 if (rxq && rxq->q_set)
7910 i40e_pf_config_rss(struct i40e_pf *pf)
7912 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7913 struct rte_eth_rss_conf rss_conf;
7914 uint32_t i, lut = 0;
7918 * If both VMDQ and RSS enabled, not all of PF queues are configured.
7919 * It's necessary to calculate the actual PF queues that are configured.
7921 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7922 num = i40e_pf_calc_configured_queues_num(pf);
7924 num = pf->dev_data->nb_rx_queues;
7926 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7927 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7931 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7935 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7938 lut = (lut << 8) | (j & ((0x1 <<
7939 hw->func_caps.rss_table_entry_width) - 1));
7941 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7944 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7945 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
7946 i40e_pf_disable_rss(pf);
7949 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7950 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7951 /* Random default keys */
7952 static uint32_t rss_key_default[] = {0x6b793944,
7953 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7954 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7955 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7957 rss_conf.rss_key = (uint8_t *)rss_key_default;
7958 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7962 return i40e_hw_rss_hash_set(pf, &rss_conf);
7966 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7967 struct rte_eth_tunnel_filter_conf *filter)
7969 if (pf == NULL || filter == NULL) {
7970 PMD_DRV_LOG(ERR, "Invalid parameter");
7974 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7975 PMD_DRV_LOG(ERR, "Invalid queue ID");
7979 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7980 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7984 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7985 (is_zero_ether_addr(&filter->outer_mac))) {
7986 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7990 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7991 (is_zero_ether_addr(&filter->inner_mac))) {
7992 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7999 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8000 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
8002 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8007 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8008 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8011 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8012 } else if (len == 4) {
8013 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8015 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8020 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
8024 i40e_global_cfg_warning(I40E_WARNING_GRE_KEY_LEN);
8028 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8029 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8035 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8042 switch (cfg->cfg_type) {
8043 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8044 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8047 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8055 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8056 enum rte_filter_op filter_op,
8059 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8060 int ret = I40E_ERR_PARAM;
8062 switch (filter_op) {
8063 case RTE_ETH_FILTER_SET:
8064 ret = i40e_dev_global_config_set(hw,
8065 (struct rte_eth_global_cfg *)arg);
8068 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8076 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8077 enum rte_filter_op filter_op,
8080 struct rte_eth_tunnel_filter_conf *filter;
8081 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8082 int ret = I40E_SUCCESS;
8084 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8086 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8087 return I40E_ERR_PARAM;
8089 switch (filter_op) {
8090 case RTE_ETH_FILTER_NOP:
8091 if (!(pf->flags & I40E_FLAG_VXLAN))
8092 ret = I40E_NOT_SUPPORTED;
8094 case RTE_ETH_FILTER_ADD:
8095 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8097 case RTE_ETH_FILTER_DELETE:
8098 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8101 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8102 ret = I40E_ERR_PARAM;
8110 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8113 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8116 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8117 ret = i40e_pf_config_rss(pf);
8119 i40e_pf_disable_rss(pf);
8124 /* Get the symmetric hash enable configurations per port */
8126 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8128 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8130 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8133 /* Set the symmetric hash enable configurations per port */
8135 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8137 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8140 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8142 "Symmetric hash has already been enabled");
8145 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8147 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8149 "Symmetric hash has already been disabled");
8152 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8154 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8155 I40E_WRITE_FLUSH(hw);
8159 * Get global configurations of hash function type and symmetric hash enable
8160 * per flow type (pctype). Note that global configuration means it affects all
8161 * the ports on the same NIC.
8164 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8165 struct rte_eth_hash_global_conf *g_cfg)
8167 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8171 memset(g_cfg, 0, sizeof(*g_cfg));
8172 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8173 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8174 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8176 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8177 PMD_DRV_LOG(DEBUG, "Hash function is %s",
8178 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8181 * As i40e supports less than 64 flow types, only first 64 bits need to
8184 for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8185 g_cfg->valid_bit_mask[i] = 0ULL;
8186 g_cfg->sym_hash_enable_mask[i] = 0ULL;
8189 g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
8191 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
8192 if (!adapter->pctypes_tbl[i])
8194 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8195 j < I40E_FILTER_PCTYPE_MAX; j++) {
8196 if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8197 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8198 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8199 g_cfg->sym_hash_enable_mask[0] |=
8210 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8211 const struct rte_eth_hash_global_conf *g_cfg)
8214 uint64_t mask0, i40e_mask = adapter->flow_types_mask;
8216 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8217 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8218 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8219 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8225 * As i40e supports less than 64 flow types, only first 64 bits need to
8228 mask0 = g_cfg->valid_bit_mask[0];
8229 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8231 /* Check if any unsupported flow type configured */
8232 if ((mask0 | i40e_mask) ^ i40e_mask)
8235 if (g_cfg->valid_bit_mask[i])
8243 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8249 * Set global configurations of hash function type and symmetric hash enable
8250 * per flow type (pctype). Note any modifying global configuration will affect
8251 * all the ports on the same NIC.
8254 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8255 struct rte_eth_hash_global_conf *g_cfg)
8257 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8261 uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
8263 /* Check the input parameters */
8264 ret = i40e_hash_global_config_check(adapter, g_cfg);
8269 * As i40e supports less than 64 flow types, only first 64 bits need to
8272 for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
8273 if (mask0 & (1UL << i)) {
8274 reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
8275 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8277 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8278 j < I40E_FILTER_PCTYPE_MAX; j++) {
8279 if (adapter->pctypes_tbl[i] & (1ULL << j))
8280 i40e_write_rx_ctl(hw,
8284 i40e_global_cfg_warning(I40E_WARNING_HSYM);
8288 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8289 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8291 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8293 "Hash function already set to Toeplitz");
8296 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8297 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8299 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8301 "Hash function already set to Simple XOR");
8304 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8306 /* Use the default, and keep it as it is */
8309 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
8310 i40e_global_cfg_warning(I40E_WARNING_QF_CTL);
8313 I40E_WRITE_FLUSH(hw);
8319 * Valid input sets for hash and flow director filters per PCTYPE
8322 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8323 enum rte_filter_type filter)
8327 static const uint64_t valid_hash_inset_table[] = {
8328 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8329 I40E_INSET_DMAC | I40E_INSET_SMAC |
8330 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8331 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8332 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8333 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8334 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8335 I40E_INSET_FLEX_PAYLOAD,
8336 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8337 I40E_INSET_DMAC | I40E_INSET_SMAC |
8338 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8339 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8340 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8341 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8342 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8343 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8344 I40E_INSET_FLEX_PAYLOAD,
8345 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8346 I40E_INSET_DMAC | I40E_INSET_SMAC |
8347 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8348 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8349 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8350 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8351 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8352 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8353 I40E_INSET_FLEX_PAYLOAD,
8354 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8355 I40E_INSET_DMAC | I40E_INSET_SMAC |
8356 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8357 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8358 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8359 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8360 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8361 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8362 I40E_INSET_FLEX_PAYLOAD,
8363 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8364 I40E_INSET_DMAC | I40E_INSET_SMAC |
8365 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8366 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8367 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8368 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8369 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8370 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8371 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8372 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8373 I40E_INSET_DMAC | I40E_INSET_SMAC |
8374 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8375 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8376 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8377 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8378 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8379 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8380 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8381 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8382 I40E_INSET_DMAC | I40E_INSET_SMAC |
8383 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8384 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8385 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8386 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8387 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8388 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8389 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8390 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8391 I40E_INSET_DMAC | I40E_INSET_SMAC |
8392 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8393 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8394 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8395 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8396 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8397 I40E_INSET_FLEX_PAYLOAD,
8398 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8399 I40E_INSET_DMAC | I40E_INSET_SMAC |
8400 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8401 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8402 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8403 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8404 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8405 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8406 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8407 I40E_INSET_DMAC | I40E_INSET_SMAC |
8408 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8409 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8410 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8411 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8412 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8413 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8414 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8415 I40E_INSET_DMAC | I40E_INSET_SMAC |
8416 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8417 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8418 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8419 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8420 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8421 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8422 I40E_INSET_FLEX_PAYLOAD,
8423 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8424 I40E_INSET_DMAC | I40E_INSET_SMAC |
8425 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8426 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8427 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8428 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8429 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8430 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8431 I40E_INSET_FLEX_PAYLOAD,
8432 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8433 I40E_INSET_DMAC | I40E_INSET_SMAC |
8434 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8435 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8436 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8437 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8438 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8439 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8440 I40E_INSET_FLEX_PAYLOAD,
8441 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8442 I40E_INSET_DMAC | I40E_INSET_SMAC |
8443 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8444 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8445 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8446 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8447 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8448 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8449 I40E_INSET_FLEX_PAYLOAD,
8450 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8451 I40E_INSET_DMAC | I40E_INSET_SMAC |
8452 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8453 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8454 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8455 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8456 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8457 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8458 I40E_INSET_FLEX_PAYLOAD,
8459 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8460 I40E_INSET_DMAC | I40E_INSET_SMAC |
8461 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8462 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8463 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8464 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8465 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8466 I40E_INSET_FLEX_PAYLOAD,
8467 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8468 I40E_INSET_DMAC | I40E_INSET_SMAC |
8469 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8470 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8471 I40E_INSET_FLEX_PAYLOAD,
8475 * Flow director supports only fields defined in
8476 * union rte_eth_fdir_flow.
8478 static const uint64_t valid_fdir_inset_table[] = {
8479 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8480 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8481 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8482 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8483 I40E_INSET_IPV4_TTL,
8484 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8485 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8486 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8487 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8488 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8489 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8490 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8491 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8492 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8493 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8494 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8495 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8496 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8497 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8498 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8499 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8500 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8501 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8502 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8503 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8504 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8505 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8506 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8507 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8508 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8509 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8510 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8511 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8512 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8513 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8515 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8516 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8517 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8518 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8519 I40E_INSET_IPV4_TTL,
8520 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8521 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8522 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8523 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8524 I40E_INSET_IPV6_HOP_LIMIT,
8525 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8526 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8527 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8528 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8529 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8530 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8531 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8532 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8533 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8534 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8535 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8536 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8537 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8538 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8539 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8540 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8541 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8542 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8543 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8544 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8545 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8546 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8547 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8548 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8549 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8550 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8551 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8552 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8553 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8554 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8556 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8557 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8558 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8559 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8560 I40E_INSET_IPV6_HOP_LIMIT,
8561 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8562 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8563 I40E_INSET_LAST_ETHER_TYPE,
8566 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8568 if (filter == RTE_ETH_FILTER_HASH)
8569 valid = valid_hash_inset_table[pctype];
8571 valid = valid_fdir_inset_table[pctype];
8577 * Validate if the input set is allowed for a specific PCTYPE
8580 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8581 enum rte_filter_type filter, uint64_t inset)
8585 valid = i40e_get_valid_input_set(pctype, filter);
8586 if (inset & (~valid))
8592 /* default input set fields combination per pctype */
8594 i40e_get_default_input_set(uint16_t pctype)
8596 static const uint64_t default_inset_table[] = {
8597 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8598 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8599 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8600 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8601 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8602 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8603 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8604 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8605 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8606 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8607 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8608 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8609 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8610 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8611 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8612 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8613 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8614 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8615 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8616 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8618 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8619 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8620 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8621 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8622 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8623 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8624 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8625 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8626 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8627 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8628 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8629 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8630 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8631 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8632 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8633 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8634 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8635 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8636 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8637 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8638 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8639 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8641 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8642 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8643 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8644 I40E_INSET_LAST_ETHER_TYPE,
8647 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8650 return default_inset_table[pctype];
8654 * Parse the input set from index to logical bit masks
8657 i40e_parse_input_set(uint64_t *inset,
8658 enum i40e_filter_pctype pctype,
8659 enum rte_eth_input_set_field *field,
8665 static const struct {
8666 enum rte_eth_input_set_field field;
8668 } inset_convert_table[] = {
8669 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8670 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8671 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8672 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8673 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8674 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8675 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8676 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8677 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8678 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8679 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8680 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8681 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8682 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8683 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8684 I40E_INSET_IPV6_NEXT_HDR},
8685 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8686 I40E_INSET_IPV6_HOP_LIMIT},
8687 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8688 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8689 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8690 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8691 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8692 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8693 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8694 I40E_INSET_SCTP_VT},
8695 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8696 I40E_INSET_TUNNEL_DMAC},
8697 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8698 I40E_INSET_VLAN_TUNNEL},
8699 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8700 I40E_INSET_TUNNEL_ID},
8701 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8702 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8703 I40E_INSET_FLEX_PAYLOAD_W1},
8704 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8705 I40E_INSET_FLEX_PAYLOAD_W2},
8706 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8707 I40E_INSET_FLEX_PAYLOAD_W3},
8708 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8709 I40E_INSET_FLEX_PAYLOAD_W4},
8710 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8711 I40E_INSET_FLEX_PAYLOAD_W5},
8712 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8713 I40E_INSET_FLEX_PAYLOAD_W6},
8714 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8715 I40E_INSET_FLEX_PAYLOAD_W7},
8716 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8717 I40E_INSET_FLEX_PAYLOAD_W8},
8720 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8723 /* Only one item allowed for default or all */
8725 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8726 *inset = i40e_get_default_input_set(pctype);
8728 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8729 *inset = I40E_INSET_NONE;
8734 for (i = 0, *inset = 0; i < size; i++) {
8735 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8736 if (field[i] == inset_convert_table[j].field) {
8737 *inset |= inset_convert_table[j].inset;
8742 /* It contains unsupported input set, return immediately */
8743 if (j == RTE_DIM(inset_convert_table))
8751 * Translate the input set from bit masks to register aware bit masks
8755 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8765 static const struct inset_map inset_map_common[] = {
8766 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8767 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8768 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8769 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8770 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8771 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8772 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8773 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8774 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8775 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8776 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8777 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8778 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8779 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8780 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8781 {I40E_INSET_TUNNEL_DMAC,
8782 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8783 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8784 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8785 {I40E_INSET_TUNNEL_SRC_PORT,
8786 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8787 {I40E_INSET_TUNNEL_DST_PORT,
8788 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8789 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8790 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8791 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8792 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8793 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8794 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8795 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8796 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8797 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8800 /* some different registers map in x722*/
8801 static const struct inset_map inset_map_diff_x722[] = {
8802 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8803 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8804 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8805 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8808 static const struct inset_map inset_map_diff_not_x722[] = {
8809 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8810 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8811 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8812 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8818 /* Translate input set to register aware inset */
8819 if (type == I40E_MAC_X722) {
8820 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8821 if (input & inset_map_diff_x722[i].inset)
8822 val |= inset_map_diff_x722[i].inset_reg;
8825 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8826 if (input & inset_map_diff_not_x722[i].inset)
8827 val |= inset_map_diff_not_x722[i].inset_reg;
8831 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8832 if (input & inset_map_common[i].inset)
8833 val |= inset_map_common[i].inset_reg;
8840 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8843 uint64_t inset_need_mask = inset;
8845 static const struct {
8848 } inset_mask_map[] = {
8849 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8850 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8851 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8852 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8853 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8854 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8855 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8856 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8859 if (!inset || !mask || !nb_elem)
8862 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8863 /* Clear the inset bit, if no MASK is required,
8864 * for example proto + ttl
8866 if ((inset & inset_mask_map[i].inset) ==
8867 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8868 inset_need_mask &= ~inset_mask_map[i].inset;
8869 if (!inset_need_mask)
8872 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8873 if ((inset_need_mask & inset_mask_map[i].inset) ==
8874 inset_mask_map[i].inset) {
8875 if (idx >= nb_elem) {
8876 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8879 mask[idx] = inset_mask_map[i].mask;
8888 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8890 uint32_t reg = i40e_read_rx_ctl(hw, addr);
8892 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8894 i40e_write_rx_ctl(hw, addr, val);
8895 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8896 (uint32_t)i40e_read_rx_ctl(hw, addr));
8900 i40e_filter_input_set_init(struct i40e_pf *pf)
8902 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8903 enum i40e_filter_pctype pctype;
8904 uint64_t input_set, inset_reg;
8905 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8909 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8910 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8911 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
8913 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
8916 input_set = i40e_get_default_input_set(pctype);
8918 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8919 I40E_INSET_MASK_NUM_REG);
8922 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8925 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8926 (uint32_t)(inset_reg & UINT32_MAX));
8927 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8928 (uint32_t)((inset_reg >>
8929 I40E_32_BIT_WIDTH) & UINT32_MAX));
8930 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8931 (uint32_t)(inset_reg & UINT32_MAX));
8932 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8933 (uint32_t)((inset_reg >>
8934 I40E_32_BIT_WIDTH) & UINT32_MAX));
8936 for (i = 0; i < num; i++) {
8937 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8939 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8942 /*clear unused mask registers of the pctype */
8943 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8944 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8946 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8949 I40E_WRITE_FLUSH(hw);
8951 /* store the default input set */
8952 pf->hash_input_set[pctype] = input_set;
8953 pf->fdir.input_set[pctype] = input_set;
8956 i40e_global_cfg_warning(I40E_WARNING_HASH_INSET);
8957 i40e_global_cfg_warning(I40E_WARNING_FD_MSK);
8958 i40e_global_cfg_warning(I40E_WARNING_HASH_MSK);
8962 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8963 struct rte_eth_input_set_conf *conf)
8965 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8966 enum i40e_filter_pctype pctype;
8967 uint64_t input_set, inset_reg = 0;
8968 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8972 PMD_DRV_LOG(ERR, "Invalid pointer");
8975 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8976 conf->op != RTE_ETH_INPUT_SET_ADD) {
8977 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8981 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
8982 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
8983 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8987 if (hw->mac.type == I40E_MAC_X722) {
8988 /* get translated pctype value in fd pctype register */
8989 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8990 I40E_GLQF_FD_PCTYPES((int)pctype));
8993 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8996 PMD_DRV_LOG(ERR, "Failed to parse input set");
9000 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9001 /* get inset value in register */
9002 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9003 inset_reg <<= I40E_32_BIT_WIDTH;
9004 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9005 input_set |= pf->hash_input_set[pctype];
9007 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9008 I40E_INSET_MASK_NUM_REG);
9012 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9014 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9015 (uint32_t)(inset_reg & UINT32_MAX));
9016 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9017 (uint32_t)((inset_reg >>
9018 I40E_32_BIT_WIDTH) & UINT32_MAX));
9019 i40e_global_cfg_warning(I40E_WARNING_HASH_INSET);
9021 for (i = 0; i < num; i++)
9022 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9024 /*clear unused mask registers of the pctype */
9025 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9026 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9028 i40e_global_cfg_warning(I40E_WARNING_HASH_MSK);
9029 I40E_WRITE_FLUSH(hw);
9031 pf->hash_input_set[pctype] = input_set;
9036 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9037 struct rte_eth_input_set_conf *conf)
9039 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9040 enum i40e_filter_pctype pctype;
9041 uint64_t input_set, inset_reg = 0;
9042 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9046 PMD_DRV_LOG(ERR, "Invalid pointer");
9049 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9050 conf->op != RTE_ETH_INPUT_SET_ADD) {
9051 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9055 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9057 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9058 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9062 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9065 PMD_DRV_LOG(ERR, "Failed to parse input set");
9069 /* get inset value in register */
9070 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9071 inset_reg <<= I40E_32_BIT_WIDTH;
9072 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9074 /* Can not change the inset reg for flex payload for fdir,
9075 * it is done by writing I40E_PRTQF_FD_FLXINSET
9076 * in i40e_set_flex_mask_on_pctype.
9078 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9079 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9081 input_set |= pf->fdir.input_set[pctype];
9082 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9083 I40E_INSET_MASK_NUM_REG);
9087 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9089 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9090 (uint32_t)(inset_reg & UINT32_MAX));
9091 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9092 (uint32_t)((inset_reg >>
9093 I40E_32_BIT_WIDTH) & UINT32_MAX));
9095 for (i = 0; i < num; i++)
9096 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
9098 /*clear unused mask registers of the pctype */
9099 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9100 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
9102 i40e_global_cfg_warning(I40E_WARNING_FD_MSK);
9103 I40E_WRITE_FLUSH(hw);
9105 pf->fdir.input_set[pctype] = input_set;
9110 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9115 PMD_DRV_LOG(ERR, "Invalid pointer");
9119 switch (info->info_type) {
9120 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9121 i40e_get_symmetric_hash_enable_per_port(hw,
9122 &(info->info.enable));
9124 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9125 ret = i40e_get_hash_filter_global_config(hw,
9126 &(info->info.global_conf));
9129 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9139 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9144 PMD_DRV_LOG(ERR, "Invalid pointer");
9148 switch (info->info_type) {
9149 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9150 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9152 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9153 ret = i40e_set_hash_filter_global_config(hw,
9154 &(info->info.global_conf));
9156 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9157 ret = i40e_hash_filter_inset_select(hw,
9158 &(info->info.input_set_conf));
9162 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9171 /* Operations for hash function */
9173 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9174 enum rte_filter_op filter_op,
9177 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9180 switch (filter_op) {
9181 case RTE_ETH_FILTER_NOP:
9183 case RTE_ETH_FILTER_GET:
9184 ret = i40e_hash_filter_get(hw,
9185 (struct rte_eth_hash_filter_info *)arg);
9187 case RTE_ETH_FILTER_SET:
9188 ret = i40e_hash_filter_set(hw,
9189 (struct rte_eth_hash_filter_info *)arg);
9192 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9201 /* Convert ethertype filter structure */
9203 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9204 struct i40e_ethertype_filter *filter)
9206 rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
9207 filter->input.ether_type = input->ether_type;
9208 filter->flags = input->flags;
9209 filter->queue = input->queue;
9214 /* Check if there exists the ehtertype filter */
9215 struct i40e_ethertype_filter *
9216 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9217 const struct i40e_ethertype_filter_input *input)
9221 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9225 return ethertype_rule->hash_map[ret];
9228 /* Add ethertype filter in SW list */
9230 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9231 struct i40e_ethertype_filter *filter)
9233 struct i40e_ethertype_rule *rule = &pf->ethertype;
9236 ret = rte_hash_add_key(rule->hash_table, &filter->input);
9239 "Failed to insert ethertype filter"
9240 " to hash table %d!",
9244 rule->hash_map[ret] = filter;
9246 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9251 /* Delete ethertype filter in SW list */
9253 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9254 struct i40e_ethertype_filter_input *input)
9256 struct i40e_ethertype_rule *rule = &pf->ethertype;
9257 struct i40e_ethertype_filter *filter;
9260 ret = rte_hash_del_key(rule->hash_table, input);
9263 "Failed to delete ethertype filter"
9264 " to hash table %d!",
9268 filter = rule->hash_map[ret];
9269 rule->hash_map[ret] = NULL;
9271 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9278 * Configure ethertype filter, which can director packet by filtering
9279 * with mac address and ether_type or only ether_type
9282 i40e_ethertype_filter_set(struct i40e_pf *pf,
9283 struct rte_eth_ethertype_filter *filter,
9286 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9287 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9288 struct i40e_ethertype_filter *ethertype_filter, *node;
9289 struct i40e_ethertype_filter check_filter;
9290 struct i40e_control_filter_stats stats;
9294 if (filter->queue >= pf->dev_data->nb_rx_queues) {
9295 PMD_DRV_LOG(ERR, "Invalid queue ID");
9298 if (filter->ether_type == ETHER_TYPE_IPv4 ||
9299 filter->ether_type == ETHER_TYPE_IPv6) {
9301 "unsupported ether_type(0x%04x) in control packet filter.",
9302 filter->ether_type);
9305 if (filter->ether_type == ETHER_TYPE_VLAN)
9306 PMD_DRV_LOG(WARNING,
9307 "filter vlan ether_type in first tag is not supported.");
9309 /* Check if there is the filter in SW list */
9310 memset(&check_filter, 0, sizeof(check_filter));
9311 i40e_ethertype_filter_convert(filter, &check_filter);
9312 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9313 &check_filter.input);
9315 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9319 if (!add && !node) {
9320 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9324 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9325 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9326 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9327 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9328 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9330 memset(&stats, 0, sizeof(stats));
9331 ret = i40e_aq_add_rem_control_packet_filter(hw,
9332 filter->mac_addr.addr_bytes,
9333 filter->ether_type, flags,
9335 filter->queue, add, &stats, NULL);
9338 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9339 ret, stats.mac_etype_used, stats.etype_used,
9340 stats.mac_etype_free, stats.etype_free);
9344 /* Add or delete a filter in SW list */
9346 ethertype_filter = rte_zmalloc("ethertype_filter",
9347 sizeof(*ethertype_filter), 0);
9348 if (ethertype_filter == NULL) {
9349 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
9353 rte_memcpy(ethertype_filter, &check_filter,
9354 sizeof(check_filter));
9355 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9357 rte_free(ethertype_filter);
9359 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9366 * Handle operations for ethertype filter.
9369 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9370 enum rte_filter_op filter_op,
9373 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9376 if (filter_op == RTE_ETH_FILTER_NOP)
9380 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9385 switch (filter_op) {
9386 case RTE_ETH_FILTER_ADD:
9387 ret = i40e_ethertype_filter_set(pf,
9388 (struct rte_eth_ethertype_filter *)arg,
9391 case RTE_ETH_FILTER_DELETE:
9392 ret = i40e_ethertype_filter_set(pf,
9393 (struct rte_eth_ethertype_filter *)arg,
9397 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9405 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9406 enum rte_filter_type filter_type,
9407 enum rte_filter_op filter_op,
9415 switch (filter_type) {
9416 case RTE_ETH_FILTER_NONE:
9417 /* For global configuration */
9418 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9420 case RTE_ETH_FILTER_HASH:
9421 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9423 case RTE_ETH_FILTER_MACVLAN:
9424 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9426 case RTE_ETH_FILTER_ETHERTYPE:
9427 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9429 case RTE_ETH_FILTER_TUNNEL:
9430 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9432 case RTE_ETH_FILTER_FDIR:
9433 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9435 case RTE_ETH_FILTER_GENERIC:
9436 if (filter_op != RTE_ETH_FILTER_GET)
9438 *(const void **)arg = &i40e_flow_ops;
9441 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9451 * Check and enable Extended Tag.
9452 * Enabling Extended Tag is important for 40G performance.
9455 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9457 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9461 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9464 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9468 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9469 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9474 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9477 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9481 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9482 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9485 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9486 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9489 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9496 * As some registers wouldn't be reset unless a global hardware reset,
9497 * hardware initialization is needed to put those registers into an
9498 * expected initial state.
9501 i40e_hw_init(struct rte_eth_dev *dev)
9503 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9505 i40e_enable_extended_tag(dev);
9507 /* clear the PF Queue Filter control register */
9508 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9510 /* Disable symmetric hash per port */
9511 i40e_set_symmetric_hash_enable_per_port(hw, 0);
9515 * For X722 it is possible to have multiple pctypes mapped to the same flowtype
9516 * however this function will return only one highest pctype index,
9517 * which is not quite correct. This is known problem of i40e driver
9518 * and needs to be fixed later.
9520 enum i40e_filter_pctype
9521 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
9524 uint64_t pctype_mask;
9526 if (flow_type < I40E_FLOW_TYPE_MAX) {
9527 pctype_mask = adapter->pctypes_tbl[flow_type];
9528 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
9529 if (pctype_mask & (1ULL << i))
9530 return (enum i40e_filter_pctype)i;
9533 return I40E_FILTER_PCTYPE_INVALID;
9537 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
9538 enum i40e_filter_pctype pctype)
9541 uint64_t pctype_mask = 1ULL << pctype;
9543 for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
9545 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
9549 return RTE_ETH_FLOW_UNKNOWN;
9553 * On X710, performance number is far from the expectation on recent firmware
9554 * versions; on XL710, performance number is also far from the expectation on
9555 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9556 * mode is enabled and port MAC address is equal to the packet destination MAC
9557 * address. The fix for this issue may not be integrated in the following
9558 * firmware version. So the workaround in software driver is needed. It needs
9559 * to modify the initial values of 3 internal only registers for both X710 and
9560 * XL710. Note that the values for X710 or XL710 could be different, and the
9561 * workaround can be removed when it is fixed in firmware in the future.
9564 /* For both X710 and XL710 */
9565 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1 0x10000200
9566 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x203F0200
9567 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
9569 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9570 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
9573 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9574 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9577 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
9579 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
9580 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
9583 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9585 enum i40e_status_code status;
9586 struct i40e_aq_get_phy_abilities_resp phy_ab;
9590 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9594 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
9597 rte_delay_us(100000);
9599 status = i40e_aq_get_phy_capabilities(hw, false,
9600 true, &phy_ab, NULL);
9608 i40e_configure_registers(struct i40e_hw *hw)
9614 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9615 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9616 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9622 for (i = 0; i < RTE_DIM(reg_table); i++) {
9623 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9624 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9626 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9627 else /* For X710/XL710/XXV710 */
9628 if (hw->aq.fw_maj_ver < 6)
9630 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
9633 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
9636 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9637 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9639 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9640 else /* For X710/XL710/XXV710 */
9642 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9645 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9646 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9647 I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9649 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9652 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9655 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9658 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9662 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9663 reg_table[i].addr, reg);
9664 if (reg == reg_table[i].val)
9667 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9668 reg_table[i].val, NULL);
9671 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9672 reg_table[i].val, reg_table[i].addr);
9675 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9676 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9680 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
9681 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
9682 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
9683 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9685 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9690 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9691 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9695 /* Configure for double VLAN RX stripping */
9696 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9697 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9698 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9699 ret = i40e_aq_debug_write_register(hw,
9700 I40E_VSI_TSR(vsi->vsi_id),
9703 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9705 return I40E_ERR_CONFIG;
9709 /* Configure for double VLAN TX insertion */
9710 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9711 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9712 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9713 ret = i40e_aq_debug_write_register(hw,
9714 I40E_VSI_L2TAGSTXVALID(
9715 vsi->vsi_id), reg, NULL);
9718 "Failed to update VSI_L2TAGSTXVALID[%d]",
9720 return I40E_ERR_CONFIG;
9728 * i40e_aq_add_mirror_rule
9729 * @hw: pointer to the hardware structure
9730 * @seid: VEB seid to add mirror rule to
9731 * @dst_id: destination vsi seid
9732 * @entries: Buffer which contains the entities to be mirrored
9733 * @count: number of entities contained in the buffer
9734 * @rule_id:the rule_id of the rule to be added
9736 * Add a mirror rule for a given veb.
9739 static enum i40e_status_code
9740 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9741 uint16_t seid, uint16_t dst_id,
9742 uint16_t rule_type, uint16_t *entries,
9743 uint16_t count, uint16_t *rule_id)
9745 struct i40e_aq_desc desc;
9746 struct i40e_aqc_add_delete_mirror_rule cmd;
9747 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9748 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9751 enum i40e_status_code status;
9753 i40e_fill_default_direct_cmd_desc(&desc,
9754 i40e_aqc_opc_add_mirror_rule);
9755 memset(&cmd, 0, sizeof(cmd));
9757 buff_len = sizeof(uint16_t) * count;
9758 desc.datalen = rte_cpu_to_le_16(buff_len);
9760 desc.flags |= rte_cpu_to_le_16(
9761 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9762 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9763 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9764 cmd.num_entries = rte_cpu_to_le_16(count);
9765 cmd.seid = rte_cpu_to_le_16(seid);
9766 cmd.destination = rte_cpu_to_le_16(dst_id);
9768 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9769 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9771 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9772 hw->aq.asq_last_status, resp->rule_id,
9773 resp->mirror_rules_used, resp->mirror_rules_free);
9774 *rule_id = rte_le_to_cpu_16(resp->rule_id);
9780 * i40e_aq_del_mirror_rule
9781 * @hw: pointer to the hardware structure
9782 * @seid: VEB seid to add mirror rule to
9783 * @entries: Buffer which contains the entities to be mirrored
9784 * @count: number of entities contained in the buffer
9785 * @rule_id:the rule_id of the rule to be delete
9787 * Delete a mirror rule for a given veb.
9790 static enum i40e_status_code
9791 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9792 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9793 uint16_t count, uint16_t rule_id)
9795 struct i40e_aq_desc desc;
9796 struct i40e_aqc_add_delete_mirror_rule cmd;
9797 uint16_t buff_len = 0;
9798 enum i40e_status_code status;
9801 i40e_fill_default_direct_cmd_desc(&desc,
9802 i40e_aqc_opc_delete_mirror_rule);
9803 memset(&cmd, 0, sizeof(cmd));
9804 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9805 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9807 cmd.num_entries = count;
9808 buff_len = sizeof(uint16_t) * count;
9809 desc.datalen = rte_cpu_to_le_16(buff_len);
9810 buff = (void *)entries;
9812 /* rule id is filled in destination field for deleting mirror rule */
9813 cmd.destination = rte_cpu_to_le_16(rule_id);
9815 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9816 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9817 cmd.seid = rte_cpu_to_le_16(seid);
9819 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9820 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9826 * i40e_mirror_rule_set
9827 * @dev: pointer to the hardware structure
9828 * @mirror_conf: mirror rule info
9829 * @sw_id: mirror rule's sw_id
9830 * @on: enable/disable
9832 * set a mirror rule.
9836 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9837 struct rte_eth_mirror_conf *mirror_conf,
9838 uint8_t sw_id, uint8_t on)
9840 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9841 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9842 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9843 struct i40e_mirror_rule *parent = NULL;
9844 uint16_t seid, dst_seid, rule_id;
9848 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9850 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9852 "mirror rule can not be configured without veb or vfs.");
9855 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9856 PMD_DRV_LOG(ERR, "mirror table is full.");
9859 if (mirror_conf->dst_pool > pf->vf_num) {
9860 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9861 mirror_conf->dst_pool);
9865 seid = pf->main_vsi->veb->seid;
9867 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9868 if (sw_id <= it->index) {
9874 if (mirr_rule && sw_id == mirr_rule->index) {
9876 PMD_DRV_LOG(ERR, "mirror rule exists.");
9879 ret = i40e_aq_del_mirror_rule(hw, seid,
9880 mirr_rule->rule_type,
9882 mirr_rule->num_entries, mirr_rule->id);
9885 "failed to remove mirror rule: ret = %d, aq_err = %d.",
9886 ret, hw->aq.asq_last_status);
9889 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9890 rte_free(mirr_rule);
9891 pf->nb_mirror_rule--;
9895 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9899 mirr_rule = rte_zmalloc("i40e_mirror_rule",
9900 sizeof(struct i40e_mirror_rule) , 0);
9902 PMD_DRV_LOG(ERR, "failed to allocate memory");
9903 return I40E_ERR_NO_MEMORY;
9905 switch (mirror_conf->rule_type) {
9906 case ETH_MIRROR_VLAN:
9907 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9908 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9909 mirr_rule->entries[j] =
9910 mirror_conf->vlan.vlan_id[i];
9915 PMD_DRV_LOG(ERR, "vlan is not specified.");
9916 rte_free(mirr_rule);
9919 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9921 case ETH_MIRROR_VIRTUAL_POOL_UP:
9922 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9923 /* check if the specified pool bit is out of range */
9924 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9925 PMD_DRV_LOG(ERR, "pool mask is out of range.");
9926 rte_free(mirr_rule);
9929 for (i = 0, j = 0; i < pf->vf_num; i++) {
9930 if (mirror_conf->pool_mask & (1ULL << i)) {
9931 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9935 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9936 /* add pf vsi to entries */
9937 mirr_rule->entries[j] = pf->main_vsi_seid;
9941 PMD_DRV_LOG(ERR, "pool is not specified.");
9942 rte_free(mirr_rule);
9945 /* egress and ingress in aq commands means from switch but not port */
9946 mirr_rule->rule_type =
9947 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9948 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9949 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9951 case ETH_MIRROR_UPLINK_PORT:
9952 /* egress and ingress in aq commands means from switch but not port*/
9953 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9955 case ETH_MIRROR_DOWNLINK_PORT:
9956 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9959 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9960 mirror_conf->rule_type);
9961 rte_free(mirr_rule);
9965 /* If the dst_pool is equal to vf_num, consider it as PF */
9966 if (mirror_conf->dst_pool == pf->vf_num)
9967 dst_seid = pf->main_vsi_seid;
9969 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9971 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9972 mirr_rule->rule_type, mirr_rule->entries,
9976 "failed to add mirror rule: ret = %d, aq_err = %d.",
9977 ret, hw->aq.asq_last_status);
9978 rte_free(mirr_rule);
9982 mirr_rule->index = sw_id;
9983 mirr_rule->num_entries = j;
9984 mirr_rule->id = rule_id;
9985 mirr_rule->dst_vsi_seid = dst_seid;
9988 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9990 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9992 pf->nb_mirror_rule++;
9997 * i40e_mirror_rule_reset
9998 * @dev: pointer to the device
9999 * @sw_id: mirror rule's sw_id
10001 * reset a mirror rule.
10005 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10007 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10008 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10009 struct i40e_mirror_rule *it, *mirr_rule = NULL;
10013 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10015 seid = pf->main_vsi->veb->seid;
10017 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10018 if (sw_id == it->index) {
10024 ret = i40e_aq_del_mirror_rule(hw, seid,
10025 mirr_rule->rule_type,
10026 mirr_rule->entries,
10027 mirr_rule->num_entries, mirr_rule->id);
10030 "failed to remove mirror rule: status = %d, aq_err = %d.",
10031 ret, hw->aq.asq_last_status);
10034 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10035 rte_free(mirr_rule);
10036 pf->nb_mirror_rule--;
10038 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10045 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10047 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10048 uint64_t systim_cycles;
10050 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10051 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10054 return systim_cycles;
10058 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10060 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10061 uint64_t rx_tstamp;
10063 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10064 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10071 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10073 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10074 uint64_t tx_tstamp;
10076 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10077 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10084 i40e_start_timecounters(struct rte_eth_dev *dev)
10086 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10087 struct i40e_adapter *adapter =
10088 (struct i40e_adapter *)dev->data->dev_private;
10089 struct rte_eth_link link;
10090 uint32_t tsync_inc_l;
10091 uint32_t tsync_inc_h;
10093 /* Get current link speed. */
10094 memset(&link, 0, sizeof(link));
10095 i40e_dev_link_update(dev, 1);
10096 rte_i40e_dev_atomic_read_link_status(dev, &link);
10098 switch (link.link_speed) {
10099 case ETH_SPEED_NUM_40G:
10100 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10101 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10103 case ETH_SPEED_NUM_10G:
10104 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10105 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10107 case ETH_SPEED_NUM_1G:
10108 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10109 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10116 /* Set the timesync increment value. */
10117 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10118 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10120 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10121 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10122 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10124 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10125 adapter->systime_tc.cc_shift = 0;
10126 adapter->systime_tc.nsec_mask = 0;
10128 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10129 adapter->rx_tstamp_tc.cc_shift = 0;
10130 adapter->rx_tstamp_tc.nsec_mask = 0;
10132 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10133 adapter->tx_tstamp_tc.cc_shift = 0;
10134 adapter->tx_tstamp_tc.nsec_mask = 0;
10138 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10140 struct i40e_adapter *adapter =
10141 (struct i40e_adapter *)dev->data->dev_private;
10143 adapter->systime_tc.nsec += delta;
10144 adapter->rx_tstamp_tc.nsec += delta;
10145 adapter->tx_tstamp_tc.nsec += delta;
10151 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10154 struct i40e_adapter *adapter =
10155 (struct i40e_adapter *)dev->data->dev_private;
10157 ns = rte_timespec_to_ns(ts);
10159 /* Set the timecounters to a new value. */
10160 adapter->systime_tc.nsec = ns;
10161 adapter->rx_tstamp_tc.nsec = ns;
10162 adapter->tx_tstamp_tc.nsec = ns;
10168 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10170 uint64_t ns, systime_cycles;
10171 struct i40e_adapter *adapter =
10172 (struct i40e_adapter *)dev->data->dev_private;
10174 systime_cycles = i40e_read_systime_cyclecounter(dev);
10175 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10176 *ts = rte_ns_to_timespec(ns);
10182 i40e_timesync_enable(struct rte_eth_dev *dev)
10184 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10185 uint32_t tsync_ctl_l;
10186 uint32_t tsync_ctl_h;
10188 /* Stop the timesync system time. */
10189 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10190 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10191 /* Reset the timesync system time value. */
10192 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10193 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10195 i40e_start_timecounters(dev);
10197 /* Clear timesync registers. */
10198 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10199 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10200 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10201 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10202 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10203 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10205 /* Enable timestamping of PTP packets. */
10206 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10207 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10209 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10210 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10211 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10213 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10214 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10220 i40e_timesync_disable(struct rte_eth_dev *dev)
10222 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10223 uint32_t tsync_ctl_l;
10224 uint32_t tsync_ctl_h;
10226 /* Disable timestamping of transmitted PTP packets. */
10227 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10228 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10230 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10231 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10233 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10234 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10236 /* Reset the timesync increment value. */
10237 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10238 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10244 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10245 struct timespec *timestamp, uint32_t flags)
10247 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10248 struct i40e_adapter *adapter =
10249 (struct i40e_adapter *)dev->data->dev_private;
10251 uint32_t sync_status;
10252 uint32_t index = flags & 0x03;
10253 uint64_t rx_tstamp_cycles;
10256 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10257 if ((sync_status & (1 << index)) == 0)
10260 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10261 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10262 *timestamp = rte_ns_to_timespec(ns);
10268 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10269 struct timespec *timestamp)
10271 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10272 struct i40e_adapter *adapter =
10273 (struct i40e_adapter *)dev->data->dev_private;
10275 uint32_t sync_status;
10276 uint64_t tx_tstamp_cycles;
10279 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10280 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10283 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10284 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10285 *timestamp = rte_ns_to_timespec(ns);
10291 * i40e_parse_dcb_configure - parse dcb configure from user
10292 * @dev: the device being configured
10293 * @dcb_cfg: pointer of the result of parse
10294 * @*tc_map: bit map of enabled traffic classes
10296 * Returns 0 on success, negative value on failure
10299 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10300 struct i40e_dcbx_config *dcb_cfg,
10303 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10304 uint8_t i, tc_bw, bw_lf;
10306 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10308 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10309 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10310 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10314 /* assume each tc has the same bw */
10315 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10316 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10317 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10318 /* to ensure the sum of tcbw is equal to 100 */
10319 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10320 for (i = 0; i < bw_lf; i++)
10321 dcb_cfg->etscfg.tcbwtable[i]++;
10323 /* assume each tc has the same Transmission Selection Algorithm */
10324 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10325 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10327 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10328 dcb_cfg->etscfg.prioritytable[i] =
10329 dcb_rx_conf->dcb_tc[i];
10331 /* FW needs one App to configure HW */
10332 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10333 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10334 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10335 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10337 if (dcb_rx_conf->nb_tcs == 0)
10338 *tc_map = 1; /* tc0 only */
10340 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10342 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10343 dcb_cfg->pfc.willing = 0;
10344 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10345 dcb_cfg->pfc.pfcenable = *tc_map;
10351 static enum i40e_status_code
10352 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10353 struct i40e_aqc_vsi_properties_data *info,
10354 uint8_t enabled_tcmap)
10356 enum i40e_status_code ret;
10357 int i, total_tc = 0;
10358 uint16_t qpnum_per_tc, bsf, qp_idx;
10359 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10360 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10361 uint16_t used_queues;
10363 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10364 if (ret != I40E_SUCCESS)
10367 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10368 if (enabled_tcmap & (1 << i))
10373 vsi->enabled_tc = enabled_tcmap;
10375 /* different VSI has different queues assigned */
10376 if (vsi->type == I40E_VSI_MAIN)
10377 used_queues = dev_data->nb_rx_queues -
10378 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10379 else if (vsi->type == I40E_VSI_VMDQ2)
10380 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10382 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10383 return I40E_ERR_NO_AVAILABLE_VSI;
10386 qpnum_per_tc = used_queues / total_tc;
10387 /* Number of queues per enabled TC */
10388 if (qpnum_per_tc == 0) {
10389 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10390 return I40E_ERR_INVALID_QP_ID;
10392 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10393 I40E_MAX_Q_PER_TC);
10394 bsf = rte_bsf32(qpnum_per_tc);
10397 * Configure TC and queue mapping parameters, for enabled TC,
10398 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10399 * default queue will serve it.
10402 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10403 if (vsi->enabled_tc & (1 << i)) {
10404 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10405 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10406 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10407 qp_idx += qpnum_per_tc;
10409 info->tc_mapping[i] = 0;
10412 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10413 if (vsi->type == I40E_VSI_SRIOV) {
10414 info->mapping_flags |=
10415 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10416 for (i = 0; i < vsi->nb_qps; i++)
10417 info->queue_mapping[i] =
10418 rte_cpu_to_le_16(vsi->base_queue + i);
10420 info->mapping_flags |=
10421 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10422 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10424 info->valid_sections |=
10425 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10427 return I40E_SUCCESS;
10431 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10432 * @veb: VEB to be configured
10433 * @tc_map: enabled TC bitmap
10435 * Returns 0 on success, negative value on failure
10437 static enum i40e_status_code
10438 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10440 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10441 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10442 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10443 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10444 enum i40e_status_code ret = I40E_SUCCESS;
10448 /* Check if enabled_tc is same as existing or new TCs */
10449 if (veb->enabled_tc == tc_map)
10452 /* configure tc bandwidth */
10453 memset(&veb_bw, 0, sizeof(veb_bw));
10454 veb_bw.tc_valid_bits = tc_map;
10455 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10456 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10457 if (tc_map & BIT_ULL(i))
10458 veb_bw.tc_bw_share_credits[i] = 1;
10460 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10464 "AQ command Config switch_comp BW allocation per TC failed = %d",
10465 hw->aq.asq_last_status);
10469 memset(&ets_query, 0, sizeof(ets_query));
10470 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10472 if (ret != I40E_SUCCESS) {
10474 "Failed to get switch_comp ETS configuration %u",
10475 hw->aq.asq_last_status);
10478 memset(&bw_query, 0, sizeof(bw_query));
10479 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10481 if (ret != I40E_SUCCESS) {
10483 "Failed to get switch_comp bandwidth configuration %u",
10484 hw->aq.asq_last_status);
10488 /* store and print out BW info */
10489 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10490 veb->bw_info.bw_max = ets_query.tc_bw_max;
10491 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10492 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10493 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10494 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10495 I40E_16_BIT_WIDTH);
10496 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10497 veb->bw_info.bw_ets_share_credits[i] =
10498 bw_query.tc_bw_share_credits[i];
10499 veb->bw_info.bw_ets_credits[i] =
10500 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10501 /* 4 bits per TC, 4th bit is reserved */
10502 veb->bw_info.bw_ets_max[i] =
10503 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10504 RTE_LEN2MASK(3, uint8_t));
10505 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10506 veb->bw_info.bw_ets_share_credits[i]);
10507 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10508 veb->bw_info.bw_ets_credits[i]);
10509 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10510 veb->bw_info.bw_ets_max[i]);
10513 veb->enabled_tc = tc_map;
10520 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10521 * @vsi: VSI to be configured
10522 * @tc_map: enabled TC bitmap
10524 * Returns 0 on success, negative value on failure
10526 static enum i40e_status_code
10527 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10529 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10530 struct i40e_vsi_context ctxt;
10531 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10532 enum i40e_status_code ret = I40E_SUCCESS;
10535 /* Check if enabled_tc is same as existing or new TCs */
10536 if (vsi->enabled_tc == tc_map)
10539 /* configure tc bandwidth */
10540 memset(&bw_data, 0, sizeof(bw_data));
10541 bw_data.tc_valid_bits = tc_map;
10542 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10543 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10544 if (tc_map & BIT_ULL(i))
10545 bw_data.tc_bw_credits[i] = 1;
10547 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10550 "AQ command Config VSI BW allocation per TC failed = %d",
10551 hw->aq.asq_last_status);
10554 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10555 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10557 /* Update Queue Pairs Mapping for currently enabled UPs */
10558 ctxt.seid = vsi->seid;
10559 ctxt.pf_num = hw->pf_id;
10561 ctxt.uplink_seid = vsi->uplink_seid;
10562 ctxt.info = vsi->info;
10564 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10568 /* Update the VSI after updating the VSI queue-mapping information */
10569 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10571 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10572 hw->aq.asq_last_status);
10575 /* update the local VSI info with updated queue map */
10576 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10577 sizeof(vsi->info.tc_mapping));
10578 rte_memcpy(&vsi->info.queue_mapping,
10579 &ctxt.info.queue_mapping,
10580 sizeof(vsi->info.queue_mapping));
10581 vsi->info.mapping_flags = ctxt.info.mapping_flags;
10582 vsi->info.valid_sections = 0;
10584 /* query and update current VSI BW information */
10585 ret = i40e_vsi_get_bw_config(vsi);
10588 "Failed updating vsi bw info, err %s aq_err %s",
10589 i40e_stat_str(hw, ret),
10590 i40e_aq_str(hw, hw->aq.asq_last_status));
10594 vsi->enabled_tc = tc_map;
10601 * i40e_dcb_hw_configure - program the dcb setting to hw
10602 * @pf: pf the configuration is taken on
10603 * @new_cfg: new configuration
10604 * @tc_map: enabled TC bitmap
10606 * Returns 0 on success, negative value on failure
10608 static enum i40e_status_code
10609 i40e_dcb_hw_configure(struct i40e_pf *pf,
10610 struct i40e_dcbx_config *new_cfg,
10613 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10614 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10615 struct i40e_vsi *main_vsi = pf->main_vsi;
10616 struct i40e_vsi_list *vsi_list;
10617 enum i40e_status_code ret;
10621 /* Use the FW API if FW > v4.4*/
10622 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10623 (hw->aq.fw_maj_ver >= 5))) {
10625 "FW < v4.4, can not use FW LLDP API to configure DCB");
10626 return I40E_ERR_FIRMWARE_API_VERSION;
10629 /* Check if need reconfiguration */
10630 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10631 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10632 return I40E_SUCCESS;
10635 /* Copy the new config to the current config */
10636 *old_cfg = *new_cfg;
10637 old_cfg->etsrec = old_cfg->etscfg;
10638 ret = i40e_set_dcb_config(hw);
10640 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10641 i40e_stat_str(hw, ret),
10642 i40e_aq_str(hw, hw->aq.asq_last_status));
10645 /* set receive Arbiter to RR mode and ETS scheme by default */
10646 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10647 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10648 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
10649 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10650 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10651 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10652 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10653 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10654 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10655 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10656 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10657 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10658 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10660 /* get local mib to check whether it is configured correctly */
10662 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10663 /* Get Local DCB Config */
10664 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10665 &hw->local_dcbx_config);
10667 /* if Veb is created, need to update TC of it at first */
10668 if (main_vsi->veb) {
10669 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10671 PMD_INIT_LOG(WARNING,
10672 "Failed configuring TC for VEB seid=%d",
10673 main_vsi->veb->seid);
10675 /* Update each VSI */
10676 i40e_vsi_config_tc(main_vsi, tc_map);
10677 if (main_vsi->veb) {
10678 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10679 /* Beside main VSI and VMDQ VSIs, only enable default
10680 * TC for other VSIs
10682 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10683 ret = i40e_vsi_config_tc(vsi_list->vsi,
10686 ret = i40e_vsi_config_tc(vsi_list->vsi,
10687 I40E_DEFAULT_TCMAP);
10689 PMD_INIT_LOG(WARNING,
10690 "Failed configuring TC for VSI seid=%d",
10691 vsi_list->vsi->seid);
10695 return I40E_SUCCESS;
10699 * i40e_dcb_init_configure - initial dcb config
10700 * @dev: device being configured
10701 * @sw_dcb: indicate whether dcb is sw configured or hw offload
10703 * Returns 0 on success, negative value on failure
10706 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10708 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10709 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10712 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10713 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10717 /* DCB initialization:
10718 * Update DCB configuration from the Firmware and configure
10719 * LLDP MIB change event.
10721 if (sw_dcb == TRUE) {
10722 ret = i40e_init_dcb(hw);
10723 /* If lldp agent is stopped, the return value from
10724 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10725 * adminq status. Otherwise, it should return success.
10727 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10728 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10729 memset(&hw->local_dcbx_config, 0,
10730 sizeof(struct i40e_dcbx_config));
10731 /* set dcb default configuration */
10732 hw->local_dcbx_config.etscfg.willing = 0;
10733 hw->local_dcbx_config.etscfg.maxtcs = 0;
10734 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10735 hw->local_dcbx_config.etscfg.tsatable[0] =
10737 /* all UPs mapping to TC0 */
10738 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10739 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10740 hw->local_dcbx_config.etsrec =
10741 hw->local_dcbx_config.etscfg;
10742 hw->local_dcbx_config.pfc.willing = 0;
10743 hw->local_dcbx_config.pfc.pfccap =
10744 I40E_MAX_TRAFFIC_CLASS;
10745 /* FW needs one App to configure HW */
10746 hw->local_dcbx_config.numapps = 1;
10747 hw->local_dcbx_config.app[0].selector =
10748 I40E_APP_SEL_ETHTYPE;
10749 hw->local_dcbx_config.app[0].priority = 3;
10750 hw->local_dcbx_config.app[0].protocolid =
10751 I40E_APP_PROTOID_FCOE;
10752 ret = i40e_set_dcb_config(hw);
10755 "default dcb config fails. err = %d, aq_err = %d.",
10756 ret, hw->aq.asq_last_status);
10761 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10762 ret, hw->aq.asq_last_status);
10766 ret = i40e_aq_start_lldp(hw, NULL);
10767 if (ret != I40E_SUCCESS)
10768 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10770 ret = i40e_init_dcb(hw);
10772 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10774 "HW doesn't support DCBX offload.");
10779 "DCBX configuration failed, err = %d, aq_err = %d.",
10780 ret, hw->aq.asq_last_status);
10788 * i40e_dcb_setup - setup dcb related config
10789 * @dev: device being configured
10791 * Returns 0 on success, negative value on failure
10794 i40e_dcb_setup(struct rte_eth_dev *dev)
10796 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10797 struct i40e_dcbx_config dcb_cfg;
10798 uint8_t tc_map = 0;
10801 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10802 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10806 if (pf->vf_num != 0)
10807 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10809 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10811 PMD_INIT_LOG(ERR, "invalid dcb config");
10814 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10816 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10824 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10825 struct rte_eth_dcb_info *dcb_info)
10827 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10828 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10829 struct i40e_vsi *vsi = pf->main_vsi;
10830 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10831 uint16_t bsf, tc_mapping;
10834 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10835 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10837 dcb_info->nb_tcs = 1;
10838 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10839 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10840 for (i = 0; i < dcb_info->nb_tcs; i++)
10841 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10843 /* get queue mapping if vmdq is disabled */
10844 if (!pf->nb_cfg_vmdq_vsi) {
10845 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10846 if (!(vsi->enabled_tc & (1 << i)))
10848 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10849 dcb_info->tc_queue.tc_rxq[j][i].base =
10850 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10851 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10852 dcb_info->tc_queue.tc_txq[j][i].base =
10853 dcb_info->tc_queue.tc_rxq[j][i].base;
10854 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10855 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10856 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10857 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10858 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10863 /* get queue mapping if vmdq is enabled */
10865 vsi = pf->vmdq[j].vsi;
10866 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10867 if (!(vsi->enabled_tc & (1 << i)))
10869 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10870 dcb_info->tc_queue.tc_rxq[j][i].base =
10871 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10872 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10873 dcb_info->tc_queue.tc_txq[j][i].base =
10874 dcb_info->tc_queue.tc_rxq[j][i].base;
10875 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10876 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10877 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10878 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10879 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10882 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10887 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10889 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10890 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10891 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10892 uint16_t interval =
10893 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL, 1);
10894 uint16_t msix_intr;
10896 msix_intr = intr_handle->intr_vec[queue_id];
10897 if (msix_intr == I40E_MISC_VEC_ID)
10898 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10899 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10900 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10901 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10903 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10906 I40E_PFINT_DYN_CTLN(msix_intr -
10907 I40E_RX_VEC_START),
10908 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10909 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10910 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10912 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10914 I40E_WRITE_FLUSH(hw);
10915 rte_intr_enable(&pci_dev->intr_handle);
10921 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10923 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10924 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10925 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10926 uint16_t msix_intr;
10928 msix_intr = intr_handle->intr_vec[queue_id];
10929 if (msix_intr == I40E_MISC_VEC_ID)
10930 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10933 I40E_PFINT_DYN_CTLN(msix_intr -
10934 I40E_RX_VEC_START),
10936 I40E_WRITE_FLUSH(hw);
10941 static int i40e_get_regs(struct rte_eth_dev *dev,
10942 struct rte_dev_reg_info *regs)
10944 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10945 uint32_t *ptr_data = regs->data;
10946 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10947 const struct i40e_reg_info *reg_info;
10949 if (ptr_data == NULL) {
10950 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10951 regs->width = sizeof(uint32_t);
10955 /* The first few registers have to be read using AQ operations */
10957 while (i40e_regs_adminq[reg_idx].name) {
10958 reg_info = &i40e_regs_adminq[reg_idx++];
10959 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10961 arr_idx2 <= reg_info->count2;
10963 reg_offset = arr_idx * reg_info->stride1 +
10964 arr_idx2 * reg_info->stride2;
10965 reg_offset += reg_info->base_addr;
10966 ptr_data[reg_offset >> 2] =
10967 i40e_read_rx_ctl(hw, reg_offset);
10971 /* The remaining registers can be read using primitives */
10973 while (i40e_regs_others[reg_idx].name) {
10974 reg_info = &i40e_regs_others[reg_idx++];
10975 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10977 arr_idx2 <= reg_info->count2;
10979 reg_offset = arr_idx * reg_info->stride1 +
10980 arr_idx2 * reg_info->stride2;
10981 reg_offset += reg_info->base_addr;
10982 ptr_data[reg_offset >> 2] =
10983 I40E_READ_REG(hw, reg_offset);
10990 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10992 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10994 /* Convert word count to byte count */
10995 return hw->nvm.sr_size << 1;
10998 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10999 struct rte_dev_eeprom_info *eeprom)
11001 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11002 uint16_t *data = eeprom->data;
11003 uint16_t offset, length, cnt_words;
11006 offset = eeprom->offset >> 1;
11007 length = eeprom->length >> 1;
11008 cnt_words = length;
11010 if (offset > hw->nvm.sr_size ||
11011 offset + length > hw->nvm.sr_size) {
11012 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11016 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11018 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11019 if (ret_code != I40E_SUCCESS || cnt_words != length) {
11020 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11027 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11028 struct ether_addr *mac_addr)
11030 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11031 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11032 struct i40e_vsi *vsi = pf->main_vsi;
11033 struct i40e_mac_filter_info mac_filter;
11034 struct i40e_mac_filter *f;
11037 if (!is_valid_assigned_ether_addr(mac_addr)) {
11038 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11042 TAILQ_FOREACH(f, &vsi->mac_list, next) {
11043 if (is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
11048 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11052 mac_filter = f->mac_info;
11053 ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11054 if (ret != I40E_SUCCESS) {
11055 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11058 memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11059 ret = i40e_vsi_add_mac(vsi, &mac_filter);
11060 if (ret != I40E_SUCCESS) {
11061 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11064 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11066 i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11067 mac_addr->addr_bytes, NULL);
11071 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
11073 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11074 struct rte_eth_dev_data *dev_data = pf->dev_data;
11075 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
11078 /* check if mtu is within the allowed range */
11079 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
11082 /* mtu setting is forbidden if port is start */
11083 if (dev_data->dev_started) {
11084 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
11085 dev_data->port_id);
11089 if (frame_size > ETHER_MAX_LEN)
11090 dev_data->dev_conf.rxmode.jumbo_frame = 1;
11092 dev_data->dev_conf.rxmode.jumbo_frame = 0;
11094 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
11099 /* Restore ethertype filter */
11101 i40e_ethertype_filter_restore(struct i40e_pf *pf)
11103 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11104 struct i40e_ethertype_filter_list
11105 *ethertype_list = &pf->ethertype.ethertype_list;
11106 struct i40e_ethertype_filter *f;
11107 struct i40e_control_filter_stats stats;
11110 TAILQ_FOREACH(f, ethertype_list, rules) {
11112 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
11113 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
11114 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
11115 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
11116 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
11118 memset(&stats, 0, sizeof(stats));
11119 i40e_aq_add_rem_control_packet_filter(hw,
11120 f->input.mac_addr.addr_bytes,
11121 f->input.ether_type,
11122 flags, pf->main_vsi->seid,
11123 f->queue, 1, &stats, NULL);
11125 PMD_DRV_LOG(INFO, "Ethertype filter:"
11126 " mac_etype_used = %u, etype_used = %u,"
11127 " mac_etype_free = %u, etype_free = %u",
11128 stats.mac_etype_used, stats.etype_used,
11129 stats.mac_etype_free, stats.etype_free);
11132 /* Restore tunnel filter */
11134 i40e_tunnel_filter_restore(struct i40e_pf *pf)
11136 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11137 struct i40e_vsi *vsi;
11138 struct i40e_pf_vf *vf;
11139 struct i40e_tunnel_filter_list
11140 *tunnel_list = &pf->tunnel.tunnel_list;
11141 struct i40e_tunnel_filter *f;
11142 struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
11143 bool big_buffer = 0;
11145 TAILQ_FOREACH(f, tunnel_list, rules) {
11147 vsi = pf->main_vsi;
11149 vf = &pf->vfs[f->vf_id];
11152 memset(&cld_filter, 0, sizeof(cld_filter));
11153 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
11154 (struct ether_addr *)&cld_filter.element.outer_mac);
11155 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
11156 (struct ether_addr *)&cld_filter.element.inner_mac);
11157 cld_filter.element.inner_vlan = f->input.inner_vlan;
11158 cld_filter.element.flags = f->input.flags;
11159 cld_filter.element.tenant_id = f->input.tenant_id;
11160 cld_filter.element.queue_number = f->queue;
11161 rte_memcpy(cld_filter.general_fields,
11162 f->input.general_fields,
11163 sizeof(f->input.general_fields));
11165 if (((f->input.flags &
11166 I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
11167 I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
11169 I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
11170 I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
11172 I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
11173 I40E_AQC_ADD_CLOUD_FILTER_0X10))
11177 i40e_aq_add_cloud_filters_big_buffer(hw,
11178 vsi->seid, &cld_filter, 1);
11180 i40e_aq_add_cloud_filters(hw, vsi->seid,
11181 &cld_filter.element, 1);
11185 /* Restore rss filter */
11187 i40e_rss_filter_restore(struct i40e_pf *pf)
11189 struct i40e_rte_flow_rss_conf *conf =
11192 i40e_config_rss_filter(pf, conf, TRUE);
11196 i40e_filter_restore(struct i40e_pf *pf)
11198 i40e_ethertype_filter_restore(pf);
11199 i40e_tunnel_filter_restore(pf);
11200 i40e_fdir_filter_restore(pf);
11201 i40e_rss_filter_restore(pf);
11205 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
11207 if (strcmp(dev->device->driver->name, drv->driver.name))
11214 is_i40e_supported(struct rte_eth_dev *dev)
11216 return is_device_supported(dev, &rte_i40e_pmd);
11219 struct i40e_customized_pctype*
11220 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
11224 for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
11225 if (pf->customized_pctype[i].index == index)
11226 return &pf->customized_pctype[i];
11232 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
11233 uint32_t pkg_size, uint32_t proto_num,
11234 struct rte_pmd_i40e_proto_info *proto)
11236 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11237 uint32_t pctype_num;
11238 struct rte_pmd_i40e_ptype_info *pctype;
11239 uint32_t buff_size;
11240 struct i40e_customized_pctype *new_pctype = NULL;
11242 uint8_t pctype_value;
11247 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11248 (uint8_t *)&pctype_num, sizeof(pctype_num),
11249 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
11251 PMD_DRV_LOG(ERR, "Failed to get pctype number");
11255 PMD_DRV_LOG(INFO, "No new pctype added");
11259 buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
11260 pctype = rte_zmalloc("new_pctype", buff_size, 0);
11262 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11265 /* get information about new pctype list */
11266 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11267 (uint8_t *)pctype, buff_size,
11268 RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
11270 PMD_DRV_LOG(ERR, "Failed to get pctype list");
11275 /* Update customized pctype. */
11276 for (i = 0; i < pctype_num; i++) {
11277 pctype_value = pctype[i].ptype_id;
11278 memset(name, 0, sizeof(name));
11279 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11280 proto_id = pctype[i].protocols[j];
11281 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11283 for (n = 0; n < proto_num; n++) {
11284 if (proto[n].proto_id != proto_id)
11286 strcat(name, proto[n].name);
11291 name[strlen(name) - 1] = '\0';
11292 if (!strcmp(name, "GTPC"))
11294 i40e_find_customized_pctype(pf,
11295 I40E_CUSTOMIZED_GTPC);
11296 else if (!strcmp(name, "GTPU_IPV4"))
11298 i40e_find_customized_pctype(pf,
11299 I40E_CUSTOMIZED_GTPU_IPV4);
11300 else if (!strcmp(name, "GTPU_IPV6"))
11302 i40e_find_customized_pctype(pf,
11303 I40E_CUSTOMIZED_GTPU_IPV6);
11304 else if (!strcmp(name, "GTPU"))
11306 i40e_find_customized_pctype(pf,
11307 I40E_CUSTOMIZED_GTPU);
11309 new_pctype->pctype = pctype_value;
11310 new_pctype->valid = true;
11319 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
11320 uint32_t pkg_size, uint32_t proto_num,
11321 struct rte_pmd_i40e_proto_info *proto)
11323 struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
11324 uint16_t port_id = dev->data->port_id;
11325 uint32_t ptype_num;
11326 struct rte_pmd_i40e_ptype_info *ptype;
11327 uint32_t buff_size;
11329 char name[RTE_PMD_I40E_DDP_NAME_SIZE];
11334 /* get information about new ptype num */
11335 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11336 (uint8_t *)&ptype_num, sizeof(ptype_num),
11337 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
11339 PMD_DRV_LOG(ERR, "Failed to get ptype number");
11343 PMD_DRV_LOG(INFO, "No new ptype added");
11347 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
11348 ptype = rte_zmalloc("new_ptype", buff_size, 0);
11350 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11354 /* get information about new ptype list */
11355 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11356 (uint8_t *)ptype, buff_size,
11357 RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
11359 PMD_DRV_LOG(ERR, "Failed to get ptype list");
11364 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
11365 ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
11366 if (!ptype_mapping) {
11367 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11372 /* Update ptype mapping table. */
11373 for (i = 0; i < ptype_num; i++) {
11374 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
11375 ptype_mapping[i].sw_ptype = 0;
11377 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11378 proto_id = ptype[i].protocols[j];
11379 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11381 for (n = 0; n < proto_num; n++) {
11382 if (proto[n].proto_id != proto_id)
11384 memset(name, 0, sizeof(name));
11385 strcpy(name, proto[n].name);
11386 if (!strncasecmp(name, "PPPOE", 5))
11387 ptype_mapping[i].sw_ptype |=
11388 RTE_PTYPE_L2_ETHER_PPPOE;
11389 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
11391 ptype_mapping[i].sw_ptype |=
11392 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11393 ptype_mapping[i].sw_ptype |=
11395 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
11397 ptype_mapping[i].sw_ptype |=
11398 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11399 ptype_mapping[i].sw_ptype |=
11400 RTE_PTYPE_INNER_L4_FRAG;
11401 } else if (!strncasecmp(name, "OIPV4", 5)) {
11402 ptype_mapping[i].sw_ptype |=
11403 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11405 } else if (!strncasecmp(name, "IPV4", 4) &&
11407 ptype_mapping[i].sw_ptype |=
11408 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11409 else if (!strncasecmp(name, "IPV4", 4) &&
11411 ptype_mapping[i].sw_ptype |=
11412 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11413 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
11415 ptype_mapping[i].sw_ptype |=
11416 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11417 ptype_mapping[i].sw_ptype |=
11419 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
11421 ptype_mapping[i].sw_ptype |=
11422 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11423 ptype_mapping[i].sw_ptype |=
11424 RTE_PTYPE_INNER_L4_FRAG;
11425 } else if (!strncasecmp(name, "OIPV6", 5)) {
11426 ptype_mapping[i].sw_ptype |=
11427 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11429 } else if (!strncasecmp(name, "IPV6", 4) &&
11431 ptype_mapping[i].sw_ptype |=
11432 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11433 else if (!strncasecmp(name, "IPV6", 4) &&
11435 ptype_mapping[i].sw_ptype |=
11436 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11437 else if (!strncasecmp(name, "UDP", 3) &&
11439 ptype_mapping[i].sw_ptype |=
11441 else if (!strncasecmp(name, "UDP", 3) &&
11443 ptype_mapping[i].sw_ptype |=
11444 RTE_PTYPE_INNER_L4_UDP;
11445 else if (!strncasecmp(name, "TCP", 3) &&
11447 ptype_mapping[i].sw_ptype |=
11449 else if (!strncasecmp(name, "TCP", 3) &&
11451 ptype_mapping[i].sw_ptype |=
11452 RTE_PTYPE_INNER_L4_TCP;
11453 else if (!strncasecmp(name, "SCTP", 4) &&
11455 ptype_mapping[i].sw_ptype |=
11457 else if (!strncasecmp(name, "SCTP", 4) &&
11459 ptype_mapping[i].sw_ptype |=
11460 RTE_PTYPE_INNER_L4_SCTP;
11461 else if ((!strncasecmp(name, "ICMP", 4) ||
11462 !strncasecmp(name, "ICMPV6", 6)) &&
11464 ptype_mapping[i].sw_ptype |=
11466 else if ((!strncasecmp(name, "ICMP", 4) ||
11467 !strncasecmp(name, "ICMPV6", 6)) &&
11469 ptype_mapping[i].sw_ptype |=
11470 RTE_PTYPE_INNER_L4_ICMP;
11471 else if (!strncasecmp(name, "GTPC", 4)) {
11472 ptype_mapping[i].sw_ptype |=
11473 RTE_PTYPE_TUNNEL_GTPC;
11475 } else if (!strncasecmp(name, "GTPU", 4)) {
11476 ptype_mapping[i].sw_ptype |=
11477 RTE_PTYPE_TUNNEL_GTPU;
11479 } else if (!strncasecmp(name, "GRENAT", 6)) {
11480 ptype_mapping[i].sw_ptype |=
11481 RTE_PTYPE_TUNNEL_GRENAT;
11483 } else if (!strncasecmp(name, "L2TPV2CTL", 9)) {
11484 ptype_mapping[i].sw_ptype |=
11485 RTE_PTYPE_TUNNEL_L2TP;
11494 ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
11497 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
11499 rte_free(ptype_mapping);
11505 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
11508 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11509 uint32_t proto_num;
11510 struct rte_pmd_i40e_proto_info *proto;
11511 uint32_t buff_size;
11515 /* get information about protocol number */
11516 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11517 (uint8_t *)&proto_num, sizeof(proto_num),
11518 RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
11520 PMD_DRV_LOG(ERR, "Failed to get protocol number");
11524 PMD_DRV_LOG(INFO, "No new protocol added");
11528 buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
11529 proto = rte_zmalloc("new_proto", buff_size, 0);
11531 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11535 /* get information about protocol list */
11536 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11537 (uint8_t *)proto, buff_size,
11538 RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
11540 PMD_DRV_LOG(ERR, "Failed to get protocol list");
11545 /* Check if GTP is supported. */
11546 for (i = 0; i < proto_num; i++) {
11547 if (!strncmp(proto[i].name, "GTP", 3)) {
11548 pf->gtp_support = true;
11553 /* Update customized pctype info */
11554 ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
11557 PMD_DRV_LOG(INFO, "No pctype is updated.");
11559 /* Update customized ptype info */
11560 ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
11563 PMD_DRV_LOG(INFO, "No ptype is updated.");
11568 /* Create a QinQ cloud filter
11570 * The Fortville NIC has limited resources for tunnel filters,
11571 * so we can only reuse existing filters.
11573 * In step 1 we define which Field Vector fields can be used for
11575 * As we do not have the inner tag defined as a field,
11576 * we have to define it first, by reusing one of L1 entries.
11578 * In step 2 we are replacing one of existing filter types with
11579 * a new one for QinQ.
11580 * As we reusing L1 and replacing L2, some of the default filter
11581 * types will disappear,which depends on L1 and L2 entries we reuse.
11583 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
11585 * 1. Create L1 filter of outer vlan (12b) which will be in use
11586 * later when we define the cloud filter.
11587 * a. Valid_flags.replace_cloud = 0
11588 * b. Old_filter = 10 (Stag_Inner_Vlan)
11589 * c. New_filter = 0x10
11590 * d. TR bit = 0xff (optional, not used here)
11591 * e. Buffer – 2 entries:
11592 * i. Byte 0 = 8 (outer vlan FV index).
11594 * Byte 2-3 = 0x0fff
11595 * ii. Byte 0 = 37 (inner vlan FV index).
11597 * Byte 2-3 = 0x0fff
11600 * 2. Create cloud filter using two L1 filters entries: stag and
11601 * new filter(outer vlan+ inner vlan)
11602 * a. Valid_flags.replace_cloud = 1
11603 * b. Old_filter = 1 (instead of outer IP)
11604 * c. New_filter = 0x10
11605 * d. Buffer – 2 entries:
11606 * i. Byte 0 = 0x80 | 7 (valid | Stag).
11607 * Byte 1-3 = 0 (rsv)
11608 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
11609 * Byte 9-11 = 0 (rsv)
11612 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
11614 int ret = -ENOTSUP;
11615 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
11616 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
11617 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11620 memset(&filter_replace, 0,
11621 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11622 memset(&filter_replace_buf, 0,
11623 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11625 /* create L1 filter */
11626 filter_replace.old_filter_type =
11627 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
11628 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11629 filter_replace.tr_bit = 0;
11631 /* Prepare the buffer, 2 entries */
11632 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
11633 filter_replace_buf.data[0] |=
11634 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11635 /* Field Vector 12b mask */
11636 filter_replace_buf.data[2] = 0xff;
11637 filter_replace_buf.data[3] = 0x0f;
11638 filter_replace_buf.data[4] =
11639 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
11640 filter_replace_buf.data[4] |=
11641 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11642 /* Field Vector 12b mask */
11643 filter_replace_buf.data[6] = 0xff;
11644 filter_replace_buf.data[7] = 0x0f;
11645 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11646 &filter_replace_buf);
11647 if (ret != I40E_SUCCESS)
11650 /* Apply the second L2 cloud filter */
11651 memset(&filter_replace, 0,
11652 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11653 memset(&filter_replace_buf, 0,
11654 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11656 /* create L2 filter, input for L2 filter will be L1 filter */
11657 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
11658 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
11659 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11661 /* Prepare the buffer, 2 entries */
11662 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
11663 filter_replace_buf.data[0] |=
11664 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11665 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11666 filter_replace_buf.data[4] |=
11667 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11668 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11669 &filter_replace_buf);
11671 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
11676 i40e_config_rss_filter(struct i40e_pf *pf,
11677 struct i40e_rte_flow_rss_conf *conf, bool add)
11679 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11680 uint32_t i, lut = 0;
11682 struct rte_eth_rss_conf rss_conf = conf->rss_conf;
11683 struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
11686 if (memcmp(conf, rss_info,
11687 sizeof(struct i40e_rte_flow_rss_conf)) == 0) {
11688 i40e_pf_disable_rss(pf);
11689 memset(rss_info, 0,
11690 sizeof(struct i40e_rte_flow_rss_conf));
11699 /* If both VMDQ and RSS enabled, not all of PF queues are configured.
11700 * It's necessary to calculate the actual PF queues that are configured.
11702 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
11703 num = i40e_pf_calc_configured_queues_num(pf);
11705 num = pf->dev_data->nb_rx_queues;
11707 num = RTE_MIN(num, conf->num);
11708 PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
11712 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS");
11716 /* Fill in redirection table */
11717 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
11720 lut = (lut << 8) | (conf->queue[j] & ((0x1 <<
11721 hw->func_caps.rss_table_entry_width) - 1));
11723 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
11726 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
11727 i40e_pf_disable_rss(pf);
11730 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
11731 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
11732 /* Random default keys */
11733 static uint32_t rss_key_default[] = {0x6b793944,
11734 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
11735 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
11736 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
11738 rss_conf.rss_key = (uint8_t *)rss_key_default;
11739 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
11743 i40e_hw_rss_hash_set(pf, &rss_conf);
11745 rte_memcpy(rss_info,
11746 conf, sizeof(struct i40e_rte_flow_rss_conf));
11751 RTE_INIT(i40e_init_log);
11753 i40e_init_log(void)
11755 i40e_logtype_init = rte_log_register("pmd.net.i40e.init");
11756 if (i40e_logtype_init >= 0)
11757 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
11758 i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver");
11759 if (i40e_logtype_driver >= 0)
11760 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);