1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
15 #include <rte_string_fns.h>
17 #include <rte_bus_pci.h>
18 #include <rte_ether.h>
19 #include <rte_ethdev.h>
20 #include <rte_ethdev_pci.h>
21 #include <rte_memzone.h>
22 #include <rte_malloc.h>
23 #include <rte_memcpy.h>
24 #include <rte_alarm.h>
26 #include <rte_eth_ctrl.h>
27 #include <rte_tailq.h>
28 #include <rte_hash_crc.h>
30 #include "i40e_logs.h"
31 #include "base/i40e_prototype.h"
32 #include "base/i40e_adminq_cmd.h"
33 #include "base/i40e_type.h"
34 #include "base/i40e_register.h"
35 #include "base/i40e_dcb.h"
36 #include "i40e_ethdev.h"
37 #include "i40e_rxtx.h"
39 #include "i40e_regs.h"
40 #include "rte_pmd_i40e.h"
42 #define ETH_I40E_FLOATING_VEB_ARG "enable_floating_veb"
43 #define ETH_I40E_FLOATING_VEB_LIST_ARG "floating_veb_list"
45 #define I40E_CLEAR_PXE_WAIT_MS 200
47 /* Maximun number of capability elements */
48 #define I40E_MAX_CAP_ELE_NUM 128
50 /* Wait count and interval */
51 #define I40E_CHK_Q_ENA_COUNT 1000
52 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
54 /* Maximun number of VSI */
55 #define I40E_MAX_NUM_VSIS (384UL)
57 #define I40E_PRE_TX_Q_CFG_WAIT_US 10 /* 10 us */
59 /* Flow control default timer */
60 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
62 /* Flow control enable fwd bit */
63 #define I40E_PRTMAC_FWD_CTRL 0x00000001
65 /* Receive Packet Buffer size */
66 #define I40E_RXPBSIZE (968 * 1024)
69 #define I40E_KILOSHIFT 10
71 /* Flow control default high water */
72 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
74 /* Flow control default low water */
75 #define I40E_DEFAULT_LOW_WATER (0xF2000 >> I40E_KILOSHIFT)
77 /* Receive Average Packet Size in Byte*/
78 #define I40E_PACKET_AVERAGE_SIZE 128
80 /* Mask of PF interrupt causes */
81 #define I40E_PFINT_ICR0_ENA_MASK ( \
82 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
83 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
84 I40E_PFINT_ICR0_ENA_GRST_MASK | \
85 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
86 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
87 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
88 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
89 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
90 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
92 #define I40E_FLOW_TYPES ( \
93 (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
94 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
95 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
96 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
97 (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
98 (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
99 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
100 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
101 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
102 (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
103 (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
105 /* Additional timesync values. */
106 #define I40E_PTP_40GB_INCVAL 0x0199999999ULL
107 #define I40E_PTP_10GB_INCVAL 0x0333333333ULL
108 #define I40E_PTP_1GB_INCVAL 0x2000000000ULL
109 #define I40E_PRTTSYN_TSYNENA 0x80000000
110 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
111 #define I40E_CYCLECOUNTER_MASK 0xffffffffffffffffULL
114 * Below are values for writing un-exposed registers suggested
117 /* Destination MAC address */
118 #define I40E_REG_INSET_L2_DMAC 0xE000000000000000ULL
119 /* Source MAC address */
120 #define I40E_REG_INSET_L2_SMAC 0x1C00000000000000ULL
121 /* Outer (S-Tag) VLAN tag in the outer L2 header */
122 #define I40E_REG_INSET_L2_OUTER_VLAN 0x0000000004000000ULL
123 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
124 #define I40E_REG_INSET_L2_INNER_VLAN 0x0080000000000000ULL
125 /* Single VLAN tag in the inner L2 header */
126 #define I40E_REG_INSET_TUNNEL_VLAN 0x0100000000000000ULL
127 /* Source IPv4 address */
128 #define I40E_REG_INSET_L3_SRC_IP4 0x0001800000000000ULL
129 /* Destination IPv4 address */
130 #define I40E_REG_INSET_L3_DST_IP4 0x0000001800000000ULL
131 /* Source IPv4 address for X722 */
132 #define I40E_X722_REG_INSET_L3_SRC_IP4 0x0006000000000000ULL
133 /* Destination IPv4 address for X722 */
134 #define I40E_X722_REG_INSET_L3_DST_IP4 0x0000060000000000ULL
135 /* IPv4 Protocol for X722 */
136 #define I40E_X722_REG_INSET_L3_IP4_PROTO 0x0010000000000000ULL
137 /* IPv4 Time to Live for X722 */
138 #define I40E_X722_REG_INSET_L3_IP4_TTL 0x0010000000000000ULL
139 /* IPv4 Type of Service (TOS) */
140 #define I40E_REG_INSET_L3_IP4_TOS 0x0040000000000000ULL
142 #define I40E_REG_INSET_L3_IP4_PROTO 0x0004000000000000ULL
143 /* IPv4 Time to Live */
144 #define I40E_REG_INSET_L3_IP4_TTL 0x0004000000000000ULL
145 /* Source IPv6 address */
146 #define I40E_REG_INSET_L3_SRC_IP6 0x0007F80000000000ULL
147 /* Destination IPv6 address */
148 #define I40E_REG_INSET_L3_DST_IP6 0x000007F800000000ULL
149 /* IPv6 Traffic Class (TC) */
150 #define I40E_REG_INSET_L3_IP6_TC 0x0040000000000000ULL
151 /* IPv6 Next Header */
152 #define I40E_REG_INSET_L3_IP6_NEXT_HDR 0x0008000000000000ULL
154 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT 0x0008000000000000ULL
156 #define I40E_REG_INSET_L4_SRC_PORT 0x0000000400000000ULL
157 /* Destination L4 port */
158 #define I40E_REG_INSET_L4_DST_PORT 0x0000000200000000ULL
159 /* SCTP verification tag */
160 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG 0x0000000180000000ULL
161 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
162 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC 0x0000000001C00000ULL
163 /* Source port of tunneling UDP */
164 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT 0x0000000000200000ULL
165 /* Destination port of tunneling UDP */
166 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT 0x0000000000100000ULL
167 /* UDP Tunneling ID, NVGRE/GRE key */
168 #define I40E_REG_INSET_TUNNEL_ID 0x00000000000C0000ULL
169 /* Last ether type */
170 #define I40E_REG_INSET_LAST_ETHER_TYPE 0x0000000000004000ULL
171 /* Tunneling outer destination IPv4 address */
172 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4 0x00000000000000C0ULL
173 /* Tunneling outer destination IPv6 address */
174 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6 0x0000000000003FC0ULL
175 /* 1st word of flex payload */
176 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1 0x0000000000002000ULL
177 /* 2nd word of flex payload */
178 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2 0x0000000000001000ULL
179 /* 3rd word of flex payload */
180 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3 0x0000000000000800ULL
181 /* 4th word of flex payload */
182 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4 0x0000000000000400ULL
183 /* 5th word of flex payload */
184 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5 0x0000000000000200ULL
185 /* 6th word of flex payload */
186 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6 0x0000000000000100ULL
187 /* 7th word of flex payload */
188 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7 0x0000000000000080ULL
189 /* 8th word of flex payload */
190 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8 0x0000000000000040ULL
191 /* all 8 words flex payload */
192 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS 0x0000000000003FC0ULL
193 #define I40E_REG_INSET_MASK_DEFAULT 0x0000000000000000ULL
195 #define I40E_TRANSLATE_INSET 0
196 #define I40E_TRANSLATE_REG 1
198 #define I40E_INSET_IPV4_TOS_MASK 0x0009FF00UL
199 #define I40E_INSET_IPv4_TTL_MASK 0x000D00FFUL
200 #define I40E_INSET_IPV4_PROTO_MASK 0x000DFF00UL
201 #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL
202 #define I40E_INSET_IPV6_HOP_LIMIT_MASK 0x000CFF00UL
203 #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL
205 /* PCI offset for querying capability */
206 #define PCI_DEV_CAP_REG 0xA4
207 /* PCI offset for enabling/disabling Extended Tag */
208 #define PCI_DEV_CTRL_REG 0xA8
209 /* Bit mask of Extended Tag capability */
210 #define PCI_DEV_CAP_EXT_TAG_MASK 0x20
211 /* Bit shift of Extended Tag enable/disable */
212 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
213 /* Bit mask of Extended Tag enable/disable */
214 #define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
216 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
217 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
218 static int i40e_dev_configure(struct rte_eth_dev *dev);
219 static int i40e_dev_start(struct rte_eth_dev *dev);
220 static void i40e_dev_stop(struct rte_eth_dev *dev);
221 static void i40e_dev_close(struct rte_eth_dev *dev);
222 static int i40e_dev_reset(struct rte_eth_dev *dev);
223 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
224 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
225 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
226 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
227 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
228 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
229 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
230 struct rte_eth_stats *stats);
231 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
232 struct rte_eth_xstat *xstats, unsigned n);
233 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
234 struct rte_eth_xstat_name *xstats_names,
236 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
237 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
241 static int i40e_fw_version_get(struct rte_eth_dev *dev,
242 char *fw_version, size_t fw_size);
243 static void i40e_dev_info_get(struct rte_eth_dev *dev,
244 struct rte_eth_dev_info *dev_info);
245 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
248 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
249 enum rte_vlan_type vlan_type,
251 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
252 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
255 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
256 static int i40e_dev_led_on(struct rte_eth_dev *dev);
257 static int i40e_dev_led_off(struct rte_eth_dev *dev);
258 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
259 struct rte_eth_fc_conf *fc_conf);
260 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
261 struct rte_eth_fc_conf *fc_conf);
262 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
263 struct rte_eth_pfc_conf *pfc_conf);
264 static int i40e_macaddr_add(struct rte_eth_dev *dev,
265 struct ether_addr *mac_addr,
268 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
269 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
270 struct rte_eth_rss_reta_entry64 *reta_conf,
272 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
273 struct rte_eth_rss_reta_entry64 *reta_conf,
276 static int i40e_get_cap(struct i40e_hw *hw);
277 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
278 static int i40e_pf_setup(struct i40e_pf *pf);
279 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
280 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
281 static int i40e_dcb_setup(struct rte_eth_dev *dev);
282 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
283 bool offset_loaded, uint64_t *offset, uint64_t *stat);
284 static void i40e_stat_update_48(struct i40e_hw *hw,
290 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
291 static void i40e_dev_interrupt_handler(void *param);
292 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
293 uint32_t base, uint32_t num);
294 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
295 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
297 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
299 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
300 static int i40e_veb_release(struct i40e_veb *veb);
301 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
302 struct i40e_vsi *vsi);
303 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
304 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
305 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
306 struct i40e_macvlan_filter *mv_f,
309 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
310 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
311 struct rte_eth_rss_conf *rss_conf);
312 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
313 struct rte_eth_rss_conf *rss_conf);
314 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
315 struct rte_eth_udp_tunnel *udp_tunnel);
316 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
317 struct rte_eth_udp_tunnel *udp_tunnel);
318 static void i40e_filter_input_set_init(struct i40e_pf *pf);
319 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
320 enum rte_filter_op filter_op,
322 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
323 enum rte_filter_type filter_type,
324 enum rte_filter_op filter_op,
326 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
327 struct rte_eth_dcb_info *dcb_info);
328 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
329 static void i40e_configure_registers(struct i40e_hw *hw);
330 static void i40e_hw_init(struct rte_eth_dev *dev);
331 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
332 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
338 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
339 struct rte_eth_mirror_conf *mirror_conf,
340 uint8_t sw_id, uint8_t on);
341 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
343 static int i40e_timesync_enable(struct rte_eth_dev *dev);
344 static int i40e_timesync_disable(struct rte_eth_dev *dev);
345 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
346 struct timespec *timestamp,
348 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
349 struct timespec *timestamp);
350 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
352 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
354 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
355 struct timespec *timestamp);
356 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
357 const struct timespec *timestamp);
359 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
361 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
364 static int i40e_get_regs(struct rte_eth_dev *dev,
365 struct rte_dev_reg_info *regs);
367 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
369 static int i40e_get_eeprom(struct rte_eth_dev *dev,
370 struct rte_dev_eeprom_info *eeprom);
372 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
373 struct ether_addr *mac_addr);
375 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
377 static int i40e_ethertype_filter_convert(
378 const struct rte_eth_ethertype_filter *input,
379 struct i40e_ethertype_filter *filter);
380 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
381 struct i40e_ethertype_filter *filter);
383 static int i40e_tunnel_filter_convert(
384 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
385 struct i40e_tunnel_filter *tunnel_filter);
386 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
387 struct i40e_tunnel_filter *tunnel_filter);
388 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
390 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
391 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
392 static void i40e_filter_restore(struct i40e_pf *pf);
393 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
395 int i40e_logtype_init;
396 int i40e_logtype_driver;
398 static const struct rte_pci_id pci_id_i40e_map[] = {
399 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
400 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
401 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
402 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
403 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
404 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
405 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
406 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
407 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
408 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
409 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
410 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
411 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
412 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
413 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
414 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
415 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
416 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
417 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
418 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
419 { .vendor_id = 0, /* sentinel */ },
422 static const struct eth_dev_ops i40e_eth_dev_ops = {
423 .dev_configure = i40e_dev_configure,
424 .dev_start = i40e_dev_start,
425 .dev_stop = i40e_dev_stop,
426 .dev_close = i40e_dev_close,
427 .dev_reset = i40e_dev_reset,
428 .promiscuous_enable = i40e_dev_promiscuous_enable,
429 .promiscuous_disable = i40e_dev_promiscuous_disable,
430 .allmulticast_enable = i40e_dev_allmulticast_enable,
431 .allmulticast_disable = i40e_dev_allmulticast_disable,
432 .dev_set_link_up = i40e_dev_set_link_up,
433 .dev_set_link_down = i40e_dev_set_link_down,
434 .link_update = i40e_dev_link_update,
435 .stats_get = i40e_dev_stats_get,
436 .xstats_get = i40e_dev_xstats_get,
437 .xstats_get_names = i40e_dev_xstats_get_names,
438 .stats_reset = i40e_dev_stats_reset,
439 .xstats_reset = i40e_dev_stats_reset,
440 .queue_stats_mapping_set = i40e_dev_queue_stats_mapping_set,
441 .fw_version_get = i40e_fw_version_get,
442 .dev_infos_get = i40e_dev_info_get,
443 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
444 .vlan_filter_set = i40e_vlan_filter_set,
445 .vlan_tpid_set = i40e_vlan_tpid_set,
446 .vlan_offload_set = i40e_vlan_offload_set,
447 .vlan_strip_queue_set = i40e_vlan_strip_queue_set,
448 .vlan_pvid_set = i40e_vlan_pvid_set,
449 .rx_queue_start = i40e_dev_rx_queue_start,
450 .rx_queue_stop = i40e_dev_rx_queue_stop,
451 .tx_queue_start = i40e_dev_tx_queue_start,
452 .tx_queue_stop = i40e_dev_tx_queue_stop,
453 .rx_queue_setup = i40e_dev_rx_queue_setup,
454 .rx_queue_intr_enable = i40e_dev_rx_queue_intr_enable,
455 .rx_queue_intr_disable = i40e_dev_rx_queue_intr_disable,
456 .rx_queue_release = i40e_dev_rx_queue_release,
457 .rx_queue_count = i40e_dev_rx_queue_count,
458 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
459 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
460 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
461 .tx_queue_setup = i40e_dev_tx_queue_setup,
462 .tx_queue_release = i40e_dev_tx_queue_release,
463 .dev_led_on = i40e_dev_led_on,
464 .dev_led_off = i40e_dev_led_off,
465 .flow_ctrl_get = i40e_flow_ctrl_get,
466 .flow_ctrl_set = i40e_flow_ctrl_set,
467 .priority_flow_ctrl_set = i40e_priority_flow_ctrl_set,
468 .mac_addr_add = i40e_macaddr_add,
469 .mac_addr_remove = i40e_macaddr_remove,
470 .reta_update = i40e_dev_rss_reta_update,
471 .reta_query = i40e_dev_rss_reta_query,
472 .rss_hash_update = i40e_dev_rss_hash_update,
473 .rss_hash_conf_get = i40e_dev_rss_hash_conf_get,
474 .udp_tunnel_port_add = i40e_dev_udp_tunnel_port_add,
475 .udp_tunnel_port_del = i40e_dev_udp_tunnel_port_del,
476 .filter_ctrl = i40e_dev_filter_ctrl,
477 .rxq_info_get = i40e_rxq_info_get,
478 .txq_info_get = i40e_txq_info_get,
479 .mirror_rule_set = i40e_mirror_rule_set,
480 .mirror_rule_reset = i40e_mirror_rule_reset,
481 .timesync_enable = i40e_timesync_enable,
482 .timesync_disable = i40e_timesync_disable,
483 .timesync_read_rx_timestamp = i40e_timesync_read_rx_timestamp,
484 .timesync_read_tx_timestamp = i40e_timesync_read_tx_timestamp,
485 .get_dcb_info = i40e_dev_get_dcb_info,
486 .timesync_adjust_time = i40e_timesync_adjust_time,
487 .timesync_read_time = i40e_timesync_read_time,
488 .timesync_write_time = i40e_timesync_write_time,
489 .get_reg = i40e_get_regs,
490 .get_eeprom_length = i40e_get_eeprom_length,
491 .get_eeprom = i40e_get_eeprom,
492 .mac_addr_set = i40e_set_default_mac_addr,
493 .mtu_set = i40e_dev_mtu_set,
494 .tm_ops_get = i40e_tm_ops_get,
497 /* store statistics names and its offset in stats structure */
498 struct rte_i40e_xstats_name_off {
499 char name[RTE_ETH_XSTATS_NAME_SIZE];
503 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
504 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
505 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
506 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
507 {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
508 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
509 rx_unknown_protocol)},
510 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
511 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
512 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
513 {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
516 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
517 sizeof(rte_i40e_stats_strings[0]))
519 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
520 {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
521 tx_dropped_link_down)},
522 {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
523 {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
525 {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
526 {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
528 {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
530 {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
532 {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
533 {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
534 {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
535 {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
536 {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
537 {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
539 {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
541 {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
543 {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
545 {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
547 {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
549 {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
551 {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
553 {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
554 mac_short_packet_dropped)},
555 {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
557 {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
558 {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
559 {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
561 {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
563 {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
565 {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
567 {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
569 {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
571 {"rx_flow_director_atr_match_packets",
572 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
573 {"rx_flow_director_sb_match_packets",
574 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
575 {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
577 {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
579 {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
581 {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
585 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
586 sizeof(rte_i40e_hw_port_strings[0]))
588 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
589 {"xon_packets", offsetof(struct i40e_hw_port_stats,
591 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
595 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
596 sizeof(rte_i40e_rxq_prio_strings[0]))
598 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
599 {"xon_packets", offsetof(struct i40e_hw_port_stats,
601 {"xoff_packets", offsetof(struct i40e_hw_port_stats,
603 {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
604 priority_xon_2_xoff)},
607 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
608 sizeof(rte_i40e_txq_prio_strings[0]))
610 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
611 struct rte_pci_device *pci_dev)
613 return rte_eth_dev_pci_generic_probe(pci_dev,
614 sizeof(struct i40e_adapter), eth_i40e_dev_init);
617 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
619 return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
622 static struct rte_pci_driver rte_i40e_pmd = {
623 .id_table = pci_id_i40e_map,
624 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
625 RTE_PCI_DRV_IOVA_AS_VA,
626 .probe = eth_i40e_pci_probe,
627 .remove = eth_i40e_pci_remove,
631 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
632 struct rte_eth_link *link)
634 struct rte_eth_link *dst = link;
635 struct rte_eth_link *src = &(dev->data->dev_link);
637 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
638 *(uint64_t *)src) == 0)
645 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
646 struct rte_eth_link *link)
648 struct rte_eth_link *dst = &(dev->data->dev_link);
649 struct rte_eth_link *src = link;
651 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
652 *(uint64_t *)src) == 0)
658 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
659 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
660 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
662 #ifndef I40E_GLQF_ORT
663 #define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4))
665 #ifndef I40E_GLQF_PIT
666 #define I40E_GLQF_PIT(_i) (0x00268C80 + ((_i) * 4))
668 #ifndef I40E_GLQF_L3_MAP
669 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
672 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
675 * Force global configuration for flexible payload
676 * to the first 16 bytes of the corresponding L2/L3/L4 paylod.
677 * This should be removed from code once proper
678 * configuration API is added to avoid configuration conflicts
679 * between ports of the same device.
681 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
682 I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
683 I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
686 * Initialize registers for parsing packet type of QinQ
687 * This should be removed from code once proper
688 * configuration API is added to avoid configuration conflicts
689 * between ports of the same device.
691 I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
692 I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
695 #define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
698 * Add a ethertype filter to drop all flow control frames transmitted
702 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
704 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
705 uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
706 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
707 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
710 ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
711 I40E_FLOW_CONTROL_ETHERTYPE, flags,
712 pf->main_vsi_seid, 0,
716 "Failed to add filter to drop flow control frames from VSIs.");
720 floating_veb_list_handler(__rte_unused const char *key,
721 const char *floating_veb_value,
725 unsigned int count = 0;
728 bool *vf_floating_veb = opaque;
730 while (isblank(*floating_veb_value))
731 floating_veb_value++;
733 /* Reset floating VEB configuration for VFs */
734 for (idx = 0; idx < I40E_MAX_VF; idx++)
735 vf_floating_veb[idx] = false;
739 while (isblank(*floating_veb_value))
740 floating_veb_value++;
741 if (*floating_veb_value == '\0')
744 idx = strtoul(floating_veb_value, &end, 10);
745 if (errno || end == NULL)
747 while (isblank(*end))
751 } else if ((*end == ';') || (*end == '\0')) {
753 if (min == I40E_MAX_VF)
755 if (max >= I40E_MAX_VF)
756 max = I40E_MAX_VF - 1;
757 for (idx = min; idx <= max; idx++) {
758 vf_floating_veb[idx] = true;
765 floating_veb_value = end + 1;
766 } while (*end != '\0');
775 config_vf_floating_veb(struct rte_devargs *devargs,
776 uint16_t floating_veb,
777 bool *vf_floating_veb)
779 struct rte_kvargs *kvlist;
781 const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
785 /* All the VFs attach to the floating VEB by default
786 * when the floating VEB is enabled.
788 for (i = 0; i < I40E_MAX_VF; i++)
789 vf_floating_veb[i] = true;
794 kvlist = rte_kvargs_parse(devargs->args, NULL);
798 if (!rte_kvargs_count(kvlist, floating_veb_list)) {
799 rte_kvargs_free(kvlist);
802 /* When the floating_veb_list parameter exists, all the VFs
803 * will attach to the legacy VEB firstly, then configure VFs
804 * to the floating VEB according to the floating_veb_list.
806 if (rte_kvargs_process(kvlist, floating_veb_list,
807 floating_veb_list_handler,
808 vf_floating_veb) < 0) {
809 rte_kvargs_free(kvlist);
812 rte_kvargs_free(kvlist);
816 i40e_check_floating_handler(__rte_unused const char *key,
818 __rte_unused void *opaque)
820 if (strcmp(value, "1"))
827 is_floating_veb_supported(struct rte_devargs *devargs)
829 struct rte_kvargs *kvlist;
830 const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
835 kvlist = rte_kvargs_parse(devargs->args, NULL);
839 if (!rte_kvargs_count(kvlist, floating_veb_key)) {
840 rte_kvargs_free(kvlist);
843 /* Floating VEB is enabled when there's key-value:
844 * enable_floating_veb=1
846 if (rte_kvargs_process(kvlist, floating_veb_key,
847 i40e_check_floating_handler, NULL) < 0) {
848 rte_kvargs_free(kvlist);
851 rte_kvargs_free(kvlist);
857 config_floating_veb(struct rte_eth_dev *dev)
859 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
860 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
861 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
863 memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
865 if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
867 is_floating_veb_supported(pci_dev->device.devargs);
868 config_vf_floating_veb(pci_dev->device.devargs,
870 pf->floating_veb_list);
872 pf->floating_veb = false;
876 #define I40E_L2_TAGS_S_TAG_SHIFT 1
877 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
880 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
882 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
883 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
884 char ethertype_hash_name[RTE_HASH_NAMESIZE];
887 struct rte_hash_parameters ethertype_hash_params = {
888 .name = ethertype_hash_name,
889 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
890 .key_len = sizeof(struct i40e_ethertype_filter_input),
891 .hash_func = rte_hash_crc,
892 .hash_func_init_val = 0,
893 .socket_id = rte_socket_id(),
896 /* Initialize ethertype filter rule list and hash */
897 TAILQ_INIT(ðertype_rule->ethertype_list);
898 snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
899 "ethertype_%s", dev->device->name);
900 ethertype_rule->hash_table = rte_hash_create(ðertype_hash_params);
901 if (!ethertype_rule->hash_table) {
902 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
905 ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
906 sizeof(struct i40e_ethertype_filter *) *
907 I40E_MAX_ETHERTYPE_FILTER_NUM,
909 if (!ethertype_rule->hash_map) {
911 "Failed to allocate memory for ethertype hash map!");
913 goto err_ethertype_hash_map_alloc;
918 err_ethertype_hash_map_alloc:
919 rte_hash_free(ethertype_rule->hash_table);
925 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
927 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
928 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
929 char tunnel_hash_name[RTE_HASH_NAMESIZE];
932 struct rte_hash_parameters tunnel_hash_params = {
933 .name = tunnel_hash_name,
934 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
935 .key_len = sizeof(struct i40e_tunnel_filter_input),
936 .hash_func = rte_hash_crc,
937 .hash_func_init_val = 0,
938 .socket_id = rte_socket_id(),
941 /* Initialize tunnel filter rule list and hash */
942 TAILQ_INIT(&tunnel_rule->tunnel_list);
943 snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
944 "tunnel_%s", dev->device->name);
945 tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
946 if (!tunnel_rule->hash_table) {
947 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
950 tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
951 sizeof(struct i40e_tunnel_filter *) *
952 I40E_MAX_TUNNEL_FILTER_NUM,
954 if (!tunnel_rule->hash_map) {
956 "Failed to allocate memory for tunnel hash map!");
958 goto err_tunnel_hash_map_alloc;
963 err_tunnel_hash_map_alloc:
964 rte_hash_free(tunnel_rule->hash_table);
970 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
972 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
973 struct i40e_fdir_info *fdir_info = &pf->fdir;
974 char fdir_hash_name[RTE_HASH_NAMESIZE];
977 struct rte_hash_parameters fdir_hash_params = {
978 .name = fdir_hash_name,
979 .entries = I40E_MAX_FDIR_FILTER_NUM,
980 .key_len = sizeof(struct rte_eth_fdir_input),
981 .hash_func = rte_hash_crc,
982 .hash_func_init_val = 0,
983 .socket_id = rte_socket_id(),
986 /* Initialize flow director filter rule list and hash */
987 TAILQ_INIT(&fdir_info->fdir_list);
988 snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
989 "fdir_%s", dev->device->name);
990 fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
991 if (!fdir_info->hash_table) {
992 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
995 fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
996 sizeof(struct i40e_fdir_filter *) *
997 I40E_MAX_FDIR_FILTER_NUM,
999 if (!fdir_info->hash_map) {
1001 "Failed to allocate memory for fdir hash map!");
1003 goto err_fdir_hash_map_alloc;
1007 err_fdir_hash_map_alloc:
1008 rte_hash_free(fdir_info->hash_table);
1014 i40e_init_customized_info(struct i40e_pf *pf)
1018 /* Initialize customized pctype */
1019 for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1020 pf->customized_pctype[i].index = i;
1021 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1022 pf->customized_pctype[i].valid = false;
1025 pf->gtp_support = false;
1029 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1031 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1032 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1033 struct i40e_queue_regions *info = &pf->queue_region;
1036 for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1037 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1039 memset(info, 0, sizeof(struct i40e_queue_regions));
1043 eth_i40e_dev_init(struct rte_eth_dev *dev)
1045 struct rte_pci_device *pci_dev;
1046 struct rte_intr_handle *intr_handle;
1047 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1048 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1049 struct i40e_vsi *vsi;
1052 uint8_t aq_fail = 0;
1054 PMD_INIT_FUNC_TRACE();
1056 dev->dev_ops = &i40e_eth_dev_ops;
1057 dev->rx_pkt_burst = i40e_recv_pkts;
1058 dev->tx_pkt_burst = i40e_xmit_pkts;
1059 dev->tx_pkt_prepare = i40e_prep_pkts;
1061 /* for secondary processes, we don't initialise any further as primary
1062 * has already done this work. Only check we don't need a different
1064 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1065 i40e_set_rx_function(dev);
1066 i40e_set_tx_function(dev);
1069 i40e_set_default_ptype_table(dev);
1070 i40e_set_default_pctype_table(dev);
1071 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1072 intr_handle = &pci_dev->intr_handle;
1074 rte_eth_copy_pci_info(dev, pci_dev);
1076 pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1077 pf->adapter->eth_dev = dev;
1078 pf->dev_data = dev->data;
1080 hw->back = I40E_PF_TO_ADAPTER(pf);
1081 hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1084 "Hardware is not available, as address is NULL");
1088 hw->vendor_id = pci_dev->id.vendor_id;
1089 hw->device_id = pci_dev->id.device_id;
1090 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1091 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1092 hw->bus.device = pci_dev->addr.devid;
1093 hw->bus.func = pci_dev->addr.function;
1094 hw->adapter_stopped = 0;
1096 /* Make sure all is clean before doing PF reset */
1099 /* Initialize the hardware */
1102 /* Reset here to make sure all is clean for each PF */
1103 ret = i40e_pf_reset(hw);
1105 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1109 /* Initialize the shared code (base driver) */
1110 ret = i40e_init_shared_code(hw);
1112 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1117 * To work around the NVM issue, initialize registers
1118 * for flexible payload and packet type of QinQ by
1119 * software. It should be removed once issues are fixed
1122 i40e_GLQF_reg_init(hw);
1124 /* Initialize the input set for filters (hash and fd) to default value */
1125 i40e_filter_input_set_init(pf);
1127 /* Initialize the parameters for adminq */
1128 i40e_init_adminq_parameter(hw);
1129 ret = i40e_init_adminq(hw);
1130 if (ret != I40E_SUCCESS) {
1131 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1134 PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1135 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1136 hw->aq.api_maj_ver, hw->aq.api_min_ver,
1137 ((hw->nvm.version >> 12) & 0xf),
1138 ((hw->nvm.version >> 4) & 0xff),
1139 (hw->nvm.version & 0xf), hw->nvm.eetrack);
1141 /* initialise the L3_MAP register */
1142 ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1145 PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
1147 /* Need the special FW version to support floating VEB */
1148 config_floating_veb(dev);
1149 /* Clear PXE mode */
1150 i40e_clear_pxe_mode(hw);
1151 i40e_dev_sync_phy_type(hw);
1154 * On X710, performance number is far from the expectation on recent
1155 * firmware versions. The fix for this issue may not be integrated in
1156 * the following firmware version. So the workaround in software driver
1157 * is needed. It needs to modify the initial values of 3 internal only
1158 * registers. Note that the workaround can be removed when it is fixed
1159 * in firmware in the future.
1161 i40e_configure_registers(hw);
1163 /* Get hw capabilities */
1164 ret = i40e_get_cap(hw);
1165 if (ret != I40E_SUCCESS) {
1166 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1167 goto err_get_capabilities;
1170 /* Initialize parameters for PF */
1171 ret = i40e_pf_parameter_init(dev);
1173 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1174 goto err_parameter_init;
1177 /* Initialize the queue management */
1178 ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1180 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1181 goto err_qp_pool_init;
1183 ret = i40e_res_pool_init(&pf->msix_pool, 1,
1184 hw->func_caps.num_msix_vectors - 1);
1186 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1187 goto err_msix_pool_init;
1190 /* Initialize lan hmc */
1191 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1192 hw->func_caps.num_rx_qp, 0, 0);
1193 if (ret != I40E_SUCCESS) {
1194 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1195 goto err_init_lan_hmc;
1198 /* Configure lan hmc */
1199 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1200 if (ret != I40E_SUCCESS) {
1201 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1202 goto err_configure_lan_hmc;
1205 /* Get and check the mac address */
1206 i40e_get_mac_addr(hw, hw->mac.addr);
1207 if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1208 PMD_INIT_LOG(ERR, "mac address is not valid");
1210 goto err_get_mac_addr;
1212 /* Copy the permanent MAC address */
1213 ether_addr_copy((struct ether_addr *) hw->mac.addr,
1214 (struct ether_addr *) hw->mac.perm_addr);
1216 /* Disable flow control */
1217 hw->fc.requested_mode = I40E_FC_NONE;
1218 i40e_set_fc(hw, &aq_fail, TRUE);
1220 /* Set the global registers with default ether type value */
1221 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER, ETHER_TYPE_VLAN);
1222 if (ret != I40E_SUCCESS) {
1224 "Failed to set the default outer VLAN ether type");
1225 goto err_setup_pf_switch;
1228 /* PF setup, which includes VSI setup */
1229 ret = i40e_pf_setup(pf);
1231 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1232 goto err_setup_pf_switch;
1235 /* reset all stats of the device, including pf and main vsi */
1236 i40e_dev_stats_reset(dev);
1240 /* Disable double vlan by default */
1241 i40e_vsi_config_double_vlan(vsi, FALSE);
1243 /* Disable S-TAG identification when floating_veb is disabled */
1244 if (!pf->floating_veb) {
1245 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1246 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1247 ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1248 I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1252 if (!vsi->max_macaddrs)
1253 len = ETHER_ADDR_LEN;
1255 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1257 /* Should be after VSI initialized */
1258 dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1259 if (!dev->data->mac_addrs) {
1261 "Failed to allocated memory for storing mac address");
1264 ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1265 &dev->data->mac_addrs[0]);
1267 /* Init dcb to sw mode by default */
1268 ret = i40e_dcb_init_configure(dev, TRUE);
1269 if (ret != I40E_SUCCESS) {
1270 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1271 pf->flags &= ~I40E_FLAG_DCB;
1273 /* Update HW struct after DCB configuration */
1276 /* initialize pf host driver to setup SRIOV resource if applicable */
1277 i40e_pf_host_init(dev);
1279 /* register callback func to eal lib */
1280 rte_intr_callback_register(intr_handle,
1281 i40e_dev_interrupt_handler, dev);
1283 /* configure and enable device interrupt */
1284 i40e_pf_config_irq0(hw, TRUE);
1285 i40e_pf_enable_irq0(hw);
1287 /* enable uio intr after callback register */
1288 rte_intr_enable(intr_handle);
1290 * Add an ethertype filter to drop all flow control frames transmitted
1291 * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1294 i40e_add_tx_flow_control_drop_filter(pf);
1296 /* Set the max frame size to 0x2600 by default,
1297 * in case other drivers changed the default value.
1299 i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1301 /* initialize mirror rule list */
1302 TAILQ_INIT(&pf->mirror_list);
1304 /* initialize Traffic Manager configuration */
1305 i40e_tm_conf_init(dev);
1307 /* Initialize customized information */
1308 i40e_init_customized_info(pf);
1310 ret = i40e_init_ethtype_filter_list(dev);
1312 goto err_init_ethtype_filter_list;
1313 ret = i40e_init_tunnel_filter_list(dev);
1315 goto err_init_tunnel_filter_list;
1316 ret = i40e_init_fdir_filter_list(dev);
1318 goto err_init_fdir_filter_list;
1320 /* initialize queue region configuration */
1321 i40e_init_queue_region_conf(dev);
1325 err_init_fdir_filter_list:
1326 rte_free(pf->tunnel.hash_table);
1327 rte_free(pf->tunnel.hash_map);
1328 err_init_tunnel_filter_list:
1329 rte_free(pf->ethertype.hash_table);
1330 rte_free(pf->ethertype.hash_map);
1331 err_init_ethtype_filter_list:
1332 rte_free(dev->data->mac_addrs);
1334 i40e_vsi_release(pf->main_vsi);
1335 err_setup_pf_switch:
1337 err_configure_lan_hmc:
1338 (void)i40e_shutdown_lan_hmc(hw);
1340 i40e_res_pool_destroy(&pf->msix_pool);
1342 i40e_res_pool_destroy(&pf->qp_pool);
1345 err_get_capabilities:
1346 (void)i40e_shutdown_adminq(hw);
1352 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1354 struct i40e_ethertype_filter *p_ethertype;
1355 struct i40e_ethertype_rule *ethertype_rule;
1357 ethertype_rule = &pf->ethertype;
1358 /* Remove all ethertype filter rules and hash */
1359 if (ethertype_rule->hash_map)
1360 rte_free(ethertype_rule->hash_map);
1361 if (ethertype_rule->hash_table)
1362 rte_hash_free(ethertype_rule->hash_table);
1364 while ((p_ethertype = TAILQ_FIRST(ðertype_rule->ethertype_list))) {
1365 TAILQ_REMOVE(ðertype_rule->ethertype_list,
1366 p_ethertype, rules);
1367 rte_free(p_ethertype);
1372 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1374 struct i40e_tunnel_filter *p_tunnel;
1375 struct i40e_tunnel_rule *tunnel_rule;
1377 tunnel_rule = &pf->tunnel;
1378 /* Remove all tunnel director rules and hash */
1379 if (tunnel_rule->hash_map)
1380 rte_free(tunnel_rule->hash_map);
1381 if (tunnel_rule->hash_table)
1382 rte_hash_free(tunnel_rule->hash_table);
1384 while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1385 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1391 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1393 struct i40e_fdir_filter *p_fdir;
1394 struct i40e_fdir_info *fdir_info;
1396 fdir_info = &pf->fdir;
1397 /* Remove all flow director rules and hash */
1398 if (fdir_info->hash_map)
1399 rte_free(fdir_info->hash_map);
1400 if (fdir_info->hash_table)
1401 rte_hash_free(fdir_info->hash_table);
1403 while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1404 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1410 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1413 struct rte_pci_device *pci_dev;
1414 struct rte_intr_handle *intr_handle;
1416 struct i40e_filter_control_settings settings;
1417 struct rte_flow *p_flow;
1419 uint8_t aq_fail = 0;
1421 PMD_INIT_FUNC_TRACE();
1423 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1426 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1427 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1428 pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1429 intr_handle = &pci_dev->intr_handle;
1431 if (hw->adapter_stopped == 0)
1432 i40e_dev_close(dev);
1434 dev->dev_ops = NULL;
1435 dev->rx_pkt_burst = NULL;
1436 dev->tx_pkt_burst = NULL;
1438 /* Clear PXE mode */
1439 i40e_clear_pxe_mode(hw);
1441 /* Unconfigure filter control */
1442 memset(&settings, 0, sizeof(settings));
1443 ret = i40e_set_filter_control(hw, &settings);
1445 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1448 /* Disable flow control */
1449 hw->fc.requested_mode = I40E_FC_NONE;
1450 i40e_set_fc(hw, &aq_fail, TRUE);
1452 /* uninitialize pf host driver */
1453 i40e_pf_host_uninit(dev);
1455 rte_free(dev->data->mac_addrs);
1456 dev->data->mac_addrs = NULL;
1458 /* disable uio intr before callback unregister */
1459 rte_intr_disable(intr_handle);
1461 /* register callback func to eal lib */
1462 rte_intr_callback_unregister(intr_handle,
1463 i40e_dev_interrupt_handler, dev);
1465 i40e_rm_ethtype_filter_list(pf);
1466 i40e_rm_tunnel_filter_list(pf);
1467 i40e_rm_fdir_filter_list(pf);
1469 /* Remove all flows */
1470 while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1471 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1475 /* Remove all Traffic Manager configuration */
1476 i40e_tm_conf_uninit(dev);
1482 i40e_dev_configure(struct rte_eth_dev *dev)
1484 struct i40e_adapter *ad =
1485 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1486 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1487 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1488 enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1491 ret = i40e_dev_sync_phy_type(hw);
1495 /* Initialize to TRUE. If any of Rx queues doesn't meet the
1496 * bulk allocation or vector Rx preconditions we will reset it.
1498 ad->rx_bulk_alloc_allowed = true;
1499 ad->rx_vec_allowed = true;
1500 ad->tx_simple_allowed = true;
1501 ad->tx_vec_allowed = true;
1503 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1504 ret = i40e_fdir_setup(pf);
1505 if (ret != I40E_SUCCESS) {
1506 PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1509 ret = i40e_fdir_configure(dev);
1511 PMD_DRV_LOG(ERR, "failed to configure fdir.");
1515 i40e_fdir_teardown(pf);
1517 ret = i40e_dev_init_vlan(dev);
1522 * Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1523 * RSS setting have different requirements.
1524 * General PMD driver call sequence are NIC init, configure,
1525 * rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1526 * will try to lookup the VSI that specific queue belongs to if VMDQ
1527 * applicable. So, VMDQ setting has to be done before
1528 * rx/tx_queue_setup(). This function is good to place vmdq_setup.
1529 * For RSS setting, it will try to calculate actual configured RX queue
1530 * number, which will be available after rx_queue_setup(). dev_start()
1531 * function is good to place RSS setup.
1533 if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1534 ret = i40e_vmdq_setup(dev);
1539 if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1540 ret = i40e_dcb_setup(dev);
1542 PMD_DRV_LOG(ERR, "failed to configure DCB.");
1547 TAILQ_INIT(&pf->flow_list);
1552 /* need to release vmdq resource if exists */
1553 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1554 i40e_vsi_release(pf->vmdq[i].vsi);
1555 pf->vmdq[i].vsi = NULL;
1560 /* need to release fdir resource if exists */
1561 i40e_fdir_teardown(pf);
1566 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1568 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1569 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1570 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1571 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1572 uint16_t msix_vect = vsi->msix_intr;
1575 for (i = 0; i < vsi->nb_qps; i++) {
1576 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1577 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1581 if (vsi->type != I40E_VSI_SRIOV) {
1582 if (!rte_intr_allow_others(intr_handle)) {
1583 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1584 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1586 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1589 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1590 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1592 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1597 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1598 vsi->user_param + (msix_vect - 1);
1600 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1601 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1603 I40E_WRITE_FLUSH(hw);
1607 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1608 int base_queue, int nb_queue,
1613 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1615 /* Bind all RX queues to allocated MSIX interrupt */
1616 for (i = 0; i < nb_queue; i++) {
1617 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1618 itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1619 ((base_queue + i + 1) <<
1620 I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1621 (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1622 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1624 if (i == nb_queue - 1)
1625 val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1626 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1629 /* Write first RX queue to Link list register as the head element */
1630 if (vsi->type != I40E_VSI_SRIOV) {
1632 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1634 if (msix_vect == I40E_MISC_VEC_ID) {
1635 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1637 I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1639 I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1641 I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1644 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1646 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1648 I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1650 I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1657 if (msix_vect == I40E_MISC_VEC_ID) {
1659 I40E_VPINT_LNKLST0(vsi->user_param),
1661 I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1663 I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1665 /* num_msix_vectors_vf needs to minus irq0 */
1666 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1667 vsi->user_param + (msix_vect - 1);
1669 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1671 I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1673 I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1677 I40E_WRITE_FLUSH(hw);
1681 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1683 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1684 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1685 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1686 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1687 uint16_t msix_vect = vsi->msix_intr;
1688 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1689 uint16_t queue_idx = 0;
1694 for (i = 0; i < vsi->nb_qps; i++) {
1695 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1696 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1699 /* INTENA flag is not auto-cleared for interrupt */
1700 val = I40E_READ_REG(hw, I40E_GLINT_CTL);
1701 val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
1702 I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK |
1703 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
1704 I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
1706 /* VF bind interrupt */
1707 if (vsi->type == I40E_VSI_SRIOV) {
1708 __vsi_queues_bind_intr(vsi, msix_vect,
1709 vsi->base_queue, vsi->nb_qps,
1714 /* PF & VMDq bind interrupt */
1715 if (rte_intr_dp_is_en(intr_handle)) {
1716 if (vsi->type == I40E_VSI_MAIN) {
1719 } else if (vsi->type == I40E_VSI_VMDQ2) {
1720 struct i40e_vsi *main_vsi =
1721 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1722 queue_idx = vsi->base_queue - main_vsi->nb_qps;
1727 for (i = 0; i < vsi->nb_used_qps; i++) {
1729 if (!rte_intr_allow_others(intr_handle))
1730 /* allow to share MISC_VEC_ID */
1731 msix_vect = I40E_MISC_VEC_ID;
1733 /* no enough msix_vect, map all to one */
1734 __vsi_queues_bind_intr(vsi, msix_vect,
1735 vsi->base_queue + i,
1736 vsi->nb_used_qps - i,
1738 for (; !!record && i < vsi->nb_used_qps; i++)
1739 intr_handle->intr_vec[queue_idx + i] =
1743 /* 1:1 queue/msix_vect mapping */
1744 __vsi_queues_bind_intr(vsi, msix_vect,
1745 vsi->base_queue + i, 1,
1748 intr_handle->intr_vec[queue_idx + i] = msix_vect;
1756 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1758 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1759 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1760 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1761 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1762 uint16_t interval = i40e_calc_itr_interval(\
1763 RTE_LIBRTE_I40E_ITR_INTERVAL);
1764 uint16_t msix_intr, i;
1766 if (rte_intr_allow_others(intr_handle))
1767 for (i = 0; i < vsi->nb_msix; i++) {
1768 msix_intr = vsi->msix_intr + i;
1769 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1770 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1771 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1772 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1774 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
1777 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1778 I40E_PFINT_DYN_CTL0_INTENA_MASK |
1779 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1780 (0 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1782 I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT));
1784 I40E_WRITE_FLUSH(hw);
1788 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1790 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1791 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1792 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1793 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1794 uint16_t msix_intr, i;
1796 if (rte_intr_allow_others(intr_handle))
1797 for (i = 0; i < vsi->nb_msix; i++) {
1798 msix_intr = vsi->msix_intr + i;
1799 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1803 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
1805 I40E_WRITE_FLUSH(hw);
1808 static inline uint8_t
1809 i40e_parse_link_speeds(uint16_t link_speeds)
1811 uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1813 if (link_speeds & ETH_LINK_SPEED_40G)
1814 link_speed |= I40E_LINK_SPEED_40GB;
1815 if (link_speeds & ETH_LINK_SPEED_25G)
1816 link_speed |= I40E_LINK_SPEED_25GB;
1817 if (link_speeds & ETH_LINK_SPEED_20G)
1818 link_speed |= I40E_LINK_SPEED_20GB;
1819 if (link_speeds & ETH_LINK_SPEED_10G)
1820 link_speed |= I40E_LINK_SPEED_10GB;
1821 if (link_speeds & ETH_LINK_SPEED_1G)
1822 link_speed |= I40E_LINK_SPEED_1GB;
1823 if (link_speeds & ETH_LINK_SPEED_100M)
1824 link_speed |= I40E_LINK_SPEED_100MB;
1830 i40e_phy_conf_link(struct i40e_hw *hw,
1832 uint8_t force_speed,
1835 enum i40e_status_code status;
1836 struct i40e_aq_get_phy_abilities_resp phy_ab;
1837 struct i40e_aq_set_phy_config phy_conf;
1838 enum i40e_aq_phy_type cnt;
1839 uint32_t phy_type_mask = 0;
1841 const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1842 I40E_AQ_PHY_FLAG_PAUSE_RX |
1843 I40E_AQ_PHY_FLAG_PAUSE_RX |
1844 I40E_AQ_PHY_FLAG_LOW_POWER;
1845 const uint8_t advt = I40E_LINK_SPEED_40GB |
1846 I40E_LINK_SPEED_25GB |
1847 I40E_LINK_SPEED_10GB |
1848 I40E_LINK_SPEED_1GB |
1849 I40E_LINK_SPEED_100MB;
1853 status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1858 /* If link already up, no need to set up again */
1859 if (is_up && phy_ab.phy_type != 0)
1860 return I40E_SUCCESS;
1862 memset(&phy_conf, 0, sizeof(phy_conf));
1864 /* bits 0-2 use the values from get_phy_abilities_resp */
1866 abilities |= phy_ab.abilities & mask;
1868 /* update ablities and speed */
1869 if (abilities & I40E_AQ_PHY_AN_ENABLED)
1870 phy_conf.link_speed = advt;
1872 phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed;
1874 phy_conf.abilities = abilities;
1878 /* To enable link, phy_type mask needs to include each type */
1879 for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_MAX; cnt++)
1880 phy_type_mask |= 1 << cnt;
1882 /* use get_phy_abilities_resp value for the rest */
1883 phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
1884 phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
1885 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
1886 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
1887 phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1888 phy_conf.eee_capability = phy_ab.eee_capability;
1889 phy_conf.eeer = phy_ab.eeer_val;
1890 phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1892 PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
1893 phy_ab.abilities, phy_ab.link_speed);
1894 PMD_DRV_LOG(DEBUG, "\tConfig: abilities %x, link_speed %x",
1895 phy_conf.abilities, phy_conf.link_speed);
1897 status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
1901 return I40E_SUCCESS;
1905 i40e_apply_link_speed(struct rte_eth_dev *dev)
1908 uint8_t abilities = 0;
1909 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1910 struct rte_eth_conf *conf = &dev->data->dev_conf;
1912 speed = i40e_parse_link_speeds(conf->link_speeds);
1913 abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1914 if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
1915 abilities |= I40E_AQ_PHY_AN_ENABLED;
1916 abilities |= I40E_AQ_PHY_LINK_ENABLED;
1918 return i40e_phy_conf_link(hw, abilities, speed, true);
1922 i40e_dev_start(struct rte_eth_dev *dev)
1924 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1925 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1926 struct i40e_vsi *main_vsi = pf->main_vsi;
1928 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1929 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1930 uint32_t intr_vector = 0;
1931 struct i40e_vsi *vsi;
1933 hw->adapter_stopped = 0;
1935 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1937 "Invalid link_speeds for port %u, autonegotiation disabled",
1938 dev->data->port_id);
1942 rte_intr_disable(intr_handle);
1944 if ((rte_intr_cap_multiple(intr_handle) ||
1945 !RTE_ETH_DEV_SRIOV(dev).active) &&
1946 dev->data->dev_conf.intr_conf.rxq != 0) {
1947 intr_vector = dev->data->nb_rx_queues;
1948 ret = rte_intr_efd_enable(intr_handle, intr_vector);
1953 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1954 intr_handle->intr_vec =
1955 rte_zmalloc("intr_vec",
1956 dev->data->nb_rx_queues * sizeof(int),
1958 if (!intr_handle->intr_vec) {
1960 "Failed to allocate %d rx_queues intr_vec",
1961 dev->data->nb_rx_queues);
1966 /* Initialize VSI */
1967 ret = i40e_dev_rxtx_init(pf);
1968 if (ret != I40E_SUCCESS) {
1969 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1973 /* Map queues with MSIX interrupt */
1974 main_vsi->nb_used_qps = dev->data->nb_rx_queues -
1975 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1976 i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
1977 i40e_vsi_enable_queues_intr(main_vsi);
1979 /* Map VMDQ VSI queues with MSIX interrupt */
1980 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1981 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
1982 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
1983 I40E_ITR_INDEX_DEFAULT);
1984 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1987 /* enable FDIR MSIX interrupt */
1988 if (pf->fdir.fdir_vsi) {
1989 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
1990 I40E_ITR_INDEX_NONE);
1991 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1994 /* Enable all queues which have been configured */
1995 ret = i40e_dev_switch_queues(pf, TRUE);
1996 if (ret != I40E_SUCCESS) {
1997 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2001 /* Enable receiving broadcast packets */
2002 ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2003 if (ret != I40E_SUCCESS)
2004 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2006 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2007 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2009 if (ret != I40E_SUCCESS)
2010 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2013 /* Enable the VLAN promiscuous mode. */
2015 for (i = 0; i < pf->vf_num; i++) {
2016 vsi = pf->vfs[i].vsi;
2017 i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2022 /* Enable mac loopback mode */
2023 if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2024 dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2025 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2026 if (ret != I40E_SUCCESS) {
2027 PMD_DRV_LOG(ERR, "fail to set loopback link");
2032 /* Apply link configure */
2033 if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
2034 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
2035 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
2036 ETH_LINK_SPEED_40G)) {
2037 PMD_DRV_LOG(ERR, "Invalid link setting");
2040 ret = i40e_apply_link_speed(dev);
2041 if (I40E_SUCCESS != ret) {
2042 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2046 if (!rte_intr_allow_others(intr_handle)) {
2047 rte_intr_callback_unregister(intr_handle,
2048 i40e_dev_interrupt_handler,
2050 /* configure and enable device interrupt */
2051 i40e_pf_config_irq0(hw, FALSE);
2052 i40e_pf_enable_irq0(hw);
2054 if (dev->data->dev_conf.intr_conf.lsc != 0)
2056 "lsc won't enable because of no intr multiplex");
2058 ret = i40e_aq_set_phy_int_mask(hw,
2059 ~(I40E_AQ_EVENT_LINK_UPDOWN |
2060 I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2061 I40E_AQ_EVENT_MEDIA_NA), NULL);
2062 if (ret != I40E_SUCCESS)
2063 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2065 /* Call get_link_info aq commond to enable/disable LSE */
2066 i40e_dev_link_update(dev, 0);
2069 /* enable uio intr after callback register */
2070 rte_intr_enable(intr_handle);
2072 i40e_filter_restore(pf);
2074 if (pf->tm_conf.root && !pf->tm_conf.committed)
2075 PMD_DRV_LOG(WARNING,
2076 "please call hierarchy_commit() "
2077 "before starting the port");
2079 return I40E_SUCCESS;
2082 i40e_dev_switch_queues(pf, FALSE);
2083 i40e_dev_clear_queues(dev);
2089 i40e_dev_stop(struct rte_eth_dev *dev)
2091 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2092 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2093 struct i40e_vsi *main_vsi = pf->main_vsi;
2094 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2095 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2098 if (hw->adapter_stopped == 1)
2100 /* Disable all queues */
2101 i40e_dev_switch_queues(pf, FALSE);
2103 /* un-map queues with interrupt registers */
2104 i40e_vsi_disable_queues_intr(main_vsi);
2105 i40e_vsi_queues_unbind_intr(main_vsi);
2107 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2108 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2109 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2112 if (pf->fdir.fdir_vsi) {
2113 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2114 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2116 /* Clear all queues and release memory */
2117 i40e_dev_clear_queues(dev);
2120 i40e_dev_set_link_down(dev);
2122 if (!rte_intr_allow_others(intr_handle))
2123 /* resume to the default handler */
2124 rte_intr_callback_register(intr_handle,
2125 i40e_dev_interrupt_handler,
2128 /* Clean datapath event and queue/vec mapping */
2129 rte_intr_efd_disable(intr_handle);
2130 if (intr_handle->intr_vec) {
2131 rte_free(intr_handle->intr_vec);
2132 intr_handle->intr_vec = NULL;
2135 /* reset hierarchy commit */
2136 pf->tm_conf.committed = false;
2138 /* Remove all the queue region configuration */
2139 i40e_flush_queue_region_all_conf(dev, hw, pf, 0);
2141 hw->adapter_stopped = 1;
2145 i40e_dev_close(struct rte_eth_dev *dev)
2147 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2148 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2149 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2150 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2151 struct i40e_mirror_rule *p_mirror;
2156 PMD_INIT_FUNC_TRACE();
2160 /* Remove all mirror rules */
2161 while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2162 ret = i40e_aq_del_mirror_rule(hw,
2163 pf->main_vsi->veb->seid,
2164 p_mirror->rule_type,
2166 p_mirror->num_entries,
2169 PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2170 "status = %d, aq_err = %d.", ret,
2171 hw->aq.asq_last_status);
2173 /* remove mirror software resource anyway */
2174 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2176 pf->nb_mirror_rule--;
2179 i40e_dev_free_queues(dev);
2181 /* Disable interrupt */
2182 i40e_pf_disable_irq0(hw);
2183 rte_intr_disable(intr_handle);
2185 /* shutdown and destroy the HMC */
2186 i40e_shutdown_lan_hmc(hw);
2188 for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2189 i40e_vsi_release(pf->vmdq[i].vsi);
2190 pf->vmdq[i].vsi = NULL;
2195 /* release all the existing VSIs and VEBs */
2196 i40e_fdir_teardown(pf);
2197 i40e_vsi_release(pf->main_vsi);
2199 /* shutdown the adminq */
2200 i40e_aq_queue_shutdown(hw, true);
2201 i40e_shutdown_adminq(hw);
2203 i40e_res_pool_destroy(&pf->qp_pool);
2204 i40e_res_pool_destroy(&pf->msix_pool);
2206 /* force a PF reset to clean anything leftover */
2207 reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2208 I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2209 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2210 I40E_WRITE_FLUSH(hw);
2214 * Reset PF device only to re-initialize resources in PMD layer
2217 i40e_dev_reset(struct rte_eth_dev *dev)
2221 /* When a DPDK PMD PF begin to reset PF port, it should notify all
2222 * its VF to make them align with it. The detailed notification
2223 * mechanism is PMD specific. As to i40e PF, it is rather complex.
2224 * To avoid unexpected behavior in VF, currently reset of PF with
2225 * SR-IOV activation is not supported. It might be supported later.
2227 if (dev->data->sriov.active)
2230 ret = eth_i40e_dev_uninit(dev);
2234 ret = eth_i40e_dev_init(dev);
2240 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2242 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2243 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2244 struct i40e_vsi *vsi = pf->main_vsi;
2247 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2249 if (status != I40E_SUCCESS)
2250 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2252 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2254 if (status != I40E_SUCCESS)
2255 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2260 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2262 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2263 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2264 struct i40e_vsi *vsi = pf->main_vsi;
2267 status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2269 if (status != I40E_SUCCESS)
2270 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2272 status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2274 if (status != I40E_SUCCESS)
2275 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2279 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2281 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2282 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2283 struct i40e_vsi *vsi = pf->main_vsi;
2286 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2287 if (ret != I40E_SUCCESS)
2288 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2292 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2294 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2295 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2296 struct i40e_vsi *vsi = pf->main_vsi;
2299 if (dev->data->promiscuous == 1)
2300 return; /* must remain in all_multicast mode */
2302 ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2303 vsi->seid, FALSE, NULL);
2304 if (ret != I40E_SUCCESS)
2305 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2309 * Set device link up.
2312 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2314 /* re-apply link speed setting */
2315 return i40e_apply_link_speed(dev);
2319 * Set device link down.
2322 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2324 uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2325 uint8_t abilities = 0;
2326 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2328 abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2329 return i40e_phy_conf_link(hw, abilities, speed, false);
2333 i40e_dev_link_update(struct rte_eth_dev *dev,
2334 int wait_to_complete)
2336 #define CHECK_INTERVAL 100 /* 100ms */
2337 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2338 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2339 struct i40e_link_status link_status;
2340 struct rte_eth_link link, old;
2342 unsigned rep_cnt = MAX_REPEAT_TIME;
2343 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2345 memset(&link, 0, sizeof(link));
2346 memset(&old, 0, sizeof(old));
2347 memset(&link_status, 0, sizeof(link_status));
2348 rte_i40e_dev_atomic_read_link_status(dev, &old);
2351 /* Get link status information from hardware */
2352 status = i40e_aq_get_link_info(hw, enable_lse,
2353 &link_status, NULL);
2354 if (status != I40E_SUCCESS) {
2355 link.link_speed = ETH_SPEED_NUM_100M;
2356 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2357 PMD_DRV_LOG(ERR, "Failed to get link info");
2361 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
2362 if (!wait_to_complete || link.link_status)
2365 rte_delay_ms(CHECK_INTERVAL);
2366 } while (--rep_cnt);
2368 if (!link.link_status)
2371 /* i40e uses full duplex only */
2372 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2374 /* Parse the link status */
2375 switch (link_status.link_speed) {
2376 case I40E_LINK_SPEED_100MB:
2377 link.link_speed = ETH_SPEED_NUM_100M;
2379 case I40E_LINK_SPEED_1GB:
2380 link.link_speed = ETH_SPEED_NUM_1G;
2382 case I40E_LINK_SPEED_10GB:
2383 link.link_speed = ETH_SPEED_NUM_10G;
2385 case I40E_LINK_SPEED_20GB:
2386 link.link_speed = ETH_SPEED_NUM_20G;
2388 case I40E_LINK_SPEED_25GB:
2389 link.link_speed = ETH_SPEED_NUM_25G;
2391 case I40E_LINK_SPEED_40GB:
2392 link.link_speed = ETH_SPEED_NUM_40G;
2395 link.link_speed = ETH_SPEED_NUM_100M;
2399 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2400 ETH_LINK_SPEED_FIXED);
2403 rte_i40e_dev_atomic_write_link_status(dev, &link);
2404 if (link.link_status == old.link_status)
2407 i40e_notify_all_vfs_link_status(dev);
2412 /* Get all the statistics of a VSI */
2414 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2416 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2417 struct i40e_eth_stats *nes = &vsi->eth_stats;
2418 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2419 int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2421 i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2422 vsi->offset_loaded, &oes->rx_bytes,
2424 i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2425 vsi->offset_loaded, &oes->rx_unicast,
2427 i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2428 vsi->offset_loaded, &oes->rx_multicast,
2429 &nes->rx_multicast);
2430 i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2431 vsi->offset_loaded, &oes->rx_broadcast,
2432 &nes->rx_broadcast);
2433 /* exclude CRC bytes */
2434 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2435 nes->rx_broadcast) * ETHER_CRC_LEN;
2437 i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2438 &oes->rx_discards, &nes->rx_discards);
2439 /* GLV_REPC not supported */
2440 /* GLV_RMPC not supported */
2441 i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2442 &oes->rx_unknown_protocol,
2443 &nes->rx_unknown_protocol);
2444 i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2445 vsi->offset_loaded, &oes->tx_bytes,
2447 i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2448 vsi->offset_loaded, &oes->tx_unicast,
2450 i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2451 vsi->offset_loaded, &oes->tx_multicast,
2452 &nes->tx_multicast);
2453 i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2454 vsi->offset_loaded, &oes->tx_broadcast,
2455 &nes->tx_broadcast);
2456 /* GLV_TDPC not supported */
2457 i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2458 &oes->tx_errors, &nes->tx_errors);
2459 vsi->offset_loaded = true;
2461 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2463 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
2464 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
2465 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
2466 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
2467 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
2468 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2469 nes->rx_unknown_protocol);
2470 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
2471 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
2472 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
2473 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
2474 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
2475 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
2476 PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2481 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2484 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2485 struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2487 /* Get rx/tx bytes of internal transfer packets */
2488 i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2489 I40E_GLV_GORCL(hw->port),
2491 &pf->internal_stats_offset.rx_bytes,
2492 &pf->internal_stats.rx_bytes);
2494 i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2495 I40E_GLV_GOTCL(hw->port),
2497 &pf->internal_stats_offset.tx_bytes,
2498 &pf->internal_stats.tx_bytes);
2499 /* Get total internal rx packet count */
2500 i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2501 I40E_GLV_UPRCL(hw->port),
2503 &pf->internal_stats_offset.rx_unicast,
2504 &pf->internal_stats.rx_unicast);
2505 i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2506 I40E_GLV_MPRCL(hw->port),
2508 &pf->internal_stats_offset.rx_multicast,
2509 &pf->internal_stats.rx_multicast);
2510 i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2511 I40E_GLV_BPRCL(hw->port),
2513 &pf->internal_stats_offset.rx_broadcast,
2514 &pf->internal_stats.rx_broadcast);
2516 /* exclude CRC size */
2517 pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2518 pf->internal_stats.rx_multicast +
2519 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2521 /* Get statistics of struct i40e_eth_stats */
2522 i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2523 I40E_GLPRT_GORCL(hw->port),
2524 pf->offset_loaded, &os->eth.rx_bytes,
2526 i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2527 I40E_GLPRT_UPRCL(hw->port),
2528 pf->offset_loaded, &os->eth.rx_unicast,
2529 &ns->eth.rx_unicast);
2530 i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2531 I40E_GLPRT_MPRCL(hw->port),
2532 pf->offset_loaded, &os->eth.rx_multicast,
2533 &ns->eth.rx_multicast);
2534 i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2535 I40E_GLPRT_BPRCL(hw->port),
2536 pf->offset_loaded, &os->eth.rx_broadcast,
2537 &ns->eth.rx_broadcast);
2538 /* Workaround: CRC size should not be included in byte statistics,
2539 * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2541 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2542 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2544 /* Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2545 * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negtive
2548 if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2549 ns->eth.rx_bytes = 0;
2550 /* exlude internal rx bytes */
2552 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2554 i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2555 pf->offset_loaded, &os->eth.rx_discards,
2556 &ns->eth.rx_discards);
2557 /* GLPRT_REPC not supported */
2558 /* GLPRT_RMPC not supported */
2559 i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2561 &os->eth.rx_unknown_protocol,
2562 &ns->eth.rx_unknown_protocol);
2563 i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2564 I40E_GLPRT_GOTCL(hw->port),
2565 pf->offset_loaded, &os->eth.tx_bytes,
2567 i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2568 I40E_GLPRT_UPTCL(hw->port),
2569 pf->offset_loaded, &os->eth.tx_unicast,
2570 &ns->eth.tx_unicast);
2571 i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2572 I40E_GLPRT_MPTCL(hw->port),
2573 pf->offset_loaded, &os->eth.tx_multicast,
2574 &ns->eth.tx_multicast);
2575 i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2576 I40E_GLPRT_BPTCL(hw->port),
2577 pf->offset_loaded, &os->eth.tx_broadcast,
2578 &ns->eth.tx_broadcast);
2579 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2580 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2582 /* exclude internal tx bytes */
2583 if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2584 ns->eth.tx_bytes = 0;
2586 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2588 /* GLPRT_TEPC not supported */
2590 /* additional port specific stats */
2591 i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2592 pf->offset_loaded, &os->tx_dropped_link_down,
2593 &ns->tx_dropped_link_down);
2594 i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2595 pf->offset_loaded, &os->crc_errors,
2597 i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2598 pf->offset_loaded, &os->illegal_bytes,
2599 &ns->illegal_bytes);
2600 /* GLPRT_ERRBC not supported */
2601 i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2602 pf->offset_loaded, &os->mac_local_faults,
2603 &ns->mac_local_faults);
2604 i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2605 pf->offset_loaded, &os->mac_remote_faults,
2606 &ns->mac_remote_faults);
2607 i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2608 pf->offset_loaded, &os->rx_length_errors,
2609 &ns->rx_length_errors);
2610 i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2611 pf->offset_loaded, &os->link_xon_rx,
2613 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2614 pf->offset_loaded, &os->link_xoff_rx,
2616 for (i = 0; i < 8; i++) {
2617 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2619 &os->priority_xon_rx[i],
2620 &ns->priority_xon_rx[i]);
2621 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2623 &os->priority_xoff_rx[i],
2624 &ns->priority_xoff_rx[i]);
2626 i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2627 pf->offset_loaded, &os->link_xon_tx,
2629 i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2630 pf->offset_loaded, &os->link_xoff_tx,
2632 for (i = 0; i < 8; i++) {
2633 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2635 &os->priority_xon_tx[i],
2636 &ns->priority_xon_tx[i]);
2637 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2639 &os->priority_xoff_tx[i],
2640 &ns->priority_xoff_tx[i]);
2641 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2643 &os->priority_xon_2_xoff[i],
2644 &ns->priority_xon_2_xoff[i]);
2646 i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2647 I40E_GLPRT_PRC64L(hw->port),
2648 pf->offset_loaded, &os->rx_size_64,
2650 i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2651 I40E_GLPRT_PRC127L(hw->port),
2652 pf->offset_loaded, &os->rx_size_127,
2654 i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2655 I40E_GLPRT_PRC255L(hw->port),
2656 pf->offset_loaded, &os->rx_size_255,
2658 i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2659 I40E_GLPRT_PRC511L(hw->port),
2660 pf->offset_loaded, &os->rx_size_511,
2662 i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2663 I40E_GLPRT_PRC1023L(hw->port),
2664 pf->offset_loaded, &os->rx_size_1023,
2666 i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2667 I40E_GLPRT_PRC1522L(hw->port),
2668 pf->offset_loaded, &os->rx_size_1522,
2670 i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2671 I40E_GLPRT_PRC9522L(hw->port),
2672 pf->offset_loaded, &os->rx_size_big,
2674 i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2675 pf->offset_loaded, &os->rx_undersize,
2677 i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2678 pf->offset_loaded, &os->rx_fragments,
2680 i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2681 pf->offset_loaded, &os->rx_oversize,
2683 i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2684 pf->offset_loaded, &os->rx_jabber,
2686 i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2687 I40E_GLPRT_PTC64L(hw->port),
2688 pf->offset_loaded, &os->tx_size_64,
2690 i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2691 I40E_GLPRT_PTC127L(hw->port),
2692 pf->offset_loaded, &os->tx_size_127,
2694 i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2695 I40E_GLPRT_PTC255L(hw->port),
2696 pf->offset_loaded, &os->tx_size_255,
2698 i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2699 I40E_GLPRT_PTC511L(hw->port),
2700 pf->offset_loaded, &os->tx_size_511,
2702 i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2703 I40E_GLPRT_PTC1023L(hw->port),
2704 pf->offset_loaded, &os->tx_size_1023,
2706 i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2707 I40E_GLPRT_PTC1522L(hw->port),
2708 pf->offset_loaded, &os->tx_size_1522,
2710 i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2711 I40E_GLPRT_PTC9522L(hw->port),
2712 pf->offset_loaded, &os->tx_size_big,
2714 i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2716 &os->fd_sb_match, &ns->fd_sb_match);
2717 /* GLPRT_MSPDC not supported */
2718 /* GLPRT_XEC not supported */
2720 pf->offset_loaded = true;
2723 i40e_update_vsi_stats(pf->main_vsi);
2726 /* Get all statistics of a port */
2728 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2730 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2731 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2732 struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2735 /* call read registers - updates values, now write them to struct */
2736 i40e_read_stats_registers(pf, hw);
2738 stats->ipackets = ns->eth.rx_unicast +
2739 ns->eth.rx_multicast +
2740 ns->eth.rx_broadcast -
2741 ns->eth.rx_discards -
2742 pf->main_vsi->eth_stats.rx_discards;
2743 stats->opackets = ns->eth.tx_unicast +
2744 ns->eth.tx_multicast +
2745 ns->eth.tx_broadcast;
2746 stats->ibytes = ns->eth.rx_bytes;
2747 stats->obytes = ns->eth.tx_bytes;
2748 stats->oerrors = ns->eth.tx_errors +
2749 pf->main_vsi->eth_stats.tx_errors;
2752 stats->imissed = ns->eth.rx_discards +
2753 pf->main_vsi->eth_stats.rx_discards;
2754 stats->ierrors = ns->crc_errors +
2755 ns->rx_length_errors + ns->rx_undersize +
2756 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2758 PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2759 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
2760 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
2761 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", ns->eth.rx_multicast);
2762 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", ns->eth.rx_broadcast);
2763 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", ns->eth.rx_discards);
2764 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2765 ns->eth.rx_unknown_protocol);
2766 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
2767 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
2768 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", ns->eth.tx_multicast);
2769 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", ns->eth.tx_broadcast);
2770 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", ns->eth.tx_discards);
2771 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
2773 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
2774 ns->tx_dropped_link_down);
2775 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
2776 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
2778 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
2779 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
2780 ns->mac_local_faults);
2781 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
2782 ns->mac_remote_faults);
2783 PMD_DRV_LOG(DEBUG, "rx_length_errors: %"PRIu64"",
2784 ns->rx_length_errors);
2785 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
2786 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
2787 for (i = 0; i < 8; i++) {
2788 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]: %"PRIu64"",
2789 i, ns->priority_xon_rx[i]);
2790 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]: %"PRIu64"",
2791 i, ns->priority_xoff_rx[i]);
2793 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
2794 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
2795 for (i = 0; i < 8; i++) {
2796 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]: %"PRIu64"",
2797 i, ns->priority_xon_tx[i]);
2798 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]: %"PRIu64"",
2799 i, ns->priority_xoff_tx[i]);
2800 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]: %"PRIu64"",
2801 i, ns->priority_xon_2_xoff[i]);
2803 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
2804 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
2805 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
2806 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
2807 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
2808 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
2809 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
2810 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
2811 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
2812 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
2813 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
2814 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
2815 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
2816 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
2817 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
2818 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
2819 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
2820 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
2821 PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
2822 ns->mac_short_packet_dropped);
2823 PMD_DRV_LOG(DEBUG, "checksum_error: %"PRIu64"",
2824 ns->checksum_error);
2825 PMD_DRV_LOG(DEBUG, "fdir_match: %"PRIu64"", ns->fd_sb_match);
2826 PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
2830 /* Reset the statistics */
2832 i40e_dev_stats_reset(struct rte_eth_dev *dev)
2834 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2835 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2837 /* Mark PF and VSI stats to update the offset, aka "reset" */
2838 pf->offset_loaded = false;
2840 pf->main_vsi->offset_loaded = false;
2842 /* read the stats, reading current register values into offset */
2843 i40e_read_stats_registers(pf, hw);
2847 i40e_xstats_calc_num(void)
2849 return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
2850 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
2851 (I40E_NB_TXQ_PRIO_XSTATS * 8);
2854 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
2855 struct rte_eth_xstat_name *xstats_names,
2856 __rte_unused unsigned limit)
2861 if (xstats_names == NULL)
2862 return i40e_xstats_calc_num();
2864 /* Note: limit checked in rte_eth_xstats_names() */
2866 /* Get stats from i40e_eth_stats struct */
2867 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2868 snprintf(xstats_names[count].name,
2869 sizeof(xstats_names[count].name),
2870 "%s", rte_i40e_stats_strings[i].name);
2874 /* Get individiual stats from i40e_hw_port struct */
2875 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2876 snprintf(xstats_names[count].name,
2877 sizeof(xstats_names[count].name),
2878 "%s", rte_i40e_hw_port_strings[i].name);
2882 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2883 for (prio = 0; prio < 8; prio++) {
2884 snprintf(xstats_names[count].name,
2885 sizeof(xstats_names[count].name),
2886 "rx_priority%u_%s", prio,
2887 rte_i40e_rxq_prio_strings[i].name);
2892 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2893 for (prio = 0; prio < 8; prio++) {
2894 snprintf(xstats_names[count].name,
2895 sizeof(xstats_names[count].name),
2896 "tx_priority%u_%s", prio,
2897 rte_i40e_txq_prio_strings[i].name);
2905 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2908 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2909 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2910 unsigned i, count, prio;
2911 struct i40e_hw_port_stats *hw_stats = &pf->stats;
2913 count = i40e_xstats_calc_num();
2917 i40e_read_stats_registers(pf, hw);
2924 /* Get stats from i40e_eth_stats struct */
2925 for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
2926 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
2927 rte_i40e_stats_strings[i].offset);
2928 xstats[count].id = count;
2932 /* Get individiual stats from i40e_hw_port struct */
2933 for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
2934 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
2935 rte_i40e_hw_port_strings[i].offset);
2936 xstats[count].id = count;
2940 for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
2941 for (prio = 0; prio < 8; prio++) {
2942 xstats[count].value =
2943 *(uint64_t *)(((char *)hw_stats) +
2944 rte_i40e_rxq_prio_strings[i].offset +
2945 (sizeof(uint64_t) * prio));
2946 xstats[count].id = count;
2951 for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
2952 for (prio = 0; prio < 8; prio++) {
2953 xstats[count].value =
2954 *(uint64_t *)(((char *)hw_stats) +
2955 rte_i40e_txq_prio_strings[i].offset +
2956 (sizeof(uint64_t) * prio));
2957 xstats[count].id = count;
2966 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
2967 __rte_unused uint16_t queue_id,
2968 __rte_unused uint8_t stat_idx,
2969 __rte_unused uint8_t is_rx)
2971 PMD_INIT_FUNC_TRACE();
2977 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2979 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2985 full_ver = hw->nvm.oem_ver;
2986 ver = (u8)(full_ver >> 24);
2987 build = (u16)((full_ver >> 8) & 0xffff);
2988 patch = (u8)(full_ver & 0xff);
2990 ret = snprintf(fw_version, fw_size,
2991 "%d.%d%d 0x%08x %d.%d.%d",
2992 ((hw->nvm.version >> 12) & 0xf),
2993 ((hw->nvm.version >> 4) & 0xff),
2994 (hw->nvm.version & 0xf), hw->nvm.eetrack,
2997 ret += 1; /* add the size of '\0' */
2998 if (fw_size < (u32)ret)
3005 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3007 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3008 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3009 struct i40e_vsi *vsi = pf->main_vsi;
3010 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3012 dev_info->pci_dev = pci_dev;
3013 dev_info->max_rx_queues = vsi->nb_qps;
3014 dev_info->max_tx_queues = vsi->nb_qps;
3015 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3016 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3017 dev_info->max_mac_addrs = vsi->max_macaddrs;
3018 dev_info->max_vfs = pci_dev->max_vfs;
3019 dev_info->rx_offload_capa =
3020 DEV_RX_OFFLOAD_VLAN_STRIP |
3021 DEV_RX_OFFLOAD_QINQ_STRIP |
3022 DEV_RX_OFFLOAD_IPV4_CKSUM |
3023 DEV_RX_OFFLOAD_UDP_CKSUM |
3024 DEV_RX_OFFLOAD_TCP_CKSUM;
3025 dev_info->tx_offload_capa =
3026 DEV_TX_OFFLOAD_VLAN_INSERT |
3027 DEV_TX_OFFLOAD_QINQ_INSERT |
3028 DEV_TX_OFFLOAD_IPV4_CKSUM |
3029 DEV_TX_OFFLOAD_UDP_CKSUM |
3030 DEV_TX_OFFLOAD_TCP_CKSUM |
3031 DEV_TX_OFFLOAD_SCTP_CKSUM |
3032 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3033 DEV_TX_OFFLOAD_TCP_TSO |
3034 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3035 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3036 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3037 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
3038 dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3040 dev_info->reta_size = pf->hash_lut_size;
3041 dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3043 dev_info->default_rxconf = (struct rte_eth_rxconf) {
3045 .pthresh = I40E_DEFAULT_RX_PTHRESH,
3046 .hthresh = I40E_DEFAULT_RX_HTHRESH,
3047 .wthresh = I40E_DEFAULT_RX_WTHRESH,
3049 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3053 dev_info->default_txconf = (struct rte_eth_txconf) {
3055 .pthresh = I40E_DEFAULT_TX_PTHRESH,
3056 .hthresh = I40E_DEFAULT_TX_HTHRESH,
3057 .wthresh = I40E_DEFAULT_TX_WTHRESH,
3059 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3060 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3061 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3062 ETH_TXQ_FLAGS_NOOFFLOADS,
3065 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3066 .nb_max = I40E_MAX_RING_DESC,
3067 .nb_min = I40E_MIN_RING_DESC,
3068 .nb_align = I40E_ALIGN_RING_DESC,
3071 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3072 .nb_max = I40E_MAX_RING_DESC,
3073 .nb_min = I40E_MIN_RING_DESC,
3074 .nb_align = I40E_ALIGN_RING_DESC,
3075 .nb_seg_max = I40E_TX_MAX_SEG,
3076 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3079 if (pf->flags & I40E_FLAG_VMDQ) {
3080 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3081 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3082 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3083 pf->max_nb_vmdq_vsi;
3084 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3085 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3086 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3089 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
3091 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3092 else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
3094 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3097 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3101 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3103 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3104 struct i40e_vsi *vsi = pf->main_vsi;
3105 PMD_INIT_FUNC_TRACE();
3108 return i40e_vsi_add_vlan(vsi, vlan_id);
3110 return i40e_vsi_delete_vlan(vsi, vlan_id);
3114 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3115 enum rte_vlan_type vlan_type,
3116 uint16_t tpid, int qinq)
3118 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3121 uint16_t reg_id = 3;
3125 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3129 ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3131 if (ret != I40E_SUCCESS) {
3133 "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3138 "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3141 reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3142 reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3143 if (reg_r == reg_w) {
3144 PMD_DRV_LOG(DEBUG, "No need to write");
3148 ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3150 if (ret != I40E_SUCCESS) {
3152 "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3157 "Debug write 0x%08"PRIx64" to I40E_GL_SWT_L2TAGCTRL[%d]",
3164 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3165 enum rte_vlan_type vlan_type,
3168 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3169 int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
3172 if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3173 vlan_type != ETH_VLAN_TYPE_OUTER) ||
3174 (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3176 "Unsupported vlan type.");
3179 /* 802.1ad frames ability is added in NVM API 1.7*/
3180 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3182 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3183 hw->first_tag = rte_cpu_to_le_16(tpid);
3184 else if (vlan_type == ETH_VLAN_TYPE_INNER)
3185 hw->second_tag = rte_cpu_to_le_16(tpid);
3187 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3188 hw->second_tag = rte_cpu_to_le_16(tpid);
3190 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3191 if (ret != I40E_SUCCESS) {
3193 "Set switch config failed aq_err: %d",
3194 hw->aq.asq_last_status);
3198 /* If NVM API < 1.7, keep the register setting */
3199 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3206 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3208 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3209 struct i40e_vsi *vsi = pf->main_vsi;
3211 if (mask & ETH_VLAN_FILTER_MASK) {
3212 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3213 i40e_vsi_config_vlan_filter(vsi, TRUE);
3215 i40e_vsi_config_vlan_filter(vsi, FALSE);
3218 if (mask & ETH_VLAN_STRIP_MASK) {
3219 /* Enable or disable VLAN stripping */
3220 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3221 i40e_vsi_config_vlan_stripping(vsi, TRUE);
3223 i40e_vsi_config_vlan_stripping(vsi, FALSE);
3226 if (mask & ETH_VLAN_EXTEND_MASK) {
3227 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3228 i40e_vsi_config_double_vlan(vsi, TRUE);
3229 /* Set global registers with default ethertype. */
3230 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3232 i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3236 i40e_vsi_config_double_vlan(vsi, FALSE);
3243 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3244 __rte_unused uint16_t queue,
3245 __rte_unused int on)
3247 PMD_INIT_FUNC_TRACE();
3251 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3253 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3254 struct i40e_vsi *vsi = pf->main_vsi;
3255 struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3256 struct i40e_vsi_vlan_pvid_info info;
3258 memset(&info, 0, sizeof(info));
3261 info.config.pvid = pvid;
3263 info.config.reject.tagged =
3264 data->dev_conf.txmode.hw_vlan_reject_tagged;
3265 info.config.reject.untagged =
3266 data->dev_conf.txmode.hw_vlan_reject_untagged;
3269 return i40e_vsi_vlan_pvid_set(vsi, &info);
3273 i40e_dev_led_on(struct rte_eth_dev *dev)
3275 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3276 uint32_t mode = i40e_led_get(hw);
3279 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3285 i40e_dev_led_off(struct rte_eth_dev *dev)
3287 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3288 uint32_t mode = i40e_led_get(hw);
3291 i40e_led_set(hw, 0, false);
3297 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3299 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3300 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3302 fc_conf->pause_time = pf->fc_conf.pause_time;
3304 /* read out from register, in case they are modified by other port */
3305 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3306 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3307 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3308 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3310 fc_conf->high_water = pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3311 fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3313 /* Return current mode according to actual setting*/
3314 switch (hw->fc.current_mode) {
3316 fc_conf->mode = RTE_FC_FULL;
3318 case I40E_FC_TX_PAUSE:
3319 fc_conf->mode = RTE_FC_TX_PAUSE;
3321 case I40E_FC_RX_PAUSE:
3322 fc_conf->mode = RTE_FC_RX_PAUSE;
3326 fc_conf->mode = RTE_FC_NONE;
3333 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3335 uint32_t mflcn_reg, fctrl_reg, reg;
3336 uint32_t max_high_water;
3337 uint8_t i, aq_failure;
3341 enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3342 [RTE_FC_NONE] = I40E_FC_NONE,
3343 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3344 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3345 [RTE_FC_FULL] = I40E_FC_FULL
3348 /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3350 max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3351 if ((fc_conf->high_water > max_high_water) ||
3352 (fc_conf->high_water < fc_conf->low_water)) {
3354 "Invalid high/low water setup value in KB, High_water must be <= %d.",
3359 hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3360 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3361 hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3363 pf->fc_conf.pause_time = fc_conf->pause_time;
3364 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3365 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3367 PMD_INIT_FUNC_TRACE();
3369 /* All the link flow control related enable/disable register
3370 * configuration is handle by the F/W
3372 err = i40e_set_fc(hw, &aq_failure, true);
3376 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3377 /* Configure flow control refresh threshold,
3378 * the value for stat_tx_pause_refresh_timer[8]
3379 * is used for global pause operation.
3383 I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3384 pf->fc_conf.pause_time);
3386 /* configure the timer value included in transmitted pause
3388 * the value for stat_tx_pause_quanta[8] is used for global
3391 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3392 pf->fc_conf.pause_time);
3394 fctrl_reg = I40E_READ_REG(hw,
3395 I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3397 if (fc_conf->mac_ctrl_frame_fwd != 0)
3398 fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3400 fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3402 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3405 /* Configure pause time (2 TCs per register) */
3406 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3407 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3408 I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3410 /* Configure flow control refresh threshold value */
3411 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3412 pf->fc_conf.pause_time / 2);
3414 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3416 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3417 *depending on configuration
3419 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3420 mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3421 mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3423 mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3424 mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3427 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3430 /* config the water marker both based on the packets and bytes */
3431 I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
3432 (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3433 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3434 I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
3435 (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3436 << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3437 I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
3438 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3440 I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
3441 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3444 I40E_WRITE_FLUSH(hw);
3450 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3451 __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3453 PMD_INIT_FUNC_TRACE();
3458 /* Add a MAC address, and update filters */
3460 i40e_macaddr_add(struct rte_eth_dev *dev,
3461 struct ether_addr *mac_addr,
3462 __rte_unused uint32_t index,
3465 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3466 struct i40e_mac_filter_info mac_filter;
3467 struct i40e_vsi *vsi;
3470 /* If VMDQ not enabled or configured, return */
3471 if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3472 !pf->nb_cfg_vmdq_vsi)) {
3473 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3474 pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3479 if (pool > pf->nb_cfg_vmdq_vsi) {
3480 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3481 pool, pf->nb_cfg_vmdq_vsi);
3485 rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3486 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3487 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3489 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3494 vsi = pf->vmdq[pool - 1].vsi;
3496 ret = i40e_vsi_add_mac(vsi, &mac_filter);
3497 if (ret != I40E_SUCCESS) {
3498 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3504 /* Remove a MAC address, and update filters */
3506 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3508 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3509 struct i40e_vsi *vsi;
3510 struct rte_eth_dev_data *data = dev->data;
3511 struct ether_addr *macaddr;
3516 macaddr = &(data->mac_addrs[index]);
3518 pool_sel = dev->data->mac_pool_sel[index];
3520 for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3521 if (pool_sel & (1ULL << i)) {
3525 /* No VMDQ pool enabled or configured */
3526 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3527 (i > pf->nb_cfg_vmdq_vsi)) {
3529 "No VMDQ pool enabled/configured");
3532 vsi = pf->vmdq[i - 1].vsi;
3534 ret = i40e_vsi_delete_mac(vsi, macaddr);
3537 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3544 /* Set perfect match or hash match of MAC and VLAN for a VF */
3546 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3547 struct rte_eth_mac_filter *filter,
3551 struct i40e_mac_filter_info mac_filter;
3552 struct ether_addr old_mac;
3553 struct ether_addr *new_mac;
3554 struct i40e_pf_vf *vf = NULL;
3559 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3562 hw = I40E_PF_TO_HW(pf);
3564 if (filter == NULL) {
3565 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3569 new_mac = &filter->mac_addr;
3571 if (is_zero_ether_addr(new_mac)) {
3572 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3576 vf_id = filter->dst_id;
3578 if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3579 PMD_DRV_LOG(ERR, "Invalid argument.");
3582 vf = &pf->vfs[vf_id];
3584 if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3585 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3590 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3591 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3593 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3596 mac_filter.filter_type = filter->filter_type;
3597 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3598 if (ret != I40E_SUCCESS) {
3599 PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3602 ether_addr_copy(new_mac, &pf->dev_addr);
3604 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3606 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3607 if (ret != I40E_SUCCESS) {
3608 PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3612 /* Clear device address as it has been removed */
3613 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3614 memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3620 /* MAC filter handle */
3622 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3625 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3626 struct rte_eth_mac_filter *filter;
3627 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3628 int ret = I40E_NOT_SUPPORTED;
3630 filter = (struct rte_eth_mac_filter *)(arg);
3632 switch (filter_op) {
3633 case RTE_ETH_FILTER_NOP:
3636 case RTE_ETH_FILTER_ADD:
3637 i40e_pf_disable_irq0(hw);
3639 ret = i40e_vf_mac_filter_set(pf, filter, 1);
3640 i40e_pf_enable_irq0(hw);
3642 case RTE_ETH_FILTER_DELETE:
3643 i40e_pf_disable_irq0(hw);
3645 ret = i40e_vf_mac_filter_set(pf, filter, 0);
3646 i40e_pf_enable_irq0(hw);
3649 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3650 ret = I40E_ERR_PARAM;
3658 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3660 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3661 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3667 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3668 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3671 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3675 uint32_t *lut_dw = (uint32_t *)lut;
3676 uint16_t i, lut_size_dw = lut_size / 4;
3678 for (i = 0; i < lut_size_dw; i++)
3679 lut_dw[i] = I40E_READ_REG(hw, I40E_PFQF_HLUT(i));
3686 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3695 pf = I40E_VSI_TO_PF(vsi);
3696 hw = I40E_VSI_TO_HW(vsi);
3698 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3699 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3702 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3706 uint32_t *lut_dw = (uint32_t *)lut;
3707 uint16_t i, lut_size_dw = lut_size / 4;
3709 for (i = 0; i < lut_size_dw; i++)
3710 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
3711 I40E_WRITE_FLUSH(hw);
3718 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3719 struct rte_eth_rss_reta_entry64 *reta_conf,
3722 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3723 uint16_t i, lut_size = pf->hash_lut_size;
3724 uint16_t idx, shift;
3728 if (reta_size != lut_size ||
3729 reta_size > ETH_RSS_RETA_SIZE_512) {
3731 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3732 reta_size, lut_size);
3736 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3738 PMD_DRV_LOG(ERR, "No memory can be allocated");
3741 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3744 for (i = 0; i < reta_size; i++) {
3745 idx = i / RTE_RETA_GROUP_SIZE;
3746 shift = i % RTE_RETA_GROUP_SIZE;
3747 if (reta_conf[idx].mask & (1ULL << shift))
3748 lut[i] = reta_conf[idx].reta[shift];
3750 ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
3759 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
3760 struct rte_eth_rss_reta_entry64 *reta_conf,
3763 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3764 uint16_t i, lut_size = pf->hash_lut_size;
3765 uint16_t idx, shift;
3769 if (reta_size != lut_size ||
3770 reta_size > ETH_RSS_RETA_SIZE_512) {
3772 "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3773 reta_size, lut_size);
3777 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3779 PMD_DRV_LOG(ERR, "No memory can be allocated");
3783 ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3786 for (i = 0; i < reta_size; i++) {
3787 idx = i / RTE_RETA_GROUP_SIZE;
3788 shift = i % RTE_RETA_GROUP_SIZE;
3789 if (reta_conf[idx].mask & (1ULL << shift))
3790 reta_conf[idx].reta[shift] = lut[i];
3800 * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
3801 * @hw: pointer to the HW structure
3802 * @mem: pointer to mem struct to fill out
3803 * @size: size of memory requested
3804 * @alignment: what to align the allocation to
3806 enum i40e_status_code
3807 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3808 struct i40e_dma_mem *mem,
3812 const struct rte_memzone *mz = NULL;
3813 char z_name[RTE_MEMZONE_NAMESIZE];
3816 return I40E_ERR_PARAM;
3818 snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
3819 mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
3820 alignment, RTE_PGSIZE_2M);
3822 return I40E_ERR_NO_MEMORY;
3827 mem->zone = (const void *)mz;
3829 "memzone %s allocated with physical address: %"PRIu64,
3832 return I40E_SUCCESS;
3836 * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
3837 * @hw: pointer to the HW structure
3838 * @mem: ptr to mem struct to free
3840 enum i40e_status_code
3841 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3842 struct i40e_dma_mem *mem)
3845 return I40E_ERR_PARAM;
3848 "memzone %s to be freed with physical address: %"PRIu64,
3849 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
3850 rte_memzone_free((const struct rte_memzone *)mem->zone);
3855 return I40E_SUCCESS;
3859 * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
3860 * @hw: pointer to the HW structure
3861 * @mem: pointer to mem struct to fill out
3862 * @size: size of memory requested
3864 enum i40e_status_code
3865 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3866 struct i40e_virt_mem *mem,
3870 return I40E_ERR_PARAM;
3873 mem->va = rte_zmalloc("i40e", size, 0);
3876 return I40E_SUCCESS;
3878 return I40E_ERR_NO_MEMORY;
3882 * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
3883 * @hw: pointer to the HW structure
3884 * @mem: pointer to mem struct to free
3886 enum i40e_status_code
3887 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
3888 struct i40e_virt_mem *mem)
3891 return I40E_ERR_PARAM;
3896 return I40E_SUCCESS;
3900 i40e_init_spinlock_d(struct i40e_spinlock *sp)
3902 rte_spinlock_init(&sp->spinlock);
3906 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
3908 rte_spinlock_lock(&sp->spinlock);
3912 i40e_release_spinlock_d(struct i40e_spinlock *sp)
3914 rte_spinlock_unlock(&sp->spinlock);
3918 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
3924 * Get the hardware capabilities, which will be parsed
3925 * and saved into struct i40e_hw.
3928 i40e_get_cap(struct i40e_hw *hw)
3930 struct i40e_aqc_list_capabilities_element_resp *buf;
3931 uint16_t len, size = 0;
3934 /* Calculate a huge enough buff for saving response data temporarily */
3935 len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
3936 I40E_MAX_CAP_ELE_NUM;
3937 buf = rte_zmalloc("i40e", len, 0);
3939 PMD_DRV_LOG(ERR, "Failed to allocate memory");
3940 return I40E_ERR_NO_MEMORY;
3943 /* Get, parse the capabilities and save it to hw */
3944 ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
3945 i40e_aqc_opc_list_func_capabilities, NULL);
3946 if (ret != I40E_SUCCESS)
3947 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
3949 /* Free the temporary buffer after being used */
3956 i40e_pf_parameter_init(struct rte_eth_dev *dev)
3958 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3959 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3960 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3961 uint16_t qp_count = 0, vsi_count = 0;
3963 if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
3964 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
3967 /* Add the parameter init for LFC */
3968 pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
3969 pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
3970 pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
3972 pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
3973 pf->max_num_vsi = hw->func_caps.num_vsis;
3974 pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
3975 pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
3976 pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
3978 /* FDir queue/VSI allocation */
3979 pf->fdir_qp_offset = 0;
3980 if (hw->func_caps.fd) {
3981 pf->flags |= I40E_FLAG_FDIR;
3982 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
3984 pf->fdir_nb_qps = 0;
3986 qp_count += pf->fdir_nb_qps;
3989 /* LAN queue/VSI allocation */
3990 pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
3991 if (!hw->func_caps.rss) {
3994 pf->flags |= I40E_FLAG_RSS;
3995 if (hw->mac.type == I40E_MAC_X722)
3996 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
3997 pf->lan_nb_qps = pf->lan_nb_qp_max;
3999 qp_count += pf->lan_nb_qps;
4002 /* VF queue/VSI allocation */
4003 pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4004 if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4005 pf->flags |= I40E_FLAG_SRIOV;
4006 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4007 pf->vf_num = pci_dev->max_vfs;
4009 "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4010 pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4015 qp_count += pf->vf_nb_qps * pf->vf_num;
4016 vsi_count += pf->vf_num;
4018 /* VMDq queue/VSI allocation */
4019 pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4020 pf->vmdq_nb_qps = 0;
4021 pf->max_nb_vmdq_vsi = 0;
4022 if (hw->func_caps.vmdq) {
4023 if (qp_count < hw->func_caps.num_tx_qp &&
4024 vsi_count < hw->func_caps.num_vsis) {
4025 pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4026 qp_count) / pf->vmdq_nb_qp_max;
4028 /* Limit the maximum number of VMDq vsi to the maximum
4029 * ethdev can support
4031 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4032 hw->func_caps.num_vsis - vsi_count);
4033 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4035 if (pf->max_nb_vmdq_vsi) {
4036 pf->flags |= I40E_FLAG_VMDQ;
4037 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4039 "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4040 pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4041 pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4044 "No enough queues left for VMDq");
4047 PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4050 qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4051 vsi_count += pf->max_nb_vmdq_vsi;
4053 if (hw->func_caps.dcb)
4054 pf->flags |= I40E_FLAG_DCB;
4056 if (qp_count > hw->func_caps.num_tx_qp) {
4058 "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4059 qp_count, hw->func_caps.num_tx_qp);
4062 if (vsi_count > hw->func_caps.num_vsis) {
4064 "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4065 vsi_count, hw->func_caps.num_vsis);
4073 i40e_pf_get_switch_config(struct i40e_pf *pf)
4075 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4076 struct i40e_aqc_get_switch_config_resp *switch_config;
4077 struct i40e_aqc_switch_config_element_resp *element;
4078 uint16_t start_seid = 0, num_reported;
4081 switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4082 rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4083 if (!switch_config) {
4084 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4088 /* Get the switch configurations */
4089 ret = i40e_aq_get_switch_config(hw, switch_config,
4090 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4091 if (ret != I40E_SUCCESS) {
4092 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4095 num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4096 if (num_reported != 1) { /* The number should be 1 */
4097 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4101 /* Parse the switch configuration elements */
4102 element = &(switch_config->element[0]);
4103 if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4104 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4105 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4107 PMD_DRV_LOG(INFO, "Unknown element type");
4110 rte_free(switch_config);
4116 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4119 struct pool_entry *entry;
4121 if (pool == NULL || num == 0)
4124 entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4125 if (entry == NULL) {
4126 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4130 /* queue heap initialize */
4131 pool->num_free = num;
4132 pool->num_alloc = 0;
4134 LIST_INIT(&pool->alloc_list);
4135 LIST_INIT(&pool->free_list);
4137 /* Initialize element */
4141 LIST_INSERT_HEAD(&pool->free_list, entry, next);
4146 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4148 struct pool_entry *entry, *next_entry;
4153 for (entry = LIST_FIRST(&pool->alloc_list);
4154 entry && (next_entry = LIST_NEXT(entry, next), 1);
4155 entry = next_entry) {
4156 LIST_REMOVE(entry, next);
4160 for (entry = LIST_FIRST(&pool->free_list);
4161 entry && (next_entry = LIST_NEXT(entry, next), 1);
4162 entry = next_entry) {
4163 LIST_REMOVE(entry, next);
4168 pool->num_alloc = 0;
4170 LIST_INIT(&pool->alloc_list);
4171 LIST_INIT(&pool->free_list);
4175 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4178 struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4179 uint32_t pool_offset;
4183 PMD_DRV_LOG(ERR, "Invalid parameter");
4187 pool_offset = base - pool->base;
4188 /* Lookup in alloc list */
4189 LIST_FOREACH(entry, &pool->alloc_list, next) {
4190 if (entry->base == pool_offset) {
4191 valid_entry = entry;
4192 LIST_REMOVE(entry, next);
4197 /* Not find, return */
4198 if (valid_entry == NULL) {
4199 PMD_DRV_LOG(ERR, "Failed to find entry");
4204 * Found it, move it to free list and try to merge.
4205 * In order to make merge easier, always sort it by qbase.
4206 * Find adjacent prev and last entries.
4209 LIST_FOREACH(entry, &pool->free_list, next) {
4210 if (entry->base > valid_entry->base) {
4218 /* Try to merge with next one*/
4220 /* Merge with next one */
4221 if (valid_entry->base + valid_entry->len == next->base) {
4222 next->base = valid_entry->base;
4223 next->len += valid_entry->len;
4224 rte_free(valid_entry);
4231 /* Merge with previous one */
4232 if (prev->base + prev->len == valid_entry->base) {
4233 prev->len += valid_entry->len;
4234 /* If it merge with next one, remove next node */
4236 LIST_REMOVE(valid_entry, next);
4237 rte_free(valid_entry);
4239 rte_free(valid_entry);
4245 /* Not find any entry to merge, insert */
4248 LIST_INSERT_AFTER(prev, valid_entry, next);
4249 else if (next != NULL)
4250 LIST_INSERT_BEFORE(next, valid_entry, next);
4251 else /* It's empty list, insert to head */
4252 LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4255 pool->num_free += valid_entry->len;
4256 pool->num_alloc -= valid_entry->len;
4262 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4265 struct pool_entry *entry, *valid_entry;
4267 if (pool == NULL || num == 0) {
4268 PMD_DRV_LOG(ERR, "Invalid parameter");
4272 if (pool->num_free < num) {
4273 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4274 num, pool->num_free);
4279 /* Lookup in free list and find most fit one */
4280 LIST_FOREACH(entry, &pool->free_list, next) {
4281 if (entry->len >= num) {
4283 if (entry->len == num) {
4284 valid_entry = entry;
4287 if (valid_entry == NULL || valid_entry->len > entry->len)
4288 valid_entry = entry;
4292 /* Not find one to satisfy the request, return */
4293 if (valid_entry == NULL) {
4294 PMD_DRV_LOG(ERR, "No valid entry found");
4298 * The entry have equal queue number as requested,
4299 * remove it from alloc_list.
4301 if (valid_entry->len == num) {
4302 LIST_REMOVE(valid_entry, next);
4305 * The entry have more numbers than requested,
4306 * create a new entry for alloc_list and minus its
4307 * queue base and number in free_list.
4309 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4310 if (entry == NULL) {
4312 "Failed to allocate memory for resource pool");
4315 entry->base = valid_entry->base;
4317 valid_entry->base += num;
4318 valid_entry->len -= num;
4319 valid_entry = entry;
4322 /* Insert it into alloc list, not sorted */
4323 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4325 pool->num_free -= valid_entry->len;
4326 pool->num_alloc += valid_entry->len;
4328 return valid_entry->base + pool->base;
4332 * bitmap_is_subset - Check whether src2 is subset of src1
4335 bitmap_is_subset(uint8_t src1, uint8_t src2)
4337 return !((src1 ^ src2) & src2);
4340 static enum i40e_status_code
4341 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4343 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4345 /* If DCB is not supported, only default TC is supported */
4346 if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4347 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4348 return I40E_NOT_SUPPORTED;
4351 if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4353 "Enabled TC map 0x%x not applicable to HW support 0x%x",
4354 hw->func_caps.enabled_tcmap, enabled_tcmap);
4355 return I40E_NOT_SUPPORTED;
4357 return I40E_SUCCESS;
4361 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4362 struct i40e_vsi_vlan_pvid_info *info)
4365 struct i40e_vsi_context ctxt;
4366 uint8_t vlan_flags = 0;
4369 if (vsi == NULL || info == NULL) {
4370 PMD_DRV_LOG(ERR, "invalid parameters");
4371 return I40E_ERR_PARAM;
4375 vsi->info.pvid = info->config.pvid;
4377 * If insert pvid is enabled, only tagged pkts are
4378 * allowed to be sent out.
4380 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4381 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4384 if (info->config.reject.tagged == 0)
4385 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4387 if (info->config.reject.untagged == 0)
4388 vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4390 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4391 I40E_AQ_VSI_PVLAN_MODE_MASK);
4392 vsi->info.port_vlan_flags |= vlan_flags;
4393 vsi->info.valid_sections =
4394 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4395 memset(&ctxt, 0, sizeof(ctxt));
4396 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4397 ctxt.seid = vsi->seid;
4399 hw = I40E_VSI_TO_HW(vsi);
4400 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4401 if (ret != I40E_SUCCESS)
4402 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4408 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4410 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4412 struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4414 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4415 if (ret != I40E_SUCCESS)
4419 PMD_DRV_LOG(ERR, "seid not valid");
4423 memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4424 tc_bw_data.tc_valid_bits = enabled_tcmap;
4425 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4426 tc_bw_data.tc_bw_credits[i] =
4427 (enabled_tcmap & (1 << i)) ? 1 : 0;
4429 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4430 if (ret != I40E_SUCCESS) {
4431 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4435 rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4436 sizeof(vsi->info.qs_handle));
4437 return I40E_SUCCESS;
4440 static enum i40e_status_code
4441 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4442 struct i40e_aqc_vsi_properties_data *info,
4443 uint8_t enabled_tcmap)
4445 enum i40e_status_code ret;
4446 int i, total_tc = 0;
4447 uint16_t qpnum_per_tc, bsf, qp_idx;
4449 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4450 if (ret != I40E_SUCCESS)
4453 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4454 if (enabled_tcmap & (1 << i))
4458 vsi->enabled_tc = enabled_tcmap;
4460 /* Number of queues per enabled TC */
4461 qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4462 qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4463 bsf = rte_bsf32(qpnum_per_tc);
4465 /* Adjust the queue number to actual queues that can be applied */
4466 if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4467 vsi->nb_qps = qpnum_per_tc * total_tc;
4470 * Configure TC and queue mapping parameters, for enabled TC,
4471 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4472 * default queue will serve it.
4475 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4476 if (vsi->enabled_tc & (1 << i)) {
4477 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4478 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4479 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4480 qp_idx += qpnum_per_tc;
4482 info->tc_mapping[i] = 0;
4485 /* Associate queue number with VSI */
4486 if (vsi->type == I40E_VSI_SRIOV) {
4487 info->mapping_flags |=
4488 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4489 for (i = 0; i < vsi->nb_qps; i++)
4490 info->queue_mapping[i] =
4491 rte_cpu_to_le_16(vsi->base_queue + i);
4493 info->mapping_flags |=
4494 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4495 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4497 info->valid_sections |=
4498 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4500 return I40E_SUCCESS;
4504 i40e_veb_release(struct i40e_veb *veb)
4506 struct i40e_vsi *vsi;
4512 if (!TAILQ_EMPTY(&veb->head)) {
4513 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4516 /* associate_vsi field is NULL for floating VEB */
4517 if (veb->associate_vsi != NULL) {
4518 vsi = veb->associate_vsi;
4519 hw = I40E_VSI_TO_HW(vsi);
4521 vsi->uplink_seid = veb->uplink_seid;
4524 veb->associate_pf->main_vsi->floating_veb = NULL;
4525 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4528 i40e_aq_delete_element(hw, veb->seid, NULL);
4530 return I40E_SUCCESS;
4534 static struct i40e_veb *
4535 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4537 struct i40e_veb *veb;
4543 "veb setup failed, associated PF shouldn't null");
4546 hw = I40E_PF_TO_HW(pf);
4548 veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4550 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4554 veb->associate_vsi = vsi;
4555 veb->associate_pf = pf;
4556 TAILQ_INIT(&veb->head);
4557 veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4559 /* create floating veb if vsi is NULL */
4561 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4562 I40E_DEFAULT_TCMAP, false,
4563 &veb->seid, false, NULL);
4565 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4566 true, &veb->seid, false, NULL);
4569 if (ret != I40E_SUCCESS) {
4570 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4571 hw->aq.asq_last_status);
4574 veb->enabled_tc = I40E_DEFAULT_TCMAP;
4576 /* get statistics index */
4577 ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4578 &veb->stats_idx, NULL, NULL, NULL);
4579 if (ret != I40E_SUCCESS) {
4580 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4581 hw->aq.asq_last_status);
4584 /* Get VEB bandwidth, to be implemented */
4585 /* Now associated vsi binding to the VEB, set uplink to this VEB */
4587 vsi->uplink_seid = veb->seid;
4596 i40e_vsi_release(struct i40e_vsi *vsi)
4600 struct i40e_vsi_list *vsi_list;
4603 struct i40e_mac_filter *f;
4604 uint16_t user_param;
4607 return I40E_SUCCESS;
4612 user_param = vsi->user_param;
4614 pf = I40E_VSI_TO_PF(vsi);
4615 hw = I40E_VSI_TO_HW(vsi);
4617 /* VSI has child to attach, release child first */
4619 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4620 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4623 i40e_veb_release(vsi->veb);
4626 if (vsi->floating_veb) {
4627 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4628 if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4633 /* Remove all macvlan filters of the VSI */
4634 i40e_vsi_remove_all_macvlan_filter(vsi);
4635 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4638 if (vsi->type != I40E_VSI_MAIN &&
4639 ((vsi->type != I40E_VSI_SRIOV) ||
4640 !pf->floating_veb_list[user_param])) {
4641 /* Remove vsi from parent's sibling list */
4642 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4643 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4644 return I40E_ERR_PARAM;
4646 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4647 &vsi->sib_vsi_list, list);
4649 /* Remove all switch element of the VSI */
4650 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4651 if (ret != I40E_SUCCESS)
4652 PMD_DRV_LOG(ERR, "Failed to delete element");
4655 if ((vsi->type == I40E_VSI_SRIOV) &&
4656 pf->floating_veb_list[user_param]) {
4657 /* Remove vsi from parent's sibling list */
4658 if (vsi->parent_vsi == NULL ||
4659 vsi->parent_vsi->floating_veb == NULL) {
4660 PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4661 return I40E_ERR_PARAM;
4663 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4664 &vsi->sib_vsi_list, list);
4666 /* Remove all switch element of the VSI */
4667 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4668 if (ret != I40E_SUCCESS)
4669 PMD_DRV_LOG(ERR, "Failed to delete element");
4672 i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4674 if (vsi->type != I40E_VSI_SRIOV)
4675 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4678 return I40E_SUCCESS;
4682 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
4684 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4685 struct i40e_aqc_remove_macvlan_element_data def_filter;
4686 struct i40e_mac_filter_info filter;
4689 if (vsi->type != I40E_VSI_MAIN)
4690 return I40E_ERR_CONFIG;
4691 memset(&def_filter, 0, sizeof(def_filter));
4692 rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
4694 def_filter.vlan_tag = 0;
4695 def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4696 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4697 ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
4698 if (ret != I40E_SUCCESS) {
4699 struct i40e_mac_filter *f;
4700 struct ether_addr *mac;
4703 "Cannot remove the default macvlan filter");
4704 /* It needs to add the permanent mac into mac list */
4705 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4707 PMD_DRV_LOG(ERR, "failed to allocate memory");
4708 return I40E_ERR_NO_MEMORY;
4710 mac = &f->mac_info.mac_addr;
4711 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
4713 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4714 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4719 rte_memcpy(&filter.mac_addr,
4720 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
4721 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4722 return i40e_vsi_add_mac(vsi, &filter);
4726 * i40e_vsi_get_bw_config - Query VSI BW Information
4727 * @vsi: the VSI to be queried
4729 * Returns 0 on success, negative value on failure
4731 static enum i40e_status_code
4732 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
4734 struct i40e_aqc_query_vsi_bw_config_resp bw_config;
4735 struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
4736 struct i40e_hw *hw = &vsi->adapter->hw;
4741 memset(&bw_config, 0, sizeof(bw_config));
4742 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4743 if (ret != I40E_SUCCESS) {
4744 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
4745 hw->aq.asq_last_status);
4749 memset(&ets_sla_config, 0, sizeof(ets_sla_config));
4750 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
4751 &ets_sla_config, NULL);
4752 if (ret != I40E_SUCCESS) {
4754 "VSI failed to get TC bandwdith configuration %u",
4755 hw->aq.asq_last_status);
4759 /* store and print out BW info */
4760 vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
4761 vsi->bw_info.bw_max = bw_config.max_bw;
4762 PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
4763 PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
4764 bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
4765 (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
4767 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4768 vsi->bw_info.bw_ets_share_credits[i] =
4769 ets_sla_config.share_credits[i];
4770 vsi->bw_info.bw_ets_credits[i] =
4771 rte_le_to_cpu_16(ets_sla_config.credits[i]);
4772 /* 4 bits per TC, 4th bit is reserved */
4773 vsi->bw_info.bw_ets_max[i] =
4774 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
4775 RTE_LEN2MASK(3, uint8_t));
4776 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
4777 vsi->bw_info.bw_ets_share_credits[i]);
4778 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
4779 vsi->bw_info.bw_ets_credits[i]);
4780 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
4781 vsi->bw_info.bw_ets_max[i]);
4784 return I40E_SUCCESS;
4787 /* i40e_enable_pf_lb
4788 * @pf: pointer to the pf structure
4790 * allow loopback on pf
4793 i40e_enable_pf_lb(struct i40e_pf *pf)
4795 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4796 struct i40e_vsi_context ctxt;
4799 /* Use the FW API if FW >= v5.0 */
4800 if (hw->aq.fw_maj_ver < 5) {
4801 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
4805 memset(&ctxt, 0, sizeof(ctxt));
4806 ctxt.seid = pf->main_vsi_seid;
4807 ctxt.pf_num = hw->pf_id;
4808 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4810 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
4811 ret, hw->aq.asq_last_status);
4814 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
4815 ctxt.info.valid_sections =
4816 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
4817 ctxt.info.switch_id |=
4818 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
4820 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4822 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
4823 hw->aq.asq_last_status);
4828 i40e_vsi_setup(struct i40e_pf *pf,
4829 enum i40e_vsi_type type,
4830 struct i40e_vsi *uplink_vsi,
4831 uint16_t user_param)
4833 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4834 struct i40e_vsi *vsi;
4835 struct i40e_mac_filter_info filter;
4837 struct i40e_vsi_context ctxt;
4838 struct ether_addr broadcast =
4839 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
4841 if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
4842 uplink_vsi == NULL) {
4844 "VSI setup failed, VSI link shouldn't be NULL");
4848 if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
4850 "VSI setup failed, MAIN VSI uplink VSI should be NULL");
4855 * 1.type is not MAIN and uplink vsi is not NULL
4856 * If uplink vsi didn't setup VEB, create one first under veb field
4857 * 2.type is SRIOV and the uplink is NULL
4858 * If floating VEB is NULL, create one veb under floating veb field
4861 if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
4862 uplink_vsi->veb == NULL) {
4863 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
4865 if (uplink_vsi->veb == NULL) {
4866 PMD_DRV_LOG(ERR, "VEB setup failed");
4869 /* set ALLOWLOOPBACk on pf, when veb is created */
4870 i40e_enable_pf_lb(pf);
4873 if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
4874 pf->main_vsi->floating_veb == NULL) {
4875 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
4877 if (pf->main_vsi->floating_veb == NULL) {
4878 PMD_DRV_LOG(ERR, "VEB setup failed");
4883 vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
4885 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
4888 TAILQ_INIT(&vsi->mac_list);
4890 vsi->adapter = I40E_PF_TO_ADAPTER(pf);
4891 vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
4892 vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
4893 vsi->user_param = user_param;
4894 vsi->vlan_anti_spoof_on = 0;
4895 vsi->vlan_filter_on = 0;
4896 /* Allocate queues */
4897 switch (vsi->type) {
4898 case I40E_VSI_MAIN :
4899 vsi->nb_qps = pf->lan_nb_qps;
4901 case I40E_VSI_SRIOV :
4902 vsi->nb_qps = pf->vf_nb_qps;
4904 case I40E_VSI_VMDQ2:
4905 vsi->nb_qps = pf->vmdq_nb_qps;
4908 vsi->nb_qps = pf->fdir_nb_qps;
4914 * The filter status descriptor is reported in rx queue 0,
4915 * while the tx queue for fdir filter programming has no
4916 * such constraints, can be non-zero queues.
4917 * To simplify it, choose FDIR vsi use queue 0 pair.
4918 * To make sure it will use queue 0 pair, queue allocation
4919 * need be done before this function is called
4921 if (type != I40E_VSI_FDIR) {
4922 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
4924 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
4928 vsi->base_queue = ret;
4930 vsi->base_queue = I40E_FDIR_QUEUE_ID;
4932 /* VF has MSIX interrupt in VF range, don't allocate here */
4933 if (type == I40E_VSI_MAIN) {
4934 ret = i40e_res_pool_alloc(&pf->msix_pool,
4935 RTE_MIN(vsi->nb_qps,
4936 RTE_MAX_RXTX_INTR_VEC_ID));
4938 PMD_DRV_LOG(ERR, "VSI MAIN %d get heap failed %d",
4940 goto fail_queue_alloc;
4942 vsi->msix_intr = ret;
4943 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
4944 } else if (type != I40E_VSI_SRIOV) {
4945 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
4947 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
4948 goto fail_queue_alloc;
4950 vsi->msix_intr = ret;
4958 if (type == I40E_VSI_MAIN) {
4959 /* For main VSI, no need to add since it's default one */
4960 vsi->uplink_seid = pf->mac_seid;
4961 vsi->seid = pf->main_vsi_seid;
4962 /* Bind queues with specific MSIX interrupt */
4964 * Needs 2 interrupt at least, one for misc cause which will
4965 * enabled from OS side, Another for queues binding the
4966 * interrupt from device side only.
4969 /* Get default VSI parameters from hardware */
4970 memset(&ctxt, 0, sizeof(ctxt));
4971 ctxt.seid = vsi->seid;
4972 ctxt.pf_num = hw->pf_id;
4973 ctxt.uplink_seid = vsi->uplink_seid;
4975 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
4976 if (ret != I40E_SUCCESS) {
4977 PMD_DRV_LOG(ERR, "Failed to get VSI params");
4978 goto fail_msix_alloc;
4980 rte_memcpy(&vsi->info, &ctxt.info,
4981 sizeof(struct i40e_aqc_vsi_properties_data));
4982 vsi->vsi_id = ctxt.vsi_number;
4983 vsi->info.valid_sections = 0;
4985 /* Configure tc, enabled TC0 only */
4986 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
4988 PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
4989 goto fail_msix_alloc;
4992 /* TC, queue mapping */
4993 memset(&ctxt, 0, sizeof(ctxt));
4994 vsi->info.valid_sections |=
4995 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4996 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
4997 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
4998 rte_memcpy(&ctxt.info, &vsi->info,
4999 sizeof(struct i40e_aqc_vsi_properties_data));
5000 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5001 I40E_DEFAULT_TCMAP);
5002 if (ret != I40E_SUCCESS) {
5004 "Failed to configure TC queue mapping");
5005 goto fail_msix_alloc;
5007 ctxt.seid = vsi->seid;
5008 ctxt.pf_num = hw->pf_id;
5009 ctxt.uplink_seid = vsi->uplink_seid;
5012 /* Update VSI parameters */
5013 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5014 if (ret != I40E_SUCCESS) {
5015 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5016 goto fail_msix_alloc;
5019 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5020 sizeof(vsi->info.tc_mapping));
5021 rte_memcpy(&vsi->info.queue_mapping,
5022 &ctxt.info.queue_mapping,
5023 sizeof(vsi->info.queue_mapping));
5024 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5025 vsi->info.valid_sections = 0;
5027 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5031 * Updating default filter settings are necessary to prevent
5032 * reception of tagged packets.
5033 * Some old firmware configurations load a default macvlan
5034 * filter which accepts both tagged and untagged packets.
5035 * The updating is to use a normal filter instead if needed.
5036 * For NVM 4.2.2 or after, the updating is not needed anymore.
5037 * The firmware with correct configurations load the default
5038 * macvlan filter which is expected and cannot be removed.
5040 i40e_update_default_filter_setting(vsi);
5041 i40e_config_qinq(hw, vsi);
5042 } else if (type == I40E_VSI_SRIOV) {
5043 memset(&ctxt, 0, sizeof(ctxt));
5045 * For other VSI, the uplink_seid equals to uplink VSI's
5046 * uplink_seid since they share same VEB
5048 if (uplink_vsi == NULL)
5049 vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5051 vsi->uplink_seid = uplink_vsi->uplink_seid;
5052 ctxt.pf_num = hw->pf_id;
5053 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5054 ctxt.uplink_seid = vsi->uplink_seid;
5055 ctxt.connection_type = 0x1;
5056 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5058 /* Use the VEB configuration if FW >= v5.0 */
5059 if (hw->aq.fw_maj_ver >= 5) {
5060 /* Configure switch ID */
5061 ctxt.info.valid_sections |=
5062 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5063 ctxt.info.switch_id =
5064 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5067 /* Configure port/vlan */
5068 ctxt.info.valid_sections |=
5069 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5070 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5071 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5072 hw->func_caps.enabled_tcmap);
5073 if (ret != I40E_SUCCESS) {
5075 "Failed to configure TC queue mapping");
5076 goto fail_msix_alloc;
5079 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5080 ctxt.info.valid_sections |=
5081 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5083 * Since VSI is not created yet, only configure parameter,
5084 * will add vsi below.
5087 i40e_config_qinq(hw, vsi);
5088 } else if (type == I40E_VSI_VMDQ2) {
5089 memset(&ctxt, 0, sizeof(ctxt));
5091 * For other VSI, the uplink_seid equals to uplink VSI's
5092 * uplink_seid since they share same VEB
5094 vsi->uplink_seid = uplink_vsi->uplink_seid;
5095 ctxt.pf_num = hw->pf_id;
5097 ctxt.uplink_seid = vsi->uplink_seid;
5098 ctxt.connection_type = 0x1;
5099 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5101 ctxt.info.valid_sections |=
5102 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5103 /* user_param carries flag to enable loop back */
5105 ctxt.info.switch_id =
5106 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5107 ctxt.info.switch_id |=
5108 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5111 /* Configure port/vlan */
5112 ctxt.info.valid_sections |=
5113 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5114 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5115 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5116 I40E_DEFAULT_TCMAP);
5117 if (ret != I40E_SUCCESS) {
5119 "Failed to configure TC queue mapping");
5120 goto fail_msix_alloc;
5122 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5123 ctxt.info.valid_sections |=
5124 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5125 } else if (type == I40E_VSI_FDIR) {
5126 memset(&ctxt, 0, sizeof(ctxt));
5127 vsi->uplink_seid = uplink_vsi->uplink_seid;
5128 ctxt.pf_num = hw->pf_id;
5130 ctxt.uplink_seid = vsi->uplink_seid;
5131 ctxt.connection_type = 0x1; /* regular data port */
5132 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5133 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5134 I40E_DEFAULT_TCMAP);
5135 if (ret != I40E_SUCCESS) {
5137 "Failed to configure TC queue mapping.");
5138 goto fail_msix_alloc;
5140 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5141 ctxt.info.valid_sections |=
5142 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5144 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5145 goto fail_msix_alloc;
5148 if (vsi->type != I40E_VSI_MAIN) {
5149 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5150 if (ret != I40E_SUCCESS) {
5151 PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5152 hw->aq.asq_last_status);
5153 goto fail_msix_alloc;
5155 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5156 vsi->info.valid_sections = 0;
5157 vsi->seid = ctxt.seid;
5158 vsi->vsi_id = ctxt.vsi_number;
5159 vsi->sib_vsi_list.vsi = vsi;
5160 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5161 TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5162 &vsi->sib_vsi_list, list);
5164 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5165 &vsi->sib_vsi_list, list);
5169 /* MAC/VLAN configuration */
5170 rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5171 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5173 ret = i40e_vsi_add_mac(vsi, &filter);
5174 if (ret != I40E_SUCCESS) {
5175 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5176 goto fail_msix_alloc;
5179 /* Get VSI BW information */
5180 i40e_vsi_get_bw_config(vsi);
5183 i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5185 i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5191 /* Configure vlan filter on or off */
5193 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5196 struct i40e_mac_filter *f;
5198 struct i40e_mac_filter_info *mac_filter;
5199 enum rte_mac_filter_type desired_filter;
5200 int ret = I40E_SUCCESS;
5203 /* Filter to match MAC and VLAN */
5204 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5206 /* Filter to match only MAC */
5207 desired_filter = RTE_MAC_PERFECT_MATCH;
5212 mac_filter = rte_zmalloc("mac_filter_info_data",
5213 num * sizeof(*mac_filter), 0);
5214 if (mac_filter == NULL) {
5215 PMD_DRV_LOG(ERR, "failed to allocate memory");
5216 return I40E_ERR_NO_MEMORY;
5221 /* Remove all existing mac */
5222 TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5223 mac_filter[i] = f->mac_info;
5224 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5226 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5227 on ? "enable" : "disable");
5233 /* Override with new filter */
5234 for (i = 0; i < num; i++) {
5235 mac_filter[i].filter_type = desired_filter;
5236 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5238 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5239 on ? "enable" : "disable");
5245 rte_free(mac_filter);
5249 /* Configure vlan stripping on or off */
5251 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5253 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5254 struct i40e_vsi_context ctxt;
5256 int ret = I40E_SUCCESS;
5258 /* Check if it has been already on or off */
5259 if (vsi->info.valid_sections &
5260 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5262 if ((vsi->info.port_vlan_flags &
5263 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5264 return 0; /* already on */
5266 if ((vsi->info.port_vlan_flags &
5267 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5268 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5269 return 0; /* already off */
5274 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5276 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5277 vsi->info.valid_sections =
5278 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5279 vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5280 vsi->info.port_vlan_flags |= vlan_flags;
5281 ctxt.seid = vsi->seid;
5282 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5283 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5285 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5286 on ? "enable" : "disable");
5292 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5294 struct rte_eth_dev_data *data = dev->data;
5298 /* Apply vlan offload setting */
5299 mask = ETH_VLAN_STRIP_MASK |
5300 ETH_VLAN_FILTER_MASK |
5301 ETH_VLAN_EXTEND_MASK;
5302 ret = i40e_vlan_offload_set(dev, mask);
5304 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5308 /* Apply pvid setting */
5309 ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5310 data->dev_conf.txmode.hw_vlan_insert_pvid);
5312 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5318 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5320 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5322 return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5326 i40e_update_flow_control(struct i40e_hw *hw)
5328 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5329 struct i40e_link_status link_status;
5330 uint32_t rxfc = 0, txfc = 0, reg;
5334 memset(&link_status, 0, sizeof(link_status));
5335 ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5336 if (ret != I40E_SUCCESS) {
5337 PMD_DRV_LOG(ERR, "Failed to get link status information");
5338 goto write_reg; /* Disable flow control */
5341 an_info = hw->phy.link_info.an_info;
5342 if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5343 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5344 ret = I40E_ERR_NOT_READY;
5345 goto write_reg; /* Disable flow control */
5348 * If link auto negotiation is enabled, flow control needs to
5349 * be configured according to it
5351 switch (an_info & I40E_LINK_PAUSE_RXTX) {
5352 case I40E_LINK_PAUSE_RXTX:
5355 hw->fc.current_mode = I40E_FC_FULL;
5357 case I40E_AQ_LINK_PAUSE_RX:
5359 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5361 case I40E_AQ_LINK_PAUSE_TX:
5363 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5366 hw->fc.current_mode = I40E_FC_NONE;
5371 I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5372 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5373 reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5374 reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5375 reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5376 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5383 i40e_pf_setup(struct i40e_pf *pf)
5385 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5386 struct i40e_filter_control_settings settings;
5387 struct i40e_vsi *vsi;
5390 /* Clear all stats counters */
5391 pf->offset_loaded = FALSE;
5392 memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5393 memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5394 memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5395 memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5397 ret = i40e_pf_get_switch_config(pf);
5398 if (ret != I40E_SUCCESS) {
5399 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5402 if (pf->flags & I40E_FLAG_FDIR) {
5403 /* make queue allocated first, let FDIR use queue pair 0*/
5404 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5405 if (ret != I40E_FDIR_QUEUE_ID) {
5407 "queue allocation fails for FDIR: ret =%d",
5409 pf->flags &= ~I40E_FLAG_FDIR;
5412 /* main VSI setup */
5413 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5415 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5416 return I40E_ERR_NOT_READY;
5420 /* Configure filter control */
5421 memset(&settings, 0, sizeof(settings));
5422 if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5423 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5424 else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5425 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5427 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5428 hw->func_caps.rss_table_size);
5429 return I40E_ERR_PARAM;
5431 PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5432 hw->func_caps.rss_table_size);
5433 pf->hash_lut_size = hw->func_caps.rss_table_size;
5435 /* Enable ethtype and macvlan filters */
5436 settings.enable_ethtype = TRUE;
5437 settings.enable_macvlan = TRUE;
5438 ret = i40e_set_filter_control(hw, &settings);
5440 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5443 /* Update flow control according to the auto negotiation */
5444 i40e_update_flow_control(hw);
5446 return I40E_SUCCESS;
5450 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5456 * Set or clear TX Queue Disable flags,
5457 * which is required by hardware.
5459 i40e_pre_tx_queue_cfg(hw, q_idx, on);
5460 rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5462 /* Wait until the request is finished */
5463 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5464 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5465 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5466 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5467 ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5473 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5474 return I40E_SUCCESS; /* already on, skip next steps */
5476 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5477 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5479 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5480 return I40E_SUCCESS; /* already off, skip next steps */
5481 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5483 /* Write the register */
5484 I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5485 /* Check the result */
5486 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5487 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5488 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5490 if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5491 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5494 if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5495 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5499 /* Check if it is timeout */
5500 if (j >= I40E_CHK_Q_ENA_COUNT) {
5501 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5502 (on ? "enable" : "disable"), q_idx);
5503 return I40E_ERR_TIMEOUT;
5506 return I40E_SUCCESS;
5509 /* Swith on or off the tx queues */
5511 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5513 struct rte_eth_dev_data *dev_data = pf->dev_data;
5514 struct i40e_tx_queue *txq;
5515 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5519 for (i = 0; i < dev_data->nb_tx_queues; i++) {
5520 txq = dev_data->tx_queues[i];
5521 /* Don't operate the queue if not configured or
5522 * if starting only per queue */
5523 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5526 ret = i40e_dev_tx_queue_start(dev, i);
5528 ret = i40e_dev_tx_queue_stop(dev, i);
5529 if ( ret != I40E_SUCCESS)
5533 return I40E_SUCCESS;
5537 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5542 /* Wait until the request is finished */
5543 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5544 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5545 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5546 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5547 ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5552 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5553 return I40E_SUCCESS; /* Already on, skip next steps */
5554 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5556 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5557 return I40E_SUCCESS; /* Already off, skip next steps */
5558 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5561 /* Write the register */
5562 I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5563 /* Check the result */
5564 for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5565 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5566 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5568 if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5569 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5572 if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5573 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5578 /* Check if it is timeout */
5579 if (j >= I40E_CHK_Q_ENA_COUNT) {
5580 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5581 (on ? "enable" : "disable"), q_idx);
5582 return I40E_ERR_TIMEOUT;
5585 return I40E_SUCCESS;
5587 /* Switch on or off the rx queues */
5589 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5591 struct rte_eth_dev_data *dev_data = pf->dev_data;
5592 struct i40e_rx_queue *rxq;
5593 struct rte_eth_dev *dev = pf->adapter->eth_dev;
5597 for (i = 0; i < dev_data->nb_rx_queues; i++) {
5598 rxq = dev_data->rx_queues[i];
5599 /* Don't operate the queue if not configured or
5600 * if starting only per queue */
5601 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5604 ret = i40e_dev_rx_queue_start(dev, i);
5606 ret = i40e_dev_rx_queue_stop(dev, i);
5607 if (ret != I40E_SUCCESS)
5611 return I40E_SUCCESS;
5614 /* Switch on or off all the rx/tx queues */
5616 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5621 /* enable rx queues before enabling tx queues */
5622 ret = i40e_dev_switch_rx_queues(pf, on);
5624 PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5627 ret = i40e_dev_switch_tx_queues(pf, on);
5629 /* Stop tx queues before stopping rx queues */
5630 ret = i40e_dev_switch_tx_queues(pf, on);
5632 PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5635 ret = i40e_dev_switch_rx_queues(pf, on);
5641 /* Initialize VSI for TX */
5643 i40e_dev_tx_init(struct i40e_pf *pf)
5645 struct rte_eth_dev_data *data = pf->dev_data;
5647 uint32_t ret = I40E_SUCCESS;
5648 struct i40e_tx_queue *txq;
5650 for (i = 0; i < data->nb_tx_queues; i++) {
5651 txq = data->tx_queues[i];
5652 if (!txq || !txq->q_set)
5654 ret = i40e_tx_queue_init(txq);
5655 if (ret != I40E_SUCCESS)
5658 if (ret == I40E_SUCCESS)
5659 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5665 /* Initialize VSI for RX */
5667 i40e_dev_rx_init(struct i40e_pf *pf)
5669 struct rte_eth_dev_data *data = pf->dev_data;
5670 int ret = I40E_SUCCESS;
5672 struct i40e_rx_queue *rxq;
5674 i40e_pf_config_mq_rx(pf);
5675 for (i = 0; i < data->nb_rx_queues; i++) {
5676 rxq = data->rx_queues[i];
5677 if (!rxq || !rxq->q_set)
5680 ret = i40e_rx_queue_init(rxq);
5681 if (ret != I40E_SUCCESS) {
5683 "Failed to do RX queue initialization");
5687 if (ret == I40E_SUCCESS)
5688 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
5695 i40e_dev_rxtx_init(struct i40e_pf *pf)
5699 err = i40e_dev_tx_init(pf);
5701 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
5704 err = i40e_dev_rx_init(pf);
5706 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
5714 i40e_vmdq_setup(struct rte_eth_dev *dev)
5716 struct rte_eth_conf *conf = &dev->data->dev_conf;
5717 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5718 int i, err, conf_vsis, j, loop;
5719 struct i40e_vsi *vsi;
5720 struct i40e_vmdq_info *vmdq_info;
5721 struct rte_eth_vmdq_rx_conf *vmdq_conf;
5722 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5725 * Disable interrupt to avoid message from VF. Furthermore, it will
5726 * avoid race condition in VSI creation/destroy.
5728 i40e_pf_disable_irq0(hw);
5730 if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
5731 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
5735 conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
5736 if (conf_vsis > pf->max_nb_vmdq_vsi) {
5737 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
5738 conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
5739 pf->max_nb_vmdq_vsi);
5743 if (pf->vmdq != NULL) {
5744 PMD_INIT_LOG(INFO, "VMDQ already configured");
5748 pf->vmdq = rte_zmalloc("vmdq_info_struct",
5749 sizeof(*vmdq_info) * conf_vsis, 0);
5751 if (pf->vmdq == NULL) {
5752 PMD_INIT_LOG(ERR, "Failed to allocate memory");
5756 vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
5758 /* Create VMDQ VSI */
5759 for (i = 0; i < conf_vsis; i++) {
5760 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
5761 vmdq_conf->enable_loop_back);
5763 PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
5767 vmdq_info = &pf->vmdq[i];
5769 vmdq_info->vsi = vsi;
5771 pf->nb_cfg_vmdq_vsi = conf_vsis;
5773 /* Configure Vlan */
5774 loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
5775 for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
5776 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
5777 if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
5778 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
5779 vmdq_conf->pool_map[i].vlan_id, j);
5781 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
5782 vmdq_conf->pool_map[i].vlan_id);
5784 PMD_INIT_LOG(ERR, "Failed to add vlan");
5792 i40e_pf_enable_irq0(hw);
5797 for (i = 0; i < conf_vsis; i++)
5798 if (pf->vmdq[i].vsi == NULL)
5801 i40e_vsi_release(pf->vmdq[i].vsi);
5805 i40e_pf_enable_irq0(hw);
5810 i40e_stat_update_32(struct i40e_hw *hw,
5818 new_data = (uint64_t)I40E_READ_REG(hw, reg);
5822 if (new_data >= *offset)
5823 *stat = (uint64_t)(new_data - *offset);
5825 *stat = (uint64_t)((new_data +
5826 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
5830 i40e_stat_update_48(struct i40e_hw *hw,
5839 new_data = (uint64_t)I40E_READ_REG(hw, loreg);
5840 new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
5841 I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
5846 if (new_data >= *offset)
5847 *stat = new_data - *offset;
5849 *stat = (uint64_t)((new_data +
5850 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
5852 *stat &= I40E_48_BIT_MASK;
5857 i40e_pf_disable_irq0(struct i40e_hw *hw)
5859 /* Disable all interrupt types */
5860 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
5861 I40E_WRITE_FLUSH(hw);
5866 i40e_pf_enable_irq0(struct i40e_hw *hw)
5868 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
5869 I40E_PFINT_DYN_CTL0_INTENA_MASK |
5870 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
5871 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
5872 I40E_WRITE_FLUSH(hw);
5876 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
5878 /* read pending request and disable first */
5879 i40e_pf_disable_irq0(hw);
5880 I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
5881 I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
5882 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
5885 /* Link no queues with irq0 */
5886 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
5887 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
5891 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
5893 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5894 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5897 uint32_t index, offset, val;
5902 * Try to find which VF trigger a reset, use absolute VF id to access
5903 * since the reg is global register.
5905 for (i = 0; i < pf->vf_num; i++) {
5906 abs_vf_id = hw->func_caps.vf_base_id + i;
5907 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
5908 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
5909 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
5910 /* VFR event occurred */
5911 if (val & (0x1 << offset)) {
5914 /* Clear the event first */
5915 I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
5917 PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
5919 * Only notify a VF reset event occurred,
5920 * don't trigger another SW reset
5922 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
5923 if (ret != I40E_SUCCESS)
5924 PMD_DRV_LOG(ERR, "Failed to do VF reset");
5930 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
5932 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5935 for (i = 0; i < pf->vf_num; i++)
5936 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
5940 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
5942 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5943 struct i40e_arq_event_info info;
5944 uint16_t pending, opcode;
5947 info.buf_len = I40E_AQ_BUF_SZ;
5948 info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
5949 if (!info.msg_buf) {
5950 PMD_DRV_LOG(ERR, "Failed to allocate mem");
5956 ret = i40e_clean_arq_element(hw, &info, &pending);
5958 if (ret != I40E_SUCCESS) {
5960 "Failed to read msg from AdminQ, aq_err: %u",
5961 hw->aq.asq_last_status);
5964 opcode = rte_le_to_cpu_16(info.desc.opcode);
5967 case i40e_aqc_opc_send_msg_to_pf:
5968 /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
5969 i40e_pf_host_handle_vf_msg(dev,
5970 rte_le_to_cpu_16(info.desc.retval),
5971 rte_le_to_cpu_32(info.desc.cookie_high),
5972 rte_le_to_cpu_32(info.desc.cookie_low),
5976 case i40e_aqc_opc_get_link_status:
5977 ret = i40e_dev_link_update(dev, 0);
5979 _rte_eth_dev_callback_process(dev,
5980 RTE_ETH_EVENT_INTR_LSC, NULL, NULL);
5983 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
5988 rte_free(info.msg_buf);
5992 * Interrupt handler triggered by NIC for handling
5993 * specific interrupt.
5996 * Pointer to interrupt handle.
5998 * The address of parameter (struct rte_eth_dev *) regsitered before.
6004 i40e_dev_interrupt_handler(void *param)
6006 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6007 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6010 /* Disable interrupt */
6011 i40e_pf_disable_irq0(hw);
6013 /* read out interrupt causes */
6014 icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6016 /* No interrupt event indicated */
6017 if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6018 PMD_DRV_LOG(INFO, "No interrupt event");
6021 if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6022 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6023 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6024 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6025 if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6026 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6027 if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6028 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6029 if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6030 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6031 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6032 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6033 if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6034 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6036 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6037 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6038 i40e_dev_handle_vfr_event(dev);
6040 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6041 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6042 i40e_dev_handle_aq_msg(dev);
6046 /* Enable interrupt */
6047 i40e_pf_enable_irq0(hw);
6048 rte_intr_enable(dev->intr_handle);
6052 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6053 struct i40e_macvlan_filter *filter,
6056 int ele_num, ele_buff_size;
6057 int num, actual_num, i;
6059 int ret = I40E_SUCCESS;
6060 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6061 struct i40e_aqc_add_macvlan_element_data *req_list;
6063 if (filter == NULL || total == 0)
6064 return I40E_ERR_PARAM;
6065 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6066 ele_buff_size = hw->aq.asq_buf_size;
6068 req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6069 if (req_list == NULL) {
6070 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6071 return I40E_ERR_NO_MEMORY;
6076 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6077 memset(req_list, 0, ele_buff_size);
6079 for (i = 0; i < actual_num; i++) {
6080 rte_memcpy(req_list[i].mac_addr,
6081 &filter[num + i].macaddr, ETH_ADDR_LEN);
6082 req_list[i].vlan_tag =
6083 rte_cpu_to_le_16(filter[num + i].vlan_id);
6085 switch (filter[num + i].filter_type) {
6086 case RTE_MAC_PERFECT_MATCH:
6087 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6088 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6090 case RTE_MACVLAN_PERFECT_MATCH:
6091 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6093 case RTE_MAC_HASH_MATCH:
6094 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6095 I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6097 case RTE_MACVLAN_HASH_MATCH:
6098 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6101 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6102 ret = I40E_ERR_PARAM;
6106 req_list[i].queue_number = 0;
6108 req_list[i].flags = rte_cpu_to_le_16(flags);
6111 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6113 if (ret != I40E_SUCCESS) {
6114 PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6118 } while (num < total);
6126 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6127 struct i40e_macvlan_filter *filter,
6130 int ele_num, ele_buff_size;
6131 int num, actual_num, i;
6133 int ret = I40E_SUCCESS;
6134 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6135 struct i40e_aqc_remove_macvlan_element_data *req_list;
6137 if (filter == NULL || total == 0)
6138 return I40E_ERR_PARAM;
6140 ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6141 ele_buff_size = hw->aq.asq_buf_size;
6143 req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6144 if (req_list == NULL) {
6145 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6146 return I40E_ERR_NO_MEMORY;
6151 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6152 memset(req_list, 0, ele_buff_size);
6154 for (i = 0; i < actual_num; i++) {
6155 rte_memcpy(req_list[i].mac_addr,
6156 &filter[num + i].macaddr, ETH_ADDR_LEN);
6157 req_list[i].vlan_tag =
6158 rte_cpu_to_le_16(filter[num + i].vlan_id);
6160 switch (filter[num + i].filter_type) {
6161 case RTE_MAC_PERFECT_MATCH:
6162 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6163 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6165 case RTE_MACVLAN_PERFECT_MATCH:
6166 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6168 case RTE_MAC_HASH_MATCH:
6169 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6170 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6172 case RTE_MACVLAN_HASH_MATCH:
6173 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6176 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6177 ret = I40E_ERR_PARAM;
6180 req_list[i].flags = rte_cpu_to_le_16(flags);
6183 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6185 if (ret != I40E_SUCCESS) {
6186 PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6190 } while (num < total);
6197 /* Find out specific MAC filter */
6198 static struct i40e_mac_filter *
6199 i40e_find_mac_filter(struct i40e_vsi *vsi,
6200 struct ether_addr *macaddr)
6202 struct i40e_mac_filter *f;
6204 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6205 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6213 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6216 uint32_t vid_idx, vid_bit;
6218 if (vlan_id > ETH_VLAN_ID_MAX)
6221 vid_idx = I40E_VFTA_IDX(vlan_id);
6222 vid_bit = I40E_VFTA_BIT(vlan_id);
6224 if (vsi->vfta[vid_idx] & vid_bit)
6231 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6232 uint16_t vlan_id, bool on)
6234 uint32_t vid_idx, vid_bit;
6236 vid_idx = I40E_VFTA_IDX(vlan_id);
6237 vid_bit = I40E_VFTA_BIT(vlan_id);
6240 vsi->vfta[vid_idx] |= vid_bit;
6242 vsi->vfta[vid_idx] &= ~vid_bit;
6246 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6247 uint16_t vlan_id, bool on)
6249 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6250 struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6253 if (vlan_id > ETH_VLAN_ID_MAX)
6256 i40e_store_vlan_filter(vsi, vlan_id, on);
6258 if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6261 vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6264 ret = i40e_aq_add_vlan(hw, vsi->seid,
6265 &vlan_data, 1, NULL);
6266 if (ret != I40E_SUCCESS)
6267 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6269 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6270 &vlan_data, 1, NULL);
6271 if (ret != I40E_SUCCESS)
6273 "Failed to remove vlan filter");
6278 * Find all vlan options for specific mac addr,
6279 * return with actual vlan found.
6282 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6283 struct i40e_macvlan_filter *mv_f,
6284 int num, struct ether_addr *addr)
6290 * Not to use i40e_find_vlan_filter to decrease the loop time,
6291 * although the code looks complex.
6293 if (num < vsi->vlan_num)
6294 return I40E_ERR_PARAM;
6297 for (j = 0; j < I40E_VFTA_SIZE; j++) {
6299 for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6300 if (vsi->vfta[j] & (1 << k)) {
6303 "vlan number doesn't match");
6304 return I40E_ERR_PARAM;
6306 rte_memcpy(&mv_f[i].macaddr,
6307 addr, ETH_ADDR_LEN);
6309 j * I40E_UINT32_BIT_SIZE + k;
6315 return I40E_SUCCESS;
6319 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6320 struct i40e_macvlan_filter *mv_f,
6325 struct i40e_mac_filter *f;
6327 if (num < vsi->mac_num)
6328 return I40E_ERR_PARAM;
6330 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6332 PMD_DRV_LOG(ERR, "buffer number not match");
6333 return I40E_ERR_PARAM;
6335 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6337 mv_f[i].vlan_id = vlan;
6338 mv_f[i].filter_type = f->mac_info.filter_type;
6342 return I40E_SUCCESS;
6346 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6349 struct i40e_mac_filter *f;
6350 struct i40e_macvlan_filter *mv_f;
6351 int ret = I40E_SUCCESS;
6353 if (vsi == NULL || vsi->mac_num == 0)
6354 return I40E_ERR_PARAM;
6356 /* Case that no vlan is set */
6357 if (vsi->vlan_num == 0)
6360 num = vsi->mac_num * vsi->vlan_num;
6362 mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6364 PMD_DRV_LOG(ERR, "failed to allocate memory");
6365 return I40E_ERR_NO_MEMORY;
6369 if (vsi->vlan_num == 0) {
6370 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6371 rte_memcpy(&mv_f[i].macaddr,
6372 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6373 mv_f[i].filter_type = f->mac_info.filter_type;
6374 mv_f[i].vlan_id = 0;
6378 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6379 ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6380 vsi->vlan_num, &f->mac_info.mac_addr);
6381 if (ret != I40E_SUCCESS)
6383 for (j = i; j < i + vsi->vlan_num; j++)
6384 mv_f[j].filter_type = f->mac_info.filter_type;
6389 ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6397 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6399 struct i40e_macvlan_filter *mv_f;
6401 int ret = I40E_SUCCESS;
6403 if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6404 return I40E_ERR_PARAM;
6406 /* If it's already set, just return */
6407 if (i40e_find_vlan_filter(vsi,vlan))
6408 return I40E_SUCCESS;
6410 mac_num = vsi->mac_num;
6413 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6414 return I40E_ERR_PARAM;
6417 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6420 PMD_DRV_LOG(ERR, "failed to allocate memory");
6421 return I40E_ERR_NO_MEMORY;
6424 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6426 if (ret != I40E_SUCCESS)
6429 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6431 if (ret != I40E_SUCCESS)
6434 i40e_set_vlan_filter(vsi, vlan, 1);
6444 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6446 struct i40e_macvlan_filter *mv_f;
6448 int ret = I40E_SUCCESS;
6451 * Vlan 0 is the generic filter for untagged packets
6452 * and can't be removed.
6454 if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6455 return I40E_ERR_PARAM;
6457 /* If can't find it, just return */
6458 if (!i40e_find_vlan_filter(vsi, vlan))
6459 return I40E_ERR_PARAM;
6461 mac_num = vsi->mac_num;
6464 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6465 return I40E_ERR_PARAM;
6468 mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6471 PMD_DRV_LOG(ERR, "failed to allocate memory");
6472 return I40E_ERR_NO_MEMORY;
6475 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6477 if (ret != I40E_SUCCESS)
6480 ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6482 if (ret != I40E_SUCCESS)
6485 /* This is last vlan to remove, replace all mac filter with vlan 0 */
6486 if (vsi->vlan_num == 1) {
6487 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6488 if (ret != I40E_SUCCESS)
6491 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6492 if (ret != I40E_SUCCESS)
6496 i40e_set_vlan_filter(vsi, vlan, 0);
6506 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6508 struct i40e_mac_filter *f;
6509 struct i40e_macvlan_filter *mv_f;
6510 int i, vlan_num = 0;
6511 int ret = I40E_SUCCESS;
6513 /* If it's add and we've config it, return */
6514 f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6516 return I40E_SUCCESS;
6517 if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6518 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6521 * If vlan_num is 0, that's the first time to add mac,
6522 * set mask for vlan_id 0.
6524 if (vsi->vlan_num == 0) {
6525 i40e_set_vlan_filter(vsi, 0, 1);
6528 vlan_num = vsi->vlan_num;
6529 } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6530 (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6533 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6535 PMD_DRV_LOG(ERR, "failed to allocate memory");
6536 return I40E_ERR_NO_MEMORY;
6539 for (i = 0; i < vlan_num; i++) {
6540 mv_f[i].filter_type = mac_filter->filter_type;
6541 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6545 if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6546 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6547 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6548 &mac_filter->mac_addr);
6549 if (ret != I40E_SUCCESS)
6553 ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6554 if (ret != I40E_SUCCESS)
6557 /* Add the mac addr into mac list */
6558 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6560 PMD_DRV_LOG(ERR, "failed to allocate memory");
6561 ret = I40E_ERR_NO_MEMORY;
6564 rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6566 f->mac_info.filter_type = mac_filter->filter_type;
6567 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6578 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6580 struct i40e_mac_filter *f;
6581 struct i40e_macvlan_filter *mv_f;
6583 enum rte_mac_filter_type filter_type;
6584 int ret = I40E_SUCCESS;
6586 /* Can't find it, return an error */
6587 f = i40e_find_mac_filter(vsi, addr);
6589 return I40E_ERR_PARAM;
6591 vlan_num = vsi->vlan_num;
6592 filter_type = f->mac_info.filter_type;
6593 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6594 filter_type == RTE_MACVLAN_HASH_MATCH) {
6595 if (vlan_num == 0) {
6596 PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6597 return I40E_ERR_PARAM;
6599 } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6600 filter_type == RTE_MAC_HASH_MATCH)
6603 mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6605 PMD_DRV_LOG(ERR, "failed to allocate memory");
6606 return I40E_ERR_NO_MEMORY;
6609 for (i = 0; i < vlan_num; i++) {
6610 mv_f[i].filter_type = filter_type;
6611 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6614 if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6615 filter_type == RTE_MACVLAN_HASH_MATCH) {
6616 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6617 if (ret != I40E_SUCCESS)
6621 ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6622 if (ret != I40E_SUCCESS)
6625 /* Remove the mac addr into mac list */
6626 TAILQ_REMOVE(&vsi->mac_list, f, next);
6636 /* Configure hash enable flags for RSS */
6638 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
6646 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6647 if (flags & (1ULL << i))
6648 hena |= adapter->pctypes_tbl[i];
6654 /* Parse the hash enable flags */
6656 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
6658 uint64_t rss_hf = 0;
6664 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6665 if (flags & adapter->pctypes_tbl[i])
6666 rss_hf |= (1ULL << i);
6673 i40e_pf_disable_rss(struct i40e_pf *pf)
6675 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6677 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
6678 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
6679 I40E_WRITE_FLUSH(hw);
6683 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
6685 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6686 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6689 if (!key || key_len == 0) {
6690 PMD_DRV_LOG(DEBUG, "No key to be configured");
6692 } else if (key_len != (I40E_PFQF_HKEY_MAX_INDEX + 1) *
6694 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
6698 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6699 struct i40e_aqc_get_set_rss_key_data *key_dw =
6700 (struct i40e_aqc_get_set_rss_key_data *)key;
6702 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
6704 PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
6706 uint32_t *hash_key = (uint32_t *)key;
6709 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6710 i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), hash_key[i]);
6711 I40E_WRITE_FLUSH(hw);
6718 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
6720 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
6721 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6724 if (!key || !key_len)
6727 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
6728 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
6729 (struct i40e_aqc_get_set_rss_key_data *)key);
6731 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
6735 uint32_t *key_dw = (uint32_t *)key;
6738 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
6739 key_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
6741 *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
6747 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
6749 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6753 ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
6754 rss_conf->rss_key_len);
6758 hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
6759 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
6760 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
6761 I40E_WRITE_FLUSH(hw);
6767 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
6768 struct rte_eth_rss_conf *rss_conf)
6770 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6771 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6772 uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
6775 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6776 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6778 if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
6779 if (rss_hf != 0) /* Enable RSS */
6781 return 0; /* Nothing to do */
6784 if (rss_hf == 0) /* Disable RSS */
6787 return i40e_hw_rss_hash_set(pf, rss_conf);
6791 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
6792 struct rte_eth_rss_conf *rss_conf)
6794 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6795 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6798 i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
6799 &rss_conf->rss_key_len);
6801 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
6802 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
6803 rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
6809 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
6811 switch (filter_type) {
6812 case RTE_TUNNEL_FILTER_IMAC_IVLAN:
6813 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
6815 case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
6816 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
6818 case RTE_TUNNEL_FILTER_IMAC_TENID:
6819 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
6821 case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
6822 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
6824 case ETH_TUNNEL_FILTER_IMAC:
6825 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
6827 case ETH_TUNNEL_FILTER_OIP:
6828 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
6830 case ETH_TUNNEL_FILTER_IIP:
6831 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
6834 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
6841 /* Convert tunnel filter structure */
6843 i40e_tunnel_filter_convert(
6844 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
6845 struct i40e_tunnel_filter *tunnel_filter)
6847 ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
6848 (struct ether_addr *)&tunnel_filter->input.outer_mac);
6849 ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
6850 (struct ether_addr *)&tunnel_filter->input.inner_mac);
6851 tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
6852 if ((rte_le_to_cpu_16(cld_filter->element.flags) &
6853 I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
6854 I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
6855 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
6857 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
6858 tunnel_filter->input.flags = cld_filter->element.flags;
6859 tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
6860 tunnel_filter->queue = cld_filter->element.queue_number;
6861 rte_memcpy(tunnel_filter->input.general_fields,
6862 cld_filter->general_fields,
6863 sizeof(cld_filter->general_fields));
6868 /* Check if there exists the tunnel filter */
6869 struct i40e_tunnel_filter *
6870 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
6871 const struct i40e_tunnel_filter_input *input)
6875 ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
6879 return tunnel_rule->hash_map[ret];
6882 /* Add a tunnel filter into the SW list */
6884 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
6885 struct i40e_tunnel_filter *tunnel_filter)
6887 struct i40e_tunnel_rule *rule = &pf->tunnel;
6890 ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
6893 "Failed to insert tunnel filter to hash table %d!",
6897 rule->hash_map[ret] = tunnel_filter;
6899 TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
6904 /* Delete a tunnel filter from the SW list */
6906 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
6907 struct i40e_tunnel_filter_input *input)
6909 struct i40e_tunnel_rule *rule = &pf->tunnel;
6910 struct i40e_tunnel_filter *tunnel_filter;
6913 ret = rte_hash_del_key(rule->hash_table, input);
6916 "Failed to delete tunnel filter to hash table %d!",
6920 tunnel_filter = rule->hash_map[ret];
6921 rule->hash_map[ret] = NULL;
6923 TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
6924 rte_free(tunnel_filter);
6930 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
6931 struct rte_eth_tunnel_filter_conf *tunnel_filter,
6935 uint32_t ipv4_addr, ipv4_addr_le;
6936 uint8_t i, tun_type = 0;
6937 /* internal varialbe to convert ipv6 byte order */
6938 uint32_t convert_ipv6[4];
6940 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6941 struct i40e_vsi *vsi = pf->main_vsi;
6942 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
6943 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
6944 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
6945 struct i40e_tunnel_filter *tunnel, *node;
6946 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
6948 cld_filter = rte_zmalloc("tunnel_filter",
6949 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
6952 if (NULL == cld_filter) {
6953 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
6956 pfilter = cld_filter;
6958 ether_addr_copy(&tunnel_filter->outer_mac,
6959 (struct ether_addr *)&pfilter->element.outer_mac);
6960 ether_addr_copy(&tunnel_filter->inner_mac,
6961 (struct ether_addr *)&pfilter->element.inner_mac);
6963 pfilter->element.inner_vlan =
6964 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
6965 if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
6966 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
6967 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
6968 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
6969 rte_memcpy(&pfilter->element.ipaddr.v4.data,
6971 sizeof(pfilter->element.ipaddr.v4.data));
6973 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
6974 for (i = 0; i < 4; i++) {
6976 rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
6978 rte_memcpy(&pfilter->element.ipaddr.v6.data,
6980 sizeof(pfilter->element.ipaddr.v6.data));
6983 /* check tunneled type */
6984 switch (tunnel_filter->tunnel_type) {
6985 case RTE_TUNNEL_TYPE_VXLAN:
6986 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
6988 case RTE_TUNNEL_TYPE_NVGRE:
6989 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
6991 case RTE_TUNNEL_TYPE_IP_IN_GRE:
6992 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
6995 /* Other tunnel types is not supported. */
6996 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
6997 rte_free(cld_filter);
7001 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7002 &pfilter->element.flags);
7004 rte_free(cld_filter);
7008 pfilter->element.flags |= rte_cpu_to_le_16(
7009 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7010 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7011 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7012 pfilter->element.queue_number =
7013 rte_cpu_to_le_16(tunnel_filter->queue_id);
7015 /* Check if there is the filter in SW list */
7016 memset(&check_filter, 0, sizeof(check_filter));
7017 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7018 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7020 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7024 if (!add && !node) {
7025 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7030 ret = i40e_aq_add_cloud_filters(hw,
7031 vsi->seid, &cld_filter->element, 1);
7033 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7036 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7037 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7038 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7040 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7041 &cld_filter->element, 1);
7043 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7046 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7049 rte_free(cld_filter);
7053 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7054 #define I40E_TR_VXLAN_GRE_KEY_MASK 0x4
7055 #define I40E_TR_GENEVE_KEY_MASK 0x8
7056 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK 0x40
7057 #define I40E_TR_GRE_KEY_MASK 0x400
7058 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK 0x800
7059 #define I40E_TR_GRE_NO_KEY_MASK 0x8000
7062 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7064 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7065 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7066 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7067 enum i40e_status_code status = I40E_SUCCESS;
7069 memset(&filter_replace, 0,
7070 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7071 memset(&filter_replace_buf, 0,
7072 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7074 /* create L1 filter */
7075 filter_replace.old_filter_type =
7076 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7077 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7078 filter_replace.tr_bit = 0;
7080 /* Prepare the buffer, 3 entries */
7081 filter_replace_buf.data[0] =
7082 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7083 filter_replace_buf.data[0] |=
7084 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7085 filter_replace_buf.data[2] = 0xFF;
7086 filter_replace_buf.data[3] = 0xFF;
7087 filter_replace_buf.data[4] =
7088 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7089 filter_replace_buf.data[4] |=
7090 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7091 filter_replace_buf.data[7] = 0xF0;
7092 filter_replace_buf.data[8]
7093 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7094 filter_replace_buf.data[8] |=
7095 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7096 filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7097 I40E_TR_GENEVE_KEY_MASK |
7098 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7099 filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7100 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7101 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7103 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7104 &filter_replace_buf);
7109 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7111 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7112 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7113 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7114 enum i40e_status_code status = I40E_SUCCESS;
7117 memset(&filter_replace, 0,
7118 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7119 memset(&filter_replace_buf, 0,
7120 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7121 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7122 I40E_AQC_MIRROR_CLOUD_FILTER;
7123 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7124 filter_replace.new_filter_type =
7125 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7126 /* Prepare the buffer, 2 entries */
7127 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7128 filter_replace_buf.data[0] |=
7129 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7130 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7131 filter_replace_buf.data[4] |=
7132 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7133 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7134 &filter_replace_buf);
7139 memset(&filter_replace, 0,
7140 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7141 memset(&filter_replace_buf, 0,
7142 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7144 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7145 I40E_AQC_MIRROR_CLOUD_FILTER;
7146 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7147 filter_replace.new_filter_type =
7148 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7149 /* Prepare the buffer, 2 entries */
7150 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7151 filter_replace_buf.data[0] |=
7152 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7153 filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7154 filter_replace_buf.data[4] |=
7155 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7157 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7158 &filter_replace_buf);
7162 static enum i40e_status_code
7163 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7165 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7166 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7167 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7168 enum i40e_status_code status = I40E_SUCCESS;
7171 memset(&filter_replace, 0,
7172 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7173 memset(&filter_replace_buf, 0,
7174 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7175 /* create L1 filter */
7176 filter_replace.old_filter_type =
7177 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7178 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7179 filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7180 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7181 /* Prepare the buffer, 2 entries */
7182 filter_replace_buf.data[0] =
7183 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7184 filter_replace_buf.data[0] |=
7185 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7186 filter_replace_buf.data[2] = 0xFF;
7187 filter_replace_buf.data[3] = 0xFF;
7188 filter_replace_buf.data[4] =
7189 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7190 filter_replace_buf.data[4] |=
7191 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7192 filter_replace_buf.data[6] = 0xFF;
7193 filter_replace_buf.data[7] = 0xFF;
7194 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7195 &filter_replace_buf);
7200 memset(&filter_replace, 0,
7201 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7202 memset(&filter_replace_buf, 0,
7203 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7204 /* create L1 filter */
7205 filter_replace.old_filter_type =
7206 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
7207 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
7208 filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
7209 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7210 /* Prepare the buffer, 2 entries */
7211 filter_replace_buf.data[0] =
7212 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7213 filter_replace_buf.data[0] |=
7214 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7215 filter_replace_buf.data[2] = 0xFF;
7216 filter_replace_buf.data[3] = 0xFF;
7217 filter_replace_buf.data[4] =
7218 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7219 filter_replace_buf.data[4] |=
7220 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7221 filter_replace_buf.data[6] = 0xFF;
7222 filter_replace_buf.data[7] = 0xFF;
7224 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7225 &filter_replace_buf);
7230 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
7232 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
7233 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
7234 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7235 enum i40e_status_code status = I40E_SUCCESS;
7238 memset(&filter_replace, 0,
7239 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7240 memset(&filter_replace_buf, 0,
7241 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7242 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7243 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7244 filter_replace.new_filter_type =
7245 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7246 /* Prepare the buffer, 2 entries */
7247 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
7248 filter_replace_buf.data[0] |=
7249 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7250 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7251 filter_replace_buf.data[4] |=
7252 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7253 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7254 &filter_replace_buf);
7259 memset(&filter_replace, 0,
7260 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7261 memset(&filter_replace_buf, 0,
7262 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7263 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7264 filter_replace.old_filter_type =
7265 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7266 filter_replace.new_filter_type =
7267 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7268 /* Prepare the buffer, 2 entries */
7269 filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
7270 filter_replace_buf.data[0] |=
7271 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7272 filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7273 filter_replace_buf.data[4] |=
7274 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7276 status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7277 &filter_replace_buf);
7282 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7283 struct i40e_tunnel_filter_conf *tunnel_filter,
7287 uint32_t ipv4_addr, ipv4_addr_le;
7288 uint8_t i, tun_type = 0;
7289 /* internal variable to convert ipv6 byte order */
7290 uint32_t convert_ipv6[4];
7292 struct i40e_pf_vf *vf = NULL;
7293 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7294 struct i40e_vsi *vsi;
7295 struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7296 struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7297 struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7298 struct i40e_tunnel_filter *tunnel, *node;
7299 struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7301 bool big_buffer = 0;
7303 cld_filter = rte_zmalloc("tunnel_filter",
7304 sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7307 if (cld_filter == NULL) {
7308 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7311 pfilter = cld_filter;
7313 ether_addr_copy(&tunnel_filter->outer_mac,
7314 (struct ether_addr *)&pfilter->element.outer_mac);
7315 ether_addr_copy(&tunnel_filter->inner_mac,
7316 (struct ether_addr *)&pfilter->element.inner_mac);
7318 pfilter->element.inner_vlan =
7319 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7320 if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7321 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7322 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7323 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7324 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7326 sizeof(pfilter->element.ipaddr.v4.data));
7328 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7329 for (i = 0; i < 4; i++) {
7331 rte_cpu_to_le_32(rte_be_to_cpu_32(
7332 tunnel_filter->ip_addr.ipv6_addr[i]));
7334 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7336 sizeof(pfilter->element.ipaddr.v6.data));
7339 /* check tunneled type */
7340 switch (tunnel_filter->tunnel_type) {
7341 case I40E_TUNNEL_TYPE_VXLAN:
7342 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7344 case I40E_TUNNEL_TYPE_NVGRE:
7345 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7347 case I40E_TUNNEL_TYPE_IP_IN_GRE:
7348 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7350 case I40E_TUNNEL_TYPE_MPLSoUDP:
7351 if (!pf->mpls_replace_flag) {
7352 i40e_replace_mpls_l1_filter(pf);
7353 i40e_replace_mpls_cloud_filter(pf);
7354 pf->mpls_replace_flag = 1;
7356 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7357 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7359 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7360 (teid_le & 0xF) << 12;
7361 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7364 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
7366 case I40E_TUNNEL_TYPE_MPLSoGRE:
7367 if (!pf->mpls_replace_flag) {
7368 i40e_replace_mpls_l1_filter(pf);
7369 i40e_replace_mpls_cloud_filter(pf);
7370 pf->mpls_replace_flag = 1;
7372 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7373 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7375 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7376 (teid_le & 0xF) << 12;
7377 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7380 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
7382 case I40E_TUNNEL_TYPE_GTPC:
7383 if (!pf->gtp_replace_flag) {
7384 i40e_replace_gtp_l1_filter(pf);
7385 i40e_replace_gtp_cloud_filter(pf);
7386 pf->gtp_replace_flag = 1;
7388 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7389 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
7390 (teid_le >> 16) & 0xFFFF;
7391 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
7393 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
7397 case I40E_TUNNEL_TYPE_GTPU:
7398 if (!pf->gtp_replace_flag) {
7399 i40e_replace_gtp_l1_filter(pf);
7400 i40e_replace_gtp_cloud_filter(pf);
7401 pf->gtp_replace_flag = 1;
7403 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7404 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
7405 (teid_le >> 16) & 0xFFFF;
7406 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
7408 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
7412 case I40E_TUNNEL_TYPE_QINQ:
7413 if (!pf->qinq_replace_flag) {
7414 ret = i40e_cloud_filter_qinq_create(pf);
7417 "QinQ tunnel filter already created.");
7418 pf->qinq_replace_flag = 1;
7420 /* Add in the General fields the values of
7421 * the Outer and Inner VLAN
7422 * Big Buffer should be set, see changes in
7423 * i40e_aq_add_cloud_filters
7425 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7426 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7430 /* Other tunnel types is not supported. */
7431 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7432 rte_free(cld_filter);
7436 if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7437 pfilter->element.flags =
7438 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7439 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7440 pfilter->element.flags =
7441 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7442 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
7443 pfilter->element.flags =
7444 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7445 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
7446 pfilter->element.flags =
7447 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7448 else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7449 pfilter->element.flags |=
7450 I40E_AQC_ADD_CLOUD_FILTER_0X10;
7452 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7453 &pfilter->element.flags);
7455 rte_free(cld_filter);
7460 pfilter->element.flags |= rte_cpu_to_le_16(
7461 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7462 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7463 pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7464 pfilter->element.queue_number =
7465 rte_cpu_to_le_16(tunnel_filter->queue_id);
7467 if (!tunnel_filter->is_to_vf)
7470 if (tunnel_filter->vf_id >= pf->vf_num) {
7471 PMD_DRV_LOG(ERR, "Invalid argument.");
7474 vf = &pf->vfs[tunnel_filter->vf_id];
7478 /* Check if there is the filter in SW list */
7479 memset(&check_filter, 0, sizeof(check_filter));
7480 i40e_tunnel_filter_convert(cld_filter, &check_filter);
7481 check_filter.is_to_vf = tunnel_filter->is_to_vf;
7482 check_filter.vf_id = tunnel_filter->vf_id;
7483 node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7485 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7489 if (!add && !node) {
7490 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7496 ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7497 vsi->seid, cld_filter, 1);
7499 ret = i40e_aq_add_cloud_filters(hw,
7500 vsi->seid, &cld_filter->element, 1);
7502 PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7505 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7506 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7507 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7510 ret = i40e_aq_remove_cloud_filters_big_buffer(
7511 hw, vsi->seid, cld_filter, 1);
7513 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7514 &cld_filter->element, 1);
7516 PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7519 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7522 rte_free(cld_filter);
7527 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7531 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7532 if (pf->vxlan_ports[i] == port)
7540 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7544 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7546 idx = i40e_get_vxlan_port_idx(pf, port);
7548 /* Check if port already exists */
7550 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7554 /* Now check if there is space to add the new port */
7555 idx = i40e_get_vxlan_port_idx(pf, 0);
7558 "Maximum number of UDP ports reached, not adding port %d",
7563 ret = i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
7566 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
7570 PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
7573 /* New port: add it and mark its index in the bitmap */
7574 pf->vxlan_ports[idx] = port;
7575 pf->vxlan_bitmap |= (1 << idx);
7577 if (!(pf->flags & I40E_FLAG_VXLAN))
7578 pf->flags |= I40E_FLAG_VXLAN;
7584 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
7587 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7589 if (!(pf->flags & I40E_FLAG_VXLAN)) {
7590 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
7594 idx = i40e_get_vxlan_port_idx(pf, port);
7597 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
7601 if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
7602 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
7606 PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
7609 pf->vxlan_ports[idx] = 0;
7610 pf->vxlan_bitmap &= ~(1 << idx);
7612 if (!pf->vxlan_bitmap)
7613 pf->flags &= ~I40E_FLAG_VXLAN;
7618 /* Add UDP tunneling port */
7620 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
7621 struct rte_eth_udp_tunnel *udp_tunnel)
7624 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7626 if (udp_tunnel == NULL)
7629 switch (udp_tunnel->prot_type) {
7630 case RTE_TUNNEL_TYPE_VXLAN:
7631 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
7634 case RTE_TUNNEL_TYPE_GENEVE:
7635 case RTE_TUNNEL_TYPE_TEREDO:
7636 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7641 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7649 /* Remove UDP tunneling port */
7651 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
7652 struct rte_eth_udp_tunnel *udp_tunnel)
7655 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7657 if (udp_tunnel == NULL)
7660 switch (udp_tunnel->prot_type) {
7661 case RTE_TUNNEL_TYPE_VXLAN:
7662 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
7664 case RTE_TUNNEL_TYPE_GENEVE:
7665 case RTE_TUNNEL_TYPE_TEREDO:
7666 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
7670 PMD_DRV_LOG(ERR, "Invalid tunnel type");
7678 /* Calculate the maximum number of contiguous PF queues that are configured */
7680 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
7682 struct rte_eth_dev_data *data = pf->dev_data;
7684 struct i40e_rx_queue *rxq;
7687 for (i = 0; i < pf->lan_nb_qps; i++) {
7688 rxq = data->rx_queues[i];
7689 if (rxq && rxq->q_set)
7700 i40e_pf_config_rss(struct i40e_pf *pf)
7702 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7703 struct rte_eth_rss_conf rss_conf;
7704 uint32_t i, lut = 0;
7708 * If both VMDQ and RSS enabled, not all of PF queues are configured.
7709 * It's necessary to calculate the actual PF queues that are configured.
7711 if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
7712 num = i40e_pf_calc_configured_queues_num(pf);
7714 num = pf->dev_data->nb_rx_queues;
7716 num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
7717 PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
7721 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
7725 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
7728 lut = (lut << 8) | (j & ((0x1 <<
7729 hw->func_caps.rss_table_entry_width) - 1));
7731 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
7734 rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
7735 if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
7736 i40e_pf_disable_rss(pf);
7739 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
7740 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
7741 /* Random default keys */
7742 static uint32_t rss_key_default[] = {0x6b793944,
7743 0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
7744 0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
7745 0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
7747 rss_conf.rss_key = (uint8_t *)rss_key_default;
7748 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7752 return i40e_hw_rss_hash_set(pf, &rss_conf);
7756 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
7757 struct rte_eth_tunnel_filter_conf *filter)
7759 if (pf == NULL || filter == NULL) {
7760 PMD_DRV_LOG(ERR, "Invalid parameter");
7764 if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
7765 PMD_DRV_LOG(ERR, "Invalid queue ID");
7769 if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
7770 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
7774 if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
7775 (is_zero_ether_addr(&filter->outer_mac))) {
7776 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
7780 if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
7781 (is_zero_ether_addr(&filter->inner_mac))) {
7782 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
7789 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
7790 #define I40E_GL_PRS_FVBM(_i) (0x00269760 + ((_i) * 4))
7792 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
7797 val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
7798 PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
7801 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
7802 } else if (len == 4) {
7803 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
7805 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
7810 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
7817 PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
7818 I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
7824 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
7831 switch (cfg->cfg_type) {
7832 case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
7833 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
7836 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
7844 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
7845 enum rte_filter_op filter_op,
7848 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7849 int ret = I40E_ERR_PARAM;
7851 switch (filter_op) {
7852 case RTE_ETH_FILTER_SET:
7853 ret = i40e_dev_global_config_set(hw,
7854 (struct rte_eth_global_cfg *)arg);
7857 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7865 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
7866 enum rte_filter_op filter_op,
7869 struct rte_eth_tunnel_filter_conf *filter;
7870 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7871 int ret = I40E_SUCCESS;
7873 filter = (struct rte_eth_tunnel_filter_conf *)(arg);
7875 if (i40e_tunnel_filter_param_check(pf, filter) < 0)
7876 return I40E_ERR_PARAM;
7878 switch (filter_op) {
7879 case RTE_ETH_FILTER_NOP:
7880 if (!(pf->flags & I40E_FLAG_VXLAN))
7881 ret = I40E_NOT_SUPPORTED;
7883 case RTE_ETH_FILTER_ADD:
7884 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
7886 case RTE_ETH_FILTER_DELETE:
7887 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
7890 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
7891 ret = I40E_ERR_PARAM;
7899 i40e_pf_config_mq_rx(struct i40e_pf *pf)
7902 enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
7905 if (mq_mode & ETH_MQ_RX_RSS_FLAG)
7906 ret = i40e_pf_config_rss(pf);
7908 i40e_pf_disable_rss(pf);
7913 /* Get the symmetric hash enable configurations per port */
7915 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
7917 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7919 *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
7922 /* Set the symmetric hash enable configurations per port */
7924 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
7926 uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
7929 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
7931 "Symmetric hash has already been enabled");
7934 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7936 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
7938 "Symmetric hash has already been disabled");
7941 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
7943 i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
7944 I40E_WRITE_FLUSH(hw);
7948 * Get global configurations of hash function type and symmetric hash enable
7949 * per flow type (pctype). Note that global configuration means it affects all
7950 * the ports on the same NIC.
7953 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
7954 struct rte_eth_hash_global_conf *g_cfg)
7956 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
7960 memset(g_cfg, 0, sizeof(*g_cfg));
7961 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
7962 if (reg & I40E_GLQF_CTL_HTOEP_MASK)
7963 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
7965 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
7966 PMD_DRV_LOG(DEBUG, "Hash function is %s",
7967 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
7970 * We work only with lowest 32 bits which is not correct, but to work
7971 * properly the valid_bit_mask size should be increased up to 64 bits
7972 * and this will brake ABI. This modification will be done in next
7975 g_cfg->valid_bit_mask[0] = (uint32_t)adapter->flow_types_mask;
7977 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT32_BIT; i++) {
7978 if (!adapter->pctypes_tbl[i])
7980 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
7981 j < I40E_FILTER_PCTYPE_MAX; j++) {
7982 if (adapter->pctypes_tbl[i] & (1ULL << j)) {
7983 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
7984 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
7985 g_cfg->sym_hash_enable_mask[0] |=
7996 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
7997 const struct rte_eth_hash_global_conf *g_cfg)
8000 uint32_t mask0, i40e_mask = adapter->flow_types_mask;
8002 if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8003 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8004 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8005 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8011 * As i40e supports less than 32 flow types, only first 32 bits need to
8014 mask0 = g_cfg->valid_bit_mask[0];
8015 for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8017 /* Check if any unsupported flow type configured */
8018 if ((mask0 | i40e_mask) ^ i40e_mask)
8021 if (g_cfg->valid_bit_mask[i])
8029 PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8035 * Set global configurations of hash function type and symmetric hash enable
8036 * per flow type (pctype). Note any modifying global configuration will affect
8037 * all the ports on the same NIC.
8040 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8041 struct rte_eth_hash_global_conf *g_cfg)
8043 struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8048 * We work only with lowest 32 bits which is not correct, but to work
8049 * properly the valid_bit_mask size should be increased up to 64 bits
8050 * and this will brake ABI. This modification will be done in next
8053 uint32_t mask0 = g_cfg->valid_bit_mask[0] &
8054 (uint32_t)adapter->flow_types_mask;
8056 /* Check the input parameters */
8057 ret = i40e_hash_global_config_check(adapter, g_cfg);
8061 for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT32_BIT; i++) {
8062 if (mask0 & (1UL << i)) {
8063 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
8064 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8066 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8067 j < I40E_FILTER_PCTYPE_MAX; j++) {
8068 if (adapter->pctypes_tbl[i] & (1ULL << j))
8069 i40e_write_rx_ctl(hw,
8076 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8077 if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8079 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8081 "Hash function already set to Toeplitz");
8084 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8085 } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8087 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8089 "Hash function already set to Simple XOR");
8092 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8094 /* Use the default, and keep it as it is */
8097 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
8100 I40E_WRITE_FLUSH(hw);
8106 * Valid input sets for hash and flow director filters per PCTYPE
8109 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8110 enum rte_filter_type filter)
8114 static const uint64_t valid_hash_inset_table[] = {
8115 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8116 I40E_INSET_DMAC | I40E_INSET_SMAC |
8117 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8118 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8119 I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8120 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8121 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8122 I40E_INSET_FLEX_PAYLOAD,
8123 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8124 I40E_INSET_DMAC | I40E_INSET_SMAC |
8125 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8126 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8127 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8128 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8129 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8130 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8131 I40E_INSET_FLEX_PAYLOAD,
8132 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8133 I40E_INSET_DMAC | I40E_INSET_SMAC |
8134 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8135 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8136 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8137 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8138 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8139 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8140 I40E_INSET_FLEX_PAYLOAD,
8141 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8142 I40E_INSET_DMAC | I40E_INSET_SMAC |
8143 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8144 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8145 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8146 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8147 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8148 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8149 I40E_INSET_FLEX_PAYLOAD,
8150 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8151 I40E_INSET_DMAC | I40E_INSET_SMAC |
8152 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8153 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8154 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8155 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8156 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8157 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8158 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8159 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8160 I40E_INSET_DMAC | I40E_INSET_SMAC |
8161 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8162 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8163 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8164 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8165 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8166 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8167 I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8168 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8169 I40E_INSET_DMAC | I40E_INSET_SMAC |
8170 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8171 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8172 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8173 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8174 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8175 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8176 I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8177 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8178 I40E_INSET_DMAC | I40E_INSET_SMAC |
8179 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8180 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8181 I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8182 I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8183 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8184 I40E_INSET_FLEX_PAYLOAD,
8185 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8186 I40E_INSET_DMAC | I40E_INSET_SMAC |
8187 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8188 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8189 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8190 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8191 I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8192 I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8193 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8194 I40E_INSET_DMAC | I40E_INSET_SMAC |
8195 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8196 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8197 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8198 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8199 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8200 I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8201 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8202 I40E_INSET_DMAC | I40E_INSET_SMAC |
8203 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8204 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8205 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8206 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8207 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8208 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8209 I40E_INSET_FLEX_PAYLOAD,
8210 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8211 I40E_INSET_DMAC | I40E_INSET_SMAC |
8212 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8213 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8214 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8215 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8216 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8217 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8218 I40E_INSET_FLEX_PAYLOAD,
8219 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8220 I40E_INSET_DMAC | I40E_INSET_SMAC |
8221 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8222 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8223 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8224 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8225 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8226 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8227 I40E_INSET_FLEX_PAYLOAD,
8228 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8229 I40E_INSET_DMAC | I40E_INSET_SMAC |
8230 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8231 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8232 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8233 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8234 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8235 I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8236 I40E_INSET_FLEX_PAYLOAD,
8237 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8238 I40E_INSET_DMAC | I40E_INSET_SMAC |
8239 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8240 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8241 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8242 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8243 I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8244 I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8245 I40E_INSET_FLEX_PAYLOAD,
8246 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8247 I40E_INSET_DMAC | I40E_INSET_SMAC |
8248 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8249 I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8250 I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8251 I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8252 I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8253 I40E_INSET_FLEX_PAYLOAD,
8254 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8255 I40E_INSET_DMAC | I40E_INSET_SMAC |
8256 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8257 I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8258 I40E_INSET_FLEX_PAYLOAD,
8262 * Flow director supports only fields defined in
8263 * union rte_eth_fdir_flow.
8265 static const uint64_t valid_fdir_inset_table[] = {
8266 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8267 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8268 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8269 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8270 I40E_INSET_IPV4_TTL,
8271 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8272 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8273 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8274 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8275 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8276 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8277 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8278 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8279 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8280 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8281 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8282 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8283 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8284 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8285 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8286 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8287 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8288 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8289 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8290 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8291 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8292 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8293 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8294 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8295 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8296 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8297 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8298 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8299 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8300 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8302 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8303 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8304 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8305 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8306 I40E_INSET_IPV4_TTL,
8307 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8308 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8309 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8310 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8311 I40E_INSET_IPV6_HOP_LIMIT,
8312 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8313 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8314 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8315 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8316 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8317 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8318 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8319 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8320 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8321 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8322 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8323 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8324 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8325 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8326 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8327 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8328 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8329 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8330 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8331 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8332 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8333 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8334 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8335 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8336 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8337 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8338 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8339 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8340 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8341 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8343 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8344 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8345 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8346 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8347 I40E_INSET_IPV6_HOP_LIMIT,
8348 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8349 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8350 I40E_INSET_LAST_ETHER_TYPE,
8353 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8355 if (filter == RTE_ETH_FILTER_HASH)
8356 valid = valid_hash_inset_table[pctype];
8358 valid = valid_fdir_inset_table[pctype];
8364 * Validate if the input set is allowed for a specific PCTYPE
8367 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8368 enum rte_filter_type filter, uint64_t inset)
8372 valid = i40e_get_valid_input_set(pctype, filter);
8373 if (inset & (~valid))
8379 /* default input set fields combination per pctype */
8381 i40e_get_default_input_set(uint16_t pctype)
8383 static const uint64_t default_inset_table[] = {
8384 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8385 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8386 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8387 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8388 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8389 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8390 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8391 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8392 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8393 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8394 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8395 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8396 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8397 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8398 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8399 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8400 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8401 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8402 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8403 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8405 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8406 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8407 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8408 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8409 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8410 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8411 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8412 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8413 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8414 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8415 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8416 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8417 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8418 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8419 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8420 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8421 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8422 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8423 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8424 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8425 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8426 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8428 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8429 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8430 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8431 I40E_INSET_LAST_ETHER_TYPE,
8434 if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8437 return default_inset_table[pctype];
8441 * Parse the input set from index to logical bit masks
8444 i40e_parse_input_set(uint64_t *inset,
8445 enum i40e_filter_pctype pctype,
8446 enum rte_eth_input_set_field *field,
8452 static const struct {
8453 enum rte_eth_input_set_field field;
8455 } inset_convert_table[] = {
8456 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8457 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8458 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8459 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8460 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8461 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8462 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8463 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8464 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8465 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8466 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8467 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8468 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8469 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8470 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8471 I40E_INSET_IPV6_NEXT_HDR},
8472 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8473 I40E_INSET_IPV6_HOP_LIMIT},
8474 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8475 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8476 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8477 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8478 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8479 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8480 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8481 I40E_INSET_SCTP_VT},
8482 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8483 I40E_INSET_TUNNEL_DMAC},
8484 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8485 I40E_INSET_VLAN_TUNNEL},
8486 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8487 I40E_INSET_TUNNEL_ID},
8488 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8489 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8490 I40E_INSET_FLEX_PAYLOAD_W1},
8491 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8492 I40E_INSET_FLEX_PAYLOAD_W2},
8493 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8494 I40E_INSET_FLEX_PAYLOAD_W3},
8495 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8496 I40E_INSET_FLEX_PAYLOAD_W4},
8497 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8498 I40E_INSET_FLEX_PAYLOAD_W5},
8499 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8500 I40E_INSET_FLEX_PAYLOAD_W6},
8501 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8502 I40E_INSET_FLEX_PAYLOAD_W7},
8503 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8504 I40E_INSET_FLEX_PAYLOAD_W8},
8507 if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8510 /* Only one item allowed for default or all */
8512 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8513 *inset = i40e_get_default_input_set(pctype);
8515 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8516 *inset = I40E_INSET_NONE;
8521 for (i = 0, *inset = 0; i < size; i++) {
8522 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8523 if (field[i] == inset_convert_table[j].field) {
8524 *inset |= inset_convert_table[j].inset;
8529 /* It contains unsupported input set, return immediately */
8530 if (j == RTE_DIM(inset_convert_table))
8538 * Translate the input set from bit masks to register aware bit masks
8542 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
8552 static const struct inset_map inset_map_common[] = {
8553 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
8554 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
8555 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
8556 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
8557 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
8558 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
8559 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
8560 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
8561 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
8562 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
8563 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
8564 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
8565 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
8566 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
8567 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
8568 {I40E_INSET_TUNNEL_DMAC,
8569 I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
8570 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
8571 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
8572 {I40E_INSET_TUNNEL_SRC_PORT,
8573 I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
8574 {I40E_INSET_TUNNEL_DST_PORT,
8575 I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
8576 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
8577 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
8578 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
8579 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
8580 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
8581 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
8582 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
8583 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
8584 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
8587 /* some different registers map in x722*/
8588 static const struct inset_map inset_map_diff_x722[] = {
8589 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
8590 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
8591 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
8592 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
8595 static const struct inset_map inset_map_diff_not_x722[] = {
8596 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
8597 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
8598 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
8599 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
8605 /* Translate input set to register aware inset */
8606 if (type == I40E_MAC_X722) {
8607 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
8608 if (input & inset_map_diff_x722[i].inset)
8609 val |= inset_map_diff_x722[i].inset_reg;
8612 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
8613 if (input & inset_map_diff_not_x722[i].inset)
8614 val |= inset_map_diff_not_x722[i].inset_reg;
8618 for (i = 0; i < RTE_DIM(inset_map_common); i++) {
8619 if (input & inset_map_common[i].inset)
8620 val |= inset_map_common[i].inset_reg;
8627 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
8630 uint64_t inset_need_mask = inset;
8632 static const struct {
8635 } inset_mask_map[] = {
8636 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
8637 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
8638 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
8639 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
8640 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
8641 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
8642 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
8643 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
8646 if (!inset || !mask || !nb_elem)
8649 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8650 /* Clear the inset bit, if no MASK is required,
8651 * for example proto + ttl
8653 if ((inset & inset_mask_map[i].inset) ==
8654 inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
8655 inset_need_mask &= ~inset_mask_map[i].inset;
8656 if (!inset_need_mask)
8659 for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
8660 if ((inset_need_mask & inset_mask_map[i].inset) ==
8661 inset_mask_map[i].inset) {
8662 if (idx >= nb_elem) {
8663 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
8666 mask[idx] = inset_mask_map[i].mask;
8675 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
8677 uint32_t reg = i40e_read_rx_ctl(hw, addr);
8679 PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
8681 i40e_write_rx_ctl(hw, addr, val);
8682 PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
8683 (uint32_t)i40e_read_rx_ctl(hw, addr));
8687 i40e_filter_input_set_init(struct i40e_pf *pf)
8689 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8690 enum i40e_filter_pctype pctype;
8691 uint64_t input_set, inset_reg;
8692 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8696 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
8697 pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
8698 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
8700 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
8703 input_set = i40e_get_default_input_set(pctype);
8705 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8706 I40E_INSET_MASK_NUM_REG);
8709 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
8712 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8713 (uint32_t)(inset_reg & UINT32_MAX));
8714 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8715 (uint32_t)((inset_reg >>
8716 I40E_32_BIT_WIDTH) & UINT32_MAX));
8717 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8718 (uint32_t)(inset_reg & UINT32_MAX));
8719 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8720 (uint32_t)((inset_reg >>
8721 I40E_32_BIT_WIDTH) & UINT32_MAX));
8723 for (i = 0; i < num; i++) {
8724 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8726 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8729 /*clear unused mask registers of the pctype */
8730 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
8731 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8733 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8736 I40E_WRITE_FLUSH(hw);
8738 /* store the default input set */
8739 pf->hash_input_set[pctype] = input_set;
8740 pf->fdir.input_set[pctype] = input_set;
8745 i40e_hash_filter_inset_select(struct i40e_hw *hw,
8746 struct rte_eth_input_set_conf *conf)
8748 struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8749 enum i40e_filter_pctype pctype;
8750 uint64_t input_set, inset_reg = 0;
8751 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8755 PMD_DRV_LOG(ERR, "Invalid pointer");
8758 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8759 conf->op != RTE_ETH_INPUT_SET_ADD) {
8760 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8764 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
8765 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
8766 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8770 if (hw->mac.type == I40E_MAC_X722) {
8771 /* get translated pctype value in fd pctype register */
8772 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
8773 I40E_GLQF_FD_PCTYPES((int)pctype));
8776 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8779 PMD_DRV_LOG(ERR, "Failed to parse input set");
8783 if (conf->op == RTE_ETH_INPUT_SET_ADD) {
8784 /* get inset value in register */
8785 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
8786 inset_reg <<= I40E_32_BIT_WIDTH;
8787 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
8788 input_set |= pf->hash_input_set[pctype];
8790 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8791 I40E_INSET_MASK_NUM_REG);
8795 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8797 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
8798 (uint32_t)(inset_reg & UINT32_MAX));
8799 i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
8800 (uint32_t)((inset_reg >>
8801 I40E_32_BIT_WIDTH) & UINT32_MAX));
8803 for (i = 0; i < num; i++)
8804 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8806 /*clear unused mask registers of the pctype */
8807 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8808 i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
8810 I40E_WRITE_FLUSH(hw);
8812 pf->hash_input_set[pctype] = input_set;
8817 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
8818 struct rte_eth_input_set_conf *conf)
8820 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8821 enum i40e_filter_pctype pctype;
8822 uint64_t input_set, inset_reg = 0;
8823 uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
8827 PMD_DRV_LOG(ERR, "Invalid pointer");
8830 if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
8831 conf->op != RTE_ETH_INPUT_SET_ADD) {
8832 PMD_DRV_LOG(ERR, "Unsupported input set operation");
8836 pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
8838 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
8839 PMD_DRV_LOG(ERR, "invalid flow_type input.");
8843 ret = i40e_parse_input_set(&input_set, pctype, conf->field,
8846 PMD_DRV_LOG(ERR, "Failed to parse input set");
8850 /* get inset value in register */
8851 inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
8852 inset_reg <<= I40E_32_BIT_WIDTH;
8853 inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
8855 /* Can not change the inset reg for flex payload for fdir,
8856 * it is done by writing I40E_PRTQF_FD_FLXINSET
8857 * in i40e_set_flex_mask_on_pctype.
8859 if (conf->op == RTE_ETH_INPUT_SET_SELECT)
8860 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
8862 input_set |= pf->fdir.input_set[pctype];
8863 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
8864 I40E_INSET_MASK_NUM_REG);
8868 inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
8870 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
8871 (uint32_t)(inset_reg & UINT32_MAX));
8872 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
8873 (uint32_t)((inset_reg >>
8874 I40E_32_BIT_WIDTH) & UINT32_MAX));
8876 for (i = 0; i < num; i++)
8877 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8879 /*clear unused mask registers of the pctype */
8880 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
8881 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
8883 I40E_WRITE_FLUSH(hw);
8885 pf->fdir.input_set[pctype] = input_set;
8890 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8895 PMD_DRV_LOG(ERR, "Invalid pointer");
8899 switch (info->info_type) {
8900 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8901 i40e_get_symmetric_hash_enable_per_port(hw,
8902 &(info->info.enable));
8904 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8905 ret = i40e_get_hash_filter_global_config(hw,
8906 &(info->info.global_conf));
8909 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8919 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
8924 PMD_DRV_LOG(ERR, "Invalid pointer");
8928 switch (info->info_type) {
8929 case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
8930 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
8932 case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
8933 ret = i40e_set_hash_filter_global_config(hw,
8934 &(info->info.global_conf));
8936 case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
8937 ret = i40e_hash_filter_inset_select(hw,
8938 &(info->info.input_set_conf));
8942 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
8951 /* Operations for hash function */
8953 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
8954 enum rte_filter_op filter_op,
8957 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8960 switch (filter_op) {
8961 case RTE_ETH_FILTER_NOP:
8963 case RTE_ETH_FILTER_GET:
8964 ret = i40e_hash_filter_get(hw,
8965 (struct rte_eth_hash_filter_info *)arg);
8967 case RTE_ETH_FILTER_SET:
8968 ret = i40e_hash_filter_set(hw,
8969 (struct rte_eth_hash_filter_info *)arg);
8972 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
8981 /* Convert ethertype filter structure */
8983 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
8984 struct i40e_ethertype_filter *filter)
8986 rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
8987 filter->input.ether_type = input->ether_type;
8988 filter->flags = input->flags;
8989 filter->queue = input->queue;
8994 /* Check if there exists the ehtertype filter */
8995 struct i40e_ethertype_filter *
8996 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
8997 const struct i40e_ethertype_filter_input *input)
9001 ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9005 return ethertype_rule->hash_map[ret];
9008 /* Add ethertype filter in SW list */
9010 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9011 struct i40e_ethertype_filter *filter)
9013 struct i40e_ethertype_rule *rule = &pf->ethertype;
9016 ret = rte_hash_add_key(rule->hash_table, &filter->input);
9019 "Failed to insert ethertype filter"
9020 " to hash table %d!",
9024 rule->hash_map[ret] = filter;
9026 TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9031 /* Delete ethertype filter in SW list */
9033 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9034 struct i40e_ethertype_filter_input *input)
9036 struct i40e_ethertype_rule *rule = &pf->ethertype;
9037 struct i40e_ethertype_filter *filter;
9040 ret = rte_hash_del_key(rule->hash_table, input);
9043 "Failed to delete ethertype filter"
9044 " to hash table %d!",
9048 filter = rule->hash_map[ret];
9049 rule->hash_map[ret] = NULL;
9051 TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9058 * Configure ethertype filter, which can director packet by filtering
9059 * with mac address and ether_type or only ether_type
9062 i40e_ethertype_filter_set(struct i40e_pf *pf,
9063 struct rte_eth_ethertype_filter *filter,
9066 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9067 struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9068 struct i40e_ethertype_filter *ethertype_filter, *node;
9069 struct i40e_ethertype_filter check_filter;
9070 struct i40e_control_filter_stats stats;
9074 if (filter->queue >= pf->dev_data->nb_rx_queues) {
9075 PMD_DRV_LOG(ERR, "Invalid queue ID");
9078 if (filter->ether_type == ETHER_TYPE_IPv4 ||
9079 filter->ether_type == ETHER_TYPE_IPv6) {
9081 "unsupported ether_type(0x%04x) in control packet filter.",
9082 filter->ether_type);
9085 if (filter->ether_type == ETHER_TYPE_VLAN)
9086 PMD_DRV_LOG(WARNING,
9087 "filter vlan ether_type in first tag is not supported.");
9089 /* Check if there is the filter in SW list */
9090 memset(&check_filter, 0, sizeof(check_filter));
9091 i40e_ethertype_filter_convert(filter, &check_filter);
9092 node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9093 &check_filter.input);
9095 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9099 if (!add && !node) {
9100 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9104 if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9105 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9106 if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9107 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9108 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9110 memset(&stats, 0, sizeof(stats));
9111 ret = i40e_aq_add_rem_control_packet_filter(hw,
9112 filter->mac_addr.addr_bytes,
9113 filter->ether_type, flags,
9115 filter->queue, add, &stats, NULL);
9118 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9119 ret, stats.mac_etype_used, stats.etype_used,
9120 stats.mac_etype_free, stats.etype_free);
9124 /* Add or delete a filter in SW list */
9126 ethertype_filter = rte_zmalloc("ethertype_filter",
9127 sizeof(*ethertype_filter), 0);
9128 rte_memcpy(ethertype_filter, &check_filter,
9129 sizeof(check_filter));
9130 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9132 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9139 * Handle operations for ethertype filter.
9142 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9143 enum rte_filter_op filter_op,
9146 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9149 if (filter_op == RTE_ETH_FILTER_NOP)
9153 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9158 switch (filter_op) {
9159 case RTE_ETH_FILTER_ADD:
9160 ret = i40e_ethertype_filter_set(pf,
9161 (struct rte_eth_ethertype_filter *)arg,
9164 case RTE_ETH_FILTER_DELETE:
9165 ret = i40e_ethertype_filter_set(pf,
9166 (struct rte_eth_ethertype_filter *)arg,
9170 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9178 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9179 enum rte_filter_type filter_type,
9180 enum rte_filter_op filter_op,
9188 switch (filter_type) {
9189 case RTE_ETH_FILTER_NONE:
9190 /* For global configuration */
9191 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9193 case RTE_ETH_FILTER_HASH:
9194 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9196 case RTE_ETH_FILTER_MACVLAN:
9197 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9199 case RTE_ETH_FILTER_ETHERTYPE:
9200 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9202 case RTE_ETH_FILTER_TUNNEL:
9203 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9205 case RTE_ETH_FILTER_FDIR:
9206 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9208 case RTE_ETH_FILTER_GENERIC:
9209 if (filter_op != RTE_ETH_FILTER_GET)
9211 *(const void **)arg = &i40e_flow_ops;
9214 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9224 * Check and enable Extended Tag.
9225 * Enabling Extended Tag is important for 40G performance.
9228 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9230 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9234 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9237 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9241 if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9242 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9247 ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9250 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9254 if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9255 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9258 buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9259 ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9262 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9269 * As some registers wouldn't be reset unless a global hardware reset,
9270 * hardware initialization is needed to put those registers into an
9271 * expected initial state.
9274 i40e_hw_init(struct rte_eth_dev *dev)
9276 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9278 i40e_enable_extended_tag(dev);
9280 /* clear the PF Queue Filter control register */
9281 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9283 /* Disable symmetric hash per port */
9284 i40e_set_symmetric_hash_enable_per_port(hw, 0);
9288 * For X722 it is possible to have multiple pctypes mapped to the same flowtype
9289 * however this function will return only one highest pctype index,
9290 * which is not quite correct. This is known problem of i40e driver
9291 * and needs to be fixed later.
9293 enum i40e_filter_pctype
9294 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
9297 uint64_t pctype_mask;
9299 if (flow_type < I40E_FLOW_TYPE_MAX) {
9300 pctype_mask = adapter->pctypes_tbl[flow_type];
9301 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
9302 if (pctype_mask & (1ULL << i))
9303 return (enum i40e_filter_pctype)i;
9306 return I40E_FILTER_PCTYPE_INVALID;
9310 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
9311 enum i40e_filter_pctype pctype)
9314 uint64_t pctype_mask = 1ULL << pctype;
9316 for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
9318 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
9322 return RTE_ETH_FLOW_UNKNOWN;
9326 * On X710, performance number is far from the expectation on recent firmware
9327 * versions; on XL710, performance number is also far from the expectation on
9328 * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9329 * mode is enabled and port MAC address is equal to the packet destination MAC
9330 * address. The fix for this issue may not be integrated in the following
9331 * firmware version. So the workaround in software driver is needed. It needs
9332 * to modify the initial values of 3 internal only registers for both X710 and
9333 * XL710. Note that the values for X710 or XL710 could be different, and the
9334 * workaround can be removed when it is fixed in firmware in the future.
9337 /* For both X710 and XL710 */
9338 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1 0x10000200
9339 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2 0x203F0200
9340 #define I40E_GL_SWR_PRI_JOIN_MAP_0 0x26CE00
9342 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9343 #define I40E_GL_SWR_PRI_JOIN_MAP_2 0x26CE08
9346 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9347 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9350 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE 0x03030303
9352 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE 0x06060606
9353 #define I40E_GL_SWR_PM_UP_THR 0x269FBC
9356 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9358 enum i40e_status_code status;
9359 struct i40e_aq_get_phy_abilities_resp phy_ab;
9363 status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9367 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
9370 rte_delay_us(100000);
9372 status = i40e_aq_get_phy_capabilities(hw, false,
9373 true, &phy_ab, NULL);
9381 i40e_configure_registers(struct i40e_hw *hw)
9387 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9388 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9389 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9395 for (i = 0; i < RTE_DIM(reg_table); i++) {
9396 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9397 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9399 I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9400 else /* For X710/XL710/XXV710 */
9401 if (hw->aq.fw_maj_ver < 6)
9403 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
9406 I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
9409 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9410 if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9412 I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9413 else /* For X710/XL710/XXV710 */
9415 I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9418 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9419 if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9420 I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9422 I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9425 I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9428 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9431 PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9435 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9436 reg_table[i].addr, reg);
9437 if (reg == reg_table[i].val)
9440 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9441 reg_table[i].val, NULL);
9444 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9445 reg_table[i].val, reg_table[i].addr);
9448 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9449 "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9453 #define I40E_VSI_TSR(_i) (0x00050800 + ((_i) * 4))
9454 #define I40E_VSI_TSR_QINQ_CONFIG 0xc030
9455 #define I40E_VSI_L2TAGSTXVALID(_i) (0x00042800 + ((_i) * 4))
9456 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9458 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9463 if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9464 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9468 /* Configure for double VLAN RX stripping */
9469 reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9470 if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9471 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9472 ret = i40e_aq_debug_write_register(hw,
9473 I40E_VSI_TSR(vsi->vsi_id),
9476 PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9478 return I40E_ERR_CONFIG;
9482 /* Configure for double VLAN TX insertion */
9483 reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
9484 if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
9485 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
9486 ret = i40e_aq_debug_write_register(hw,
9487 I40E_VSI_L2TAGSTXVALID(
9488 vsi->vsi_id), reg, NULL);
9491 "Failed to update VSI_L2TAGSTXVALID[%d]",
9493 return I40E_ERR_CONFIG;
9501 * i40e_aq_add_mirror_rule
9502 * @hw: pointer to the hardware structure
9503 * @seid: VEB seid to add mirror rule to
9504 * @dst_id: destination vsi seid
9505 * @entries: Buffer which contains the entities to be mirrored
9506 * @count: number of entities contained in the buffer
9507 * @rule_id:the rule_id of the rule to be added
9509 * Add a mirror rule for a given veb.
9512 static enum i40e_status_code
9513 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
9514 uint16_t seid, uint16_t dst_id,
9515 uint16_t rule_type, uint16_t *entries,
9516 uint16_t count, uint16_t *rule_id)
9518 struct i40e_aq_desc desc;
9519 struct i40e_aqc_add_delete_mirror_rule cmd;
9520 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
9521 (struct i40e_aqc_add_delete_mirror_rule_completion *)
9524 enum i40e_status_code status;
9526 i40e_fill_default_direct_cmd_desc(&desc,
9527 i40e_aqc_opc_add_mirror_rule);
9528 memset(&cmd, 0, sizeof(cmd));
9530 buff_len = sizeof(uint16_t) * count;
9531 desc.datalen = rte_cpu_to_le_16(buff_len);
9533 desc.flags |= rte_cpu_to_le_16(
9534 (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
9535 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9536 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9537 cmd.num_entries = rte_cpu_to_le_16(count);
9538 cmd.seid = rte_cpu_to_le_16(seid);
9539 cmd.destination = rte_cpu_to_le_16(dst_id);
9541 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9542 status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
9544 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
9545 hw->aq.asq_last_status, resp->rule_id,
9546 resp->mirror_rules_used, resp->mirror_rules_free);
9547 *rule_id = rte_le_to_cpu_16(resp->rule_id);
9553 * i40e_aq_del_mirror_rule
9554 * @hw: pointer to the hardware structure
9555 * @seid: VEB seid to add mirror rule to
9556 * @entries: Buffer which contains the entities to be mirrored
9557 * @count: number of entities contained in the buffer
9558 * @rule_id:the rule_id of the rule to be delete
9560 * Delete a mirror rule for a given veb.
9563 static enum i40e_status_code
9564 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
9565 uint16_t seid, uint16_t rule_type, uint16_t *entries,
9566 uint16_t count, uint16_t rule_id)
9568 struct i40e_aq_desc desc;
9569 struct i40e_aqc_add_delete_mirror_rule cmd;
9570 uint16_t buff_len = 0;
9571 enum i40e_status_code status;
9574 i40e_fill_default_direct_cmd_desc(&desc,
9575 i40e_aqc_opc_delete_mirror_rule);
9576 memset(&cmd, 0, sizeof(cmd));
9577 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
9578 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
9580 cmd.num_entries = count;
9581 buff_len = sizeof(uint16_t) * count;
9582 desc.datalen = rte_cpu_to_le_16(buff_len);
9583 buff = (void *)entries;
9585 /* rule id is filled in destination field for deleting mirror rule */
9586 cmd.destination = rte_cpu_to_le_16(rule_id);
9588 cmd.rule_type = rte_cpu_to_le_16(rule_type <<
9589 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
9590 cmd.seid = rte_cpu_to_le_16(seid);
9592 rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
9593 status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
9599 * i40e_mirror_rule_set
9600 * @dev: pointer to the hardware structure
9601 * @mirror_conf: mirror rule info
9602 * @sw_id: mirror rule's sw_id
9603 * @on: enable/disable
9605 * set a mirror rule.
9609 i40e_mirror_rule_set(struct rte_eth_dev *dev,
9610 struct rte_eth_mirror_conf *mirror_conf,
9611 uint8_t sw_id, uint8_t on)
9613 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9614 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9615 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9616 struct i40e_mirror_rule *parent = NULL;
9617 uint16_t seid, dst_seid, rule_id;
9621 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
9623 if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
9625 "mirror rule can not be configured without veb or vfs.");
9628 if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
9629 PMD_DRV_LOG(ERR, "mirror table is full.");
9632 if (mirror_conf->dst_pool > pf->vf_num) {
9633 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
9634 mirror_conf->dst_pool);
9638 seid = pf->main_vsi->veb->seid;
9640 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9641 if (sw_id <= it->index) {
9647 if (mirr_rule && sw_id == mirr_rule->index) {
9649 PMD_DRV_LOG(ERR, "mirror rule exists.");
9652 ret = i40e_aq_del_mirror_rule(hw, seid,
9653 mirr_rule->rule_type,
9655 mirr_rule->num_entries, mirr_rule->id);
9658 "failed to remove mirror rule: ret = %d, aq_err = %d.",
9659 ret, hw->aq.asq_last_status);
9662 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9663 rte_free(mirr_rule);
9664 pf->nb_mirror_rule--;
9668 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9672 mirr_rule = rte_zmalloc("i40e_mirror_rule",
9673 sizeof(struct i40e_mirror_rule) , 0);
9675 PMD_DRV_LOG(ERR, "failed to allocate memory");
9676 return I40E_ERR_NO_MEMORY;
9678 switch (mirror_conf->rule_type) {
9679 case ETH_MIRROR_VLAN:
9680 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
9681 if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
9682 mirr_rule->entries[j] =
9683 mirror_conf->vlan.vlan_id[i];
9688 PMD_DRV_LOG(ERR, "vlan is not specified.");
9689 rte_free(mirr_rule);
9692 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
9694 case ETH_MIRROR_VIRTUAL_POOL_UP:
9695 case ETH_MIRROR_VIRTUAL_POOL_DOWN:
9696 /* check if the specified pool bit is out of range */
9697 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
9698 PMD_DRV_LOG(ERR, "pool mask is out of range.");
9699 rte_free(mirr_rule);
9702 for (i = 0, j = 0; i < pf->vf_num; i++) {
9703 if (mirror_conf->pool_mask & (1ULL << i)) {
9704 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
9708 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
9709 /* add pf vsi to entries */
9710 mirr_rule->entries[j] = pf->main_vsi_seid;
9714 PMD_DRV_LOG(ERR, "pool is not specified.");
9715 rte_free(mirr_rule);
9718 /* egress and ingress in aq commands means from switch but not port */
9719 mirr_rule->rule_type =
9720 (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
9721 I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
9722 I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
9724 case ETH_MIRROR_UPLINK_PORT:
9725 /* egress and ingress in aq commands means from switch but not port*/
9726 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
9728 case ETH_MIRROR_DOWNLINK_PORT:
9729 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
9732 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
9733 mirror_conf->rule_type);
9734 rte_free(mirr_rule);
9738 /* If the dst_pool is equal to vf_num, consider it as PF */
9739 if (mirror_conf->dst_pool == pf->vf_num)
9740 dst_seid = pf->main_vsi_seid;
9742 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
9744 ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
9745 mirr_rule->rule_type, mirr_rule->entries,
9749 "failed to add mirror rule: ret = %d, aq_err = %d.",
9750 ret, hw->aq.asq_last_status);
9751 rte_free(mirr_rule);
9755 mirr_rule->index = sw_id;
9756 mirr_rule->num_entries = j;
9757 mirr_rule->id = rule_id;
9758 mirr_rule->dst_vsi_seid = dst_seid;
9761 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
9763 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
9765 pf->nb_mirror_rule++;
9770 * i40e_mirror_rule_reset
9771 * @dev: pointer to the device
9772 * @sw_id: mirror rule's sw_id
9774 * reset a mirror rule.
9778 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
9780 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9781 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9782 struct i40e_mirror_rule *it, *mirr_rule = NULL;
9786 PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
9788 seid = pf->main_vsi->veb->seid;
9790 TAILQ_FOREACH(it, &pf->mirror_list, rules) {
9791 if (sw_id == it->index) {
9797 ret = i40e_aq_del_mirror_rule(hw, seid,
9798 mirr_rule->rule_type,
9800 mirr_rule->num_entries, mirr_rule->id);
9803 "failed to remove mirror rule: status = %d, aq_err = %d.",
9804 ret, hw->aq.asq_last_status);
9807 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
9808 rte_free(mirr_rule);
9809 pf->nb_mirror_rule--;
9811 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
9818 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
9820 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9821 uint64_t systim_cycles;
9823 systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
9824 systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
9827 return systim_cycles;
9831 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
9833 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9836 rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
9837 rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
9844 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
9846 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9849 tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
9850 tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
9857 i40e_start_timecounters(struct rte_eth_dev *dev)
9859 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9860 struct i40e_adapter *adapter =
9861 (struct i40e_adapter *)dev->data->dev_private;
9862 struct rte_eth_link link;
9863 uint32_t tsync_inc_l;
9864 uint32_t tsync_inc_h;
9866 /* Get current link speed. */
9867 memset(&link, 0, sizeof(link));
9868 i40e_dev_link_update(dev, 1);
9869 rte_i40e_dev_atomic_read_link_status(dev, &link);
9871 switch (link.link_speed) {
9872 case ETH_SPEED_NUM_40G:
9873 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
9874 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
9876 case ETH_SPEED_NUM_10G:
9877 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
9878 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
9880 case ETH_SPEED_NUM_1G:
9881 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
9882 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
9889 /* Set the timesync increment value. */
9890 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
9891 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
9893 memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
9894 memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9895 memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
9897 adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9898 adapter->systime_tc.cc_shift = 0;
9899 adapter->systime_tc.nsec_mask = 0;
9901 adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9902 adapter->rx_tstamp_tc.cc_shift = 0;
9903 adapter->rx_tstamp_tc.nsec_mask = 0;
9905 adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
9906 adapter->tx_tstamp_tc.cc_shift = 0;
9907 adapter->tx_tstamp_tc.nsec_mask = 0;
9911 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
9913 struct i40e_adapter *adapter =
9914 (struct i40e_adapter *)dev->data->dev_private;
9916 adapter->systime_tc.nsec += delta;
9917 adapter->rx_tstamp_tc.nsec += delta;
9918 adapter->tx_tstamp_tc.nsec += delta;
9924 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
9927 struct i40e_adapter *adapter =
9928 (struct i40e_adapter *)dev->data->dev_private;
9930 ns = rte_timespec_to_ns(ts);
9932 /* Set the timecounters to a new value. */
9933 adapter->systime_tc.nsec = ns;
9934 adapter->rx_tstamp_tc.nsec = ns;
9935 adapter->tx_tstamp_tc.nsec = ns;
9941 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
9943 uint64_t ns, systime_cycles;
9944 struct i40e_adapter *adapter =
9945 (struct i40e_adapter *)dev->data->dev_private;
9947 systime_cycles = i40e_read_systime_cyclecounter(dev);
9948 ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
9949 *ts = rte_ns_to_timespec(ns);
9955 i40e_timesync_enable(struct rte_eth_dev *dev)
9957 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9958 uint32_t tsync_ctl_l;
9959 uint32_t tsync_ctl_h;
9961 /* Stop the timesync system time. */
9962 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
9963 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
9964 /* Reset the timesync system time value. */
9965 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
9966 I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
9968 i40e_start_timecounters(dev);
9970 /* Clear timesync registers. */
9971 I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
9972 I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
9973 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
9974 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
9975 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
9976 I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
9978 /* Enable timestamping of PTP packets. */
9979 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
9980 tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
9982 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
9983 tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
9984 tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
9986 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
9987 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
9993 i40e_timesync_disable(struct rte_eth_dev *dev)
9995 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9996 uint32_t tsync_ctl_l;
9997 uint32_t tsync_ctl_h;
9999 /* Disable timestamping of transmitted PTP packets. */
10000 tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10001 tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10003 tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10004 tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10006 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10007 I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10009 /* Reset the timesync increment value. */
10010 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10011 I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10017 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10018 struct timespec *timestamp, uint32_t flags)
10020 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10021 struct i40e_adapter *adapter =
10022 (struct i40e_adapter *)dev->data->dev_private;
10024 uint32_t sync_status;
10025 uint32_t index = flags & 0x03;
10026 uint64_t rx_tstamp_cycles;
10029 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10030 if ((sync_status & (1 << index)) == 0)
10033 rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10034 ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10035 *timestamp = rte_ns_to_timespec(ns);
10041 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10042 struct timespec *timestamp)
10044 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10045 struct i40e_adapter *adapter =
10046 (struct i40e_adapter *)dev->data->dev_private;
10048 uint32_t sync_status;
10049 uint64_t tx_tstamp_cycles;
10052 sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10053 if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10056 tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10057 ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10058 *timestamp = rte_ns_to_timespec(ns);
10064 * i40e_parse_dcb_configure - parse dcb configure from user
10065 * @dev: the device being configured
10066 * @dcb_cfg: pointer of the result of parse
10067 * @*tc_map: bit map of enabled traffic classes
10069 * Returns 0 on success, negative value on failure
10072 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10073 struct i40e_dcbx_config *dcb_cfg,
10076 struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10077 uint8_t i, tc_bw, bw_lf;
10079 memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10081 dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10082 if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10083 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10087 /* assume each tc has the same bw */
10088 tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10089 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10090 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10091 /* to ensure the sum of tcbw is equal to 100 */
10092 bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10093 for (i = 0; i < bw_lf; i++)
10094 dcb_cfg->etscfg.tcbwtable[i]++;
10096 /* assume each tc has the same Transmission Selection Algorithm */
10097 for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10098 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10100 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10101 dcb_cfg->etscfg.prioritytable[i] =
10102 dcb_rx_conf->dcb_tc[i];
10104 /* FW needs one App to configure HW */
10105 dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10106 dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10107 dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10108 dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10110 if (dcb_rx_conf->nb_tcs == 0)
10111 *tc_map = 1; /* tc0 only */
10113 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10115 if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10116 dcb_cfg->pfc.willing = 0;
10117 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10118 dcb_cfg->pfc.pfcenable = *tc_map;
10124 static enum i40e_status_code
10125 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10126 struct i40e_aqc_vsi_properties_data *info,
10127 uint8_t enabled_tcmap)
10129 enum i40e_status_code ret;
10130 int i, total_tc = 0;
10131 uint16_t qpnum_per_tc, bsf, qp_idx;
10132 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10133 struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10134 uint16_t used_queues;
10136 ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10137 if (ret != I40E_SUCCESS)
10140 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10141 if (enabled_tcmap & (1 << i))
10146 vsi->enabled_tc = enabled_tcmap;
10148 /* different VSI has different queues assigned */
10149 if (vsi->type == I40E_VSI_MAIN)
10150 used_queues = dev_data->nb_rx_queues -
10151 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10152 else if (vsi->type == I40E_VSI_VMDQ2)
10153 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10155 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10156 return I40E_ERR_NO_AVAILABLE_VSI;
10159 qpnum_per_tc = used_queues / total_tc;
10160 /* Number of queues per enabled TC */
10161 if (qpnum_per_tc == 0) {
10162 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10163 return I40E_ERR_INVALID_QP_ID;
10165 qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10166 I40E_MAX_Q_PER_TC);
10167 bsf = rte_bsf32(qpnum_per_tc);
10170 * Configure TC and queue mapping parameters, for enabled TC,
10171 * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10172 * default queue will serve it.
10175 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10176 if (vsi->enabled_tc & (1 << i)) {
10177 info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10178 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10179 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10180 qp_idx += qpnum_per_tc;
10182 info->tc_mapping[i] = 0;
10185 /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10186 if (vsi->type == I40E_VSI_SRIOV) {
10187 info->mapping_flags |=
10188 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10189 for (i = 0; i < vsi->nb_qps; i++)
10190 info->queue_mapping[i] =
10191 rte_cpu_to_le_16(vsi->base_queue + i);
10193 info->mapping_flags |=
10194 rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10195 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10197 info->valid_sections |=
10198 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10200 return I40E_SUCCESS;
10204 * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10205 * @veb: VEB to be configured
10206 * @tc_map: enabled TC bitmap
10208 * Returns 0 on success, negative value on failure
10210 static enum i40e_status_code
10211 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10213 struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10214 struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10215 struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10216 struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10217 enum i40e_status_code ret = I40E_SUCCESS;
10221 /* Check if enabled_tc is same as existing or new TCs */
10222 if (veb->enabled_tc == tc_map)
10225 /* configure tc bandwidth */
10226 memset(&veb_bw, 0, sizeof(veb_bw));
10227 veb_bw.tc_valid_bits = tc_map;
10228 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10229 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10230 if (tc_map & BIT_ULL(i))
10231 veb_bw.tc_bw_share_credits[i] = 1;
10233 ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10237 "AQ command Config switch_comp BW allocation per TC failed = %d",
10238 hw->aq.asq_last_status);
10242 memset(&ets_query, 0, sizeof(ets_query));
10243 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10245 if (ret != I40E_SUCCESS) {
10247 "Failed to get switch_comp ETS configuration %u",
10248 hw->aq.asq_last_status);
10251 memset(&bw_query, 0, sizeof(bw_query));
10252 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10254 if (ret != I40E_SUCCESS) {
10256 "Failed to get switch_comp bandwidth configuration %u",
10257 hw->aq.asq_last_status);
10261 /* store and print out BW info */
10262 veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10263 veb->bw_info.bw_max = ets_query.tc_bw_max;
10264 PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10265 PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10266 bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10267 (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10268 I40E_16_BIT_WIDTH);
10269 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10270 veb->bw_info.bw_ets_share_credits[i] =
10271 bw_query.tc_bw_share_credits[i];
10272 veb->bw_info.bw_ets_credits[i] =
10273 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10274 /* 4 bits per TC, 4th bit is reserved */
10275 veb->bw_info.bw_ets_max[i] =
10276 (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10277 RTE_LEN2MASK(3, uint8_t));
10278 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10279 veb->bw_info.bw_ets_share_credits[i]);
10280 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10281 veb->bw_info.bw_ets_credits[i]);
10282 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10283 veb->bw_info.bw_ets_max[i]);
10286 veb->enabled_tc = tc_map;
10293 * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10294 * @vsi: VSI to be configured
10295 * @tc_map: enabled TC bitmap
10297 * Returns 0 on success, negative value on failure
10299 static enum i40e_status_code
10300 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10302 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10303 struct i40e_vsi_context ctxt;
10304 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10305 enum i40e_status_code ret = I40E_SUCCESS;
10308 /* Check if enabled_tc is same as existing or new TCs */
10309 if (vsi->enabled_tc == tc_map)
10312 /* configure tc bandwidth */
10313 memset(&bw_data, 0, sizeof(bw_data));
10314 bw_data.tc_valid_bits = tc_map;
10315 /* Enable ETS TCs with equal BW Share for now across all VSIs */
10316 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10317 if (tc_map & BIT_ULL(i))
10318 bw_data.tc_bw_credits[i] = 1;
10320 ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10323 "AQ command Config VSI BW allocation per TC failed = %d",
10324 hw->aq.asq_last_status);
10327 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10328 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10330 /* Update Queue Pairs Mapping for currently enabled UPs */
10331 ctxt.seid = vsi->seid;
10332 ctxt.pf_num = hw->pf_id;
10334 ctxt.uplink_seid = vsi->uplink_seid;
10335 ctxt.info = vsi->info;
10337 ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10341 /* Update the VSI after updating the VSI queue-mapping information */
10342 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10344 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10345 hw->aq.asq_last_status);
10348 /* update the local VSI info with updated queue map */
10349 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10350 sizeof(vsi->info.tc_mapping));
10351 rte_memcpy(&vsi->info.queue_mapping,
10352 &ctxt.info.queue_mapping,
10353 sizeof(vsi->info.queue_mapping));
10354 vsi->info.mapping_flags = ctxt.info.mapping_flags;
10355 vsi->info.valid_sections = 0;
10357 /* query and update current VSI BW information */
10358 ret = i40e_vsi_get_bw_config(vsi);
10361 "Failed updating vsi bw info, err %s aq_err %s",
10362 i40e_stat_str(hw, ret),
10363 i40e_aq_str(hw, hw->aq.asq_last_status));
10367 vsi->enabled_tc = tc_map;
10374 * i40e_dcb_hw_configure - program the dcb setting to hw
10375 * @pf: pf the configuration is taken on
10376 * @new_cfg: new configuration
10377 * @tc_map: enabled TC bitmap
10379 * Returns 0 on success, negative value on failure
10381 static enum i40e_status_code
10382 i40e_dcb_hw_configure(struct i40e_pf *pf,
10383 struct i40e_dcbx_config *new_cfg,
10386 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10387 struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10388 struct i40e_vsi *main_vsi = pf->main_vsi;
10389 struct i40e_vsi_list *vsi_list;
10390 enum i40e_status_code ret;
10394 /* Use the FW API if FW > v4.4*/
10395 if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10396 (hw->aq.fw_maj_ver >= 5))) {
10398 "FW < v4.4, can not use FW LLDP API to configure DCB");
10399 return I40E_ERR_FIRMWARE_API_VERSION;
10402 /* Check if need reconfiguration */
10403 if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10404 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10405 return I40E_SUCCESS;
10408 /* Copy the new config to the current config */
10409 *old_cfg = *new_cfg;
10410 old_cfg->etsrec = old_cfg->etscfg;
10411 ret = i40e_set_dcb_config(hw);
10413 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10414 i40e_stat_str(hw, ret),
10415 i40e_aq_str(hw, hw->aq.asq_last_status));
10418 /* set receive Arbiter to RR mode and ETS scheme by default */
10419 for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10420 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10421 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK |
10422 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10423 I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10424 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10425 I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10426 I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10427 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10428 I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10429 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10430 I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10431 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10433 /* get local mib to check whether it is configured correctly */
10435 hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10436 /* Get Local DCB Config */
10437 i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10438 &hw->local_dcbx_config);
10440 /* if Veb is created, need to update TC of it at first */
10441 if (main_vsi->veb) {
10442 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10444 PMD_INIT_LOG(WARNING,
10445 "Failed configuring TC for VEB seid=%d",
10446 main_vsi->veb->seid);
10448 /* Update each VSI */
10449 i40e_vsi_config_tc(main_vsi, tc_map);
10450 if (main_vsi->veb) {
10451 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10452 /* Beside main VSI and VMDQ VSIs, only enable default
10453 * TC for other VSIs
10455 if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10456 ret = i40e_vsi_config_tc(vsi_list->vsi,
10459 ret = i40e_vsi_config_tc(vsi_list->vsi,
10460 I40E_DEFAULT_TCMAP);
10462 PMD_INIT_LOG(WARNING,
10463 "Failed configuring TC for VSI seid=%d",
10464 vsi_list->vsi->seid);
10468 return I40E_SUCCESS;
10472 * i40e_dcb_init_configure - initial dcb config
10473 * @dev: device being configured
10474 * @sw_dcb: indicate whether dcb is sw configured or hw offload
10476 * Returns 0 on success, negative value on failure
10479 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10481 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10482 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10485 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10486 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10490 /* DCB initialization:
10491 * Update DCB configuration from the Firmware and configure
10492 * LLDP MIB change event.
10494 if (sw_dcb == TRUE) {
10495 ret = i40e_init_dcb(hw);
10496 /* If lldp agent is stopped, the return value from
10497 * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
10498 * adminq status. Otherwise, it should return success.
10500 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
10501 hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
10502 memset(&hw->local_dcbx_config, 0,
10503 sizeof(struct i40e_dcbx_config));
10504 /* set dcb default configuration */
10505 hw->local_dcbx_config.etscfg.willing = 0;
10506 hw->local_dcbx_config.etscfg.maxtcs = 0;
10507 hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
10508 hw->local_dcbx_config.etscfg.tsatable[0] =
10510 /* all UPs mapping to TC0 */
10511 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10512 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
10513 hw->local_dcbx_config.etsrec =
10514 hw->local_dcbx_config.etscfg;
10515 hw->local_dcbx_config.pfc.willing = 0;
10516 hw->local_dcbx_config.pfc.pfccap =
10517 I40E_MAX_TRAFFIC_CLASS;
10518 /* FW needs one App to configure HW */
10519 hw->local_dcbx_config.numapps = 1;
10520 hw->local_dcbx_config.app[0].selector =
10521 I40E_APP_SEL_ETHTYPE;
10522 hw->local_dcbx_config.app[0].priority = 3;
10523 hw->local_dcbx_config.app[0].protocolid =
10524 I40E_APP_PROTOID_FCOE;
10525 ret = i40e_set_dcb_config(hw);
10528 "default dcb config fails. err = %d, aq_err = %d.",
10529 ret, hw->aq.asq_last_status);
10534 "DCB initialization in FW fails, err = %d, aq_err = %d.",
10535 ret, hw->aq.asq_last_status);
10539 ret = i40e_aq_start_lldp(hw, NULL);
10540 if (ret != I40E_SUCCESS)
10541 PMD_INIT_LOG(DEBUG, "Failed to start lldp");
10543 ret = i40e_init_dcb(hw);
10545 if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
10547 "HW doesn't support DCBX offload.");
10552 "DCBX configuration failed, err = %d, aq_err = %d.",
10553 ret, hw->aq.asq_last_status);
10561 * i40e_dcb_setup - setup dcb related config
10562 * @dev: device being configured
10564 * Returns 0 on success, negative value on failure
10567 i40e_dcb_setup(struct rte_eth_dev *dev)
10569 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10570 struct i40e_dcbx_config dcb_cfg;
10571 uint8_t tc_map = 0;
10574 if ((pf->flags & I40E_FLAG_DCB) == 0) {
10575 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
10579 if (pf->vf_num != 0)
10580 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
10582 ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
10584 PMD_INIT_LOG(ERR, "invalid dcb config");
10587 ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
10589 PMD_INIT_LOG(ERR, "dcb sw configure fails");
10597 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
10598 struct rte_eth_dcb_info *dcb_info)
10600 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10601 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10602 struct i40e_vsi *vsi = pf->main_vsi;
10603 struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
10604 uint16_t bsf, tc_mapping;
10607 if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
10608 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
10610 dcb_info->nb_tcs = 1;
10611 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10612 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
10613 for (i = 0; i < dcb_info->nb_tcs; i++)
10614 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
10616 /* get queue mapping if vmdq is disabled */
10617 if (!pf->nb_cfg_vmdq_vsi) {
10618 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10619 if (!(vsi->enabled_tc & (1 << i)))
10621 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10622 dcb_info->tc_queue.tc_rxq[j][i].base =
10623 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10624 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10625 dcb_info->tc_queue.tc_txq[j][i].base =
10626 dcb_info->tc_queue.tc_rxq[j][i].base;
10627 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10628 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10629 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10630 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10631 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10636 /* get queue mapping if vmdq is enabled */
10638 vsi = pf->vmdq[j].vsi;
10639 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10640 if (!(vsi->enabled_tc & (1 << i)))
10642 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
10643 dcb_info->tc_queue.tc_rxq[j][i].base =
10644 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
10645 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
10646 dcb_info->tc_queue.tc_txq[j][i].base =
10647 dcb_info->tc_queue.tc_rxq[j][i].base;
10648 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
10649 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
10650 dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
10651 dcb_info->tc_queue.tc_txq[j][i].nb_queue =
10652 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
10655 } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
10660 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
10662 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10663 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10664 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10665 uint16_t interval =
10666 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
10667 uint16_t msix_intr;
10669 msix_intr = intr_handle->intr_vec[queue_id];
10670 if (msix_intr == I40E_MISC_VEC_ID)
10671 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
10672 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10673 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10674 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10676 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10679 I40E_PFINT_DYN_CTLN(msix_intr -
10680 I40E_RX_VEC_START),
10681 I40E_PFINT_DYN_CTLN_INTENA_MASK |
10682 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
10683 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
10685 I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
10687 I40E_WRITE_FLUSH(hw);
10688 rte_intr_enable(&pci_dev->intr_handle);
10694 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
10696 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10697 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
10698 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10699 uint16_t msix_intr;
10701 msix_intr = intr_handle->intr_vec[queue_id];
10702 if (msix_intr == I40E_MISC_VEC_ID)
10703 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
10706 I40E_PFINT_DYN_CTLN(msix_intr -
10707 I40E_RX_VEC_START),
10709 I40E_WRITE_FLUSH(hw);
10714 static int i40e_get_regs(struct rte_eth_dev *dev,
10715 struct rte_dev_reg_info *regs)
10717 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10718 uint32_t *ptr_data = regs->data;
10719 uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
10720 const struct i40e_reg_info *reg_info;
10722 if (ptr_data == NULL) {
10723 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
10724 regs->width = sizeof(uint32_t);
10728 /* The first few registers have to be read using AQ operations */
10730 while (i40e_regs_adminq[reg_idx].name) {
10731 reg_info = &i40e_regs_adminq[reg_idx++];
10732 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10734 arr_idx2 <= reg_info->count2;
10736 reg_offset = arr_idx * reg_info->stride1 +
10737 arr_idx2 * reg_info->stride2;
10738 reg_offset += reg_info->base_addr;
10739 ptr_data[reg_offset >> 2] =
10740 i40e_read_rx_ctl(hw, reg_offset);
10744 /* The remaining registers can be read using primitives */
10746 while (i40e_regs_others[reg_idx].name) {
10747 reg_info = &i40e_regs_others[reg_idx++];
10748 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
10750 arr_idx2 <= reg_info->count2;
10752 reg_offset = arr_idx * reg_info->stride1 +
10753 arr_idx2 * reg_info->stride2;
10754 reg_offset += reg_info->base_addr;
10755 ptr_data[reg_offset >> 2] =
10756 I40E_READ_REG(hw, reg_offset);
10763 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
10765 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10767 /* Convert word count to byte count */
10768 return hw->nvm.sr_size << 1;
10771 static int i40e_get_eeprom(struct rte_eth_dev *dev,
10772 struct rte_dev_eeprom_info *eeprom)
10774 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10775 uint16_t *data = eeprom->data;
10776 uint16_t offset, length, cnt_words;
10779 offset = eeprom->offset >> 1;
10780 length = eeprom->length >> 1;
10781 cnt_words = length;
10783 if (offset > hw->nvm.sr_size ||
10784 offset + length > hw->nvm.sr_size) {
10785 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
10789 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
10791 ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
10792 if (ret_code != I40E_SUCCESS || cnt_words != length) {
10793 PMD_DRV_LOG(ERR, "EEPROM read failed.");
10800 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
10801 struct ether_addr *mac_addr)
10803 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10805 if (!is_valid_assigned_ether_addr(mac_addr)) {
10806 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
10810 /* Flags: 0x3 updates port address */
10811 i40e_aq_mac_address_write(hw, 0x3, mac_addr->addr_bytes, NULL);
10815 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
10817 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10818 struct rte_eth_dev_data *dev_data = pf->dev_data;
10819 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
10822 /* check if mtu is within the allowed range */
10823 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
10826 /* mtu setting is forbidden if port is start */
10827 if (dev_data->dev_started) {
10828 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
10829 dev_data->port_id);
10833 if (frame_size > ETHER_MAX_LEN)
10834 dev_data->dev_conf.rxmode.jumbo_frame = 1;
10836 dev_data->dev_conf.rxmode.jumbo_frame = 0;
10838 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
10843 /* Restore ethertype filter */
10845 i40e_ethertype_filter_restore(struct i40e_pf *pf)
10847 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10848 struct i40e_ethertype_filter_list
10849 *ethertype_list = &pf->ethertype.ethertype_list;
10850 struct i40e_ethertype_filter *f;
10851 struct i40e_control_filter_stats stats;
10854 TAILQ_FOREACH(f, ethertype_list, rules) {
10856 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
10857 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10858 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
10859 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10860 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10862 memset(&stats, 0, sizeof(stats));
10863 i40e_aq_add_rem_control_packet_filter(hw,
10864 f->input.mac_addr.addr_bytes,
10865 f->input.ether_type,
10866 flags, pf->main_vsi->seid,
10867 f->queue, 1, &stats, NULL);
10869 PMD_DRV_LOG(INFO, "Ethertype filter:"
10870 " mac_etype_used = %u, etype_used = %u,"
10871 " mac_etype_free = %u, etype_free = %u",
10872 stats.mac_etype_used, stats.etype_used,
10873 stats.mac_etype_free, stats.etype_free);
10876 /* Restore tunnel filter */
10878 i40e_tunnel_filter_restore(struct i40e_pf *pf)
10880 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10881 struct i40e_vsi *vsi;
10882 struct i40e_pf_vf *vf;
10883 struct i40e_tunnel_filter_list
10884 *tunnel_list = &pf->tunnel.tunnel_list;
10885 struct i40e_tunnel_filter *f;
10886 struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
10887 bool big_buffer = 0;
10889 TAILQ_FOREACH(f, tunnel_list, rules) {
10891 vsi = pf->main_vsi;
10893 vf = &pf->vfs[f->vf_id];
10896 memset(&cld_filter, 0, sizeof(cld_filter));
10897 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
10898 (struct ether_addr *)&cld_filter.element.outer_mac);
10899 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
10900 (struct ether_addr *)&cld_filter.element.inner_mac);
10901 cld_filter.element.inner_vlan = f->input.inner_vlan;
10902 cld_filter.element.flags = f->input.flags;
10903 cld_filter.element.tenant_id = f->input.tenant_id;
10904 cld_filter.element.queue_number = f->queue;
10905 rte_memcpy(cld_filter.general_fields,
10906 f->input.general_fields,
10907 sizeof(f->input.general_fields));
10909 if (((f->input.flags &
10910 I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
10911 I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
10913 I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
10914 I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
10916 I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
10917 I40E_AQC_ADD_CLOUD_FILTER_0X10))
10921 i40e_aq_add_cloud_filters_big_buffer(hw,
10922 vsi->seid, &cld_filter, 1);
10924 i40e_aq_add_cloud_filters(hw, vsi->seid,
10925 &cld_filter.element, 1);
10930 i40e_filter_restore(struct i40e_pf *pf)
10932 i40e_ethertype_filter_restore(pf);
10933 i40e_tunnel_filter_restore(pf);
10934 i40e_fdir_filter_restore(pf);
10938 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
10940 if (strcmp(dev->device->driver->name, drv->driver.name))
10947 is_i40e_supported(struct rte_eth_dev *dev)
10949 return is_device_supported(dev, &rte_i40e_pmd);
10952 struct i40e_customized_pctype*
10953 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
10957 for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
10958 if (pf->customized_pctype[i].index == index)
10959 return &pf->customized_pctype[i];
10965 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
10966 uint32_t pkg_size, uint32_t proto_num,
10967 struct rte_pmd_i40e_proto_info *proto)
10969 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10970 uint32_t pctype_num;
10971 struct rte_pmd_i40e_ptype_info *pctype;
10972 uint32_t buff_size;
10973 struct i40e_customized_pctype *new_pctype = NULL;
10975 uint8_t pctype_value;
10980 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
10981 (uint8_t *)&pctype_num, sizeof(pctype_num),
10982 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
10984 PMD_DRV_LOG(ERR, "Failed to get pctype number");
10988 PMD_DRV_LOG(INFO, "No new pctype added");
10992 buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
10993 pctype = rte_zmalloc("new_pctype", buff_size, 0);
10995 PMD_DRV_LOG(ERR, "Failed to allocate memory");
10998 /* get information about new pctype list */
10999 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11000 (uint8_t *)pctype, buff_size,
11001 RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
11003 PMD_DRV_LOG(ERR, "Failed to get pctype list");
11008 /* Update customized pctype. */
11009 for (i = 0; i < pctype_num; i++) {
11010 pctype_value = pctype[i].ptype_id;
11011 memset(name, 0, sizeof(name));
11012 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11013 proto_id = pctype[i].protocols[j];
11014 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11016 for (n = 0; n < proto_num; n++) {
11017 if (proto[n].proto_id != proto_id)
11019 strcat(name, proto[n].name);
11024 name[strlen(name) - 1] = '\0';
11025 if (!strcmp(name, "GTPC"))
11027 i40e_find_customized_pctype(pf,
11028 I40E_CUSTOMIZED_GTPC);
11029 else if (!strcmp(name, "GTPU_IPV4"))
11031 i40e_find_customized_pctype(pf,
11032 I40E_CUSTOMIZED_GTPU_IPV4);
11033 else if (!strcmp(name, "GTPU_IPV6"))
11035 i40e_find_customized_pctype(pf,
11036 I40E_CUSTOMIZED_GTPU_IPV6);
11037 else if (!strcmp(name, "GTPU"))
11039 i40e_find_customized_pctype(pf,
11040 I40E_CUSTOMIZED_GTPU);
11042 new_pctype->pctype = pctype_value;
11043 new_pctype->valid = true;
11052 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
11053 uint32_t pkg_size, uint32_t proto_num,
11054 struct rte_pmd_i40e_proto_info *proto)
11056 struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
11057 uint16_t port_id = dev->data->port_id;
11058 uint32_t ptype_num;
11059 struct rte_pmd_i40e_ptype_info *ptype;
11060 uint32_t buff_size;
11062 char name[RTE_PMD_I40E_DDP_NAME_SIZE];
11067 /* get information about new ptype num */
11068 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11069 (uint8_t *)&ptype_num, sizeof(ptype_num),
11070 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
11072 PMD_DRV_LOG(ERR, "Failed to get ptype number");
11076 PMD_DRV_LOG(INFO, "No new ptype added");
11080 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
11081 ptype = rte_zmalloc("new_ptype", buff_size, 0);
11083 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11087 /* get information about new ptype list */
11088 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11089 (uint8_t *)ptype, buff_size,
11090 RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
11092 PMD_DRV_LOG(ERR, "Failed to get ptype list");
11097 buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
11098 ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
11099 if (!ptype_mapping) {
11100 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11105 /* Update ptype mapping table. */
11106 for (i = 0; i < ptype_num; i++) {
11107 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
11108 ptype_mapping[i].sw_ptype = 0;
11110 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11111 proto_id = ptype[i].protocols[j];
11112 if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11114 for (n = 0; n < proto_num; n++) {
11115 if (proto[n].proto_id != proto_id)
11117 memset(name, 0, sizeof(name));
11118 strcpy(name, proto[n].name);
11119 if (!strncmp(name, "PPPOE", 5))
11120 ptype_mapping[i].sw_ptype |=
11121 RTE_PTYPE_L2_ETHER_PPPOE;
11122 else if (!strncmp(name, "OIPV4", 5)) {
11123 ptype_mapping[i].sw_ptype |=
11124 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11126 } else if (!strncmp(name, "IPV4", 4) &&
11128 ptype_mapping[i].sw_ptype |=
11129 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11130 else if (!strncmp(name, "IPV4FRAG", 8) &&
11132 ptype_mapping[i].sw_ptype |=
11133 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11134 ptype_mapping[i].sw_ptype |=
11135 RTE_PTYPE_INNER_L4_FRAG;
11136 } else if (!strncmp(name, "IPV4", 4) &&
11138 ptype_mapping[i].sw_ptype |=
11139 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11140 else if (!strncmp(name, "OIPV6", 5)) {
11141 ptype_mapping[i].sw_ptype |=
11142 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11144 } else if (!strncmp(name, "IPV6", 4) &&
11146 ptype_mapping[i].sw_ptype |=
11147 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11148 else if (!strncmp(name, "IPV6FRAG", 8) &&
11150 ptype_mapping[i].sw_ptype |=
11151 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11152 ptype_mapping[i].sw_ptype |=
11153 RTE_PTYPE_INNER_L4_FRAG;
11154 } else if (!strncmp(name, "IPV6", 4) &&
11156 ptype_mapping[i].sw_ptype |=
11157 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11158 else if (!strncmp(name, "UDP", 3) && !in_tunnel)
11159 ptype_mapping[i].sw_ptype |=
11161 else if (!strncmp(name, "UDP", 3) && in_tunnel)
11162 ptype_mapping[i].sw_ptype |=
11163 RTE_PTYPE_INNER_L4_UDP;
11164 else if (!strncmp(name, "TCP", 3) && !in_tunnel)
11165 ptype_mapping[i].sw_ptype |=
11167 else if (!strncmp(name, "TCP", 3) && in_tunnel)
11168 ptype_mapping[i].sw_ptype |=
11169 RTE_PTYPE_INNER_L4_TCP;
11170 else if (!strncmp(name, "SCTP", 4) &&
11172 ptype_mapping[i].sw_ptype |=
11174 else if (!strncmp(name, "SCTP", 4) && in_tunnel)
11175 ptype_mapping[i].sw_ptype |=
11176 RTE_PTYPE_INNER_L4_SCTP;
11177 else if ((!strncmp(name, "ICMP", 4) ||
11178 !strncmp(name, "ICMPV6", 6)) &&
11180 ptype_mapping[i].sw_ptype |=
11182 else if ((!strncmp(name, "ICMP", 4) ||
11183 !strncmp(name, "ICMPV6", 6)) &&
11185 ptype_mapping[i].sw_ptype |=
11186 RTE_PTYPE_INNER_L4_ICMP;
11187 else if (!strncmp(name, "GTPC", 4)) {
11188 ptype_mapping[i].sw_ptype |=
11189 RTE_PTYPE_TUNNEL_GTPC;
11191 } else if (!strncmp(name, "GTPU", 4)) {
11192 ptype_mapping[i].sw_ptype |=
11193 RTE_PTYPE_TUNNEL_GTPU;
11195 } else if (!strncmp(name, "GRENAT", 6)) {
11196 ptype_mapping[i].sw_ptype |=
11197 RTE_PTYPE_TUNNEL_GRENAT;
11199 } else if (!strncmp(name, "L2TPv2CTL", 9)) {
11200 ptype_mapping[i].sw_ptype |=
11201 RTE_PTYPE_TUNNEL_L2TP;
11210 ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
11213 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
11215 rte_free(ptype_mapping);
11221 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
11224 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11225 uint32_t proto_num;
11226 struct rte_pmd_i40e_proto_info *proto;
11227 uint32_t buff_size;
11231 /* get information about protocol number */
11232 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11233 (uint8_t *)&proto_num, sizeof(proto_num),
11234 RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
11236 PMD_DRV_LOG(ERR, "Failed to get protocol number");
11240 PMD_DRV_LOG(INFO, "No new protocol added");
11244 buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
11245 proto = rte_zmalloc("new_proto", buff_size, 0);
11247 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11251 /* get information about protocol list */
11252 ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11253 (uint8_t *)proto, buff_size,
11254 RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
11256 PMD_DRV_LOG(ERR, "Failed to get protocol list");
11261 /* Check if GTP is supported. */
11262 for (i = 0; i < proto_num; i++) {
11263 if (!strncmp(proto[i].name, "GTP", 3)) {
11264 pf->gtp_support = true;
11269 /* Update customized pctype info */
11270 ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
11273 PMD_DRV_LOG(INFO, "No pctype is updated.");
11275 /* Update customized ptype info */
11276 ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
11279 PMD_DRV_LOG(INFO, "No ptype is updated.");
11284 /* Create a QinQ cloud filter
11286 * The Fortville NIC has limited resources for tunnel filters,
11287 * so we can only reuse existing filters.
11289 * In step 1 we define which Field Vector fields can be used for
11291 * As we do not have the inner tag defined as a field,
11292 * we have to define it first, by reusing one of L1 entries.
11294 * In step 2 we are replacing one of existing filter types with
11295 * a new one for QinQ.
11296 * As we reusing L1 and replacing L2, some of the default filter
11297 * types will disappear,which depends on L1 and L2 entries we reuse.
11299 * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
11301 * 1. Create L1 filter of outer vlan (12b) which will be in use
11302 * later when we define the cloud filter.
11303 * a. Valid_flags.replace_cloud = 0
11304 * b. Old_filter = 10 (Stag_Inner_Vlan)
11305 * c. New_filter = 0x10
11306 * d. TR bit = 0xff (optional, not used here)
11307 * e. Buffer – 2 entries:
11308 * i. Byte 0 = 8 (outer vlan FV index).
11310 * Byte 2-3 = 0x0fff
11311 * ii. Byte 0 = 37 (inner vlan FV index).
11313 * Byte 2-3 = 0x0fff
11316 * 2. Create cloud filter using two L1 filters entries: stag and
11317 * new filter(outer vlan+ inner vlan)
11318 * a. Valid_flags.replace_cloud = 1
11319 * b. Old_filter = 1 (instead of outer IP)
11320 * c. New_filter = 0x10
11321 * d. Buffer – 2 entries:
11322 * i. Byte 0 = 0x80 | 7 (valid | Stag).
11323 * Byte 1-3 = 0 (rsv)
11324 * ii. Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
11325 * Byte 9-11 = 0 (rsv)
11328 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
11330 int ret = -ENOTSUP;
11331 struct i40e_aqc_replace_cloud_filters_cmd filter_replace;
11332 struct i40e_aqc_replace_cloud_filters_cmd_buf filter_replace_buf;
11333 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11336 memset(&filter_replace, 0,
11337 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11338 memset(&filter_replace_buf, 0,
11339 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11341 /* create L1 filter */
11342 filter_replace.old_filter_type =
11343 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
11344 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11345 filter_replace.tr_bit = 0;
11347 /* Prepare the buffer, 2 entries */
11348 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
11349 filter_replace_buf.data[0] |=
11350 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11351 /* Field Vector 12b mask */
11352 filter_replace_buf.data[2] = 0xff;
11353 filter_replace_buf.data[3] = 0x0f;
11354 filter_replace_buf.data[4] =
11355 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
11356 filter_replace_buf.data[4] |=
11357 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11358 /* Field Vector 12b mask */
11359 filter_replace_buf.data[6] = 0xff;
11360 filter_replace_buf.data[7] = 0x0f;
11361 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11362 &filter_replace_buf);
11363 if (ret != I40E_SUCCESS)
11366 /* Apply the second L2 cloud filter */
11367 memset(&filter_replace, 0,
11368 sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11369 memset(&filter_replace_buf, 0,
11370 sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11372 /* create L2 filter, input for L2 filter will be L1 filter */
11373 filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
11374 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
11375 filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11377 /* Prepare the buffer, 2 entries */
11378 filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
11379 filter_replace_buf.data[0] |=
11380 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11381 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11382 filter_replace_buf.data[4] |=
11383 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11384 ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11385 &filter_replace_buf);
11389 RTE_INIT(i40e_init_log);
11391 i40e_init_log(void)
11393 i40e_logtype_init = rte_log_register("pmd.i40e.init");
11394 if (i40e_logtype_init >= 0)
11395 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
11396 i40e_logtype_driver = rte_log_register("pmd.i40e.driver");
11397 if (i40e_logtype_driver >= 0)
11398 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);